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tomoasleep/vhdl_test_script | examples/state_machine.vhd | 1 | 1,415 | library ieee;
use ieee.std_logic_1164.all;
library work;
use work.const_state.all;
use work.const_order.all;
-- DOCTEST DEPENDENCIES: state_machine_lib.vhd
entity state_machine is
port(
input: in std_logic;
reset: in std_logic;
state: out std_logic_vector(2 downto 0);
clk : in std_logic
);
end state_machine;
architecture behave of state_machine is
signal current_state: std_logic_vector(2 downto 0);
begin
main: process(clk) begin
if rising_edge(clk) then
case reset is
when '1' =>
current_state <= STATE_A;
when others =>
case current_state is
when STATE_A =>
current_state <= STATE_B;
when STATE_B =>
case input is
when ORDER_A =>
current_state <= STATE_C;
when others =>
current_state <= STATE_A;
end case;
when STATE_C =>
case input is
when ORDER_B =>
current_state <= STATE_D;
when others =>
current_state <= STATE_A;
end case;
when STATE_D =>
current_state <= STATE_A;
when others =>
current_state <= STATE_A;
end case;
end case;
end if;
end process;
state <= current_state;
end behave;
| mit | d6d9494656872b881c1dadf303231d66 | 0.508127 | 4.186391 | false | false | false | false |
Nooxet/embedded_bruteforce | vhdl/sg_pp_md_top.vhd | 4 | 3,629 | ----------------------------------------------------------------------------------
-- Engineer: Noxet
--
-- Module Name: sg_pp_md_top - Structural
-- Description:
-- A top module for string_generator, pre_processing and md5 modules
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity sg_pp_md_top is
port (
clk : in std_logic;
rstn : in std_logic;
i_start_sg : in std_logic;
i_halt_sg : in std_logic;
i_start_md5 : in std_logic;
o_hash : out unsigned(127 downto 0);
o_done_md5 : out std_logic
);
end sg_pp_md_top;
architecture Structural of sg_pp_md_top is
component string_generator
port (
clk : in std_logic;
rstn : in std_logic; -- active low reset ofc
i_start : in std_logic;
i_halt : in std_logic;
o_done : out std_logic;
o_length : out std_logic_vector(2 downto 0); -- max 6 chars
o_string : out std_logic_vector(47 downto 0) -- 6 char string
);
end component;
component pre_process
Port ( i_data : in STD_LOGIC_VECTOR (47 downto 0);
i_length : in STD_LOGIC_VECTOR (2 downto 0);
o_data_0 : out unsigned (31 downto 0);
o_data_1 : out unsigned (31 downto 0);
o_length : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component MD5
port (
clk : in std_logic;
rstn : in std_logic;
i_start : in std_logic;
--i_data : in unsigned(71 downto 0); -- 8 chars + 1 appended bit
i_data_0 : in unsigned(31 downto 0); -- first 4 chars
i_data_1 : in unsigned(31 downto 0); -- next 4 chars
i_length : in std_logic_vector(7 downto 0); -- nbr of chars
o_done : out std_logic;
o_hash_0 : out unsigned(31 downto 0);
o_hash_1 : out unsigned(31 downto 0);
o_hash_2 : out unsigned(31 downto 0);
o_hash_3 : out unsigned(31 downto 0)
);
end component;
signal s_len_sg_pp : std_logic_vector(2 downto 0); -- length sg->pp
signal s_len_pp_md5 : std_logic_vector(7 downto 0); -- length pp->md5
signal s_string_sg_pp : std_logic_vector(47 downto 0);
signal s_string1_pp_md5 : unsigned(31 downto 0);
signal s_string2_pp_md5 : unsigned(31 downto 0);
begin
sg_inst: string_generator
port map (
clk => clk,
rstn => rstn,
i_start => i_start_sg,
i_halt => i_halt_sg,
o_done => open,
o_length => s_len_sg_pp,
o_string => s_string_sg_pp
);
pp_inst: pre_process
port map(
i_data => s_string_sg_pp,
i_length => s_len_sg_pp,
o_data_0 => s_string1_pp_md5,
o_data_1 => s_string2_pp_md5,
o_length => s_len_pp_md5
);
MD5_inst: MD5
port map (
clk => clk,
rstn => rstn,
i_start => i_start_md5,
i_data_0 => s_string1_pp_md5,
i_data_1 => s_string2_pp_md5,
i_length => s_len_pp_md5,
o_done => o_done_md5,
o_hash_0 => o_hash(31 downto 0),
o_hash_1 => o_hash(63 downto 32),
o_hash_2 => o_hash(95 downto 64),
o_hash_3 => o_hash(127 downto 96)
);
end Structural;
| mit | a9c15065aac8b187db95d8c7cc0312af | 0.477818 | 3.516473 | false | false | false | false |
mithro/HDMI2USB | hdl/jpeg_encoder/design/DC_CR_ROM.vhd | 3 | 6,524 | -------------------------------------------------------------------------------
-- File Name : DC_CR_ROM.vhd
--
-- Project : JPEG_ENC
--
-- Module : DC_CR_ROM
--
-- Content : DC_CR_ROM Chrominance
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090329: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity DC_CR_ROM is
port
(
CLK : in std_logic;
RST : in std_logic;
VLI_size : in std_logic_vector(3 downto 0);
VLC_DC_size : out std_logic_vector(3 downto 0);
VLC_DC : out unsigned(10 downto 0)
);
end entity DC_CR_ROM;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of DC_CR_ROM is
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- DC-ROM
-------------------------------------------------------------------
p_DC_CR_ROM : process(CLK, RST)
begin
if RST = '1' then
VLC_DC_size <= X"0";
VLC_DC <= (others => '0');
elsif CLK'event and CLK = '1' then
case VLI_size is
when X"0" =>
VLC_DC_size <= X"2";
VLC_DC <= resize("00", VLC_DC'length);
when X"1" =>
VLC_DC_size <= X"2";
VLC_DC <= resize("01", VLC_DC'length);
when X"2" =>
VLC_DC_size <= X"2";
VLC_DC <= resize("10", VLC_DC'length);
when X"3" =>
VLC_DC_size <= X"3";
VLC_DC <= resize("110", VLC_DC'length);
when X"4" =>
VLC_DC_size <= X"4";
VLC_DC <= resize("1110", VLC_DC'length);
when X"5" =>
VLC_DC_size <= X"5";
VLC_DC <= resize("11110", VLC_DC'length);
when X"6" =>
VLC_DC_size <= X"6";
VLC_DC <= resize("111110", VLC_DC'length);
when X"7" =>
VLC_DC_size <= X"7";
VLC_DC <= resize("1111110", VLC_DC'length);
when X"8" =>
VLC_DC_size <= X"8";
VLC_DC <= resize("11111110", VLC_DC'length);
when X"9" =>
VLC_DC_size <= X"9";
VLC_DC <= resize("111111110", VLC_DC'length);
when X"A" =>
VLC_DC_size <= X"A";
VLC_DC <= resize("1111111110", VLC_DC'length);
when X"B" =>
VLC_DC_size <= X"B";
VLC_DC <= resize("11111111110", VLC_DC'length);
when others =>
VLC_DC_size <= X"0";
VLC_DC <= (others => '0');
end case;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- | bsd-2-clause | f407a8c2834805aa9328ae168f6cbbba | 0.353617 | 5.387283 | false | false | false | false |
mithro/HDMI2USB | hdl/jpeg_encoder/design/DCT1D.vhd | 3 | 14,044 | --------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT1D
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : DCT1D.VHD
-- Created : Sat Mar 5 7:37 2006
--
--------------------------------------------------------------------------------
--
-- Description : 1D Discrete Cosine Transform (1st stage)
--
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library WORK;
use WORK.MDCT_PKG.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity DCT1D is
port(
clk : in STD_LOGIC;
rst : in std_logic;
dcti : in std_logic_vector(IP_W-1 downto 0);
idv : in STD_LOGIC;
romedatao : in T_ROM1DATAO;
romodatao : in T_ROM1DATAO;
odv : out STD_LOGIC;
dcto : out std_logic_vector(OP_W-1 downto 0);
romeaddro : out T_ROM1ADDRO;
romoaddro : out T_ROM1ADDRO;
ramwaddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
ramdatai : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
ramwe : out STD_LOGIC;
wmemsel : out STD_LOGIC
);
end DCT1D;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture RTL of DCT1D is
type INPUT_DATA is array (N-1 downto 0) of SIGNED(IP_W downto 0);
signal databuf_reg : INPUT_DATA;
signal latchbuf_reg : INPUT_DATA;
signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0):=(others=>'0');
signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0):=(others=>'0');
signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0):=(others=>'0');
signal inpcnt_reg : UNSIGNED(RAMADRR_W/2-1 downto 0):=(others=>'0');
signal ramwe_s : STD_LOGIC:='0';
signal wmemsel_reg : STD_LOGIC:='0';
signal stage2_reg : STD_LOGIC:='0';
signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0):=(others=>'1');
signal col_2_reg : UNSIGNED(RAMADRR_W/2-1 downto 0):=(others=>'0');
signal ramwaddro_s : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0):=(others=>'0');
signal even_not_odd : std_logic:='0';
signal even_not_odd_d1 : std_logic:='0';
signal even_not_odd_d2 : std_logic:='0';
signal even_not_odd_d3 : std_logic:='0';
signal ramwe_d1 : STD_LOGIC:='0';
signal ramwe_d2 : STD_LOGIC:='0';
signal ramwe_d3 : STD_LOGIC:='0';
signal ramwe_d4 : STD_LOGIC:='0';
signal ramwaddro_d1 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0):=(others=>'0');
signal ramwaddro_d2 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0):=(others=>'0');
signal ramwaddro_d3 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0):=(others=>'0');
signal ramwaddro_d4 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0):=(others=>'0');
signal wmemsel_d1 : STD_LOGIC:='0';
signal wmemsel_d2 : STD_LOGIC:='0';
signal wmemsel_d3 : STD_LOGIC:='0';
signal wmemsel_d4 : STD_LOGIC:='0';
signal romedatao_d1 : T_ROM1DATAO;
signal romodatao_d1 : T_ROM1DATAO;
signal romedatao_d2 : T_ROM1DATAO;
signal romodatao_d2 : T_ROM1DATAO;
signal romedatao_d3 : T_ROM1DATAO;
signal romodatao_d3 : T_ROM1DATAO;
signal dcto_1 : STD_LOGIC_VECTOR(DA_W-1 downto 0):=(others=>'0');
signal dcto_2 : STD_LOGIC_VECTOR(DA_W-1 downto 0):=(others=>'0');
signal dcto_3 : STD_LOGIC_VECTOR(DA_W-1 downto 0):=(others=>'0');
signal dcto_4 : STD_LOGIC_VECTOR(DA_W-1 downto 0):=(others=>'0');
begin
ramwaddro <= ramwaddro_d4;
ramwe <= ramwe_d4;
ramdatai <= dcto_4(DA_W-1 downto 12);
wmemsel <= wmemsel_d4;
process(clk,rst)
begin
if rst = '1' then
inpcnt_reg <= (others => '0');
latchbuf_reg <= (others => (others => '0'));
databuf_reg <= (others => (others => '0'));
stage2_reg <= '0';
stage2_cnt_reg <= (others => '1');
ramwe_s <= '0';
ramwaddro_s <= (others => '0');
col_reg <= (others => '0');
row_reg <= (others => '0');
wmemsel_reg <= '0';
col_2_reg <= (others => '0');
elsif rising_edge(clk) then
stage2_reg <= '0';
ramwe_s <= '0';
--------------------------------
-- 1st stage
--------------------------------
if idv = '1' then
inpcnt_reg <= inpcnt_reg + 1;
-- right shift input data
latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
latchbuf_reg(N-1) <= SIGNED('0' & dcti) - LEVEL_SHIFT;
if inpcnt_reg = N-1 then
-- after this sum databuf_reg is in range of -256 to 254 (min to max)
databuf_reg(0) <= latchbuf_reg(1)+(SIGNED('0' & dcti) - LEVEL_SHIFT);
databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7);
databuf_reg(2) <= latchbuf_reg(3)+latchbuf_reg(6);
databuf_reg(3) <= latchbuf_reg(4)+latchbuf_reg(5);
databuf_reg(4) <= latchbuf_reg(1)-(SIGNED('0' & dcti) - LEVEL_SHIFT);
databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7);
databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6);
databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5);
stage2_reg <= '1';
end if;
end if;
--------------------------------
--------------------------------
-- 2nd stage
--------------------------------
if stage2_cnt_reg < N then
stage2_cnt_reg <= stage2_cnt_reg + 1;
-- write RAM
ramwe_s <= '1';
-- reverse col/row order for transposition purpose
ramwaddro_s <= STD_LOGIC_VECTOR(col_2_reg & row_reg);
-- increment column counter
col_reg <= col_reg + 1;
col_2_reg <= col_2_reg + 1;
-- finished processing one input row
if col_reg = 0 then
row_reg <= row_reg + 1;
-- switch to 2nd memory
if row_reg = N - 1 then
wmemsel_reg <= not wmemsel_reg;
col_reg <= (others => '0');
end if;
end if;
end if;
if stage2_reg = '1' then
stage2_cnt_reg <= (others => '0');
col_reg <= (0=>'1',others => '0');
col_2_reg <= (others => '0');
end if;
----------------------------------
end if;
end process;
-- output data pipeline
p_data_out_pipe : process(CLK, RST)
begin
if RST = '1' then
even_not_odd <= '0';
even_not_odd_d1 <= '0';
even_not_odd_d2 <= '0';
even_not_odd_d3 <= '0';
ramwe_d1 <= '0';
ramwe_d2 <= '0';
ramwe_d3 <= '0';
ramwe_d4 <= '0';
ramwaddro_d1 <= (others => '0');
ramwaddro_d2 <= (others => '0');
ramwaddro_d3 <= (others => '0');
ramwaddro_d4 <= (others => '0');
wmemsel_d1 <= '0';
wmemsel_d2 <= '0';
wmemsel_d3 <= '0';
wmemsel_d4 <= '0';
dcto_1 <= (others => '0');
dcto_2 <= (others => '0');
dcto_3 <= (others => '0');
dcto_4 <= (others => '0');
elsif CLK'event and CLK = '1' then
even_not_odd <= stage2_cnt_reg(0);
even_not_odd_d1 <= even_not_odd;
even_not_odd_d2 <= even_not_odd_d1;
even_not_odd_d3 <= even_not_odd_d2;
ramwe_d1 <= ramwe_s;
ramwe_d2 <= ramwe_d1;
ramwe_d3 <= ramwe_d2;
ramwe_d4 <= ramwe_d3;
ramwaddro_d1 <= ramwaddro_s;
ramwaddro_d2 <= ramwaddro_d1;
ramwaddro_d3 <= ramwaddro_d2;
ramwaddro_d4 <= ramwaddro_d3;
wmemsel_d1 <= wmemsel_reg;
wmemsel_d2 <= wmemsel_d1;
wmemsel_d3 <= wmemsel_d2;
wmemsel_d4 <= wmemsel_d3;
if even_not_odd = '0' then
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romedatao(0)),DA_W) +
(RESIZE(SIGNED(romedatao(1)),DA_W-1) & '0') +
(RESIZE(SIGNED(romedatao(2)),DA_W-2) & "00"),
DA_W));
else
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romodatao(0)),DA_W) +
(RESIZE(SIGNED(romodatao(1)),DA_W-1) & '0') +
(RESIZE(SIGNED(romodatao(2)),DA_W-2) & "00"),
DA_W));
end if;
if even_not_odd_d1 = '0' then
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romedatao_d1(3)),DA_W-3) & "000") +
(RESIZE(SIGNED(romedatao_d1(4)),DA_W-4) & "0000"),
DA_W));
else
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romodatao_d1(3)),DA_W-3) & "000") +
(RESIZE(SIGNED(romodatao_d1(4)),DA_W-4) & "0000"),
DA_W));
end if;
if even_not_odd_d2 = '0' then
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romedatao_d2(5)),DA_W-5) & "00000") +
(RESIZE(SIGNED(romedatao_d2(6)),DA_W-6) & "000000"),
DA_W));
else
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romodatao_d2(5)),DA_W-5) & "00000") +
(RESIZE(SIGNED(romodatao_d2(6)),DA_W-6) & "000000"),
DA_W));
end if;
if even_not_odd_d3 = '0' then
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romedatao_d3(7)),DA_W-7) & "0000000") -
(RESIZE(SIGNED(romedatao_d3(8)),DA_W-8) & "00000000"),
DA_W));
else
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romodatao_d3(7)),DA_W-7) & "0000000") -
(RESIZE(SIGNED(romodatao_d3(8)),DA_W-8) & "00000000"),
DA_W));
end if;
end if;
end process;
-- read precomputed MAC results from LUT
p_romaddr : process(CLK, RST)
begin
if RST = '1' then
romeaddro <= (others => (others => '0'));
romoaddro <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
for i in 0 to 8 loop
-- even
romeaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(i) &
databuf_reg(1)(i) &
databuf_reg(2)(i) &
databuf_reg(3)(i);
-- odd
romoaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(i) &
databuf_reg(5)(i) &
databuf_reg(6)(i) &
databuf_reg(7)(i);
end loop;
end if;
end process;
p_romdatao_d1 : process(CLK, RST)
begin
if RST = '1' then
romedatao_d1 <= (others => (others => '0'));
romodatao_d1 <= (others => (others => '0'));
romedatao_d2 <= (others => (others => '0'));
romodatao_d2 <= (others => (others => '0'));
romedatao_d3 <= (others => (others => '0'));
romodatao_d3 <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
romedatao_d1 <= romedatao;
romodatao_d1 <= romodatao;
romedatao_d2 <= romedatao_d1;
romodatao_d2 <= romodatao_d1;
romedatao_d3 <= romedatao_d2;
romodatao_d3 <= romodatao_d2;
end if;
end process;
end RTL;
--------------------------------------------------------------------------------
| bsd-2-clause | 240643afe81e06d0bfef8dcc2f258142 | 0.472515 | 3.641172 | false | false | false | false |
mithro/HDMI2USB | hdl/misc/image_selector.vhd | 3 | 11,357 | LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity image_selector is
port
(
-- HMDI input 0
rgb_H0 : in std_logic_vector(23 downto 0);
de_H0 : in std_logic;
pclk_H0 : in std_logic;
hsync_H0 : in std_logic;
vsync_H0 : in std_logic;
resX_H0 : in std_logic_vector(15 downto 0);
resY_H0 : in std_logic_vector(15 downto 0);
-- HMDI input 1
rgb_H1 : in std_logic_vector(23 downto 0);
de_H1 : in std_logic;
pclk_H1 : in std_logic;
hsync_H1 : in std_logic;
vsync_H1 : in std_logic;
resX_H1 : in std_logic_vector(15 downto 0);
resY_H1 : in std_logic_vector(15 downto 0);
-- Test Pattern
rgb_tp : in std_logic_vector(23 downto 0);
de_tp : in std_logic;
pclk_tp : in std_logic;
hsync_tp : in std_logic;
vsync_tp : in std_logic;
resX_tp : in std_logic_vector(15 downto 0);
resY_tp : in std_logic_vector(15 downto 0);
-- VGA input
rgb_vga : in std_logic_vector(23 downto 0);
de_vga : in std_logic;
pclk_vga : in std_logic;
hsync_vga : in std_logic;
vsync_vga : in std_logic;
resX_vga : in std_logic_vector(15 downto 0);
resY_vga : in std_logic_vector(15 downto 0);
-- selector_cmd
selector_cmd : in std_logic_vector(12 downto 0);
--Heart Beat Signals
HB_on : in std_logic; -- Port control of heart beat
HB_sw : in std_logic; -- Switch Control of heart beat
-- selected output
rgb : out std_logic_vector(23 downto 0);
de : out std_logic;
hsync : out std_logic;
vsync : out std_logic;
resX : out std_logic_vector(15 downto 0);
resY : out std_logic_vector(15 downto 0);
-- for HDMI Matrix input
rgb_H : out std_logic_vector(23 downto 0);
de_H : out std_logic;
pclk_H : out std_logic;
clk : in std_logic;
rst : in std_logic
);
end entity image_selector;
architecture rtl of image_selector is
COMPONENT image_selector_fifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT heart_beater is
Generic( HB_length : integer :=5; --length of the heart beat in pixels
HB_width : integer :=5; --width of the heart beat in pixels
alt_aft_frame : integer :=3 --alternate color after this many frames (max value 31)
);
PORT
(
clk : in std_logic;
rst : in std_logic;
HB_on : in std_logic;
HB_sw : in std_logic;
din : in std_logic_vector(23 downto 0);
vsync : in std_logic;
wr_en : in std_logic;
pclk_i : in std_logic;
resX : in std_logic_vector(15 downto 0);
resY : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(23 downto 0)
);
END COMPONENT;
signal pclk_i : std_logic;
signal hdmi_clk : std_logic;
--signal vga_tp_clk : std_logic;
signal full : std_logic;
signal almost_full : std_logic;
signal empty : std_logic;
signal almost_empty : std_logic;
signal valid : std_logic;
signal de_q : std_logic;
signal de_qq : std_logic;
signal de_qqq : std_logic;
signal de_qqqq : std_logic;
signal de_qqqqq : std_logic;
signal de_i : std_logic;
signal rgb_q : std_logic_vector(23 downto 0);
signal rgb_i : std_logic_vector(23 downto 0);
signal din : std_logic_vector(23 downto 0);
signal din_q : std_logic_vector(23 downto 0);
signal Y : std_logic_vector(17 downto 0);
signal Y1 : std_logic_vector(14 downto 0);
signal Y2 : std_logic_vector(16 downto 0);
signal Y3 : std_logic_vector(17 downto 0);
signal red_i : std_logic_vector(7 downto 0);
signal green_i : std_logic_vector(7 downto 0);
signal blue_i : std_logic_vector(7 downto 0);
signal red_q : std_logic_vector(7 downto 0);
signal green_q : std_logic_vector(7 downto 0);
signal blue_q : std_logic_vector(7 downto 0);
signal red_qq : std_logic_vector(7 downto 0);
signal green_qq : std_logic_vector(7 downto 0);
signal blue_qq : std_logic_vector(7 downto 0);
signal red_qqq : std_logic_vector(7 downto 0);
signal green_qqq : std_logic_vector(7 downto 0);
signal blue_qqq : std_logic_vector(7 downto 0);
signal selector : std_logic_vector(12 downto 0);
signal wr_en : std_logic;
signal de_H0_q : std_logic;
signal rgb_H0_q : std_logic_vector(23 downto 0);
signal hsync_H0_q : std_logic;
signal vsync_H0_q : std_logic;
signal resX_H0_q : std_logic_vector(15 downto 0);
signal resY_H0_q : std_logic_vector(15 downto 0);
signal rgb_H1_q : std_logic_vector(23 downto 0);
signal hsync_H1_q : std_logic;
signal de_H1_q : std_logic;
signal vsync_H1_q : std_logic;
signal resX_H1_q : std_logic_vector(15 downto 0);
signal resY_H1_q : std_logic_vector(15 downto 0);
signal rgb_tp_q : std_logic_vector(23 downto 0);
signal de_tp_q : std_logic;
signal hsync_tp_q : std_logic;
signal vsync_tp_q : std_logic;
signal resX_tp_q : std_logic_vector(15 downto 0);
signal resY_tp_q : std_logic_vector(15 downto 0);
signal resX_signal : std_logic_vector(15 downto 0);
signal resY_signal : std_logic_vector(15 downto 0);
signal vsync_s : std_logic;
begin
pclk_H <= pclk_i;--clk input to HDMI Matrix
resX <= resX_signal;
resY <= resY_signal;
process(rst,pclk_H0)
begin
if rst = '1' then
elsif rising_edge(pclk_H0) then
rgb_H0_q <=rgb_H0;
de_H0_q <= de_H0;
hsync_H0_q <= hsync_H0;
vsync_H0_q <= vsync_H0;
resX_H0_q <= resX_H0;
resY_H0_q <= resY_H0;
end if;
end process;
process(rst,pclk_H1)
begin
if rst = '1' then
elsif rising_edge(pclk_H1) then
rgb_H1_q <= rgb_H1;
de_H1_q <= de_H1;
hsync_H1_q <= hsync_H1;
vsync_H1_q <= vsync_H1;
resX_H1_q <= resX_H1;
resY_H1_q <= resY_H1;
end if;
end process;
process(rst,pclk_tp)
begin
if rst = '1' then
elsif rising_edge(pclk_tp) then
rgb_tp_q <= rgb_tp;
de_tp_q <= de_tp;
hsync_tp_q <= hsync_tp;
vsync_tp_q <= vsync_tp;
resX_tp_q <= resX_tp;
resY_tp_q <= resY_tp;
end if;
end process;
process(rst,pclk_i)
begin
if rst = '1' then
valid <= '0';
rgb_i <= (others => '0');
hsync <= '0';
vsync <= '0';
resX_signal <= (others => '0');
resY_signal <= (others => '0');
selector <= (others => '0');
elsif rising_edge(pclk_i) then
selector <= selector_cmd;
case selector(1 downto 0) is
when "00" => -- hdmi 0
rgb_i <= rgb_H0_q;
de_i <= de_H0_q;
hsync <= hsync_H0_q;
vsync <= vsync_H0_q;
resX_signal <= resX_H0_q;
resY_signal <= resY_H0_q;
vsync_s <= vsync_H0_q;
when "01" => -- hdmi 1
rgb_i <= rgb_H1_q;
de_i <= de_H1_q;
hsync <= hsync_H1_q;
vsync <= vsync_H1_q;
resX_signal <= resX_H1_q;
resY_signal <= resY_H1_q;
vsync_s <= vsync_H1_q;
-- when "10" => -- VGA
-- rgb_i <= rgb_vga_q;
-- valid <= de_vga_q;
-- hsync <= hsync_vga_q;
-- vsync <= vsync_vga_q;
-- resX_signal <= resX_vga_q;
-- resY_signal <= resY_vga_q;
when "11" => -- Test Pattern
rgb_i <= rgb_tp_q;
de_i <= de_tp_q;
hsync <= hsync_tp_q;
vsync <= vsync_tp_q;
resX_signal <= resX_tp_q;
resY_signal <= resY_tp_q;
vsync_s <= vsync_tp_q;
when others =>
end case;
end if;
end process;
BUFGMUX_HDMI : BUFGMUX
generic map (
CLK_SEL_TYPE => "SYNC" -- Glitchles ("SYNC") or fast ("ASYNC") clock switch-over
)
port map (
O => hdmi_clk, -- 1-bit output: Clock buffer output
I0 => pclk_H0, -- 1-bit input: Clock buffer input (S=0)
I1 => pclk_H1, -- 1-bit input: Clock buffer input (S=1)
S => selector_cmd(0) -- 1-bit input: Clock buffer select
);
-- BUFGMUX_VGATP : BUFGMUX
-- generic map (
-- CLK_SEL_TYPE => "SYNC" -- Glitchles ("SYNC") or fast ("ASYNC") clock switch-over
-- )
-- port map (
-- O => vga_tp_clk, -- 1-bit output: Clock buffer output
-- I0 => pclk_vga, -- 1-bit input: Clock buffer input (S=0)
-- I1 => pclk_tp, -- 1-bit input: Clock buffer input (S=1)
-- S => selector_q(0) -- 1-bit input: Clock buffer select
-- );
BUFGMUX_PCLK : BUFGMUX
generic map (
CLK_SEL_TYPE => "SYNC" -- Glitchles ("SYNC") or fast ("ASYNC") clock switch-over
)
port map (
O => pclk_i, -- 1-bit output: Clock buffer output
I0 => hdmi_clk, -- 1-bit input: Clock buffer input (S=0)
I1 => pclk_tp, -- 1-bit input: Clock buffer input (S=1)
S => selector_cmd(1) -- 1-bit input: Clock buffer select
);
Y <= Y1 + Y2 + Y3;
rgb_H <= din_q;
de_H <= wr_en;
imgprocess: process(rst,pclk_i)
begin
if rst = '1' then
rgb_q <= (others => '0');
elsif rising_edge(pclk_i) then
Y1 <= conv_std_logic_vector(113,7)*blue_qqq;
Y2 <= conv_std_logic_vector(307,9)*red_qqq;
Y3 <= conv_std_logic_vector(604,10)*green_qqq;
rgb_q <= (blue_i & green_i & red_i);
din <= rgb_q;
wr_en <= de_qqqqq;
de_q <= de_i;
de_qq <= de_q;
de_qqq <= de_qq;
de_qqqq <= de_qqq;
de_qqqqq<= de_qqqq;
if selector(10) = '1' then blue_q <= rgb_i(23 downto 16); else blue_q <= (others => '0'); end if;
if selector(11) = '1' then green_q <= rgb_i(15 downto 8); else green_q <= (others => '0'); end if;
if selector(12) = '1' then red_q <= rgb_i(7 downto 0); else red_q <= (others => '0'); end if;
case selector(5 downto 4) is -- blue
when "00" => blue_qq <= blue_q;
when "01" => blue_qq <= (blue_q(7 downto 3) & "000");
when "10" => blue_qq <= (blue_q(7 downto 4) & "0000");
when "11" => blue_qq <= (blue_q(7 downto 5) & "00000");
when others =>
end case;
case selector(7 downto 6) is -- green
when "00" => green_qq <= green_q;
when "01" => green_qq <= (green_q(7 downto 3) & "000");
when "10" => green_qq <= (green_q(7 downto 4) & "0000");
when "11" => green_qq <= (green_q(7 downto 5) & "00000");
when others =>
end case;
case selector(9 downto 8) is -- red
when "00" => red_qq <= red_q;
when "01" => red_qq <= (red_q(7 downto 3) & "000");
when "10" => red_qq <= (red_q(7 downto 4) & "0000");
when "11" => red_qq <= (red_q(7 downto 5) & "00000");
when others =>
end case;
if selector(3) = '1' then
blue_qqq <= ("11111111" - blue_qq);
green_qqq <= ("11111111" - green_qq);
red_qqq <= ("11111111" - red_qq);
else
blue_qqq <= blue_qq;
green_qqq <= green_qq;
red_qqq <= red_qq;
end if;
if selector(2) = '1' then
blue_i <= blue_qqq;
green_i <= green_qqq;
red_i <= red_qqq;
else
blue_i <= Y(17 downto 10);
green_i <= Y(17 downto 10);
red_i <= Y(17 downto 10);
end if;
end if;-- clk
end process; -- imgprocess
selector_fifo : image_selector_fifo
PORT MAP (
rst => rst,
wr_clk => pclk_i,
rd_clk => clk,
din => din_q,
wr_en => wr_en,
rd_en => '1',
dout => rgb,
full => full,
almost_full => almost_full,
empty => empty,
almost_empty => almost_empty,
valid => de
);
Inst_heart_beater: heart_beater
GENERIC MAP (
HB_length => 5,-- length of heart beat in pixel
HB_width => 5,-- width of heart beat in pixel
alt_aft_frame=>30 --the color alternates after this many frames
)
PORT MAP(
clk => clk,
rst =>rst ,
HB_on => HB_on,
HB_sw => HB_sw,
din => din,
wr_en => wr_en,
vsync => vsync_s,
pclk_i => pclk_i,
resX => resX_signal,
resY => resY_signal,
dout => din_q
);
end architecture;
| bsd-2-clause | cb9cf242ddf0fc05613b46c1e1779b05 | 0.608611 | 2.518182 | false | false | false | false |
freecores/gpib_controller | vhdl/src/gpib_helper/Clk2x.vhd | 1 | 2,249 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: Clk2x
-- Date:2012-02-02
-- Author: Andrzej Paluch
--
-- Description ${cursor}
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.VComponents.all;
entity Clk2x is
port (
reset: in std_logic;
clk : in std_logic;
clk2x : out std_logic
);
end Clk2x;
architecture arch of Clk2x is
signal GND_BIT, CLKFX_BUF : STD_LOGIC;
signal STATUS : std_logic_vector(7 downto 0);
begin
GND_BIT <= '0';
clk2x <= CLKFX_BUF;
DCM_INST : DCM
generic map(
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 2,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 20.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE
)
port map (CLKFB=>open,
CLKIN=>clk,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>reset,
CLKDV=>open,
CLKFX=>CLKFX_BUF,
CLKFX180=>open,
CLK0=>open,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>open,
PSDONE=>open,
STATUS(7 downto 0)=>STATUS
);
end arch;
| gpl-3.0 | 8934c121e2eed59a2b8056ad61bd6afb | 0.600711 | 3.402421 | false | false | false | false |
mithro/HDMI2USB | hdl/jpeg_encoder/jpeg_encoder_top.vhd | 3 | 13,486 | -- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- // Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity jpeg_encoder_top is
port
(
clk : in std_logic;
uvc_rst : in std_logic;
-- IMAGE RAM
iram_wdata : in std_logic_vector(23 downto 0);
iram_wren : in std_logic;
iram_fifo_afull : out std_logic;
-- OUT RAM
ram_byte : out std_logic_vector(7 downto 0);
ram_wren : out std_logic;
ram_wraddr : out std_logic_vector(23 downto 0); -- not used, not required
outif_almost_full : in std_logic;
resx : in std_logic_vector(15 DOWNTO 0);
resy : in std_logic_vector(15 DOWNTO 0);
-- cmd
jpeg_encoder_cmd : in std_logic_vector(1 downto 0); -- , encodingQuality(1 downto 0)
enable : in std_logic;
-- others
start : in std_logic;
done : out std_logic;
busy : out std_logic;
--debug signal
frame_size : out std_logic_vector(23 downto 0)
);
end entity jpeg_encoder_top;
architecture RTL of jpeg_encoder_top is
---------------------------------------------------------------------------------
component JpegEnc is
port
(
CLK : in std_logic;
RST : in std_logic;
-- OPB
OPB_ABus : in std_logic_vector(31 downto 0);
OPB_BE : in std_logic_vector(3 downto 0);
OPB_DBus_in : in std_logic_vector(31 downto 0);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_DBus_out : out std_logic_vector(31 downto 0);
OPB_XferAck : out std_logic;
OPB_retry : out std_logic;
OPB_toutSup : out std_logic;
OPB_errAck : out std_logic;
--% IMAGE RAM
iram_wdata : in std_logic_vector(23 downto 0);
iram_wren : in std_logic;
iram_fifo_afull : out std_logic;
--% OUT RAM
ram_byte : out std_logic_vector(7 downto 0);
ram_wren : out std_logic;
ram_wraddr : out std_logic_vector(23 downto 0);
outif_almost_full : in std_logic;
-- debug signal
frame_size : out std_logic_vector(23 downto 0)
);
end component JpegEnc;
------------------------------------------------------------------------
type ROMQ_TYPE is array (0 to 256-1) of std_logic_vector(7 downto 0);
constant qrom_lum : ROMQ_TYPE :=
(
-- 100%
X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01",
X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01",
X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01",
X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01",
X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01",
X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01",
X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01",
X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01",
-- 85%
X"05", X"03", X"04", X"04", X"04", X"03", X"05", X"04",
X"04", X"04", X"05", X"05", X"05", X"06", X"07", X"0C",
X"08", X"07", X"07", X"07", X"07", X"0F", X"0B", X"0B",
X"09", X"0C", X"11", X"0F", X"12", X"12", X"11", X"0F",
X"11", X"11", X"13", X"16", X"1C", X"17", X"13", X"14",
X"1A", X"15", X"11", X"11", X"18", X"21", X"18", X"1A",
X"1D", X"1D", X"1F", X"1F", X"1F", X"13", X"17", X"22",
X"24", X"22", X"1E", X"24", X"1C", X"1E", X"1F", X"1E",
-- 75%
X"08", X"06", X"06", X"07", X"06", X"05", X"08", X"07",
X"07", X"07", X"09", X"09", X"08", X"0A", X"0C", X"14",
X"0D", X"0C", X"0B", X"0B", X"0C", X"19", X"12", X"13",
X"0F", X"14", X"1D", X"1A", X"1F", X"1E", X"1D", X"1A",
X"1C", X"1C", X"20", X"24", X"2E", X"27", X"20", X"22",
X"2C", X"23", X"1C", X"1C", X"28", X"37", X"29", X"2C",
X"30", X"31", X"34", X"34", X"34", X"1F", X"27", X"39",
X"3D", X"38", X"32", X"3C", X"2E", X"33", X"34", X"32",
-- 50%
X"10", X"0B", X"0C", X"0E", X"0C", X"0A", X"10", X"0E",
X"0D", X"0E", X"12", X"11", X"10", X"13", X"18", X"28",
X"1A", X"18", X"16", X"16", X"18", X"31", X"23", X"25",
X"1D", X"28", X"3A", X"33", X"3D", X"3C", X"39", X"33",
X"38", X"37", X"40", X"48", X"5C", X"4E", X"40", X"44",
X"57", X"45", X"37", X"38", X"50", X"6D", X"51", X"57",
X"5F", X"62", X"67", X"68", X"67", X"3E", X"4D", X"71",
X"79", X"70", X"64", X"78", X"5C", X"65", X"67", X"63"
);
constant qrom_chr : ROMQ_TYPE :=
(
-- 100%
X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01",
X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01",
X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01",
X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01",
X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01",
X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01",
X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01",
X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01",
-- 85%
X"08", X"06", X"06", X"07", X"06", X"05", X"08", X"07",
X"07", X"07", X"09", X"09", X"08", X"0A", X"0C", X"14",
X"0D", X"0C", X"0B", X"0B", X"0C", X"19", X"12", X"13",
X"0F", X"14", X"1D", X"1A", X"1F", X"1E", X"1D", X"1A",
X"1C", X"1C", X"20", X"24", X"2E", X"27", X"20", X"22",
X"2C", X"23", X"1C", X"1C", X"28", X"37", X"29", X"2C",
X"30", X"31", X"34", X"34", X"34", X"1F", X"27", X"39",
X"3D", X"38", X"32", X"3C", X"2E", X"33", X"34", X"32",
-- 75% chrominance
X"09", X"09", X"09", X"0C", X"0B", X"0C", X"18", X"0D",
X"0D", X"18", X"32", X"21", X"1C", X"21", X"32", X"32",
X"32", X"32", X"32", X"32", X"32", X"32", X"32", X"32",
X"32", X"32", X"32", X"32", X"32", X"32", X"32", X"32",
X"32", X"32", X"32", X"32", X"32", X"32", X"32", X"32",
X"32", X"32", X"32", X"32", X"32", X"32", X"32", X"32",
X"32", X"32", X"32", X"32", X"32", X"32", X"32", X"32",
X"32", X"32", X"32", X"32", X"32", X"32", X"32", X"32",
-- 50% for chrominance
X"11", X"12", X"12", X"18", X"15", X"18", X"2F", X"1A",
X"1A", X"2F", X"63", X"42", X"38", X"42", X"63", X"63",
X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63",
X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63",
X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63",
X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63",
X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63",
X"63", X"63", X"63", X"63", X"63", X"63", X"63", X"63"
);
TYPE states is (s_reset,wait_for_enable,wait_for_start,write_lum_tables_wait,write_lum_tables,write_chr_tables_wait,write_res_reg,write_chr_tables,write_res_reg_done,write_start_reg,write_start_reg_done,write_reg_check_done,check_done);
SIGNAL ps : states;
-- OPB
signal OPB_ABus : std_logic_vector(31 downto 0);
signal OPB_BE : std_logic_vector(3 downto 0);
signal OPB_DBus_in : std_logic_vector(31 downto 0);
signal OPB_RNW : std_logic;
signal OPB_select : std_logic;
signal OPB_DBus_out : std_logic_vector(31 downto 0);
signal OPB_XferAck : std_logic;
signal OPB_retry : std_logic;
signal OPB_toutSup : std_logic;
signal OPB_errAck : std_logic;
signal counter : std_logic_vector(5 downto 0);
signal rst : std_logic;
signal iram_wdata_i : std_logic;
signal resx_q : std_logic_vector(15 DOWNTO 0);
signal resy_q : std_logic_vector(15 DOWNTO 0);
-- debug
signal frame_size_s : std_logic_vector(23 downto 0);
begin
--- sync process -----------------------------------------
sync: PROCESS(clk,uvc_rst)
BEGIN
IF uvc_rst = '1' THEN
ps <= s_reset;
rst <= '1';
ELSIF rising_edge(clk) THEN
resx_q <= resx;
resy_q <= resy;
CASE ps IS
when s_reset =>
counter <= (others => '0');
OPB_ABus <= (others => '0');
OPB_BE <= (others => '0');
OPB_DBus_in <= (others => '0');
OPB_RNW <= '0';
OPB_select <= '0';
busy <= '0';
done <= '1';
rst <= '1';
ps <= wait_for_enable;
when wait_for_enable =>
if enable = '1' then
ps <= write_lum_tables;
rst <= '0';
end if;
when write_lum_tables =>
counter <= counter + 1;
OPB_select <= '1';
OPB_ABus <= X"0000_0100" + counter*X"04";
OPB_RNW <= '0';
OPB_BE <= X"F";
OPB_DBus_in <= X"0000_00" & (qrom_lum(conv_integer((jpeg_encoder_cmd(1 downto 0) & counter))));
ps <= write_lum_tables_wait;
when write_lum_tables_wait =>
if OPB_XferAck /= '1' then
else
OPB_ABus <= (others => '0');
OPB_BE <= (others => '0');
OPB_DBus_in <= (others => '0');
OPB_RNW <= '0';
OPB_select <= '0';
if counter = 0 then
ps <= write_chr_tables;
counter <= (others =>'0');
else
ps <= write_lum_tables;
end if;
end if;
when write_chr_tables =>
counter <= counter + 1;
OPB_select <= '1';
OPB_ABus <= X"0000_0200" + counter*X"04";
OPB_RNW <= '0';
OPB_BE <= X"F";
OPB_DBus_in <= X"0000_00" & (qrom_chr(conv_integer((jpeg_encoder_cmd(0 downto 0) & counter))));
ps <= write_chr_tables_wait;
when write_chr_tables_wait =>
if OPB_XferAck /= '1' then
else
OPB_ABus <= (others => '0');
OPB_BE <= (others => '0');
OPB_DBus_in <= (others => '0');
OPB_RNW <= '0';
OPB_select <= '0';
if counter = 0 then
ps <= wait_for_start;
else
ps <= write_chr_tables;
end if;
end if;
when wait_for_start =>
if start = '1' then
OPB_select <= '1';
OPB_ABus <= X"0000_0004";
OPB_RNW <= '0';
OPB_BE <= X"F";
busy <= '1';
done <= '0';
OPB_DBus_in <= resx_q & resy_q;
ps <= write_res_reg_done;
end if;
when write_res_reg_done =>
if OPB_XferAck /= '1' then
else
OPB_ABus <= (others => '0');
OPB_BE <= (others => '0');
OPB_DBus_in <= (others => '0');
OPB_RNW <= '0';
OPB_select <= '0';
ps <= write_start_reg;
end if;
when write_start_reg =>
OPB_select <= '1';
OPB_ABus <= X"0000_0000";
OPB_RNW <= '0';
OPB_BE <= X"F";
OPB_DBus_in <= X"0000_0007"; -- RGB= 11, sof= 1,
ps <= write_start_reg_done;
when write_start_reg_done =>
if OPB_XferAck /= '1' then
else
OPB_ABus <= (others => '0');
OPB_BE <= (others => '0');
OPB_DBus_in <= (others => '0');
OPB_RNW <= '0';
OPB_select <= '0';
ps <= write_reg_check_done;
end if;
when write_reg_check_done =>
ps <= check_done;
OPB_select <= '1';
OPB_ABus <= X"0000_000C";
OPB_RNW <= '1';
OPB_BE <= X"F";
when check_done =>
if OPB_XferAck /= '1' then
else
if OPB_DBus_out = X"0000_0002" then
ps <= s_reset;
done <= '1';
busy <= '0';
frame_size <= frame_size_s;
else
OPB_ABus <= (others => '0');
OPB_BE <= (others => '0');
OPB_DBus_in <= (others => '0');
OPB_RNW <= '0';
OPB_select <= '0';
ps <= write_reg_check_done;
end if;
end if;
WHEN OTHERS =>
ps <= s_reset;
END CASE;
END IF;
END PROCESS sync;
iram_wdata_i <= iram_wren and enable;
-------------------------------------------------------------
jpegencoder: JpegEnc port map
(
--debug signal
frame_size => frame_size_s,
CLK => clk,
RST => rst,
-- OPB
OPB_ABus => OPB_ABus,
OPB_BE => OPB_BE,
OPB_DBus_in => OPB_DBus_in,
OPB_RNW => OPB_RNW,
OPB_select => OPB_select,
OPB_DBus_out => OPB_DBus_out,
OPB_XferAck => OPB_XferAck,
OPB_retry => OPB_retry,
OPB_toutSup => OPB_toutSup,
OPB_errAck => OPB_errAck,
-- IMAGE RAM
iram_wdata => iram_wdata,
iram_wren => iram_wdata_i,
iram_fifo_afull => iram_fifo_afull,
-- OUT RAM
ram_byte => ram_byte,
ram_wren => ram_wren,
ram_wraddr => ram_wraddr,
outif_almost_full => outif_almost_full
);
end architecture RTL;
| bsd-2-clause | 74a633a3539f174a84051bad04ef0ed0 | 0.506451 | 2.49141 | false | false | false | false |
Nooxet/embedded_bruteforce | brutus_system/hdl/system_clock_generator_0_wrapper.vhd | 1 | 3,263 | -------------------------------------------------------------------------------
-- system_clock_generator_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library clock_generator_0_v4_03_a;
use clock_generator_0_v4_03_a.all;
library clock_generator_v4_03_a;
use clock_generator_v4_03_a.all;
entity system_clock_generator_0_wrapper is
port (
CLKIN : in std_logic;
CLKOUT0 : out std_logic;
CLKOUT1 : out std_logic;
CLKOUT2 : out std_logic;
CLKOUT3 : out std_logic;
CLKOUT4 : out std_logic;
CLKOUT5 : out std_logic;
CLKOUT6 : out std_logic;
CLKOUT7 : out std_logic;
CLKOUT8 : out std_logic;
CLKOUT9 : out std_logic;
CLKOUT10 : out std_logic;
CLKOUT11 : out std_logic;
CLKOUT12 : out std_logic;
CLKOUT13 : out std_logic;
CLKOUT14 : out std_logic;
CLKOUT15 : out std_logic;
CLKFBIN : in std_logic;
CLKFBOUT : out std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
PSDONE : out std_logic;
RST : in std_logic;
LOCKED : out std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of system_clock_generator_0_wrapper : entity is "clock_generator_v4_03_a";
end system_clock_generator_0_wrapper;
architecture STRUCTURE of system_clock_generator_0_wrapper is
component clock_generator is
generic (
C_FAMILY : STRING;
C_DEVICE : STRING;
C_PACKAGE : STRING;
C_SPEEDGRADE : STRING
);
port (
CLKIN : in std_logic;
CLKOUT0 : out std_logic;
CLKOUT1 : out std_logic;
CLKOUT2 : out std_logic;
CLKOUT3 : out std_logic;
CLKOUT4 : out std_logic;
CLKOUT5 : out std_logic;
CLKOUT6 : out std_logic;
CLKOUT7 : out std_logic;
CLKOUT8 : out std_logic;
CLKOUT9 : out std_logic;
CLKOUT10 : out std_logic;
CLKOUT11 : out std_logic;
CLKOUT12 : out std_logic;
CLKOUT13 : out std_logic;
CLKOUT14 : out std_logic;
CLKOUT15 : out std_logic;
CLKFBIN : in std_logic;
CLKFBOUT : out std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
PSDONE : out std_logic;
RST : in std_logic;
LOCKED : out std_logic
);
end component;
begin
clock_generator_0 : clock_generator
generic map (
C_FAMILY => "spartan6",
C_DEVICE => "6slx16",
C_PACKAGE => "csg324",
C_SPEEDGRADE => "-3"
)
port map (
CLKIN => CLKIN,
CLKOUT0 => CLKOUT0,
CLKOUT1 => CLKOUT1,
CLKOUT2 => CLKOUT2,
CLKOUT3 => CLKOUT3,
CLKOUT4 => CLKOUT4,
CLKOUT5 => CLKOUT5,
CLKOUT6 => CLKOUT6,
CLKOUT7 => CLKOUT7,
CLKOUT8 => CLKOUT8,
CLKOUT9 => CLKOUT9,
CLKOUT10 => CLKOUT10,
CLKOUT11 => CLKOUT11,
CLKOUT12 => CLKOUT12,
CLKOUT13 => CLKOUT13,
CLKOUT14 => CLKOUT14,
CLKOUT15 => CLKOUT15,
CLKFBIN => CLKFBIN,
CLKFBOUT => CLKFBOUT,
PSCLK => PSCLK,
PSEN => PSEN,
PSINCDEC => PSINCDEC,
PSDONE => PSDONE,
RST => RST,
LOCKED => LOCKED
);
end architecture STRUCTURE;
| mit | 0ec609cdb5c51af889efd95824db5eed | 0.57585 | 3.641741 | false | false | false | false |
UdayanSinha/Code_Blocks | Nios-2/Nios/practica4/mi_nios/mi_nios_inst.vhd | 1 | 2,791 | component mi_nios is
port (
clk_clk : in std_logic := 'X'; -- clk
flash_dclk : out std_logic; -- dclk
flash_sce : out std_logic; -- sce
flash_sdo : out std_logic; -- sdo
flash_data0 : in std_logic := 'X'; -- data0
led_export : out std_logic_vector(7 downto 0); -- export
reset_reset_n : in std_logic := 'X'; -- reset_n
sdram_addr : out std_logic_vector(11 downto 0); -- addr
sdram_ba : out std_logic_vector(1 downto 0); -- ba
sdram_cas_n : out std_logic; -- cas_n
sdram_cke : out std_logic; -- cke
sdram_cs_n : out std_logic; -- cs_n
sdram_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
sdram_dqm : out std_logic_vector(1 downto 0); -- dqm
sdram_ras_n : out std_logic; -- ras_n
sdram_we_n : out std_logic; -- we_n
sdram_clk_clk : out std_logic; -- clk
sw_export : in std_logic_vector(3 downto 0) := (others => 'X') -- export
);
end component mi_nios;
u0 : component mi_nios
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
flash_dclk => CONNECTED_TO_flash_dclk, -- flash.dclk
flash_sce => CONNECTED_TO_flash_sce, -- .sce
flash_sdo => CONNECTED_TO_flash_sdo, -- .sdo
flash_data0 => CONNECTED_TO_flash_data0, -- .data0
led_export => CONNECTED_TO_led_export, -- led.export
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
sdram_addr => CONNECTED_TO_sdram_addr, -- sdram.addr
sdram_ba => CONNECTED_TO_sdram_ba, -- .ba
sdram_cas_n => CONNECTED_TO_sdram_cas_n, -- .cas_n
sdram_cke => CONNECTED_TO_sdram_cke, -- .cke
sdram_cs_n => CONNECTED_TO_sdram_cs_n, -- .cs_n
sdram_dq => CONNECTED_TO_sdram_dq, -- .dq
sdram_dqm => CONNECTED_TO_sdram_dqm, -- .dqm
sdram_ras_n => CONNECTED_TO_sdram_ras_n, -- .ras_n
sdram_we_n => CONNECTED_TO_sdram_we_n, -- .we_n
sdram_clk_clk => CONNECTED_TO_sdram_clk_clk, -- sdram_clk.clk
sw_export => CONNECTED_TO_sw_export -- sw.export
);
| mit | e181ec78599b99626eaff52d7b5bb5f7 | 0.424221 | 3.44143 | false | false | false | false |
quicky2000/giovanni_card | giovanni_card.vhd | 1 | 3,807 | --
-- This file is part of giovanni_card
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity giovanni_card is
Port ( w1a : inout STD_LOGIC_VECTOR (15 downto 0);
w1b : inout STD_LOGIC_VECTOR (15 downto 0);
scr_red : in STD_LOGIC_VECTOR (5 downto 0);
scr_green : in STD_LOGIC_VECTOR (5 downto 0);
scr_blue : in STD_LOGIC_VECTOR (5 downto 0);
scr_clk : in STD_LOGIC;
scr_hsync : in STD_LOGIC;
scr_vsync : in STD_LOGIC;
scr_enable : in STD_LOGIC;
scr_right_left : in STD_LOGIC;
scr_up_down : in STD_LOGIC;
audio_right : in STD_LOGIC; --pin 2 audio
audio_left : in STD_LOGIC; -- pin 3 audio
audio_stereo_ok : out STD_LOGIC; -- pin 4 audio
audio_plugged : out STD_LOGIC; -- pin 5 audio
io : inout STD_LOGIC_VECTOR (3 downto 0));
end giovanni_card;
architecture Behavioral of giovanni_card is
signal reg_scr_red : std_logic_vector(5 downto 0) := (others => '0');
signal reg_scr_green : std_logic_vector(5 downto 0) := (others => '0');
signal reg_scr_blue : std_logic_vector(5 downto 0) := (others => '0');
signal reg_scr_hsync : std_logic := '0';
signal reg_scr_vsync : std_logic := '0';
signal reg_scr_enable : std_logic := '0';
begin
screens_signals_register : process(scr_clk)
begin
if rising_edge(scr_clk) then
reg_scr_red <= scr_red;
reg_scr_green <= scr_green;
reg_scr_blue <= scr_blue;
reg_scr_hsync <= scr_hsync;
reg_scr_vsync <= scr_vsync;
reg_scr_enable <= scr_enable;
end if;
end process;
w1a(0) <= io(0);
w1a(1) <= io(1);
w1a(2) <= scr_up_down; -- LCD_31
w1a(3) <= reg_scr_enable; -- LCD_27
w1a(4) <= reg_scr_blue(5); -- LCD_25
w1a(5) <= reg_scr_blue(3); -- LCD_23
w1a(6) <= reg_scr_blue(1); -- LCD_21
w1a(7) <= reg_scr_green(4); -- LCD_17
w1a(8) <= reg_scr_green(2); -- LCD_15
w1a(9) <= reg_scr_green(0); -- LCD_13
w1a(10) <= reg_scr_red(5); -- LCD_11
w1a(11) <= reg_scr_red(3); -- LCD_9
w1a(12) <= reg_scr_red(1); -- LCD_7
w1a(13) <= reg_scr_hsync; -- LCD_3
w1a(14) <= audio_right;
w1a(15) <= audio_left;
audio_stereo_ok <= w1b(0);
audio_plugged <= w1b(1);
w1b(2) <= scr_clk; -- LCD 2
w1b(3) <= reg_scr_vsync; -- LCD 4
w1b(4) <= reg_scr_red(0); -- LCD_6
w1b(5) <= reg_scr_red(2); -- LCD_8
w1b(6) <= reg_scr_red(4); -- LCD_10
w1b(7) <= reg_scr_green(1); -- LCD_14
w1b(8) <= reg_scr_green(3); -- LCD_16
w1b(9) <= reg_scr_green(5); -- LCD_18
w1b(10) <= reg_scr_blue(0); -- LCD_20
w1b(11) <= reg_scr_blue(2); -- LCD_22
w1b(12) <= reg_scr_blue(4); -- LCD_24
w1b(13) <= scr_right_left; --LCD_30
w1b(14) <= io(2);
w1b(15) <= io(3);
end Behavioral;
| gpl-3.0 | fe4792dca0f84d1786e5211fcdb03d31 | 0.606777 | 2.824184 | false | false | false | false |
freecores/gpib_controller | vhdl/test/gpibCableEmulator.vhd | 1 | 3,179 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
-- Author: Andrzej Paluch
--
-- Create Date: 17:07:00 10/22/2011
-- Design Name:
-- Module Name: gpibCableEmulator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity gpibCableEmulator is port (
-- interface signals
DIO_1 : in std_logic_vector (7 downto 0);
output_valid_1 : in std_logic;
DIO_2 : in std_logic_vector (7 downto 0);
output_valid_2 : in std_logic;
DIO : out std_logic_vector (7 downto 0);
-- attention
ATN_1 : in std_logic;
ATN_2 : in std_logic;
ATN : out std_logic;
-- data valid
DAV_1 : in std_logic;
DAV_2 : in std_logic;
DAV : out std_logic;
-- not ready for data
NRFD_1 : in std_logic;
NRFD_2 : in std_logic;
NRFD : out std_logic;
-- no data accepted
NDAC_1 : in std_logic;
NDAC_2 : in std_logic;
NDAC : out std_logic;
-- end or identify
EOI_1 : in std_logic;
EOI_2 : in std_logic;
EOI : out std_logic;
-- service request
SRQ_1 : in std_logic;
SRQ_2 : in std_logic;
SRQ : out std_logic;
-- interface clear
IFC_1 : in std_logic;
IFC_2 : in std_logic;
IFC : out std_logic;
-- remote enable
REN_1 : in std_logic;
REN_2 : in std_logic;
REN : out std_logic
);
end gpibCableEmulator;
architecture Behavioral of gpibCableEmulator is
signal DIO_1_mid, DIO_2_mid : std_logic_vector (7 downto 0);
begin
with output_valid_1 select DIO_1_mid <=
DIO_1 when '1',
"00000000" when others;
with output_valid_2 select DIO_2_mid <=
DIO_2 when '1',
"00000000" when others;
DIO <= not (not DIO_1_mid and not DIO_2_mid);
ATN <= not(not ATN_1 and not ATN_2);
DAV <= not(not DAV_1 and not DAV_2);
NRFD <= not(not NRFD_1 and not NRFD_2);
NDAC <= not(not NDAC_1 and not NDAC_2);
EOI <= not(not EOI_1 and not EOI_2);
SRQ <= not(not SRQ_1 and not SRQ_2);
IFC <= not(not IFC_1 and not IFC_2);
REN <= not(not REN_1 and not REN_2);
end Behavioral;
| gpl-3.0 | 4ad13d5b00826742219d03bd009313c1 | 0.631645 | 3.237271 | false | false | false | false |
esar/hdmilight-v2 | fpga/top.vhd | 1 | 15,635 | ----------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Stephen Robinson
--
-- This file is part of HDMI-Light
--
-- HDMI-Light is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- HDMI-Light is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file names COPING).
-- If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity HdmilightTop is
Port
(
ADV_P : in STD_LOGIC_VECTOR(23 downto 0);
ADV_LLC : in STD_LOGIC;
ADV_AP : in STD_LOGIC;
ADV_SCLK : in STD_LOGIC;
ADV_LRCLK : in STD_LOGIC;
ADV_MCLK : in STD_LOGIC;
ADV_SCL : inout STD_LOGIC;
ADV_SDA : inout STD_LOGIC;
ADV_INT1 : in STD_LOGIC;
ADV_RST : out STD_LOGIC;
ADV_HS : in STD_LOGIC;
ADV_VS : in STD_LOGIC;
ADV_DE : in STD_LOGIC;
OUTPUT : out STD_LOGIC_VECTOR(7 downto 0);
RX : in STD_LOGIC;
TX : inout STD_LOGIC;
CLK : in STD_LOGIC;
FLASH_CK : out STD_LOGIC;
FLASH_CS : out STD_LOGIC;
FLASH_SI : out STD_LOGIC;
FLASH_SO : in STD_LOGIC;
GPIO : inout STD_LOGIC_VECTOR(3 downto 0)
);
end HdmilightTop;
architecture Behavioral of HdmilightTop is
-----------------------------------------------
-- Component Definitions
-----------------------------------------------
COMPONENT DCM32to16
PORT(
CLKIN_IN : IN std_logic;
CLKFX_OUT : OUT std_logic;
CLKIN_IBUFG_OUT : OUT std_logic;
CLK0_OUT : OUT std_logic
);
END COMPONENT;
component data_mem
port ( I_CLK : in std_logic;
I_ADR : in std_logic_vector(10 downto 0);
I_DIN : in std_logic_vector(15 downto 0);
I_WE : in std_logic_vector( 1 downto 0);
Q_DOUT : out std_logic_vector(15 downto 0));
end component;
component cpu_core
port ( I_CLK : in std_logic;
I_CE : in std_logic;
I_CLR : in std_logic;
I_INTVEC : in std_logic_vector( 5 downto 0);
I_DIN : in std_logic_vector(15 downto 0);
Q_OPC : out std_logic_vector(15 downto 0);
Q_PC : out std_logic_vector(15 downto 0);
Q_DOUT : out std_logic_vector(15 downto 0);
Q_ADR : out std_logic_vector(15 downto 0);
Q_RD_IO : out std_logic;
Q_WE_IO : out std_logic;
Q_WE_SRAM : out std_logic_vector(1 downto 0));
end component;
component uart
generic (
divisor : integer := 139 );
port (
clk : in std_logic;
reset : in std_logic;
--
txdata : in std_logic_vector(7 downto 0);
rxdata : out std_logic_vector(7 downto 0);
wr : in std_logic;
rd : in std_logic;
tx_avail : out std_logic;
tx_busy : out std_logic;
rx_avail : out std_logic;
rx_full : out std_logic;
rx_error : out std_logic;
--
uart_rxd : in std_logic;
uart_txd : out std_logic
);
end component;
component flashDMAController
Port (
clk : in std_logic;
flashStartAddr : in std_logic_vector(23 downto 0);
sramStartAddr : in std_logic_vector(15 downto 0);
copySize : in std_logic_vector(15 downto 0);
write : in std_logic;
start : in std_logic;
busy : out std_logic;
we : out std_logic;
addr : out std_logic_vector(15 downto 0);
din : in std_logic_vector( 7 downto 0);
dout : out std_logic_vector( 7 downto 0);
spiClk : out std_logic;
spiCs : out std_logic;
spiSi : out std_logic;
spiSo : in std_logic
);
end component;
-----------------------------------------------
-- Signals
-----------------------------------------------
signal RST: std_logic:= '1';
signal RST_COUNT: std_logic_vector(1 downto 0):="00";
signal CLK16: std_logic;
-- UART
signal UART_TX_DATA : std_logic_vector(7 downto 0):=X"00";
signal UART_RX_DATA : std_logic_vector(7 downto 0):=X"00";
signal UART_WR : std_logic := '0';
signal UART_RD : std_logic := '0';
signal UART_TX_AVAIL : std_logic := '0';
signal UART_TX_BUSY : std_logic := '0';
signal UART_RX_AVAIL : std_logic := '0';
signal UART_RX_FULL : std_logic := '0';
signal UART_RX_ERROR : std_logic := '0';
-- MCU
signal MCU_RST: std_logic:= '1';
signal MCU_RUN: std_logic:= '0';
signal MCU_CLK: std_logic:= '0';
signal MCU_INTVEC: std_logic_vector(5 downto 0);
signal MCU_INST : std_logic_vector(16-1 downto 0):=(others=>'0');
signal MCU_PC : std_logic_vector(16-1 downto 0):=(others=>'0');
-- MCU IO bus control
signal MCU_IO_RD: std_logic:= '0';
signal MCU_IO_WR: std_logic:= '0';
signal MCU_SRAM_WR : std_logic_vector(1 downto 0);
signal MCU_ADDR : std_logic_vector(15 downto 0):=(others=>'0');
signal MCU_DOUT : std_logic_vector(15 downto 0);
signal MCU_DIN : std_logic_vector(15 downto 0);
signal MCU_IO_DATA_READ : std_logic_vector(8-1 downto 0):=(others=>'0');
signal MASTER_WE : std_logic_vector(1 downto 0);
signal MASTER_ADDR : std_logic_vector(15 downto 0);
signal MASTER_DOUT : std_logic_vector(15 downto 0);
signal MASTER_DIN : std_logic_vector(15 downto 0);
signal SRAM_WE : std_logic_vector(1 downto 0);
signal SRAM_DOUT : std_logic_vector(15 downto 0);
signal SRAM_DIN : std_logic_vector(15 downto 0);
-- MCU TMR
signal MCU_TIMER_VAL : std_logic_vector(32-1 downto 0):=(others=>'0');
signal MCU_TIMER_CNT : std_logic_vector(32-1 downto 0):=(others=>'0');
signal MCU_TIMER_LATCHED : std_logic_vector(32-1 downto 0):=(others=>'0');
signal DDRD : std_logic_vector(7 downto 0);
signal PIND : std_logic_vector(7 downto 0);
signal PORTD : std_logic_vector(7 downto 0);
signal DMA_SRAM_ADDR : std_logic_vector(15 downto 0);
signal DMA_FLASH_ADDR : std_logic_vector(23 downto 0);
signal DMA_BYTE_COUNT : std_logic_vector(15 downto 0);
signal DMA_WRITE : std_logic;
signal DMA_START : std_logic;
signal DMA_BUSY : std_logic;
signal DMA_WE : std_logic;
signal DMA_ADDR : std_logic_vector(15 downto 0);
signal DMA_DOUT : std_logic_vector(7 downto 0);
signal DMA_DIN : std_logic_vector(7 downto 0);
signal DMA_IN_PROGRESS: std_logic;
signal DMA_BUSY_PREV : std_logic;
signal vidclk : std_logic;
signal viddata_r : std_logic_vector(7 downto 0);
signal viddata_g : std_logic_vector(7 downto 0);
signal viddata_b : std_logic_vector(7 downto 0);
signal hblank : std_logic_vector(1 downto 0);
signal vblank : std_logic_vector(1 downto 0);
signal dataenable : std_logic_vector(1 downto 0);
signal AMBILIGHT_CFG_WE : std_logic;
signal AMBILIGHT_CFG_ADDR : std_logic_vector(15 downto 0);
signal AMBILIGHT_CFG_DIN : std_logic_vector(7 downto 0);
signal AMBILIGHT_CFG_DOUT : std_logic_vector(7 downto 0);
signal driverOutput : std_logic_vector(7 downto 0);
signal INT_CLEAR : std_logic_vector(7 downto 0);
signal INT_FORMAT : std_logic;
signal formatChanged : std_logic;
begin
-----------------------------------------------
-- Instantiation
-----------------------------------------------
ambilight : entity work.ambilight port map(vidclk, viddata_r, viddata_g, viddata_b, hblank(1), vblank(1), dataenable(1),
CLK16,
AMBILIGHT_CFG_WE,
AMBILIGHT_CFG_ADDR,
AMBILIGHT_CFG_DIN,
AMBILIGHT_CFG_DOUT,
driverOutput,
formatChanged);
Inst_DCM32to16: DCM32to16 PORT MAP(
CLKIN_IN => CLK,
CLKFX_OUT => CLK16,
CLKIN_IBUFG_OUT => open,
CLK0_OUT => open
);
dma : flashDMAController port map(
CLK16,
DMA_FLASH_ADDR,
DMA_SRAM_ADDR,
DMA_BYTE_COUNT,
DMA_WRITE,
DMA_START,
DMA_BUSY,
DMA_WE,
DMA_ADDR,
DMA_DIN,
DMA_DOUT,
FLASH_CK,
FLASH_CS,
FLASH_SI,
FLASH_SO
);
SRAM : data_mem port map(
I_CLK => CLK16,
I_ADR => MASTER_ADDR(10 downto 0),
I_DIN => SRAM_DIN,
I_WE => SRAM_WE,
Q_DOUT => SRAM_DOUT
);
-- Simple fixed baud UART
U2_UART: uart port map ( CLK16, RST, UART_TX_DATA, UART_RX_DATA, UART_WR, UART_RD,
UART_TX_AVAIL, UART_TX_BUSY, UART_RX_AVAIL, UART_RX_FULL, UART_RX_ERROR,
rx, tx);
-- AVR Core
U3_AVR_MCU: cpu_core port map (
I_CLK => MCU_CLK,
I_CE => MCU_RUN,
I_CLR => MCU_RST,
I_DIN => MCU_DIN,
I_INTVEC => MCU_INTVEC,
Q_ADR => MCU_ADDR,
Q_DOUT => MCU_DOUT,
Q_OPC => MCU_INST,
Q_PC => MCU_PC,
Q_RD_IO => MCU_IO_RD,
Q_WE_IO => MCU_IO_WR,
Q_WE_SRAM => MCU_SRAM_WR);
-----------------------------------------------
-- Implementation
-----------------------------------------------
-- Reset Generator
process (CLK16)
begin
if (rising_edge(CLK16)) then
if (RST_COUNT = X"3") then
RST <= '0';
else
RST_COUNT <= RST_COUNT + 1;
end if;
end if;
end process;
process(RST,CLK16)
begin
if(RST = '1') then
INT_FORMAT <= '0';
MCU_INTVEC <= (others => '0');
elsif(rising_edge(CLK16)) then
if(formatChanged = '1') then
INT_FORMAT <= '1';
elsif(INT_CLEAR(0) = '1') then
INT_FORMAT <= '0';
end if;
if(ADV_INT1 = '1') then
MCU_INTVEC <= "100010";
elsif(INT_FORMAT = '1') then
MCU_INTVEC <= "100001";
else
MCU_INTVEC <= (others => '0');
end if;
end if;
end process;
-- IO memory space handler
process (RST,CLK16)
begin
if (RST = '1') then
UART_TX_DATA <= X"00";
UART_WR <= '0';
UART_RD <= '0';
MCU_TIMER_LATCHED <= (others=>'0');
INT_CLEAR <= (others => '0');
elsif (rising_edge(CLK16)) then
UART_WR <= '0';
UART_RD <= '0';
DMA_START <= '0';
INT_CLEAR <= (others => '0');
-- IO Read Cycle
if (MCU_IO_RD = '1') then
case MASTER_ADDR is
-- 0x21 -> Uart - UDR - TX BUF
when X"0041" =>
UART_RD <= '1';
when others =>
end case;
end if;
-- IO Write Cycle
if (MCU_IO_WR = '1') then
case MASTER_ADDR is
-- 0x21 -> Uart - UDR - TX BUF
when X"0041" =>
UART_TX_DATA <= MASTER_DOUT(7 downto 0);
UART_WR <= '1';
-- 0x22 -> 32-bit Timer Control
when X"0042" =>
-- Take snapshot of current timer value
MCU_TIMER_LATCHED <= MCU_TIMER_VAL;
when X"0049" =>
DDRD <= MASTER_DOUT(7 downto 0);
when X"004b" =>
PORTD <= MASTER_DOUT(7 downto 0);
when X"004c" =>
DMA_FLASH_ADDR(23 downto 16) <= MASTER_DOUT(7 downto 0);
when X"004d" =>
DMA_FLASH_ADDR(15 downto 8) <= MASTER_DOUT(7 downto 0);
when X"004e" =>
DMA_FLASH_ADDR( 7 downto 0) <= MASTER_DOUT(7 downto 0);
when X"004f" =>
DMA_SRAM_ADDR(15 downto 8) <= MASTER_DOUT(7 downto 0);
when X"0050" =>
DMA_SRAM_ADDR( 7 downto 0) <= MASTER_DOUT(7 downto 0);
when X"0051" =>
DMA_BYTE_COUNT(15 downto 8) <= MASTER_DOUT(7 downto 0);
when X"0052" =>
DMA_BYTE_COUNT( 7 downto 0) <= MASTER_DOUT(7 downto 0);
when X"0053" =>
DMA_WRITE <= MASTER_DOUT(0);
DMA_IN_PROGRESS <= '1';
DMA_START <= '1';
when X"0054" =>
INT_CLEAR <= MASTER_DOUT(7 downto 0);
when others =>
end case;
end if;
if(DMA_BUSY = '0' and DMA_BUSY_PREV = '1') then
DMA_IN_PROGRESS <= '0';
end if;
DMA_BUSY_PREV <= DMA_BUSY;
end if;
end process;
-- Asynchronous IO Read Process
process (MCU_IO_RD, MASTER_ADDR, UART_RX_ERROR, UART_TX_BUSY, UART_RX_FULL, UART_TX_AVAIL, UART_RX_AVAIL, UART_RX_DATA, MCU_TIMER_LATCHED,
DDRD, PIND, PORTD)
begin
-- Read cycle?
if (MCU_IO_RD = '1') then
case MASTER_ADDR is
-- 0x20 -> Uart - USR - Status Reg
when X"0040" =>
MCU_IO_DATA_READ <= "000" & UART_RX_ERROR & UART_TX_BUSY & UART_RX_FULL & UART_TX_AVAIL & UART_RX_AVAIL;
-- 0x21 -> Uart - UDR - RX BUF
when X"0041" =>
MCU_IO_DATA_READ <= UART_RX_DATA;
-- 0x22,23,24,25 -> 32-bit Timer
when X"0042" =>
MCU_IO_DATA_READ <= MCU_TIMER_LATCHED(7 downto 0);
when X"0043" =>
MCU_IO_DATA_READ <= MCU_TIMER_LATCHED(15 downto 8);
when X"0044" =>
MCU_IO_DATA_READ <= MCU_TIMER_LATCHED(23 downto 16);
when X"0045" =>
MCU_IO_DATA_READ <= MCU_TIMER_LATCHED(31 downto 24);
when X"0049" =>
MCU_IO_DATA_READ <= DDRD;
when X"004a" =>
MCU_IO_DATA_READ <= PIND;
when X"004b" =>
MCU_IO_DATA_READ <= PORTD;
when others =>
MCU_IO_DATA_READ <= X"00";
end case;
else
MCU_IO_DATA_READ <= X"00";
end if;
end process;
-- Timer (1 ms resolution)
process (RST,CLK16)
begin
if (RST = '1') then
MCU_TIMER_VAL <= (others=>'0');
MCU_TIMER_CNT <= (others=>'0');
elsif (rising_edge(CLK16)) then
-- 16000/0x3E80 = 1ms @ 16MHz
if (MCU_TIMER_CNT = X"3E80") then
MCU_TIMER_VAL <= MCU_TIMER_VAL + 1;
MCU_TIMER_CNT <= (others=>'0');
else
MCU_TIMER_CNT <= MCU_TIMER_CNT + 1;
end if;
end if;
end process;
process(ADV_LLC)
begin
if(rising_edge(ADV_LLC)) then
viddata_r <= ADV_P(23 downto 16);
viddata_g <= ADV_P(15 downto 8);
viddata_b <= ADV_P( 7 downto 0);
end if;
end process;
process(ADV_LLC)
begin
if(rising_edge(ADV_LLC)) then
hblank <= hblank(0) & (not ADV_HS);
vblank <= vblank(0) & (not ADV_VS);
dataenable <= dataenable(0) & ADV_DE;
end if;
end process;
-----------------------------------------------
-- Combinatorial
-----------------------------------------------
MCU_CLK <= CLK16;
MCU_RST <= RST;
MCU_RUN <= not DMA_IN_PROGRESS;
MASTER_WE <= '0' & DMA_WE when DMA_IN_PROGRESS = '1' else MCU_SRAM_WR;
MASTER_ADDR <= DMA_ADDR when DMA_IN_PROGRESS = '1' else MCU_ADDR;
MASTER_DIN <= "00000000" & MCU_IO_DATA_READ when MCU_IO_RD = '1' else
SRAM_DOUT when MASTER_ADDR(15) = '0' else
"00000000" & AMBILIGHT_CFG_DOUT;
MASTER_DOUT <= "00000000" & DMA_DOUT when DMA_IN_PROGRESS = '1' else MCU_DOUT;
MCU_DIN <= MASTER_DIN;
DMA_DIN <= MASTER_DIN(7 downto 0);
AMBILIGHT_CFG_DIN <= MASTER_DOUT(7 downto 0);
AMBILIGHT_CFG_ADDR <= '0' & MASTER_ADDR(14 downto 0);
AMBILIGHT_CFG_WE <= MASTER_WE(0) and MASTER_ADDR(15);
SRAM_DIN <= MASTER_DOUT;
SRAM_WE <= MASTER_WE when MASTER_ADDR(15) = '0' else "00";
ADV_RST <= '1';
OUTPUT <= driverOutput;
ADV_SCL <= PORTD(7) when DDRD(7) = '1' else 'Z';
ADV_SDA <= PORTD(6) when DDRD(6) = '1' else 'Z';
GPIO(3) <= PORTD(3) when DDRD(3) = '1' else 'Z';
GPIO(2) <= PORTD(2) when DDRD(2) = '1' else 'Z';
GPIO(1) <= PORTD(1) when DDRD(1) = '1' else 'Z';
GPIO(0) <= PORTD(0) when DDRD(0) = '1' else 'Z';
PIND <= ADV_SCL & ADV_SDA & "00" & GPIO(3) & GPIO(2) & GPIO(1) & GPIO(0);
vidclk <= ADV_LLC;
end Behavioral;
| gpl-2.0 | 12b19ec0a8dafd7b4f7211cb9192cef7 | 0.556124 | 3.044791 | false | false | false | false |
Nooxet/embedded_bruteforce | brutus_system/hdl/system_push_buttons_4bits_wrapper.vhd | 1 | 5,051 | -------------------------------------------------------------------------------
-- system_push_buttons_4bits_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library axi_gpio_v1_01_b;
use axi_gpio_v1_01_b.all;
entity system_push_buttons_4bits_wrapper is
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(8 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(8 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
IP2INTC_Irpt : out std_logic;
GPIO_IO_I : in std_logic_vector(3 downto 0);
GPIO_IO_O : out std_logic_vector(3 downto 0);
GPIO_IO_T : out std_logic_vector(3 downto 0);
GPIO2_IO_I : in std_logic_vector(31 downto 0);
GPIO2_IO_O : out std_logic_vector(31 downto 0);
GPIO2_IO_T : out std_logic_vector(31 downto 0)
);
attribute x_core_info : STRING;
attribute x_core_info of system_push_buttons_4bits_wrapper : entity is "axi_gpio_v1_01_b";
end system_push_buttons_4bits_wrapper;
architecture STRUCTURE of system_push_buttons_4bits_wrapper is
component axi_gpio is
generic (
C_FAMILY : STRING;
C_INSTANCE : STRING;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : std_logic_vector(31 downto 0);
C_TRI_DEFAULT : std_logic_vector(31 downto 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : std_logic_vector(31 downto 0);
C_TRI_DEFAULT_2 : std_logic_vector(31 downto 0)
);
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(8 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_WSTRB : in std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(8 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
IP2INTC_Irpt : out std_logic;
GPIO_IO_I : in std_logic_vector((C_GPIO_WIDTH-1) downto 0);
GPIO_IO_O : out std_logic_vector((C_GPIO_WIDTH-1) downto 0);
GPIO_IO_T : out std_logic_vector((C_GPIO_WIDTH-1) downto 0);
GPIO2_IO_I : in std_logic_vector((C_GPIO2_WIDTH-1) downto 0);
GPIO2_IO_O : out std_logic_vector((C_GPIO2_WIDTH-1) downto 0);
GPIO2_IO_T : out std_logic_vector((C_GPIO2_WIDTH-1) downto 0)
);
end component;
begin
Push_Buttons_4Bits : axi_gpio
generic map (
C_FAMILY => "spartan6",
C_INSTANCE => "Push_Buttons_4Bits",
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 4,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 1,
C_ALL_INPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"ffffffff",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"ffffffff"
)
port map (
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
IP2INTC_Irpt => IP2INTC_Irpt,
GPIO_IO_I => GPIO_IO_I,
GPIO_IO_O => GPIO_IO_O,
GPIO_IO_T => GPIO_IO_T,
GPIO2_IO_I => GPIO2_IO_I,
GPIO2_IO_O => GPIO2_IO_O,
GPIO2_IO_T => GPIO2_IO_T
);
end architecture STRUCTURE;
| mit | b65e2f73a447ed232317ded39b90f823 | 0.588992 | 2.928116 | false | false | false | false |
kb3gtn/mojo_modulator | vhdl/src/uart.vhd | 3 | 22,059 | --------------------------------------------------------------------------
-- uart.vhd
-- Simple RS232 like uart tx/rx design
-- Does not handle any flow control.
-- Does not perform any meaning full buffering.
--
-- Peter Fetterer <[email protected]>
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity uart is
Port (
i_clk : in std_logic; -- system clock
i_srst : in std_logic; -- synchronious reset, 1 - active
i_baud_div : in std_logic_vector(15 downto 0); -- clk divider to get to baud rate
-- UART Interface
o_uart_tx : out std_logic; -- tx bit stream
i_uart_rx : in std_logic; -- uart rx bit stream input
-- FPGA Side
i_tx_send : in std_logic_vector(7 downto 0); -- data byte in
i_tx_send_we : in std_logic; -- write enable
o_tx_send_busy : out std_logic; -- tx is busy, writes are ignored.
o_rx_read : out std_logic_vector(7 downto 0); -- data byte out
o_rx_read_valid : out std_logic; -- read data valid this clock cycle
i_rx_read_rd : in std_logic -- read request, get next byte..
);
end entity uart;
architecture Behavioral of uart is
-- holding registers (buffer, 1 byte deep)
signal rx_byte_last : std_logic_vector( 7 downto 0 ); -- buffer byte next byte to receive
signal rx_byte_last_valid : std_logic; -- if rx_byte_complete is holding a valid byte
signal rx_byte_working : std_logic_vector( 7 downto 0 ); -- working space for symbols be received
signal tx_byte_next : std_logic_vector(7 downto 0 ); -- next byte to send
signal tx_byte_valid : std_logic; -- if tx_byte_next is holding a valid byte
signal tx_byte_working : std_logic_vector( 7 downto 0 ); -- working byte being transmitted
-- baud divider stuff
signal divider_count : unsigned( 15 downto 0); -- symbol period
signal divider_count_div2 : unsigned( 15 downto 0); -- 1/2 symbol period
signal rx_symbol_count : unsigned( 15 downto 0); -- rx clk count periods
signal rx_gen_state : integer;
signal tx_symbol_count : unsigned( 15 downto 0); -- tx clk count periods
signal tx_gen_state : integer;
signal tx_active : std_logic;
signal uart_tx : std_logic;
signal rx_start_det : std_logic; -- signals that we detected the rising edge of a start bit. (start symbol_ce)
signal rx_symbol_ce : std_logic; -- clock enable on rx symbol sample
signal rx_symbol_complete : std_logic; -- last bit being received this clock enable
signal rx_symbol_complete_d1 : std_logic; -- delayed 1 clock
signal tx_symbol_ce : std_logic; -- clock enable on tx symbol sample
--signal tx_complete : std_logic; -- finished sending working byte
signal uart_rx : std_logic;
signal uart_rx_d1 : std_logic; -- rx_uart delayed 1 ( edge detction )
begin
-- baud_div is the counts of i_clks per bit period at the baudrate
divider_count <= unsigned(i_baud_div);
divider_count_div2 <= '0' & divider_count( 15 downto 1 ); -- shift left by 1 (divide by 1)
o_uart_tx <= uart_tx; -- register for output..
o_tx_send_busy <= tx_byte_valid;
o_rx_read <= rx_byte_last;
o_rx_read_valid <= rx_byte_last_valid;
----------------------------------------------------------------------
-- Receive State Machines
-- Chain of affectors
-- rx_start_dectector -> rx_sample_timing_gen -> rx_byte_builder
--
-- with TTL serial interface following the RS232 timing format,
-- when there is no data, the line should idle as a '1'
-- The start of a byte transmission always starts with a start bit '0'
-- which last 1 bit period in length ( 1/baudrate )
--
-- The rx_start_detector detect's when a falling_edge occurs on rx_uart.
-- if the rx_sample_timing_gen is in state 0, it will start generating
-- the sampling clock enables when rx_start_det = '1'.
--
-- The rx_byte_builder receives the sample_ce sigals from the sample
-- timing generator and shifts in the value of the rx_uart line on
-- each clock enable building a byte.
--
-- Note that the rx_sample_timing_gen does not produces a sample_ce
-- for the start or stop bits.
--
-- In RS232 TTL levels, > 2.5v is a '0' and < 2.5v is a '1'.
-- serial data is transmited as LSB first.
--
-- ** Top Level interaction Note:
--
-- There is no real output buffering going on in this code.
-- if we finish receiving a incomming byte and the last working byte
-- has not been read yet, we will overwrite it transparently.
-- ( On overflow, ew drop the oldest data )
--
-- This shouldn't really be a big issue since the update rate is
-- very slow (500+ clock cycles) for each byte. It is assmed
-- that upper level components will read the byte as soon as
-- it is available and perform there own buffering if needed.
--------------------------------------------------------------------------
-- detect start bit
rx_start_detector : process( i_clk )
begin
if ( rising_edge( i_clk ) ) then
if ( i_srst = '1' ) then
uart_rx_d1 <= '1';
uart_rx <= i_uart_rx; -- flop to resync to clock domain.
else
uart_rx <= i_uart_rx;
uart_rx_d1 <= uart_rx; -- detect falling edge on uart_rx
if ( (uart_rx_d1 = '1') and ( uart_rx = '0' ) ) then
rx_start_det <= '1'; -- rising_edge detected
-- this will go high on other bits in the byte received, but the
-- receive state machine will be active and ignore these pulses.
else
rx_start_det <= '0'; -- no rising_edge detected
end if;
end if;
end if;
end process;
-- rx sample ce generator
rx_sample_timing_gen : process( i_clk )
begin
if ( rising_edge( i_clk ) ) then
if ( i_srst = '1' ) then
rx_symbol_ce <= '0';
rx_symbol_count <= (others=>'0');
rx_gen_state <= 0;
rx_symbol_complete <= '0';
else
case rx_gen_state is
when 0 =>
-- waiting for start detect
rx_symbol_ce <= '0';
rx_symbol_complete <= '0';
if ( rx_start_det = '1' ) then
rx_gen_state <= 1; -- rising_edge detected (ignored for reset of byte receive)
end if;
when 1 =>
-- need to wait 1/2 a symbol period
if ( rx_symbol_count = divider_count_div2 ) then
-- done!
rx_symbol_count <= (others=>'0'); -- reset bit period counter
rx_gen_state <= 2;
else
-- increment counter
rx_symbol_count <= rx_symbol_count + 1;
-- stay in this state.. until symbol count is reached
end if;
when 2 =>
-- half way into the start bit...
-- test to see if we still see the start bit (rx_uart = 0)
if ( uart_rx = '0' ) then
rx_gen_state <= 3;
else
rx_gen_state <= 0; -- fail, go back, look for falling edge again..
end if;
when 3 =>
-- need to wait 1 symbol period ad signal to sample bit0
if ( rx_symbol_count = divider_count ) then
rx_symbol_count <= (others=>'0');
rx_symbol_ce <= '1'; -- sample bit..
rx_gen_state <= 4;
else
rx_symbol_count <= rx_symbol_count + 1;
rx_symbol_ce <= '0';
end if;
when 4 =>
-- need to wait 1 symbol period and signal to sample bit1
if ( rx_symbol_count = divider_count ) then
-- sample bit
rx_symbol_count <= (others=>'0');
rx_symbol_ce <= '1'; -- sample bit..
rx_gen_state <= 5;
else
-- wait
rx_symbol_count <= rx_symbol_count + 1;
rx_symbol_ce <= '0';
end if;
when 5 =>
-- need to wait 1 symbol period and signal to sample bit2
if ( rx_symbol_count = divider_count ) then
rx_symbol_count <= (others=>'0');
rx_symbol_ce <= '1'; -- sample bit..
rx_gen_state <= 6;
else
rx_symbol_count <= rx_symbol_count + 1;
rx_symbol_ce <= '0';
end if;
when 6 =>
-- need to wait 1 symbol period and signal to sample bit3
if ( rx_symbol_count = divider_count ) then
rx_symbol_count <= (others=>'0');
rx_symbol_ce <= '1'; -- sample bit..
rx_gen_state <= 7;
else
rx_symbol_count <= rx_symbol_count + 1;
rx_symbol_ce <= '0';
end if;
when 7 =>
-- need to wait 1 symbol period and signal to sample bit4
if ( rx_symbol_count = divider_count ) then
rx_symbol_count <= (others=>'0');
rx_symbol_ce <= '1'; -- sample bit..
rx_gen_state <= 8;
else
rx_symbol_count <= rx_symbol_count + 1;
rx_symbol_ce <= '0';
end if;
when 8 =>
-- need to wait 1 symbol period and signal to sample bit5
if ( rx_symbol_count = divider_count ) then
rx_symbol_count <= (others=>'0');
rx_symbol_ce <= '1'; -- sample bit..
rx_gen_state <= 9;
else
rx_symbol_count <= rx_symbol_count + 1;
rx_symbol_ce <= '0';
end if;
when 9 =>
-- need to wait 1 symbol period and signal to sample bit6
if ( rx_symbol_count = divider_count ) then
rx_symbol_count <= (others=>'0');
rx_symbol_ce <= '1'; -- sample bit..
rx_gen_state <= 10;
else
rx_symbol_count <= rx_symbol_count + 1;
rx_symbol_ce <= '0';
end if;
when 10 =>
-- need to wait 1 symbol period and signal to sample bit7
if ( rx_symbol_count = divider_count ) then
rx_symbol_count <= (others=>'0');
rx_symbol_ce <= '1'; -- sample bit..
rx_gen_state <= 11;
else
rx_symbol_count <= rx_symbol_count + 1;
rx_symbol_ce <= '0';
end if;
when 11 =>
-- wait for stop bit, before resetting
-- this stops a stuck '1' line from spitting out a bunch of 0xff's
-- wait until the line goes idle..
if ( rx_symbol_count = divider_count ) then
rx_symbol_count <= (others=>'0');
rx_symbol_ce <= '0';
if ( uart_rx = '1' ) then
rx_symbol_complete <= '1';
rx_gen_state <= 0; -- ready for next byte
end if;
else
rx_symbol_count <= rx_symbol_count + 1;
rx_symbol_ce <= '0';
end if;
when others =>
rx_gen_state <= 0; -- should never happen, reset if it does.
end case;
end if;
end if;
end process;
rx_sym_delay1 : process( i_clk )
begin
if ( rising_edge(i_clk) ) then
-- delay 1 clock cycle
rx_symbol_complete_d1 <= rx_symbol_complete;
end if;
end process;
rx_byte_builder : process ( i_clk )
begin
if ( rising_edge( i_clk ) ) then
if ( i_srst = '1' ) then
-- reset
rx_byte_working <= (others=>'0');
rx_byte_last_valid <= '0';
rx_byte_last <= (others=>'0');
else
if (rx_symbol_ce = '1' ) then
-- shift in new input symbol
rx_byte_working <= uart_rx & rx_byte_working(7 downto 1);
end if;
-- complete_d1 will be 1 clock cycle after rx_symbol_ce for bit 7
if ( rx_symbol_complete_d1 = '1' ) then
-- byte complete
rx_byte_last <= rx_byte_working;
rx_byte_last_valid <= '1';
end if;
-- handle rx_byte_last reads
if ( rx_byte_last_valid = '1' ) then
if ( i_rx_read_rd = '1' ) then
rx_byte_last_valid <= '0'; -- reset valid flag for next byte.
end if;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------------
-- ** Transmit State Machine
-- * Chain of affectors
-- tx_timing_generator -> tx_state_machine -> tx_shift_register
-- tx_handler ----^
--
-- The tx_timing_generate just takes the i_clk signal and divides down
-- to get the serial bit timing. This is feed to the tx_state_machine
-- to control what bit is being transmitted.
--
-- tx_state_machine checks to see if tx_byte_valid is a 1.
-- This will cause the state machine to load the tx_shift_register
-- with the new byte and to shift it own with a start bit prepended.
--
-- The tx_handler is reponsible for handling input from a higher level (UI)
--
-------------------------------------------------------------------------
-- generater tx bit period clock enable signal tx_symbol_ce
-- (clock divider)
tx_timing_generator : process( i_clk )
begin
if ( rising_edge( i_clk )) then
if ( i_srst = '1' ) then
tx_symbol_count <= (others=>'0');
else
if ( tx_symbol_count = divider_count ) then
tx_symbol_ce <= '1';
tx_symbol_count <= (others=>'0');
else
tx_symbol_ce <= '0';
tx_symbol_count <= tx_symbol_count + 1;
end if;
end if;
end if;
end process;
-- transmit state machine
tx_state_machine : process( i_clk )
begin
if ( rising_edge( i_clk) ) then
if ( i_srst = '1' ) then
tx_gen_state <= 0;
tx_active <= '0';
uart_tx <= '1'; -- idle state
--tx_complete <= '0';
else
case tx_gen_state is
when 0 =>
-- waiting for a tx byte to be ready to send
--tx_complete <= '0';
if ( tx_byte_valid = '1' ) then
-- got a byte to send, progress though states
tx_gen_state <= 1;
tx_byte_working <= tx_byte_next;
tx_active <= '1'; -- signal to tx_handler we have latched in the next byte and are going to start sending it.
else
tx_gen_state <= 0;
tx_active <= '0';
uart_tx <= '1'; -- idle
end if;
when 1 =>
-- wait for a clock enable
if ( tx_symbol_ce = '1' ) then
-- send start bit
uart_tx <= '0';
tx_gen_state <= 2;
else
-- wait for clk enable
tx_gen_state <= 1;
end if;
when 2 =>
-- wait for clock enable then send bit 0
if ( tx_symbol_ce = '1' ) then
-- send bit 1
uart_tx <= tx_byte_working(0);
tx_gen_state <= 3;
else
tx_gen_state <= 2;
end if;
when 3 =>
-- wait for clock enable then send bit 1
if ( tx_symbol_ce = '1' ) then
uart_tx <= tx_byte_working(1);
tx_gen_state <= 4;
else
tx_gen_state <= 3;
end if;
when 4 =>
-- wait for clock enable send bit 2
if ( tx_symbol_ce = '1' ) then
uart_tx <= tx_byte_working(2);
tx_gen_state <= 5;
else
tx_gen_state <= 4;
end if;
when 5 =>
-- wait for clock enable send bit 3
if ( tx_symbol_ce = '1' ) then
uart_tx <= tx_byte_working(3);
tx_gen_state <= 6;
else
tx_gen_state <= 5;
end if;
when 6 =>
-- wait for clock enable send bit 4
if ( tx_symbol_ce = '1' ) then
uart_tx <= tx_byte_working(4);
tx_gen_state <= 7;
else
tx_gen_state <= 6;
end if;
when 7 =>
-- wait for clock enable send bit 5
if ( tx_symbol_ce = '1' ) then
uart_tx <= tx_byte_working(5);
tx_gen_state <= 8;
else
tx_gen_state <= 7;
end if;
when 8 =>
-- wait for clock enable send bit 6
if ( tx_symbol_ce = '1' ) then
uart_tx <= tx_byte_working(6);
tx_gen_state <= 9;
else
tx_gen_state <= 8;
end if;
when 9 =>
-- wait for clock eanble, send bit 7
if ( tx_symbol_ce = '1' ) then
uart_tx <= tx_byte_working(7);
tx_gen_state <= 10;
else
tx_gen_state <= 9;
end if;
when 10 =>
-- send stop bit on next clock enable
if ( tx_symbol_ce = '1' ) then
uart_tx <= '1';
tx_gen_state <= 11;
else
tx_gen_state <= 10;
end if;
when 11 =>
-- signal complete with transmit
-- finish stop bit period
if ( tx_symbol_ce = '1' ) then
tx_gen_state <= 0;
--tx_complete <= '1';
end if;
when others =>
tx_gen_state <= 0; -- should never get here..
end case;
end if;
end if;
end process;
-- tx input byte buffer handler
-- handle UI to working_byte transfersin
tx_handler : process( i_clk )
begin
if ( rising_edge( i_clk ) ) then
if ( i_srst = '1' ) then
tx_byte_valid <= '0';
else
-- handle new bytes comming in to transmit
if ( i_tx_send_we = '1' ) then
if ( tx_byte_valid = '0' ) then
-- we can accept a new byte in.
tx_byte_next <= i_tx_send;
tx_byte_valid <= '1'; -- signal to tx state machine there is data ready to send
-- note: o_tx_send_busy <= tx_byte_valid
end if;
end if;
-- clear event to load new incomming bytes.
if ( tx_byte_valid = '1' ) then
if ( tx_active = '1' ) then
-- tx state machine sucked in the byte_next
tx_byte_valid <= '0'; -- next byte no longer valid, can accept a new data byte to go next.
end if;
end if;
end if;
end if;
end process;
end architecture Behavioral;
| apache-2.0 | 50d4c6bf0b85ac2ff645b74a7bdf2694 | 0.424861 | 4.585117 | false | false | false | false |
Nooxet/embedded_bruteforce | brutus_system/hdl/system_microblaze_0_d_bram_ctrl_wrapper.vhd | 1 | 18,546 | -------------------------------------------------------------------------------
-- system_microblaze_0_d_bram_ctrl_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_bram_if_cntlr_v3_10_a;
use lmb_bram_if_cntlr_v3_10_a.all;
entity system_microblaze_0_d_bram_ctrl_wrapper is
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to 31);
LMB_WriteDBus : in std_logic_vector(0 to 31);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to 3);
Sl_DBus : out std_logic_vector(0 to 31);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
LMB1_ABus : in std_logic_vector(0 to 31);
LMB1_WriteDBus : in std_logic_vector(0 to 31);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to 3);
Sl1_DBus : out std_logic_vector(0 to 31);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
LMB2_ABus : in std_logic_vector(0 to 31);
LMB2_WriteDBus : in std_logic_vector(0 to 31);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to 3);
Sl2_DBus : out std_logic_vector(0 to 31);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
LMB3_ABus : in std_logic_vector(0 to 31);
LMB3_WriteDBus : in std_logic_vector(0 to 31);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to 3);
Sl3_DBus : out std_logic_vector(0 to 31);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to 3);
BRAM_Addr_A : out std_logic_vector(0 to 31);
BRAM_Din_A : in std_logic_vector(0 to 31);
BRAM_Dout_A : out std_logic_vector(0 to 31);
Interrupt : out std_logic;
UE : out std_logic;
CE : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to 0);
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to 31);
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to 31);
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to 0);
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to 0);
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of system_microblaze_0_d_bram_ctrl_wrapper : entity is "lmb_bram_if_cntlr_v3_10_a";
end system_microblaze_0_d_bram_ctrl_wrapper;
architecture STRUCTURE of system_microblaze_0_d_bram_ctrl_wrapper is
component lmb_bram_if_cntlr is
generic (
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_FAMILY : string;
C_MASK : std_logic_vector(0 to 31);
C_MASK1 : std_logic_vector(0 to 31);
C_MASK2 : std_logic_vector(0 to 31);
C_MASK3 : std_logic_vector(0 to 31);
C_LMB_AWIDTH : integer;
C_LMB_DWIDTH : integer;
C_ECC : integer;
C_INTERCONNECT : integer;
C_FAULT_INJECT : integer;
C_CE_FAILING_REGISTERS : integer;
C_UE_FAILING_REGISTERS : integer;
C_ECC_STATUS_REGISTERS : integer;
C_ECC_ONOFF_REGISTER : integer;
C_ECC_ONOFF_RESET_VALUE : integer;
C_CE_COUNTER_WIDTH : integer;
C_WRITE_ACCESS : integer;
C_NUM_LMB : integer;
C_SPLB_CTRL_BASEADDR : std_logic_vector;
C_SPLB_CTRL_HIGHADDR : std_logic_vector;
C_SPLB_CTRL_AWIDTH : INTEGER;
C_SPLB_CTRL_DWIDTH : INTEGER;
C_SPLB_CTRL_P2P : INTEGER;
C_SPLB_CTRL_MID_WIDTH : INTEGER;
C_SPLB_CTRL_NUM_MASTERS : INTEGER;
C_SPLB_CTRL_SUPPORT_BURSTS : INTEGER;
C_SPLB_CTRL_NATIVE_DWIDTH : INTEGER;
C_S_AXI_CTRL_BASEADDR : std_logic_vector(31 downto 0);
C_S_AXI_CTRL_HIGHADDR : std_logic_vector(31 downto 0);
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER
);
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to ((C_LMB_DWIDTH+8*C_ECC)/8)-1);
BRAM_Addr_A : out std_logic_vector(0 to C_LMB_AWIDTH-1);
BRAM_Din_A : in std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC);
BRAM_Dout_A : out std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC);
Interrupt : out std_logic;
UE : out std_logic;
CE : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to (C_SPLB_CTRL_MID_WIDTH-1));
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to ((C_SPLB_CTRL_DWIDTH/8)-1));
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1));
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1));
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(((C_S_AXI_CTRL_DATA_WIDTH/8)-1) downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
end component;
begin
microblaze_0_d_bram_ctrl : lmb_bram_if_cntlr
generic map (
C_BASEADDR => X"00000000",
C_HIGHADDR => X"00007fff",
C_FAMILY => "spartan6",
C_MASK => X"40000000",
C_MASK1 => X"00800000",
C_MASK2 => X"00800000",
C_MASK3 => X"00800000",
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32,
C_ECC => 0,
C_INTERCONNECT => 0,
C_FAULT_INJECT => 0,
C_CE_FAILING_REGISTERS => 0,
C_UE_FAILING_REGISTERS => 0,
C_ECC_STATUS_REGISTERS => 0,
C_ECC_ONOFF_REGISTER => 0,
C_ECC_ONOFF_RESET_VALUE => 1,
C_CE_COUNTER_WIDTH => 0,
C_WRITE_ACCESS => 2,
C_NUM_LMB => 1,
C_SPLB_CTRL_BASEADDR => X"FFFFFFFF",
C_SPLB_CTRL_HIGHADDR => X"00000000",
C_SPLB_CTRL_AWIDTH => 32,
C_SPLB_CTRL_DWIDTH => 32,
C_SPLB_CTRL_P2P => 0,
C_SPLB_CTRL_MID_WIDTH => 1,
C_SPLB_CTRL_NUM_MASTERS => 1,
C_SPLB_CTRL_SUPPORT_BURSTS => 0,
C_SPLB_CTRL_NATIVE_DWIDTH => 32,
C_S_AXI_CTRL_BASEADDR => X"FFFFFFFF",
C_S_AXI_CTRL_HIGHADDR => X"00000000",
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32
)
port map (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB_ABus => LMB_ABus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_BE => LMB_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB1_ABus => LMB1_ABus,
LMB1_WriteDBus => LMB1_WriteDBus,
LMB1_AddrStrobe => LMB1_AddrStrobe,
LMB1_ReadStrobe => LMB1_ReadStrobe,
LMB1_WriteStrobe => LMB1_WriteStrobe,
LMB1_BE => LMB1_BE,
Sl1_DBus => Sl1_DBus,
Sl1_Ready => Sl1_Ready,
Sl1_Wait => Sl1_Wait,
Sl1_UE => Sl1_UE,
Sl1_CE => Sl1_CE,
LMB2_ABus => LMB2_ABus,
LMB2_WriteDBus => LMB2_WriteDBus,
LMB2_AddrStrobe => LMB2_AddrStrobe,
LMB2_ReadStrobe => LMB2_ReadStrobe,
LMB2_WriteStrobe => LMB2_WriteStrobe,
LMB2_BE => LMB2_BE,
Sl2_DBus => Sl2_DBus,
Sl2_Ready => Sl2_Ready,
Sl2_Wait => Sl2_Wait,
Sl2_UE => Sl2_UE,
Sl2_CE => Sl2_CE,
LMB3_ABus => LMB3_ABus,
LMB3_WriteDBus => LMB3_WriteDBus,
LMB3_AddrStrobe => LMB3_AddrStrobe,
LMB3_ReadStrobe => LMB3_ReadStrobe,
LMB3_WriteStrobe => LMB3_WriteStrobe,
LMB3_BE => LMB3_BE,
Sl3_DBus => Sl3_DBus,
Sl3_Ready => Sl3_Ready,
Sl3_Wait => Sl3_Wait,
Sl3_UE => Sl3_UE,
Sl3_CE => Sl3_CE,
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_Din_A => BRAM_Din_A,
BRAM_Dout_A => BRAM_Dout_A,
Interrupt => Interrupt,
UE => UE,
CE => CE,
SPLB_CTRL_PLB_ABus => SPLB_CTRL_PLB_ABus,
SPLB_CTRL_PLB_PAValid => SPLB_CTRL_PLB_PAValid,
SPLB_CTRL_PLB_masterID => SPLB_CTRL_PLB_masterID,
SPLB_CTRL_PLB_RNW => SPLB_CTRL_PLB_RNW,
SPLB_CTRL_PLB_BE => SPLB_CTRL_PLB_BE,
SPLB_CTRL_PLB_size => SPLB_CTRL_PLB_size,
SPLB_CTRL_PLB_type => SPLB_CTRL_PLB_type,
SPLB_CTRL_PLB_wrDBus => SPLB_CTRL_PLB_wrDBus,
SPLB_CTRL_Sl_addrAck => SPLB_CTRL_Sl_addrAck,
SPLB_CTRL_Sl_SSize => SPLB_CTRL_Sl_SSize,
SPLB_CTRL_Sl_wait => SPLB_CTRL_Sl_wait,
SPLB_CTRL_Sl_rearbitrate => SPLB_CTRL_Sl_rearbitrate,
SPLB_CTRL_Sl_wrDAck => SPLB_CTRL_Sl_wrDAck,
SPLB_CTRL_Sl_wrComp => SPLB_CTRL_Sl_wrComp,
SPLB_CTRL_Sl_rdDBus => SPLB_CTRL_Sl_rdDBus,
SPLB_CTRL_Sl_rdDAck => SPLB_CTRL_Sl_rdDAck,
SPLB_CTRL_Sl_rdComp => SPLB_CTRL_Sl_rdComp,
SPLB_CTRL_Sl_MBusy => SPLB_CTRL_Sl_MBusy,
SPLB_CTRL_Sl_MWrErr => SPLB_CTRL_Sl_MWrErr,
SPLB_CTRL_Sl_MRdErr => SPLB_CTRL_Sl_MRdErr,
SPLB_CTRL_PLB_UABus => SPLB_CTRL_PLB_UABus,
SPLB_CTRL_PLB_SAValid => SPLB_CTRL_PLB_SAValid,
SPLB_CTRL_PLB_rdPrim => SPLB_CTRL_PLB_rdPrim,
SPLB_CTRL_PLB_wrPrim => SPLB_CTRL_PLB_wrPrim,
SPLB_CTRL_PLB_abort => SPLB_CTRL_PLB_abort,
SPLB_CTRL_PLB_busLock => SPLB_CTRL_PLB_busLock,
SPLB_CTRL_PLB_MSize => SPLB_CTRL_PLB_MSize,
SPLB_CTRL_PLB_lockErr => SPLB_CTRL_PLB_lockErr,
SPLB_CTRL_PLB_wrBurst => SPLB_CTRL_PLB_wrBurst,
SPLB_CTRL_PLB_rdBurst => SPLB_CTRL_PLB_rdBurst,
SPLB_CTRL_PLB_wrPendReq => SPLB_CTRL_PLB_wrPendReq,
SPLB_CTRL_PLB_rdPendReq => SPLB_CTRL_PLB_rdPendReq,
SPLB_CTRL_PLB_wrPendPri => SPLB_CTRL_PLB_wrPendPri,
SPLB_CTRL_PLB_rdPendPri => SPLB_CTRL_PLB_rdPendPri,
SPLB_CTRL_PLB_reqPri => SPLB_CTRL_PLB_reqPri,
SPLB_CTRL_PLB_TAttribute => SPLB_CTRL_PLB_TAttribute,
SPLB_CTRL_Sl_wrBTerm => SPLB_CTRL_Sl_wrBTerm,
SPLB_CTRL_Sl_rdWdAddr => SPLB_CTRL_Sl_rdWdAddr,
SPLB_CTRL_Sl_rdBTerm => SPLB_CTRL_Sl_rdBTerm,
SPLB_CTRL_Sl_MIRQ => SPLB_CTRL_Sl_MIRQ,
S_AXI_CTRL_ACLK => S_AXI_CTRL_ACLK,
S_AXI_CTRL_ARESETN => S_AXI_CTRL_ARESETN,
S_AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR,
S_AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID,
S_AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY,
S_AXI_CTRL_WDATA => S_AXI_CTRL_WDATA,
S_AXI_CTRL_WSTRB => S_AXI_CTRL_WSTRB,
S_AXI_CTRL_WVALID => S_AXI_CTRL_WVALID,
S_AXI_CTRL_WREADY => S_AXI_CTRL_WREADY,
S_AXI_CTRL_BRESP => S_AXI_CTRL_BRESP,
S_AXI_CTRL_BVALID => S_AXI_CTRL_BVALID,
S_AXI_CTRL_BREADY => S_AXI_CTRL_BREADY,
S_AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR,
S_AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID,
S_AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY,
S_AXI_CTRL_RDATA => S_AXI_CTRL_RDATA,
S_AXI_CTRL_RRESP => S_AXI_CTRL_RRESP,
S_AXI_CTRL_RVALID => S_AXI_CTRL_RVALID,
S_AXI_CTRL_RREADY => S_AXI_CTRL_RREADY
);
end architecture STRUCTURE;
| mit | c48f7b7139a084eb6ea2039c2ad16d27 | 0.616575 | 2.929395 | false | false | false | false |
freecores/gpib_controller | vhdl/test/gpib_TE_LE_Test.vhd | 1 | 14,006 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Author: Andrzej Paluch
--
-- Create Date: 23:21:05 10/21/2011
-- Design Name:
-- Module Name: /windows/h/projekty/elektronika/USB_to_HPIB/usbToHpib/test_scr//gpibInterfaceTest.vhd
-- Project Name: usbToHpib
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: gpibInterface
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use work.gpibComponents.all;
use work.helperComponents.all;
ENTITY gpib_TE_LE_Test IS
END gpib_TE_LE_Test;
ARCHITECTURE behavior OF gpib_TE_LE_Test IS
-- Component Declaration for the Unit Under Test (UUT)
component gpibCableEmulator is port (
-- interface signals
DIO_1 : in std_logic_vector (7 downto 0);
output_valid_1 : in std_logic;
DIO_2 : in std_logic_vector (7 downto 0);
output_valid_2 : in std_logic;
DIO : out std_logic_vector (7 downto 0);
-- attention
ATN_1 : in std_logic;
ATN_2 : in std_logic;
ATN : out std_logic;
-- data valid
DAV_1 : in std_logic;
DAV_2 : in std_logic;
DAV : out std_logic;
-- not ready for data
NRFD_1 : in std_logic;
NRFD_2 : in std_logic;
NRFD : out std_logic;
-- no data accepted
NDAC_1 : in std_logic;
NDAC_2 : in std_logic;
NDAC : out std_logic;
-- end or identify
EOI_1 : in std_logic;
EOI_2 : in std_logic;
EOI : out std_logic;
-- service request
SRQ_1 : in std_logic;
SRQ_2 : in std_logic;
SRQ : out std_logic;
-- interface clear
IFC_1 : in std_logic;
IFC_2 : in std_logic;
IFC : out std_logic;
-- remote enable
REN_1 : in std_logic;
REN_2 : in std_logic;
REN : out std_logic
);
end component;
-- inputs common
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal T1 : std_logic_vector(7 downto 0) := "00000100";
-- inputs 1
signal data_1 : std_logic_vector(7 downto 0) := (others => '0');
signal status_byte_1 : std_logic_vector(7 downto 0) := (others => '0');
signal rdy_1 : std_logic := '0';
signal nba_1 : std_logic := '0';
signal ltn_1 : std_logic := '0';
signal lun_1 : std_logic := '0';
signal lon_1 : std_logic := '0';
signal ton_1 : std_logic := '0';
signal endOf_1 : std_logic := '0';
signal gts_1 : std_logic := '0';
signal rpp_1 : std_logic := '0';
signal tcs_1 : std_logic := '0';
signal tca_1 : std_logic := '0';
signal sic_1 : std_logic := '0';
signal rsc_1 : std_logic := '0';
signal sre_1 : std_logic := '0';
signal rtl_1 : std_logic := '0';
signal rsv_1 : std_logic := '0';
signal ist_1 : std_logic := '0';
signal lpe_1 : std_logic := '0';
-- inputs 2
signal data_2 : std_logic_vector(7 downto 0) := (others => '0');
signal status_byte_2 : std_logic_vector(7 downto 0) := (others => '0');
signal rdy_2 : std_logic := '0';
signal nba_2 : std_logic := '0';
signal ltn_2 : std_logic := '0';
signal lun_2 : std_logic := '0';
signal lon_2 : std_logic := '0';
signal ton_2 : std_logic := '0';
signal endOf_2 : std_logic := '0';
signal gts_2 : std_logic := '0';
signal rpp_2 : std_logic := '0';
signal tcs_2 : std_logic := '0';
signal tca_2 : std_logic := '0';
signal sic_2 : std_logic := '0';
signal rsc_2 : std_logic := '0';
signal sre_2 : std_logic := '0';
signal rtl_2 : std_logic := '0';
signal rsv_2 : std_logic := '0';
signal ist_2 : std_logic := '0';
signal lpe_2 : std_logic := '0';
-- outputs 1
signal dvd_1 : std_logic;
signal wnc_1 : std_logic;
signal tac_1 : std_logic;
signal lac_1 : std_logic;
signal cwrc_1 : std_logic;
signal cwrd_1 : std_logic;
signal clr_1 : std_logic;
signal trg_1 : std_logic;
signal atl_1 : std_logic;
signal att_1 : std_logic;
signal mla_1 : std_logic;
signal lsb_1 : std_logic;
signal spa_1 : std_logic;
signal ppr_1 : std_logic;
signal sreq_1 : std_logic;
signal isLocal_1 : std_logic;
signal currentSecAddr_1 : std_logic_vector (4 downto 0);
-- outputs 2
signal dvd_2 : std_logic;
signal wnc_2 : std_logic;
signal tac_2 : std_logic;
signal lac_2 : std_logic;
signal cwrc_2 : std_logic;
signal cwrd_2 : std_logic;
signal clr_2 : std_logic;
signal trg_2 : std_logic;
signal atl_2 : std_logic;
signal att_2 : std_logic;
signal mla_2 : std_logic;
signal lsb_2 : std_logic;
signal spa_2 : std_logic;
signal ppr_2 : std_logic;
signal sreq_2 : std_logic;
signal isLocal_2 : std_logic;
signal currentSecAddr_2 : std_logic_vector (4 downto 0);
-- common
signal DO : std_logic_vector (7 downto 0);
signal DI_1 : std_logic_vector (7 downto 0);
signal output_valid_1 : std_logic;
signal DI_2 : std_logic_vector (7 downto 0);
signal output_valid_2 : std_logic;
signal ATN_1, ATN_2, ATN : std_logic;
signal DAV_1, DAV_2, DAV : std_logic;
signal NRFD_1, NRFD_2, NRFD : std_logic;
signal NDAC_1, NDAC_2, NDAC : std_logic;
signal EOI_1, EOI_2, EOI : std_logic;
signal SRQ_1, SRQ_2, SRQ : std_logic;
signal IFC_1, IFC_2, IFC : std_logic;
signal REN_1, REN_2, REN : std_logic;
-- gpib reader
signal buf_interrupt : std_logic;
signal data_available : std_logic;
signal last_byte_addr : std_logic_vector (3 downto 0);
signal end_of_stream : std_logic;
signal byte_addr : std_logic_vector (3 downto 0);
signal data_out : std_logic_vector (7 downto 0);
signal reset_buffer : std_logic := '0';
signal dataSecAddr : std_logic_vector (4 downto 0);
-- gpib writer
signal w_last_byte_addr : std_logic_vector (3 downto 0)
:= (others => '0');
signal w_end_of_stream : std_logic := '0';
signal w_data_available : std_logic := '0';
signal w_buf_interrupt : std_logic;
signal w_data_in : std_logic_vector (7 downto 0);
signal w_byte_addr : std_logic_vector (3 downto 0);
signal w_reset_buffer : std_logic := '0';
signal w_dataSecAddr : std_logic_vector (4 downto 0);
type WR_BUF_TYPE is
array (0 to 15) of std_logic_vector (7 downto 0);
signal w_write_buffer : WR_BUF_TYPE;
-- Clock period definitions
constant clk_period : time := 2ps;
BEGIN
-- Instantiate the Unit Under Test (UUT)
gpib1: gpibInterface PORT MAP (
clk => clk,
reset => reset,
isLE => '1',
isTE => '1',
lpeUsed => '0',
fixedPpLine => "000",
eosUsed => '0',
eosMark => "00000000",
myListAddr => "00001",
myTalkAddr => "00001",
secAddrMask => "00000000000000000000000000000110",
data => data_1,
status_byte => status_byte_1,
T1 => T1,
rdy => rdy_1,
nba => nba_1,
ltn => ltn_1,
lun => lun_1,
lon => lon_1,
ton => ton_1,
endOf => endOf_1,
gts => gts_1,
rpp => rpp_1,
tcs => tcs_1,
tca => tca_1,
sic => sic_1,
rsc => rsc_1,
sre => sre_1,
rtl => rtl_1,
rsv => rsv_1,
ist => ist_1,
lpe => lpe_1,
dvd => dvd_1,
wnc => wnc_1,
tac => tac_1,
lac => lac_1,
cwrc => cwrc_1,
cwrd => cwrd_1,
clr => clr_1,
trg => trg_1,
atl => atl_1,
att => att_1,
mla => mla_1,
lsb => lsb_1,
spa => spa_1,
ppr => ppr_1,
sreq => sreq_1,
isLocal => isLocal_1,
currentSecAddr => currentSecAddr_1,
DI => DO,
DO => DI_1,
output_valid => output_valid_1,
ATN_in => ATN,
ATN_out => ATN_1,
DAV_in => DAV,
DAV_out => DAV_1,
NRFD_in => NRFD,
NRFD_out => NRFD_1,
NDAC_in => NDAC,
NDAC_out => NDAC_1,
EOI_in => EOI,
EOI_out => EOI_1,
SRQ_in => SRQ,
SRQ_out => SRQ_1,
IFC_in => IFC,
IFC_out => IFC_1,
REN_in => REN,
REN_out => REN_1
);
-- Instantiate the Unit Under Test (UUT)
gpib2: gpibInterface PORT MAP (
clk => clk,
reset => reset,
isLE => '1',
isTE => '1',
lpeUsed => '0',
fixedPpLine => "000",
eosUsed => '0',
eosMark => "00000000",
myListAddr => "00010",
myTalkAddr => "00010",
secAddrMask => "00000000000000000000000000000110",
data => data_2,
status_byte => status_byte_2,
T1 => T1,
rdy => rdy_2,
nba => nba_2,
ltn => ltn_2,
lun => lun_2,
lon => lon_2,
ton => ton_2,
endOf => endOf_2,
gts => gts_2,
rpp => rpp_2,
tcs => tcs_2,
tca => tca_2,
sic => sic_2,
rsc => rsc_2,
sre => sre_2,
rtl => rtl_2,
rsv => rsv_2,
ist => ist_2,
lpe => lpe_2,
dvd => dvd_2,
wnc => wnc_2,
tac => tac_2,
lac => lac_2,
cwrc => cwrc_2,
cwrd => cwrd_2,
clr => clr_2,
trg => trg_2,
atl => atl_2,
att => att_2,
mla => mla_2,
lsb => lsb_2,
spa => spa_2,
ppr => ppr_2,
sreq => sreq_2,
isLocal => isLocal_2,
currentSecAddr => currentSecAddr_2,
DI => DO,
DO => DI_2,
output_valid => output_valid_2,
ATN_in => ATN,
ATN_out => ATN_2,
DAV_in => DAV,
DAV_out => DAV_2,
NRFD_in => NRFD,
NRFD_out => NRFD_2,
NDAC_in => NDAC,
NDAC_out => NDAC_2,
EOI_in => EOI,
EOI_out => EOI_2,
SRQ_in => SRQ,
SRQ_out => SRQ_2,
IFC_in => IFC,
IFC_out => IFC_2,
REN_in => REN,
REN_out => REN_2
);
ce: gpibCableEmulator port map (
-- interface signals
DIO_1 => DI_1,
output_valid_1 => output_valid_1,
DIO_2 => DI_2,
output_valid_2 => output_valid_2,
DIO => DO,
-- attention
ATN_1 => ATN_1, ATN_2 => ATN_2, ATN => ATN,
DAV_1 => DAV_1, DAV_2 => DAV_2, DAV => DAV,
NRFD_1 => NRFD_1, NRFD_2 => NRFD_2, NRFD => NRFD,
NDAC_1 => NDAC_1, NDAC_2 => NDAC_2, NDAC => NDAC,
EOI_1 => EOI_1, EOI_2 => EOI_2, EOI => EOI,
SRQ_1 => SRQ_1, SRQ_2 => SRQ_2, SRQ => SRQ,
IFC_1 => IFC_1, IFC_2 => IFC_2, IFC => IFC,
REN_1 => REN_1, REN_2 => REN_2, REN => REN
);
gr: gpibReader generic map (ADDR_WIDTH => 4) port map (
clk => clk, reset => reset,
------------------------------------------------------------------------
------ GPIB interface --------------------------------------------------
------------------------------------------------------------------------
data_in => DO, dvd => dvd_2, lac => lac_2, lsb => lsb_2, rdy => rdy_2,
------------------------------------------------------------------------
------ external interface ----------------------------------------------
------------------------------------------------------------------------
isLE => '1', secAddr => currentSecAddr_1, dataSecAddr => dataSecAddr,
buf_interrupt => buf_interrupt, data_available => data_available,
last_byte_addr => last_byte_addr, end_of_stream => end_of_stream,
byte_addr => byte_addr, data_out => data_out,
reset_buffer => reset_buffer
);
w_data_in <= w_write_buffer(conv_integer(w_byte_addr));
gw: gpibWriter generic map (ADDR_WIDTH => 4) port map (
clk => clk, reset => reset,
------------------------------------------------------------------------
------ GPIB interface --------------------------------------------------
------------------------------------------------------------------------
data_out => data_1, wnc => wnc_1, spa => spa_1, nba => nba_1,
endOf => endOf_1, tac => tac_1, cwrc => cwrc_1,
------------------------------------------------------------------------
------ external interface ----------------------------------------------
------------------------------------------------------------------------
isTE => '1', secAddr => currentSecAddr_1, dataSecAddr => w_dataSecAddr,
last_byte_addr => w_last_byte_addr, end_of_stream => w_end_of_stream,
data_available => w_data_available, buf_interrupt => w_buf_interrupt,
data_in => w_data_in, byte_addr => w_byte_addr,
reset_buffer => w_reset_buffer
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 10 clock periods.
reset <= '1';
wait for clk_period*10;
reset <= '0';
wait for clk_period*10;
-- requests system control
rsc_1 <= '1';
-- interface clear
sic_1 <= '1';
wait until IFC_1 = '1';
sic_1 <= '0';
wait until IFC_1 = '0';
-- gpib2 to listen
w_write_buffer(0) <= "00100010";
w_write_buffer(1) <= "01100010";
-- gpib1 to talk
w_write_buffer(2) <= "01000001";
w_write_buffer(3) <= "01100010";
w_last_byte_addr <= "0011";
w_data_available <= '1';
wait until w_buf_interrupt='1';
gts_1 <= '1';
wait until ATN='0';
w_reset_buffer <= '1';
wait for clk_period*2;
w_reset_buffer <= '0';
w_dataSecAddr <= "00010";
wait for clk_period*1;
w_write_buffer(0) <= "10101010";
w_write_buffer(1) <= "01010101";
w_write_buffer(2) <= "11111111";
w_last_byte_addr <= "0010";
w_end_of_stream <= '1';
w_data_available <= '1';
wait until buf_interrupt='1';
byte_addr <= "0000";
wait for clk_period*1;
assert data_out = "10101010";
byte_addr <= "0001";
wait for clk_period*1;
assert data_out = "01010101";
byte_addr <= "0010";
wait for clk_period*1;
assert data_out = "11111111";
report "$$$ END OF TEST - TE / LE $$$";
wait;
end process;
END;
| gpl-3.0 | e365d6b20a6dba7eeab490c5de3f9ffb | 0.566614 | 2.893802 | false | false | false | false |
mithro/HDMI2USB | hdl/jpeg_encoder/design/AC_ROM.vhd | 3 | 35,202 | -------------------------------------------------------------------------------
-- File Name : AC_ROM.vhd
--
-- Project : JPEG_ENC
--
-- Module : AC_ROM
--
-- Content : AC_ROM Luminance
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090228: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity AC_ROM is
port
(
CLK : in std_logic;
RST : in std_logic;
runlength : in std_logic_vector(3 downto 0);
VLI_size : in std_logic_vector(3 downto 0);
VLC_AC_size : out unsigned(4 downto 0);
VLC_AC : out unsigned(15 downto 0)
);
end entity AC_ROM;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of AC_ROM is
signal rom_addr : std_logic_vector(7 downto 0);
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
rom_addr <= runlength & VLI_size;
-------------------------------------------------------------------
-- AC-ROM
-------------------------------------------------------------------
p_AC_ROM : process(CLK, RST)
begin
if RST = '1' then
VLC_AC_size <= (others => '0');
VLC_AC <= (others => '0');
elsif CLK'event and CLK = '1' then
case runlength is
when X"0" =>
case VLI_size is
when X"0" =>
VLC_AC_size <= to_unsigned(4, VLC_AC_size'length);
VLC_AC <= resize("1010", VLC_AC'length);
when X"1" =>
VLC_AC_size <= to_unsigned(2, VLC_AC_size'length);
VLC_AC <= resize("00", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(2, VLC_AC_size'length);
VLC_AC <= resize("01", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(3, VLC_AC_size'length);
VLC_AC <= resize("100", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(4, VLC_AC_size'length);
VLC_AC <= resize("1011", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(5, VLC_AC_size'length);
VLC_AC <= resize("11010", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(7, VLC_AC_size'length);
VLC_AC <= resize("1111000", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(8, VLC_AC_size'length);
VLC_AC <= resize("11111000", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111110110", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110000010", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110000011", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"1" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(4, VLC_AC_size'length);
VLC_AC <= resize("1100", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(5, VLC_AC_size'length);
VLC_AC <= resize("11011", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(7, VLC_AC_size'length);
VLC_AC <= resize("1111001", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111110110", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(11, VLC_AC_size'length);
VLC_AC <= resize("11111110110", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110000100", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110000101", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110000110", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110000111", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001000", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"2" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(5, VLC_AC_size'length);
VLC_AC <= resize("11100", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(8, VLC_AC_size'length);
VLC_AC <= resize("11111001", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111110111", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(12, VLC_AC_size'length);
VLC_AC <= resize("111111110100", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001001", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001010", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001011", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001100", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001101", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001110", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"3" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(6, VLC_AC_size'length);
VLC_AC <= resize("111010", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111110111", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(12, VLC_AC_size'length);
VLC_AC <= resize("111111110101", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001111", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010000", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010001", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010010", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010011", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010100", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010101", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"4" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(6, VLC_AC_size'length);
VLC_AC <= resize("111011", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111111000", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010110", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010111", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011000", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011001", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011010", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011011", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011100", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011101", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"5" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(7, VLC_AC_size'length);
VLC_AC <= resize("1111010", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(11, VLC_AC_size'length);
VLC_AC <= resize("11111110111", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011110", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011111", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100000", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100001", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100010", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100011", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100100", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100101", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"6" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(7, VLC_AC_size'length);
VLC_AC <= resize("1111011", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(12, VLC_AC_size'length);
VLC_AC <= resize("111111110110", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100110", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100111", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101000", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101001", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101010", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101011", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101100", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101101", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"7" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(8, VLC_AC_size'length);
VLC_AC <= resize("11111010", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(12, VLC_AC_size'length);
VLC_AC <= resize("111111110111", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101110", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101111", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110000", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110001", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110010", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110011", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110100", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110101", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"8" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111111000", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(15, VLC_AC_size'length);
VLC_AC <= resize("111111111000000", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110110", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110111", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111000", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111001", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111010", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111011", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111100", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111101", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"9" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111111001", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111110", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111111", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000000", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000001", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000010", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000011", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000100", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000101", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000110", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"A" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111111010", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000111", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001000", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001001", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001010", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001011", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001100", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001101", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001110", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001111", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"B" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111111001", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010000", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010001", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010010", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010011", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010100", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010101", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010110", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010111", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011000", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"C" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111111010", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011001", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011010", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011011", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011100", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011101", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011110", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011111", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100000", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100001", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"D" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(11, VLC_AC_size'length);
VLC_AC <= resize("11111111000", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100010", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100011", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100100", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100101", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100110", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100111", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101000", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101001", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101010", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"E" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101011", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101100", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101101", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101110", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101111", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110000", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110001", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110010", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110011", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110100", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"F" =>
case VLI_size is
when X"0" =>
VLC_AC_size <= to_unsigned(11, VLC_AC_size'length);
VLC_AC <= resize("11111111001", VLC_AC'length);
when X"1" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110101", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110110", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110111", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111000", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111001", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111010", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111011", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111100", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111101", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111110", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when others =>
VLC_AC_size <= (others => '0');
VLC_AC <= (others => '0');
end case;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- | bsd-2-clause | b1a9099d97895ceec1a909340d241d4c | 0.45452 | 3.911768 | false | false | false | false |
tomoasleep/vhdl_test_script | examples/datapath.vhd | 1 | 746 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity datapath is
port (
input : in std_logic_vector(1 downto 0);
clk : in std_logic;
output : out std_logic_vector(2 downto 0)
);
end datapath;
architecture behave of datapath is
component state_machine
port(
input: in std_logic;
reset: in std_logic;
state : out std_logic_vector(2 downto 0);
clk : in std_logic
);
end component;
signal stin: std_logic := '0';
signal streset: std_logic := '1';
begin -- behave
st: state_machine port map (
input => stin,
reset => streset,
clk => clk,
state => output);
streset <= input(1);
stin <= input(0);
end behave;
| mit | 0c36697a2cb8b89b9b5a6c414dc965e6 | 0.628686 | 3.174468 | false | false | false | false |
mithro/HDMI2USB | ipcore_dir/image_selector_fifo.vhd | 3 | 10,548 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file image_selector_fifo.vhd when simulating
-- the core, image_selector_fifo. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY image_selector_fifo IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END image_selector_fifo;
ARCHITECTURE image_selector_fifo_a OF image_selector_fifo IS
-- synthesis translate_off
COMPONENT wrapped_image_selector_fifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_image_selector_fifo USE ENTITY XilinxCoreLib.fifo_generator_v9_2(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 8,
c_default_value => "BlankString",
c_din_width => 24,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 24,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 0,
c_has_almost_empty => 1,
c_has_almost_full => 1,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 1,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "512x36",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 255,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 254,
c_prog_full_type => 0,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 8,
c_rd_depth => 256,
c_rd_freq => 1,
c_rd_pntr_width => 8,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 8,
c_wr_depth => 256,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 8,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_image_selector_fifo
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
almost_full => almost_full,
empty => empty,
almost_empty => almost_empty,
valid => valid
);
-- synthesis translate_on
END image_selector_fifo_a;
| bsd-2-clause | 6216edfc8eaa9183c45e7152ae0cacfd | 0.541335 | 3.347509 | false | false | false | false |
dhmeves/ece-485 | ece-485-project-2/control_unit.vhd | 1 | 3,854 | library IEEE;
use ieee.std_logic_1164.all;
entity control_unit is
port(
op : in std_logic_vector(5 downto 0);
clk : in std_logic;
pcWriteCond, pcWrite, IorD, memRead, memWrite, memToReg, irWrite, ALUSrcA, regWrite, regDst, branch_type : out std_logic;
pcSource, ALUSrcB, ALUOp : out std_logic_vector(1 downto 0)
);
end control_unit;
architecture behav of control_unit is
type states is (S_If, S_Id, S_Ex, S_Mem, S_Wb);
type operate is (branch, rtype, load, store, jump, orop, itype);
signal operation : operate;
signal current_state : states;
begin
process(clk) is
begin
if rising_edge(clk) then
if (current_state=S_If) then
current_state<=S_Id;
elsif (current_state=S_Id) then
current_state<=S_Ex;
elsif (current_state=S_Ex) then
current_state<=S_Mem;
elsif (current_state=S_Mem) then
current_state<=S_Wb;
elsif (current_state=S_WB) then
current_state<=S_If;
end if;
end if;
end process;
process(current_state, clk) is
begin
if (current_state=S_If) then
pcWriteCond <= '0';
pcWrite <= '1';
IorD <= '0';
memRead <= '1';
memWrite <= '0';
memToReg <= '0';
irWrite <= '1';
ALUSrcA <= '0';
regWrite <= '1';
regDst <= '1';
pcSource <= "00";
ALUSrcB <= "01";
ALUOp <= "00";
branch_type <= '0';
end if;
if (current_state=S_ID) then
pcWriteCond <= '0';
pcWrite <= '0';
IorD <= '0';
memRead <= '0';
memWrite <= '0';
memToReg <= '0';
irWrite <= '0';
ALUSrcA <= '0';
regWrite <= '0';
regDst <= '0';
pcSource <= "11";
ALUSrcB <= "11";
ALUOp <= "00";
branch_type <= '0';
if (op="000000") then -- rtype
operation<=rtype;
elsif (op="100011") then -- load
operation<=load;
elsif (op="101011") then -- store
operation<=store;
elsif (op="000100") then -- branch
operation<=branch;
ALUOp <= "01";
elsif (op="010000") then -- or
operation<=orop;
elsif (op="001100") then -- itype
operation<=itype;
end if;
end if;
if (current_state=S_Ex) then
pcWriteCond <= '0';
pcWrite <= '0';
IorD <= '0';
memRead <= '0';
memWrite <= '0';
memToReg <= '0';
irWrite <= '0';
ALUSrcA <= '0';
regWrite <= '0';
regDst <= '0';
pcSource <= "11";
ALUSrcB <= "00";
ALUOp <= "00";
if (operation=rtype) then -- add
ALUSrcA <= '1';
ALUSrcB <= "00";
ALUOp <= "10";
elsif (operation=load) then -- lw
ALUSrcA <= '1';
ALUSrcB <= "10";
ALUOp <= "00";
elsif (operation=store) then --sw
ALUSrcA <= '1';
ALUSrcB <= "10";
ALUOp <= "00";
elsif (operation=branch) then -- bne/beq
ALUSrcA <= '1';
ALUSrcB <= "00";
ALUOp <= "01";
pcWriteCond <= '1';
pcSource <= "01";
branch_type <= '0';
elsif (operation=orop) then -- or
ALUSrcA <= '1';
ALUSrcB <= "00";
ALUOp <= "00";
elsif (operation=itype) then -- andi
ALUSrcA <= '1';
ALUSrcB <= "10";
ALUOp <= "10";
end if;
end if;
if (current_state=S_Mem) then
pcSource<= "11";
if falling_edge(clk) and (operation=load) then -- lw
memRead <= '1';
memWrite <= '0';
IorD <= '1';
elsif rising_edge(clk) and (operation=store) then --sw
memRead <= '0';
memWrite <= '1';
IorD <= '1';
end if;
end if;
if (current_state=S_Wb) then
pcSource <= "11";
if (operation=rtype) then
regDst <= '1';
regWrite <= '1';
memToReg <= '0';
elsif (operation=load) then -- lw
regDst <= '1';
regWrite <= '1';
memToReg <= '0';
elsif (operation=orop) then -- or
regDst <= '1';
regWrite <= '1';
memToReg <= '1';
elsif (operation=itype) then -- andi
regDst <= '1';
regWrite <= '1';
memToReg <= '0';
end if;
end if;
end process;
end behav;
| gpl-3.0 | 91c5d84d9729d6a23c1bfe96ac863d13 | 0.541256 | 2.84428 | false | false | false | false |
esar/hdmilight-v2 | fpga/lightAverager.vhd | 1 | 8,641 | ----------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Stephen Robinson
--
-- This file is part of HDMI-Light
--
-- HDMI-Light is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- HDMI-Light is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file names COPING).
-- If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity lightAverager is
port (
CLK : in std_logic;
CE : in std_logic;
START : in std_logic;
YPOS : in std_logic_vector(5 downto 0);
LINE_BUF_ADDR : out std_logic_vector(6 downto 0);
LINE_BUF_DATA : in std_logic_vector(23 downto 0);
CFG_CLK : in std_logic;
CFG_WE : in std_logic;
CFG_ADDR : in std_logic_vector(11 downto 0);
CFG_DIN : in std_logic_vector(7 downto 0);
CFG_DOUT : out std_logic_vector(7 downto 0);
RESULT_CLK : in std_logic;
RESULT_ADDR : in std_logic_vector(7 downto 0);
RESULT_DATA : out std_logic_vector(31 downto 0)
);
end lightAverager;
architecture Behavioral of lightAverager is
-- count is overflow (1), xpos (6), light (8), read/write (1) = 16 bits
signal COUNT : std_logic_vector(15 downto 0);
signal FRAME : std_logic := '0';
signal RUNNING : std_logic;
signal WRITE_CYCLE : std_logic;
signal XPOS : std_logic_vector(5 downto 0);
signal LIGHT_ADDR : std_logic_vector(7 downto 0);
signal WRITE_ENABLE : std_logic;
signal WRITE_ADDR : std_logic_vector(7 downto 0);
signal WRITE_DATA : std_logic_vector(71 downto 0);
signal CONFIG_ADDR : std_logic_vector(8 downto 0);
signal CONFIG_DATA : std_logic_vector(31 downto 0);
signal RESULT_RAM_ADDR : std_logic_vector(8 downto 0);
signal RESULT_RAM_WE : std_logic;
signal RESULT_RAM_D : std_logic_vector(71 downto 0);
signal RESULT_RAM_Q : std_logic_vector(71 downto 0);
signal RESULT_RAM_B_ADDR : std_logic_vector(8 downto 0);
signal RESULT_RAM_B_Q : std_logic_vector(71 downto 0);
signal XMIN_p0 : std_logic_vector(5 downto 0);
signal XMAX_p0 : std_logic_vector(5 downto 0);
signal YMIN_p0 : std_logic_vector(5 downto 0);
signal YMAX_p0 : std_logic_vector(5 downto 0);
signal SHIFT_p0 : std_logic_vector(3 downto 0);
signal R_TOTAL_p0 : std_logic_vector(20 downto 0);
signal G_TOTAL_p0 : std_logic_vector(20 downto 0);
signal B_TOTAL_p0 : std_logic_vector(20 downto 0);
signal R_p0 : std_logic_vector(7 downto 0);
signal G_p0 : std_logic_vector(7 downto 0);
signal B_p0 : std_logic_vector(7 downto 0);
signal WRITE_ADDR_p0 : std_logic_vector(7 downto 0);
signal XPOS_p0 : std_logic_vector(5 downto 0);
signal YPOS_p0 : std_logic_vector(5 downto 0);
signal RUNNING_p0 : std_logic;
signal SHIFT_p1 : std_logic_vector(3 downto 0);
signal R_TOTAL_p1 : std_logic_vector(20 downto 0);
signal G_TOTAL_p1 : std_logic_vector(20 downto 0);
signal B_TOTAL_p1 : std_logic_vector(20 downto 0);
signal WRITE_ADDR_p1 : std_logic_vector(7 downto 0);
signal WRITE_ENABLE_p1 : std_logic;
signal R_TOTAL_p2 : std_logic_vector(20 downto 0);
signal G_TOTAL_p2 : std_logic_vector(20 downto 0);
signal B_TOTAL_p2 : std_logic_vector(20 downto 0);
signal WRITE_ADDR_p2 : std_logic_vector(7 downto 0);
signal WRITE_ENABLE_p2 : std_logic;
begin
resultBuffer : entity work.blockram
GENERIC MAP(
ADDR => 9,
DATA => 72
)
PORT MAP (
a_clk => CLK,
a_en => CE,
a_wr => RESULT_RAM_WE,
a_rst => '0',
a_addr => RESULT_RAM_ADDR,
a_din => RESULT_RAM_D,
a_dout => RESULT_RAM_Q,
b_clk => RESULT_CLK,
b_en => '1',
b_wr => '0',
b_rst => '0',
b_addr => RESULT_RAM_B_ADDR,
b_din => (others=> '0'),
b_dout => RESULT_RAM_B_Q
);
configRam : entity work.lightConfigRam
PORT MAP (
a_clk => CFG_CLK,
a_wr => CFG_WE,
a_addr => CFG_ADDR,
a_din => CFG_DIN,
a_dout => CFG_DOUT,
b_clk => CLK,
b_addr => CONFIG_ADDR,
b_dout => CONFIG_DATA
);
process(CLK)
begin
if(rising_edge(CLK)) then
if(CE = '1') then
if(START = '1') then
COUNT <= (others => '0');
RUNNING <= '1';
if(YPOS = "000000") then
FRAME <= not FRAME;
end if;
elsif(COUNT(15) = '1') then
RUNNING <= '0';
else
COUNT <= std_logic_vector(unsigned(COUNT) + 1);
end if;
end if;
end if;
end process;
process(CLK)
begin
if(rising_edge(CLK)) then
if(CE = '1') then
-- read address is set when write_cycle = '0'
-- so read data is available when write_cycle = '1'
if(WRITE_CYCLE = '1') then
XMIN_p0 <= CONFIG_DATA(5 downto 0);
XMAX_p0 <= CONFIG_DATA(11 downto 6);
YMIN_p0 <= CONFIG_DATA(17 downto 12);
YMAX_p0 <= CONFIG_DATA(23 downto 18);
SHIFT_p0 <= CONFIG_DATA(27 downto 24);
R_TOTAL_p0 <= RESULT_RAM_Q(62 downto 42);
G_TOTAL_p0 <= RESULT_RAM_Q(41 downto 21);
B_TOTAL_p0 <= RESULT_RAM_Q(20 downto 0);
R_p0 <= LINE_BUF_DATA(23 downto 16);
G_p0 <= LINE_BUF_DATA(15 downto 8);
B_p0 <= LINE_BUF_DATA( 7 downto 0);
WRITE_ADDR_p0 <= LIGHT_ADDR;
XPOS_p0 <= XPOS;
YPOS_p0 <= YPOS;
RUNNING_p0 <= RUNNING;
end if;
end if;
end if;
end process;
process(CLK)
begin
if(rising_edge(CLK)) then
if(CE = '1') then
if(RUNNING_p0 = '1' and
unsigned(XPOS_p0) >= unsigned(XMIN_p0) and unsigned(XPOS_p0) <= unsigned(XMAX_p0) and
unsigned(YPOS_p0) >= unsigned(YMIN_p0) and unsigned(YPOS_p0) <= unsigned(YMAX_p0)) then
WRITE_ENABLE_p1 <= '1';
else
WRITE_ENABLE_p1 <= '0';
end if;
if(XPOS_p0 = XMIN_p0 and YPOS_p0 = YMIN_p0) then
R_TOTAL_p1 <= "0000000000000" & R_p0;
G_TOTAL_p1 <= "0000000000000" & G_p0;
B_TOTAL_p1 <= "0000000000000" & B_p0;
else
R_TOTAL_p1 <= std_logic_vector(unsigned(R_TOTAL_p0) + unsigned(R_p0));
G_TOTAL_p1 <= std_logic_vector(unsigned(G_TOTAL_p0) + unsigned(G_p0));
B_TOTAL_p1 <= std_logic_vector(unsigned(B_TOTAL_p0) + unsigned(B_p0));
end if;
if(XPOS_p0 = XMAX_p0 and YPOS_p0 = YMAX_p0) then
SHIFT_p1 <= SHIFT_p0;
else
SHIFT_p1 <= (others => '0');
end if;
WRITE_ADDR_p1 <= WRITE_ADDR_p0;
end if;
end if;
end process;
process(CLK)
begin
if(rising_edge(CLK)) then
if(CE = '1') then
R_TOTAL_p2 <= std_logic_vector(unsigned(R_TOTAL_p1) srl to_integer(unsigned(SHIFT_p1)));
G_TOTAL_p2 <= std_logic_vector(unsigned(G_TOTAL_p1) srl to_integer(unsigned(SHIFT_p1)));
B_TOTAL_p2 <= std_logic_vector(unsigned(B_TOTAL_p1) srl to_integer(unsigned(SHIFT_p1)));
WRITE_ENABLE_p2 <= WRITE_ENABLE_p1;
WRITE_ADDR_p2 <= WRITE_ADDR_p1;
end if;
end if;
end process;
WRITE_ENABLE <= '1' when WRITE_ENABLE_p2 = '1' and WRITE_CYCLE = '1' else '0';
WRITE_ADDR <= WRITE_ADDR_p2;
WRITE_DATA(71 downto 63) <= (others => '0');
WRITE_DATA(62 downto 42) <= R_TOTAL_p2;
WRITE_DATA(41 downto 21) <= G_TOTAL_p2;
WRITE_DATA(20 downto 0) <= B_TOTAL_p2;
WRITE_CYCLE <= COUNT(0);
LIGHT_ADDR <= COUNT(8 downto 1);
XPOS <= COUNT(14 downto 9);
CONFIG_ADDR <= "0" & LIGHT_ADDR;
LINE_BUF_ADDR <= YPOS(0) & XPOS;
RESULT_RAM_ADDR <= (not FRAME) & LIGHT_ADDR when WRITE_CYCLE = '0' else (not FRAME) & WRITE_ADDR;
RESULT_RAM_WE <= '0' when WRITE_CYCLE = '0' else WRITE_ENABLE;
RESULT_RAM_D <= WRITE_DATA;
RESULT_RAM_B_ADDR <= FRAME & RESULT_ADDR;
RESULT_DATA( 7 downto 0) <= RESULT_RAM_B_Q( 7 downto 0);
RESULT_DATA(15 downto 8) <= RESULT_RAM_B_Q(28 downto 21);
RESULT_DATA(23 downto 16) <= RESULT_RAM_B_Q(49 downto 42);
RESULT_DATA(26 downto 24) <= RESULT_RAM_B_Q(65 downto 63);
RESULT_DATA(31 downto 27) <= (others => '0');
end Behavioral;
| gpl-2.0 | 6453e8aa804f804b757a4177c476d49b | 0.616827 | 2.870764 | false | false | false | false |
RickvanLoo/Synthesizer | DDS.vhd | 1 | 3,405 | LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY DDS IS
GENERIC(lut_bit_width : integer := 8;
pa_bit_width : integer := 32
);
PORT (
clk : IN std_logic;
reset : IN std_logic;
ENABLE : in std_logic;
NOTE_ON_DDS: in std_logic_vector(7 downto 0); --Note ON/OFF 0x80(off), 0xFF(on);
SI_DATA, SQ_DATA, SA_DATA, TR_DATA : OUT std_logic_vector(15 downto 0);
a_clk : OUT std_logic
);
END ENTITY DDS;
ARCHITECTURE behav of DDS is
component NOTE_2_PA IS
GENERIC(lut_bit_width : integer := 8;
pa_bit_width : integer := 32
);
PORT ( CLK : in std_logic;
RESET : in std_logic;
ENABLE : in std_logic;
NOTE_ON : in std_logic_vector(7 downto 0); --Note ON/OFF 0x80(off), 0xFF(on);
PA_word : OUT unsigned(pa_bit_width-1 downto 0)
);
END component;
component phaseaccum_entity
GENERIC(max_length : integer := 2147483647;
lut_bit_width : integer := 8;
pa_bit_width : integer := 32
);
PORT (a_clk : IN std_logic;
reset : IN std_logic;
PA_word : IN unsigned(pa_bit_width-1 downto 0);
phase_out : OUT unsigned(lut_bit_width-1 downto 0)
);
END component;
component sinelut_entity IS
GENERIC(lut_bit_width : integer := 8
);
PORT(
phase_in : in unsigned(lut_bit_width-1 downto 0);
a_clk : in std_logic;
reset : in std_logic;
DATA : OUT std_logic_vector(15 downto 0)
);
END component;
component pulselut_entity IS
GENERIC(lut_bit_width : integer := 8
);
PORT(
phase_in : in unsigned(lut_bit_width-1 downto 0);
a_clk : in std_logic;
reset : in std_logic;
DATA : OUT std_logic_vector(15 downto 0)
);
END component;
component sawlut_entity IS
GENERIC(lut_bit_width : integer := 8
);
PORT(
phase_in : in unsigned(lut_bit_width-1 downto 0);
a_clk : in std_logic;
reset : in std_logic;
DATA : OUT std_logic_vector(15 downto 0)
);
END component;
component trilut_entity IS
GENERIC(lut_bit_width : integer := 8
);
PORT(
phase_in : in unsigned(lut_bit_width-1 downto 0);
a_clk : in std_logic;
reset : in std_logic;
DATA : OUT std_logic_vector(15 downto 0)
);
END component;
component sample_clk_gen_entity is
GENERIC(divider : integer := 512
);
PORT (clk : IN std_logic;
reset : IN std_logic;
a_clk : OUT std_logic;
a_clk_main : OUT std_logic
);
END component;
signal as_clk : std_logic;
signal a_phase_out : unsigned(lut_bit_width-1 downto 0);
signal PAs_word : unsigned(pa_bit_width-1 downto 0);
BEGIN
G1: sample_clk_gen_entity port map(clk=>clk, reset=>reset, a_clk=>as_clk, a_clk_main=>a_clk);
G2: NOTE_2_PA port map(CLK=>CLK, RESET=>RESET, NOTE_ON=>NOTE_ON_DDS, ENABLE=>ENABLE, PA_word=>PAs_word);
G3: phaseaccum_entity port map(a_clk=>as_clk, reset=>reset, PA_word=>PAs_word, phase_out=>a_phase_out);
G4: sinelut_entity port map(phase_in=>a_phase_out, a_clk=>as_clk, reset=>reset, DATA=>SI_DATA);
G5: pulselut_entity port map(phase_in=>a_phase_out, a_clk=>as_clk, reset=>reset, DATA=>SQ_DATA);
G6: sawlut_entity port map(phase_in=>a_phase_out, a_clk=>as_clk, reset=>reset, DATA=>SA_DATA);
G7: trilut_entity port map(phase_in=>a_phase_out, a_clk=>as_clk, reset=>reset, DATA=>TR_DATA);
END BEHAV; | mit | 44be56c7d6c5f3c7996d4b6e2f336c59 | 0.61674 | 2.880711 | false | false | false | false |
Nooxet/embedded_bruteforce | brutus_system/hdl/elaborate/microblaze_0_bram_block_elaborate_v1_00_a/hdl/vhdl/microblaze_0_bram_block_elaborate.vhd | 1 | 35,484 | -------------------------------------------------------------------------------
-- microblaze_0_bram_block_elaborate.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity microblaze_0_bram_block_elaborate is
generic (
C_MEMSIZE : integer;
C_PORT_DWIDTH : integer;
C_PORT_AWIDTH : integer;
C_NUM_WE : integer;
C_FAMILY : string
);
port (
BRAM_Rst_A : in std_logic;
BRAM_Clk_A : in std_logic;
BRAM_EN_A : in std_logic;
BRAM_WEN_A : in std_logic_vector(0 to C_NUM_WE-1);
BRAM_Addr_A : in std_logic_vector(0 to C_PORT_AWIDTH-1);
BRAM_Din_A : out std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Dout_A : in std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Rst_B : in std_logic;
BRAM_Clk_B : in std_logic;
BRAM_EN_B : in std_logic;
BRAM_WEN_B : in std_logic_vector(0 to C_NUM_WE-1);
BRAM_Addr_B : in std_logic_vector(0 to C_PORT_AWIDTH-1);
BRAM_Din_B : out std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Dout_B : in std_logic_vector(0 to C_PORT_DWIDTH-1)
);
attribute keep_hierarchy : STRING;
attribute keep_hierarchy of microblaze_0_bram_block_elaborate : entity is "yes";
end microblaze_0_bram_block_elaborate;
architecture STRUCTURE of microblaze_0_bram_block_elaborate is
component RAMB16BWER is
generic (
INIT_FILE : string;
DATA_WIDTH_A : integer;
DATA_WIDTH_B : integer
);
port (
ADDRA : in std_logic_vector(13 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector(31 downto 0);
DIPA : in std_logic_vector(3 downto 0);
DOA : out std_logic_vector(31 downto 0);
DOPA : out std_logic_vector(3 downto 0);
ENA : in std_logic;
REGCEA : in std_logic;
RSTA : in std_logic;
WEA : in std_logic_vector(3 downto 0);
ADDRB : in std_logic_vector(13 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector(31 downto 0);
DIPB : in std_logic_vector(3 downto 0);
DOB : out std_logic_vector(31 downto 0);
DOPB : out std_logic_vector(3 downto 0);
ENB : in std_logic;
REGCEB : in std_logic;
RSTB : in std_logic;
WEB : in std_logic_vector(3 downto 0)
);
end component;
attribute BMM_INFO : STRING;
attribute BMM_INFO of ramb16bwer_0: label is " ";
attribute BMM_INFO of ramb16bwer_1: label is " ";
attribute BMM_INFO of ramb16bwer_2: label is " ";
attribute BMM_INFO of ramb16bwer_3: label is " ";
attribute BMM_INFO of ramb16bwer_4: label is " ";
attribute BMM_INFO of ramb16bwer_5: label is " ";
attribute BMM_INFO of ramb16bwer_6: label is " ";
attribute BMM_INFO of ramb16bwer_7: label is " ";
attribute BMM_INFO of ramb16bwer_8: label is " ";
attribute BMM_INFO of ramb16bwer_9: label is " ";
attribute BMM_INFO of ramb16bwer_10: label is " ";
attribute BMM_INFO of ramb16bwer_11: label is " ";
attribute BMM_INFO of ramb16bwer_12: label is " ";
attribute BMM_INFO of ramb16bwer_13: label is " ";
attribute BMM_INFO of ramb16bwer_14: label is " ";
attribute BMM_INFO of ramb16bwer_15: label is " ";
-- Internal signals
signal net_gnd0 : std_logic;
signal net_gnd4 : std_logic_vector(3 downto 0);
signal pgassign1 : std_logic_vector(0 to 0);
signal pgassign2 : std_logic_vector(0 to 29);
signal pgassign3 : std_logic_vector(13 downto 0);
signal pgassign4 : std_logic_vector(31 downto 0);
signal pgassign5 : std_logic_vector(31 downto 0);
signal pgassign6 : std_logic_vector(3 downto 0);
signal pgassign7 : std_logic_vector(13 downto 0);
signal pgassign8 : std_logic_vector(31 downto 0);
signal pgassign9 : std_logic_vector(31 downto 0);
signal pgassign10 : std_logic_vector(3 downto 0);
signal pgassign11 : std_logic_vector(13 downto 0);
signal pgassign12 : std_logic_vector(31 downto 0);
signal pgassign13 : std_logic_vector(31 downto 0);
signal pgassign14 : std_logic_vector(3 downto 0);
signal pgassign15 : std_logic_vector(13 downto 0);
signal pgassign16 : std_logic_vector(31 downto 0);
signal pgassign17 : std_logic_vector(31 downto 0);
signal pgassign18 : std_logic_vector(3 downto 0);
signal pgassign19 : std_logic_vector(13 downto 0);
signal pgassign20 : std_logic_vector(31 downto 0);
signal pgassign21 : std_logic_vector(31 downto 0);
signal pgassign22 : std_logic_vector(3 downto 0);
signal pgassign23 : std_logic_vector(13 downto 0);
signal pgassign24 : std_logic_vector(31 downto 0);
signal pgassign25 : std_logic_vector(31 downto 0);
signal pgassign26 : std_logic_vector(3 downto 0);
signal pgassign27 : std_logic_vector(13 downto 0);
signal pgassign28 : std_logic_vector(31 downto 0);
signal pgassign29 : std_logic_vector(31 downto 0);
signal pgassign30 : std_logic_vector(3 downto 0);
signal pgassign31 : std_logic_vector(13 downto 0);
signal pgassign32 : std_logic_vector(31 downto 0);
signal pgassign33 : std_logic_vector(31 downto 0);
signal pgassign34 : std_logic_vector(3 downto 0);
signal pgassign35 : std_logic_vector(13 downto 0);
signal pgassign36 : std_logic_vector(31 downto 0);
signal pgassign37 : std_logic_vector(31 downto 0);
signal pgassign38 : std_logic_vector(3 downto 0);
signal pgassign39 : std_logic_vector(13 downto 0);
signal pgassign40 : std_logic_vector(31 downto 0);
signal pgassign41 : std_logic_vector(31 downto 0);
signal pgassign42 : std_logic_vector(3 downto 0);
signal pgassign43 : std_logic_vector(13 downto 0);
signal pgassign44 : std_logic_vector(31 downto 0);
signal pgassign45 : std_logic_vector(31 downto 0);
signal pgassign46 : std_logic_vector(3 downto 0);
signal pgassign47 : std_logic_vector(13 downto 0);
signal pgassign48 : std_logic_vector(31 downto 0);
signal pgassign49 : std_logic_vector(31 downto 0);
signal pgassign50 : std_logic_vector(3 downto 0);
signal pgassign51 : std_logic_vector(13 downto 0);
signal pgassign52 : std_logic_vector(31 downto 0);
signal pgassign53 : std_logic_vector(31 downto 0);
signal pgassign54 : std_logic_vector(3 downto 0);
signal pgassign55 : std_logic_vector(13 downto 0);
signal pgassign56 : std_logic_vector(31 downto 0);
signal pgassign57 : std_logic_vector(31 downto 0);
signal pgassign58 : std_logic_vector(3 downto 0);
signal pgassign59 : std_logic_vector(13 downto 0);
signal pgassign60 : std_logic_vector(31 downto 0);
signal pgassign61 : std_logic_vector(31 downto 0);
signal pgassign62 : std_logic_vector(3 downto 0);
signal pgassign63 : std_logic_vector(13 downto 0);
signal pgassign64 : std_logic_vector(31 downto 0);
signal pgassign65 : std_logic_vector(31 downto 0);
signal pgassign66 : std_logic_vector(3 downto 0);
signal pgassign67 : std_logic_vector(13 downto 0);
signal pgassign68 : std_logic_vector(31 downto 0);
signal pgassign69 : std_logic_vector(31 downto 0);
signal pgassign70 : std_logic_vector(3 downto 0);
signal pgassign71 : std_logic_vector(13 downto 0);
signal pgassign72 : std_logic_vector(31 downto 0);
signal pgassign73 : std_logic_vector(31 downto 0);
signal pgassign74 : std_logic_vector(3 downto 0);
signal pgassign75 : std_logic_vector(13 downto 0);
signal pgassign76 : std_logic_vector(31 downto 0);
signal pgassign77 : std_logic_vector(31 downto 0);
signal pgassign78 : std_logic_vector(3 downto 0);
signal pgassign79 : std_logic_vector(13 downto 0);
signal pgassign80 : std_logic_vector(31 downto 0);
signal pgassign81 : std_logic_vector(31 downto 0);
signal pgassign82 : std_logic_vector(3 downto 0);
signal pgassign83 : std_logic_vector(13 downto 0);
signal pgassign84 : std_logic_vector(31 downto 0);
signal pgassign85 : std_logic_vector(31 downto 0);
signal pgassign86 : std_logic_vector(3 downto 0);
signal pgassign87 : std_logic_vector(13 downto 0);
signal pgassign88 : std_logic_vector(31 downto 0);
signal pgassign89 : std_logic_vector(31 downto 0);
signal pgassign90 : std_logic_vector(3 downto 0);
signal pgassign91 : std_logic_vector(13 downto 0);
signal pgassign92 : std_logic_vector(31 downto 0);
signal pgassign93 : std_logic_vector(31 downto 0);
signal pgassign94 : std_logic_vector(3 downto 0);
signal pgassign95 : std_logic_vector(13 downto 0);
signal pgassign96 : std_logic_vector(31 downto 0);
signal pgassign97 : std_logic_vector(31 downto 0);
signal pgassign98 : std_logic_vector(3 downto 0);
signal pgassign99 : std_logic_vector(13 downto 0);
signal pgassign100 : std_logic_vector(31 downto 0);
signal pgassign101 : std_logic_vector(31 downto 0);
signal pgassign102 : std_logic_vector(3 downto 0);
signal pgassign103 : std_logic_vector(13 downto 0);
signal pgassign104 : std_logic_vector(31 downto 0);
signal pgassign105 : std_logic_vector(31 downto 0);
signal pgassign106 : std_logic_vector(3 downto 0);
signal pgassign107 : std_logic_vector(13 downto 0);
signal pgassign108 : std_logic_vector(31 downto 0);
signal pgassign109 : std_logic_vector(31 downto 0);
signal pgassign110 : std_logic_vector(3 downto 0);
signal pgassign111 : std_logic_vector(13 downto 0);
signal pgassign112 : std_logic_vector(31 downto 0);
signal pgassign113 : std_logic_vector(31 downto 0);
signal pgassign114 : std_logic_vector(3 downto 0);
signal pgassign115 : std_logic_vector(13 downto 0);
signal pgassign116 : std_logic_vector(31 downto 0);
signal pgassign117 : std_logic_vector(31 downto 0);
signal pgassign118 : std_logic_vector(3 downto 0);
signal pgassign119 : std_logic_vector(13 downto 0);
signal pgassign120 : std_logic_vector(31 downto 0);
signal pgassign121 : std_logic_vector(31 downto 0);
signal pgassign122 : std_logic_vector(3 downto 0);
signal pgassign123 : std_logic_vector(13 downto 0);
signal pgassign124 : std_logic_vector(31 downto 0);
signal pgassign125 : std_logic_vector(31 downto 0);
signal pgassign126 : std_logic_vector(3 downto 0);
signal pgassign127 : std_logic_vector(13 downto 0);
signal pgassign128 : std_logic_vector(31 downto 0);
signal pgassign129 : std_logic_vector(31 downto 0);
signal pgassign130 : std_logic_vector(3 downto 0);
begin
-- Internal assignments
pgassign1(0 to 0) <= B"0";
pgassign2(0 to 29) <= B"000000000000000000000000000000";
pgassign3(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign3(0 downto 0) <= B"0";
pgassign4(31 downto 2) <= B"000000000000000000000000000000";
pgassign4(1 downto 0) <= BRAM_Dout_A(0 to 1);
BRAM_Din_A(0 to 1) <= pgassign5(1 downto 0);
pgassign6(3 downto 3) <= BRAM_WEN_A(0 to 0);
pgassign6(2 downto 2) <= BRAM_WEN_A(0 to 0);
pgassign6(1 downto 1) <= BRAM_WEN_A(0 to 0);
pgassign6(0 downto 0) <= BRAM_WEN_A(0 to 0);
pgassign7(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign7(0 downto 0) <= B"0";
pgassign8(31 downto 2) <= B"000000000000000000000000000000";
pgassign8(1 downto 0) <= BRAM_Dout_B(0 to 1);
BRAM_Din_B(0 to 1) <= pgassign9(1 downto 0);
pgassign10(3 downto 3) <= BRAM_WEN_B(0 to 0);
pgassign10(2 downto 2) <= BRAM_WEN_B(0 to 0);
pgassign10(1 downto 1) <= BRAM_WEN_B(0 to 0);
pgassign10(0 downto 0) <= BRAM_WEN_B(0 to 0);
pgassign11(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign11(0 downto 0) <= B"0";
pgassign12(31 downto 2) <= B"000000000000000000000000000000";
pgassign12(1 downto 0) <= BRAM_Dout_A(2 to 3);
BRAM_Din_A(2 to 3) <= pgassign13(1 downto 0);
pgassign14(3 downto 3) <= BRAM_WEN_A(0 to 0);
pgassign14(2 downto 2) <= BRAM_WEN_A(0 to 0);
pgassign14(1 downto 1) <= BRAM_WEN_A(0 to 0);
pgassign14(0 downto 0) <= BRAM_WEN_A(0 to 0);
pgassign15(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign15(0 downto 0) <= B"0";
pgassign16(31 downto 2) <= B"000000000000000000000000000000";
pgassign16(1 downto 0) <= BRAM_Dout_B(2 to 3);
BRAM_Din_B(2 to 3) <= pgassign17(1 downto 0);
pgassign18(3 downto 3) <= BRAM_WEN_B(0 to 0);
pgassign18(2 downto 2) <= BRAM_WEN_B(0 to 0);
pgassign18(1 downto 1) <= BRAM_WEN_B(0 to 0);
pgassign18(0 downto 0) <= BRAM_WEN_B(0 to 0);
pgassign19(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign19(0 downto 0) <= B"0";
pgassign20(31 downto 2) <= B"000000000000000000000000000000";
pgassign20(1 downto 0) <= BRAM_Dout_A(4 to 5);
BRAM_Din_A(4 to 5) <= pgassign21(1 downto 0);
pgassign22(3 downto 3) <= BRAM_WEN_A(0 to 0);
pgassign22(2 downto 2) <= BRAM_WEN_A(0 to 0);
pgassign22(1 downto 1) <= BRAM_WEN_A(0 to 0);
pgassign22(0 downto 0) <= BRAM_WEN_A(0 to 0);
pgassign23(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign23(0 downto 0) <= B"0";
pgassign24(31 downto 2) <= B"000000000000000000000000000000";
pgassign24(1 downto 0) <= BRAM_Dout_B(4 to 5);
BRAM_Din_B(4 to 5) <= pgassign25(1 downto 0);
pgassign26(3 downto 3) <= BRAM_WEN_B(0 to 0);
pgassign26(2 downto 2) <= BRAM_WEN_B(0 to 0);
pgassign26(1 downto 1) <= BRAM_WEN_B(0 to 0);
pgassign26(0 downto 0) <= BRAM_WEN_B(0 to 0);
pgassign27(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign27(0 downto 0) <= B"0";
pgassign28(31 downto 2) <= B"000000000000000000000000000000";
pgassign28(1 downto 0) <= BRAM_Dout_A(6 to 7);
BRAM_Din_A(6 to 7) <= pgassign29(1 downto 0);
pgassign30(3 downto 3) <= BRAM_WEN_A(0 to 0);
pgassign30(2 downto 2) <= BRAM_WEN_A(0 to 0);
pgassign30(1 downto 1) <= BRAM_WEN_A(0 to 0);
pgassign30(0 downto 0) <= BRAM_WEN_A(0 to 0);
pgassign31(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign31(0 downto 0) <= B"0";
pgassign32(31 downto 2) <= B"000000000000000000000000000000";
pgassign32(1 downto 0) <= BRAM_Dout_B(6 to 7);
BRAM_Din_B(6 to 7) <= pgassign33(1 downto 0);
pgassign34(3 downto 3) <= BRAM_WEN_B(0 to 0);
pgassign34(2 downto 2) <= BRAM_WEN_B(0 to 0);
pgassign34(1 downto 1) <= BRAM_WEN_B(0 to 0);
pgassign34(0 downto 0) <= BRAM_WEN_B(0 to 0);
pgassign35(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign35(0 downto 0) <= B"0";
pgassign36(31 downto 2) <= B"000000000000000000000000000000";
pgassign36(1 downto 0) <= BRAM_Dout_A(8 to 9);
BRAM_Din_A(8 to 9) <= pgassign37(1 downto 0);
pgassign38(3 downto 3) <= BRAM_WEN_A(1 to 1);
pgassign38(2 downto 2) <= BRAM_WEN_A(1 to 1);
pgassign38(1 downto 1) <= BRAM_WEN_A(1 to 1);
pgassign38(0 downto 0) <= BRAM_WEN_A(1 to 1);
pgassign39(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign39(0 downto 0) <= B"0";
pgassign40(31 downto 2) <= B"000000000000000000000000000000";
pgassign40(1 downto 0) <= BRAM_Dout_B(8 to 9);
BRAM_Din_B(8 to 9) <= pgassign41(1 downto 0);
pgassign42(3 downto 3) <= BRAM_WEN_B(1 to 1);
pgassign42(2 downto 2) <= BRAM_WEN_B(1 to 1);
pgassign42(1 downto 1) <= BRAM_WEN_B(1 to 1);
pgassign42(0 downto 0) <= BRAM_WEN_B(1 to 1);
pgassign43(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign43(0 downto 0) <= B"0";
pgassign44(31 downto 2) <= B"000000000000000000000000000000";
pgassign44(1 downto 0) <= BRAM_Dout_A(10 to 11);
BRAM_Din_A(10 to 11) <= pgassign45(1 downto 0);
pgassign46(3 downto 3) <= BRAM_WEN_A(1 to 1);
pgassign46(2 downto 2) <= BRAM_WEN_A(1 to 1);
pgassign46(1 downto 1) <= BRAM_WEN_A(1 to 1);
pgassign46(0 downto 0) <= BRAM_WEN_A(1 to 1);
pgassign47(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign47(0 downto 0) <= B"0";
pgassign48(31 downto 2) <= B"000000000000000000000000000000";
pgassign48(1 downto 0) <= BRAM_Dout_B(10 to 11);
BRAM_Din_B(10 to 11) <= pgassign49(1 downto 0);
pgassign50(3 downto 3) <= BRAM_WEN_B(1 to 1);
pgassign50(2 downto 2) <= BRAM_WEN_B(1 to 1);
pgassign50(1 downto 1) <= BRAM_WEN_B(1 to 1);
pgassign50(0 downto 0) <= BRAM_WEN_B(1 to 1);
pgassign51(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign51(0 downto 0) <= B"0";
pgassign52(31 downto 2) <= B"000000000000000000000000000000";
pgassign52(1 downto 0) <= BRAM_Dout_A(12 to 13);
BRAM_Din_A(12 to 13) <= pgassign53(1 downto 0);
pgassign54(3 downto 3) <= BRAM_WEN_A(1 to 1);
pgassign54(2 downto 2) <= BRAM_WEN_A(1 to 1);
pgassign54(1 downto 1) <= BRAM_WEN_A(1 to 1);
pgassign54(0 downto 0) <= BRAM_WEN_A(1 to 1);
pgassign55(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign55(0 downto 0) <= B"0";
pgassign56(31 downto 2) <= B"000000000000000000000000000000";
pgassign56(1 downto 0) <= BRAM_Dout_B(12 to 13);
BRAM_Din_B(12 to 13) <= pgassign57(1 downto 0);
pgassign58(3 downto 3) <= BRAM_WEN_B(1 to 1);
pgassign58(2 downto 2) <= BRAM_WEN_B(1 to 1);
pgassign58(1 downto 1) <= BRAM_WEN_B(1 to 1);
pgassign58(0 downto 0) <= BRAM_WEN_B(1 to 1);
pgassign59(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign59(0 downto 0) <= B"0";
pgassign60(31 downto 2) <= B"000000000000000000000000000000";
pgassign60(1 downto 0) <= BRAM_Dout_A(14 to 15);
BRAM_Din_A(14 to 15) <= pgassign61(1 downto 0);
pgassign62(3 downto 3) <= BRAM_WEN_A(1 to 1);
pgassign62(2 downto 2) <= BRAM_WEN_A(1 to 1);
pgassign62(1 downto 1) <= BRAM_WEN_A(1 to 1);
pgassign62(0 downto 0) <= BRAM_WEN_A(1 to 1);
pgassign63(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign63(0 downto 0) <= B"0";
pgassign64(31 downto 2) <= B"000000000000000000000000000000";
pgassign64(1 downto 0) <= BRAM_Dout_B(14 to 15);
BRAM_Din_B(14 to 15) <= pgassign65(1 downto 0);
pgassign66(3 downto 3) <= BRAM_WEN_B(1 to 1);
pgassign66(2 downto 2) <= BRAM_WEN_B(1 to 1);
pgassign66(1 downto 1) <= BRAM_WEN_B(1 to 1);
pgassign66(0 downto 0) <= BRAM_WEN_B(1 to 1);
pgassign67(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign67(0 downto 0) <= B"0";
pgassign68(31 downto 2) <= B"000000000000000000000000000000";
pgassign68(1 downto 0) <= BRAM_Dout_A(16 to 17);
BRAM_Din_A(16 to 17) <= pgassign69(1 downto 0);
pgassign70(3 downto 3) <= BRAM_WEN_A(2 to 2);
pgassign70(2 downto 2) <= BRAM_WEN_A(2 to 2);
pgassign70(1 downto 1) <= BRAM_WEN_A(2 to 2);
pgassign70(0 downto 0) <= BRAM_WEN_A(2 to 2);
pgassign71(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign71(0 downto 0) <= B"0";
pgassign72(31 downto 2) <= B"000000000000000000000000000000";
pgassign72(1 downto 0) <= BRAM_Dout_B(16 to 17);
BRAM_Din_B(16 to 17) <= pgassign73(1 downto 0);
pgassign74(3 downto 3) <= BRAM_WEN_B(2 to 2);
pgassign74(2 downto 2) <= BRAM_WEN_B(2 to 2);
pgassign74(1 downto 1) <= BRAM_WEN_B(2 to 2);
pgassign74(0 downto 0) <= BRAM_WEN_B(2 to 2);
pgassign75(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign75(0 downto 0) <= B"0";
pgassign76(31 downto 2) <= B"000000000000000000000000000000";
pgassign76(1 downto 0) <= BRAM_Dout_A(18 to 19);
BRAM_Din_A(18 to 19) <= pgassign77(1 downto 0);
pgassign78(3 downto 3) <= BRAM_WEN_A(2 to 2);
pgassign78(2 downto 2) <= BRAM_WEN_A(2 to 2);
pgassign78(1 downto 1) <= BRAM_WEN_A(2 to 2);
pgassign78(0 downto 0) <= BRAM_WEN_A(2 to 2);
pgassign79(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign79(0 downto 0) <= B"0";
pgassign80(31 downto 2) <= B"000000000000000000000000000000";
pgassign80(1 downto 0) <= BRAM_Dout_B(18 to 19);
BRAM_Din_B(18 to 19) <= pgassign81(1 downto 0);
pgassign82(3 downto 3) <= BRAM_WEN_B(2 to 2);
pgassign82(2 downto 2) <= BRAM_WEN_B(2 to 2);
pgassign82(1 downto 1) <= BRAM_WEN_B(2 to 2);
pgassign82(0 downto 0) <= BRAM_WEN_B(2 to 2);
pgassign83(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign83(0 downto 0) <= B"0";
pgassign84(31 downto 2) <= B"000000000000000000000000000000";
pgassign84(1 downto 0) <= BRAM_Dout_A(20 to 21);
BRAM_Din_A(20 to 21) <= pgassign85(1 downto 0);
pgassign86(3 downto 3) <= BRAM_WEN_A(2 to 2);
pgassign86(2 downto 2) <= BRAM_WEN_A(2 to 2);
pgassign86(1 downto 1) <= BRAM_WEN_A(2 to 2);
pgassign86(0 downto 0) <= BRAM_WEN_A(2 to 2);
pgassign87(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign87(0 downto 0) <= B"0";
pgassign88(31 downto 2) <= B"000000000000000000000000000000";
pgassign88(1 downto 0) <= BRAM_Dout_B(20 to 21);
BRAM_Din_B(20 to 21) <= pgassign89(1 downto 0);
pgassign90(3 downto 3) <= BRAM_WEN_B(2 to 2);
pgassign90(2 downto 2) <= BRAM_WEN_B(2 to 2);
pgassign90(1 downto 1) <= BRAM_WEN_B(2 to 2);
pgassign90(0 downto 0) <= BRAM_WEN_B(2 to 2);
pgassign91(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign91(0 downto 0) <= B"0";
pgassign92(31 downto 2) <= B"000000000000000000000000000000";
pgassign92(1 downto 0) <= BRAM_Dout_A(22 to 23);
BRAM_Din_A(22 to 23) <= pgassign93(1 downto 0);
pgassign94(3 downto 3) <= BRAM_WEN_A(2 to 2);
pgassign94(2 downto 2) <= BRAM_WEN_A(2 to 2);
pgassign94(1 downto 1) <= BRAM_WEN_A(2 to 2);
pgassign94(0 downto 0) <= BRAM_WEN_A(2 to 2);
pgassign95(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign95(0 downto 0) <= B"0";
pgassign96(31 downto 2) <= B"000000000000000000000000000000";
pgassign96(1 downto 0) <= BRAM_Dout_B(22 to 23);
BRAM_Din_B(22 to 23) <= pgassign97(1 downto 0);
pgassign98(3 downto 3) <= BRAM_WEN_B(2 to 2);
pgassign98(2 downto 2) <= BRAM_WEN_B(2 to 2);
pgassign98(1 downto 1) <= BRAM_WEN_B(2 to 2);
pgassign98(0 downto 0) <= BRAM_WEN_B(2 to 2);
pgassign99(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign99(0 downto 0) <= B"0";
pgassign100(31 downto 2) <= B"000000000000000000000000000000";
pgassign100(1 downto 0) <= BRAM_Dout_A(24 to 25);
BRAM_Din_A(24 to 25) <= pgassign101(1 downto 0);
pgassign102(3 downto 3) <= BRAM_WEN_A(3 to 3);
pgassign102(2 downto 2) <= BRAM_WEN_A(3 to 3);
pgassign102(1 downto 1) <= BRAM_WEN_A(3 to 3);
pgassign102(0 downto 0) <= BRAM_WEN_A(3 to 3);
pgassign103(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign103(0 downto 0) <= B"0";
pgassign104(31 downto 2) <= B"000000000000000000000000000000";
pgassign104(1 downto 0) <= BRAM_Dout_B(24 to 25);
BRAM_Din_B(24 to 25) <= pgassign105(1 downto 0);
pgassign106(3 downto 3) <= BRAM_WEN_B(3 to 3);
pgassign106(2 downto 2) <= BRAM_WEN_B(3 to 3);
pgassign106(1 downto 1) <= BRAM_WEN_B(3 to 3);
pgassign106(0 downto 0) <= BRAM_WEN_B(3 to 3);
pgassign107(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign107(0 downto 0) <= B"0";
pgassign108(31 downto 2) <= B"000000000000000000000000000000";
pgassign108(1 downto 0) <= BRAM_Dout_A(26 to 27);
BRAM_Din_A(26 to 27) <= pgassign109(1 downto 0);
pgassign110(3 downto 3) <= BRAM_WEN_A(3 to 3);
pgassign110(2 downto 2) <= BRAM_WEN_A(3 to 3);
pgassign110(1 downto 1) <= BRAM_WEN_A(3 to 3);
pgassign110(0 downto 0) <= BRAM_WEN_A(3 to 3);
pgassign111(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign111(0 downto 0) <= B"0";
pgassign112(31 downto 2) <= B"000000000000000000000000000000";
pgassign112(1 downto 0) <= BRAM_Dout_B(26 to 27);
BRAM_Din_B(26 to 27) <= pgassign113(1 downto 0);
pgassign114(3 downto 3) <= BRAM_WEN_B(3 to 3);
pgassign114(2 downto 2) <= BRAM_WEN_B(3 to 3);
pgassign114(1 downto 1) <= BRAM_WEN_B(3 to 3);
pgassign114(0 downto 0) <= BRAM_WEN_B(3 to 3);
pgassign115(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign115(0 downto 0) <= B"0";
pgassign116(31 downto 2) <= B"000000000000000000000000000000";
pgassign116(1 downto 0) <= BRAM_Dout_A(28 to 29);
BRAM_Din_A(28 to 29) <= pgassign117(1 downto 0);
pgassign118(3 downto 3) <= BRAM_WEN_A(3 to 3);
pgassign118(2 downto 2) <= BRAM_WEN_A(3 to 3);
pgassign118(1 downto 1) <= BRAM_WEN_A(3 to 3);
pgassign118(0 downto 0) <= BRAM_WEN_A(3 to 3);
pgassign119(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign119(0 downto 0) <= B"0";
pgassign120(31 downto 2) <= B"000000000000000000000000000000";
pgassign120(1 downto 0) <= BRAM_Dout_B(28 to 29);
BRAM_Din_B(28 to 29) <= pgassign121(1 downto 0);
pgassign122(3 downto 3) <= BRAM_WEN_B(3 to 3);
pgassign122(2 downto 2) <= BRAM_WEN_B(3 to 3);
pgassign122(1 downto 1) <= BRAM_WEN_B(3 to 3);
pgassign122(0 downto 0) <= BRAM_WEN_B(3 to 3);
pgassign123(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign123(0 downto 0) <= B"0";
pgassign124(31 downto 2) <= B"000000000000000000000000000000";
pgassign124(1 downto 0) <= BRAM_Dout_A(30 to 31);
BRAM_Din_A(30 to 31) <= pgassign125(1 downto 0);
pgassign126(3 downto 3) <= BRAM_WEN_A(3 to 3);
pgassign126(2 downto 2) <= BRAM_WEN_A(3 to 3);
pgassign126(1 downto 1) <= BRAM_WEN_A(3 to 3);
pgassign126(0 downto 0) <= BRAM_WEN_A(3 to 3);
pgassign127(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign127(0 downto 0) <= B"0";
pgassign128(31 downto 2) <= B"000000000000000000000000000000";
pgassign128(1 downto 0) <= BRAM_Dout_B(30 to 31);
BRAM_Din_B(30 to 31) <= pgassign129(1 downto 0);
pgassign130(3 downto 3) <= BRAM_WEN_B(3 to 3);
pgassign130(2 downto 2) <= BRAM_WEN_B(3 to 3);
pgassign130(1 downto 1) <= BRAM_WEN_B(3 to 3);
pgassign130(0 downto 0) <= BRAM_WEN_B(3 to 3);
net_gnd0 <= '0';
net_gnd4(3 downto 0) <= B"0000";
ramb16bwer_0 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_0.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign3,
CLKA => BRAM_Clk_A,
DIA => pgassign4,
DIPA => net_gnd4,
DOA => pgassign5,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign6,
ADDRB => pgassign7,
CLKB => BRAM_Clk_B,
DIB => pgassign8,
DIPB => net_gnd4,
DOB => pgassign9,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign10
);
ramb16bwer_1 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_1.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign11,
CLKA => BRAM_Clk_A,
DIA => pgassign12,
DIPA => net_gnd4,
DOA => pgassign13,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign14,
ADDRB => pgassign15,
CLKB => BRAM_Clk_B,
DIB => pgassign16,
DIPB => net_gnd4,
DOB => pgassign17,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign18
);
ramb16bwer_2 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_2.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign19,
CLKA => BRAM_Clk_A,
DIA => pgassign20,
DIPA => net_gnd4,
DOA => pgassign21,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign22,
ADDRB => pgassign23,
CLKB => BRAM_Clk_B,
DIB => pgassign24,
DIPB => net_gnd4,
DOB => pgassign25,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign26
);
ramb16bwer_3 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_3.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign27,
CLKA => BRAM_Clk_A,
DIA => pgassign28,
DIPA => net_gnd4,
DOA => pgassign29,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign30,
ADDRB => pgassign31,
CLKB => BRAM_Clk_B,
DIB => pgassign32,
DIPB => net_gnd4,
DOB => pgassign33,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign34
);
ramb16bwer_4 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_4.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign35,
CLKA => BRAM_Clk_A,
DIA => pgassign36,
DIPA => net_gnd4,
DOA => pgassign37,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign38,
ADDRB => pgassign39,
CLKB => BRAM_Clk_B,
DIB => pgassign40,
DIPB => net_gnd4,
DOB => pgassign41,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign42
);
ramb16bwer_5 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_5.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign43,
CLKA => BRAM_Clk_A,
DIA => pgassign44,
DIPA => net_gnd4,
DOA => pgassign45,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign46,
ADDRB => pgassign47,
CLKB => BRAM_Clk_B,
DIB => pgassign48,
DIPB => net_gnd4,
DOB => pgassign49,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign50
);
ramb16bwer_6 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_6.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign51,
CLKA => BRAM_Clk_A,
DIA => pgassign52,
DIPA => net_gnd4,
DOA => pgassign53,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign54,
ADDRB => pgassign55,
CLKB => BRAM_Clk_B,
DIB => pgassign56,
DIPB => net_gnd4,
DOB => pgassign57,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign58
);
ramb16bwer_7 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_7.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign59,
CLKA => BRAM_Clk_A,
DIA => pgassign60,
DIPA => net_gnd4,
DOA => pgassign61,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign62,
ADDRB => pgassign63,
CLKB => BRAM_Clk_B,
DIB => pgassign64,
DIPB => net_gnd4,
DOB => pgassign65,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign66
);
ramb16bwer_8 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_8.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign67,
CLKA => BRAM_Clk_A,
DIA => pgassign68,
DIPA => net_gnd4,
DOA => pgassign69,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign70,
ADDRB => pgassign71,
CLKB => BRAM_Clk_B,
DIB => pgassign72,
DIPB => net_gnd4,
DOB => pgassign73,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign74
);
ramb16bwer_9 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_9.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign75,
CLKA => BRAM_Clk_A,
DIA => pgassign76,
DIPA => net_gnd4,
DOA => pgassign77,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign78,
ADDRB => pgassign79,
CLKB => BRAM_Clk_B,
DIB => pgassign80,
DIPB => net_gnd4,
DOB => pgassign81,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign82
);
ramb16bwer_10 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_10.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign83,
CLKA => BRAM_Clk_A,
DIA => pgassign84,
DIPA => net_gnd4,
DOA => pgassign85,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign86,
ADDRB => pgassign87,
CLKB => BRAM_Clk_B,
DIB => pgassign88,
DIPB => net_gnd4,
DOB => pgassign89,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign90
);
ramb16bwer_11 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_11.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign91,
CLKA => BRAM_Clk_A,
DIA => pgassign92,
DIPA => net_gnd4,
DOA => pgassign93,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign94,
ADDRB => pgassign95,
CLKB => BRAM_Clk_B,
DIB => pgassign96,
DIPB => net_gnd4,
DOB => pgassign97,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign98
);
ramb16bwer_12 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_12.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign99,
CLKA => BRAM_Clk_A,
DIA => pgassign100,
DIPA => net_gnd4,
DOA => pgassign101,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign102,
ADDRB => pgassign103,
CLKB => BRAM_Clk_B,
DIB => pgassign104,
DIPB => net_gnd4,
DOB => pgassign105,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign106
);
ramb16bwer_13 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_13.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign107,
CLKA => BRAM_Clk_A,
DIA => pgassign108,
DIPA => net_gnd4,
DOA => pgassign109,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign110,
ADDRB => pgassign111,
CLKB => BRAM_Clk_B,
DIB => pgassign112,
DIPB => net_gnd4,
DOB => pgassign113,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign114
);
ramb16bwer_14 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_14.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign115,
CLKA => BRAM_Clk_A,
DIA => pgassign116,
DIPA => net_gnd4,
DOA => pgassign117,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign118,
ADDRB => pgassign119,
CLKB => BRAM_Clk_B,
DIB => pgassign120,
DIPB => net_gnd4,
DOB => pgassign121,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign122
);
ramb16bwer_15 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_15.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign123,
CLKA => BRAM_Clk_A,
DIA => pgassign124,
DIPA => net_gnd4,
DOA => pgassign125,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign126,
ADDRB => pgassign127,
CLKB => BRAM_Clk_B,
DIB => pgassign128,
DIPB => net_gnd4,
DOB => pgassign129,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign130
);
end architecture STRUCTURE;
| mit | 5c5458366071aa845256e6e35efdba93 | 0.619096 | 3.130481 | false | false | false | false |
freecores/gpib_controller | vhdl/src/gpib/if_func_RL.vhd | 1 | 3,712 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
-- Author: Andrzej Paluch
--
-- Create Date: 01:04:57 10/03/2011
-- Design Name:
-- Module Name: if_func_RL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.utilPkg.all;
entity if_func_RL is
port(
-- device inputs
clk : in std_logic; -- clock
pon : in std_logic; -- power on
rtl : in std_logic; -- return to local
-- state inputs
ACDS : in std_logic; -- listener active state (AH)
LADS : in std_logic; -- listener addressed state (L or LE)
-- instructions
REN : in std_logic; -- remote enable
LLO : in std_logic; -- local lockout
MLA : in std_logic; -- my listen address
GTL : in std_logic; -- go to local
-- reported state
LOCS : out std_logic; -- local state
LWLS : out std_logic -- local with lockout state
);
end if_func_RL;
architecture Behavioral of if_func_RL is
-- states
type RL_STATE is (
-- local state
ST_LOCS,
-- remote state
ST_REMS,
-- local with lockout state
ST_LWLS,
-- remote with lockout state
ST_RWLS
);
-- current state
signal current_state : RL_STATE;
-- events
signal event0, event1, event2, event3, event4, event5 : boolean;
begin
-- state machine process
process(pon, clk) begin
if pon = '1' then
current_state <= ST_LOCS;
elsif rising_edge(clk) then
case current_state is
------------------
when ST_LOCS =>
if event0 then
-- no state change
elsif event1 then
current_state <= ST_REMS;
elsif event3 then
current_state <= ST_LWLS;
end if;
------------------
when ST_REMS =>
if event0 then
current_state <= ST_LOCS;
elsif event2 then
current_state <= ST_LOCS;
elsif event3 then
current_state <= ST_RWLS;
end if;
------------------
when ST_RWLS =>
if event0 then
current_state <= ST_LOCS;
elsif event5 then
current_state <= ST_LWLS;
end if;
------------------
when ST_LWLS =>
if event0 then
current_state <= ST_LOCS;
elsif event4 then
current_state <= ST_RWLS;
end if;
------------------
when others =>
current_state <= ST_LOCS;
end case;
end if;
end process;
-- events
event0 <= REN='0';
event1 <= rtl='0' and MLA='1' and ACDS='1';
event2 <=
(GTL='1' and LADS='1' and ACDS='1') or
(rtl='1' and not(LLO='1' and ACDS='1'));
event3 <= LLO='1' and ACDS='1';
event4 <= MLA='1' and ACDS='1';
event5 <= GTL='1' and LADS='1' and ACDS='1';
-- reported states
LOCS <= to_stdl(current_state = ST_LOCS);
LWLS <= to_stdl(current_state = ST_LWLS);
end Behavioral;
| gpl-3.0 | 08e13f3caa2d977acde1880cde08df81 | 0.582166 | 3.430684 | false | false | false | false |
freecores/gpib_controller | vhdl/src/gpib/if_func_DT.vhd | 1 | 2,738 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
-- Author: Andrzej Paluch
--
-- Create Date: 01:04:57 10/03/2011
-- Design Name:
-- Module Name: if_func_DT - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity if_func_DT is
port(
-- device inputs
clk : in std_logic; -- clock
-- state inputs
LADS : in std_logic; -- listener addressed state (L or LE)
ACDS : in std_logic; -- accept data state (AH)
-- instructions
GET : in std_logic; -- group execute trigger
-- local instructions
trg : out std_logic -- trigger
);
end if_func_DT;
architecture Behavioral of if_func_DT is
-- states
type DT_STATE is (
-- device trigger idle state
ST_DTIS,
-- device trigger active state
ST_DTAS
);
-- current state
signal current_state : DT_STATE;
-- predicates
signal pred1 : boolean;
signal pred2 : boolean;
begin
-- state machine process
process(clk) begin
if rising_edge(clk) then
case current_state is
------------------
when ST_DTIS =>
if pred1 then
current_state <= ST_DTAS;
end if;
------------------
when ST_DTAS =>
if pred2 then
current_state <= ST_DTIS;
end if;
------------------
when others =>
current_state <= ST_DTIS;
end case;
end if;
end process;
-- predicates
pred1 <= GET='1' and LADS='1' and ACDS='1';
pred2 <= not pred1;
-- trg generator
with current_state select
trg <=
'1' when ST_DTAS,
'0' when others;
end Behavioral;
| gpl-3.0 | 4e61f1279b48c555403149caf0b48e58 | 0.597151 | 3.933908 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | filtering_algorithm_RTL/source/vhdl/compute_squared_sums.vhd | 1 | 5,000 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: compute_squared_sums - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.filtering_algorithm_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity compute_squared_sums is
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
u_sum_sq : in coord_type_ext;
u_count : in coord_type_ext;
op1 : in coord_type_ext;
op2 : in coord_type_ext;
rdy : out std_logic;
squared_sums : out coord_type_ext
);
end compute_squared_sums;
architecture Behavioral of compute_squared_sums is
constant MUL_LAT : integer := MUL_CORE_LATENCY+1; -- +1 because of addition!!
type op_delay_type is array(0 to MUL_LAT-1) of coord_type_ext;
component madd
generic (
MUL_LATENCY : integer := 3;
A_BITWIDTH : integer := 16;
B_BITWIDTH : integer := 16;
INCLUDE_ADD : boolean := false;
C_BITWIDTH : integer := 16;
RES_BITWIDTH : integer := 16
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
a : in std_logic_vector(A_BITWIDTH-1 downto 0);
b : in std_logic_vector(B_BITWIDTH-1 downto 0);
c : in std_logic_vector(C_BITWIDTH-1 downto 0);
res : out std_logic_vector(RES_BITWIDTH-1 downto 0);
rdy : out std_logic
);
end component;
component addorsub
generic (
USE_DSP : boolean := true;
A_BITWIDTH : integer := 16;
B_BITWIDTH : integer := 16;
RES_BITWIDTH : integer := 16
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
sub : in std_logic;
a : in std_logic_vector(A_BITWIDTH-1 downto 0);
b : in std_logic_vector(B_BITWIDTH-1 downto 0);
res : out std_logic_vector(RES_BITWIDTH-1 downto 0);
rdy : out std_logic
);
end component;
signal tmp_mul_res : std_logic_vector(2*MUL_BITWIDTH+1-1 downto 0);
signal tmp_mul_rdy : std_logic;
signal tmp_op1_ext : std_logic_vector(COORD_BITWIDTH_EXT+1-1 downto 0);
signal tmp_sub_rdy : std_logic;
signal tmp_sub_res : std_logic_vector(2*MUL_BITWIDTH+2-1 downto 0);
signal tmp_final_res : coord_type_ext;
signal op_delay : op_delay_type;
begin
op_delay_proc : process(clk)
begin
if rising_edge(clk) then
op_delay(0) <= op1;
op_delay(1 to MUL_LAT-1) <= op_delay(0 to MUL_LAT-2);
end if;
end process op_delay_proc;
madd_inst : madd
generic map(
MUL_LATENCY => MUL_CORE_LATENCY,
A_BITWIDTH => MUL_BITWIDTH,
B_BITWIDTH => MUL_BITWIDTH,
INCLUDE_ADD => true,
C_BITWIDTH => COORD_BITWIDTH_EXT,
RES_BITWIDTH => 2*MUL_BITWIDTH+1
)
port map (
clk => clk,
sclr => sclr,
nd => nd,
a => saturate(u_count),
b => saturate(op2),
c => u_sum_sq,
res => tmp_mul_res,
rdy => tmp_mul_rdy
);
tmp_op1_ext <= op_delay(MUL_LAT-1) & '0';
addorsub_inst : addorsub
generic map (
USE_DSP => USE_DSP_FOR_ADD,
A_BITWIDTH => 2*MUL_BITWIDTH+1,
B_BITWIDTH => COORD_BITWIDTH_EXT+1,
RES_BITWIDTH => 2*MUL_BITWIDTH+2
)
port map (
clk => clk,
sclr => sclr,
nd => tmp_mul_rdy,
sub => '1',
a => tmp_mul_res,
b => tmp_op1_ext,
res => tmp_sub_res,
rdy => tmp_sub_rdy
);
G3: if COORD_BITWIDTH_EXT <= 2*MUL_BITWIDTH+2 generate
tmp_final_res <= tmp_sub_res(COORD_BITWIDTH_EXT-1 downto 0);
end generate G3;
G4: if COORD_BITWIDTH_EXT > 2*MUL_BITWIDTH+2 generate
tmp_final_res(2*MUL_BITWIDTH+2-1 downto 0) <= tmp_sub_res(2*MUL_BITWIDTH+2-1 downto 0);
tmp_final_res(COORD_BITWIDTH_EXT-1 downto 2*MUL_BITWIDTH+2) <= (others => tmp_sub_res(2*MUL_BITWIDTH+2-1));
end generate G4;
rdy <= tmp_sub_rdy;
squared_sums <= tmp_final_res;
end Behavioral;
| bsd-3-clause | b44fca12ceae8769bd6b9971504d1394 | 0.5242 | 3.770739 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | filtering_algorithm_RTL/source/vhdl/node_stack_mgmt.vhd | 1 | 4,887 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: node_stack_mgmt - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.filtering_algorithm_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity node_stack_mgmt is
port (
clk : in STD_LOGIC;
sclr : in STD_LOGIC;
push : in std_logic;
pop : in std_logic;
node_addr_in : in node_address_type;
node_addr_out : out node_address_type;
empty : out std_logic;
valid : out std_logic
);
end node_stack_mgmt;
architecture Behavioral of node_stack_mgmt is
constant MEM_LAT : integer := 2;
constant STACK_POINTER_BITWIDTH : integer := integer(ceil(log2(real(STACK_SIZE))));
--type stack_pointer_delay_line_type is array(0 to MEM_LAT-1) of unsigned(STACK_POINTER_BITWIDTH-1 downto 0);
component node_stack_memory
port (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(STACK_POINTER_BITWIDTH-1 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(NODE_POINTER_BITWIDTH-1 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(STACK_POINTER_BITWIDTH-1 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(NODE_POINTER_BITWIDTH-1 DOWNTO 0)
);
end component;
signal stack_pointer : unsigned(STACK_POINTER_BITWIDTH-1 downto 0);
signal pop_reg : std_logic;
signal tmp_stack_addr_rd : unsigned(STACK_POINTER_BITWIDTH-1 downto 0);
signal stack_addr_rd_reg : unsigned(STACK_POINTER_BITWIDTH-1 downto 0);
signal tmp_node_stack_dout : std_logic_vector(NODE_POINTER_BITWIDTH-1 downto 0);
signal tmp_empty : std_logic;
signal rdy_delay_line : std_logic_vector(0 to MEM_LAT-1);
signal emp_delay_line : std_logic_vector(0 to MEM_LAT-1);
--signal stack_pointer_delay_line : stack_pointer_delay_line_type;
begin
update_stack_ptr_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
stack_pointer <= (others => '0');
else
if push = '1' AND pop = '0' then
stack_pointer <= stack_pointer+1;
elsif push = '0' AND pop = '1' then
stack_pointer <= stack_pointer-1;
elsif push = '1' AND pop = '1' then
stack_pointer <= stack_pointer; -- add 1, remove 1
end if;
end if;
end if;
end process update_stack_ptr_proc;
tmp_stack_addr_rd <= stack_pointer-1;
tmp_empty <= '1' WHEN stack_pointer = 0 ELSE '0';
input_reg_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
pop_reg <= '0';
else
pop_reg <= pop;
stack_addr_rd_reg <= tmp_stack_addr_rd;
end if;
end if;
end process input_reg_proc;
node_stack_memory_inst : node_stack_memory
port map (
clka => clk,
wea(0) => push,
addra => std_logic_vector(stack_pointer),
dina => std_logic_vector(node_addr_in),
clkb => clk,
addrb => std_logic_vector(tmp_stack_addr_rd),--std_logic_vector(stack_addr_rd_reg),
doutb => tmp_node_stack_dout
);
delay_line_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
rdy_delay_line <= (others => '0');
--emp_delay_line <= (others => '0');
else
rdy_delay_line(0) <= pop;--pop_reg;
rdy_delay_line(1 to MEM_LAT-1) <= rdy_delay_line(0 to MEM_LAT-2);
--emp_delay_line(0) <= tmp_empty;
--emp_delay_line(1 to MEM_LAT-1) <= emp_delay_line(0 to MEM_LAT-2);
end if;
end if;
end process delay_line_proc;
node_addr_out <= tmp_node_stack_dout;
valid <= rdy_delay_line(MEM_LAT-1); -- AND NOT(emp_delay_line(MEM_LAT-1));
empty <= tmp_empty;--emp_delay_line(MEM_LAT-1);
end Behavioral;
| bsd-3-clause | 759de24a82c97e3b113a19e2057972a8 | 0.536321 | 3.887828 | false | false | false | false |
mithro/HDMI2USB | ipcore_dir/rawUVCfifo/example_design/rawUVCfifo_exdes.vhd | 3 | 5,723 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rawUVCfifo_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity rawUVCfifo_exdes is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(24-1 DOWNTO 0);
DOUT : OUT std_logic_vector(24-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end rawUVCfifo_exdes;
architecture xilinx of rawUVCfifo_exdes is
signal wr_clk_i : std_logic;
signal rd_clk_i : std_logic;
component rawUVCfifo is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(24-1 DOWNTO 0);
DOUT : OUT std_logic_vector(24-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
exdes_inst : rawUVCfifo
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
VALID => valid,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| bsd-2-clause | f2344c05fb5c055b73543996be3cc50a | 0.502359 | 4.925129 | false | false | false | false |
Nooxet/embedded_bruteforce | brutus_system/pcores/ready4hood_v1_00_a/hdl/vhdl/ready4hood.vhd | 1 | 3,091 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ready4hood is
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
FSL_Clk : in std_logic;
FSL_Rst : in std_logic;
FSL_S_Clk : in std_logic;
FSL_S_Read : out std_logic;
FSL_S_Data : in std_logic_vector(0 to 31);
FSL_S_Control : in std_logic;
FSL_S_Exists : in std_logic;
FSL_M_Clk : in std_logic;
FSL_M_Write : out std_logic;
FSL_M_Data : out std_logic_vector(0 to 31);
FSL_M_Control : out std_logic;
FSL_M_Full : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of FSL_Clk : signal is "Clk";
attribute SIGIS of FSL_S_Clk : signal is "Clk";
attribute SIGIS of FSL_M_Clk : signal is "Clk";
end ready4hood;
architecture EXAMPLE of ready4hood is
-- Total number of input data.
constant NUMBER_OF_INPUT_WORDS : natural := 4;
-- Total number of output data
constant NUMBER_OF_OUTPUT_WORDS : natural := 1;
type STATE_TYPE is (Idle, Read_Inputs, Write_Outputs);
signal state : STATE_TYPE;
-- Accumulator to hold sum of inputs read at any point in time
signal sum : std_logic_vector(0 to 31);
-- Counters to store the number inputs read & outputs written
signal nr_of_reads : natural range 0 to NUMBER_OF_INPUT_WORDS - 1;
signal nr_of_writes : natural range 0 to NUMBER_OF_OUTPUT_WORDS - 1;
begin
FSL_S_Read <= FSL_S_Exists when state = Read_Inputs else '0';
FSL_M_Write <= not FSL_M_Full when state = Write_Outputs else '0';
FSL_M_Data <= sum;
The_SW_accelerator : process (FSL_Clk) is
begin -- process The_SW_accelerator
if FSL_Clk'event and FSL_Clk = '1' then -- Rising clock edge
if FSL_Rst = '1' then -- Synchronous reset (active high)
state <= Idle;
nr_of_reads <= 0;
nr_of_writes <= 0;
sum <= (others => '0');
else
case state is
when Idle =>
if (FSL_S_Exists = '1') then
state <= Read_Inputs;
nr_of_reads <= NUMBER_OF_INPUT_WORDS - 1;
sum <= (others => '0');
end if;
when Read_Inputs =>
if (FSL_S_Exists = '1') then
-- Coprocessor function (Adding) happens here
sum <= std_logic_vector(unsigned(sum) + unsigned(FSL_S_Data));
if (nr_of_reads = 0) then
state <= Write_Outputs;
nr_of_writes <= NUMBER_OF_OUTPUT_WORDS - 1;
else
nr_of_reads <= nr_of_reads - 1;
end if;
end if;
when Write_Outputs =>
if (nr_of_writes = 0) then
state <= Idle;
else
if (FSL_M_Full = '0') then
nr_of_writes <= nr_of_writes - 1;
end if;
end if;
end case;
end if;
end if;
end process The_SW_accelerator;
end architecture EXAMPLE;
| mit | 37c28060c432fc462974b295b2df0dd3 | 0.552572 | 3.404185 | false | false | false | false |
freecores/gpib_controller | vhdl/src/gpib_helper/GpibSynchronizer.vhd | 1 | 2,261 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: GpibSynchronizer
-- Date:2012-02-06
-- Author: Andrzej Paluch
--
-- Description ${cursor}
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity GpibSynchronizer is
port (
-- clk
clk : std_logic;
-- DIO
DI : in std_logic_vector (7 downto 0);
DO : out std_logic_vector (7 downto 0);
-- attention
ATN_in : in std_logic;
ATN_out : out std_logic;
-- data valid
DAV_in : in std_logic;
DAV_out : out std_logic;
-- not ready for data
NRFD_in : in std_logic;
NRFD_out : out std_logic;
-- no data accepted
NDAC_in : in std_logic;
NDAC_out : out std_logic;
-- end or identify
EOI_in : in std_logic;
EOI_out : out std_logic;
-- service request
SRQ_in : in std_logic;
SRQ_out : out std_logic;
-- interface clear
IFC_in : in std_logic;
IFC_out : out std_logic;
-- remote enable
REN_in : in std_logic;
REN_out : out std_logic
);
end GpibSynchronizer;
architecture arch of GpibSynchronizer is
begin
process(clk) begin
if rising_edge(clk) then
DO <= DI;
ATN_out <= ATN_in;
DAV_out <= DAV_in;
NRFD_out <= NRFD_in;
NDAC_out <= NDAC_in;
EOI_out <= EOI_in;
SRQ_out <= SRQ_in;
IFC_out <= IFC_in;
REN_out <= REN_in;
end if;
end process;
end arch;
| gpl-3.0 | fa09eb8b797082f4097e78804e5a6e97 | 0.592658 | 3.49459 | false | false | false | false |
autosub-team/autosub | src/tests/testTasksVHDL/testsubmissions/crc/crc_beh.vhdl | 2 | 2,789 | library IEEE;
use IEEE.std_logic_1164.all;
architecture behavior of crc is
constant msg_len :integer := 21;
constant gen_degree : integer := 8;
type crc_state is
(
PREPARE,
CALC,
FINISH,
IDLE
);
signal state,state_next : crc_state;
signal EN_next, RST_next,CRC_VALID_next: std_logic;
signal bit_nr,bit_nr_next:integer;
signal DATA_IN_next: std_logic;
component fsr is
port
(
EN : in std_logic;
RST : in std_logic; -- rising edge of RST should reset the content of the shift register to all 0
CLK : in std_logic; -- shift and feedback operations should be done on rising edge of CLK
DATA_IN : in std_logic; -- the bit which shall be shifted in
DATA : out std_logic_vector(gen_degree-1 downto 0) -- the current content of the feedback shift register
);
end component;
signal EN,RST,CLK_UUT,DATA_In : std_logic;
signal DATA: std_logic_vector(gen_degree-1 downto 0);
begin
CLK_UUT<=CLK;
UUT:fsr
port map
(
EN=>EN,
RST=>RST,
CLK=>CLK_UUT,
DATA_IN=>DATA_IN,
DATA=>DATA
);
--Next State Logic and communication with FSR----
nextState : process(state,bit_nr)
constant top_bit :integer:= msg_len-1;
begin
case state is
when PREPARE =>
CRC_VALID_next<='0';
EN_next<='1';
RST_next<='1';
bit_nr_next<=top_bit;
state_next<=CALC;
when CALC =>
RST_next<='0';
DATA_IN_next<=MSG(bit_nr);
if(bit_nr=0) then
state_next<=FINISH;
else
state_next<=CALC;
bit_nr_next<=bit_nr-1;
end if;
when FINISH =>
EN_next<='0';
CRC_VALID_next<='1';
state_next<=IDLE;
when IDLE =>
CRC <= DATA;
state_next <= IDLE;
when others=>
null;
end case;
end process nextState;
--Sync and Reset Logic--
sync_proc : process(clk, NEW_MSG)
begin
if rising_edge(NEW_MSG) then
state <= PREPARE;
elsif(rising_edge(CLK)) then
state <= state_next;
EN <= EN_next;
RST <= RST_next;
CRC_VALID <= CRC_VALID_next;
bit_nr <=bit_nr_next;
DATA_in<=DATA_IN_next;
end if;
end process sync_proc;
end behavior;
| gpl-2.0 | 2abfd4d9b3ba441837344eeecabba5ee | 0.468627 | 4.23217 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | lloyds_algorithm_RTL/source/vhdl/centre_positions_memory_top.vhd | 1 | 2,816 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: centre_positions_memory_top - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.lloyds_algorithm_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity centre_positions_memory_top is
port (
clk : in std_logic;
wea : in std_logic_vector(0 to PARALLEL_UNITS-1);
addra : in par_centre_index_type;
dina : in par_data_type;
addrb : in par_centre_index_type;
doutb : out par_data_type
);
end centre_positions_memory_top;
architecture Behavioral of centre_positions_memory_top is
type p_addr_type is array(0 to PARALLEL_UNITS-1) of std_logic_vector(INDEX_BITWIDTH-1 downto 0);
type p_data_type is array(0 to PARALLEL_UNITS-1) of std_logic_vector(D*COORD_BITWIDTH-1 downto 0);
component centre_positions_memory
port (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(INDEX_BITWIDTH-1 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(D*COORD_BITWIDTH-1 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(INDEX_BITWIDTH-1 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(D*COORD_BITWIDTH-1 DOWNTO 0)
);
end component;
signal p_addra : p_addr_type;
signal p_addrb : p_addr_type;
signal p_dina : p_data_type;
signal p_doutb : p_data_type;
begin
-- fixme: this memory parallelism could also be achieved by memory segmentation which would be muhch better... to be done
G_PAR_0: for I in 0 to PARALLEL_UNITS-1 generate
p_addra(I) <= std_logic_vector(addra(I));
p_addrb(I) <= std_logic_vector(addrb(I));
p_dina(I) <= datapoint_2_stdlogic(dina(I));
centre_positions_memory_inst : centre_positions_memory
port map(
clka => clk,
wea(0) => wea(I),
addra => p_addra(I),
dina => p_dina(I),
clkb => clk,
addrb => p_addrb(I),
doutb => p_doutb(I)
);
doutb(I) <= stdlogic_2_datapoint(p_doutb(I));
end generate G_PAR_0;
end Behavioral;
| bsd-3-clause | 4bdb3379d0fe8e27c5ab5c32d8a619b8 | 0.57919 | 3.889503 | false | false | false | false |
Nooxet/embedded_bruteforce | brutus_system/hdl/system_dip_switches_8bits_wrapper.vhd | 1 | 5,051 | -------------------------------------------------------------------------------
-- system_dip_switches_8bits_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library axi_gpio_v1_01_b;
use axi_gpio_v1_01_b.all;
entity system_dip_switches_8bits_wrapper is
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(8 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(8 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
IP2INTC_Irpt : out std_logic;
GPIO_IO_I : in std_logic_vector(7 downto 0);
GPIO_IO_O : out std_logic_vector(7 downto 0);
GPIO_IO_T : out std_logic_vector(7 downto 0);
GPIO2_IO_I : in std_logic_vector(31 downto 0);
GPIO2_IO_O : out std_logic_vector(31 downto 0);
GPIO2_IO_T : out std_logic_vector(31 downto 0)
);
attribute x_core_info : STRING;
attribute x_core_info of system_dip_switches_8bits_wrapper : entity is "axi_gpio_v1_01_b";
end system_dip_switches_8bits_wrapper;
architecture STRUCTURE of system_dip_switches_8bits_wrapper is
component axi_gpio is
generic (
C_FAMILY : STRING;
C_INSTANCE : STRING;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : std_logic_vector(31 downto 0);
C_TRI_DEFAULT : std_logic_vector(31 downto 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : std_logic_vector(31 downto 0);
C_TRI_DEFAULT_2 : std_logic_vector(31 downto 0)
);
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(8 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_WSTRB : in std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(8 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
IP2INTC_Irpt : out std_logic;
GPIO_IO_I : in std_logic_vector((C_GPIO_WIDTH-1) downto 0);
GPIO_IO_O : out std_logic_vector((C_GPIO_WIDTH-1) downto 0);
GPIO_IO_T : out std_logic_vector((C_GPIO_WIDTH-1) downto 0);
GPIO2_IO_I : in std_logic_vector((C_GPIO2_WIDTH-1) downto 0);
GPIO2_IO_O : out std_logic_vector((C_GPIO2_WIDTH-1) downto 0);
GPIO2_IO_T : out std_logic_vector((C_GPIO2_WIDTH-1) downto 0)
);
end component;
begin
DIP_Switches_8Bits : axi_gpio
generic map (
C_FAMILY => "spartan6",
C_INSTANCE => "DIP_Switches_8Bits",
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 8,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 1,
C_ALL_INPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"ffffffff",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"ffffffff"
)
port map (
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
IP2INTC_Irpt => IP2INTC_Irpt,
GPIO_IO_I => GPIO_IO_I,
GPIO_IO_O => GPIO_IO_O,
GPIO_IO_T => GPIO_IO_T,
GPIO2_IO_I => GPIO2_IO_I,
GPIO2_IO_O => GPIO2_IO_O,
GPIO2_IO_T => GPIO2_IO_T
);
end architecture STRUCTURE;
| mit | eac8ac7f63274408ff8b1f8e6007f678 | 0.588992 | 2.928116 | false | false | false | false |
tsotnep/vhdl_soc_audio_mixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/superip_v1_00_a/hdl/vhdl/Filter_Top_Level.vhd | 1 | 8,506 | ---------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:51:05 05/05/2015
-- Design Name:
-- Module Name: Filter_Top_Level - RTL
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Filter_Top_Level is
Port(slv_reg0 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg1 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg2 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg3 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg4 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg5 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg6 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg7 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg8 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg9 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg10 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg11 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg12 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg13 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg14 : in STD_LOGIC_VECTOR(31 downto 0);
CLK_48 : in std_logic;
RST : in std_logic;
SAMPLE_TRIG : in std_logic;
sample_trigger_en : in std_logic;
HP_SW : in std_logic;
BP_SW : in std_logic;
LP_SW : in std_logic;
AUDIO_IN_L : in std_logic_vector(23 downto 0);
AUDIO_IN_R : in std_logic_vector(23 downto 0);
AUDIO_OUT_L : out std_logic_vector(23 downto 0);
AUDIO_OUT_R : out std_logic_vector(23 downto 0);
FILTER_DONE : out std_logic
-- clk : in STD_LOGIC;
-- rst : in STD_LOGIC;
-- sample_trig : in STD_LOGIC;
-- Audio_in : in STD_LOGIC_VECTOR (23 downto 0);
-- filter_done : in STD_LOGIC;
-- Audio_out : in STD_LOGIC_VECTOR (23 downto 0)
);
end Filter_Top_Level;
architecture RTL of Filter_Top_Level is
Component IIR_Biquad_II_v3 is
Port(
Coef_b0 : std_logic_vector(31 downto 0);
Coef_b1 : std_logic_vector(31 downto 0);
Coef_b2 : std_logic_vector(31 downto 0);
Coef_a1 : std_logic_vector(31 downto 0);
Coef_a2 : std_logic_vector(31 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
sample_trig : in STD_LOGIC;
X_in : in STD_LOGIC_VECTOR(23 downto 0);
filter_done : out STD_LOGIC;
Y_out : out STD_LOGIC_VECTOR(23 downto 0)
);
end Component;
signal IIR_LP_Done_R, IIR_LP_Done_L, IIR_BP_Done_R, IIR_BP_Done_L, IIR_HP_Done_R, IIR_HP_Done_L : std_logic;
signal AUDIO_OUT_TRUNC_L, AUDIO_OUT_TRUNC_R, IIR_LP_Y_Out_R, IIR_LP_Y_Out_L, IIR_BP_Y_Out_R, IIR_BP_Y_Out_L, IIR_HP_Y_Out_R, IIR_HP_Y_Out_L : std_logic_vector(23 downto 0);
signal sample_trigger_safe : STD_LOGIC := '0';
signal val : std_logic_vector(2 downto 0);
begin
sample_trigger_safe <= SAMPLE_TRIG or (not sample_trigger_en);
val <= HP_SW & BP_SW & LP_SW;
--USER logic implementation added here
---- connect all the "filter done" with an AND gate to the user_logic top level entity.
FILTER_DONE <= IIR_LP_Done_R and IIR_LP_Done_L and IIR_BP_Done_R and IIR_BP_Done_L and IIR_HP_Done_R and IIR_HP_Done_L;
AUDIO_OUT_L <= AUDIO_OUT_TRUNC_L; -- & X"00";
AUDIO_OUT_R <= AUDIO_OUT_TRUNC_R; -- & X"00";
---this process controls each individual filter and the final output of the filter.
MUX_filters: process(IIR_BP_Y_Out_L, IIR_BP_Y_Out_R, IIR_HP_Y_Out_L, IIR_HP_Y_Out_R, IIR_LP_Y_Out_L, IIR_LP_Y_Out_R, val, RST)
begin
if rst = '1' then
AUDIO_OUT_TRUNC_L <= (others => '0'); --IIR_LP_Y_Out_L + IIR_BP_Y_Out_L + IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= (others => '0'); --IIR_LP_Y_Out_R + IIR_BP_Y_Out_R + IIR_HP_Y_Out_R;
else
case VAL is -- i reversed case decodings, so instead of 111 now its 000, and etc. so now, 0 means enable, 1 means disable
when "111" =>
AUDIO_OUT_TRUNC_L <= (others => '0'); --IIR_LP_Y_Out_L + IIR_BP_Y_Out_L + IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= (others => '0'); --IIR_LP_Y_Out_R + IIR_BP_Y_Out_R + IIR_HP_Y_Out_R;
when "110" =>
AUDIO_OUT_TRUNC_L <= IIR_LP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_LP_Y_Out_R;
when "101" =>
AUDIO_OUT_TRUNC_L <= IIR_BP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_BP_Y_Out_R;
when "100" =>
AUDIO_OUT_TRUNC_L <= IIR_LP_Y_Out_L + IIR_BP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_LP_Y_Out_R + IIR_BP_Y_Out_R;
when "011" =>
AUDIO_OUT_TRUNC_L <= IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_HP_Y_Out_R;
when "010" =>
AUDIO_OUT_TRUNC_L <= IIR_LP_Y_Out_L + IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_LP_Y_Out_R + IIR_HP_Y_Out_R;
when "001" =>
AUDIO_OUT_TRUNC_L <= IIR_HP_Y_Out_L + IIR_BP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_HP_Y_Out_R + IIR_BP_Y_Out_R;
when "000" =>
AUDIO_OUT_TRUNC_L <= IIR_LP_Y_Out_L + IIR_BP_Y_Out_L + IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_LP_Y_Out_R + IIR_BP_Y_Out_R + IIR_HP_Y_Out_R;
when others =>
AUDIO_OUT_TRUNC_L <= (others => '0'); --IIR_LP_Y_Out_L + IIR_BP_Y_Out_L + IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= (others => '0'); --IIR_LP_Y_Out_R + IIR_BP_Y_Out_R + IIR_HP_Y_Out_R;
end case;
end if;
end process;
IIR_LP_R : IIR_Biquad_II_v3
Port map(
Coef_b0 => slv_reg0,
Coef_b1 => slv_reg1,
Coef_b2 => slv_reg2,
Coef_a1 => slv_reg3,
Coef_a2 => slv_reg4,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_R(23 downto 0),
filter_done => IIR_LP_Done_R,
Y_out => IIR_LP_Y_Out_R
);
IIR_LP_L : IIR_Biquad_II_v3
Port map(
Coef_b0 => slv_reg0,
Coef_b1 => slv_reg1,
Coef_b2 => slv_reg2,
Coef_a1 => slv_reg3,
Coef_a2 => slv_reg4,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_L(23 downto 0), --X_in_truncated_L,
filter_done => IIR_LP_Done_L,
Y_out => IIR_LP_Y_Out_L
);
IIR_BP_R : IIR_Biquad_II_v3 --(20 - 20000)
Port map(
Coef_b0 => slv_reg5,
Coef_b1 => slv_reg6,
Coef_b2 => slv_reg7,
Coef_a1 => slv_reg8,
Coef_a2 => slv_reg9,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_R(23 downto 0), --X_in_truncated_R,
filter_done => IIR_BP_Done_R,
Y_out => IIR_BP_Y_Out_R
);
IIR_BP_L : IIR_Biquad_II_v3 --(20 - 20000)
Port map(
Coef_b0 => slv_reg5,
Coef_b1 => slv_reg6,
Coef_b2 => slv_reg7,
Coef_a1 => slv_reg8,
Coef_a2 => slv_reg9,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_L(23 downto 0), --X_in_truncated_L,
filter_done => IIR_BP_Done_L,
Y_out => IIR_BP_Y_Out_L
);
IIR_HP_R : IIR_Biquad_II_v3
Port map(
Coef_b0 => slv_reg10,
Coef_b1 => slv_reg11,
Coef_b2 => slv_reg12,
Coef_a1 => slv_reg13,
Coef_a2 => slv_reg14,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_R(23 downto 0), --X_in_truncated_R,
filter_done => IIR_HP_Done_R,
Y_out => IIR_HP_Y_Out_R
);
IIR_HP_L : IIR_Biquad_II_v3
Port map(
Coef_b0 => slv_reg10,
Coef_b1 => slv_reg11,
Coef_b2 => slv_reg12,
Coef_a1 => slv_reg13,
Coef_a2 => slv_reg14,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_L(23 downto 0), --X_in_truncated_L,
filter_done => IIR_HP_Done_L,
Y_out => IIR_HP_Y_Out_L
);
end RTL;
| mit | c3fb7a35071d719c5635563fb58b70bb | 0.547143 | 2.598045 | false | false | false | false |
esar/hdmilight-v2 | fpga/avr/opc_fetch.vhd | 1 | 7,280 | -------------------------------------------------------------------------------
--
-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
--
-- This code is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file named COPYING).
-- If not, see http://www.gnu.org/licenses/.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Module Name: opc_fetch - Behavioral
-- Create Date: 13:00:44 10/30/2009
-- Description: the opcode fetch stage of a CPU.
--
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_ARITH.ALL;
use IEEE.std_logic_UNSIGNED.ALL;
entity opc_fetch is
port ( I_CLK : in std_logic;
I_CE : in std_logic;
I_CLR : in std_logic;
I_INTVEC : in std_logic_vector( 5 downto 0);
I_LOAD_PC : in std_logic;
I_NEW_PC : in std_logic_vector(15 downto 0);
I_PM_ADR : in std_logic_vector(15 downto 0);
I_SKIP : in std_logic;
Q_OPC : out std_logic_vector(31 downto 0);
Q_PC : out std_logic_vector(15 downto 0);
Q_PM_DOUT : out std_logic_vector( 7 downto 0);
Q_T0 : out std_logic);
end opc_fetch;
architecture Behavioral of opc_fetch is
component prog_mem
port ( I_CLK : in std_logic;
I_CE : in std_logic;
I_WAIT : in std_logic;
I_PC : in std_logic_vector (15 downto 0);
I_PM_ADR : in std_logic_vector (15 downto 0);
Q_OPC : out std_logic_vector (31 downto 0);
Q_PC : out std_logic_vector (15 downto 0);
Q_PM_DOUT : out std_logic_vector ( 7 downto 0));
end component;
signal P_OPC : std_logic_vector(31 downto 0);
signal P_PC : std_logic_vector(15 downto 0);
signal L_INVALIDATE : std_logic;
signal L_LONG_OP : std_logic;
signal L_NEXT_PC : std_logic_vector(15 downto 0);
signal L_OPC_1_0123 : std_logic;
signal L_OPC_8A_014589CD: std_logic;
signal L_OPC_9_01 : std_logic;
signal L_OPC_9_5_01_8 : std_logic;
signal L_OPC_9_5_CD_8 : std_logic;
signal L_OPC_9_9B : std_logic;
signal L_OPC_F_CDEF : std_logic;
signal L_PC : std_logic_vector(15 downto 0);
signal L_T0 : std_logic;
signal L_WAIT : std_logic;
begin
pmem : prog_mem
port map( I_CLK => I_CLK,
I_CE => I_CE,
I_WAIT => L_WAIT,
I_PC => L_NEXT_PC,
I_PM_ADR => I_PM_ADR,
Q_OPC => P_OPC,
Q_PC => P_PC,
Q_PM_DOUT => Q_PM_DOUT);
lpc: process(I_CE, I_CLK)
begin
if (I_CE = '1' and rising_edge(I_CLK)) then
L_PC <= L_NEXT_PC;
L_T0 <= not L_WAIT;
end if;
end process;
L_NEXT_PC <= X"0000" when (I_CLR = '1')
else L_PC when (L_WAIT = '1')
else I_NEW_PC when (I_LOAD_PC = '1')
else L_PC + X"0002" when (L_LONG_OP = '1')
else L_PC + X"0001";
-- Two word opcodes:
--
-- 9 3210
-- 1001 000d dddd 0000 kkkk kkkk kkkk kkkk - LDS
-- 1001 001d dddd 0000 kkkk kkkk kkkk kkkk - SDS
-- 1001 010k kkkk 110k kkkk kkkk kkkk kkkk - JMP
-- 1001 010k kkkk 111k kkkk kkkk kkkk kkkk - CALL
--
L_LONG_OP <= '1' when (((P_OPC(15 downto 9) = "1001010") and
(P_OPC( 3 downto 2) = "11")) -- JMP, CALL
or ((P_OPC(15 downto 10) = "100100") and
(P_OPC( 3 downto 0) = "0000"))) -- LDS, STS
else '0';
----------------------------------
-- Two cycle opcodes... --
----------------------------------
-------------------------------------------------
-- 0001 00rd dddd rrrr - CPSE
--
L_OPC_1_0123 <= '1' when (P_OPC(15 downto 10) = "000100" )
else '0';
-------------------------------------------------
-- 10q0 qq0d dddd 1qqq - LDD (Y + q)
-- 10q0 qq0d dddd 0qqq - LDD (Z + q)
--
L_OPC_8A_014589CD <= '1' when ((P_OPC(15 downto 14) = "10" )
and (P_OPC(12) = '0')
and (P_OPC( 9) = '0'))
else '0';
-------------------------------------------------
-- 1001 000d dddd .... - LDS, LD, LPM (ii/iii), ELPM, POP
--
L_OPC_9_01 <= '1' when ( P_OPC(15 downto 9) = "1001000")
else '0';
-------------------------------------------------
-- 1001 0101 0000 1000 - RET
-- 1001 0101 0001 1000 - RETI
--
L_OPC_9_5_01_8 <= '1' when ((P_OPC(15 downto 5) = "10010101000")
and (P_OPC( 3 downto 0) = "1000"))
else '0';
-------------------------------------------------
-- 1001 0101 1100 1000 - LPM (i)
-- 1001 0101 1101 1000 - ELPM
--
L_OPC_9_5_CD_8 <= '1' when ((P_OPC(15 downto 5) = "10010101110")
and (P_OPC( 3 downto 0) = "1000"))
else '0';
-------------------------------------------------
-- 1001 1001 AAAA Abbb - SBIC
-- 1001 1011 AAAA Abbb - SBIS
--
L_OPC_9_9B <= '1' when ((P_OPC(15 downto 10) = "100110")
and (P_OPC(8) = '1'))
else '0';
-------------------------------------------------
-- 1111 110r rrrr 0bbb - SBRC
-- 1111 111r rrrr 0bbb - SBRS
--
L_OPC_F_CDEF <= '1' when ( P_OPC(15 downto 10) = "111111")
else '0';
L_WAIT <= L_T0 and (not L_INVALIDATE)
and (not I_INTVEC(5))
and (L_OPC_1_0123 or -- CPSE
L_OPC_8A_014589CD or -- LDD
L_OPC_9_01 or -- LDS, LD, LPM, POP
L_OPC_9_5_01_8 or -- RET, RETI
L_OPC_9_5_CD_8 or -- LPM, ELPM
L_OPC_9_9B or -- SBIC, SBIS
L_OPC_F_CDEF); -- SBRC, SBRS
L_INVALIDATE <= I_CLR or I_SKIP;
Q_OPC <= X"00000000" when (L_INVALIDATE = '1')
else P_OPC when (I_INTVEC(5) = '0')
else (X"000000" & "00" & I_INTVEC); -- "interrupt opcode"
Q_PC <= P_PC;
Q_T0 <= L_T0;
end Behavioral;
| gpl-2.0 | 72130da20bf27f5bc44ee171b7aeeb3f | 0.425549 | 3.593287 | false | false | false | false |
tomoasleep/vhdl_test_script | examples/state_machine_lib.vhd | 1 | 902 | library ieee;
use ieee.std_logic_1164.all;
package const_state is
constant STATE_A : std_logic_vector(2 downto 0) := "000";
constant STATE_B : std_logic_vector(2 downto 0) := "001";
constant STATE_C : std_logic_vector(2 downto 0) := "010";
constant STATE_D : std_logic_vector(2 downto 0) := "011";
end const_state;
library ieee;
use ieee.std_logic_1164.all;
package const_order is
constant ORDER_A : std_logic := '0';
constant ORDER_B : std_logic := '1';
end const_order;
library ieee;
use ieee.std_logic_1164.all;
package const_state2 is
subtype state_type is std_logic_vector(2 downto 0);
constant STATE_E : state_type := "000";
constant STATE_F : state_type := "001";
constant STATE_G : state_type := "010";
constant STATE_H : state_type := "011";
end const_state2;
| mit | 4ac190712e28a7fd5428bcfd15df3f34 | 0.601996 | 3.268116 | false | false | false | false |
myhdl/myhdl | example/manual/FramerCtrl.vhd | 7 | 2,127 | -- File: FramerCtrl.vhd
-- Generated by MyHDL 1.0dev
-- Date: Mon Feb 15 21:03:52 2016
package pck_FramerCtrl is
attribute enum_encoding: string;
type t_enum_t_State_1 is (
SEARCH,
CONFIRM,
SYNC
);
attribute enum_encoding of t_enum_t_State_1: type is "001 010 100";
end package pck_FramerCtrl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_10.all;
use work.pck_FramerCtrl.all;
entity FramerCtrl is
port (
SOF: out std_logic;
state: inout t_enum_t_State_1;
syncFlag: in std_logic;
clk: in std_logic;
reset_n: in std_logic
);
end entity FramerCtrl;
-- Framing control FSM.
--
-- SOF -- start-of-frame output bit
-- state -- FramerState output
-- syncFlag -- sync pattern found indication input
-- clk -- clock input
-- reset_n -- active low reset
architecture MyHDL of FramerCtrl is
signal index: unsigned(7 downto 0);
begin
FRAMERCTRL_FSM: process (clk, reset_n) is
begin
if (reset_n = '0') then
SOF <= '0';
index <= to_unsigned(0, 8);
state <= SEARCH;
elsif rising_edge(clk) then
index <= ((index + 1) mod 8);
SOF <= '0';
case state is
when SEARCH =>
index <= to_unsigned(1, 8);
if bool(syncFlag) then
state <= CONFIRM;
end if;
when CONFIRM =>
if (index = 0) then
if bool(syncFlag) then
state <= SYNC;
else
state <= SEARCH;
end if;
end if;
when SYNC =>
if (index = 0) then
if (not bool(syncFlag)) then
state <= SEARCH;
end if;
end if;
SOF <= stdl(signed(resize(index, 9)) = (8 - 1));
when others =>
assert False report "End of Simulation" severity Failure;
end case;
end if;
end process FRAMERCTRL_FSM;
end architecture MyHDL;
| lgpl-2.1 | 9b5be287cd4b695ae2312dc0b229bd9a | 0.527033 | 3.818671 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | filtering_algorithm_RTL/source/vhdl/dot_product.vhd | 1 | 10,488 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: dot_product - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.all;
use ieee.math_real.all;
use work.filtering_algorithm_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dot_product is
generic (
SCALE_MUL_RESULT : integer := 0
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
point_1 : in data_type_ext;
point_2 : in data_type_ext;
result : out coord_type_ext;
rdy : out std_logic
);
end dot_product;
architecture Behavioral of dot_product is
constant LAYERS_TREE_ADDER : integer := integer(ceil(log2(real(D))));
type mul_res_array_type is array(0 to D-1) of std_logic_vector(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1-1 downto 0);
--type tree_adder_res_array_type is array(0 to LAYERS_TREE_ADDER-1, 0 to D/2-1) of std_logic_vector(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER-1 downto 0);
component addorsub
generic (
USE_DSP : boolean := true;
A_BITWIDTH : integer := 16;
B_BITWIDTH : integer := 16;
RES_BITWIDTH : integer := 16
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
sub : in std_logic;
a : in std_logic_vector(A_BITWIDTH-1 downto 0);
b : in std_logic_vector(B_BITWIDTH-1 downto 0);
res : out std_logic_vector(RES_BITWIDTH-1 downto 0);
rdy : out std_logic
);
end component;
component madd
generic (
MUL_LATENCY : integer := 3;
A_BITWIDTH : integer := 16;
B_BITWIDTH : integer := 16;
INCLUDE_ADD : boolean := false;
C_BITWIDTH : integer := 16;
RES_BITWIDTH : integer := 16
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
a : in std_logic_vector(A_BITWIDTH-1 downto 0);
b : in std_logic_vector(B_BITWIDTH-1 downto 0);
c : in std_logic_vector(C_BITWIDTH-1 downto 0);
res : out std_logic_vector(RES_BITWIDTH-1 downto 0);
rdy : out std_logic
);
end component;
component adder_tree
generic (
USE_DSP_FOR_ADD : boolean := true;
NUMBER_OF_INPUTS : integer := 4;
INPUT_BITWIDTH : integer := 16
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
sub : in std_logic;
input_string : in std_logic_vector(NUMBER_OF_INPUTS*INPUT_BITWIDTH-1 downto 0);
rdy : out std_logic;
output : out std_logic_vector(INPUT_BITWIDTH+integer(ceil(log2(real(NUMBER_OF_INPUTS))))-1 downto 0)
);
end component;
signal tmp_mul_res : mul_res_array_type;
signal tmp_tree_adder_input_string : std_logic_vector(D*(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1)-1 downto 0);
--signal tmp_tree_adder_res : tree_adder_res_array_type;
signal tmp_tree_adder_res : std_logic_vector(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER-1 downto 0);
signal const_0 : std_logic_vector(MUL_BITWIDTH-1 downto 0);
signal tmp_mul_rdy : std_logic;
signal delay_line_tree_adder : std_logic_vector(0 to 2*LAYERS_TREE_ADDER-1);
signal tmp_final_res : coord_type_ext;
begin
const_0 <= (others => '0');
G1: for I in 0 to D-1 generate
G_FIRST: if I = 0 generate
madd_inst : madd
generic map(
MUL_LATENCY => MUL_CORE_LATENCY,
A_BITWIDTH => MUL_BITWIDTH,
B_BITWIDTH => MUL_BITWIDTH,
INCLUDE_ADD => false,
C_BITWIDTH => MUL_BITWIDTH,
RES_BITWIDTH => 2*MUL_BITWIDTH-SCALE_MUL_RESULT+1
)
port map (
clk => clk,
sclr => sclr,
nd => nd,
a => saturate(point_1(I)),
b => saturate(point_2(I)),
c => const_0,
res => tmp_mul_res(I),
rdy => tmp_mul_rdy
);
end generate G_FIRST;
G_OTHER: if I > 0 generate
madd_inst : madd
generic map(
MUL_LATENCY => MUL_CORE_LATENCY,
A_BITWIDTH => MUL_BITWIDTH,
B_BITWIDTH => MUL_BITWIDTH,
INCLUDE_ADD => false,
C_BITWIDTH => MUL_BITWIDTH,
RES_BITWIDTH => 2*MUL_BITWIDTH-SCALE_MUL_RESULT+1
)
port map (
clk => clk,
sclr => sclr,
nd => nd,
a => saturate(point_1(I)),
b => saturate(point_2(I)),
c => const_0,
res => tmp_mul_res(I),
rdy => open
);
end generate G_OTHER;
end generate G1;
-- -- FIXME: this will not work if D is not power of 2
-- G2: for I in 0 to LAYERS_TREE_ADDER-1 generate
--
-- G_TOP_LAYER: if I = 0 generate
-- G2_2: for J in 0 to (D/(2**(I+1)))-1 generate
--
-- addorsub_inst_2 : addorsub
-- generic map (
-- A_BITWIDTH => 2*MUL_BITWIDTH-SCALE_MUL_RESULT+1,
-- B_BITWIDTH => 2*MUL_BITWIDTH-SCALE_MUL_RESULT+1,
-- RES_BITWIDTH => 2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER
-- )
-- port map (
-- clk => clk,
-- sclr => sclr,
-- nd => '1',
-- sub => '0',
-- a => tmp_mul_res(2*J),
-- b => tmp_mul_res(2*J+1),
-- res => tmp_tree_adder_res(I,J),
-- rdy => open
-- );
-- end generate G2_2;
--
-- end generate G_TOP_LAYER;
--
-- G_OTHER_LAYER: if I > 0 generate
-- G2_2: for J in 0 to (D/(2**(I+1)))-1 generate
-- addorsub_inst_2 : addorsub
-- generic map (
-- A_BITWIDTH => 2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER,
-- B_BITWIDTH => 2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER,
-- RES_BITWIDTH => 2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER
-- )
-- port map (
-- clk => clk,
-- sclr => sclr,
-- nd => '1',
-- sub => '0',
-- a => tmp_tree_adder_res(I-1,2*J),
-- b => tmp_tree_adder_res(I-1,2*J+1),
-- res => tmp_tree_adder_res(I,J),
-- rdy => open
-- );
-- end generate G2_2;
-- end generate G_OTHER_LAYER;
--
-- end generate G2;
--
-- -- compensate for latency
-- delay_line_proc : process(clk)
-- begin
-- if rising_edge(clk) then
-- if sclr = '1' then
-- delay_line_tree_adder <= (others => '0');
-- else
-- delay_line_tree_adder(0) <= tmp_mul_rdy;
-- delay_line_tree_adder(1 to 2*LAYERS_TREE_ADDER-1) <= delay_line_tree_adder(0 to 2*LAYERS_TREE_ADDER-2);
-- end if;
-- end if;
-- end process delay_line_proc;
--
G2 : for I in 0 to D-1 generate
tmp_tree_adder_input_string((I+1)*(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1)-1 downto I*(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1)) <= tmp_mul_res(I);
end generate G2;
adder_tree_inst : adder_tree
generic map (
USE_DSP_FOR_ADD => USE_DSP_FOR_ADD,
NUMBER_OF_INPUTS => D,
INPUT_BITWIDTH => 2*MUL_BITWIDTH-SCALE_MUL_RESULT+1
)
port map (
clk => clk,
sclr => sclr,
nd => tmp_mul_rdy,
sub => '0',
input_string => tmp_tree_adder_input_string,
rdy => rdy,
output => tmp_tree_adder_res
);
G3: if COORD_BITWIDTH_EXT <= 2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER generate
--tmp_final_res <= tmp_tree_adder_res(LAYERS_TREE_ADDER-1,0)(COORD_BITWIDTH_EXT-1 downto 0);
tmp_final_res <= tmp_tree_adder_res(COORD_BITWIDTH_EXT-1 downto 0);
end generate G3;
G4: if COORD_BITWIDTH_EXT > 2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER generate
--tmp_final_res(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER-1 downto 0) <= tmp_tree_adder_res(LAYERS_TREE_ADDER-1,0)(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER-1 downto 0);
--tmp_final_res(COORD_BITWIDTH_EXT-1 downto 2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER) <= (others => tmp_tree_adder_res(LAYERS_TREE_ADDER-1,0)(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER-1));
tmp_final_res(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER-1 downto 0) <= tmp_tree_adder_res(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER-1 downto 0);
tmp_final_res(COORD_BITWIDTH_EXT-1 downto 2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER) <= (others => tmp_tree_adder_res(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER-1));
end generate G4;
--rdy <= delay_line_tree_adder(2*LAYERS_TREE_ADDER-1);
result <= tmp_final_res;
end Behavioral;
| bsd-3-clause | a9281231e9d8431f767bce9399ed4955 | 0.490847 | 3.752415 | false | false | false | false |
freecores/gpib_controller | vhdl/test/gpib_DC_Test.vhd | 1 | 14,055 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Author: Andrzej Paluch
--
-- Create Date: 23:21:05 10/21/2011
-- Design Name:
-- Module Name: /windows/h/projekty/elektronika/USB_to_HPIB/usbToHpib/test_scr//gpibInterfaceTest.vhd
-- Project Name: usbToHpib
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: gpibInterface
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use work.gpibComponents.all;
use work.helperComponents.all;
ENTITY gpib_DC_Test IS
END gpib_DC_Test;
ARCHITECTURE behavior OF gpib_DC_Test IS
-- Component Declaration for the Unit Under Test (UUT)
component gpibCableEmulator is port (
-- interface signals
DIO_1 : in std_logic_vector (7 downto 0);
output_valid_1 : in std_logic;
DIO_2 : in std_logic_vector (7 downto 0);
output_valid_2 : in std_logic;
DIO : out std_logic_vector (7 downto 0);
-- attention
ATN_1 : in std_logic;
ATN_2 : in std_logic;
ATN : out std_logic;
-- data valid
DAV_1 : in std_logic;
DAV_2 : in std_logic;
DAV : out std_logic;
-- not ready for data
NRFD_1 : in std_logic;
NRFD_2 : in std_logic;
NRFD : out std_logic;
-- no data accepted
NDAC_1 : in std_logic;
NDAC_2 : in std_logic;
NDAC : out std_logic;
-- end or identify
EOI_1 : in std_logic;
EOI_2 : in std_logic;
EOI : out std_logic;
-- service request
SRQ_1 : in std_logic;
SRQ_2 : in std_logic;
SRQ : out std_logic;
-- interface clear
IFC_1 : in std_logic;
IFC_2 : in std_logic;
IFC : out std_logic;
-- remote enable
REN_1 : in std_logic;
REN_2 : in std_logic;
REN : out std_logic
);
end component;
-- inputs common
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal T1 : std_logic_vector(7 downto 0) := "00000100";
-- inputs 1
signal data_1 : std_logic_vector(7 downto 0) := (others => '0');
signal status_byte_1 : std_logic_vector(7 downto 0) := (others => '0');
signal rdy_1 : std_logic := '0';
signal nba_1 : std_logic := '0';
signal ltn_1 : std_logic := '0';
signal lun_1 : std_logic := '0';
signal lon_1 : std_logic := '0';
signal ton_1 : std_logic := '0';
signal endOf_1 : std_logic := '0';
signal gts_1 : std_logic := '0';
signal rpp_1 : std_logic := '0';
signal tcs_1 : std_logic := '0';
signal tca_1 : std_logic := '0';
signal sic_1 : std_logic := '0';
signal rsc_1 : std_logic := '0';
signal sre_1 : std_logic := '0';
signal rtl_1 : std_logic := '0';
signal rsv_1 : std_logic := '0';
signal ist_1 : std_logic := '0';
signal lpe_1 : std_logic := '0';
-- inputs 2
signal data_2 : std_logic_vector(7 downto 0) := (others => '0');
signal status_byte_2 : std_logic_vector(7 downto 0) := (others => '0');
signal rdy_2 : std_logic := '0';
signal nba_2 : std_logic := '0';
signal ltn_2 : std_logic := '0';
signal lun_2 : std_logic := '0';
signal lon_2 : std_logic := '0';
signal ton_2 : std_logic := '0';
signal endOf_2 : std_logic := '0';
signal gts_2 : std_logic := '0';
signal rpp_2 : std_logic := '0';
signal tcs_2 : std_logic := '0';
signal tca_2 : std_logic := '0';
signal sic_2 : std_logic := '0';
signal rsc_2 : std_logic := '0';
signal sre_2 : std_logic := '0';
signal rtl_2 : std_logic := '0';
signal rsv_2 : std_logic := '0';
signal ist_2 : std_logic := '0';
signal lpe_2 : std_logic := '0';
-- outputs 1
signal dvd_1 : std_logic;
signal wnc_1 : std_logic;
signal tac_1 : std_logic;
signal cwrc_1 : std_logic;
signal cwrd_1 : std_logic;
signal clr_1 : std_logic;
signal trg_1 : std_logic;
signal atl_1 : std_logic;
signal att_1 : std_logic;
signal mla_1 : std_logic;
signal lsb_1 : std_logic;
signal spa_1 : std_logic;
signal ppr_1 : std_logic;
signal sreq_1 : std_logic;
signal isLocal_1 : std_logic;
signal currentSecAddr_1 : std_logic_vector (4 downto 0);
-- outputs 2
signal dvd_2 : std_logic;
signal wnc_2 : std_logic;
signal tac_2 : std_logic;
signal cwrc_2 : std_logic;
signal cwrd_2 : std_logic;
signal clr_2 : std_logic;
signal trg_2 : std_logic;
signal atl_2 : std_logic;
signal att_2 : std_logic;
signal mla_2 : std_logic;
signal lsb_2 : std_logic;
signal spa_2 : std_logic;
signal ppr_2 : std_logic;
signal sreq_2 : std_logic;
signal isLocal_2 : std_logic;
signal currentSecAddr_2 : std_logic_vector (4 downto 0);
-- common
signal DO : std_logic_vector (7 downto 0);
signal DI_1 : std_logic_vector (7 downto 0);
signal output_valid_1 : std_logic;
signal DI_2 : std_logic_vector (7 downto 0);
signal output_valid_2 : std_logic;
signal ATN_1, ATN_2, ATN : std_logic;
signal DAV_1, DAV_2, DAV : std_logic;
signal NRFD_1, NRFD_2, NRFD : std_logic;
signal NDAC_1, NDAC_2, NDAC : std_logic;
signal EOI_1, EOI_2, EOI : std_logic;
signal SRQ_1, SRQ_2, SRQ : std_logic;
signal IFC_1, IFC_2, IFC : std_logic;
signal REN_1, REN_2, REN : std_logic;
-- gpib reader
signal buf_interrupt : std_logic;
signal data_available : std_logic;
signal last_byte_addr : std_logic_vector (3 downto 0);
signal end_of_stream : std_logic;
signal byte_addr : std_logic_vector (3 downto 0);
signal data_out : std_logic_vector (7 downto 0);
signal reset_buffer : std_logic := '0';
signal dataSecAddr : std_logic_vector (4 downto 0);
-- gpib writer
signal w_last_byte_addr : std_logic_vector (3 downto 0)
:= (others => '0');
signal w_end_of_stream : std_logic := '0';
signal w_data_available : std_logic := '0';
signal w_buf_interrupt : std_logic;
signal w_data_in : std_logic_vector (7 downto 0);
signal w_byte_addr : std_logic_vector (3 downto 0);
signal w_reset_buffer : std_logic := '0';
type WR_BUF_TYPE is
array (0 to 15) of std_logic_vector (7 downto 0);
signal w_write_buffer : WR_BUF_TYPE;
-- Clock period definitions
constant clk_period : time := 2ps;
BEGIN
-- Instantiate the Unit Under Test (UUT)
gpib1: gpibInterface PORT MAP (
clk => clk,
reset => reset,
isLE => '0',
isTE => '0',
lpeUsed => '0',
fixedPpLine => "000",
eosUsed => '0',
eosMark => "00000000",
myListAddr => "00001",
myTalkAddr => "00001",
secAddrMask => (others => '0'),
data => data_1,
status_byte => status_byte_1,
T1 => T1,
rdy => rdy_1,
nba => nba_1,
ltn => ltn_1,
lun => lun_1,
lon => lon_1,
ton => ton_1,
endOf => endOf_1,
gts => gts_1,
rpp => rpp_1,
tcs => tcs_1,
tca => tca_1,
sic => sic_1,
rsc => rsc_1,
sre => sre_1,
rtl => rtl_1,
rsv => rsv_1,
ist => ist_1,
lpe => lpe_1,
dvd => dvd_1,
wnc => wnc_1,
tac => tac_1,
cwrc => cwrc_1,
cwrd => cwrd_1,
clr => clr_1,
trg => trg_1,
atl => atl_1,
att => att_1,
mla => mla_1,
lsb => lsb_1,
spa => spa_1,
ppr => ppr_1,
sreq => sreq_1,
isLocal => isLocal_1,
currentSecAddr => currentSecAddr_1,
DI => DO,
DO => DI_1,
output_valid => output_valid_1,
ATN_in => ATN,
ATN_out => ATN_1,
DAV_in => DAV,
DAV_out => DAV_1,
NRFD_in => NRFD,
NRFD_out => NRFD_1,
NDAC_in => NDAC,
NDAC_out => NDAC_1,
EOI_in => EOI,
EOI_out => EOI_1,
SRQ_in => SRQ,
SRQ_out => SRQ_1,
IFC_in => IFC,
IFC_out => IFC_1,
REN_in => REN,
REN_out => REN_1
);
-- Instantiate the Unit Under Test (UUT)
gpib2: gpibInterface PORT MAP (
clk => clk,
reset => reset,
isLE => '0',
isTE => '0',
lpeUsed => '0',
fixedPpLine => "000",
eosUsed => '0',
eosMark => "00000000",
myListAddr => "00010",
myTalkAddr => "00010",
secAddrMask => (others => '0'),
data => data_2,
status_byte => status_byte_2,
T1 => T1,
rdy => rdy_2,
nba => nba_2,
ltn => ltn_2,
lun => lun_2,
lon => lon_2,
ton => ton_2,
endOf => endOf_2,
gts => gts_2,
rpp => rpp_2,
tcs => tcs_2,
tca => tca_2,
sic => sic_2,
rsc => rsc_2,
sre => sre_2,
rtl => rtl_2,
rsv => rsv_2,
ist => ist_2,
lpe => lpe_2,
dvd => dvd_2,
wnc => wnc_2,
tac => tac_2,
cwrc => cwrc_2,
cwrd => cwrd_2,
clr => clr_2,
trg => trg_2,
atl => atl_2,
att => att_2,
mla => mla_2,
lsb => lsb_2,
spa => spa_2,
ppr => ppr_2,
sreq => sreq_2,
isLocal => isLocal_2,
currentSecAddr => currentSecAddr_2,
DI => DO,
DO => DI_2,
output_valid => output_valid_2,
ATN_in => ATN,
ATN_out => ATN_2,
DAV_in => DAV,
DAV_out => DAV_2,
NRFD_in => NRFD,
NRFD_out => NRFD_2,
NDAC_in => NDAC,
NDAC_out => NDAC_2,
EOI_in => EOI,
EOI_out => EOI_2,
SRQ_in => SRQ,
SRQ_out => SRQ_2,
IFC_in => IFC,
IFC_out => IFC_2,
REN_in => REN,
REN_out => REN_2
);
ce: gpibCableEmulator port map (
-- interface signals
DIO_1 => DI_1,
output_valid_1 => output_valid_1,
DIO_2 => DI_2,
output_valid_2 => output_valid_2,
DIO => DO,
-- attention
ATN_1 => ATN_1, ATN_2 => ATN_2, ATN => ATN,
DAV_1 => DAV_1, DAV_2 => DAV_2, DAV => DAV,
NRFD_1 => NRFD_1, NRFD_2 => NRFD_2, NRFD => NRFD,
NDAC_1 => NDAC_1, NDAC_2 => NDAC_2, NDAC => NDAC,
EOI_1 => EOI_1, EOI_2 => EOI_2, EOI => EOI,
SRQ_1 => SRQ_1, SRQ_2 => SRQ_2, SRQ => SRQ,
IFC_1 => IFC_1, IFC_2 => IFC_2, IFC => IFC,
REN_1 => REN_1, REN_2 => REN_2, REN => REN
);
gr: gpibReader generic map (ADDR_WIDTH => 4) port map (
clk => clk, reset => reset,
------------------------------------------------------------------------
------ GPIB interface --------------------------------------------------
------------------------------------------------------------------------
data_in => DO, dvd => dvd_2, atl => atl_2, lsb => lsb_2, rdy => rdy_2,
------------------------------------------------------------------------
------ external interface ----------------------------------------------
------------------------------------------------------------------------
isLE => '0', secAddr => (others => '0'), dataSecAddr => dataSecAddr,
buf_interrupt => buf_interrupt, data_available => data_available,
last_byte_addr => last_byte_addr, end_of_stream => end_of_stream,
byte_addr => byte_addr, data_out => data_out,
reset_buffer => reset_buffer
);
w_data_in <= w_write_buffer(conv_integer(w_byte_addr));
gw: gpibWriter generic map (ADDR_WIDTH => 4) port map (
clk => clk, reset => reset,
------------------------------------------------------------------------
------ GPIB interface --------------------------------------------------
------------------------------------------------------------------------
data_out => data_1, wnc => wnc_1, spa => spa_1, nba => nba_1,
endOf => endOf_1, att => att_1, cwrc => cwrc_1,
------------------------------------------------------------------------
------ external interface ----------------------------------------------
------------------------------------------------------------------------
isTE => '0', secAddr => (others => '0'), dataSecAddr => (others => '0'),
last_byte_addr => w_last_byte_addr, end_of_stream => w_end_of_stream,
data_available => w_data_available, buf_interrupt => w_buf_interrupt,
data_in => w_data_in, byte_addr => w_byte_addr,
reset_buffer => w_reset_buffer
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 10 clock periods.
reset <= '1';
wait for clk_period*10;
reset <= '0';
wait for clk_period*10;
-- requests system control
rsc_1 <= '1';
-- interface clear
sic_1 <= '1';
wait until IFC_1 = '1';
sic_1 <= '0';
wait until IFC_1 = '0';
assert clr_2 = '0';
-- send DCL (device clear)
w_write_buffer(0) <= "00010100";
w_last_byte_addr <= "0000";
w_data_available <= '1';
wait until w_buf_interrupt='1';
assert clr_1 = '1';
assert clr_2 = '1';
w_reset_buffer <= '1';
wait for clk_period*2;
w_reset_buffer <= '0';
-- send SDC (selected device clear)
w_write_buffer(0) <= "00000100";
w_last_byte_addr <= "0000";
w_data_available <= '1';
wait until w_buf_interrupt='1';
wait for clk_period*2;
assert clr_1 = '0';
assert clr_2 = '0';
w_reset_buffer <= '1';
wait for clk_period*2;
w_reset_buffer <= '0';
-- gpib2 to listen
w_write_buffer(0) <= "00100010";
w_last_byte_addr <= "0000";
w_data_available <= '1';
wait until w_buf_interrupt='1';
wait for clk_period*2;
assert clr_1 = '0';
assert clr_2 = '0';
w_reset_buffer <= '1';
wait for clk_period*2;
w_reset_buffer <= '0';
-- send SDC (selected device clear)
w_write_buffer(0) <= "00000100";
w_last_byte_addr <= "0000";
w_data_available <= '1';
wait until w_buf_interrupt='1';
wait for clk_period*2;
assert clr_1 = '0';
assert clr_2 = '1';
report "$$$ END OF TEST - DC (device clear) $$$";
wait;
end process;
END;
| gpl-3.0 | 26d107f150aac2a2ff1c61890e9c969c | 0.562504 | 2.871297 | false | false | false | false |
autosub-team/autosub | src/tests/testTasksVHDL/testsubmissions/gates/gates_beh.vhdl | 2 | 901 | library IEEE;
use IEEE.std_logic_1164.all;
use work.IEEE_1164_Gates_pkg.all;
architecture behavior of gates is
signal s1 : std_logic;
signal s2 : std_logic;
signal s3 : std_logic;
signal s4 : std_logic;
signal s5 : std_logic;
signal notA : std_logic;
signal notB : std_logic;
signal notC : std_logic;
signal notD : std_logic;
begin
G0 : NOR3
port map
(
I1 => notA,
I2 => notB,
I3 => D,
O => s1
);
G1 : OR3
port map
(
I1 => B,
I2 => notC,
I3 => notD,
O => s2
);
G2 : NAND2
port map
(
I1 => A,
I2 => notD,
O => s3
);
G3 : AND2
port map
(
I1 => A,
I2 => notD,
O => s4
);
G4 : NOR4
port map
(
I1=>s1,
I2=>s2,
I3=>s3,
I4=>s4,
O=> s5
);
O <= s5;
notA <= not A;
notB <= not B;
notC <= not C;
notD <= not D;
end behavior;
| gpl-2.0 | cfae7f765ce71b81cf04550879e57bae | 0.482797 | 2.574286 | false | false | false | false |
Nooxet/embedded_bruteforce | brutus_system/hdl/system_bajsd_0_wrapper.vhd | 1 | 1,814 | -------------------------------------------------------------------------------
-- system_bajsd_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library bajsd_v1_00_a;
use bajsd_v1_00_a.all;
entity system_bajsd_0_wrapper is
port (
FSL_Clk : in std_logic;
FSL_Rst : in std_logic;
FSL_S_Clk : in std_logic;
FSL_S_Read : out std_logic;
FSL_S_Data : in std_logic_vector(0 to 31);
FSL_S_Control : in std_logic;
FSL_S_Exists : in std_logic;
FSL_M_Clk : in std_logic;
FSL_M_Write : out std_logic;
FSL_M_Data : out std_logic_vector(0 to 31);
FSL_M_Control : out std_logic;
FSL_M_Full : in std_logic
);
end system_bajsd_0_wrapper;
architecture STRUCTURE of system_bajsd_0_wrapper is
component bajsd is
port (
FSL_Clk : in std_logic;
FSL_Rst : in std_logic;
FSL_S_Clk : in std_logic;
FSL_S_Read : out std_logic;
FSL_S_Data : in std_logic_vector(0 to 31);
FSL_S_Control : in std_logic;
FSL_S_Exists : in std_logic;
FSL_M_Clk : in std_logic;
FSL_M_Write : out std_logic;
FSL_M_Data : out std_logic_vector(0 to 31);
FSL_M_Control : out std_logic;
FSL_M_Full : in std_logic
);
end component;
begin
bajsd_0 : bajsd
port map (
FSL_Clk => FSL_Clk,
FSL_Rst => FSL_Rst,
FSL_S_Clk => FSL_S_Clk,
FSL_S_Read => FSL_S_Read,
FSL_S_Data => FSL_S_Data,
FSL_S_Control => FSL_S_Control,
FSL_S_Exists => FSL_S_Exists,
FSL_M_Clk => FSL_M_Clk,
FSL_M_Write => FSL_M_Write,
FSL_M_Data => FSL_M_Data,
FSL_M_Control => FSL_M_Control,
FSL_M_Full => FSL_M_Full
);
end architecture STRUCTURE;
| mit | 056dceb7506936984ba06348cc3bd35e | 0.544653 | 3.048739 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | filtering_algorithm_RTL/source/vhdl/centre_index_memory_top.vhd | 1 | 6,516 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: centre_index_memory_top - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.filtering_algorithm_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity centre_index_memory_top is
port (
clk : in std_logic;
sclr : in std_logic;
rd : in std_logic;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(CNTR_POINTER_BITWIDTH+INDEX_BITWIDTH-1 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(INDEX_BITWIDTH-1 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(CNTR_POINTER_BITWIDTH+INDEX_BITWIDTH-1 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(INDEX_BITWIDTH-1 DOWNTO 0);
item_read_twice : out std_logic;
item_address : out std_logic_vector(CNTR_POINTER_BITWIDTH-1 downto 0)
);
end centre_index_memory_top;
architecture Behavioral of centre_index_memory_top is
constant CENTRE_INDEX_MEM_LAT : integer := 3;
constant CENTRE_LIST_BASE_ADDR_BITWIDTH : integer := CNTR_POINTER_BITWIDTH;
type state_type is (idle, write_write, write_read);
component centre_index_memory
port (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(CNTR_POINTER_BITWIDTH+INDEX_BITWIDTH-1 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(INDEX_BITWIDTH-1 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(CNTR_POINTER_BITWIDTH+INDEX_BITWIDTH-1 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(INDEX_BITWIDTH-1 DOWNTO 0)
);
end component;
COMPONENT centre_index_trace_memory
PORT (
a : IN STD_LOGIC_VECTOR(CNTR_POINTER_BITWIDTH-1 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
dpra : IN STD_LOGIC_VECTOR(CNTR_POINTER_BITWIDTH-1 DOWNTO 0);
clk : IN STD_LOGIC;
we : IN STD_LOGIC;
qdpo : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT;
signal state : state_type;
signal tmp_rd : std_logic;
signal rd_reg : std_logic;
signal wr_reg : std_logic;
signal rd_first_cl : std_logic;
signal rd_first_cl_reg : std_logic;
signal wr_first_cl : std_logic;
signal rd_addr_reg : std_logic_vector(CNTR_POINTER_BITWIDTH-1 downto 0);
signal rd_addr_reg_out : std_logic_vector(CNTR_POINTER_BITWIDTH-1 downto 0);
signal trace_mem_we : std_logic;
signal trace_mem_wr_addr : std_logic_vector(CNTR_POINTER_BITWIDTH-1 downto 0);
signal trace_mem_d : std_logic_vector(0 downto 0);
signal trace_mem_dout : std_logic_vector(0 downto 0);
signal trace_mem_dout_reg : std_logic;
signal trace_mem_dout_reg_out : std_logic;
begin
-- read address 0 corresponds is virtual
tmp_rd <= rd;--'0' WHEN addrb(CNTR_POINTER_BITWIDTH+INDEX_BITWIDTH-1 DOWNTO INDEX_BITWIDTH) = std_logic_vector(to_unsigned(0,CNTR_POINTER_BITWIDTH)) ELSE rd;
fsm_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
state <= write_write;
elsif state = write_write AND rd_first_cl = '1' AND wr_first_cl = '1' then
state <= write_read;
elsif state = write_read then
state <= write_write;
end if;
end if;
end process fsm_proc;
input_latch_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
rd_reg <= '0';
wr_reg <= '0';
rd_first_cl_reg <= '0';
else
rd_reg <= tmp_rd;
wr_reg <= wea(0);
rd_first_cl_reg <= rd_first_cl;
end if;
if rd_first_cl = '1' then
rd_addr_reg <= addrb(CNTR_POINTER_BITWIDTH+INDEX_BITWIDTH-1 downto INDEX_BITWIDTH);
end if;
end if;
end process input_latch_proc;
rd_first_cl <= tmp_rd AND NOT(rd_reg);
wr_first_cl <= wea(0) AND NOT(wr_reg);
trace_mem_we <= '1' WHEN rd_first_cl = '1' OR wr_first_cl = '1' OR state = write_read ELSE '0';
trace_mem_wr_addr <= addra(CNTR_POINTER_BITWIDTH+INDEX_BITWIDTH-1 downto INDEX_BITWIDTH) WHEN wr_first_cl = '1' ELSE
addrb(CNTR_POINTER_BITWIDTH+INDEX_BITWIDTH-1 downto INDEX_BITWIDTH) WHEN wr_first_cl = '0' AND rd_first_cl = '1' ELSE
rd_addr_reg;
trace_mem_d(0) <= NOT(wr_first_cl);
centre_index_trace_memory_inst : centre_index_trace_memory
port map (
a => trace_mem_wr_addr,
d => trace_mem_d,
dpra => addrb(CNTR_POINTER_BITWIDTH+INDEX_BITWIDTH-1 downto INDEX_BITWIDTH),
clk => clk,
we => trace_mem_we,
qdpo => trace_mem_dout
);
centre_index_memory_inst : centre_index_memory
port map (
clka => clk,
wea => wea,
addra => addra,
dina => dina,
clkb => clk,
addrb => addrb,
doutb => doutb
);
-- sample trace memory output in the right moment (2nd cycle)
sample_output_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
trace_mem_dout_reg <= '0';
else
if rd_first_cl_reg = '1' then
trace_mem_dout_reg <= trace_mem_dout(0);
end if;
end if;
rd_addr_reg_out <= rd_addr_reg;
trace_mem_dout_reg_out <= trace_mem_dout_reg;
end if;
end process sample_output_proc;
item_read_twice <= trace_mem_dout_reg_out;
item_address <= rd_addr_reg_out;
end Behavioral;
| bsd-3-clause | 1fa358b3de837f65a81df7e61071ba79 | 0.552333 | 3.848789 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | filtering_algorithm_RTL/source/vhdl/allocator.vhd | 1 | 5,530 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: allocator - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.filtering_algorithm_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity allocator is
generic (
MEMORY_SIZE : integer := 1024
);
port (
clk : in std_logic;
sclr : in std_logic;
alloc : in std_logic;
free : in std_logic;
address_in : in std_logic_vector(integer(ceil(log2(real(MEMORY_SIZE))))-1 downto 0);
rdy : out std_logic;
address_out : out std_logic_vector(integer(ceil(log2(real(MEMORY_SIZE))))-1 downto 0);
heap_full : out std_logic
);
end allocator;
architecture Behavioral of allocator is
constant FREE_LIST_BITWIDTH : integer := integer(ceil(log2(real(MEMORY_SIZE))));
constant HEAP_BOUND : integer := MEMORY_SIZE-1;
COMPONENT free_list_memory
PORT (
a : IN STD_LOGIC_VECTOR(FREE_LIST_BITWIDTH-1 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(FREE_LIST_BITWIDTH-1 DOWNTO 0);
dpra : IN STD_LOGIC_VECTOR(FREE_LIST_BITWIDTH-1 DOWNTO 0);
clk : IN STD_LOGIC;
we : IN STD_LOGIC;
dpo : OUT STD_LOGIC_VECTOR(FREE_LIST_BITWIDTH-1 DOWNTO 0)
);
END COMPONENT;
signal tmp_free : std_logic;
signal current_free_location : std_logic_vector(FREE_LIST_BITWIDTH-1 downto 0);
signal free_list_mem_we : std_logic;
signal free_list_mem_dout : std_logic_vector(FREE_LIST_BITWIDTH-1 downto 0);
signal free_list_mem_din : std_logic_vector(FREE_LIST_BITWIDTH-1 downto 0);
signal address_in_reg : std_logic_vector(FREE_LIST_BITWIDTH-1 downto 0);
signal alloc_count : unsigned(FREE_LIST_BITWIDTH-1 downto 0);
signal tmp_heap_full : std_logic;
signal debug_max_alloc_count : unsigned(FREE_LIST_BITWIDTH-1 downto 0);
signal debug_fl_last_item_reached : std_logic;
signal debug_invalid_location : std_logic;
signal debug_invalid_malloc : std_logic;
begin
tmp_free <= '0' WHEN address_in = std_logic_vector(to_unsigned(0,FREE_LIST_BITWIDTH)) ELSE free; -- do not deallocate address 0
alloc_free_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
current_free_location <= std_logic_vector(to_unsigned(1,FREE_LIST_BITWIDTH)); --first list is always pre-allocated
alloc_count <= to_unsigned(1,FREE_LIST_BITWIDTH); --first list is always pre-allocated
else
if alloc = '1' AND tmp_free = '0' then
if tmp_heap_full = '0' then
current_free_location <= free_list_mem_dout;
alloc_count <= alloc_count + 1;
end if;
elsif tmp_free = '1' AND alloc = '0' then
current_free_location <= address_in;
alloc_count <= alloc_count - 1;
end if;
end if;
address_in_reg <= address_in;
end if;
end process alloc_free_proc;
free_list_mem_we <= tmp_free OR (tmp_free AND alloc);
free_list_mem_din <= address_in;
-- replace this memory by register file in case of timing issues
free_list_memory_inst : free_list_memory
port map (
a => free_list_mem_din,
d => current_free_location,
dpra => current_free_location,
clk => clk,
we => free_list_mem_we,
dpo => free_list_mem_dout
);
tmp_heap_full <= '1' WHEN alloc_count = to_unsigned(HEAP_BOUND,FREE_LIST_BITWIDTH) ELSE '0';
rdy <= alloc;
address_out <= address_in WHEN alloc = '1' AND tmp_free = '1' ELSE
(others => '0') WHEN tmp_heap_full = '1' AND alloc = '1' AND tmp_free = '0' ELSE
current_free_location;
heap_full <= tmp_heap_full;
-- debuggin info
G_NOSYNTH_0 : if SYNTHESIS = false generate
stats_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
debug_max_alloc_count <= (others => '0');
else
if debug_max_alloc_count < alloc_count then
debug_max_alloc_count <= alloc_count;
end if;
end if;
end if;
end process stats_proc;
debug_fl_last_item_reached <= '1' WHEN current_free_location = std_logic_vector(to_unsigned(HEAP_BOUND,FREE_LIST_BITWIDTH)) ELSE '0';
debug_invalid_location <= '1' WHEN current_free_location > std_logic_vector(to_unsigned(HEAP_BOUND,FREE_LIST_BITWIDTH)) ELSE '0';
debug_invalid_malloc <= '1' WHEN alloc = '1' AND debug_invalid_location = '1' ELSE '0';
end generate G_NOSYNTH_0;
end Behavioral;
| bsd-3-clause | f3aa7b2c5f25ce3fc703bb937e5e9691 | 0.566908 | 3.933144 | false | false | false | false |
UdayanSinha/Code_Blocks | VHDL/Projects/work/tb_test3.vhd | 1 | 1,231 | ---------------------------------------------------------
---
-- Test Bench for Four Bit Up-Down Counter
-- File name : counter_sig_tb.vhd
---------------------------------------------------------
---
Library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_signed.ALL;
architecture tb_counter_var of test is
component counter_sig
port( UP, CLK, RESET : in std_logic;
OUT1 : out std_logic;
OUT2 : out std_logic_vector(3 downto 0)
);
end component;
signal UP : std_logic := '1';
signal RESET : std_logic := '0';
signal CLK : std_logic := '0';
signal Out1 : std_logic := '0';
signal Out2 : std_logic_vector(3 downto 0):=(others=>'0');
for U1:counter_sig use entity work.counter_sig(Arch_counter_var);
begin
U1: counter_sig port map ( UP, CLK, RESET, OUT1, OUT2);
RESET <= '1' after 125 ns;
CLK <= not(CLK) after 50 ns;
-----------------------------------------------------
tb: process
begin
UP <= transport '0' after 945 ns;
UP <= transport '1' after 1825 ns;
UP <= transport '0' after 2025 ns;
wait;
end process; --tb
-----------------------------------------------------
end; -- tb_counter_var
| mit | 7d025305e4167e3bd428c1176f5a5312 | 0.484972 | 3.811146 | false | true | false | false |
mithro/HDMI2USB | ipcore_dir/cdcfifo/simulation/cdcfifo_dverif.vhd | 3 | 5,496 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: cdcfifo_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.cdcfifo_pkg.ALL;
ENTITY cdcfifo_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF cdcfifo_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:cdcfifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
| bsd-2-clause | ed1840bb800392264dde9c27498e8502 | 0.575328 | 4.123031 | false | false | false | false |
dhmeves/ece-485 | ece-485-project-2/four_to_one_mux_1_bit.vhd | 1 | 542 | library IEEE;
use ieee.std_logic_1164.all;
entity four_to_one_mux_1_bit is
port(
a, b, c, d : in std_logic;
sel : in std_logic_vector(1 downto 0);
output : out std_logic
);
end entity four_to_one_mux_1_bit;
architecture behav of four_to_one_mux_1_bit is
begin
--output <= (a and (not sel(0)) and (not sel(1))) or (b and sel(0) and (not sel(1))) or (c and (not sel(0)) and sel(1)) or (d and sel(0) and sel(1));
output <= a when (sel = "00") else b when (sel = "01") else c when (sel = "10") else d when (sel = "11");
end behav; | gpl-3.0 | 4318a90f3b829eedbb72c1f049c018de | 0.619926 | 2.486239 | false | false | false | false |
tsotnep/vhdl_soc_audio_mixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/superip_v1_00_a/hdl/vhdl/user_logic.vhd | 1 | 31,542 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Tue May 5 20:44:19 2015 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port(
-- ADD USER PORTS BELOW THIS LINE ------------------
CLK_48_in : in std_logic;
CLK_100M_in : in std_logic;
Audio_Left_in : in std_logic_vector(23 downto 0);
Audio_Right_in : in std_logic_vector(23 downto 0);
SAMPLE_TRIG : in std_logic;
Mux3_BalanceORMux2_Left_out : out std_logic_vector(23 downto 0);
Mux3_BalanceORMux2_Right_out : out std_logic_vector(23 downto 0);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH / 8 - 1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG - 1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG - 1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg1 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg2 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg3 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg4 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg5 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg6 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg7 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg8 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg9 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg10 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg11 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg12 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg13 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg14 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg15 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg16 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg17 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg18 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg19 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg20 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg21 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg22 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg23 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg24 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg25 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg26 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg27 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg28 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg29 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg30 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg31 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg_write_sel : std_logic_vector(31 downto 0);
signal slv_reg_read_sel : std_logic_vector(31 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal slv_reg26_internal : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg28_internal : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg29_internal : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg30_internal : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg31_internal : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
component superip_internal is
port(
-- Outputs
Mux3_BalanceORMux2_Left_out : out std_logic_vector(23 downto 0);
Mux3_BalanceORMux2_Right_out : out std_logic_vector(23 downto 0);
slv_reg26 : out STD_LOGIC_VECTOR(31 downto 0);
slv_reg28 : out STD_LOGIC_VECTOR(31 downto 0);
slv_reg29 : out STD_LOGIC_VECTOR(31 downto 0);
slv_reg30 : out STD_LOGIC_VECTOR(31 downto 0);
slv_reg31 : out STD_LOGIC_VECTOR(31 downto 0);
-- Inputs
CLK_48_in : in std_logic;
CLK_100M_in : in std_logic;
Audio_Left_in : in std_logic_vector(23 downto 0);
Audio_Right_in : in std_logic_vector(23 downto 0);
SAMPLE_TRIG : in std_logic;
-- REGISTERS
slv_reg0 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg1 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg2 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg3 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg4 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg5 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg6 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg7 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg8 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg9 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg10 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg11 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg12 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg13 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg14 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg15 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg16 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg17 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg18 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg19 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg20 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg21 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg22 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg23 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg24 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg25 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg27 : in STD_LOGIC_VECTOR(31 downto 0)
);
end component;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(31 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(31 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12) or Bus2IP_WrCE(13)
or Bus2IP_WrCE(14) or Bus2IP_WrCE(15) or Bus2IP_WrCE(16) or Bus2IP_WrCE(17) or Bus2IP_WrCE(18) or Bus2IP_WrCE(19) or Bus2IP_WrCE(20) or Bus2IP_WrCE(21) or Bus2IP_WrCE(22) or Bus2IP_WrCE(23) or Bus2IP_WrCE(24) or Bus2IP_WrCE(25) or Bus2IP_WrCE(26) or Bus2IP_WrCE(27) or
Bus2IP_WrCE(28) or Bus2IP_WrCE(29) or Bus2IP_WrCE(30) or Bus2IP_WrCE(31);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4) or Bus2IP_RdCE(5) or Bus2IP_RdCE(6) or Bus2IP_RdCE(7) or Bus2IP_RdCE(8) or Bus2IP_RdCE(9) or Bus2IP_RdCE(10) or Bus2IP_RdCE(11) or Bus2IP_RdCE(12) or Bus2IP_RdCE(13)
or Bus2IP_RdCE(14) or Bus2IP_RdCE(15) or Bus2IP_RdCE(16) or Bus2IP_RdCE(17) or Bus2IP_RdCE(18) or Bus2IP_RdCE(19) or Bus2IP_RdCE(20) or Bus2IP_RdCE(21) or Bus2IP_RdCE(22) or Bus2IP_RdCE(23) or Bus2IP_RdCE(24) or Bus2IP_RdCE(25) or Bus2IP_RdCE(26) or Bus2IP_RdCE(27) or
Bus2IP_RdCE(28) or Bus2IP_RdCE(29) or Bus2IP_RdCE(30) or Bus2IP_RdCE(31);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process(Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
slv_reg8 <= (others => '0');
slv_reg9 <= (others => '0');
slv_reg10 <= (others => '0');
slv_reg11 <= (others => '0');
slv_reg12 <= (others => '0');
slv_reg13 <= (others => '0');
slv_reg14 <= (others => '0');
slv_reg15 <= (others => '0');
slv_reg16 <= (others => '0');
slv_reg17 <= (others => '0');
slv_reg18 <= (others => '0');
slv_reg19 <= (others => '0');
slv_reg20 <= (others => '0');
slv_reg21 <= (others => '0');
slv_reg22 <= (others => '0');
slv_reg23 <= (others => '0');
slv_reg24 <= (others => '0');
slv_reg25 <= (others => '0');
slv_reg26 <= (others => '0');
slv_reg27 <= (others => '0');
slv_reg28 <= (others => '0');
slv_reg29 <= (others => '0');
slv_reg30 <= (others => '0');
slv_reg31 <= (others => '0');
else
case slv_reg_write_sel is
when "10000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg0(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "01000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg1(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00100000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg2(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00010000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg3(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00001000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg4(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000100000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg5(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000010000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg6(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000001000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg7(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000000100000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg8(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000000010000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg9(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000000001000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg10(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000000000100000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg11(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000000000010000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg12(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000000000001000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg13(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000000000000100000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg14(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000000000000010000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg15(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000000000000001000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg16(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000000000000000100000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg17(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000000000000000010000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg18(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000000000000000001000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg19(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000000000000000000100000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg20(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000000000000000000010000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg21(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000000000000000000001000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg22(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000000000000000000000100000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg23(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000000000000000000000010000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg24(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000000000000000000000001000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg25(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
-- when "00000000000000000000000000100000" =>
-- for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
-- if (Bus2IP_BE(byte_index) = '1') then
-- slv_reg26(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
-- end if;
-- end loop;
when "00000000000000000000000000010000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg27(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
-- when "00000000000000000000000000001000" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg28(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when "00000000000000000000000000000100" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg29(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when "00000000000000000000000000000010" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg30(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when "00000000000000000000000000000001" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg31(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
when others => null;
end case;
slv_reg26 <= slv_reg26_internal;
slv_reg28 <= slv_reg28_internal;
slv_reg29 <= slv_reg29_internal;
slv_reg30 <= slv_reg30_internal;
slv_reg31 <= slv_reg31_internal;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process(slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, slv_reg18, slv_reg19, slv_reg20, slv_reg21, slv_reg22, slv_reg23, slv_reg24, slv_reg25, slv_reg26, slv_reg27, slv_reg28, slv_reg29, slv_reg30, slv_reg31)
is
begin
case slv_reg_read_sel is
when "10000000000000000000000000000000" => slv_ip2bus_data <= slv_reg0;
when "01000000000000000000000000000000" => slv_ip2bus_data <= slv_reg1;
when "00100000000000000000000000000000" => slv_ip2bus_data <= slv_reg2;
when "00010000000000000000000000000000" => slv_ip2bus_data <= slv_reg3;
when "00001000000000000000000000000000" => slv_ip2bus_data <= slv_reg4;
when "00000100000000000000000000000000" => slv_ip2bus_data <= slv_reg5;
when "00000010000000000000000000000000" => slv_ip2bus_data <= slv_reg6;
when "00000001000000000000000000000000" => slv_ip2bus_data <= slv_reg7;
when "00000000100000000000000000000000" => slv_ip2bus_data <= slv_reg8;
when "00000000010000000000000000000000" => slv_ip2bus_data <= slv_reg9;
when "00000000001000000000000000000000" => slv_ip2bus_data <= slv_reg10;
when "00000000000100000000000000000000" => slv_ip2bus_data <= slv_reg11;
when "00000000000010000000000000000000" => slv_ip2bus_data <= slv_reg12;
when "00000000000001000000000000000000" => slv_ip2bus_data <= slv_reg13;
when "00000000000000100000000000000000" => slv_ip2bus_data <= slv_reg14;
when "00000000000000010000000000000000" => slv_ip2bus_data <= slv_reg15;
when "00000000000000001000000000000000" => slv_ip2bus_data <= slv_reg16;
when "00000000000000000100000000000000" => slv_ip2bus_data <= slv_reg17;
when "00000000000000000010000000000000" => slv_ip2bus_data <= slv_reg18;
when "00000000000000000001000000000000" => slv_ip2bus_data <= slv_reg19;
when "00000000000000000000100000000000" => slv_ip2bus_data <= slv_reg20;
when "00000000000000000000010000000000" => slv_ip2bus_data <= slv_reg21;
when "00000000000000000000001000000000" => slv_ip2bus_data <= slv_reg22;
when "00000000000000000000000100000000" => slv_ip2bus_data <= slv_reg23;
when "00000000000000000000000010000000" => slv_ip2bus_data <= slv_reg24;
when "00000000000000000000000001000000" => slv_ip2bus_data <= slv_reg25;
when "00000000000000000000000000100000" => slv_ip2bus_data <= slv_reg26;
when "00000000000000000000000000010000" => slv_ip2bus_data <= slv_reg27;
when "00000000000000000000000000001000" => slv_ip2bus_data <= slv_reg28;
when "00000000000000000000000000000100" => slv_ip2bus_data <= slv_reg29;
when "00000000000000000000000000000010" => slv_ip2bus_data <= slv_reg30;
when "00000000000000000000000000000001" => slv_ip2bus_data <= slv_reg31;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
SIP : superip_internal port map(
Mux3_BalanceORMux2_Left_out => Mux3_BalanceORMux2_Left_out,
Mux3_BalanceORMux2_Right_out => Mux3_BalanceORMux2_Right_out,
slv_reg26 => slv_reg26_internal,
slv_reg28 => slv_reg28_internal,
slv_reg29 => slv_reg29_internal,
slv_reg30 => slv_reg30_internal,
slv_reg31 => slv_reg31_internal,
CLK_48_in => CLK_48_in,
CLK_100M_in => CLK_100M_in,
Audio_Left_in => Audio_Left_in,
Audio_Right_in => Audio_Right_in,
SAMPLE_TRIG => SAMPLE_TRIG,
slv_reg0 => slv_reg0,
slv_reg1 => slv_reg1,
slv_reg2 => slv_reg2,
slv_reg3 => slv_reg3,
slv_reg4 => slv_reg4,
slv_reg5 => slv_reg5,
slv_reg6 => slv_reg6,
slv_reg7 => slv_reg7,
slv_reg8 => slv_reg8,
slv_reg9 => slv_reg9,
slv_reg10 => slv_reg10,
slv_reg11 => slv_reg11,
slv_reg12 => slv_reg12,
slv_reg13 => slv_reg13,
slv_reg14 => slv_reg14,
slv_reg15 => slv_reg15,
slv_reg16 => slv_reg16,
slv_reg17 => slv_reg17,
slv_reg18 => slv_reg18,
slv_reg19 => slv_reg19,
slv_reg20 => slv_reg20,
slv_reg21 => slv_reg21,
slv_reg22 => slv_reg22,
slv_reg23 => slv_reg23,
slv_reg24 => slv_reg24,
slv_reg25 => slv_reg25,
slv_reg27 => slv_reg27
);
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else (others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
| mit | be8cba9a88e8eab182f0bd70bb3c4642 | 0.553453 | 3.309064 | false | false | false | false |
freecores/gpib_controller | vhdl/src/wrapper/SettingsReg0.vhd | 1 | 2,194 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: SettingsReg0
-- Date:2011-11-09
-- Author: Andrzej Paluch
--
-- Description ${cursor}
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity SettingsReg0 is
port (
reset : in std_logic;
strobe : in std_logic;
data_in : in std_logic_vector (15 downto 0);
data_out : out std_logic_vector (15 downto 0);
------------- gpib -----------------------------
isLE_TE : out std_logic;
lpeUsed : out std_logic;
fixedPpLine : out std_logic_vector (2 downto 0);
eosUsed : out std_logic;
eosMark : out std_logic_vector (7 downto 0);
lon : out std_logic;
ton : out std_logic
);
end SettingsReg0;
architecture arch of SettingsReg0 is
signal inner_buf : std_logic_vector (15 downto 0);
begin
data_out <= inner_buf;
isLE_TE <= inner_buf(0);
lpeUsed <= inner_buf(1);
fixedPpLine <= inner_buf(4 downto 2);
eosUsed <= inner_buf(5);
eosMark <= inner_buf(13 downto 6);
lon <= inner_buf(14);
ton <= inner_buf(15);
process (reset, strobe) begin
if reset = '1' then
inner_buf <= "0000000000000000";
elsif rising_edge(strobe) then
inner_buf <= data_in;
end if;
end process;
end arch;
| gpl-3.0 | 1366540e7db7851a4b4a29c61c141a88 | 0.613036 | 3.706081 | false | false | false | false |
tomoasleep/vhdl_test_script | examples/illigal_dut.vhd | 1 | 785 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library work;
use work.not_exist.all;
entity datapath is
port (
input : in std_logic_vector(1 downto 0);
clk : in std_logic;
output : out std_logic_vector(2 downto 0)
);
end datapath;
architecture behave of datapath is
component state_machine
port(
input: in std_logic;
reset: in std_logic;
state : out std_logic_vector(2 downto 0);
clk : in std_logic
);
end component;
signal stin: std_logic := '0';
signal streset: std_logic := '1';
begin -- behave
st: state_machine port map (
input => stin,
reset => streset,
clk => clk,
state => output);
streset <= input(1);
stin <= input(0);
end behave;
| mit | 16d9a629eaa458a618e6152d7b5bb8c0 | 0.634395 | 3.14 | false | false | false | false |
Nooxet/embedded_bruteforce | brutus_system/hdl/elaborate/clock_generator_0_v4_03_a/hdl/vhdl/clock_generator.vhd | 1 | 37,674 | ------------------------------------------------------------------------------
-- C:/Users/ael10jso/Xilinx/embedded_bruteforce/brutus_system/hdl/elaborate/clock_generator_0_v4_03_a/hdl/vhdl/clock_generator.vhd
------------------------------------------------------------------------------
-- ClkGen Wrapper HDL file generated by ClkGen's TCL generator
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
library Unisim;
use Unisim.vcomponents.all;
library clock_generator_v4_03_a;
use clock_generator_v4_03_a.all;
entity clock_generator is
generic (
C_FAMILY : string := "spartan6" ;
C_DEVICE : string := "6slx16";
C_PACKAGE : string := "csg324";
C_SPEEDGRADE : string := "-3";
C_CLK_GEN : string := "PASSED"
);
port (
-- clock generation
CLKIN : in std_logic;
CLKOUT0 : out std_logic;
CLKOUT1 : out std_logic;
CLKOUT2 : out std_logic;
CLKOUT3 : out std_logic;
CLKOUT4 : out std_logic;
CLKOUT5 : out std_logic;
CLKOUT6 : out std_logic;
CLKOUT7 : out std_logic;
CLKOUT8 : out std_logic;
CLKOUT9 : out std_logic;
CLKOUT10 : out std_logic;
CLKOUT11 : out std_logic;
CLKOUT12 : out std_logic;
CLKOUT13 : out std_logic;
CLKOUT14 : out std_logic;
CLKOUT15 : out std_logic;
-- external feedback
CLKFBIN : in std_logic;
CLKFBOUT : out std_logic;
-- variable phase shift
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
PSDONE : out std_logic;
-- reset
RST : in std_logic;
LOCKED : out std_logic
);
end clock_generator;
architecture STRUCTURE of clock_generator is
----------------------------------------------------------------------------
-- Components ( copy from entity, exact the same in low level parameters )
----------------------------------------------------------------------------
component pll_module is
generic (
C_BANDWIDTH : string := "OPTIMIZED";
C_CLKFBOUT_MULT : integer := 1;
C_CLKFBOUT_PHASE : real := 0.0;
C_CLKIN1_PERIOD : real := 0.000;
-- C_CLKIN2_PERIOD : real := 0.000;
C_CLKOUT0_DIVIDE : integer := 1;
C_CLKOUT0_DUTY_CYCLE : real := 0.5;
C_CLKOUT0_PHASE : real := 0.0;
C_CLKOUT1_DIVIDE : integer := 1;
C_CLKOUT1_DUTY_CYCLE : real := 0.5;
C_CLKOUT1_PHASE : real := 0.0;
C_CLKOUT2_DIVIDE : integer := 1;
C_CLKOUT2_DUTY_CYCLE : real := 0.5;
C_CLKOUT2_PHASE : real := 0.0;
C_CLKOUT3_DIVIDE : integer := 1;
C_CLKOUT3_DUTY_CYCLE : real := 0.5;
C_CLKOUT3_PHASE : real := 0.0;
C_CLKOUT4_DIVIDE : integer := 1;
C_CLKOUT4_DUTY_CYCLE : real := 0.5;
C_CLKOUT4_PHASE : real := 0.0;
C_CLKOUT5_DIVIDE : integer := 1;
C_CLKOUT5_DUTY_CYCLE : real := 0.5;
C_CLKOUT5_PHASE : real := 0.0;
C_COMPENSATION : string := "SYSTEM_SYNCHRONOUS";
C_DIVCLK_DIVIDE : integer := 1;
-- C_EN_REL : boolean := false;
-- C_PLL_PMCD_MODE : boolean := false;
C_REF_JITTER : real := 0.100;
C_RESET_ON_LOSS_OF_LOCK : boolean := false;
C_RST_DEASSERT_CLK : string := "CLKIN1";
C_CLKOUT0_DESKEW_ADJUST : string := "NONE";
C_CLKOUT1_DESKEW_ADJUST : string := "NONE";
C_CLKOUT2_DESKEW_ADJUST : string := "NONE";
C_CLKOUT3_DESKEW_ADJUST : string := "NONE";
C_CLKOUT4_DESKEW_ADJUST : string := "NONE";
C_CLKOUT5_DESKEW_ADJUST : string := "NONE";
C_CLKFBOUT_DESKEW_ADJUST : string := "NONE";
C_CLKIN1_BUF : boolean := false;
-- C_CLKIN2_BUF : boolean := false;
C_CLKFBOUT_BUF : boolean := false;
C_CLKOUT0_BUF : boolean := false;
C_CLKOUT1_BUF : boolean := false;
C_CLKOUT2_BUF : boolean := false;
C_CLKOUT3_BUF : boolean := false;
C_CLKOUT4_BUF : boolean := false;
C_CLKOUT5_BUF : boolean := false;
C_EXT_RESET_HIGH : integer := 1;
C_FAMILY : string := "spartan6"
);
port (
CLKFBDCM : out std_logic;
CLKFBOUT : out std_logic;
CLKOUT0 : out std_logic;
CLKOUT1 : out std_logic;
CLKOUT2 : out std_logic;
CLKOUT3 : out std_logic;
CLKOUT4 : out std_logic;
CLKOUT5 : out std_logic;
CLKOUTDCM0 : out std_logic;
CLKOUTDCM1 : out std_logic;
CLKOUTDCM2 : out std_logic;
CLKOUTDCM3 : out std_logic;
CLKOUTDCM4 : out std_logic;
CLKOUTDCM5 : out std_logic;
-- DO : out std_logic_vector (15 downto 0);
-- DRDY : out std_logic;
LOCKED : out std_logic;
CLKFBIN : in std_logic;
CLKIN1 : in std_logic;
-- CLKIN2 : in std_logic;
-- CLKINSEL : in std_logic;
-- DADDR : in std_logic_vector (4 downto 0);
-- DCLK : in std_logic;
-- DEN : in std_logic;
-- DI : in std_logic_vector (15 downto 0);
-- DWE : in std_logic;
-- REL : in std_logic;
RST : in std_logic
);
end component;
----------------------------------------------------------------------------
-- Functions
----------------------------------------------------------------------------
-- Note : The string functions are put here to remove dependency to other pcore level libraries
function UpperCase_Char(char : character) return character is
begin
-- If char is not an upper case letter then return char
if char < 'a' or char > 'z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'a' => return 'A'; when 'b' => return 'B'; when 'c' => return 'C'; when 'd' => return 'D';
when 'e' => return 'E'; when 'f' => return 'F'; when 'g' => return 'G'; when 'h' => return 'H';
when 'i' => return 'I'; when 'j' => return 'J'; when 'k' => return 'K'; when 'l' => return 'L';
when 'm' => return 'M'; when 'n' => return 'N'; when 'o' => return 'O'; when 'p' => return 'P';
when 'q' => return 'Q'; when 'r' => return 'R'; when 's' => return 'S'; when 't' => return 'T';
when 'u' => return 'U'; when 'v' => return 'V'; when 'w' => return 'W'; when 'x' => return 'X';
when 'y' => return 'Y'; when 'z' => return 'Z';
when others => return char;
end case;
end UpperCase_Char;
function UpperCase_String (s : string) return string is
variable res : string(s'range);
begin -- function LoweerCase_String
for I in s'range loop
res(I) := UpperCase_Char(s(I));
end loop; -- I
return res;
end function UpperCase_String;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
function equalString( str1, str2 : string ) return boolean is
constant len1 : integer := str1'length;
constant len2 : integer := str2'length;
variable equal : boolean := true;
begin
if not (len1 = len2) then
equal := false;
else
for i in str1'range loop
if not (UpperCase_Char(str1(i)) = UpperCase_Char(str2(i))) then
equal := false;
end if;
end loop;
end if;
return equal;
end equalString;
----------------------------------------------------------------------------
-- Signals
----------------------------------------------------------------------------
-- signals: gnd
signal net_gnd0 : std_logic;
signal net_gnd1 : std_logic_vector(0 to 0);
signal net_gnd16 : std_logic_vector(0 to 15);
-- signals: vdd
signal net_vdd0 : std_logic;
-- signals : PLL0 wrapper
signal SIG_PLL0_CLKFBDCM : std_logic;
signal SIG_PLL0_CLKFBOUT : std_logic;
signal SIG_PLL0_CLKOUT0 : std_logic;
signal SIG_PLL0_CLKOUT1 : std_logic;
signal SIG_PLL0_CLKOUT2 : std_logic;
signal SIG_PLL0_CLKOUT3 : std_logic;
signal SIG_PLL0_CLKOUT4 : std_logic;
signal SIG_PLL0_CLKOUT5 : std_logic;
signal SIG_PLL0_CLKOUTDCM0 : std_logic;
signal SIG_PLL0_CLKOUTDCM1 : std_logic;
signal SIG_PLL0_CLKOUTDCM2 : std_logic;
signal SIG_PLL0_CLKOUTDCM3 : std_logic;
signal SIG_PLL0_CLKOUTDCM4 : std_logic;
signal SIG_PLL0_CLKOUTDCM5 : std_logic;
signal SIG_PLL0_LOCKED : std_logic;
signal SIG_PLL0_CLKFBIN : std_logic;
signal SIG_PLL0_CLKIN1 : std_logic;
signal SIG_PLL0_RST : std_logic;
signal SIG_PLL0_CLKFBOUT_BUF : std_logic;
signal SIG_PLL0_CLKOUT0_BUF : std_logic;
signal SIG_PLL0_CLKOUT1_BUF : std_logic;
signal SIG_PLL0_CLKOUT2_BUF : std_logic;
signal SIG_PLL0_CLKOUT3_BUF : std_logic;
signal SIG_PLL0_CLKOUT4_BUF : std_logic;
signal SIG_PLL0_CLKOUT5_BUF : std_logic;
begin
----------------------------------------------------------------------------
-- GND and VCC signals
----------------------------------------------------------------------------
net_gnd0 <= '0';
net_gnd1(0 to 0) <= B"0";
net_gnd16(0 to 15) <= B"0000000000000000";
net_vdd0 <= '1';
----------------------------------------------------------------------------
-- DCM wrappers
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- PLL wrappers
----------------------------------------------------------------------------
-- PLL0 wrapper
PLL0_INST : pll_module
generic map (
C_BANDWIDTH => "OPTIMIZED",
C_CLKFBOUT_MULT => 10,
C_CLKFBOUT_PHASE => 0.0,
C_CLKIN1_PERIOD => 10.000000,
C_CLKOUT0_DIVIDE => 20,
C_CLKOUT0_DUTY_CYCLE => 0.5,
C_CLKOUT0_PHASE => 0.0000,
C_CLKOUT1_DIVIDE => 1,
C_CLKOUT1_DUTY_CYCLE => 0.5,
C_CLKOUT1_PHASE => 0.0,
C_CLKOUT2_DIVIDE => 1,
C_CLKOUT2_DUTY_CYCLE => 0.5,
C_CLKOUT2_PHASE => 0.0,
C_CLKOUT3_DIVIDE => 1,
C_CLKOUT3_DUTY_CYCLE => 0.5,
C_CLKOUT3_PHASE => 0.0,
C_CLKOUT4_DIVIDE => 1,
C_CLKOUT4_DUTY_CYCLE => 0.5,
C_CLKOUT4_PHASE => 0.0,
C_CLKOUT5_DIVIDE => 1,
C_CLKOUT5_DUTY_CYCLE => 0.5,
C_CLKOUT5_PHASE => 0.0,
C_COMPENSATION => "SYSTEM_SYNCHRONOUS",
C_DIVCLK_DIVIDE => 1,
C_REF_JITTER => 0.100,
C_RESET_ON_LOSS_OF_LOCK => false,
C_RST_DEASSERT_CLK => "CLKIN1",
C_CLKOUT0_DESKEW_ADJUST => "NONE",
C_CLKOUT1_DESKEW_ADJUST => "NONE",
C_CLKOUT2_DESKEW_ADJUST => "NONE",
C_CLKOUT3_DESKEW_ADJUST => "NONE",
C_CLKOUT4_DESKEW_ADJUST => "NONE",
C_CLKOUT5_DESKEW_ADJUST => "NONE",
C_CLKFBOUT_DESKEW_ADJUST => "NONE",
C_CLKIN1_BUF => false,
C_CLKFBOUT_BUF => false,
C_CLKOUT0_BUF => false,
C_CLKOUT1_BUF => false,
C_CLKOUT2_BUF => false,
C_CLKOUT3_BUF => false,
C_CLKOUT4_BUF => false,
C_CLKOUT5_BUF => false,
C_EXT_RESET_HIGH => 1,
C_FAMILY => "spartan6"
)
port map (
CLKFBDCM => SIG_PLL0_CLKFBDCM,
CLKFBOUT => SIG_PLL0_CLKFBOUT,
CLKOUT0 => SIG_PLL0_CLKOUT0,
CLKOUT1 => SIG_PLL0_CLKOUT1,
CLKOUT2 => SIG_PLL0_CLKOUT2,
CLKOUT3 => SIG_PLL0_CLKOUT3,
CLKOUT4 => SIG_PLL0_CLKOUT4,
CLKOUT5 => SIG_PLL0_CLKOUT5,
CLKOUTDCM0 => SIG_PLL0_CLKOUTDCM0,
CLKOUTDCM1 => SIG_PLL0_CLKOUTDCM1,
CLKOUTDCM2 => SIG_PLL0_CLKOUTDCM2,
CLKOUTDCM3 => SIG_PLL0_CLKOUTDCM3,
CLKOUTDCM4 => SIG_PLL0_CLKOUTDCM4,
CLKOUTDCM5 => SIG_PLL0_CLKOUTDCM5,
-- DO
-- DRDY
LOCKED => SIG_PLL0_LOCKED,
CLKFBIN => SIG_PLL0_CLKFBIN,
CLKIN1 => SIG_PLL0_CLKIN1,
-- CLKIN2
-- CLKINSEL
-- DADDR
-- DCLK
-- DEN
-- DI
-- DWE
-- REL
RST => SIG_PLL0_RST
);
-- wrapper of clkout : CLKOUT0
PLL0_CLKOUT0_BUFG_INST : BUFG
port map (
I => SIG_PLL0_CLKOUT0,
O => SIG_PLL0_CLKOUT0_BUF
);
-- wrapper of clkout : CLKOUT1
SIG_PLL0_CLKOUT1_BUF <= SIG_PLL0_CLKOUT1;
-- wrapper of clkout : CLKOUT2
SIG_PLL0_CLKOUT2_BUF <= SIG_PLL0_CLKOUT2;
-- wrapper of clkout : CLKOUT3
SIG_PLL0_CLKOUT3_BUF <= SIG_PLL0_CLKOUT3;
-- wrapper of clkout : CLKOUT4
SIG_PLL0_CLKOUT4_BUF <= SIG_PLL0_CLKOUT4;
-- wrapper of clkout : CLKOUT5
SIG_PLL0_CLKOUT5_BUF <= SIG_PLL0_CLKOUT5;
-- wrapper of clkout : CLKFBOUT
PLL0_CLKFBOUT_BUFG_INST : BUFG
port map (
I => SIG_PLL0_CLKFBOUT,
O => SIG_PLL0_CLKFBOUT_BUF
);
----------------------------------------------------------------------------
-- MMCM wrappers
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- PLLE wrappers
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- DCMs CLKIN, CLKFB and RST signal connection
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- PLLs CLKIN1, CLKFBIN and RST signal connection
----------------------------------------------------------------------------
-- PLL0 CLKIN1
SIG_PLL0_CLKIN1 <= CLKIN;
-- PLL0 CLKFBIN
SIG_PLL0_CLKFBIN <= SIG_PLL0_CLKFBOUT;
-- PLL0 RST
SIG_PLL0_RST <= RST;
----------------------------------------------------------------------------
-- MMCMs CLKIN1, CLKFBIN, RST and Variable_Phase_Control signal connection
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- PLLEs CLKIN1, CLKFBIN, RST and Variable_Phase_Control signal connection
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- CLKGEN CLKOUT, CLKFBOUT and LOCKED signal connection
----------------------------------------------------------------------------
-- CLKGEN CLKOUT
CLKOUT0 <= SIG_PLL0_CLKOUT0_BUF;
CLKOUT1 <= '0';
CLKOUT2 <= '0';
CLKOUT3 <= '0';
CLKOUT4 <= '0';
CLKOUT5 <= '0';
CLKOUT6 <= '0';
CLKOUT7 <= '0';
CLKOUT8 <= '0';
CLKOUT9 <= '0';
CLKOUT10 <= '0';
CLKOUT11 <= '0';
CLKOUT12 <= '0';
CLKOUT13 <= '0';
CLKOUT14 <= '0';
CLKOUT15 <= '0';
-- CLKGEN CLKFBOUT
-- CLKGEN LOCKED
LOCKED <= SIG_PLL0_LOCKED;
end architecture STRUCTURE;
------------------------------------------------------------------------------
-- High level parameters
------------------------------------------------------------------------------
-- C_CLK_GEN = PASSED
-- C_ELABORATE_DIR =
-- C_ELABORATE_RES = NOT_SET
-- C_FAMILY = spartan6
-- C_DEVICE = 6slx16
-- C_PACKAGE = csg324
-- C_SPEEDGRADE = -3
----------------------------------------
-- C_EXTRA_MMCM_FOR_DESKEW =
-- C_MMCMExtra_CLKIN_FREQ =
-- C_MMCMExtra_CLKOUT0 =
-- C_MMCMExtra_CLKOUT1 =
-- C_MMCMExtra_CLKOUT2 =
-- C_MMCMExtra_CLKOUT3 =
-- C_MMCMExtra_CLKOUT4 =
-- C_MMCMExtra_CLKOUT5 =
-- C_MMCMExtra_CLKOUT6 =
-- C_MMCMExtra_CLKOUT7 =
-- C_MMCMExtra_CLKOUT8 =
-- C_MMCMExtra_CLKOUT9 =
-- C_MMCMExtra_CLKOUT10 =
-- C_MMCMExtra_CLKOUT11 =
-- C_MMCMExtra_CLKOUT12 =
-- C_MMCMExtra_CLKOUT13 =
-- C_MMCMExtra_CLKOUT14 =
-- C_MMCMExtra_CLKOUT15 =
-- C_MMCMExtra_CLKFBOUT_MULT =
-- C_MMCMExtra_DIVCLK_DIVIDE =
-- C_MMCMExtra_CLKOUT0_DIVIDE =
-- C_MMCMExtra_CLKOUT1_DIVIDE =
-- C_MMCMExtra_CLKOUT2_DIVIDE =
-- C_MMCMExtra_CLKOUT3_DIVIDE =
-- C_MMCMExtra_CLKOUT4_DIVIDE =
-- C_MMCMExtra_CLKOUT5_DIVIDE =
-- C_MMCMExtra_CLKOUT6_DIVIDE =
-- C_MMCMExtra_CLKOUT0_BUF =
-- C_MMCMExtra_CLKOUT1_BUF =
-- C_MMCMExtra_CLKOUT2_BUF =
-- C_MMCMExtra_CLKOUT3_BUF =
-- C_MMCMExtra_CLKOUT4_BUF =
-- C_MMCMExtra_CLKOUT5_BUF =
-- C_MMCMExtra_CLKOUT6_BUF =
-- C_MMCMExtra_CLKFBOUT_BUF =
-- C_MMCMExtra_CLKOUT0_PHASE =
-- C_MMCMExtra_CLKOUT1_PHASE =
-- C_MMCMExtra_CLKOUT2_PHASE =
-- C_MMCMExtra_CLKOUT3_PHASE =
-- C_MMCMExtra_CLKOUT4_PHASE =
-- C_MMCMExtra_CLKOUT5_PHASE =
-- C_MMCMExtra_CLKOUT6_PHASE =
----------------------------------------
-- C_CLKIN_FREQ = 100000000
-- C_CLKOUT0_FREQ = 50000000
-- C_CLKOUT0_PHASE = 0
-- C_CLKOUT0_GROUP = NONE
-- C_CLKOUT0_BUF = TRUE
-- C_CLKOUT0_VARIABLE_PHASE = FALSE
-- C_CLKOUT1_FREQ = 0
-- C_CLKOUT1_PHASE = 0
-- C_CLKOUT1_GROUP = NONE
-- C_CLKOUT1_BUF = TRUE
-- C_CLKOUT1_VARIABLE_PHASE = FALSE
-- C_CLKOUT2_FREQ = 0
-- C_CLKOUT2_PHASE = 0
-- C_CLKOUT2_GROUP = NONE
-- C_CLKOUT2_BUF = TRUE
-- C_CLKOUT2_VARIABLE_PHASE = FALSE
-- C_CLKOUT3_FREQ = 0
-- C_CLKOUT3_PHASE = 0
-- C_CLKOUT3_GROUP = NONE
-- C_CLKOUT3_BUF = TRUE
-- C_CLKOUT3_VARIABLE_PHASE = FALSE
-- C_CLKOUT4_FREQ = 0
-- C_CLKOUT4_PHASE = 0
-- C_CLKOUT4_GROUP = NONE
-- C_CLKOUT4_BUF = TRUE
-- C_CLKOUT4_VARIABLE_PHASE = FALSE
-- C_CLKOUT5_FREQ = 0
-- C_CLKOUT5_PHASE = 0
-- C_CLKOUT5_GROUP = NONE
-- C_CLKOUT5_BUF = TRUE
-- C_CLKOUT5_VARIABLE_PHASE = FALSE
-- C_CLKOUT6_FREQ = 0
-- C_CLKOUT6_PHASE = 0
-- C_CLKOUT6_GROUP = NONE
-- C_CLKOUT6_BUF = TRUE
-- C_CLKOUT6_VARIABLE_PHASE = FALSE
-- C_CLKOUT7_FREQ = 0
-- C_CLKOUT7_PHASE = 0
-- C_CLKOUT7_GROUP = NONE
-- C_CLKOUT7_BUF = TRUE
-- C_CLKOUT7_VARIABLE_PHASE = FALSE
-- C_CLKOUT8_FREQ = 0
-- C_CLKOUT8_PHASE = 0
-- C_CLKOUT8_GROUP = NONE
-- C_CLKOUT8_BUF = TRUE
-- C_CLKOUT8_VARIABLE_PHASE = FALSE
-- C_CLKOUT9_FREQ = 0
-- C_CLKOUT9_PHASE = 0
-- C_CLKOUT9_GROUP = NONE
-- C_CLKOUT9_BUF = TRUE
-- C_CLKOUT9_VARIABLE_PHASE = FALSE
-- C_CLKOUT10_FREQ = 0
-- C_CLKOUT10_PHASE = 0
-- C_CLKOUT10_GROUP = NONE
-- C_CLKOUT10_BUF = TRUE
-- C_CLKOUT10_VARIABLE_PHASE = FALSE
-- C_CLKOUT11_FREQ = 0
-- C_CLKOUT11_PHASE = 0
-- C_CLKOUT11_GROUP = NONE
-- C_CLKOUT11_BUF = TRUE
-- C_CLKOUT11_VARIABLE_PHASE = FALSE
-- C_CLKOUT12_FREQ = 0
-- C_CLKOUT12_PHASE = 0
-- C_CLKOUT12_GROUP = NONE
-- C_CLKOUT12_BUF = TRUE
-- C_CLKOUT12_VARIABLE_PHASE = FALSE
-- C_CLKOUT13_FREQ = 0
-- C_CLKOUT13_PHASE = 0
-- C_CLKOUT13_GROUP = NONE
-- C_CLKOUT13_BUF = TRUE
-- C_CLKOUT13_VARIABLE_PHASE = FALSE
-- C_CLKOUT14_FREQ = 0
-- C_CLKOUT14_PHASE = 0
-- C_CLKOUT14_GROUP = NONE
-- C_CLKOUT14_BUF = TRUE
-- C_CLKOUT14_VARIABLE_PHASE = FALSE
-- C_CLKOUT15_FREQ = 0
-- C_CLKOUT15_PHASE = 0
-- C_CLKOUT15_GROUP = NONE
-- C_CLKOUT15_BUF = TRUE
-- C_CLKOUT15_VARIABLE_PHASE = FALSE
----------------------------------------
-- C_CLKFBIN_FREQ = 0
-- C_CLKFBIN_DESKEW = NONE
-- C_CLKFBOUT_FREQ = 0
-- C_CLKFBOUT_GROUP = NONE
-- C_CLKFBOUT_BUF = TRUE
----------------------------------------
-- C_PSDONE_GROUP = NONE
------------------------------------------------------------------------------
-- Low level parameters
------------------------------------------------------------------------------
-- C_CLKOUT0_MODULE = PLL0
-- C_CLKOUT0_PORT = CLKOUT0B
-- C_CLKOUT1_MODULE = NONE
-- C_CLKOUT1_PORT = NONE
-- C_CLKOUT2_MODULE = NONE
-- C_CLKOUT2_PORT = NONE
-- C_CLKOUT3_MODULE = NONE
-- C_CLKOUT3_PORT = NONE
-- C_CLKOUT4_MODULE = NONE
-- C_CLKOUT4_PORT = NONE
-- C_CLKOUT5_MODULE = NONE
-- C_CLKOUT5_PORT = NONE
-- C_CLKOUT6_MODULE = NONE
-- C_CLKOUT6_PORT = NONE
-- C_CLKOUT7_MODULE = NONE
-- C_CLKOUT7_PORT = NONE
-- C_CLKOUT8_MODULE = NONE
-- C_CLKOUT8_PORT = NONE
-- C_CLKOUT9_MODULE = NONE
-- C_CLKOUT9_PORT = NONE
-- C_CLKOUT10_MODULE = NONE
-- C_CLKOUT10_PORT = NONE
-- C_CLKOUT11_MODULE = NONE
-- C_CLKOUT11_PORT = NONE
-- C_CLKOUT12_MODULE = NONE
-- C_CLKOUT12_PORT = NONE
-- C_CLKOUT13_MODULE = NONE
-- C_CLKOUT13_PORT = NONE
-- C_CLKOUT14_MODULE = NONE
-- C_CLKOUT14_PORT = NONE
-- C_CLKOUT15_MODULE = NONE
-- C_CLKOUT15_PORT = NONE
----------------------------------------
-- C_CLKFBOUT_MODULE = NONE
-- C_CLKFBOUT_PORT = NONE
-- C_CLKFBOUT_get_clkgen_dcm_default_params = NONE
----------------------------------------
-- C_PSDONE_MODULE = NONE
----------------------------------------
-- C_DCM0_DFS_FREQUENCY_MODE = "LOW"
-- C_DCM0_DLL_FREQUENCY_MODE = "LOW"
-- C_DCM0_DUTY_CYCLE_CORRECTION = true
-- C_DCM0_CLKIN_DIVIDE_BY_2 = false
-- C_DCM0_CLK_FEEDBACK = "1X"
-- C_DCM0_CLKOUT_PHASE_SHIFT = "NONE"
-- C_DCM0_DSS_MODE = "NONE"
-- C_DCM0_STARTUP_WAIT = false
-- C_DCM0_PHASE_SHIFT = 0
-- C_DCM0_CLKFX_MULTIPLY = 4
-- C_DCM0_CLKFX_DIVIDE = 1
-- C_DCM0_CLKDV_DIVIDE = 2.0
-- C_DCM0_CLKIN_PERIOD = 41.6666666
-- C_DCM0_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"
-- C_DCM0_CLKIN_BUF = false
-- C_DCM0_CLKFB_BUF = false
-- C_DCM0_CLK0_BUF = false
-- C_DCM0_CLK90_BUF = false
-- C_DCM0_CLK180_BUF = false
-- C_DCM0_CLK270_BUF = false
-- C_DCM0_CLKDV_BUF = false
-- C_DCM0_CLK2X_BUF = false
-- C_DCM0_CLK2X180_BUF = false
-- C_DCM0_CLKFX_BUF = false
-- C_DCM0_CLKFX180_BUF = false
-- C_DCM0_EXT_RESET_HIGH = 1
-- C_DCM0_FAMILY = "spartan6"
-- C_DCM0_CLKIN_MODULE = NONE
-- C_DCM0_CLKIN_PORT = NONE
-- C_DCM0_CLKFB_MODULE = NONE
-- C_DCM0_CLKFB_PORT = NONE
-- C_DCM0_RST_MODULE = NONE
-- C_DCM1_DFS_FREQUENCY_MODE = "LOW"
-- C_DCM1_DLL_FREQUENCY_MODE = "LOW"
-- C_DCM1_DUTY_CYCLE_CORRECTION = true
-- C_DCM1_CLKIN_DIVIDE_BY_2 = false
-- C_DCM1_CLK_FEEDBACK = "1X"
-- C_DCM1_CLKOUT_PHASE_SHIFT = "NONE"
-- C_DCM1_DSS_MODE = "NONE"
-- C_DCM1_STARTUP_WAIT = false
-- C_DCM1_PHASE_SHIFT = 0
-- C_DCM1_CLKFX_MULTIPLY = 4
-- C_DCM1_CLKFX_DIVIDE = 1
-- C_DCM1_CLKDV_DIVIDE = 2.0
-- C_DCM1_CLKIN_PERIOD = 41.6666666
-- C_DCM1_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"
-- C_DCM1_CLKIN_BUF = false
-- C_DCM1_CLKFB_BUF = false
-- C_DCM1_CLK0_BUF = false
-- C_DCM1_CLK90_BUF = false
-- C_DCM1_CLK180_BUF = false
-- C_DCM1_CLK270_BUF = false
-- C_DCM1_CLKDV_BUF = false
-- C_DCM1_CLK2X_BUF = false
-- C_DCM1_CLK2X180_BUF = false
-- C_DCM1_CLKFX_BUF = false
-- C_DCM1_CLKFX180_BUF = false
-- C_DCM1_EXT_RESET_HIGH = 1
-- C_DCM1_FAMILY = "spartan6"
-- C_DCM1_CLKIN_MODULE = NONE
-- C_DCM1_CLKIN_PORT = NONE
-- C_DCM1_CLKFB_MODULE = NONE
-- C_DCM1_CLKFB_PORT = NONE
-- C_DCM1_RST_MODULE = NONE
-- C_DCM2_DFS_FREQUENCY_MODE = "LOW"
-- C_DCM2_DLL_FREQUENCY_MODE = "LOW"
-- C_DCM2_DUTY_CYCLE_CORRECTION = true
-- C_DCM2_CLKIN_DIVIDE_BY_2 = false
-- C_DCM2_CLK_FEEDBACK = "1X"
-- C_DCM2_CLKOUT_PHASE_SHIFT = "NONE"
-- C_DCM2_DSS_MODE = "NONE"
-- C_DCM2_STARTUP_WAIT = false
-- C_DCM2_PHASE_SHIFT = 0
-- C_DCM2_CLKFX_MULTIPLY = 4
-- C_DCM2_CLKFX_DIVIDE = 1
-- C_DCM2_CLKDV_DIVIDE = 2.0
-- C_DCM2_CLKIN_PERIOD = 41.6666666
-- C_DCM2_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"
-- C_DCM2_CLKIN_BUF = false
-- C_DCM2_CLKFB_BUF = false
-- C_DCM2_CLK0_BUF = false
-- C_DCM2_CLK90_BUF = false
-- C_DCM2_CLK180_BUF = false
-- C_DCM2_CLK270_BUF = false
-- C_DCM2_CLKDV_BUF = false
-- C_DCM2_CLK2X_BUF = false
-- C_DCM2_CLK2X180_BUF = false
-- C_DCM2_CLKFX_BUF = false
-- C_DCM2_CLKFX180_BUF = false
-- C_DCM2_EXT_RESET_HIGH = 1
-- C_DCM2_FAMILY = "spartan6"
-- C_DCM2_CLKIN_MODULE = NONE
-- C_DCM2_CLKIN_PORT = NONE
-- C_DCM2_CLKFB_MODULE = NONE
-- C_DCM2_CLKFB_PORT = NONE
-- C_DCM2_RST_MODULE = NONE
-- C_DCM3_DFS_FREQUENCY_MODE = "LOW"
-- C_DCM3_DLL_FREQUENCY_MODE = "LOW"
-- C_DCM3_DUTY_CYCLE_CORRECTION = true
-- C_DCM3_CLKIN_DIVIDE_BY_2 = false
-- C_DCM3_CLK_FEEDBACK = "1X"
-- C_DCM3_CLKOUT_PHASE_SHIFT = "NONE"
-- C_DCM3_DSS_MODE = "NONE"
-- C_DCM3_STARTUP_WAIT = false
-- C_DCM3_PHASE_SHIFT = 0
-- C_DCM3_CLKFX_MULTIPLY = 4
-- C_DCM3_CLKFX_DIVIDE = 1
-- C_DCM3_CLKDV_DIVIDE = 2.0
-- C_DCM3_CLKIN_PERIOD = 41.6666666
-- C_DCM3_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"
-- C_DCM3_CLKIN_BUF = false
-- C_DCM3_CLKFB_BUF = false
-- C_DCM3_CLK0_BUF = false
-- C_DCM3_CLK90_BUF = false
-- C_DCM3_CLK180_BUF = false
-- C_DCM3_CLK270_BUF = false
-- C_DCM3_CLKDV_BUF = false
-- C_DCM3_CLK2X_BUF = false
-- C_DCM3_CLK2X180_BUF = false
-- C_DCM3_CLKFX_BUF = false
-- C_DCM3_CLKFX180_BUF = false
-- C_DCM3_EXT_RESET_HIGH = 1
-- C_DCM3_FAMILY = "spartan6"
-- C_DCM3_CLKIN_MODULE = NONE
-- C_DCM3_CLKIN_PORT = NONE
-- C_DCM3_CLKFB_MODULE = NONE
-- C_DCM3_CLKFB_PORT = NONE
-- C_DCM3_RST_MODULE = NONE
----------------------------------------
-- C_PLL0_BANDWIDTH = "OPTIMIZED"
-- C_PLL0_CLKFBOUT_MULT = 10
-- C_PLL0_CLKFBOUT_PHASE = 0.0
-- C_PLL0_CLKIN1_PERIOD = 10.000000
-- C_PLL0_CLKOUT0_DIVIDE = 20
-- C_PLL0_CLKOUT0_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT0_PHASE = 0.0000
-- C_PLL0_CLKOUT1_DIVIDE = 1
-- C_PLL0_CLKOUT1_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT1_PHASE = 0.0
-- C_PLL0_CLKOUT2_DIVIDE = 1
-- C_PLL0_CLKOUT2_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT2_PHASE = 0.0
-- C_PLL0_CLKOUT3_DIVIDE = 1
-- C_PLL0_CLKOUT3_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT3_PHASE = 0.0
-- C_PLL0_CLKOUT4_DIVIDE = 1
-- C_PLL0_CLKOUT4_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT4_PHASE = 0.0
-- C_PLL0_CLKOUT5_DIVIDE = 1
-- C_PLL0_CLKOUT5_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT5_PHASE = 0.0
-- C_PLL0_COMPENSATION = "SYSTEM_SYNCHRONOUS"
-- C_PLL0_DIVCLK_DIVIDE = 1
-- C_PLL0_REF_JITTER = 0.100
-- C_PLL0_RESET_ON_LOSS_OF_LOCK = false
-- C_PLL0_RST_DEASSERT_CLK = "CLKIN1"
-- C_PLL0_CLKOUT0_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKOUT1_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKOUT2_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKOUT3_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKOUT4_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKOUT5_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKFBOUT_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKIN1_BUF = false
-- C_PLL0_CLKFBOUT_BUF = TRUE
-- C_PLL0_CLKOUT0_BUF = TRUE
-- C_PLL0_CLKOUT1_BUF = false
-- C_PLL0_CLKOUT2_BUF = false
-- C_PLL0_CLKOUT3_BUF = false
-- C_PLL0_CLKOUT4_BUF = false
-- C_PLL0_CLKOUT5_BUF = false
-- C_PLL0_EXT_RESET_HIGH = 1
-- C_PLL0_FAMILY = "spartan6"
-- C_PLL0_CLKIN1_MODULE = CLKGEN
-- C_PLL0_CLKIN1_PORT = CLKIN
-- C_PLL0_CLKFBIN_MODULE = PLL0
-- C_PLL0_CLKFBIN_PORT = CLKFBOUT
-- C_PLL0_RST_MODULE = CLKGEN
-- C_PLL1_BANDWIDTH = "OPTIMIZED"
-- C_PLL1_CLKFBOUT_MULT = 1
-- C_PLL1_CLKFBOUT_PHASE = 0.0
-- C_PLL1_CLKIN1_PERIOD = 0.000
-- C_PLL1_CLKOUT0_DIVIDE = 1
-- C_PLL1_CLKOUT0_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT0_PHASE = 0.0
-- C_PLL1_CLKOUT1_DIVIDE = 1
-- C_PLL1_CLKOUT1_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT1_PHASE = 0.0
-- C_PLL1_CLKOUT2_DIVIDE = 1
-- C_PLL1_CLKOUT2_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT2_PHASE = 0.0
-- C_PLL1_CLKOUT3_DIVIDE = 1
-- C_PLL1_CLKOUT3_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT3_PHASE = 0.0
-- C_PLL1_CLKOUT4_DIVIDE = 1
-- C_PLL1_CLKOUT4_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT4_PHASE = 0.0
-- C_PLL1_CLKOUT5_DIVIDE = 1
-- C_PLL1_CLKOUT5_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT5_PHASE = 0.0
-- C_PLL1_COMPENSATION = "SYSTEM_SYNCHRONOUS"
-- C_PLL1_DIVCLK_DIVIDE = 1
-- C_PLL1_REF_JITTER = 0.100
-- C_PLL1_RESET_ON_LOSS_OF_LOCK = false
-- C_PLL1_RST_DEASSERT_CLK = "CLKIN1"
-- C_PLL1_CLKOUT0_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKOUT1_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKOUT2_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKOUT3_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKOUT4_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKOUT5_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKFBOUT_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKIN1_BUF = false
-- C_PLL1_CLKFBOUT_BUF = false
-- C_PLL1_CLKOUT0_BUF = false
-- C_PLL1_CLKOUT1_BUF = false
-- C_PLL1_CLKOUT2_BUF = false
-- C_PLL1_CLKOUT3_BUF = false
-- C_PLL1_CLKOUT4_BUF = false
-- C_PLL1_CLKOUT5_BUF = false
-- C_PLL1_EXT_RESET_HIGH = 1
-- C_PLL1_FAMILY = "spartan6"
-- C_PLL1_CLKIN1_MODULE = NONE
-- C_PLL1_CLKIN1_PORT = NONE
-- C_PLL1_CLKFBIN_MODULE = NONE
-- C_PLL1_CLKFBIN_PORT = NONE
-- C_PLL1_RST_MODULE = NONE
----------------------------------------
-- C_MMCM0_BANDWIDTH = "OPTIMIZED"
-- C_MMCM0_CLKFBOUT_MULT_F = 1.0
-- C_MMCM0_CLKFBOUT_PHASE = 0.0
-- C_MMCM0_CLKFBOUT_USE_FINE_PS = false
-- C_MMCM0_CLKIN1_PERIOD = 0.000
-- C_MMCM0_CLKOUT0_DIVIDE_F = 1.0
-- C_MMCM0_CLKOUT0_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT0_PHASE = 0.0
-- C_MMCM0_CLKOUT1_DIVIDE = 1
-- C_MMCM0_CLKOUT1_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT1_PHASE = 0.0
-- C_MMCM0_CLKOUT2_DIVIDE = 1
-- C_MMCM0_CLKOUT2_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT2_PHASE = 0.0
-- C_MMCM0_CLKOUT3_DIVIDE = 1
-- C_MMCM0_CLKOUT3_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT3_PHASE = 0.0
-- C_MMCM0_CLKOUT4_DIVIDE = 1
-- C_MMCM0_CLKOUT4_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT4_PHASE = 0.0
-- C_MMCM0_CLKOUT4_CASCADE = false
-- C_MMCM0_CLKOUT5_DIVIDE = 1
-- C_MMCM0_CLKOUT5_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT5_PHASE = 0.0
-- C_MMCM0_CLKOUT6_DIVIDE = 1
-- C_MMCM0_CLKOUT6_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT6_PHASE = 0.0
-- C_MMCM0_CLKOUT0_USE_FINE_PS = false
-- C_MMCM0_CLKOUT1_USE_FINE_PS = false
-- C_MMCM0_CLKOUT2_USE_FINE_PS = false
-- C_MMCM0_CLKOUT3_USE_FINE_PS = false
-- C_MMCM0_CLKOUT4_USE_FINE_PS = false
-- C_MMCM0_CLKOUT5_USE_FINE_PS = false
-- C_MMCM0_CLKOUT6_USE_FINE_PS = false
-- C_MMCM0_COMPENSATION = "ZHOLD"
-- C_MMCM0_DIVCLK_DIVIDE = 1
-- C_MMCM0_REF_JITTER1 = 0.010
-- C_MMCM0_CLKIN1_BUF = false
-- C_MMCM0_CLKFBOUT_BUF = false
-- C_MMCM0_CLKOUT0_BUF = false
-- C_MMCM0_CLKOUT1_BUF = false
-- C_MMCM0_CLKOUT2_BUF = false
-- C_MMCM0_CLKOUT3_BUF = false
-- C_MMCM0_CLKOUT4_BUF = false
-- C_MMCM0_CLKOUT5_BUF = false
-- C_MMCM0_CLKOUT6_BUF = false
-- C_MMCM0_CLOCK_HOLD = false
-- C_MMCM0_STARTUP_WAIT = false
-- C_MMCM0_EXT_RESET_HIGH = 1
-- C_MMCM0_FAMILY = "spartan6"
-- C_MMCM0_CLKIN1_MODULE = NONE
-- C_MMCM0_CLKIN1_PORT = NONE
-- C_MMCM0_CLKFBIN_MODULE = NONE
-- C_MMCM0_CLKFBIN_PORT = NONE
-- C_MMCM0_RST_MODULE = NONE
-- C_MMCM1_BANDWIDTH = "OPTIMIZED"
-- C_MMCM1_CLKFBOUT_MULT_F = 1.0
-- C_MMCM1_CLKFBOUT_PHASE = 0.0
-- C_MMCM1_CLKFBOUT_USE_FINE_PS = false
-- C_MMCM1_CLKIN1_PERIOD = 0.000
-- C_MMCM1_CLKOUT0_DIVIDE_F = 1.0
-- C_MMCM1_CLKOUT0_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT0_PHASE = 0.0
-- C_MMCM1_CLKOUT1_DIVIDE = 1
-- C_MMCM1_CLKOUT1_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT1_PHASE = 0.0
-- C_MMCM1_CLKOUT2_DIVIDE = 1
-- C_MMCM1_CLKOUT2_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT2_PHASE = 0.0
-- C_MMCM1_CLKOUT3_DIVIDE = 1
-- C_MMCM1_CLKOUT3_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT3_PHASE = 0.0
-- C_MMCM1_CLKOUT4_DIVIDE = 1
-- C_MMCM1_CLKOUT4_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT4_PHASE = 0.0
-- C_MMCM1_CLKOUT4_CASCADE = false
-- C_MMCM1_CLKOUT5_DIVIDE = 1
-- C_MMCM1_CLKOUT5_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT5_PHASE = 0.0
-- C_MMCM1_CLKOUT6_DIVIDE = 1
-- C_MMCM1_CLKOUT6_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT6_PHASE = 0.0
-- C_MMCM1_CLKOUT0_USE_FINE_PS = false
-- C_MMCM1_CLKOUT1_USE_FINE_PS = false
-- C_MMCM1_CLKOUT2_USE_FINE_PS = false
-- C_MMCM1_CLKOUT3_USE_FINE_PS = false
-- C_MMCM1_CLKOUT4_USE_FINE_PS = false
-- C_MMCM1_CLKOUT5_USE_FINE_PS = false
-- C_MMCM1_CLKOUT6_USE_FINE_PS = false
-- C_MMCM1_COMPENSATION = "ZHOLD"
-- C_MMCM1_DIVCLK_DIVIDE = 1
-- C_MMCM1_REF_JITTER1 = 0.010
-- C_MMCM1_CLKIN1_BUF = false
-- C_MMCM1_CLKFBOUT_BUF = false
-- C_MMCM1_CLKOUT0_BUF = false
-- C_MMCM1_CLKOUT1_BUF = false
-- C_MMCM1_CLKOUT2_BUF = false
-- C_MMCM1_CLKOUT3_BUF = false
-- C_MMCM1_CLKOUT4_BUF = false
-- C_MMCM1_CLKOUT5_BUF = false
-- C_MMCM1_CLKOUT6_BUF = false
-- C_MMCM1_CLOCK_HOLD = false
-- C_MMCM1_STARTUP_WAIT = false
-- C_MMCM1_EXT_RESET_HIGH = 1
-- C_MMCM1_FAMILY = "spartan6"
-- C_MMCM1_CLKIN1_MODULE = NONE
-- C_MMCM1_CLKIN1_PORT = NONE
-- C_MMCM1_CLKFBIN_MODULE = NONE
-- C_MMCM1_CLKFBIN_PORT = NONE
-- C_MMCM1_RST_MODULE = NONE
-- C_MMCM2_BANDWIDTH = "OPTIMIZED"
-- C_MMCM2_CLKFBOUT_MULT_F = 1.0
-- C_MMCM2_CLKFBOUT_PHASE = 0.0
-- C_MMCM2_CLKFBOUT_USE_FINE_PS = false
-- C_MMCM2_CLKIN1_PERIOD = 0.000
-- C_MMCM2_CLKOUT0_DIVIDE_F = 1.0
-- C_MMCM2_CLKOUT0_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT0_PHASE = 0.0
-- C_MMCM2_CLKOUT1_DIVIDE = 1
-- C_MMCM2_CLKOUT1_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT1_PHASE = 0.0
-- C_MMCM2_CLKOUT2_DIVIDE = 1
-- C_MMCM2_CLKOUT2_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT2_PHASE = 0.0
-- C_MMCM2_CLKOUT3_DIVIDE = 1
-- C_MMCM2_CLKOUT3_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT3_PHASE = 0.0
-- C_MMCM2_CLKOUT4_DIVIDE = 1
-- C_MMCM2_CLKOUT4_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT4_PHASE = 0.0
-- C_MMCM2_CLKOUT4_CASCADE = false
-- C_MMCM2_CLKOUT5_DIVIDE = 1
-- C_MMCM2_CLKOUT5_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT5_PHASE = 0.0
-- C_MMCM2_CLKOUT6_DIVIDE = 1
-- C_MMCM2_CLKOUT6_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT6_PHASE = 0.0
-- C_MMCM2_CLKOUT0_USE_FINE_PS = false
-- C_MMCM2_CLKOUT1_USE_FINE_PS = false
-- C_MMCM2_CLKOUT2_USE_FINE_PS = false
-- C_MMCM2_CLKOUT3_USE_FINE_PS = false
-- C_MMCM2_CLKOUT4_USE_FINE_PS = false
-- C_MMCM2_CLKOUT5_USE_FINE_PS = false
-- C_MMCM2_CLKOUT6_USE_FINE_PS = false
-- C_MMCM2_COMPENSATION = "ZHOLD"
-- C_MMCM2_DIVCLK_DIVIDE = 1
-- C_MMCM2_REF_JITTER1 = 0.010
-- C_MMCM2_CLKIN1_BUF = false
-- C_MMCM2_CLKFBOUT_BUF = false
-- C_MMCM2_CLKOUT0_BUF = false
-- C_MMCM2_CLKOUT1_BUF = false
-- C_MMCM2_CLKOUT2_BUF = false
-- C_MMCM2_CLKOUT3_BUF = false
-- C_MMCM2_CLKOUT4_BUF = false
-- C_MMCM2_CLKOUT5_BUF = false
-- C_MMCM2_CLKOUT6_BUF = false
-- C_MMCM2_CLOCK_HOLD = false
-- C_MMCM2_STARTUP_WAIT = false
-- C_MMCM2_EXT_RESET_HIGH = 1
-- C_MMCM2_FAMILY = "spartan6"
-- C_MMCM2_CLKIN1_MODULE = NONE
-- C_MMCM2_CLKIN1_PORT = NONE
-- C_MMCM2_CLKFBIN_MODULE = NONE
-- C_MMCM2_CLKFBIN_PORT = NONE
-- C_MMCM2_RST_MODULE = NONE
-- C_MMCM3_BANDWIDTH = "OPTIMIZED"
-- C_MMCM3_CLKFBOUT_MULT_F = 1.0
-- C_MMCM3_CLKFBOUT_PHASE = 0.0
-- C_MMCM3_CLKFBOUT_USE_FINE_PS = false
-- C_MMCM3_CLKIN1_PERIOD = 0.000
-- C_MMCM3_CLKOUT0_DIVIDE_F = 1.0
-- C_MMCM3_CLKOUT0_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT0_PHASE = 0.0
-- C_MMCM3_CLKOUT1_DIVIDE = 1
-- C_MMCM3_CLKOUT1_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT1_PHASE = 0.0
-- C_MMCM3_CLKOUT2_DIVIDE = 1
-- C_MMCM3_CLKOUT2_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT2_PHASE = 0.0
-- C_MMCM3_CLKOUT3_DIVIDE = 1
-- C_MMCM3_CLKOUT3_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT3_PHASE = 0.0
-- C_MMCM3_CLKOUT4_DIVIDE = 1
-- C_MMCM3_CLKOUT4_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT4_PHASE = 0.0
-- C_MMCM3_CLKOUT4_CASCADE = false
-- C_MMCM3_CLKOUT5_DIVIDE = 1
-- C_MMCM3_CLKOUT5_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT5_PHASE = 0.0
-- C_MMCM3_CLKOUT6_DIVIDE = 1
-- C_MMCM3_CLKOUT6_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT6_PHASE = 0.0
-- C_MMCM3_CLKOUT0_USE_FINE_PS = false
-- C_MMCM3_CLKOUT1_USE_FINE_PS = false
-- C_MMCM3_CLKOUT2_USE_FINE_PS = false
-- C_MMCM3_CLKOUT3_USE_FINE_PS = false
-- C_MMCM3_CLKOUT4_USE_FINE_PS = false
-- C_MMCM3_CLKOUT5_USE_FINE_PS = false
-- C_MMCM3_CLKOUT6_USE_FINE_PS = false
-- C_MMCM3_COMPENSATION = "ZHOLD"
-- C_MMCM3_DIVCLK_DIVIDE = 1
-- C_MMCM3_REF_JITTER1 = 0.010
-- C_MMCM3_CLKIN1_BUF = false
-- C_MMCM3_CLKFBOUT_BUF = false
-- C_MMCM3_CLKOUT0_BUF = false
-- C_MMCM3_CLKOUT1_BUF = false
-- C_MMCM3_CLKOUT2_BUF = false
-- C_MMCM3_CLKOUT3_BUF = false
-- C_MMCM3_CLKOUT4_BUF = false
-- C_MMCM3_CLKOUT5_BUF = false
-- C_MMCM3_CLKOUT6_BUF = false
-- C_MMCM3_CLOCK_HOLD = false
-- C_MMCM3_STARTUP_WAIT = false
-- C_MMCM3_EXT_RESET_HIGH = 1
-- C_MMCM3_FAMILY = "spartan6"
-- C_MMCM3_CLKIN1_MODULE = NONE
-- C_MMCM3_CLKIN1_PORT = NONE
-- C_MMCM3_CLKFBIN_MODULE = NONE
-- C_MMCM3_CLKFBIN_PORT = NONE
-- C_MMCM3_RST_MODULE = NONE
----------------------------------------
-- C_PLLE0_BANDWIDTH = "OPTIMIZED"
-- C_PLLE0_CLKFBOUT_MULT = 1
-- C_PLLE0_CLKFBOUT_PHASE = 0.0
-- C_PLLE0_CLKIN1_PERIOD = 0.000
-- C_PLLE0_CLKOUT0_DIVIDE = 1
-- C_PLLE0_CLKOUT0_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT0_PHASE = 0.0
-- C_PLLE0_CLKOUT1_DIVIDE = 1
-- C_PLLE0_CLKOUT1_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT1_PHASE = 0.0
-- C_PLLE0_CLKOUT2_DIVIDE = 1
-- C_PLLE0_CLKOUT2_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT2_PHASE = 0.0
-- C_PLLE0_CLKOUT3_DIVIDE = 1
-- C_PLLE0_CLKOUT3_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT3_PHASE = 0.0
-- C_PLLE0_CLKOUT4_DIVIDE = 1
-- C_PLLE0_CLKOUT4_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT4_PHASE = 0.0
-- C_PLLE0_CLKOUT5_DIVIDE = 1
-- C_PLLE0_CLKOUT5_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT5_PHASE = 0.0
-- C_PLLE0_COMPENSATION = "ZHOLD"
-- C_PLLE0_DIVCLK_DIVIDE = 1
-- C_PLLE0_REF_JITTER1 = 0.010
-- C_PLLE0_CLKIN1_BUF = false
-- C_PLLE0_CLKFBOUT_BUF = false
-- C_PLLE0_CLKOUT0_BUF = false
-- C_PLLE0_CLKOUT1_BUF = false
-- C_PLLE0_CLKOUT2_BUF = false
-- C_PLLE0_CLKOUT3_BUF = false
-- C_PLLE0_CLKOUT4_BUF = false
-- C_PLLE0_CLKOUT5_BUF = false
-- C_PLLE0_STARTUP_WAIT = "false"
-- C_PLLE0_EXT_RESET_HIGH = 1
-- C_PLLE0_FAMILY = "virtex7"
-- C_PLLE0_CLKIN1_MODULE = NONE
-- C_PLLE0_CLKIN1_PORT = NONE
-- C_PLLE0_CLKFBIN_MODULE = NONE
-- C_PLLE0_CLKFBIN_PORT = NONE
-- C_PLLE0_RST_MODULE = NONE
----------------------------------------
| mit | 9383524e246f5a4d1942dac8122a8179 | 0.551813 | 2.947657 | false | false | false | false |
freecores/gpib_controller | vhdl/test/gpibInterfaceTest.vhd | 1 | 10,850 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Author: Andrzej Paluch
--
-- Create Date: 23:21:05 10/21/2011
-- Design Name:
-- Module Name: /windows/h/projekty/elektronika/USB_to_HPIB/usbToHpib/test_scr//gpibInterfaceTest.vhd
-- Project Name: usbToHpib
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: gpibInterface
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use work.gpibComponents.all;
use work.helperComponents.all;
ENTITY gpibInterfaceTest IS
END gpibInterfaceTest;
ARCHITECTURE behavior OF gpibInterfaceTest IS
-- Component Declaration for the Unit Under Test (UUT)
component gpibCableEmulator is port (
-- interface signals
DIO_1 : in std_logic_vector (7 downto 0);
output_valid_1 : in std_logic;
DIO_2 : in std_logic_vector (7 downto 0);
output_valid_2 : in std_logic;
DIO : out std_logic_vector (7 downto 0);
-- attention
ATN_1 : in std_logic;
ATN_2 : in std_logic;
ATN : out std_logic;
-- data valid
DAV_1 : in std_logic;
DAV_2 : in std_logic;
DAV : out std_logic;
-- not ready for data
NRFD_1 : in std_logic;
NRFD_2 : in std_logic;
NRFD : out std_logic;
-- no data accepted
NDAC_1 : in std_logic;
NDAC_2 : in std_logic;
NDAC : out std_logic;
-- end or identify
EOI_1 : in std_logic;
EOI_2 : in std_logic;
EOI : out std_logic;
-- service request
SRQ_1 : in std_logic;
SRQ_2 : in std_logic;
SRQ : out std_logic;
-- interface clear
IFC_1 : in std_logic;
IFC_2 : in std_logic;
IFC : out std_logic;
-- remote enable
REN_1 : in std_logic;
REN_2 : in std_logic;
REN : out std_logic
);
end component;
-- inputs common
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal T1 : std_logic_vector(7 downto 0) := "00000100";
-- inputs 1
signal data_1 : std_logic_vector(7 downto 0) := (others => '0');
signal status_byte_1 : std_logic_vector(7 downto 0) := (others => '0');
signal rdy_1 : std_logic := '0';
signal nba_1 : std_logic := '0';
signal ltn_1 : std_logic := '0';
signal lun_1 : std_logic := '0';
signal lon_1 : std_logic := '0';
signal ton_1 : std_logic := '0';
signal endOf_1 : std_logic := '0';
signal gts_1 : std_logic := '0';
signal rpp_1 : std_logic := '0';
signal tcs_1 : std_logic := '0';
signal tca_1 : std_logic := '0';
signal sic_1 : std_logic := '0';
signal rsc_1 : std_logic := '0';
signal sre_1 : std_logic := '0';
signal rtl_1 : std_logic := '0';
signal rsv_1 : std_logic := '0';
signal ist_1 : std_logic := '0';
signal lpe_1 : std_logic := '0';
-- inputs 2
signal data_2 : std_logic_vector(7 downto 0) := (others => '0');
signal status_byte_2 : std_logic_vector(7 downto 0) := (others => '0');
signal rdy_2 : std_logic := '0';
signal nba_2 : std_logic := '0';
signal ltn_2 : std_logic := '0';
signal lun_2 : std_logic := '0';
signal lon_2 : std_logic := '0';
signal ton_2 : std_logic := '0';
signal endOf_2 : std_logic := '0';
signal gts_2 : std_logic := '0';
signal rpp_2 : std_logic := '0';
signal tcs_2 : std_logic := '0';
signal tca_2 : std_logic := '0';
signal sic_2 : std_logic := '0';
signal rsc_2 : std_logic := '0';
signal sre_2 : std_logic := '0';
signal rtl_2 : std_logic := '0';
signal rsv_2 : std_logic := '0';
signal ist_2 : std_logic := '0';
signal lpe_2 : std_logic := '0';
-- outputs 1
signal dvd_1 : std_logic;
signal wnc_1 : std_logic;
signal tac_1 : std_logic;
signal cwrc_1 : std_logic;
signal cwrd_1 : std_logic;
signal clr_1 : std_logic;
signal trg_1 : std_logic;
signal atl_1 : std_logic;
signal att_1 : std_logic;
signal mla_1 : std_logic;
signal lsb_1 : std_logic;
signal spa_1 : std_logic;
signal ppr_1 : std_logic;
signal sreq_1 : std_logic;
signal isLocal_1 : std_logic;
signal currentSecAddr_1 : std_logic_vector (4 downto 0);
-- outputs 2
signal dvd_2 : std_logic;
signal wnc_2 : std_logic;
signal tac_2 : std_logic;
signal cwrc_2 : std_logic;
signal cwrd_2 : std_logic;
signal clr_2 : std_logic;
signal trg_2 : std_logic;
signal atl_2 : std_logic;
signal att_2 : std_logic;
signal mla_2 : std_logic;
signal lsb_2 : std_logic;
signal spa_2 : std_logic;
signal ppr_2 : std_logic;
signal sreq_2 : std_logic;
signal isLocal_2 : std_logic;
signal currentSecAddr_2 : std_logic_vector (4 downto 0);
-- common
signal DO : std_logic_vector (7 downto 0);
signal DI_1 : std_logic_vector (7 downto 0);
signal output_valid_1 : std_logic;
signal DI_2 : std_logic_vector (7 downto 0);
signal output_valid_2 : std_logic;
signal ATN_1, ATN_2, ATN : std_logic;
signal DAV_1, DAV_2, DAV : std_logic;
signal NRFD_1, NRFD_2, NRFD : std_logic;
signal NDAC_1, NDAC_2, NDAC : std_logic;
signal EOI_1, EOI_2, EOI : std_logic;
signal SRQ_1, SRQ_2, SRQ : std_logic;
signal IFC_1, IFC_2, IFC : std_logic;
signal REN_1, REN_2, REN : std_logic;
-- Clock period definitions
constant clk_period : time := 2ps;
BEGIN
-- Instantiate the Unit Under Test (UUT)
gpib1: gpibInterface PORT MAP (
clk => clk,
reset => reset,
isLE => '0',
isTE => '0',
lpeUsed => '0',
fixedPpLine => "000",
eosUsed => '0',
eosMark => "00000000",
myListAddr => "00001",
myTalkAddr => "00001",
secAddrMask => (others => '0'),
data => data_1,
status_byte => status_byte_1,
T1 => T1,
rdy => rdy_1,
nba => nba_1,
ltn => ltn_1,
lun => lun_1,
lon => lon_1,
ton => ton_1,
endOf => endOf_1,
gts => gts_1,
rpp => rpp_1,
tcs => tcs_1,
tca => tca_1,
sic => sic_1,
rsc => rsc_1,
sre => sre_1,
rtl => rtl_1,
rsv => rsv_1,
ist => ist_1,
lpe => lpe_1,
dvd => dvd_1,
wnc => wnc_1,
tac => tac_1,
cwrc => cwrc_1,
cwrd => cwrd_1,
clr => clr_1,
trg => trg_1,
atl => atl_1,
att => att_1,
mla => mla_1,
lsb => lsb_1,
spa => spa_1,
ppr => ppr_1,
sreq => sreq_1,
isLocal => isLocal_1,
currentSecAddr => currentSecAddr_1,
DI => DO,
DO => DI_1,
output_valid => output_valid_1,
ATN_in => ATN,
ATN_out => ATN_1,
DAV_in => DAV,
DAV_out => DAV_1,
NRFD_in => NRFD,
NRFD_out => NRFD_1,
NDAC_in => NDAC,
NDAC_out => NDAC_1,
EOI_in => EOI,
EOI_out => EOI_1,
SRQ_in => SRQ,
SRQ_out => SRQ_1,
IFC_in => IFC,
IFC_out => IFC_1,
REN_in => REN,
REN_out => REN_1
);
-- Instantiate the Unit Under Test (UUT)
gpib2: gpibInterface PORT MAP (
clk => clk,
reset => reset,
isLE => '0',
isTE => '0',
lpeUsed => '0',
fixedPpLine => "000",
eosUsed => '0',
eosMark => "00000000",
myListAddr => "00010",
myTalkAddr => "00010",
secAddrMask => (others => '0'),
data => data_2,
status_byte => status_byte_2,
T1 => T1,
rdy => rdy_2,
nba => nba_2,
ltn => ltn_2,
lun => lun_2,
lon => lon_2,
ton => ton_2,
endOf => endOf_2,
gts => gts_2,
rpp => rpp_2,
tcs => tcs_2,
tca => tca_2,
sic => sic_2,
rsc => rsc_2,
sre => sre_2,
rtl => rtl_2,
rsv => rsv_2,
ist => ist_2,
lpe => lpe_2,
dvd => dvd_2,
wnc => wnc_2,
tac => tac_2,
cwrc => cwrc_2,
cwrd => cwrd_2,
clr => clr_2,
trg => trg_2,
atl => atl_2,
att => att_2,
mla => mla_2,
lsb => lsb_2,
spa => spa_2,
ppr => ppr_2,
sreq => sreq_2,
isLocal => isLocal_2,
currentSecAddr => currentSecAddr_2,
DI => DO,
DO => DI_2,
output_valid => output_valid_2,
ATN_in => ATN,
ATN_out => ATN_2,
DAV_in => DAV,
DAV_out => DAV_2,
NRFD_in => NRFD,
NRFD_out => NRFD_2,
NDAC_in => NDAC,
NDAC_out => NDAC_2,
EOI_in => EOI,
EOI_out => EOI_2,
SRQ_in => SRQ,
SRQ_out => SRQ_2,
IFC_in => IFC,
IFC_out => IFC_2,
REN_in => REN,
REN_out => REN_2
);
ce: gpibCableEmulator port map (
-- interface signals
DIO_1 => DI_1,
output_valid_1 => output_valid_1,
DIO_2 => DI_2,
output_valid_2 => output_valid_2,
DIO => DO,
-- attention
ATN_1 => ATN_1, ATN_2 => ATN_2, ATN => ATN,
DAV_1 => DAV_1, DAV_2 => DAV_2, DAV => DAV,
NRFD_1 => NRFD_1, NRFD_2 => NRFD_2, NRFD => NRFD,
NDAC_1 => NDAC_1, NDAC_2 => NDAC_2, NDAC => NDAC,
EOI_1 => EOI_1, EOI_2 => EOI_2, EOI => EOI,
SRQ_1 => SRQ_1, SRQ_2 => SRQ_2, SRQ => SRQ,
IFC_1 => IFC_1, IFC_2 => IFC_2, IFC => IFC,
REN_1 => REN_1, REN_2 => REN_2, REN => REN
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 10 clock periods.
reset <= '1';
wait for clk_period*10;
reset <= '0';
wait for clk_period*10;
-- requests system control
rsc_1 <= '1';
-- interface clear
sic_1 <= '1';
wait for clk_period*2;
sic_1 <= '0';
wait until ifc_1='0';
-- address gpib2 to listen
data_1 <= "00100010";
nba_1 <= '1';
wait until DAV='1';
nba_1 <= '0';
wait for clk_period*20;
-- address gpib1 to talk
data_1 <= "01000001";
wait for clk_period*1;
nba_1 <= '1';
wait until DAV='1';
nba_1 <= '0';
wait for clk_period*30;
gts_1 <= '1';
wait until tac_1='1';
-- send data to gpib2
rdy_2 <= '1';
wait until NRFD='0';
data_1 <= "10101010";
nba_1 <= '1';
wait until DAV_1='1';
nba_1 <= '0';
wait until dvd_2='1';
rdy_2 <= '0';
wait until NDAC_2='0';
rdy_2 <= '1';
-- send end data to gpib2
wait until NRFD='0';
data_1 <= "10101010";
endOf_1 <= '1';
nba_1 <= '1';
wait until DAV_1='1';
nba_1 <= '0';
wait until dvd_2='1';
rdy_2 <= '0';
wait until NDAC_2='0';
rdy_2 <= '1';
wait;
end process;
END;
| gpl-3.0 | 866d221b74c2db4c281b85d4427b3ab7 | 0.587926 | 2.682987 | false | false | false | false |
Nooxet/embedded_bruteforce | brutus_system/hdl/system_fsl_v20_1_wrapper.vhd | 1 | 2,827 | -------------------------------------------------------------------------------
-- system_fsl_v20_1_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library fsl_v20_v2_11_e;
use fsl_v20_v2_11_e.all;
entity system_fsl_v20_1_wrapper is
port (
FSL_Clk : in std_logic;
SYS_Rst : in std_logic;
FSL_Rst : out std_logic;
FSL_M_Clk : in std_logic;
FSL_M_Data : in std_logic_vector(0 to 31);
FSL_M_Control : in std_logic;
FSL_M_Write : in std_logic;
FSL_M_Full : out std_logic;
FSL_S_Clk : in std_logic;
FSL_S_Data : out std_logic_vector(0 to 31);
FSL_S_Control : out std_logic;
FSL_S_Read : in std_logic;
FSL_S_Exists : out std_logic;
FSL_Full : out std_logic;
FSL_Has_Data : out std_logic;
FSL_Control_IRQ : out std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of system_fsl_v20_1_wrapper : entity is "fsl_v20_v2_11_e";
end system_fsl_v20_1_wrapper;
architecture STRUCTURE of system_fsl_v20_1_wrapper is
component fsl_v20 is
generic (
C_EXT_RESET_HIGH : integer;
C_ASYNC_CLKS : integer;
C_IMPL_STYLE : integer;
C_USE_CONTROL : integer;
C_FSL_DWIDTH : integer;
C_FSL_DEPTH : integer;
C_READ_CLOCK_PERIOD : integer
);
port (
FSL_Clk : in std_logic;
SYS_Rst : in std_logic;
FSL_Rst : out std_logic;
FSL_M_Clk : in std_logic;
FSL_M_Data : in std_logic_vector(0 to C_FSL_DWIDTH-1);
FSL_M_Control : in std_logic;
FSL_M_Write : in std_logic;
FSL_M_Full : out std_logic;
FSL_S_Clk : in std_logic;
FSL_S_Data : out std_logic_vector(0 to C_FSL_DWIDTH-1);
FSL_S_Control : out std_logic;
FSL_S_Read : in std_logic;
FSL_S_Exists : out std_logic;
FSL_Full : out std_logic;
FSL_Has_Data : out std_logic;
FSL_Control_IRQ : out std_logic
);
end component;
begin
fsl_v20_1 : fsl_v20
generic map (
C_EXT_RESET_HIGH => 1,
C_ASYNC_CLKS => 0,
C_IMPL_STYLE => 0,
C_USE_CONTROL => 1,
C_FSL_DWIDTH => 32,
C_FSL_DEPTH => 16,
C_READ_CLOCK_PERIOD => 0
)
port map (
FSL_Clk => FSL_Clk,
SYS_Rst => SYS_Rst,
FSL_Rst => FSL_Rst,
FSL_M_Clk => FSL_M_Clk,
FSL_M_Data => FSL_M_Data,
FSL_M_Control => FSL_M_Control,
FSL_M_Write => FSL_M_Write,
FSL_M_Full => FSL_M_Full,
FSL_S_Clk => FSL_S_Clk,
FSL_S_Data => FSL_S_Data,
FSL_S_Control => FSL_S_Control,
FSL_S_Read => FSL_S_Read,
FSL_S_Exists => FSL_S_Exists,
FSL_Full => FSL_Full,
FSL_Has_Data => FSL_Has_Data,
FSL_Control_IRQ => FSL_Control_IRQ
);
end architecture STRUCTURE;
| mit | 151b70bee2e014b523fcfa3d4f65e4d3 | 0.552883 | 2.975789 | false | false | false | false |
freecores/gpib_controller | vhdl/src/wrapper/gpibControlReg.vhd | 1 | 2,822 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: gpibControlReg
-- Date:2011-11-12
-- Author: Andrzej Paluch
--
-- Description ${cursor}
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity gpibControlReg is
port (
reset : in std_logic;
strobe : in std_logic;
data_in : in std_logic_vector (15 downto 0);
data_out : out std_logic_vector (15 downto 0);
------------------ gpib ------------------------
ltn : out std_logic; -- listen (L, LE)
lun : out std_logic; -- local unlisten (L, LE)
rtl : out std_logic; -- return to local (RL)
rsv : out std_logic; -- request service (SR)
ist : out std_logic; -- individual status (PP)
lpe : out std_logic; -- local poll enable (PP)
------------------------------------------------
rsc : out std_logic; -- request system control (C)
sic : out std_logic; -- send interface clear (C)
sre : out std_logic; -- send remote enable (C)
gts : out std_logic; -- go to standby (C)
tcs : out std_logic; -- take control synchronously (C, AH)
tca : out std_logic; -- take control asynchronously (C)
rpp : out std_logic; -- request parallel poll (C)
rec_stb : out std_logic -- receives status byte (C)
);
end gpibControlReg;
architecture arch of gpibControlReg is
signal inner_buf : std_logic_vector (15 downto 0);
begin
ltn <= inner_buf(0);
lun <= inner_buf(1);
rtl <= inner_buf(2);
rsv <= inner_buf(3);
ist <= inner_buf(4);
lpe <= inner_buf(5);
------------------------------------------------
rsc <= inner_buf(6);
sic <= inner_buf(7);
sre <= inner_buf(8);
gts <= inner_buf(9);
tcs <= inner_buf(10);
tca <= inner_buf(11);
rpp <= inner_buf(12);
rec_stb <= inner_buf(13);
data_out <= inner_buf;
process (reset, strobe) begin
if reset = '1' then
inner_buf <= "0000000000000000";
elsif rising_edge(strobe) then
inner_buf <= data_in;
end if;
end process;
end arch;
| gpl-3.0 | af45ab3a123b7b64b99171b809cddb76 | 0.583629 | 3.594904 | false | false | false | false |
UdayanSinha/Code_Blocks | VHDL/Projects/work/opc_pack.vhd | 1 | 2,767 | PACKAGE opc_pack IS
TYPE opc5 IS ('X', -- Forcing Unknown
'0', -- Forcing 0
'1', -- Forcing 1
'Z', -- High Impedance
'H' -- Weak 1
);
TYPE opc5_vector IS ARRAY (NATURAL RANGE <>) OF opc5;
TYPE opc_table IS ARRAY (opc5, opc5) OF opc5;
TYPE opc5_1d IS ARRAY (opc5) OF opc5;
FUNCTION RESOLVED (s : opc5_vector) RETURN opc5;
FUNCTION "xor" (l : opc5; r : opc5) RETURN opc5;
FUNCTION "xnor" (l : opc5; r : opc5) RETURN opc5;
FUNCTION "not" (l : opc5) return opc5;
SUBTYPE opc IS resolved opc5;
--SUBTYPE opc_vector IS resolved opc5_vector;
CONSTANT resolution_table : opc_table := (
-- ---------------------------------------------------------
-- | X 0 1 Z H
-- ---------------------------------------------------------
('X', 'X', 'X', 'X', 'X'), -- | X |
('X', '0', 'X', '0', '0'), -- | 0 |
('X', 'X', '1', '1', '1'), -- | 1 |
('X', '0', '1', 'Z', 'H'), -- | Z |
('X', '0', '1', 'H', 'H') -- | H |
);
CONSTANT xor_table : opc_table := (
-- ---------------------------------------------------------
-- | X 0 1 Z H
-- ---------------------------------------------------------
('X', 'X', 'X', 'X', 'X'), -- | X |
('X', '0', '1', 'X', '1'), -- | 0 |
('X', '1', '0', 'X', '0'), -- | 1 |
('X', 'X', 'X', 'X', 'X'), -- | Z |
('X', '1', '0', 'X', '0') -- | H |
);
CONSTANT not_table : opc5_1d :=
-- -------------------------------------------------
-- | X 0 1 Z H |
-- -------------------------------------------------
('X', '1', '0', 'X', '0');
END PACKAGE opc_pack;
PACKAGE BODY opc_pack is
FUNCTION RESOLVED (s : opc5_vector) RETURN opc5 IS
VARIABLE result : opc5 := 'Z'; -- weakest state default
BEGIN
-- the test for a single driver is essential otherwise the
-- loop would return 'X' for a single driver of '-' and that
-- would conflict with the value of a single driver unresolved
-- signal.
IF (s'LENGTH = 1) THEN RETURN s(s'LOW);
ELSE
FOR i IN s'RANGE LOOP
result := resolution_table(result, s(i));
END LOOP;
END IF;
RETURN result;
END FUNCTION resolved;
FUNCTION "xor" (l : opc5; r : opc5) RETURN opc5 IS
BEGIN
RETURN (xor_table(l, r));
END FUNCTION "xor";
FUNCTION "not" (l : opc5) RETURN opc5 IS
BEGIN
RETURN (not_table(l));
END FUNCTION "not";
FUNCTION "xnor" (l : opc5; r : opc5) RETURN opc5 IS
BEGIN
RETURN (not_table(xor_table(l, r)));
END FUNCTION "xnor";
END opc_pack; | mit | 3191baee768f96a10d5624806431af87 | 0.404048 | 3.37028 | false | false | false | false |
UdayanSinha/Code_Blocks | VHDL/Projects/work/tb_mux_2x1_busInput.vhd | 1 | 927 | LIBRARY IEEE; -- These lines informs the compiler that the library IEEE is used
USE IEEE.std_logic_1164.all; -- contains the definition for the std_logic type plus some useful conversion functions
ENTITY tb_mux_2x1_busInput IS END tb_mux_2x1_busInput;
ARCHITECTURE test OF tb_mux_2x1_busInput IS
CONSTANT size: INTEGER:=4;
COMPONENT mux_2x1_busInput IS
GENERIC(size: INTEGER);
PORT(a, b: IN STD_LOGIC_VECTOR(size-1 downto 0);
ctrl: IN STD_LOGIC;
q: OUT STD_LOGIC_VECTOR(size-1 downto 0));
END COMPONENT;
SIGNAL i1: STD_LOGIC_VECTOR(size-1 DOWNTO 0):="0000";
SIGNAL i2: STD_LOGIC_VECTOR(size-1 DOWNTO 0):="1111";
SIGNAL result: STD_LOGIC_VECTOR(size-1 DOWNTO 0);
SIGNAL address: STD_LOGIC;
BEGIN
T1: mux_2x1_busInput GENERIC MAP(size) PORT MAP(a=>i1, b=>i2, ctrl=>address, q=>result);
address<='0',
'1' AFTER 20 ns;
i1<="1010" AFTER 30 ns;
i2<="0111" AFTER 30 ns;
END test; | mit | 767330b73252abdb8030633093186e3b | 0.695793 | 3.019544 | false | true | false | false |
esar/hdmilight-v2 | fpga/avr/data_path.vhd | 1 | 9,677 | -------------------------------------------------------------------------------
--
-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
--
-- This code is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file named COPYING).
-- If not, see http://www.gnu.org/licenses/.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Module Name: data_path - Behavioral
-- Create Date: 13:24:10 10/29/2009
-- Description: the data path of a CPU.
--
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_ARITH.ALL;
use IEEE.std_logic_UNSIGNED.ALL;
use work.common.ALL;
entity data_path is
port( I_CLK : in std_logic;
I_CE : in std_logic;
I_ALU_OP : in std_logic_vector( 4 downto 0);
I_AMOD : in std_logic_vector( 5 downto 0);
I_BIT : in std_logic_vector( 3 downto 0);
I_DDDDD : in std_logic_vector( 4 downto 0);
I_DIN : in std_logic_vector(15 downto 0);
I_IMM : in std_logic_vector(15 downto 0);
I_JADR : in std_logic_vector(15 downto 0);
I_OPC : in std_logic_vector(15 downto 0);
I_PC : in std_logic_vector(15 downto 0);
I_PC_OP : in std_logic_vector( 2 downto 0);
I_PMS : in std_logic; -- program memory select
I_RD_M : in std_logic;
I_RRRRR : in std_logic_vector( 4 downto 0);
I_RSEL : in std_logic_vector( 1 downto 0);
I_WE_01 : in std_logic;
I_WE_D : in std_logic_vector( 1 downto 0);
I_WE_F : in std_logic;
I_WE_M : in std_logic_vector( 1 downto 0);
I_WE_XYZS : in std_logic;
Q_ADR : out std_logic_vector(15 downto 0);
Q_DOUT : out std_logic_vector(15 downto 0);
Q_INT_ENA : out std_logic;
Q_LOAD_PC : out std_logic;
Q_NEW_PC : out std_logic_vector(15 downto 0);
Q_OPC : out std_logic_vector(15 downto 0);
Q_PC : out std_logic_vector(15 downto 0);
Q_RD_IO : out std_logic;
Q_SKIP : out std_logic;
Q_WE_IO : out std_logic;
Q_WE_SRAM : out std_logic_vector(1 downto 0));
end data_path;
architecture Behavioral of data_path is
component alu
port ( I_ALU_OP : in std_logic_vector( 4 downto 0);
I_BIT : in std_logic_vector( 3 downto 0);
I_D : in std_logic_vector(15 downto 0);
I_D0 : in std_logic;
I_DIN : in std_logic_vector( 7 downto 0);
I_FLAGS : in std_logic_vector( 7 downto 0);
I_IMM : in std_logic_vector( 7 downto 0);
I_PC : in std_logic_vector(15 downto 0);
I_R : in std_logic_vector(15 downto 0);
I_R0 : in std_logic;
I_RSEL : in std_logic_vector( 1 downto 0);
Q_FLAGS : out std_logic_vector( 9 downto 0);
Q_DOUT : out std_logic_vector(15 downto 0));
end component;
signal A_DOUT : std_logic_vector(15 downto 0);
signal A_FLAGS : std_logic_vector( 9 downto 0);
component register_file
port ( I_CLK : in std_logic;
I_AMOD : in std_logic_vector( 5 downto 0);
I_COND : in std_logic_vector( 3 downto 0);
I_DDDDD : in std_logic_vector( 4 downto 0);
I_DIN : in std_logic_vector(15 downto 0);
I_FLAGS : in std_logic_vector( 7 downto 0);
I_IMM : in std_logic_vector(15 downto 0);
I_RRRR : in std_logic_vector( 4 downto 1);
I_WE_01 : in std_logic;
I_WE_D : in std_logic_vector( 1 downto 0);
I_WE_F : in std_logic;
I_WE_M : in std_logic;
I_WE_XYZS : in std_logic;
Q_ADR : out std_logic_vector(15 downto 0);
Q_CC : out std_logic;
Q_D : out std_logic_vector(15 downto 0);
Q_FLAGS : out std_logic_vector( 7 downto 0);
Q_R : out std_logic_vector(15 downto 0);
Q_S : out std_logic_vector( 7 downto 0);
Q_Z : out std_logic_vector(15 downto 0));
end component;
signal F_ADR : std_logic_vector(15 downto 0);
signal F_CC : std_logic;
signal F_D : std_logic_vector(15 downto 0);
signal F_FLAGS : std_logic_vector( 7 downto 0);
signal F_R : std_logic_vector(15 downto 0);
signal F_S : std_logic_vector( 7 downto 0);
signal F_Z : std_logic_vector(15 downto 0);
signal L_DIN : std_logic_vector( 7 downto 0);
signal L_WE_SRAM : std_logic_vector( 1 downto 0);
signal L_FLAGS_98 : std_logic_vector( 9 downto 8);
begin
alui : alu
port map( I_ALU_OP => I_ALU_OP,
I_BIT => I_BIT,
I_D => F_D,
I_D0 => I_DDDDD(0),
I_DIN => L_DIN,
I_FLAGS => F_FLAGS,
I_IMM => I_IMM(7 downto 0),
I_PC => I_PC,
I_R => F_R,
I_R0 => I_RRRRR(0),
I_RSEL => I_RSEL,
Q_FLAGS => A_FLAGS,
Q_DOUT => A_DOUT);
regs : register_file
port map( I_CLK => I_CLK,
I_AMOD => I_AMOD,
I_COND(3) => I_OPC(10),
I_COND(2 downto 0)=> I_OPC(2 downto 0),
I_DDDDD => I_DDDDD,
I_DIN => A_DOUT,
I_FLAGS => A_FLAGS(7 downto 0),
I_IMM => I_IMM,
I_RRRR => I_RRRRR(4 downto 1),
I_WE_01 => I_WE_01,
I_WE_D => I_WE_D,
I_WE_F => I_WE_F,
I_WE_M => I_WE_M(0),
I_WE_XYZS => I_WE_XYZS,
Q_ADR => F_ADR,
Q_CC => F_CC,
Q_D => F_D,
Q_FLAGS => F_FLAGS,
Q_R => F_R,
Q_S => F_S, -- Q_Rxx(F_ADR)
Q_Z => F_Z);
-- remember A_FLAGS(9 downto 8) (within the current instruction).
--
flg98: process(I_CE, I_CLK)
begin
if (I_CE = '1' and rising_edge(I_CLK)) then
L_FLAGS_98 <= A_FLAGS(9 downto 8);
end if;
end process;
-- whether PC shall be loaded with NEW_PC or not.
-- I.e. if a branch shall be taken or not.
--
process(I_PC_OP, F_CC)
begin
case I_PC_OP is
when PC_BCC => Q_LOAD_PC <= F_CC; -- maybe (PC on I_JADR)
when PC_LD_I => Q_LOAD_PC <= '1'; -- yes: new PC on I_JADR
when PC_LD_Z => Q_LOAD_PC <= '1'; -- yes: new PC in Z
when PC_LD_S => Q_LOAD_PC <= '1'; -- yes: new PC on stack
when others => Q_LOAD_PC <= '0'; -- no.
end case;
end process;
-- whether the next instruction shall be skipped or not.
--
process(I_PC_OP, L_FLAGS_98, F_CC)
begin
case I_PC_OP is
when PC_BCC => Q_SKIP <= F_CC; -- if cond met
when PC_LD_I => Q_SKIP <= '1'; -- yes
when PC_LD_Z => Q_SKIP <= '1'; -- yes
when PC_LD_S => Q_SKIP <= '1'; -- yes
when PC_SKIP_Z => Q_SKIP <= L_FLAGS_98(8); -- if Z set
when PC_SKIP_T => Q_SKIP <= L_FLAGS_98(9); -- if T set
when others => Q_SKIP <= '0'; -- no.
end case;
end process;
Q_ADR <= F_ADR;
Q_DOUT <= A_DOUT;
Q_INT_ENA <= A_FLAGS(7);
Q_OPC <= I_OPC;
Q_PC <= I_PC;
Q_RD_IO <= '0' when (F_ADR < X"20")
else (I_RD_M and not I_PMS) when (F_ADR < X"5D")
else '0';
Q_WE_IO <= '0' when (F_ADR < X"20")
else I_WE_M(0) when (F_ADR < X"5D")
else '0';
Q_WE_SRAM <= "00" when (F_ADR < X"0060") else I_WE_M;
L_DIN <= I_DIN(7 downto 0) when (I_PMS = '1')
else F_S when (F_ADR < X"0020")
else I_DIN(7 downto 0) when (F_ADR < X"005D")
else F_S when (F_ADR < X"0060")
else I_DIN(7 downto 0);
-- compute potential new PC value from Z, (SP), or IMM.
--
Q_NEW_PC <= F_Z when I_PC_OP = PC_LD_Z -- IJMP, ICALL
else I_DIN when I_PC_OP = PC_LD_S -- RET, RETI
else I_JADR; -- JMP adr
end Behavioral;
| gpl-2.0 | 4b47a4cfa2bf9b89dadd69d4c909e5dd | 0.443733 | 3.374128 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | filtering_algorithm_RTL/source/vhdl/filtering_algorithm_pkg.vhd | 1 | 13,730 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: filtering_algorithm_pkg - Package
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.all;
use ieee.math_real.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
package filtering_algorithm_pkg is
constant N_MAX : integer := 32768;
constant D : integer := 3;
constant L_MAX : integer := 6;
constant K_MAX : integer := 256;
constant N_MAX_TREE_NODES : integer := 2*N_MAX;
constant STACK_SIZE : integer := 32768;
constant HEAP_SIZE : integer := 256;
constant COORD_BITWIDTH : integer := 16;
constant COORD_BITWIDTH_EXT : integer := 32;
constant INDEX_BITWIDTH : integer := integer(ceil(log2(real(K_MAX))));
constant NODE_POINTER_BITWIDTH : integer := integer(ceil(log2(real(N_MAX_TREE_NODES))));
constant CNTR_POINTER_BITWIDTH : integer := integer(ceil(log2(real(HEAP_SIZE))));
constant MUL_FRACTIONAL_BITS : integer := 6;
constant MUL_INTEGER_BITS : integer := 12;
constant MUL_BITWIDTH : integer := MUL_INTEGER_BITS+MUL_FRACTIONAL_BITS;
constant MUL_CORE_LATENCY : integer := 3;
constant DYN_ALLOC : boolean := true;
constant SYNTHESIS : boolean := false;
constant VIRTEX7 : boolean := true;
constant USE_DSP_FOR_ADD : boolean := false;
constant PARALLEL_UNITS : integer := 1;
subtype coord_type is std_logic_vector(COORD_BITWIDTH-1 downto 0);
subtype centre_index_type is unsigned(INDEX_BITWIDTH-1 downto 0);
subtype node_address_type is std_logic_vector(NODE_POINTER_BITWIDTH-1 downto 0);
subtype centre_list_address_type is std_logic_vector(CNTR_POINTER_BITWIDTH-1 downto 0);
type data_type is array(0 to D-1) of coord_type;
subtype coord_type_ext is std_logic_vector(COORD_BITWIDTH_EXT-1 downto 0);
type data_type_ext is array(0 to D-1) of coord_type_ext;
type node_data_type is
record
wgtCent : data_type_ext;
midPoint : data_type;
bnd_lo : data_type;
bnd_hi : data_type;
sum_sq : coord_type_ext;
count : coord_type;
left : node_address_type;
right : node_address_type;
end record;
-- size of node_data_type : 3*D*COORD_BITWIDTH+D*COORD_BITWIDTH_EXT+COORD_BITWIDTH+COORD_BITWIDTH_EXT+2*NODE_POINTER_BITWIDTH
-- array types for parallelism
type par_centre_index_type is array(0 to PARALLEL_UNITS-1) of centre_index_type;
type par_centre_list_address_type is array(0 to PARALLEL_UNITS-1) of centre_list_address_type;
type par_coord_type is array(0 to PARALLEL_UNITS-1) of coord_type;
type par_coord_type_ext is array(0 to PARALLEL_UNITS-1) of coord_type_ext;
type par_data_type is array(0 to PARALLEL_UNITS-1) of data_type;
type par_data_type_ext is array(0 to PARALLEL_UNITS-1) of data_type_ext;
type par_node_address_type is array(0 to PARALLEL_UNITS-1) of node_address_type;
type par_node_data_type is array(0 to PARALLEL_UNITS-1) of node_data_type;
type par_element_type_ext is array(0 to D-1) of std_logic_vector(PARALLEL_UNITS*COORD_BITWIDTH_EXT-1 downto 0);
type par_element_type_ext_sum is array(0 to D-1) of std_logic_vector(COORD_BITWIDTH_EXT+integer(ceil(log2(real(PARALLEL_UNITS))))-1 downto 0);
-- helper functions
function stdlogic_2_datapoint(c : std_logic_vector) return data_type;
function stdlogic_2_datapoint_ext(c : std_logic_vector) return data_type_ext;
function datapoint_2_stdlogic(c : data_type) return std_logic_vector;
function datapoint_ext_2_stdlogic(c : data_type_ext) return std_logic_vector;
function nodedata_2_stdlogic(n : node_data_type) return std_logic_vector;
function stdlogic_2_nodedata(n : std_logic_vector) return node_data_type;
function saturate(val : std_logic_vector) return std_logic_vector;
function sext(val : std_logic_vector; length : integer) return std_logic_vector;
function zext(val : std_logic_vector; length : integer) return std_logic_vector;
function conv_ext_2_normal(val : data_type_ext) return data_type;
function conv_normal_2_ext(val : data_type) return data_type_ext;
end filtering_algorithm_pkg;
package body filtering_algorithm_pkg is
function datapoint_2_stdlogic(c : data_type) return std_logic_vector is
variable result : std_logic_vector(D*COORD_BITWIDTH-1 downto 0);
begin
for I in 0 to D-1 loop
result((I+1)*COORD_BITWIDTH-1 downto I*COORD_BITWIDTH) := std_logic_vector(c(I));
end loop;
return result;
end datapoint_2_stdlogic;
function datapoint_ext_2_stdlogic(c : data_type_ext) return std_logic_vector is
variable result : std_logic_vector(D*COORD_BITWIDTH_EXT-1 downto 0);
begin
for I in 0 to D-1 loop
result((I+1)*COORD_BITWIDTH_EXT-1 downto I*COORD_BITWIDTH_EXT) := std_logic_vector(c(I));
end loop;
return result;
end datapoint_ext_2_stdlogic;
function stdlogic_2_datapoint(c : std_logic_vector) return data_type is
variable result : data_type;
begin
for I in 0 to D-1 loop
result(I) := c((I+1)*COORD_BITWIDTH-1 downto I*COORD_BITWIDTH);
end loop;
return result;
end stdlogic_2_datapoint;
function stdlogic_2_datapoint_ext(c : std_logic_vector) return data_type_ext is
variable result : data_type_ext;
begin
for I in 0 to D-1 loop
result(I) := c((I+1)*COORD_BITWIDTH_EXT-1 downto I*COORD_BITWIDTH_EXT);
end loop;
return result;
end stdlogic_2_datapoint_ext;
function nodedata_2_stdlogic(n : node_data_type) return std_logic_vector is
variable result : std_logic_vector(D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+COORD_BITWIDTH_EXT+COORD_BITWIDTH+2*NODE_POINTER_BITWIDTH-1 downto 0);
begin
for I in 0 to D-1 loop
result((I+1)*COORD_BITWIDTH_EXT+0*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto I*COORD_BITWIDTH_EXT+0*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH) := n.wgtCent(I);
result(1*D*COORD_BITWIDTH_EXT+(I+1)*COORD_BITWIDTH+0*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+I*COORD_BITWIDTH+0*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH) := n.midPoint(I);
result(1*D*COORD_BITWIDTH_EXT+(I+1)*COORD_BITWIDTH+1*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+I*COORD_BITWIDTH+1*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH) := n.bnd_lo(I);
result(1*D*COORD_BITWIDTH_EXT+(I+1)*COORD_BITWIDTH+2*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+I*COORD_BITWIDTH+2*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH) := n.bnd_hi(I);
end loop;
result(1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH) := n.sum_sq;
result(1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+1*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH) := n.count;
result(1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+1*COORD_BITWIDTH+1*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+1*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH) := std_logic_vector(n.left);
result(1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+1*COORD_BITWIDTH+2*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+1*COORD_BITWIDTH+1*NODE_POINTER_BITWIDTH) := std_logic_vector(n.right);
return result;
end nodedata_2_stdlogic;
function stdlogic_2_nodedata(n : std_logic_vector) return node_data_type is
variable result : node_data_type;
begin
for I in 0 to D-1 loop
result.wgtCent(I) := n((I+1)*COORD_BITWIDTH_EXT+0*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto I*COORD_BITWIDTH_EXT+0*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH);
result.midPoint(I) := n(1*D*COORD_BITWIDTH_EXT+(I+1)*COORD_BITWIDTH+0*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+I*COORD_BITWIDTH+0*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH);
result.bnd_lo(I) := n(1*D*COORD_BITWIDTH_EXT+(I+1)*COORD_BITWIDTH+1*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+I*COORD_BITWIDTH+1*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH);
result.bnd_hi(I) := n(1*D*COORD_BITWIDTH_EXT+(I+1)*COORD_BITWIDTH+2*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+I*COORD_BITWIDTH+2*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH);
end loop;
result.sum_sq := n(1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+0*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH);
result.count := n(1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+1*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+0*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH);
result.left := n(1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+1*COORD_BITWIDTH+1*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+1*COORD_BITWIDTH+0*NODE_POINTER_BITWIDTH);
result.right := n(1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+1*COORD_BITWIDTH+2*NODE_POINTER_BITWIDTH-1 downto 1*D*COORD_BITWIDTH_EXT+3*D*COORD_BITWIDTH+1*COORD_BITWIDTH_EXT+1*COORD_BITWIDTH+1*NODE_POINTER_BITWIDTH);
return result;
end stdlogic_2_nodedata;
function saturate(val : std_logic_vector) return std_logic_vector is
variable val_msb : std_logic;
variable comp : std_logic_vector((val'length-MUL_INTEGER_BITS-MUL_FRACTIONAL_BITS)-1 downto 0);
variable result : std_logic_vector(MUL_INTEGER_BITS+MUL_FRACTIONAL_BITS-1 downto 0);
begin
if MUL_INTEGER_BITS+MUL_FRACTIONAL_BITS < val'length then
val_msb := val(val'length-1);
for I in (val'length-MUL_INTEGER_BITS-MUL_FRACTIONAL_BITS)-1 downto 0 loop
comp(I) := val_msb;
end loop;
if val(val'length-2 downto MUL_INTEGER_BITS+MUL_FRACTIONAL_BITS-1) = comp then
result := val(MUL_INTEGER_BITS+MUL_FRACTIONAL_BITS-1 downto 0);
else
result(MUL_INTEGER_BITS+MUL_FRACTIONAL_BITS-1) := val_msb;
result(MUL_INTEGER_BITS+MUL_FRACTIONAL_BITS-2 downto 0) := (others => NOT(val_msb));
end if;
else
result := sext(val,MUL_INTEGER_BITS+MUL_FRACTIONAL_BITS);
end if;
return result;
end saturate;
function sext(val : std_logic_vector; length : integer) return std_logic_vector is
variable val_msb : std_logic;
variable result : std_logic_vector(length-1 downto 0);
begin
val_msb := val(val'length-1);
result(val'length-1 downto 0) := val;
result(length-1 downto val'length) := (others => val_msb);
return result;
end sext;
function zext(val : std_logic_vector; length : integer) return std_logic_vector is
variable result : std_logic_vector(length-1 downto 0);
begin
result(val'length-1 downto 0) := val;
result(length-1 downto val'length) := (others => '0');
return result;
end zext;
function conv_ext_2_normal(val : data_type_ext) return data_type is
variable result : data_type;
begin
for I in 0 to D-1 loop
result(I) := val(I)(COORD_BITWIDTH-1 downto 0);
end loop;
return result;
end conv_ext_2_normal;
function conv_normal_2_ext(val : data_type) return data_type_ext is
variable result : data_type_ext;
begin
for I in 0 to D-1 loop
result(I) := sext(val(I),COORD_BITWIDTH_EXT);
end loop;
return result;
end conv_normal_2_ext;
end package body;
| bsd-3-clause | 9262a23ff752b4bd437f8ec81f23e10e | 0.653023 | 3.405258 | false | false | false | false |
esar/hdmilight-v2 | fpga/resultDelayRegisters.vhd | 1 | 2,426 | ----------------------------------------------------------------------------------
--
-- Copyright (C) 2014 Stephen Robinson
--
-- This file is part of HDMI-Light
--
-- HDMI-Light is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- HDMI-Light is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file names COPING).
-- If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity resultDelayRegisters is
Port ( clk : in STD_LOGIC;
addr : in STD_LOGIC_VECTOR (2 downto 0);
din : in STD_LOGIC_VECTOR (7 downto 0);
dout : out STD_LOGIC_VECTOR (7 downto 0);
we : in STD_LOGIC;
frameCount : out STD_LOGIC_VECTOR (7 downto 0);
tickCount : out STD_LOGIC_VECTOR (23 downto 0);
temporalSmoothingRatio : out STD_LOGIC_VECTOR (8 downto 0)
);
end resultDelayRegisters;
architecture Behavioral of resultDelayRegisters is
constant ADDR_WIDTH : integer := 3;
constant DATA_WIDTH : integer := 8;
type mem_type is array ( (2**ADDR_WIDTH)-1 downto 0 ) of std_logic_vector(DATA_WIDTH-1 downto 0);
shared variable mem : mem_type := ("11101000", "00000011", "00000000", "00000010", "00000000", "00000000", "00000000", "00000000");
begin
process(clk)
begin
if(rising_edge(clk)) then
if(we = '1') then
mem(conv_integer(addr)) := din;
end if;
dout <= mem(conv_integer(addr));
end if;
end process;
frameCount <= mem(0);
tickCount <= mem(1) & mem(2) & mem(3);
temporalSmoothingRatio <= mem(4)(0) & mem(5);
end Behavioral;
| gpl-2.0 | 1155d0d63a02b452136c1e2c7daeb881 | 0.645919 | 3.906602 | false | false | false | false |
Nooxet/embedded_bruteforce | brutus_system/pcores/test_v1_00_a/hdl/vhdl/test.vhd | 1 | 8,075 | ------------------------------------------------------------------------------
-- test - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: test
-- Version: 1.00.a
-- Description: Example FSL core (VHDL).
-- Date: Mon Sep 29 12:13:18 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------------
--
--
-- Definition of Ports
-- FSL_Clk : Synchronous clock
-- FSL_Rst : System reset, should always come from FSL bus
-- FSL_S_Clk : Slave asynchronous clock
-- FSL_S_Read : Read signal, requiring next available input to be read
-- FSL_S_Data : Input data
-- FSL_S_CONTROL : Control Bit, indicating the input data are control word
-- FSL_S_Exists : Data Exist Bit, indicating data exist in the input FSL bus
-- FSL_M_Clk : Master asynchronous clock
-- FSL_M_Write : Write signal, enabling writing to output FSL bus
-- FSL_M_Data : Output data
-- FSL_M_Control : Control Bit, indicating the output data are contol word
-- FSL_M_Full : Full Bit, indicating output FSL bus is full
--
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity test is
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
FSL_Clk : in std_logic;
FSL_Rst : in std_logic;
FSL_S_Clk : in std_logic;
FSL_S_Read : out std_logic;
FSL_S_Data : in std_logic_vector(0 to 31);
FSL_S_Control : in std_logic;
FSL_S_Exists : in std_logic;
FSL_M_Clk : in std_logic;
FSL_M_Write : out std_logic;
FSL_M_Data : out std_logic_vector(0 to 31);
FSL_M_Control : out std_logic;
FSL_M_Full : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of FSL_Clk : signal is "Clk";
attribute SIGIS of FSL_S_Clk : signal is "Clk";
attribute SIGIS of FSL_M_Clk : signal is "Clk";
end test;
------------------------------------------------------------------------------
-- Architecture Section
------------------------------------------------------------------------------
-- In this section, we povide an example implementation of ENTITY test
-- that does the following:
--
-- 1. Read all inputs
-- 2. Add each input to the contents of register 'sum' which
-- acts as an accumulator
-- 3. After all the inputs have been read, write out the
-- content of 'sum' into the output FSL bus NUMBER_OF_OUTPUT_WORDS times
--
-- You will need to modify this example or implement a new architecture for
-- ENTITY test to implement your coprocessor
architecture EXAMPLE of test is
-- Total number of input data.
constant NUMBER_OF_INPUT_WORDS : natural := 4;
-- Total number of output data
constant NUMBER_OF_OUTPUT_WORDS : natural := 2;
type STATE_TYPE is (Idle, Read_Inputs, Write_Outputs);
signal state : STATE_TYPE;
-- Accumulator to hold sum of inputs read at any point in time
signal sum : std_logic_vector(0 to 31);
-- Counters to store the number inputs read & outputs written
signal nr_of_reads : natural range 0 to NUMBER_OF_INPUT_WORDS - 1;
signal nr_of_writes : natural range 0 to NUMBER_OF_OUTPUT_WORDS - 1;
begin
FSL_S_Read <= FSL_S_Exists when state = Read_Inputs else '0';
FSL_M_Write <= not FSL_M_Full when state = Write_Outputs else '0';
FSL_M_Data <= sum;
sum <= std_logic_vector(unsigned(sum) + unsigned(FSL_S_Data));
The_SW_accelerator : process (FSL_Clk) is
begin -- process The_SW_accelerator
if FSL_Clk'event and FSL_Clk = '1' then -- Rising clock edge
if FSL_Rst = '1' then -- Synchronous reset (active high)
-- CAUTION: make sure your reset polarity is consistent with the
-- system reset polarity
state <= Idle;
nr_of_reads <= 0;
nr_of_writes <= 0;
sum <= (others => '0');
else
case state is
when Idle =>
if (FSL_S_Exists = '1') then
state <= Read_Inputs;
nr_of_reads <= NUMBER_OF_INPUT_WORDS - 1;
sum <= (others => '0');
end if;
when Read_Inputs =>
if (FSL_S_Exists = '1') then
-- Coprocessor function (Adding) happens here
sum <= std_logic_vector(unsigned(sum) + unsigned(FSL_S_Data));
if (nr_of_reads = 0) then
state <= Write_Outputs;
nr_of_writes <= NUMBER_OF_OUTPUT_WORDS - 1;
else
nr_of_reads <= nr_of_reads - 1;
end if;
end if;
when Write_Outputs =>
if (nr_of_writes = 0) then
state <= Idle;
else
if (FSL_M_Full = '0') then
nr_of_writes <= nr_of_writes - 1;
end if;
end if;
end case;
end if;
end if;
end process The_SW_accelerator;
end architecture EXAMPLE;
| mit | feadb7bc550f801d7710898c693811d4 | 0.481238 | 4.488605 | false | false | false | false |
mithro/HDMI2USB | ipcore_dir/edidram/simulation/bmg_stim_gen.vhd | 3 | 12,272 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_2 Core - Stimulus Generator For Simple Dual Port RAM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SDP Configuration
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLKA : IN STD_LOGIC;
CLKB : IN STD_LOGIC;
TB_RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
ADDRB: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL DO_READ_R : STD_LOGIC := '0';
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(5 DOWNTO 0) :=(OTHERS => '0');
SIGNAL PORTA_WR : STD_LOGIC:='0';
SIGNAL COUNT : INTEGER :=0;
SIGNAL INCR_WR_CNT : STD_LOGIC:='0';
SIGNAL PORTA_WR_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_RD : STD_LOGIC:='0';
SIGNAL COUNT_RD : INTEGER :=0;
SIGNAL INCR_RD_CNT : STD_LOGIC:='0';
SIGNAL PORTB_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL LATCH_PORTA_WR_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_RD_HAPPENED : STD_LOGIC := '0';
SIGNAL PORTA_WR_L1 :STD_LOGIC := '0';
SIGNAL PORTA_WR_L2 :STD_LOGIC := '0';
SIGNAL PORTB_RD_R2 :STD_LOGIC := '0';
SIGNAL PORTB_RD_R1 :STD_LOGIC := '0';
SIGNAL LATCH_PORTB_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTA_WR_HAPPENED : STD_LOGIC := '0';
SIGNAL PORTB_RD_L1 : STD_LOGIC := '0';
SIGNAL PORTB_RD_L2 : STD_LOGIC := '0';
SIGNAL PORTA_WR_R2 : STD_LOGIC := '0';
SIGNAL PORTA_WR_R1 : STD_LOGIC := '0';
CONSTANT WR_RD_DEEP_COUNT :INTEGER :=8;
CONSTANT WR_DEEP_COUNT : INTEGER := if_then_else((8 <= 8),WR_RD_DEEP_COUNT,
((8/8)*WR_RD_DEEP_COUNT));
CONSTANT RD_DEEP_COUNT : INTEGER := if_then_else((8 <= 8),WR_RD_DEEP_COUNT,
((8/8)*WR_RD_DEEP_COUNT));
BEGIN
ADDRA <= WRITE_ADDR(7 DOWNTO 0) ;
DINA <= DINA_INT ;
ADDRB <= READ_ADDR(7 DOWNTO 0) when (DO_READ='1') else (OTHERS=>'0');
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 256 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 256,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 8,
DOUT_WIDTH => 8 ,
DATA_PART_CNT => 1,
SEED => 2)
PORT MAP (
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
PORTA_WR_PROCESS: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTA_WR<='1';
ELSE
PORTA_WR<=PORTB_RD_COMPLETE;
END IF;
END IF;
END PROCESS;
PORTB_RD_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTB_RD<='0';
ELSE
PORTB_RD<=PORTA_WR_L2;
END IF;
END IF;
END PROCESS;
PORTB_RD_COMPLETE_LATCH: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
LATCH_PORTB_RD_COMPLETE<='0';
ELSIF(PORTB_RD_COMPLETE='1') THEN
LATCH_PORTB_RD_COMPLETE <='1';
ELSIF(PORTA_WR_HAPPENED='1') THEN
LATCH_PORTB_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_RD_L1 <='0';
PORTB_RD_L2 <='0';
ELSE
PORTB_RD_L1 <= LATCH_PORTB_RD_COMPLETE;
PORTB_RD_L2 <= PORTB_RD_L1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_R1 <='0';
PORTA_WR_R2 <='0';
ELSE
PORTA_WR_R1 <= PORTA_WR;
PORTA_WR_R2 <= PORTA_WR_R1;
END IF;
END IF;
END PROCESS;
PORTA_WR_HAPPENED <= PORTA_WR_R2;
PORTA_WR_COMPLETE_LATCH: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
LATCH_PORTA_WR_COMPLETE<='0';
ELSIF(PORTA_WR_COMPLETE='1') THEN
LATCH_PORTA_WR_COMPLETE <='1';
--ELSIF(PORTB_RD_HAPPENED='1') THEN
ELSE
LATCH_PORTA_WR_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_L1 <='0';
PORTA_WR_L2 <='0';
ELSE
PORTA_WR_L1 <= LATCH_PORTA_WR_COMPLETE;
PORTA_WR_L2 <= PORTA_WR_L1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_RD_R1 <='0';
PORTB_RD_R2 <='0';
ELSE
PORTB_RD_R1 <= PORTB_RD;
PORTB_RD_R2 <= PORTB_RD_R1;
END IF;
END IF;
END PROCESS;
PORTB_RD_HAPPENED <= PORTB_RD_R2;
PORTB_RD_COMPLETE <= '1' when (count_rd=RD_DEEP_COUNT) else '0';
start_rd_counter: process(clkb)
begin
if(rising_edge(clkb)) then
if(tb_rst='1') then
incr_rd_cnt <= '0';
elsif(portb_rd ='1') then
incr_rd_cnt <='1';
elsif(portb_rd_complete='1') then
incr_rd_cnt <='0';
end if;
end if;
end process;
RD_COUNTER: process(clkb)
begin
if(rising_edge(clkb)) then
if(tb_rst='1') then
count_rd <= 0;
elsif(incr_rd_cnt='1') then
count_rd<=count_rd+1;
end if;
--if(count_rd=(wr_rd_deep_count)) then
if(count_rd=(RD_DEEP_COUNT)) then
count_rd<=0;
end if;
end if;
end process;
DO_READ<='1' when (count_rd <RD_DEEP_COUNT and incr_rd_cnt='1') else '0';
PORTA_WR_COMPLETE <= '1' when (count=WR_DEEP_COUNT) else '0';
start_counter: process(clka)
begin
if(rising_edge(clka)) then
if(tb_rst='1') then
incr_wr_cnt <= '0';
elsif(porta_wr ='1') then
incr_wr_cnt <='1';
elsif(porta_wr_complete='1') then
incr_wr_cnt <='0';
end if;
end if;
end process;
COUNTER: process(clka)
begin
if(rising_edge(clka)) then
if(tb_rst='1') then
count <= 0;
elsif(incr_wr_cnt='1') then
count<=count+1;
end if;
if(count=(WR_DEEP_COUNT)) then
count<=0;
end if;
end if;
end process;
DO_WRITE<='1' when (count <WR_DEEP_COUNT and incr_wr_cnt='1') else '0';
BEGIN_SHIFT_REG: FOR I IN 0 TO 5 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLKB,
RST => TB_RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=5)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLKB,
RST =>TB_RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
REGCE_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
DO_READ_R <= '0';
ELSE
DO_READ_R <= DO_READ;
END IF;
END IF;
END PROCESS;
WEA(0) <= DO_WRITE ;
END ARCHITECTURE;
| bsd-2-clause | f6be81d4fd8a8b90df7e6da61bde7e30 | 0.542291 | 3.542725 | false | false | false | false |
whitef0x0/EECE353-Lab4 | fsm-challenge.vhd | 1 | 3,817 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
LIBRARY WORK;
USE WORK.ALL;
ENTITY fsm_challenge IS
PORT (
clock : IN STD_LOGIC;
resetb : IN STD_LOGIC;
xdone, ydone, ldone : IN STD_LOGIC;
sw : IN STD_LOGIC_VECTOR(17 downto 0);
draw : IN STD_LOGIC;
initx, inity, loady, loadx, plot, initl, drawl : OUT STD_LOGIC;
colour : OUT STD_LOGIC_VECTOR(2 downto 0);
x : OUT STD_LOGIC_VECTOR(7 downto 0);
y : OUT STD_LOGIC_VECTOR(6 downto 0);
ledg : OUT STD_LOGIC_VECTOR(7 downto 0);
initLoad : OUT STD_LOGIC
);
END fsm_challenge;
ARCHITECTURE behavioural OF fsm_challenge IS
TYPE state_types is (START, LOAD_Y, LOAD_X, LOAD_DONE, INIT_LINE, DRAW_LINE, DONE_LINE);
SIGNAL curr_state, next_state : state_types := START;
SIGNAL loadCount : integer := 0;
BEGIN
PROCESS(clock, resetb)
--VARIABLE next_state : state_types;
BEGIN
IF (resetb = '0') THEN
curr_state <= START;
loadCount <= 0;
ELSIF rising_edge(clock) THEN
curr_state <= next_state;
IF(next_state = DONE_LINE) THEN
loadCount <= 1;
END IF;
END IF;
END PROCESS;
PROCESS(curr_state, next_state)
BEGIN
CASE curr_state IS
WHEN START =>
INITX <= '1';
INITY <= '1';
LOADY <= '1';
LOADX <= '1';
INITL <= '0';
DRAWL <= '0';
PLOT <= '0';
initLoad <= '1';
colour <= "000";
ledg <= "00000000";
next_state <= LOAD_X;
WHEN LOAD_Y =>
INITX <= '1';
INITY <= '0';
LOADY <= '1';
LOADX <= '1';
INITL <= '0';
DRAWL <= '0';
PLOT <= '0';
IF(loadCount > 0) THEN
initLoad <= '0';
ELSE
initLoad <= '1';
END IF;
ledg <= "00000001";
next_state <= LOAD_X;
WHEN LOAD_X =>
INITX <= '0';
INITY <= '0';
LOADY <= '0';
LOADX <= '1';
INITL <= '0';
DRAWL <= '0';
PLOT <= '1';
IF(loadCount > 0) THEN
initLoad <= '0';
ELSE
initLoad <= '1';
END IF;
ledg <= "00000010";
IF (XDONE = '0') THEN
next_state <= LOAD_X;
ELSIF (XDONE = '1' AND YDONE = '0') THEN
next_state <= LOAD_Y;
ELSE
next_state <= LOAD_DONE;
END IF;
when LOAD_DONE =>
INITX <= '0';
INITY <= '0';
LOADY <= '0';
LOADX <= '0';
INITL <= '0';
DRAWL <= '0';
PLOT <= '0';
ledg <= "00000100";
IF (draw = '0') THEN
x <= sw(17 downto 10);
y <= sw(9 downto 3);
--Clip input to within bounds
IF (unsigned(sw(17 downto 10)) > 159) THEN
x <= "10011111";
END IF;
IF (unsigned(sw(9 downto 3)) > 119) THEN
y <= "1110111";
END IF;
next_state <= INIT_LINE;
ELSE
next_state <= LOAD_DONE;
END IF;
WHEN INIT_LINE =>
IF(loadCount > 0) THEN
initLoad <= '0';
ELSE
initLoad <= '1';
END IF;
INITX <= '0';
INITY <= '0';
LOADY <= '0';
LOADX <= '0';
INITL <= '1';
DRAWL <= '0';
PLOT <= '0';
ledg <= "00001000";
colour <= sw(2 downto 0);
next_state <= DRAW_LINE;
WHEN DRAW_LINE =>
INITX <= '0';
INITY <= '0';
LOADY <= '0';
LOADX <= '0';
INITL <= '0';
DRAWL <= '1';
PLOT <= '1';
ledg <= "00010000";
IF (LDONE = '1') THEN
ledg <= "11111111";
next_state <= DONE_LINE;
ELSE
next_state <= DRAW_LINE;
END IF;
WHEN DONE_LINE =>
ledg <= "00100000";
INITX <= '0';
INITY <= '0';
LOADY <= '0';
LOADX <= '0';
INITL <= '0';
DRAWL <= '0';
PLOT <= '0';
next_state <= LOAD_DONE;
WHEN others =>
ledg <= "01000000";
INITX <= '0';
INITY <= '0';
LOADY <= '0';
LOADX <= '0';
INITL <= '0';
DRAWL <= '0';
PLOT <= '0';
next_state <= DONE_LINE;
END CASE;
END PROCESS;
END behavioural;
| mit | 0e39088497686ffad9857190c4be74f0 | 0.499083 | 2.907083 | false | false | false | false |
mithro/HDMI2USB | ipcore_dir/edidram/example_design/edidram_exdes.vhd | 3 | 4,962 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: edidram_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY edidram_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END edidram_exdes;
ARCHITECTURE xilinx OF edidram_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT edidram IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bufg_B : BUFG
PORT MAP (
I => CLKB,
O => CLKB_buf
);
bmg0 : edidram
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
CLKA => CLKA_buf,
--Port B
ADDRB => ADDRB,
DOUTB => DOUTB,
CLKB => CLKB_buf
);
END xilinx;
| bsd-2-clause | c8801486dff9fe4ddc3abe4c961f8862 | 0.557638 | 4.672316 | false | false | false | false |
RickvanLoo/Synthesizer | osc_handler.vhd | 1 | 1,665 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
ENTITY osc_handler IS
PORT(
CLK : in std_logic;
RESET : in std_logic;
NOTE_ON_OSC : in std_logic_vector(7 downto 0); --Note ON/OFF 0x80(off), 0xFF(on)
NOTE_OFF_OSC : in std_logic_vector(7 downto 0); --Note ON/OFF 0x80(off), 0xFF(on)
NOTE0, NOTE1 : out std_logic_vector(7 downto 0);
ENABLE0, ENABLE1 : out std_logic
);
END osc_handler;
ARCHITECTURE behav of osc_handler is
signal osc_case : std_logic := '0';
signal aNOTE0, aNOTE1 : std_logic_vector(7 downto 0);
signal OLD_NOTE : std_logic_vector(7 downto 0) := (others => '0'); --Note ON/OFF 0x80(off), 0xFF(on)
BEGIN
process(CLK, RESET)
variable flag : std_logic := '0';
begin
if reset = '0' then
NOTE0 <= (others => '0');
NOTE1 <= (others => '0');
osc_case <= '0';
aNOTE0 <= (others => '0');
aNOTE1 <= (others => '0');
ENABLE0 <= '0';
ENABLE1 <= '0';
elsif rising_edge(clk) then
OLD_NOTE <= NOTE_ON_OSC;
if NOTE_ON_OSC /= OLD_NOTE then
flag := '1';
else
flag := '0';
end if;
if flag = '1' then
case(osc_case) is
when '0' => aNOTE0 <= NOTE_ON_OSC;
osc_case <= NOT osc_case;
when '1' => aNOTE1 <= NOTE_ON_OSC;
osc_case <= NOT osc_case;
when others => --DO NOTHING
end case;
end if;
if NOTE_OFF_OSC = aNOTE0 then
ENABLE0 <= '0';
else
NOTE0 <= aNOTE0;
ENABLE0 <= '1';
end if;
if NOTE_OFF_OSC = aNOTE1 then
ENABLE1 <= '0';
else
NOTE1 <= aNOTE1;
ENABLE1 <= '1';
end if;
end if;
end process;
END behav; | mit | 1950d8a2a7c8ae35d2405a8c8081b036 | 0.554354 | 2.720588 | false | false | false | false |
tsotnep/vhdl_soc_audio_mixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/axi_hdmi_tx_16b_v1_00_a/hdl/vhdl/axi_hdmi_tx_16b.vhd | 3 | 11,922 | -- ***************************************************************************
-- ***************************************************************************
-- [email protected] (c) Analog Devices Inc.
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
entity axi_hdmi_tx_16b is
generic
(
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
);
port
(
hdmi_ref_clk : in std_logic;
hdmi_clk : out std_logic;
hdmi_vsync : out std_logic;
hdmi_hsync : out std_logic;
hdmi_data_e : out std_logic;
hdmi_data : out std_logic_vector(15 downto 0);
vdma_clk : in std_logic;
vdma_fs : out std_logic;
vdma_fs_ret : in std_logic;
vdma_empty : in std_logic;
vdma_almost_empty : in std_logic;
up_status : out std_logic_vector(7 downto 0);
debug_trigger : out std_logic_vector(7 downto 0);
debug_data : out std_logic_vector(63 downto 0);
M_AXIS_MM2S_TVALID : in std_logic;
M_AXIS_MM2S_TDATA : in std_logic_vector(63 downto 0);
M_AXIS_MM2S_TKEEP : in std_logic_vector(7 downto 0);
M_AXIS_MM2S_TLAST : in std_logic;
M_AXIS_MM2S_TREADY : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity axi_hdmi_tx_16b;
architecture IMP of axi_hdmi_tx_16b is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(ZERO_ADDR_PAD & USER_SLV_BASEADDR, ZERO_ADDR_PAD & USER_SLV_HIGHADDR);
constant USER_SLV_NUM_REG : integer := 32;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := (0 => (USER_SLV_NUM_REG));
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
component user_logic is
generic
(
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32
);
port
(
hdmi_ref_clk : in std_logic;
hdmi_clk : out std_logic;
hdmi_vsync : out std_logic;
hdmi_hsync : out std_logic;
hdmi_data_e : out std_logic;
hdmi_data : out std_logic_vector(15 downto 0);
vdma_clk : in std_logic;
vdma_fs : out std_logic;
vdma_fs_ret : in std_logic;
vdma_empty : in std_logic;
vdma_almost_empty : in std_logic;
vdma_valid : in std_logic;
vdma_data : in std_logic_vector(63 downto 0);
vdma_be : in std_logic_vector(7 downto 0);
vdma_last : in std_logic;
vdma_ready : out std_logic;
up_status : out std_logic_vector(7 downto 0);
debug_trigger : out std_logic_vector(7 downto 0);
debug_data : out std_logic_vector(63 downto 0);
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
);
end component user_logic;
begin
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
USER_LOGIC_I : component user_logic
generic map
(
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
hdmi_ref_clk => hdmi_ref_clk,
hdmi_clk => hdmi_clk,
hdmi_vsync => hdmi_vsync,
hdmi_hsync => hdmi_hsync,
hdmi_data_e => hdmi_data_e,
hdmi_data => hdmi_data,
vdma_clk => vdma_clk,
vdma_fs => vdma_fs,
vdma_fs_ret => vdma_fs_ret,
vdma_empty => vdma_empty,
vdma_almost_empty => vdma_almost_empty,
vdma_valid => M_AXIS_MM2S_TVALID,
vdma_data => M_AXIS_MM2S_TDATA,
vdma_be => M_AXIS_MM2S_TKEEP,
vdma_last => M_AXIS_MM2S_TLAST,
vdma_ready => M_AXIS_MM2S_TREADY,
up_status => up_status,
debug_trigger => debug_trigger,
debug_data => debug_data,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
-- ***************************************************************************
-- ***************************************************************************
| mit | da79bd33fe20b9eff885ce4a44260546 | 0.507633 | 3.304324 | false | false | false | false |
Nooxet/embedded_bruteforce | brutus_system/hdl/system.vhd | 1 | 145,040 | -------------------------------------------------------------------------------
-- system.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system is
port (
RS232_Uart_1_sout : out std_logic;
RS232_Uart_1_sin : in std_logic;
RESET : in std_logic;
Push_Buttons_4Bits_TRI_I : in std_logic_vector(0 to 3);
LEDs_8Bits_TRI_O : out std_logic_vector(7 downto 0);
GCLK : in std_logic;
DIP_Switches_8Bits_TRI_I : in std_logic_vector(7 downto 0)
);
end system;
architecture STRUCTURE of system is
component system_proc_sys_reset_0_wrapper is
port (
Slowest_sync_clk : in std_logic;
Ext_Reset_In : in std_logic;
Aux_Reset_In : in std_logic;
MB_Debug_Sys_Rst : in std_logic;
Core_Reset_Req_0 : in std_logic;
Chip_Reset_Req_0 : in std_logic;
System_Reset_Req_0 : in std_logic;
Core_Reset_Req_1 : in std_logic;
Chip_Reset_Req_1 : in std_logic;
System_Reset_Req_1 : in std_logic;
Dcm_locked : in std_logic;
RstcPPCresetcore_0 : out std_logic;
RstcPPCresetchip_0 : out std_logic;
RstcPPCresetsys_0 : out std_logic;
RstcPPCresetcore_1 : out std_logic;
RstcPPCresetchip_1 : out std_logic;
RstcPPCresetsys_1 : out std_logic;
MB_Reset : out std_logic;
Bus_Struct_Reset : out std_logic_vector(0 to 0);
Peripheral_Reset : out std_logic_vector(0 to 0);
Interconnect_aresetn : out std_logic_vector(0 to 0);
Peripheral_aresetn : out std_logic_vector(0 to 0)
);
end component;
component system_microblaze_0_ilmb_wrapper is
port (
LMB_Clk : in std_logic;
SYS_Rst : in std_logic;
LMB_Rst : out std_logic;
M_ABus : in std_logic_vector(0 to 31);
M_ReadStrobe : in std_logic;
M_WriteStrobe : in std_logic;
M_AddrStrobe : in std_logic;
M_DBus : in std_logic_vector(0 to 31);
M_BE : in std_logic_vector(0 to 3);
Sl_DBus : in std_logic_vector(0 to 31);
Sl_Ready : in std_logic_vector(0 to 0);
Sl_Wait : in std_logic_vector(0 to 0);
Sl_UE : in std_logic_vector(0 to 0);
Sl_CE : in std_logic_vector(0 to 0);
LMB_ABus : out std_logic_vector(0 to 31);
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_AddrStrobe : out std_logic;
LMB_ReadDBus : out std_logic_vector(0 to 31);
LMB_WriteDBus : out std_logic_vector(0 to 31);
LMB_Ready : out std_logic;
LMB_Wait : out std_logic;
LMB_UE : out std_logic;
LMB_CE : out std_logic;
LMB_BE : out std_logic_vector(0 to 3)
);
end component;
component system_microblaze_0_i_bram_ctrl_wrapper is
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to 31);
LMB_WriteDBus : in std_logic_vector(0 to 31);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to 3);
Sl_DBus : out std_logic_vector(0 to 31);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
LMB1_ABus : in std_logic_vector(0 to 31);
LMB1_WriteDBus : in std_logic_vector(0 to 31);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to 3);
Sl1_DBus : out std_logic_vector(0 to 31);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
LMB2_ABus : in std_logic_vector(0 to 31);
LMB2_WriteDBus : in std_logic_vector(0 to 31);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to 3);
Sl2_DBus : out std_logic_vector(0 to 31);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
LMB3_ABus : in std_logic_vector(0 to 31);
LMB3_WriteDBus : in std_logic_vector(0 to 31);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to 3);
Sl3_DBus : out std_logic_vector(0 to 31);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to 3);
BRAM_Addr_A : out std_logic_vector(0 to 31);
BRAM_Din_A : in std_logic_vector(0 to 31);
BRAM_Dout_A : out std_logic_vector(0 to 31);
Interrupt : out std_logic;
UE : out std_logic;
CE : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to 0);
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to 31);
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to 31);
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to 0);
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to 0);
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
end component;
component system_microblaze_0_dlmb_wrapper is
port (
LMB_Clk : in std_logic;
SYS_Rst : in std_logic;
LMB_Rst : out std_logic;
M_ABus : in std_logic_vector(0 to 31);
M_ReadStrobe : in std_logic;
M_WriteStrobe : in std_logic;
M_AddrStrobe : in std_logic;
M_DBus : in std_logic_vector(0 to 31);
M_BE : in std_logic_vector(0 to 3);
Sl_DBus : in std_logic_vector(0 to 31);
Sl_Ready : in std_logic_vector(0 to 0);
Sl_Wait : in std_logic_vector(0 to 0);
Sl_UE : in std_logic_vector(0 to 0);
Sl_CE : in std_logic_vector(0 to 0);
LMB_ABus : out std_logic_vector(0 to 31);
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_AddrStrobe : out std_logic;
LMB_ReadDBus : out std_logic_vector(0 to 31);
LMB_WriteDBus : out std_logic_vector(0 to 31);
LMB_Ready : out std_logic;
LMB_Wait : out std_logic;
LMB_UE : out std_logic;
LMB_CE : out std_logic;
LMB_BE : out std_logic_vector(0 to 3)
);
end component;
component system_microblaze_0_d_bram_ctrl_wrapper is
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to 31);
LMB_WriteDBus : in std_logic_vector(0 to 31);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to 3);
Sl_DBus : out std_logic_vector(0 to 31);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
LMB1_ABus : in std_logic_vector(0 to 31);
LMB1_WriteDBus : in std_logic_vector(0 to 31);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to 3);
Sl1_DBus : out std_logic_vector(0 to 31);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
LMB2_ABus : in std_logic_vector(0 to 31);
LMB2_WriteDBus : in std_logic_vector(0 to 31);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to 3);
Sl2_DBus : out std_logic_vector(0 to 31);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
LMB3_ABus : in std_logic_vector(0 to 31);
LMB3_WriteDBus : in std_logic_vector(0 to 31);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to 3);
Sl3_DBus : out std_logic_vector(0 to 31);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to 3);
BRAM_Addr_A : out std_logic_vector(0 to 31);
BRAM_Din_A : in std_logic_vector(0 to 31);
BRAM_Dout_A : out std_logic_vector(0 to 31);
Interrupt : out std_logic;
UE : out std_logic;
CE : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to 0);
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to 31);
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to 31);
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to 0);
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to 0);
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
end component;
component system_microblaze_0_bram_block_wrapper is
port (
BRAM_Rst_A : in std_logic;
BRAM_Clk_A : in std_logic;
BRAM_EN_A : in std_logic;
BRAM_WEN_A : in std_logic_vector(0 to 3);
BRAM_Addr_A : in std_logic_vector(0 to 31);
BRAM_Din_A : out std_logic_vector(0 to 31);
BRAM_Dout_A : in std_logic_vector(0 to 31);
BRAM_Rst_B : in std_logic;
BRAM_Clk_B : in std_logic;
BRAM_EN_B : in std_logic;
BRAM_WEN_B : in std_logic_vector(0 to 3);
BRAM_Addr_B : in std_logic_vector(0 to 31);
BRAM_Din_B : out std_logic_vector(0 to 31);
BRAM_Dout_B : in std_logic_vector(0 to 31)
);
end component;
component system_microblaze_0_wrapper is
port (
CLK : in std_logic;
RESET : in std_logic;
MB_RESET : in std_logic;
INTERRUPT : in std_logic;
INTERRUPT_ADDRESS : in std_logic_vector(0 to 31);
INTERRUPT_ACK : out std_logic_vector(0 to 1);
EXT_BRK : in std_logic;
EXT_NM_BRK : in std_logic;
DBG_STOP : in std_logic;
MB_Halted : out std_logic;
MB_Error : out std_logic;
WAKEUP : in std_logic_vector(0 to 1);
SLEEP : out std_logic;
DBG_WAKEUP : out std_logic;
LOCKSTEP_MASTER_OUT : out std_logic_vector(0 to 4095);
LOCKSTEP_SLAVE_IN : in std_logic_vector(0 to 4095);
LOCKSTEP_OUT : out std_logic_vector(0 to 4095);
INSTR : in std_logic_vector(0 to 31);
IREADY : in std_logic;
IWAIT : in std_logic;
ICE : in std_logic;
IUE : in std_logic;
INSTR_ADDR : out std_logic_vector(0 to 31);
IFETCH : out std_logic;
I_AS : out std_logic;
IPLB_M_ABort : out std_logic;
IPLB_M_ABus : out std_logic_vector(0 to 31);
IPLB_M_UABus : out std_logic_vector(0 to 31);
IPLB_M_BE : out std_logic_vector(0 to 3);
IPLB_M_busLock : out std_logic;
IPLB_M_lockErr : out std_logic;
IPLB_M_MSize : out std_logic_vector(0 to 1);
IPLB_M_priority : out std_logic_vector(0 to 1);
IPLB_M_rdBurst : out std_logic;
IPLB_M_request : out std_logic;
IPLB_M_RNW : out std_logic;
IPLB_M_size : out std_logic_vector(0 to 3);
IPLB_M_TAttribute : out std_logic_vector(0 to 15);
IPLB_M_type : out std_logic_vector(0 to 2);
IPLB_M_wrBurst : out std_logic;
IPLB_M_wrDBus : out std_logic_vector(0 to 31);
IPLB_MBusy : in std_logic;
IPLB_MRdErr : in std_logic;
IPLB_MWrErr : in std_logic;
IPLB_MIRQ : in std_logic;
IPLB_MWrBTerm : in std_logic;
IPLB_MWrDAck : in std_logic;
IPLB_MAddrAck : in std_logic;
IPLB_MRdBTerm : in std_logic;
IPLB_MRdDAck : in std_logic;
IPLB_MRdDBus : in std_logic_vector(0 to 31);
IPLB_MRdWdAddr : in std_logic_vector(0 to 3);
IPLB_MRearbitrate : in std_logic;
IPLB_MSSize : in std_logic_vector(0 to 1);
IPLB_MTimeout : in std_logic;
DATA_READ : in std_logic_vector(0 to 31);
DREADY : in std_logic;
DWAIT : in std_logic;
DCE : in std_logic;
DUE : in std_logic;
DATA_WRITE : out std_logic_vector(0 to 31);
DATA_ADDR : out std_logic_vector(0 to 31);
D_AS : out std_logic;
READ_STROBE : out std_logic;
WRITE_STROBE : out std_logic;
BYTE_ENABLE : out std_logic_vector(0 to 3);
DPLB_M_ABort : out std_logic;
DPLB_M_ABus : out std_logic_vector(0 to 31);
DPLB_M_UABus : out std_logic_vector(0 to 31);
DPLB_M_BE : out std_logic_vector(0 to 3);
DPLB_M_busLock : out std_logic;
DPLB_M_lockErr : out std_logic;
DPLB_M_MSize : out std_logic_vector(0 to 1);
DPLB_M_priority : out std_logic_vector(0 to 1);
DPLB_M_rdBurst : out std_logic;
DPLB_M_request : out std_logic;
DPLB_M_RNW : out std_logic;
DPLB_M_size : out std_logic_vector(0 to 3);
DPLB_M_TAttribute : out std_logic_vector(0 to 15);
DPLB_M_type : out std_logic_vector(0 to 2);
DPLB_M_wrBurst : out std_logic;
DPLB_M_wrDBus : out std_logic_vector(0 to 31);
DPLB_MBusy : in std_logic;
DPLB_MRdErr : in std_logic;
DPLB_MWrErr : in std_logic;
DPLB_MIRQ : in std_logic;
DPLB_MWrBTerm : in std_logic;
DPLB_MWrDAck : in std_logic;
DPLB_MAddrAck : in std_logic;
DPLB_MRdBTerm : in std_logic;
DPLB_MRdDAck : in std_logic;
DPLB_MRdDBus : in std_logic_vector(0 to 31);
DPLB_MRdWdAddr : in std_logic_vector(0 to 3);
DPLB_MRearbitrate : in std_logic;
DPLB_MSSize : in std_logic_vector(0 to 1);
DPLB_MTimeout : in std_logic;
M_AXI_IP_AWID : out std_logic_vector(0 downto 0);
M_AXI_IP_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_IP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_AWLOCK : out std_logic;
M_AXI_IP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_AWVALID : out std_logic;
M_AXI_IP_AWREADY : in std_logic;
M_AXI_IP_WDATA : out std_logic_vector(31 downto 0);
M_AXI_IP_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_IP_WLAST : out std_logic;
M_AXI_IP_WVALID : out std_logic;
M_AXI_IP_WREADY : in std_logic;
M_AXI_IP_BID : in std_logic_vector(0 downto 0);
M_AXI_IP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_BVALID : in std_logic;
M_AXI_IP_BREADY : out std_logic;
M_AXI_IP_ARID : out std_logic_vector(0 downto 0);
M_AXI_IP_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_IP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_ARLOCK : out std_logic;
M_AXI_IP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_ARVALID : out std_logic;
M_AXI_IP_ARREADY : in std_logic;
M_AXI_IP_RID : in std_logic_vector(0 downto 0);
M_AXI_IP_RDATA : in std_logic_vector(31 downto 0);
M_AXI_IP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_RLAST : in std_logic;
M_AXI_IP_RVALID : in std_logic;
M_AXI_IP_RREADY : out std_logic;
M_AXI_DP_AWID : out std_logic_vector(0 downto 0);
M_AXI_DP_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_DP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_AWLOCK : out std_logic;
M_AXI_DP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_AWVALID : out std_logic;
M_AXI_DP_AWREADY : in std_logic;
M_AXI_DP_WDATA : out std_logic_vector(31 downto 0);
M_AXI_DP_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_DP_WLAST : out std_logic;
M_AXI_DP_WVALID : out std_logic;
M_AXI_DP_WREADY : in std_logic;
M_AXI_DP_BID : in std_logic_vector(0 downto 0);
M_AXI_DP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_BVALID : in std_logic;
M_AXI_DP_BREADY : out std_logic;
M_AXI_DP_ARID : out std_logic_vector(0 downto 0);
M_AXI_DP_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_DP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_ARLOCK : out std_logic;
M_AXI_DP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_ARVALID : out std_logic;
M_AXI_DP_ARREADY : in std_logic;
M_AXI_DP_RID : in std_logic_vector(0 downto 0);
M_AXI_DP_RDATA : in std_logic_vector(31 downto 0);
M_AXI_DP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_RLAST : in std_logic;
M_AXI_DP_RVALID : in std_logic;
M_AXI_DP_RREADY : out std_logic;
M_AXI_IC_AWID : out std_logic_vector(0 downto 0);
M_AXI_IC_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_IC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_AWLOCK : out std_logic;
M_AXI_IC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_AWVALID : out std_logic;
M_AXI_IC_AWREADY : in std_logic;
M_AXI_IC_AWUSER : out std_logic_vector(4 downto 0);
M_AXI_IC_WDATA : out std_logic_vector(31 downto 0);
M_AXI_IC_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_IC_WLAST : out std_logic;
M_AXI_IC_WVALID : out std_logic;
M_AXI_IC_WREADY : in std_logic;
M_AXI_IC_WUSER : out std_logic_vector(0 downto 0);
M_AXI_IC_BID : in std_logic_vector(0 downto 0);
M_AXI_IC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_BVALID : in std_logic;
M_AXI_IC_BREADY : out std_logic;
M_AXI_IC_BUSER : in std_logic_vector(0 downto 0);
M_AXI_IC_ARID : out std_logic_vector(0 downto 0);
M_AXI_IC_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_IC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_ARLOCK : out std_logic;
M_AXI_IC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_ARVALID : out std_logic;
M_AXI_IC_ARREADY : in std_logic;
M_AXI_IC_ARUSER : out std_logic_vector(4 downto 0);
M_AXI_IC_RID : in std_logic_vector(0 downto 0);
M_AXI_IC_RDATA : in std_logic_vector(31 downto 0);
M_AXI_IC_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_RLAST : in std_logic;
M_AXI_IC_RVALID : in std_logic;
M_AXI_IC_RREADY : out std_logic;
M_AXI_IC_RUSER : in std_logic_vector(0 downto 0);
M_AXI_DC_AWID : out std_logic_vector(0 downto 0);
M_AXI_DC_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_DC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_AWLOCK : out std_logic;
M_AXI_DC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_AWVALID : out std_logic;
M_AXI_DC_AWREADY : in std_logic;
M_AXI_DC_AWUSER : out std_logic_vector(4 downto 0);
M_AXI_DC_WDATA : out std_logic_vector(31 downto 0);
M_AXI_DC_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_DC_WLAST : out std_logic;
M_AXI_DC_WVALID : out std_logic;
M_AXI_DC_WREADY : in std_logic;
M_AXI_DC_WUSER : out std_logic_vector(0 downto 0);
M_AXI_DC_BID : in std_logic_vector(0 downto 0);
M_AXI_DC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_BVALID : in std_logic;
M_AXI_DC_BREADY : out std_logic;
M_AXI_DC_BUSER : in std_logic_vector(0 downto 0);
M_AXI_DC_ARID : out std_logic_vector(0 downto 0);
M_AXI_DC_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_DC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_ARLOCK : out std_logic;
M_AXI_DC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_ARVALID : out std_logic;
M_AXI_DC_ARREADY : in std_logic;
M_AXI_DC_ARUSER : out std_logic_vector(4 downto 0);
M_AXI_DC_RID : in std_logic_vector(0 downto 0);
M_AXI_DC_RDATA : in std_logic_vector(31 downto 0);
M_AXI_DC_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_RLAST : in std_logic;
M_AXI_DC_RVALID : in std_logic;
M_AXI_DC_RREADY : out std_logic;
M_AXI_DC_RUSER : in std_logic_vector(0 downto 0);
DBG_CLK : in std_logic;
DBG_TDI : in std_logic;
DBG_TDO : out std_logic;
DBG_REG_EN : in std_logic_vector(0 to 7);
DBG_SHIFT : in std_logic;
DBG_CAPTURE : in std_logic;
DBG_UPDATE : in std_logic;
DEBUG_RST : in std_logic;
Trace_Instruction : out std_logic_vector(0 to 31);
Trace_Valid_Instr : out std_logic;
Trace_PC : out std_logic_vector(0 to 31);
Trace_Reg_Write : out std_logic;
Trace_Reg_Addr : out std_logic_vector(0 to 4);
Trace_MSR_Reg : out std_logic_vector(0 to 14);
Trace_PID_Reg : out std_logic_vector(0 to 7);
Trace_New_Reg_Value : out std_logic_vector(0 to 31);
Trace_Exception_Taken : out std_logic;
Trace_Exception_Kind : out std_logic_vector(0 to 4);
Trace_Jump_Taken : out std_logic;
Trace_Delay_Slot : out std_logic;
Trace_Data_Address : out std_logic_vector(0 to 31);
Trace_Data_Access : out std_logic;
Trace_Data_Read : out std_logic;
Trace_Data_Write : out std_logic;
Trace_Data_Write_Value : out std_logic_vector(0 to 31);
Trace_Data_Byte_Enable : out std_logic_vector(0 to 3);
Trace_DCache_Req : out std_logic;
Trace_DCache_Hit : out std_logic;
Trace_DCache_Rdy : out std_logic;
Trace_DCache_Read : out std_logic;
Trace_ICache_Req : out std_logic;
Trace_ICache_Hit : out std_logic;
Trace_ICache_Rdy : out std_logic;
Trace_OF_PipeRun : out std_logic;
Trace_EX_PipeRun : out std_logic;
Trace_MEM_PipeRun : out std_logic;
Trace_MB_Halted : out std_logic;
Trace_Jump_Hit : out std_logic;
FSL0_S_CLK : out std_logic;
FSL0_S_READ : out std_logic;
FSL0_S_DATA : in std_logic_vector(0 to 31);
FSL0_S_CONTROL : in std_logic;
FSL0_S_EXISTS : in std_logic;
FSL0_M_CLK : out std_logic;
FSL0_M_WRITE : out std_logic;
FSL0_M_DATA : out std_logic_vector(0 to 31);
FSL0_M_CONTROL : out std_logic;
FSL0_M_FULL : in std_logic;
FSL1_S_CLK : out std_logic;
FSL1_S_READ : out std_logic;
FSL1_S_DATA : in std_logic_vector(0 to 31);
FSL1_S_CONTROL : in std_logic;
FSL1_S_EXISTS : in std_logic;
FSL1_M_CLK : out std_logic;
FSL1_M_WRITE : out std_logic;
FSL1_M_DATA : out std_logic_vector(0 to 31);
FSL1_M_CONTROL : out std_logic;
FSL1_M_FULL : in std_logic;
FSL2_S_CLK : out std_logic;
FSL2_S_READ : out std_logic;
FSL2_S_DATA : in std_logic_vector(0 to 31);
FSL2_S_CONTROL : in std_logic;
FSL2_S_EXISTS : in std_logic;
FSL2_M_CLK : out std_logic;
FSL2_M_WRITE : out std_logic;
FSL2_M_DATA : out std_logic_vector(0 to 31);
FSL2_M_CONTROL : out std_logic;
FSL2_M_FULL : in std_logic;
FSL3_S_CLK : out std_logic;
FSL3_S_READ : out std_logic;
FSL3_S_DATA : in std_logic_vector(0 to 31);
FSL3_S_CONTROL : in std_logic;
FSL3_S_EXISTS : in std_logic;
FSL3_M_CLK : out std_logic;
FSL3_M_WRITE : out std_logic;
FSL3_M_DATA : out std_logic_vector(0 to 31);
FSL3_M_CONTROL : out std_logic;
FSL3_M_FULL : in std_logic;
FSL4_S_CLK : out std_logic;
FSL4_S_READ : out std_logic;
FSL4_S_DATA : in std_logic_vector(0 to 31);
FSL4_S_CONTROL : in std_logic;
FSL4_S_EXISTS : in std_logic;
FSL4_M_CLK : out std_logic;
FSL4_M_WRITE : out std_logic;
FSL4_M_DATA : out std_logic_vector(0 to 31);
FSL4_M_CONTROL : out std_logic;
FSL4_M_FULL : in std_logic;
FSL5_S_CLK : out std_logic;
FSL5_S_READ : out std_logic;
FSL5_S_DATA : in std_logic_vector(0 to 31);
FSL5_S_CONTROL : in std_logic;
FSL5_S_EXISTS : in std_logic;
FSL5_M_CLK : out std_logic;
FSL5_M_WRITE : out std_logic;
FSL5_M_DATA : out std_logic_vector(0 to 31);
FSL5_M_CONTROL : out std_logic;
FSL5_M_FULL : in std_logic;
FSL6_S_CLK : out std_logic;
FSL6_S_READ : out std_logic;
FSL6_S_DATA : in std_logic_vector(0 to 31);
FSL6_S_CONTROL : in std_logic;
FSL6_S_EXISTS : in std_logic;
FSL6_M_CLK : out std_logic;
FSL6_M_WRITE : out std_logic;
FSL6_M_DATA : out std_logic_vector(0 to 31);
FSL6_M_CONTROL : out std_logic;
FSL6_M_FULL : in std_logic;
FSL7_S_CLK : out std_logic;
FSL7_S_READ : out std_logic;
FSL7_S_DATA : in std_logic_vector(0 to 31);
FSL7_S_CONTROL : in std_logic;
FSL7_S_EXISTS : in std_logic;
FSL7_M_CLK : out std_logic;
FSL7_M_WRITE : out std_logic;
FSL7_M_DATA : out std_logic_vector(0 to 31);
FSL7_M_CONTROL : out std_logic;
FSL7_M_FULL : in std_logic;
FSL8_S_CLK : out std_logic;
FSL8_S_READ : out std_logic;
FSL8_S_DATA : in std_logic_vector(0 to 31);
FSL8_S_CONTROL : in std_logic;
FSL8_S_EXISTS : in std_logic;
FSL8_M_CLK : out std_logic;
FSL8_M_WRITE : out std_logic;
FSL8_M_DATA : out std_logic_vector(0 to 31);
FSL8_M_CONTROL : out std_logic;
FSL8_M_FULL : in std_logic;
FSL9_S_CLK : out std_logic;
FSL9_S_READ : out std_logic;
FSL9_S_DATA : in std_logic_vector(0 to 31);
FSL9_S_CONTROL : in std_logic;
FSL9_S_EXISTS : in std_logic;
FSL9_M_CLK : out std_logic;
FSL9_M_WRITE : out std_logic;
FSL9_M_DATA : out std_logic_vector(0 to 31);
FSL9_M_CONTROL : out std_logic;
FSL9_M_FULL : in std_logic;
FSL10_S_CLK : out std_logic;
FSL10_S_READ : out std_logic;
FSL10_S_DATA : in std_logic_vector(0 to 31);
FSL10_S_CONTROL : in std_logic;
FSL10_S_EXISTS : in std_logic;
FSL10_M_CLK : out std_logic;
FSL10_M_WRITE : out std_logic;
FSL10_M_DATA : out std_logic_vector(0 to 31);
FSL10_M_CONTROL : out std_logic;
FSL10_M_FULL : in std_logic;
FSL11_S_CLK : out std_logic;
FSL11_S_READ : out std_logic;
FSL11_S_DATA : in std_logic_vector(0 to 31);
FSL11_S_CONTROL : in std_logic;
FSL11_S_EXISTS : in std_logic;
FSL11_M_CLK : out std_logic;
FSL11_M_WRITE : out std_logic;
FSL11_M_DATA : out std_logic_vector(0 to 31);
FSL11_M_CONTROL : out std_logic;
FSL11_M_FULL : in std_logic;
FSL12_S_CLK : out std_logic;
FSL12_S_READ : out std_logic;
FSL12_S_DATA : in std_logic_vector(0 to 31);
FSL12_S_CONTROL : in std_logic;
FSL12_S_EXISTS : in std_logic;
FSL12_M_CLK : out std_logic;
FSL12_M_WRITE : out std_logic;
FSL12_M_DATA : out std_logic_vector(0 to 31);
FSL12_M_CONTROL : out std_logic;
FSL12_M_FULL : in std_logic;
FSL13_S_CLK : out std_logic;
FSL13_S_READ : out std_logic;
FSL13_S_DATA : in std_logic_vector(0 to 31);
FSL13_S_CONTROL : in std_logic;
FSL13_S_EXISTS : in std_logic;
FSL13_M_CLK : out std_logic;
FSL13_M_WRITE : out std_logic;
FSL13_M_DATA : out std_logic_vector(0 to 31);
FSL13_M_CONTROL : out std_logic;
FSL13_M_FULL : in std_logic;
FSL14_S_CLK : out std_logic;
FSL14_S_READ : out std_logic;
FSL14_S_DATA : in std_logic_vector(0 to 31);
FSL14_S_CONTROL : in std_logic;
FSL14_S_EXISTS : in std_logic;
FSL14_M_CLK : out std_logic;
FSL14_M_WRITE : out std_logic;
FSL14_M_DATA : out std_logic_vector(0 to 31);
FSL14_M_CONTROL : out std_logic;
FSL14_M_FULL : in std_logic;
FSL15_S_CLK : out std_logic;
FSL15_S_READ : out std_logic;
FSL15_S_DATA : in std_logic_vector(0 to 31);
FSL15_S_CONTROL : in std_logic;
FSL15_S_EXISTS : in std_logic;
FSL15_M_CLK : out std_logic;
FSL15_M_WRITE : out std_logic;
FSL15_M_DATA : out std_logic_vector(0 to 31);
FSL15_M_CONTROL : out std_logic;
FSL15_M_FULL : in std_logic;
M0_AXIS_TLAST : out std_logic;
M0_AXIS_TDATA : out std_logic_vector(31 downto 0);
M0_AXIS_TVALID : out std_logic;
M0_AXIS_TREADY : in std_logic;
S0_AXIS_TLAST : in std_logic;
S0_AXIS_TDATA : in std_logic_vector(31 downto 0);
S0_AXIS_TVALID : in std_logic;
S0_AXIS_TREADY : out std_logic;
M1_AXIS_TLAST : out std_logic;
M1_AXIS_TDATA : out std_logic_vector(31 downto 0);
M1_AXIS_TVALID : out std_logic;
M1_AXIS_TREADY : in std_logic;
S1_AXIS_TLAST : in std_logic;
S1_AXIS_TDATA : in std_logic_vector(31 downto 0);
S1_AXIS_TVALID : in std_logic;
S1_AXIS_TREADY : out std_logic;
M2_AXIS_TLAST : out std_logic;
M2_AXIS_TDATA : out std_logic_vector(31 downto 0);
M2_AXIS_TVALID : out std_logic;
M2_AXIS_TREADY : in std_logic;
S2_AXIS_TLAST : in std_logic;
S2_AXIS_TDATA : in std_logic_vector(31 downto 0);
S2_AXIS_TVALID : in std_logic;
S2_AXIS_TREADY : out std_logic;
M3_AXIS_TLAST : out std_logic;
M3_AXIS_TDATA : out std_logic_vector(31 downto 0);
M3_AXIS_TVALID : out std_logic;
M3_AXIS_TREADY : in std_logic;
S3_AXIS_TLAST : in std_logic;
S3_AXIS_TDATA : in std_logic_vector(31 downto 0);
S3_AXIS_TVALID : in std_logic;
S3_AXIS_TREADY : out std_logic;
M4_AXIS_TLAST : out std_logic;
M4_AXIS_TDATA : out std_logic_vector(31 downto 0);
M4_AXIS_TVALID : out std_logic;
M4_AXIS_TREADY : in std_logic;
S4_AXIS_TLAST : in std_logic;
S4_AXIS_TDATA : in std_logic_vector(31 downto 0);
S4_AXIS_TVALID : in std_logic;
S4_AXIS_TREADY : out std_logic;
M5_AXIS_TLAST : out std_logic;
M5_AXIS_TDATA : out std_logic_vector(31 downto 0);
M5_AXIS_TVALID : out std_logic;
M5_AXIS_TREADY : in std_logic;
S5_AXIS_TLAST : in std_logic;
S5_AXIS_TDATA : in std_logic_vector(31 downto 0);
S5_AXIS_TVALID : in std_logic;
S5_AXIS_TREADY : out std_logic;
M6_AXIS_TLAST : out std_logic;
M6_AXIS_TDATA : out std_logic_vector(31 downto 0);
M6_AXIS_TVALID : out std_logic;
M6_AXIS_TREADY : in std_logic;
S6_AXIS_TLAST : in std_logic;
S6_AXIS_TDATA : in std_logic_vector(31 downto 0);
S6_AXIS_TVALID : in std_logic;
S6_AXIS_TREADY : out std_logic;
M7_AXIS_TLAST : out std_logic;
M7_AXIS_TDATA : out std_logic_vector(31 downto 0);
M7_AXIS_TVALID : out std_logic;
M7_AXIS_TREADY : in std_logic;
S7_AXIS_TLAST : in std_logic;
S7_AXIS_TDATA : in std_logic_vector(31 downto 0);
S7_AXIS_TVALID : in std_logic;
S7_AXIS_TREADY : out std_logic;
M8_AXIS_TLAST : out std_logic;
M8_AXIS_TDATA : out std_logic_vector(31 downto 0);
M8_AXIS_TVALID : out std_logic;
M8_AXIS_TREADY : in std_logic;
S8_AXIS_TLAST : in std_logic;
S8_AXIS_TDATA : in std_logic_vector(31 downto 0);
S8_AXIS_TVALID : in std_logic;
S8_AXIS_TREADY : out std_logic;
M9_AXIS_TLAST : out std_logic;
M9_AXIS_TDATA : out std_logic_vector(31 downto 0);
M9_AXIS_TVALID : out std_logic;
M9_AXIS_TREADY : in std_logic;
S9_AXIS_TLAST : in std_logic;
S9_AXIS_TDATA : in std_logic_vector(31 downto 0);
S9_AXIS_TVALID : in std_logic;
S9_AXIS_TREADY : out std_logic;
M10_AXIS_TLAST : out std_logic;
M10_AXIS_TDATA : out std_logic_vector(31 downto 0);
M10_AXIS_TVALID : out std_logic;
M10_AXIS_TREADY : in std_logic;
S10_AXIS_TLAST : in std_logic;
S10_AXIS_TDATA : in std_logic_vector(31 downto 0);
S10_AXIS_TVALID : in std_logic;
S10_AXIS_TREADY : out std_logic;
M11_AXIS_TLAST : out std_logic;
M11_AXIS_TDATA : out std_logic_vector(31 downto 0);
M11_AXIS_TVALID : out std_logic;
M11_AXIS_TREADY : in std_logic;
S11_AXIS_TLAST : in std_logic;
S11_AXIS_TDATA : in std_logic_vector(31 downto 0);
S11_AXIS_TVALID : in std_logic;
S11_AXIS_TREADY : out std_logic;
M12_AXIS_TLAST : out std_logic;
M12_AXIS_TDATA : out std_logic_vector(31 downto 0);
M12_AXIS_TVALID : out std_logic;
M12_AXIS_TREADY : in std_logic;
S12_AXIS_TLAST : in std_logic;
S12_AXIS_TDATA : in std_logic_vector(31 downto 0);
S12_AXIS_TVALID : in std_logic;
S12_AXIS_TREADY : out std_logic;
M13_AXIS_TLAST : out std_logic;
M13_AXIS_TDATA : out std_logic_vector(31 downto 0);
M13_AXIS_TVALID : out std_logic;
M13_AXIS_TREADY : in std_logic;
S13_AXIS_TLAST : in std_logic;
S13_AXIS_TDATA : in std_logic_vector(31 downto 0);
S13_AXIS_TVALID : in std_logic;
S13_AXIS_TREADY : out std_logic;
M14_AXIS_TLAST : out std_logic;
M14_AXIS_TDATA : out std_logic_vector(31 downto 0);
M14_AXIS_TVALID : out std_logic;
M14_AXIS_TREADY : in std_logic;
S14_AXIS_TLAST : in std_logic;
S14_AXIS_TDATA : in std_logic_vector(31 downto 0);
S14_AXIS_TVALID : in std_logic;
S14_AXIS_TREADY : out std_logic;
M15_AXIS_TLAST : out std_logic;
M15_AXIS_TDATA : out std_logic_vector(31 downto 0);
M15_AXIS_TVALID : out std_logic;
M15_AXIS_TREADY : in std_logic;
S15_AXIS_TLAST : in std_logic;
S15_AXIS_TDATA : in std_logic_vector(31 downto 0);
S15_AXIS_TVALID : in std_logic;
S15_AXIS_TREADY : out std_logic;
ICACHE_FSL_IN_CLK : out std_logic;
ICACHE_FSL_IN_READ : out std_logic;
ICACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
ICACHE_FSL_IN_CONTROL : in std_logic;
ICACHE_FSL_IN_EXISTS : in std_logic;
ICACHE_FSL_OUT_CLK : out std_logic;
ICACHE_FSL_OUT_WRITE : out std_logic;
ICACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
ICACHE_FSL_OUT_CONTROL : out std_logic;
ICACHE_FSL_OUT_FULL : in std_logic;
DCACHE_FSL_IN_CLK : out std_logic;
DCACHE_FSL_IN_READ : out std_logic;
DCACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
DCACHE_FSL_IN_CONTROL : in std_logic;
DCACHE_FSL_IN_EXISTS : in std_logic;
DCACHE_FSL_OUT_CLK : out std_logic;
DCACHE_FSL_OUT_WRITE : out std_logic;
DCACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
DCACHE_FSL_OUT_CONTROL : out std_logic;
DCACHE_FSL_OUT_FULL : in std_logic
);
end component;
component system_debug_module_wrapper is
port (
Interrupt : out std_logic;
Debug_SYS_Rst : out std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 2);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 3);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 31);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 31);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 7);
Sl_MWrErr : out std_logic_vector(0 to 7);
Sl_MRdErr : out std_logic_vector(0 to 7);
Sl_MIRQ : out std_logic_vector(0 to 7);
Dbg_Clk_0 : out std_logic;
Dbg_TDI_0 : out std_logic;
Dbg_TDO_0 : in std_logic;
Dbg_Reg_En_0 : out std_logic_vector(0 to 7);
Dbg_Capture_0 : out std_logic;
Dbg_Shift_0 : out std_logic;
Dbg_Update_0 : out std_logic;
Dbg_Rst_0 : out std_logic;
Dbg_Clk_1 : out std_logic;
Dbg_TDI_1 : out std_logic;
Dbg_TDO_1 : in std_logic;
Dbg_Reg_En_1 : out std_logic_vector(0 to 7);
Dbg_Capture_1 : out std_logic;
Dbg_Shift_1 : out std_logic;
Dbg_Update_1 : out std_logic;
Dbg_Rst_1 : out std_logic;
Dbg_Clk_2 : out std_logic;
Dbg_TDI_2 : out std_logic;
Dbg_TDO_2 : in std_logic;
Dbg_Reg_En_2 : out std_logic_vector(0 to 7);
Dbg_Capture_2 : out std_logic;
Dbg_Shift_2 : out std_logic;
Dbg_Update_2 : out std_logic;
Dbg_Rst_2 : out std_logic;
Dbg_Clk_3 : out std_logic;
Dbg_TDI_3 : out std_logic;
Dbg_TDO_3 : in std_logic;
Dbg_Reg_En_3 : out std_logic_vector(0 to 7);
Dbg_Capture_3 : out std_logic;
Dbg_Shift_3 : out std_logic;
Dbg_Update_3 : out std_logic;
Dbg_Rst_3 : out std_logic;
Dbg_Clk_4 : out std_logic;
Dbg_TDI_4 : out std_logic;
Dbg_TDO_4 : in std_logic;
Dbg_Reg_En_4 : out std_logic_vector(0 to 7);
Dbg_Capture_4 : out std_logic;
Dbg_Shift_4 : out std_logic;
Dbg_Update_4 : out std_logic;
Dbg_Rst_4 : out std_logic;
Dbg_Clk_5 : out std_logic;
Dbg_TDI_5 : out std_logic;
Dbg_TDO_5 : in std_logic;
Dbg_Reg_En_5 : out std_logic_vector(0 to 7);
Dbg_Capture_5 : out std_logic;
Dbg_Shift_5 : out std_logic;
Dbg_Update_5 : out std_logic;
Dbg_Rst_5 : out std_logic;
Dbg_Clk_6 : out std_logic;
Dbg_TDI_6 : out std_logic;
Dbg_TDO_6 : in std_logic;
Dbg_Reg_En_6 : out std_logic_vector(0 to 7);
Dbg_Capture_6 : out std_logic;
Dbg_Shift_6 : out std_logic;
Dbg_Update_6 : out std_logic;
Dbg_Rst_6 : out std_logic;
Dbg_Clk_7 : out std_logic;
Dbg_TDI_7 : out std_logic;
Dbg_TDO_7 : in std_logic;
Dbg_Reg_En_7 : out std_logic_vector(0 to 7);
Dbg_Capture_7 : out std_logic;
Dbg_Shift_7 : out std_logic;
Dbg_Update_7 : out std_logic;
Dbg_Rst_7 : out std_logic;
Dbg_Clk_8 : out std_logic;
Dbg_TDI_8 : out std_logic;
Dbg_TDO_8 : in std_logic;
Dbg_Reg_En_8 : out std_logic_vector(0 to 7);
Dbg_Capture_8 : out std_logic;
Dbg_Shift_8 : out std_logic;
Dbg_Update_8 : out std_logic;
Dbg_Rst_8 : out std_logic;
Dbg_Clk_9 : out std_logic;
Dbg_TDI_9 : out std_logic;
Dbg_TDO_9 : in std_logic;
Dbg_Reg_En_9 : out std_logic_vector(0 to 7);
Dbg_Capture_9 : out std_logic;
Dbg_Shift_9 : out std_logic;
Dbg_Update_9 : out std_logic;
Dbg_Rst_9 : out std_logic;
Dbg_Clk_10 : out std_logic;
Dbg_TDI_10 : out std_logic;
Dbg_TDO_10 : in std_logic;
Dbg_Reg_En_10 : out std_logic_vector(0 to 7);
Dbg_Capture_10 : out std_logic;
Dbg_Shift_10 : out std_logic;
Dbg_Update_10 : out std_logic;
Dbg_Rst_10 : out std_logic;
Dbg_Clk_11 : out std_logic;
Dbg_TDI_11 : out std_logic;
Dbg_TDO_11 : in std_logic;
Dbg_Reg_En_11 : out std_logic_vector(0 to 7);
Dbg_Capture_11 : out std_logic;
Dbg_Shift_11 : out std_logic;
Dbg_Update_11 : out std_logic;
Dbg_Rst_11 : out std_logic;
Dbg_Clk_12 : out std_logic;
Dbg_TDI_12 : out std_logic;
Dbg_TDO_12 : in std_logic;
Dbg_Reg_En_12 : out std_logic_vector(0 to 7);
Dbg_Capture_12 : out std_logic;
Dbg_Shift_12 : out std_logic;
Dbg_Update_12 : out std_logic;
Dbg_Rst_12 : out std_logic;
Dbg_Clk_13 : out std_logic;
Dbg_TDI_13 : out std_logic;
Dbg_TDO_13 : in std_logic;
Dbg_Reg_En_13 : out std_logic_vector(0 to 7);
Dbg_Capture_13 : out std_logic;
Dbg_Shift_13 : out std_logic;
Dbg_Update_13 : out std_logic;
Dbg_Rst_13 : out std_logic;
Dbg_Clk_14 : out std_logic;
Dbg_TDI_14 : out std_logic;
Dbg_TDO_14 : in std_logic;
Dbg_Reg_En_14 : out std_logic_vector(0 to 7);
Dbg_Capture_14 : out std_logic;
Dbg_Shift_14 : out std_logic;
Dbg_Update_14 : out std_logic;
Dbg_Rst_14 : out std_logic;
Dbg_Clk_15 : out std_logic;
Dbg_TDI_15 : out std_logic;
Dbg_TDO_15 : in std_logic;
Dbg_Reg_En_15 : out std_logic_vector(0 to 7);
Dbg_Capture_15 : out std_logic;
Dbg_Shift_15 : out std_logic;
Dbg_Update_15 : out std_logic;
Dbg_Rst_15 : out std_logic;
Dbg_Clk_16 : out std_logic;
Dbg_TDI_16 : out std_logic;
Dbg_TDO_16 : in std_logic;
Dbg_Reg_En_16 : out std_logic_vector(0 to 7);
Dbg_Capture_16 : out std_logic;
Dbg_Shift_16 : out std_logic;
Dbg_Update_16 : out std_logic;
Dbg_Rst_16 : out std_logic;
Dbg_Clk_17 : out std_logic;
Dbg_TDI_17 : out std_logic;
Dbg_TDO_17 : in std_logic;
Dbg_Reg_En_17 : out std_logic_vector(0 to 7);
Dbg_Capture_17 : out std_logic;
Dbg_Shift_17 : out std_logic;
Dbg_Update_17 : out std_logic;
Dbg_Rst_17 : out std_logic;
Dbg_Clk_18 : out std_logic;
Dbg_TDI_18 : out std_logic;
Dbg_TDO_18 : in std_logic;
Dbg_Reg_En_18 : out std_logic_vector(0 to 7);
Dbg_Capture_18 : out std_logic;
Dbg_Shift_18 : out std_logic;
Dbg_Update_18 : out std_logic;
Dbg_Rst_18 : out std_logic;
Dbg_Clk_19 : out std_logic;
Dbg_TDI_19 : out std_logic;
Dbg_TDO_19 : in std_logic;
Dbg_Reg_En_19 : out std_logic_vector(0 to 7);
Dbg_Capture_19 : out std_logic;
Dbg_Shift_19 : out std_logic;
Dbg_Update_19 : out std_logic;
Dbg_Rst_19 : out std_logic;
Dbg_Clk_20 : out std_logic;
Dbg_TDI_20 : out std_logic;
Dbg_TDO_20 : in std_logic;
Dbg_Reg_En_20 : out std_logic_vector(0 to 7);
Dbg_Capture_20 : out std_logic;
Dbg_Shift_20 : out std_logic;
Dbg_Update_20 : out std_logic;
Dbg_Rst_20 : out std_logic;
Dbg_Clk_21 : out std_logic;
Dbg_TDI_21 : out std_logic;
Dbg_TDO_21 : in std_logic;
Dbg_Reg_En_21 : out std_logic_vector(0 to 7);
Dbg_Capture_21 : out std_logic;
Dbg_Shift_21 : out std_logic;
Dbg_Update_21 : out std_logic;
Dbg_Rst_21 : out std_logic;
Dbg_Clk_22 : out std_logic;
Dbg_TDI_22 : out std_logic;
Dbg_TDO_22 : in std_logic;
Dbg_Reg_En_22 : out std_logic_vector(0 to 7);
Dbg_Capture_22 : out std_logic;
Dbg_Shift_22 : out std_logic;
Dbg_Update_22 : out std_logic;
Dbg_Rst_22 : out std_logic;
Dbg_Clk_23 : out std_logic;
Dbg_TDI_23 : out std_logic;
Dbg_TDO_23 : in std_logic;
Dbg_Reg_En_23 : out std_logic_vector(0 to 7);
Dbg_Capture_23 : out std_logic;
Dbg_Shift_23 : out std_logic;
Dbg_Update_23 : out std_logic;
Dbg_Rst_23 : out std_logic;
Dbg_Clk_24 : out std_logic;
Dbg_TDI_24 : out std_logic;
Dbg_TDO_24 : in std_logic;
Dbg_Reg_En_24 : out std_logic_vector(0 to 7);
Dbg_Capture_24 : out std_logic;
Dbg_Shift_24 : out std_logic;
Dbg_Update_24 : out std_logic;
Dbg_Rst_24 : out std_logic;
Dbg_Clk_25 : out std_logic;
Dbg_TDI_25 : out std_logic;
Dbg_TDO_25 : in std_logic;
Dbg_Reg_En_25 : out std_logic_vector(0 to 7);
Dbg_Capture_25 : out std_logic;
Dbg_Shift_25 : out std_logic;
Dbg_Update_25 : out std_logic;
Dbg_Rst_25 : out std_logic;
Dbg_Clk_26 : out std_logic;
Dbg_TDI_26 : out std_logic;
Dbg_TDO_26 : in std_logic;
Dbg_Reg_En_26 : out std_logic_vector(0 to 7);
Dbg_Capture_26 : out std_logic;
Dbg_Shift_26 : out std_logic;
Dbg_Update_26 : out std_logic;
Dbg_Rst_26 : out std_logic;
Dbg_Clk_27 : out std_logic;
Dbg_TDI_27 : out std_logic;
Dbg_TDO_27 : in std_logic;
Dbg_Reg_En_27 : out std_logic_vector(0 to 7);
Dbg_Capture_27 : out std_logic;
Dbg_Shift_27 : out std_logic;
Dbg_Update_27 : out std_logic;
Dbg_Rst_27 : out std_logic;
Dbg_Clk_28 : out std_logic;
Dbg_TDI_28 : out std_logic;
Dbg_TDO_28 : in std_logic;
Dbg_Reg_En_28 : out std_logic_vector(0 to 7);
Dbg_Capture_28 : out std_logic;
Dbg_Shift_28 : out std_logic;
Dbg_Update_28 : out std_logic;
Dbg_Rst_28 : out std_logic;
Dbg_Clk_29 : out std_logic;
Dbg_TDI_29 : out std_logic;
Dbg_TDO_29 : in std_logic;
Dbg_Reg_En_29 : out std_logic_vector(0 to 7);
Dbg_Capture_29 : out std_logic;
Dbg_Shift_29 : out std_logic;
Dbg_Update_29 : out std_logic;
Dbg_Rst_29 : out std_logic;
Dbg_Clk_30 : out std_logic;
Dbg_TDI_30 : out std_logic;
Dbg_TDO_30 : in std_logic;
Dbg_Reg_En_30 : out std_logic_vector(0 to 7);
Dbg_Capture_30 : out std_logic;
Dbg_Shift_30 : out std_logic;
Dbg_Update_30 : out std_logic;
Dbg_Rst_30 : out std_logic;
Dbg_Clk_31 : out std_logic;
Dbg_TDI_31 : out std_logic;
Dbg_TDO_31 : in std_logic;
Dbg_Reg_En_31 : out std_logic_vector(0 to 7);
Dbg_Capture_31 : out std_logic;
Dbg_Shift_31 : out std_logic;
Dbg_Update_31 : out std_logic;
Dbg_Rst_31 : out std_logic;
bscan_tdi : out std_logic;
bscan_reset : out std_logic;
bscan_shift : out std_logic;
bscan_update : out std_logic;
bscan_capture : out std_logic;
bscan_sel1 : out std_logic;
bscan_drck1 : out std_logic;
bscan_tdo1 : in std_logic;
bscan_ext_tdi : in std_logic;
bscan_ext_reset : in std_logic;
bscan_ext_shift : in std_logic;
bscan_ext_update : in std_logic;
bscan_ext_capture : in std_logic;
bscan_ext_sel : in std_logic;
bscan_ext_drck : in std_logic;
bscan_ext_tdo : out std_logic;
Ext_JTAG_DRCK : out std_logic;
Ext_JTAG_RESET : out std_logic;
Ext_JTAG_SEL : out std_logic;
Ext_JTAG_CAPTURE : out std_logic;
Ext_JTAG_SHIFT : out std_logic;
Ext_JTAG_UPDATE : out std_logic;
Ext_JTAG_TDI : out std_logic;
Ext_JTAG_TDO : in std_logic
);
end component;
component system_clock_generator_0_wrapper is
port (
CLKIN : in std_logic;
CLKOUT0 : out std_logic;
CLKOUT1 : out std_logic;
CLKOUT2 : out std_logic;
CLKOUT3 : out std_logic;
CLKOUT4 : out std_logic;
CLKOUT5 : out std_logic;
CLKOUT6 : out std_logic;
CLKOUT7 : out std_logic;
CLKOUT8 : out std_logic;
CLKOUT9 : out std_logic;
CLKOUT10 : out std_logic;
CLKOUT11 : out std_logic;
CLKOUT12 : out std_logic;
CLKOUT13 : out std_logic;
CLKOUT14 : out std_logic;
CLKOUT15 : out std_logic;
CLKFBIN : in std_logic;
CLKFBOUT : out std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
PSDONE : out std_logic;
RST : in std_logic;
LOCKED : out std_logic
);
end component;
component system_axi4lite_0_wrapper is
port (
INTERCONNECT_ACLK : in std_logic;
INTERCONNECT_ARESETN : in std_logic;
S_AXI_ARESET_OUT_N : out std_logic_vector(0 to 0);
M_AXI_ARESET_OUT_N : out std_logic_vector(4 downto 0);
IRQ : out std_logic;
S_AXI_ACLK : in std_logic_vector(0 to 0);
S_AXI_AWID : in std_logic_vector(0 to 0);
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_AWLOCK : in std_logic_vector(1 downto 0);
S_AXI_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_AWUSER : in std_logic_vector(0 to 0);
S_AXI_AWVALID : in std_logic_vector(0 to 0);
S_AXI_AWREADY : out std_logic_vector(0 to 0);
S_AXI_WID : in std_logic_vector(0 to 0);
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WLAST : in std_logic_vector(0 to 0);
S_AXI_WUSER : in std_logic_vector(0 to 0);
S_AXI_WVALID : in std_logic_vector(0 to 0);
S_AXI_WREADY : out std_logic_vector(0 to 0);
S_AXI_BID : out std_logic_vector(0 to 0);
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BUSER : out std_logic_vector(0 to 0);
S_AXI_BVALID : out std_logic_vector(0 to 0);
S_AXI_BREADY : in std_logic_vector(0 to 0);
S_AXI_ARID : in std_logic_vector(0 to 0);
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ARLOCK : in std_logic_vector(1 downto 0);
S_AXI_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_ARUSER : in std_logic_vector(0 to 0);
S_AXI_ARVALID : in std_logic_vector(0 to 0);
S_AXI_ARREADY : out std_logic_vector(0 to 0);
S_AXI_RID : out std_logic_vector(0 to 0);
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RLAST : out std_logic_vector(0 to 0);
S_AXI_RUSER : out std_logic_vector(0 to 0);
S_AXI_RVALID : out std_logic_vector(0 to 0);
S_AXI_RREADY : in std_logic_vector(0 to 0);
M_AXI_ACLK : in std_logic_vector(4 downto 0);
M_AXI_AWID : out std_logic_vector(4 downto 0);
M_AXI_AWADDR : out std_logic_vector(159 downto 0);
M_AXI_AWLEN : out std_logic_vector(39 downto 0);
M_AXI_AWSIZE : out std_logic_vector(14 downto 0);
M_AXI_AWBURST : out std_logic_vector(9 downto 0);
M_AXI_AWLOCK : out std_logic_vector(9 downto 0);
M_AXI_AWCACHE : out std_logic_vector(19 downto 0);
M_AXI_AWPROT : out std_logic_vector(14 downto 0);
M_AXI_AWREGION : out std_logic_vector(19 downto 0);
M_AXI_AWQOS : out std_logic_vector(19 downto 0);
M_AXI_AWUSER : out std_logic_vector(4 downto 0);
M_AXI_AWVALID : out std_logic_vector(4 downto 0);
M_AXI_AWREADY : in std_logic_vector(4 downto 0);
M_AXI_WID : out std_logic_vector(4 downto 0);
M_AXI_WDATA : out std_logic_vector(159 downto 0);
M_AXI_WSTRB : out std_logic_vector(19 downto 0);
M_AXI_WLAST : out std_logic_vector(4 downto 0);
M_AXI_WUSER : out std_logic_vector(4 downto 0);
M_AXI_WVALID : out std_logic_vector(4 downto 0);
M_AXI_WREADY : in std_logic_vector(4 downto 0);
M_AXI_BID : in std_logic_vector(4 downto 0);
M_AXI_BRESP : in std_logic_vector(9 downto 0);
M_AXI_BUSER : in std_logic_vector(4 downto 0);
M_AXI_BVALID : in std_logic_vector(4 downto 0);
M_AXI_BREADY : out std_logic_vector(4 downto 0);
M_AXI_ARID : out std_logic_vector(4 downto 0);
M_AXI_ARADDR : out std_logic_vector(159 downto 0);
M_AXI_ARLEN : out std_logic_vector(39 downto 0);
M_AXI_ARSIZE : out std_logic_vector(14 downto 0);
M_AXI_ARBURST : out std_logic_vector(9 downto 0);
M_AXI_ARLOCK : out std_logic_vector(9 downto 0);
M_AXI_ARCACHE : out std_logic_vector(19 downto 0);
M_AXI_ARPROT : out std_logic_vector(14 downto 0);
M_AXI_ARREGION : out std_logic_vector(19 downto 0);
M_AXI_ARQOS : out std_logic_vector(19 downto 0);
M_AXI_ARUSER : out std_logic_vector(4 downto 0);
M_AXI_ARVALID : out std_logic_vector(4 downto 0);
M_AXI_ARREADY : in std_logic_vector(4 downto 0);
M_AXI_RID : in std_logic_vector(4 downto 0);
M_AXI_RDATA : in std_logic_vector(159 downto 0);
M_AXI_RRESP : in std_logic_vector(9 downto 0);
M_AXI_RLAST : in std_logic_vector(4 downto 0);
M_AXI_RUSER : in std_logic_vector(4 downto 0);
M_AXI_RVALID : in std_logic_vector(4 downto 0);
M_AXI_RREADY : out std_logic_vector(4 downto 0);
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic;
INTERCONNECT_ARESET_OUT_N : out std_logic;
DEBUG_AW_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AW_ARB_GRANT : out std_logic_vector(7 downto 0);
DEBUG_AR_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AR_ARB_GRANT : out std_logic_vector(7 downto 0);
DEBUG_AW_TRANS_QUAL : out std_logic_vector(0 to 0);
DEBUG_AW_ACCEPT_CNT : out std_logic_vector(7 downto 0);
DEBUG_AW_ACTIVE_THREAD : out std_logic_vector(15 downto 0);
DEBUG_AW_ACTIVE_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AW_ACTIVE_REGION : out std_logic_vector(7 downto 0);
DEBUG_AW_ERROR : out std_logic_vector(7 downto 0);
DEBUG_AW_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AR_TRANS_QUAL : out std_logic_vector(0 to 0);
DEBUG_AR_ACCEPT_CNT : out std_logic_vector(7 downto 0);
DEBUG_AR_ACTIVE_THREAD : out std_logic_vector(15 downto 0);
DEBUG_AR_ACTIVE_TARGET : out std_logic_vector(7 downto 0);
DEBUG_AR_ACTIVE_REGION : out std_logic_vector(7 downto 0);
DEBUG_AR_ERROR : out std_logic_vector(7 downto 0);
DEBUG_AR_TARGET : out std_logic_vector(7 downto 0);
DEBUG_B_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_R_BEAT_CNT : out std_logic_vector(7 downto 0);
DEBUG_R_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_AW_ISSUING_CNT : out std_logic_vector(7 downto 0);
DEBUG_AR_ISSUING_CNT : out std_logic_vector(7 downto 0);
DEBUG_W_BEAT_CNT : out std_logic_vector(7 downto 0);
DEBUG_W_TRANS_SEQ : out std_logic_vector(7 downto 0);
DEBUG_BID_TARGET : out std_logic_vector(7 downto 0);
DEBUG_BID_ERROR : out std_logic;
DEBUG_RID_TARGET : out std_logic_vector(7 downto 0);
DEBUG_RID_ERROR : out std_logic;
DEBUG_SR_SC_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_SR_SC_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_SR_SC_BRESP : out std_logic_vector(4 downto 0);
DEBUG_SR_SC_RDATA : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_SR_SC_WDATA : out std_logic_vector(31 downto 0);
DEBUG_SR_SC_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_SC_SF_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_SC_SF_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_SC_SF_BRESP : out std_logic_vector(4 downto 0);
DEBUG_SC_SF_RDATA : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_SC_SF_WDATA : out std_logic_vector(31 downto 0);
DEBUG_SC_SF_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_SF_CB_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_SF_CB_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_SF_CB_BRESP : out std_logic_vector(4 downto 0);
DEBUG_SF_CB_RDATA : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_SF_CB_WDATA : out std_logic_vector(31 downto 0);
DEBUG_SF_CB_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_CB_MF_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_CB_MF_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_CB_MF_BRESP : out std_logic_vector(4 downto 0);
DEBUG_CB_MF_RDATA : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_CB_MF_WDATA : out std_logic_vector(31 downto 0);
DEBUG_CB_MF_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_MF_MC_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_MF_MC_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_MF_MC_BRESP : out std_logic_vector(4 downto 0);
DEBUG_MF_MC_RDATA : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_MF_MC_WDATA : out std_logic_vector(31 downto 0);
DEBUG_MF_MC_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_MC_MP_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_MC_MP_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_MC_MP_BRESP : out std_logic_vector(4 downto 0);
DEBUG_MC_MP_RDATA : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_MC_MP_WDATA : out std_logic_vector(31 downto 0);
DEBUG_MC_MP_WDATACONTROL : out std_logic_vector(6 downto 0);
DEBUG_MP_MR_ARADDR : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_ARADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_MP_MR_AWADDR : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_AWADDRCONTROL : out std_logic_vector(23 downto 0);
DEBUG_MP_MR_BRESP : out std_logic_vector(4 downto 0);
DEBUG_MP_MR_RDATA : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_RDATACONTROL : out std_logic_vector(5 downto 0);
DEBUG_MP_MR_WDATA : out std_logic_vector(31 downto 0);
DEBUG_MP_MR_WDATACONTROL : out std_logic_vector(6 downto 0)
);
end component;
component system_rs232_uart_1_wrapper is
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
Interrupt : out std_logic;
S_AXI_AWADDR : in std_logic_vector(3 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(3 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
RX : in std_logic;
TX : out std_logic
);
end component;
component system_push_buttons_4bits_wrapper is
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(8 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(8 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
IP2INTC_Irpt : out std_logic;
GPIO_IO_I : in std_logic_vector(3 downto 0);
GPIO_IO_O : out std_logic_vector(3 downto 0);
GPIO_IO_T : out std_logic_vector(3 downto 0);
GPIO2_IO_I : in std_logic_vector(31 downto 0);
GPIO2_IO_O : out std_logic_vector(31 downto 0);
GPIO2_IO_T : out std_logic_vector(31 downto 0)
);
end component;
component system_leds_8bits_wrapper is
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(8 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(8 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
IP2INTC_Irpt : out std_logic;
GPIO_IO_I : in std_logic_vector(7 downto 0);
GPIO_IO_O : out std_logic_vector(7 downto 0);
GPIO_IO_T : out std_logic_vector(7 downto 0);
GPIO2_IO_I : in std_logic_vector(31 downto 0);
GPIO2_IO_O : out std_logic_vector(31 downto 0);
GPIO2_IO_T : out std_logic_vector(31 downto 0)
);
end component;
component system_dip_switches_8bits_wrapper is
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(8 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(8 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
IP2INTC_Irpt : out std_logic;
GPIO_IO_I : in std_logic_vector(7 downto 0);
GPIO_IO_O : out std_logic_vector(7 downto 0);
GPIO_IO_T : out std_logic_vector(7 downto 0);
GPIO2_IO_I : in std_logic_vector(31 downto 0);
GPIO2_IO_O : out std_logic_vector(31 downto 0);
GPIO2_IO_T : out std_logic_vector(31 downto 0)
);
end component;
component system_fsl_v20_0_wrapper is
port (
FSL_Clk : in std_logic;
SYS_Rst : in std_logic;
FSL_Rst : out std_logic;
FSL_M_Clk : in std_logic;
FSL_M_Data : in std_logic_vector(0 to 31);
FSL_M_Control : in std_logic;
FSL_M_Write : in std_logic;
FSL_M_Full : out std_logic;
FSL_S_Clk : in std_logic;
FSL_S_Data : out std_logic_vector(0 to 31);
FSL_S_Control : out std_logic;
FSL_S_Read : in std_logic;
FSL_S_Exists : out std_logic;
FSL_Full : out std_logic;
FSL_Has_Data : out std_logic;
FSL_Control_IRQ : out std_logic
);
end component;
component system_fsl_v20_1_wrapper is
port (
FSL_Clk : in std_logic;
SYS_Rst : in std_logic;
FSL_Rst : out std_logic;
FSL_M_Clk : in std_logic;
FSL_M_Data : in std_logic_vector(0 to 31);
FSL_M_Control : in std_logic;
FSL_M_Write : in std_logic;
FSL_M_Full : out std_logic;
FSL_S_Clk : in std_logic;
FSL_S_Data : out std_logic_vector(0 to 31);
FSL_S_Control : out std_logic;
FSL_S_Read : in std_logic;
FSL_S_Exists : out std_logic;
FSL_Full : out std_logic;
FSL_Has_Data : out std_logic;
FSL_Control_IRQ : out std_logic
);
end component;
component system_bajsd_0_wrapper is
port (
FSL_Clk : in std_logic;
FSL_Rst : in std_logic;
FSL_S_Clk : in std_logic;
FSL_S_Read : out std_logic;
FSL_S_Data : in std_logic_vector(0 to 31);
FSL_S_Control : in std_logic;
FSL_S_Exists : in std_logic;
FSL_M_Clk : in std_logic;
FSL_M_Write : out std_logic;
FSL_M_Data : out std_logic_vector(0 to 31);
FSL_M_Control : out std_logic;
FSL_M_Full : in std_logic
);
end component;
-- Internal signals
signal Ext_BRK : std_logic;
signal Ext_NM_BRK : std_logic;
signal axi4lite_0_M_ARADDR : std_logic_vector(159 downto 0);
signal axi4lite_0_M_ARESETN : std_logic_vector(4 downto 0);
signal axi4lite_0_M_ARREADY : std_logic_vector(4 downto 0);
signal axi4lite_0_M_ARVALID : std_logic_vector(4 downto 0);
signal axi4lite_0_M_AWADDR : std_logic_vector(159 downto 0);
signal axi4lite_0_M_AWREADY : std_logic_vector(4 downto 0);
signal axi4lite_0_M_AWVALID : std_logic_vector(4 downto 0);
signal axi4lite_0_M_BREADY : std_logic_vector(4 downto 0);
signal axi4lite_0_M_BRESP : std_logic_vector(9 downto 0);
signal axi4lite_0_M_BVALID : std_logic_vector(4 downto 0);
signal axi4lite_0_M_RDATA : std_logic_vector(159 downto 0);
signal axi4lite_0_M_RREADY : std_logic_vector(4 downto 0);
signal axi4lite_0_M_RRESP : std_logic_vector(9 downto 0);
signal axi4lite_0_M_RVALID : std_logic_vector(4 downto 0);
signal axi4lite_0_M_WDATA : std_logic_vector(159 downto 0);
signal axi4lite_0_M_WREADY : std_logic_vector(4 downto 0);
signal axi4lite_0_M_WSTRB : std_logic_vector(19 downto 0);
signal axi4lite_0_M_WVALID : std_logic_vector(4 downto 0);
signal axi4lite_0_S_ARADDR : std_logic_vector(31 downto 0);
signal axi4lite_0_S_ARBURST : std_logic_vector(1 downto 0);
signal axi4lite_0_S_ARCACHE : std_logic_vector(3 downto 0);
signal axi4lite_0_S_ARID : std_logic_vector(0 to 0);
signal axi4lite_0_S_ARLEN : std_logic_vector(7 downto 0);
signal axi4lite_0_S_ARLOCK : std_logic_vector(1 downto 0);
signal axi4lite_0_S_ARPROT : std_logic_vector(2 downto 0);
signal axi4lite_0_S_ARQOS : std_logic_vector(3 downto 0);
signal axi4lite_0_S_ARREADY : std_logic_vector(0 to 0);
signal axi4lite_0_S_ARSIZE : std_logic_vector(2 downto 0);
signal axi4lite_0_S_ARVALID : std_logic_vector(0 to 0);
signal axi4lite_0_S_AWADDR : std_logic_vector(31 downto 0);
signal axi4lite_0_S_AWBURST : std_logic_vector(1 downto 0);
signal axi4lite_0_S_AWCACHE : std_logic_vector(3 downto 0);
signal axi4lite_0_S_AWID : std_logic_vector(0 to 0);
signal axi4lite_0_S_AWLEN : std_logic_vector(7 downto 0);
signal axi4lite_0_S_AWLOCK : std_logic_vector(1 downto 0);
signal axi4lite_0_S_AWPROT : std_logic_vector(2 downto 0);
signal axi4lite_0_S_AWQOS : std_logic_vector(3 downto 0);
signal axi4lite_0_S_AWREADY : std_logic_vector(0 to 0);
signal axi4lite_0_S_AWSIZE : std_logic_vector(2 downto 0);
signal axi4lite_0_S_AWVALID : std_logic_vector(0 to 0);
signal axi4lite_0_S_BID : std_logic_vector(0 downto 0);
signal axi4lite_0_S_BREADY : std_logic_vector(0 to 0);
signal axi4lite_0_S_BRESP : std_logic_vector(1 downto 0);
signal axi4lite_0_S_BVALID : std_logic_vector(0 to 0);
signal axi4lite_0_S_RDATA : std_logic_vector(31 downto 0);
signal axi4lite_0_S_RID : std_logic_vector(0 downto 0);
signal axi4lite_0_S_RLAST : std_logic_vector(0 to 0);
signal axi4lite_0_S_RREADY : std_logic_vector(0 to 0);
signal axi4lite_0_S_RRESP : std_logic_vector(1 downto 0);
signal axi4lite_0_S_RVALID : std_logic_vector(0 to 0);
signal axi4lite_0_S_WDATA : std_logic_vector(31 downto 0);
signal axi4lite_0_S_WLAST : std_logic_vector(0 to 0);
signal axi4lite_0_S_WREADY : std_logic_vector(0 to 0);
signal axi4lite_0_S_WSTRB : std_logic_vector(3 downto 0);
signal axi4lite_0_S_WVALID : std_logic_vector(0 to 0);
signal clk_100_0000MHz : std_logic_vector(0 to 0);
signal fsl_v20_0_FSL_M_Control : std_logic;
signal fsl_v20_0_FSL_M_Data : std_logic_vector(0 to 31);
signal fsl_v20_0_FSL_M_Full : std_logic;
signal fsl_v20_0_FSL_M_Write : std_logic;
signal fsl_v20_0_FSL_S_Control : std_logic;
signal fsl_v20_0_FSL_S_Data : std_logic_vector(0 to 31);
signal fsl_v20_0_FSL_S_Exists : std_logic;
signal fsl_v20_0_FSL_S_Read : std_logic;
signal fsl_v20_1_FSL_M_Control : std_logic;
signal fsl_v20_1_FSL_M_Data : std_logic_vector(0 to 31);
signal fsl_v20_1_FSL_M_Full : std_logic;
signal fsl_v20_1_FSL_M_Write : std_logic;
signal fsl_v20_1_FSL_S_Control : std_logic;
signal fsl_v20_1_FSL_S_Data : std_logic_vector(0 to 31);
signal fsl_v20_1_FSL_S_Exists : std_logic;
signal fsl_v20_1_FSL_S_Read : std_logic;
signal fsl_v20_1_LMB_Rst : std_logic;
signal microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr : std_logic_vector(0 to 31);
signal microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk : std_logic;
signal microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din : std_logic_vector(0 to 31);
signal microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout : std_logic_vector(0 to 31);
signal microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN : std_logic;
signal microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst : std_logic;
signal microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN : std_logic_vector(0 to 3);
signal microblaze_0_debug_Dbg_Capture : std_logic;
signal microblaze_0_debug_Dbg_Clk : std_logic;
signal microblaze_0_debug_Dbg_Reg_En : std_logic_vector(0 to 7);
signal microblaze_0_debug_Dbg_Shift : std_logic;
signal microblaze_0_debug_Dbg_TDI : std_logic;
signal microblaze_0_debug_Dbg_TDO : std_logic;
signal microblaze_0_debug_Dbg_Update : std_logic;
signal microblaze_0_debug_Debug_Rst : std_logic;
signal microblaze_0_dlmb_LMB_ABus : std_logic_vector(0 to 31);
signal microblaze_0_dlmb_LMB_AddrStrobe : std_logic;
signal microblaze_0_dlmb_LMB_BE : std_logic_vector(0 to 3);
signal microblaze_0_dlmb_LMB_CE : std_logic;
signal microblaze_0_dlmb_LMB_ReadDBus : std_logic_vector(0 to 31);
signal microblaze_0_dlmb_LMB_ReadStrobe : std_logic;
signal microblaze_0_dlmb_LMB_Ready : std_logic;
signal microblaze_0_dlmb_LMB_Rst : std_logic;
signal microblaze_0_dlmb_LMB_UE : std_logic;
signal microblaze_0_dlmb_LMB_Wait : std_logic;
signal microblaze_0_dlmb_LMB_WriteDBus : std_logic_vector(0 to 31);
signal microblaze_0_dlmb_LMB_WriteStrobe : std_logic;
signal microblaze_0_dlmb_M_ABus : std_logic_vector(0 to 31);
signal microblaze_0_dlmb_M_AddrStrobe : std_logic;
signal microblaze_0_dlmb_M_BE : std_logic_vector(0 to 3);
signal microblaze_0_dlmb_M_DBus : std_logic_vector(0 to 31);
signal microblaze_0_dlmb_M_ReadStrobe : std_logic;
signal microblaze_0_dlmb_M_WriteStrobe : std_logic;
signal microblaze_0_dlmb_Sl_CE : std_logic_vector(0 to 0);
signal microblaze_0_dlmb_Sl_DBus : std_logic_vector(0 to 31);
signal microblaze_0_dlmb_Sl_Ready : std_logic_vector(0 to 0);
signal microblaze_0_dlmb_Sl_UE : std_logic_vector(0 to 0);
signal microblaze_0_dlmb_Sl_Wait : std_logic_vector(0 to 0);
signal microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr : std_logic_vector(0 to 31);
signal microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk : std_logic;
signal microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din : std_logic_vector(0 to 31);
signal microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout : std_logic_vector(0 to 31);
signal microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN : std_logic;
signal microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst : std_logic;
signal microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN : std_logic_vector(0 to 3);
signal microblaze_0_ilmb_LMB_ABus : std_logic_vector(0 to 31);
signal microblaze_0_ilmb_LMB_AddrStrobe : std_logic;
signal microblaze_0_ilmb_LMB_BE : std_logic_vector(0 to 3);
signal microblaze_0_ilmb_LMB_CE : std_logic;
signal microblaze_0_ilmb_LMB_ReadDBus : std_logic_vector(0 to 31);
signal microblaze_0_ilmb_LMB_ReadStrobe : std_logic;
signal microblaze_0_ilmb_LMB_Ready : std_logic;
signal microblaze_0_ilmb_LMB_Rst : std_logic;
signal microblaze_0_ilmb_LMB_UE : std_logic;
signal microblaze_0_ilmb_LMB_Wait : std_logic;
signal microblaze_0_ilmb_LMB_WriteDBus : std_logic_vector(0 to 31);
signal microblaze_0_ilmb_LMB_WriteStrobe : std_logic;
signal microblaze_0_ilmb_M_ABus : std_logic_vector(0 to 31);
signal microblaze_0_ilmb_M_AddrStrobe : std_logic;
signal microblaze_0_ilmb_M_ReadStrobe : std_logic;
signal microblaze_0_ilmb_Sl_CE : std_logic_vector(0 to 0);
signal microblaze_0_ilmb_Sl_DBus : std_logic_vector(0 to 31);
signal microblaze_0_ilmb_Sl_Ready : std_logic_vector(0 to 0);
signal microblaze_0_ilmb_Sl_UE : std_logic_vector(0 to 0);
signal microblaze_0_ilmb_Sl_Wait : std_logic_vector(0 to 0);
signal net_gnd0 : std_logic;
signal net_gnd1 : std_logic_vector(0 to 0);
signal net_gnd2 : std_logic_vector(0 to 1);
signal net_gnd3 : std_logic_vector(0 to 2);
signal net_gnd4 : std_logic_vector(0 to 3);
signal net_gnd5 : std_logic_vector(4 downto 0);
signal net_gnd8 : std_logic_vector(7 downto 0);
signal net_gnd16 : std_logic_vector(0 to 15);
signal net_gnd32 : std_logic_vector(0 to 31);
signal net_gnd4096 : std_logic_vector(0 to 4095);
signal net_vcc0 : std_logic;
signal pgassign1 : std_logic_vector(4 downto 0);
signal proc_sys_reset_0_BUS_STRUCT_RESET : std_logic_vector(0 to 0);
signal proc_sys_reset_0_Dcm_locked : std_logic;
signal proc_sys_reset_0_Interconnect_aresetn : std_logic_vector(0 to 0);
signal proc_sys_reset_0_MB_Debug_Sys_Rst : std_logic;
signal proc_sys_reset_0_MB_Reset : std_logic;
attribute BOX_TYPE : STRING;
attribute BOX_TYPE of system_proc_sys_reset_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_microblaze_0_ilmb_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_microblaze_0_i_bram_ctrl_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_microblaze_0_dlmb_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_microblaze_0_d_bram_ctrl_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_microblaze_0_bram_block_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_microblaze_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_debug_module_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_clock_generator_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_axi4lite_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_rs232_uart_1_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_push_buttons_4bits_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_leds_8bits_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_dip_switches_8bits_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_fsl_v20_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_fsl_v20_1_wrapper : component is "user_black_box";
attribute BOX_TYPE of system_bajsd_0_wrapper : component is "user_black_box";
begin
-- Internal assignments
pgassign1(4 downto 4) <= clk_100_0000MHz(0 to 0);
pgassign1(3 downto 3) <= clk_100_0000MHz(0 to 0);
pgassign1(2 downto 2) <= clk_100_0000MHz(0 to 0);
pgassign1(1 downto 1) <= clk_100_0000MHz(0 to 0);
pgassign1(0 downto 0) <= clk_100_0000MHz(0 to 0);
net_gnd0 <= '0';
net_gnd1(0 to 0) <= B"0";
net_gnd16(0 to 15) <= B"0000000000000000";
net_gnd2(0 to 1) <= B"00";
net_gnd3(0 to 2) <= B"000";
net_gnd32(0 to 31) <= B"00000000000000000000000000000000";
net_gnd4(0 to 3) <= B"0000";
net_gnd4096(0 to 4095) <= X"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
net_gnd5(4 downto 0) <= B"00000";
net_gnd8(7 downto 0) <= B"00000000";
net_vcc0 <= '1';
proc_sys_reset_0 : system_proc_sys_reset_0_wrapper
port map (
Slowest_sync_clk => pgassign1(4),
Ext_Reset_In => RESET,
Aux_Reset_In => net_gnd0,
MB_Debug_Sys_Rst => proc_sys_reset_0_MB_Debug_Sys_Rst,
Core_Reset_Req_0 => net_gnd0,
Chip_Reset_Req_0 => net_gnd0,
System_Reset_Req_0 => net_gnd0,
Core_Reset_Req_1 => net_gnd0,
Chip_Reset_Req_1 => net_gnd0,
System_Reset_Req_1 => net_gnd0,
Dcm_locked => proc_sys_reset_0_Dcm_locked,
RstcPPCresetcore_0 => open,
RstcPPCresetchip_0 => open,
RstcPPCresetsys_0 => open,
RstcPPCresetcore_1 => open,
RstcPPCresetchip_1 => open,
RstcPPCresetsys_1 => open,
MB_Reset => proc_sys_reset_0_MB_Reset,
Bus_Struct_Reset => proc_sys_reset_0_BUS_STRUCT_RESET(0 to 0),
Peripheral_Reset => open,
Interconnect_aresetn => proc_sys_reset_0_Interconnect_aresetn(0 to 0),
Peripheral_aresetn => open
);
microblaze_0_ilmb : system_microblaze_0_ilmb_wrapper
port map (
LMB_Clk => pgassign1(4),
SYS_Rst => proc_sys_reset_0_BUS_STRUCT_RESET(0),
LMB_Rst => microblaze_0_ilmb_LMB_Rst,
M_ABus => microblaze_0_ilmb_M_ABus,
M_ReadStrobe => microblaze_0_ilmb_M_ReadStrobe,
M_WriteStrobe => net_gnd0,
M_AddrStrobe => microblaze_0_ilmb_M_AddrStrobe,
M_DBus => net_gnd32,
M_BE => net_gnd4,
Sl_DBus => microblaze_0_ilmb_Sl_DBus,
Sl_Ready => microblaze_0_ilmb_Sl_Ready(0 to 0),
Sl_Wait => microblaze_0_ilmb_Sl_Wait(0 to 0),
Sl_UE => microblaze_0_ilmb_Sl_UE(0 to 0),
Sl_CE => microblaze_0_ilmb_Sl_CE(0 to 0),
LMB_ABus => microblaze_0_ilmb_LMB_ABus,
LMB_ReadStrobe => microblaze_0_ilmb_LMB_ReadStrobe,
LMB_WriteStrobe => microblaze_0_ilmb_LMB_WriteStrobe,
LMB_AddrStrobe => microblaze_0_ilmb_LMB_AddrStrobe,
LMB_ReadDBus => microblaze_0_ilmb_LMB_ReadDBus,
LMB_WriteDBus => microblaze_0_ilmb_LMB_WriteDBus,
LMB_Ready => microblaze_0_ilmb_LMB_Ready,
LMB_Wait => microblaze_0_ilmb_LMB_Wait,
LMB_UE => microblaze_0_ilmb_LMB_UE,
LMB_CE => microblaze_0_ilmb_LMB_CE,
LMB_BE => microblaze_0_ilmb_LMB_BE
);
microblaze_0_i_bram_ctrl : system_microblaze_0_i_bram_ctrl_wrapper
port map (
LMB_Clk => pgassign1(4),
LMB_Rst => microblaze_0_ilmb_LMB_Rst,
LMB_ABus => microblaze_0_ilmb_LMB_ABus,
LMB_WriteDBus => microblaze_0_ilmb_LMB_WriteDBus,
LMB_AddrStrobe => microblaze_0_ilmb_LMB_AddrStrobe,
LMB_ReadStrobe => microblaze_0_ilmb_LMB_ReadStrobe,
LMB_WriteStrobe => microblaze_0_ilmb_LMB_WriteStrobe,
LMB_BE => microblaze_0_ilmb_LMB_BE,
Sl_DBus => microblaze_0_ilmb_Sl_DBus,
Sl_Ready => microblaze_0_ilmb_Sl_Ready(0),
Sl_Wait => microblaze_0_ilmb_Sl_Wait(0),
Sl_UE => microblaze_0_ilmb_Sl_UE(0),
Sl_CE => microblaze_0_ilmb_Sl_CE(0),
LMB1_ABus => net_gnd32,
LMB1_WriteDBus => net_gnd32,
LMB1_AddrStrobe => net_gnd0,
LMB1_ReadStrobe => net_gnd0,
LMB1_WriteStrobe => net_gnd0,
LMB1_BE => net_gnd4,
Sl1_DBus => open,
Sl1_Ready => open,
Sl1_Wait => open,
Sl1_UE => open,
Sl1_CE => open,
LMB2_ABus => net_gnd32,
LMB2_WriteDBus => net_gnd32,
LMB2_AddrStrobe => net_gnd0,
LMB2_ReadStrobe => net_gnd0,
LMB2_WriteStrobe => net_gnd0,
LMB2_BE => net_gnd4,
Sl2_DBus => open,
Sl2_Ready => open,
Sl2_Wait => open,
Sl2_UE => open,
Sl2_CE => open,
LMB3_ABus => net_gnd32,
LMB3_WriteDBus => net_gnd32,
LMB3_AddrStrobe => net_gnd0,
LMB3_ReadStrobe => net_gnd0,
LMB3_WriteStrobe => net_gnd0,
LMB3_BE => net_gnd4,
Sl3_DBus => open,
Sl3_Ready => open,
Sl3_Wait => open,
Sl3_UE => open,
Sl3_CE => open,
BRAM_Rst_A => microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst,
BRAM_Clk_A => microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk,
BRAM_EN_A => microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN,
BRAM_WEN_A => microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN,
BRAM_Addr_A => microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr,
BRAM_Din_A => microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din,
BRAM_Dout_A => microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout,
Interrupt => open,
UE => open,
CE => open,
SPLB_CTRL_PLB_ABus => net_gnd32,
SPLB_CTRL_PLB_PAValid => net_gnd0,
SPLB_CTRL_PLB_masterID => net_gnd1(0 to 0),
SPLB_CTRL_PLB_RNW => net_gnd0,
SPLB_CTRL_PLB_BE => net_gnd4,
SPLB_CTRL_PLB_size => net_gnd4,
SPLB_CTRL_PLB_type => net_gnd3,
SPLB_CTRL_PLB_wrDBus => net_gnd32,
SPLB_CTRL_Sl_addrAck => open,
SPLB_CTRL_Sl_SSize => open,
SPLB_CTRL_Sl_wait => open,
SPLB_CTRL_Sl_rearbitrate => open,
SPLB_CTRL_Sl_wrDAck => open,
SPLB_CTRL_Sl_wrComp => open,
SPLB_CTRL_Sl_rdDBus => open,
SPLB_CTRL_Sl_rdDAck => open,
SPLB_CTRL_Sl_rdComp => open,
SPLB_CTRL_Sl_MBusy => open,
SPLB_CTRL_Sl_MWrErr => open,
SPLB_CTRL_Sl_MRdErr => open,
SPLB_CTRL_PLB_UABus => net_gnd32,
SPLB_CTRL_PLB_SAValid => net_gnd0,
SPLB_CTRL_PLB_rdPrim => net_gnd0,
SPLB_CTRL_PLB_wrPrim => net_gnd0,
SPLB_CTRL_PLB_abort => net_gnd0,
SPLB_CTRL_PLB_busLock => net_gnd0,
SPLB_CTRL_PLB_MSize => net_gnd2,
SPLB_CTRL_PLB_lockErr => net_gnd0,
SPLB_CTRL_PLB_wrBurst => net_gnd0,
SPLB_CTRL_PLB_rdBurst => net_gnd0,
SPLB_CTRL_PLB_wrPendReq => net_gnd0,
SPLB_CTRL_PLB_rdPendReq => net_gnd0,
SPLB_CTRL_PLB_wrPendPri => net_gnd2,
SPLB_CTRL_PLB_rdPendPri => net_gnd2,
SPLB_CTRL_PLB_reqPri => net_gnd2,
SPLB_CTRL_PLB_TAttribute => net_gnd16,
SPLB_CTRL_Sl_wrBTerm => open,
SPLB_CTRL_Sl_rdWdAddr => open,
SPLB_CTRL_Sl_rdBTerm => open,
SPLB_CTRL_Sl_MIRQ => open,
S_AXI_CTRL_ACLK => net_vcc0,
S_AXI_CTRL_ARESETN => net_gnd0,
S_AXI_CTRL_AWADDR => net_gnd32(0 to 31),
S_AXI_CTRL_AWVALID => net_gnd0,
S_AXI_CTRL_AWREADY => open,
S_AXI_CTRL_WDATA => net_gnd32(0 to 31),
S_AXI_CTRL_WSTRB => net_gnd4(0 to 3),
S_AXI_CTRL_WVALID => net_gnd0,
S_AXI_CTRL_WREADY => open,
S_AXI_CTRL_BRESP => open,
S_AXI_CTRL_BVALID => open,
S_AXI_CTRL_BREADY => net_gnd0,
S_AXI_CTRL_ARADDR => net_gnd32(0 to 31),
S_AXI_CTRL_ARVALID => net_gnd0,
S_AXI_CTRL_ARREADY => open,
S_AXI_CTRL_RDATA => open,
S_AXI_CTRL_RRESP => open,
S_AXI_CTRL_RVALID => open,
S_AXI_CTRL_RREADY => net_gnd0
);
microblaze_0_dlmb : system_microblaze_0_dlmb_wrapper
port map (
LMB_Clk => pgassign1(4),
SYS_Rst => proc_sys_reset_0_BUS_STRUCT_RESET(0),
LMB_Rst => microblaze_0_dlmb_LMB_Rst,
M_ABus => microblaze_0_dlmb_M_ABus,
M_ReadStrobe => microblaze_0_dlmb_M_ReadStrobe,
M_WriteStrobe => microblaze_0_dlmb_M_WriteStrobe,
M_AddrStrobe => microblaze_0_dlmb_M_AddrStrobe,
M_DBus => microblaze_0_dlmb_M_DBus,
M_BE => microblaze_0_dlmb_M_BE,
Sl_DBus => microblaze_0_dlmb_Sl_DBus,
Sl_Ready => microblaze_0_dlmb_Sl_Ready(0 to 0),
Sl_Wait => microblaze_0_dlmb_Sl_Wait(0 to 0),
Sl_UE => microblaze_0_dlmb_Sl_UE(0 to 0),
Sl_CE => microblaze_0_dlmb_Sl_CE(0 to 0),
LMB_ABus => microblaze_0_dlmb_LMB_ABus,
LMB_ReadStrobe => microblaze_0_dlmb_LMB_ReadStrobe,
LMB_WriteStrobe => microblaze_0_dlmb_LMB_WriteStrobe,
LMB_AddrStrobe => microblaze_0_dlmb_LMB_AddrStrobe,
LMB_ReadDBus => microblaze_0_dlmb_LMB_ReadDBus,
LMB_WriteDBus => microblaze_0_dlmb_LMB_WriteDBus,
LMB_Ready => microblaze_0_dlmb_LMB_Ready,
LMB_Wait => microblaze_0_dlmb_LMB_Wait,
LMB_UE => microblaze_0_dlmb_LMB_UE,
LMB_CE => microblaze_0_dlmb_LMB_CE,
LMB_BE => microblaze_0_dlmb_LMB_BE
);
microblaze_0_d_bram_ctrl : system_microblaze_0_d_bram_ctrl_wrapper
port map (
LMB_Clk => pgassign1(4),
LMB_Rst => microblaze_0_dlmb_LMB_Rst,
LMB_ABus => microblaze_0_dlmb_LMB_ABus,
LMB_WriteDBus => microblaze_0_dlmb_LMB_WriteDBus,
LMB_AddrStrobe => microblaze_0_dlmb_LMB_AddrStrobe,
LMB_ReadStrobe => microblaze_0_dlmb_LMB_ReadStrobe,
LMB_WriteStrobe => microblaze_0_dlmb_LMB_WriteStrobe,
LMB_BE => microblaze_0_dlmb_LMB_BE,
Sl_DBus => microblaze_0_dlmb_Sl_DBus,
Sl_Ready => microblaze_0_dlmb_Sl_Ready(0),
Sl_Wait => microblaze_0_dlmb_Sl_Wait(0),
Sl_UE => microblaze_0_dlmb_Sl_UE(0),
Sl_CE => microblaze_0_dlmb_Sl_CE(0),
LMB1_ABus => net_gnd32,
LMB1_WriteDBus => net_gnd32,
LMB1_AddrStrobe => net_gnd0,
LMB1_ReadStrobe => net_gnd0,
LMB1_WriteStrobe => net_gnd0,
LMB1_BE => net_gnd4,
Sl1_DBus => open,
Sl1_Ready => open,
Sl1_Wait => open,
Sl1_UE => open,
Sl1_CE => open,
LMB2_ABus => net_gnd32,
LMB2_WriteDBus => net_gnd32,
LMB2_AddrStrobe => net_gnd0,
LMB2_ReadStrobe => net_gnd0,
LMB2_WriteStrobe => net_gnd0,
LMB2_BE => net_gnd4,
Sl2_DBus => open,
Sl2_Ready => open,
Sl2_Wait => open,
Sl2_UE => open,
Sl2_CE => open,
LMB3_ABus => net_gnd32,
LMB3_WriteDBus => net_gnd32,
LMB3_AddrStrobe => net_gnd0,
LMB3_ReadStrobe => net_gnd0,
LMB3_WriteStrobe => net_gnd0,
LMB3_BE => net_gnd4,
Sl3_DBus => open,
Sl3_Ready => open,
Sl3_Wait => open,
Sl3_UE => open,
Sl3_CE => open,
BRAM_Rst_A => microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst,
BRAM_Clk_A => microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk,
BRAM_EN_A => microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN,
BRAM_WEN_A => microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN,
BRAM_Addr_A => microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr,
BRAM_Din_A => microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din,
BRAM_Dout_A => microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout,
Interrupt => open,
UE => open,
CE => open,
SPLB_CTRL_PLB_ABus => net_gnd32,
SPLB_CTRL_PLB_PAValid => net_gnd0,
SPLB_CTRL_PLB_masterID => net_gnd1(0 to 0),
SPLB_CTRL_PLB_RNW => net_gnd0,
SPLB_CTRL_PLB_BE => net_gnd4,
SPLB_CTRL_PLB_size => net_gnd4,
SPLB_CTRL_PLB_type => net_gnd3,
SPLB_CTRL_PLB_wrDBus => net_gnd32,
SPLB_CTRL_Sl_addrAck => open,
SPLB_CTRL_Sl_SSize => open,
SPLB_CTRL_Sl_wait => open,
SPLB_CTRL_Sl_rearbitrate => open,
SPLB_CTRL_Sl_wrDAck => open,
SPLB_CTRL_Sl_wrComp => open,
SPLB_CTRL_Sl_rdDBus => open,
SPLB_CTRL_Sl_rdDAck => open,
SPLB_CTRL_Sl_rdComp => open,
SPLB_CTRL_Sl_MBusy => open,
SPLB_CTRL_Sl_MWrErr => open,
SPLB_CTRL_Sl_MRdErr => open,
SPLB_CTRL_PLB_UABus => net_gnd32,
SPLB_CTRL_PLB_SAValid => net_gnd0,
SPLB_CTRL_PLB_rdPrim => net_gnd0,
SPLB_CTRL_PLB_wrPrim => net_gnd0,
SPLB_CTRL_PLB_abort => net_gnd0,
SPLB_CTRL_PLB_busLock => net_gnd0,
SPLB_CTRL_PLB_MSize => net_gnd2,
SPLB_CTRL_PLB_lockErr => net_gnd0,
SPLB_CTRL_PLB_wrBurst => net_gnd0,
SPLB_CTRL_PLB_rdBurst => net_gnd0,
SPLB_CTRL_PLB_wrPendReq => net_gnd0,
SPLB_CTRL_PLB_rdPendReq => net_gnd0,
SPLB_CTRL_PLB_wrPendPri => net_gnd2,
SPLB_CTRL_PLB_rdPendPri => net_gnd2,
SPLB_CTRL_PLB_reqPri => net_gnd2,
SPLB_CTRL_PLB_TAttribute => net_gnd16,
SPLB_CTRL_Sl_wrBTerm => open,
SPLB_CTRL_Sl_rdWdAddr => open,
SPLB_CTRL_Sl_rdBTerm => open,
SPLB_CTRL_Sl_MIRQ => open,
S_AXI_CTRL_ACLK => net_vcc0,
S_AXI_CTRL_ARESETN => net_gnd0,
S_AXI_CTRL_AWADDR => net_gnd32(0 to 31),
S_AXI_CTRL_AWVALID => net_gnd0,
S_AXI_CTRL_AWREADY => open,
S_AXI_CTRL_WDATA => net_gnd32(0 to 31),
S_AXI_CTRL_WSTRB => net_gnd4(0 to 3),
S_AXI_CTRL_WVALID => net_gnd0,
S_AXI_CTRL_WREADY => open,
S_AXI_CTRL_BRESP => open,
S_AXI_CTRL_BVALID => open,
S_AXI_CTRL_BREADY => net_gnd0,
S_AXI_CTRL_ARADDR => net_gnd32(0 to 31),
S_AXI_CTRL_ARVALID => net_gnd0,
S_AXI_CTRL_ARREADY => open,
S_AXI_CTRL_RDATA => open,
S_AXI_CTRL_RRESP => open,
S_AXI_CTRL_RVALID => open,
S_AXI_CTRL_RREADY => net_gnd0
);
microblaze_0_bram_block : system_microblaze_0_bram_block_wrapper
port map (
BRAM_Rst_A => microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst,
BRAM_Clk_A => microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk,
BRAM_EN_A => microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN,
BRAM_WEN_A => microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN,
BRAM_Addr_A => microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr,
BRAM_Din_A => microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din,
BRAM_Dout_A => microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout,
BRAM_Rst_B => microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst,
BRAM_Clk_B => microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk,
BRAM_EN_B => microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN,
BRAM_WEN_B => microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN,
BRAM_Addr_B => microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr,
BRAM_Din_B => microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din,
BRAM_Dout_B => microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout
);
microblaze_0 : system_microblaze_0_wrapper
port map (
CLK => pgassign1(4),
RESET => microblaze_0_dlmb_LMB_Rst,
MB_RESET => proc_sys_reset_0_MB_Reset,
INTERRUPT => net_gnd0,
INTERRUPT_ADDRESS => net_gnd32,
INTERRUPT_ACK => open,
EXT_BRK => Ext_BRK,
EXT_NM_BRK => Ext_NM_BRK,
DBG_STOP => net_gnd0,
MB_Halted => open,
MB_Error => open,
WAKEUP => net_gnd2,
SLEEP => open,
DBG_WAKEUP => open,
LOCKSTEP_MASTER_OUT => open,
LOCKSTEP_SLAVE_IN => net_gnd4096,
LOCKSTEP_OUT => open,
INSTR => microblaze_0_ilmb_LMB_ReadDBus,
IREADY => microblaze_0_ilmb_LMB_Ready,
IWAIT => microblaze_0_ilmb_LMB_Wait,
ICE => microblaze_0_ilmb_LMB_CE,
IUE => microblaze_0_ilmb_LMB_UE,
INSTR_ADDR => microblaze_0_ilmb_M_ABus,
IFETCH => microblaze_0_ilmb_M_ReadStrobe,
I_AS => microblaze_0_ilmb_M_AddrStrobe,
IPLB_M_ABort => open,
IPLB_M_ABus => open,
IPLB_M_UABus => open,
IPLB_M_BE => open,
IPLB_M_busLock => open,
IPLB_M_lockErr => open,
IPLB_M_MSize => open,
IPLB_M_priority => open,
IPLB_M_rdBurst => open,
IPLB_M_request => open,
IPLB_M_RNW => open,
IPLB_M_size => open,
IPLB_M_TAttribute => open,
IPLB_M_type => open,
IPLB_M_wrBurst => open,
IPLB_M_wrDBus => open,
IPLB_MBusy => net_gnd0,
IPLB_MRdErr => net_gnd0,
IPLB_MWrErr => net_gnd0,
IPLB_MIRQ => net_gnd0,
IPLB_MWrBTerm => net_gnd0,
IPLB_MWrDAck => net_gnd0,
IPLB_MAddrAck => net_gnd0,
IPLB_MRdBTerm => net_gnd0,
IPLB_MRdDAck => net_gnd0,
IPLB_MRdDBus => net_gnd32,
IPLB_MRdWdAddr => net_gnd4,
IPLB_MRearbitrate => net_gnd0,
IPLB_MSSize => net_gnd2,
IPLB_MTimeout => net_gnd0,
DATA_READ => microblaze_0_dlmb_LMB_ReadDBus,
DREADY => microblaze_0_dlmb_LMB_Ready,
DWAIT => microblaze_0_dlmb_LMB_Wait,
DCE => microblaze_0_dlmb_LMB_CE,
DUE => microblaze_0_dlmb_LMB_UE,
DATA_WRITE => microblaze_0_dlmb_M_DBus,
DATA_ADDR => microblaze_0_dlmb_M_ABus,
D_AS => microblaze_0_dlmb_M_AddrStrobe,
READ_STROBE => microblaze_0_dlmb_M_ReadStrobe,
WRITE_STROBE => microblaze_0_dlmb_M_WriteStrobe,
BYTE_ENABLE => microblaze_0_dlmb_M_BE,
DPLB_M_ABort => open,
DPLB_M_ABus => open,
DPLB_M_UABus => open,
DPLB_M_BE => open,
DPLB_M_busLock => open,
DPLB_M_lockErr => open,
DPLB_M_MSize => open,
DPLB_M_priority => open,
DPLB_M_rdBurst => open,
DPLB_M_request => open,
DPLB_M_RNW => open,
DPLB_M_size => open,
DPLB_M_TAttribute => open,
DPLB_M_type => open,
DPLB_M_wrBurst => open,
DPLB_M_wrDBus => open,
DPLB_MBusy => net_gnd0,
DPLB_MRdErr => net_gnd0,
DPLB_MWrErr => net_gnd0,
DPLB_MIRQ => net_gnd0,
DPLB_MWrBTerm => net_gnd0,
DPLB_MWrDAck => net_gnd0,
DPLB_MAddrAck => net_gnd0,
DPLB_MRdBTerm => net_gnd0,
DPLB_MRdDAck => net_gnd0,
DPLB_MRdDBus => net_gnd32,
DPLB_MRdWdAddr => net_gnd4,
DPLB_MRearbitrate => net_gnd0,
DPLB_MSSize => net_gnd2,
DPLB_MTimeout => net_gnd0,
M_AXI_IP_AWID => open,
M_AXI_IP_AWADDR => open,
M_AXI_IP_AWLEN => open,
M_AXI_IP_AWSIZE => open,
M_AXI_IP_AWBURST => open,
M_AXI_IP_AWLOCK => open,
M_AXI_IP_AWCACHE => open,
M_AXI_IP_AWPROT => open,
M_AXI_IP_AWQOS => open,
M_AXI_IP_AWVALID => open,
M_AXI_IP_AWREADY => net_gnd0,
M_AXI_IP_WDATA => open,
M_AXI_IP_WSTRB => open,
M_AXI_IP_WLAST => open,
M_AXI_IP_WVALID => open,
M_AXI_IP_WREADY => net_gnd0,
M_AXI_IP_BID => net_gnd1(0 to 0),
M_AXI_IP_BRESP => net_gnd2(0 to 1),
M_AXI_IP_BVALID => net_gnd0,
M_AXI_IP_BREADY => open,
M_AXI_IP_ARID => open,
M_AXI_IP_ARADDR => open,
M_AXI_IP_ARLEN => open,
M_AXI_IP_ARSIZE => open,
M_AXI_IP_ARBURST => open,
M_AXI_IP_ARLOCK => open,
M_AXI_IP_ARCACHE => open,
M_AXI_IP_ARPROT => open,
M_AXI_IP_ARQOS => open,
M_AXI_IP_ARVALID => open,
M_AXI_IP_ARREADY => net_gnd0,
M_AXI_IP_RID => net_gnd1(0 to 0),
M_AXI_IP_RDATA => net_gnd32(0 to 31),
M_AXI_IP_RRESP => net_gnd2(0 to 1),
M_AXI_IP_RLAST => net_gnd0,
M_AXI_IP_RVALID => net_gnd0,
M_AXI_IP_RREADY => open,
M_AXI_DP_AWID => axi4lite_0_S_AWID(0 to 0),
M_AXI_DP_AWADDR => axi4lite_0_S_AWADDR,
M_AXI_DP_AWLEN => axi4lite_0_S_AWLEN,
M_AXI_DP_AWSIZE => axi4lite_0_S_AWSIZE,
M_AXI_DP_AWBURST => axi4lite_0_S_AWBURST,
M_AXI_DP_AWLOCK => axi4lite_0_S_AWLOCK(0),
M_AXI_DP_AWCACHE => axi4lite_0_S_AWCACHE,
M_AXI_DP_AWPROT => axi4lite_0_S_AWPROT,
M_AXI_DP_AWQOS => axi4lite_0_S_AWQOS,
M_AXI_DP_AWVALID => axi4lite_0_S_AWVALID(0),
M_AXI_DP_AWREADY => axi4lite_0_S_AWREADY(0),
M_AXI_DP_WDATA => axi4lite_0_S_WDATA,
M_AXI_DP_WSTRB => axi4lite_0_S_WSTRB,
M_AXI_DP_WLAST => axi4lite_0_S_WLAST(0),
M_AXI_DP_WVALID => axi4lite_0_S_WVALID(0),
M_AXI_DP_WREADY => axi4lite_0_S_WREADY(0),
M_AXI_DP_BID => axi4lite_0_S_BID(0 downto 0),
M_AXI_DP_BRESP => axi4lite_0_S_BRESP,
M_AXI_DP_BVALID => axi4lite_0_S_BVALID(0),
M_AXI_DP_BREADY => axi4lite_0_S_BREADY(0),
M_AXI_DP_ARID => axi4lite_0_S_ARID(0 to 0),
M_AXI_DP_ARADDR => axi4lite_0_S_ARADDR,
M_AXI_DP_ARLEN => axi4lite_0_S_ARLEN,
M_AXI_DP_ARSIZE => axi4lite_0_S_ARSIZE,
M_AXI_DP_ARBURST => axi4lite_0_S_ARBURST,
M_AXI_DP_ARLOCK => axi4lite_0_S_ARLOCK(0),
M_AXI_DP_ARCACHE => axi4lite_0_S_ARCACHE,
M_AXI_DP_ARPROT => axi4lite_0_S_ARPROT,
M_AXI_DP_ARQOS => axi4lite_0_S_ARQOS,
M_AXI_DP_ARVALID => axi4lite_0_S_ARVALID(0),
M_AXI_DP_ARREADY => axi4lite_0_S_ARREADY(0),
M_AXI_DP_RID => axi4lite_0_S_RID(0 downto 0),
M_AXI_DP_RDATA => axi4lite_0_S_RDATA,
M_AXI_DP_RRESP => axi4lite_0_S_RRESP,
M_AXI_DP_RLAST => axi4lite_0_S_RLAST(0),
M_AXI_DP_RVALID => axi4lite_0_S_RVALID(0),
M_AXI_DP_RREADY => axi4lite_0_S_RREADY(0),
M_AXI_IC_AWID => open,
M_AXI_IC_AWADDR => open,
M_AXI_IC_AWLEN => open,
M_AXI_IC_AWSIZE => open,
M_AXI_IC_AWBURST => open,
M_AXI_IC_AWLOCK => open,
M_AXI_IC_AWCACHE => open,
M_AXI_IC_AWPROT => open,
M_AXI_IC_AWQOS => open,
M_AXI_IC_AWVALID => open,
M_AXI_IC_AWREADY => net_gnd0,
M_AXI_IC_AWUSER => open,
M_AXI_IC_WDATA => open,
M_AXI_IC_WSTRB => open,
M_AXI_IC_WLAST => open,
M_AXI_IC_WVALID => open,
M_AXI_IC_WREADY => net_gnd0,
M_AXI_IC_WUSER => open,
M_AXI_IC_BID => net_gnd1(0 to 0),
M_AXI_IC_BRESP => net_gnd2(0 to 1),
M_AXI_IC_BVALID => net_gnd0,
M_AXI_IC_BREADY => open,
M_AXI_IC_BUSER => net_gnd1(0 to 0),
M_AXI_IC_ARID => open,
M_AXI_IC_ARADDR => open,
M_AXI_IC_ARLEN => open,
M_AXI_IC_ARSIZE => open,
M_AXI_IC_ARBURST => open,
M_AXI_IC_ARLOCK => open,
M_AXI_IC_ARCACHE => open,
M_AXI_IC_ARPROT => open,
M_AXI_IC_ARQOS => open,
M_AXI_IC_ARVALID => open,
M_AXI_IC_ARREADY => net_gnd0,
M_AXI_IC_ARUSER => open,
M_AXI_IC_RID => net_gnd1(0 to 0),
M_AXI_IC_RDATA => net_gnd32(0 to 31),
M_AXI_IC_RRESP => net_gnd2(0 to 1),
M_AXI_IC_RLAST => net_gnd0,
M_AXI_IC_RVALID => net_gnd0,
M_AXI_IC_RREADY => open,
M_AXI_IC_RUSER => net_gnd1(0 to 0),
M_AXI_DC_AWID => open,
M_AXI_DC_AWADDR => open,
M_AXI_DC_AWLEN => open,
M_AXI_DC_AWSIZE => open,
M_AXI_DC_AWBURST => open,
M_AXI_DC_AWLOCK => open,
M_AXI_DC_AWCACHE => open,
M_AXI_DC_AWPROT => open,
M_AXI_DC_AWQOS => open,
M_AXI_DC_AWVALID => open,
M_AXI_DC_AWREADY => net_gnd0,
M_AXI_DC_AWUSER => open,
M_AXI_DC_WDATA => open,
M_AXI_DC_WSTRB => open,
M_AXI_DC_WLAST => open,
M_AXI_DC_WVALID => open,
M_AXI_DC_WREADY => net_gnd0,
M_AXI_DC_WUSER => open,
M_AXI_DC_BID => net_gnd1(0 to 0),
M_AXI_DC_BRESP => net_gnd2(0 to 1),
M_AXI_DC_BVALID => net_gnd0,
M_AXI_DC_BREADY => open,
M_AXI_DC_BUSER => net_gnd1(0 to 0),
M_AXI_DC_ARID => open,
M_AXI_DC_ARADDR => open,
M_AXI_DC_ARLEN => open,
M_AXI_DC_ARSIZE => open,
M_AXI_DC_ARBURST => open,
M_AXI_DC_ARLOCK => open,
M_AXI_DC_ARCACHE => open,
M_AXI_DC_ARPROT => open,
M_AXI_DC_ARQOS => open,
M_AXI_DC_ARVALID => open,
M_AXI_DC_ARREADY => net_gnd0,
M_AXI_DC_ARUSER => open,
M_AXI_DC_RID => net_gnd1(0 to 0),
M_AXI_DC_RDATA => net_gnd32(0 to 31),
M_AXI_DC_RRESP => net_gnd2(0 to 1),
M_AXI_DC_RLAST => net_gnd0,
M_AXI_DC_RVALID => net_gnd0,
M_AXI_DC_RREADY => open,
M_AXI_DC_RUSER => net_gnd1(0 to 0),
DBG_CLK => microblaze_0_debug_Dbg_Clk,
DBG_TDI => microblaze_0_debug_Dbg_TDI,
DBG_TDO => microblaze_0_debug_Dbg_TDO,
DBG_REG_EN => microblaze_0_debug_Dbg_Reg_En,
DBG_SHIFT => microblaze_0_debug_Dbg_Shift,
DBG_CAPTURE => microblaze_0_debug_Dbg_Capture,
DBG_UPDATE => microblaze_0_debug_Dbg_Update,
DEBUG_RST => microblaze_0_debug_Debug_Rst,
Trace_Instruction => open,
Trace_Valid_Instr => open,
Trace_PC => open,
Trace_Reg_Write => open,
Trace_Reg_Addr => open,
Trace_MSR_Reg => open,
Trace_PID_Reg => open,
Trace_New_Reg_Value => open,
Trace_Exception_Taken => open,
Trace_Exception_Kind => open,
Trace_Jump_Taken => open,
Trace_Delay_Slot => open,
Trace_Data_Address => open,
Trace_Data_Access => open,
Trace_Data_Read => open,
Trace_Data_Write => open,
Trace_Data_Write_Value => open,
Trace_Data_Byte_Enable => open,
Trace_DCache_Req => open,
Trace_DCache_Hit => open,
Trace_DCache_Rdy => open,
Trace_DCache_Read => open,
Trace_ICache_Req => open,
Trace_ICache_Hit => open,
Trace_ICache_Rdy => open,
Trace_OF_PipeRun => open,
Trace_EX_PipeRun => open,
Trace_MEM_PipeRun => open,
Trace_MB_Halted => open,
Trace_Jump_Hit => open,
FSL0_S_CLK => open,
FSL0_S_READ => fsl_v20_1_FSL_S_Read,
FSL0_S_DATA => fsl_v20_1_FSL_S_Data,
FSL0_S_CONTROL => fsl_v20_1_FSL_S_Control,
FSL0_S_EXISTS => fsl_v20_1_FSL_S_Exists,
FSL0_M_CLK => open,
FSL0_M_WRITE => fsl_v20_0_FSL_M_Write,
FSL0_M_DATA => fsl_v20_0_FSL_M_Data,
FSL0_M_CONTROL => fsl_v20_0_FSL_M_Control,
FSL0_M_FULL => fsl_v20_0_FSL_M_Full,
FSL1_S_CLK => open,
FSL1_S_READ => open,
FSL1_S_DATA => net_gnd32,
FSL1_S_CONTROL => net_gnd0,
FSL1_S_EXISTS => net_gnd0,
FSL1_M_CLK => open,
FSL1_M_WRITE => open,
FSL1_M_DATA => open,
FSL1_M_CONTROL => open,
FSL1_M_FULL => net_gnd0,
FSL2_S_CLK => open,
FSL2_S_READ => open,
FSL2_S_DATA => net_gnd32,
FSL2_S_CONTROL => net_gnd0,
FSL2_S_EXISTS => net_gnd0,
FSL2_M_CLK => open,
FSL2_M_WRITE => open,
FSL2_M_DATA => open,
FSL2_M_CONTROL => open,
FSL2_M_FULL => net_gnd0,
FSL3_S_CLK => open,
FSL3_S_READ => open,
FSL3_S_DATA => net_gnd32,
FSL3_S_CONTROL => net_gnd0,
FSL3_S_EXISTS => net_gnd0,
FSL3_M_CLK => open,
FSL3_M_WRITE => open,
FSL3_M_DATA => open,
FSL3_M_CONTROL => open,
FSL3_M_FULL => net_gnd0,
FSL4_S_CLK => open,
FSL4_S_READ => open,
FSL4_S_DATA => net_gnd32,
FSL4_S_CONTROL => net_gnd0,
FSL4_S_EXISTS => net_gnd0,
FSL4_M_CLK => open,
FSL4_M_WRITE => open,
FSL4_M_DATA => open,
FSL4_M_CONTROL => open,
FSL4_M_FULL => net_gnd0,
FSL5_S_CLK => open,
FSL5_S_READ => open,
FSL5_S_DATA => net_gnd32,
FSL5_S_CONTROL => net_gnd0,
FSL5_S_EXISTS => net_gnd0,
FSL5_M_CLK => open,
FSL5_M_WRITE => open,
FSL5_M_DATA => open,
FSL5_M_CONTROL => open,
FSL5_M_FULL => net_gnd0,
FSL6_S_CLK => open,
FSL6_S_READ => open,
FSL6_S_DATA => net_gnd32,
FSL6_S_CONTROL => net_gnd0,
FSL6_S_EXISTS => net_gnd0,
FSL6_M_CLK => open,
FSL6_M_WRITE => open,
FSL6_M_DATA => open,
FSL6_M_CONTROL => open,
FSL6_M_FULL => net_gnd0,
FSL7_S_CLK => open,
FSL7_S_READ => open,
FSL7_S_DATA => net_gnd32,
FSL7_S_CONTROL => net_gnd0,
FSL7_S_EXISTS => net_gnd0,
FSL7_M_CLK => open,
FSL7_M_WRITE => open,
FSL7_M_DATA => open,
FSL7_M_CONTROL => open,
FSL7_M_FULL => net_gnd0,
FSL8_S_CLK => open,
FSL8_S_READ => open,
FSL8_S_DATA => net_gnd32,
FSL8_S_CONTROL => net_gnd0,
FSL8_S_EXISTS => net_gnd0,
FSL8_M_CLK => open,
FSL8_M_WRITE => open,
FSL8_M_DATA => open,
FSL8_M_CONTROL => open,
FSL8_M_FULL => net_gnd0,
FSL9_S_CLK => open,
FSL9_S_READ => open,
FSL9_S_DATA => net_gnd32,
FSL9_S_CONTROL => net_gnd0,
FSL9_S_EXISTS => net_gnd0,
FSL9_M_CLK => open,
FSL9_M_WRITE => open,
FSL9_M_DATA => open,
FSL9_M_CONTROL => open,
FSL9_M_FULL => net_gnd0,
FSL10_S_CLK => open,
FSL10_S_READ => open,
FSL10_S_DATA => net_gnd32,
FSL10_S_CONTROL => net_gnd0,
FSL10_S_EXISTS => net_gnd0,
FSL10_M_CLK => open,
FSL10_M_WRITE => open,
FSL10_M_DATA => open,
FSL10_M_CONTROL => open,
FSL10_M_FULL => net_gnd0,
FSL11_S_CLK => open,
FSL11_S_READ => open,
FSL11_S_DATA => net_gnd32,
FSL11_S_CONTROL => net_gnd0,
FSL11_S_EXISTS => net_gnd0,
FSL11_M_CLK => open,
FSL11_M_WRITE => open,
FSL11_M_DATA => open,
FSL11_M_CONTROL => open,
FSL11_M_FULL => net_gnd0,
FSL12_S_CLK => open,
FSL12_S_READ => open,
FSL12_S_DATA => net_gnd32,
FSL12_S_CONTROL => net_gnd0,
FSL12_S_EXISTS => net_gnd0,
FSL12_M_CLK => open,
FSL12_M_WRITE => open,
FSL12_M_DATA => open,
FSL12_M_CONTROL => open,
FSL12_M_FULL => net_gnd0,
FSL13_S_CLK => open,
FSL13_S_READ => open,
FSL13_S_DATA => net_gnd32,
FSL13_S_CONTROL => net_gnd0,
FSL13_S_EXISTS => net_gnd0,
FSL13_M_CLK => open,
FSL13_M_WRITE => open,
FSL13_M_DATA => open,
FSL13_M_CONTROL => open,
FSL13_M_FULL => net_gnd0,
FSL14_S_CLK => open,
FSL14_S_READ => open,
FSL14_S_DATA => net_gnd32,
FSL14_S_CONTROL => net_gnd0,
FSL14_S_EXISTS => net_gnd0,
FSL14_M_CLK => open,
FSL14_M_WRITE => open,
FSL14_M_DATA => open,
FSL14_M_CONTROL => open,
FSL14_M_FULL => net_gnd0,
FSL15_S_CLK => open,
FSL15_S_READ => open,
FSL15_S_DATA => net_gnd32,
FSL15_S_CONTROL => net_gnd0,
FSL15_S_EXISTS => net_gnd0,
FSL15_M_CLK => open,
FSL15_M_WRITE => open,
FSL15_M_DATA => open,
FSL15_M_CONTROL => open,
FSL15_M_FULL => net_gnd0,
M0_AXIS_TLAST => open,
M0_AXIS_TDATA => open,
M0_AXIS_TVALID => open,
M0_AXIS_TREADY => net_gnd0,
S0_AXIS_TLAST => net_gnd0,
S0_AXIS_TDATA => net_gnd32(0 to 31),
S0_AXIS_TVALID => net_gnd0,
S0_AXIS_TREADY => open,
M1_AXIS_TLAST => open,
M1_AXIS_TDATA => open,
M1_AXIS_TVALID => open,
M1_AXIS_TREADY => net_gnd0,
S1_AXIS_TLAST => net_gnd0,
S1_AXIS_TDATA => net_gnd32(0 to 31),
S1_AXIS_TVALID => net_gnd0,
S1_AXIS_TREADY => open,
M2_AXIS_TLAST => open,
M2_AXIS_TDATA => open,
M2_AXIS_TVALID => open,
M2_AXIS_TREADY => net_gnd0,
S2_AXIS_TLAST => net_gnd0,
S2_AXIS_TDATA => net_gnd32(0 to 31),
S2_AXIS_TVALID => net_gnd0,
S2_AXIS_TREADY => open,
M3_AXIS_TLAST => open,
M3_AXIS_TDATA => open,
M3_AXIS_TVALID => open,
M3_AXIS_TREADY => net_gnd0,
S3_AXIS_TLAST => net_gnd0,
S3_AXIS_TDATA => net_gnd32(0 to 31),
S3_AXIS_TVALID => net_gnd0,
S3_AXIS_TREADY => open,
M4_AXIS_TLAST => open,
M4_AXIS_TDATA => open,
M4_AXIS_TVALID => open,
M4_AXIS_TREADY => net_gnd0,
S4_AXIS_TLAST => net_gnd0,
S4_AXIS_TDATA => net_gnd32(0 to 31),
S4_AXIS_TVALID => net_gnd0,
S4_AXIS_TREADY => open,
M5_AXIS_TLAST => open,
M5_AXIS_TDATA => open,
M5_AXIS_TVALID => open,
M5_AXIS_TREADY => net_gnd0,
S5_AXIS_TLAST => net_gnd0,
S5_AXIS_TDATA => net_gnd32(0 to 31),
S5_AXIS_TVALID => net_gnd0,
S5_AXIS_TREADY => open,
M6_AXIS_TLAST => open,
M6_AXIS_TDATA => open,
M6_AXIS_TVALID => open,
M6_AXIS_TREADY => net_gnd0,
S6_AXIS_TLAST => net_gnd0,
S6_AXIS_TDATA => net_gnd32(0 to 31),
S6_AXIS_TVALID => net_gnd0,
S6_AXIS_TREADY => open,
M7_AXIS_TLAST => open,
M7_AXIS_TDATA => open,
M7_AXIS_TVALID => open,
M7_AXIS_TREADY => net_gnd0,
S7_AXIS_TLAST => net_gnd0,
S7_AXIS_TDATA => net_gnd32(0 to 31),
S7_AXIS_TVALID => net_gnd0,
S7_AXIS_TREADY => open,
M8_AXIS_TLAST => open,
M8_AXIS_TDATA => open,
M8_AXIS_TVALID => open,
M8_AXIS_TREADY => net_gnd0,
S8_AXIS_TLAST => net_gnd0,
S8_AXIS_TDATA => net_gnd32(0 to 31),
S8_AXIS_TVALID => net_gnd0,
S8_AXIS_TREADY => open,
M9_AXIS_TLAST => open,
M9_AXIS_TDATA => open,
M9_AXIS_TVALID => open,
M9_AXIS_TREADY => net_gnd0,
S9_AXIS_TLAST => net_gnd0,
S9_AXIS_TDATA => net_gnd32(0 to 31),
S9_AXIS_TVALID => net_gnd0,
S9_AXIS_TREADY => open,
M10_AXIS_TLAST => open,
M10_AXIS_TDATA => open,
M10_AXIS_TVALID => open,
M10_AXIS_TREADY => net_gnd0,
S10_AXIS_TLAST => net_gnd0,
S10_AXIS_TDATA => net_gnd32(0 to 31),
S10_AXIS_TVALID => net_gnd0,
S10_AXIS_TREADY => open,
M11_AXIS_TLAST => open,
M11_AXIS_TDATA => open,
M11_AXIS_TVALID => open,
M11_AXIS_TREADY => net_gnd0,
S11_AXIS_TLAST => net_gnd0,
S11_AXIS_TDATA => net_gnd32(0 to 31),
S11_AXIS_TVALID => net_gnd0,
S11_AXIS_TREADY => open,
M12_AXIS_TLAST => open,
M12_AXIS_TDATA => open,
M12_AXIS_TVALID => open,
M12_AXIS_TREADY => net_gnd0,
S12_AXIS_TLAST => net_gnd0,
S12_AXIS_TDATA => net_gnd32(0 to 31),
S12_AXIS_TVALID => net_gnd0,
S12_AXIS_TREADY => open,
M13_AXIS_TLAST => open,
M13_AXIS_TDATA => open,
M13_AXIS_TVALID => open,
M13_AXIS_TREADY => net_gnd0,
S13_AXIS_TLAST => net_gnd0,
S13_AXIS_TDATA => net_gnd32(0 to 31),
S13_AXIS_TVALID => net_gnd0,
S13_AXIS_TREADY => open,
M14_AXIS_TLAST => open,
M14_AXIS_TDATA => open,
M14_AXIS_TVALID => open,
M14_AXIS_TREADY => net_gnd0,
S14_AXIS_TLAST => net_gnd0,
S14_AXIS_TDATA => net_gnd32(0 to 31),
S14_AXIS_TVALID => net_gnd0,
S14_AXIS_TREADY => open,
M15_AXIS_TLAST => open,
M15_AXIS_TDATA => open,
M15_AXIS_TVALID => open,
M15_AXIS_TREADY => net_gnd0,
S15_AXIS_TLAST => net_gnd0,
S15_AXIS_TDATA => net_gnd32(0 to 31),
S15_AXIS_TVALID => net_gnd0,
S15_AXIS_TREADY => open,
ICACHE_FSL_IN_CLK => open,
ICACHE_FSL_IN_READ => open,
ICACHE_FSL_IN_DATA => net_gnd32,
ICACHE_FSL_IN_CONTROL => net_gnd0,
ICACHE_FSL_IN_EXISTS => net_gnd0,
ICACHE_FSL_OUT_CLK => open,
ICACHE_FSL_OUT_WRITE => open,
ICACHE_FSL_OUT_DATA => open,
ICACHE_FSL_OUT_CONTROL => open,
ICACHE_FSL_OUT_FULL => net_gnd0,
DCACHE_FSL_IN_CLK => open,
DCACHE_FSL_IN_READ => open,
DCACHE_FSL_IN_DATA => net_gnd32,
DCACHE_FSL_IN_CONTROL => net_gnd0,
DCACHE_FSL_IN_EXISTS => net_gnd0,
DCACHE_FSL_OUT_CLK => open,
DCACHE_FSL_OUT_WRITE => open,
DCACHE_FSL_OUT_DATA => open,
DCACHE_FSL_OUT_CONTROL => open,
DCACHE_FSL_OUT_FULL => net_gnd0
);
debug_module : system_debug_module_wrapper
port map (
Interrupt => open,
Debug_SYS_Rst => proc_sys_reset_0_MB_Debug_Sys_Rst,
Ext_BRK => Ext_BRK,
Ext_NM_BRK => Ext_NM_BRK,
S_AXI_ACLK => pgassign1(4),
S_AXI_ARESETN => axi4lite_0_M_ARESETN(0),
S_AXI_AWADDR => axi4lite_0_M_AWADDR(31 downto 0),
S_AXI_AWVALID => axi4lite_0_M_AWVALID(0),
S_AXI_AWREADY => axi4lite_0_M_AWREADY(0),
S_AXI_WDATA => axi4lite_0_M_WDATA(31 downto 0),
S_AXI_WSTRB => axi4lite_0_M_WSTRB(3 downto 0),
S_AXI_WVALID => axi4lite_0_M_WVALID(0),
S_AXI_WREADY => axi4lite_0_M_WREADY(0),
S_AXI_BRESP => axi4lite_0_M_BRESP(1 downto 0),
S_AXI_BVALID => axi4lite_0_M_BVALID(0),
S_AXI_BREADY => axi4lite_0_M_BREADY(0),
S_AXI_ARADDR => axi4lite_0_M_ARADDR(31 downto 0),
S_AXI_ARVALID => axi4lite_0_M_ARVALID(0),
S_AXI_ARREADY => axi4lite_0_M_ARREADY(0),
S_AXI_RDATA => axi4lite_0_M_RDATA(31 downto 0),
S_AXI_RRESP => axi4lite_0_M_RRESP(1 downto 0),
S_AXI_RVALID => axi4lite_0_M_RVALID(0),
S_AXI_RREADY => axi4lite_0_M_RREADY(0),
SPLB_Clk => net_gnd0,
SPLB_Rst => net_gnd0,
PLB_ABus => net_gnd32,
PLB_UABus => net_gnd32,
PLB_PAValid => net_gnd0,
PLB_SAValid => net_gnd0,
PLB_rdPrim => net_gnd0,
PLB_wrPrim => net_gnd0,
PLB_masterID => net_gnd3,
PLB_abort => net_gnd0,
PLB_busLock => net_gnd0,
PLB_RNW => net_gnd0,
PLB_BE => net_gnd4,
PLB_MSize => net_gnd2,
PLB_size => net_gnd4,
PLB_type => net_gnd3,
PLB_lockErr => net_gnd0,
PLB_wrDBus => net_gnd32,
PLB_wrBurst => net_gnd0,
PLB_rdBurst => net_gnd0,
PLB_wrPendReq => net_gnd0,
PLB_rdPendReq => net_gnd0,
PLB_wrPendPri => net_gnd2,
PLB_rdPendPri => net_gnd2,
PLB_reqPri => net_gnd2,
PLB_TAttribute => net_gnd16,
Sl_addrAck => open,
Sl_SSize => open,
Sl_wait => open,
Sl_rearbitrate => open,
Sl_wrDAck => open,
Sl_wrComp => open,
Sl_wrBTerm => open,
Sl_rdDBus => open,
Sl_rdWdAddr => open,
Sl_rdDAck => open,
Sl_rdComp => open,
Sl_rdBTerm => open,
Sl_MBusy => open,
Sl_MWrErr => open,
Sl_MRdErr => open,
Sl_MIRQ => open,
Dbg_Clk_0 => microblaze_0_debug_Dbg_Clk,
Dbg_TDI_0 => microblaze_0_debug_Dbg_TDI,
Dbg_TDO_0 => microblaze_0_debug_Dbg_TDO,
Dbg_Reg_En_0 => microblaze_0_debug_Dbg_Reg_En,
Dbg_Capture_0 => microblaze_0_debug_Dbg_Capture,
Dbg_Shift_0 => microblaze_0_debug_Dbg_Shift,
Dbg_Update_0 => microblaze_0_debug_Dbg_Update,
Dbg_Rst_0 => microblaze_0_debug_Debug_Rst,
Dbg_Clk_1 => open,
Dbg_TDI_1 => open,
Dbg_TDO_1 => net_gnd0,
Dbg_Reg_En_1 => open,
Dbg_Capture_1 => open,
Dbg_Shift_1 => open,
Dbg_Update_1 => open,
Dbg_Rst_1 => open,
Dbg_Clk_2 => open,
Dbg_TDI_2 => open,
Dbg_TDO_2 => net_gnd0,
Dbg_Reg_En_2 => open,
Dbg_Capture_2 => open,
Dbg_Shift_2 => open,
Dbg_Update_2 => open,
Dbg_Rst_2 => open,
Dbg_Clk_3 => open,
Dbg_TDI_3 => open,
Dbg_TDO_3 => net_gnd0,
Dbg_Reg_En_3 => open,
Dbg_Capture_3 => open,
Dbg_Shift_3 => open,
Dbg_Update_3 => open,
Dbg_Rst_3 => open,
Dbg_Clk_4 => open,
Dbg_TDI_4 => open,
Dbg_TDO_4 => net_gnd0,
Dbg_Reg_En_4 => open,
Dbg_Capture_4 => open,
Dbg_Shift_4 => open,
Dbg_Update_4 => open,
Dbg_Rst_4 => open,
Dbg_Clk_5 => open,
Dbg_TDI_5 => open,
Dbg_TDO_5 => net_gnd0,
Dbg_Reg_En_5 => open,
Dbg_Capture_5 => open,
Dbg_Shift_5 => open,
Dbg_Update_5 => open,
Dbg_Rst_5 => open,
Dbg_Clk_6 => open,
Dbg_TDI_6 => open,
Dbg_TDO_6 => net_gnd0,
Dbg_Reg_En_6 => open,
Dbg_Capture_6 => open,
Dbg_Shift_6 => open,
Dbg_Update_6 => open,
Dbg_Rst_6 => open,
Dbg_Clk_7 => open,
Dbg_TDI_7 => open,
Dbg_TDO_7 => net_gnd0,
Dbg_Reg_En_7 => open,
Dbg_Capture_7 => open,
Dbg_Shift_7 => open,
Dbg_Update_7 => open,
Dbg_Rst_7 => open,
Dbg_Clk_8 => open,
Dbg_TDI_8 => open,
Dbg_TDO_8 => net_gnd0,
Dbg_Reg_En_8 => open,
Dbg_Capture_8 => open,
Dbg_Shift_8 => open,
Dbg_Update_8 => open,
Dbg_Rst_8 => open,
Dbg_Clk_9 => open,
Dbg_TDI_9 => open,
Dbg_TDO_9 => net_gnd0,
Dbg_Reg_En_9 => open,
Dbg_Capture_9 => open,
Dbg_Shift_9 => open,
Dbg_Update_9 => open,
Dbg_Rst_9 => open,
Dbg_Clk_10 => open,
Dbg_TDI_10 => open,
Dbg_TDO_10 => net_gnd0,
Dbg_Reg_En_10 => open,
Dbg_Capture_10 => open,
Dbg_Shift_10 => open,
Dbg_Update_10 => open,
Dbg_Rst_10 => open,
Dbg_Clk_11 => open,
Dbg_TDI_11 => open,
Dbg_TDO_11 => net_gnd0,
Dbg_Reg_En_11 => open,
Dbg_Capture_11 => open,
Dbg_Shift_11 => open,
Dbg_Update_11 => open,
Dbg_Rst_11 => open,
Dbg_Clk_12 => open,
Dbg_TDI_12 => open,
Dbg_TDO_12 => net_gnd0,
Dbg_Reg_En_12 => open,
Dbg_Capture_12 => open,
Dbg_Shift_12 => open,
Dbg_Update_12 => open,
Dbg_Rst_12 => open,
Dbg_Clk_13 => open,
Dbg_TDI_13 => open,
Dbg_TDO_13 => net_gnd0,
Dbg_Reg_En_13 => open,
Dbg_Capture_13 => open,
Dbg_Shift_13 => open,
Dbg_Update_13 => open,
Dbg_Rst_13 => open,
Dbg_Clk_14 => open,
Dbg_TDI_14 => open,
Dbg_TDO_14 => net_gnd0,
Dbg_Reg_En_14 => open,
Dbg_Capture_14 => open,
Dbg_Shift_14 => open,
Dbg_Update_14 => open,
Dbg_Rst_14 => open,
Dbg_Clk_15 => open,
Dbg_TDI_15 => open,
Dbg_TDO_15 => net_gnd0,
Dbg_Reg_En_15 => open,
Dbg_Capture_15 => open,
Dbg_Shift_15 => open,
Dbg_Update_15 => open,
Dbg_Rst_15 => open,
Dbg_Clk_16 => open,
Dbg_TDI_16 => open,
Dbg_TDO_16 => net_gnd0,
Dbg_Reg_En_16 => open,
Dbg_Capture_16 => open,
Dbg_Shift_16 => open,
Dbg_Update_16 => open,
Dbg_Rst_16 => open,
Dbg_Clk_17 => open,
Dbg_TDI_17 => open,
Dbg_TDO_17 => net_gnd0,
Dbg_Reg_En_17 => open,
Dbg_Capture_17 => open,
Dbg_Shift_17 => open,
Dbg_Update_17 => open,
Dbg_Rst_17 => open,
Dbg_Clk_18 => open,
Dbg_TDI_18 => open,
Dbg_TDO_18 => net_gnd0,
Dbg_Reg_En_18 => open,
Dbg_Capture_18 => open,
Dbg_Shift_18 => open,
Dbg_Update_18 => open,
Dbg_Rst_18 => open,
Dbg_Clk_19 => open,
Dbg_TDI_19 => open,
Dbg_TDO_19 => net_gnd0,
Dbg_Reg_En_19 => open,
Dbg_Capture_19 => open,
Dbg_Shift_19 => open,
Dbg_Update_19 => open,
Dbg_Rst_19 => open,
Dbg_Clk_20 => open,
Dbg_TDI_20 => open,
Dbg_TDO_20 => net_gnd0,
Dbg_Reg_En_20 => open,
Dbg_Capture_20 => open,
Dbg_Shift_20 => open,
Dbg_Update_20 => open,
Dbg_Rst_20 => open,
Dbg_Clk_21 => open,
Dbg_TDI_21 => open,
Dbg_TDO_21 => net_gnd0,
Dbg_Reg_En_21 => open,
Dbg_Capture_21 => open,
Dbg_Shift_21 => open,
Dbg_Update_21 => open,
Dbg_Rst_21 => open,
Dbg_Clk_22 => open,
Dbg_TDI_22 => open,
Dbg_TDO_22 => net_gnd0,
Dbg_Reg_En_22 => open,
Dbg_Capture_22 => open,
Dbg_Shift_22 => open,
Dbg_Update_22 => open,
Dbg_Rst_22 => open,
Dbg_Clk_23 => open,
Dbg_TDI_23 => open,
Dbg_TDO_23 => net_gnd0,
Dbg_Reg_En_23 => open,
Dbg_Capture_23 => open,
Dbg_Shift_23 => open,
Dbg_Update_23 => open,
Dbg_Rst_23 => open,
Dbg_Clk_24 => open,
Dbg_TDI_24 => open,
Dbg_TDO_24 => net_gnd0,
Dbg_Reg_En_24 => open,
Dbg_Capture_24 => open,
Dbg_Shift_24 => open,
Dbg_Update_24 => open,
Dbg_Rst_24 => open,
Dbg_Clk_25 => open,
Dbg_TDI_25 => open,
Dbg_TDO_25 => net_gnd0,
Dbg_Reg_En_25 => open,
Dbg_Capture_25 => open,
Dbg_Shift_25 => open,
Dbg_Update_25 => open,
Dbg_Rst_25 => open,
Dbg_Clk_26 => open,
Dbg_TDI_26 => open,
Dbg_TDO_26 => net_gnd0,
Dbg_Reg_En_26 => open,
Dbg_Capture_26 => open,
Dbg_Shift_26 => open,
Dbg_Update_26 => open,
Dbg_Rst_26 => open,
Dbg_Clk_27 => open,
Dbg_TDI_27 => open,
Dbg_TDO_27 => net_gnd0,
Dbg_Reg_En_27 => open,
Dbg_Capture_27 => open,
Dbg_Shift_27 => open,
Dbg_Update_27 => open,
Dbg_Rst_27 => open,
Dbg_Clk_28 => open,
Dbg_TDI_28 => open,
Dbg_TDO_28 => net_gnd0,
Dbg_Reg_En_28 => open,
Dbg_Capture_28 => open,
Dbg_Shift_28 => open,
Dbg_Update_28 => open,
Dbg_Rst_28 => open,
Dbg_Clk_29 => open,
Dbg_TDI_29 => open,
Dbg_TDO_29 => net_gnd0,
Dbg_Reg_En_29 => open,
Dbg_Capture_29 => open,
Dbg_Shift_29 => open,
Dbg_Update_29 => open,
Dbg_Rst_29 => open,
Dbg_Clk_30 => open,
Dbg_TDI_30 => open,
Dbg_TDO_30 => net_gnd0,
Dbg_Reg_En_30 => open,
Dbg_Capture_30 => open,
Dbg_Shift_30 => open,
Dbg_Update_30 => open,
Dbg_Rst_30 => open,
Dbg_Clk_31 => open,
Dbg_TDI_31 => open,
Dbg_TDO_31 => net_gnd0,
Dbg_Reg_En_31 => open,
Dbg_Capture_31 => open,
Dbg_Shift_31 => open,
Dbg_Update_31 => open,
Dbg_Rst_31 => open,
bscan_tdi => open,
bscan_reset => open,
bscan_shift => open,
bscan_update => open,
bscan_capture => open,
bscan_sel1 => open,
bscan_drck1 => open,
bscan_tdo1 => net_gnd0,
bscan_ext_tdi => net_gnd0,
bscan_ext_reset => net_gnd0,
bscan_ext_shift => net_gnd0,
bscan_ext_update => net_gnd0,
bscan_ext_capture => net_gnd0,
bscan_ext_sel => net_gnd0,
bscan_ext_drck => net_gnd0,
bscan_ext_tdo => open,
Ext_JTAG_DRCK => open,
Ext_JTAG_RESET => open,
Ext_JTAG_SEL => open,
Ext_JTAG_CAPTURE => open,
Ext_JTAG_SHIFT => open,
Ext_JTAG_UPDATE => open,
Ext_JTAG_TDI => open,
Ext_JTAG_TDO => net_gnd0
);
clock_generator_0 : system_clock_generator_0_wrapper
port map (
CLKIN => GCLK,
CLKOUT0 => clk_100_0000MHz(0),
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
CLKOUT7 => open,
CLKOUT8 => open,
CLKOUT9 => open,
CLKOUT10 => open,
CLKOUT11 => open,
CLKOUT12 => open,
CLKOUT13 => open,
CLKOUT14 => open,
CLKOUT15 => open,
CLKFBIN => net_gnd0,
CLKFBOUT => open,
PSCLK => net_gnd0,
PSEN => net_gnd0,
PSINCDEC => net_gnd0,
PSDONE => open,
RST => RESET,
LOCKED => proc_sys_reset_0_Dcm_locked
);
axi4lite_0 : system_axi4lite_0_wrapper
port map (
INTERCONNECT_ACLK => pgassign1(4),
INTERCONNECT_ARESETN => proc_sys_reset_0_Interconnect_aresetn(0),
S_AXI_ARESET_OUT_N => open,
M_AXI_ARESET_OUT_N => axi4lite_0_M_ARESETN,
IRQ => open,
S_AXI_ACLK => pgassign1(4 downto 4),
S_AXI_AWID => axi4lite_0_S_AWID(0 to 0),
S_AXI_AWADDR => axi4lite_0_S_AWADDR,
S_AXI_AWLEN => axi4lite_0_S_AWLEN,
S_AXI_AWSIZE => axi4lite_0_S_AWSIZE,
S_AXI_AWBURST => axi4lite_0_S_AWBURST,
S_AXI_AWLOCK => axi4lite_0_S_AWLOCK,
S_AXI_AWCACHE => axi4lite_0_S_AWCACHE,
S_AXI_AWPROT => axi4lite_0_S_AWPROT,
S_AXI_AWQOS => axi4lite_0_S_AWQOS,
S_AXI_AWUSER => net_gnd1(0 to 0),
S_AXI_AWVALID => axi4lite_0_S_AWVALID(0 to 0),
S_AXI_AWREADY => axi4lite_0_S_AWREADY(0 to 0),
S_AXI_WID => net_gnd1(0 to 0),
S_AXI_WDATA => axi4lite_0_S_WDATA,
S_AXI_WSTRB => axi4lite_0_S_WSTRB,
S_AXI_WLAST => axi4lite_0_S_WLAST(0 to 0),
S_AXI_WUSER => net_gnd1(0 to 0),
S_AXI_WVALID => axi4lite_0_S_WVALID(0 to 0),
S_AXI_WREADY => axi4lite_0_S_WREADY(0 to 0),
S_AXI_BID => axi4lite_0_S_BID(0 downto 0),
S_AXI_BRESP => axi4lite_0_S_BRESP,
S_AXI_BUSER => open,
S_AXI_BVALID => axi4lite_0_S_BVALID(0 to 0),
S_AXI_BREADY => axi4lite_0_S_BREADY(0 to 0),
S_AXI_ARID => axi4lite_0_S_ARID(0 to 0),
S_AXI_ARADDR => axi4lite_0_S_ARADDR,
S_AXI_ARLEN => axi4lite_0_S_ARLEN,
S_AXI_ARSIZE => axi4lite_0_S_ARSIZE,
S_AXI_ARBURST => axi4lite_0_S_ARBURST,
S_AXI_ARLOCK => axi4lite_0_S_ARLOCK,
S_AXI_ARCACHE => axi4lite_0_S_ARCACHE,
S_AXI_ARPROT => axi4lite_0_S_ARPROT,
S_AXI_ARQOS => axi4lite_0_S_ARQOS,
S_AXI_ARUSER => net_gnd1(0 to 0),
S_AXI_ARVALID => axi4lite_0_S_ARVALID(0 to 0),
S_AXI_ARREADY => axi4lite_0_S_ARREADY(0 to 0),
S_AXI_RID => axi4lite_0_S_RID(0 downto 0),
S_AXI_RDATA => axi4lite_0_S_RDATA,
S_AXI_RRESP => axi4lite_0_S_RRESP,
S_AXI_RLAST => axi4lite_0_S_RLAST(0 to 0),
S_AXI_RUSER => open,
S_AXI_RVALID => axi4lite_0_S_RVALID(0 to 0),
S_AXI_RREADY => axi4lite_0_S_RREADY(0 to 0),
M_AXI_ACLK => pgassign1,
M_AXI_AWID => open,
M_AXI_AWADDR => axi4lite_0_M_AWADDR,
M_AXI_AWLEN => open,
M_AXI_AWSIZE => open,
M_AXI_AWBURST => open,
M_AXI_AWLOCK => open,
M_AXI_AWCACHE => open,
M_AXI_AWPROT => open,
M_AXI_AWREGION => open,
M_AXI_AWQOS => open,
M_AXI_AWUSER => open,
M_AXI_AWVALID => axi4lite_0_M_AWVALID,
M_AXI_AWREADY => axi4lite_0_M_AWREADY,
M_AXI_WID => open,
M_AXI_WDATA => axi4lite_0_M_WDATA,
M_AXI_WSTRB => axi4lite_0_M_WSTRB,
M_AXI_WLAST => open,
M_AXI_WUSER => open,
M_AXI_WVALID => axi4lite_0_M_WVALID,
M_AXI_WREADY => axi4lite_0_M_WREADY,
M_AXI_BID => net_gnd5,
M_AXI_BRESP => axi4lite_0_M_BRESP,
M_AXI_BUSER => net_gnd5,
M_AXI_BVALID => axi4lite_0_M_BVALID,
M_AXI_BREADY => axi4lite_0_M_BREADY,
M_AXI_ARID => open,
M_AXI_ARADDR => axi4lite_0_M_ARADDR,
M_AXI_ARLEN => open,
M_AXI_ARSIZE => open,
M_AXI_ARBURST => open,
M_AXI_ARLOCK => open,
M_AXI_ARCACHE => open,
M_AXI_ARPROT => open,
M_AXI_ARREGION => open,
M_AXI_ARQOS => open,
M_AXI_ARUSER => open,
M_AXI_ARVALID => axi4lite_0_M_ARVALID,
M_AXI_ARREADY => axi4lite_0_M_ARREADY,
M_AXI_RID => net_gnd5,
M_AXI_RDATA => axi4lite_0_M_RDATA,
M_AXI_RRESP => axi4lite_0_M_RRESP,
M_AXI_RLAST => net_gnd5,
M_AXI_RUSER => net_gnd5,
M_AXI_RVALID => axi4lite_0_M_RVALID,
M_AXI_RREADY => axi4lite_0_M_RREADY,
S_AXI_CTRL_AWADDR => net_gnd32(0 to 31),
S_AXI_CTRL_AWVALID => net_gnd0,
S_AXI_CTRL_AWREADY => open,
S_AXI_CTRL_WDATA => net_gnd32(0 to 31),
S_AXI_CTRL_WVALID => net_gnd0,
S_AXI_CTRL_WREADY => open,
S_AXI_CTRL_BRESP => open,
S_AXI_CTRL_BVALID => open,
S_AXI_CTRL_BREADY => net_gnd0,
S_AXI_CTRL_ARADDR => net_gnd32(0 to 31),
S_AXI_CTRL_ARVALID => net_gnd0,
S_AXI_CTRL_ARREADY => open,
S_AXI_CTRL_RDATA => open,
S_AXI_CTRL_RRESP => open,
S_AXI_CTRL_RVALID => open,
S_AXI_CTRL_RREADY => net_gnd0,
INTERCONNECT_ARESET_OUT_N => open,
DEBUG_AW_TRANS_SEQ => open,
DEBUG_AW_ARB_GRANT => open,
DEBUG_AR_TRANS_SEQ => open,
DEBUG_AR_ARB_GRANT => open,
DEBUG_AW_TRANS_QUAL => open,
DEBUG_AW_ACCEPT_CNT => open,
DEBUG_AW_ACTIVE_THREAD => open,
DEBUG_AW_ACTIVE_TARGET => open,
DEBUG_AW_ACTIVE_REGION => open,
DEBUG_AW_ERROR => open,
DEBUG_AW_TARGET => open,
DEBUG_AR_TRANS_QUAL => open,
DEBUG_AR_ACCEPT_CNT => open,
DEBUG_AR_ACTIVE_THREAD => open,
DEBUG_AR_ACTIVE_TARGET => open,
DEBUG_AR_ACTIVE_REGION => open,
DEBUG_AR_ERROR => open,
DEBUG_AR_TARGET => open,
DEBUG_B_TRANS_SEQ => open,
DEBUG_R_BEAT_CNT => open,
DEBUG_R_TRANS_SEQ => open,
DEBUG_AW_ISSUING_CNT => open,
DEBUG_AR_ISSUING_CNT => open,
DEBUG_W_BEAT_CNT => open,
DEBUG_W_TRANS_SEQ => open,
DEBUG_BID_TARGET => open,
DEBUG_BID_ERROR => open,
DEBUG_RID_TARGET => open,
DEBUG_RID_ERROR => open,
DEBUG_SR_SC_ARADDR => open,
DEBUG_SR_SC_ARADDRCONTROL => open,
DEBUG_SR_SC_AWADDR => open,
DEBUG_SR_SC_AWADDRCONTROL => open,
DEBUG_SR_SC_BRESP => open,
DEBUG_SR_SC_RDATA => open,
DEBUG_SR_SC_RDATACONTROL => open,
DEBUG_SR_SC_WDATA => open,
DEBUG_SR_SC_WDATACONTROL => open,
DEBUG_SC_SF_ARADDR => open,
DEBUG_SC_SF_ARADDRCONTROL => open,
DEBUG_SC_SF_AWADDR => open,
DEBUG_SC_SF_AWADDRCONTROL => open,
DEBUG_SC_SF_BRESP => open,
DEBUG_SC_SF_RDATA => open,
DEBUG_SC_SF_RDATACONTROL => open,
DEBUG_SC_SF_WDATA => open,
DEBUG_SC_SF_WDATACONTROL => open,
DEBUG_SF_CB_ARADDR => open,
DEBUG_SF_CB_ARADDRCONTROL => open,
DEBUG_SF_CB_AWADDR => open,
DEBUG_SF_CB_AWADDRCONTROL => open,
DEBUG_SF_CB_BRESP => open,
DEBUG_SF_CB_RDATA => open,
DEBUG_SF_CB_RDATACONTROL => open,
DEBUG_SF_CB_WDATA => open,
DEBUG_SF_CB_WDATACONTROL => open,
DEBUG_CB_MF_ARADDR => open,
DEBUG_CB_MF_ARADDRCONTROL => open,
DEBUG_CB_MF_AWADDR => open,
DEBUG_CB_MF_AWADDRCONTROL => open,
DEBUG_CB_MF_BRESP => open,
DEBUG_CB_MF_RDATA => open,
DEBUG_CB_MF_RDATACONTROL => open,
DEBUG_CB_MF_WDATA => open,
DEBUG_CB_MF_WDATACONTROL => open,
DEBUG_MF_MC_ARADDR => open,
DEBUG_MF_MC_ARADDRCONTROL => open,
DEBUG_MF_MC_AWADDR => open,
DEBUG_MF_MC_AWADDRCONTROL => open,
DEBUG_MF_MC_BRESP => open,
DEBUG_MF_MC_RDATA => open,
DEBUG_MF_MC_RDATACONTROL => open,
DEBUG_MF_MC_WDATA => open,
DEBUG_MF_MC_WDATACONTROL => open,
DEBUG_MC_MP_ARADDR => open,
DEBUG_MC_MP_ARADDRCONTROL => open,
DEBUG_MC_MP_AWADDR => open,
DEBUG_MC_MP_AWADDRCONTROL => open,
DEBUG_MC_MP_BRESP => open,
DEBUG_MC_MP_RDATA => open,
DEBUG_MC_MP_RDATACONTROL => open,
DEBUG_MC_MP_WDATA => open,
DEBUG_MC_MP_WDATACONTROL => open,
DEBUG_MP_MR_ARADDR => open,
DEBUG_MP_MR_ARADDRCONTROL => open,
DEBUG_MP_MR_AWADDR => open,
DEBUG_MP_MR_AWADDRCONTROL => open,
DEBUG_MP_MR_BRESP => open,
DEBUG_MP_MR_RDATA => open,
DEBUG_MP_MR_RDATACONTROL => open,
DEBUG_MP_MR_WDATA => open,
DEBUG_MP_MR_WDATACONTROL => open
);
RS232_Uart_1 : system_rs232_uart_1_wrapper
port map (
S_AXI_ACLK => pgassign1(4),
S_AXI_ARESETN => axi4lite_0_M_ARESETN(1),
Interrupt => open,
S_AXI_AWADDR => axi4lite_0_M_AWADDR(35 downto 32),
S_AXI_AWVALID => axi4lite_0_M_AWVALID(1),
S_AXI_AWREADY => axi4lite_0_M_AWREADY(1),
S_AXI_WDATA => axi4lite_0_M_WDATA(63 downto 32),
S_AXI_WSTRB => axi4lite_0_M_WSTRB(7 downto 4),
S_AXI_WVALID => axi4lite_0_M_WVALID(1),
S_AXI_WREADY => axi4lite_0_M_WREADY(1),
S_AXI_BRESP => axi4lite_0_M_BRESP(3 downto 2),
S_AXI_BVALID => axi4lite_0_M_BVALID(1),
S_AXI_BREADY => axi4lite_0_M_BREADY(1),
S_AXI_ARADDR => axi4lite_0_M_ARADDR(35 downto 32),
S_AXI_ARVALID => axi4lite_0_M_ARVALID(1),
S_AXI_ARREADY => axi4lite_0_M_ARREADY(1),
S_AXI_RDATA => axi4lite_0_M_RDATA(63 downto 32),
S_AXI_RRESP => axi4lite_0_M_RRESP(3 downto 2),
S_AXI_RVALID => axi4lite_0_M_RVALID(1),
S_AXI_RREADY => axi4lite_0_M_RREADY(1),
RX => RS232_Uart_1_sin,
TX => RS232_Uart_1_sout
);
Push_Buttons_4Bits : system_push_buttons_4bits_wrapper
port map (
S_AXI_ACLK => pgassign1(4),
S_AXI_ARESETN => axi4lite_0_M_ARESETN(2),
S_AXI_AWADDR => axi4lite_0_M_AWADDR(72 downto 64),
S_AXI_AWVALID => axi4lite_0_M_AWVALID(2),
S_AXI_AWREADY => axi4lite_0_M_AWREADY(2),
S_AXI_WDATA => axi4lite_0_M_WDATA(95 downto 64),
S_AXI_WSTRB => axi4lite_0_M_WSTRB(11 downto 8),
S_AXI_WVALID => axi4lite_0_M_WVALID(2),
S_AXI_WREADY => axi4lite_0_M_WREADY(2),
S_AXI_BRESP => axi4lite_0_M_BRESP(5 downto 4),
S_AXI_BVALID => axi4lite_0_M_BVALID(2),
S_AXI_BREADY => axi4lite_0_M_BREADY(2),
S_AXI_ARADDR => axi4lite_0_M_ARADDR(72 downto 64),
S_AXI_ARVALID => axi4lite_0_M_ARVALID(2),
S_AXI_ARREADY => axi4lite_0_M_ARREADY(2),
S_AXI_RDATA => axi4lite_0_M_RDATA(95 downto 64),
S_AXI_RRESP => axi4lite_0_M_RRESP(5 downto 4),
S_AXI_RVALID => axi4lite_0_M_RVALID(2),
S_AXI_RREADY => axi4lite_0_M_RREADY(2),
IP2INTC_Irpt => open,
GPIO_IO_I => Push_Buttons_4Bits_TRI_I(0 to 3),
GPIO_IO_O => open,
GPIO_IO_T => open,
GPIO2_IO_I => net_gnd32(0 to 31),
GPIO2_IO_O => open,
GPIO2_IO_T => open
);
LEDs_8Bits : system_leds_8bits_wrapper
port map (
S_AXI_ACLK => pgassign1(4),
S_AXI_ARESETN => axi4lite_0_M_ARESETN(3),
S_AXI_AWADDR => axi4lite_0_M_AWADDR(104 downto 96),
S_AXI_AWVALID => axi4lite_0_M_AWVALID(3),
S_AXI_AWREADY => axi4lite_0_M_AWREADY(3),
S_AXI_WDATA => axi4lite_0_M_WDATA(127 downto 96),
S_AXI_WSTRB => axi4lite_0_M_WSTRB(15 downto 12),
S_AXI_WVALID => axi4lite_0_M_WVALID(3),
S_AXI_WREADY => axi4lite_0_M_WREADY(3),
S_AXI_BRESP => axi4lite_0_M_BRESP(7 downto 6),
S_AXI_BVALID => axi4lite_0_M_BVALID(3),
S_AXI_BREADY => axi4lite_0_M_BREADY(3),
S_AXI_ARADDR => axi4lite_0_M_ARADDR(104 downto 96),
S_AXI_ARVALID => axi4lite_0_M_ARVALID(3),
S_AXI_ARREADY => axi4lite_0_M_ARREADY(3),
S_AXI_RDATA => axi4lite_0_M_RDATA(127 downto 96),
S_AXI_RRESP => axi4lite_0_M_RRESP(7 downto 6),
S_AXI_RVALID => axi4lite_0_M_RVALID(3),
S_AXI_RREADY => axi4lite_0_M_RREADY(3),
IP2INTC_Irpt => open,
GPIO_IO_I => net_gnd8,
GPIO_IO_O => LEDs_8Bits_TRI_O,
GPIO_IO_T => open,
GPIO2_IO_I => net_gnd32(0 to 31),
GPIO2_IO_O => open,
GPIO2_IO_T => open
);
DIP_Switches_8Bits : system_dip_switches_8bits_wrapper
port map (
S_AXI_ACLK => pgassign1(4),
S_AXI_ARESETN => axi4lite_0_M_ARESETN(4),
S_AXI_AWADDR => axi4lite_0_M_AWADDR(136 downto 128),
S_AXI_AWVALID => axi4lite_0_M_AWVALID(4),
S_AXI_AWREADY => axi4lite_0_M_AWREADY(4),
S_AXI_WDATA => axi4lite_0_M_WDATA(159 downto 128),
S_AXI_WSTRB => axi4lite_0_M_WSTRB(19 downto 16),
S_AXI_WVALID => axi4lite_0_M_WVALID(4),
S_AXI_WREADY => axi4lite_0_M_WREADY(4),
S_AXI_BRESP => axi4lite_0_M_BRESP(9 downto 8),
S_AXI_BVALID => axi4lite_0_M_BVALID(4),
S_AXI_BREADY => axi4lite_0_M_BREADY(4),
S_AXI_ARADDR => axi4lite_0_M_ARADDR(136 downto 128),
S_AXI_ARVALID => axi4lite_0_M_ARVALID(4),
S_AXI_ARREADY => axi4lite_0_M_ARREADY(4),
S_AXI_RDATA => axi4lite_0_M_RDATA(159 downto 128),
S_AXI_RRESP => axi4lite_0_M_RRESP(9 downto 8),
S_AXI_RVALID => axi4lite_0_M_RVALID(4),
S_AXI_RREADY => axi4lite_0_M_RREADY(4),
IP2INTC_Irpt => open,
GPIO_IO_I => DIP_Switches_8Bits_TRI_I,
GPIO_IO_O => open,
GPIO_IO_T => open,
GPIO2_IO_I => net_gnd32(0 to 31),
GPIO2_IO_O => open,
GPIO2_IO_T => open
);
fsl_v20_0 : system_fsl_v20_0_wrapper
port map (
FSL_Clk => pgassign1(4),
SYS_Rst => proc_sys_reset_0_BUS_STRUCT_RESET(0),
FSL_Rst => open,
FSL_M_Clk => net_gnd0,
FSL_M_Data => fsl_v20_0_FSL_M_Data,
FSL_M_Control => fsl_v20_0_FSL_M_Control,
FSL_M_Write => fsl_v20_0_FSL_M_Write,
FSL_M_Full => fsl_v20_0_FSL_M_Full,
FSL_S_Clk => net_gnd0,
FSL_S_Data => fsl_v20_0_FSL_S_Data,
FSL_S_Control => fsl_v20_0_FSL_S_Control,
FSL_S_Read => fsl_v20_0_FSL_S_Read,
FSL_S_Exists => fsl_v20_0_FSL_S_Exists,
FSL_Full => open,
FSL_Has_Data => open,
FSL_Control_IRQ => open
);
fsl_v20_1 : system_fsl_v20_1_wrapper
port map (
FSL_Clk => pgassign1(4),
SYS_Rst => proc_sys_reset_0_BUS_STRUCT_RESET(0),
FSL_Rst => fsl_v20_1_LMB_Rst,
FSL_M_Clk => net_gnd0,
FSL_M_Data => fsl_v20_1_FSL_M_Data,
FSL_M_Control => fsl_v20_1_FSL_M_Control,
FSL_M_Write => fsl_v20_1_FSL_M_Write,
FSL_M_Full => fsl_v20_1_FSL_M_Full,
FSL_S_Clk => net_gnd0,
FSL_S_Data => fsl_v20_1_FSL_S_Data,
FSL_S_Control => fsl_v20_1_FSL_S_Control,
FSL_S_Read => fsl_v20_1_FSL_S_Read,
FSL_S_Exists => fsl_v20_1_FSL_S_Exists,
FSL_Full => open,
FSL_Has_Data => open,
FSL_Control_IRQ => open
);
bajsd_0 : system_bajsd_0_wrapper
port map (
FSL_Clk => pgassign1(4),
FSL_Rst => fsl_v20_1_LMB_Rst,
FSL_S_Clk => net_gnd0,
FSL_S_Read => fsl_v20_0_FSL_S_Read,
FSL_S_Data => fsl_v20_0_FSL_S_Data,
FSL_S_Control => fsl_v20_0_FSL_S_Control,
FSL_S_Exists => fsl_v20_0_FSL_S_Exists,
FSL_M_Clk => net_gnd0,
FSL_M_Write => fsl_v20_1_FSL_M_Write,
FSL_M_Data => fsl_v20_1_FSL_M_Data,
FSL_M_Control => fsl_v20_1_FSL_M_Control,
FSL_M_Full => fsl_v20_1_FSL_M_Full
);
end architecture STRUCTURE;
| mit | 9a455893fd7b426364ac51cdfc86aeb3 | 0.601193 | 2.92555 | false | false | false | false |
tsotnep/vhdl_soc_audio_mixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/axi_i2s_adi_v1_00_a/hdl/vhdl/user_logic.vhd | 3 | 19,765 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
entity user_logic is
generic
(
C_NUM_REG : integer := 12;
C_SLV_DWIDTH : integer := 24;
C_MSB_POS : integer := 0; -- MSB Position in the LRCLK frame (0 - MSB first, 1 - LSB first)
C_FRM_SYNC : integer := 0; -- Frame sync type (0 - 50% Duty Cycle, 1 - Pulse mode)
C_LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge)
C_BCLK_POL : integer := 0 -- BCLK Polarity (0 - Falling edge, 1 - Rising edge)
);
port
(
-- I2S
BCLK_O : out std_logic;
LRCLK_O : out std_logic;
SDATA_I : in std_logic;
SDATA_O : out std_logic;
-- added mem_rd for debugging
MEM_RD_O : out std_logic;
-- AXI4-Lite
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(31 downto 0);
Bus2IP_BE : in std_logic_vector(3 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(31 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic;
-- AXI Streaming interface
S_AXIS_ACLK : in std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_TDATA : in std_logic_vector(31 downto 0);
S_AXIS_TLAST : in std_logic;
S_AXIS_TVALID : in std_logic;
M_AXIS_ACLK : in std_logic;
M_AXIS_TREADY : in std_logic;
M_AXIS_TDATA : out std_logic_vector(31 downto 0);
M_AXIS_TLAST : out std_logic;
M_AXIS_TVALID : out std_logic;
M_AXIS_TKEEP : out std_logic_vector(3 downto 0)
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of S_AXIS_ACLK : signal is "CLK";
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture Behavioral of user_logic is
component i2s_rx_tx is
generic(
C_SLOT_WIDTH : integer := 24;
C_MSB_POS : integer := 0;
C_FRM_SYNC : integer := 0;
C_LRCLK_POL : integer := 0;
C_BCLK_POL : integer := 0
);
port(
CLK_I : in std_logic;
RST_I : in std_logic;
START_TX_I : in std_logic;
START_RX_I : in std_logic;
STOP_RX_I : in std_logic;
DIV_RATE_I : in std_logic_vector(7 downto 0);
LRCLK_RATE_I : in std_logic_vector(7 downto 0);
TX_DATA_I : in std_logic_vector(C_SLOT_WIDTH-1 downto 0);
OE_S_O : out std_logic;
RX_DATA_O : out std_logic_vector(C_SLOT_WIDTH-1 downto 0);
WE_S_O : out std_logic;
BCLK_O : out std_logic;
LRCLK_O : out std_logic;
SDATA_I : in std_logic;
SDATA_O : out std_logic
);
end component;
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal I2S_RST_I : std_logic;
signal I2S_RST_TX_FIFO : std_logic;
signal I2S_RST_RX_FIFO : std_logic;
signal START_TX_I_int : std_logic;
signal START_RX_I_int : std_logic;
signal OE_S_O_int : std_logic;
signal WE_S_O_int : std_logic;
signal RX_DATA_O_int : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal TX_DATA_I_int : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal mem_rd : std_logic;
signal mem_rd_d1 : std_logic;
signal sample_wr : std_logic;
signal sample_wr_d1 : std_logic;
signal period_cnt : integer range 0 to 65535;
signal period_cnt2 : integer range 0 to 65535;
signal I2S_RESET_REG : std_logic_vector(31 downto 0);
signal I2S_CONTROL_REG : std_logic_vector(31 downto 0);
signal I2S_CLK_CONTROL_REG : std_logic_vector(31 downto 0);
signal I2S_STATUS_REG : std_logic_vector(31 downto 0);
signal DIV_RATE_REG : std_logic_vector(7 downto 0);
signal LRCLK_RATE_REG : std_logic_vector(7 downto 0);
signal I2S_NR_CHAN_REG : std_logic_vector(31 downto 0);
signal PERIOD_CNT_REG : std_logic_vector(31 downto 0);
signal slv_reg7 : std_logic_vector(31 downto 0);
signal slv_reg4 : std_logic_vector(31 downto 0);
signal slv_reg8 : std_logic_vector(31 downto 0);
signal slv_reg9 : std_logic_vector(31 downto 0);
signal I2S_REG10 : std_logic_vector(31 downto 0);
signal I2S_REG11 : std_logic_vector(31 downto 0);
signal slv_reg_write_sel : std_logic_vector(11 downto 0);
signal slv_reg_read_sel : std_logic_vector(11 downto 0);
signal slv_ip2bus_data : std_logic_vector(31 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
-- Audio samples FIFO
constant RAM_ADDR_WIDTH : integer := 7;
type RAM_TYPE is array (0 to (2**RAM_ADDR_WIDTH - 1)) of std_logic_vector(31 downto 0);
-- TX FIFO signals
signal audio_fifo_tx : RAM_TYPE;
signal audio_fifo_tx_wr_addr : integer range 0 to 2**RAM_ADDR_WIDTH-1;
signal audio_fifo_tx_rd_addr : integer range 0 to 2**RAM_ADDR_WIDTH-1;
signal audio_fifo_tx_full : std_logic;
signal audio_fifo_tx_empty : std_logic;
-- RX FIFO signals
signal audio_fifo_rx : RAM_TYPE;
signal audio_fifo_rx_wr_addr : integer range 0 to 2**RAM_ADDR_WIDTH-1;
signal audio_fifo_rx_rd_addr : integer range 0 to 2**RAM_ADDR_WIDTH-1;
signal tvalid : std_logic := '0';
signal rx_tlast : std_logic;
signal drain_tx_dma : std_logic;
begin
drain_process: process (Bus2IP_Clk) is
variable START_TX_I_int_d1 : std_logic;
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
drain_tx_dma <= '0';
else
if S_AXIS_TLAST = '1' then
drain_tx_dma <= '0';
elsif START_TX_I_int_d1 = '1' and START_TX_I_int = '0' then
drain_tx_dma <= '1';
end if;
START_TX_I_int_d1 := START_TX_I_int;
end if;
end if;
end process;
-- Audio FIFO samples management
-- TX FIFO
S_AXIS_TREADY <= '1' when (audio_fifo_tx_full = '0' or drain_tx_dma = '1') else '0';
mem_rd <= OE_S_O_int;
-- MEM_RD_O for debugging
MEM_RD_O <= mem_rd;
--
AUDIO_FIFO_TX_PROCESS : process(S_AXIS_ACLK) is
variable audio_fifo_free_cnt : integer range 0 to 2**RAM_ADDR_WIDTH;
begin
if(S_AXIS_ACLK'event and S_AXIS_ACLK = '1') then
if(Bus2IP_Resetn = '0') then
audio_fifo_tx_wr_addr <= 0;
audio_fifo_tx_rd_addr <= 0;
audio_fifo_free_cnt := 2**RAM_ADDR_WIDTH;
audio_fifo_tx_full <= '0';
audio_fifo_tx_empty <= '1';
mem_rd_d1 <= '0';
elsif(I2S_RST_TX_FIFO = '1') then
-- Fill TX FIFO with zeros
for i in 0 to (2**RAM_ADDR_WIDTH - 1) loop
audio_fifo_tx(conv_integer(i)) <= (others => '0');
end loop;
-- Reset FIFO counters
audio_fifo_tx_wr_addr <= 0;
audio_fifo_tx_rd_addr <= 0;
audio_fifo_free_cnt := 2**RAM_ADDR_WIDTH;
audio_fifo_tx_full <= '0';
audio_fifo_tx_empty <= '1';
mem_rd_d1 <= '0';
else
mem_rd_d1 <= mem_rd;
if((S_AXIS_TVALID = '1')and(audio_fifo_free_cnt > 0)) then
audio_fifo_tx(audio_fifo_tx_wr_addr) <= S_AXIS_TDATA;
audio_fifo_tx_wr_addr <= audio_fifo_tx_wr_addr + 1;
audio_fifo_free_cnt := audio_fifo_free_cnt - 1;
end if;
if(((mem_rd_d1 = '1')and(mem_rd = '0'))and(audio_fifo_free_cnt < (2**RAM_ADDR_WIDTH))) then
audio_fifo_tx_rd_addr <= audio_fifo_tx_rd_addr + 1;
audio_fifo_free_cnt := audio_fifo_free_cnt + 1;
end if;
if(audio_fifo_free_cnt = 0) then
audio_fifo_tx_full <= '1';
else
audio_fifo_tx_full <= '0';
end if;
if(audio_fifo_free_cnt = 2**RAM_ADDR_WIDTH) then
audio_fifo_tx_empty <= '1';
else
audio_fifo_tx_empty <= '0';
end if;
--TX_DATA_I_int(C_SLV_DWIDTH-1 downto 0) <= audio_fifo_tx(audio_fifo_tx_rd_addr)(C_SLV_DWIDTH-1 downto 0);
TX_DATA_I_int(C_SLV_DWIDTH-1 downto 0) <= audio_fifo_tx(audio_fifo_tx_rd_addr)(31 downto 32-C_SLV_DWIDTH);
end if;
end if;
end process AUDIO_FIFO_TX_PROCESS;
-- RX FIFO
sample_wr <= WE_S_O_int;
AUDIO_FIFO_RX_PROCESS: process(M_AXIS_ACLK) is
variable data_cnt : integer range 0 to 2**RAM_ADDR_WIDTH-1;
begin
if(M_AXIS_ACLK'event and M_AXIS_ACLK = '1') then
if(Bus2IP_Resetn = '0') then
audio_fifo_rx_wr_addr <= 0;
audio_fifo_rx_rd_addr <= 0;
data_cnt := 0;
elsif(I2S_RST_RX_FIFO = '1') then
-- Fill TX FIFO with zeros
for i in 0 to (2**RAM_ADDR_WIDTH - 1) loop
audio_fifo_rx(conv_integer(i)) <= (others => '0');
end loop;
-- Reset FIFO counters
audio_fifo_rx_wr_addr <= 0;
audio_fifo_rx_rd_addr <= 0;
data_cnt := 0;
else
sample_wr_d1 <= sample_wr;
if((sample_wr_d1 = '0')and(sample_wr = '1')) then
audio_fifo_rx(audio_fifo_rx_wr_addr) <= RX_DATA_O_int & "00000000";
--audio_fifo_rx(audio_fifo_rx_wr_addr) <= "0" & RX_DATA_O_int & "0000000";
audio_fifo_rx_wr_addr <= audio_fifo_rx_wr_addr + 1;
if(data_cnt < (2**RAM_ADDR_WIDTH - 1)) then
data_cnt := data_cnt + 1;
end if;
end if;
if((tvalid = '1')and(M_AXIS_TREADY = '1')) then
audio_fifo_rx_rd_addr <= audio_fifo_rx_rd_addr + 1;
data_cnt := data_cnt - 1;
-- Added counter
if(period_cnt2 = 0) then
period_cnt2 <= period_cnt;
rx_tlast <= '1';
else
period_cnt2 <= period_cnt2 - 1;
rx_tlast <= '0';
end if;
end if;
if(data_cnt > 0) then
tvalid <= '1';
else
tvalid <= '0';
end if;
end if;
end if;
end process AUDIO_FIFO_RX_PROCESS;
M_AXIS_TDATA <= audio_fifo_rx(audio_fifo_rx_rd_addr);
M_AXIS_TVALID <= tvalid;
M_AXIS_TLAST <= rx_tlast;
M_AXIS_TKEEP <= "1111";
Inst_I2sCtl: i2s_rx_tx
generic map(
C_SLOT_WIDTH => C_SLV_DWIDTH,
C_MSB_POS => C_MSB_POS,
C_FRM_SYNC => C_FRM_SYNC,
C_LRCLK_POL => C_LRCLK_POL,
C_BCLK_POL => C_BCLK_POL
)
port map(
CLK_I => Bus2IP_Clk,
RST_I => I2S_RST_I,
START_TX_I => START_TX_I_int,
START_RX_I => START_RX_I_int,
STOP_RX_I => rx_tlast,
DIV_RATE_I => DIV_RATE_REG,
LRCLK_RATE_I => LRCLK_RATE_REG,
TX_DATA_I => TX_DATA_I_int,
OE_S_O => OE_S_O_int,
WE_S_O => WE_S_O_int,
RX_DATA_O => RX_DATA_O_int,
BCLK_O => BCLK_O,
LRCLK_O => LRCLK_O,
SDATA_I => SDATA_I,
SDATA_O => SDATA_O
);
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(11 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(11 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4) or Bus2IP_RdCE(5) or Bus2IP_RdCE(6) or Bus2IP_RdCE(7) or Bus2IP_RdCE(8) or Bus2IP_RdCE(9) or Bus2IP_RdCE(10) or Bus2IP_RdCE(11);
I2S_RST_I <= I2S_RESET_REG(0);
I2S_RST_TX_FIFO <= I2S_RESET_REG(1);
I2S_RST_RX_FIFO <= I2S_RESET_REG(2);
START_TX_I_int <= I2S_CONTROL_REG(0);
START_RX_I_int <= I2S_CONTROL_REG(1);
DIV_RATE_REG <= I2S_CLK_CONTROL_REG(7 downto 0);
LRCLK_RATE_REG <= I2S_CLK_CONTROL_REG(23 downto 16);
period_cnt <= conv_integer(PERIOD_CNT_REG);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
I2S_RESET_REG <= (others => '0');
I2S_CONTROL_REG <= (others => '0');
I2S_CLK_CONTROL_REG <= (others => '0');
I2S_STATUS_REG <= (others => '0');
I2S_NR_CHAN_REG <= (others => '0');
PERIOD_CNT_REG <= (others => '0');
slv_reg7 <= (others => '0');
slv_reg8 <= (others => '0');
slv_reg9 <= (others => '0');
I2S_REG10 <= (others => '0');
I2S_REG11 <= (others => '0');
else
-- Auto-clear the Reset Register bits
I2S_RESET_REG(0) <= '0';
I2S_RESET_REG(1) <= '0';
I2S_RESET_REG(2) <= '0';
case slv_reg_write_sel is
when "100000000000" => -- 0x00 RESET
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
I2S_RESET_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "010000000000" => -- 0x04 CONTROL
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
I2S_CONTROL_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "001000000000" => -- 0x08 CLOCK CONTROL
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
I2S_CLK_CONTROL_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "000100000000" => -- 0x0C RESERVED
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg4(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "000010000000" => -- 0x10 STATUS
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
I2S_STATUS_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "000001000000" => -- 0x14 NR CHANNELS REG
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
I2S_NR_CHAN_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "000000100000" => -- 0x18 PERIOD_CNT_REG
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
PERIOD_CNT_REG(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "000000010000" => -- 0x1C
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg7(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "000000001000" => -- 0x20
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg8(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "000000000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg9(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "000000000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
I2S_REG10(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "000000000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
I2S_REG11(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
--LRCLK_RATE_REG(31 downto 0) <= RX_DATA_O_int & "00000000";
I2S_STATUS_REG(0) <= OE_S_O_int;
I2S_STATUS_REG(1) <= WE_S_O_int;
I2S_STATUS_REG(2) <= audio_fifo_tx_full;
I2S_STATUS_REG(3) <= audio_fifo_tx_empty;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, I2S_RESET_REG, I2S_CONTROL_REG, I2S_STATUS_REG, DIV_RATE_REG, LRCLK_RATE_REG, I2S_NR_CHAN_REG, PERIOD_CNT_REG, slv_reg7, slv_reg8, slv_reg9, I2S_REG10, I2S_REG11 ) is
begin
case slv_reg_read_sel is
when "100000000000" => slv_ip2bus_data <= I2S_RESET_REG;
when "010000000000" => slv_ip2bus_data <= I2S_CONTROL_REG;
when "001000000000" => slv_ip2bus_data <= I2S_CLK_CONTROL_REG;
when "000100000000" => slv_ip2bus_data <= slv_reg4;
when "000010000000" => slv_ip2bus_data <= I2S_STATUS_REG;
when "000001000000" => slv_ip2bus_data <= I2S_NR_CHAN_REG;
when "000000100000" => slv_ip2bus_data <= PERIOD_CNT_REG;
when "000000010000" => slv_ip2bus_data <= slv_reg7;
when "000000001000" => slv_ip2bus_data <= slv_reg8;
when "000000000100" => slv_ip2bus_data <= slv_reg9;
when "000000000010" => slv_ip2bus_data <= I2S_REG10;
when "000000000001" => slv_ip2bus_data <= I2S_REG11;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end Behavioral;
| mit | d20ae48325d1c9e4a8776453ad7fcf53 | 0.526587 | 2.982496 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/readout/select_data.vhd | 1 | 4,893 | ----------------------------------------------------------------------------------
-- Company: NTU ATHNENS - BNL
-- Engineer: Panagiotis Gkountoumis
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Panagiotis Gkountoumis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 18.04.2016 13:00:21
-- Design Name:
-- Module Name: config_logic - Behavioral
-- Project Name: MMFE8
-- Target Devices: Arix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2016.2
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Chandelog:
-- 19.07.2016 Reverted component to work asynchronously (Reid Pinkham)
-- 20.07.2016 Changed packet length from integer to std_logic_vector (Reid Pinkham)
-- 04.08.2016 Added XADC support (Reid Pinkham)
----------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity select_data is
port(
configuring : in std_logic;
data_acq : in std_logic;
xadc : in std_logic;
we_data : in std_logic;
we_conf : in std_logic;
we_xadc : in std_logic;
daq_data_in : in std_logic_vector(15 downto 0);
conf_data_in : in std_logic_vector(15 downto 0);
xadc_data_in : in std_logic_vector(15 downto 0);
data_packet_length : in std_logic_vector(11 downto 0);
xadc_packet_length : in std_logic_vector(11 downto 0);
conf_packet_length : in std_logic_vector(11 downto 0);
end_packet_conf : in std_logic;
end_packet_daq : in std_logic;
end_packet_xadc : in std_logic;
fifo_rst_daq : in std_logic;
fifo_rst_xadc : in std_logic;
rstFIFO_top : in std_logic;
data_out : out std_logic_vector(15 downto 0);
packet_length : out std_logic_vector(11 downto 0);
we : out std_logic;
end_packet : out std_logic;
fifo_rst : out std_logic
);
end select_data;
architecture Behavioral of select_data is
signal sel : std_logic_vector(2 downto 0);
signal fifo_rst_i : std_logic;
begin
data_selection: process(configuring, data_acq, xadc, we_conf, conf_data_in, conf_packet_length, end_packet_conf,
we_data, daq_data_in, data_packet_length, end_packet_daq, fifo_rst_daq,
we_xadc, xadc_data_in, xadc_packet_length, end_packet_xadc, fifo_rst_xadc)
begin
sel <= configuring & data_acq & xadc;
case sel is
when "100" => -- Configuration
we <= we_conf;
data_out <= conf_data_in;
packet_length <= conf_packet_length;
end_packet <= end_packet_conf;
fifo_rst_i <= '0';
when "010" => -- DAQ
we <= we_data;
data_out <= daq_data_in;
packet_length <= data_packet_length;
end_packet <= end_packet_daq;
fifo_rst_i <= fifo_rst_daq;
when "001" => -- XADC
we <= we_xadc;
data_out <= xadc_data_in;
packet_length <= xadc_packet_length;
end_packet <= end_packet_xadc;
fifo_rst_i <= fifo_rst_xadc;
when others =>
we <= '0';
data_out <= (others => '0');
packet_length <= x"000";
end_packet <= '0';
fifo_rst_i <= '0';
end case;
end process;
fifo_rst <= fifo_rst_i or rstFIFO_top; -- top reset always will work
end Behavioral;
| gpl-3.0 | 3d3bca9009f6e3ac4815cf191403a1e0 | 0.52708 | 3.883333 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/configuration/skew_gen.vhd | 1 | 7,606 | ----------------------------------------------------------------------------------
-- Company: NTU Athens - BNL
-- Engineer: Christos Bakalis ([email protected])
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Christos Bakalis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 20.02.2017 18:41:18
-- Design Name:
-- Module Name: skew_gen - RTL
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description: Skewing module. Receives a CKTP aligned with the CKBC, and shifts
-- CKTP with a 500 Mhz clock in progressive stages (2 ns step size). Measurements
-- show that the first 2-3 delay stages may give unstable results. The rest stages
-- are all close to the theoretical values.
--
-- Dependencies: "Configurable CKBC/CKTP Constraints" .xdc snippet must be added to
-- the main .xdc file of the design. Can be found at the project repository.
--
-- Changelog:
-- 23.02.2017 Slowed down the skewing process to 500 Mhz. (Christos Bakalis)
-- 04.07.2017 Added delay levels to introduce skewing step-size of 1ns.
-- (Christos Bakalis)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity skew_gen is
Port(
clk_500 : in std_logic;
CKTP_preSkew : in std_logic;
skew : in std_logic_vector(4 downto 0);
CKTP_skewed : out std_logic
);
end skew_gen;
architecture RTL of skew_gen is
signal cktp_02 : std_logic := '0';
signal cktp_04 : std_logic := '0';
signal cktp_06 : std_logic := '0';
signal cktp_08 : std_logic := '0';
signal cktp_10 : std_logic := '0';
signal cktp_12 : std_logic := '0';
signal cktp_14 : std_logic := '0';
signal cktp_16 : std_logic := '0';
signal cktp_18 : std_logic := '0';
signal cktp_20 : std_logic := '0';
signal cktp_22 : std_logic := '0';
signal cktp_24 : std_logic := '0';
signal cktp_26 : std_logic := '0';
signal cktp_28 : std_logic := '0';
signal cktp_30 : std_logic := '0';
signal cktp_32 : std_logic := '0';
signal cktp_34 : std_logic := '0';
signal cktp_36 : std_logic := '0';
signal cktp_38 : std_logic := '0';
signal cktp_40 : std_logic := '0';
signal cktp_42 : std_logic := '0';
signal cktp_44 : std_logic := '0';
signal cktp_46 : std_logic := '0';
signal skew_i : std_logic_vector(4 downto 0) := (others => '0');
signal CKTP_internal : std_logic := '0';
begin
-- skew conversion
conv_skew_proc: process(skew)
begin
case skew is
when "00001" => skew_i <= "01101"; -- 1 ns
when "00010" => skew_i <= "00001"; -- 2 ns
when "00011" => skew_i <= "01110"; -- 3 ns
when "00100" => skew_i <= "00010"; -- 4 ns
when "00101" => skew_i <= "01111"; -- 5 ns
when "00110" => skew_i <= "00011"; -- 6 ns
when "00111" => skew_i <= "10000"; -- 7 ns
when "01000" => skew_i <= "00100"; -- 8 ns
when "01001" => skew_i <= "10001"; -- 9 ns
when "01010" => skew_i <= "00101"; -- 10 ns
when "01011" => skew_i <= "10010"; -- 11 ns
when "01100" => skew_i <= "00110"; -- 12 ns
when "01101" => skew_i <= "10011"; -- 13 ns
when "01110" => skew_i <= "00111"; -- 14 ns
when "01111" => skew_i <= "10100"; -- 15 ns
when "10000" => skew_i <= "01000"; -- 16 ns
when "10001" => skew_i <= "10101"; -- 17 ns
when "10010" => skew_i <= "01001"; -- 18 ns
when "10011" => skew_i <= "10110"; -- 19 ns
when "10100" => skew_i <= "01010"; -- 20 ns
when "10101" => skew_i <= "10111"; -- 21 ns
when "10110" => skew_i <= "01011"; -- 22 ns
when "10111" => skew_i <= "11000"; -- 23 ns
when "11000" => skew_i <= "01100"; -- 24 ns
when others => skew_i <= "00001"; -- 2 ns
end case;
end process;
-- select CKTP skewing
sel_skew_proc: process(skew_i, CKTP_preSkew, cktp_02, cktp_04, cktp_06, cktp_08,
cktp_10, cktp_12, cktp_14, cktp_16, cktp_18, cktp_20, cktp_22,
cktp_24, cktp_26, cktp_28, cktp_30, cktp_32, cktp_34, cktp_36,
cktp_38, cktp_40, cktp_42, cktp_44, cktp_46)
begin
case skew_i is
when "00001" => CKTP_internal <= CKTP_preSkew; -- 02 ns (1) (one extra reg at the end)
when "00010" => CKTP_internal <= cktp_02; -- 04 ns (2)
when "00011" => CKTP_internal <= cktp_04; -- 06 ns (3)
when "00100" => CKTP_internal <= cktp_06; -- 08 ns (4)
when "00101" => CKTP_internal <= cktp_08; -- 10 ns (5)
when "00110" => CKTP_internal <= cktp_10; -- 12 ns (6)
when "00111" => CKTP_internal <= cktp_12; -- 14 ns (7)
when "01000" => CKTP_internal <= cktp_14; -- 16 ns (8)
when "01001" => CKTP_internal <= cktp_16; -- 18 ns (9)
when "01010" => CKTP_internal <= cktp_18; -- 20 ns (10)
when "01011" => CKTP_internal <= cktp_20; -- 22 ns (11)
when "01100" => CKTP_internal <= cktp_22; -- 24 ns (12)
when "01101" => CKTP_internal <= cktp_24; -- 26 ns (13) 1 ns (rolled over)
when "01110" => CKTP_internal <= cktp_26; -- 28 ns (14) 3 ns
when "01111" => CKTP_internal <= cktp_28; -- 30 ns (15) 5 ns
when "10000" => CKTP_internal <= cktp_30; -- 32 ns (16) 7 ns
when "10001" => CKTP_internal <= cktp_32; -- 34 ns (17) 9 ns
when "10010" => CKTP_internal <= cktp_34; -- 36 ns (18) 11 ns
when "10011" => CKTP_internal <= cktp_36; -- 38 ns (19) 13 ns
when "10100" => CKTP_internal <= cktp_38; -- 40 ns (20) 15 ns
when "10101" => CKTP_internal <= cktp_40; -- 42 ns (21) 17 ns
when "10110" => CKTP_internal <= cktp_42; -- 44 ns (22) 19 ns
when "10111" => CKTP_internal <= cktp_44; -- 46 ns (23) 21 ns
when "11000" => CKTP_internal <= cktp_46; -- 48 ns (24) 23 ns
when others => CKTP_internal <= CKTP_preSkew; -- 02 ns
end case;
end process;
-- delay/skewing line
reg_cktp_proc: process(clk_500)
begin
if(rising_edge(clk_500))then
cktp_02 <= CKTP_preSkew;
cktp_04 <= cktp_02;
cktp_06 <= cktp_04;
cktp_08 <= cktp_06;
cktp_10 <= cktp_08;
cktp_12 <= cktp_10;
cktp_14 <= cktp_12;
cktp_16 <= cktp_14;
cktp_18 <= cktp_16;
cktp_20 <= cktp_18;
cktp_22 <= cktp_20;
cktp_24 <= cktp_22;
cktp_26 <= cktp_24;
cktp_28 <= cktp_26;
cktp_30 <= cktp_28;
cktp_32 <= cktp_30;
cktp_34 <= cktp_32;
cktp_36 <= cktp_34;
cktp_38 <= cktp_36;
cktp_40 <= cktp_38;
cktp_42 <= cktp_40;
cktp_44 <= cktp_42;
cktp_46 <= cktp_44;
end if;
end process;
-- CKTP is registered one final time to optimize timing
regCKTP: process(clk_500)
begin
if(rising_edge(clk_500))then
CKTP_skewed <= CKTP_internal;
end if;
end process;
end RTL;
| gpl-3.0 | a3f066eec839930f75c9e59979b02d94 | 0.554431 | 3.2546 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/MMFE8_1VMM/sources_1/readout/vmm_readout.vhd | 1 | 12,398 | ----------------------------------------------------------------------------------
-- Company: NTU ATHNENS - BNL
-- Engineer: Paris Moschovakos
--
-- Create Date: 18.04.2016 13:00:21
-- Design Name:
-- Module Name: vmm_readout.vhd - Behavioral
-- Project Name: MMFE8
-- Target Devices: Arix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2016.2
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 1.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity vmm_readout is
Port (
vmm_data0 : in std_logic; -- Single-ended data0 from VMM
vmm_data1 : in std_logic; -- Single-ended data1 from VMM
clk_10_phase45 : in std_logic; -- Used to clock checking for data process
clk_50 : in std_logic; -- Used to clock word readout process
clk_200 : in std_logic; -- Used for fast ILA signal sampling
daq_enable : in std_logic;
trigger_pulse : in std_logic; -- To be used trigger
ethernet_fifo_wr_en : out std_logic; -- To be used to for ethernet to software readout
latency : in std_logic_vector(15 downto 0);
vmm_ckdt : out std_logic; -- Strobe to VMM CKDT
vmm_cktk : out std_logic; -- Strobe to VMM CKTK
acq_rst_from_data0 : out std_logic; -- Send a soft reset when done
vmm_data_buf : buffer std_logic_vector(37 downto 0);
vmm_wen : out std_logic;
vmm_ena : out std_logic;
vmmWordReady : out std_logic;
vmmWord : out std_logic_vector(63 downto 0);
vmmEventDone : out std_logic
);
end vmm_readout;
architecture Behavioral of vmm_readout is
-- readoutControlProc
signal reading_out_word : std_logic := '0';
-- tokenProc
signal dt_state : std_logic_vector( 3 DOWNTO 0 ) := ( others => '0' );
signal vmm_wen_1_i : std_logic := '0';
signal vmm_ena_1_i : std_logic := '0';
signal vmm_cktk_1_i : std_logic := '0';
signal ethernet_fifo_wr_en_i: std_logic := '0'; -- Not used
-- signal trig_latency_counter : std_logic_vector( 15 DOWNTO 0 ) := ( others => '0' );
-- signal trig_latency : std_logic_vector( 15 DOWNTO 0 ) := x"008C"; -- x"008C"; 700ns @200MHz (User defined)
signal latency_i : integer := 7;
signal latencyCnt : integer := 0;
signal NoFlg_counter : integer := 0; -- Counter of CKTKs
signal NoFlg : integer := 2; -- How many (#+1) CKTKs before soft reset (User defined)
signal vmmEventDone_i : std_logic := '0';
signal trigger_pulse_i : std_logic := '0';
signal hitsLen_cnt : integer := 0;
signal hitsLenMax : integer := 150;
-- readoutProc
signal dt_done : std_logic := '1';
signal vmm_data_buf_i : std_logic_vector( 37 DOWNTO 0 ) := ( others => '0' );
signal dt_cntr_intg : integer := 0;
signal dt_cntr_intg0 : integer := 0;
signal dt_cntr_intg1 : integer := 0;
signal vmm_ckdt_1_i : std_logic;
signal dataBitRead : integer := 0;
signal vmmWordReady_i : std_logic := '0';
signal vmmWord_i : std_logic_vector(63 DOWNTO 0);
-- Internal signal direct assign from ports
signal vmm_data0_i : std_logic := '0';
signal vmm_data1_i : std_logic := '0';
signal daq_enable_i : std_logic := '0';
begin
readoutControlProc: process(clk_200, daq_enable_i, dt_done, vmm_data0_i)
begin
if (dt_done = '1') then
reading_out_word <= '0'; -- readoutProc done, stop it
end if;
if (vmm_data0_i = '1') then
reading_out_word <= '1'; -- new data, trigger readoutProc
end if;
end process;
-- by using this clock the CKTK strobe has f=5MHz (T=200ns, D=50%, phase=45deg)
tokenProc: process(clk_10_phase45, daq_enable_i, dt_done, vmm_data0_i, trigger_pulse)
begin
if (rising_edge(clk_10_phase45)) then
if (daq_enable_i = '1') then
case dt_state is
when x"0" =>
vmmEventDone_i <= '0';
vmm_wen_1_i <= '0';
vmm_ena_1_i <= '1';
latencyCnt <= 0;
if (trigger_pulse_i = '1') then
vmm_cktk_1_i <= '0';
ethernet_fifo_wr_en_i <= '0';
dt_state <= x"1";
end if;
when x"1" =>
if (latencyCnt = latency_i) then
dt_state <= x"2";
else
latencyCnt <= latencyCnt + 1;
end if;
when x"2" =>
vmm_cktk_1_i <= '0';
dt_state <= x"3";
when x"3" =>
if (reading_out_word /= '1') then
vmm_cktk_1_i <= '1';
hitsLen_cnt <= hitsLen_cnt + 1;
dt_state <= x"4";
else
NoFlg_counter <= 0;
dt_state <= x"6";
end if;
when x"4" =>
vmm_cktk_1_i <= '0';
dt_state <= x"5";
when x"5" =>
if (vmm_data0_i = '1') then -- Data presence: wait to read out
NoFlg_counter <= 0;
dt_state <= x"6";
else
if (NoFlg_counter = NoFlg) then
dt_state <= x"7"; -- If NoFlg = 4 : time to soft reset and transmit data
else
dt_state <= x"3"; -- Send new CKTK strobe
end if;
NoFlg_counter <= NoFlg_counter + 1;
end if;
when x"6" => -- Wait until word readout is done
if (dt_done = '1') then
if hitsLen_cnt >= hitsLenMax then -- Maximum UDP packet length reached
dt_state <= x"7";
else
dt_state <= x"3"; -- Issue new CKTK strobe
end if;
end if;
when x"7" => -- Start the soft reset sequence, there is still a chance
if (reading_out_word /= '1') then -- of getting data at this point so check that before soft reset
vmm_wen_1_i <= '0';
vmm_ena_1_i <= '0';
dt_state <= x"8";
else
NoFlg_counter <= 0;
dt_state <= x"6";
end if;
when x"8" =>
vmm_wen_1_i <= '1';
vmm_ena_1_i <= '0';
hitsLen_cnt <= 0;
dt_state <= x"9";
when others =>
vmmEventDone_i <= '1';
vmm_wen_1_i <= '0';
vmm_ena_1_i <= '0';
NoFlg_counter <= 0;
ethernet_fifo_wr_en_i <= '1';
dt_state <= x"0";
end case;
else
vmm_ena_1_i <= '0';
vmm_wen_1_i <= '0';
end if;
end if;
end process;
-- by using this clock the CKDT strobe has f=25MHz (T=40ns, D=50%, phase=0deg) to click in data0 and data1
readoutProc: process(clk_50, reading_out_word)
begin
if rising_edge(clk_50) then
if (reading_out_word = '1') then
case dt_cntr_intg is
when 0 => -- Initiate values
dt_done <= '0';
vmm_data_buf <= (others => '0');
dt_cntr_intg <= dt_cntr_intg + 1;
dt_cntr_intg0 <= 0;
dt_cntr_intg1 <= 1;
vmm_ckdt_1_i <= '0'; -- Go for the first ckdt
when 1 =>
vmm_ckdt_1_i <= '1';
dt_cntr_intg <= dt_cntr_intg + 1;
when 2 => -- 19 ckdt and collect data
vmm_ckdt_1_i <= '0';
if (dataBitRead /= 19) then
vmm_data_buf(dt_cntr_intg0) <= vmm_data0;
vmm_data_buf(dt_cntr_intg1) <= vmm_data1;
vmm_data_buf_i <= vmm_data_buf;
dt_cntr_intg <= 1;
dataBitRead <= dataBitRead + 1;
else
vmm_data_buf(dt_cntr_intg0) <= vmm_data0;
vmm_data_buf(dt_cntr_intg1) <= vmm_data1;
vmm_data_buf_i <= vmm_data_buf;
dataBitRead <= 1;
dt_cntr_intg <= 3;
end if;
dt_cntr_intg0 <= dt_cntr_intg0 + 2;
dt_cntr_intg1 <= dt_cntr_intg1 + 2;
when 3 =>
vmmWordReady_i <= '0';
-- daqFIFO_din_i <= b"000" & b"111" & vmm_data_buf(25 downto 0) & b"0000" & b"1010101010101010" & vmm_data_buf(37 downto 26);
vmmWord_i <= b"00" & vmm_data_buf(25 downto 18) & vmm_data_buf(37 downto 26) & vmm_data_buf(17 downto 8) & b"000000000000000000000000" & vmm_data_buf(7 downto 2) & vmm_data_buf(1) & vmm_data_buf(0);
-- TDO & Gray & PDO & & Address & Threshold & Flag;
dt_cntr_intg <= dt_cntr_intg + 1;
when 4 =>
vmmWordReady_i <= '1';
dt_cntr_intg <= dt_cntr_intg + 1;
when others => -- Word read
dt_cntr_intg0 <= 0;
dt_cntr_intg1 <= 1;
dt_cntr_intg <= 0;
vmmWordReady_i <= '0';
dt_done <= '1';
end case;
else
dt_cntr_intg0 <= 0;
dt_cntr_intg1 <= 1;
dt_cntr_intg <= 0;
end if;
end if;
end process;
vmm_cktk <= vmm_cktk_1_i; -- Used
vmm_ckdt <= vmm_ckdt_1_i; -- Used
vmm_wen <= vmm_wen_1_i; -- Used
vmm_ena <= vmm_ena_1_i; -- Used
daq_enable_i <= daq_enable; -- Used
vmm_data0_i <= vmm_data0; -- Used
vmm_data1_i <= vmm_data1; -- Used
vmmWordReady <= vmmWordReady_i; -- Used
vmmWord <= vmmWord_i; -- Used
vmmEventDone <= vmmEventDone_i; -- Used
trigger_pulse_i <= trigger_pulse; -- Used
latency_i <= to_integer(unsigned(latency));
end behavioral; | gpl-3.0 | c6561754197ccda88a244c338eccefa1 | 0.393854 | 4.121676 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/configuration/clk_gen_wrapper.vhd | 1 | 8,534 | ----------------------------------------------------------------------------------
-- Company: NTU Athens - BNL
-- Engineer: Christos Bakalis ([email protected])
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Christos Bakalis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 19.02.2017 12:07:30
-- Design Name:
-- Module Name: clk_gen_wrapper - RTL
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description: Wrapper that contains the CKTP and CKBC generators. It also
-- instantiates a skewing module with 2 ns resolution. See skew_gen for more
-- information.
--
-- Dependencies: "Configurable CKBC/CKTP Constraints" .xdc snippet must be added to
-- the main .xdc file of the design. Can be found at the project repository.
--
-- Changelog:
-- 23.02.2017 Slowed down the skewing process to 500 Mhz. (Christos Bakalis)
-- 09.03.2017 Shortened the bus widths and added conversion multipliers for
-- area usage optimization. (Christos Bakalis)
-- 26.03.2017 Added CKTP counting module. (Christos Bakalis)
--
----------------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
use UNISIM.VComponents.all;
entity clk_gen_wrapper is
Port(
------------------------------------
------- General Interface ----------
clk_500 : in std_logic;
clk_160 : in std_logic;
clk_125 : in std_logic;
rst : in std_logic;
mmcm_locked : in std_logic;
CKTP_raw : out std_logic;
------------------------------------
----- Configuration Interface ------
cktp_enable : in std_logic;
cktp_primary : in std_logic;
readout_mode : in std_logic;
enable_ro_ckbc : in std_logic;
cktp_pulse_width : in std_logic_vector(4 downto 0);
cktp_max_num : in std_logic_vector(15 downto 0);
cktp_period : in std_logic_vector(15 downto 0);
cktp_skew : in std_logic_vector(4 downto 0);
ckbc_freq : in std_logic_vector(5 downto 0);
ckbc_max_num : in std_logic_vector(7 downto 0);
------------------------------------
---------- VMM Interface -----------
CKTP : out std_logic;
CKBC : out std_logic
);
end clk_gen_wrapper;
architecture RTL of clk_gen_wrapper is
component cktp_gen
port(
clk_160 : in std_logic;
cktp_start : in std_logic;
vmm_ckbc : in std_logic; -- CKBC clock currently dynamic
cktp_primary : in std_logic;
ckbc_mode : in std_logic;
ckbc_freq : in std_logic_vector(5 downto 0);
skew : in std_logic_vector(4 downto 0);
pulse_width : in std_logic_vector(11 downto 0);
period : in std_logic_vector(21 downto 0);
CKTP : out std_logic
);
end component;
component cktp_counter
port(
clk_160 : in std_logic;
cktp_start : in std_logic;
cktp_pulse : in std_logic;
cktp_max : in std_logic_vector(15 downto 0);
cktp_inhibit : out std_logic
);
end component;
component ckbc_gen
port(
clk_160 : in std_logic;
duty_cycle : in std_logic_vector(7 downto 0);
freq : in std_logic_vector(5 downto 0);
readout_mode : in std_logic;
enable_ro_ckbc : in std_logic;
ready : in std_logic;
ckbc_ro_out : out std_logic;
ckbc_out : out std_logic;
ckbc_max_num : in std_logic_vector(7 downto 0)
);
end component;
component skew_gen
port(
clk_500 : in std_logic;
CKTP_preSkew : in std_logic;
skew : in std_logic_vector(4 downto 0);
CKTP_skewed : out std_logic
);
end component;
signal ckbc_start : std_logic := '0';
signal cktp_start : std_logic := '0';
signal cktp_gen_start : std_logic := '0';
signal cktp_inhibit : std_logic := '0';
signal CKBC_preBuf : std_logic := '0';
signal CKBC_ro_preBuf : std_logic := '0';
signal CKBC_glbl : std_logic := '0';
signal CKTP_from_orig_gen : std_logic := '0';
signal CKTP_from_skew_gen : std_logic := '0';
signal CKTP_glbl : std_logic := '0';
signal sel_skew_gen : std_logic := '0';
signal skew_cktp_gen : std_logic_vector(4 downto 0) := (others => '0');
signal cktp_width_final : std_logic_vector(11 downto 0) := "000101000000"; --4 * 80 = 320
signal cktp_period_final : std_logic_vector(21 downto 0) := "0000100111000100000000"; --5'000 * 32 = 160'000
begin
ckbc_generator: ckbc_gen
port map(
clk_160 => clk_160,
duty_cycle => (others => '0'), -- unused
readout_mode => readout_mode,
enable_ro_ckbc => enable_ro_ckbc,
freq => ckbc_freq,
ready => ckbc_start,
ckbc_ro_out => CKBC_ro_preBuf,
ckbc_out => CKBC_preBuf,
ckbc_max_num => ckbc_max_num
);
CKBC_BUFGMUX: BUFGMUX
port map(O => CKBC_glbl, I0 => CKBC_preBuf, I1 => CKBC_ro_preBuf, S => readout_mode);
cktp_generator: cktp_gen
port map(
clk_160 => clk_160,
cktp_start => cktp_gen_start,
cktp_primary => cktp_primary,
vmm_ckbc => CKBC_preBuf,
ckbc_mode => readout_mode,
ckbc_freq => ckbc_freq,
skew => skew_cktp_gen,
pulse_width => cktp_width_final,
period => cktp_period_final,
CKTP => CKTP_from_orig_gen
);
cktp_max_module: cktp_counter
port map(
clk_160 => clk_160,
cktp_start => cktp_start,
cktp_pulse => CKTP_from_orig_gen,
cktp_max => cktp_max_num,
cktp_inhibit => cktp_inhibit
);
skewing_module: skew_gen
port map(
clk_500 => clk_500,
CKTP_preSkew => CKTP_from_orig_gen,
skew => cktp_skew,
CKTP_skewed => CKTP_from_skew_gen
);
CKTP_BUFGMUX: BUFGMUX
port map(O => CKTP_glbl, I0 => CKTP_from_orig_gen, I1 => CKTP_from_skew_gen, S => sel_skew_gen);
skew_sel_proc: process(ckbc_freq, cktp_skew)
begin
case ckbc_freq is
when "101000" => -- 40
skew_cktp_gen <= (others => '0'); -- skewing controlled by skew_gen
if(cktp_skew = "00000")then
sel_skew_gen <= '0'; -- no skew
else
sel_skew_gen <= '1'; -- select high granularity skewing module (2 ns step size)
end if;
when others =>
sel_skew_gen <= '0'; -- select low granularity skewing from cktp_gen (6.125 ns step size)
skew_cktp_gen <= cktp_skew;
end case;
end process;
cktp_start <= not rst and cktp_enable and mmcm_locked;
cktp_gen_start <= not rst and cktp_enable and mmcm_locked and not cktp_inhibit;
ckbc_start <= not rst and mmcm_locked;
CKBC <= CKBC_glbl;
CKTP <= CKTP_glbl;
CKTP_raw <= CKTP_from_orig_gen;
--- conversions ----
cktp_width_final <= std_logic_vector(unsigned(cktp_pulse_width)*"1010000"); -- input x 80
cktp_period_final <= std_logic_vector(unsigned(cktp_period)*"100000"); -- input x 32
end RTL;
| gpl-3.0 | 3f266f746ffdd05a3e0f36d22f91326c | 0.531755 | 3.772767 | false | false | false | false |
HackLinux/ION | src/rtl/buses/ion_ctcm_arbiter.vhdl | 1 | 5,361 | --------------------------------------------------------------------------------
-- ion_ctcm_arbiter.vhdl -- Arbiter for access to CTCM from data & code buses.
--------------------------------------------------------------------------------
-- This is a minimalistic arbiter meant to enable access to the code TCM from
-- both the code and data buses, for both read and write.
-- The code TCM needs to be accessible so that the SW can load code into it
-- and so that the SW can access its constants without resorting to linker
-- trickery.
--
-- Note that this stuff only works for masters that don´t produce any wait
-- states themselves, like the code TCM.
-- Also, the data port is always given priority over the code port.
-- This is NOT a generic arbiter nor a good starting point for one!
--
-- REFERENCES
-- [1] ion_notes.pdf -- ION project design notes.
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.ION_INTERFACES_PKG.all;
use work.ION_INTERNAL_PKG.all;
-- IMPORTANT: This is NOT a GENERAL ION BUS ARBITER; it does not pass along the
-- slave wait line. It works with the Code TCM but will fail with other slaves.
-- Also, it's tailored for Data and Code master ports.
entity ION_CTCM_ARBITER is
generic(
-- Size of memory area occupied by slave 0 in bytes.
SLAVE_0_AREA_SIZE : integer := 4096
);
port(
CLK_I : in std_logic;
RESET_I : in std_logic;
MASTER_D_CE_I : in std_logic;
MASTER_D_MOSI_I : in t_cpumem_mosi;
MASTER_D_MISO_O : out t_cpumem_miso;
MASTER_C_CE_I : in std_logic;
MASTER_C_MOSI_I : in t_cpumem_mosi;
MASTER_C_MISO_O : out t_cpumem_miso;
SLAVE_MOSI_O : out t_cpumem_mosi;
SLAVE_MISO_I : in t_cpumem_miso
);
end;
architecture rtl of ION_CTCM_ARBITER is
-- Asserted when both masters attempt to access the slave in the same cycle.
signal clash : std_logic;
signal clash_reg : std_logic;
signal data_request : std_logic;
signal data_request_reg : std_logic;
signal code_request : std_logic;
begin
----------------------------------------------------------------------------
---- Arbitration logic.
-- Figure up when the masters are actually using the port.
data_request <=
'1' when MASTER_D_MOSI_I.rd_en='1' else
'1' when MASTER_D_MOSI_I.wr_be /="0000" else
'0';
code_request <=
'1' when MASTER_C_MOSI_I.rd_en='1' else
'0';
-- when both masters attempt an access on the same cycle we have a clash.
clash <= (MASTER_D_CE_I and data_request);-- and
--(MASTER_C_CE_I and code_request);
-- We need to register a clash because we have to wait the code for two
-- cycles, clash and clash+1.
-- FIXME this is not necessary, test it with a single wait.
process(CLK_I)
begin
if (CLK_I'event and CLK_I='1') then
if RESET_I='1' then
clash_reg <= '0';
data_request_reg <= '0';
else
clash_reg <= clash;
data_request_reg <= data_request;
end if;
end if;
end process;
-- MOSI is combinationally multiplexed giving priority to the data port.
SLAVE_MOSI_O <=
MASTER_D_MOSI_I when MASTER_D_CE_I='1' and data_request='1' else
MASTER_C_MOSI_I;
-- The data mosi comes straight from the slave.
MASTER_D_MISO_O <= SLAVE_MISO_I;
-- The code port will be stalled during a clash cycle.
MASTER_C_MISO_O.rd_data <= SLAVE_MISO_I.rd_data;
-- FIXME explain
MASTER_C_MISO_O.mwait <= clash_reg;
end architecture rtl;
| lgpl-3.0 | 0aa6bca728b4305de1b5890aa7848196 | 0.543555 | 4.330372 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/sgmii_10_100_1000/ipcore_dir/i2c_top.vhd | 2 | 1,550 | ----------------------------------------------------------------------------------
-- Company: NTU ATHNENS - BNL
-- Engineer: Panagiotis Gkountoumis
--
-- Create Date: 18.04.2016 13:00:21
-- Design Name:
-- Module Name: config_logic - Behavioral
-- Project Name: MMFE8
-- Target Devices: Arix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2016.2
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use UNISIM.VComponents.all;
entity i2c_top is
generic(cnt_1ms : natural := 50_000; -- 20ns*50_000 = 1ms
cnt_10ms : natural := 500_000); --20ns*500_000 = 10ms
port(
clk_in : in std_logic; -- clk40, W19, LVCMOS33
phy_rstn_out : out std_logic
);
end i2c_top;
architecture rtl of i2c_top is
signal phy_resetn : std_logic := '0';
begin
phy_rstn_out <= phy_resetn;
phy_resetn_process : process(clk_in, phy_resetn) is
variable cnt : natural range 0 to cnt_1ms := 0; --1ms
begin
if (rising_edge(clk_in)) then
if phy_resetn = '0' then --resetn
if(cnt < cnt_1ms)then --cnt
cnt := cnt + 1;
elsif(cnt = cnt_1ms)then
cnt := 0;
phy_resetn <= '1';
else null;
end if; --cnt
else null;
end if; --resetn check
end if; --clk
end process;
end rtl;
| gpl-3.0 | 88c3aa8f16a7c6c689c24915a5b4822f | 0.536129 | 3.215768 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/Multirate/tb_decimator.vhd | 1 | 3,344 | --------------------------------------------------------------------------------------------------
-- Decimator Testbench
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tb_clockgen_pkg.all;
use work.tb_read_csv_pkg.all;
use work.tb_write_csv_pkg.all;
use work.dsp_pkg.all;
use work.decimator_pkg.all;
--This module is a test-bench for simulating the fir filter
entity tb_fir_filter is
end tb_fir_filter;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture sim of tb_fir_filter is
-- constant INPUT_FILE : string
-- := "X:\Education\Masters Thesis\matlab\fir_filters\singleSig.csv";
-- constant OUTPUT_FILE : string
-- := "X:\Education\Masters Thesis\matlab\fir_filters\singleSig_decimated.csv";
-- constant INPUT_FILE : string
-- := "X:\Education\Masters Thesis\matlab\fir_filters\mixedSigs.csv";
-- constant OUTPUT_FILE : string
-- := "X:\Education\Masters Thesis\matlab\fir_filters\mixedSigs_decimated.csv";
constant INPUT_FILE : string
:= "X:\Education\Masters Thesis\matlab\fir_filters\chirp.csv";
constant OUTPUT_FILE : string
:= "X:\Education\Masters Thesis\matlab\fir_filters\chirp_decimated.csv";
signal rst : std_logic := '0';
signal clk_10ns : std_logic := '0';
signal clk_20ns : std_logic := '0';
signal sig_in : sig := (others => '0');
signal sig_out : sig := (others => '0');
begin
--Instantiate clock generator
clk1 : tb_clockgen
generic map(PERIOD => 10ns,
DUTY_CYCLE => 0.50)
port map( clk => clk_10ns);
clk2 : tb_clockgen
generic map(PERIOD => 20ns,
DUTY_CYCLE => 0.50)
port map( clk => clk_20ns);
--Instantiate file reader
reader : tb_read_csv
generic map(FILENAME => INPUT_FILE)
port map( clk => clk_10ns,
sig(data) => sig_in);
--Instantiate unit under test
uut : entity work.decimator(behave)
-- generic map(h => LOW_PASS)
generic map(h => PR_ANALYSIS_LOW)
port map( clk_high => clk_10ns,
clk_low => clk_20ns,
rst => rst,
sig_high => sig_in,
sig_low => sig_out);
--Instantiate a file writer
writer : tb_write_csv
generic map(FILENAME => OUTPUT_FILE)
port map( clk => clk_20ns,
data => std_logic_vector(sig_out));
--Main Process
--TODO: Add a check for end of file, once reached terminate simulation.
main: process
begin
rst <= '1';
wait for 16ns;
rst <= '0';
wait;
end process;
end sim;
| mit | 02c6d268178a4b96ed23ef734dd57519 | 0.464115 | 4.314839 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/EPROC_IN8_ALIGN_BLOCK.vhd | 2 | 4,177 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/25/2014
--! Module Name: EPROC_IN8_ALIGN_BLOCK
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.all;
use work.centralRouter_package.all;
--! continuously aligns 8bit bit-stream to two commas
entity EPROC_IN8_ALIGN_BLOCK is
port (
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
bytes : in word10b_4array_type;
bytes_rdy : in std_logic;
------------
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic;
------------
busyOut : out std_logic
);
end EPROC_IN8_ALIGN_BLOCK;
architecture Behavioral of EPROC_IN8_ALIGN_BLOCK is
signal bytes_r : word10b_4array_type := ((others=>'0'),(others=>'0'),(others=>'0'),(others=>'0'));
signal send_state : std_logic := '0';
signal dataOUT_s : std_logic_vector(9 downto 0) := (others => '0');
signal dataOUTrdy_s, bytes_rdy_r : std_logic := '0';
signal byte_count : std_logic_vector(1 downto 0) := "00";
begin
-------------------------------------------------------------------------------------------
-- clock1
-- input register
-------------------------------------------------------------------------------------------
process(bitCLKx2, rst)
begin
if rst = '1' then
bytes_rdy_r <= '0';
elsif rising_edge(bitCLKx2) then
if bytes_rdy = '1' then
bytes_rdy_r <= not bytes_rdy_r;
else
bytes_rdy_r <= '0';
end if;
end if;
end process;
--
input_latch: process(bitCLKx2)
begin
if rising_edge(bitCLKx2) then
if bytes_rdy = '1' then
bytes_r <= bytes;
end if;
end if;
end process;
--
--
process(bitCLKx2, rst)
begin
if rst = '1' then
send_state <= '0';
elsif rising_edge(bitCLKx2) then
if bytes_rdy = '1' then
send_state <= '1';
else
if byte_count = "11" then
send_state <= '0';
end if;
end if;
end if;
end process;
--
process(bitCLKx2)
begin
if rising_edge(bitCLKx2) then
if send_state = '1' then
byte_count <= byte_count + 1;
else
byte_count <= "00";
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------------
process(bitCLKx4)
begin
if rising_edge(bitCLKx4) then
if send_state = '1' then
dataOUTrdy_s <= not dataOUTrdy_s;
else
dataOUTrdy_s <= '0';
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------------
out_select_proc: process(byte_count, bytes_r)
begin
case (byte_count) is
when "00" => dataOUT_s <= bytes_r(0);
when "01" => dataOUT_s <= bytes_r(1);
when "10" => dataOUT_s <= bytes_r(2);
when "11" => dataOUT_s <= bytes_r(3);
when others =>
end case;
end process;
--
-------------------------------------------------------------------------------------------
-- dataOUT_s (@bitCLKx4) & dataOUTrdy_s (@bitCLKx4, 2nd clock) can be used when
-- decoder is moved up
-------------------------------------------------------------------------------------------
dec_8b10: entity work.dec_8b10_wrap
port map(
RESET => rst,
RBYTECLK => bitCLKx4,
ABCDEIFGHJ_IN => dataOUT_s,
HGFEDCBA => dataOUT(7 downto 0),
ISK => dataOUT(9 downto 8),
BUSY => busyOut
);
--
dataOUTrdy <= dataOUTrdy_s;
--
end Behavioral;
| gpl-3.0 | 6d6f42d29360d55f68b8c7e2ec271e9c | 0.421116 | 4.000958 | false | false | false | false |
azeemshaikh38/PipelinedProcessorWithInterrupts | Processor/alu2register_reg.vhd | 1 | 1,098 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity alu2register_reg is
port(
clk, rst : in std_logic;
raddr_in : in std_logic_vector(3 downto 0);
op_in : in std_logic_vector(1 downto 0);
result_in : in std_logic_vector(7 downto 0);
reg_wr_en_in : in std_logic;
raddr_out : out std_logic_vector(3 downto 0);
op_out : out std_logic_vector(1 downto 0);
result_out : out std_logic_vector(7 downto 0);
reg_wr_en_out : out std_logic
);
end alu2register_reg;
architecture mixed of alu2register_reg is
begin
process(clk, rst)
begin
if (rst = '1') then
raddr_out <= "0000";
op_out <= "00";
result_out <= X"00";
reg_wr_en_out <= '0';
elsif falling_edge(clk) then
raddr_out <= raddr_in;
op_out <= op_in;
result_out <= result_in;
reg_wr_en_out <= reg_wr_en_in;
end if;
end process;
end mixed;
| unlicense | 813171fe3cda4399e186846dd6ad66fc | 0.535519 | 3.347561 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/BLOCK_WORD_COUNTER.vhd | 2 | 4,951 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 07/13/2014
--! Module Name: BLOCK_WORD_COUNTER
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.centralRouter_package.all;
use work.all;
--! counts block words, inserts block header
entity BLOCK_WORD_COUNTER is
generic (
GBTid : integer := 0;
egroupID : integer := 0;
epathID : integer := 0
);
port (
CLK : in std_logic;
RESET : in std_logic;
RESTART : in std_logic;
BW_RDY : in std_logic; -- Block Word Ready Enable
-------------
EOB_MARK : out std_logic; -- End Of Block flag to send the trailer
BLOCK_HEADER_OUT : out std_logic_vector(15 downto 0); --> sending block header
BLOCK_HEADER_OUT_RDY : out std_logic; --> sending block header
-------------
BLOCK_COUNT_RDY : out std_logic
);
end BLOCK_WORD_COUNTER;
architecture Behavioral of BLOCK_WORD_COUNTER is
signal count_sig : std_logic_vector (9 downto 0) := (others => '0');
signal seq_num : std_logic_vector (4 downto 0) := (others => '0');
signal SOB_MARK, SOB_MARK0, seqCNTcase, seqCNTtrig, EOB_MARK_sig : std_logic;
signal SOB_MARK1, blockCountRdy : std_logic := '0';
signal BLOCK_HEADER : std_logic_vector(31 downto 0);
-- two first words are always sent in the beginning of a block transmittion
constant count_offset : std_logic_vector (9 downto 0) := "0000000001";
begin
ce: process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' or RESTART = '1' then
blockCountRdy <= '0';
elsif SOB_MARK1 = '1' then
blockCountRdy <= '1';
end if;
end if;
end process;
--
BLOCK_COUNT_RDY <= blockCountRdy;
--------------------------------------------------------------
-- counting block words, data partition
--------------------------------------------------------------
counter: process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
count_sig <= (others => '0');
else
if EOB_MARK_sig = '1' or RESTART = '1' then
count_sig <= count_offset;
elsif BW_RDY = '1' then
count_sig <= count_sig + 1;
end if;
end if;
end if;
end process;
--------------------------------------------------------------
-- End Of Block trigger out for the
-- sub-chunk data manager to insert a trailer
--------------------------------------------------------------
EOB_MARK_sig <= '1' when (count_sig = BLOCK_WORDn) else '0'; -- there is one more space left, for the trailer
EOB_MARK <= EOB_MARK_sig; -- to output
--------------------------------------------------------------
-- Block Sequence counter, 5 bit
--------------------------------------------------------------
seqCNTcase <= EOB_MARK_sig or RESTART;
seqCNTtrig_pulse: entity work.pulse_pdxx_pwxx generic map(pd=>2,pw=>1) port map(CLK, seqCNTcase, seqCNTtrig);
--
scounter: process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
seq_num <= (others => '0');
else
if seqCNTtrig = '1' then
seq_num <= seq_num + 1;
end if;
end if;
end if;
end process;
--------------------------------------------------------------
-- Start Of Block Mark to insert block header
--------------------------------------------------------------
SOB_MARK <= '1' when (count_sig = count_offset) else '0';
--------------------------------------------------------------
-- Start Of Block produces 2 triggers
-- to send 2 words, as header is 32bit
--------------------------------------------------------------
SOB_MARK0_PULSE: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(CLK, SOB_MARK, SOB_MARK0); -- FIFO WE to send word0
SOB_MARK1_PULSE: process(CLK)
begin
if rising_edge(CLK) then
SOB_MARK1 <= SOB_MARK0; -- FIFO WE to send word1
end if;
end process;
--
-- [0xABCD_16] [[block_counter_5] [GBTid_5 egroupID_3 epathID_3]]
BLOCK_HEADER <= "1010101111001101" & seq_num & (std_logic_vector(to_unsigned(GBTid, 5))) & (std_logic_vector(to_unsigned(egroupID, 3))) & (std_logic_vector(to_unsigned(epathID, 3)));
--
out_sel: process(CLK)
begin
if rising_edge(CLK) then
if SOB_MARK0 = '1' then
BLOCK_HEADER_OUT <= BLOCK_HEADER(31 downto 16);
else
BLOCK_HEADER_OUT <= BLOCK_HEADER(15 downto 0);
end if;
end if;
end process;
--
BLOCK_HEADER_OUT_RDY <= SOB_MARK0 or SOB_MARK1;
--
end Behavioral; | gpl-3.0 | acb04536387cd93d45071306c15482e8 | 0.495859 | 3.808462 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/TB_elinkInterface_top.vhd | 3 | 4,217 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 27/11/2016
--! Module Name: TB_elinkInterface_top
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library work, ieee, std;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use std.textio.all;
--use work.txt_util.all;
--! Test Bench for a GBT_DATA_MANAGERtest module,
--! stand alone GBT_DATA_MANAGER driven by EgroupDriver E-link emulator
ENTITY TB_elinkInterface_top IS
END TB_elinkInterface_top;
ARCHITECTURE behavior OF TB_elinkInterface_top IS
-- Component Declaration for the Unit Under Test (UUT)
component elinkInterface_top
port (
clk_200_in_n : in std_logic;
clk_200_in_p : in std_logic;
sys_reset_n : in std_logic;
rst_sw : in std_logic;
locked : out std_logic;
clk40_out : out std_logic;
rst_state : out std_logic;
------
emu_ena : in std_logic;
--
edata_clk : out std_logic;
edata : out std_logic_vector (15 downto 0);
edata_rdy : out std_logic
------
);
end component elinkInterface_top;
--Inputs
signal clk_200_in_n, sys_reset_n : std_logic := '1';
signal clk_200_in_p, rst_sw : std_logic := '0';
signal emu_ena : std_logic := '0';
--Outputs
signal edata : std_logic_vector(15 downto 0);
signal edata_rdy, locked, edata_clk, rst_state, clk40_out : std_logic;
--
signal sim_rdy : std_logic := '0';
-- Clock period definitions
constant clk_200_period : time := 5 ns;
constant clk40_period : time := 25 ns;
constant clk_320_period : time := 3.125 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: component elinkInterface_top
port map (
clk_200_in_n => clk_200_in_n,
clk_200_in_p => clk_200_in_p,
sys_reset_n => sys_reset_n,
rst_sw => rst_sw,
locked => locked,
clk40_out => clk40_out,
rst_state => rst_state,
------
emu_ena => emu_ena,
--
edata_clk => edata_clk,
edata => edata,
edata_rdy => edata_rdy
------
);
----------------------------------
-- Clock process definition
CLK_200_process :process
begin
clk_200_in_p <= '1';
wait for clk_200_period/2;
clk_200_in_p <= '0';
wait for clk_200_period/2;
end process;
--
clk_200_in_n <= not clk_200_in_p;
----------------------------------
---------------------------------------------------------------
-- elink data is written to file: "elink_data_16bit.txt"
---------------------------------------------------------------
process(edata_clk) -- write to a file
file results_file: text open write_mode is "elink_data_16bit.txt";
variable line_out: line;
begin
if edata_clk'event and edata_clk = '0' then
if edata_rdy = '1' then
write(line_out, edata);
writeline(results_file, line_out);
end if;
end if;
end process;
--
---------------------------------------------------------------
-- reset/fifo flush process is inside top module
---------------------------------------------------------------
reset_proc: process
begin
wait for 200 ns;
sys_reset_n <= '0'; --<--------------- reset_n MMCMs
wait for 200 ns;
sys_reset_n <= '1';
wait until locked = '1'; --<--------------- clocks are locked
wait until clk40_out = '0'; --
wait until clk40_out = '1'; -- next clock
rst_sw <= '1';
wait until clk40_out = '0'; --
wait until clk40_out = '1'; -- next clock
rst_sw <= '0';
wait until rst_state = '0';
------
wait until clk40_out = '0'; --
wait until clk40_out = '1'; -- next clock
sim_rdy <= '1';
wait;
end process;
--
--
ena_proc: process
begin
wait until sim_rdy = '1';
wait for 200 ns;
wait until clk40_out = '0'; --
wait until clk40_out = '1'; -- next clock
emu_ena <= '1';
wait;
end process;
--
end;
| gpl-3.0 | 6d46fee22ce648cfdb2ef83faed682fb | 0.504624 | 3.32571 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/enc8b10_wrap.vhd | 4 | 4,912 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/19/2014
--! Module Name: enc_8b10_wrap
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE, work;
use IEEE.STD_LOGIC_1164.ALL;
use work.centralRouter_package.all;
use work.all;
--! a wrap for 8b10b encoder
entity enc8b10_wrap is
port (
clk : in std_logic;
rst : in std_logic;
dataCode : in std_logic_vector (1 downto 0); -- 00"data, 01"eop, 10"sop, 11"comma
dataIN : in std_logic_vector (7 downto 0);
dataINrdy : in std_logic;
encDataOut : out std_logic_vector (9 downto 0);
encDataOutrdy : out std_logic
);
end enc8b10_wrap;
architecture Behavioral of enc8b10_wrap is
----------------------------------
----------------------------------
component MUX4_Nbit
generic (N : integer := 1);
port (
data0 : in std_logic_vector((N-1) downto 0);
data1 : in std_logic_vector((N-1) downto 0);
data2 : in std_logic_vector((N-1) downto 0);
data3 : in std_logic_vector((N-1) downto 0);
sel : in std_logic_vector(1 downto 0);
data_out : out std_logic_vector((N-1) downto 0)
);
end component MUX4_Nbit;
----------------------------------
----------------------------------
component enc_8b10b
port(
RESET : in std_logic ; -- Global asynchronous reset (active high)
clk : in std_logic ;
ena : in std_logic ;
--enaRise : in std_logic ;
--enaFall : in std_logic ;
--SBYTECLK : in std_logic ; -- Master synchronous send byte clock
KI : in std_logic ; -- Control (K) input(active high)
AI, BI, CI, DI, EI, FI, GI, HI : in std_logic ; -- Unencoded input data
JO, HO, GO, FO, IO, EO, DO, CO, BO, AO : out std_logic -- Encoded out
);
end component enc_8b10b;
----------------------------------
----------------------------------
signal isk : std_logic := '1';
signal encoder_rst, enc_ena_s : std_logic;
signal enc_ena, encoder_rst_delayed, encoder_rst_clk1 : std_logic := '1';
signal dataINrdy_s : std_logic;
signal rst_state : std_logic := '1';
signal dataIN_s, byte : std_logic_vector(7 downto 0);
signal dataCode_s : std_logic_vector(1 downto 0) := (others => '1');
begin
dataINrdy_s <= dataINrdy and (not encoder_rst);
-------------------------------------------------------------------------------------------
-- input registers
-------------------------------------------------------------------------------------------
process(clk)
begin
if clk'event and clk = '1' then
rst_state <= rst;
end if;
end process;
--
process(clk)
begin
if clk'event and clk = '1' then
if dataINrdy_s = '1' then
dataIN_s <= dataIN;
dataCode_s <= dataCode;
isk <= dataCode(1) or dataCode(0);
--rst_state <= '0';
-- else
-- dataIN_s <= Kchar_comma;
-- dataCode_s <= "11";
end if;
end if;
end process;
--
encoder_rst <= rst_state or rst;
--
-------------------------------------------------------------------------------------------
-- data code cases
-- 00"data, 01"eop, 10"sop, 11"comma
-------------------------------------------------------------------------------------------
inmux: MUX4_Nbit
generic map (N=>8)
port map (
data0 => dataIN_s,
data1 => Kchar_eop,
data2 => Kchar_sop,
data3 => Kchar_comma,
sel => dataCode_s,
data_out => byte
);
--
-------------------------------------------------------------------------------------------
-- 8b10b encoder
-------------------------------------------------------------------------------------------
process(clk)
begin
if clk'event and clk = '0' then
enc_ena <= dataINrdy_s or encoder_rst;
encoder_rst_clk1 <= encoder_rst;
encoder_rst_delayed <= encoder_rst_clk1;
end if;
end process;
--
enc_ena_s <= enc_ena or encoder_rst_delayed;
--
enc_8b10bx: enc_8b10b
port map(
RESET => encoder_rst, -- Global asynchronous reset (active high)
clk => clk,
ena => enc_ena_s,
--SBYTECLK => encClk_s, --clk, -- Master synchronous send byte clock
KI => isk, -- Control (K) input(active high)
AI=>byte(0), BI=>byte(1), CI=>byte(2), DI=>byte(3), EI=>byte(4), FI=>byte(5), GI=>byte(6), HI=>byte(7), -- Unencoded input data
JO=>encDataOut(9),HO=>encDataOut(8),GO=>encDataOut(7),FO=>encDataOut(6),IO=>encDataOut(5),EO=>encDataOut(4),DO=>encDataOut(3),CO=>encDataOut(2),BO=>encDataOut(1),AO=>encDataOut(0) -- Encoded out
);
--
--
process(clk)
begin
if clk'event and clk = '1' then
encDataOutrdy <= dataINrdy_s and (not encoder_rst);
end if;
end process;
--
end Behavioral;
| gpl-3.0 | 336e967f464d934efc9836b3746e4c94 | 0.479031 | 3.355191 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/Filter_Bank/tb_filter_bank.vhd | 1 | 3,526 | --------------------------------------------------------------------------------------------------
-- Filter Bank Testbench
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tb_clockgen_pkg.all;
use work.tb_read_csv_pkg.all;
use work.tb_write_csv_pkg.all;
use work.dsp_pkg.all;
use work.filter_bank_pkg.all;
--This module is a test-bench for simulating the fir filter
entity tb_filter_bank is
end tb_filter_bank;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture sim of tb_filter_bank is
constant INPUT_FILE : string
:= "X:\Education\Masters Thesis\matlab\filter_bank\chirp_long.csv";
constant OUTPUT_FILE : string
:= "X:\Education\Masters Thesis\matlab\filter_bank\chirp_filter_bank.csv";
signal rst : std_logic := '0';
signal clk_10ns : std_logic := '0';
signal clk_20ns : std_logic := '0';
signal clk_40ns : std_logic := '0';
signal clk_80ns : std_logic := '0';
signal sig_in : sig := (others => '0');
signal sig_out : sig := (others => '0');
begin
--Instantiate clock generator
clk1 : tb_clockgen
generic map(PERIOD => 10ns,
DUTY_CYCLE => 0.50)
port map( clk => clk_10ns);
clk2 : tb_clockgen
generic map(PERIOD => 20ns,
DUTY_CYCLE => 0.50)
port map( clk => clk_20ns);
clk3 : tb_clockgen
generic map(PERIOD => 40ns,
DUTY_CYCLE => 0.50)
port map( clk => clk_40ns);
clk4 : tb_clockgen
generic map(PERIOD => 80ns,
DUTY_CYCLE => 0.50)
port map( clk => clk_80ns);
--Instantiate file reader
reader : tb_read_csv
generic map(FILENAME => INPUT_FILE)
port map( clk => clk_10ns,
sig(data) => sig_in);
--Instantiate unit under test
uut : entity work.filter_bank(behave)
generic map(analysis_low => PR_ANALYSIS_LOW,
analysis_high => PR_ANALYSIS_HIGH,
synthesis_low => PR_SYNTHESIS_LOW,
synthesis_high => PR_SYNTHESIS_HIGH)
port map( clk0 => clk_10ns,
clk1 => clk_20ns,
clk2 => clk_40ns,
clk3 => clk_80ns,
rst => rst,
x => sig_in,
y => sig_out);
--Instantiate a file writer
writer1 : tb_write_csv
generic map(FILENAME => OUTPUT_FILE)
port map( clk => clk_10ns,
data => std_logic_vector(sig_out));
--Main Process
--TODO: Add a check for end of file, once reached terminate simulation.
main: process
begin
rst <= '1';
wait for 76ns;
rst <= '0';
wait;
end process;
end sim;
| mit | 92ca2b7d4c4f1c2f2cb62c49b7663c3d | 0.424277 | 4.42409 | false | false | false | false |
adelapie/noekeon | output_trans.vhd | 5 | 2,757 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity output_trans is
port(clk : in std_logic;
enc : in std_logic; -- (enc, 0) / (dec, 1)
rc_in : in std_logic_vector(31 downto 0);
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end output_trans;
architecture Behavioral of output_trans is
component theta is
port(a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
signal a_0_s : std_logic_vector(31 downto 0);
signal a_0_in_s : std_logic_vector(31 downto 0);
signal a_0_out_s : std_logic_vector(31 downto 0);
begin
a_0_s <= a_0_in xor rc_in;
a_0_in_s <= a_0_s when enc = '0' else a_0_in;
THETA_0 : theta port map (a_0_in_s,
a_1_in,
a_2_in,
a_3_in,
k_0_in,
k_1_in,
k_2_in,
k_3_in,
a_0_out_s,
a_1_out,
a_2_out,
a_3_out);
a_0_out <= (a_0_out_s xor rc_in) when enc = '1' else a_0_out_s;
end Behavioral;
| gpl-3.0 | 50461a3131b69dca7885e9acdda44149 | 0.615161 | 2.886911 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/pulse_pdxx_pwxx.vhd | 3 | 3,086 | ----------------------------------------------------------------------------------
--! Company: Weizmann Institute of Science
--! Engineer: juna
--!
--! Create Date: 18/12/2014
--! Module Name: pulse_pdxx_pwxx
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--! generates a one clk-pulse pd clkss after trigger rising edge
entity pulse_pdxx_pwxx is
generic (
pd : integer := 0; -- pulse delay in clks
pw : integer := 1 -- pulse width in clks
);
port (
clk : in std_logic;
trigger : in std_logic;
pulseout : out std_logic
);
end pulse_pdxx_pwxx;
architecture Behavioral of pulse_pdxx_pwxx is
------
constant shreg_pd_zeros: std_logic_vector(pd downto 0) := (others => '0');
constant shreg_pw_zeros: std_logic_vector(pw downto 0) := (others => '0');
--
signal shreg_pd: std_logic_vector(pd downto 0) := (others => '0');
signal shreg_pw: std_logic_vector(pw downto 0) := (others => '0');
--
signal on_s : std_logic := '0';
signal pulseout_s_pw_gt1_case_s : std_logic := '0';
signal trigger_1clk_delayed, t0, off_s : std_logic := '0';
------
begin
process (clk)
begin
if rising_edge(clk) then
trigger_1clk_delayed <= trigger;
end if;
end process;
t0 <= trigger and (not trigger_1clk_delayed); -- the first clk of a trigger, one clk pulse
--
----------------------------------------
-- shift register for pulse delay
----------------------------------------
pd0_case: if (pd = 0) generate
on_s <= t0;
end generate pd0_case;
--
--
pd1_case: if (pd = 1) generate
process (clk)
begin
if rising_edge(clk) then
on_s <= t0;
end if;
end process;
end generate pd1_case;
--
--
pd_gt1_case: if (pd > 1) generate
--
process (clk)
begin
if rising_edge(clk) then
if t0 = '1' then
shreg_pd <= shreg_pd_zeros(pd-1 downto 0) & '1';
else
shreg_pd <= shreg_pd(pd-1 downto 0) & '0';
end if;
end if;
end process;
--
on_s <= shreg_pd(pd-1);
end generate pd_gt1_case;
----------------------------------------
-- shift register for pulse width
----------------------------------------
pw1_case: if (pw = 1) generate
pulseout <= on_s;
end generate pw1_case;
pw_gt1_case: if (pw > 1) generate
--
process (clk)
begin
if rising_edge(clk) then
if on_s = '1' then
shreg_pw <= shreg_pw_zeros(pw-1 downto 0) & '1';
else
shreg_pw <= shreg_pw(pw-1 downto 0) & '0';
end if;
end if;
end process;
--
off_s <= shreg_pw(pw-1);
--
process (clk)
begin
if rising_edge(clk) then
if off_s = '1' then
pulseout_s_pw_gt1_case_s <= '0';
elsif on_s = '1' then
pulseout_s_pw_gt1_case_s <= '1';
end if;
end if;
end process;
--
pulseout <= (pulseout_s_pw_gt1_case_s or on_s) and (not off_s);
end generate pw_gt1_case;
end Behavioral;
| gpl-3.0 | c0e2b1e1b33fcdbc09665b7ef1b1d630 | 0.505833 | 3.168378 | false | false | false | false |
GustaMagik/RSA_Security_Token | VHDL_code/ver_A/RSA_Security_Token_Keyboard_Version/mem_array_ROM.vhdl | 1 | 2,607 |
--Copyright 2017 Gustav Örtenberg
--Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
--
--1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
--
--2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the
--documentation and/or other materials provided with the distribution.
--
--3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this
--software without specific prior written permission.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS
--BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
--GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
--LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use std.textio.ALL;
entity mem_array_ROM is
GENERIC(
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 6;
INIT_FILE : string);
Port(
ADDR : in STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
OUTPUT : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0)
);
end mem_array_ROM;
architecture dataflow of mem_array_ROM is
Type MEMORY_ARRAY is ARRAY (0 to 2**(ADDR_WIDTH)-1) of STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
impure function init_memory_wfile(mif_file_name : in string) return MEMORY_ARRAY is
file mif_file : text open read_mode is mif_file_name;
variable mif_line : line;
variable temp_bv : bit_vector(DATA_WIDTH-1 downto 0);
variable temp_mem : MEMORY_ARRAY;
begin
for i in MEMORY_ARRAY'range loop
readline(mif_file, mif_line);
read(mif_line, temp_bv);
temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
constant memory : MEMORY_ARRAY:=(init_memory_wfile(INIT_FILE));
begin
OUTPUT <= memory(to_integer(unsigned(ADDR)));
end dataflow; | bsd-3-clause | 1047c3c04e586e94b411ad4ff21047e0 | 0.751438 | 3.992343 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/MMFE8_1VMM/sources_1/imports/IPv4_TX.vhd | 1 | 23,845 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 16:20:42 06/01/2011
-- Design Name:
-- Module Name: IPv4_TX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple IP TX
-- doesnt handle segmentation
-- dest MAC addr resolution through ARP layer
-- Handle IPv4 protocol
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - fixed up setting of tx_result control defaults
-- Revision 0.03 - Added data_out_first
-- Revision 0.04 - Added handling of broadcast address
-- Revision 0.05 - Fix cks calc when add of high bits causes another ovf
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity IPv4_TX is
port (
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
-- system signals
clk : in std_logic; -- same clock used to clock mac data and ip data
reset : in std_logic;
our_ip_address : in std_logic_vector (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
-- ARP lookup signals
arp_req_req : out arp_req_req_type;
arp_req_rslt : in arp_req_rslt_type;
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
mac_data_out_ready : in std_logic; -- indicates system ready to consume data
mac_data_out_valid : out std_logic; -- indicates data out is valid
mac_data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
mac_data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
mac_data_out : out std_logic_vector (7 downto 0) -- ethernet frame (from dst mac addr through to last byte of frame)
);
end IPv4_TX;
architecture Behavioral of IPv4_TX is
type tx_state_type is (
IDLE,
WAIT_MAC, -- waiting for response from ARP for mac lookup
WAIT_CHN, -- waiting for tx access to MAC channel
SEND_ETH_HDR, -- sending the ethernet header
SEND_IP_HDR, -- sending the IP header
SEND_USER_DATA -- sending the users data
);
type crc_state_type is (IDLE, TOT_LEN, ID, FLAGS, TTL, CKS, SAH, SAL, DAH, DAL, ADDOVF, FINAL, WAIT_END);
type count_mode_type is (RST, INCR, HOLD);
type settable_cnt_type is (RST, SET, INCR, HOLD);
type set_clr_type is (SET, CLR, HOLD);
-- Configuration
constant IP_TTL : std_logic_vector (7 downto 0) := x"80";
-- TX state variables
signal tx_state : tx_state_type;
signal tx_count : unsigned (11 downto 0);
signal tx_result_reg : std_logic_vector (1 downto 0);
signal tx_mac : std_logic_vector (47 downto 0);
signal tx_mac_chn_reqd : std_logic;
signal tx_hdr_cks : std_logic_vector (23 downto 0);
signal mac_lookup_req : std_logic;
signal crc_state : crc_state_type;
signal arp_req_ip_reg : std_logic_vector (31 downto 0);
signal mac_data_out_ready_reg : std_logic;
-- tx control signals
signal next_tx_state : tx_state_type;
signal set_tx_state : std_logic;
signal next_tx_result : std_logic_vector (1 downto 0);
signal set_tx_result : std_logic;
signal tx_mac_value : std_logic_vector (47 downto 0);
signal set_tx_mac : std_logic;
signal tx_count_val : unsigned (11 downto 0);
signal tx_count_mode : settable_cnt_type;
signal tx_data : std_logic_vector (7 downto 0);
signal set_last : std_logic;
signal set_chn_reqd : set_clr_type;
signal set_mac_lku_req : set_clr_type;
signal tx_data_valid : std_logic; -- indicates whether data is valid to tx or not
-- tx temp signals
signal total_length : std_logic_vector (15 downto 0); -- computed combinatorially from header size
function inv_if_one(s1 : std_logic_vector; en : std_logic) return std_logic_vector is
--this function inverts all the bits of a vector if
--'en' is '1'.
variable Z : std_logic_vector(s1'high downto s1'low);
begin
for i in (s1'low) to s1'high loop
Z(i) := en xor s1(i);
end loop;
return Z;
end inv_if_one; -- end function
-- IP datagram header format
--
-- 0 4 8 16 19 24 31
-- --------------------------------------------------------------------------------------------
-- | Version | *Header | Service Type | Total Length including header |
-- | (4) | Length | (ignored) | (in bytes) |
-- --------------------------------------------------------------------------------------------
-- | Identification | Flags | Fragment Offset |
-- | | | (in 32 bit words) |
-- --------------------------------------------------------------------------------------------
-- | Time To Live | Protocol | Header Checksum |
-- | (ignored) | | |
-- --------------------------------------------------------------------------------------------
-- | Source IP Address |
-- | |
-- --------------------------------------------------------------------------------------------
-- | Destination IP Address |
-- | |
-- --------------------------------------------------------------------------------------------
-- | Options (if any - ignored) | Padding |
-- | | (if needed) |
-- --------------------------------------------------------------------------------------------
-- | Data |
-- | |
-- --------------------------------------------------------------------------------------------
-- | .... |
-- | |
-- --------------------------------------------------------------------------------------------
--
-- * - in 32 bit words
begin
-----------------------------------------------------------------------
-- combinatorial process to implement FSM and determine control signals
-----------------------------------------------------------------------
tx_combinatorial : process(
-- input signals
ip_tx_start, ip_tx, our_ip_address, our_mac_address, arp_req_rslt, --clk,
mac_tx_granted, mac_data_out_ready,
-- state variables
tx_state, tx_count, tx_result_reg, tx_mac, tx_mac_chn_reqd,
mac_lookup_req, tx_hdr_cks, arp_req_ip_reg, mac_data_out_ready_reg,
-- control signals
next_tx_state, set_tx_state, next_tx_result, set_tx_result, tx_mac_value, set_tx_mac, tx_count_mode,
tx_data, set_last, set_chn_reqd, set_mac_lku_req, total_length,
tx_data_valid, tx_count_val
)
begin
-- set output followers
ip_tx_result <= tx_result_reg;
mac_tx_req <= tx_mac_chn_reqd;
arp_req_req.lookup_req <= mac_lookup_req;
arp_req_req.ip <= arp_req_ip_reg;
-- set initial values for combinatorial outputs
mac_data_out_first <= '0';
case tx_state is
when SEND_ETH_HDR | SEND_IP_HDR =>
mac_data_out <= tx_data;
tx_data_valid <= mac_data_out_ready; -- generated internally
mac_data_out_last <= set_last;
when SEND_USER_DATA =>
mac_data_out <= ip_tx.data.data_out;
tx_data_valid <= ip_tx.data.data_out_valid;
mac_data_out_last <= ip_tx.data.data_out_last;
when others =>
mac_data_out <= (others => '0');
tx_data_valid <= '0'; -- not transmitting during this phase
mac_data_out_last <= '0';
end case;
mac_data_out_valid <= tx_data_valid and mac_data_out_ready;
-- set signal defaults
next_tx_state <= IDLE;
set_tx_state <= '0';
tx_count_mode <= HOLD;
tx_data <= x"00";
set_last <= '0';
set_tx_mac <= '0';
set_chn_reqd <= HOLD;
set_mac_lku_req <= HOLD;
next_tx_result <= IPTX_RESULT_NONE;
set_tx_result <= '0';
tx_count_val <= (others => '0');
tx_mac_value <= (others => '0');
-- set temp signals
total_length <= std_logic_vector(unsigned(ip_tx.hdr.data_length) + 20); -- total length = user data length + header length (bytes)
-- TX FSM
case tx_state is
when IDLE =>
ip_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
tx_count_mode <= RST;
set_chn_reqd <= CLR;
if ip_tx_start = '1' then
-- check header count for error if too high
if unsigned(ip_tx.hdr.data_length) > 8980 then --1480
next_tx_result <= IPTX_RESULT_ERR;
set_tx_result <= '1';
else
next_tx_result <= IPTX_RESULT_SENDING;
set_tx_result <= '1';
-- TODO - check if we already have the mac addr for this ip, if so, bypass the WAIT_MAC state
if ip_tx.hdr.dst_ip_addr = IP_BC_ADDR then
-- for IP broadcast, dont need to look up the MAC addr
tx_mac_value <= MAC_BC_ADDR;
set_tx_mac <= '1';
next_tx_state <= WAIT_CHN;
set_tx_state <= '1';
else
-- need to req the mac address for this ip
set_mac_lku_req <= SET;
next_tx_state <= WAIT_MAC;
set_tx_state <= '1';
end if;
end if;
else
set_mac_lku_req <= CLR;
end if;
when WAIT_MAC =>
ip_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
set_mac_lku_req <= CLR; -- clear the request - will have been latched in the ARP layer
-- if arp_req_rslt.got_mac = '1' then
-- save the MAC we got back from the ARP lookup
tx_mac_value <= arp_req_rslt.mac;
set_tx_mac <= '1';
set_chn_reqd <= SET;
-- check for optimise when already have the channel
-- if mac_tx_granted = '1' then
-- ready to send data
next_tx_state <= SEND_ETH_HDR;
set_tx_state <= '1';
-- else
-- next_tx_state <= WAIT_CHN;
-- set_tx_state <= '1';
-- end if;
-- elsif arp_req_rslt.got_err = '1' then
-- set_mac_lku_req <= CLR;
-- next_tx_result <= IPTX_RESULT_ERR;
-- set_tx_result <= '1';
-- next_tx_state <= IDLE;
-- set_tx_state <= '1';
-- end if;
when WAIT_CHN =>
ip_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
if mac_tx_granted = '1' then
-- ready to send data
next_tx_state <= SEND_ETH_HDR;
set_tx_state <= '1';
end if;
-- probably should handle a timeout here
when SEND_ETH_HDR =>
ip_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
if mac_data_out_ready = '1' then
if tx_count = x"00d" then
tx_count_mode <= RST;
next_tx_state <= SEND_IP_HDR;
set_tx_state <= '1';
else
tx_count_mode <= INCR;
end if;
case tx_count is
when x"000" =>
mac_data_out_first <= mac_data_out_ready;
tx_data <= tx_mac (47 downto 40); -- trg = mac from ARP lookup
when x"001" => tx_data <= tx_mac (39 downto 32);
when x"002" => tx_data <= tx_mac (31 downto 24);
when x"003" => tx_data <= tx_mac (23 downto 16);
when x"004" => tx_data <= tx_mac (15 downto 8);
when x"005" => tx_data <= tx_mac (7 downto 0);
when x"006" => tx_data <= our_mac_address (47 downto 40); -- src = our mac
when x"007" => tx_data <= our_mac_address (39 downto 32);
when x"008" => tx_data <= our_mac_address (31 downto 24);
when x"009" => tx_data <= our_mac_address (23 downto 16);
when x"00a" => tx_data <= our_mac_address (15 downto 8);
when x"00b" => tx_data <= our_mac_address (7 downto 0);
when x"00c" => tx_data <= x"08"; -- pkt type = 0800 : IP
when x"00d" => tx_data <= x"00";
when others =>
-- shouldnt get here - handle as error
next_tx_result <= IPTX_RESULT_ERR;
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
end case;
end if;
when SEND_IP_HDR =>
ip_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
if mac_data_out_ready = '1' then
if tx_count = x"013" then
tx_count_val <= x"001";
tx_count_mode <= SET;
next_tx_state <= SEND_USER_DATA;
set_tx_state <= '1';
else
tx_count_mode <= INCR;
end if;
case tx_count is
when x"000" => tx_data <= x"45"; -- v4, 5 words in hdr
when x"001" => tx_data <= x"00"; -- service type
when x"002" => tx_data <= total_length (15 downto 8); -- total length
when x"003" => tx_data <= total_length (7 downto 0);
when x"004" => tx_data <= x"00"; -- identification
when x"005" => tx_data <= x"00";
when x"006" => tx_data <= x"00"; -- flags and fragment offset
when x"007" => tx_data <= x"00";
when x"008" => tx_data <= IP_TTL; -- TTL
when x"009" => tx_data <= ip_tx.hdr.protocol; -- protocol
when x"00a" => tx_data <= tx_hdr_cks (15 downto 8); -- HDR checksum
when x"00b" => tx_data <= tx_hdr_cks (7 downto 0); -- HDR checksum
when x"00c" => tx_data <= our_ip_address (31 downto 24); -- src ip
when x"00d" => tx_data <= our_ip_address (23 downto 16);
when x"00e" => tx_data <= our_ip_address (15 downto 8);
when x"00f" => tx_data <= our_ip_address (7 downto 0);
when x"010" => tx_data <= ip_tx.hdr.dst_ip_addr (31 downto 24); -- dst ip
when x"011" => tx_data <= ip_tx.hdr.dst_ip_addr (23 downto 16);
when x"012" => tx_data <= ip_tx.hdr.dst_ip_addr (15 downto 8);
when x"013" => tx_data <= ip_tx.hdr.dst_ip_addr (7 downto 0);
when others =>
-- shouldnt get here - handle as error
next_tx_result <= IPTX_RESULT_ERR;
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
end case;
end if;
when SEND_USER_DATA =>
ip_tx_data_out_ready <= mac_data_out_ready;-- and mac_data_out_ready_reg; -- in this state, we are always ready to accept user data for tx
if mac_data_out_ready = '1' then
if ip_tx.data.data_out_valid = '1' or tx_count = x"000" then
-- only increment if ready and valid has been subsequently established, otherwise data count moves on too fast
if unsigned(tx_count) = unsigned(ip_tx.hdr.data_length) then
-- TX terminated due to count - end normally
set_last <= '1';
set_chn_reqd <= CLR;
tx_data <= ip_tx.data.data_out;
next_tx_result <= IPTX_RESULT_SENT;
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
if ip_tx.data.data_out_last = '0' then
next_tx_result <= IPTX_RESULT_ERR;
end if;
elsif ip_tx.data.data_out_last = '1' then
-- TX terminated due to receiving last indication from upstream - end with error
set_last <= '1';
set_chn_reqd <= CLR;
tx_data <= ip_tx.data.data_out;
next_tx_result <= IPTX_RESULT_ERR;
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
else
-- TX continues
tx_count_mode <= INCR;
tx_data <= ip_tx.data.data_out;
end if;
end if;
end if;
end case;
end process;
-----------------------------------------------------------------------------
-- sequential process to action control signals and change states and outputs
-----------------------------------------------------------------------------
tx_sequential : process (clk)--, reset, mac_data_out_ready_reg)
begin
-- if rising_edge(clk) then
-- mac_data_out_ready_reg <= mac_data_out_ready;
-- else
-- mac_data_out_ready_reg <= mac_data_out_ready_reg;
-- end if;
if rising_edge(clk) then
if reset = '1' then
-- reset state variables
tx_state <= IDLE;
tx_count <= x"000";
tx_result_reg <= IPTX_RESULT_NONE;
tx_mac <= (others => '0');
tx_mac_chn_reqd <= '0';
mac_lookup_req <= '0';
else
-- Next tx_state processing
if set_tx_state = '1' then
tx_state <= next_tx_state;
else
tx_state <= tx_state;
end if;
-- tx result processing
if set_tx_result = '1' then
tx_result_reg <= next_tx_result;
else
tx_result_reg <= tx_result_reg;
end if;
-- control arp lookup request
case set_mac_lku_req is
when SET =>
arp_req_ip_reg <= ip_tx.hdr.dst_ip_addr;
mac_lookup_req <= '1';
when CLR =>
mac_lookup_req <= '0';
arp_req_ip_reg <= arp_req_ip_reg;
when HOLD =>
mac_lookup_req <= mac_lookup_req;
arp_req_ip_reg <= arp_req_ip_reg;
end case;
-- save MAC
if set_tx_mac = '1' then
tx_mac <= tx_mac_value;
else
tx_mac <= tx_mac;
end if;
-- control access request to mac tx chn
case set_chn_reqd is
when SET => tx_mac_chn_reqd <= '1';
when CLR => tx_mac_chn_reqd <= '0';
when HOLD => tx_mac_chn_reqd <= tx_mac_chn_reqd;
end case;
-- tx_count processing
case tx_count_mode is
when RST => tx_count <= x"000";
when SET => tx_count <= tx_count_val;
when INCR => tx_count <= tx_count + 1;
when HOLD => tx_count <= tx_count;
end case;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Process to calculate CRC in parallel with pkt out processing
-- this process must yield a valid CRC before it is required to be used in the hdr
-----------------------------------------------------------------------------
crc : process (clk)--, reset)
begin
if rising_edge(clk) then
case crc_state is
when IDLE =>
if ip_tx_start = '1' then
tx_hdr_cks <= x"004500"; -- vers & hdr len & service
crc_state <= TOT_LEN;
end if;
when TOT_LEN =>
tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(total_length));
crc_state <= ID;
when ID =>
tx_hdr_cks <= tx_hdr_cks;
crc_state <= FLAGS;
when FLAGS =>
tx_hdr_cks <= tx_hdr_cks;
crc_state <= TTL;
when TTL =>
tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(IP_TTL & ip_tx.hdr.protocol));
crc_state <= CKS;
when CKS =>
tx_hdr_cks <= tx_hdr_cks;
crc_state <= SAH;
when SAH =>
tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(our_ip_address(31 downto 16)));
crc_state <= SAL;
when SAL =>
tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(our_ip_address(15 downto 0)));
crc_state <= DAH;
when DAH =>
tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(ip_tx.hdr.dst_ip_addr(31 downto 16)));
crc_state <= DAL;
when DAL =>
tx_hdr_cks <= std_logic_vector (unsigned(tx_hdr_cks) + unsigned(ip_tx.hdr.dst_ip_addr(15 downto 0)));
crc_state <= ADDOVF;
when ADDOVF =>
tx_hdr_cks <= std_logic_vector ((unsigned(tx_hdr_cks) and x"00ffff")+ unsigned(tx_hdr_cks(23 downto 16)));
crc_state <= FINAL;
when FINAL =>
tx_hdr_cks <= inv_if_one(std_logic_vector (unsigned(tx_hdr_cks) + unsigned(tx_hdr_cks(23 downto 16))), '1');
crc_state <= WAIT_END;
when WAIT_END =>
tx_hdr_cks <= tx_hdr_cks;
if ip_tx_start = '0' then
crc_state <= IDLE;
else
crc_state <= WAIT_END;
end if;
end case;
end if;
end process;
end Behavioral;
| gpl-3.0 | 8eca8d9a0ff482908359a4bf034d9963 | 0.444286 | 3.963597 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4400/EPROC_OUT4.vhd | 3 | 5,127 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 18/03/2015
--! Module Name: EPROC_OUT4
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee,work;
use ieee.std_logic_1164.all;
use work.all;
--! E-link processor, 4bit output
entity EPROC_OUT4 is
generic (do_generate : boolean := true);
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
ENA : in std_logic;
getDataTrig : out std_logic; -- @ bitCLKx4
ENCODING : in std_logic_vector (3 downto 0);
EDATA_OUT : out std_logic_vector (3 downto 0);
TTCin : in std_logic_vector (4 downto 0);
DATA_IN : in std_logic_vector (9 downto 0);
DATA_RDY : in std_logic
);
end EPROC_OUT4;
architecture Behavioral of EPROC_OUT4 is
constant zeros4bit : std_logic_vector (3 downto 0) := (others=>'0');
signal EdataOUT_ENC8b10b_case, EdataOUT_direct_case, EdataOUT_HDLC_case, EdataOUT_TTC1_case, EdataOUT_TTC2_case : std_logic_vector (3 downto 0);
signal rst_s, rst_case000, rst_case001, rst_case010, rst_case011 : std_logic;
signal getDataTrig_ENC8b10b_case, getDataTrig_direct_case, getDataTrig_HDLC_case, getDataTrig_TTC_cases : std_logic;
begin
gen_enabled: if do_generate = true generate
rst_s <= rst or (not ENA);
-------------------------------------------------------------------------------------------
-- case 0: direct data, no delimeter...
-------------------------------------------------------------------------------------------
rst_case000 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "000")) else '1';
--
direct_case: entity work.EPROC_OUT4_direct
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case000,
getDataTrig => getDataTrig_direct_case,
edataIN => DATA_IN,
edataINrdy => DATA_RDY,
EdataOUT => EdataOUT_direct_case
);
--
-------------------------------------------------------------------------------------------
-- case 1: DEC8b10b
-------------------------------------------------------------------------------------------
rst_case001 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "001")) else '1';
--
ENC8b10b_case: entity work.EPROC_OUT4_ENC8b10b
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case001,
getDataTrig => getDataTrig_ENC8b10b_case,
edataIN => DATA_IN,
edataINrdy => DATA_RDY,
EdataOUT => EdataOUT_ENC8b10b_case
);
--
-------------------------------------------------------------------------------------------
-- case 2: HDLC
-------------------------------------------------------------------------------------------
rst_case010 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "010")) else '1';
--
getDataTrig_HDLC_case <= '0'; --'1' when (ENCODING(2 downto 0) = "010") else '0';
EdataOUT_HDLC_case <= (others=>'0'); --<---TBD
--
-------------------------------------------------------------------------------------------
-- case 3&4: TTC-1 & TTC-2
-------------------------------------------------------------------------------------------
rst_case011 <= '0' when ((rst_s = '0') and ((ENCODING(2 downto 0) = "011") or (ENCODING(2 downto 0) = "100"))) else '1';
--
getDataTrig_TTC_cases <= '0'; --'1' when ((ENCODING(2 downto 0) = "011") or (ENCODING(2 downto 0) = "100")) else '0';
--
ttc_r: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if rst_case011 = '1' then
EdataOUT_TTC1_case <= zeros4bit;
EdataOUT_TTC2_case <= zeros4bit;
else
EdataOUT_TTC1_case <= TTCin(1) & TTCin(3 downto 2) & TTCin(0);
EdataOUT_TTC2_case <= TTCin(4 downto 2) & TTCin(0);
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- output data and busy according to the encoding settings
-------------------------------------------------------------------------------------------
dataOUTmux: entity work.MUX8_Nbit
generic map (N=>4)
port map(
data0 => EdataOUT_direct_case,
data1 => EdataOUT_ENC8b10b_case,
data2 => EdataOUT_HDLC_case,
data3 => EdataOUT_TTC1_case,
data4 => EdataOUT_TTC2_case,
data5 => zeros4bit,
data6 => zeros4bit,
data7 => zeros4bit,
sel => ENCODING(2 downto 0),
data_out => EDATA_OUT
);
--
getDataTrig <= ENA and (getDataTrig_TTC_cases or getDataTrig_HDLC_case or getDataTrig_ENC8b10b_case or getDataTrig_direct_case);
--
end generate gen_enabled;
--
--
gen_disabled: if do_generate = false generate
EDATA_OUT <= (others=>'0');
getDataTrig <= '0';
end generate gen_disabled;
end Behavioral;
| gpl-3.0 | 9a1e409aba16c1ccd99d0fb8a8f80bb3 | 0.46811 | 3.769853 | false | false | false | false |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/hdl/ZynqDesign_wrapper.vhd | 1 | 3,309 | library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity ZynqDesign_wrapper is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
leds_8bits_tri_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
sws_8bits_tri_i : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end ZynqDesign_wrapper;
architecture STRUCTURE of ZynqDesign_wrapper is
component ZynqDesign is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
leds_8bits_tri_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
sws_8bits_tri_i : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component ZynqDesign;
begin
ZynqDesign_i: component ZynqDesign
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
leds_8bits_tri_o(7 downto 0) => leds_8bits_tri_o(7 downto 0),
sws_8bits_tri_i(7 downto 0) => sws_8bits_tri_i(7 downto 0)
);
end STRUCTURE;
| mit | ba60e90d1930b54d4bcd9723a4a61c4a | 0.615594 | 2.897548 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/EPATH_FIFO_WRAP.vhd | 3 | 2,753 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 09/14/2014
--! Module Name: EPATH_FIFO_WRAP
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
--! EPATH FIFO 16 bit wide, 1K deep
entity EPATH_FIFO_WRAP is
port (
rst : in std_logic;
fifoFlush : in std_logic;
wr_clk : in std_logic;
rd_clk : in std_logic;
din : in std_logic_vector(15 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(15 downto 0);
almost_full : out std_logic;
prog_full : out std_logic
);
end EPATH_FIFO_WRAP;
architecture Behavioral of EPATH_FIFO_WRAP is
----------------------------------
----------------------------------
component EPATH_FIFO -- IP
port (
wr_clk : in std_logic;
wr_rst : in std_logic;
rd_clk : in std_logic;
rd_rst : in std_logic;
din : in std_logic_vector(15 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(15 downto 0);
full : out std_logic;
empty : out std_logic;
prog_full : out std_logic;
prog_empty : out std_logic;
prog_empty_thresh : in std_logic_vector(9 downto 0);
prog_full_thresh : in std_logic_vector(9 downto 0)
);
end component;
----------------------------------
----------------------------------
signal rd_en_s, wr_en_s : std_logic;
signal prog_full_s, full_s, empty_s, prog_empty_s : std_logic;
signal rst_state : std_logic;
begin
--
rd_en_s <= rd_en and (not rst_state);
wr_en_s <= wr_en and (not rst_state);
--
EPATH_FIFO_INST: EPATH_FIFO
PORT MAP (
wr_clk => wr_clk,
wr_rst => fifoFlush,
rd_clk => rd_clk,
rd_rst => fifoFlush,
din => din,
wr_en => wr_en_s,
rd_en => rd_en_s,
dout => dout,
full => full_s,
empty => empty_s,
prog_full => prog_full_s,
prog_empty => prog_empty_s,
prog_full_thresh => std_logic_vector(to_unsigned(512, 10)),
prog_empty_thresh => std_logic_vector(to_unsigned(1010, 10))
);
--
rst_state <= rst or (full_s and empty_s);
--
process(rd_clk)
begin
if rising_edge(rd_clk) then
prog_full <= prog_full_s and (not rst_state);
end if;
end process;
--
process(wr_clk)
begin
if rising_edge(wr_clk) then
almost_full <= not prog_empty_s;
end if;
end process;
--
end Behavioral;
| gpl-3.0 | 3fa6419627e39f815fdbcf5aa1ea9298 | 0.497276 | 3.15711 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/Filter_Bank/reconstruction.vhd | 1 | 3,080 | --------------------------------------------------------------------------------------------------
-- Signal Reconstruction
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- PACKAGE
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.dsp_pkg.all;
package reconstruction_pkg is
--FIR filter component declaration
component reconstruction is
generic( low_pass : coefficient_array;
high_pass : coefficient_array);
port( clk_low : in std_logic;
clk_high : in std_logic;
rst : in std_logic;
x_low : in sig;
x_high : in sig;
y : out sig);
end component;
end package;
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dsp_pkg.all;
use work.interpolator_pkg.all;
entity reconstruction is
generic( low_pass : coefficient_array;
high_pass : coefficient_array);
port( clk_low : in std_logic;
clk_high : in std_logic;
rst : in std_logic;
x_low : in sig;
x_high : in sig;
y : out sig);
end reconstruction;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture behave of reconstruction is
signal y_low : sig := (others => '0');
signal y_high : sig := (others => '0');
begin
--Decimate the signal using a low pass filter
low_filter_bank : interpolator
generic map(h => low_pass)
port map( clk_high => clk_high,
clk_low => clk_low,
rst => rst,
sig_low => x_low,
sig_high => y_low);
--Decimate the signal using a high pass filter
high_filter_bank : interpolator
generic map(h => high_pass)
port map( clk_high => clk_high,
clk_low => clk_low,
rst => rst,
sig_low => x_high,
sig_high => y_high);
--Sum the 2 banks together
update_sum : process(clk_high)
begin
if(rising_edge(clk_high)) then
if(rst = '1') then
y <= (others => '0');
else
y <= signed(y_low) + signed(y_high);
end if;
end if;
end process;
end behave;
| mit | 38fe79510bd220a849233592e2879876 | 0.373701 | 5 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4371/EPROC_IN2_ALIGN_BLOCK.vhd | 2 | 4,064 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 05/19/2014
--! Module Name: EPROC_IN2_ALIGN_BLOCK
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.STD_LOGIC_1164.ALL;
use ieee.STD_LOGIC_UNSIGNED.ALL;
use work.all;
use work.centralRouter_package.all;
--! continuously aligns 2bit bit-stream to a comma
entity EPROC_IN2_ALIGN_BLOCK is
Port (
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
bytes : in std_logic_vector(9 downto 0);
bytes_rdy : in std_logic;
------------
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic;
------------
busyOut : out std_logic
);
end EPROC_IN2_ALIGN_BLOCK;
architecture Behavioral of EPROC_IN2_ALIGN_BLOCK is
signal bytes_rdy_enabled : std_logic;
signal bytes_r, bytes_c3 : std_logic_vector(9 downto 0) := (others => '0');
signal bytes_rdy_r, send_state : std_logic := '0';
signal dataOUT_s : std_logic_vector(9 downto 0) := (others => '0');
signal dataOUTrdy_s, dataOUTrdy_s1, bytes_rdy_s, dataOUTrdy_c3 : std_logic := '0';
signal dataOUT_s_fe : std_logic_vector(9 downto 0);
begin
-------------------------------------------------------------------------------------------
-- clock1
-- input register
-------------------------------------------------------------------------------------------
bytes_rdy_enabled <= bytes_rdy;
--
process(bitCLKx2, rst)
begin
if rst = '1' then
bytes_rdy_s <= '0';
elsif bitCLKx2'event and bitCLKx2 = '1' then
if bytes_rdy_enabled = '1' then
bytes_rdy_s <= (not bytes_rdy_s);
else
bytes_rdy_s <= '0';
end if;
end if;
end process;
--
input_latch: process(bitCLKx2, rst)
begin
if rst = '1' then
bytes_r <= (others=>'0');
elsif bitCLKx2'event and bitCLKx2 = '1' then
if bytes_rdy_enabled = '1' then
bytes_r <= bytes;
end if;
end if;
end process;
--
bytes_rdy_r <= bytes_rdy_s and bytes_rdy_enabled;
--
send_state <= bytes_rdy_r;
-------------------------------------------------------------------------------------------
-- clock2
--
-------------------------------------------------------------------------------------------
process(bitCLKx4)
begin
if bitCLKx4'event and bitCLKx4 = '1' then
if send_state = '1' then
dataOUTrdy_s <= not dataOUTrdy_s;
else
dataOUTrdy_s <= '0';
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- clock3*
-- bitCLKx2 -> bitCLKx4
-------------------------------------------------------------------------------------------
process(bitCLKx4)
begin
if bitCLKx4'event and bitCLKx4 = '1' then
bytes_c3 <= bytes_r;
dataOUTrdy_c3 <= dataOUTrdy_s;
end if;
end process;
--
dataOUT_s <= bytes_c3;
--
-------------------------------------------------------------------------------------------
-- clock4*
--
-------------------------------------------------------------------------------------------
process(bitCLKx4)
begin
if bitCLKx4'event and bitCLKx4 = '1' then
dataOUTrdy_s1 <= dataOUTrdy_c3;
end if;
end process;
--
dec_8b10: entity work.dec_8b10_wrap
port map(
RESET => rst,
RBYTECLK => bitCLKx4,
ABCDEIFGHJ_IN => dataOUT_s,
HGFEDCBA => dataOUT_s_fe(7 downto 0),
ISK => dataOUT_s_fe(9 downto 8),
BUSY => busyOut
);
--
process(bitCLKx4)
begin
if bitCLKx4'event and bitCLKx4 = '1' then
dataOUT <= dataOUT_s_fe;
--dataOUTrdy <= dataOUTrdy_s1;
end if;
end process;
--
dataOUTrdy <= dataOUTrdy_s1;
--
end Behavioral;
| gpl-3.0 | e25e03ef411f8b7d4b4494dd7c8ea7d7 | 0.443898 | 3.852133 | false | false | false | false |
atti92/heterogenhomework | project1/solution1/syn/vhdl/fir_hw_smpl_V.vhd | 1 | 3,068 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.2
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fir_hw_smpl_V_ram is
generic(
mem_type : string := "block";
dwidth : integer := 18;
awidth : integer := 7;
mem_size : integer := 128
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of fir_hw_smpl_V_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array := (others=>(others=>'0'));
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity fir_hw_smpl_V is
generic (
DataWidth : INTEGER := 18;
AddressRange : INTEGER := 128;
AddressWidth : INTEGER := 7);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of fir_hw_smpl_V is
component fir_hw_smpl_V_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
fir_hw_smpl_V_ram_U : component fir_hw_smpl_V_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0);
end architecture;
| gpl-2.0 | 4519597a37e54186b874c3820beca706 | 0.536832 | 3.510297 | false | false | false | false |
HackLinux/ION | src/rtl/buses/ion_tcm_data.vhdl | 1 | 5,572 | --------------------------------------------------------------------------------
-- ion_tcm_data.vhdl -- Tightly Coupled Memory for the data space.
--------------------------------------------------------------------------------
-- FIXME explain!
--
-- REFERENCES
-- [1] ion_design_notes.pdf -- ION project design notes.
--------------------------------------------------------------------------------
--
--
--------------------------------------------------------------------------------
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.ION_INTERFACES_PKG.all;
use work.ION_INTERNAL_PKG.all;
entity ION_TCM_DATA is
generic(
-- Size of TCM block in 32-bit words. Set to zero to disable TCM.
SIZE : integer := 4096;
-- Initial contents of TCM. Default is zeros.
INIT_DATA : t_obj_code := zero_objcode(16)
);
port(
CLK_I : in std_logic;
RESET_I : in std_logic;
EN_I : in std_logic;
MEM_MOSI_I : in t_cpumem_mosi;
MEM_MISO_O : out t_cpumem_miso
);
end;
architecture rtl of ION_TCM_DATA is
constant TCM_ADDR_SIZE : integer := log2(SIZE);
subtype t_tcm_address is std_logic_vector(TCM_ADDR_SIZE-1 downto 2);
signal tcm_addr : t_tcm_address;
signal tcm_rd_data : t_word;
signal tcm_rd_data0 : t_byte;
signal tcm_rd_data1 : t_byte;
signal tcm_rd_data2 : t_byte;
signal tcm_rd_data3 : t_byte;
signal wr_data0 : t_byte;
signal wr_data1 : t_byte;
signal wr_data2 : t_byte;
signal wr_data3 : t_byte;
signal tcm_ram0: t_byte_table(0 to ((SIZE/4)-1)) :=
objcode_to_btable(INIT_DATA, SIZE/4, 0);
signal tcm_ram1: t_byte_table(0 to ((SIZE/4)-1)) :=
objcode_to_btable(INIT_DATA, SIZE/4, 1);
signal tcm_ram2: t_byte_table(0 to ((SIZE/4)-1)) :=
objcode_to_btable(INIT_DATA, SIZE/4, 2);
signal tcm_ram3: t_byte_table(0 to ((SIZE/4)-1)) :=
objcode_to_btable(INIT_DATA, SIZE/4, 3);
begin
tcm_addr <= MEM_MOSI_I.addr(tcm_addr'high downto 2);
--------------------------------------------------------------------------------
---- Memory block inference.
-- We ned to implement the TCM as four independent blocks because it's not
-- possible to just infer a BRAM with byte enables. We just don't want to
-- instantiate vendor-specific BRAM entities.
tcm_memory_block0:
process(CLK_I)
begin
if (CLK_I'event and CLK_I='1') then
tcm_rd_data0 <= tcm_ram0(conv_integer(tcm_addr));
if MEM_MOSI_I.wr_be(0)='1' and EN_I='1' then
tcm_ram0(conv_integer(unsigned(tcm_addr))) <= wr_data0;
end if;
end if;
end process tcm_memory_block0;
tcm_memory_block1:
process(CLK_I)
begin
if (CLK_I'event and CLK_I='1') then
tcm_rd_data1 <= tcm_ram1(conv_integer(tcm_addr));
if MEM_MOSI_I.wr_be(1)='1' and EN_I='1' then
tcm_ram1(conv_integer(unsigned(tcm_addr))) <= wr_data1;
end if;
end if;
end process tcm_memory_block1;
tcm_memory_block2:
process(CLK_I)
begin
if (CLK_I'event and CLK_I='1') then
tcm_rd_data2 <= tcm_ram2(conv_integer(tcm_addr));
if MEM_MOSI_I.wr_be(2)='1' and EN_I='1' then
tcm_ram2(conv_integer(unsigned(tcm_addr))) <= wr_data2;
end if;
end if;
end process tcm_memory_block2;
tcm_memory_block3:
process(CLK_I)
begin
if (CLK_I'event and CLK_I='1') then
tcm_rd_data3 <= tcm_ram3(conv_integer(tcm_addr));
if MEM_MOSI_I.wr_be(3)='1' and EN_I='1' then
tcm_ram3(conv_integer(unsigned(tcm_addr))) <= wr_data3;
end if;
end if;
end process tcm_memory_block3;
wr_data0 <= MEM_MOSI_I.wr_data( 7 downto 0);
wr_data1 <= MEM_MOSI_I.wr_data(15 downto 8);
wr_data2 <= MEM_MOSI_I.wr_data(23 downto 16);
wr_data3 <= MEM_MOSI_I.wr_data(31 downto 24);
MEM_MISO_O.rd_data <= tcm_rd_data3 & tcm_rd_data2 & tcm_rd_data1 & tcm_rd_data0;
MEM_MISO_O.mwait <= '0';
end architecture rtl;
| lgpl-3.0 | e5e6f07a252375d874c27da63a3fea78 | 0.529074 | 3.611147 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/ICMP_TX.vhd | 1 | 14,002 | ----------------------------------------------------------------------------------
-- Company: NTU Athens - BNL
-- Engineer: Christos Bakalis ([email protected])
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Christos Bakalis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 03.02.2017
-- Design Name: ICMP Transmitter
-- Module Name: ICMP_TX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions: Vivado 2016.2
-- Description: Handles simple ICMP TX
--
-- Dependencies:
--
-- Changelog:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
entity ICMP_TX is
Port(
-- ICMP layer signals
icmp_tx_start : in std_logic; -- indicates req to tx ICMP
icmp_txi : in icmp_tx_type; -- icmp tx cxns
icmp_tx_data_out_ready : out std_logic; -- indicates icmp_tx is ready to take data
-- system signals
clk : in STD_LOGIC; -- same clock used to clock mac data and ip data
reset : in STD_LOGIC;
icmp_tx_is_idle : out STD_LOGIC;
-- IP layer TX signals
ip_tx_start : out std_logic;
ip_tx : out ipv4_tx_type; -- IP tx cxns
ip_tx_result : in std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : in std_logic -- indicates IP TX is ready to take data
);
end ICMP_TX;
architecture Behavioral of ICMP_TX is
type tx_state_type is (IDLE, PAUSE, SEND_ICMP_HDR, SEND_PAYLOAD);
type count_mode_type is (RST, INCR, HOLD);
type settable_cnt_type is (RST, SET, INCR, HOLD);
type set_clr_type is (SET, CLR, HOLD);
-- TX state variables
signal icmp_tx_state : tx_state_type;
signal tx_count : unsigned (15 downto 0);
signal ip_tx_start_reg : std_logic;
signal data_out_ready_reg : std_logic;
signal icmp_tx_is_idle_reg : std_logic;
-- tx control signals
signal next_tx_state : tx_state_type;
signal set_tx_state : std_logic;
signal tx_count_val : unsigned (15 downto 0);
signal tx_count_mode : settable_cnt_type;
signal tx_is_idle_state : set_clr_type;
signal tx_data : std_logic_vector (7 downto 0);
signal set_last : std_logic;
signal set_ip_tx_start : set_clr_type;
signal tx_data_valid : std_logic; -- indicates whether data is valid to tx or not
-- tx temp signals
signal total_length : std_logic_vector (15 downto 0); -- computed combinatorially from header size
-- ICMP datagram header format
--
-- 0 8 16 31
-- --------------------------------------------------------------------------------------------
-- | Type | Code | Checksum |
-- | | | |
-- --------------------------------------------------------------------------------------------
-- | Identifier | Sequence Number |
-- | | |
-- --------------------------------------------------------------------------------------------
-- | Payload |
-- | |
-- --------------------------------------------------------------------------------------------
-- | .... |
-- | |
-- --------------------------------------------------------------------------------------------
--
-- Type = 8 and Code = 0 (echo request)
-- Type = 0 and Code = 0 (echo reply)
begin
-----------------------------------------------------------------------
-- combinatorial process to implement FSM and determine control signals
-----------------------------------------------------------------------
tx_combinatorial : process(
-- input signals
icmp_tx_start, icmp_txi, clk, ip_tx_result, ip_tx_data_out_ready,
-- state variables
icmp_tx_state, tx_count, ip_tx_start_reg, data_out_ready_reg,
icmp_tx_is_idle_reg,
-- control signals
next_tx_state, set_tx_state, tx_count_mode, tx_count_val,
tx_data, set_last, total_length, set_ip_tx_start, tx_data_valid
)
begin
icmp_tx_is_idle <= icmp_tx_is_idle_reg;
-- set output followers
ip_tx_start <= ip_tx_start_reg;
ip_tx.hdr.protocol <= x"01"; -- ICMP protocol
ip_tx.hdr.data_length <= total_length;
ip_tx.hdr.dst_ip_addr <= icmp_txi.hdr.dst_ip_addr;
case icmp_tx_state is
when SEND_PAYLOAD =>
ip_tx.data.data_out <= icmp_txi.payload.data_out;
tx_data_valid <= icmp_txi.payload.data_out_valid;
ip_tx.data.data_out_last <= icmp_txi.payload.data_out_last;
when SEND_ICMP_HDR =>
ip_tx.data.data_out <= tx_data;
tx_data_valid <= ip_tx_data_out_ready;
ip_tx.data.data_out_last <= set_last;
when others =>
ip_tx.data.data_out <= (others => '0');
tx_data_valid <= '0';
ip_tx.data.data_out_last <= set_last;
end case;
ip_tx.data.data_out_valid <= tx_data_valid and ip_tx_data_out_ready;
-- set signal defaults
next_tx_state <= IDLE;
set_tx_state <= '0';
tx_count_mode <= HOLD;
tx_data <= x"00";
set_last <= '0';
set_ip_tx_start <= HOLD;
tx_is_idle_state <= SET;
tx_count_val <= (others => '0');
icmp_tx_data_out_ready <= '0';
-- set temp signals
total_length <= std_logic_vector(unsigned(icmp_txi.hdr.icmp_pay_len) + 8); -- total length = user data length + header length (bytes)
-- TX FSM
case icmp_tx_state is
when IDLE =>
icmp_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
tx_count_mode <= RST;
tx_is_idle_state <= SET;
if icmp_tx_start = '1' then
tx_count_mode <= RST;
set_ip_tx_start <= SET;
next_tx_state <= PAUSE;
set_tx_state <= '1';
end if;
when PAUSE =>
-- delay one clock for IP layer to respond to ip_tx_start and remove any tx error result
next_tx_state <= SEND_ICMP_HDR;
tx_is_idle_state <= CLR;
set_tx_state <= '1';
when SEND_ICMP_HDR =>
icmp_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
tx_is_idle_state <= HOLD;
if ip_tx_result = IPTX_RESULT_ERR then -- 10
set_ip_tx_start <= CLR;
next_tx_state <= IDLE;
set_tx_state <= '1';
elsif ip_tx_data_out_ready = '1' then
if tx_count = x"0007" then
tx_count_val <= x"0001";
tx_count_mode <= SET;
next_tx_state <= SEND_PAYLOAD;
set_tx_state <= '1';
else
tx_count_mode <= INCR;
end if;
case tx_count is
when x"0000" => tx_data <= icmp_txi.hdr.icmp_type (7 downto 0); -- type
when x"0001" => tx_data <= icmp_txi.hdr.icmp_code (7 downto 0); -- code
when x"0002" => tx_data <= icmp_txi.hdr.icmp_chksum (15 downto 8); -- checksum 1/2
when x"0003" => tx_data <= icmp_txi.hdr.icmp_chksum (7 downto 0); -- checksum 2/2
when x"0004" => tx_data <= icmp_txi.hdr.icmp_ident (15 downto 8); -- identifier 1/2
when x"0005" => tx_data <= icmp_txi.hdr.icmp_ident (7 downto 0); -- identifier 2/2
when x"0006" => tx_data <= icmp_txi.hdr.icmp_seqNum (15 downto 8); -- sequence number 1/2
when x"0007" => tx_data <= icmp_txi.hdr.icmp_seqNum (7 downto 0); -- sequence number 2/2
when others =>
end case;
end if;
when SEND_PAYLOAD =>
icmp_tx_data_out_ready <= ip_tx_data_out_ready; -- in this state, we can accept user data if IP TX rdy
if ip_tx_data_out_ready = '1' then
if icmp_txi.payload.data_out_valid = '1' or tx_count = x"000" then
-- only increment if ready and valid has been subsequently established, otherwise data count moves on too fast
if unsigned(tx_count) = unsigned(icmp_txi.hdr.icmp_pay_len) then
-- TX terminated due to count - end normally
set_last <= '1';
tx_data <= icmp_txi.payload.data_out;
set_ip_tx_start <= CLR;
next_tx_state <= IDLE;
set_tx_state <= '1';
elsif icmp_txi.payload.data_out_last = '1' then
-- terminate tx with error as got last from upstream before exhausting count
set_last <= '1';
tx_data <= icmp_txi.payload.data_out;
set_ip_tx_start <= CLR;
next_tx_state <= IDLE;
set_tx_state <= '1';
else
-- TX continues
tx_count_mode <= INCR;
tx_data <= icmp_txi.payload.data_out;
end if;
end if;
end if;
end case;
end process;
-----------------------------------------------------------------------------
-- sequential process to action control signals and change states and outputs
-----------------------------------------------------------------------------
tx_sequential : process (clk,reset,data_out_ready_reg)
begin
if rising_edge(clk) then
data_out_ready_reg <= ip_tx_data_out_ready;
else
data_out_ready_reg <= data_out_ready_reg;
end if;
if rising_edge(clk) then
if reset = '1' then
-- reset state variables
icmp_tx_state <= IDLE;
tx_count <= x"0000";
icmp_tx_is_idle_reg <= '0';
ip_tx_start_reg <= '0';
else
-- Next icmp_tx_state processing
if set_tx_state = '1' then
icmp_tx_state <= next_tx_state;
else
icmp_tx_state <= icmp_tx_state;
end if;
-- ip_tx_start_reg processing
case set_ip_tx_start is
when SET => ip_tx_start_reg <= '1';
when CLR => ip_tx_start_reg <= '0';
when HOLD => ip_tx_start_reg <= ip_tx_start_reg;
end case;
-- state signal to be used by reply processor
case tx_is_idle_state is
when SET => icmp_tx_is_idle_reg <= '1';
when CLR => icmp_tx_is_idle_reg <= '0';
when HOLD => icmp_tx_is_idle_reg <= icmp_tx_is_idle_reg;
end case;
-- tx_count processing
case tx_count_mode is
when RST => tx_count <= x"0000";
when SET => tx_count <= tx_count_val;
when INCR => tx_count <= tx_count + 1;
when HOLD => tx_count <= tx_count;
end case;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 65deb5b79b922c16b83dfb161e644019 | 0.42194 | 4.433819 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/MMFE8_1VMM/sources_1/imports/vmm_global_reset.vhd | 1 | 5,193 | ----------------------------------------------------------------------------------
-- Company: NTU ATHNENS - BNL
-- Engineer: Paris Moschovakos
--
-- Create Date:
-- Design Name:
-- Module Name:
-- Project Name: MMFE8
-- Target Devices: Arix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2016.2
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
--
-- global reset
-- -----
-- ENA ------- --------
-- ---------
-- WEN ----- ------
--
-- IEEE VHDL standard library:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_bit.all;
use IEEE.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity vmm_global_reset is
port( clk : in std_logic; -- 100MHz
rst : in std_logic; -- reset
gbl_rst : in std_logic ; -- from control register. a pulse
vmm_ena : out std_logic ; -- these will be ored with same from other sm
vmm_wen : out std_logic -- these will be ored with same from other sm
);
end vmm_global_reset ;
architecture beh of vmm_global_reset is
signal state_switch_count : std_logic_vector(31 downto 0) := x"00010000"; --fast
signal cfg_rst_ctr : std_logic_vector(31 downto 0) := x"00000000";
signal state_nxt : std_logic_vector(2 downto 0) ;
signal vmm_wen_int, vmm_ena_int : std_logic ;
signal gbl_rst_int, done_int : std_logic ;
attribute keep: boolean;
attribute keep of vmm_ena_int: signal is true;
attribute keep of vmm_wen_int: signal is true;
attribute keep of cfg_rst_ctr: signal is true;
begin
process( clk, rst, done_int, gbl_rst, gbl_rst_int)
begin
if( rst = '1' or done_int = '1') then
gbl_rst_int <= '0' ;
else
if( rising_edge( clk)) then --100MHz
if (gbl_rst = '1') then
gbl_rst_int <= '1' ;
end if ;
end if ;
end if ;
end process ;
process( clk, state_nxt, rst, gbl_rst_int, vmm_ena_int, vmm_wen_int)
begin
if ( rising_edge( clk)) then --100MHz
if (rst = '1') then
state_nxt <= (others=>'0') ;
done_int <= '0' ;
vmm_ena_int <= '0' ;
vmm_wen_int <= '0' ;
cfg_rst_ctr <= (others=>'0') ;
else
case state_nxt is
when "000" =>
vmm_wen_int <= '0' ;
vmm_ena_int <= '0' ;
done_int <= '0' ;
if (gbl_rst_int = '1') then
state_nxt <= "001" ;
cfg_rst_ctr <= (others=>'0') ;
else
state_nxt <= "000" ;
end if ;
when "001" =>
vmm_ena_int <= '0' ;
vmm_wen_int <= '1' ;
if (cfg_rst_ctr = state_switch_count) then
state_nxt <= "010" ;
cfg_rst_ctr <= (others=>'0') ;
else
state_nxt <= "001" ;
cfg_rst_ctr <= cfg_rst_ctr + '1';
end if ;
when "010" =>
vmm_ena_int <= '1' ;
vmm_wen_int <= '1' ;
if (cfg_rst_ctr = state_switch_count) then
state_nxt <= "011" ;
cfg_rst_ctr <= (others=>'0') ;
else
state_nxt <= "010" ;
cfg_rst_ctr <= cfg_rst_ctr + '1';
end if ;
when "011" =>
vmm_ena_int <= '0' ;
vmm_wen_int <= '1' ;
if (cfg_rst_ctr = state_switch_count) then
state_nxt <= "100" ;
cfg_rst_ctr <= (others=>'0') ;
else
state_nxt <= "011" ;
cfg_rst_ctr <= cfg_rst_ctr + '1';
end if ;
when "100" =>
vmm_ena_int <= '0' ;
vmm_wen_int <= '0' ;
state_nxt <= "000" ;
done_int <= '1' ;
when others => vmm_ena_int <= '0' ;
vmm_wen_int <= '0' ;
done_int <= '1' ;
state_nxt <= (others=>'0') ;
end case ;
end if ;
end if;
end process ;
vmm_wen <= vmm_wen_int ;
vmm_ena <= vmm_ena_int ;
end beh ;
| gpl-3.0 | 70e6e067b9ac8cef52a14a1d5b80a9ea | 0.379164 | 3.860967 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/sgmii_10_100_1000/ipcore_dir/temac_10_100_1000/example_design/fifo/temac_10_100_1000_tx_client_fifo.vhd | 2 | 66,963 | --------------------------------------------------------------------------------
-- Title : Transmitter FIFO with AxiStream interfaces
-- Version : 1.3
-- Project : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : temac_10_100_1000_tx_client_fifo.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2008 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This is a transmitter side FIFO for the design example
-- of the Tri-Mode Ethernet MAC core. AxiStream interfaces are used.
--
-- The FIFO is created from 2 Block RAMs of size 2048
-- words of 8-bits per word, giving a total frame memory capacity
-- of 4096 bytes.
--
-- Valid frame data received from the user interface is written
-- into the Block RAM on the tx_fifo_aclkk. The FIFO will store
-- frames up to 4kbytes in length. If larger frames are written
-- to the FIFO, the AxiStream interface will accept the rest of the
-- frame, but that frame will be dropped by the FIFO and the
-- overflow signal will be asserted.
--
-- The FIFO is designed to work with a minimum frame length of 14
-- bytes.
--
-- When there is at least one complete frame in the FIFO, the MAC
-- transmitter AxiStream interface will be driven to request frame
-- transmission by placing the first byte of the frame onto
-- tx_axis_mac_tdata and by asserting tx_axis_mac_tvalid. The MAC will later
-- respond by asserting tx_axis_mac_tready. At this point the remaining
-- frame data is read out of the FIFO subject to tx_axis_mac_tready.
-- Data is read out of the FIFO on the tx_mac_aclk.
--
-- If the generic FULL_DUPLEX_ONLY is set to false, the FIFO will
-- requeue and retransmit frames as requested by the MAC. Once a
-- frame has been transmitted by the FIFO it is stored until the
-- possible retransmit window for that frame has expired.
--
-- The FIFO has been designed to operate with different clocks
-- on the write and read sides. The write clock (user-side
-- AxiStream clock) can be an equal or faster frequency than the
-- read clock (MAC-side AxiStream clock). The minimum write clock
-- frequency is the read clock frequency divided by 2.
--
-- The FIFO memory size can be increased by expanding the rd_addr
-- and wr_addr signal widths, to address further BRAMs.
--
--------------------------------------------------------------------------------
library unimacro;
use unimacro.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
-- Entity declaration for the Transmitter FIFO
--------------------------------------------------------------------------------
entity temac_10_100_1000_tx_client_fifo is
generic (
FULL_DUPLEX_ONLY : boolean := false);
port (
-- User-side (write-side) AxiStream interface
tx_fifo_aclk : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tlast : in std_logic;
tx_axis_fifo_tready : out std_logic;
-- MAC-side (read-side) AxiStream interface
tx_mac_aclk : in std_logic;
tx_mac_resetn : in std_logic;
tx_axis_mac_tdata : out std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : out std_logic;
tx_axis_mac_tlast : out std_logic;
tx_axis_mac_tready : in std_logic;
tx_axis_mac_tuser : out std_logic;
-- FIFO status and overflow indication,
-- synchronous to write-side (tx_user_aclk) interface
fifo_overflow : out std_logic;
fifo_status : out std_logic_vector(3 downto 0);
-- FIFO collision and retransmission requests from MAC
tx_collision : in std_logic;
tx_retransmit : in std_logic
);
end temac_10_100_1000_tx_client_fifo;
architecture RTL of temac_10_100_1000_tx_client_fifo is
------------------------------------------------------------------------------
-- Component declaration for the synchronisation flip-flop pair
------------------------------------------------------------------------------
component temac_10_100_1000_sync_block
port (
clk : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Define internal signals
------------------------------------------------------------------------------
signal VCC : std_logic;
signal GND : std_logic_vector(0 downto 0);
signal GND_BUS : std_logic_vector(8 downto 0);
-- Encoded read state machine states.
type rd_state_typ is (IDLE_s,
QUEUE1_s,
QUEUE2_s,
QUEUE3_s,
START_DATA1_s,
DATA_PRELOAD1_s,
DATA_PRELOAD2_s,
WAIT_HANDSHAKE_s,
FRAME_s,
HANDSHAKE_s,
FINISH_s,
DROP_ERR_s,
DROP_s,
RETRANSMIT_ERR_s,
RETRANSMIT_s);
signal rd_state : rd_state_typ;
signal rd_nxt_state : rd_state_typ;
-- Encoded write state machine states,
type wr_state_typ is (WAIT_s,
DATA_s,
EOF_s,
OVFLOW_s);
signal wr_state : wr_state_typ;
signal wr_nxt_state : wr_state_typ;
type data_pipe is array (0 to 1) of std_logic_vector(7 downto 0);
type cntl_pipe is array (0 to 1) of std_logic;
signal wr_eof_data_bram : std_logic_vector(8 downto 0);
signal wr_data_bram : std_logic_vector(7 downto 0);
signal wr_data_pipe : data_pipe;
signal wr_sof_pipe : cntl_pipe;
signal wr_eof_pipe : cntl_pipe;
signal wr_accept_pipe : cntl_pipe;
signal wr_accept_bram : std_logic;
signal wr_sof_int : std_logic;
signal wr_eof_bram : std_logic_vector(0 downto 0);
signal wr_eof_reg : std_logic;
signal wr_addr : unsigned(11 downto 0);
signal wr_addr_inc : std_logic;
signal wr_start_addr_load : std_logic;
signal wr_addr_reload : std_logic;
signal wr_start_addr : unsigned(11 downto 0);
signal wr_fifo_full : std_logic;
signal wr_en : std_logic;
signal wr_en_u : std_logic;
signal wr_en_u_bram : std_logic_vector(0 downto 0);
signal wr_en_l : std_logic;
signal wr_en_l_bram : std_logic_vector(0 downto 0);
signal wr_ovflow_dst_rdy : std_logic;
signal tx_axis_fifo_tready_int_n : std_logic;
signal frame_in_fifo : std_logic;
signal rd_eof : std_logic;
signal rd_eof_pipe : std_logic;
signal rd_eof_reg : std_logic;
signal rd_addr : unsigned(11 downto 0);
signal rd_addr_inc : std_logic;
signal rd_addr_reload : std_logic;
signal rd_bram_u_unused : std_logic_vector(8 downto 0);
signal rd_bram_l_unused : std_logic_vector(8 downto 0);
signal rd_eof_data_bram_u : std_logic_vector(8 downto 0);
signal rd_eof_data_bram_l : std_logic_vector(8 downto 0);
signal rd_data_bram_u : std_logic_vector(7 downto 0);
signal rd_data_bram_l : std_logic_vector(7 downto 0);
signal rd_data_pipe_u : std_logic_vector(7 downto 0);
signal rd_data_pipe_l : std_logic_vector(7 downto 0);
signal rd_data_pipe : std_logic_vector(7 downto 0);
signal rd_eof_bram_u : std_logic_vector(0 downto 0);
signal rd_eof_bram_l : std_logic_vector(0 downto 0);
signal rd_en : std_logic;
signal rd_bram_u : std_logic;
signal rd_bram_u_reg : std_logic;
signal rd_addr_slv : std_logic_vector(10 downto 0);
signal wr_addr_slv : std_logic_vector(10 downto 0);
signal rd_tran_frame_tog : std_logic := '0';
signal wr_tran_frame_sync : std_logic;
signal wr_tran_frame_delay : std_logic := '0';
signal rd_retran_frame_tog : std_logic := '0';
signal wr_retran_frame_sync : std_logic;
signal wr_retran_frame_delay : std_logic := '0';
signal wr_store_frame : std_logic;
signal wr_eof_state : std_logic;
signal wr_eof_state_reg : std_logic;
signal wr_transmit_frame : std_logic;
signal wr_retransmit_frame : std_logic;
signal wr_frames : unsigned(8 downto 0);
signal wr_frame_in_fifo : std_logic;
signal rd_16_count : unsigned(3 downto 0);
signal rd_txfer_en : std_logic;
signal rd_addr_txfer : unsigned(11 downto 0);
signal rd_txfer_tog : std_logic := '0';
signal wr_txfer_tog_sync : std_logic;
signal wr_txfer_tog_delay : std_logic := '0';
signal wr_txfer_en : std_logic;
signal wr_rd_addr : unsigned(11 downto 0);
signal wr_addr_diff : unsigned(11 downto 0);
signal wr_fifo_status : unsigned(3 downto 0);
signal rd_drop_frame : std_logic;
signal rd_retransmit : std_logic;
signal rd_start_addr : unsigned(11 downto 0);
signal rd_start_addr_load : std_logic;
signal rd_start_addr_reload : std_logic;
signal rd_dec_addr : unsigned(11 downto 0);
signal rd_transmit_frame : std_logic;
signal rd_retransmit_frame : std_logic;
signal rd_col_window_expire : std_logic;
signal rd_col_window_pipe : cntl_pipe;
signal wr_col_window_pipe : cntl_pipe;
signal wr_fifo_overflow : std_logic;
signal rd_slot_timer : unsigned(9 downto 0);
signal wr_col_window_expire : std_logic;
signal rd_idle_state : std_logic;
signal tx_axis_mac_tdata_int_frame : std_logic_vector(7 downto 0);
signal tx_axis_mac_tdata_int_handshake : std_logic_vector(7 downto 0);
signal tx_axis_mac_tdata_int : std_logic_vector(7 downto 0);
signal tx_axis_mac_tvalid_int_finish : std_logic;
signal tx_axis_mac_tvalid_int_droperr : std_logic;
signal tx_axis_mac_tvalid_int_retransmiterr : std_logic;
signal tx_axis_mac_tlast_int_frame_handshake : std_logic;
signal tx_axis_mac_tlast_int_finish : std_logic;
signal tx_axis_mac_tlast_int_droperr : std_logic;
signal tx_axis_mac_tlast_int_retransmiterr : std_logic;
signal tx_axis_mac_tuser_int_droperr : std_logic;
signal tx_axis_mac_tuser_int_retransmit : std_logic;
signal tx_fifo_reset : std_logic;
signal tx_mac_reset : std_logic;
-- Small delay for simulation purposes.
constant dly : time := 1 ps;
------------------------------------------------------------------------------
-- Attributes for FIFO simulation and synthesis
------------------------------------------------------------------------------
-- ASYNC_REG attributes added to simulate actual behaviour under
-- asynchronous operating conditions.
attribute ASYNC_REG : string;
attribute ASYNC_REG of wr_rd_addr : signal is "TRUE";
attribute ASYNC_REG of wr_col_window_pipe : signal is "TRUE";
------------------------------------------------------------------------------
-- Begin FIFO architecture
------------------------------------------------------------------------------
begin
VCC <= '1';
GND <= (others => '0');
GND_BUS <= (others => '0');
-- invert reset sense as architecture is optimised for active high resets
tx_fifo_reset <= not tx_fifo_resetn;
tx_mac_reset <= not tx_mac_resetn;
------------------------------------------------------------------------------
-- Write state machine and control
------------------------------------------------------------------------------
-- Write state machine.
-- States are WAIT, DATA, EOF, OVFLOW.
-- Clock state to next state.
clock_wrs_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
if tx_fifo_reset = '1' then
wr_state <= WAIT_s after dly;
else
wr_state <= wr_nxt_state after dly;
end if;
end if;
end process clock_wrs_p;
-- Decode next state, combinitorial.
next_wrs_p : process(wr_state, wr_sof_pipe(1), wr_eof_pipe(0), wr_eof_pipe(1),
wr_eof_bram(0), wr_fifo_overflow)
begin
case wr_state is
when WAIT_s =>
if wr_sof_pipe(1) = '1' and wr_eof_pipe(1) = '0' then
wr_nxt_state <= DATA_s;
else
wr_nxt_state <= WAIT_s;
end if;
when DATA_s =>
-- Wait for the end of frame to be detected.
if wr_fifo_overflow = '1' and wr_eof_pipe(0) = '0'
and wr_eof_pipe(1) = '0' then
wr_nxt_state <= OVFLOW_s;
elsif wr_eof_pipe(1) = '1' then
wr_nxt_state <= EOF_s;
else
wr_nxt_state <= DATA_s;
end if;
when EOF_s =>
-- If the start of frame is already in the pipe, a back-to-back frame
-- transmission has occured. Move straight back to frame state.
if wr_sof_pipe(1) = '1' and wr_eof_pipe(1) = '0' then
wr_nxt_state <= DATA_s;
elsif wr_eof_bram(0) = '1' then
wr_nxt_state <= WAIT_s;
else
wr_nxt_state <= EOF_s;
end if;
when OVFLOW_s =>
-- Wait until the end of frame is reached before clearing the overflow.
if wr_eof_bram(0) = '1' then
wr_nxt_state <= WAIT_s;
else
wr_nxt_state <= OVFLOW_s;
end if;
when others =>
wr_nxt_state <= WAIT_s;
end case;
end process;
-- Decode output signals, combinatorial.
-- wr_en is used to enable the BRAM write and the address to increment.
wr_en <= '0' when wr_state = OVFLOW_s else wr_accept_bram;
-- The upper and lower signals are used to distinguish between the upper and
-- lower BRAMs.
wr_en_l <= wr_en and not(wr_addr(11));
wr_en_u <= wr_en and wr_addr(11);
wr_en_l_bram(0) <= wr_en_l;
wr_en_u_bram(0) <= wr_en_u;
wr_addr_inc <= wr_en;
wr_addr_reload <= '1' when wr_state = OVFLOW_s else '0';
wr_start_addr_load <= '1' when wr_state = EOF_s and wr_nxt_state = WAIT_s
else
'1' when wr_state = EOF_s and wr_nxt_state = DATA_s
else '0';
-- Pause the AxiStream handshake when the FIFO is full.
tx_axis_fifo_tready_int_n <= wr_ovflow_dst_rdy when wr_state = OVFLOW_s
else wr_fifo_full;
tx_axis_fifo_tready <= not tx_axis_fifo_tready_int_n;
-- Generate user overflow indicator.
fifo_overflow <= '1' when wr_state = OVFLOW_s else '0';
-- When in overflow and have captured ovflow EOF, set tx_axis_fifo_tready again.
p_ovflow_dst_rdy : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_ovflow_dst_rdy <= '0' after dly;
else
if wr_fifo_overflow = '1' and wr_state = DATA_s then
wr_ovflow_dst_rdy <= '0' after dly;
elsif tx_axis_fifo_tvalid = '1' and tx_axis_fifo_tlast = '1' then
wr_ovflow_dst_rdy <= '1' after dly;
end if;
end if;
end if;
end process;
-- EOF signals for use in overflow logic.
wr_eof_state <= '1' when wr_state = EOF_s else '0';
p_reg_eof_st : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_eof_state_reg <= '0' after dly;
else
wr_eof_state_reg <= wr_eof_state after dly;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- Read state machine and control
------------------------------------------------------------------------------
-- Read state machine.
-- States are IDLE, QUEUE1, QUEUE2, QUEUE3, QUEUE_ACK, WAIT_ACK, FRAME,
-- HANDSHAKE, FINISH, DROP_ERR, DROP, RETRANSMIT_ERR, RETRANSMIT.
-- Clock state to next state.
clock_rds_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_state <= IDLE_s after dly;
else
rd_state <= rd_nxt_state after dly;
end if;
end if;
end process clock_rds_p;
------------------------------------------------------------------------------
-- Full duplex-only state machine.
gen_fd_sm : if (FULL_DUPLEX_ONLY = TRUE) generate
-- Decode next state, combinatorial.
next_rds_p : process(rd_state, frame_in_fifo, rd_eof, rd_eof_reg, tx_axis_mac_tready)
begin
case rd_state is
when IDLE_s =>
-- If there is a frame in the FIFO, start to queue the new frame
-- to the output.
if frame_in_fifo = '1' then
rd_nxt_state <= QUEUE1_s;
else
rd_nxt_state <= IDLE_s;
end if;
-- Load the output pipeline, which takes three clock cycles.
when QUEUE1_s =>
rd_nxt_state <= QUEUE2_s;
when QUEUE2_s =>
rd_nxt_state <= QUEUE3_s;
when QUEUE3_s =>
rd_nxt_state <= START_DATA1_s;
when START_DATA1_s =>
-- The pipeline is full and the frame output starts now.
rd_nxt_state <= DATA_PRELOAD1_s;
when DATA_PRELOAD1_s =>
-- Await the tx_axis_mac_tready acknowledge before moving on.
if tx_axis_mac_tready = '1' then
rd_nxt_state <= FRAME_s;
else
rd_nxt_state <= DATA_PRELOAD1_s;
end if;
when FRAME_s =>
-- Read the frame out of the FIFO. If the MAC deasserts
-- tx_axis_mac_tready, stall in the handshake state. If the EOF
-- flag is encountered, move to the finish state.
if tx_axis_mac_tready = '0' then
rd_nxt_state <= HANDSHAKE_s;
elsif rd_eof = '1' then
rd_nxt_state <= FINISH_s;
else
rd_nxt_state <= FRAME_s;
end if;
when HANDSHAKE_s =>
-- Await tx_axis_mac_tready before continuing frame transmission.
-- If the EOF flag is encountered, move to the finish state.
if tx_axis_mac_tready = '1' and rd_eof_reg = '1' then
rd_nxt_state <= FINISH_s;
elsif tx_axis_mac_tready = '1' and rd_eof_reg = '0' then
rd_nxt_state <= FRAME_s;
else
rd_nxt_state <= HANDSHAKE_s;
end if;
when FINISH_s =>
-- Frame has finished. Assure that the MAC has accepted the final
-- byte by transitioning to idle only when tx_axis_mac_tready is high.
if tx_axis_mac_tready = '1' then
rd_nxt_state <= IDLE_s;
else
rd_nxt_state <= FINISH_s;
end if;
when others =>
rd_nxt_state <= IDLE_s;
end case;
end process next_rds_p;
end generate gen_fd_sm;
------------------------------------------------------------------------------
-- Full and half duplex state machine.
gen_hd_sm : if (FULL_DUPLEX_ONLY = FALSE) generate
-- Decode the next state, combinatorial.
next_rds_p : process(rd_state, frame_in_fifo, rd_eof_reg, tx_axis_mac_tready,
rd_drop_frame, rd_retransmit)
begin
case rd_state is
when IDLE_s =>
-- If a retransmit request is detected then prepare to retransmit.
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
-- If there is a frame in the FIFO, then queue the new frame to
-- the output.
elsif frame_in_fifo = '1' then
rd_nxt_state <= QUEUE1_s;
else
rd_nxt_state <= IDLE_s;
end if;
-- Load the output pipeline, which takes three clock cycles.
when QUEUE1_s =>
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
else
rd_nxt_state <= QUEUE2_s;
end if;
when QUEUE2_s =>
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
else
rd_nxt_state <= QUEUE3_s;
end if;
when QUEUE3_s =>
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
else
rd_nxt_state <= START_DATA1_s;
end if;
when START_DATA1_s =>
-- The pipeline is full and the frame output starts now.
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
else
rd_nxt_state <= DATA_PRELOAD1_s;
end if;
when DATA_PRELOAD1_s =>
-- Await the tx_axis_mac_tready acknowledge before moving on.
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
elsif tx_axis_mac_tready = '1' then
rd_nxt_state <= DATA_PRELOAD2_s;
else
rd_nxt_state <= DATA_PRELOAD1_s;
end if;
when DATA_PRELOAD2_s =>
-- If a collision-only request, then must drop the rest of the
-- current frame. If collision and retransmit, then prepare
-- to retransmit the frame.
if rd_drop_frame = '1' then
rd_nxt_state <= DROP_ERR_s;
elsif rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
-- Read the frame out of the FIFO. If the MAC deasserts
-- tx_axis_mac_tready, stall in the handshake state. If the EOF
-- flag is encountered, move to the finish state.
elsif tx_axis_mac_tready = '0' then
rd_nxt_state <= WAIT_HANDSHAKE_s;
elsif rd_eof_reg = '1' then
rd_nxt_state <= FINISH_s;
else
rd_nxt_state <= DATA_PRELOAD2_s;
end if;
when WAIT_HANDSHAKE_s =>
-- Await tx_axis_mac_tready before continuing frame transmission.
-- If the EOF flag is encountered, move to the finish state.
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
elsif tx_axis_mac_tready = '1' and rd_eof_reg = '1' then
rd_nxt_state <= FINISH_s;
elsif tx_axis_mac_tready = '1' and rd_eof_reg = '0' then
rd_nxt_state <= FRAME_s;
else
rd_nxt_state <= WAIT_HANDSHAKE_s;
end if;
when FRAME_s =>
-- If a collision-only request, then must drop the rest of the
-- current frame. If a collision and retransmit, then prepare
-- to retransmit the frame.
if rd_drop_frame = '1' then
rd_nxt_state <= DROP_ERR_s;
elsif rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
-- Read the frame out of the FIFO. If the MAC deasserts
-- tx_axis_mac_tready, stall in the handshake state. If the EOF
-- flag is encountered, move to the finish state.
elsif tx_axis_mac_tready = '0' then
rd_nxt_state <= HANDSHAKE_s;
elsif rd_eof_reg = '1' then
rd_nxt_state <= FINISH_s;
else
rd_nxt_state <= FRAME_s;
end if;
when HANDSHAKE_s =>
-- Await tx_axis_mac_tready before continuing frame transmission.
-- If the EOF flag is encountered, move to the finish state.
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
elsif tx_axis_mac_tready = '1' and rd_eof_reg = '1' then
rd_nxt_state <= FINISH_s;
elsif tx_axis_mac_tready = '1' and rd_eof_reg = '0' then
rd_nxt_state <= FRAME_s;
else
rd_nxt_state <= HANDSHAKE_s;
end if;
when FINISH_s =>
-- Frame has finished. Assure that the MAC has accepted the final
-- byte by transitioning to idle only when tx_axis_mac_tready is high.
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
elsif tx_axis_mac_tready = '1' then
rd_nxt_state <= IDLE_s;
else
rd_nxt_state <= FINISH_s;
end if;
when DROP_ERR_s =>
-- FIFO is ready to drop the frame. Assure that the MAC has
-- accepted the final byte and err signal before dropping.
if tx_axis_mac_tready = '1' then
rd_nxt_state <= DROP_s;
else
rd_nxt_state <= DROP_ERR_s;
end if;
when DROP_s =>
-- Wait until rest of frame has been cleared.
if rd_eof_reg = '1' then
rd_nxt_state <= IDLE_s;
else
rd_nxt_state <= DROP_s;
end if;
when RETRANSMIT_ERR_s =>
-- FIFO is ready to retransmit the frame. Assure that the MAC has
-- accepted the final byte and err signal before retransmitting.
if tx_axis_mac_tready = '1' then
rd_nxt_state <= RETRANSMIT_s;
else
rd_nxt_state <= RETRANSMIT_ERR_s;
end if;
when RETRANSMIT_s =>
-- Reload the data pipeline from the start of the frame.
rd_nxt_state <= QUEUE1_s;
when others =>
rd_nxt_state <= IDLE_s;
end case;
end process next_rds_p;
end generate gen_hd_sm;
-- Combinatorially select tdata candidates.
tx_axis_mac_tdata_int_frame <= tx_axis_mac_tdata_int when rd_nxt_state = HANDSHAKE_s or rd_nxt_state = WAIT_HANDSHAKE_s
else rd_data_pipe;
tx_axis_mac_tdata_int_handshake <= rd_data_pipe when rd_nxt_state = FINISH_s
else tx_axis_mac_tdata_int;
tx_axis_mac_tdata <= tx_axis_mac_tdata_int;
-- Decode output tdata based on current and next read state.
rd_data_decode_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if rd_nxt_state = FRAME_s or rd_nxt_state = DATA_PRELOAD2_s then
tx_axis_mac_tdata_int <= rd_data_pipe after dly;
elsif (rd_nxt_state = RETRANSMIT_ERR_s or rd_nxt_state = DROP_ERR_s)
then tx_axis_mac_tdata_int <= tx_axis_mac_tdata_int after dly;
else
case rd_state is
when START_DATA1_s =>
tx_axis_mac_tdata_int <= rd_data_pipe after dly;
when FRAME_s | DATA_PRELOAD2_s =>
tx_axis_mac_tdata_int <= tx_axis_mac_tdata_int_frame after dly;
when HANDSHAKE_s | WAIT_HANDSHAKE_s =>
tx_axis_mac_tdata_int <= tx_axis_mac_tdata_int_handshake after dly;
when others =>
tx_axis_mac_tdata_int <= tx_axis_mac_tdata_int after dly;
end case;
end if;
end if;
end process rd_data_decode_p;
-- Combinatorially select tvalid candidates.
tx_axis_mac_tvalid_int_finish <= '0' when rd_nxt_state = IDLE_s
else '1';
tx_axis_mac_tvalid_int_droperr <= '0' when rd_nxt_state = DROP_s
else '1';
tx_axis_mac_tvalid_int_retransmiterr <= '0' when rd_nxt_state = RETRANSMIT_s
else '1';
-- Decode output tvalid based on current and next read state.
rd_dv_decode_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if rd_nxt_state = FRAME_s or rd_nxt_state = DATA_PRELOAD2_s then
tx_axis_mac_tvalid <= '1' after dly;
elsif (rd_nxt_state = RETRANSMIT_ERR_s or rd_nxt_state = DROP_ERR_s)
then tx_axis_mac_tvalid <= '1' after dly;
else
case rd_state is
when START_DATA1_s =>
tx_axis_mac_tvalid <= '1' after dly;
when DATA_PRELOAD1_s =>
tx_axis_mac_tvalid <= '1' after dly;
when FRAME_s | DATA_PRELOAD2_s =>
tx_axis_mac_tvalid <= '1' after dly;
when HANDSHAKE_s | WAIT_HANDSHAKE_s =>
tx_axis_mac_tvalid <= '1' after dly;
when FINISH_s =>
tx_axis_mac_tvalid <= tx_axis_mac_tvalid_int_finish after dly;
when DROP_ERR_s =>
tx_axis_mac_tvalid <= tx_axis_mac_tvalid_int_droperr after dly;
when RETRANSMIT_ERR_s =>
tx_axis_mac_tvalid <= tx_axis_mac_tvalid_int_retransmiterr after dly;
when others =>
tx_axis_mac_tvalid <= '0' after dly;
end case;
end if;
end if;
end process rd_dv_decode_p;
-- Combinatorially select tlast candidates.
tx_axis_mac_tlast_int_frame_handshake <= rd_eof_reg when rd_nxt_state = FINISH_s
else '0';
tx_axis_mac_tlast_int_finish <= '0' when rd_nxt_state = IDLE_s
else rd_eof_reg;
tx_axis_mac_tlast_int_droperr <= '0' when rd_nxt_state = DROP_s
else '1';
tx_axis_mac_tlast_int_retransmiterr <= '0' when rd_nxt_state = RETRANSMIT_s
else '1';
-- Decode output tlast based on current and next read state.
rd_last_decode_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if rd_nxt_state = FRAME_s or rd_nxt_state = DATA_PRELOAD2_s then
tx_axis_mac_tlast <= rd_eof after dly;
elsif (rd_nxt_state = RETRANSMIT_ERR_s or rd_nxt_state = DROP_ERR_s)
then tx_axis_mac_tlast <= '1' after dly;
else
case rd_state is
when DATA_PRELOAD1_s =>
tx_axis_mac_tlast <= rd_eof after dly;
when FRAME_s | DATA_PRELOAD2_s =>
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_frame_handshake after dly;
when HANDSHAKE_s | WAIT_HANDSHAKE_s =>
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_frame_handshake after dly;
when FINISH_s =>
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_finish after dly;
when DROP_ERR_s =>
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_droperr after dly;
when RETRANSMIT_ERR_s =>
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_retransmiterr after dly;
when others =>
tx_axis_mac_tlast <= '0' after dly;
end case;
end if;
end if;
end process rd_last_decode_p;
-- Combinatorially select tuser candidates.
tx_axis_mac_tuser_int_droperr <= '0' when rd_nxt_state = DROP_s
else '1';
tx_axis_mac_tuser_int_retransmit <= '0' when rd_nxt_state = RETRANSMIT_s
else '1';
-- Decode output tuser based on current and next read state.
rd_user_decode_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if (rd_nxt_state = RETRANSMIT_ERR_s or rd_nxt_state = DROP_ERR_s)
then tx_axis_mac_tuser <= '1' after dly;
else
case rd_state is
when DROP_ERR_s =>
tx_axis_mac_tuser <= tx_axis_mac_tuser_int_droperr after dly;
when RETRANSMIT_ERR_s =>
tx_axis_mac_tuser <= tx_axis_mac_tuser_int_retransmit after dly;
when others =>
tx_axis_mac_tuser <= '0' after dly;
end case;
end if;
end if;
end process rd_user_decode_p;
------------------------------------------------------------------------------
-- Decode full duplex-only control signals.
gen_fd_decode : if (FULL_DUPLEX_ONLY = TRUE) generate
-- rd_en is used to enable the BRAM read and load the output pipeline.
rd_en <= '0' when rd_state = IDLE_s else
'1' when rd_nxt_state = FRAME_s else
'0' when (rd_state = FRAME_s and rd_nxt_state = HANDSHAKE_s) else
'0' when rd_nxt_state = HANDSHAKE_s else
'0' when rd_state = FINISH_s else
'0' when rd_state = DATA_PRELOAD1_s else '1';
-- When the BRAM is being read, enable the read address to be incremented.
rd_addr_inc <= rd_en;
rd_addr_reload <= '1' when rd_state /= FINISH_s and rd_nxt_state = FINISH_s
else '0';
-- Transmit frame pulse must never be more frequent than once per 64 clocks to
-- allow toggle to cross clock domain.
rd_transmit_frame <= '1' when rd_state = DATA_PRELOAD1_s and rd_nxt_state = FRAME_s
else '0';
-- Unused for full duplex only.
rd_start_addr_reload <= '0';
rd_start_addr_load <= '0';
rd_retransmit_frame <= '0';
end generate gen_fd_decode;
------------------------------------------------------------------------------
-- Decode full and half duplex control signals.
gen_hd_decode : if (FULL_DUPLEX_ONLY = FALSE) generate
-- rd_en is used to enable the BRAM read and load the output pipeline.
rd_en <= '0' when rd_state = IDLE_s else
'0' when rd_nxt_state = DROP_ERR_s else
'0' when (rd_nxt_state = DROP_s and rd_eof = '1') else
'1' when rd_nxt_state = FRAME_s or rd_nxt_state = DATA_PRELOAD2_s else
'0' when (rd_state = DATA_PRELOAD2_s and rd_nxt_state = WAIT_HANDSHAKE_s) else
'0' when (rd_state = FRAME_s and rd_nxt_state = HANDSHAKE_s) else
'0' when (rd_nxt_state = HANDSHAKE_s or rd_nxt_state = WAIT_HANDSHAKE_s) else
'0' when rd_state = FINISH_s else
'0' when rd_state = RETRANSMIT_ERR_s else
'0' when rd_state = RETRANSMIT_s else
'0' when rd_state = DATA_PRELOAD1_s else '1';
-- When the BRAM is being read, enable the read address to be incremented.
rd_addr_inc <= rd_en;
rd_addr_reload <= '1' when rd_state /= FINISH_s and rd_nxt_state = FINISH_s
else
'1' when rd_state = DROP_s and rd_nxt_state = IDLE_s
else '0';
-- Assertion indicates that the starting address must be reloaded to enable
-- the current frame to be retransmitted.
rd_start_addr_reload <= '1' when rd_state = RETRANSMIT_s else '0';
rd_start_addr_load <= '1' when rd_state= WAIT_HANDSHAKE_s and rd_nxt_state = FRAME_s
else
'1' when rd_col_window_expire = '1' else '0';
-- Transmit frame pulse must never be more frequent than once per 64 clocks to
-- allow toggle to cross clock domain.
rd_transmit_frame <= '1' when rd_state = WAIT_HANDSHAKE_s and rd_nxt_state = FRAME_s
else '0';
-- Retransmit frame pulse must never be more frequent than once per 16 clocks
-- to allow toggle to cross clock domain.
rd_retransmit_frame <= '1' when rd_state = RETRANSMIT_s else '0';
end generate gen_hd_decode; -- half duplex control signals
------------------------------------------------------------------------------
-- Frame count
-- We need to maintain a count of frames in the FIFO, so that we know when a
-- frame is available for transmission. The counter must be held on the write
-- clock domain as this is the faster clock if they differ.
------------------------------------------------------------------------------
-- A frame has been written to the FIFO.
wr_store_frame <= '1' when wr_state = EOF_s and wr_nxt_state /= EOF_s
else '0';
-- Generate a toggle to indicate when a frame has been transmitted by the FIFO.
p_rd_trans_tog : process (tx_mac_aclk)
begin
if tx_mac_aclk'event and tx_mac_aclk = '1' then
if rd_transmit_frame = '1' then
rd_tran_frame_tog <= not rd_tran_frame_tog after dly;
end if;
end if;
end process;
-- Synchronize the read transmit frame signal into the write clock domain.
resync_rd_tran_frame_tog : temac_10_100_1000_sync_block
port map (
clk => tx_fifo_aclk,
data_in => rd_tran_frame_tog,
data_out => wr_tran_frame_sync
);
-- Edge-detect of the resynchronized transmit frame signal.
p_delay_wr_trans : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
wr_tran_frame_delay <= wr_tran_frame_sync after dly;
end if;
end process p_delay_wr_trans;
p_sync_wr_trans : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_transmit_frame <= '0' after dly;
else
-- Edge detector
if (wr_tran_frame_delay xor wr_tran_frame_sync) = '1' then
wr_transmit_frame <= '1' after dly;
else
wr_transmit_frame <= '0' after dly;
end if;
end if;
end if;
end process p_sync_wr_trans;
------------------------------------------------------------------------------
-- Full duplex-only frame count.
gen_fd_count : if (FULL_DUPLEX_ONLY = TRUE) generate
-- Count the number of frames in the FIFO. The counter is incremented when a
-- frame is stored and decremented when a frame is transmitted. Need to keep
-- the counter on the write clock as this is the fastest clock if they differ.
p_wr_frames : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_frames <= (others => '0') after dly;
else
if (wr_store_frame and not wr_transmit_frame) = '1' then
wr_frames <= wr_frames + 1 after dly;
elsif (not wr_store_frame and wr_transmit_frame) = '1' then
wr_frames <= wr_frames - 1 after dly;
end if;
end if;
end if;
end process p_wr_frames;
end generate gen_fd_count;
------------------------------------------------------------------------------
-- Full and half duplex frame count.
gen_hd_count : if (FULL_DUPLEX_ONLY = FALSE) generate
-- Generate a toggle to indicate when a frame has been retransmitted from
-- the FIFO.
p_rd_retran_tog : process (tx_mac_aclk)
begin
if tx_mac_aclk'event and tx_mac_aclk = '1' then
if rd_retransmit_frame = '1' then
rd_retran_frame_tog <= not rd_retran_frame_tog after dly;
end if;
end if;
end process;
-- Synchronize the read retransmit frame signal into the write clock domain.
resync_rd_tran_frame_tog : temac_10_100_1000_sync_block
port map (
clk => tx_fifo_aclk,
data_in => rd_retran_frame_tog,
data_out => wr_retran_frame_sync
);
-- Edge detect of the resynchronized read transmit frame signal.
p_delay_wr_trans : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
wr_retran_frame_delay <= wr_retran_frame_sync after dly;
end if;
end process p_delay_wr_trans;
p_sync_wr_trans : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_retransmit_frame <= '0' after dly;
else
-- Edge detector
if (wr_retran_frame_delay xor wr_retran_frame_sync) = '1' then
wr_retransmit_frame <= '1' after dly;
else
wr_retransmit_frame <= '0' after dly;
end if;
end if;
end if;
end process p_sync_wr_trans;
-- Count the number of frames in the FIFO. The counter is incremented when a
-- frame is stored or retransmitted and decremented when a frame is
-- transmitted. Need to keep the counter on the write clock as this is the
-- fastest clock if they differ. Logic assumes transmit and retransmit cannot
-- happen at same time.
p_wr_frames : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_frames <= (others => '0') after dly;
else
if (wr_store_frame and wr_retransmit_frame) = '1' then
wr_frames <= wr_frames + 2 after dly;
elsif ((wr_store_frame or wr_retransmit_frame)
and not wr_transmit_frame) = '1' then
wr_frames <= wr_frames + 1 after dly;
elsif (wr_transmit_frame and not wr_store_frame) = '1' then
wr_frames <= wr_frames - 1 after dly;
end if;
end if;
end if;
end process p_wr_frames;
end generate gen_hd_count;
-- Generate a frame in FIFO signal for use in control logic.
p_wr_avail : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_frame_in_fifo <= '0' after dly;
else
if wr_frames /= (wr_frames'range => '0') then
wr_frame_in_fifo <= '1' after dly;
else
wr_frame_in_fifo <= '0' after dly;
end if;
end if;
end if;
end process p_wr_avail;
-- Synchronize it back onto read domain for use in the read logic.
resync_wr_frame_in_fifo : temac_10_100_1000_sync_block
port map (
clk => tx_mac_aclk,
data_in => wr_frame_in_fifo,
data_out => frame_in_fifo
);
------------------------------------------------------------------------------
-- Address counters
------------------------------------------------------------------------------
-- Write address is incremented when write enable signal has been asserted
wr_addr_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
if tx_fifo_reset = '1' then
wr_addr <= (others => '0') after dly;
elsif wr_addr_reload = '1' then
wr_addr <= wr_start_addr after dly;
elsif wr_addr_inc = '1' then
wr_addr <= wr_addr + 1 after dly;
end if;
end if;
end process wr_addr_p;
-- Store the start address in case the address must be reset.
wr_staddr_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
if tx_fifo_reset = '1' then
wr_start_addr <= (others => '0') after dly;
elsif wr_start_addr_load = '1' then
wr_start_addr <= wr_addr + 1 after dly;
end if;
end if;
end process wr_staddr_p;
------------------------------------------------------------------------------
-- Half duplex-only read address counters.
gen_fd_addr : if (FULL_DUPLEX_ONLY = TRUE) generate
-- Read address is incremented when read enable signal has been asserted.
rd_addr_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_addr <= (others => '0') after dly;
else
if rd_addr_reload = '1' then
rd_addr <= rd_dec_addr after dly;
elsif rd_addr_inc = '1' then
rd_addr <= rd_addr + 1 after dly;
end if;
end if;
end if;
end process rd_addr_p;
-- Do not need to keep a start address, but the address is needed to
-- calculate FIFO occupancy.
rd_start_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_start_addr <= (others => '0') after dly;
else
rd_start_addr <= rd_addr after dly;
end if;
end if;
end process rd_start_p;
end generate gen_fd_addr;
------------------------------------------------------------------------------
-- Full and half duplex read address counters
gen_hd_addr : if (FULL_DUPLEX_ONLY = FALSE) generate
-- Read address is incremented when read enable signal has been asserted.
rd_addr_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_addr <= (others => '0') after dly;
else
if rd_addr_reload = '1' then
rd_addr <= rd_dec_addr after dly;
elsif rd_start_addr_reload = '1' then
rd_addr <= rd_start_addr after dly;
elsif rd_addr_inc = '1' then
rd_addr <= rd_addr + 1 after dly;
end if;
end if;
end if;
end process rd_addr_p;
rd_staddr_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_start_addr <= (others => '0') after dly;
else
if rd_start_addr_load = '1' then
rd_start_addr <= rd_addr - 6 after dly;
end if;
end if;
end if;
end process rd_staddr_p;
-- Collision window expires after MAC has been transmitting for required slot
-- time. This is 512 clock cycles at 1Gbps. Also if the end of frame has fully
-- been transmitted by the MAC then a collision cannot occur. This collision
-- expiration signal goes high at 768 cycles from the start of the frame.
-- This is inefficient for short frames, however it should be enough to
-- prevent the FIFO from locking up.
rd_col_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_col_window_expire <= '0' after dly;
else
if rd_transmit_frame = '1' then
rd_col_window_expire <= '0' after dly;
elsif rd_slot_timer(9 downto 7) = "110" then
rd_col_window_expire <= '1' after dly;
end if;
end if;
end if;
end process;
rd_idle_state <= '1' when rd_state = IDLE_s else '0';
rd_colreg_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
rd_col_window_pipe(0) <= rd_col_window_expire
and rd_idle_state after dly;
if rd_txfer_en = '1' then
rd_col_window_pipe(1) <= rd_col_window_pipe(0) after dly;
end if;
end if;
end process;
rd_slot_time_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
-- Will not count until after the first frame is sent.
if tx_mac_reset = '1' then
rd_slot_timer <= "1111111111" after dly;
else
-- Reset counter.
if rd_transmit_frame = '1' then
rd_slot_timer <= (others => '0') after dly;
-- Do not allow counter to roll over, and
-- only count when frame is being transmitted.
elsif rd_slot_timer /= "1111111111" then
rd_slot_timer <= rd_slot_timer + 1 after dly;
end if;
end if;
end if;
end process;
end generate gen_hd_addr;
-- Read address generation
rd_decaddr_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_dec_addr <= (others => '0') after dly;
else
if rd_addr_inc = '1' then
rd_dec_addr <= rd_addr - 1 after dly;
end if;
end if;
end if;
end process rd_decaddr_p;
-- Which BRAM is read from is dependant on the upper bit of the address
-- space. This needs to be registered to give the correct timing.
rd_bram_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_bram_u <= '0' after dly;
rd_bram_u_reg <= '0' after dly;
else
if rd_addr_inc = '1' then
rd_bram_u <= rd_addr(11) after dly;
rd_bram_u_reg <= rd_bram_u after dly;
end if;
end if;
end if;
end process rd_bram_p;
------------------------------------------------------------------------------
-- Data pipelines
------------------------------------------------------------------------------
-- Register data inputs to BRAM.
-- No resets to allow for SRL16 target.
reg_din_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
wr_data_pipe(0) <= tx_axis_fifo_tdata after dly;
if wr_accept_pipe(0) = '1' then
wr_data_pipe(1) <= wr_data_pipe(0) after dly;
end if;
if wr_accept_pipe(1) = '1' then
wr_data_bram <= wr_data_pipe(1) after dly;
end if;
end if;
end process reg_din_p;
-- Start of frame set when tvalid is asserted and previous frame has ended.
wr_sof_int <= tx_axis_fifo_tvalid and wr_eof_reg;
-- Set end of frame flag when tlast and tvalid are asserted together.
-- Reset to logic 1 to enable first frame's start of frame flag.
reg_eofreg_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
if tx_fifo_reset = '1' then
wr_eof_reg <= '1';
else
if tx_axis_fifo_tvalid = '1' and tx_axis_fifo_tready_int_n = '0' then
wr_eof_reg <= tx_axis_fifo_tlast;
end if;
end if;
end if;
end process reg_eofreg_p;
-- Pipeline the start of frame flag when the pipe is enabled.
reg_sof_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
wr_sof_pipe(0) <= wr_sof_int after dly;
if wr_accept_pipe(0) = '1' then
wr_sof_pipe(1) <= wr_sof_pipe(0) after dly;
end if;
end if;
end process reg_sof_p;
-- Pipeline the pipeline enable signal, which is derived from simultaneous
-- assertion of tvalid and tready.
reg_acc_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
if (tx_fifo_reset = '1') then
wr_accept_pipe(0) <= '0' after dly;
wr_accept_pipe(1) <= '0' after dly;
wr_accept_bram <= '0' after dly;
else
wr_accept_pipe(0) <= tx_axis_fifo_tvalid and (not tx_axis_fifo_tready_int_n) after dly;
wr_accept_pipe(1) <= wr_accept_pipe(0) after dly;
wr_accept_bram <= wr_accept_pipe(1) after dly;
end if;
end if;
end process reg_acc_p;
-- Pipeline the end of frame flag when the pipe is enabled.
reg_eof_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
wr_eof_pipe(0) <= tx_axis_fifo_tvalid and tx_axis_fifo_tlast after dly;
if wr_accept_pipe(0) = '1' then
wr_eof_pipe(1) <= wr_eof_pipe(0) after dly;
end if;
if wr_accept_pipe(1) = '1' then
wr_eof_bram(0) <= wr_eof_pipe(1) after dly;
end if;
end if;
end process reg_eof_p;
-- Register data outputs from BRAM.
-- No resets to allow SRL16 target.
reg_dout_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if rd_en = '1' then
rd_data_pipe_u <= rd_data_bram_u after dly;
rd_data_pipe_l <= rd_data_bram_l after dly;
if rd_bram_u_reg = '1' then
rd_data_pipe <= rd_data_pipe_u after dly;
else
rd_data_pipe <= rd_data_pipe_l after dly;
end if;
end if;
end if;
end process reg_dout_p;
reg_eofout_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if rd_en = '1' then
if rd_bram_u = '1' then
rd_eof_pipe <= rd_eof_bram_u(0) after dly;
else
rd_eof_pipe <= rd_eof_bram_l(0) after dly;
end if;
rd_eof <= rd_eof_pipe after dly;
rd_eof_reg <= rd_eof or rd_eof_pipe after dly;
end if;
end if;
end process reg_eofout_p;
------------------------------------------------------------------------------
-- Half duplex-only drop and retransmission controls.
gen_hd_input : if (FULL_DUPLEX_ONLY = FALSE) generate
-- Register the collision without retransmit signal, which is a pulse that
-- causes the FIFO to drop the frame.
reg_col_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
rd_drop_frame <= tx_collision and (not tx_retransmit) after dly;
end if;
end process reg_col_p;
-- Register the collision with retransmit signal, which is a pulse that
-- causes the FIFO to retransmit the frame.
reg_retr_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
rd_retransmit <= tx_collision and tx_retransmit after dly;
end if;
end process reg_retr_p;
end generate gen_hd_input;
------------------------------------------------------------------------------
-- FIFO full functionality
------------------------------------------------------------------------------
-- Full functionality is the difference between read and write addresses.
-- We cannot use gray code this time as the read address and read start
-- addresses jump by more than 1.
-- We generate an enable pulse for the read side every 16 read clocks. This
-- provides for the worst-case situation where the write clock is 20MHz and
-- read clock is 125MHz.
p_rd_16_pulse : process (tx_mac_aclk)
begin
if tx_mac_aclk'event and tx_mac_aclk = '1' then
if tx_mac_reset = '1' then
rd_16_count <= (others => '0') after dly;
else
rd_16_count <= rd_16_count + 1 after dly;
end if;
end if;
end process;
rd_txfer_en <= '1' when rd_16_count = "1111" else '0';
-- Register the start address on the enable pulse.
p_rd_addr_txfer : process (tx_mac_aclk)
begin
if tx_mac_aclk'event and tx_mac_aclk = '1' then
if tx_mac_reset = '1' then
rd_addr_txfer <= (others => '0') after dly;
else
if rd_txfer_en = '1' then
rd_addr_txfer <= rd_start_addr after dly;
end if;
end if;
end if;
end process;
-- Generate a toggle to indicate that the address has been loaded.
p_rd_tog_txfer : process (tx_mac_aclk)
begin
if tx_mac_aclk'event and tx_mac_aclk = '1' then
if rd_txfer_en = '1' then
rd_txfer_tog <= not rd_txfer_tog after dly;
end if;
end if;
end process;
-- Synchronize the toggle to the write side.
resync_rd_txfer_tog : temac_10_100_1000_sync_block
port map (
clk => tx_fifo_aclk,
data_in => rd_txfer_tog,
data_out => wr_txfer_tog_sync
);
-- Delay the synchronized toggle by one cycle.
p_wr_tog_txfer : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
wr_txfer_tog_delay <= wr_txfer_tog_sync after dly;
end if;
end process;
-- Generate an enable pulse from the toggle. The address should have been
-- steady on the wr clock input for at least one clock.
wr_txfer_en <= wr_txfer_tog_delay xor wr_txfer_tog_sync;
-- Capture the address on the write clock when the enable pulse is high.
p_wr_addr_txfer : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_rd_addr <= (others => '0') after dly;
elsif wr_txfer_en = '1' then
wr_rd_addr <= rd_addr_txfer after dly;
end if;
end if;
end process;
-- Obtain the difference between write and read pointers
p_wr_addr_diff : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_addr_diff <= (others => '0') after dly;
else
wr_addr_diff <= wr_rd_addr - wr_addr after dly;
end if;
end if;
end process;
-- Detect when the FIFO is full.
-- The FIFO is considered to be full if the write address pointer is
-- within 0 to 3 of the read address pointer.
p_wr_full : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_fifo_full <= '0' after dly;
else
if wr_addr_diff(11 downto 4) = 0
and wr_addr_diff(3 downto 2) /= "00" then
wr_fifo_full <= '1' after dly;
else
wr_fifo_full <= '0' after dly;
end if;
end if;
end if;
end process p_wr_full;
-- Memory overflow occurs when the FIFO is full and there are no frames
-- available in the FIFO for transmission. If the collision window has
-- expired and there are no frames in the FIFO and the FIFO is full, then the
-- FIFO is in an overflow state. We must accept the rest of the incoming
-- frame in overflow condition.
gen_fd_ovflow : if (FULL_DUPLEX_ONLY = TRUE) generate
-- In full duplex mode, the FIFO memory can only overflow if the FIFO goes
-- full but there is no frame available to be retranmsitted. Therefore,
-- prevent signal from being asserted when store_frame signal is high, as
-- frame count is being updated.
wr_fifo_overflow <= '1' when wr_fifo_full = '1' and wr_frame_in_fifo = '0'
and wr_eof_state = '0' and wr_eof_state_reg = '0'
else '0';
end generate gen_fd_ovflow;
gen_hd_ovflow : if (FULL_DUPLEX_ONLY = FALSE) generate
-- In half duplex mode, register write collision window to give address
-- counter sufficient time to update. This will prevent the signal from
-- being asserted when the store_frame signal is high, as the frame count
-- is being updated.
wr_fifo_overflow <= '1' when wr_fifo_full = '1' and wr_frame_in_fifo = '0'
and wr_eof_state = '0' and wr_eof_state_reg = '0'
and wr_col_window_expire = '1'
else '0';
-- Register rd_col_window signal.
-- This signal is long, and will remain high until overflow functionality
-- has finished, so save just to register the once.
p_wr_col_expire : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_col_window_pipe(0) <= '0' after dly;
wr_col_window_pipe(1) <= '0' after dly;
wr_col_window_expire <= '0' after dly;
else
if wr_txfer_en = '1' then
wr_col_window_pipe(0) <= rd_col_window_pipe(1) after dly;
end if;
wr_col_window_pipe(1) <= wr_col_window_pipe(0) after dly;
wr_col_window_expire <= wr_col_window_pipe(1) after dly;
end if;
end if;
end process;
end generate gen_hd_ovflow;
------------------------------------------------------------------------------
-- FIFO status signals
------------------------------------------------------------------------------
-- The FIFO status is four bits which represents the occupancy of the FIFO
-- in sixteenths. To generate this signal we therefore only need to compare
-- the 4 most significant bits of the write address pointer with the 4 most
-- significant bits of the read address pointer.
p_fifo_status : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_fifo_status <= "0000" after dly;
else
if wr_addr_diff = (wr_addr_diff'range => '0') then
wr_fifo_status <= "0000" after dly;
else
wr_fifo_status(3) <= not wr_addr_diff(11) after dly;
wr_fifo_status(2) <= not wr_addr_diff(10) after dly;
wr_fifo_status(1) <= not wr_addr_diff(9) after dly;
wr_fifo_status(0) <= not wr_addr_diff(8) after dly;
end if;
end if;
end if;
end process p_fifo_status;
fifo_status <= std_logic_vector(wr_fifo_status);
wr_addr_slv <= std_logic_vector(wr_addr(10 downto 0));
rd_addr_slv <= std_logic_vector(rd_addr(10 downto 0));
------------------------------------------------------------------------------
-- Instantiate FIFO block memory
------------------------------------------------------------------------------
wr_eof_data_bram(8) <= wr_eof_bram(0);
wr_eof_data_bram(7 downto 0) <= wr_data_bram;
-- Block RAM for lower address space (rd_addr(11) = '0')
rd_eof_bram_l(0) <= rd_eof_data_bram_l(8);
rd_data_bram_l <= rd_eof_data_bram_l(7 downto 0);
ramgen_l : BRAM_TDP_MACRO
generic map (
DEVICE => "7SERIES",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9,
READ_WIDTH_A => 9,
READ_WIDTH_B => 9)
port map (
DOA => rd_bram_l_unused,
DOB => rd_eof_data_bram_l,
ADDRA => wr_addr_slv,
ADDRB => rd_addr_slv,
CLKA => tx_fifo_aclk,
CLKB => tx_mac_aclk,
DIA => wr_eof_data_bram,
DIB => GND_BUS(8 downto 0),
ENA => VCC,
ENB => rd_en,
REGCEA => VCC,
REGCEB => VCC,
RSTA => tx_fifo_reset,
RSTB => tx_mac_reset,
WEA => wr_en_l_bram,
WEB => GND
);
-- Block RAM for lower address space (rd_addr(11) = '0')
rd_eof_bram_u(0) <= rd_eof_data_bram_u(8);
rd_data_bram_u <= rd_eof_data_bram_u(7 downto 0);
ramgen_u : BRAM_TDP_MACRO
generic map (
DEVICE => "7SERIES",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9,
READ_WIDTH_A => 9,
READ_WIDTH_B => 9)
port map (
DOA => rd_bram_u_unused,
DOB => rd_eof_data_bram_u,
ADDRA => wr_addr_slv,
ADDRB => rd_addr_slv,
CLKA => tx_fifo_aclk,
CLKB => tx_mac_aclk,
DIA => wr_eof_data_bram,
DIB => GND_BUS(8 downto 0),
ENA => VCC,
ENB => rd_en,
REGCEA => VCC,
REGCEB => VCC,
RSTA => tx_fifo_reset,
RSTB => tx_mac_reset,
WEA => wr_en_u_bram,
WEB => GND
);
end RTL;
| gpl-3.0 | 90cd3c4314bfdc3aa7b2ad8a13d2a6eb | 0.529905 | 3.827551 | false | false | false | false |
HackLinux/ION | src/testbench/ion_application_tb.vhdl | 1 | 8,555 | --##############################################################################
-- ion_application_tb.vhdl -- Test bench for ION core sample application module.
--
-- Simulates the sample ION application module, which includes the full core
-- with TCM and caches, plus the memory controllers and some amount of
-- external SRAM.
--
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- SIMULATED IO DEVICES:
--
-- Those included in th sampl application module.
--
--------------------------------------------------------------------------------
-- SIMULATED MEMORY:
--
-- FIXME explain!
--
--------------------------------------------------------------------------------
-- Console logging:
--
-- Console output (at address 0xffff0000) is logged to text file
-- "hw_sim_console_log.txt".
--
-- IMPORTANT: The code that echoes UART TX data to the simulation console does
-- line buffering; it will not print anything until it gets a CR (0x0d), and
-- will ignore LFs (0x0a). Bear this in mind if you see no output when you
-- expect it.
--
-- Console logging is done by monitoring CPU writes to the UART, NOT by looking
-- at the TxD pin. It will NOT catch baud-related problems, etc.
--------------------------------------------------------------------------------
-- WARNING: Will only work on Modelsim 6.3+; uses proprietary library SignalSpy.
--##############################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Project packages.
use work.ION_INTERFACES_PKG.all;
use work.ION_INTERNAL_PKG.all;
-- Tst bench support packages.
use std.textio.all;
use work.txt_util.all;
use work.ION_TB_PKG.all;
-- Simulation parameters defined in the SW makefile (generated package).
use work.SIM_PARAMS_PKG.all;
-- Hardware parameters & memory contents from SW build (generated package).
use work.OBJ_CODE_PKG.all;
entity ION_APPLICATION_TB is
end;
architecture testbench of ION_APPLICATION_TB is
-- Simulation clock rate
constant CLOCK_RATE : integer := 50e6;
-- Simulation clock period
constant T : time := (1.0e9/real(CLOCK_RATE)) * 1 ns;
--------------------------------------------------------------------------------
-- Core interface.
signal clk : std_logic := '0';
signal reset : std_logic := '1';
--------------------------------------------------------------------------------
-- Simulated GPIO.
signal port0_out : std_logic_vector(15 downto 0);
signal port0_in : std_logic_vector(15 downto 0);
--------------------------------------------------------------------------------
-- Simulated external 16-bit SRAM.
constant SRAM_SIZE : integer := 64 * 1024;
constant SRAM_ADDR_SIZE : integer := log2(SRAM_SIZE);
signal mpu_sram_addr : std_logic_vector(SRAM_ADDR_SIZE downto 1);
signal sram_data_out : std_logic_vector(15 downto 0);
signal sram_data_in : std_logic_vector(15 downto 0);
signal sram_output : std_logic_vector(15 downto 0);
signal sram_wen : std_logic;
signal sram_ben : std_logic_vector(1 downto 0);
signal sram_oen : std_logic;
signal sram_cen : std_logic;
signal sram_drive_en : std_logic;
signal irq : std_logic_vector(5 downto 0);
-- Static 16-bit wide RAM.
-- Using shared variables for big memory arrays speeds up simulation a lot;
-- see Modelsim 6.3 User Manual, section on 'Modelling Memory'.
-- WARNING: I have only tested this construct with Modelsim SE 6.3.
shared variable sram : t_hword_table(0 to SRAM_SIZE-1);
signal sram_addr : std_logic_vector(SRAM_ADDR_SIZE downto 1);
signal sram_data : std_logic_vector(15 downto 0);
--------------------------------------------------------------------------------
-- Logging signals & simulation control.
signal done : std_logic := '0';
-- Log file
file log_file: TEXT open write_mode is "hw_sim_log.txt";
-- Console output log file
file con_file: TEXT open write_mode is "hw_sim_console_log.txt";
-- All the info needed by the logger is here
signal log_info : t_log_info;
--------------------------------------------------------------------------------
begin
mpu: entity work.ION_APPLICATION
generic map (
TCM_CODE_SIZE => CODE_MEM_SIZE,
TCM_CODE_INIT => OBJ_CODE,
TCM_DATA_SIZE => DATA_MEM_SIZE,
SRAM_SIZE => SRAM_SIZE,
DATA_CACHE_LINES => 128,
CODE_CACHE_LINES => 128
)
port map (
CLK_I => clk,
RESET_I => reset,
SRAM_ADDR_O => mpu_sram_addr,
SRAM_DATA_I => sram_data_in,
SRAM_DATA_O => sram_data_out,
SRAM_WEn_O => sram_wen,
SRAM_OEn_O => sram_oen,
SRAM_UBn_O => sram_ben(1),
SRAM_LBn_O => sram_ben(0),
SRAM_CEn_O => sram_cen,
SRAM_DRIVE_EN_O => sram_drive_en,
IRQ_I => irq,
GPIO_0_OUT_O => port0_out,
GPIO_0_INP_I => port0_in
);
-- Master clock: free running clock used as main module clock --------------
run_master_clock:
process(done, clk)
begin
if done = '0' then
clk <= not clk after T/2;
end if;
end process run_master_clock;
-- Main simulation process: reset MCU and wait for fixed period ------------
drive_uut:
process
variable l : line;
begin
wait for T*4;
reset <= '0';
wait for T*SIMULATION_LENGTH;
-- Flush console output to log console file (in case the end of the
-- simulation caught an unterminated line in the buffer)
if log_info.con_line_ix > 1 then
write(l, log_info.con_line_buf(1 to log_info.con_line_ix));
writeline(con_file, l);
end if;
print("TB finished");
done <= '1';
file_close(con_file);
wait;
end process drive_uut;
-- Do a very basic simulation of an external SRAM --------------------------
sram_addr <= mpu_sram_addr(SRAM_ADDR_SIZE downto 1);
sram_data_in <= sram_output;
sram_data <= sram_data_out; --output when sram_drive_en='1' else (others => 'Z');
-- Simulated SRAM read.
-- FIXME byte enables missing in read
sram_output <=
sram(conv_integer(unsigned(sram_addr))) when sram_cen='0'
else (others => 'Z');
-- Simulated SRAM write.
simulated_sram_write:
process(sram_wen, sram_addr, sram_oen, sram_cen, sram_ben)
begin
-- Write cycle
-- FIXME should add OE\ to write control logic
if sram_wen'event or sram_addr'event or sram_cen'event or sram_ben'event then
if sram_ben(1)='0' and sram_cen='0' and sram_wen='0' then
sram(conv_integer(unsigned(sram_addr)))(15 downto 8) := sram_data(15 downto 8);
end if;
if sram_ben(0)='0' and sram_cen='0' and sram_wen='0' then
sram(conv_integer(unsigned(sram_addr)))( 7 downto 0) := sram_data( 7 downto 0);
end if;
end if;
end process simulated_sram_write;
-- HW interrupt simulation -------------------------------------------------
-- Wire the IRQ inputs to a simulation-only signal in the sim package.
interrupt_registers:
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
irq <= (others => '0');
else
irq <= log_info.hw_irq;
end if;
end if;
end process interrupt_registers;
-- GPIO simulation ---------------------------------------------------------
-- For the time being just loop back the ports.
port0_in <= port0_out + X"2901";
-- Logging process: launch logger function ---------------------------------
log_execution:
process
begin
log_cpu_activity(clk, reset, done,
"ION_APPLICATION_TB", "mpu/core/cpu",
log_info, "log_info",
LOG_TRIGGER_ADDRESS, log_file, con_file);
wait;
end process log_execution;
end architecture testbench;
| lgpl-3.0 | b02826a33550f9d699160ccb9f19e1fe | 0.510462 | 4.18952 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/FIR_Filter/lp_fir_filter.vhd | 1 | 5,165 | --------------------------------------------------------------------------------------------------
-- FIR Filter
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- PACKAGE
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.dsp_pkg.all;
package lp_fir_filter_pkg is
--linear phase FIR filter component declaration
component lp_fir_filter is
generic( h : coefficient_array);
port( clk : in std_logic;
rst : in std_logic;
x : in sig;
y : out fir_sig);
end component;
end package;
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.dsp_pkg.all;
use work.lp_fir_tap_pkg.all;
entity lp_fir_filter is
generic( h : coefficient_array);
port( clk : in std_logic;
rst : in std_logic;
x : in sig;
y : out fir_sig);
end lp_fir_filter;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture behave of lp_fir_filter is
constant N : natural := h'length;
constant NTAPS : natural := N - N/2;
constant RETURN_DELAY : natural := NTAPS*2-1;
constant FIRST_TAP : natural := h'low;
constant LAST_TAP : natural := h'low + NTAPS-1;
signal x_chain : sig_array(0 to NTAPS-1);
signal x_return_delay : sig_array(0 to RETURN_DELAY-1);
signal running_sum : fir_sig_array(0 to NTAPS-1);
begin
--The return path can be replicated useing a fifo of an appropriate delay
x_return_fifo : process(clk)
begin
if(rising_edge(clk)) then
if(rst = '1') then
x_return_delay <= (others => (others => '0'));
else
x_return_delay(0) <= x;
for xn in 1 to RETURN_DELAY-1 loop
x_return_delay(xn) <= x_return_delay(xn-1);
end loop;
end if;
end if;
end process;
--This chain links the taps together
filter_chain : for tap in FIRST_TAP to LAST_TAP generate
begin
head_tap_gen : if tap = FIRST_TAP generate
head_tap : lp_fir_tap
port map(clk => clk,
rst => rst,
coef => h(tap),
sig_in => x,
return_sig_in => x_return_delay(x_return_delay'high),
sig_out => x_chain(tap),
sum_in => (others => '0'),
sum_out => running_sum(tap));
end generate; --if head tap
mid_taps_gen : if tap /= FIRST_TAP and tap /= LAST_TAP generate
mid_tap : lp_fir_tap
port map(clk => clk,
rst => rst,
coef => h(tap),
sig_in => x_chain(tap-1),
return_sig_in => x_return_delay(x_return_delay'high),
sig_out => x_chain(tap),
sum_in => running_sum(tap-1),
sum_out => running_sum(tap));
end generate; --if mid taps
last_tap_even_gen : if tap = LAST_TAP and (NTAPS mod 2) = 0 generate
last_tap_even_tap : lp_fir_tap
port map(clk => clk,
rst => rst,
coef => h(tap),
sig_in => x_chain(tap-1),
return_sig_in => x_return_delay(x_return_delay'high),
sig_out => x_chain(tap),
sum_in => running_sum(tap-1),
sum_out => running_sum(tap));
end generate; --if last even tap
last_tap_odd_gen : if tap = LAST_TAP and (NTAPS mod 2) = 1 generate
last_tap_odd_tap : lp_fir_tap
port map(clk => clk,
rst => rst,
coef => h(tap),
sig_in => x_chain(tap-1),
return_sig_in => (others => '0'),
sig_out => x_chain(tap),
sum_in => running_sum(tap-1),
sum_out => running_sum(tap));
end generate; --if last odd tap
end generate;
--output end of the running sum
y <= running_sum(NTAPS-1);
end behave;
| mit | e4c26442d38241d0a9bd5f796cb2fc97 | 0.381801 | 4.538664 | false | false | false | false |
HackLinux/ION | src/rtl/caches/ion_cache.vhdl | 1 | 15,093 | --------------------------------------------------------------------------------
-- ion_icache.vhdl -- Instruction/Data Cache.
--------------------------------------------------------------------------------
--
--
-- NOTES:
--
-- @note1:
-- All supported CACHE instruction functions involve invalidating a line
-- or explicity zeroing a tag. So the valid flag is always written as 0
-- except when REFILL.
-- Remember our "Store Tag" implementation uses a hardwired zero TagLo.
--
-- @ note2:
-- In the first clock cycle of all write accesses, the addressed line
-- is invalidated. The CPU address is only valid in this cycle so we
-- do it right now and save a register and a mux.
--
-- @note3:
-- When a RD comes the cycle after a WR, we'll lose it unless we register
-- the fact. This happens because the rd_en signal is asserted for a single
-- clock cycle, even if the RD instruction is stalled waiting for the WR
-- to finish.
-- The same thing happens when a WR follows a RD.
--
-- REFERENCES
-- [1] ion_design_notes.pdf -- ION project design notes.
--------------------------------------------------------------------------------
-- NOTES:
--
--
--------------------------------------------------------------------------------
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.ION_INTERFACES_PKG.all;
use work.ION_INTERNAL_PKG.all;
entity ION_CACHE is
generic(
-- Number of lines per way.
NUM_LINES : integer := 128;
-- Size of line in 32-bit words.
LINE_SIZE : integer := 8
);
port(
CLK_I : in std_logic;
RESET_I : in std_logic;
CACHE_CTRL_MOSI_I : in t_cache_mosi;
CACHE_CTRL_MISO_O : out t_cache_miso;
CE_I : in std_logic;
CPU_MOSI_I : in t_cpumem_mosi;
CPU_MISO_O : out t_cpumem_miso;
MEM_MOSI_O : out t_wishbone_mosi;
MEM_MISO_I : in t_wishbone_miso
);
end;
architecture rtl of ION_CACHE is
constant LINE_INDEX_WIDTH : integer := log2(NUM_LINES);
constant LINE_OFFSET_WIDTH : integer := log2(LINE_SIZE);
constant LINE_ADDRESS_WIDTH : integer := LINE_INDEX_WIDTH + LINE_OFFSET_WIDTH;
constant TAG_WIDTH : integer := 32 - 2 - LINE_ADDRESS_WIDTH;
constant LINE_TABLE_SIZE : integer := LINE_SIZE * NUM_LINES;
-- Tag table signals.
subtype t_index is std_logic_vector(LINE_INDEX_WIDTH-1 downto 0);
subtype t_offset is std_logic_vector(LINE_OFFSET_WIDTH-1 downto 0);
subtype t_line_address is std_logic_vector(LINE_ADDRESS_WIDTH-1 downto 0);
subtype t_tag_address is std_logic_vector(TAG_WIDTH-1 downto 0);
-- Valid bit appended to address tag; this is what's stored in the tag table.
subtype t_tag is std_logic_vector(TAG_WIDTH+1-1 downto 0);
-- Tag table implemented as (inferred) synchronous BRAM.
type t_tag_table is array(0 to NUM_LINES-1) of t_tag;
-- Initial value meant for TB only. Helps catch errors in invalidation opcodes.
signal tag_table : t_tag_table; -- := (others => '1' & X"90000");
-- Signals used to access the tag table.
signal tag : t_tag_address;
signal tag_reg : t_tag_address;
signal cached_tag_addr : t_tag_address;
signal line_index : t_index;
signal line_address : t_line_address;
signal cached_tag : t_tag;
signal tag_table_we : std_logic;
-- Valid flag to be stored in tag table.
signal new_valid_flag : std_logic;
-- Valid flag read from tag table during a lookup.
signal cached_tag_valid : std_logic;
-- Line table implemented as (inferred) BRAM table.
type t_line_table is array(0 to LINE_TABLE_SIZE-1) of t_word;
signal line_table : t_line_table;
-- Signals used to access the line table.
signal refill_line_address : t_line_address;
signal refill_line_address_reg : t_line_address;
signal cached_word : t_word;
signal line_table_we : std_logic;
-- Misc control signals.
signal miss : std_logic;
signal lookup : std_logic;
signal lookup_reg : std_logic;
signal write_cycle : std_logic;
signal update_tag : std_logic;
signal data_wr_reg : t_word;
signal addr_reg : t_word;
signal wr_be_reg : std_logic_vector(3 downto 0);
signal read_pending : std_logic;
-- Refill state machine signals.
type t_refill_state is (
HIT,
REFILL,
WRITETHROUGH,
REFILL_LAST_WORD
);
signal ns, ps : t_refill_state;
signal refill_ctr : t_offset;
signal store_delay_ctr : integer range 0 to 2;
signal refill_done : std_logic;
begin
-- CPU interface -----------------------------------------------------------
CPU_MISO_O.rd_data <= cached_word;
CPU_MISO_O.mwait <=
'1' when ps = REFILL else
'1' when ps = REFILL_LAST_WORD else
'1' when ps = HIT and miss = '1' else -- !!
'1' when ps = HIT and read_pending = '1' else -- see @note3
'1' when ps = WRITETHROUGH else
'0';
lookup <=
'1' when CPU_MOSI_I.rd_en='1' and CE_I='1' else
'1' when read_pending='1' and ps=HIT else
'0';
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if RESET_I='1' then
lookup_reg <= '0';
else
lookup_reg <= lookup;
if CPU_MOSI_I.wr_be/="0000" then
data_wr_reg <= CPU_MOSI_I.wr_data;
wr_be_reg <= CPU_MOSI_I.wr_be;
end if;
if CPU_MOSI_I.rd_en='1' or CPU_MOSI_I.wr_be/="0000" then
addr_reg <= CPU_MOSI_I.addr;
end if;
end if;
end if;
end process;
-- Assert update_tag for special CACHE instructions only.
-- FIXME control interface is crude and needs to be defined & refactored
update_tag <= '1' when
CACHE_CTRL_MOSI_I.data_cache = '1' and
CACHE_CTRL_MOSI_I.function_en = '1'
else '0';
-- Tag table ---------------------------------------------------------------
-- Extract all relevand fields from incoming CPU address.
tag <= CPU_MOSI_I.addr(31 downto LINE_ADDRESS_WIDTH+2);
tag_reg <= addr_reg(31 downto LINE_ADDRESS_WIDTH+2);
line_index <= CPU_MOSI_I.addr(LINE_ADDRESS_WIDTH+1 downto LINE_OFFSET_WIDTH + 2);
line_address <= CPU_MOSI_I.addr(LINE_ADDRESS_WIDTH+1 downto 2);
-- Tag table inferred BRAM.
synchronous_tag_table:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if tag_table_we='1' then
tag_table(conv_integer(line_index)) <= new_valid_flag & tag;
end if;
cached_tag <= tag_table(conv_integer(line_index));
end if;
end process synchronous_tag_table;
-- Extract fields from the word we just read from the tag table.
cached_tag_valid <= cached_tag(cached_tag'high);
cached_tag_addr <= cached_tag(cached_tag'high-1 downto 0);
-- When in REFILL, set valid flag. Otherwise reset it.
with ps select new_valid_flag <=
'1' when REFILL,
'0' when others; -- see @note1
-- The miss signal needs only be valid in the "HIT" state.
miss <=
'1' when ((cached_tag_addr /= tag_reg) or
(cached_tag_valid = '0')) and
lookup_reg = '1'
else '0';
write_cycle <= '1' when CPU_MOSI_I.wr_be/="0000" and CE_I='1' else '0';
-- Line table --------------------------------------------------------------
-- Line table (inferred) BRAM.
synchronous_line_table:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if line_table_we='1' then
line_table(conv_integer(refill_line_address_reg)) <= MEM_MISO_I.dat;
end if;
cached_word <= line_table(conv_integer(line_address));
end if;
end process synchronous_line_table;
-- Since the target address is only present in the ION CPU bus for a single
-- cycle, we need to register it to use it along the refill operation.
refill_addr_register:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if lookup = '1' and ps=HIT then
refill_line_address(LINE_ADDRESS_WIDTH-1 downto LINE_OFFSET_WIDTH) <=
CPU_MOSI_I.addr(LINE_ADDRESS_WIDTH-1+2 downto LINE_OFFSET_WIDTH+2);
end if;
refill_line_address_reg <= refill_line_address;
end if;
end process refill_addr_register;
-- The low bits of the refill address come from the refill counter.
refill_line_address(LINE_OFFSET_WIDTH-1 downto 0) <= refill_ctr;
-- We write onto the line table only in the cycles in which there is valid
-- refill data in the refill WB bus.
line_table_we <=
'1' when ps = REFILL and MEM_MISO_I.ack = '1' else
'1' when ps = REFILL_LAST_WORD and store_delay_ctr = 2 else
'0';
-- Refill State Machine ----------------------------------------------------
refill_state_machine_reg:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if RESET_I='1' then
ps <= HIT;
else
ps <= ns;
end if;
end if;
end process refill_state_machine_reg;
refill_state_machine_transitions:
process(ps, miss, refill_done, write_cycle, MEM_MISO_I.stall,
store_delay_ctr, read_pending)
begin
case ps is
when HIT =>
if miss='1' then
ns <= REFILL;
elsif write_cycle='1' then
ns <= WRITETHROUGH;
else
ns <= ps;
end if;
when REFILL =>
if refill_done='1' then
ns <= REFILL_LAST_WORD;
else
ns <= ps;
end if;
when REFILL_LAST_WORD =>
if store_delay_ctr = 0 then
ns <= HIT;
else
ns <= ps;
end if;
when WRITETHROUGH =>
if MEM_MISO_I.stall='0' then
ns <= HIT;
else
ns <= ps;
end if;
when others =>
-- NOTE: We´re not detecting here a real derailed HW state machine,
-- only a buggy rtl.
ns <= HIT;
end case;
end process refill_state_machine_transitions;
-- When the last word in the line has been read from the WB bus, we are done
-- REFILL.
refill_done <=
'1' when refill_ctr = (LINE_SIZE-1) and MEM_MISO_I.stall = '0'
else '0';
refill_word_counter:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if RESET_I = '1' then
refill_ctr <= (others => '0');
elsif ps = REFILL and MEM_MISO_I.stall = '0' then
refill_ctr <= refill_ctr + 1;
end if;
end if;
end process refill_word_counter;
store_delay_counter:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if RESET_I = '1' then
store_delay_ctr <= 2;
elsif ps = REFILL_LAST_WORD then
if store_delay_ctr /= 0 then
store_delay_ctr <= store_delay_ctr - 1;
end if;
else
store_delay_ctr <= 2;
end if;
end if;
end process store_delay_counter;
tag_table_we <=
'1' when ps = REFILL and MEM_MISO_I.ack = '1' and refill_ctr="001" else
'1' when ps = HIT and CPU_MOSI_I.wr_be/="0000" else -- see @note2
'1' when update_tag = '1' else -- see @note1
'0';
-- Refill WB interface -----------------------------------------------------
MEM_MOSI_O.adr(31 downto LINE_ADDRESS_WIDTH+2) <= addr_reg(31 downto LINE_ADDRESS_WIDTH+2);
with ps select MEM_MOSI_O.adr(LINE_ADDRESS_WIDTH-1+2 downto 2) <=
refill_line_address when REFILL,
addr_reg(LINE_ADDRESS_WIDTH-1+2 downto 2) when others;
MEM_MOSI_O.adr(1 downto 0) <= (others => '0');
MEM_MOSI_O.dat <= data_wr_reg;
MEM_MOSI_O.stb <= '1' when (ps = REFILL or ps = WRITETHROUGH) else '0';
MEM_MOSI_O.cyc <= '1' when (ps = REFILL or ps = WRITETHROUGH) else '0';
MEM_MOSI_O.we <= '1' when ps = WRITETHROUGH else '0';
MEM_MOSI_O.tga <= "0000"; -- FIXME tag use unspecified yet
MEM_MOSI_O.sel <= wr_be_reg;
-- The cache control interface MOSI consists of this lone "present" signal.
CACHE_CTRL_MISO_O.present <= '1';
-- Back-to-back access support logic ---------------------------------------
-- This flag will be raised when a READ comes immediately aftr a write (in
-- the following clock cycle). Since the ION bus control signals are valid
-- for only one cycle we need to remember the request here.
-- The address is not going to change in the meantime.
read_pending_register:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if RESET_I='1' then
read_pending <= '0';
elsif ps=WRITETHROUGH and CPU_MOSI_I.rd_en='1' then
read_pending <= '1';
elsif ps/=WRITETHROUGH then
read_pending <= '0';
end if;
end if;
end process read_pending_register;
-- FIXME support RD-WR operations too.
end architecture rtl;
| lgpl-3.0 | 1d67dcdfc471a2406b577259eb76e5cc | 0.539257 | 3.901008 | false | false | false | false |
HackLinux/ION | src/application/ion_cop2_stub.vhdl | 1 | 5,371 | --------------------------------------------------------------------------------
-- ion_cop2_stub.vhdl -- Dummy COP2 for test purposes.
--------------------------------------------------------------------------------
--
-- This is a dummy COP2 meant to serve two purposes:
-- -# Support the tests for COP2 functionality.
-- -# Provide a working example for the implementation of the COP2 interface.
--
-- FUNCTIONALITY:
--
-- This COP2 stub provides only just enough functionality to test the COP2
-- interface, it's not meant to do any useful work.
-- This is what this module does at the moment:
--
-- -# Register bank with 16 32-bit general purpose registers.
-- -# Register bank with 16 32-bit general purpose registers.
-- (Both implemented in a single BRAM.)
-- -# "Sel" field is written to top 3 bits of register when writing.
-- -# "Sel" field is ignored on reads.
-- -# Operation fields are ignored.
--
-- FIXME cover all the COP2 interface including function codes.
--
-- REFERENCES
-- [1] ion_design_notes.pdf -- ION project design notes.
-- [1] ion_core.pdf -- ION core datasheet.
--------------------------------------------------------------------------------
--
--
--------------------------------------------------------------------------------
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.ION_INTERFACES_PKG.all;
use work.ION_INTERNAL_PKG.all;
entity ION_COP2_STUB is
generic(
-- Size of TCM block in 32-bit words. Set to zero to disable TCM.
SIZE : integer := 4096;
-- Initial contents of TCM. Default is zeros.
INIT_DATA : t_obj_code := zero_objcode(16)
);
port(
CLK_I : in std_logic;
RESET_I : in std_logic;
CPU_MOSI_I : in t_cop2_mosi;
CPU_MISO_O : out t_cop2_miso
);
end;
architecture rtl of ION_COP2_STUB is
signal rbank : t_rbank := (others => X"00000000");
signal rs_rbank : t_word;
signal rbank_wr_data : t_word;
signal rbank_we : std_logic;
signal rbank_wr_addr : t_regnum;
signal rbank_rd_addr : t_regnum;
-- IMPORTANT: This attribute is used by Xilinx tools to select how to implement
-- the register bank. If we don't use it, by default XST would infer 1 BRAMs for
-- the 1024-bit 2-port reg bank, which we don't want.
-- This can take the values {distributed|block}.
attribute ram_style : string;
attribute ram_style of rbank : signal is "distributed";
begin
-- Connect the register bank adress inputs straight to the MOSI.
rbank_we <= CPU_MOSI_I.reg_wr_en;
rbank_wr_addr <=
CPU_MOSI_I.reg_wr.control &
CPU_MOSI_I.reg_wr.index(3 downto 0);
rbank_rd_addr <=
CPU_MOSI_I.reg_rd.control &
CPU_MOSI_I.reg_rd.index(3 downto 0);
-- When reading regular registers (as opposed to control), put the SEL
-- field in the high 3 bits so we at least have some way to check the
-- connection. This will have to be improved...
with CPU_MOSI_I.reg_wr.control select rbank_wr_data <=
CPU_MOSI_I.reg_wr.sel & CPU_MOSI_I.data(28 downto 0) when '0',
CPU_MOSI_I.data when others;
-- Register bank as double-port RAM. Should synth to 1 BRAM unless you use
-- synth attributes to prevent it (see 'ram_style' attribute above) or your
-- FPGA has no BRAMs.
-- This is a near-identical copy-paste of the main CPU reg bank.
synchronous_reg_bank:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if rbank_we='1' then
rbank(conv_integer(rbank_wr_addr)) <= rbank_wr_data;
end if;
rs_rbank <= rbank(conv_integer(rbank_rd_addr));
end if;
end process synchronous_reg_bank;
CPU_MISO_O.stall <= '0';
CPU_MISO_O.data <= rs_rbank;
end architecture rtl;
| lgpl-3.0 | ea03e36d65c6e3d89bfb9dc61bceeda3 | 0.56172 | 4.222484 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/readout/l0_link_health.vhd | 1 | 7,230 | ----------------------------------------------------------------------------------
-- Company: NTU Athens - BNL
-- Engineer: Christos Bakalis ([email protected])
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Christos Bakalis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 19.06.2017 12:38:23
-- Design Name: Level-0 Link Health Monitor
-- Module Name: l0_link_health - RTL
-- Project Name: NTUA-BNL VMM3 Readout Firmware
-- Target Devices: Xilinx xc7a200t-2fbg484
-- Tool Versions: Vivado 2017.1
-- Description: Module that checks if there is proper aligmnent with the comma
-- characters on each VMM's link.
--
-- Dependencies:
--
-- Changelog:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
entity l0_link_health is
Generic(is_mmfe8 : std_logic);
Port(
------------------------------------
------- General Interface ----------
clk : in std_logic;
vmm_conf : in std_logic;
daqOn_inhibit : out std_logic;
------------------------------------
--- Deserializer Interface ---------
commas_true : in std_logic_vector(8 downto 1);
------------------------------------
---- Packet Formation Interface ----
EventDone_dummy : out std_logic_vector(8 downto 1);
linkHealth_bitmask : out std_logic_vector(8 downto 1)
);
end l0_link_health;
architecture RTL of l0_link_health is
signal commas_true_i : std_logic_vector(7 downto 0) := (others => '0');
signal linkHealth_bitmask_i : std_logic_vector(7 downto 0) := (others => '0');
signal vmm_id : integer range 0 to 7 := 0;
signal cnt : integer range 0 to 1023 := 0;
constant timeout_conf : integer := 1023;
constant timeout_vmm : integer := 512;
type StateType is (ST_IDLE, ST_CHECK, ST_INCR_ID, ST_DONE);
signal state : StateType := ST_IDLE;
attribute FSM_ENCODING : string;
attribute FSM_ENCODING of state : signal is "ONE_HOT";
begin
-- FSM that labels a VMM link as healthy or not
link_health_FSM: process(clk)
begin
if(rising_edge(clk))then
if(vmm_conf = '1')then
daqOn_inhibit <= '1';
cnt <= 0;
vmm_id <= 0;
linkHealth_bitmask_i <= (others => '0');
state <= ST_IDLE;
else
case state is
-- wait before checking the lines
when ST_IDLE =>
daqOn_inhibit <= '1';
if(cnt < timeout_conf)then
cnt <= cnt + 1;
state <= ST_IDLE;
else
cnt <= 0;
state <= ST_CHECK;
end if;
-- check the VMM lines
when ST_CHECK =>
if(commas_true_i(vmm_id) = '0')then -- misalignment detected, bad link
cnt <= 0;
linkHealth_bitmask_i(vmm_id) <= '0';
state <= ST_INCR_ID;
elsif(cnt = timeout_vmm)then -- link is healthy, proceed
cnt <= 0;
linkHealth_bitmask_i(vmm_id) <= '1';
state <= ST_INCR_ID;
else -- keep counting
cnt <= cnt + 1;
state <= ST_CHECK;
end if;
-- switch to the next VMM, or go to last state
when ST_INCR_ID =>
if(vmm_id = 7 and is_mmfe8 = '1')then -- cycled through all
state <= ST_DONE;
elsif(vmm_id = 0 and is_mmfe8 = '0')then -- only one to check anyway
linkHealth_bitmask_i(1) <= '0';
linkHealth_bitmask_i(2) <= '0';
linkHealth_bitmask_i(3) <= '0';
linkHealth_bitmask_i(4) <= '0';
linkHealth_bitmask_i(5) <= '0';
linkHealth_bitmask_i(6) <= '0';
linkHealth_bitmask_i(7) <= '0';
state <= ST_DONE;
else
vmm_id <= vmm_id + 1;
state <= ST_CHECK;
end if;
-- stay here until a new VMM configuration is sent, let flow_fsm read out the chips
when ST_DONE =>
daqOn_inhibit <= '0';
when others =>
daqOn_inhibit <= '1';
cnt <= 0;
vmm_id <= 0;
linkHealth_bitmask_i <= (others => '0');
state <= ST_IDLE;
end case;
end if;
end if;
end process;
commas_true_i(0) <= commas_true(1);
commas_true_i(1) <= commas_true(2);
commas_true_i(2) <= commas_true(3);
commas_true_i(3) <= commas_true(4);
commas_true_i(4) <= commas_true(5);
commas_true_i(5) <= commas_true(6);
commas_true_i(6) <= commas_true(7);
commas_true_i(7) <= commas_true(8);
linkHealth_bitmask(1) <= linkHealth_bitmask_i(0);
linkHealth_bitmask(2) <= linkHealth_bitmask_i(1);
linkHealth_bitmask(3) <= linkHealth_bitmask_i(2);
linkHealth_bitmask(4) <= linkHealth_bitmask_i(3);
linkHealth_bitmask(5) <= linkHealth_bitmask_i(4);
linkHealth_bitmask(6) <= linkHealth_bitmask_i(5);
linkHealth_bitmask(7) <= linkHealth_bitmask_i(6);
linkHealth_bitmask(8) <= linkHealth_bitmask_i(7);
EventDone_dummy(1) <= not linkHealth_bitmask_i(0);
EventDone_dummy(2) <= not linkHealth_bitmask_i(1);
EventDone_dummy(3) <= not linkHealth_bitmask_i(2);
EventDone_dummy(4) <= not linkHealth_bitmask_i(3);
EventDone_dummy(5) <= not linkHealth_bitmask_i(4);
EventDone_dummy(6) <= not linkHealth_bitmask_i(5);
EventDone_dummy(7) <= not linkHealth_bitmask_i(6);
EventDone_dummy(8) <= not linkHealth_bitmask_i(7);
end RTL; | gpl-3.0 | a1fa7da6badb0bd6c72b8bd1a056610f | 0.482434 | 4.150402 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/EPROC_IN8_direct.vhd | 2 | 2,785 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 04/13/2015
--! Module Name: EPROC_IN8_direct
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.centralRouter_package.all;
--! direct data driver for EPROC_IN2 module
entity EPROC_IN8_direct is
port (
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
edataIN : in std_logic_vector (7 downto 0);
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic
);
end EPROC_IN8_direct;
architecture Behavioral of EPROC_IN8_direct is
----------------------------------
----------------------------------
component pulse_pdxx_pwxx
generic(
pd : integer := 0;
pw : integer := 1);
port(
clk : in std_logic;
trigger : in std_logic;
pulseout : out std_logic
);
end component pulse_pdxx_pwxx;
----------------------------------
----------------------------------
signal word10b : std_logic_vector (9 downto 0) := "1100000000"; -- comma
signal word8b, word8b_s : std_logic_vector (7 downto 0) := (others=>'0');
signal word8bRdy, word10bRdy : std_logic := '0';
begin
-------------------------------------------------------------------------------------------
-- input registers
-------------------------------------------------------------------------------------------
input_map: process(bitCLKx2)
begin
if bitCLKx2'event and bitCLKx2 = '1' then
word8b_s <= edataIN;
word8b <= word8b_s;
end if;
end process;
-------------------------------------------------------------------------------------------
-- output (code = "00" = data)
-------------------------------------------------------------------------------------------
process(bitCLKx2, rst)
begin
if rst = '1' then
word8bRdy <= '0';
elsif bitCLKx2'event and bitCLKx2 = '1' then
word8bRdy <= not word8bRdy;
end if;
end process;
--
process(bitCLKx2, rst)
begin
if rst = '1' then
word10bRdy <= '0';
elsif bitCLKx2'event and bitCLKx2 = '1' then
if word8bRdy = '1' then
word10b <= "00" & word8b; -- data
word10bRdy <= '1';
else
word10bRdy <= '0';
end if;
end if;
end process;
dataOUT <= word10b;
dataOUTrdy_pulse: pulse_pdxx_pwxx GENERIC MAP(pd=>0,pw=>1) PORT MAP(bitCLKx4, word10bRdy, dataOUTrdy);
end Behavioral;
| gpl-3.0 | 9478a860dc981f3dd0c6093033a8e62f | 0.435548 | 4.053857 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/FIR_Filter/multichannel_fir_tap.vhd | 1 | 3,841 | --------------------------------------------------------------------------------------------------
-- Multi-channel FIR Tap
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- PACKAGE
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.dsp_pkg.all;
package multichannel_fir_tap_pkg is
--FIR tap component declaration
component multichannel_fir_tap is
port( clk : in std_logic;
rst : in std_logic;
coef : in coefficient;
sig_in : in sig;
sig_out : out sig;
sum_in : in fir_sig;
sum_out : out fir_sig);
end component;
end package;
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dsp_pkg.all;
--This entity represents a single tap in a FIR filter. The taps are designed to implement a
--cascade adder allowing for chaining an indefinite (tho definitely finite) number of taps.
entity multichannel_fir_tap is
port( clk : in std_logic;
rst : in std_logic;
coef : in coefficient;
sig_in : in sig;
sig_out : out sig;
sum_in : in fir_sig;
sum_out : out fir_sig);
end multichannel_fir_tap;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE (behavioral)
--------------------------------------------------------------------------------------------------
architecture behave of multichannel_fir_tap is
signal sig_delay : sig_array(1 to 4) := (others => (others => '0'));
signal coef_reg : coefficient := (others => '0');
signal product : fir_sig := (others => '0');
begin
--delay the input signal
delay_sig : process(clk)
begin
if(rising_edge(clk)) then
if(rst = '1') then
sig_delay <= (others => (others => '0'));
else
sig_delay(1) <= sig_in;
sig_delay(2) <= sig_delay(1);
sig_delay(3) <= sig_delay(2);
sig_delay(4) <= sig_delay(3);
end if;
end if;
end process;
sig_out <= sig_delay(3);
--register the coefficient
reg_coef : process(clk)
begin
if(rising_edge(clk)) then
if(rst = '1') then
coef_reg <= (others => '0');
else
coef_reg <= coef;
end if;
end if;
end process;
--multiply the signal to the tap coefficient
multiply : process(clk)
begin
if(rising_edge(clk)) then
if(rst = '1') then
product <= (others => '0');
else
product <= resize(sig_delay(4) * coef_reg, NUM_FIR_BITS);
end if;
end if;
end process;
--update the sum
update_sum : process(clk)
begin
if(rising_edge(clk)) then
if(rst = '1') then
sum_out <= (others => '0');
else
sum_out <= sum_in + product;
end if;
end if;
end process;
end behave;
| mit | 0070f3ce669c109a8613b2f3a83e361d | 0.383754 | 4.843632 | false | false | false | false |
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