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adelapie/noekeon | tb_pi_2.vhd | 5 | 2,708 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_pi_2 IS
END tb_pi_2;
ARCHITECTURE behavior OF tb_pi_2 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT pi_2
PORT(
a_1_in : IN std_logic_vector(31 downto 0);
a_2_in : IN std_logic_vector(31 downto 0);
a_3_in : IN std_logic_vector(31 downto 0);
a_1_out : OUT std_logic_vector(31 downto 0);
a_2_out : OUT std_logic_vector(31 downto 0);
a_3_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal a_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_3_in : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal a_1_out : std_logic_vector(31 downto 0);
signal a_2_out : std_logic_vector(31 downto 0);
signal a_3_out : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: pi_2 PORT MAP (
a_1_in => a_1_in,
a_2_in => a_2_in,
a_3_in => a_3_in,
a_1_out => a_1_out,
a_2_out => a_2_out,
a_3_out => a_3_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
a_1_in <= X"43575679";
a_2_in <= X"465647e0";
a_3_in <= X"c002aeef";
wait for clk_period;
assert a_1_out = X"a1abab3c"
report "PI1 ERROR (a_0)" severity FAILURE;
assert a_2_out = X"0232b23f"
report "PI1 ERROR (a_1)" severity FAILURE;
assert a_3_out = X"f000abbb"
report "PI1 ERROR (a_2)" severity FAILURE;
wait;
end process;
END;
| gpl-3.0 | 0446d572af42495b98a5d1db3c51d956 | 0.594165 | 3.231504 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/MMFE8_1VMM/sources_1/configuration/config_logic.vhd | 1 | 25,237 | ----------------------------------------------------------------------------------
-- Company: NTU ATHNENS - BNL
-- Engineer: Panagiotis Gkountoumis
--
-- Create Date: 18.04.2016 13:00:21
-- Design Name:
-- Module Name: config_logic - Behavioral
-- Project Name: MMFE8
-- Target Devices: Arix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2016.2
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity config_logic is
Port (
clk125 : in std_logic;
clk200 : in std_logic;
clk_in : in std_logic;
reset : in std_logic;
user_data_in : in std_logic_vector (7 downto 0);
user_data_out : out std_logic_vector (63 downto 0);
udp_rx : in udp_rx_type;
resp_data : out udp_response;
send_error : out std_logic;
user_conf : out std_logic;
user_wr_en : in std_logic;
user_last : in std_logic;
configuring : in std_logic;
we_conf : out std_logic;
conf_packet_length : out integer;
vmm_id : out std_logic_vector(15 downto 0);
cfg_bit_out : out std_logic ;
vmm_cktk : out std_logic ;
status : out std_logic_vector(3 downto 0);
start_vmm_conf : in std_logic;
conf_done : out std_logic;
ext_trigger : out std_logic;
ACQ_sync : out std_logic_vector(15 downto 0);
-- vmm_we : in std_logic;
udp_header : in std_logic;
packet_length : in std_logic_vector (15 downto 0));
end config_logic;
architecture rtl of config_logic is
signal packet_length_int : integer := 0;
signal reading_packet : std_logic := '0';
signal user_last_int : std_logic := '0';
signal count, timeout : integer := 0;
signal last_synced200 : std_logic := '0';
signal i,w,del_cnt : integer := 0;
signal del_cnt2 : integer := 0;
signal counter, k, j : integer := 0;
signal sig_out : std_logic_vector(255 downto 0);
signal sn : std_logic_vector(31 downto 0);
signal vmm_id_int : std_logic_vector(15 downto 0);
signal cmd : std_logic_vector(15 downto 0);
signal user_data_in_int : std_logic_vector(7 downto 0);
signal status_int : std_logic_vector(3 downto 0);
signal user_wr_en_int : std_logic := '0';
signal cfg_bit_out_i : std_logic := '0';
signal vmm_cktk_i : std_logic := '0';
signal start_conf_process : std_logic := '0';
signal conf_done_i : std_logic := '0';
signal cnt_array : integer := 0;
signal MainFSMstate : std_logic_vector(3 downto 0);
signal ConfFSMstate : std_logic_vector(3 downto 0);
signal test_data_int : std_logic_vector(31 downto 0);
signal delay_data : std_logic_vector(7 downto 0);
signal udp_header_int : std_logic := '0';
type data_buffer is array(0 to 60) of std_logic_vector(31 downto 0);
signal conf_data : data_buffer;
signal reply_package : std_logic_vector(63 downto 0);
signal udp_response_int : udp_response;
signal start_vmm_conf_int : std_logic := '0';
signal start_vmm_conf_synced : std_logic := '0';
-- signal we_conf_int : std_logic := '0';
signal vmm_we_int : std_logic := '0';
signal cnt_cktk : integer := 0;
signal DAQ_START_STOP : std_logic_vector(31 downto 0);
signal dest_port : std_logic_vector(15 downto 0);
signal data_length : integer := 0;
signal cnt_reply : integer := 0;
signal delay_user_last : std_logic := '0';
signal ERROR : std_logic_vector(15 downto 0);
type tx_state is (IDLE, SerialNo, VMMID, COMMAND, DATA, CHECK, VMM_CONF, DELAY, FPGA_CONF, XADC, SEND_REPLY, TEST, REPLY);
signal state : tx_state;
type state_t is (START, SEND1,SEND0, FINISHED);
signal conf_state : state_t;
attribute keep : string;
attribute dont_touch : string;
attribute keep of sn : signal is "true";
attribute keep of vmm_id_int : signal is "true";
attribute keep of user_last_int : signal is "true";
attribute keep of cmd : signal is "true";
attribute keep of count : signal is "true";
attribute keep of last_synced200 : signal is "true";
attribute keep of reading_packet : signal is "true";
attribute keep of user_data_in_int : signal is "true";
attribute keep of user_wr_en_int : signal is "true";
attribute keep of packet_length_int : signal is "true";
attribute keep of cfg_bit_out_i : signal is "true";
attribute keep of status_int : signal is "true";
attribute keep of start_conf_process : signal is "true";
attribute keep of conf_done_i : signal is "true";
attribute keep of DAQ_START_STOP : signal is "true";
attribute dont_touch of DAQ_START_STOP : signal is "true";
attribute keep of user_wr_en : signal is "true";
attribute dont_touch of user_wr_en : signal is "true";
attribute keep of MainFSMstate : signal is "true";
attribute keep of ConfFSMstate : signal is "true";
attribute keep of test_data_int : signal is "true";
attribute keep of delay_data : signal is "true";
attribute keep of i : signal is "true";
attribute keep of vmm_cktk_i : signal is "true";
attribute keep of cnt_array : signal is "true";
attribute keep of udp_header_int : signal is "true";
attribute keep of j : signal is "true";
attribute keep of start_vmm_conf_int : signal is "true";
attribute keep of start_vmm_conf_synced : signal is "true";
attribute keep of dest_port : signal is "true";
-- attribute keep of vmm_we_int : signal is "true";
-- attribute dont_touch of vmm_we_int : signal is "true";
attribute keep of cnt_cktk : signal is "true";
attribute dont_touch of cnt_cktk : signal is "true";
attribute keep of k : signal is "true";
attribute dont_touch of k : signal is "true";
attribute keep of counter : signal is "true";
attribute dont_touch of counter : signal is "true";
attribute keep of del_cnt : signal is "true";
attribute dont_touch of del_cnt : signal is "true";
component ila_user_FIFO IS
PORT (
clk : IN std_logic;
probe0 : IN std_logic_vector(255 DOWNTO 0)
);
end component;
begin
process (clk125)
begin
if clk125'event and clk125 = '1' then
user_wr_en_int <= user_wr_en;
delay_data <= user_data_in;
delay_user_last <= user_last;
end if;
end process;
user_last_int <= user_last;
user_data_in_int <= user_data_in;
--synced_to_125: process(clk125)
-- begin
-- if rising_edge(clk125) then
-- start_vmm_conf_synced <= start_vmm_conf_int;
-- end if;
-- end process;
------------------------ IDLE 0000
------------------------ VMM_CONF 0001
------------------------ XADC 0010
------------------------ RESET FPGA 0011
------------------------ DAQ OFF 1000
------------------------ FPGA_CONF 1001
------------------------ REPLY 1011
------------------------ DAQ ON 1111
process (clk125, state, configuring, cmd, reading_packet, count, packet_length_int, user_wr_en_int, last_synced200, user_wr_en, dest_port)
-- variable i : natural range 0 to 10 := 0; --1ms
begin
if clk125'event and clk125 = '1' then
if reset = '1' then
state <= IDLE;
else
case state is
when IDLE =>
MainFSMstate <= "0000";
status_int <= "0000";
count <= 0;
j <= 3;
cnt_array <= 0;
sn <= (others=> '0');
vmm_id_int <= x"0000";
cmd <= x"0000";
if user_wr_en = '1' then
state <= DATA;
end if;
when DATA =>
MainFSMstate <= "0001";
if j = 0 then
cnt_array <= cnt_array + 1;
conf_data(cnt_array)(8*j+ 7 downto 8*j) <= delay_data;
j <= 3;
else
conf_data(cnt_array)(8*j+ 7 downto 8*j) <= delay_data;
j <= j - 1;
end if;
if delay_user_last = '1' then
cnt_array <= 0;
-- count <= 4;
j <= 0;
state <= SerialNo;
end if;
when SerialNo =>
MainFSMstate <= "0010";
-- count <= count - 1;
sn <= conf_data(0);
reply_package(63 downto 32) <= sn;
state <= VMMID;
when VMMID =>
MainFSMstate <= "0011";
vmm_id_int <= conf_data(1)(31 downto 16);
packet_length_int <= to_integer(unsigned(packet_length));
data_length <= packet_length_int - 8;
reply_package(31 downto 16) <= vmm_id_int;
state <= COMMAND;
when COMMAND =>
MainFSMstate <= "0100";
cmd <= conf_data(1)(15 downto 0);
reply_package(15 downto 0) <= cmd;
state <= CHECK;
when CHECK =>
MainFSMstate <= "0101";
if dest_port = x"1778" then -- 6008 VMM CONFIGURATION
state <= VMM_CONF;
if vmm_id_int /= x"ffff" then
status_int <= "0001";
else
status_int <= "0010";
end if;
elsif dest_port = x"19C8" or dest_port = x"1777" then -- 6600 FPGA CONFIGURATION
cmd <= conf_data(1)(31 downto 16);
vmm_id_int <= conf_data(1)(15 downto 0);
state <= FPGA_CONF;
status_int <= "1001";
count <= 0;
elsif dest_port = x"19D0" then -- 6608 XADC
state <= XADC;
status_int <= "0010";
else
count <= 0;
state <= IDLE;
end if;
when VMM_CONF =>
MainFSMstate <= "0110";
if timeout = 5000000 then
state <= IDLE;
timeout <= 0;
ERROR <= x"ffff";
else
timeout <= timeout + 1;
end if;
if conf_done_i = '1' then
-- user_data_out <= reply_package;
state <= DELAY;-- SEND_REPLY;
-- reading_packet <= '0';
ERROR <= x"0000";
status_int <= "1011";
end if;
when DELAY =>
if del_cnt2 = 10 then
state <= REPLY;
del_cnt2 <= 0;
else
del_cnt2 <= del_cnt2 + 1;
end if;
when XADC =>
when FPGA_CONF =>
MainFSMstate <= "1011";
-- DAQ_START_STOP <= conf_data(count+2);
-------------------------------------set this for the real configuration
-- if count*8 <= data_length then
-- if conf_data(count + 2) = x"00000000" and conf_data(count + 3) = x"00000004" then -- EXTERNAL
-- ext_trigger <= '1';
-- elsif conf_data(count + 2) = x"00000000" and conf_data(count + 3) = x"00000007" then -- PULSER
-- ext_trigger <= '0';
-- elsif conf_data(count + 2) = x"00001111" and conf_data(count + 3) = x"00000001" then -- DAQ ON
-- status_int <= "1111";
-- elsif conf_data(count + 2) = x"00001111" and conf_data(count + 3) = x"00000000" then -- DAQ OFF
-- status_int <= "1000";
-- elsif conf_data(count + 2) = x"ffffffff" and conf_data(count + 3) = x"ffff8000" then -- RESET FPGA
-- status_int <= "0011";
-- else
-- state <= IDLE;
-- end if;
-- else
-- count <= 0;
-- state <= IDLE;
-- end if;
-------------------------------------set this for the real configuration
DAQ_START_STOP <= conf_data(4);
if conf_data(5) = x"00000004" and conf_data(4) = x"00000000" then -- EXTERNAL
ext_trigger <= '1';
state <= TEST;
elsif conf_data(5) = x"00000007" and conf_data(4) = x"00000000" then -- PULSER
ext_trigger <= '0';
state <= TEST;
elsif conf_data(5) = x"00000001" and conf_data(4) = x"0000000f" then -- DAQ ON
status_int <= "1111";
state <= TEST;
elsif conf_data(5) = x"00000000" and conf_data(4) = x"0000000f" then -- DAQ OFF
status_int <= "1000";
state <= TEST;
elsif conf_data(4) = x"ffffffff" and conf_data(5) = x"ffff8000" then -- RESET FPGA
status_int <= "0011";
state <= IDLE;
elsif conf_data(4) = x"00000005" then -- RESET FPGA
ACQ_sync <= conf_data(5)(15 downto 0);
state <= IDLE;
else
state <= TEST;
end if;
when TEST =>
if count < 10 then
DAQ_START_STOP <= conf_data(count);
count <= count + 1;
else
count <= 0;
state <= IDLE;
end if;
when REPLY =>
state <= IDLE;
-- if cnt_reply = 0 then
---- user_data_out_i <= conf_data_out_i;
-- user_data_out <= reply_package;
-- cnt_reply <= cnt_reply + 1;
-- elsif cnt_reply = 1 then
-- user_data_out_i <= (others => '0');
-- cnt_reply <= cnt_reply + 1;
-- end_packet_conf_int <= '1';
-- we_conf_int <= '0';
-- elsif cnt_reply > 1 and cnt_reply < 100 then
-- cnt_reply <= cnt_reply + 1;
-- else
-- cnt_reply <= 0;
-- state <= IDLE;
---- state <= DAQ_INIT;
-- end_packet_conf_int <= '1';
-- end if;
when others =>
end case;
end if;
end if;
end process;
--synced_to_clkin: process(clk_in)
-- begin
-- if rising_edge(clk_in) then
-- start_vmm_conf_synced <= start_vmm_conf;
-- end if;
-- end process;
sync_start_vmm_conf: process(clk200)
begin
if rising_edge(clk200) then
if start_vmm_conf = '1' then
start_vmm_conf_synced <= '1';
end if;
if w = 40 then
start_vmm_conf_synced <= '0';
w <= 0;
else
w <= w + 1;
end if;
end if;
end process;
config_vmm_fsm : process( clk_in, conf_state, k, i, counter, del_cnt)
begin
if rising_edge( clk_in) then
if reset = '1' or status_int = "0011" then
conf_state <= START;
else
case conf_state is
when START =>
ConfFSMstate <= "0001";
-- counter <= (packet_length_int - 16) * 8;
counter <= 1616;
i <= 31;
k <= 2;
cfg_bit_out_i <= '0';
test_data_int <= conf_data(k);
conf_done_i <= '0';
if start_vmm_conf = '1' then
conf_state <= SEND0;
end if;
when SEND0 =>
ConfFSMstate <= "0010";
vmm_cktk_i <= '1';
conf_state <= SEND1;
cnt_cktk <= cnt_cktk + 1;
if k <= packet_length_int - 1 then
test_data_int <= conf_data(k);
if i /= 0 then
cfg_bit_out_i <= conf_data(k)(i);--(0);
i <= i - 1;
else
cfg_bit_out_i <= conf_data(k)(0);
k <= k + 1;
i <= 31;
end if;
end if;
when SEND1 =>
ConfFSMstate <= "0011";
-- i <= 0;
vmm_cktk_i <= '0';
if (counter - 2) >= 0 then
counter <= counter - 1;
conf_state <= SEND0;
else
-- conf_done_i <= '1';
conf_state <= FINISHED;
end if;
when FINISHED =>
ConfFSMstate <= "0100";
cfg_bit_out_i <= '0';
if del_cnt = 5 then
conf_done_i <= '1';
del_cnt <= del_cnt + 1;
elsif del_cnt = 100 then
conf_state <= START;
del_cnt <= 0;
else
del_cnt <= del_cnt + 1;
end if;
-- conf_done_i <= '1';
vmm_cktk_i <= '0';
counter <= 0;
cnt_cktk <= 0;
end case;
end if;
end if;
end process config_vmm_fsm ;
start_vmm_conf_int <= start_vmm_conf;
vmm_id <= vmm_id_int;
dest_port <= udp_rx.hdr.dst_port;
status <= status_int;
conf_done <= conf_done_i;
cfg_bit_out <= cfg_bit_out_i;
vmm_cktk <=vmm_cktk_i;
ila_conf_logic : ila_user_FIFO
port map(
clk => clk125,
probe0 => sig_out
);
--we_conf <= we_conf_int;
--vmm_we_int <= vmm_we;
sig_out(7 downto 0) <= delay_data;
sig_out(8) <= start_vmm_conf_int;--user_fifo_empty;
sig_out(9) <= start_vmm_conf_synced;--user_fifo_en_main;--'0'; --user_fifo_en;
sig_out(10) <= udp_header_int;--send_error_int;
sig_out(11) <= user_wr_en;
sig_out(43 downto 12) <= sn;
sig_out(59 downto 44) <= vmm_id_int;
sig_out(75 downto 60) <= cmd;
sig_out(83 downto 76) <= std_logic_vector(to_unsigned(count, sig_out(83 downto 76)'length));
sig_out(91 downto 84) <= std_logic_vector(to_unsigned(cnt_array, sig_out(91 downto 84)'length));
sig_out(92) <= user_last_int;
sig_out(93) <= last_synced200;
--sig_out(110) <= reading_packet;
sig_out(101 downto 94) <= user_data_in_int;
sig_out(102) <= user_wr_en_int;
sig_out(103) <= vmm_cktk_i;--user_conf_int;
sig_out(104) <= cfg_bit_out_i;--reset_fifo_int;
sig_out(112 downto 105) <= std_logic_vector(to_unsigned(packet_length_int, sig_out(112 downto 105)'length));
sig_out(113) <= conf_done_i;--configuring_int;
sig_out(117 downto 114) <= status_int;
sig_out(118) <= start_conf_process;
sig_out(122 downto 119) <= MainFSMstate;
sig_out(126 downto 123) <= ConfFSMstate;
sig_out(134 downto 127) <= std_logic_vector(to_unsigned(i, sig_out(135 downto 128)'length));
sig_out(166 downto 135) <= test_data_int;
sig_out(174 downto 167) <= std_logic_vector(to_unsigned(j, sig_out(175 downto 168)'length));
sig_out(190 downto 175) <= std_logic_vector(to_unsigned(counter, sig_out(190 downto 175)'length));
sig_out(198 downto 191) <= std_logic_vector(to_unsigned(k, sig_out(198 downto 191)'length));
sig_out(214 downto 199) <= dest_port;
--sig_out(224) <= we_conf_int;
sig_out(246 downto 215) <= DAQ_START_STOP;
--sig_out(2) <= vmm_we;
--sig_out(18 downto 3) <= std_logic_vector(to_unsigned(k, sig_out(18 downto 3)'length));
--sig_out(34 downto 19) <= std_logic_vector(to_unsigned(cnt_cktk, sig_out(34 downto 19)'length));
--sig_out(50 downto 35) <= std_logic_vector(to_unsigned(counter, sig_out(50 downto 35)'length));
--sig_out(66 downto 51) <= std_logic_vector(to_unsigned(del_cnt, sig_out(66 downto 51)'length));
sig_out(255 downto 247) <= (others => '0');
end rtl; | gpl-3.0 | f021f49a871309059ccaa5a8ad171217 | 0.394302 | 4.41515 | false | false | false | false |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_1_1/sim/ZynqDesign_axi_gpio_1_1.vhd | 1 | 8,767 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0;
USE axi_gpio_v2_0.axi_gpio;
ENTITY ZynqDesign_axi_gpio_1_1 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ZynqDesign_axi_gpio_1_1;
ARCHITECTURE ZynqDesign_axi_gpio_1_1_arch OF ZynqDesign_axi_gpio_1_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ZynqDesign_axi_gpio_1_1_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 8,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 1,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END ZynqDesign_axi_gpio_1_1_arch;
| mit | f1fd14774be4ec27f0984648e42775d7 | 0.680621 | 3.26032 | false | false | false | false |
tfiwits/93c46_eeprom | eeprom.vhd | 1 | 8,060 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity eeprom is
port(
sw_in:in std_logic_vector(3 downto 0);
addr:in std_logic_vector(6 downto 0);
addr_16:in std_logic_vector(5 downto 0);
cs: out std_logic;
di: out std_logic;
do: in std_logic;
send_ok:in std_logic;
aa,ss:out std_logic;
org_in:in std_logic;
org: out std_logic;
clk_in: in std_logic;
sk:out std_logic;
data_out:out std_logic_vector(7 downto 0);
data_out_16:out std_logic_vector(15 downto 0)
);
end eeprom;
architecture a of eeprom is
signal sta : std_logic_vector(3 downto 0):="1000";
signal hh:std_logic:='0';
signal aa_sig:std_logic:='0';
signal ss_sig:std_logic:='0';
signal clk_sig:std_logic;
signal st_a:std_logic_vector(8 downto 0):="000000000";
signal di_tmp: std_logic_vector(21 downto 0);
signal di_tmp_16: std_logic_vector(26 downto 0);
signal di_tmp_s: std_logic;
signal data_in : std_logic_vector(15 downto 0);
signal data_in_16 : std_logic_vector(18 downto 0);
signal data_out_tmp:std_logic_vector(7 downto 0);
signal data_out_tmp_16:std_logic_vector(15 downto 0);
signal chk:std_logic;
--"000"wait
--"001"ERASE
--"010"WRITE
--"011"EWEN--s
--"100"EWDS-st
--"101"ERAL-e-all
--"110"WRAL-s-all
--"111"sw-wait
--"1000"read
begin
process(clk_in)
variable stt:integer:=0;
begin
if clk_in'event and clk_in='1' then
if stt=2700 then
clk_sig<=not clk_sig;
stt:=0;
else
stt:=stt+1;
end if;
end if;
end process;
process(sta,clk_sig,send_ok,org_in)
variable st : integer:=21;
variable do_st:integer:=9;
variable st_16 : integer:=26;
variable do_st_16:integer:=17;
begin
if clk_sig'event and clk_sig='1' then
if org_in='0' then
case sta is
when "0000"=>
if sw_in/="0000" then
sta<="0011";
else
sta<="0000";
end if;
when "0001"=>
cs<='1';
di_tmp(21 downto 0)<=(di_tmp'range=>'0');
di_tmp(21 downto 12)<="111" & addr;
if st>11 then
di_tmp_s<=di_tmp(st);
st:=st-1;
else
di_tmp_s<='0';
cs<='0';
st:=21;
sta<="0100";
end if;
when "0010"=>
cs<='1';
di_tmp(21 downto 0)<=(di_tmp'range=>'0');
data_out_tmp<="10000010";
di_tmp(21 downto 4)<="101" & addr & data_out_tmp;
if st>3 then
di_tmp_s<=di_tmp(st);
st:=st-1;
else
cs<='0';
di_tmp_s<='0';
st:=21;
sta<="0100";
end if;
when "0011"=>
cs<='1';
di_tmp(21 downto 0)<=(di_tmp'range=>'0');
di_tmp(21 downto 12)<="100" & "1100000";
if st>11 then
di_tmp_s<=di_tmp(st);
st:=st-1;
else
di_tmp_s<='0';
cs<='0';
st:=21;
hh<='0';
sta<="0111";
end if;
when "0100"=>
cs<='1';
di_tmp(21 downto 0)<=(di_tmp'range=>'0');
di_tmp(21 downto 12)<="100" & "0000000";
if st>11 then
di_tmp_s<=di_tmp(st);
st:=st-1;
else
di_tmp_s<='0';
cs<='0';
st:=21;
hh<='1';
sta<="0111";
end if;
when "0101"=>
cs<='1';
di_tmp(21 downto 0)<=(di_tmp'range=>'0');
di_tmp(21 downto 12)<="100" & "1000000";
if st>11 then
di_tmp_s<=di_tmp(st);
st:=st-1;
else
di_tmp_s<='0';
cs<='0';
st:=21;
sta<="0100";
end if;
when "0110"=>
cs<='1';
di_tmp(21 downto 0)<=(di_tmp'range=>'0');
di_tmp(21 downto 4)<="100" & "0100000" & data_out_tmp;
if st>3 then
di_tmp_s<=di_tmp(st);
st:=st-1;
else
di_tmp_s<='0';
cs<='0';
st:=21;
sta<="0100";
end if;
when "0111"=>
cs<='0';
if st_a="111111111" then
st_a<="000000000";
if hh='0' then
sta<=sw_in;
aa_sig<='1';
else
aa_sig<='0';
sta<="0000";
end if;
else
st_a<=st_a+1;
end if;
when "1000"=>
cs<='1';
di_tmp(21 downto 0)<=(di_tmp'range=>'0');
di_tmp(21 downto 12)<="110" & addr;
if st>11 then
di_tmp_s<=di_tmp(st);
st:=st-1;
else
di_tmp_s<='0';
if do_st<0 then
data_out<=data_in(7 downto 0);
cs<='0';
st:=21;
do_st:=9;
ss_sig<='1';
sta<="0100";
else
data_in(do_st)<=do;
do_st:=do_st-1;
end if;
end if;
when others=>
null;
end case;
org<='0';
else
case sta is
when "0000"=>
if sw_in/="0000" then
sta<="0011";
else
sta<="0000";
end if;
when "0001"=>
cs<='1';
di_tmp(21 downto 0)<=(di_tmp'range=>'0');
di_tmp(21 downto 13)<="111" & addr_16;
if st>12 then
di_tmp_s<=di_tmp(st);
st:=st-1;
else
di_tmp_s<='0';
cs<='0';
st:=21;
sta<="0100";
end if;
when "0010"=>
cs<='1';
di_tmp_16(26 downto 0)<=(di_tmp_16'range=>'0');
di_tmp_16(26 downto 2)<="101" & addr_16 & data_out_tmp_16;
if st>=2 then
di_tmp_s<=di_tmp_16(st_16);
st:=st-1;
else
cs<='0';
di_tmp_s<='0';
st_16:=26;
sta<="0100";
end if;
when "0011"=>
cs<='1';
di_tmp(21 downto 0)<=(di_tmp'range=>'0');
di_tmp(21 downto 13)<="100" & "110000";
if st>12 then
di_tmp_s<=di_tmp(st);
st:=st-1;
else
di_tmp_s<='0';
cs<='0';
st:=21;
hh<='0';
sta<="0111";
end if;
when "0100"=>
cs<='1';
di_tmp(21 downto 0)<=(di_tmp'range=>'0');
di_tmp(21 downto 13)<="100" & "000000";
if st>12 then
di_tmp_s<=di_tmp(st);
st:=st-1;
else
di_tmp_s<='0';
cs<='0';
st:=21;
hh<='1';
sta<="0111";
end if;
when "0101"=>
cs<='1';
di_tmp(21 downto 0)<=(di_tmp'range=>'0');
di_tmp(21 downto 13)<="100" & "100000";
if st>12 then
di_tmp_s<=di_tmp(st);
st:=st-1;
else
di_tmp_s<='0';
cs<='0';
st:=21;
sta<="0100";
end if;
when "0110"=>
cs<='1';
di_tmp_16(26 downto 0)<=(di_tmp_16'range=>'0');
di_tmp_16(26 downto 2)<="100" & "010000" & data_out_tmp_16;
if st_16>=2 then
di_tmp_s<=di_tmp_16(st_16);
st:=st-1;
else
di_tmp_s<='0';
cs<='0';
st_16:=26;
sta<="0100";
end if;
when "0111"=>
cs<='0';
if st_a="111111111" then
st_a<="000000000";
if hh='0' then
sta<=sw_in;
aa_sig<='1';
else
aa_sig<='0';
sta<="0000";
end if;
else
st_a<=st_a+1;
end if;
when "1000"=>
cs<='1';
di_tmp(21 downto 0)<=(di_tmp'range=>'0');
di_tmp(21 downto 13)<="110" & addr_16;
if st>12 then
di_tmp_s<=di_tmp(st);
st:=st-1;
else
di_tmp_s<='0';
if do_st<0 then
data_out_16<=data_in_16(15 downto 0);
cs<='0';
st:=21;
do_st_16:=17;
ss_sig<='1';
sta<="0100";
else
data_in_16(do_st_16)<=do;
do_st_16:=do_st_16-1;
end if;
end if;
when others=>
null;
end case;
org<='1';
end if;
end if;
if send_ok='1' then
ss_sig<='0';
end if;
end process;
sk<=clk_sig;
ss<=ss_sig;
aa<=aa_sig;
di<=di_tmp_s;
end a; | gpl-2.0 | 6aa1cd540f9cfe0d32da5668efcddf97 | 0.434988 | 2.817197 | false | false | false | false |
qynvi/rtl-paritygen | paritygen.vhd | 1 | 559 | -- William Fan
-- 02/14/2011
-- Parity Gen RTL
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity paritygen is
generic (N: positive := 7);
port (x: in bit_vector(N-1 downto 0);
y: out bit_vector(N downto 0));
end entity;
architecture pg of paritygen is
signal temp: bit_vector(n-1 downto 0);
signal nparity: bit;
begin
temp(0) <= x(0);
gen: for i in 1 to n-1 generate
temp(i) <= temp(i-1) XOR x(i);
end generate;
nparity <= temp(N-1) NAND temp(N-1);
y(N-1 downto 0) <= x;
y(N) <= nparity;
end architecture;
| mit | e5dc134112f336d559af345fb6d25678 | 0.647585 | 2.56422 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/readout/vmm_readout.vhd | 1 | 27,505 | ----------------------------------------------------------------------------------
-- Company: NTU ATHENS - BNL
-- Engineer: Paris Moschovakos
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Paris Moschovakos
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 21.07.2016
-- Design Name:
-- Module Name: vmm_readout.vhd - Behavioral
-- Project Name: MMFE8
-- Target Devices: Artix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2016.2
--
-- Changelog:
-- 22.08.2016 Changed state_dt (integer) to state_dt (4 bit vector) (Reid Pinkham)
-- 26.02.2017 Moved to a global clock domain @125MHz (Paris)
-- 06.06.2017 Added vmm_driver interfacing process and readout buffer. (Christos Bakalis)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity vmm_readout is
Port (
clkTkProc : in std_logic; -- Used to clock checking for data process
clkDtProc : in std_logic; -- Used to clock word readout process
clk : in std_logic; -- Main clock
vmm_data0_vec : in std_logic_vector(8 downto 1); -- Single-ended data0 from VMM
vmm_data1_vec : in std_logic_vector(8 downto 1); -- Single-ended data1 from VMM
vmm_ckdt_enable : out std_logic_vector(8 downto 1); -- Enable signal for VMM CKDT
vmm_cktk_vec : out std_logic_vector(8 downto 1); -- Strobe to VMM CKTK
vmm_wen_vec : out std_logic_vector(8 downto 1); -- Strobe to VMM WEN
vmm_ena_vec : out std_logic_vector(8 downto 1); -- Strobe to VMM ENA
vmm_ckdt : out std_logic; -- Strobe to VMM CKDT
daq_enable : in std_logic;
trigger_pulse : in std_logic; -- Trigger
cktk_max : in std_logic_vector(7 downto 0); -- Max number of CKTKs
vmmId : in std_logic_vector(2 downto 0); -- VMM to be readout
ethernet_fifo_wr_en : out std_logic; -- To be used for reading out seperate FIFOs in VMMx8 parallel readout
vmm_data_buf : buffer std_logic_vector(37 downto 0);
vmmWordReady : out std_logic;
vmmWord : out std_logic_vector(15 downto 0);
vmmEventDone : out std_logic;
rd_en : in std_logic;
dt_state_o : out std_logic_vector(3 downto 0);
dt_cntr_st_o : out std_logic_vector(3 downto 0)
);
end vmm_readout;
architecture Behavioral of vmm_readout is
-- Interconnected signals
signal reading_out_word : std_logic := '0';
signal reading_out_word_stage1 : std_logic := '0';
signal reading_out_word_ff_sync : std_logic := '0';
signal reading_out_word_i_125 : std_logic := '0';
signal reading_out_word_s_125 : std_logic := '0';
signal cktkSent : std_logic := '0';
signal cktkSent_stage1 : std_logic := '0';
signal cktkSent_ff_sync : std_logic := '0';
signal timeoutCnt : unsigned(3 downto 0) := b"0000";
signal timeout : unsigned(3 downto 0) := b"0111";
signal daq_enable_stage1_Dt : std_logic := '0';
signal daq_enable_ff_sync_Dt : std_logic := '0';
-- tokenProc
signal state_tk : std_logic_vector( 3 downto 0 ) := x"1";
signal daq_enable_stage1 : std_logic := '0';
signal daq_enable_ff_sync : std_logic := '0';
signal vmm_wen_i : std_logic := '0';
signal vmm_ena_i : std_logic := '0';
signal vmm_cktk_i : std_logic := '0';
signal NoFlg_counter : unsigned(7 downto 0) := (others => '0'); -- Counter of CKTKs
signal cktk_max_i : std_logic_vector(7 downto 0) := x"07";
signal cktk_max_sync : std_logic_vector(7 downto 0) := x"07";
signal vmmEventDone_i : std_logic := '0';
signal vmmEventDone_i_125 : std_logic := '0';
signal vmmEventDone_s_125 : std_logic := '0';
signal trigger_pulse_stage1 : std_logic := '0';
signal trigger_pulse_ff_sync: std_logic := '0';
signal hitsLen_cnt : integer := 0;
signal hitsLenMax : integer := 150; --Real maximum is 1119 for a jumbo UDP frame and 184 for a normal UDP frame
-- readoutProc
signal vmm_data_buf_i : std_logic_vector( 37 downto 0 ) := ( others => '0' );
signal state_dt : std_logic_vector(3 downto 0) := "0000";
signal dt_cntr_intg0 : integer := 0;
signal dt_cntr_intg1 : integer := 0;
signal dataBitRead : integer := 0;
signal vmmWordReady_i : std_logic := '0';
signal vmmWord_i : std_logic_vector(63 downto 0);
signal vmm_data1 : std_logic := '0';
signal vmm_data0 : std_logic := '0';
signal vmm_data0_stage1 : std_logic := '0';
signal vmm_data0_ff_sync : std_logic := '0';
signal vmm_data1_stage1 : std_logic := '0';
signal vmm_data1_ff_sync : std_logic := '0';
signal vmm_cktk : std_logic := '0'; -- Strobe to VMM CKTK
signal vmm_ckdt_i : std_logic := '0';
-- driverInterface and readout buffer
signal wr_rst_busy : std_logic := '0';
signal rd_rst_busy : std_logic := '0';
signal rst_buff : std_logic := '0';
signal wr_en : std_logic := '0';
signal fifo_empty : std_logic := '0';
signal fifo_full : std_logic := '0';
signal dbg_intf_state : std_logic_vector(2 downto 0) := (others => '0');
type stateType is (ST_IDLE, ST_WAIT_FOR_DATA, ST_WAIT_FOR_DONE, ST_WAIT_FOR_READ, ST_DONE);
signal state_intf : stateType := ST_IDLE;
-- ASYNC_REG attributes
attribute ASYNC_REG : string;
attribute ASYNC_REG of vmmEventDone_i_125 : signal is "TRUE";
attribute ASYNC_REG of vmmEventDone_s_125 : signal is "TRUE";
attribute ASYNC_REG of daq_enable_stage1 : signal is "TRUE";
attribute ASYNC_REG of daq_enable_ff_sync : signal is "TRUE";
attribute ASYNC_REG of daq_enable_stage1_Dt : signal is "TRUE";
attribute ASYNC_REG of daq_enable_ff_sync_Dt : signal is "TRUE";
attribute ASYNC_REG of trigger_pulse_stage1 : signal is "TRUE";
attribute ASYNC_REG of trigger_pulse_ff_sync : signal is "TRUE";
attribute ASYNC_REG of cktk_max_i : signal is "TRUE";
attribute ASYNC_REG of cktk_max_sync : signal is "TRUE";
attribute ASYNC_REG of reading_out_word_stage1 : signal is "TRUE";
attribute ASYNC_REG of reading_out_word_ff_sync : signal is "TRUE";
attribute ASYNC_REG of reading_out_word_i_125 : signal is "TRUE";
attribute ASYNC_REG of reading_out_word_s_125 : signal is "TRUE";
attribute ASYNC_REG of vmm_data0_stage1 : signal is "TRUE";
attribute ASYNC_REG of vmm_data0_ff_sync : signal is "TRUE";
attribute ASYNC_REG of vmm_data1_stage1 : signal is "TRUE";
attribute ASYNC_REG of vmm_data1_ff_sync : signal is "TRUE";
attribute ASYNC_REG of cktkSent_stage1 : signal is "TRUE";
attribute ASYNC_REG of cktkSent_ff_sync : signal is "TRUE";
-- Debugging
signal probe0_out : std_logic_vector(127 downto 0);
-------------------------------------------------------------------
-- Keep signals for ILA
-----------------------------------------------------------------
attribute mark_debug : string;
-- attribute mark_debug of state_tk : signal is "true";
-- attribute mark_debug of NoFlg_counter : signal is "true";
-- attribute mark_debug of reading_out_word : signal is "true";
-- attribute mark_debug of cktkSent_ff_sync : signal is "true";
-- attribute mark_debug of vmm_ckdt_i : signal is "true";
-- attribute mark_debug of vmm_cktk_i : signal is "true";
-- attribute mark_debug of vmm_data0_ff_sync : signal is "true";
-- attribute mark_debug of vmm_data1_ff_sync : signal is "true";
-- attribute mark_debug of dataBitRead : signal is "true";
-- attribute mark_debug of state_dt : signal is "true";
-- attribute mark_debug of vmmEventDone_i : signal is "true";
-- attribute mark_debug of hitsLen_cnt : signal is "true";
-- attribute mark_debug of vmmWordReady_i : signal is "true";
-- attribute mark_debug of vmmWord_i : signal is "true";
-- attribute mark_debug of trigger_pulse : signal is "true";
-- attribute mark_debug of reading_out_word_ff_sync : signal is "true";
-- attribute mark_debug of timeoutCnt : signal is "true";
-- attribute mark_debug of fifo_empty : signal is "true";
-- attribute mark_debug of dbg_intf_state : signal is "true";
-- attribute mark_debug of rd_en : signal is "true";
-- attribute mark_debug of wr_en : signal is "true";
-- attribute mark_debug of vmm_data0 : signal is "true";
component vmmSignalsDemux
port(
selVMM : in std_logic_vector(2 downto 0);
vmm_data0_vec : in std_logic_vector(8 downto 1);
vmm_data1_vec : in std_logic_vector(8 downto 1);
vmm_data0 : out std_logic;
vmm_data1 : out std_logic;
vmm_cktk : in std_logic;
vmm_ckdt_enable : out std_logic_vector(8 downto 1);
vmm_cktk_vec : out std_logic_vector(8 downto 1)
);
end component;
component ila_readout
port(
clk : in std_logic;
probe0 : in std_logic_vector(127 downto 0)
);
end component;
component cont_buffer
port(
rst : in std_logic;
wr_clk : in std_logic;
rd_clk : in std_logic;
din : in std_logic_vector(63 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(15 downto 0);
full : out std_logic;
empty : out std_logic;
wr_rst_busy : out std_logic;
rd_rst_busy : out std_logic
);
end component;
begin
-- by using this clock the CKTK strobe has f=20MHz (T=50ns, D=50%)
tokenProc: process(clkTkProc)
begin
if (rising_edge(clkTkProc)) then
if (daq_enable_ff_sync = '1') then
case state_tk is
when x"1" =>
vmmEventDone_i <= '0';
if (trigger_pulse_ff_sync = '1') then
state_tk <= x"2";
end if;
when x"2" =>
if (reading_out_word_ff_sync = '0') then -- If we are not reading issue a CKTK
vmm_cktk_i <= '1';
cktkSent <= '1';
hitsLen_cnt <= hitsLen_cnt + 1;
state_tk <= x"3";
else
NoFlg_counter <= ( others => '0' );
state_tk <= x"5";
end if;
when x"3" =>
vmm_cktk_i <= '0';
timeoutCnt <= b"0000";
state_tk <= x"4";
when x"4" =>
if (NoFlg_counter = unsigned(cktk_max_sync)) then
cktkSent <= '0'; -- cktkSent intentionally stays high for x1.5 of ckdt proc clock + VMM delay + datapath delay
state_tk <= x"6"; -- If NoFlg_counter = 7 : time to transmit data
elsif (timeoutCnt = timeout) then -- No data (wait for reading_out_word signal to pass through the synchronizer)
cktkSent <= '0'; -- cktkSent intentionally stays high for x1.5 of ckdt proc clock + VMM delay + datapath delay
NoFlg_counter <= NoFlg_counter + 1;
state_tk <= x"2";
elsif (reading_out_word_ff_sync = '1') then -- Data proc started clocking out VMM data. Wait...
cktkSent <= '0'; -- cktkSent intentionally stays high for x1.5 of ckdt proc clock + VMM delay + datapath delay
NoFlg_counter <= ( others => '0' );
state_tk <= x"5";
else
timeoutCnt <= timeoutCnt + 1;
end if;
when x"5" => -- Wait until word readout is done
if (reading_out_word_ff_sync = '0') then
if hitsLen_cnt >= hitsLenMax then -- Maximum UDP packet length reached
state_tk <= x"6";
else
state_tk <= x"2"; -- Issue new CKTK strobe
end if;
end if;
when x"6" => -- Start the soft reset sequence, there is still a chance
if (reading_out_word_ff_sync = '0') then -- of getting data at this point so check that before soft reset
NoFlg_counter <= ( others => '0' );
state_tk <= x"7";
else
NoFlg_counter <= ( others => '0' );
state_tk <= x"5";
end if;
when x"7" =>
hitsLen_cnt <= 0;
vmmEventDone_i <= '1';
state_tk <= x"1";
when others =>
hitsLen_cnt <= 0;
NoFlg_counter <= ( others => '0' );
state_tk <= x"1";
end case;
else
state_tk <= x"1";
vmm_ena_i <= '0';
vmm_cktk_i <= '0';
timeoutCnt <= b"0000";
hitsLen_cnt <= 0;
NoFlg_counter <= ( others => '0' );
cktkSent <= '0';
vmm_wen_i <= '0';
end if;
end if;
end process;
-- by using this clock the CKDT strobe has f=25MHz (T=40ns, D=50%, phase=0deg) to clock in data0 and data1
readoutProc: process(clkDtProc)
begin
if rising_edge(clkDtProc) then
if (daq_enable_ff_sync_Dt = '1') then
case state_dt is
when x"0" =>
reading_out_word <= '0';
vmm_data_buf <= (others => '0');
dt_cntr_intg0 <= 0;
dt_cntr_intg1 <= 1;
wr_en <= '0';
vmm_ckdt_i <= '0';
if (cktkSent_ff_sync = '1' and vmm_data0_ff_sync = '1') then
state_dt <= x"1";
end if;
when x"1" =>
reading_out_word<= '1';
vmm_ckdt_i <= '1';
state_dt <= x"a";
when x"a" =>
vmm_ckdt_i <= '0';
state_dt <= x"b";
when x"b" =>
if (dataBitRead < 19) then
vmm_ckdt_i <= '1';
end if;
state_dt <= x"2";
when x"2" => -- 19 ckdt and collect data
vmm_ckdt_i <= '0';
if (dataBitRead /= 19) then
vmm_data_buf(dt_cntr_intg0) <= vmm_data0_ff_sync;
vmm_data_buf(dt_cntr_intg1) <= vmm_data1_ff_sync;
vmm_data_buf_i <= vmm_data_buf;
state_dt <= x"b";
dataBitRead <= dataBitRead + 1;
else
vmm_data_buf(dt_cntr_intg0) <= vmm_data0_ff_sync;
vmm_data_buf(dt_cntr_intg1) <= vmm_data1_ff_sync;
vmm_data_buf_i <= vmm_data_buf;
dataBitRead <= 1;
state_dt <= x"3";
end if;
dt_cntr_intg0 <= dt_cntr_intg0 + 2;
dt_cntr_intg1 <= dt_cntr_intg1 + 2;
when x"3" =>
wr_en <= '0';
state_dt <= x"4";
when x"4" =>
wr_en <= '1';
state_dt <= x"5";
when x"5" =>
wr_en <= '0';
state_dt <= x"6";
when x"6" =>
dt_cntr_intg0 <= 0;
dt_cntr_intg1 <= 1;
state_dt <= x"0";
when others =>
dt_cntr_intg0 <= 0;
dt_cntr_intg1 <= 1;
state_dt <= x"0";
end case;
else
dt_cntr_intg0 <= 0;
dt_cntr_intg1 <= 1;
wr_en <= '0';
reading_out_word <= '0';
vmm_ckdt_i <= '0';
state_dt <= x"0";
end if;
end if;
end process;
-- FSM that interfaces with driver
driverInterface: process(clk)
begin
if(rising_edge(clk))then
if(daq_enable = '0')then
state_intf <= ST_IDLE;
vmmWordReady <= '0';
vmmEventDone <= '0';
else
case state_intf is
when ST_IDLE =>
dbg_intf_state <= "000";
vmmWordReady <= '0';
vmmEventDone <= '0';
if(trigger_pulse = '1')then
state_intf <= ST_WAIT_FOR_DATA;
else
state_intf <= ST_IDLE;
end if;
when ST_WAIT_FOR_DATA =>
dbg_intf_state <= "001";
vmmWordReady <= '0';
vmmEventDone <= '0';
if(reading_out_word_s_125 = '1')then -- data detected, wait all to be read out
state_intf <= ST_WAIT_FOR_DONE;
elsif(vmmEventDone_s_125 = '1')then -- no data in the first place
state_intf <= ST_DONE;
else
state_intf <= ST_WAIT_FOR_DATA;
end if;
when ST_WAIT_FOR_DONE =>
dbg_intf_state <= "010";
vmmWordReady <= '0';
vmmEventDone <= '0';
if(vmmEventDone_s_125 = '1')then -- all have been read out
state_intf <= ST_WAIT_FOR_READ;
else
state_intf <= ST_WAIT_FOR_DONE;
end if;
when ST_WAIT_FOR_READ =>
dbg_intf_state <= "011";
vmmWordReady <= '1';
vmmEventDone <= '0';
if(fifo_empty = '1')then -- fifo emptied, go to IDLE
state_intf <= ST_DONE;
else
state_intf <= ST_WAIT_FOR_READ;
end if;
when ST_DONE =>
dbg_intf_state <= "100";
vmmWordReady <= '0';
vmmEventDone <= '1';
if(vmmEventDone_s_125 = '0' and trigger_pulse = '1')then
state_intf <= ST_WAIT_FOR_DATA;
else
state_intf <= ST_DONE;
end if;
end case;
end if;
end if;
end process;
driverInterfaceSynchronizer: process(clk) -- 125
begin
if(rising_edge(clk))then
reading_out_word_i_125 <= reading_out_word;
reading_out_word_s_125 <= reading_out_word_i_125;
vmmEventDone_i_125 <= vmmEventDone_i;
vmmEventDone_s_125 <= vmmEventDone_i_125;
end if;
end process;
tokenProcSynchronizer: process(clkTkProc) --40
begin
if rising_edge (clkTkProc) then
daq_enable_stage1 <= daq_enable;
daq_enable_ff_sync <= daq_enable_stage1;
trigger_pulse_stage1 <= trigger_pulse;
trigger_pulse_ff_sync <= trigger_pulse_stage1;
reading_out_word_stage1 <= reading_out_word;
reading_out_word_ff_sync <= reading_out_word_stage1;
cktk_max_i <= cktk_max;
cktk_max_sync <= cktk_max_i;
end if;
end process;
readoutProcSynchronizer: process(clkDtProc) --50
begin
if rising_edge(clkDtProc) then
daq_enable_stage1_Dt <= daq_enable;
daq_enable_ff_sync_Dt <= daq_enable_stage1_Dt;
cktkSent_stage1 <= cktkSent;
cktkSent_ff_sync <= cktkSent_stage1;
vmm_data0_stage1 <= vmm_data0;
vmm_data0_ff_sync <= vmm_data0_stage1;
vmm_data1_stage1 <= vmm_data1;
vmm_data1_ff_sync <= vmm_data1_stage1;
end if;
end process;
cont_buffer_inst: cont_buffer
PORT MAP (
rst => rst_buff,
wr_clk => clkDtProc,
rd_clk => clk,
din => vmmWord_i,
wr_en => wr_en,
rd_en => rd_en,
dout => vmmWord,
full => fifo_full,
empty => fifo_empty,
wr_rst_busy => wr_rst_busy,
rd_rst_busy => rd_rst_busy
);
vmm_cktk <= vmm_cktk_i;
vmm_ckdt <= vmm_ckdt_i;
dt_state_o <= state_tk;
dt_cntr_st_o <= state_dt;
rst_buff <= not daq_enable;
vmmWord_i <= b"00" & vmm_data_buf(25 downto 18) & vmm_data_buf(37 downto 26) & vmm_data_buf(17 downto 8) & b"000000000000000000000000" & vmm_data_buf(7 downto 2) & vmm_data_buf(1) & vmm_data_buf(0);
-- TDO & Gray & PDO & & Address & Threshold & Flag;
VMMdemux: vmmSignalsDemux
port map(
selVMM => vmmId,
vmm_data0_vec => vmm_data0_vec,
vmm_data1_vec => vmm_data1_vec,
vmm_data0 => vmm_data0,
vmm_data1 => vmm_data1,
vmm_cktk => vmm_cktk,
vmm_ckdt_enable => vmm_ckdt_enable,
vmm_cktk_vec => vmm_cktk_vec
);
--ilaDAQ: ila_readout
--port map
-- (
-- clk => clk,
-- probe0 => probe0_out
-- );
-- probe0_out(0) <= vmm_cktk_i; -- OK
-- probe0_out(4 downto 1) <= state_tk; -- OK
-- probe0_out(5) <= vmm_data0;
-- probe0_out(7 downto 6) <= (others => '0');
-- probe0_out(10 downto 8) <= (others => '0'); -- OK
-- probe0_out(14 downto 11) <= state_dt; -- OK
-- probe0_out(15) <= daq_enable_ff_sync; -- OK
-- probe0_out(16) <= reading_out_word; -- OK
-- probe0_out(17) <= cktkSent_ff_sync; -- OK
-- probe0_out(18) <= vmm_ckdt_i; -- OK
-- probe0_out(19) <= vmm_data0_ff_sync; -- OK
-- probe0_out(20) <= vmm_data1_ff_sync; -- OK
-- probe0_out(25 downto 21) <= std_logic_vector(to_unsigned(dataBitRead, probe0_out(28 downto 24)'length)); -- OK
-- probe0_out(26) <= vmmWordReady_i; -- OK
-- probe0_out(90 downto 27) <= vmmWord_i; -- OK
-- probe0_out(91) <= trigger_pulse; -- OK
-- probe0_out(92) <= reading_out_word_ff_sync;
-- probe0_out(96 downto 93) <= std_logic_vector(timeoutCnt);
-- probe0_out(97) <= fifo_empty;
-- probe0_out(98) <= rd_en;
-- probe0_out(99) <= wr_en;
-- probe0_out(102 downto 100) <= dbg_intf_state;
-- probe0_out(127 downto 103) <= (others => '0');
end Behavioral; | gpl-3.0 | 3066f8c7dc508aa5e2b9ee9b4abb5a8b | 0.434576 | 4.100328 | false | false | false | false |
HackLinux/ION | src/rtl/buses/ion_tcm_code.vhdl | 1 | 3,800 | --------------------------------------------------------------------------------
-- ion_tcm_code.vhdl -- Tightly Coupled Memory.
--------------------------------------------------------------------------------
-- Tightly Coupled Memory for code space.
-- This block is meant to contain code so it has no byte enables -- see comments
-- for module ION_TCM_CODE for an explanation about why this is a good thing.
--
-- TODO is mips16 is ever implemented, some byte enables might be needed.
--
-- REFERENCES
-- [1] ion_design_notes.pdf -- ION project design notes.
--------------------------------------------------------------------------------
--
--
--------------------------------------------------------------------------------
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.ION_INTERFACES_PKG.all;
use work.ION_INTERNAL_PKG.all;
entity ION_TCM_CODE is
generic(
-- Size of TCM block in 32-bit words. Set to zero to disable TCM.
SIZE : integer := 4096;
-- Initial contents of TCM. Default is zeros.
INIT_DATA : t_obj_code := zero_objcode(16)
);
port(
CLK_I : in std_logic;
RESET_I : in std_logic;
EN_I : in std_logic;
MEM_MOSI_I : in t_cpumem_mosi;
MEM_MISO_O : out t_cpumem_miso
);
end;
architecture rtl of ION_TCM_CODE is
constant TCM_ADDR_SIZE : integer := log2(SIZE);
subtype t_tcm_address is std_logic_vector(TCM_ADDR_SIZE+2-1 downto 2);
signal tcm_addr : t_tcm_address;
signal tcm_rd_data : t_word;
-- TCM memory block, initialized with constant data table.
signal tcm_ram : t_word_table(0 to ((SIZE)-1)) :=
objcode_to_wtable(INIT_DATA, SIZE*4);
begin
tcm_addr <= MEM_MOSI_I.addr(tcm_addr'high downto 2);
--------------------------------------------------------------------------------
---- Memory block inference.
tcm_memory_block:
process(CLK_I)
begin
if (CLK_I'event and CLK_I='1') then
tcm_rd_data <= tcm_ram(conv_integer(tcm_addr));
if MEM_MOSI_I.wr_be/="0000" and EN_I='1' then
tcm_ram(conv_integer(unsigned(tcm_addr))) <= MEM_MOSI_I.wr_data;
end if;
end if;
end process tcm_memory_block;
MEM_MISO_O.rd_data <= tcm_rd_data;
MEM_MISO_O.mwait <= '0';
end architecture rtl;
| lgpl-3.0 | 6fbb1b3d0af3b6c596dcd6e3ad30b673 | 0.516579 | 4.37788 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/FIR_Filter/fir_tap.vhd | 1 | 3,328 | --------------------------------------------------------------------------------------------------
-- FIR Tap
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- PACKAGE
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.dsp_pkg.all;
package fir_tap_pkg is
--FIR tap component declaration
component fir_tap is
port( clk : in std_logic;
rst : in std_logic;
coef : in coefficient;
sig_in : in sig;
sig_out : out sig;
sum_in : in fir_sig;
sum_out : out fir_sig);
end component;
end package;
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dsp_pkg.all;
--This entity represents a single tap in a FIR filter. The taps are designed to implement a
--cascade adder allowing for chaining an indefinite (tho definitely finite) number of taps.
entity fir_tap is
port( clk : in std_logic;
rst : in std_logic;
coef : in coefficient;
sig_in : in sig;
sig_out : out sig;
sum_in : in fir_sig;
sum_out : out fir_sig);
end fir_tap;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE (behavioral)
--------------------------------------------------------------------------------------------------
architecture behave of fir_tap is
signal sig_delay : sig_array(1 to 2) := (others => (others => '0'));
signal product : fir_sig := (others => '0');
begin
--delay the input signal
delay_sig : process(clk)
begin
if(rising_edge(clk)) then
if(rst = '1') then
sig_delay <= (others => (others => '0'));
else
sig_delay(1) <= sig_in;
sig_delay(2) <= sig_delay(1);
end if;
end if;
end process;
sig_out <= sig_delay(2);
--multiply the signal to the tap coefficient
multiply : process(clk)
begin
if(rising_edge(clk)) then
if(rst = '1') then
product <= (others => '0');
else
product <= resize(sig_delay(2) * coef, NUM_FIR_BITS);
end if;
end if;
end process;
--update the sum
update_sum : process(clk)
begin
if(rising_edge(clk)) then
if(rst = '1') then
sum_out <= (others => '0');
else
sum_out <= sum_in + product;
end if;
end if;
end process;
end behave;
| mit | 194036cd4d01e9657f6188ae9889d2fa | 0.363582 | 5.004511 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/configuration/select_vmm.vhd | 1 | 5,459 | ----------------------------------------------------------------------------------
-- Company: NTU ATHNENS - BNL
-- Engineer: Panagiotis Gkountoumis
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Panagiotis Gkountoumis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 18.04.2016 13:00:21
-- Design Name:
-- Module Name: config_logic - Behavioral
-- Project Name: MMFE8
-- Target Devices: Arix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2016.2
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity select_vmm is
Port (
clk_in : in std_logic;
vmm_id : in std_logic_vector(15 downto 0);
conf_di : in std_logic;
conf_di_vec : out std_logic_vector(8 downto 1);
conf_do : out std_logic;
conf_do_vec : in std_logic_vector(8 downto 1);
cktk_out : in std_logic;
cktk_out_vec : out std_logic_vector(8 downto 1);
conf_wen : in std_logic;
conf_wen_vec : out std_logic_vector(8 downto 1);
conf_ena : in std_logic;
conf_ena_vec : out std_logic_vector(8 downto 1)
);
end select_vmm;
architecture Behavioral of select_vmm is
begin
fill_fifo : process(clk_in, vmm_id)
begin
if rising_edge(clk_in) then
if vmm_id = x"0001" then
conf_wen_vec(1) <= conf_wen;
cktk_out_vec(1) <= cktk_out;
conf_ena_vec(1) <= conf_ena;
conf_do <= conf_do_vec(1);
conf_di_vec(1) <= conf_di;
elsif vmm_id = x"0002" then
conf_wen_vec(2) <= conf_wen;
cktk_out_vec(2) <= cktk_out;
conf_ena_vec(2) <= conf_ena;
conf_do <= conf_do_vec(2);
conf_di_vec(2) <= conf_di;
elsif vmm_id = x"0003" then
conf_wen_vec(3) <= conf_wen;
cktk_out_vec(3) <= cktk_out;
conf_ena_vec(3) <= conf_ena;
conf_do <= conf_do_vec(3);
conf_di_vec(3) <= conf_di;
elsif vmm_id = x"0004" then
conf_wen_vec(4) <= conf_wen;
cktk_out_vec(4) <= cktk_out;
conf_ena_vec(4) <= conf_ena;
conf_do <= conf_do_vec(4);
conf_di_vec(4) <= conf_di;
elsif vmm_id = x"0005" then
conf_wen_vec(5) <= conf_wen;
cktk_out_vec(5) <= cktk_out;
conf_ena_vec(5) <= conf_ena;
conf_do <= conf_do_vec(5);
conf_di_vec(5) <= conf_di;
elsif vmm_id = x"0006" then
conf_wen_vec(6) <= conf_wen;
cktk_out_vec(6) <= cktk_out;
conf_ena_vec(6) <= conf_ena;
conf_do <= conf_do_vec(6);
conf_di_vec(6) <= conf_di;
elsif vmm_id = x"0007" then
conf_wen_vec(7) <= conf_wen;
cktk_out_vec(7) <= cktk_out;
conf_ena_vec(7) <= conf_ena;
conf_do <= conf_do_vec(7);
conf_di_vec(7) <= conf_di;
elsif vmm_id = x"0008" then
conf_wen_vec(8) <= conf_wen;
cktk_out_vec(8) <= cktk_out;
conf_ena_vec(8) <= conf_ena;
conf_do <= conf_do_vec(8);
conf_di_vec(8) <= conf_di;
else
conf_wen_vec <= (others => '0');
cktk_out_vec <= (others => '0');
conf_ena_vec <= (others => '0');
conf_di_vec <= (others => '0');
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 4463be36c5318690af9c293795ce87c7 | 0.459791 | 3.833567 | false | false | false | false |
EltonBroering/Estacionamento-Inteligente-com-portas-logicas | sensordeled.vhd | 1 | 17,911 | -- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- PROGRAM "Quartus II 32-bit"
-- VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version"
-- CREATED "Thu May 22 09:36:15 2014"
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY sensordeled IS
PORT
(
Vaga1 : IN STD_LOGIC;
Vaga2 : IN STD_LOGIC;
Vaga3 : IN STD_LOGIC;
Vaga4 : IN STD_LOGIC;
Vaga5 : IN STD_LOGIC;
Vaga6 : IN STD_LOGIC;
Vaga7 : IN STD_LOGIC;
Vaga8 : IN STD_LOGIC;
Vaga9 : IN STD_LOGIC;
Vaga11 : IN STD_LOGIC;
Vaga10 : IN STD_LOGIC;
Vaga12 : IN STD_LOGIC;
Vaga13 : IN STD_LOGIC;
Vaga14 : IN STD_LOGIC;
Vaga15 : IN STD_LOGIC;
Vaga16 : IN STD_LOGIC;
Led_Vaga2 : OUT STD_LOGIC;
Led_Vaga3 : OUT STD_LOGIC;
Led_Vaga4 : OUT STD_LOGIC;
Led_Vaga5 : OUT STD_LOGIC;
Led_Vaga6 : OUT STD_LOGIC;
Led_Vaga7 : OUT STD_LOGIC;
Led_Vaga_Deficiente : OUT STD_LOGIC;
Led_Vaga8 : OUT STD_LOGIC;
Led_Vaga9 : OUT STD_LOGIC;
Led_Vaga10 : OUT STD_LOGIC;
Led_Vaga11 : OUT STD_LOGIC;
Led_Vaga12 : OUT STD_LOGIC;
Led_Vaga13 : OUT STD_LOGIC;
Led_Vaga14 : OUT STD_LOGIC;
Led_Vaga15 : OUT STD_LOGIC;
pin_name1 : OUT STD_LOGIC;
pin_name2 : OUT STD_LOGIC;
pin_name3 : OUT STD_LOGIC;
pin_name4 : OUT STD_LOGIC;
Led_Vaga1 : OUT STD_LOGIC
);
END sensordeled;
ARCHITECTURE bdf_type OF sensordeled IS
ATTRIBUTE black_box : BOOLEAN;
ATTRIBUTE noopt : BOOLEAN;
COMPONENT \74283_0\
PORT(CIN : IN STD_LOGIC;
A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
SUM4 : OUT STD_LOGIC;
SUM1 : OUT STD_LOGIC;
SUM2 : OUT STD_LOGIC;
SUM3 : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74283_0\: COMPONENT IS true;
ATTRIBUTE noopt OF \74283_0\: COMPONENT IS true;
COMPONENT \74283_1\
PORT(CIN : IN STD_LOGIC;
A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
SUM4 : OUT STD_LOGIC;
SUM1 : OUT STD_LOGIC;
SUM2 : OUT STD_LOGIC;
SUM3 : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74283_1\: COMPONENT IS true;
ATTRIBUTE noopt OF \74283_1\: COMPONENT IS true;
COMPONENT \74283_10\
PORT(CIN : IN STD_LOGIC;
A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
SUM4 : OUT STD_LOGIC;
SUM1 : OUT STD_LOGIC;
SUM2 : OUT STD_LOGIC;
SUM3 : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74283_10\: COMPONENT IS true;
ATTRIBUTE noopt OF \74283_10\: COMPONENT IS true;
COMPONENT \74283_11\
PORT(CIN : IN STD_LOGIC;
A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
SUM4 : OUT STD_LOGIC;
SUM1 : OUT STD_LOGIC;
SUM2 : OUT STD_LOGIC;
SUM3 : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74283_11\: COMPONENT IS true;
ATTRIBUTE noopt OF \74283_11\: COMPONENT IS true;
COMPONENT \74283_12\
PORT(CIN : IN STD_LOGIC;
A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
SUM4 : OUT STD_LOGIC;
SUM1 : OUT STD_LOGIC;
SUM2 : OUT STD_LOGIC;
SUM3 : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74283_12\: COMPONENT IS true;
ATTRIBUTE noopt OF \74283_12\: COMPONENT IS true;
COMPONENT \74283_13\
PORT(CIN : IN STD_LOGIC;
A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
SUM4 : OUT STD_LOGIC;
SUM1 : OUT STD_LOGIC;
SUM2 : OUT STD_LOGIC;
SUM3 : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74283_13\: COMPONENT IS true;
ATTRIBUTE noopt OF \74283_13\: COMPONENT IS true;
COMPONENT \74283_2\
PORT(CIN : IN STD_LOGIC;
A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
SUM4 : OUT STD_LOGIC;
SUM1 : OUT STD_LOGIC;
SUM2 : OUT STD_LOGIC;
SUM3 : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74283_2\: COMPONENT IS true;
ATTRIBUTE noopt OF \74283_2\: COMPONENT IS true;
COMPONENT \74283_3\
PORT(CIN : IN STD_LOGIC;
A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
SUM4 : OUT STD_LOGIC;
SUM1 : OUT STD_LOGIC;
SUM2 : OUT STD_LOGIC;
SUM3 : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74283_3\: COMPONENT IS true;
ATTRIBUTE noopt OF \74283_3\: COMPONENT IS true;
COMPONENT \74283_4\
PORT(CIN : IN STD_LOGIC;
A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
SUM4 : OUT STD_LOGIC;
SUM1 : OUT STD_LOGIC;
SUM2 : OUT STD_LOGIC;
SUM3 : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74283_4\: COMPONENT IS true;
ATTRIBUTE noopt OF \74283_4\: COMPONENT IS true;
COMPONENT \74283_5\
PORT(CIN : IN STD_LOGIC;
A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
SUM4 : OUT STD_LOGIC;
SUM1 : OUT STD_LOGIC;
SUM2 : OUT STD_LOGIC;
SUM3 : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74283_5\: COMPONENT IS true;
ATTRIBUTE noopt OF \74283_5\: COMPONENT IS true;
COMPONENT \74283_6\
PORT(CIN : IN STD_LOGIC;
A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
SUM4 : OUT STD_LOGIC;
SUM1 : OUT STD_LOGIC;
SUM2 : OUT STD_LOGIC;
SUM3 : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74283_6\: COMPONENT IS true;
ATTRIBUTE noopt OF \74283_6\: COMPONENT IS true;
COMPONENT \74283_7\
PORT(CIN : IN STD_LOGIC;
A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
SUM4 : OUT STD_LOGIC;
SUM1 : OUT STD_LOGIC;
SUM2 : OUT STD_LOGIC;
SUM3 : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74283_7\: COMPONENT IS true;
ATTRIBUTE noopt OF \74283_7\: COMPONENT IS true;
COMPONENT \74283_8\
PORT(CIN : IN STD_LOGIC;
A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
SUM4 : OUT STD_LOGIC;
SUM1 : OUT STD_LOGIC;
SUM2 : OUT STD_LOGIC;
SUM3 : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74283_8\: COMPONENT IS true;
ATTRIBUTE noopt OF \74283_8\: COMPONENT IS true;
COMPONENT \74283_9\
PORT(CIN : IN STD_LOGIC;
A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
SUM4 : OUT STD_LOGIC;
SUM1 : OUT STD_LOGIC;
SUM2 : OUT STD_LOGIC;
SUM3 : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74283_9\: COMPONENT IS true;
ATTRIBUTE noopt OF \74283_9\: COMPONENT IS true;
SIGNAL SYNTHESIZED_WIRE_118 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_7 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_9 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_10 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_12 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_13 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_119 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_17 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_18 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_20 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_21 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_25 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_26 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_28 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_29 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_120 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_33 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_34 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_36 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_37 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_41 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_42 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_44 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_45 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_121 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_49 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_50 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_52 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_53 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_56 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_58 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_59 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_61 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_62 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_122 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_66 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_67 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_69 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_70 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_74 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_75 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_77 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_78 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_123 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_82 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_83 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_85 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_86 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_90 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_91 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_93 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_94 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_124 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_98 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_99 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_101 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_102 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_106 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_107 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_109 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_110 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_113 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_114 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_115 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_116 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_117 : STD_LOGIC;
BEGIN
Led_Vaga2 <= Vaga2;
Led_Vaga3 <= Vaga3;
Led_Vaga4 <= Vaga4;
Led_Vaga5 <= Vaga5;
Led_Vaga6 <= Vaga6;
Led_Vaga7 <= Vaga7;
Led_Vaga_Deficiente <= Vaga16;
Led_Vaga8 <= Vaga8;
Led_Vaga9 <= Vaga9;
Led_Vaga10 <= Vaga10;
Led_Vaga11 <= Vaga11;
Led_Vaga12 <= Vaga12;
Led_Vaga13 <= Vaga13;
Led_Vaga14 <= Vaga14;
Led_Vaga15 <= Vaga15;
Led_Vaga1 <= Vaga1;
SYNTHESIZED_WIRE_7 <= '1';
SYNTHESIZED_WIRE_56 <= '1';
SYNTHESIZED_WIRE_113 <= '1';
SYNTHESIZED_WIRE_114 <= '1';
SYNTHESIZED_WIRE_115 <= '1';
SYNTHESIZED_WIRE_116 <= '1';
SYNTHESIZED_WIRE_117 <= '1';
b2v_inst : 74283_0
PORT MAP(CIN => SYNTHESIZED_WIRE_118,
A1 => Vaga1,
A2 => SYNTHESIZED_WIRE_118,
B2 => SYNTHESIZED_WIRE_118,
A3 => SYNTHESIZED_WIRE_118,
A4 => SYNTHESIZED_WIRE_118,
B4 => SYNTHESIZED_WIRE_118,
B1 => Vaga2,
B3 => SYNTHESIZED_WIRE_118,
SUM4 => SYNTHESIZED_WIRE_13,
SUM1 => SYNTHESIZED_WIRE_9,
SUM2 => SYNTHESIZED_WIRE_10,
SUM3 => SYNTHESIZED_WIRE_12);
SYNTHESIZED_WIRE_118 <= NOT(SYNTHESIZED_WIRE_7);
b2v_inst14 : 74283_1
PORT MAP(CIN => SYNTHESIZED_WIRE_118,
A1 => SYNTHESIZED_WIRE_9,
A2 => SYNTHESIZED_WIRE_10,
B2 => SYNTHESIZED_WIRE_118,
A3 => SYNTHESIZED_WIRE_12,
A4 => SYNTHESIZED_WIRE_13,
B4 => SYNTHESIZED_WIRE_118,
B1 => Vaga3,
B3 => SYNTHESIZED_WIRE_118,
SUM4 => SYNTHESIZED_WIRE_21,
SUM1 => SYNTHESIZED_WIRE_17,
SUM2 => SYNTHESIZED_WIRE_18,
SUM3 => SYNTHESIZED_WIRE_20);
b2v_inst15 : 74283_2
PORT MAP(CIN => SYNTHESIZED_WIRE_119,
A1 => SYNTHESIZED_WIRE_17,
A2 => SYNTHESIZED_WIRE_18,
B2 => SYNTHESIZED_WIRE_119,
A3 => SYNTHESIZED_WIRE_20,
A4 => SYNTHESIZED_WIRE_21,
B4 => SYNTHESIZED_WIRE_119,
B1 => Vaga4,
B3 => SYNTHESIZED_WIRE_119,
SUM4 => SYNTHESIZED_WIRE_29,
SUM1 => SYNTHESIZED_WIRE_25,
SUM2 => SYNTHESIZED_WIRE_26,
SUM3 => SYNTHESIZED_WIRE_28);
b2v_inst16 : 74283_3
PORT MAP(CIN => SYNTHESIZED_WIRE_119,
A1 => SYNTHESIZED_WIRE_25,
A2 => SYNTHESIZED_WIRE_26,
B2 => SYNTHESIZED_WIRE_119,
A3 => SYNTHESIZED_WIRE_28,
A4 => SYNTHESIZED_WIRE_29,
B4 => SYNTHESIZED_WIRE_119,
B1 => Vaga5,
B3 => SYNTHESIZED_WIRE_119,
SUM4 => SYNTHESIZED_WIRE_37,
SUM1 => SYNTHESIZED_WIRE_33,
SUM2 => SYNTHESIZED_WIRE_34,
SUM3 => SYNTHESIZED_WIRE_36);
b2v_inst17 : 74283_4
PORT MAP(CIN => SYNTHESIZED_WIRE_120,
A1 => SYNTHESIZED_WIRE_33,
A2 => SYNTHESIZED_WIRE_34,
B2 => SYNTHESIZED_WIRE_120,
A3 => SYNTHESIZED_WIRE_36,
A4 => SYNTHESIZED_WIRE_37,
B4 => SYNTHESIZED_WIRE_120,
B1 => Vaga6,
B3 => SYNTHESIZED_WIRE_120,
SUM4 => SYNTHESIZED_WIRE_45,
SUM1 => SYNTHESIZED_WIRE_41,
SUM2 => SYNTHESIZED_WIRE_42,
SUM3 => SYNTHESIZED_WIRE_44);
b2v_inst18 : 74283_5
PORT MAP(CIN => SYNTHESIZED_WIRE_120,
A1 => SYNTHESIZED_WIRE_41,
A2 => SYNTHESIZED_WIRE_42,
B2 => SYNTHESIZED_WIRE_120,
A3 => SYNTHESIZED_WIRE_44,
A4 => SYNTHESIZED_WIRE_45,
B4 => SYNTHESIZED_WIRE_120,
B1 => Vaga7,
B3 => SYNTHESIZED_WIRE_120,
SUM4 => SYNTHESIZED_WIRE_53,
SUM1 => SYNTHESIZED_WIRE_49,
SUM2 => SYNTHESIZED_WIRE_50,
SUM3 => SYNTHESIZED_WIRE_52);
b2v_inst19 : 74283_6
PORT MAP(CIN => SYNTHESIZED_WIRE_121,
A1 => SYNTHESIZED_WIRE_49,
A2 => SYNTHESIZED_WIRE_50,
B2 => SYNTHESIZED_WIRE_121,
A3 => SYNTHESIZED_WIRE_52,
A4 => SYNTHESIZED_WIRE_53,
B4 => SYNTHESIZED_WIRE_121,
B1 => Vaga8,
B3 => SYNTHESIZED_WIRE_121,
SUM4 => SYNTHESIZED_WIRE_62,
SUM1 => SYNTHESIZED_WIRE_58,
SUM2 => SYNTHESIZED_WIRE_59,
SUM3 => SYNTHESIZED_WIRE_61);
SYNTHESIZED_WIRE_119 <= NOT(SYNTHESIZED_WIRE_56);
b2v_inst20 : 74283_7
PORT MAP(CIN => SYNTHESIZED_WIRE_121,
A1 => SYNTHESIZED_WIRE_58,
A2 => SYNTHESIZED_WIRE_59,
B2 => SYNTHESIZED_WIRE_121,
A3 => SYNTHESIZED_WIRE_61,
A4 => SYNTHESIZED_WIRE_62,
B4 => SYNTHESIZED_WIRE_121,
B1 => Vaga9,
B3 => SYNTHESIZED_WIRE_121,
SUM4 => SYNTHESIZED_WIRE_70,
SUM1 => SYNTHESIZED_WIRE_66,
SUM2 => SYNTHESIZED_WIRE_67,
SUM3 => SYNTHESIZED_WIRE_69);
b2v_inst21 : 74283_8
PORT MAP(CIN => SYNTHESIZED_WIRE_122,
A1 => SYNTHESIZED_WIRE_66,
A2 => SYNTHESIZED_WIRE_67,
B2 => SYNTHESIZED_WIRE_122,
A3 => SYNTHESIZED_WIRE_69,
A4 => SYNTHESIZED_WIRE_70,
B4 => SYNTHESIZED_WIRE_122,
B1 => Vaga10,
B3 => SYNTHESIZED_WIRE_122,
SUM4 => SYNTHESIZED_WIRE_78,
SUM1 => SYNTHESIZED_WIRE_74,
SUM2 => SYNTHESIZED_WIRE_75,
SUM3 => SYNTHESIZED_WIRE_77);
b2v_inst22 : 74283_9
PORT MAP(CIN => SYNTHESIZED_WIRE_122,
A1 => SYNTHESIZED_WIRE_74,
A2 => SYNTHESIZED_WIRE_75,
B2 => SYNTHESIZED_WIRE_122,
A3 => SYNTHESIZED_WIRE_77,
A4 => SYNTHESIZED_WIRE_78,
B4 => SYNTHESIZED_WIRE_122,
B1 => Vaga11,
B3 => SYNTHESIZED_WIRE_122,
SUM4 => SYNTHESIZED_WIRE_86,
SUM1 => SYNTHESIZED_WIRE_82,
SUM2 => SYNTHESIZED_WIRE_83,
SUM3 => SYNTHESIZED_WIRE_85);
b2v_inst23 : 74283_10
PORT MAP(CIN => SYNTHESIZED_WIRE_123,
A1 => SYNTHESIZED_WIRE_82,
A2 => SYNTHESIZED_WIRE_83,
B2 => SYNTHESIZED_WIRE_123,
A3 => SYNTHESIZED_WIRE_85,
A4 => SYNTHESIZED_WIRE_86,
B4 => SYNTHESIZED_WIRE_123,
B1 => Vaga12,
B3 => SYNTHESIZED_WIRE_123,
SUM4 => SYNTHESIZED_WIRE_94,
SUM1 => SYNTHESIZED_WIRE_90,
SUM2 => SYNTHESIZED_WIRE_91,
SUM3 => SYNTHESIZED_WIRE_93);
b2v_inst24 : 74283_11
PORT MAP(CIN => SYNTHESIZED_WIRE_123,
A1 => SYNTHESIZED_WIRE_90,
A2 => SYNTHESIZED_WIRE_91,
B2 => SYNTHESIZED_WIRE_123,
A3 => SYNTHESIZED_WIRE_93,
A4 => SYNTHESIZED_WIRE_94,
B4 => SYNTHESIZED_WIRE_123,
B1 => Vaga13,
B3 => SYNTHESIZED_WIRE_123,
SUM4 => SYNTHESIZED_WIRE_102,
SUM1 => SYNTHESIZED_WIRE_98,
SUM2 => SYNTHESIZED_WIRE_99,
SUM3 => SYNTHESIZED_WIRE_101);
b2v_inst25 : 74283_12
PORT MAP(CIN => SYNTHESIZED_WIRE_124,
A1 => SYNTHESIZED_WIRE_98,
A2 => SYNTHESIZED_WIRE_99,
B2 => SYNTHESIZED_WIRE_124,
A3 => SYNTHESIZED_WIRE_101,
A4 => SYNTHESIZED_WIRE_102,
B4 => SYNTHESIZED_WIRE_124,
B1 => Vaga14,
B3 => SYNTHESIZED_WIRE_124,
SUM4 => SYNTHESIZED_WIRE_110,
SUM1 => SYNTHESIZED_WIRE_106,
SUM2 => SYNTHESIZED_WIRE_107,
SUM3 => SYNTHESIZED_WIRE_109);
b2v_inst26 : 74283_13
PORT MAP(CIN => SYNTHESIZED_WIRE_124,
A1 => SYNTHESIZED_WIRE_106,
A2 => SYNTHESIZED_WIRE_107,
B2 => SYNTHESIZED_WIRE_124,
A3 => SYNTHESIZED_WIRE_109,
A4 => SYNTHESIZED_WIRE_110,
B4 => SYNTHESIZED_WIRE_124,
B1 => Vaga15,
B3 => SYNTHESIZED_WIRE_124,
SUM4 => pin_name4,
SUM1 => pin_name1,
SUM2 => pin_name2,
SUM3 => pin_name3);
SYNTHESIZED_WIRE_120 <= NOT(SYNTHESIZED_WIRE_113);
SYNTHESIZED_WIRE_121 <= NOT(SYNTHESIZED_WIRE_114);
SYNTHESIZED_WIRE_122 <= NOT(SYNTHESIZED_WIRE_115);
SYNTHESIZED_WIRE_123 <= NOT(SYNTHESIZED_WIRE_116);
SYNTHESIZED_WIRE_124 <= NOT(SYNTHESIZED_WIRE_117);
END bdf_type; | gpl-2.0 | e3a8cc7d146127dbdecc9d0d2747b7f0 | 0.663056 | 2.884684 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/sgmii_10_100_1000/ipcore_dir/temac_10_100_1000/example_design/temac_10_100_1000_fifo_block.vhd | 1 | 20,084 | --------------------------------------------------------------------------------
-- File : temac_10_100_1000_fifo_block.v
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This is the FIFO Block level vhdl wrapper for the Tri-Mode
-- Ethernet MAC core. This wrapper enhances the standard MAC core
-- with an example FIFO. The interface to this FIFO is
-- designed to the AXI-S specification.
-- Please refer to core documentation for
-- additional FIFO and AXI-S information.
--
-- _________________________________________________________
-- | |
-- | FIFO BLOCK LEVEL WRAPPER |
-- | |
-- | _____________________ ______________________ |
-- | | _________________ | | | |
-- | | | | | | | |
-- -------->| | TX AXI FIFO | |---->| Tx Tx |--------->
-- | | | | | | AXI-S PHY | |
-- | | |_________________| | | I/F I/F | |
-- | | | | | |
-- AXI | | 10/100/1G | | TRI-MODE ETHERNET | |
-- Stream | | ETHERNET FIFO | | MAC CORE | | PHY I/F
-- | | | | BLOCK WRAPPER | |
-- | | _________________ | | | |
-- | | | | | | | |
-- <--------| | RX AXI FIFO | |<----| Rx Rx |<---------
-- | | | | | | AXI-S PHY | |
-- | | |_________________| | | I/F I/F | |
-- | |_____________________| |______________________| |
-- | |
-- |_________________________________________________________|
--
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
-- The module declaration for the fifo block level wrapper.
--------------------------------------------------------------------------------
entity temac_10_100_1000_fifo_block is
port(
gtx_clk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Receiver Statistics Interface
-----------------------------------------
rx_reset : out std_logic;
rx_statistics_vector : out std_logic_vector(27 downto 0);
rx_statistics_valid : out std_logic;
-- Receiver (AXI-S) Interface
------------------------------------------
rx_fifo_clock : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tready : in std_logic;
rx_axis_fifo_tlast : out std_logic;
-- Transmitter Statistics Interface
--------------------------------------------
tx_reset : out std_logic;
tx_ifg_delay : in std_logic_vector(7 downto 0);
tx_statistics_vector : out std_logic_vector(31 downto 0);
tx_statistics_valid : out std_logic;
-- Transmitter (AXI-S) Interface
---------------------------------------------
tx_fifo_clock : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tready : out std_logic;
tx_axis_fifo_tlast : in std_logic;
-- MAC Control Interface
--------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(15 downto 0);
-- GMII Interface
-------------------
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
clk_enable : in std_logic;
speedis100 : out std_logic;
speedis10100 : out std_logic;
-- Configuration Vector
-------------------------
rx_configuration_vector : in std_logic_vector(79 downto 0);
tx_configuration_vector : in std_logic_vector(79 downto 0)
);
end temac_10_100_1000_fifo_block;
architecture wrapper of temac_10_100_1000_fifo_block is
------------------------------------------------------------------------------
-- Component declaration for the block level
------------------------------------------------------------------------------
component temac_10_100_1000_block
port(
gtx_clk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Receiver Interface
----------------------------
rx_statistics_vector : out std_logic_vector(27 downto 0);
rx_statistics_valid : out std_logic;
rx_reset : out std_logic;
rx_axis_mac_tdata : out std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : out std_logic;
rx_axis_mac_tlast : out std_logic;
rx_axis_mac_tuser : out std_logic;
-- Transmitter Interface
-------------------------------
tx_ifg_delay : in std_logic_vector(7 downto 0);
tx_statistics_vector : out std_logic_vector(31 downto 0);
tx_statistics_valid : out std_logic;
tx_reset : out std_logic;
tx_axis_mac_tdata : in std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : in std_logic;
tx_axis_mac_tlast : in std_logic;
tx_axis_mac_tuser : in std_logic;
tx_axis_mac_tready : out std_logic;
-- MAC Control Interface
------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(15 downto 0);
clk_enable : in std_logic;
speedis100 : out std_logic;
speedis10100 : out std_logic;
-- GMII Interface
-----------------
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
-- Configuration Vector
-----------------------
rx_configuration_vector : in std_logic_vector(79 downto 0);
tx_configuration_vector : in std_logic_vector(79 downto 0)
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the fifo
------------------------------------------------------------------------------
component temac_10_100_1000_ten_100_1g_eth_fifo
generic (
FULL_DUPLEX_ONLY : boolean := true); -- If fifo is to be used only in full
-- duplex set to true for optimised implementation
port (
tx_fifo_aclk : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tlast : in std_logic;
tx_axis_fifo_tready : out std_logic;
tx_mac_aclk : in std_logic;
tx_mac_resetn : in std_logic;
tx_axis_mac_tdata : out std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : out std_logic;
tx_axis_mac_tlast : out std_logic;
tx_axis_mac_tready : in std_logic;
tx_axis_mac_tuser : out std_logic;
tx_fifo_overflow : out std_logic;
tx_fifo_status : out std_logic_vector(3 downto 0);
tx_collision : in std_logic;
tx_retransmit : in std_logic;
rx_fifo_aclk : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tlast : out std_logic;
rx_axis_fifo_tready : in std_logic;
rx_mac_aclk : in std_logic;
rx_mac_resetn : in std_logic;
rx_axis_mac_tdata : in std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : in std_logic;
rx_axis_mac_tlast : in std_logic;
rx_axis_mac_tready : out std_logic;
rx_axis_mac_tuser : in std_logic;
rx_fifo_status : out std_logic_vector(3 downto 0);
rx_fifo_overflow : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the reset synchroniser
------------------------------------------------------------------------------
component temac_10_100_1000_reset_sync
port (
reset_in : in std_logic; -- Active high asynchronous reset
enable : in std_logic;
clk : in std_logic; -- clock to be sync'ed to
reset_out : out std_logic -- "Synchronised" reset signal
);
end component;
------------------------------------------------------------------------------
-- Internal signals used in this fifo block level wrapper.
------------------------------------------------------------------------------
-- Note: KEEP attributes preserve signal names so they can be displayed in
-- simulator wave windows
signal rx_reset_int : std_logic; -- MAC Rx reset
signal tx_reset_int : std_logic; -- MAC Tx reset
signal tx_mac_resetn : std_logic;
signal rx_mac_resetn : std_logic;
signal tx_mac_reset : std_logic;
signal rx_mac_reset : std_logic;
-- MAC receiver client I/F
signal rx_axis_mac_tdata : std_logic_vector(7 downto 0);
signal rx_axis_mac_tvalid : std_logic;
signal rx_axis_mac_tlast : std_logic;
signal rx_axis_mac_tuser : std_logic;
-- MAC transmitter client I/F
signal tx_axis_mac_tdata : std_logic_vector(7 downto 0);
signal tx_axis_mac_tvalid : std_logic;
signal tx_axis_mac_tready : std_logic;
signal tx_axis_mac_tlast : std_logic;
signal tx_axis_mac_tuser : std_logic;
-- Note: KEEP attributes preserve signal names so they can be displayed in
-- simulator wave windows
-- attribute keep : string;
-- attribute keep of rx_axis_mac_tdata : signal is "true";
-- attribute keep of rx_axis_mac_tvalid : signal is "true";
-- attribute keep of rx_axis_mac_tlast : signal is "true";
-- attribute keep of rx_axis_mac_tuser : signal is "true";
-- attribute keep of tx_axis_mac_tdata : signal is "true";
-- attribute keep of tx_axis_mac_tvalid : signal is "true";
-- attribute keep of tx_axis_mac_tready : signal is "true";
-- attribute keep of tx_axis_mac_tlast : signal is "true";
-- attribute keep of tx_axis_mac_tuser : signal is "true";
begin
------------------------------------------------------------------------------
-- Connect the output clock signals
------------------------------------------------------------------------------
rx_reset <= rx_reset_int;
tx_reset <= tx_reset_int;
------------------------------------------------------------------------------
-- Instantiate the Tri-Mode EMAC Block wrapper
------------------------------------------------------------------------------
trimac_block : temac_10_100_1000_block
port map(
gtx_clk => gtx_clk,
-- asynchronous reset
glbl_rstn => glbl_rstn,
rx_axi_rstn => rx_axi_rstn,
tx_axi_rstn => tx_axi_rstn,
-- Client Receiver Interface
rx_statistics_vector => rx_statistics_vector,
rx_statistics_valid => rx_statistics_valid,
rx_reset => rx_reset_int,
rx_axis_mac_tdata => rx_axis_mac_tdata,
rx_axis_mac_tvalid => rx_axis_mac_tvalid,
rx_axis_mac_tlast => rx_axis_mac_tlast,
rx_axis_mac_tuser => rx_axis_mac_tuser,
-- Client Transmitter Interface
tx_ifg_delay => tx_ifg_delay,
tx_statistics_vector => tx_statistics_vector,
tx_statistics_valid => tx_statistics_valid,
tx_reset => tx_reset_int,
tx_axis_mac_tdata => tx_axis_mac_tdata ,
tx_axis_mac_tvalid => tx_axis_mac_tvalid,
tx_axis_mac_tlast => tx_axis_mac_tlast,
tx_axis_mac_tuser => tx_axis_mac_tuser,
tx_axis_mac_tready => tx_axis_mac_tready,
-- Flow Control
pause_req => pause_req,
pause_val => pause_val,
clk_enable => clk_enable,
speedis100 => speedis100,
speedis10100 => speedis10100,
-- GMII Interface
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_rxd => gmii_rxd,
gmii_rx_dv => gmii_rx_dv,
gmii_rx_er => gmii_rx_er,
-- Configuration Vector
rx_configuration_vector => rx_configuration_vector,
tx_configuration_vector => tx_configuration_vector
);
------------------------------------------------------------------------------
-- Instantiate the user side FIFO
------------------------------------------------------------------------------
-- locally reset sync the mac generated resets - the resets are already fully sync
-- so adding a reset sync shouldn't change that
rx_mac_reset_gen : temac_10_100_1000_reset_sync
port map (
clk => gtx_clk,
enable => '1',
reset_in => rx_reset_int,
reset_out => rx_mac_reset
);
tx_mac_reset_gen : temac_10_100_1000_reset_sync
port map (
clk => gtx_clk,
enable => '1',
reset_in => tx_reset_int,
reset_out => tx_mac_reset
);
-- create inverted mac resets as the FIFO expects AXI compliant resets
tx_mac_resetn <= not tx_mac_reset;
rx_mac_resetn <= not rx_mac_reset;
user_side_FIFO : temac_10_100_1000_ten_100_1g_eth_fifo
generic map(
FULL_DUPLEX_ONLY => true
)
port map(
-- Transmit FIFO MAC TX Interface
tx_fifo_aclk => tx_fifo_clock,
tx_fifo_resetn => tx_fifo_resetn,
tx_axis_fifo_tdata => tx_axis_fifo_tdata,
tx_axis_fifo_tvalid => tx_axis_fifo_tvalid,
tx_axis_fifo_tlast => tx_axis_fifo_tlast,
tx_axis_fifo_tready => tx_axis_fifo_tready,
tx_mac_aclk => gtx_clk,
tx_mac_resetn => tx_mac_resetn,
tx_axis_mac_tdata => tx_axis_mac_tdata,
tx_axis_mac_tvalid => tx_axis_mac_tvalid,
tx_axis_mac_tlast => tx_axis_mac_tlast,
tx_axis_mac_tready => tx_axis_mac_tready,
tx_axis_mac_tuser => tx_axis_mac_tuser,
tx_fifo_overflow => open,
tx_fifo_status => open,
tx_collision => '0',
tx_retransmit => '0',
rx_fifo_aclk => rx_fifo_clock,
rx_fifo_resetn => rx_fifo_resetn,
rx_axis_fifo_tdata => rx_axis_fifo_tdata,
rx_axis_fifo_tvalid => rx_axis_fifo_tvalid,
rx_axis_fifo_tlast => rx_axis_fifo_tlast,
rx_axis_fifo_tready => rx_axis_fifo_tready,
rx_mac_aclk => gtx_clk,
rx_mac_resetn => rx_mac_resetn,
rx_axis_mac_tdata => rx_axis_mac_tdata,
rx_axis_mac_tvalid => rx_axis_mac_tvalid,
rx_axis_mac_tlast => rx_axis_mac_tlast,
rx_axis_mac_tready => open, -- not used as MAC cannot throttle
rx_axis_mac_tuser => rx_axis_mac_tuser,
rx_fifo_status => open,
rx_fifo_overflow => open
);
end wrapper;
| gpl-3.0 | ff69c9f5662e87e4b64499b8378c898b | 0.460964 | 4.212248 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/MMFE8_1VMM/sources_1/mmfe8_top.vhd | 1 | 80,457 | ----------------------------------------------------------------------------------
-- Company: NTU ATHNENS - BNL
-- Engineer: Paris Moschovakos & Panagiotis Gkountoumis
--
-- Create Date:
-- Design Name:
-- Module Name:
-- Project Name: MMFE8
-- Target Devices: Arix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2016.2
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity mmfe8_top is
port(
-- Trigger pins
-- CTF 1.0 External Trigger
EXT_TRIGGER_P : in std_logic;
EXT_TRIGGER_N : in std_logic;
-- Arizona Board for External Trigger
-- EXT_TRIG_IN : in std_logic;
TRIGGER_LOOP_P : out std_logic;
TRIGGER_LOOP_N : out std_logic;
-- LED's
LED_BANK_13 : out std_logic;
LED_BANK_14 : out std_logic;
LED_BANK_15 : out std_logic;
LED_BANK_16 : out std_logic;
LED_BANK_34 : out std_logic;
LED_BANK_35 : out std_logic;
-- 200.0359MHz from bank 14
X_2V5_DIFF_CLK_P : in std_logic;
X_2V5_DIFF_CLK_N : in std_logic;
-- glbl_rst : in std_logic;
-- Tranceiver Interface
-----------------------
gtrefclk_p : in std_logic; -- Differential +ve of reference clock for tranceiver: 125MHz, very high quality
gtrefclk_n : in std_logic; -- Differential -ve of reference clock for tranceiver: 125MHz, very high quality
txp : out std_logic; -- Differential +ve of serial transmission from PMA to PMD.
txn : out std_logic; -- Differential -ve of serial transmission from PMA to PMD.
rxp : in std_logic; -- Differential +ve for serial reception from PMD to PMA.
rxn : in std_logic; -- Differential -ve for serial reception from PMD to PMA.
phy_int : out std_logic;
phy_rstn_out : out std_logic;
DATA0_1_P, DATA0_1_N : IN STD_LOGIC;
DATA0_2_P, DATA0_2_N : IN STD_LOGIC;
DATA0_3_P, DATA0_3_N : IN STD_LOGIC;
DATA0_4_P, DATA0_4_N : IN STD_LOGIC;
DATA0_5_P, DATA0_5_N : IN STD_LOGIC;
DATA0_6_P, DATA0_6_N : IN STD_LOGIC;
DATA0_7_P, DATA0_7_N : IN STD_LOGIC;
DATA0_8_P, DATA0_8_N : IN STD_LOGIC;
DATA1_1_P, DATA1_1_N : IN STD_LOGIC;
DATA1_2_P, DATA1_2_N : IN STD_LOGIC;
DATA1_3_P, DATA1_3_N : IN STD_LOGIC;
DATA1_4_P, DATA1_4_N : IN STD_LOGIC;
DATA1_5_P, DATA1_5_N : IN STD_LOGIC;
DATA1_6_P, DATA1_6_N : IN STD_LOGIC;
DATA1_7_P, DATA1_7_N : IN STD_LOGIC;
DATA1_8_P, DATA1_8_N : IN STD_LOGIC;
DO_1_P, DO_1_N : IN STD_LOGIC;
DO_2_P, DO_2_N : IN STD_LOGIC;
DO_3_P, DO_3_N : IN STD_LOGIC;
DO_4_P, DO_4_N : IN STD_LOGIC;
DO_5_P, DO_5_N : IN STD_LOGIC;
DO_6_P, DO_6_N : IN STD_LOGIC;
DO_7_P, DO_7_N : IN STD_LOGIC;
DO_8_P, DO_8_N : IN STD_LOGIC;
DI_1_P, DI_1_N : OUT STD_LOGIC;
DI_2_P, DI_2_N : OUT STD_LOGIC;
DI_3_P, DI_3_N : OUT STD_LOGIC;
DI_4_P, DI_4_N : OUT STD_LOGIC;
DI_5_P, DI_5_N : OUT STD_LOGIC;
DI_6_P, DI_6_N : OUT STD_LOGIC;
DI_7_P, DI_7_N : OUT STD_LOGIC;
DI_8_P, DI_8_N : OUT STD_LOGIC;
WEN_1_P, WEN_1_N : OUT STD_LOGIC;
WEN_2_P, WEN_2_N : OUT STD_LOGIC;
WEN_3_P, WEN_3_N : OUT STD_LOGIC;
WEN_4_P, WEN_4_N : OUT STD_LOGIC;
WEN_5_P, WEN_5_N : OUT STD_LOGIC;
WEN_6_P, WEN_6_N : OUT STD_LOGIC;
WEN_7_P, WEN_7_N : OUT STD_LOGIC;
WEN_8_P, WEN_8_N : OUT STD_LOGIC;
ENA_1_P, ENA_1_N : OUT STD_LOGIC;
ENA_2_P, ENA_2_N : OUT STD_LOGIC;
ENA_3_P, ENA_3_N : OUT STD_LOGIC;
ENA_4_P, ENA_4_N : OUT STD_LOGIC;
ENA_5_P, ENA_5_N : OUT STD_LOGIC;
ENA_6_P, ENA_6_N : OUT STD_LOGIC;
ENA_7_P, ENA_7_N : OUT STD_LOGIC;
ENA_8_P, ENA_8_N : OUT STD_LOGIC;
CKTK_1_P, CKTK_1_N : OUT STD_LOGIC;
CKTK_2_P, CKTK_2_N : OUT STD_LOGIC;
CKTK_3_P, CKTK_3_N : OUT STD_LOGIC;
CKTK_4_P, CKTK_4_N : OUT STD_LOGIC;
CKTK_5_P, CKTK_5_N : OUT STD_LOGIC;
CKTK_6_P, CKTK_6_N : OUT STD_LOGIC;
CKTK_7_P, CKTK_7_N : OUT STD_LOGIC;
CKTK_8_P, CKTK_8_N : OUT STD_LOGIC;
CKTP_1_P, CKTP_1_N : OUT STD_LOGIC;
CKTP_2_P, CKTP_2_N : OUT STD_LOGIC;
CKTP_3_P, CKTP_3_N : OUT STD_LOGIC;
CKTP_4_P, CKTP_4_N : OUT STD_LOGIC;
CKTP_5_P, CKTP_5_N : OUT STD_LOGIC;
CKTP_6_P, CKTP_6_N : OUT STD_LOGIC;
CKTP_7_P, CKTP_7_N : OUT STD_LOGIC;
CKTP_8_P, CKTP_8_N : OUT STD_LOGIC;
CKBC_1_P, CKBC_1_N : OUT STD_LOGIC;
CKBC_2_P, CKBC_2_N : OUT STD_LOGIC;
CKBC_3_P, CKBC_3_N : OUT STD_LOGIC;
CKBC_4_P, CKBC_4_N : OUT STD_LOGIC;
CKBC_5_P, CKBC_5_N : OUT STD_LOGIC;
CKBC_6_P, CKBC_6_N : OUT STD_LOGIC;
CKBC_7_P, CKBC_7_N : OUT STD_LOGIC;
CKBC_8_P, CKBC_8_N : OUT STD_LOGIC;
CKDT_1_P, CKDT_1_N : OUT STD_LOGIC;
CKDT_2_P, CKDT_2_N : OUT STD_LOGIC;
CKDT_3_P, CKDT_3_N : OUT STD_LOGIC;
CKDT_4_P, CKDT_4_N : OUT STD_LOGIC;
CKDT_5_P, CKDT_5_N : OUT STD_LOGIC;
CKDT_6_P, CKDT_6_N : OUT STD_LOGIC;
CKDT_7_P, CKDT_7_N : OUT STD_LOGIC;
CKDT_8_P, CKDT_8_N : OUT STD_LOGIC
);
end mmfe8_top;
architecture Behavioral of mmfe8_top is
-- IP and MAC address of the MMFE8
constant myIP : std_logic_vector(31 downto 0) := x"c0a80003";
constant myMAC : std_logic_vector(47 downto 0) := x"002320212224";
-- clock generation signals for tranceiver
signal gtrefclkp, gtrefclkn : std_logic; -- Route gtrefclk through an IBUFG.
signal txoutclk : std_logic; -- txoutclk from GT transceiver
signal resetdone : std_logic; -- To indicate that the GT transceiver has completed its reset cycle
signal mmcm_locked : std_logic; -- MMCM locked signal.
signal mmcm_reset : std_logic; -- MMCM reset signal.
signal clkfbout : std_logic; -- MMCM feedback clock
signal userclk : std_logic; -- 62.5MHz clock for GT transceiver Tx/Rx user clocks
signal userclk2 : std_logic; -- 125MHz clock for core reference clock.
-- PMA reset generation signals for tranceiver
signal pma_reset_pipe : std_logic_vector(3 downto 0); -- flip-flop pipeline for reset duration stretch
signal pma_reset : std_logic; -- Synchronous transcevier PMA reset
-- An independent clock source used as the reference clock for an
-- IDELAYCTRL (if present) and for the main GT transceiver reset logic.
signal independent_clock_bufg: std_logic;
-- clock generation signals for SGMII clock
signal sgmii_clk_r : std_logic; -- Clock to client MAC (125MHz, 12.5MHz or 1.25MHz) (to rising edge DDR).
signal sgmii_clk_f : std_logic; -- Clock to client MAC (125MHz, 12.5MHz or 1.25MHz) (to falling edge DDR).
-- GMII signals
signal gmii_isolate : std_logic; -- Internal gmii_isolate signal.
signal gmii_txd_int : std_logic_vector(7 downto 0); -- Internal gmii_txd signal (between core and SGMII adaptation module).
signal gmii_tx_en_int : std_logic; -- Internal gmii_tx_en signal (between core and SGMII adaptation module).
signal gmii_tx_er_int : std_logic; -- Internal gmii_tx_er signal (between core and SGMII adaptation module).
signal gmii_rxd_int : std_logic_vector(7 downto 0); -- Internal gmii_rxd signal (between core and SGMII adaptation module).
signal gmii_rx_dv_int : std_logic; -- Internal gmii_rx_dv signal (between core and SGMII adaptation module).
signal gmii_rx_er_int : std_logic; -- Internal gmii_rx_er signal (between core and SGMII adaptation module).
-- Extra registers to ease IOB placement
signal status_vector_int : std_logic_vector(15 downto 0);
----------------------------panos---------------------------------
signal gmii_txd_emac : std_logic_vector(7 downto 0);
signal gmii_tx_en_emac : std_logic;
signal gmii_tx_er_emac : std_logic;
signal gmii_rxd_emac : std_logic_vector(7 downto 0);
signal gmii_rx_dv_emac : std_logic;
signal gmii_rx_er_emac : std_logic;
signal sgmii_clk_int : std_logic;
signal speed_is_10_100 : std_logic;
signal speed_is_100 : std_logic;
signal tx_axis_mac_tready_int : std_logic;
signal rx_axis_mac_tuser_int : std_logic;
signal rx_axis_mac_tlast_int : std_logic;
signal rx_axis_mac_tdata_int : std_logic_vector(7 downto 0);
signal rx_axis_mac_tvalid_int : std_logic;
signal local_gtx_reset : std_logic;
signal rx_reset : std_logic;
signal tx_reset : std_logic;
signal gtx_pre_resetn : std_logic := '0';
signal tx_axis_mac_tdata_int : std_logic_vector(7 downto 0);
signal tx_axis_mac_tvalid_int : std_logic;
signal tx_axis_mac_tlast_int : std_logic;
signal gtx_resetn : std_logic;
signal glbl_rstn : std_logic;
signal glbl_rst_i : std_logic;
signal gtx_clk_reset_int : std_logic;
signal an_restart_config_int : std_logic;
signal rx_axis_mac_tready_int : std_logic;
signal rx_configuration_vector_int : std_logic_vector(79 downto 0);
signal tx_configuration_vector_int : std_logic_vector(79 downto 0);
signal vector_resetn : std_logic := '0';
signal vector_pre_resetn : std_logic := '0';
signal vector_reset_int : std_logic;
signal independent_clock_int : std_logic;
signal rst_gtclk_int : std_logic;
signal clk_enable_int : std_logic;
signal sgmii_clk_int_oddr : std_logic;
signal udp_txi_int : udp_tx_type;
signal control : udp_control_type;
signal udp_rx_int : udp_rx_type;
signal ip_rx_hdr_int : ipv4_rx_header_type;
signal udp_tx_data_out_ready_int : std_logic;
signal udp_tx_start_int : std_logic;
signal rxp_int : std_logic;
signal rxn_int : std_logic;
signal clkfbout2, clkfbout1 : std_logic;
signal tx_axis_mac_tuser_int : std_logic := '1';
signal test_data : std_logic_vector(7 downto 0);
signal test_valid, test_last : std_logic;
signal test_data_out : std_logic_vector(7 downto 0);
signal test_valid_out, test_last_out : std_logic;
signal user_data_out_i : std_logic_vector(63 downto 0);
signal sig_out200 : std_logic_vector(127 downto 0);
signal user_conf_i : std_logic := '0';
signal send_error_int : std_logic := '0';
signal send_error_done_int : std_logic := '0';
signal resp_data_int : resp_data;
signal user_wr_en_int : std_logic := '0';
signal reset : std_logic := '0';
signal end_packet_i : std_logic := '0';
signal conf_done_int_synced : std_logic := '0';
signal we_conf_int : std_logic := '0';
signal conf_packet_length_int : integer := 0;
signal packet_length_int : integer := 0;
signal daq_data_out_i : std_logic_vector(63 downto 0);
signal conf_data_out_i : std_logic_vector(63 downto 0);
signal daq_wr_en_i : std_logic := '0';
signal end_packet_daq : std_logic := '0';
signal start_conf_proc_int : std_logic := '0';
signal status_int_old : std_logic_vector(3 downto 0);
------------------------------VMM configuration------------------------------
signal vmm_do_vec_i : std_logic_vector(8 downto 1);
signal conf_cktk_out_i : std_logic := '0';
signal trig_mode_int : std_logic := '0';
------------------------------ Select VMM ------------------------------
signal cktk_out_vec_i : std_logic_vector(8 downto 1);
signal vmm_wen_i : std_logic := '0';
signal vmm_ena_i : std_logic := '0';
-------------------------------------------------
-- Configuration Signals
-------------------------------------------------
signal configuring_i : std_logic;
signal reading_i_200 : std_logic;
signal conf_done_i_200 : std_logic;
signal cntr, cntr2 : integer := 0;
signal vmm_cnt, counter : integer := 0;
signal reset_done : std_logic := '0';
signal vmm_data0_1_syn : std_logic;
signal vmm_data1_1_syn : std_logic;
signal vmm_data0_ii_d : std_logic;
signal vmm_data0_ii : std_logic;
signal vmm_data0_i : std_logic;
signal vmm_do_fde_sync : std_logic;
signal vmm_do_fde : std_logic;
signal vmm_do_fde_i : std_logic;
signal delay_wen : integer := 0;
signal w : integer := 0;
signal data_fifo_wr_en : std_logic;
signal data_fifo_wr_en_i : std_logic;
signal data_fifo_din_i : std_logic_vector(7 DOWNTO 0);
signal data_fifo_rd_en : std_logic;
signal data_fifo_rd_en_i : std_logic;
-- signal data_fifo_dout_i : std_logic_vector(0 DOWNTO 0);
signal data_fifo_empty : std_logic;
signal data_fifo_rd_count : std_logic_vector(14 DOWNTO 0);
signal data_fifo_wr_count : std_logic_vector(14 DOWNTO 0);
signal vmm_cfg_sel_i : std_logic_vector(31 downto 0);
signal turn_counter_i : std_logic_vector(15 downto 0);
signal conf_data_in_i : std_logic_vector (7 downto 0);
signal udp_response_int : udp_response;
signal clk_400_noclean : std_logic;
signal clk_400_clean : std_logic;
signal clk_200 : std_logic;
signal clk_800 : std_logic;
signal clk_10_phase45 : std_logic;
signal clk_50 : std_logic;
signal clk_40 : std_logic;
signal clk_10 : std_logic;
signal gbl_rst : std_logic; --coming from UDP
signal acq_rst : std_logic; --coming from UDP
signal vmm_ena_gbl_rst : std_logic := '0';
signal vmm_wen_gbl_rst : std_logic := '0';
signal vmm_ena_acq_rst : std_logic := '0';
signal vmm_wen_acq_rst : std_logic := '0';
-- signal conf_data_out_i : std_logic_vector(7 downto 0);
signal vmm_data_buf_i : std_logic_vector(37 downto 0);
-- vmm signals
signal conf_di_i : std_logic;
signal conf_do_i : std_logic;
signal conf_ena_i : std_logic := '0';
signal conf_wen_i : std_logic;
signal conf_cktk_i : std_logic;
signal vmm_do_1_i : std_logic := '0';
signal vmm_di_en : std_logic;
signal vmm_di_r : std_logic;
signal vmm_wen_en : std_logic;
signal vmm_wen_R : std_logic;
signal vmm_ena_en : std_logic;
signal vmm_ena_r : std_logic;
signal vmm_cktk_en : std_logic;
signal vmm_cktk_r : std_logic;
signal vmm_cktp : std_logic;
signal vmm_cktp_en : std_logic;
signal vmm_cktp_r : std_logic;
signal vmm_ckbc : std_logic;
signal vmm_ckbc_en : std_logic;
signal vmm_ckbc_R : std_logic;
signal dt_cntr_intg0_i : integer;
signal ckdt_cntr, timeout : integer := 0;
signal dt_cntr_intg1_i : integer;
signal conf_cnt : integer := 0;
signal cnt_vmm : integer := 0;
-- signal timeout : integer := 0;
signal vmm_2cfg_i : std_logic_vector( 2 DOWNTO 0);
signal mmfeID_i : std_logic_vector( 3 DOWNTO 0);
signal clk_dt_out : std_logic;
signal vmm_ckart : std_logic;
signal vmm_ckart_en : std_logic;
signal vmm_ckart_r : std_logic;
signal clk_tk_out : std_logic;
signal clk_bc_out : std_logic;
signal testX, reading_i : std_logic := '0';
signal clk_tp_out : std_logic ;
signal write_done_i : std_logic;
signal fifo_writing_i : std_logic;
signal global_reset : std_logic := '0';
signal conf_done_i : std_logic;
signal cktp_send : std_logic := '0';
signal conf_wait : std_logic := '0';
signal udp_tx_start_reply : std_logic := '0';
signal udp_tx_start_daq : std_logic := '0';
signal re_out_int : std_logic := '0';
signal fifo_data_out_int : std_logic_vector(7 downto 0) := x"00";
signal fifo_data : std_logic_vector(7 downto 0) := x"00";
signal re_out : std_logic := '0';
signal status_int : std_logic_vector(3 downto 0) := "0000";
signal status_int_synced : std_logic_vector(3 downto 0) := "0000";
signal cnt_reset : integer := 0;
signal set_reset : std_logic := '0';
signal conf_done_int : std_logic := '0';
signal udp_header_int : std_logic := '0';
signal cnt_reply : integer := 0;
signal end_packet_conf_int : std_logic := '0';
signal end_packet_daq_int : std_logic := '0';
signal is_state : std_logic_vector(3 downto 0) := "1010";
signal ACQ_sync_int : std_logic_vector(15 downto 0) := x"0000";
signal udp_busy : std_logic := '0';
-------------------------------------------------
-- VMM2 Signals
-------------------------------------------------
signal vmm_wen_vec : std_logic_vector(8 downto 1);
signal vmm_ena_vec : std_logic_vector(8 downto 1);
signal cktk_out_vec : std_logic_vector(8 downto 1);
signal ckdt_out_vec : std_logic_vector(8 downto 1);
signal vmm_do_vec : std_logic_vector(8 downto 1);
signal vmm_di_vec_i : std_logic_vector(8 downto 1);
signal cktk_out_i : std_logic;
signal vmm_id : std_logic_vector(15 downto 0) := x"0000";
signal vmm_id_int : std_logic_vector(15 downto 0) := x"0000";
signal vmm_id_synced : std_logic_vector(15 downto 0) := x"0000";
signal vmm_id_old : std_logic_vector(15 downto 0) := x"0000";
signal vmm_do_1 : std_logic;
signal vmm_cktp_1 : std_logic;
signal vmm_data0_1 : std_logic;
signal vmm_data1_1 : std_logic;
signal vmm_art_1 : std_logic;
-- signal vmm_ckart_1 : std_logic;
signal vmm_do_2 : std_logic;
signal vmm_cktp_2 : std_logic;
signal vmm_data0_2 : std_logic;
signal vmm_data1_2 : std_logic;
signal vmm_art_2 : std_logic;
-- signal vmm_ckart_2 : std_logic;
signal vmm_do_3 : std_logic;
signal vmm_cktp_3 : std_logic;
signal vmm_data0_3 : std_logic;
signal vmm_data1_3 : std_logic;
signal vmm_art_3 : std_logic;
-- signal vmm_ckart_3 : std_logic;
signal vmm_do_4 : std_logic;
signal vmm_cktp_4 : std_logic;
signal vmm_data0_4 : std_logic;
signal vmm_data1_4 : std_logic;
signal vmm_art_4 : std_logic;
-- signal vmm_ckart_4 : std_logic;
signal vmm_do_5 : std_logic;
signal vmm_cktp_5 : std_logic;
signal vmm_data0_5 : std_logic;
signal vmm_data1_5 : std_logic;
signal vmm_art_5 : std_logic;
-- signal vmm_ckart_5 : std_logic;
signal vmm_do_6 : std_logic;
signal vmm_cktp_6 : std_logic;
signal vmm_data0_6 : std_logic;
signal vmm_data1_6 : std_logic;
signal vmm_art_6 : std_logic;
-- signal vmm_ckart_6 : std_logic;
signal vmm_do_7 : std_logic;
signal vmm_cktp_7 : std_logic;
signal vmm_data0_7 : std_logic;
signal vmm_data1_7 : std_logic;
signal vmm_art_7 : std_logic;
-- signal vmm_ckart_7 : std_logic;
signal vmm_do_8 : std_logic;
signal vmm_cktp_8 : std_logic;
signal vmm_data0_8 : std_logic;
signal vmm_data1_8 : std_logic;
signal vmm_art_8 : std_logic;
-- signal vmm_ckart_8 : std_logic;
-------------------------------------------------
-- Readout Signals
-------------------------------------------------
signal daq_enable_i : std_logic;
signal daq_done : std_logic;
signal cktp_state : integer := 0;
signal ro_cktk_8 : std_logic;
signal ro_ckdt_8 : std_logic;
signal ro_vmm_wen_8 : std_logic := '0';
signal ro_vmm_ena_8 : std_logic := '0';
signal ro_cktk_5 : std_logic;
signal ro_ckdt_5 : std_logic;
signal ro_vmm_wen_5 : std_logic := '0';
signal ro_vmm_ena_5 : std_logic := '0';
signal daqFIFO_wr_en_i : std_logic := '0';
signal daqFIFO_din_i : std_logic_vector(63 downto 0);
signal daqFIFO_dout_i : std_logic_vector(7 downto 0);
signal vmmWordReady_i : std_logic := '0';
signal vmmWord_i : std_logic_vector(63 downto 0);
signal vmmEventDone_i : std_logic := '0';
signal daqFIFO_reset : std_logic := '0';
signal daq_vmm_ena_enable : std_logic := '0';
signal daq_vmm_wen_enable : std_logic := '0';
-------------------------------------------------
-- Trigger Signals
-------------------------------------------------
signal tren : std_logic := '0';
signal tr_hold : std_logic := '0';
signal trmode : std_logic := '0';
signal ext_trigger_in : std_logic := '0';
signal trint : std_logic := '0';
signal tr_reset : std_logic := '0';
signal event_counter_i : std_logic_vector(31 downto 0);
signal event_counter_ila : std_logic_vector(31 downto 0);
signal tr_out_i : std_logic;
signal trigger_loop : std_logic;
signal trigger_loop_i : std_logic;
signal ext_trigger_i : std_logic;
signal internalTrigger_state : integer := 0;
-------------------------------------------------
-- Packet Formation Signals
-------------------------------------------------
signal pf_datain_i : std_logic_vector(63 downto 0);
signal pf_newCycle : std_logic;
signal pf_dataout : std_logic_vector(63 downto 0);
signal pf_wren : std_logic;
signal pf_packLen : integer;
signal pf_trigVmmRo : std_logic := '0';
-------------------------------------------------
-- Flow FSM signals
-------------------------------------------------
type state_t is (IDLE, CONFIGURE, CONF_DONE, SEND_CONF_REPLY, DAQ_INIT, DAQ, TRIG);
signal state : state_t;
-------------------------------------------------------------------
-- COMPONENTS --
-------------------------------------------------------------------
-- 1. clk_wiz_200_to_400
-- 2. clk_wiz_low_jitter
-- 3. clk_wiz_0
-- 4. vmm_global_reset
-- 5. event_timing_reset
-- 6. select_vmm
-- 7. configuration_block
-- 8. vmm_readout
-- 9. FIFO2UDP
-- 10. trigger
-- 11. ila_top
-- 12. FIFO2Elink
-- 13. Elink2FIFO
-- 14. Please add the components
-- ...
-- 21.
-------------------------------------------------------------------
-- 1
component clk_wiz_200_to_400
port(
clk_in1_p : in std_logic;
clk_in1_n : in std_logic;
clk_out_400 : out std_logic
);
end component;
-- 2
component clk_wiz_low_jitter
port(
clk_in1 : in std_logic;
clk_out1 : out std_logic
);
end component;
-- 3
component clk_wiz_0
port(
clk_in1 : in std_logic;
reset : in std_logic;
clk_200_o : out std_logic;
clk_800_o : out std_logic;
clk_10_phase45_o: out std_logic;
clk_50_o : out std_logic;
clk_40_o : out std_logic;
clk_10_o : out std_logic
);
end component;
-- 4
component vmm_global_reset
port(
clk : in std_logic;
rst : in std_logic; -- reset
gbl_rst : in std_logic; -- from control register. a pulse
vmm_ena : out std_logic; -- these will be ored with same from other sm
vmm_wen : out std_logic -- these will be ored with same from other sm
);
end component;
-- 5
component event_timing_reset
port(
hp_clk : in std_logic;
bc_clk : in std_logic;
trigger : in std_logic;
readout_done : in std_logic;
reset : in std_logic;
bcid : out std_logic_vector(12 downto 0);
prec_cnt : out std_logic_vector(4 downto 0);
vmm_ena : out std_logic;
vmm_wen : out std_logic
);
end component;
-- 6
component select_vmm
port (
clk_in : in std_logic;
vmm_id : in std_logic_vector(15 downto 0);
conf_di : in std_logic;
conf_di_vec : out std_logic_vector(8 downto 1);
conf_do : out std_logic;
conf_do_vec : in std_logic_vector(8 downto 1);
cktk_out : in std_logic;
cktk_out_vec : out std_logic_vector(8 downto 1);
conf_wen : in std_logic;
conf_wen_vec : out std_logic_vector(8 downto 1);
conf_ena : in std_logic;
conf_ena_vec : out std_logic_vector(8 downto 1)
);
end component;
-- 7
component configuration_block
port
(
clk_in : in STD_LOGIC;
reset : in STD_LOGIC;
cfg_bit_in : in std_logic ;
cfg_bit_out : out std_logic ;
vmm_cktk : out std_logic ;
configuring : in std_logic;
conf_done : out std_logic;
data_fifo_wr_en : in std_logic := '0'; -- signal cannot be driven from top module !!!
data_fifo_din : in std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
-- data_fifo_rd_en : in std_logic;-- := '0';
data_fifo_empty : out std_logic := '0';
data_fifo_rd_count : out std_logic_vector(14 DOWNTO 0) := (OTHERS => '0');
data_fifo_wr_count : out std_logic_vector(14 DOWNTO 0) := (OTHERS => '0');
conf_data_in : in STD_LOGIC_VECTOR(7 downto 0);
conf_data_out : out STD_LOGIC_VECTOR(7 downto 0);
vmm_cfg_sel : in STD_LOGIC_VECTOR(31 downto 0));
end component;
-- 8
component vmm_readout is
port (
vmm_data0 : in std_logic; -- Single-ended data0 from VMM
vmm_data1 : in std_logic; -- Single-ended data1 from VMM
clk_10_phase45 : in std_logic; -- Used to clock checking for data process
clk_50 : in std_logic; -- Used to clock word readout process
clk_200 : in std_logic;
daq_enable : in std_logic;
trigger_pulse : in std_logic; -- To be used trigger
ethernet_fifo_wr_en : out std_logic; -- To be used to for ethernet to software readout
latency : in std_logic_vector(15 downto 0);
vmm_ckdt : out std_logic; -- Strobe to VMM CKDT
vmm_cktk : out std_logic; -- Strobe to VMM CKTK
acq_rst_from_data0 : out std_logic; -- Send a soft reset when done
vmm_data_buf : buffer std_logic_vector(37 downto 0);
vmm_wen : out std_logic;
vmm_ena : out std_logic;
vmmWordReady : out std_logic;
vmmWord : out std_logic_vector(63 downto 0);
vmmEventDone : out std_logic
);
end component;
-- 9
component FIFO2UDP
port (
clk_200 : in std_logic;
clk_125 : in std_logic;
daq_data_in : in std_logic_vector(63 downto 0);
fifo_data_out : out std_logic_vector (7 downto 0);
udp_txi : out udp_tx_type;
udp_tx_start : out std_logic;
control : out std_logic;
re_out : out std_logic;
udp_tx_data_out_ready : in std_logic;
wr_en : in std_logic;
end_packet : in std_logic;
global_reset : in std_logic;
packet_length_in : in integer;
reset_DAQ_FIFO : in std_logic;
sending_o : out std_logic
);
end component;
-- 10
component trigger is
port (
clk_200 : in std_logic;
tren : in std_logic;
tr_hold : in std_logic;
trmode : in std_logic;
trext : in std_logic;
trint : in std_logic;
reset : in std_logic;
event_counter : out std_logic_vector(31 DOWNTO 0);
tr_out : out std_logic
);
end component;
-- 11
component packet_formation is
port (
clk_200 : in std_logic;
newCycle : in std_logic;
eventCounter : in std_logic_vector(31 downto 0);
trigVmmRo : out std_logic;
vmmWord : in std_logic_vector(63 downto 0);
vmmWordReady : in std_logic;
vmmEventDone : in std_logic;
packLen : out integer;
dataout : out std_logic_vector(63 downto 0);
wrenable : out std_logic;
end_packet : out std_logic;
udp_busy : in std_logic;
tr_hold : out std_logic
);
end component;
-- 12
component gig_ethernet_pcs_pma_0
port(
-- Transceiver Interface
---------------------
gtrefclk_p : in std_logic;
gtrefclk_n : in std_logic;
gtrefclk_out : out std_logic; -- Very high quality clock for GT transceiver.
gtrefclk_bufg_out : out std_logic;
txp : out std_logic; -- Differential +ve of serial transmission from PMA to PMD.
txn : out std_logic; -- Differential -ve of serial transmission from PMA to PMD.
rxp : in std_logic; -- Differential +ve for serial reception from PMD to PMA.
rxn : in std_logic; -- Differential -ve for serial reception from PMD to PMA.
resetdone : out std_logic; -- The GT transceiver has completed its reset cycle
userclk_out : out std_logic;
userclk2_out : out std_logic;
rxuserclk_out : out std_logic;
rxuserclk2_out : out std_logic;
pma_reset_out : out std_logic; -- transceiver PMA reset signal
mmcm_locked_out : out std_logic; -- MMCM Locked
independent_clock_bufg : in std_logic;
-- GMII Interface
-----------------
sgmii_clk_r : out std_logic;
sgmii_clk_f : out std_logic;
sgmii_clk_en : out std_logic; -- Clock enable for client MAC
gmii_txd : in std_logic_vector(7 downto 0); -- Transmit data from client MAC.
gmii_tx_en : in std_logic; -- Transmit control signal from client MAC.
gmii_tx_er : in std_logic; -- Transmit control signal from client MAC.
gmii_rxd : out std_logic_vector(7 downto 0); -- Received Data to client MAC.
gmii_rx_dv : out std_logic; -- Received control signal to client MAC.
gmii_rx_er : out std_logic; -- Received control signal to client MAC.
gmii_isolate : out std_logic; -- Tristate control to electrically isolate GMII.
-- Management: Alternative to MDIO Interface
--------------------------------------------
configuration_vector : in std_logic_vector(4 downto 0); -- Alternative to MDIO interface.
an_interrupt : out std_logic; -- Interrupt to processor to signal that Auto-Negotiation has completed
an_adv_config_vector : in std_logic_vector(15 downto 0); -- Alternate interface to program REG4 (AN ADV)
an_restart_config : in std_logic; -- Alternate signal to modify AN restart bit in REG0
-- Speed Control
----------------
speed_is_10_100 : in std_logic; -- Core should operate at either 10Mbps or 100Mbps speeds
speed_is_100 : in std_logic; -- Core should operate at 100Mbps speed
-- General IO's
---------------
status_vector : out std_logic_vector(15 downto 0); -- Core status.
reset : in std_logic; -- Asynchronous reset for entire core.
signal_detect : in std_logic; -- Input from PMD to indicate presence of optical input.
gt0_pll0outclk_out : out std_logic;
gt0_pll0outrefclk_out : out std_logic;
gt0_pll1outclk_out : out std_logic;
gt0_pll1outrefclk_out : out std_logic;
gt0_pll0refclklost_out : out std_logic;
gt0_pll0lock_out : out std_logic);
end component;
-- 13
component UDP_Complete_nomac
Port (
-- UDP TX signals
udp_tx_start : in std_logic; -- indicates req to tx UDP
udp_txi : in udp_tx_type; -- UDP tx cxns
udp_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
udp_tx_data_out_ready : out std_logic; -- indicates udp_tx is ready to take data
-- UDP RX signals
udp_rx_start : out std_logic; -- indicates receipt of udp header
udp_rxo : out udp_rx_type;
-- IP RX signals
ip_rx_hdr : out ipv4_rx_header_type;
-- system signals
rx_clk : in STD_LOGIC;
tx_clk : in STD_LOGIC;
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
control : in udp_control_type;
-- status signals
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
-- MAC Transmitter
mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx
mac_tx_tvalid : out std_logic; -- tdata is valid
mac_tx_tready : in std_logic; -- mac is ready to accept data
mac_tx_tfirst : out std_logic; -- indicates first byte of frame
mac_tx_tlast : out std_logic; -- indicates last byte of frame
-- MAC Receiver
mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received
mac_rx_tvalid : in std_logic; -- indicates tdata is valid
mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
mac_rx_tlast : in std_logic); -- indicates last byte of the trame
end component;
-- 14
component temac_10_100_1000_fifo_block
port(
gtx_clk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Receiver Statistics Interface
-----------------------------------------
rx_reset : out std_logic;
rx_statistics_vector : out std_logic_vector(27 downto 0);
rx_statistics_valid : out std_logic;
-- Receiver (AXI-S) Interface
------------------------------------------
rx_fifo_clock : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tready : in std_logic;
rx_axis_fifo_tlast : out std_logic;
-- Transmitter Statistics Interface
--------------------------------------------
tx_reset : out std_logic;
tx_ifg_delay : in std_logic_vector(7 downto 0);
tx_statistics_vector : out std_logic_vector(31 downto 0);
tx_statistics_valid : out std_logic;
-- Transmitter (AXI-S) Interface
---------------------------------------------
tx_fifo_clock : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tready : out std_logic;
tx_axis_fifo_tlast : in std_logic;
-- MAC Control Interface
--------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(15 downto 0);
-- GMII Interface
-------------------
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
clk_enable : in std_logic;
speedis100 : out std_logic;
speedis10100 : out std_logic;
-- Configuration Vector
-------------------------
rx_configuration_vector : in std_logic_vector(79 downto 0);
tx_configuration_vector : in std_logic_vector(79 downto 0));
end component;
-- 15
component temac_10_100_1000_reset_sync
port (
reset_in : in std_logic; -- Active high asynchronous reset
enable : in std_logic;
clk : in std_logic; -- clock to be sync'ed to
reset_out : out std_logic); -- "Synchronised" reset signal
end component;
-- 16
component temac_10_100_1000_config_vector_sm is
port(
gtx_clk : in std_logic;
gtx_resetn : in std_logic;
mac_speed : in std_logic_vector(1 downto 0);
update_speed : in std_logic;
rx_configuration_vector : out std_logic_vector(79 downto 0);
tx_configuration_vector : out std_logic_vector(79 downto 0));
end component;
-- 17
component i2c_top is
port(
clk_in : in std_logic;
phy_rstn_out : out std_logic
-- SCL_out : out std_logic;
-- SDA_inout : inout std_logic
);
end component;
-- 18
component config_logic is
Port (
clk125 : in std_logic;
clk200 : in std_logic;
clk_in : in std_logic;
reset : in std_logic;
user_data_in : in std_logic_vector (7 downto 0);
user_data_out : out std_logic_vector (63 downto 0);
-- user_sn_out : out std_logic_vector (31 downto 0);
udp_rx : in udp_rx_type;
resp_data : out udp_response;
send_error : out std_logic;
user_conf : out std_logic;
user_wr_en : in std_logic;
user_last : in std_logic;
configuring : in std_logic;
we_conf : out std_logic;
conf_packet_length : out integer;
vmm_id : out std_logic_vector(15 downto 0);
cfg_bit_out : out std_logic ;
vmm_cktk : out std_logic ;
status : out std_logic_vector(3 downto 0);
start_vmm_conf : in std_logic;
conf_done : out std_logic;
ext_trigger : out std_logic;
ACQ_sync : out std_logic_vector(15 downto 0);
-- vmm_we : in std_logic;
udp_header : in std_logic;
packet_length : in std_logic_vector (15 downto 0));
end component;
-- 21
component select_data
port(
clk_in : in std_logic;
configuring : in std_logic;
data_acq : in std_logic;
we_data : in std_logic;
we_conf : in std_logic;
daq_data_in : in std_logic_vector(63 downto 0);
conf_data_in : in std_logic_vector(63 downto 0);
data_packet_length : in integer;
conf_packet_length : in integer;
end_packet_conf : in std_logic;
end_packet_daq : in std_logic;
data_out : out std_logic_vector(63 downto 0);
packet_length : out integer;
we : out std_logic;
end_packet : out std_logic
);
end component;
-- These attributes will stop timing errors being reported in back annotated
-- SDF simulation.
begin
-- glbl_rst_i <= '0';
glbl_rstn <= not glbl_rst_i;
phy_int <= '1';
gen_vector_reset: process (userclk2)
begin
if userclk2'event and userclk2 = '1' then
if vector_reset_int = '1' then
vector_pre_resetn <= '0';
vector_resetn <= '0';
else
vector_pre_resetn <= '1';
vector_resetn <= vector_pre_resetn;
end if;
end if;
end process gen_vector_reset;
mmcm_reset <= glbl_rst_i; -- reset;
-----------------------------------------------------------------------------
-- Transceiver PMA reset circuitry
-----------------------------------------------------------------------------
-- Create a reset pulse of a decent length
process(glbl_rst_i, clk_200)
begin
if (glbl_rst_i = '1') then
pma_reset_pipe <= "1111";
elsif clk_200'event and clk_200 = '1' then
pma_reset_pipe <= pma_reset_pipe(2 downto 0) & glbl_rst_i;
end if;
end process;
pma_reset <= pma_reset_pipe(3);
core_wrapper: gig_ethernet_pcs_pma_0
-- generic map ( EXAMPLE_SIMULATION => 0)
port map (
gtrefclk_p => gtrefclk_p,
gtrefclk_n => gtrefclk_n,
txp => txp,
txn => txn,
rxp => rxp,
rxn => rxn,
gtrefclk_out => open,
gtrefclk_bufg_out => txoutclk,
rxuserclk_out => open,
rxuserclk2_out => open,
-- txoutclk => txoutclk,
resetdone => resetdone,
mmcm_locked_out => mmcm_locked,
userclk_out => userclk,
userclk2_out => userclk2,
independent_clock_bufg => clk_200,
pma_reset_out => pma_reset,
sgmii_clk_r => sgmii_clk_r,
sgmii_clk_f => sgmii_clk_f,
sgmii_clk_en => clk_enable_int,
gmii_txd => gmii_txd_int,
gmii_tx_en => gmii_tx_en_int,
gmii_tx_er => gmii_tx_er_int,
gmii_rxd => gmii_rxd_int,
gmii_rx_dv => gmii_rx_dv_int,
gmii_rx_er => gmii_rx_er_int,
gmii_isolate => gmii_isolate,
configuration_vector => "10000", -- configuration_vector,
status_vector => status_vector_int, -- status_vector_int,
reset => glbl_rst_i,
signal_detect => '1', -- signal_detect
speed_is_10_100 => speed_is_10_100,
speed_is_100 => speed_is_100,
an_interrupt => open, -- Interrupt to processor to signal that Auto-Negotiation has completed
an_adv_config_vector => "1111111000000001",-- Alternate interface to program REG4 (AN ADV)
an_restart_config => an_restart_config_int, -- Alternate signal to modify AN restart bit in REG0
gt0_pll0outclk_out => open,
gt0_pll0outrefclk_out => open,
gt0_pll1outclk_out => open,
gt0_pll1outrefclk_out => open,
gt0_pll0refclklost_out => open,
gt0_pll0lock_out => open);
process(userclk2)
begin
if (local_gtx_reset = '1') then
an_restart_config_int <= '1';
else
an_restart_config_int <= '0';
end if;
end process;
tri_fifo: temac_10_100_1000_fifo_block
port map(
gtx_clk => userclk2, --sgmii_clk_int, --userclk2,
-- asynchronous reset
glbl_rstn => glbl_rstn,
rx_axi_rstn => '1',
tx_axi_rstn => '1',
-- Receiver Statistics Interface
-----------------------------------------
rx_reset => rx_reset,
rx_statistics_vector => open,
rx_statistics_valid => open,
-- Receiver (AXI-S) Interface
------------------------------------------
rx_fifo_clock => userclk2,
rx_fifo_resetn => gtx_resetn,
rx_axis_fifo_tdata => rx_axis_mac_tdata_int,
rx_axis_fifo_tvalid => rx_axis_mac_tvalid_int,
rx_axis_fifo_tready => rx_axis_mac_tready_int,
rx_axis_fifo_tlast => rx_axis_mac_tlast_int,
-- Transmitter Statistics Interface
--------------------------------------------
tx_reset => tx_reset,
tx_ifg_delay => x"00",
tx_statistics_vector => open,
tx_statistics_valid => open,
-- Transmitter (AXI-S) Interface
---------------------------------------------
tx_fifo_clock => userclk2,
tx_fifo_resetn => gtx_resetn,
tx_axis_fifo_tdata => tx_axis_mac_tdata_int,
tx_axis_fifo_tvalid => tx_axis_mac_tvalid_int,
tx_axis_fifo_tready => tx_axis_mac_tready_int,
tx_axis_fifo_tlast => tx_axis_mac_tlast_int,
-- MAC Control Interface
--------------------------
pause_req => '0',
pause_val => x"0000",
-- GMII Interface
-------------------
gmii_txd => gmii_txd_emac,
gmii_tx_en => gmii_tx_en_emac,
gmii_tx_er => gmii_tx_er_emac,
gmii_rxd => gmii_rxd_emac,
gmii_rx_dv => gmii_rx_dv_emac,
gmii_rx_er => gmii_rx_er_emac,
clk_enable => clk_enable_int,
speedis100 => speed_is_100,
speedis10100 => speed_is_10_100,
-- Configuration Vector
-------------------------
rx_configuration_vector => rx_configuration_vector_int, -- x"0605_0403_02da_0000_2022",
tx_configuration_vector => tx_configuration_vector_int); -- x"0605_0403_02da_0000_2022"
-- Control vector reset
axi_lite_reset_gen: temac_10_100_1000_reset_sync
port map (
clk => userclk2,
enable => '1',
reset_in => glbl_rst_i,
reset_out => vector_reset_int);
config_vector: temac_10_100_1000_config_vector_sm
port map(
gtx_clk => userclk2, --sgmii_clk_int, --userclk2,
gtx_resetn => vector_resetn,
mac_speed => status_vector_int(11 downto 10), -- "10",
update_speed => '1',
rx_configuration_vector => rx_configuration_vector_int,
tx_configuration_vector => tx_configuration_vector_int);
-----------------------------------------------------------------------------
-- GMII transmitter data logic
-----------------------------------------------------------------------------
-- Drive input GMII signals through IOB input flip-flops (inferred).
process (userclk2)
begin
if userclk2'event and userclk2 = '1' then
gmii_txd_int <= gmii_txd_emac;
gmii_tx_en_int <= gmii_tx_en_emac;
gmii_tx_er_int <= gmii_tx_er_emac;
end if;
end process;
local_gtx_reset <= glbl_rst_i or rx_reset or tx_reset;
gtx_reset_gen: temac_10_100_1000_reset_sync
port map (
clk => userclk2,
enable => '1',
reset_in => local_gtx_reset,
reset_out => gtx_clk_reset_int);
gen_gtx_reset: process (userclk2)
begin
if userclk2'event and userclk2 = '1' then
if gtx_clk_reset_int = '1' then
gtx_pre_resetn <= '0';
gtx_resetn <= '0';
else
gtx_pre_resetn <= '1';
gtx_resetn <= gtx_pre_resetn;
end if;
end if;
end process gen_gtx_reset;
-- Drive input GMII signals through IOB output flip-flops (inferred).
process (userclk2)
begin
if userclk2'event and userclk2 = '1' then
gmii_rxd_emac <= gmii_rxd_int;
gmii_rx_dv_emac <= gmii_rx_dv_int;
gmii_rx_er_emac <= gmii_rx_er_int;
end if;
end process;
UDP_block: UDP_Complete_nomac
Port map(
udp_tx_start => udp_tx_start_int,
udp_txi => udp_txi_int,
udp_tx_result => open,
udp_tx_data_out_ready => udp_tx_data_out_ready_int,
udp_rx_start => udp_header_int, -- indicates receipt of udp header
udp_rxo => udp_rx_int,
ip_rx_hdr => ip_rx_hdr_int,
rx_clk => userclk2,
tx_clk => userclk2,
reset => glbl_rst_i,
our_ip_address => myIP,
our_mac_address => myMAC,
control => control,
arp_pkt_count => open,
ip_pkt_count => open,
mac_tx_tdata => tx_axis_mac_tdata_int,
mac_tx_tvalid => tx_axis_mac_tvalid_int,
mac_tx_tready => tx_axis_mac_tready_int,
mac_tx_tfirst => open,
mac_tx_tlast => tx_axis_mac_tlast_int,
mac_rx_tdata => rx_axis_mac_tdata_int,
mac_rx_tvalid => rx_axis_mac_tvalid_int,
mac_rx_tready => rx_axis_mac_tready_int,
mac_rx_tlast => rx_axis_mac_tlast_int);
i2c_module: i2c_top
port map( clk_in => clk_200,
phy_rstn_out => phy_rstn_out);
configuration_logic: config_logic
Port map(
clk125 => userclk2,
clk200 => clk_200,
clk_in => clk_40,
reset => reset,
user_data_in => udp_rx_int.data.data_in,
user_data_out => conf_data_out_i,
udp_rx => udp_rx_int,
resp_data => udp_response_int,
send_error => send_error_int,
user_conf => user_conf_i,
user_wr_en => udp_rx_int.data.data_in_valid,
user_last => udp_rx_int.data.data_in_last,
configuring => '0', --configuring_i,
we_conf => open, --we_conf_int,
conf_packet_length => conf_packet_length_int,
vmm_id => vmm_id,
cfg_bit_out => conf_di_i,
status => status_int,
start_vmm_conf => conf_wen_i, --start_conf_proc_int, --configuring_i,
conf_done => conf_done_int,
ext_trigger => trig_mode_int,
ACQ_sync => ACQ_sync_int,
udp_header => udp_header_int,
vmm_cktk => conf_cktk_out_i,
packet_length => udp_rx_int.hdr.data_length);
clk_200_to_400_inst: clk_wiz_200_to_400
port map(
clk_in1_p => X_2V5_DIFF_CLK_P,
clk_in1_n => X_2V5_DIFF_CLK_N,
clk_out_400 => clk_400_noclean
);
clk_400_low_jitter_inst: clk_wiz_low_jitter
port map(
clk_in1 => clk_400_noclean,
clk_out1 => clk_400_clean
);
clk_user_inst: clk_wiz_0
port map(
clk_in1 => clk_400_clean,
reset => '0',
clk_200_o => clk_200,
clk_800_o => clk_800,
clk_10_phase45_o => clk_10_phase45,
clk_50_o => clk_50,
clk_40_o => clk_40,
clk_10_o => clk_10
);
vmm_global_reset_inst: vmm_global_reset
port map(
clk => clk_200, -- main clock
rst => reset, -- reset
gbl_rst => gbl_rst, -- input
vmm_ena => vmm_ena_gbl_rst, --
vmm_wen => vmm_wen_gbl_rst --
);
event_timing_reset_instance: event_timing_reset
port map(
hp_clk => clk_800,
bc_clk => clk_10,
trigger => tr_out_i,
readout_done => '0',
reset => '0',
bcid => open,
prec_cnt => open,
vmm_ena => open,
vmm_wen => open
);
readout_vmm: vmm_readout
port map(
vmm_data0 => vmm_data0_5,
vmm_data1 => vmm_data1_5,
clk_10_phase45 => clk_10_phase45,
clk_50 => clk_50,
clk_200 => clk_200,
daq_enable => daq_enable_i,
trigger_pulse => pf_trigVmmRo,
ethernet_fifo_wr_en => open,
latency => ACQ_sync_int,
vmm_ckdt => ckdt_out_vec(5),
vmm_cktk => ro_cktk_5,
acq_rst_from_data0 => open,
vmm_data_buf => open,
vmm_wen => ro_vmm_wen_5,
vmm_ena => ro_vmm_ena_5,
vmmWordReady => vmmWordReady_i,
vmmWord => vmmWord_i,
vmmEventDone => vmmEventDone_i
);
trigger_instance: trigger
port map(
clk_200 => clk_200,
tren => tren, -- Trigger module enabled
tr_hold => tr_hold, -- Prevents trigger while high
trmode => trig_mode_int, -- Mode 0: internal / Mode 1: external
trext => ext_trigger_in, -- External trigger is to be driven to this port
trint => trint, -- Internal trigger is to be driven to this port (CKTP)
reset => tr_reset,
event_counter => event_counter_i,
tr_out => tr_out_i
);
pf_newCycle <= tr_out_i;
select_vmm_block: select_vmm
Port map (
clk_in => clk_200,
vmm_id => vmm_id_int,
conf_di => conf_di_i,
conf_di_vec => vmm_di_vec_i,
conf_do => conf_do_i,
conf_do_vec => vmm_do_vec_i,
cktk_out => cktk_out_i,
cktk_out_vec => cktk_out_vec_i,
conf_wen => vmm_wen_i,
conf_wen_vec => vmm_wen_vec,
conf_ena => vmm_ena_i,
conf_ena_vec => vmm_ena_vec
);
FIFO2UDP_instance: FIFO2UDP
Port map(
clk_200 => clk_200,
clk_125 => userclk2,
daq_data_in => daqFIFO_din_i,
fifo_data_out => fifo_data_out_int,
udp_txi => udp_txi_int,
udp_tx_start => udp_tx_start_int,
control => control.ip_controls.arp_controls.clear_cache,
re_out => re_out_int,
udp_tx_data_out_ready => udp_tx_data_out_ready_int,
wr_en => daqFIFO_wr_en_i,
end_packet => end_packet_i,
global_reset => glbl_rst_i,
packet_length_in => packet_length_int,
reset_DAQ_FIFO => daqFIFO_reset,
sending_o => udp_busy
);
packet_formation_instance: packet_formation
port map(
clk_200 => clk_200,
newCycle => pf_newCycle,
eventCounter => event_counter_i,
trigVmmRo => pf_trigVmmRo,
vmmWord => vmmWord_i,
vmmWordReady => vmmWordReady_i,
vmmEventDone => vmmEventDone_i,
packLen => pf_packLen,
dataout => daq_data_out_i,
wrenable => daq_wr_en_i,
end_packet => end_packet_daq_int,
udp_busy => udp_busy,
tr_hold => tr_hold
);
data_selection: select_data
port map(
clk_in => clk_200,
configuring => start_conf_proc_int,
data_acq => daq_vmm_ena_enable,
we_data => daq_wr_en_i,
we_conf => we_conf_int,
daq_data_in => daq_data_out_i,
conf_data_in => user_data_out_i,
data_packet_length => pf_packLen,
conf_packet_length => conf_packet_length_int,
data_out => daqFIFO_din_i,
packet_length => packet_length_int,
end_packet_conf => end_packet_conf_int,
end_packet_daq => end_packet_daq_int,
we => daqFIFO_wr_en_i,
end_packet => end_packet_i
);
----------------------------------------------------SET ENA--------------------------------------------------------------
vmm_ena_i <= conf_ena_i or (ro_vmm_ena_5 and daq_vmm_ena_enable);
ena_diff_1 : OBUFDS port map ( O => ENA_1_P, OB => ENA_1_N, I => vmm_ena_vec(1));
ena_diff_2 : OBUFDS port map ( O => ENA_2_P, OB => ENA_2_N, I => vmm_ena_vec(2));
ena_diff_3 : OBUFDS port map ( O => ENA_3_P, OB => ENA_3_N, I => vmm_ena_vec(3));
ena_diff_4 : OBUFDS port map ( O => ENA_4_P, OB => ENA_4_N, I => vmm_ena_vec(4));
ena_diff_5 : OBUFDS port map ( O => ENA_5_P, OB => ENA_5_N, I => vmm_ena_vec(5));
ena_diff_6 : OBUFDS port map ( O => ENA_6_P, OB => ENA_6_N, I => vmm_ena_vec(6));
ena_diff_7 : OBUFDS port map ( O => ENA_7_P, OB => ENA_7_N, I => vmm_ena_vec(7));
ena_diff_8 : OBUFDS port map ( O => ENA_8_P, OB => ENA_8_N, I => vmm_ena_vec(8));
----------------------------------------------------SET WEN--------------------------------------------------------------
vmm_wen_i <= conf_wen_i or (ro_vmm_wen_5 and daq_vmm_wen_enable);
wen_diff_1 : OBUFDS port map ( O => WEN_1_P, OB => WEN_1_N, I => vmm_wen_vec(1));
wen_diff_2 : OBUFDS port map ( O => WEN_2_P, OB => WEN_2_N, I => vmm_wen_vec(2));
wen_diff_3 : OBUFDS port map ( O => WEN_3_P, OB => WEN_3_N, I => vmm_wen_vec(3));
wen_diff_4 : OBUFDS port map ( O => WEN_4_P, OB => WEN_4_N, I => vmm_wen_vec(4));
wen_diff_5 : OBUFDS port map ( O => WEN_5_P, OB => WEN_5_N, I => vmm_wen_vec(5));
wen_diff_6 : OBUFDS port map ( O => WEN_6_P, OB => WEN_6_N, I => vmm_wen_vec(6));
wen_diff_7 : OBUFDS port map ( O => WEN_7_P, OB => WEN_7_N, I => vmm_wen_vec(7));
wen_diff_8 : OBUFDS port map ( O => WEN_8_P, OB => WEN_8_N, I => vmm_wen_vec(8));
----------------------------------------------------SET DI--------------------------------------------------------------
di_diff_1 : OBUFDS port map ( O => DI_1_P, OB => DI_1_N, I => vmm_di_vec_i(1));
di_diff_2 : OBUFDS port map ( O => DI_2_P, OB => DI_2_N, I => vmm_di_vec_i(2));
di_diff_3 : OBUFDS port map ( O => DI_3_P, OB => DI_3_N, I => vmm_di_vec_i(3));
di_diff_4 : OBUFDS port map ( O => DI_4_P, OB => DI_4_N, I => vmm_di_vec_i(4));
di_diff_5 : OBUFDS port map ( O => DI_5_P, OB => DI_5_N, I => vmm_di_vec_i(5));
di_diff_6 : OBUFDS port map ( O => DI_6_P, OB => DI_6_N, I => vmm_di_vec_i(6));
di_diff_7 : OBUFDS port map ( O => DI_7_P, OB => DI_7_N, I => vmm_di_vec_i(7));
di_diff_8 : OBUFDS port map ( O => DI_8_P, OB => DI_8_N, I => vmm_di_vec_i(8));
----------------------------------------------------SET CKBC--------------------------------------------------------------
vmm_ckbc <= clk_10;
ckbc_diff_1 : OBUFDS port map ( O => CKBC_1_P, OB => CKBC_1_N, I => vmm_ckbc);
ckbc_diff_2 : OBUFDS port map ( O => CKBC_2_P, OB => CKBC_2_N, I => vmm_ckbc);
ckbc_diff_3 : OBUFDS port map ( O => CKBC_3_P, OB => CKBC_3_N, I => vmm_ckbc);
ckbc_diff_4 : OBUFDS port map ( O => CKBC_4_P, OB => CKBC_4_N, I => vmm_ckbc);
ckbc_diff_5 : OBUFDS port map ( O => CKBC_5_P, OB => CKBC_5_N, I => vmm_ckbc);
ckbc_diff_6 : OBUFDS port map ( O => CKBC_6_P, OB => CKBC_6_N, I => vmm_ckbc);
ckbc_diff_7 : OBUFDS port map ( O => CKBC_7_P, OB => CKBC_7_N, I => vmm_ckbc);
ckbc_diff_8 : OBUFDS port map ( O => CKBC_8_P, OB => CKBC_8_N, I => vmm_ckbc);
----------------------------------------------------SET CKTK--------------------------------------------------------------
cktk_out_i <= conf_cktk_out_i or ro_cktk_5;
cktk_diff_1 : OBUFDS port map ( O => CKTK_1_P, OB => CKTK_1_N, I => cktk_out_vec_i(1));
cktk_diff_2 : OBUFDS port map ( O => CKTK_2_P, OB => CKTK_2_N, I => cktk_out_vec_i(2));
cktk_diff_3 : OBUFDS port map ( O => CKTK_3_P, OB => CKTK_3_N, I => cktk_out_vec_i(3));
cktk_diff_4 : OBUFDS port map ( O => CKTK_4_P, OB => CKTK_4_N, I => cktk_out_vec_i(4));
cktk_diff_5 : OBUFDS port map ( O => CKTK_5_P, OB => CKTK_5_N, I => cktk_out_vec_i(5));
cktk_diff_6 : OBUFDS port map ( O => CKTK_6_P, OB => CKTK_6_N, I => cktk_out_vec_i(6));
cktk_diff_7 : OBUFDS port map ( O => CKTK_7_P, OB => CKTK_7_N, I => cktk_out_vec_i(7));
cktk_diff_8 : OBUFDS port map ( O => CKTK_8_P, OB => CKTK_8_N, I => cktk_out_vec_i(8));
----------------------------------------------------SET CKTP--------------------------------------------------------------
cktp_diff_1 : OBUFDS port map ( O => CKTP_1_P, OB => CKTP_1_N, I => vmm_cktp);
cktp_diff_2 : OBUFDS port map ( O => CKTP_2_P, OB => CKTP_2_N, I => vmm_cktp);
cktp_diff_3 : OBUFDS port map ( O => CKTP_3_P, OB => CKTP_3_N, I => vmm_cktp);
cktp_diff_4 : OBUFDS port map ( O => CKTP_4_P, OB => CKTP_4_N, I => vmm_cktp);
cktp_diff_5 : OBUFDS port map ( O => CKTP_5_P, OB => CKTP_5_N, I => vmm_cktp);
cktp_diff_6 : OBUFDS port map ( O => CKTP_6_P, OB => CKTP_6_N, I => vmm_cktp);
cktp_diff_7 : OBUFDS port map ( O => CKTP_7_P, OB => CKTP_7_N, I => vmm_cktp);
cktp_diff_8 : OBUFDS port map ( O => CKTP_8_P, OB => CKTP_8_N, I => vmm_cktp);
----------------------------------------------------SET CKDT--------------------------------------------------------------
ckdt_diff_1 : OBUFDS port map ( O => ckdt_1_P, OB => ckdt_1_N, I => ckdt_out_vec(1));
ckdt_diff_2 : OBUFDS port map ( O => ckdt_2_P, OB => ckdt_2_N, I => ckdt_out_vec(2));
ckdt_diff_3 : OBUFDS port map ( O => ckdt_3_P, OB => ckdt_3_N, I => ckdt_out_vec(3));
ckdt_diff_4 : OBUFDS port map ( O => ckdt_4_P, OB => ckdt_4_N, I => ckdt_out_vec(4));
ckdt_diff_5 : OBUFDS port map ( O => ckdt_5_P, OB => ckdt_5_N, I => ckdt_out_vec(5));
ckdt_diff_6 : OBUFDS port map ( O => ckdt_6_P, OB => ckdt_6_N, I => ckdt_out_vec(6));
ckdt_diff_7 : OBUFDS port map ( O => ckdt_7_P, OB => ckdt_7_N, I => ckdt_out_vec(7));
ckdt_diff_8 : OBUFDS port map ( O => ckdt_8_P, OB => ckdt_8_N, I => ckdt_out_vec(8));
----------------------------------------------------DO--------------------------------------------------------------
do_diff_1 : IBUFDS port map ( O => vmm_do_1, I => DO_1_P, IB => DO_1_N);
do_diff_2 : IBUFDS port map ( O => vmm_do_2, I => DO_2_P, IB => DO_2_N);
do_diff_3 : IBUFDS port map ( O => vmm_do_3, I => DO_3_P, IB => DO_3_N);
do_diff_4 : IBUFDS port map ( O => vmm_do_4, I => DO_4_P, IB => DO_4_N);
do_diff_5 : IBUFDS port map ( O => vmm_do_5, I => DO_5_P, IB => DO_5_N);
do_diff_6 : IBUFDS port map ( O => vmm_do_6, I => DO_6_P, IB => DO_6_N);
do_diff_7 : IBUFDS port map ( O => vmm_do_7, I => DO_7_P, IB => DO_7_N);
do_diff_8 : IBUFDS port map ( O => vmm_do_8, I => DO_8_P, IB => DO_8_N);
----------------------------------------------------DATA 0--------------------------------------------------------------
data0_diff_1 : IBUFDS port map ( O => vmm_data0_1, I => DATA0_1_P, IB => DATA0_1_N);
data0_diff_2 : IBUFDS port map ( O => vmm_data0_2, I => DATA0_2_P, IB => DATA0_2_N);
data0_diff_3 : IBUFDS port map ( O => vmm_data0_3, I => DATA0_3_P, IB => DATA0_3_N);
data0_diff_4 : IBUFDS port map ( O => vmm_data0_4, I => DATA0_4_P, IB => DATA0_4_N);
data0_diff_5 : IBUFDS port map ( O => vmm_data0_5, I => DATA0_5_P, IB => DATA0_5_N);
data0_diff_6 : IBUFDS port map ( O => vmm_data0_6, I => DATA0_6_P, IB => DATA0_6_N);
data0_diff_7 : IBUFDS port map ( O => vmm_data0_7, I => DATA0_7_P, IB => DATA0_7_N);
data0_diff_8 : IBUFDS port map ( O => vmm_data0_8, I => DATA0_8_P, IB => DATA0_8_N);
----------------------------------------------------DATA 1--------------------------------------------------------------
data1_diff_1 : IBUFDS port map ( O => vmm_data1_1, I => DATA1_1_P, IB => DATA1_1_N);
data1_diff_2 : IBUFDS port map ( O => vmm_data1_2, I => DATA1_2_P, IB => DATA1_2_N);
data1_diff_3 : IBUFDS port map ( O => vmm_data1_3, I => DATA1_3_P, IB => DATA1_3_N);
data1_diff_4 : IBUFDS port map ( O => vmm_data1_4, I => DATA1_4_P, IB => DATA1_4_N);
data1_diff_5 : IBUFDS port map ( O => vmm_data1_5, I => DATA1_5_P, IB => DATA1_5_N);
data1_diff_6 : IBUFDS port map ( O => vmm_data1_6, I => DATA1_6_P, IB => DATA1_6_N);
data1_diff_7 : IBUFDS port map ( O => vmm_data1_7, I => DATA1_7_P, IB => DATA1_7_N);
data1_diff_8 : IBUFDS port map ( O => vmm_data1_8, I => DATA1_8_P, IB => DATA1_8_N);
---------------------------------------------------TRIGGERS--------------------------------------------------------------
ext_trigger : IBUFDS port map ( O => ext_trigger_in, I => EXT_TRIGGER_P, IB => EXT_TRIGGER_N);
-------------------------------------------------------------------
-- Processes --
-------------------------------------------------------------------
-- 1. internalTrigger_proc
-- 2. testPulse_proc
-- 3. synced_to_200
-- 4. FPGA_global_reset
-- 5. flow_fsm
-------------------------------------------------------------------
internalTrigger_proc: process(clk_10_phase45) -- 10MHz/#states.
begin
if rising_edge(clk_10_phase45) then
if state = DAQ and trig_mode_int = '0' then
case internalTrigger_state is
when 0 to 9979 =>
internalTrigger_state <= internalTrigger_state + 1;
trint <= '0';
when 9980 to 10000 =>
internalTrigger_state <= internalTrigger_state + 1;
trint <= '1';
when others =>
internalTrigger_state <= 0;
end case;
else
trint <= '0';
end if;
end if;
end process;
testPulse_proc: process(clk_10_phase45) -- 10MHz/#states.
begin
if rising_edge(clk_10_phase45) then
if state = DAQ and trig_mode_int = '0' then
case cktp_state is
when 0 to 9979 =>
cktp_state <= cktp_state + 1;
vmm_cktp <= '0';
when 9980 to 10000 =>
cktp_state <= cktp_state + 1;
vmm_cktp <= '1';
when others =>
cktp_state <= 0;
end case;
else
vmm_cktp <= '0';
end if;
end if;
end process;
synced_to_200: process(clk_200)
begin
if rising_edge(clk_200) then
status_int_old <= status_int;
if status_int_old = status_int then
status_int_synced <= status_int_old;
end if;
vmm_id_old <= vmm_id;
if vmm_id_old = vmm_id then
vmm_id_synced <= vmm_id_old;
end if;
conf_done_int_synced <= conf_done_int;
end if;
end process;
FPGA_global_reset: process(clk_200, status_int_synced)
begin
if rising_edge(clk_200) then
if status_int_synced = "0011" then
glbl_rst_i <= '1';
else
glbl_rst_i <= '0';
end if;
end if;
end process;
flow_fsm: process(clk_200, counter, status_int, status_int_synced, state, vmm_id, write_done_i, conf_done_i, reading_i)
begin
if rising_edge(clk_200) then
if glbl_rst_i = '1' then
state <= IDLE;
elsif is_state = "0000" then
state <= IDLE;
else
case state is
when IDLE =>
is_state <= "1111";
configuring_i <= '0';
daq_vmm_ena_enable <= '0';
daq_vmm_wen_enable <= '0';
daqFIFO_reset <= '0';
tren <= '0';
conf_wen_i <= '0';
conf_ena_i <= '0';
we_conf_int <= '0';
end_packet_conf_int <= '0';
start_conf_proc_int <= '0';
if status_int_synced = "0010" then
cnt_vmm <= 8;
vmm_id_int <= std_logic_vector(to_unsigned(cnt_vmm, vmm_id_int'length));
state <= CONFIGURE;
elsif status_int_synced = "0001" then
cnt_vmm <= 1;
vmm_id_int <= vmm_id_synced;
state <= CONFIGURE;
elsif status_int_synced = "1111" then
state <= DAQ_INIT;
end if;
when CONFIGURE =>
is_state <= "0001";
if status_int_synced = "1011" then
state <= CONF_DONE;
end if;
configuring_i <= '1';
conf_wen_i <= '1';
start_conf_proc_int <= '1';
when CONF_DONE =>
is_state <= "0010";
if w = 40 then
cnt_vmm <= cnt_vmm - 1;
if cnt_vmm = 1 then --1 VMM conf done
state <= SEND_CONF_REPLY;
we_conf_int <= '1';
else
state <= CONFIGURE after 100ns;
end if;
w <= 0;
else
w <= w + 1;
end if;
conf_wen_i <= '0';
when SEND_CONF_REPLY =>
is_state <= "1010";
if cnt_reply = 0 then
user_data_out_i <= conf_data_out_i;
cnt_reply <= cnt_reply + 1;
elsif cnt_reply = 1 then
user_data_out_i <= (others => '0');
cnt_reply <= cnt_reply + 1;
end_packet_conf_int <= '1';
we_conf_int <= '0';
elsif cnt_reply > 1 and cnt_reply < 100 then
cnt_reply <= cnt_reply + 1;
else
cnt_reply <= 0;
state <= IDLE;
end_packet_conf_int <= '1';
end if;
when DAQ_INIT =>
is_state <= "0011";
tren <= '0';
daq_vmm_ena_enable <= '1';
daq_vmm_wen_enable <= '1';
daqFIFO_reset <= '1';
if status_int_synced = "0000" or status_int_synced = "1000" then
daq_vmm_ena_enable <= '0';
daq_vmm_wen_enable <= '0';
state <= IDLE;
else
state <= TRIG;
end if;
when TRIG =>
is_state <= "0100";
daqFIFO_reset <= '0';
tren <= '1';
daq_enable_i <= '1';
state <= DAQ;
when DAQ =>
is_state <= "0101";
if status_int_synced = "1000" then -- Reset came
daq_enable_i <= '0';
state <= DAQ_INIT;
end if;
when others =>
state <= IDLE;
is_state <= "0110";
end case;
end if;
end if;
end process;
test_data <= udp_rx_int.data.data_in;
test_valid <= udp_rx_int.data.data_in_valid;
test_last <= udp_rx_int.data.data_in_last;
test_data_out <= udp_txi_int.data.data_out;
test_valid_out <= udp_txi_int.data.data_out_valid;
test_last_out <= udp_txi_int.data.data_out_last;
fifo_data <= fifo_data_out_int;
re_out <= re_out_int;
end Behavioral; | gpl-3.0 | 617eb6207c0c29d79ffc22601041ca7a | 0.444548 | 3.738708 | false | false | false | false |
GustaMagik/RSA_Security_Token | VHDL_code/ver_B/RSA_Security_Token_USB_Version/Security_Token_Top_USB.vhd | 1 | 23,239 |
--Copyright 2017 Christoffer Mathiesen, Gustav Örtenberg
--Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
--
--1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
--
--2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the
--documentation and/or other materials provided with the distribution.
--
--3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this
--software without specific prior written permission.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS
--BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
--GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
--LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Library IEEE;
Use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_MISC.ALL;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;
Use IEEE.NUMERIC_STD.all;
Use IEEE.MATH_REAL."log2";
Use IEEE.MATH_REAL."ceil";
Use work.all;
-----------------------------------Top_Module---------------------------------------------
--This module house all submodules that make up the 'koddosa' which is a
--challenge-response system that takes signs messages of length 512 bits
--with a predefined RSA key. The messages are sent over USB UART and
--uses a simple communication protocol defined in USB_TOP
--
--The flow of the program is:
--PowerOn->Init->PIN->Input from PC->RSA-encryption->Signal data avalible to PC ->
--On keyboard press soft reset circuit (returns to INIT).
--If a wrong PIN is input MAX_TRIES times in a row the program freezes at a blank screen
------------------------------------------------------------------------------------------
Entity Security_Token_Top_USB is
Generic( --PIN settings
PIN_LENGTH : Integer := 4; --Variable length of PIN
PIN_PSWRD : STD_LOGIC_VECTOR := x"ABCD"; --PIN, should have the same amount of numbers as PIN_LENGTH indicates
MAX_TRIES : Integer := 3; --Number of tries. 3 means one initial and 2 retries
SHOW_PIN : boolean := false; --If true the characters will be printed on screen when in PIN state, if false '*' will appear
TIMEOUT_SECONDS: INTEGER := 5; --Amount of seconds the device waits for a message to sign after the PIN is put
--Encryption settings
KEY_LENGTH : Integer := 512; --Key length in bits. HAS to be 512 with current modules
EXPONENT : STD_LOGIC_VECTOR := x"b15f20094a5fbcd7605b23bb7dbe7d421556df00d266c649d019cfc87eae543f703f6870013851130d3a2ed993ef76a1c377a96b95fe326f7326a319bae5fe01"; --Exponent of the RSA
MODULO : STD_LOGIC_VECTOR := x"bb847f2d87e8030926eea2a0a3f89877e6f63c1e2f65f3791e9c85549f48863a1dcc9f8b477c36dfea2573c49fc59259efe83b9996d093b4be09666e904cb17f"; --Modulus of the RSA
R_C_VAL : STD_LOGIC_VECTOR := x"8F80651391C778113C509FDD5C205AE6648A94DBC225A1ECA53F149BCF135AFCAC7E47DF209AC030325E1904AD7D260E236CE56D6753F488E3E489D50A6C2B0E"; --R_C value
--R_C is calculated by the formula 2^(16*([Words into RSA_512] + 1) * 2) mod MODULO, in standard case 2^(1056) mod MODULO
--If you are going to use this in a real world scenario, please use self-generated keys
--String pointers
STRING_PTR_0 : unsigned := to_unsigned(0,6);
STRING_PTR_1 : unsigned := to_unsigned(10,6);
STRING_PTR_2 : unsigned := to_unsigned(21,6);
STRING_PTR_3 : unsigned := to_unsigned(38,6);
--USB settings
Frequency : integer := 100_000_000;
BAUD : integer := 115200
);
Port ( clk : in STD_LOGIC;
Hex_in : in STD_LOGIC_VECTOR(3 downto 0);
Hex_out : out STD_LOGIC_VECTOR (3 downto 0);
LCD_RS : out STD_LOGIC;
LCD_RW : out STD_LOGIC;
LCD_E : out STD_LOGIC;
LCD_DB : out STD_LOGIC_VECTOR (7 downto 0);
TXD : out STD_LOGIC;
RXD : in STD_LOGIC;
RESET : in STD_LOGIC
);
end Security_Token_Top_USB;
architecture USB_behav of Security_Token_Top_USB is
constant MemSize : integer := (KEY_LENGTH/8);
constant LCD_CLEAR : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant LCD_PRINT : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant LCD_CHANGE: STD_LOGIC_VECTOR (1 downto 0) := "10";
constant PASSWORD : STD_LOGIC_VECTOR (PIN_LENGTH * 4 - 1 downto 0) := PIN_PSWRD;
constant MEM_BUS_WIDTH : Integer := integer(ceil(log2(real(MemSize))));
constant RAM_MAX_ADDR: unsigned(MEM_BUS_WIDTH-1 downto 0) := (others => '1');
constant ROM_MAX_ADDR: unsigned(5 downto 0) := (others => '1');
constant RSA_E : STD_LOGIC_VECTOR(KEY_LENGTH-1 downto 0) := EXPONENT;
constant RSA_M : STD_LOGIC_VECTOR(KEY_LENGTH-1 downto 0) := MODULO;
constant RSA_R_C : STD_LOGIC_VECTOR(KEY_LENGTH-1 downto 0) := R_C_VAL;
type PRG_STATE is (INIT, PRINT_MSG_1, GET_INPUT, PIN, RSA_2, RSA, PRINT_MSG_2,PRINT_MSG_3);
type LCD_SELECT is (SELECT_ASCII, SELECT_ROM, SELECT_RAM);
Signal STATE : PRG_STATE := INIT;
Signal WRONG_PIN_COUNTER : unsigned(1 downto 0) := (others => '0'); --if max tries more than 3, change this vector
Signal In_data : STD_LOGIC_VECTOR(3 downto 0); --From Keyboard
signal In_data_e, LCD_INPUT, INPUT_ASCII : STD_LOGIC_VECTOR (7 downto 0) := x"00";
Signal RDY, DO_CMD, RDY_CMD, WRITE_BACK, PIN_CORRECT : STD_LOGIC := '0';
Signal flag, WE, Read_RAM, INPUT_LSB, no_print : STD_LOGIC := '0';
Signal ROM_ADDR : UNSIGNED (5 downto 0) := (others => '0');
Signal RAM_ADDR : UNSIGNED (MEM_BUS_WIDTH-1 downto 0) := (others => '0');
Signal ROM_DATA, RAM_DATA_IN, RAM_DATA_OUT, ASCII_ENCODED : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
Signal Input_counter : UNSIGNED (MEM_BUS_WIDTH-1 downto 0) := (others => '0');
Signal MODE_SELECT : STD_LOGIC_VECTOR (1 downto 0) := LCD_CLEAR;
Signal TMP_INPUT : STD_LOGIC_VECTOR (3 downto 0);
Signal RSA_RESET, RSA_DONE, RSA_WE : STD_LOGIC := '0';
Signal RSA_START_ADDR, RSA_MEM_ADDR : STD_LOGIC_VECTOR (MEM_BUS_WIDTH-1 downto 0) := (others => '0');
Signal RSA_MEM_DATA_IN, RSA_MEM_DATA_OUT : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal RSA_WORD : integer range 0 to 32 := 0;
signal RSA_byte : integer range 0 to 64 := 0;
Signal LCD_INPUT_SELECT : LCD_SELECT := SELECT_ROM;
Signal valid_in, start_in, valid_out : STD_LOGIC;
Signal x, y, m, r_c, s : STD_LOGIC_VECTOR(15 downto 0);
component Keyboard
Port ( Row_Input : in STD_LOGIC_VECTOR (3 downto 0);
Col_Input_A : out STD_LOGIC_VECTOR (3 downto 0) := (others => '1');
Output : out STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
RDY : out STD_LOGIC := '0';
CLK : in STD_LOGIC;
RESET : in STD_LOGIC
);
end component;
component byte_to_six_bit_splitter
Port ( DATA_IN : in STD_LOGIC_VECTOR (7 downto 0);
DATA_OUT : out STD_LOGIC_VECTOR (5 downto 0);
INC_ADDR : out STD_LOGIC;
ACTIVE : in STD_LOGIC;
CLK : in STD_LOGIC;
RESET : in STD_LOGIC
);
end component;
component LCD
Generic (Frequency: integer := Frequency);
Port ( INPUT : in STD_LOGIC_VECTOR (7 downto 0); --ASCII IN
CLK : in STD_LOGIC; --FPGA Clock (100MHz)
RESET : in STD_LOGIC; --RESET
DATA_BUS : out STD_LOGIC_VECTOR (7 downto 0); --DB 7 downto DB 0
RW : out STD_LOGIC := '0'; --RW signal (unused as of now)
RS : out STD_LOGIC; --RS signal
E : out STD_LOGIC; --E (200Hz)
MODE_SELECT : in STD_LOGIC_VECTOR (1 downto 0); --SELECT WHAT THE SCREEN IS TO DO
RDY_CMD : out STD_LOGIC := '0'; --Tell ouside world that the ready for the command
DO_CMD : in STD_LOGIC); --Outside world tell module to do the current command
end component;
component USB_TOP is
generic ( data_addr_width : integer := MEM_BUS_WIDTH;
BAUD_RATE : integer := BAUD;
CLOCK_RATE : integer := Frequency;
OVERSAMPLES : integer := 4);
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
TXD : out STD_LOGIC;
RXD : in STD_LOGIC;
RAM_ADDR : out STD_LOGIC_VECTOR (data_addr_width-1 downto 0);
RAM_DATA_IN : in STD_LOGIC_VECTOR (7 downto 0);
RAM_DATA_OUT : out STD_LOGIC_VECTOR (7 downto 0);
RAM_WE : out STD_LOGIC;
READY_FOR_DATA : in STD_LOGIC;
RSA_DONE : in STD_LOGIC;
DATA_READY : out STD_LOGIC);
end component;
component ascii_encoder is
Port(input : in STD_LOGIC_VECTOR (7 downto 0);
output : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component mem_array is
GENERIC(
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := MEM_BUS_WIDTH);
Port(
ADDR : in STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
DATAIN : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
clk : in std_logic;
WE : in std_logic;
OUTPUT : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0)
);
end component;
component mem_array_ROM is
GENERIC(
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 6);
Port(
ADDR : in STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
OUTPUT : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0)
);
end component;
component RSA_top is
port(
clk : in std_logic;
reset : in std_logic;
valid_in : in std_logic;
start_in : in std_logic;
x : in std_logic_vector(15 downto 0); -- estos 3 son x^y mod m
y : in std_logic_vector(15 downto 0);
m : in std_logic_vector(15 downto 0);
r_c : in std_logic_vector(15 downto 0); --constante de montgomery r^2 mod m
s : out std_logic_vector(15 downto 0);
valid_out : out std_logic;
bit_size : in std_logic_vector(15 downto 0) --tamano bit del exponente y (log2(y))
);
end component;
signal RAM_DATA_IN_USB, RAM_DATA_OUT_USB : STD_LOGIC_VECTOR(7 downto 0);
signal RAM_ADDR_USB : STD_LOGIC_VECTOR(MEM_BUS_WIDTH-1 downto 0);
signal RAM_WE_USB, READY_FOR_DATA, DATA_READY: STD_LOGIC;
signal RSA_X : STD_LOGIC_VECTOR (511 downto 0);
signal RESETN, soft_reset : STD_LOGIC;
signal timeout_timer : integer := 0;
--signal clk, tog : std_logic;
begin
ASCII: ascii_encoder port map (
input => INPUT_ASCII,
output => ASCII_ENCODED
);
USB: USB_TOP Port map (
CLK => clk,
RESET => RESETN,
TXD => TXD,
RXD => RXD,
RAM_ADDR => RAM_ADDR_USB,
RAM_DATA_IN => RAM_DATA_OUT,
RAM_DATA_OUT => RAM_DATA_OUT_USB,
RAM_WE => RAM_WE_USB,
DATA_READY => DATA_READY,
READY_FOR_DATA => READY_FOR_DATA,
RSA_DONE => RSA_DONE);
RSA_MODULE: RSA_top port map(
clk => clk,
reset => RESETN,
valid_in => valid_in,
start_in => start_in,
x => x, -- estos 3 son x^y mod m
y => y,
m => m,
r_c => r_c, --constante de montgomery r^2 mod m
s => s,
valid_out => valid_out,
bit_size => x"0200" --512 --tamano bit del exponente y (log2(y))
);
SCREEN: LCD port map (
INPUT => LCD_INPUT,
CLK => clk,
RESET => RESETN,
DATA_BUS => LCD_DB,
RW => LCD_RW,
RS => LCD_RS,
E => LCD_E,
MODE_SELECT => MODE_SELECT,
RDY_CMD => RDY_CMD,
DO_CMD => DO_CMD
);
KBD : Keyboard port map (
Row_Input => Hex_in,
Col_Input_A => Hex_out,
Output => In_data,
RDY => RDY,
CLK => clk,
RESET => RESETN
);
ROM:
mem_array_ROM port map(
ADDR => STD_LOGIC_VECTOR(ROM_ADDR),
OUTPUT => ROM_DATA
);
RAM:
mem_array port map(
ADDR => STD_LOGIC_VECTOR(RAM_ADDR),
DATAIN => RAM_DATA_IN,
clk => clk,
WE => WE,
OUTPUT => RAM_DATA_OUT);
INPUT_ASCII <= "0000" & IN_DATA;
with STATE select
RAM_DATA_IN <=
RAM_DATA_OUT_USB when GET_INPUT,
RSA_MEM_DATA_IN when RSA,
RAM_DATA_OUT_USB when others;
with STATE select
RAM_ADDR <=
unsigned(RAM_ADDR_USB) when GET_INPUT,
unsigned(RSA_MEM_ADDR) when RSA, --Give the RSA access to the memory when it needs it
unsigned(RAM_ADDR_USB) when others; --Otherwise make the USB able to use it
with STATE select
WE <=
RAM_WE_USB when GET_INPUT,
RSA_WE when RSA,
RAM_WE_USB when others;
LCD_INPUT <= ROM_DATA when LCD_INPUT_SELECT = SELECT_ROM else --LCD gets data from ROM
RAM_DATA_OUT when LCD_INPUT_SELECT = SELECT_RAM else --LCD gets data from RAM
ASCII_ENCODED when (LCD_INPUT_SELECT = SELECT_ASCII AND SHOW_PIN) else -- LCD gets data from keyboard and shows the characters (show PIN)
x"2A" when (LCD_INPUT_SELECT = SELECT_ASCII AND NOT SHOW_PIN) else --LCD only prints '*' when otherwise it would read from keyboard (NOT show PIN)
ROM_DATA;
RESETN <= NOT RESET or soft_reset; --Invert the reset signal as the input is low when the button is pressed
--State changes
process(clk)
begin
if rising_edge(clk) then --synchronous reset
if RESETN = '1' then
STATE <= INIT;
flag <= '0';
ROM_ADDR <= (others => '0');
LCD_INPUT_SELECT <= SELECT_ROM;
valid_in <= '0';
start_in <= '0';
DO_CMD <= '0';
Input_counter <= (others => '0');
--WRONG_PIN_COUNTER <= (others => '0'); --Uncomment if debug
PIN_CORRECT <= '0';
READY_FOR_DATA <= '0';
RSA_DONE <= '0';
RSA_X <= (others => '0');
RSA_MEM_ADDR <= (others => '0');
RSA_BYTE <= 0;
RSA_WORD <= 0;
RSA_MEM_DATA_IN <= (others => '0');
x <= (others => '0');
y <= (others => '0');
m <= (others => '0');
r_c <= (others => '0');
READY_FOR_DATA <= '0';
soft_reset <= '0';
timeout_timer <= 0;
else
--If we are telling the screen to do a command and RDY_CMD goes to 0
--it means that the screen is working on it. Thus we should stop
--telling the screen to do commands.
if RDY_CMD = '0' and DO_CMD = '1' then
DO_CMD <= '0';
else
--reset <= '0';
case STATE is
------------------------------------------------------------------------------
when INIT =>
soft_reset <= '0';
if RDY_CMD = '1' and DO_CMD = '0' then --Wait for the LCD to be ready
MODE_SELECT <= LCD_CLEAR;
DO_CMD <= '1'; --Clear the screen
STATE <= PIN; --if PIN is unwanted, change this to Print_MSG_1
ROM_ADDR <= STRING_PTR_0 - 1;
--RESET <= '1';
flag <= '0';
end if;
------------------------------------------------------------------------------
when PIN =>
--RESET <= '0';
if flag = '0' then --If in print mode
if RDY_CMD = '1' and DO_CMD = '0' then --If the screen is ready for a command
LCD_INPUT_SELECT <= SELECT_ROM; --Use characters from ROM
MODE_SELECT <= LCD_PRINT; --Set the screen in print mode
DO_CMD <= '1'; --Execute the command
if ROM_DATA = x"00" and ROM_ADDR /= STRING_PTR_0 - 1 then --char is '\0' (and not the last rom addr)
MODE_SELECT <= LCD_CHANGE; --Set screen in change row mode
Input_counter <= to_unsigned(PIN_LENGTH, MEM_BUS_WIDTH); --Set the input counter to the PIN length
-- RAM_ADDR <= (others => '0');
PIN_CORRECT <= '1'; --Assume correct pin
flag <= '1'; --Insert PIN mode
else
ROM_ADDR <= ROM_ADDR + 1; --Inc the ROM ptr while printing
end if;
end if;
elsif RDY_CMD = '1' and DO_CMD = '0' then --If the screen is ready for a character
LCD_INPUT_SELECT <= SELECT_ASCII;
if Input_counter = 0 and PIN_CORRECT = '1' then --if the entire PIN is put and it was correct
MODE_SELECT <= LCD_CLEAR; --Clear the screen
flag <= '0'; --reset this flag
DO_CMD <= '1'; --Do the command
STATE <= PRINT_MSG_1; --move on to next part of program
ROM_ADDR <= STRING_PTR_2 - 1; --set the pointer for next part of program
WRONG_PIN_COUNTER <= (others => '0'); --Reset the amount of incorrect tries
elsif Input_counter = 0 and PIN_CORRECT = '0' then --If entire PIN is put and it was incorrect
MODE_SELECT <= LCD_CLEAR; --Clear the screen
STATE <= PRINT_MSG_3; --
ROM_ADDR <= STRING_PTR_1 - 1;
DO_CMD <= '1';
WRONG_PIN_COUNTER <= WRONG_PIN_COUNTER + 1; --Inc the counter
flag <= '0'; --reset the flag
elsif RDY = '1' then --if a character was input from the keyboard
MODE_SELECT <= LCD_PRINT;
DO_CMD <= '1';
if PASSWORD(to_integer(input_counter * 4 - 1) downto to_integer(input_counter * 4 - 4)) /= In_data then -- if the current number was wrong the entire pin is wrong
PIN_CORRECT <= '0'; --set to incorrect pin
end if;
Input_counter <= Input_counter - 1; --dec the counter
end if;
end if;
---------------------------------------------------------------------
when PRINT_MSG_3 =>
if WRONG_PIN_COUNTER < MAX_TRIES then
if RDY_CMD = '1' and DO_CMD = '0' then
LCD_INPUT_SELECT <= SELECT_ROM;
MODE_SELECT <= LCD_PRINT;
DO_CMD <= '1';
if ROM_DATA /= x"00" or ROM_ADDR = STRING_PTR_1 - 1 then --char is not '\0', continue printing
ROM_ADDR <= ROM_ADDR + 1;
elsif RDY = '1' then
MODE_SELECT <= LCD_CLEAR;
STATE <= INIT;
Input_counter <= (others => '0');
-- RAM_ADDR <= (others => '0');
else
DO_CMD <= '0';
end if;
end if;
end if;
------------------------------------------------------------------------------
when PRINT_MSG_1 =>
if RDY_CMD = '1' and DO_CMD = '0' then
LCD_INPUT_SELECT <= SELECT_ROM;
MODE_SELECT <= LCD_PRINT;
DO_CMD <= '1';
if ROM_DATA /= x"00" or ROM_ADDR = STRING_PTR_2 - 1 then --char is not '\0', continue printing
ROM_ADDR <= ROM_ADDR + 1;
else
MODE_SELECT <= LCD_CHANGE;
STATE <= GET_INPUT;
READY_FOR_DATA <= '1'; --Signal the USB-controller that we are ready for loading the RAM with data
Input_counter <= (others => '0');
-- RAM_ADDR <= (others => '0');
end if;
end if;
------------------------------------------------------------------------------
when GET_INPUT =>
READY_FOR_DATA <= '1'; --Signal the USB-controller that we are ready for loading the RAM with data
RSA_DONE <= '0'; --Signal the USB-controller that the RSA is NOT done
flag <= '1';
timeout_timer <= timeout_timer + 1;
if timeout_timer = timeout_seconds * frequency then
SOFT_RESET <= '1';
elsif DATA_READY = '1' and flag = '1' then --Data recieved. (and one cycle extra passed to let things catch up in a loop scenario)
STATE <= RSA; --Perform the RSA
READY_FOR_DATA <= '0';--And set so the USB can't write to the RAM anymore
RSA_MEM_ADDR <= (others => '0'); --reset the RSA_MEM_ADDR pointer
READY_FOR_DATA <= '0';
STATE <= RSA;
flag <= '0';
end if;
------------------------------------------------------------------------------
when RSA =>
--First prepare the data from memory to introduction into RSA_512
if flag = '0' then --if not in the writing stage
if RSA_BYTE < 64 then --Loading of the data
RSA_X(RSA_BYTE*8+7 downto RSA_BYTE*8) <= RAM_DATA_OUT;
RSA_MEM_ADDR <= RSA_MEM_ADDR + 1; --inc the pointer
RSA_BYTE <= RSA_BYTE + 1;
else
--RSA_X(RSA_BYTE*8+7 downto RSA_BYTE*8) <= RAM_DATA_OUT; --Last byte to be read
RSA_MEM_ADDR <= (others => '1'); --reset the pointer
end if;
end if;
if RSA_WORD = 32 then
valid_in <= '0';
end if;
if flag = '0' then --The loading of the RSA module
if RSA_MEM_ADDR < 31-8 then --preload the n_c value for the RSA init-sequence
m(15 downto 0) <= RSA_M(15 downto 0);
elsif RSA_MEM_ADDR = 31 - 8 then --Start the init-sequence when half-6 bytes are loaded to the register
start_in <= '1';
elsif RSA_MEM_ADDR <= 31 then --Set the flag low again and wait for 6 cycles
start_in <= '0';
elsif RSA_MEM_ADDR > 31 and RSA_WORD < 32 then --Start loading the RSA_512
x <= RSA_X(RSA_WORD*16+15 downto RSA_WORD*16); --Message value
y <= RSA_E(RSA_WORD*16+15 downto RSA_WORD*16); --Key value
m <= RSA_M(RSA_WORD*16+15 downto RSA_WORD*16); --Modulo value
r_c <= RSA_R_C(RSA_WORD*16+15 downto RSA_WORD*16); --R_C value
valid_in <= '1'; --Valid data in flag
RSA_WORD <= RSA_WORD + 1; --inc the pointer
if RSA_WORD = 31 then
--notihing
end if;
else
valid_in <= '0'; --No more data in
flag <= '1'; --set the mode to write back to memory
RSA_WORD <= 0; --reset the counter to 0
end if;
else --Writing to memory
if RSA_WORD < 32 AND valid_out = '1' then --if not the final byte from RSA_512 result (s)
RSA_X(RSA_WORD*16+15 downto RSA_WORD*16) <= s; --save it in the register
RSA_WORD <= RSA_WORD + 1; --inc the pointer
input_counter <= (others => '0');
RSA_MEM_ADDR <= (others => '1'); --Set this to max to overflow back to 0 and thus inserting the correct number in that cell
RSA_BYTE <= 0;
elsif RSA_WORD = 32 then --start writing back to RAM
if RSA_BYTE < 64 then --If we haven't written the entire result to memory
RSA_MEM_ADDR <= RSA_MEM_ADDR + 1; --increase the addr
RSA_MEM_DATA_IN <= RSA_X(RSA_BYTE*8+7 downto RSA_BYTE*8); --use the correct part of the result
RSA_WE <= '1'; --write it to memory
RSA_BYTE <= RSA_BYTE + 1; --increase the counter
else --everything written back
RSA_WE <= '0'; --stop writing
flag <= '0'; --reset this flag
RSA_DONE <= '1'; --The result is done and in memory. Tell USB-cmd so
STATE <= PRINT_MSG_2; --move on
RSA_BYTE <= 0;
RSA_WORD <= 0;
end if;
end if;
end if;
-----------------------------------------------------------------------------------------------------
when PRINT_MSG_2 =>
if RDY_CMD = '1' and DO_CMD = '0' then
MODE_SELECT <= LCD_PRINT;
DO_CMD <= '1';
LCD_INPUT_SELECT <= SELECT_ROM;
if ROM_DATA /= x"00" or ROM_ADDR = STRING_PTR_3 - 1 then --char is not '\0', continue printing
ROM_ADDR <= ROM_ADDR + 1;
else
DO_CMD <= '0';
if RDY = '1' then --wait for a press on the keyboard
Input_counter <= (others => '0');
soft_reset <= '1';
STATE <= INIT;
end if;
end if;
end if;
------------------------------------------------------------------------------
when others =>
--kill me
end case;
end if;
end if;
end if;
end process;
end USB_behav; | bsd-3-clause | 75d8d6bdd249b67c63e5fc0ee9948dd2 | 0.591506 | 3.232128 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/Scrambler/tb_scrambler.vhd | 1 | 3,129 | ----------------------------------------------------------------------------------------------------
-- Scrambler/Descramber Test-bench
----------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
----------------------------------------------------------------------------------------------------
-- ENTITY
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tb_clockgen_pkg.all;
use work.tb_write_csv_pkg.all;
use work.scrambler_pkg.all;
use work.descrambler_pkg.all;
--This module is a test-bench for simulating the LFSR
entity tb_lfsr is
end tb_lfsr;
----------------------------------------------------------------------------------------------------
-- ARCHITECTURE
----------------------------------------------------------------------------------------------------
architecture sim of tb_lfsr is
signal rst : std_logic;
signal clk : std_logic;
signal count_data : std_logic_vector(15 downto 0);
signal scrambled_data : std_logic_vector(15 downto 0);
signal unscrambled_data : std_logic_vector(15 downto 0);
constant polynomial : std_logic_vector(14 downto 0) := "110000000000000";
constant seed1 : std_logic_vector(14 downto 0) := "010101010101010";
constant seed2 : std_logic_vector(14 downto 0) := "100010100010100";
begin
--Instantiate clock generator
clk1 : tb_clockgen
generic map(PERIOD => 30ns,
DUTY_CYCLE => 0.50)
port map( clk => clk);
--count_process
counter: process(clk, rst)
variable counter : unsigned (15 downto 0) := (others => '0');
begin
if(rst = '1') then
counter := (others => '0');
else
if(rising_edge(clk)) then
counter := counter + 1;
end if;
end if;
count_data <= std_logic_vector(counter);
end process;
--UUT
count_scrambler : scrambler
port map( clk => clk,
rst => rst,
poly_mask => polynomial,
seed => seed1,
unscrambled_datain => count_data,
scrambled_dataout => scrambled_data);
count_descrambler : descrambler
port map( clk => clk,
rst => rst,
poly_mask => polynomial,
seed => seed2,
scrambled_datain => scrambled_data,
unscrambled_dataout => unscrambled_data);
writer: tb_write_csv
generic map(FILENAME => "scrambled_data.csv")
port map( clk => clk,
data => scrambled_data);
--Main Process
main: process
begin
rst <= '1';
wait for 50ns;
rst <= '0';
wait;
end process;
end sim;
| mit | d0610a3eed04788fd345729d076ccb32 | 0.422819 | 5.014423 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/Filter_Bank/decomposition.vhd | 1 | 2,653 | --------------------------------------------------------------------------------------------------
-- Signal Decomposition
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- PACKAGE
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.dsp_pkg.all;
package decomposition_pkg is
--FIR filter component declaration
component decomposition is
generic( low_pass : coefficient_array;
high_pass : coefficient_array);
port( clk_low : in std_logic;
clk_high : in std_logic;
rst : in std_logic;
x : in sig;
y_low : out sig;
y_high : out sig);
end component;
end package;
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.dsp_pkg.all;
use work.decimator_pkg.all;
entity decomposition is
generic( low_pass : coefficient_array;
high_pass : coefficient_array);
port( clk_low : in std_logic;
clk_high : in std_logic;
rst : in std_logic;
x : in sig;
y_low : out sig;
y_high : out sig);
end decomposition;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture behave of decomposition is
begin
--Decimate the signal using a low pass filter
low_filter_bank : decimator
generic map(h => low_pass)
port map( clk_high => clk_high,
clk_low => clk_low,
rst => rst,
sig_high => x,
sig_low => y_low);
--Decimate the signal using a high pass filter
high_filter_bank : decimator
generic map(h => high_pass)
port map( clk_high => clk_high,
clk_low => clk_low,
rst => rst,
sig_high => x,
sig_low => y_high);
end behave;
| mit | aae9aee30add7948445effc7466fd763 | 0.352431 | 5.403259 | false | false | false | false |
adelapie/noekeon | theta.vhd | 5 | 3,797 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity theta is
port(a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end theta;
architecture Behavioral of theta is
signal a_1_0_s : std_logic_vector(31 downto 0);
signal a_3_0_s : std_logic_vector(31 downto 0);
signal tmp_0_s : std_logic_vector(31 downto 0);
signal tmp_1_s : std_logic_vector(31 downto 0);
signal tmp_2_s : std_logic_vector(31 downto 0);
signal tmp_3_s : std_logic_vector(31 downto 0);
signal m_1_tmp_0_s : std_logic_vector(31 downto 0);
signal m_1_tmp_1_s : std_logic_vector(31 downto 0);
signal m_1_tmp_2_s : std_logic_vector(31 downto 0);
signal m_1_tmp_3_s : std_logic_vector(31 downto 0);
signal m_2_tmp_0_s : std_logic_vector(31 downto 0);
signal m_2_tmp_1_s : std_logic_vector(31 downto 0);
signal m_2_tmp_2_s : std_logic_vector(31 downto 0);
signal m_2_tmp_3_s : std_logic_vector(31 downto 0);
begin
--Theta(k,a){
-- temp = a[0]^a[2];
-- temp ^= temp>>>8 ^ temp<<<8;
-- a[1] ^= temp;
-- a[3] ^= temp;
-- a[0] ^= k[0];
-- a[1] ^= k[1];
-- a[2] ^= k[2];
-- a[3] ^= k[3];
-- temp = a[1]^a[3];
-- temp ^= temp>>>8 ^ temp<<<8;
-- a[0] ^= temp;
-- a[2] ^= temp;
--}
m_1_tmp_0_s <= a_0_in xor a_2_in; -- temp = a[0]^a[2];
m_1_tmp_1_s <= m_1_tmp_0_s(23 downto 0) & m_1_tmp_0_s(31 downto 24); -- temp>>>8
m_1_tmp_2_s <= m_1_tmp_0_s(7 downto 0) & m_1_tmp_0_s(31 downto 8); -- temp<<<8;
m_1_tmp_3_s <= m_1_tmp_0_s xor m_1_tmp_1_s xor m_1_tmp_2_s; -- temp ^= temp>>>8 ^ temp<<<8;
a_1_0_s <= a_1_in xor m_1_tmp_3_s; -- a[1] ^= temp;
a_3_0_s <= a_3_in xor m_1_tmp_3_s; -- a[3] ^= temp;
tmp_0_s <= a_0_in xor k_0_in; -- a[0] ^= k[0];
tmp_1_s <= a_1_0_s xor k_1_in; -- a[1] ^= k[1];
tmp_2_s <= a_2_in xor k_2_in; -- a[2] ^= k[2];
tmp_3_s <= a_3_0_s xor k_3_in; -- a[3] ^= k[3];
m_2_tmp_0_s <= tmp_1_s xor tmp_3_s; -- temp = a[1]^a[3];
m_2_tmp_1_s <= m_2_tmp_0_s(23 downto 0) & m_2_tmp_0_s(31 downto 24); -- temp>>>8
m_2_tmp_2_s <= m_2_tmp_0_s(7 downto 0) & m_2_tmp_0_s(31 downto 8); -- temp<<<8;
m_2_tmp_3_s <= m_2_tmp_0_s xor m_2_tmp_1_s xor m_2_tmp_2_s; -- temp ^= temp>>>8 ^ temp<<<8;
a_0_out <= tmp_0_s xor m_2_tmp_3_s; -- a[0] ^= temp;
a_2_out <= tmp_2_s xor m_2_tmp_3_s; -- a[2] ^= temp;
a_1_out <= tmp_1_s;
a_3_out <= tmp_3_s;
end Behavioral;
| gpl-3.0 | 02313e3f53e8860d663bcf3f5bfd463a | 0.549644 | 2.429303 | false | false | false | false |
GustaMagik/RSA_Security_Token | VHDL_code/ver_A/RSA_Security_Token_Keyboard_Version/Keyboard.vhdl | 1 | 6,362 |
--Copyright 2017 Christoffer Mathiesen, Gustav Örtenberg
--Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
--
--1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
--
--2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the
--documentation and/or other materials provided with the distribution.
--
--3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this
--software without specific prior written permission.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS
--BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
--GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
--LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Library IEEE;
Use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_MISC.ALL;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;
Use IEEE.NUMERIC_STD.all;
Use work.all;
Entity Keyboard is
Port ( Row_Input : in STD_LOGIC_VECTOR (3 downto 0);
Col_Input_A : out STD_LOGIC_VECTOR (3 downto 0) := (others => '1');
Output : out STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
RDY : out STD_LOGIC := '0';
CLK : in STD_LOGIC;
ARESETN : in STD_LOGIC
);
end Keyboard;
--------------------------------------------------------------------------------------
--This is a translator for the Keypad v3.0 to hex.
--To be connected to the outside world. First it debounces the signal.
--It takes the 8 bit wide input and translates it down to the corresponding hex value.
--Any input besides the accepted ones gives output 0 and the RDY-bit to 0.
--When an accepted input is parsed the module sets the RDY-bit to 1.
--------------------------------------------------------------------------------------
architecture Behaviour of Keyboard is
component Debouncer
port( Input : in STD_LOGIC;
Output : out STD_LOGIC;
CLK : in STD_LOGIC
);
end component;
type input_vector is array (3 downto 0) of STD_LOGIC;
signal input_debounced : STD_LOGIC_VECTOR (3 downto 0);
signal input_vector_tmp: input_vector := (others => '0');
signal counter : unsigned (11 downto 0) := (others => '0');
signal translated : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
Begin
Process (CLK)
Begin
if rising_edge(CLK) then
input_debounced <= Row_Input;
IF ARESETN = '1' THEN
if input_debounced = "0000" and counter = "0000" then
--counter <= "0000";
RDY <= '0';
translated <= (others => '0');
else
if counter = to_unsigned(0, 12) then Col_Input_A <= "0001";
elsif counter = to_unsigned(500, 12) then --Wait for 500 cycles
if input_debounced /= "0000" then
translated <= STD_LOGIC_VECTOR(input_debounced) & "0001";
end if;
Col_Input_A <= "0010";
elsif counter = to_unsigned(1000, 12) then--Wait for 500 cycles
if input_debounced /= "0000" then
translated <= translated or STD_LOGIC_VECTOR(input_debounced) & "0010";
end if;
Col_Input_A <= "0100";
elsif counter = to_unsigned(1500, 12) then --Wait for 500 cycles
if input_debounced /= "0000" then
translated <= translated or STD_LOGIC_VECTOR(input_debounced) & "0100";
end if;
Col_Input_A <= "1000";
elsif counter = to_unsigned(2000, 12) then --Wait for 500 cycles
if input_debounced /= "0000" then
translated <= translated or STD_LOGIC_VECTOR(input_debounced) & "1000";
end if;
Col_Input_A <= "1111";
else
end if;
if counter /= to_unsigned(4000, 12) then --Wait for 2000 cycles fom previous step
counter <= counter + 1;
elsif input_debounced = "0000" then --Wait for release of button
counter <= (others => '0');
----------------------------------------------------------------------------------
--Case for translations. In order of magnitude.
--Input is in the format 7 downto 4 row, 3 downto 0 col.
--I.e. the vector 0100 0001 is row 3, col 1.
---------------------------------------------------------------------------------
Translate: case translated is
when "10000010" =>
RDY <= '1'; --0
Output <= "0000";
when "00010001" =>
RDY <= '1'; --1
Output <= "0001";
when "00010010" =>
RDY <= '1'; --2
Output <= "0010";
when "00010100" =>
RDY <= '1'; --3
Output <= "0011";
when "00100001" =>
RDY <= '1'; --4
Output <= "0100";
when "00100010" =>
RDY <= '1'; --5
Output <= "0101";
when "00100100" =>
RDY <= '1'; --6
Output <= "0110";
when "01000001" =>
RDY <= '1'; --7
Output <= "0111";
when "01000010" =>
RDY <= '1'; --8
Output <= "1000";
when "01000100" =>
RDY <= '1'; --9
Output <= "1001";
when "00011000" =>
RDY <= '1'; --A
Output <= "1010";
when "00101000" =>
RDY <= '1'; --B
Output <= "1011";
when "01001000" =>
RDY <= '1'; --C
Output <= "1100";
when "10001000" =>
RDY <= '1'; --D
Output <= "1101";
when "10000100" =>
RDY <= '1'; --E
Output <= "1110";
when "10000001" =>
RDY <= '1'; --F
Output <= "1111";
when others =>
RDY <= '0'; --Others
end case Translate;
end if;
end if;
elsif ARESETN = '0' then
RDY <= '0';
Output <= (others => '0'); --Reset
--input_debounced <= (others => '0');
-- input_vector_debounced <= (others => '0');
translated <= (others => '0');
counter <= (others => '0');
end if;
end if;
end process;
end Behaviour;
| bsd-3-clause | 18c63bee0a05d57d99fc6caba11a790b | 0.590695 | 3.59435 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/Filter_Bank/filter_bank_demo.vhd | 1 | 3,457 | --------------------------------------------------------------------------------------------------
-- 3-stage Filter Bank
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- PACKAGE
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.dsp_pkg.all;
package filter_bank_pkg is
--FIR filter component declaration
component filter_bank is
generic( analysis_low : coefficient_array;
analysis_high : coefficient_array;
synthesis_low : coefficient_array;
synthesis_high : coefficient_array);
port( clk0 : in std_logic;
clk1 : in std_logic;
rst : in std_logic;
x : in sig;
y : out sig);
end component;
end package;
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.dsp_pkg.all;
use work.decomposition_pkg.all;
use work.reconstruction_pkg.all;
entity filter_bank is
generic( analysis_low : coefficient_array;
analysis_high : coefficient_array;
synthesis_low : coefficient_array;
synthesis_high : coefficient_array);
port( clk0 : in std_logic;
clk1 : in std_logic;
rst : in std_logic;
x : in sig;
y : out sig);
end filter_bank;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture behave of filter_bank is
-- Numerics NM : N -> stage, M -> bank
signal down_y00 : sig := (others => '0');
signal down_y01 : sig := (others => '0');
signal up_y00 : sig := (others => '0');
signal up_y01 : sig := (others => '0');
begin
------- Stage 0 Decomposition ---------------------
stage0_decomp : decomposition
generic map(low_pass => analysis_low,
high_pass => analysis_high)
port map( clk_low => clk1,
clk_high => clk0,
rst => rst,
x => x,
y_low => down_y00,
y_high => down_y01);
------- Filter Banks --------------------------------
up_y00 <= down_y00;
up_y01 <= down_y01;
------- Stage 0 Reconstruction --------------------
stage0_bank0_recon : reconstruction
generic map(low_pass => synthesis_low,
high_pass => synthesis_high)
port map( clk_low => clk1,
clk_high => clk0,
rst => rst,
x_low => up_y00,
x_high => up_y01,
y => y);
end behave;
| mit | cb303bb4988df1d3c0143ac3f0dd9a12 | 0.352907 | 5.106352 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/FIR_Filter/sparse_fir_filter_imp.vhd | 1 | 1,489 | --------------------------------------------------------------------------------------------------
-- Sparse FIR Filter Implementation
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dsp_pkg.all;
use work.sparse_fir_filter_pkg.all;
--This module is a top-level for implementing the fir filter
entity sparse_fir_filter_imp is
port( clk : in std_logic;
rst : in std_logic;
x : in sig;
y : out fir_sig);
end sparse_fir_filter_imp;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture imp of sparse_fir_filter_imp is
begin
--Instantiate unit under test
uut : entity work.sparse_fir_filter(behave)
generic map(h => LOW_PASS_101)
port map( clk => clk,
rst => rst,
x => x,
y => y);
end imp;
| mit | 8096288cbee0770ef26e6a82cec7a4c6 | 0.320349 | 5.932271 | false | false | false | false |
azeemshaikh38/PipelinedProcessorWithInterrupts | Processor/scratch_pad.vhd | 1 | 1,283 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
entity scratch_pad is
port (
data_in1, data_in2 : in std_logic_vector(7 downto 0);
raddr_write1, raddr_write2 : in std_logic_vector(3 downto 0);
data_out : out std_logic_vector(7 downto 0);
raddr_read : in std_logic_vector(3 downto 0);
re, we, clk : in std_logic
);
end entity;
architecture behav of scratch_pad is
type mem_array is array(15 downto 0) of std_logic_vector(7 downto 0);
signal mem_data : mem_array;
begin
process (clk)
begin
if (rising_edge(clk) and (we = '1')) then
mem_data(conv_integer(raddr_write1)) <= data_in1;
report "Scratch Pad write addr: " & integer'image(conv_integer(raddr_write1)) & " data: " & integer'image(conv_integer(data_in1));
mem_data(conv_integer(raddr_write2)) <= data_in2;
report "Scratch Pad write addr: " & integer'image(conv_integer(raddr_write2)) & " data: " & integer'image(conv_integer(data_in2));
elsif (falling_edge(clk) and (re = '1')) then
data_out <= mem_data(conv_integer(raddr_read));
report "Scratch Pad read addr: " & integer'image(conv_integer(raddr_read)) & " data: " & integer'image(conv_integer(mem_data(conv_integer(raddr_read))));
end if;
end process;
end architecture;
| unlicense | 18336d6e1da920d3122ced58af11a26c | 0.693687 | 2.83223 | false | false | false | false |
azeemshaikh38/PipelinedProcessorWithInterrupts | Processor/control.vhd | 1 | 3,476 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
entity hazard_control_block is
port (
dest_reg_en : in std_logic;
dest_reg : in std_logic_vector(3 downto 0);
src_reg1_en : std_logic;
src_reg1 : in std_logic_vector(3 downto 0);
src_reg2_en : in std_logic;
src_reg2 : in std_logic_vector(3 downto 0);
handlerPC : in std_logic_vector(7 downto 0);
nop : inout std_logic;
interrupt_happened : in std_logic;
interrupt_handled : in std_logic;
src_select : out std_logic_vector(1 downto 0);
PC : inout std_logic_vector(7 downto 0);
branch : in std_logic;
branch_addr : in std_logic_vector(7 downto 0);
operation : in std_logic_vector(4 downto 0);
clk, rst : in std_logic;
PC2handler : out std_logic_vector(7 downto 0)
);
end entity;
architecture behav of hazard_control_block is
signal prev_dest_reg_en : std_logic;
signal prev_dest_reg : std_logic_vector(3 downto 0);
signal state : std_logic_vector(1 downto 0);
signal temp_pc : std_logic_vector(7 downto 0);
begin
process(clk, rst)
begin
if (rst = '1') then
report "Control Block Reset";
PC <= X"00";
nop <= '0';
prev_dest_reg_en <= '0';
state <= "00";
elsif (rising_edge(clk)) then
if (state = "00") then
if (branch = '1') then
PC <= branch_addr;
elsif (nop = '1') then
PC <= PC - 1;
else
PC <= PC + 1;
end if;
else
PC <= X"00";
temp_pc <= handlerPC;
end if;
elsif falling_edge(clk) then
report "prev_dest_reg_en: " & integer'image(conv_integer(prev_dest_reg_en)) & "prev_dest_reg: " & integer'image(conv_integer(prev_dest_reg));
report "src_reg1_en: " & integer'image(conv_integer(src_reg1_en)) & "src_reg1: " & integer'image(conv_integer(src_reg1));
report "src_reg2_en: " & integer'image(conv_integer(src_reg2_en)) & "src_reg2: " & integer'image(conv_integer(src_reg2));
if (state = "00") then
nop <= '0';
src_select <= "00";
if ((src_reg1_en = '1') and (prev_dest_reg_en = '1')) then
report "Source reg 1 enable & Prev dest reg en";
if (src_reg1 = prev_dest_reg) then
report "Src reg 1, prev dest reg 1";
src_select(0) <= '1';
end if;
end if;
if ((src_reg2_en = '1') and (prev_dest_reg_en = '1')) then
report "Source reg 2 enable & prev dest reg enable";
if (src_reg2 = prev_dest_reg) then
report "Source reg 2, prev dest reg 2";
src_select(1) <= '1';
end if;
end if;
if (dest_reg_en = '1') then
report "dest reg enable1";
prev_dest_reg_en <= '1';
prev_dest_reg <= dest_reg;
else
prev_dest_reg_en <= '0';
end if;
if (branch = '1') then
nop <= '1';
end if;
if (interrupt_happened = '1' and interrupt_handled = '0') then
state <= "01";
nop <= '1';
end if;
PC2handler <= PC;
else
PC <= X"00";
nop <= '0';
if (interrupt_happened = '0' and interrupt_handled = '1') then
PC <= temp_pc;
state <= "00";
end if;
end if;
end if;
end process;
end architecture;
| unlicense | 2cb26f89f25b421b9c48de7d15a08c98 | 0.537975 | 3.162875 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/EPROC_IN8_DEC8b10b.vhd | 2 | 10,753 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/25/2014
--! Module Name: EPROC_IN8_DEC8b10b
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.ALL;
use work.all;
use work.centralRouter_package.all;
--! 8b10b decoder for EPROC_IN8 module
entity EPROC_IN8_DEC8b10b is
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
edataIN : in std_logic_vector (7 downto 0);
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic;
busyOut : out std_logic
);
end EPROC_IN8_DEC8b10b;
architecture Behavioral of EPROC_IN8_DEC8b10b is
----------------------------------
----------------------------------
component KcharTest is
port (
clk : in std_logic;
encoded10in : in std_logic_vector (9 downto 0);
KcharCode : out std_logic_vector (1 downto 0)
);
end component KcharTest;
----------------------------------
----------------------------------
signal EDATAbitstreamSREG : std_logic_vector (47 downto 0) := (others=>'0'); -- 48 bit (8 x 5 = 40, plus 8 more)
signal word10bx4_align_array, word10bx4_align_array_r : word10b_4array_8array_type;
signal word10b_array, word10b_array_s : word10b_4array_type;
signal isk_array : isk_4array_type;
signal comma_valid_bits_or, word10bx4_align_rdy_r,
word10b_array_rdy, word10b_array_rdy_s, word10b_array_rdy_s1, realignment_ena : std_logic;
signal align_select : std_logic_vector (2 downto 0) := (others=>'0');
signal comma_valid_bits : std_logic_vector (7 downto 0);
signal alignment_sreg : std_logic_vector (4 downto 0) := (others=>'0');
begin
-------------------------------------------------------------------------------------------
--live bitstream
-- 48 bit input shift register
-------------------------------------------------------------------------------------------
process(bitCLK, rst)
begin
if rst = '1' then
EDATAbitstreamSREG <= (others => '0');
elsif bitCLK'event and bitCLK = '1' then
EDATAbitstreamSREG <= edataIN & EDATAbitstreamSREG(47 downto 8);
end if;
end process;
--
-------------------------------------------------------------------------------------------
--clock0
-- input shift register mapping into 10 bit registers
-------------------------------------------------------------------------------------------
input_map: for I in 0 to 7 generate -- 4 10bit-words per alignment, 8 possible alignments
--word10bx4_align_array(I)(0) <= EDATAbitstreamSREG((I+9) downto (I+0)); -- 1st 10 bit word, alligned to bit I
--word10bx4_align_array(I)(1) <= EDATAbitstreamSREG((I+19) downto (I+10)); -- 2nd 10 bit word, alligned to bit I
--word10bx4_align_array(I)(2) <= EDATAbitstreamSREG((I+29) downto (I+20)); -- 3rd 10 bit word, alligned to bit I
--word10bx4_align_array(I)(3) <= EDATAbitstreamSREG((I+39) downto (I+30)); -- 4th 10 bit word, alligned to bit I
word10bx4_align_array(I)(0) <= EDATAbitstreamSREG(I+0)&EDATAbitstreamSREG(I+1)&EDATAbitstreamSREG(I+2)&EDATAbitstreamSREG(I+3)&EDATAbitstreamSREG(I+4)&
EDATAbitstreamSREG(I+5)&EDATAbitstreamSREG(I+6)&EDATAbitstreamSREG(I+7)&EDATAbitstreamSREG(I+8)&EDATAbitstreamSREG(I+9); -- 1st 10 bit word, alligned to bit I
word10bx4_align_array(I)(1) <= EDATAbitstreamSREG(I+10)&EDATAbitstreamSREG(I+11)&EDATAbitstreamSREG(I+12)&EDATAbitstreamSREG(I+13)&EDATAbitstreamSREG(I+14)&
EDATAbitstreamSREG(I+15)&EDATAbitstreamSREG(I+16)&EDATAbitstreamSREG(I+17)&EDATAbitstreamSREG(I+18)&EDATAbitstreamSREG(I+19); -- 2nd 10 bit word, alligned to bit I
word10bx4_align_array(I)(2) <= EDATAbitstreamSREG(I+20)&EDATAbitstreamSREG(I+21)&EDATAbitstreamSREG(I+22)&EDATAbitstreamSREG(I+23)&EDATAbitstreamSREG(I+24)&
EDATAbitstreamSREG(I+25)&EDATAbitstreamSREG(I+26)&EDATAbitstreamSREG(I+27)&EDATAbitstreamSREG(I+28)&EDATAbitstreamSREG(I+29); -- 3rd 10 bit word, alligned to bit I
word10bx4_align_array(I)(3) <= EDATAbitstreamSREG(I+30)&EDATAbitstreamSREG(I+31)&EDATAbitstreamSREG(I+32)&EDATAbitstreamSREG(I+33)&EDATAbitstreamSREG(I+34)&
EDATAbitstreamSREG(I+35)&EDATAbitstreamSREG(I+36)&EDATAbitstreamSREG(I+37)&EDATAbitstreamSREG(I+38)&EDATAbitstreamSREG(I+39); -- 4th 10 bit word, alligned to bit I
end generate input_map;
-------------------------------------------------------------------------------------------
--clock0
-- K28.5 comma test
-------------------------------------------------------------------------------------------
comma_test: for I in 0 to 7 generate -- 4 10bit-words per alignment, comma is valid if two first words have comma
comma_valid_bits(I) <= '1' when ((word10bx4_align_array(I)(0) = COMMAp or word10bx4_align_array(I)(0) = COMMAn) and
(word10bx4_align_array(I)(1) = COMMAp or word10bx4_align_array(I)(1) = COMMAn)) else '0';
end generate comma_test;
--
comma_valid_bits_or <= comma_valid_bits(7) or comma_valid_bits(6) or comma_valid_bits(5) or comma_valid_bits(4) or
comma_valid_bits(3) or comma_valid_bits(2) or comma_valid_bits(1) or comma_valid_bits(0);
--
-------------------------------------------------------------------------------------------
--clock1
-- alignment selector state
-------------------------------------------------------------------------------------------
process(bitCLK, rst)
begin
if rst = '1' then
alignment_sreg <= "00000";
elsif bitCLK'event and bitCLK = '1' then
if comma_valid_bits_or = '1' then
alignment_sreg <= "10000";
else
alignment_sreg <= alignment_sreg(0) & alignment_sreg(4 downto 1);
end if;
end if;
end process;
--
input_reg1: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10bx4_align_array_r <= word10bx4_align_array;
end if;
end process;
--
word10bx4_align_rdy_r <= alignment_sreg(4);
--
process(bitCLK, rst)
begin
if rst = '1' then
align_select <= "000";
elsif bitCLK'event and bitCLK = '1' then
if comma_valid_bits_or = '1' then
align_select(0) <= (not comma_valid_bits(0)) and (
comma_valid_bits(1) or ( (not comma_valid_bits(1)) and (not comma_valid_bits(2)) and (
comma_valid_bits(3) or ( (not comma_valid_bits(3)) and (not comma_valid_bits(4)) and (
comma_valid_bits(5) or ( (not comma_valid_bits(5)) and (not comma_valid_bits(6)) and (
comma_valid_bits(7)
)))))));
align_select(1) <= (not comma_valid_bits(0)) and (not comma_valid_bits(1)) and
((comma_valid_bits(2) or comma_valid_bits(3)) or (
(not comma_valid_bits(2)) and (not comma_valid_bits(3)) and (not comma_valid_bits(4)) and (not comma_valid_bits(5)) and (
comma_valid_bits(6) or comma_valid_bits(7))));
align_select(2) <= (not comma_valid_bits(0)) and (not comma_valid_bits(1)) and (not comma_valid_bits(2)) and (not comma_valid_bits(3)) and
(comma_valid_bits(4) or comma_valid_bits(5) or comma_valid_bits(6) or comma_valid_bits(7));
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
--clock2
-- alignment selected
-------------------------------------------------------------------------------------------
--
input_reg2: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10b_array_rdy <= word10bx4_align_rdy_r;
end if;
end process;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
case (align_select) is
when "000" => -- bit0 word got comma => align to bit0
word10b_array <= word10bx4_align_array_r(0);
when "001" => -- bit1 word got comma => align to bit1
word10b_array <= word10bx4_align_array_r(1);
when "010" => -- bit2 word got comma => align to bit2
word10b_array <= word10bx4_align_array_r(2);
when "011" => -- bit3 word got comma => align to bit3
word10b_array <= word10bx4_align_array_r(3);
when "100" => -- bit4 word got comma => align to bit4
word10b_array <= word10bx4_align_array_r(4);
when "101" => -- bit5 word got comma => align to bit5
word10b_array <= word10bx4_align_array_r(5);
when "110" => -- bit6 word got comma => align to bit6
word10b_array <= word10bx4_align_array_r(6);
when "111" => -- bit7 word got comma => align to bit7
word10b_array <= word10bx4_align_array_r(7);
when others =>
end case;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- 8b10b K-characters codes: COMMA/SOC/EOC/DATA
-------------------------------------------------------------------------------------------
KcharTests: for I in 0 to 3 generate
KcharTestn: KcharTest
port map(
clk => bitCLK,
encoded10in => word10b_array(I),
KcharCode => isk_array(I)
);
end generate KcharTests;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10b_array_s <= word10b_array;
word10b_array_rdy_s <= word10b_array_rdy;
end if;
end process;
--
-- if more that 2 commas, will repeat itself next clock
realignment_ena <= '0' when (isk_array(0) = "11" and isk_array(1) = "11" and isk_array(2) = "11") else '1';
word10b_array_rdy_s1 <= word10b_array_rdy_s and realignment_ena;
-------------------------------------------------------------------------------------------
-- 4 words get aligned and ready as 10 bit word (data 8 bit and data code 2 bit)
-------------------------------------------------------------------------------------------
EPROC_IN8_ALIGN_BLOCK_inst: entity work.EPROC_IN8_ALIGN_BLOCK
port map(
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst,
bytes => word10b_array_s,
bytes_rdy => word10b_array_rdy_s1,
dataOUT => dataOUT,
dataOUTrdy => dataOUTrdy,
busyOut => busyOut
);
end Behavioral;
| gpl-3.0 | 4e478a04822054065d6df534d735125c | 0.524319 | 3.685058 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/readout/l0_buffer_wrapper.vhd | 1 | 8,951 | ----------------------------------------------------------------------------------
-- Company: NTU Athens - BNL
-- Engineer: Christos Bakalis ([email protected])
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Christos Bakalis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 28.04.2017 14:18:44
-- Design Name: Level-0 Buffer Wrapper
-- Module Name: l0_buffer_wrapper - RTL
-- Project Name: NTUA-BNL VMM3 Readout Firmware
-- Target Devices: Xilinx xc7a200t-2fbg484
-- Tool Versions: Vivado 2016.4
-- Description: Wrapper that contains the FIFO that buffers level-0 data, and the
-- necessary acomppanying logic (packet_formation interface)
--
-- Dependencies:
--
-- Changelog:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
entity l0_buffer_wrapper is
Port(
------------------------------------
------- General Interface ----------
clk_ckdt : in std_logic;
clk : in std_logic;
rst_buff : in std_logic;
wr_accept : in std_logic;
level_0 : in std_logic;
------------------------------------
--- Deserializer Interface ---------
inhib_wr : out std_logic;
commas_true : in std_logic;
dout_dec : in std_logic_vector(7 downto 0);
wr_en : in std_logic;
------------------------------------
---- Packet Formation Interface ----
rd_ena_buff : in std_logic;
rst_intf_proc : in std_logic;
vmmWordReady : out std_logic;
vmmWord : out std_logic_vector(15 downto 0);
vmmEventDone : out std_logic
);
end l0_buffer_wrapper;
architecture RTL of l0_buffer_wrapper is
component level0_buffer
port (
wr_clk : in std_logic;
rd_clk : in std_logic;
rst : in std_logic;
din : in std_logic_vector(7 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(15 downto 0);
full : out std_logic;
empty : out std_logic;
wr_rst_busy : out std_logic;
rd_rst_busy : out std_logic
);
end component;
component ila_l0_buf
port(
clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0)
);
end component;
signal fifo_full : std_logic := '0';
signal fifo_empty : std_logic := '0';
signal commas_true_i : std_logic := '0';
signal commas_true_s : std_logic := '0';
signal inhibit_write : std_logic := '1';
signal inhib_wr_i : std_logic := '0';
signal inhib_wr_s : std_logic := '0';
signal enable_timeout : std_logic := '0';
signal timeout_cnt : integer range 0 to 511 := 0;
signal timeout : std_logic := '0';
constant timeout_max : integer := 511;
type stateType is (ST_IDLE, ST_WAIT_FOR_DATA, ST_READING, ST_DONE);
signal state : stateType := ST_IDLE;
attribute ASYNC_REG : string;
attribute ASYNC_REG of commas_true_i : signal is "TRUE";
attribute ASYNC_REG of commas_true_s : signal is "TRUE";
attribute ASYNC_REG of inhib_wr_i : signal is "TRUE";
attribute ASYNC_REG of inhib_wr_s : signal is "TRUE";
-- attribute mark_debug : string;
-- attribute mark_debug of wr_en : signal is "TRUE";
-- attribute mark_debug of dout_dec : signal is "TRUE";
-- attribute mark_debug of fifo_empty : signal is "TRUE";
-- attribute mark_debug of rd_ena_buff : signal is "TRUE";
-- attribute mark_debug of inhibit_write : signal is "TRUE";
-- attribute mark_debug of state_debug : signal is "TRUE";
-- attribute mark_debug of level_0 : signal is "TRUE";
-- attribute dont_touch : string;
-- attribute dont_touch of state_debug : signal is "TRUE";
begin
-- Moore FSM that interfaces with packet_formation and vmm_driver
pf_interface_FSM: process(clk)
begin
if(rising_edge(clk))then
if(rst_intf_proc = '1')then
vmmEventDone <= '0';
inhibit_write <= '1';
vmmWordReady <= '0';
enable_timeout <= '0';
state <= ST_IDLE;
else
case state is
-- wait for the trigger module to open the window
when ST_IDLE =>
vmmEventDone <= '0';
inhibit_write <= '1';
vmmWordReady <= '0';
enable_timeout <= '0';
if(wr_accept = '1')then
state <= ST_WAIT_FOR_DATA;
else
state <= ST_IDLE;
end if;
-- if there are data in the buffer and commas are being detected => ready to be read
when ST_WAIT_FOR_DATA =>
vmmEventDone <= '0';
vmmWordReady <= '0';
inhibit_write <= '0';
enable_timeout <= '1';
if(fifo_empty = '0' and commas_true_s = '1')then
state <= ST_READING;
-- elsif(timeout = '1')then -- timeout of 4us reached
-- state <= ST_DONE;
else
state <= ST_WAIT_FOR_DATA;
end if;
-- wait for pf to empty the buffer and prevent any further writes
when ST_READING =>
inhibit_write <= '1';
enable_timeout <= '0';
vmmWordReady <= '1';
vmmEventDone <= '0';
if(fifo_empty = '0')then
state <= ST_READING;
else
state <= ST_DONE;
end if;
-- stay here until reset by pf
when ST_DONE =>
vmmWordReady <= '0';
inhibit_write <= '1';
vmmEventDone <= '1';
enable_timeout <= '0';
state <= ST_DONE;
when others =>
vmmWordReady <= '0';
vmmEventDone <= '0';
inhibit_write <= '0';
enable_timeout <= '0';
state <= ST_IDLE;
end case;
end if;
end if;
end process;
-- sync inhibit write signals
inhib_wr_sync_proc: process(clk_ckdt)
begin
if(rising_edge(clk_ckdt))then
inhib_wr_i <= inhibit_write;
inhib_wr_s <= inhib_wr_i;
end if;
end process;
-- sync 'commas_true'
clk_sync_proc: process(clk)
begin
if(rising_edge(clk))then
commas_true_i <= commas_true;
commas_true_s <= commas_true_i;
end if;
end process;
-- timeout process
--to_proc: process(clk)
--begin
-- if(rising_edge(clk))then
-- if(enable_timeout = '1')then
-- if(timeout_cnt = timeout_max)then
-- timeout <= '1';
-- else
-- timeout_cnt <= timeout_cnt + 1;
-- end if;
-- else
-- timeout_cnt <= 0;
-- timeout <= '0';
-- end if;
-- end if;
--end process;
l0_buffering_fifo: level0_buffer
port map(
rst => rst_buff,
wr_clk => clk_ckdt,
rd_clk => clk,
din => dout_dec,
wr_en => wr_en,
rd_en => rd_ena_buff,
dout => vmmWord,
full => fifo_full,
empty => fifo_empty,
wr_rst_busy => open,
rd_rst_busy => open
);
--ila_level0_buf: ila_l0_buf
-- PORT MAP (
-- clk => clk_ckdt,
-- probe0(0) => wr_en,
-- probe0(8 downto 1) => dout_dec,
-- probe0(9) => fifo_empty,
-- probe0(10) => rd_ena_buff,
-- probe0(12 downto 11) => state_debug,
-- probe0(13) => level_0,
-- probe0(15 downto 14) => (others => '0')
-- );
inhib_wr <= inhib_wr_s;
end RTL; | gpl-3.0 | c84c3edf5ac115f3e06aacc0370abe9d | 0.494358 | 3.87657 | false | false | false | false |
adelapie/noekeon | tb_rc_gen.vhd | 5 | 5,554 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_rc_gen IS
END tb_rc_gen;
ARCHITECTURE behavior OF tb_rc_gen IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT rc_gen
PORT(
clk : IN std_logic;
rst : IN std_logic;
enc : IN std_logic;
rc_out : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal enc : std_logic := '0';
--Outputs
signal rc_out : std_logic_vector(7 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: rc_gen PORT MAP (
clk => clk,
rst => rst,
enc => enc,
rc_out => rc_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- RC = {80, 1b, 36, 6c, d8, ab, 4d, 9a, 2f, 5e, bc, 63, c6, 97, 35, 6a}
wait for clk_period/2 + clk_period;
rst <= '1';
enc <= '0';
wait for clk_period;
rst <= '0';
assert rc_out = X"80"
report "RC ERROR (rc_out)" severity FAILURE;
wait for clk_period;
assert rc_out = X"1b"
report "RC ERROR (rc_out)" severity FAILURE;
wait for clk_period;
assert rc_out = X"36"
report "RC ERROR (rc_out)" severity FAILURE;
wait for clk_period;
assert rc_out = X"6c"
report "RC ERROR (rc_out)" severity FAILURE;
wait for clk_period;
assert rc_out = X"d8"
report "RC ERROR (rc_out)" severity FAILURE;
wait for clk_period;
assert rc_out = X"ab"
report "RC ERROR (rc_out)" severity FAILURE;
wait for clk_period;
assert rc_out = X"4d"
report "RC ERROR (rc_out)" severity FAILURE;
wait for clk_period;
assert rc_out = X"9a"
report "RC ERROR (rc_out)" severity FAILURE;
wait for clk_period;
assert rc_out = X"2f"
report "RC ERROR (rc_out)" severity FAILURE;
wait for clk_period;
assert rc_out = X"5e"
report "RC ERROR (rc_out)" severity FAILURE;
wait for clk_period;
assert rc_out = X"bc"
report "RC ERROR (rc_out)" severity FAILURE;
wait for clk_period;
assert rc_out = X"63"
report "RC ERROR (rc_out)" severity FAILURE;
wait for clk_period;
assert rc_out = X"c6"
report "RC ERROR (rc_out)" severity FAILURE;
wait for clk_period;
assert rc_out = X"97"
report "RC ERROR (rc_out)" severity FAILURE;
wait for clk_period;
assert rc_out = X"35"
report "RC ERROR (rc_out)" severity FAILURE;
wait for clk_period;
assert rc_out = X"6a"
report "RC ERROR (rc_out)" severity FAILURE;
wait for clk_period;
rst <= '1';
enc <= '1';
wait for clk_period;
rst <= '0';
wait for clk_period;
assert rc_out = X"6a"
report "RC ERROR (rc_out)" severity FAILURE;
wait for clk_period;
assert rc_out = X"35"
report "RC ERROR (rc_out)" severity FAILURE;
wait for clk_period;
assert rc_out = X"97"
report "RC ERROR (rc_out)" severity FAILURE;
wait for clk_period;
assert rc_out = X"c6"
report "RC ERROR (rc_out)" severity FAILURE;
wait for clk_period;
assert rc_out = X"63"
report "RC ERROR (rc_out)" severity FAILURE;
wait for clk_period;
assert rc_out = X"bc"
report "RC ERROR (rc_out)" severity FAILURE;
wait for clk_period;
assert rc_out = X"5e"
report "RC ERROR (rc_out)" severity FAILURE;
wait for clk_period;
assert rc_out = X"2f"
report "RC ERROR (rc_out)" severity FAILURE;
wait for clk_period;
assert rc_out = X"9a"
report "RC ERROR (rc_out)" severity FAILURE;
wait for clk_period;
assert rc_out = X"4d"
report "RC ERROR (rc_out)" severity FAILURE;
wait for clk_period;
assert rc_out = X"ab"
report "RC ERROR (rc_out)" severity FAILURE;
wait for clk_period;
assert rc_out = X"d8"
report "RC ERROR (rc_out)" severity FAILURE;
wait for clk_period;
assert rc_out = X"6c"
report "RC ERROR (rc_out)" severity FAILURE;
wait for clk_period;
assert rc_out = X"36"
report "RC ERROR (rc_out)" severity FAILURE;
wait for clk_period;
assert rc_out = X"1b"
report "RC ERROR (rc_out)" severity FAILURE;
wait for clk_period;
assert rc_out = X"80"
report "RC ERROR (rc_out)" severity FAILURE;
wait for clk_period;
wait;
end process;
END;
| gpl-3.0 | 85b428368e951c3c4989e4cbb26a9c1d | 0.588585 | 3.305952 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/EPROC_IN16.vhd | 1 | 4,254 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 08/03/2014
--! Module Name: EPROC_IN16
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.ALL;
use work.all;
--! E-link processor, 16bit input
entity EPROC_IN16 is
generic (
do_generate : boolean := true;
includeNoEncodingCase : boolean := true
);
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
ENA : in std_logic;
ENCODING : in std_logic_vector (1 downto 0);
EDATA_IN : in std_logic_vector (15 downto 0);
DATA_OUT : out std_logic_vector (9 downto 0);
DATA_RDY : out std_logic;
busyOut : out std_logic
);
end EPROC_IN16;
architecture Behavioral of EPROC_IN16 is
constant zeros10array : std_logic_vector (9 downto 0) := (others=>'0');
signal DATA_OUT_direct,DATA_OUT_8b10b_case,DATA_OUT_HDLC_case,DATA_OUT_s : std_logic_vector (9 downto 0);
signal DATA_RDY_direct,DATA_RDY_8b10b_case,DATA_RDY_HDLC_case,DATA_RDY_sig : std_logic;
signal RESTART_sig, rst_case00, rst_case01 : std_logic;
---
begin
gen_enabled: if do_generate = true generate
RESTART_sig <= rst or (not ENA); -- comes from clk40 domain
-------------------------------------------------------------------------------------------
-- ENCODING case "00": direct data, no delimeter...
-------------------------------------------------------------------------------------------
direct_data_enabled: if includeNoEncodingCase = true generate
rst_case00 <= RESTART_sig or (ENCODING(1) or ENCODING(0));
EPROC_IN16_direct_inst: entity work.EPROC_IN16_direct
port map(
bitCLKx4 => bitCLKx4,
rst => rst_case00,
edataIN => EDATA_IN,
dataOUT => DATA_OUT_direct,
dataOUTrdy => DATA_RDY_direct
);
end generate direct_data_enabled;
--
direct_data_disabled: if includeNoEncodingCase = false generate
DATA_RDY_direct <= '0';
DATA_OUT_direct <= (others=>'0');
end generate direct_data_disabled;
--
-------------------------------------------------------------------------------------------
-- ENCODING case "01": DEC8b10b
-------------------------------------------------------------------------------------------
rst_case01 <= RESTART_sig or (ENCODING(1) or (not ENCODING(0)));
--
EPROC_IN16_DEC8b10b_inst: entity work.EPROC_IN16_DEC8b10b
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case01,
edataIN => EDATA_IN,
dataOUT => DATA_OUT_8b10b_case,
dataOUTrdy => DATA_RDY_8b10b_case,
busyOut => busyOut
);
-------------------------------------------------------------------------------------------
-- ENCODING case "10": HDLC
-------------------------------------------------------------------------------------------
-- TBD
DATA_OUT_HDLC_case <= (others=>'0');
DATA_RDY_HDLC_case <= '0';
-------------------------------------------------------------------------------------------
-- output data/rdy according to the encoding settings
-------------------------------------------------------------------------------------------
DATA_OUT_MUX4_10bit: entity work.MUX4_Nbit
generic map(N=>10)
port map(
data0 => DATA_OUT_direct,
data1 => DATA_OUT_8b10b_case,
data2 => DATA_OUT_HDLC_case,
data3 => zeros10array,
sel => ENCODING,
data_out => DATA_OUT_s
);
DATA_RDY_MUX4: entity work.MUX4
port map(
data0 => DATA_RDY_direct,
data1 => DATA_RDY_8b10b_case,
data2 => DATA_RDY_HDLC_case,
data3 => '0',
sel => ENCODING,
data_out => DATA_RDY_sig
);
DATA_RDY <= DATA_RDY_sig;
DATA_OUT <= DATA_OUT_s;
--------------------
end generate gen_enabled;
--
--
gen_disabled: if do_generate = false generate
DATA_OUT <= (others=>'0');
DATA_RDY <= '0';
busyOut <= '0';
end generate gen_disabled;
end Behavioral;
| gpl-3.0 | b71bdd0a42c3fd1266bc6d23d9fa28d0 | 0.476023 | 3.808415 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/FIR_Filter/tb_lp_fir_filter.vhd | 1 | 3,073 | --------------------------------------------------------------------------------------------------
-- FIR Filter Testbench
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tb_clockgen_pkg.all;
use work.tb_read_csv_pkg.all;
use work.tb_write_csv_pkg.all;
use work.dsp_pkg.all;
use work.lp_fir_filter_pkg.all;
--This module is a test-bench for simulating the fir filter
entity tb_lp_fir_filter is
end tb_lp_fir_filter;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture sim of tb_lp_fir_filter is
constant INPUT_FILE : string
:= "X:\Education\Masters Thesis\matlab\lp_fir_filter\chirp.csv";
-- constant TEST_FILTER : coefficient_array := HIGH_PASS_21;
-- constant OUTPUT_FILE : string
-- := "X:\Education\Masters Thesis\matlab\lp_fir_filter\chirp_highpass21.csv";
-- constant TEST_FILTER : coefficient_array := LOW_PASS_41;
-- constant OUTPUT_FILE : string
-- := "X:\Education\Masters Thesis\matlab\lp_fir_filter\chirp_lowpass41.csv";
constant TEST_FILTER : coefficient_array := HIGH_PASS_101;
constant OUTPUT_FILE : string
:= "X:\Education\Masters Thesis\matlab\lp_fir_filter\chirp_highpass101.csv";
signal rst : std_logic := '0';
signal clk : std_logic := '0';
signal sig : std_logic_vector(NUM_SIG_BITS-1 downto 0) := (others => '0');
signal filtered : fir_sig := (others => '0');
begin
--Instantiate clock generator
clk1 : tb_clockgen
generic map(PERIOD => 10ns,
DUTY_CYCLE => 0.50)
port map( clk => clk);
--Instantiate file reader
reader : tb_read_csv
generic map(FILENAME => INPUT_FILE)
port map( clk => clk,
data => sig);
--Instantiate unit under test
uut : entity work.lp_fir_filter(behave)
generic map(h => TEST_FILTER)
port map( clk => clk,
rst => rst,
x => signed(sig),
y => filtered);
--Instantiate a file writer
writer : tb_write_csv
generic map(FILENAME => OUTPUT_FILE)
port map( clk => clk,
data => std_logic_vector(filtered(30 downto 15)));
--Main Process
--TODO: Add a check for end of file, once reached terminate simulation.
main: process
begin
rst <= '1';
wait for 10ns;
rst <= '0';
wait;
end process;
end sim;
| mit | f973fe856fe0aed5ddbab6396c33538c | 0.467296 | 4.41523 | false | true | false | false |
EltonBroering/Estacionamento-Inteligente-com-portas-logicas | DEC10b.vhd | 1 | 5,064 | -- Copyright (C) 1991-2012 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- PROGRAM "Quartus II 32-bit"
-- VERSION "Version 12.1 Build 177 11/07/2012 SJ Full Version"
-- CREATED "Thu Aug 1 14:59:50 2013"
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY DEC10b IS
PORT
(
P0 : IN STD_LOGIC;
P1 : IN STD_LOGIC;
P2 : IN STD_LOGIC;
P3 : IN STD_LOGIC;
P4 : IN STD_LOGIC;
display_unidade_1 : OUT STD_LOGIC;
display_unidade_2 : OUT STD_LOGIC;
display_unidade_3 : OUT STD_LOGIC;
display_unidade_4 : OUT STD_LOGIC;
display_dezena1 : OUT STD_LOGIC
);
END DEC10b;
ARCHITECTURE bdf_type OF DEC10b IS
ATTRIBUTE black_box : BOOLEAN;
ATTRIBUTE noopt : BOOLEAN;
COMPONENT \74158_0\
PORT(GN : IN STD_LOGIC;
SEL : IN STD_LOGIC;
m1A : IN STD_LOGIC;
m1B : IN STD_LOGIC;
m2A : IN STD_LOGIC;
m2B : IN STD_LOGIC;
m3A : IN STD_LOGIC;
m3B : IN STD_LOGIC;
m4A : IN STD_LOGIC;
m4B : IN STD_LOGIC;
m1YN : OUT STD_LOGIC;
m2YN : OUT STD_LOGIC;
m3YN : OUT STD_LOGIC;
m4YN : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74158_0\: COMPONENT IS true;
ATTRIBUTE noopt OF \74158_0\: COMPONENT IS true;
COMPONENT \74283_1\
PORT(CIN : IN STD_LOGIC;
A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
SUM4 : OUT STD_LOGIC;
SUM1 : OUT STD_LOGIC;
SUM2 : OUT STD_LOGIC;
SUM3 : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74283_1\: COMPONENT IS true;
ATTRIBUTE noopt OF \74283_1\: COMPONENT IS true;
COMPONENT \74684_2\
PORT(P2 : IN STD_LOGIC;
Q2 : IN STD_LOGIC;
P1 : IN STD_LOGIC;
Q1 : IN STD_LOGIC;
P0 : IN STD_LOGIC;
Q0 : IN STD_LOGIC;
P7 : IN STD_LOGIC;
Q7 : IN STD_LOGIC;
Q6 : IN STD_LOGIC;
P6 : IN STD_LOGIC;
Q5 : IN STD_LOGIC;
P5 : IN STD_LOGIC;
P4 : IN STD_LOGIC;
Q4 : IN STD_LOGIC;
Q3 : IN STD_LOGIC;
P3 : IN STD_LOGIC;
P_GR_QN : OUT STD_LOGIC);
END COMPONENT;
ATTRIBUTE black_box OF \74684_2\: COMPONENT IS true;
ATTRIBUTE noopt OF \74684_2\: COMPONENT IS true;
SIGNAL SYNTHESIZED_WIRE_27 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_1 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_3 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_4 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_5 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_6 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_7 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_8 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_9 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_10 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_28 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_29 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_30 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_31 : STD_LOGIC;
BEGIN
SYNTHESIZED_WIRE_1 <= '0';
SYNTHESIZED_WIRE_28 <= '0';
SYNTHESIZED_WIRE_29 <= '1';
SYNTHESIZED_WIRE_30 <= '0';
SYNTHESIZED_WIRE_31 <= '0';
display_dezena1 <= NOT(SYNTHESIZED_WIRE_27);
b2v_inst1 : \74158_0\
PORT MAP(GN => SYNTHESIZED_WIRE_1,
SEL => SYNTHESIZED_WIRE_27,
m1A => SYNTHESIZED_WIRE_3,
m1B => P0,
m2A => SYNTHESIZED_WIRE_4,
m2B => P1,
m3A => SYNTHESIZED_WIRE_5,
m3B => P2,
m4A => SYNTHESIZED_WIRE_6,
m4B => P3,
m1YN => SYNTHESIZED_WIRE_7,
m2YN => SYNTHESIZED_WIRE_8,
m3YN => SYNTHESIZED_WIRE_9,
m4YN => SYNTHESIZED_WIRE_10);
display_unidade_1 <= NOT(SYNTHESIZED_WIRE_7);
display_unidade_2 <= NOT(SYNTHESIZED_WIRE_8);
display_unidade_3 <= NOT(SYNTHESIZED_WIRE_9);
display_unidade_4 <= NOT(SYNTHESIZED_WIRE_10);
b2v_inst26 : \74283_1\
PORT MAP(CIN => SYNTHESIZED_WIRE_28,
A1 => P0,
A2 => P1,
B2 => SYNTHESIZED_WIRE_29,
A3 => P2,
A4 => P3,
B4 => SYNTHESIZED_WIRE_28,
B1 => SYNTHESIZED_WIRE_28,
B3 => SYNTHESIZED_WIRE_29,
SUM4 => SYNTHESIZED_WIRE_6,
SUM1 => SYNTHESIZED_WIRE_3,
SUM2 => SYNTHESIZED_WIRE_4,
SUM3 => SYNTHESIZED_WIRE_5);
b2v_inst45 : \74684_2\
PORT MAP(P2 => P2,
Q2 => SYNTHESIZED_WIRE_30,
P1 => P1,
Q1 => SYNTHESIZED_WIRE_30,
P0 => P0,
Q0 => SYNTHESIZED_WIRE_29,
P7 => SYNTHESIZED_WIRE_31,
Q7 => SYNTHESIZED_WIRE_31,
Q6 => SYNTHESIZED_WIRE_31,
P6 => SYNTHESIZED_WIRE_31,
Q5 => SYNTHESIZED_WIRE_31,
P5 => SYNTHESIZED_WIRE_31,
P4 => P4,
Q4 => SYNTHESIZED_WIRE_31,
Q3 => SYNTHESIZED_WIRE_29,
P3 => P3,
P_GR_QN => SYNTHESIZED_WIRE_27);
END bdf_type; | gpl-2.0 | b8986faa91117a4fcd6844d9dedaf637 | 0.663112 | 2.877273 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/Multirate/tb_interpolator.vhd | 1 | 3,392 | --------------------------------------------------------------------------------------------------
-- Interpolator Testbench
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tb_clockgen_pkg.all;
use work.tb_read_csv_pkg.all;
use work.tb_write_csv_pkg.all;
use work.dsp_pkg.all;
use work.interpolator_pkg.all;
--This module is a test-bench for simulating the fir filter
entity tb_interpolator is
end tb_interpolator;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture sim of tb_interpolator is
-- constant INPUT_FILE : string
-- := "X:\Education\Masters Thesis\matlab\fir_filters\singleSig_decimated.csv";
-- constant OUTPUT_FILE : string
-- := "X:\Education\Masters Thesis\matlab\fir_filters\singleSig_interpolated.csv";
-- constant INPUT_FILE : string
-- := "X:\Education\Masters Thesis\matlab\fir_filters\mixedSigs_decimated.csv";
-- constant OUTPUT_FILE : string
-- := "X:\Education\Masters Thesis\matlab\fir_filters\mixedSigs_interpolated.csv";
constant INPUT_FILE : string
:= "X:\Education\Masters Thesis\matlab\fir_filters\chirp_decimated.csv";
constant OUTPUT_FILE : string
:= "X:\Education\Masters Thesis\matlab\fir_filters\chirp_interpolated.csv";
signal rst : std_logic := '0';
signal clk_10ns : std_logic := '0';
signal clk_20ns : std_logic := '0';
signal sig_in : sig := (others => '0');
signal sig_out : sig := (others => '0');
begin
--Instantiate clock generator
clk1 : tb_clockgen
generic map(PERIOD => 10ns,
DUTY_CYCLE => 0.50)
port map( clk => clk_10ns);
clk2 : tb_clockgen
generic map(PERIOD => 20ns,
DUTY_CYCLE => 0.50)
port map( clk => clk_20ns);
--Instantiate file reader
reader : tb_read_csv
generic map(FILENAME => INPUT_FILE)
port map( clk => clk_20ns,
sig(data) => sig_in);
--Instantiate unit under test
uut : entity work.interpolator(behave)
-- generic map(h => LOW_PASS)
generic map(h => PR_SYNTHESIS_LOW)
port map( clk_high => clk_10ns,
clk_low => clk_20ns,
rst => rst,
sig_low => sig_in,
sig_high => sig_out);
--Instantiate a file writer
writer : tb_write_csv
generic map(FILENAME => OUTPUT_FILE)
port map( clk => clk_10ns,
data => std_logic_vector(sig_out));
--Main Process
--TODO: Add a check for end of file, once reached terminate simulation.
main: process
begin
rst <= '1';
wait for 36ns;
rst <= '0';
wait;
end process;
end sim;
| mit | 04a87e61ac51c089cc09100374274199 | 0.473762 | 4.3543 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/Code8b10bPkg.vhd | 1 | 15,864 | -------------------------------------------------------------------------------
-- Title :
-------------------------------------------------------------------------------
-- File : Code8b10bPkg.vhd
-- Author : Benjamin Reese <[email protected]>
-- Company : SLAC National Accelerator Laboratory
-- Created : 2013-05-02
-- Last update: 2014-07-14
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013 SLAC National Accelerator Laboratory
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.StdRtlPkg.all;
package Code8b10bPkg is
-------------------------------------------------------------------------------------------------
-- Control Code Constants
-------------------------------------------------------------------------------------------------
constant K_28_0_C : slv(7 downto 0) := "00011100"; -- K28.0, 0x1C
constant K_28_1_C : slv(7 downto 0) := "00111100"; -- K28.1, 0x3C (Comma)
constant K_28_2_C : slv(7 downto 0) := "01011100"; -- K28.2, 0x5C
constant K_28_3_C : slv(7 downto 0) := "01111100"; -- K28.3, 0x7C
constant K_28_4_C : slv(7 downto 0) := "10011100"; -- K28.4, 0x9C
constant K_28_5_C : slv(7 downto 0) := "10111100"; -- K28.5, 0xBC (Comma)
constant K_28_6_C : slv(7 downto 0) := "11011100"; -- K28.6, 0xDC
constant K_28_7_C : slv(7 downto 0) := "11111100"; -- K28.7, 0xFC (Comma)
constant K_23_7_C : slv(7 downto 0) := "11110111"; -- K23.7, 0xF7
constant K_27_7_C : slv(7 downto 0) := "11111011"; -- K27.7, 0xFB
constant K_29_7_C : slv(7 downto 0) := "11111101"; -- K29.7, 0xFD
constant K_30_7_C : slv(7 downto 0) := "11111110"; -- K30.7, 0xFE
constant D_10_2_C : slv(7 downto 0) := "01001010"; -- D10.2, 0x4A
constant D_21_5_C : slv(7 downto 0) := "10110101"; -- D21.5, 0xB5
procedure encode8b10b (
dataIn : in slv(7 downto 0);
dataKIn : in sl;
dispIn : in sl;
dataOut : out slv(9 downto 0);
dispOut : out sl);
procedure decode8b10b (
dataIn : in slv(9 downto 0);
dispIn : in sl;
dataOut : out slv(7 downto 0);
dataKOut : out sl;
dispOut : out sl;
codeErr : out sl;
dispErr : out sl);
end package Code8b10bPkg;
package body Code8b10bPkg is
procedure encode8b10b (
dataIn : in slv(7 downto 0);
dataKIn : in sl;
dispIn : in sl;
dataOut : out slv(9 downto 0);
dispOut : out sl)
is
variable ai, bi, ci, di, ei, fi, gi, hi, ki : sl;
variable aeqb, ceqd : sl;
variable l22, l40, l04, l13, l31 : sl;
variable ao, bo, co, do, eo, io, fo, go, ho, jo : sl;
variable pd1s6, nd1s6, ndos6, pdos6 : sl;
variable alt6, alt7 : sl;
variable nd1s4, pd1s4, ndos4, pdos4 : sl;
variable illegalk : sl;
variable compls6, disp6, compls4 : sl;
begin
ai := dataIn(0);
bi := dataIn(1);
ci := dataIn(2);
di := dataIn(3);
ei := dataIn(4);
fi := dataIn(5);
gi := dataIn(6);
hi := dataIn(7);
ki := dataKIn;
aeqb := (ai and bi) or (not ai and not bi);
ceqd := (ci and di) or (not ci and not di);
l22 := (ai and bi and not ci and not di) or
(ci and di and not ai and not bi) or
(not aeqb and not ceqd);
l40 := ai and bi and ci and di;
l04 := not ai and not bi and not ci and not di;
l13 := (not aeqb and not ci and not di) or
(not ceqd and not ai and not bi);
l31 := (not aeqb and ci and di) or
(not ceqd and ai and bi);
-- The 5B/6B encoding
ao := ai;
bo := (bi and not l40) or l04;
co := l04 or ci or (ei and di and not ci and not bi and not ai);
do := di and not (ai and bi and ci);
eo := (ei or l13) and not (ei and di and not ci and not bi and not ai);
io := (l22 and not ei) or
(ei and not di and not ci and not (ai and bi)) or -- D16, D17, D18
(ei and l40) or
(ki and ei and di and ci and not bi and not ai) or -- K.28
(ei and not di and ci and not bi and not ai);
-- pds16 indicates cases where d-1 is assumed + to get our encoded value
pd1s6 := (ei and di and not ci and not bi and not ai) or (not ei and not l22 and not l31);
-- nds16 indicates cases where d-1 is assumed - to get our encoded value
nd1s6 := ki or (ei and not l22 and not l13) or (not ei and not di and ci and bi and ai);
-- ndos6 is pds16 cases where d-1 is + yields - disp out - all of them
ndos6 := pd1s6;
-- pdos6 is nds16 cases where d-1 is - yields + disp out - all but one
pdos6 := ki or (ei and not l22 and not l13);
-- some Dx.7 and all Kx.7 cases result in run length of 5 case unless
-- an alternate coding is used (referred to as Dx.A7, normal is Dx.P7)
-- specifically, D11, D13, D14, D17, D18, D19.
if (dispIn = '1') then
alt6 := (not ei and di and l31);
else
alt6 := (ei and not di and l13);
end if;
alt7 := fi and gi and hi and (ki or alt6);
fo := fi and not alt7;
go := gi or (not fi and not gi and not hi);
ho := hi;
jo := (not hi and (gi xor fi)) or alt7;
-- nd1s4 is cases where d-1 is assumed - to get our encoded value
nd1s4 := fi and gi;
-- pd1s4 is cases where d-1 is assumed + to get our encoded value
pd1s4 := (not fi and not gi) or (ki and ((fi and not gi) or (not fi and gi)));
-- ndos4 is pd1s4 cases where d-1 is + yields - disp out - just some
ndos4 := (not fi and not gi);
-- pdos4 is nd1s4 cases where d-1 is - yields + disp out
pdos4 := fi and gi and hi;
-- only legal K codes are K28.0- > .7, K23/27/29/30.7
-- K28.0- > 7 is ei = di = ci = 1, bi = ai = 0
-- K23 is 10111
-- K27 is 11011
-- K29 is 11101
-- K30 is 11110 - so K23/27/29/30 are ei and l31
illegalk := ki and
(ai or bi or not ci or not di or not ei) and -- not K28.0- > 7
(not fi or not gi or not hi or not ei or not l31); -- not K23/27/29/30.7
-- now determine whether to do the complementing
-- complement if prev disp is - and pd1s6 is set, or + and nd1s6 is set
compls6 := (pd1s6 and not dispin) or (nd1s6 and dispin);
-- disparity out of 5b6b is disp in with pdso6 and ndso6
-- pds16 indicates cases where d-1 is assumed + to get our encoded value
-- ndos6 is cases where d-1 is + yields - disp out
-- nds16 indicates cases where d-1 is assumed - to get our encoded value
-- pdos6 is cases where d-1 is - yields + disp out
-- disp toggles in all ndis16 cases, and all but that 1 nds16 case
disp6 := dispin xor (ndos6 or pdos6);
compls4 := (pd1s4 and not disp6) or (nd1s4 and disp6);
dispOut := disp6 xor (ndos4 or pdos4);
dataOut := (jo xor compls4) & (ho xor compls4) &
(go xor compls4) & (fo xor compls4) &
(io xor compls6) & (eo xor compls6) &
(do xor compls6) & (co xor compls6) &
(bo xor compls6) & (ao xor compls6);
end procedure encode8b10b;
procedure decode8b10b (
dataIn : in slv(9 downto 0);
dispIn : in sl;
dataOut : out slv(7 downto 0);
dataKOut : out sl;
dispOut : out sl;
codeErr : out sl;
dispErr : out sl)
is
variable ai, bi, ci, di, ei, ii, fi, gi, hi, ji : sl;
variable aeqb, ceqd : sl;
variable p22, p13, p31, p40, p04 : sl;
variable disp6a, disp6a2, disp6a0, disp6b : sl;
variable p22bceeqi, p22bncneeqi, p13in, p31i, p13dei : sl;
variable p22aceeqi, p22ancneeqi : sl;
variable p13en, anbnenin, abei, cdei, cndnenin : sl;
variable p22enin, p22ei, p31dnenin, p31e : sl;
variable compa, compb, compc, compd, compe : sl;
variable ao, bo, co, do, eo, ko, fo, go, ho : sl;
variable feqg, heqj, fghj22, fghjp13, fghjp31 : sl;
variable alt7, k28, k28p : sl;
variable disp6p, disp6n, disp4p, disp4n : sl;
begin
ai := dataIn(0);
bi := dataIn(1);
ci := dataIn(2);
di := dataIn(3);
ei := dataIn(4);
ii := dataIn(5);
fi := dataIn(6);
gi := dataIn(7);
hi := dataIn(8);
ji := dataIn(9);
aeqb := (ai and bi) or (not ai and not bi);
ceqd := (ci and di) or (not ci and not di);
p22 := (ai and bi and not ci and not di) or
(ci and di and not ai and not bi) or
(not aeqb and not ceqd);
p13 := (not aeqb and not ci and not di) or
(not ceqd and not ai and not bi);
p31 := (not aeqb and ci and di) or
(not ceqd and ai and bi);
p40 := ai and bi and ci and di;
p04 := not ai and not bi and not ci and not di;
disp6a := p31 or (p22 and dispin); -- pos disp if p22 and was pos, or p31.
disp6a2 := p31 and dispin; -- disp is ++ after 4 bits
disp6a0 := p13 and not dispin; -- -- disp after 4 bits
disp6b := (((ei and ii and not disp6a0) or (disp6a and (ei or ii)) or disp6a2 or
(ei and ii and di)) and (ei or ii or di)) ;
-- The 5B/6B decoding special cases where ABCDE not = abcde
p22bceeqi := p22 and bi and ci and (ei xnor ii);
p22bncneeqi := p22 and not bi and not ci and (ei xnor ii);
p13in := p13 and not ii;
p31i := p31 and ii;
p13dei := p13 and di and ei and ii;
p22aceeqi := p22 and ai and ci and (ei xnor ii);
p22ancneeqi := p22 and not ai and not ci and (ei xnor ii);
p13en := p13 and not ei;
anbnenin := not ai and not bi and not ei and not ii;
abei := ai and bi and ei and ii;
cdei := ci and di and ei and ii;
cndnenin := not ci and not di and not ei and not ii;
-- non-zero disparity cases:
p22enin := p22 and not ei and not ii;
p22ei := p22 and ei and ii;
-- p13in := p12 and not ii ;
-- p31i := p31 and ii ;
p31dnenin := p31 and not di and not ei and not ii;
-- p13dei := p13 and di and ei and ii ;
p31e := p31 and ei;
compa := p22bncneeqi or p31i or p13dei or p22ancneeqi or
p13en or abei or cndnenin;
compb := p22bceeqi or p31i or p13dei or p22aceeqi or
p13en or abei or cndnenin;
compc := p22bceeqi or p31i or p13dei or p22ancneeqi or
p13en or anbnenin or cndnenin;
compd := p22bncneeqi or p31i or p13dei or p22aceeqi or
p13en or abei or cndnenin;
compe := p22bncneeqi or p13in or p13dei or p22ancneeqi or
p13en or anbnenin or cndnenin;
ao := ai xor compa;
bo := bi xor compb;
co := ci xor compc;
do := di xor compd;
eo := ei xor compe;
feqg := (fi and gi) or (not fi and not gi);
heqj := (hi and ji) or (not hi and not ji);
fghj22 := (fi and gi and not hi and not ji) or
(not fi and not gi and hi and ji) or
(not feqg and not heqj);
fghjp13 := (not feqg and not hi and not ji) or
(not heqj and not fi and not gi);
fghjp31 := ((not feqg) and hi and ji) or
(not heqj and fi and gi);
dispout := (fghjp31 or (disp6b and fghj22) or (hi and ji)) and (hi or ji);
ko := ((ci and di and ei and ii) or (not ci and not di and not ei and not ii) or
(p13 and not ei and ii and gi and hi and ji) or
(p31 and ei and not ii and not gi and not hi and not ji)) ;
alt7 := (fi and not gi and not hi and -- 1000 cases, where disp6b is 1
((dispin and ci and di and not ei and not ii) or ko or
(dispin and not ci and di and not ei and not ii))) or
(not fi and gi and hi and -- 0111 cases, where disp6b is 0
((not dispin and not ci and not di and ei and ii) or ko or
(not dispin and ci and not di and ei and ii))) ;
k28 := (ci and di and ei and ii) or not (ci or di or ei or ii);
-- k28 with positive disp into fghi - .1, .2, .5, and .6 special cases
k28p := not (ci or di or ei or ii);
fo := (ji and not fi and (hi or not gi or k28p)) or
(fi and not ji and (not hi or gi or not k28p)) or
(k28p and gi and hi) or
(not k28p and not gi and not hi);
go := (ji and not fi and (hi or not gi or not k28p)) or
(fi and not ji and (not hi or gi or k28p)) or
(not k28p and gi and hi) or
(k28p and not gi and not hi);
ho := ((ji xor hi) and not ((not fi and gi and not hi and ji and not k28p) or (not fi and gi and hi and not ji and k28p) or
(fi and not gi and not hi and ji and not k28p) or (fi and not gi and hi and not ji and k28p))) or
(not fi and gi and hi and ji) or (fi and not gi and not hi and not ji);
disp6p := (p31 and (ei or ii)) or (p22 and ei and ii);
disp6n := (p13 and not (ei and ii)) or (p22 and not ei and not ii);
disp4p := fghjp31;
disp4n := fghjp13;
codeErr := p40 or p04 or (fi and gi and hi and ji) or (not fi and not gi and not hi and not ji) or
(p13 and not ei and not ii) or (p31 and ei and ii) or
(ei and ii and fi and gi and hi) or (not ei and not ii and not fi and not gi and not hi) or
(ei and not ii and gi and hi and ji) or (not ei and ii and not gi and not hi and not ji) or
(not p31 and ei and not ii and not gi and not hi and not ji) or
(not p13 and not ei and ii and gi and hi and ji) or
(((ei and ii and not gi and not hi and not ji) or
(not ei and not ii and gi and hi and ji)) and
not ((ci and di and ei) or (not ci and not di and not ei))) or
(disp6p and disp4p) or (disp6n and disp4n) or
(ai and bi and ci and not ei and not ii and ((not fi and not gi) or fghjp13)) or
(not ai and not bi and not ci and ei and ii and ((fi and gi) or fghjp31)) or
(fi and gi and not hi and not ji and disp6p) or
(not fi and not gi and hi and ji and disp6n) or
(ci and di and ei and ii and not fi and not gi and not hi) or
(not ci and not di and not ei and not ii and fi and gi and hi);
dataOut := ho & go & fo & eo & do & co & bo & ao;
dataKOut := ko;
--my disp err fires for any legal codes that violate disparity, may fire for illegal codes
dispErr := ((dispin and disp6p) or (disp6n and not dispin) or
(dispin and not disp6n and fi and gi) or
(dispin and ai and bi and ci) or
(dispin and not disp6n and disp4p) or
(not dispin and not disp6p and not fi and not gi) or
(not dispin and not ai and not bi and not ci) or
(not dispin and not disp6p and disp4n) or
(disp6p and disp4p) or (disp6n and disp4n)) ;
end procedure decode8b10b;
end package body Code8b10bPkg;
| gpl-3.0 | cb6636fc857720b68b692877a9ff6fa1 | 0.523512 | 3.353911 | false | false | false | false |
gyurco/ZX_Spectrum-128K_MIST | YM2149.vhd | 1 | 23,503 | -- changes for seperate audio outputs and enable now enables cpu access as well
--
-- A simulation model of YM2149 (AY-3-8910 with bells on)
-- Copyright (c) MikeJ - Jan 2005
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- You are responsible for any legal issues arising from your use of this code.
--
-- The latest version of this file can be found at: www.fpgaarcade.com
--
-- Email [email protected]
--
-- Revision list
--
-- version 001 initial release
--
-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA
--
-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V)
-- vol 15 .. 0
-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132
-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order
-- to produced all the required values.
-- (The first part of the curve is a bit steeper and the last bit is more linear than expected)
--
-- NOTE, when MIXER_VOLTABLE = '0', this component uses LINEAR mixing of the three analogue channels,
-- and is only accurate for designs where the outputs are buffered and not simply wired together.
-- The ouput level is more complex in that case and requires a larger table (MIXER_VOLTABLE = '1').
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity YM2149 is
generic (
MIXER_VOLTABLE : std_logic := '0'
);
port (
-- data bus
I_DA : in std_logic_vector(7 downto 0);
O_DA : out std_logic_vector(7 downto 0);
O_DA_OE_L : out std_logic;
-- control
I_A9_L : in std_logic := '0';
I_A8 : in std_logic := '1';
I_BDIR : in std_logic;
I_BC2 : in std_logic := '1';
I_BC1 : in std_logic;
I_SEL_L : in std_logic := '1';
I_STEREO : in std_logic;
-- separate channel output
O_AUDIO : out std_logic_vector(7 downto 0);
O_CHAN : out std_logic_vector(1 downto 0);
-- mixed output
O_AUDIO_L : out std_logic_vector(9 downto 0);
O_AUDIO_R : out std_logic_vector(9 downto 0);
-- port a
I_IOA : in std_logic_vector(7 downto 0);
O_IOA : out std_logic_vector(7 downto 0);
O_IOA_OE_L : out std_logic;
-- port b
I_IOB : in std_logic_vector(7 downto 0);
O_IOB : out std_logic_vector(7 downto 0);
O_IOB_OE_L : out std_logic;
ENA : in std_logic; -- clock enable for higher speed operation
RESET_L : in std_logic;
CLK : in std_logic
);
end;
architecture RTL of YM2149 is
type array_16x8 is array (0 to 15) of std_logic_vector( 7 downto 0);
type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0);
signal cnt_div : std_logic_vector(3 downto 0) := (others => '0');
signal cnt_div_t1 : std_logic_vector(3 downto 0);
signal noise_div : std_logic := '0';
signal ena_div : std_logic;
signal ena_div_noise : std_logic;
signal poly17 : std_logic_vector(16 downto 0) := (others => '0');
-- registers
signal addr : std_logic_vector(7 downto 0);
signal busctrl_addr : std_logic;
signal busctrl_we : std_logic;
signal busctrl_re : std_logic;
signal reg : array_16x8;
signal env_reset : std_logic;
signal ioa_inreg : std_logic_vector(7 downto 0);
signal iob_inreg : std_logic_vector(7 downto 0);
signal noise_gen_cnt : std_logic_vector(4 downto 0);
signal noise_gen_op : std_logic;
signal tone_gen_cnt : array_3x12 := (others => (others => '0'));
signal tone_gen_op : std_logic_vector(3 downto 1) := "000";
signal env_gen_cnt : std_logic_vector(15 downto 0);
signal env_ena : std_logic;
signal env_hold : std_logic;
signal env_inc : std_logic;
signal env_vol : std_logic_vector(4 downto 0);
signal tone_ena_l : std_logic;
signal tone_src : std_logic;
signal noise_ena_l : std_logic;
signal chan_vol : std_logic_vector(4 downto 0);
signal dac_amp : std_logic_vector(7 downto 0);
signal vol_l : std_logic_vector(9 downto 0);
signal vol_r : std_logic_vector(9 downto 0);
signal vol_mixer_l : std_logic_vector(9 downto 0);
signal vol_mixer_r : std_logic_vector(9 downto 0);
signal vol_table_in_l : std_logic_vector(11 downto 0);
signal vol_table_in_r : std_logic_vector(11 downto 0);
signal vol_table_out_l : std_logic_vector(9 downto 0);
signal vol_table_out_r : std_logic_vector(9 downto 0);
begin
-- cpu i/f
p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8)
variable cs : std_logic;
variable sel : std_logic_vector(2 downto 0);
begin
-- BDIR BC2 BC1 MODE
-- 0 0 0 inactive
-- 0 0 1 address
-- 0 1 0 inactive
-- 0 1 1 read
-- 1 0 0 address
-- 1 0 1 inactive
-- 1 1 0 write
-- 1 1 1 read
busctrl_addr <= '0';
busctrl_we <= '0';
busctrl_re <= '0';
cs := '0';
if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then
cs := '1';
end if;
sel := (I_BDIR & I_BC2 & I_BC1);
case sel is
when "000" => null;
when "001" => busctrl_addr <= '1';
when "010" => null;
when "011" => busctrl_re <= cs;
when "100" => busctrl_addr <= '1';
when "101" => null;
when "110" => busctrl_we <= cs;
when "111" => busctrl_addr <= '1';
when others => null;
end case;
end process;
p_oe : process(busctrl_re)
begin
-- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns
O_DA_OE_L <= not (busctrl_re);
end process;
--
-- CLOCKED
--
p_waddr : process(RESET_L, CLK)
begin
-- looks like registers are latches in real chip, but the address is caught at the end of the address state.
if (RESET_L = '0') then
addr <= (others => '0');
elsif rising_edge(CLK) then
if (busctrl_addr = '1') then
addr <= I_DA;
end if;
end if;
end process;
p_wdata : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
reg <= (others => (others => '0'));
env_reset <= '1';
elsif rising_edge(CLK) then
env_reset <= '0';
if (busctrl_we = '1') then
reg(to_integer(unsigned(addr(3 downto 0)))) <= I_DA;
if addr(3 downto 0) = x"D" then
env_reset <= '1';
end if;
end if;
end if;
end process;
p_rdata : process(busctrl_re, addr, reg, ioa_inreg, iob_inreg)
begin
O_DA <= (others => '0'); -- 'X'
if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator
case addr(3 downto 0) is
when x"0" => O_DA <= reg(0) ;
when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ;
when x"2" => O_DA <= reg(2) ;
when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ;
when x"4" => O_DA <= reg(4) ;
when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ;
when x"6" => O_DA <= "000" & reg(6)(4 downto 0) ;
when x"7" => O_DA <= reg(7) ;
when x"8" => O_DA <= "000" & reg(8)(4 downto 0) ;
when x"9" => O_DA <= "000" & reg(9)(4 downto 0) ;
when x"A" => O_DA <= "000" & reg(10)(4 downto 0) ;
when x"B" => O_DA <= reg(11);
when x"C" => O_DA <= reg(12);
when x"D" => O_DA <= "0000" & reg(13)(3 downto 0);
when x"E" => if (reg(7)(6) = '0') then -- input
O_DA <= ioa_inreg;
else
O_DA <= reg(14) and ioa_inreg; -- read output reg
end if;
when x"F" => if (Reg(7)(7) = '0') then
O_DA <= iob_inreg;
else
O_DA <= reg(15) and iob_inreg;
end if;
when others => null;
end case;
end if;
end process;
--
p_divider : process
begin
wait until rising_edge(CLK);
-- / 8 when SEL is high and /16 when SEL is low
if (ENA = '1') then
ena_div <= '0';
ena_div_noise <= '0';
if (cnt_div = "0000") then
cnt_div <= (not I_SEL_L) & "111";
ena_div <= '1';
noise_div <= not noise_div;
if (noise_div = '1') then
ena_div_noise <= '1';
end if;
else
cnt_div <= cnt_div - "1";
end if;
end if;
end process;
p_noise_gen : process
variable noise_gen_comp : std_logic_vector(4 downto 0);
variable poly17_zero : std_logic;
begin
wait until rising_edge(CLK);
if (reg(6)(4 downto 0) = "00000") then
noise_gen_comp := "00000";
else
noise_gen_comp := (reg(6)(4 downto 0) - "1");
end if;
poly17_zero := '0';
if (poly17 = "00000000000000000") then poly17_zero := '1'; end if;
if (ENA = '1') then
if (ena_div_noise = '1') then -- divider ena
if (noise_gen_cnt >= noise_gen_comp) then
noise_gen_cnt <= "00000";
poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1);
else
noise_gen_cnt <= (noise_gen_cnt + "1");
end if;
end if;
end if;
end process;
noise_gen_op <= poly17(0);
p_tone_gens : process
variable tone_gen_freq : array_3x12;
variable tone_gen_comp : array_3x12;
begin
wait until rising_edge(CLK);
-- looks like real chips count up - we need to get the Exact behaviour ..
tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0);
tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2);
tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4);
-- period 0 = period 1
for i in 1 to 3 loop
if (tone_gen_freq(i) = x"000") then
tone_gen_comp(i) := x"000";
else
tone_gen_comp(i) := (tone_gen_freq(i) - "1");
end if;
end loop;
if (ENA = '1') then
for i in 1 to 3 loop
if (ena_div = '1') then -- divider ena
if (tone_gen_cnt(i) >= tone_gen_comp(i)) then
tone_gen_cnt(i) <= x"000";
tone_gen_op(i) <= not tone_gen_op(i);
else
tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1");
end if;
end if;
end loop;
end if;
end process;
p_envelope_freq : process
variable env_gen_freq : std_logic_vector(15 downto 0);
variable env_gen_comp : std_logic_vector(15 downto 0);
begin
wait until rising_edge(CLK);
env_gen_freq := reg(12) & reg(11);
-- envelope freqs 1 and 0 are the same.
if (env_gen_freq = x"0000") then
env_gen_comp := x"0000";
else
env_gen_comp := (env_gen_freq - "1");
end if;
if (ENA = '1') then
env_ena <= '0';
if (ena_div = '1') then -- divider ena
if (env_gen_cnt >= env_gen_comp) then
env_gen_cnt <= x"0000";
env_ena <= '1';
else
env_gen_cnt <= (env_gen_cnt + "1");
end if;
end if;
end if;
end process;
p_envelope_shape : process(env_reset, reg, CLK)
variable is_bot : boolean;
variable is_bot_p1 : boolean;
variable is_top_m1 : boolean;
variable is_top : boolean;
begin
-- envelope shapes
-- C AtAlH
-- 0 0 x x \___
--
-- 0 1 x x /___
--
-- 1 0 0 0 \\\\
--
-- 1 0 0 1 \___
--
-- 1 0 1 0 \/\/
-- ___
-- 1 0 1 1 \
--
-- 1 1 0 0 ////
-- ___
-- 1 1 0 1 /
--
-- 1 1 1 0 /\/\
--
-- 1 1 1 1 /___
if rising_edge(CLK) then
if (env_reset = '1') then
-- load initial state
if (reg(13)(2) = '0') then -- attack
env_vol <= "11111";
env_inc <= '0'; -- -1
else
env_vol <= "00000";
env_inc <= '1'; -- +1
end if;
env_hold <= '0';
else
is_bot := (env_vol = "00000");
is_bot_p1 := (env_vol = "00001");
is_top_m1 := (env_vol = "11110");
is_top := (env_vol = "11111");
if (ENA = '1' and env_ena = '1') then
if (env_hold = '0') then
if (env_inc = '1') then
env_vol <= (env_vol + "00001");
else
env_vol <= (env_vol + "11111");
end if;
end if;
-- envelope shape control.
if (reg(13)(3) = '0') then
if (env_inc = '0') then -- down
if is_bot_p1 then env_hold <= '1'; end if;
else
if is_top then env_hold <= '1'; end if;
end if;
else
if (reg(13)(0) = '1') then -- hold = 1
if (env_inc = '0') then -- down
if (reg(13)(1) = '1') then -- alt
if is_bot then env_hold <= '1'; end if;
else
if is_bot_p1 then env_hold <= '1'; end if;
end if;
else
if (reg(13)(1) = '1') then -- alt
if is_top then env_hold <= '1'; end if;
else
if is_top_m1 then env_hold <= '1'; end if;
end if;
end if;
elsif (reg(13)(1) = '1') then -- alternate
if (env_inc = '0') then -- down
if is_bot_p1 then env_hold <= '1'; end if;
if is_bot then env_hold <= '0'; env_inc <= '1'; end if;
else
if is_top_m1 then env_hold <= '1'; end if;
if is_top then env_hold <= '0'; env_inc <= '0'; end if;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
-- output mixer
p_chan_mixer : process(cnt_div, reg, tone_gen_op)
begin
tone_ena_l <= '1'; tone_src <= '1';
noise_ena_l <= '1'; chan_vol <= "00000";
case cnt_div(1 downto 0) is
when "00" =>
tone_ena_l <= reg(7)(0); tone_src <= tone_gen_op(1); chan_vol <= reg(8)(4 downto 0);
noise_ena_l <= reg(7)(3);
when "01" =>
tone_ena_l <= reg(7)(1); tone_src <= tone_gen_op(2); chan_vol <= reg(9)(4 downto 0);
noise_ena_l <= reg(7)(4);
when "10" =>
tone_ena_l <= reg(7)(2); tone_src <= tone_gen_op(3); chan_vol <= reg(10)(4 downto 0);
noise_ena_l <= reg(7)(5);
when "11" => null; -- tone gen outputs become valid on this clock
when others => null;
end case;
end process;
p_op_mixer : process
variable chan_mixed : std_logic;
variable chan_amp : std_logic_vector(4 downto 0);
begin
wait until rising_edge(CLK);
if (ENA = '1') then
chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op);
chan_amp := (others => '0');
if (chan_mixed = '1') then
if (chan_vol(4) = '0') then
if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet
chan_amp := "00000";
else
chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone)
end if;
else
chan_amp := env_vol(4 downto 0);
end if;
end if;
dac_amp <= x"00";
case chan_amp is
when "11111" => dac_amp <= x"FF";
when "11110" => dac_amp <= x"D9";
when "11101" => dac_amp <= x"BA";
when "11100" => dac_amp <= x"9F";
when "11011" => dac_amp <= x"88";
when "11010" => dac_amp <= x"74";
when "11001" => dac_amp <= x"63";
when "11000" => dac_amp <= x"54";
when "10111" => dac_amp <= x"48";
when "10110" => dac_amp <= x"3D";
when "10101" => dac_amp <= x"34";
when "10100" => dac_amp <= x"2C";
when "10011" => dac_amp <= x"25";
when "10010" => dac_amp <= x"1F";
when "10001" => dac_amp <= x"1A";
when "10000" => dac_amp <= x"16";
when "01111" => dac_amp <= x"13";
when "01110" => dac_amp <= x"10";
when "01101" => dac_amp <= x"0D";
when "01100" => dac_amp <= x"0B";
when "01011" => dac_amp <= x"09";
when "01010" => dac_amp <= x"08";
when "01001" => dac_amp <= x"07";
when "01000" => dac_amp <= x"06";
when "00111" => dac_amp <= x"05";
when "00110" => dac_amp <= x"04";
when "00101" => dac_amp <= x"03";
when "00100" => dac_amp <= x"03";
when "00011" => dac_amp <= x"02";
when "00010" => dac_amp <= x"02";
when "00001" => dac_amp <= x"01";
when "00000" => dac_amp <= x"00";
when others => null;
end case;
cnt_div_t1 <= cnt_div;
end if;
end process;
p_audio_output : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
O_AUDIO <= (others => '0');
O_CHAN <= (others => '0');
elsif rising_edge(CLK) then
if (ENA = '1') then
O_AUDIO <= dac_amp(7 downto 0);
O_CHAN <= cnt_div_t1(1 downto 0);
end if;
end if;
end process;
-- output mixer(s)
p_chan_mixer_linear : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
vol_l <= (others => '0');
vol_r <= (others => '0');
vol_mixer_l <= (others => '0');
vol_mixer_r <= (others => '0');
elsif rising_edge(CLK) then
if (ENA = '1') then
case cnt_div_t1(1 downto 0) is
when "10" => -- Channel C
vol_r <= "00" & dac_amp;
if I_STEREO = '0' then
vol_l <= "00" & dac_amp;
else
vol_l <= (others => '0');
end if;
when "01" => -- Channel B
vol_l <= vol_l + dac_amp;
vol_r <= vol_r + dac_amp;
when "00" => -- Channel A
if I_STEREO = '0' then
vol_r <= vol_r + dac_amp;
end if;
vol_l <= vol_l + dac_amp;
when "11" =>
vol_mixer_l <= vol_l;
vol_mixer_r <= vol_r;
when others => null;
end case;
end if;
end if;
end process;
VOLTABLE: if MIXER_VOLTABLE = '1' generate
p_chan_mixer_table : process
variable chan_mixed : std_logic_vector(2 downto 0);
begin
wait until rising_edge(CLK);
if (ENA = '1') then
chan_mixed(0) := (reg(7)(0) or tone_gen_op(1)) and (reg(7)(3) or noise_gen_op);
chan_mixed(1) := (reg(7)(1) or tone_gen_op(2)) and (reg(7)(4) or noise_gen_op);
chan_mixed(2) := (reg(7)(2) or tone_gen_op(3)) and (reg(7)(5) or noise_gen_op);
vol_table_in_l <= x"000";
vol_table_in_r <= x"000";
if (chan_mixed(0) = '1') then
if(I_STEREO = '1') then
if (reg(8)(4) = '0') then
vol_table_in_l(3 downto 0) <= reg(8)(3 downto 0);
else
vol_table_in_l(3 downto 0) <= env_vol(4 downto 1);
end if;
else
if (reg(8)(4) = '0') then
vol_table_in_l(3 downto 0) <= reg(8)(3 downto 0);
vol_table_in_r(3 downto 0) <= reg(8)(3 downto 0);
else
vol_table_in_l(3 downto 0) <= env_vol(4 downto 1);
vol_table_in_r(3 downto 0) <= env_vol(4 downto 1);
end if;
end if;
end if;
if (chan_mixed(1) = '1') then
if (reg(9)(4) = '0') then
vol_table_in_l(7 downto 4) <= reg(9)(3 downto 0);
vol_table_in_r(7 downto 4) <= reg(9)(3 downto 0);
else
vol_table_in_l(7 downto 4) <= env_vol(4 downto 1);
vol_table_in_r(7 downto 4) <= env_vol(4 downto 1);
end if;
end if;
if (chan_mixed(2) = '1') then
if(I_STEREO = '1') then
if (reg(10)(4) = '0') then
vol_table_in_r(11 downto 8) <= reg(10)(3 downto 0);
else
vol_table_in_r(11 downto 8) <= env_vol(4 downto 1);
end if;
else
if (reg(10)(4) = '0') then
vol_table_in_l(11 downto 8) <= reg(10)(3 downto 0);
vol_table_in_r(11 downto 8) <= reg(10)(3 downto 0);
else
vol_table_in_l(11 downto 8) <= env_vol(4 downto 1);
vol_table_in_r(11 downto 8) <= env_vol(4 downto 1);
end if;
end if;
end if;
end if;
end process;
u_vol_table : work.vol_table
port map (
CLK => clk,
ADDR_A => vol_table_in_l,
DATA_A => vol_table_out_l,
ADDR_B => vol_table_in_r,
DATA_B => vol_table_out_r
);
end generate; -- VOLTABLE
NO_VOLTABLE: if MIXER_VOLTABLE = '0' generate
vol_table_out_l <= (others => '0');
vol_table_out_r <= (others => '0');
end generate;
-- mixed audio output
p_vol_out : process
variable chan_mixed : std_logic;
variable chan_amp : std_logic_vector(4 downto 0);
begin
wait until rising_edge(CLK);
if (RESET_L = '0') then
O_AUDIO_L <= (others => '0');
O_AUDIO_R <= (others => '0');
else
if (MIXER_VOLTABLE = '1') then
O_AUDIO_L <= vol_table_out_l;
O_AUDIO_R <= vol_table_out_r;
else
O_AUDIO_L <= vol_mixer_l;
O_AUDIO_R <= vol_mixer_r;
end if;
end if;
end process;
-- IO ports
p_io_ports : process(reg)
begin
O_IOA <= reg(14);
O_IOA_OE_L <= not reg(7)(6);
O_IOB <= reg(15);
O_IOB_OE_L <= not reg(7)(7);
end process;
p_io_ports_inreg : process
begin
wait until rising_edge(CLK);
ioa_inreg <= I_IOA;
iob_inreg <= I_IOB;
end process;
end architecture RTL;
| gpl-2.0 | 084f60eb35b157de829efe6219701588 | 0.505297 | 3.22489 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/Multirate/multirate_fir_filter_imp.vhd | 1 | 1,594 | --------------------------------------------------------------------------------------------------
-- Multirate Filter Implementation
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dsp_pkg.all;
use work.multirate_fir_filter_pkg.all;
--This module is a top-level for implementing the fir filter
entity multirate_fir_filter_imp is
port( clk_low : in std_logic;
clk_high : in std_logic;
rst : in std_logic;
x : in sig;
y : out sig);
end multirate_fir_filter_imp;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture imp of multirate_fir_filter_imp is
begin
--Instantiate unit under test
uut : entity work.multirate_fir_filter(behave)
generic map(h => LOW_PASS_41)
port map( clk_low => clk_low,
clk_high => clk_high,
rst => rst,
x => x,
y => y);
end imp;
| mit | c3cea5007726b4e08d92778d2e6ef287 | 0.331242 | 5.796364 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/tx_arbitrator.vhd | 2 | 3,035 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:03:30 06/04/2011
-- Design Name:
-- Module Name: tx_arbitrator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: arbitrate between two sources that want to transmit onto a bus
-- handles arbitration and multiplexing
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - Made sticky on port M1 to optimise access on this port and allow immediate grant
-- Revision 0.03 - Added first
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tx_arbitrator is
port (
clk : in std_logic;
reset : in std_logic;
req_1 : in std_logic;
grant_1 : out std_logic;
data_1 : in std_logic_vector(7 downto 0); -- data byte to tx
valid_1 : in std_logic; -- tdata is valid
first_1 : in std_logic; -- indicates first byte of frame
last_1 : in std_logic; -- indicates last byte of frame
req_2 : in std_logic;
grant_2 : out std_logic;
data_2 : in std_logic_vector(7 downto 0); -- data byte to tx
valid_2 : in std_logic; -- tdata is valid
first_2 : in std_logic; -- indicates first byte of frame
last_2 : in std_logic; -- indicates last byte of frame
data : out std_logic_vector(7 downto 0); -- data byte to tx
valid : out std_logic; -- tdata is valid
first : out std_logic; -- indicates first byte of frame
last : out std_logic -- indicates last byte of frame
);
end tx_arbitrator;
architecture Behavioral of tx_arbitrator is
type grant_type is (M1,M2);
signal grant : grant_type;
begin
combinatorial : process (
grant,
data_1, valid_1, first_1, last_1,
data_2, valid_2, first_2, last_2
)
begin
-- grant outputs
case grant is
when M1 =>
grant_1 <= '1';
grant_2 <= '0';
when M2 =>
grant_1 <= '0';
grant_2 <= '1';
end case;
-- multiplexer
if grant = M1 then
data <= data_1;
valid <= valid_1;
first <= first_1;
last <= last_1;
else
data <= data_2;
valid <= valid_2;
first <= first_2;
last <= last_2;
end if;
end process;
sequential : process (clk, reset, req_1, req_2, grant)
begin
if rising_edge(clk) then
if reset = '1' then
grant <= M1;
else
case grant is
when M1 =>
if req_1 = '1' then
grant <= M1;
elsif req_2 = '1' then
grant <= M2;
end if;
when M2 =>
if req_2 = '1' then
grant <= M2;
else
grant <= M1;
end if;
end case;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 73882ccab33af5917d7a88611624ca0e | 0.512356 | 3.266954 | false | false | false | false |
azeemshaikh38/PipelinedProcessorWithInterrupts | Processor/fech_mem.vhd | 1 | 5,113 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fetch_mem is
port(
clk, rst : in std_logic;
read_addr : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(15 downto 0));
end fetch_mem;
architecture mixed of fetch_mem is
type mem_type is array(255 downto 0) of std_logic_vector(15 downto 0);
signal mem_data : mem_type;
begin
process(clk, rst)
begin
if (rst = '1') then
--mem_data(0) <= X"0000";
--mem_data(1) <= X"A000"; --load R0 <= Mem(0) //R0 = 0x0A
--mem_data(2) <= X"A101"; --load R1 <= Mem(1) //R0 = 0x02
--mem_data(3) <= X"2001"; -- add R0 <= R0 + R1
--mem_data(4) <= X"A202"; --load R2
--mem_data(5) <= X"0000"; --nop
--mem_data(6) <= X"2001"; --add R0 <= R0 + R1 //R0 = 0x0C
--mem_data(7) <= X"0000";
--mem_data(8) <= X"B000"; --store Mem(0) <= R0
--mem_data(9) <= X"8021";
--mem_data(4) <= X"A101"; --load R1 <= Mem(1) //R1 = 0x02
--mem_data(5) <= X"0000"; --nop
--mem_data(6) <= X"B101"; --store Mem(1) <= R1
--mem_data(4) <= X"A202"; --load R2 <= Mem(2) //R2 = 0x31
--mem_data(5) <= X"2001"; --add R0 <= R0 + R1 //R0 = 0x0C
--mem_data(6) <= X"B001"; --store Mem(1) <= R0 //Mem(1) = 0x0C
--mem_data(6) <= X"2101"; --sub R0 <= R0 - R1 //R0 = 0x0B
--mem_data(7) <= X"B001"; --store Mem(1) <= R0 //Mem(1) = 0x0B
--mem_data(8) <= X"9011"; --store Mem(R1) <= R1 //Mem(49) = 0x31
--mem_data(9) <= X"A201"; --load R2 <= Mem(1) //R2 = 0x0B
--mem_data(10) <= X"8031"; --load R3 <= Mem(R1) //R3 = 0x31
--mem_data(11) <= X"5600"; --clear R0 //R0 = 0
--mem_data(12) <= X"5710"; --set R1 //R1 = 1
--mem_data(13) <= X"5F10"; --if (R1<R0) set R1=1
--mem_data(14) <= X"5F01"; --if (R0<R1) set R0=1 //R0 = 1
--mem_data(15) <= X"C000"; --jump
mem_data(0) <= X"0000";
mem_data(1) <= X"A000"; --load R0 <= Mem(0) //R0 = 0x0A
mem_data(2) <= X"A101"; --load R1 <= Mem(1) //R1 = 0x02
mem_data(3) <= X"8011"; --load R1 <= Mem(R1) //R1 = 0x31
mem_data(4) <= X"1001"; --add R0 <= R0 + X"01" //R0 = 0x0B
mem_data(5) <= X"2001"; --add R0 <= R0 + R1 //R0 = 0x3C
mem_data(6) <= X"2101"; --sub R0 <= R0 - R1 //R0 = 0x0B
mem_data(7) <= X"B001"; --store Mem(1) <= R0 //Mem(1) = 0x0B
mem_data(8) <= X"9011"; --store Mem(R1) <= R1 //Mem(49) = 0x31
mem_data(9) <= X"A201"; --load R2 <= Mem(1) //R2 = 0x0B
mem_data(10) <= X"8031"; --load R3 <= Mem(R1) //R3 = 0x31
mem_data(11) <= X"D00F"; --branch if R0 is zero
mem_data(12) <= X"5600"; --clear R0 //R0 = 0
mem_data(13) <= X"5710"; --set R1 //R1 = 1
mem_data(14) <= X"E110"; --branch if R1 is not zero
mem_data(15) <= X"5F10"; --if (R1<R0) set R1=1
mem_data(16) <= X"5F01"; --if (R0<R1) set R0=1 //R0 = 1
mem_data(17) <= X"5831"; --mv R3, R1 //R3 = 1
mem_data(18) <= X"C028"; --jump // PC = 40
mem_data(19) <= X"B300"; --store Mem(0) <= R3 //Mem(0) = 0x31
mem_data(20) <= X"1001"; --add R0 <= R0 + X"01" //R0 = 0x0B
mem_data(21) <= X"B001"; --store Mem(1) <= R0 //Mem(1) = 0x0B
mem_data(22) <= X"F000"; --Return from interrupt
mem_data(32) <= X"2101"; --sub R0 <= R0 - R1 //R0 = 0x0B
mem_data(33) <= X"9011"; --store Mem(R1) <= R1 //Mem(49) = 0x31
mem_data(34) <= X"F000"; --Return from interrupt
mem_data(40) <= X"5403"; --and R0, R3 //R0 = 1
end if;
if falling_edge(clk) then
data_out <= mem_data(conv_integer(read_addr));
end if;
end process;
end mixed;
| unlicense | 82208071c5e6c4f9ee7fede21af9704d | 0.355564 | 2.979604 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/upstreamEpathFifoWrap.vhd | 3 | 6,159 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 23/06/2015
--! Module Name: upstreamEpathFifoWrap
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE,work;
use IEEE.std_logic_1164.ALL;
use ieee.numeric_std.all;
use work.all;
--! EPATH FIFO 18 bit wide, 1K deep
entity upstreamEpathFifoWrap is
port (
rst : in std_logic;
fifoFLUSH : in std_logic;
---
wr_clk : in std_logic;
wr_en : in std_logic;
din : in std_logic_vector(17 downto 0);
---
rd_clk : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(9 downto 0);
doutRdy : out std_logic;
---
full : out std_logic;
empty : out std_logic;
prog_full : out std_logic
);
end upstreamEpathFifoWrap;
architecture Behavioral of upstreamEpathFifoWrap is
----------------------------------
----------------------------------
component fh_epath_fifo2K_18bit_wide -- IP
port (
wr_clk : in std_logic;
wr_rst : in std_logic;
rd_clk : in std_logic;
rd_rst : in std_logic;
din : in std_logic_vector(17 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
prog_full_thresh_assert : in std_logic_vector(9 downto 0);
prog_full_thresh_negate : in std_logic_vector(9 downto 0);
dout : out std_logic_vector(17 downto 0);
full : out std_logic;
almost_full : out std_logic;
empty : out std_logic;
prog_full : out std_logic
);
end component;
----------------------------------
----------------------------------
signal rd_en_s, empty_efifo, prog_full_s : std_logic;
signal OE, rst_state, byte_cnt,byte_mux_sel,byte_rdy,rd_en1,rd_en2 : std_logic := '0';
signal dout18bit : std_logic_vector(17 downto 0);
signal byte0, byte1 : std_logic_vector(9 downto 0) := "1100000000";
constant comma_byte : std_logic_vector(9 downto 0) := "1100000000";
signal byte0_code,byte1_code,word16_code : std_logic_vector(1 downto 0);
signal empty_efifo1,empty_efifo2,empty_efifo3 : std_logic;
signal wr_en_r : std_logic := '0';
signal din_r : std_logic_vector(17 downto 0) := "110000000000000000";
begin
-------------------------------------------------------------------------------------------
-- write pipeline
-------------------------------------------------------------------------------------------
process(wr_clk)
begin
if wr_clk'event and wr_clk = '1' then
wr_en_r <= wr_en;
din_r <= din;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- FIFO - ip
-------------------------------------------------------------------------------------------
epathFIFO: fh_epath_fifo2K_18bit_wide
port map(
wr_clk => wr_clk,
wr_rst => fifoFLUSH,
rd_clk => rd_clk,
rd_rst => fifoFLUSH,
din => din_r,
wr_en => wr_en_r,
rd_en => rd_en_s,
dout => dout18bit, --18 bit
full => full,
almost_full => open, --almost_full,
empty => empty_efifo,
prog_full => prog_full_s, -- 1008/960 from 1024
prog_full_thresh_assert => std_logic_vector(to_unsigned(990, 10)),
prog_full_thresh_negate => std_logic_vector(to_unsigned(980, 10))
);
--
-------------------------------------------------------------------------------------------
-- re pulse
-------------------------------------------------------------------------------------------
process(rd_clk,rst)
begin
if rst = '1' then
byte_cnt <= '0';
elsif rd_clk'event and rd_clk = '1' then
if rd_en = '1' then -- 1 clk trigger
byte_cnt <= not byte_cnt;
end if;
end if;
end process;
--
rd_en_s <= rd_en and (not byte_cnt) and (not empty_efifo); -- only when byte_cnt = 0
--
word16_code <= dout18bit(17 downto 16);
--
process(word16_code,empty_efifo1,empty_efifo2)
begin
if empty_efifo1 = '1' then
byte0_code <= "11";
byte1_code <= "11";
else
if word16_code = "10" then -- start of message
byte0_code <= "11";
byte1_code <= "10";
elsif word16_code = "01" then -- end of message
byte0_code <= "01";
byte1_code <= "11";
else -- "00" data
byte0_code <= empty_efifo1 & empty_efifo1;
byte1_code <= empty_efifo2 & empty_efifo2;
end if;
end if;
end process;
--
byte0 <= byte0_code & dout18bit(15 downto 8);
byte1 <= byte1_code & dout18bit(7 downto 0);
--byte0 <= byte0_code & dout18bit(7 downto 0);
--byte1 <= byte1_code & dout18bit(15 downto 8);
--
process(byte_cnt,byte0,byte1)
begin
if byte_cnt = '1' then
dout <= byte0;
else
dout <= byte1;
end if;
end process;
--
--
process(rd_clk)
begin
if rd_clk'event and rd_clk = '1' then
byte_rdy <= byte_cnt;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- re pulse
-------------------------------------------------------------------------------------------
--
process(rd_clk)
begin
if rd_clk'event and rd_clk = '1' then
doutRdy <= rd_en;
empty_efifo1 <= empty_efifo;
empty_efifo2 <= empty_efifo1;
empty_efifo3 <= empty_efifo2;
end if;
end process;
--
empty <= empty_efifo;-- rd_clk domain
--
process(rd_clk)
begin
if rd_clk'event and rd_clk = '1' then
rst_state <= rst or fifoFLUSH;
OE <= not rst_state;
end if;
end process;
--
prog_full <= prog_full_s and OE;
--
end Behavioral;
| gpl-3.0 | 6f5c7660f3580857a4811292ece916ff | 0.447475 | 3.642224 | false | false | false | false |
vad-rulezz/megabot | fusesoc/orpsoc-cores/trunk/systems/neek/backend/rtl/verilog/ddr_ctrl_ip/ddr_ctrl_ip_phy_alt_mem_phy_seq.vhd | 4 | 648,170 | --
-- -----------------------------------------------------------------------------
-- Abstract : constants package for the non-levelling AFI PHY sequencer
-- The constant package (alt_mem_phy_constants_pkg) contains global
-- 'constants' which are fixed thoughout the sequencer and will not
-- change (for constants which may change between sequencer
-- instances generics are used)
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ddr_ctrl_ip_phy_alt_mem_phy_constants_pkg is
-- -------------------------------
-- Register number definitions
-- -------------------------------
constant c_max_mode_reg_index : natural := 13; -- number of MR bits..
-- Top bit of vector (i.e. width -1) used for address decoding :
constant c_debug_reg_addr_top : natural := 3;
constant c_mmi_access_codeword : std_logic_vector(31 downto 0) := X"00D0_0DEB"; -- to check for legal Avalon interface accesses
-- Register addresses.
constant c_regofst_cal_status : natural := 0;
constant c_regofst_debug_access : natural := 1;
constant c_regofst_hl_css : natural := 2;
constant c_regofst_mr_register_a : natural := 5;
constant c_regofst_mr_register_b : natural := 6;
constant c_regofst_codvw_status : natural := 12;
constant c_regofst_if_param : natural := 13;
constant c_regofst_if_test : natural := 14; -- pll_phs_shft, ac_1t, extra stuff
constant c_regofst_test_status : natural := 15;
constant c_hl_css_reg_cal_dis_bit : natural := 0;
constant c_hl_css_reg_phy_initialise_dis_bit : natural := 1;
constant c_hl_css_reg_init_dram_dis_bit : natural := 2;
constant c_hl_css_reg_write_ihi_dis_bit : natural := 3;
constant c_hl_css_reg_write_btp_dis_bit : natural := 4;
constant c_hl_css_reg_write_mtp_dis_bit : natural := 5;
constant c_hl_css_reg_read_mtp_dis_bit : natural := 6;
constant c_hl_css_reg_rrp_reset_dis_bit : natural := 7;
constant c_hl_css_reg_rrp_sweep_dis_bit : natural := 8;
constant c_hl_css_reg_rrp_seek_dis_bit : natural := 9;
constant c_hl_css_reg_rdv_dis_bit : natural := 10;
constant c_hl_css_reg_poa_dis_bit : natural := 11;
constant c_hl_css_reg_was_dis_bit : natural := 12;
constant c_hl_css_reg_adv_rd_lat_dis_bit : natural := 13;
constant c_hl_css_reg_adv_wr_lat_dis_bit : natural := 14;
constant c_hl_css_reg_prep_customer_mr_setup_dis_bit : natural := 15;
constant c_hl_css_reg_tracking_dis_bit : natural := 16;
constant c_hl_ccs_num_stages : natural := 17;
-- -----------------------------------------------------
-- Constants for DRAM addresses used during calibration:
-- -----------------------------------------------------
-- the mtp training pattern is x30F5
-- 1. write 0011 0000 and 1100 0000 such that one location will contains 0011 0000
-- 2. write in 1111 0101
-- also require locations containing all ones and all zeros
-- default choice of calibration burst length (overriden to 8 for reads for DDR3 devices)
constant c_cal_burst_len : natural := 4;
constant c_cal_ofs_step_size : natural := 8;
constant c_cal_ofs_zeros : natural := 0 * c_cal_ofs_step_size;
constant c_cal_ofs_ones : natural := 1 * c_cal_ofs_step_size;
constant c_cal_ofs_x30_almt_0 : natural := 2 * c_cal_ofs_step_size;
constant c_cal_ofs_x30_almt_1 : natural := 3 * c_cal_ofs_step_size;
constant c_cal_ofs_xF5 : natural := 5 * c_cal_ofs_step_size;
constant c_cal_ofs_wd_lat : natural := 6 * c_cal_ofs_step_size;
constant c_cal_data_len : natural := c_cal_ofs_wd_lat + c_cal_ofs_step_size;
constant c_cal_ofs_mtp : natural := 6*c_cal_ofs_step_size;
constant c_cal_ofs_mtp_len : natural := 4*4;
constant c_cal_ofs_01_pairs : natural := 2 * c_cal_burst_len;
constant c_cal_ofs_10_pairs : natural := 3 * c_cal_burst_len;
constant c_cal_ofs_1100_step : natural := 4 * c_cal_burst_len;
constant c_cal_ofs_0011_step : natural := 5 * c_cal_burst_len;
-- -----------------------------------------------------
-- Reset values. - These are chosen as default values for one PHY variation
-- with DDR2 memory and CAS latency 6, however in each calibration
-- mode these values will be set for a given PHY configuration.
-- -----------------------------------------------------
constant c_default_rd_lat : natural := 20;
constant c_default_wr_lat : natural := 5;
-- -----------------------------------------------------
-- Errorcodes
-- -----------------------------------------------------
-- implemented
constant C_SUCCESS : natural := 0;
constant C_ERR_RESYNC_NO_VALID_PHASES : natural := 5; -- No valid data-valid windows found
constant C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS : natural := 6; -- Multiple equally-sized data valid windows
constant C_ERR_RESYNC_NO_INVALID_PHASES : natural := 7; -- No invalid data-valid windows found. Training patterns are designed so that there should always be at least one invalid phase.
constant C_ERR_CRITICAL : natural := 15; -- A condition that can't happen just happened.
constant C_ERR_READ_MTP_NO_VALID_ALMT : natural := 23;
constant C_ERR_READ_MTP_BOTH_ALMT_PASS : natural := 24;
constant C_ERR_WD_LAT_DISAGREEMENT : natural := 22; -- MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS copies of write-latency are written to memory. If all of these are not the same this error is generated.
constant C_ERR_MAX_RD_LAT_EXCEEDED : natural := 25;
constant C_ERR_MAX_TRK_SHFT_EXCEEDED : natural := 26;
-- not implemented yet
constant c_err_ac_lat_some_beats_are_different : natural := 1; -- implies DQ_1T setup failure or earlier.
constant c_err_could_not_find_read_lat : natural := 2; -- dodgy RDP setup
constant c_err_could_not_find_write_lat : natural := 3; -- dodgy WDP setup
constant c_err_clock_cycle_iteration_timeout : natural := 8; -- depends on srate calling error -- GENERIC
constant c_err_clock_cycle_it_timeout_rdp : natural := 9;
constant c_err_clock_cycle_it_timeout_rdv : natural := 10;
constant c_err_clock_cycle_it_timeout_poa : natural := 11;
constant c_err_pll_ack_timeout : natural := 13;
constant c_err_WindowProc_multiple_rsc_windows : natural := 16;
constant c_err_WindowProc_window_det_no_ones : natural := 17;
constant c_err_WindowProc_window_det_no_zeros : natural := 18;
constant c_err_WindowProc_undefined : natural := 19; -- catch all
constant c_err_tracked_mmc_offset_overflow : natural := 20;
constant c_err_no_mimic_feedback : natural := 21;
constant c_err_ctrl_ack_timeout : natural := 32;
constant c_err_ctrl_done_timeout : natural := 33;
-- -----------------------------------------------------
-- PLL phase locations per device family
-- (unused but a limited set is maintained here for reference)
-- -----------------------------------------------------
constant c_pll_resync_phs_select_ciii : natural := 5;
constant c_pll_mimic_phs_select_ciii : natural := 4;
constant c_pll_resync_phs_select_siii : natural := 5;
constant c_pll_mimic_phs_select_siii : natural := 7;
-- -----------------------------------------------------
-- Maximum sizing constraints
-- -----------------------------------------------------
constant C_MAX_NUM_PLL_RSC_PHASES : natural := 32;
-- -----------------------------------------------------
-- IO control Params
-- -----------------------------------------------------
constant c_set_oct_to_rs : std_logic := '0';
constant c_set_oct_to_rt : std_logic := '1';
constant c_set_odt_rt : std_logic := '1';
constant c_set_odt_off : std_logic := '0';
--
end ddr_ctrl_ip_phy_alt_mem_phy_constants_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : record package for the non-levelling AFI sequencer
-- The record package (alt_mem_phy_record_pkg) is used to combine
-- command and status signals (into records) to be passed between
-- sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ddr_ctrl_ip_phy_alt_mem_phy_record_pkg is
-- set some maximum constraints to bound natural numbers below
constant c_max_num_dqs_groups : natural := 24;
constant c_max_num_pins : natural := 8;
constant c_max_ranks : natural := 16;
constant c_max_pll_steps : natural := 80;
-- a prefix for all report signals to identify phy and sequencer block
--
constant record_report_prefix : string := "ddr_ctrl_ip_phy_alt_mem_phy_record_pkg : ";
type t_family is (
cyclone3,
stratix2,
stratix3
);
-- -----------------------------------------------------------------------
-- the following are required for the non-levelling AFI PHY sequencer block interfaces
-- -----------------------------------------------------------------------
-- admin mode register settings (from mmi block)
type t_admin_ctrl is record
mr0 : std_logic_vector(12 downto 0);
mr1 : std_logic_vector(12 downto 0);
mr2 : std_logic_vector(12 downto 0);
mr3 : std_logic_vector(12 downto 0);
end record;
function defaults return t_admin_ctrl;
-- current admin status
type t_admin_stat is record
mr0 : std_logic_vector(12 downto 0);
mr1 : std_logic_vector(12 downto 0);
mr2 : std_logic_vector(12 downto 0);
mr3 : std_logic_vector(12 downto 0);
init_done : std_logic;
end record;
function defaults return t_admin_stat;
-- mmi to iram ctrl signals
type t_iram_ctrl is record
addr : natural range 0 to 1023;
wdata : std_logic_vector(31 downto 0);
write : std_logic;
read : std_logic;
end record;
function defaults return t_iram_ctrl;
-- broadcast iram status to mmi and dgrb
type t_iram_stat is record
rdata : std_logic_vector(31 downto 0);
done : std_logic;
err : std_logic;
err_code : std_logic_vector(3 downto 0);
init_done : std_logic;
out_of_mem : std_logic;
contested_access : std_logic;
end record;
function defaults return t_iram_stat;
-- codvw status signals from dgrb to mmi block
type t_dgrb_mmi is record
cal_codvw_phase : std_logic_vector(7 downto 0);
cal_codvw_size : std_logic_vector(7 downto 0);
codvw_trk_shift : std_logic_vector(11 downto 0);
codvw_grt_one_dvw : std_logic;
end record;
function defaults return t_dgrb_mmi;
-- signal to id which block is active
type t_ctrl_active_block is (
idle,
admin,
dgwb,
dgrb,
proc, -- unused in non-levelling AFI sequencer
setup, -- unused in non-levelling AFI sequencer
iram
);
function ret_proc return t_ctrl_active_block;
function ret_dgrb return t_ctrl_active_block;
-- control record for dgwb, dgrb, iram and admin blocks:
-- the possible commands
type t_ctrl_cmd_id is (
cmd_idle,
-- initialisation stages
cmd_phy_initialise,
cmd_init_dram,
cmd_prog_cal_mr,
cmd_write_ihi,
-- calibration stages
cmd_write_btp,
cmd_write_mtp,
cmd_read_mtp,
cmd_rrp_reset,
cmd_rrp_sweep,
cmd_rrp_seek,
cmd_rdv,
cmd_poa,
cmd_was,
-- advertise controller settings and re-configure for customer operation mode.
cmd_prep_adv_rd_lat,
cmd_prep_adv_wr_lat,
cmd_prep_customer_mr_setup,
cmd_tr_due
);
-- which block should execute each command
function curr_active_block (
ctrl_cmd_id : t_ctrl_cmd_id
) return t_ctrl_active_block;
-- specify command operands as a record
type t_command_op is record
current_cs : natural range 0 to c_max_ranks-1; -- which chip select is being calibrated
single_bit : std_logic; -- current operation should be single bit
mtp_almt : natural range 0 to 1; -- signals mtp alignment to be used for operation
end record;
function defaults return t_command_op;
-- command request record (sent to each block)
type t_ctrl_command is record
command : t_ctrl_cmd_id;
command_op : t_command_op;
command_req : std_logic;
end record;
function defaults return t_ctrl_command;
-- a generic status record for each block
type t_ctrl_stat is record
command_ack : std_logic;
command_done : std_logic;
command_result : std_logic_vector(7 downto 0 );
command_err : std_logic;
end record;
function defaults return t_ctrl_stat;
-- push interface for dgwb / dgrb blocks (only the dgrb uses this interface at present)
type t_iram_push is record
iram_done : std_logic;
iram_write : std_logic;
iram_wordnum : natural range 0 to 511; -- acts as an offset to current location (max = 80 pll steps *2 sweeps and 80 pins)
iram_bitnum : natural range 0 to 31; -- for bitwise packing modes
iram_pushdata : std_logic_vector(31 downto 0); -- only bit zero used for bitwise packing_mode
end record;
function defaults return t_iram_push;
-- control block "master" state machine
type t_master_sm_state is
(
s_reset,
s_phy_initialise, -- wait for dll lock and init done flag from iram
s_init_dram, -- dram initialisation - reset sequence
s_prog_cal_mr, -- dram initialisation - programming mode registers (once per chip select)
s_write_ihi, -- write header information in iRAM
s_cal, -- check if calibration to be executed
s_write_btp, -- write burst training pattern
s_write_mtp, -- write more training pattern
s_read_mtp, -- read training patterns to find correct alignment for 1100 burst
-- (this is a special case of s_rrp_seek with no resych phase setting)
s_rrp_reset, -- read resync phase setup - reset initial conditions
s_rrp_sweep, -- read resync phase setup - sweep phases per chip select
s_rrp_seek, -- read resync phase setup - seek correct phase
s_rdv, -- read data valid setup
s_was, -- write datapath setup (ac to write data timing)
s_adv_rd_lat, -- advertise read latency
s_adv_wr_lat, -- advertise write latency
s_poa, -- calibrate the postamble (dqs based capture only)
s_tracking_setup, -- perform tracking (1st pass to setup mimic window)
s_prep_customer_mr_setup, -- apply user mode register settings (in admin block)
s_tracking, -- perform tracking (subsequent passes in user mode)
s_operational, -- calibration successful and in user mode
s_non_operational -- calibration unsuccessful and in user mode
);
-- record (set in mmi block) to disable calibration states
type t_hl_css_reg is record
phy_initialise_dis : std_logic;
init_dram_dis : std_logic;
write_ihi_dis : std_logic;
cal_dis : std_logic;
write_btp_dis : std_logic;
write_mtp_dis : std_logic;
read_mtp_dis : std_logic;
rrp_reset_dis : std_logic;
rrp_sweep_dis : std_logic;
rrp_seek_dis : std_logic;
rdv_dis : std_logic;
poa_dis : std_logic;
was_dis : std_logic;
adv_rd_lat_dis : std_logic;
adv_wr_lat_dis : std_logic;
prep_customer_mr_setup_dis : std_logic;
tracking_dis : std_logic;
end record;
function defaults return t_hl_css_reg;
-- record (set in ctrl block) to identify when a command has been acknowledged
type t_cal_stage_ack_seen is record
cal : std_logic;
phy_initialise : std_logic;
init_dram : std_logic;
write_ihi : std_logic;
write_btp : std_logic;
write_mtp : std_logic;
read_mtp : std_logic;
rrp_reset : std_logic;
rrp_sweep : std_logic;
rrp_seek : std_logic;
rdv : std_logic;
poa : std_logic;
was : std_logic;
adv_rd_lat : std_logic;
adv_wr_lat : std_logic;
prep_customer_mr_setup : std_logic;
tracking_setup : std_logic;
end record;
function defaults return t_cal_stage_ack_seen;
-- ctrl to mmi block interface (calibration status)
type t_ctrl_mmi is record
master_state_r : t_master_sm_state;
ctrl_calibration_success : std_logic;
ctrl_calibration_fail : std_logic;
ctrl_current_stage_done : std_logic;
ctrl_current_stage : t_ctrl_cmd_id;
ctrl_current_active_block : t_ctrl_active_block;
ctrl_cal_stage_ack_seen : t_cal_stage_ack_seen;
ctrl_err_code : std_logic_vector(7 downto 0);
end record;
function defaults return t_ctrl_mmi;
-- mmi to ctrl block interface (calibration control signals)
type t_mmi_ctrl is record
hl_css : t_hl_css_reg;
calibration_start : std_logic;
tracking_period_ms : natural range 0 to 255;
tracking_orvd_to_10ms : std_logic;
end record;
function defaults return t_mmi_ctrl;
-- algorithm parameterisation (generated in mmi block)
type t_algm_paramaterisation is record
num_phases_per_tck_pll : natural range 1 to c_max_pll_steps;
nominal_dqs_delay : natural range 0 to 4;
pll_360_sweeps : natural range 0 to 15;
nominal_poa_phase_lead : natural range 0 to 7;
maximum_poa_delay : natural range 0 to 15;
odt_enabled : boolean;
extend_octrt_by : natural range 0 to 15;
delay_octrt_by : natural range 0 to 15;
tracking_period_ms : natural range 0 to 255;
end record;
-- interface between mmi and pll to control phase shifting
type t_mmi_pll_reconfig is record
pll_phs_shft_phase_sel : natural range 0 to 15;
pll_phs_shft_up_wc : std_logic;
pll_phs_shft_dn_wc : std_logic;
end record;
type t_pll_mmi is record
pll_busy : std_logic;
err : std_logic_vector(1 downto 0);
end record;
-- specify the iram configuration this is default
-- currently always dq_bitwise packing and a write mode of overwrite_ram
type t_iram_packing_mode is (
dq_bitwise,
dq_wordwise
);
type t_iram_write_mode is (
overwrite_ram,
or_into_ram,
and_into_ram
);
type t_ctrl_iram is record
packing_mode : t_iram_packing_mode;
write_mode : t_iram_write_mode;
active_block : t_ctrl_active_block;
end record;
function defaults return t_ctrl_iram;
-- -----------------------------------------------------------------------
-- the following are required for compliance to levelling AFI PHY interface but
-- are non-functional for non-levelling AFI PHY sequencer
-- -----------------------------------------------------------------------
type t_sc_ctrl_if is record
read : std_logic;
write : std_logic;
dqs_group_sel : std_logic_vector( 4 downto 0);
sc_in_group_sel : std_logic_vector( 5 downto 0);
wdata : std_logic_vector(45 downto 0);
op_type : std_logic_vector( 1 downto 0);
end record;
function defaults return t_sc_ctrl_if;
type t_sc_stat is record
rdata : std_logic_vector(45 downto 0);
busy : std_logic;
error_det : std_logic;
err_code : std_logic_vector(1 downto 0);
sc_cap : std_logic_vector(7 downto 0);
end record;
function defaults return t_sc_stat;
type t_element_to_reconfigure is (
pp_t9,
pp_t10,
pp_t1,
dqslb_rsc_phs,
dqslb_poa_phs_ofst,
dqslb_dqs_phs,
dqslb_dq_phs_ofst,
dqslb_dq_1t,
dqslb_dqs_1t,
dqslb_rsc_1t,
dqslb_div2_phs,
dqslb_oct_t9,
dqslb_oct_t10,
dqslb_poa_t7,
dqslb_poa_t11,
dqslb_dqs_dly,
dqslb_lvlng_byps
);
type t_sc_type is (
DQS_LB,
DQS_DQ_DM_PINS,
DQ_DM_PINS,
dqs_dqsn_pins,
dq_pin,
dqs_pin,
dm_pin,
dq_pins
);
type t_sc_int_ctrl is record
group_num : natural range 0 to c_max_num_dqs_groups;
group_type : t_sc_type;
pin_num : natural range 0 to c_max_num_pins;
sc_element : t_element_to_reconfigure;
prog_val : std_logic_vector(3 downto 0);
ram_set : std_logic;
sc_update : std_logic;
end record;
function defaults return t_sc_int_ctrl;
-- -----------------------------------------------------------------------
-- record and functions for instant on mode
-- -----------------------------------------------------------------------
-- ranges on the below are not important because this logic is not synthesised
type t_preset_cal is record
codvw_phase : natural range 0 to 2*c_max_pll_steps;-- rsc phase
codvw_size : natural range 0 to c_max_pll_steps; -- rsc size (unused but reported)
rlat : natural; -- advertised read latency ctl_rlat (in phy clock cycles)
rdv_lat : natural; -- read data valid latency decrements needed (in memory clock cycles)
wlat : natural; -- advertised write latency ctl_wlat (in phy clock cycles)
ac_1t : std_logic; -- address / command 1t delay setting (HR only)
poa_lat : natural; -- poa latency decrements needed (in memory clock cycles)
end record;
-- the below are hardcoded (do not change)
constant c_ddr_default_cl : natural := 3;
constant c_ddr2_default_cl : natural := 6;
constant c_ddr3_default_cl : natural := 6;
constant c_ddr2_default_cwl : natural := 5;
constant c_ddr3_default_cwl : natural := 5;
constant c_ddr2_default_al : natural := 0;
constant c_ddr3_default_al : natural := 0;
constant c_ddr_default_rl : integer := c_ddr_default_cl;
constant c_ddr2_default_rl : integer := c_ddr2_default_cl + c_ddr2_default_al;
constant c_ddr3_default_rl : integer := c_ddr3_default_cl + c_ddr3_default_al;
constant c_ddr_default_wl : integer := 1;
constant c_ddr2_default_wl : integer := c_ddr2_default_cwl + c_ddr2_default_al;
constant c_ddr3_default_wl : integer := c_ddr3_default_cwl + c_ddr3_default_al;
function defaults return t_preset_cal;
function setup_instant_on (sim_time_red : natural;
family_id : natural;
memory_type : string;
dwidth_ratio : natural;
pll_steps : natural;
mr0 : std_logic_vector(15 downto 0);
mr1 : std_logic_vector(15 downto 0);
mr2 : std_logic_vector(15 downto 0)) return t_preset_cal;
--
end ddr_ctrl_ip_phy_alt_mem_phy_record_pkg;
--
package body ddr_ctrl_ip_phy_alt_mem_phy_record_pkg IS
-- -----------------------------------------------------------------------
-- function implementations for the above declarations
-- these are mainly default conditions for records
-- -----------------------------------------------------------------------
function defaults return t_admin_ctrl is
variable output : t_admin_ctrl;
begin
output.mr0 := (others => '0');
output.mr1 := (others => '0');
output.mr2 := (others => '0');
output.mr3 := (others => '0');
return output;
end function;
function defaults return t_admin_stat is
variable output : t_admin_stat;
begin
output.mr0 := (others => '0');
output.mr1 := (others => '0');
output.mr2 := (others => '0');
output.mr3 := (others => '0');
return output;
end function;
function defaults return t_iram_ctrl is
variable output : t_iram_ctrl;
begin
output.addr := 0;
output.wdata := (others => '0');
output.write := '0';
output.read := '0';
return output;
end function;
function defaults return t_iram_stat is
variable output : t_iram_stat;
begin
output.rdata := (others => '0');
output.done := '0';
output.err := '0';
output.err_code := (others => '0');
output.init_done := '0';
output.out_of_mem := '0';
output.contested_access := '0';
return output;
end function;
function defaults return t_dgrb_mmi is
variable output : t_dgrb_mmi;
begin
output.cal_codvw_phase := (others => '0');
output.cal_codvw_size := (others => '0');
output.codvw_trk_shift := (others => '0');
output.codvw_grt_one_dvw := '0';
return output;
end function;
function ret_proc return t_ctrl_active_block is
variable output : t_ctrl_active_block;
begin
output := proc;
return output;
end function;
function ret_dgrb return t_ctrl_active_block is
variable output : t_ctrl_active_block;
begin
output := dgrb;
return output;
end function;
function defaults return t_ctrl_iram is
variable output : t_ctrl_iram;
begin
output.packing_mode := dq_bitwise;
output.write_mode := overwrite_ram;
output.active_block := idle;
return output;
end function;
function defaults return t_command_op is
variable output : t_command_op;
begin
output.current_cs := 0;
output.single_bit := '0';
output.mtp_almt := 0;
return output;
end function;
function defaults return t_ctrl_command is
variable output : t_ctrl_command;
begin
output.command := cmd_idle;
output.command_req := '0';
output.command_op := defaults;
return output;
end function;
-- decode which block is associated with which command
function curr_active_block (
ctrl_cmd_id : t_ctrl_cmd_id
) return t_ctrl_active_block is
begin
case ctrl_cmd_id is
when cmd_idle => return idle;
when cmd_phy_initialise => return idle;
when cmd_init_dram => return admin;
when cmd_prog_cal_mr => return admin;
when cmd_write_ihi => return iram;
when cmd_write_btp => return dgwb;
when cmd_write_mtp => return dgwb;
when cmd_read_mtp => return dgrb;
when cmd_rrp_reset => return dgrb;
when cmd_rrp_sweep => return dgrb;
when cmd_rrp_seek => return dgrb;
when cmd_rdv => return dgrb;
when cmd_poa => return dgrb;
when cmd_was => return dgwb;
when cmd_prep_adv_rd_lat => return dgrb;
when cmd_prep_adv_wr_lat => return dgrb;
when cmd_prep_customer_mr_setup => return admin;
when cmd_tr_due => return dgrb;
when others => return idle;
end case;
end function;
function defaults return t_ctrl_stat is
variable output : t_ctrl_stat;
begin
output.command_ack := '0';
output.command_done := '0';
output.command_err := '0';
output.command_result := (others => '0');
return output;
end function;
function defaults return t_iram_push is
variable output : t_iram_push;
begin
output.iram_done := '0';
output.iram_write := '0';
output.iram_wordnum := 0;
output.iram_bitnum := 0;
output.iram_pushdata := (others => '0');
return output;
end function;
function defaults return t_hl_css_reg is
variable output : t_hl_css_reg;
begin
output.phy_initialise_dis := '0';
output.init_dram_dis := '0';
output.write_ihi_dis := '0';
output.cal_dis := '0';
output.write_btp_dis := '0';
output.write_mtp_dis := '0';
output.read_mtp_dis := '0';
output.rrp_reset_dis := '0';
output.rrp_sweep_dis := '0';
output.rrp_seek_dis := '0';
output.rdv_dis := '0';
output.poa_dis := '0';
output.was_dis := '0';
output.adv_rd_lat_dis := '0';
output.adv_wr_lat_dis := '0';
output.prep_customer_mr_setup_dis := '0';
output.tracking_dis := '0';
return output;
end function;
function defaults return t_cal_stage_ack_seen is
variable output : t_cal_stage_ack_seen;
begin
output.cal := '0';
output.phy_initialise := '0';
output.init_dram := '0';
output.write_ihi := '0';
output.write_btp := '0';
output.write_mtp := '0';
output.read_mtp := '0';
output.rrp_reset := '0';
output.rrp_sweep := '0';
output.rrp_seek := '0';
output.rdv := '0';
output.poa := '0';
output.was := '0';
output.adv_rd_lat := '0';
output.adv_wr_lat := '0';
output.prep_customer_mr_setup := '0';
output.tracking_setup := '0';
return output;
end function;
function defaults return t_mmi_ctrl is
variable output : t_mmi_ctrl;
begin
output.hl_css := defaults;
output.calibration_start := '0';
output.tracking_period_ms := 0;
output.tracking_orvd_to_10ms := '0';
return output;
end function;
function defaults return t_ctrl_mmi is
variable output : t_ctrl_mmi;
begin
output.master_state_r := s_reset;
output.ctrl_calibration_success := '0';
output.ctrl_calibration_fail := '0';
output.ctrl_current_stage_done := '0';
output.ctrl_current_stage := cmd_idle;
output.ctrl_current_active_block := idle;
output.ctrl_cal_stage_ack_seen := defaults;
output.ctrl_err_code := (others => '0');
return output;
end function;
-------------------------------------------------------------------------
-- the following are required for compliance to levelling AFI PHY interface but
-- are non-functional for non-levelling AFi PHY sequencer
-------------------------------------------------------------------------
function defaults return t_sc_ctrl_if is
variable output : t_sc_ctrl_if;
begin
output.read := '0';
output.write := '0';
output.dqs_group_sel := (others => '0');
output.sc_in_group_sel := (others => '0');
output.wdata := (others => '0');
output.op_type := (others => '0');
return output;
end function;
function defaults return t_sc_stat is
variable output : t_sc_stat;
begin
output.rdata := (others => '0');
output.busy := '0';
output.error_det := '0';
output.err_code := (others => '0');
output.sc_cap := (others => '0');
return output;
end function;
function defaults return t_sc_int_ctrl is
variable output : t_sc_int_ctrl;
begin
output.group_num := 0;
output.group_type := DQ_PIN;
output.pin_num := 0;
output.sc_element := pp_t9;
output.prog_val := (others => '0');
output.ram_set := '0';
output.sc_update := '0';
return output;
end function;
-- -----------------------------------------------------------------------
-- functions for instant on mode
--
--
-- Guide on how to use:
--
-- The following factors effect the setup of the PHY:
-- - AC Phase - phase at which address/command signals launched wrt PHY clock
-- - this effects the read/write latency
-- - MR settings - CL, CWL, AL
-- - Data rate - HR or FR (DDR/DDR2 only)
-- - Family - datapaths are subtly different for each
-- - Memory type - DDR/DDR2/DDR3 (different latency behaviour - see specs)
--
-- Instant on mode is designed to work for the following subset of the
-- above factors:
-- - AC Phase - out of the box defaults, which is 240 degrees for SIII type
-- families (includes SIV, HCIII, HCIV), else 90 degrees
-- - MR Settings - DDR - CL 3 only
-- - DDR2 - CL 3,4,5,6, AL 0
-- - DDR3 - CL 5,6 CWL 5, AL 0
-- - Data rate - All
-- - Families - All
-- - Memory type - All
--
-- Hints on bespoke setup for parameters outside the above or if the
-- datapath is modified (only for VHDL sim mode):
--
-- Step 1 - Run simulation with REDUCE_SIM_TIME mode 2 (FAST)
--
-- Step 2 - From the output log find the following text:
-- # -----------------------------------------------------------------------
-- **** ALTMEMPHY CALIBRATION has completed ****
-- Status:
-- calibration has : PASSED
-- PHY read latency (ctl_rlat) is : 14
-- address/command to PHY write latency (ctl_wlat) is : 2
-- read resynch phase calibration report:
-- calibrated centre of data valid window phase : 32
-- calibrated centre of data valid window size : 24
-- chosen address and command 1T delay: no 1T delay
-- poa 'dec' adjustments = 27
-- rdv 'dec' adjustments = 25
-- # -----------------------------------------------------------------------
--
-- Step 3 - Convert the text to bespoke instant on settings at the end of the
-- setup_instant_on function using the
-- override_instant_on function, note type is t_preset_cal
--
-- The mapping is as follows:
--
-- PHY read latency (ctl_rlat) is : 14 => rlat := 14
-- address/command to PHY write latency (ctl_wlat) is : 2 => wlat := 2
-- read resynch phase calibration report:
-- calibrated centre of data valid window phase : 32 => codvw_phase := 32
-- calibrated centre of data valid window size : 24 => codvw_size := 24
-- chosen address and command 1T delay: no 1T delay => ac_1t := '0'
-- poa 'dec' adjustments = 27 => poa_lat := 27
-- rdv 'dec' adjustments = 25 => rdv_lat := 25
--
-- Step 4 - Try running in REDUCE_SIM_TIME mode 1 (SUPERFAST mode)
--
-- Step 5 - If still fails observe the behaviour of the controller, for the
-- following symptoms:
-- - If first 2 beats of read data lost (POA enable too late) - inc poa_lat by 1 (poa_lat is number of POA decrements not actual latency)
-- - If last 2 beats of read data lost (POA enable too early) - dec poa_lat by 1
-- - If ctl_rdata_valid misaligned to ctl_rdata then alter number of RDV adjustments (rdv_lat)
-- - If write data is not 4-beat aligned (when written into memory) toggle ac_1t (HR only)
-- - If read data is not 4-beat aligned (but write data is) add 360 degrees to phase (PLL_STEPS_PER_CYCLE) mod 2*PLL_STEPS_PER_CYCLE (HR only)
--
-- Step 6 - If the above fails revert to REDUCE_SIM_TIME = 2 (FAST) mode
--
-- --------------------------------------------------------------------------
-- defaults
function defaults return t_preset_cal is
variable output : t_preset_cal;
begin
output.codvw_phase := 0;
output.codvw_size := 0;
output.wlat := 0;
output.rlat := 0;
output.rdv_lat := 0;
output.ac_1t := '1'; -- default on for FR
output.poa_lat := 0;
return output;
end function;
-- Functions to extract values from MR
-- return cl (for DDR memory 2*cl because of 1/2 cycle latencies)
procedure mr0_to_cl (memory_type : string;
mr0 : std_logic_vector(15 downto 0);
cl : out natural;
half_cl : out std_logic) is
variable v_cl : natural;
begin
half_cl := '0';
if memory_type = "DDR" then -- DDR memories
-- returns cl*2 because of 1/2 latencies
v_cl := to_integer(unsigned(mr0(5 downto 4)));
-- integer values of cl
if mr0(6) = '0' then
assert v_cl > 1 report record_report_prefix & "invalid cas latency for DDR memory, should be in range 1.5-3" severity failure;
end if;
if mr0(6) = '1' then
assert (v_cl = 1 or v_cl = 2) report record_report_prefix & "invalid cas latency for DDR memory, should be in range 1.5-3" severity failure;
half_cl := '1';
end if;
elsif memory_type = "DDR2" then -- DDR2 memories
v_cl := to_integer(unsigned(mr0(6 downto 4)));
-- sanity checks
assert (v_cl > 1 and v_cl < 7) report record_report_prefix & "invalid cas latency for DDR2 memory, should be in range 2-6 but equals " & integer'image(v_cl) severity failure;
elsif memory_type = "DDR3" then -- DDR3 memories
v_cl := to_integer(unsigned(mr0(6 downto 4)))+4;
--sanity checks
assert mr0(2) = '0' report record_report_prefix & "invalid cas latency for DDR3 memory, bit a2 in mr0 is set" severity failure;
assert v_cl /= 4 report record_report_prefix & "invalid cas latency for DDR3 memory, bits a6:4 set to zero" severity failure;
else
report record_report_prefix & "Undefined memory type " & memory_type severity failure;
end if;
cl := v_cl;
end procedure;
function mr1_to_al (memory_type : string;
mr1 : std_logic_vector(15 downto 0);
cl : natural) return natural is
variable al : natural;
begin
if memory_type = "DDR" then -- DDR memories
-- unsupported so return zero
al := 0;
elsif memory_type = "DDR2" then -- DDR2 memories
al := to_integer(unsigned(mr1(5 downto 3)));
assert al < 6 report record_report_prefix & "invalid additive latency for DDR2 memory, should be in range 0-5 but equals " & integer'image(al) severity failure;
elsif memory_type = "DDR3" then -- DDR3 memories
al := to_integer(unsigned(mr1(4 downto 3)));
assert al /= 3 report record_report_prefix & "invalid additive latency for DDR2 memory, should be in range 0-5 but equals " & integer'image(al) severity failure;
if al /= 0 then -- CL-1 or CL-2
al := cl - al;
end if;
else
report record_report_prefix & "Undefined memory type " & memory_type severity failure;
end if;
return al;
end function;
-- return cwl
function mr2_to_cwl (memory_type : string;
mr2 : std_logic_vector(15 downto 0);
cl : natural) return natural is
variable cwl : natural;
begin
if memory_type = "DDR" then -- DDR memories
cwl := 1;
elsif memory_type = "DDR2" then -- DDR2 memories
cwl := cl - 1;
elsif memory_type = "DDR3" then -- DDR3 memories
cwl := to_integer(unsigned(mr2(5 downto 3))) + 5;
--sanity checks
assert cwl < 9 report record_report_prefix & "invalid cas write latency for DDR3 memory, should be in range 5-8 but equals " & integer'image(cwl) severity failure;
else
report record_report_prefix & "Undefined memory type " & memory_type severity failure;
end if;
return cwl;
end function;
-- -----------------------------------
-- Functions to determine which family group
-- Include any family alias here
-- -----------------------------------
function is_siii(family_id : natural) return boolean is
begin
if family_id = 3 or family_id = 5 then
return true;
else
return false;
end if;
end function;
function is_ciii(family_id : natural) return boolean is
begin
if family_id = 2 then
return true;
else
return false;
end if;
end function;
function is_aii(family_id : natural) return boolean is
begin
if family_id = 4 then
return true;
else
return false;
end if;
end function;
function is_sii(family_id : natural) return boolean is
begin
if family_id = 1 then
return true;
else
return false;
end if;
end function;
-- -----------------------------------
-- Functions to lookup hardcoded values
-- on per family basis
-- DDR: CL = 3
-- DDR2: CL = 6, CWL = 5, AL = 0
-- DDR3: CL = 6, CWL = 5, AL = 0
-- -----------------------------------
-- default ac phase = 240
function siii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural
) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 11;
v_output.poa_lat := 11;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 23;
v_output.ac_1t := '0';
v_output.poa_lat := 24;
end if;
elsif memory_type = "DDR2" then -- CAS = 6
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 16;
v_output.rdv_lat := 10;
v_output.poa_lat := 8;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 16;
v_output.rdv_lat := 21;
v_output.ac_1t := '0';
v_output.poa_lat := 22;
end if;
elsif memory_type = "DDR3" then -- HR only, CAS = 6
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 2;
v_output.rlat := 15;
v_output.rdv_lat := 23;
v_output.ac_1t := '0';
v_output.poa_lat := 24;
end if;
-- adapt settings for ac_phase (default 240 degrees so leave commented)
-- if dwidth_ratio = 2 then
-- v_output.wlat := v_output.wlat - 1;
-- v_output.rlat := v_output.rlat - 1;
-- v_output.rdv_lat := v_output.rdv_lat + 1;
-- v_output.poa_lat := v_output.poa_lat + 1;
-- else
-- v_output.ac_1t := not v_output.ac_1t;
-- end if;
v_output.codvw_size := pll_steps;
return v_output;
end function;
-- default ac phase = 90
function ciii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := 3*pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 11;
v_output.poa_lat := 11; --unused
else
v_output.codvw_phase := 3*pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 13;
v_output.rdv_lat := 27;
v_output.ac_1t := '1';
v_output.poa_lat := 27; --unused
end if;
elsif memory_type = "DDR2" then -- CAS = 6
if dwidth_ratio = 2 then
v_output.codvw_phase := 3*pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 18;
v_output.rdv_lat := 8;
v_output.poa_lat := 8; --unused
else
v_output.codvw_phase := pll_steps + 3*pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 25; --unused
end if;
end if;
-- adapt settings for ac_phase (hardcode for 90 degrees)
if dwidth_ratio = 2 then
v_output.wlat := v_output.wlat + 1;
v_output.rlat := v_output.rlat + 1;
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.ac_1t := not v_output.ac_1t;
end if;
v_output.codvw_size := pll_steps/2;
return v_output;
end function;
-- default ac phase = 90
function sii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 11;
v_output.poa_lat := 13;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 13;
v_output.rdv_lat := 27;
v_output.ac_1t := '1';
v_output.poa_lat := 22;
end if;
elsif memory_type = "DDR2" then
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 18;
v_output.rdv_lat := 8;
v_output.poa_lat := 10;
else
v_output.codvw_phase := pll_steps + pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 20;
end if;
end if;
-- adapt settings for ac_phase (hardcode for 90 degrees)
if dwidth_ratio = 2 then
v_output.wlat := v_output.wlat + 1;
v_output.rlat := v_output.rlat + 1;
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.ac_1t := not v_output.ac_1t;
end if;
v_output.codvw_size := pll_steps;
return v_output;
end function;
-- default ac phase = 90
function aii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 16;
v_output.rdv_lat := 10;
v_output.poa_lat := 15;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 13;
v_output.rdv_lat := 27;
v_output.ac_1t := '1';
v_output.poa_lat := 24;
end if;
elsif memory_type = "DDR2" then
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 19;
v_output.rdv_lat := 9;
v_output.poa_lat := 12;
else
v_output.codvw_phase := pll_steps + pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 22;
end if;
elsif memory_type = "DDR3" then -- HR only, CAS = 6
v_output.codvw_phase := pll_steps + pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 22;
end if;
-- adapt settings for ac_phase (hardcode for 90 degrees)
if dwidth_ratio = 2 then
v_output.wlat := v_output.wlat + 1;
v_output.rlat := v_output.rlat + 1;
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.ac_1t := not v_output.ac_1t;
end if;
v_output.codvw_size := pll_steps;
return v_output;
end function;
function is_odd(num : integer) return boolean is
variable v_num : integer;
begin
v_num := num;
if v_num - (v_num/2)*2 = 0 then
return false;
else
return true;
end if;
end function;
------------------------------------------------
-- top level function to setup instant on mode
------------------------------------------------
function override_instant_on return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
-- add in overrides here
return v_output;
end function;
function setup_instant_on (sim_time_red : natural;
family_id : natural;
memory_type : string;
dwidth_ratio : natural;
pll_steps : natural;
mr0 : std_logic_vector(15 downto 0);
mr1 : std_logic_vector(15 downto 0);
mr2 : std_logic_vector(15 downto 0)) return t_preset_cal is
variable v_output : t_preset_cal;
variable v_cl : natural; -- cas latency
variable v_half_cl : std_logic; -- + 0.5 cycles (DDR only)
variable v_al : natural; -- additive latency (ddr2/ddr3 only)
variable v_cwl : natural; -- cas write latency (ddr3 only)
variable v_rl : integer range 0 to 15;
variable v_wl : integer;
variable v_delta_rl : integer range -10 to 10; -- from given defaults
variable v_delta_wl : integer; -- from given defaults
variable v_debug : boolean;
begin
v_debug := true;
v_output := defaults;
if sim_time_red = 1 then -- only set if STR equals 1
-- ----------------------------------------
-- extract required parameters from MRs
-- ----------------------------------------
mr0_to_cl(memory_type, mr0, v_cl, v_half_cl);
v_al := mr1_to_al(memory_type, mr1, v_cl);
v_cwl := mr2_to_cwl(memory_type, mr2, v_cl);
v_rl := v_cl + v_al;
v_wl := v_cwl + v_al;
if v_debug then
report record_report_prefix & "Extracted MR parameters" & LF &
"CAS = " & integer'image(v_cl) & LF &
"CWL = " & integer'image(v_cwl) & LF &
"AL = " & integer'image(v_al) & LF;
end if;
-- ----------------------------------------
-- apply per family, memory type and dwidth_ratio static setup
-- ----------------------------------------
if is_siii(family_id) then
v_output := siii_family_settings(dwidth_ratio, memory_type, pll_steps);
elsif is_ciii(family_id) then
v_output := ciii_family_settings(dwidth_ratio, memory_type, pll_steps);
elsif is_aii(family_id) then
v_output := aii_family_settings(dwidth_ratio, memory_type, pll_steps);
elsif is_sii(family_id) then
v_output := sii_family_settings(dwidth_ratio, memory_type, pll_steps);
end if;
-- ----------------------------------------
-- correct for different cwl, cl and al settings
-- ----------------------------------------
if memory_type = "DDR" then
v_delta_rl := v_rl - c_ddr_default_rl;
v_delta_wl := v_wl - c_ddr_default_wl;
elsif memory_type = "DDR2" then
v_delta_rl := v_rl - c_ddr2_default_rl;
v_delta_wl := v_wl - c_ddr2_default_wl;
else -- DDR3
v_delta_rl := v_rl - c_ddr3_default_rl;
v_delta_wl := v_wl - c_ddr3_default_wl;
end if;
if v_debug then
report record_report_prefix & "Extracted memory latency (and delta from default)" & LF &
"RL = " & integer'image(v_rl) & LF &
"WL = " & integer'image(v_wl) & LF &
"delta RL = " & integer'image(v_delta_rl) & LF &
"delta WL = " & integer'image(v_delta_wl) & LF;
end if;
if dwidth_ratio = 2 then
-- adjust rdp settings
v_output.rlat := v_output.rlat + v_delta_rl;
v_output.rdv_lat := v_output.rdv_lat - v_delta_rl;
v_output.poa_lat := v_output.poa_lat - v_delta_rl;
-- adjust wdp settings
v_output.wlat := v_output.wlat + v_delta_wl;
elsif dwidth_ratio = 4 then
-- adjust wdp settings
v_output.wlat := v_output.wlat + v_delta_wl/2;
if is_odd(v_delta_wl) then -- add / sub 1t write latency
-- toggle ac_1t in all cases
v_output.ac_1t := not v_output.ac_1t;
if v_delta_wl < 0 then -- sub 1 from latency
if v_output.ac_1t = '0' then -- phy_clk cc boundary
v_output.wlat := v_output.wlat - 1;
end if;
else -- add 1 to latency
if v_output.ac_1t = '1' then -- phy_clk cc boundary
v_output.wlat := v_output.wlat + 1;
end if;
end if;
-- update read latency
if v_output.ac_1t = '1' then -- added 1t to address/command so inc read_lat
v_delta_rl := v_delta_rl + 1;
else -- subtracted 1t from address/command so dec read_lat
v_delta_rl := v_delta_rl - 1;
end if;
end if;
-- adjust rdp settings
v_output.rlat := v_output.rlat + v_delta_rl/2;
v_output.rdv_lat := v_output.rdv_lat - v_delta_rl;
v_output.poa_lat := v_output.poa_lat - v_delta_rl;
if memory_type = "DDR3" then
if is_odd(v_delta_rl) xor is_odd(v_delta_wl) then
if is_aii(family_id) then
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.rdv_lat := v_output.rdv_lat + 1;
v_output.poa_lat := v_output.poa_lat + 1;
end if;
end if;
end if;
if is_odd(v_delta_rl) then
if v_delta_rl > 0 then -- add 1t
if v_output.codvw_phase < pll_steps then
v_output.codvw_phase := v_output.codvw_phase + pll_steps;
else
v_output.codvw_phase := v_output.codvw_phase - pll_steps;
v_output.rlat := v_output.rlat + 1;
end if;
else -- subtract 1t
if v_output.codvw_phase < pll_steps then
v_output.codvw_phase := v_output.codvw_phase + pll_steps;
v_output.rlat := v_output.rlat - 1;
else
v_output.codvw_phase := v_output.codvw_phase - pll_steps;
end if;
end if;
end if;
end if;
if v_half_cl = '1' and is_ciii(family_id) then
v_output.codvw_phase := v_output.codvw_phase - pll_steps/2;
end if;
end if;
return v_output;
end function;
--
END ddr_ctrl_ip_phy_alt_mem_phy_record_pkg;
--/* Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
-- use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any
-- output files any of the foregoing (including device programming or
-- simulation files), and any associated documentation or information are
-- expressly subject to the terms and conditions of the Altera Program
-- License Subscription Agreement or other applicable license agreement,
-- including, without limitation, that your use is for the sole purpose
-- of programming logic devices manufactured by Altera and sold by Altera
-- or its authorized distributors. Please refer to the applicable
-- agreement for further details. */
--
-- -----------------------------------------------------------------------------
-- Abstract : address and command package, shared between all variations of
-- the AFI sequencer
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is
-- used to combine DRAM address and command signals in one record
-- and unify the functions operating on this record.
--
--
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ddr_ctrl_ip_phy_alt_mem_phy_addr_cmd_pkg is
-- the following are bounds on the maximum range of address and command signals
constant c_max_addr_bits : natural := 15;
constant c_max_ba_bits : natural := 3;
constant c_max_ranks : natural := 16;
constant c_max_mode_reg_bit : natural := 12;
constant c_max_cmds_per_clk : natural := 4; -- quarter rate
-- a prefix for all report signals to identify phy and sequencer block
--
constant ac_report_prefix : string := "ddr_ctrl_ip_phy_alt_mem_phy_seq (addr_cmd_pkg) : ";
-- -------------------------------------------------------------
-- this record represents a single mem_clk command cycle
-- -------------------------------------------------------------
type t_addr_cmd is record
addr : natural range 0 to 2**c_max_addr_bits - 1;
ba : natural range 0 to 2**c_max_ba_bits - 1;
cas_n : boolean;
ras_n : boolean;
we_n : boolean;
cke : natural range 0 to 2**c_max_ranks - 1; -- bounded max of 8 ranks
cs_n : natural range 2**c_max_ranks - 1 downto 0; -- bounded max of 8 ranks
odt : natural range 0 to 2**c_max_ranks - 1; -- bounded max of 8 ranks
rst_n : boolean;
end record t_addr_cmd;
-- -------------------------------------------------------------
-- this vector is used to describe the fact that for slower clock domains
-- mutiple commands per clock can be issued and encapsulates all these options in a
-- type which can scale with rate
-- -------------------------------------------------------------
type t_addr_cmd_vector is array (natural range <>) of t_addr_cmd;
-- -------------------------------------------------------------
-- this record is used to define the memory interface type and allow packing and checking
-- (it should be used as a generic to a entity or from a poject level constant)
-- -------------------------------------------------------------
-- enumeration for mem_type
type t_mem_type is
(
DDR,
DDR2,
DDR3
);
-- memory interface configuration parameters
type t_addr_cmd_config_rec is record
num_addr_bits : natural;
num_ba_bits : natural;
num_cs_bits : natural;
num_ranks : natural;
cmds_per_clk : natural range 1 to c_max_cmds_per_clk; -- commands per clock cycle (equal to DWIDTH_RATIO/2)
mem_type : t_mem_type;
end record;
-- -----------------------------------
-- the following type is used to switch between signals
-- (for example, in the mask function below)
-- -----------------------------------
type t_addr_cmd_signals is
(
addr,
ba,
cas_n,
ras_n,
we_n,
cke,
cs_n,
odt,
rst_n
);
-- -----------------------------------
-- odt record
-- to hold the odt settings
-- (an odt_record) per rank (in odt_array)
-- -----------------------------------
type t_odt_record is record
write : natural;
read : natural;
end record t_odt_record;
type t_odt_array is array (natural range <>) of t_odt_record;
-- -------------------------------------------------------------
-- exposed functions and procedures
--
-- these functions cover the following memory types:
-- DDR3, DDR2, DDR
--
-- and the following operations:
-- MRS, REF, PRE, PREA, ACT,
-- WR, WRS8, WRS4, WRA, WRAS8, WRAS4,
-- RD, RDS8, RDS4, RDA, RDAS8, RDAS4,
--
-- for DDR3 on the fly burst length setting for reads/writes
-- is supported
-- -------------------------------------------------------------
function defaults ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector;
function reset ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector;
function int_pup_reset ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector;
function deselect ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector
) return t_addr_cmd_vector;
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function precharge_bank ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1;
bank : in natural range 0 to 2**c_max_ba_bits -1
) return t_addr_cmd_vector;
function activate ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
row : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1
) return t_addr_cmd_vector;
function write ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector;
function read ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector;
function refresh ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function self_refresh_entry ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function load_mode ( config_rec : in t_addr_cmd_config_rec;
mode_register_num : in natural range 0 to 3;
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
ranks : in natural range 0 to 2**c_max_ranks -1;
remap_addr_and_ba : in boolean
) return t_addr_cmd_vector;
function dll_reset ( config_rec : in t_addr_cmd_config_rec;
mode_reg_val : in std_logic_vector;
rank_num : in natural range 0 to 2**c_max_ranks - 1;
reorder_addr_bits : in boolean
) return t_addr_cmd_vector;
function enter_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function maintain_pd_or_sr ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function exit_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function ZQCS ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function ZQCL ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector;
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector;
function program_rdimm_register ( config_rec : in t_addr_cmd_config_rec;
control_word_addr : in std_logic_vector(3 downto 0);
control_word_data : in std_logic_vector(3 downto 0)
) return t_addr_cmd_vector;
-- -------------------------------------------------------------
-- the following function sets up the odt settings
-- NOTES: currently only supports DDR/DDR2 memories
-- -------------------------------------------------------------
-- odt setting as implemented in the altera high-performance controller for ddr2 memories
function set_odt_values (ranks : natural;
ranks_per_slot : natural;
mem_type : in string
) return t_odt_array;
-- -------------------------------------------------------------
-- the following function enables assignment to the constant config_rec
-- -------------------------------------------------------------
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
num_ranks : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec;
-- The non-levelled sequencer doesn't make a distinction between CS_WIDTH and NUM_RANKS. In this case,
-- just set the two to be the same.
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec;
-- -------------------------------------------------------------
-- the following function and procedure unpack address and
-- command signals from the t_addr_cmd_vector format
-- -------------------------------------------------------------
procedure unpack_addr_cmd_vector( addr_cmd_vector : in t_addr_cmd_vector;
config_rec : in t_addr_cmd_config_rec;
addr : out std_logic_vector;
ba : out std_logic_vector;
cas_n : out std_logic_vector;
ras_n : out std_logic_vector;
we_n : out std_logic_vector;
cke : out std_logic_vector;
cs_n : out std_logic_vector;
odt : out std_logic_vector;
rst_n : out std_logic_vector);
procedure unpack_addr_cmd_vector( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal addr : out std_logic_vector;
signal ba : out std_logic_vector;
signal cas_n : out std_logic_vector;
signal ras_n : out std_logic_vector;
signal we_n : out std_logic_vector;
signal cke : out std_logic_vector;
signal cs_n : out std_logic_vector;
signal odt : out std_logic_vector;
signal rst_n : out std_logic_vector);
-- -------------------------------------------------------------
-- the following functions perform bit masking to 0 or 1 (as
-- specified by mask_value) to a chosen address/command signal (signal_name)
-- across all signal bits or to a selected bit (mask_bit)
-- -------------------------------------------------------------
-- mask all signal bits procedure
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic) return t_addr_cmd_vector;
procedure mask( config_rec : in t_addr_cmd_config_rec;
signal addr_cmd_vector : inout t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic);
-- mask signal bit (mask_bit) procedure
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic;
mask_bit : in natural) return t_addr_cmd_vector;
--
end ddr_ctrl_ip_phy_alt_mem_phy_addr_cmd_pkg;
--
package body ddr_ctrl_ip_phy_alt_mem_phy_addr_cmd_pkg IS
-- -------------------------------------------------------------
-- Basic functions for a single command
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- defaults the bus no JEDEC abbreviated name
-- -------------------------------------------------------------
function defaults ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.addr := 0;
v_retval.ba := 0;
v_retval.cas_n := false;
v_retval.ras_n := false;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1;
v_retval.odt := 0;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- resets the addr/cmd signal (Same as default with cke and rst_n 0 )
-- -------------------------------------------------------------
function reset ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := defaults(config_rec);
v_retval.cke := 0;
if config_rec.mem_type = DDR3 then
v_retval.rst_n := true;
end if;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues deselect (command) JEDEC abbreviated name: DES
-- -------------------------------------------------------------
function deselect ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := previous;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a precharge all command JEDEC abbreviated name: PREA
-- -------------------------------------------------------------
function precharge_all( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned( c_max_addr_bits -1 downto 0);
begin
v_retval := previous;
v_addr := to_unsigned(previous.addr, c_max_addr_bits);
v_addr(10) := '1'; -- set AP bit high
v_retval.addr := to_integer(v_addr);
v_retval.ras_n := true;
v_retval.cas_n := false;
v_retval.we_n := true;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) - 1 - ranks;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- precharge (close) a bank JEDEC abbreviated name: PRE
-- -------------------------------------------------------------
function precharge_bank( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1;
bank : in natural range 0 to 2**c_max_ba_bits -1
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned( c_max_addr_bits -1 downto 0);
begin
v_retval := previous;
v_addr := to_unsigned(previous.addr, c_max_addr_bits);
v_addr(10) := '0'; -- set AP bit low
v_retval.addr := to_integer(v_addr);
v_retval.ba := bank;
v_retval.ras_n := true;
v_retval.cas_n := false;
v_retval.we_n := true;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) - ranks;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- Issues a activate (open row) JEDEC abbreviated name: ACT
-- -------------------------------------------------------------
function activate (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
bank : in natural range 0 to 2**c_max_ba_bits - 1;
row : in natural range 0 to 2**c_max_addr_bits - 1;
ranks : in natural range 0 to 2**c_max_ranks - 1
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.addr := row;
v_retval.ba := bank;
v_retval.cas_n := false;
v_retval.ras_n := true;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := previous.odt;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a write command JEDEC abbreviated name:WR, WRA
-- WRS4, WRAS4
-- WRS8, WRAS8
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL
-- Auto Precharge (AP)
-- -------------------------------------------------------------
function write (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks -1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned(c_max_addr_bits-1 downto 0);
begin
-- calculate correct address signal
v_addr := to_unsigned(col, c_max_addr_bits);
-- note pin A10 is used for AP, therfore shift the value from A10 onto A11.
v_retval.addr := to_integer(v_addr(9 downto 0));
if v_addr(10) = '1' then
v_retval.addr := v_retval.addr + 2**11;
end if;
if auto_prech = true then -- set AP bit (A10)
v_retval.addr := v_retval.addr + 2**10;
end if;
if config_rec.mem_type = DDR3 then
if op_length = 8 then -- set BL_OTF sel bit (A12)
v_retval.addr := v_retval.addr + 2**12;
elsif op_length = 4 then
null;
else
report ac_report_prefix & "DDR3 DRAM only supports writes of burst length 4 or 8, the requested length was: " & integer'image(op_length) severity failure;
end if;
elsif config_rec.mem_type = DDR2 or config_rec.mem_type = DDR then
null;
else
report ac_report_prefix & "only DDR memories are supported for memory writes" severity failure;
end if;
-- set a/c signal assignments for write
v_retval.ba := bank;
v_retval.cas_n := true;
v_retval.ras_n := false;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := ranks;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a read command JEDEC abbreviated name: RD, RDA
-- RDS4, RDAS4
-- RDS8, RDAS8
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL, Auto Precharge (AP)
-- -------------------------------------------------------------
function read (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks -1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned(c_max_addr_bits-1 downto 0);
begin
-- calculate correct address signal
v_addr := to_unsigned(col, c_max_addr_bits);
-- note pin A10 is used for AP, therfore shift the value from A10 onto A11.
v_retval.addr := to_integer(v_addr(9 downto 0));
if v_addr(10) = '1' then
v_retval.addr := v_retval.addr + 2**11;
end if;
if auto_prech = true then -- set AP bit (A10)
v_retval.addr := v_retval.addr + 2**10;
end if;
if config_rec.mem_type = DDR3 then
if op_length = 8 then -- set BL_OTF sel bit (A12)
v_retval.addr := v_retval.addr + 2**12;
elsif op_length = 4 then
null;
else
report ac_report_prefix & "DDR3 DRAM only supports reads of burst length 4 or 8" severity failure;
end if;
elsif config_rec.mem_type = DDR2 or config_rec.mem_type = DDR then
null;
else
report ac_report_prefix & "only DDR memories are supported for memory reads" severity failure;
end if;
-- set a/c signals for read command
v_retval.ba := bank;
v_retval.cas_n := true;
v_retval.ras_n := false;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := 0;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a refresh command JEDEC abbreviated name: REF
-- -------------------------------------------------------------
function refresh (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := previous;
v_retval.cas_n := true;
v_retval.ras_n := true;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.rst_n := false;
-- addr, BA and ODT are don't care therfore leave as previous value
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a mode register set command JEDEC abbreviated name: MRS
-- -------------------------------------------------------------
function load_mode ( config_rec : in t_addr_cmd_config_rec;
mode_register_num : in natural range 0 to 3;
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
ranks : in natural range 0 to 2**c_max_ranks -1;
remap_addr_and_ba : in boolean
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr_remap : unsigned(c_max_mode_reg_bit downto 0);
begin
v_retval.cas_n := true;
v_retval.ras_n := true;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := 0;
v_retval.rst_n := false;
v_retval.ba := mode_register_num;
v_retval.addr := to_integer(unsigned(mode_reg_value));
if remap_addr_and_ba = true then
v_addr_remap := unsigned(mode_reg_value);
v_addr_remap(8 downto 7) := v_addr_remap(7) & v_addr_remap(8);
v_addr_remap(6 downto 5) := v_addr_remap(5) & v_addr_remap(6);
v_addr_remap(4 downto 3) := v_addr_remap(3) & v_addr_remap(4);
v_retval.addr := to_integer(v_addr_remap);
v_addr_remap := to_unsigned(mode_register_num, c_max_mode_reg_bit + 1);
v_addr_remap(1 downto 0) := v_addr_remap(0) & v_addr_remap(1);
v_retval.ba := to_integer(v_addr_remap);
end if;
return v_retval;
end function;
-- -------------------------------------------------------------
-- maintains SR or PD mode on slected ranks.
-- -------------------------------------------------------------
function maintain_pd_or_sr (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := previous;
v_retval.cke := (2 ** config_rec.num_ranks) - 1 - ranks;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (short) JEDEC abbreviated name: ZQCS
-- NOTE - can only be issued to a single RANK at a time.
-- -------------------------------------------------------------
function ZQCS (config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.cas_n := false;
v_retval.ras_n := false;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - rank;
v_retval.rst_n := false;
v_retval.addr := 0; -- clear bit 10
v_retval.ba := 0;
v_retval.odt := 0;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (long) JEDEC abbreviated name: ZQCL
-- NOTE - can only be issued to a single RANK at a time.
-- -------------------------------------------------------------
function ZQCL (config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.cas_n := false;
v_retval.ras_n := false;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - rank;
v_retval.rst_n := false;
v_retval.addr := 1024; -- set bit 10
v_retval.ba := 0;
v_retval.odt := 0;
return v_retval;
end function;
-- -------------------------------------------------------------
-- functions acting on all clock cycles from whatever rate
-- in halfrate clock domain issues 1 command per clock
-- in quarter rate issues 1 command per clock
-- In the above cases they will be correctly aligned using the
-- ALTMEMPHY 2T and 4T SDC
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- defaults the bus no JEDEC abbreviated name
-- -------------------------------------------------------------
function defaults (config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => defaults(config_rec));
return v_retval;
end function;
-- -------------------------------------------------------------
-- resets the addr/cmd signal (same as default with cke 0)
-- -------------------------------------------------------------
function reset (config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => reset(config_rec));
return v_retval;
end function;
function int_pup_reset (config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector
is
variable v_addr_cmd_config_rst : t_addr_cmd_config_rec;
begin
v_addr_cmd_config_rst := config_rec;
v_addr_cmd_config_rst.num_ranks := c_max_ranks;
return reset(v_addr_cmd_config_rst);
end function;
-- -------------------------------------------------------------
-- issues a deselect command JEDEC abbreviated name: DES
-- -------------------------------------------------------------
function deselect ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector
) return t_addr_cmd_vector
is
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
variable v_retval : t_addr_cmd_vector(a_previous'range);
begin
for rate in a_previous'range loop
v_retval(rate) := deselect(config_rec, a_previous(a_previous'high));
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a precharge all command JEDEC abbreviated name: PREA
-- -------------------------------------------------------------
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in a_previous'range loop
v_retval(rate) := precharge_all(config_rec, previous(a_previous'high), ranks);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- precharge (close) a bank JEDEC abbreviated name: PRE
-- -------------------------------------------------------------
function precharge_bank ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1;
bank : in natural range 0 to 2**c_max_ba_bits -1
) return t_addr_cmd_vector
is
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in a_previous'range loop
v_retval(rate) := precharge_bank(config_rec, previous(a_previous'high), ranks, bank);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a activate (open row) JEDEC abbreviated name: ACT
-- -------------------------------------------------------------
function activate ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
row : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := activate(config_rec, previous(previous'high), bank, row, ranks);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a write command JEDEC abbreviated name:WR, WRA
-- WRS4, WRAS4
-- WRS8, WRAS8
--
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL
-- Auto Precharge (AP)
-- -------------------------------------------------------------
function write ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := write(config_rec, previous(previous'high), bank, col, ranks, op_length, auto_prech);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a read command JEDEC abbreviated name: RD, RDA
-- RDS4, RDAS4
-- RDS8, RDAS8
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL, Auto Precharge (AP)
-- -------------------------------------------------------------
function read ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := read(config_rec, previous(previous'high), bank, col, ranks, op_length, auto_prech);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a refresh command JEDEC abbreviated name: REF
-- -------------------------------------------------------------
function refresh (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
)return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := refresh(config_rec, previous(previous'high), ranks);
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a self_refresh_entry command JEDEC abbreviated name: SRE
-- -------------------------------------------------------------
function self_refresh_entry (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
)return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := enter_sr_pd_mode(config_rec, refresh(config_rec, previous, ranks), ranks);
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a self_refresh exit or power_down exit command
-- JEDEC abbreviated names: SRX, PDX
-- -------------------------------------------------------------
function exit_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
variable v_mask_workings : std_logic_vector(config_rec.num_ranks -1 downto 0);
variable v_mask_workings_b : std_logic_vector(config_rec.num_ranks -1 downto 0);
begin
v_retval := maintain_pd_or_sr(config_rec, previous, ranks);
v_mask_workings_b := std_logic_vector(to_unsigned(ranks, config_rec.num_ranks));
for rate in 0 to config_rec.cmds_per_clk - 1 loop
v_mask_workings := std_logic_vector(to_unsigned(v_retval(rate).cke, config_rec.num_ranks));
for i in v_mask_workings_b'range loop
v_mask_workings(i) := v_mask_workings(i) or v_mask_workings_b(i);
end loop;
if rate >= config_rec.cmds_per_clk / 2 then -- maintain command but clear CS of subsequenct command slots
v_retval(rate).cke := to_integer(unsigned(v_mask_workings)); -- almost irrelevant. but optimises logic slightly for Quater rate
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- cause the selected ranks to enter Self-refresh or Powerdown mode
-- JEDEC abbreviated names: PDE,
-- SRE (if a refresh is concurrently issued to the same ranks)
-- -------------------------------------------------------------
function enter_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
variable v_mask_workings : std_logic_vector(config_rec.num_ranks -1 downto 0);
variable v_mask_workings_b : std_logic_vector(config_rec.num_ranks -1 downto 0);
begin
v_retval := previous;
v_mask_workings_b := std_logic_vector(to_unsigned(ranks, config_rec.num_ranks));
for rate in 0 to config_rec.cmds_per_clk - 1 loop
if rate >= config_rec.cmds_per_clk / 2 then -- maintain command but clear CS of subsequenct command slots
v_mask_workings := std_logic_vector(to_unsigned(v_retval(rate).cke, config_rec.num_ranks));
for i in v_mask_workings_b'range loop
v_mask_workings(i) := v_mask_workings(i) and not v_mask_workings_b(i);
end loop;
v_retval(rate).cke := to_integer(unsigned(v_mask_workings)); -- almost irrelevant. but optimises logic slightly for Quater rate
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- Issues a mode register set command JEDEC abbreviated name: MRS
-- -------------------------------------------------------------
function load_mode ( config_rec : in t_addr_cmd_config_rec;
mode_register_num : in natural range 0 to 3;
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
ranks : in natural range 0 to 2**c_max_ranks -1;
remap_addr_and_ba : in boolean
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => load_mode(config_rec, mode_register_num, mode_reg_value, ranks, remap_addr_and_ba));
for rate in v_retval'range loop
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- maintains SR or PD mode on slected ranks.
-- NOTE: does not affect previous command
-- -------------------------------------------------------------
function maintain_pd_or_sr ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for command in v_retval'range loop
v_retval(command) := maintain_pd_or_sr(config_rec, previous(command), ranks);
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (long) JEDEC abbreviated name: ZQCL
-- NOTE - can only be issued to a single RANK ata a time.
-- -------------------------------------------------------------
function ZQCL ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in v_retval'range loop
v_retval(command) := ZQCL(config_rec, rank);
if command * 2 /= config_rec.cmds_per_clk then
v_retval(command).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (short) JEDEC abbreviated name: ZQCS
-- NOTE - can only be issued to a single RANK ata a time.
-- -------------------------------------------------------------
function ZQCS ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in v_retval'range loop
v_retval(command) := ZQCS(config_rec, rank);
if command * 2 /= config_rec.cmds_per_clk then
v_retval(command).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- ----------------------
-- Additional Rank manipulation functions (main use DDR3)
-- -------------
-- -----------------------------------
-- set the chip select for a group of ranks
-- -----------------------------------
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_mask_workings : std_logic_vector(config_rec.num_cs_bits-1 downto 0);
begin
v_retval := record_to_mask;
v_mask_workings := std_logic_vector(to_unsigned(record_to_mask.cs_n, config_rec.num_cs_bits));
for i in mem_ac_swapped_ranks'range loop
v_mask_workings(i):= v_mask_workings(i) or not mem_ac_swapped_ranks(i);
end loop;
v_retval.cs_n := to_integer(unsigned(v_mask_workings));
return v_retval;
end function;
-- -----------------------------------
-- inverse of the above
-- -----------------------------------
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_mask_workings : std_logic_vector(config_rec.num_cs_bits-1 downto 0);
begin
v_retval := record_to_mask;
v_mask_workings := std_logic_vector(to_unsigned(record_to_mask.cs_n, config_rec.num_cs_bits));
for i in mem_ac_swapped_ranks'range loop
v_mask_workings(i):= v_mask_workings(i) or mem_ac_swapped_ranks(i);
end loop;
v_retval.cs_n := to_integer(unsigned(v_mask_workings));
return v_retval;
end function;
-- -----------------------------------
-- set the chip select for a group of ranks in a way which handles diffrent rates
-- -----------------------------------
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in record_to_mask'range loop
v_retval(command) := all_unreversed_ranks(config_rec, record_to_mask(command), mem_ac_swapped_ranks);
end loop;
return v_retval;
end function;
-- -----------------------------------
-- inverse of the above handling ranks
-- -----------------------------------
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in record_to_mask'range loop
v_retval(command) := all_reversed_ranks(config_rec, record_to_mask(command), mem_ac_swapped_ranks);
end loop;
return v_retval;
end function;
-- --------------------------------------------------
-- Program a single control word onto RDIMM.
-- This is accomplished rather goofily by asserting all chip selects
-- and then writing out both the addr/data of the word onto the addr/ba bus
-- --------------------------------------------------
function program_rdimm_register ( config_rec : in t_addr_cmd_config_rec;
control_word_addr : in std_logic_vector(3 downto 0);
control_word_data : in std_logic_vector(3 downto 0)
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable ba : std_logic_vector(2 downto 0);
variable addr : std_logic_vector(4 downto 0);
begin
v_retval := defaults(config_rec);
v_retval.cs_n := 0;
ba := control_word_addr(3) & control_word_data(3) & control_word_data(2);
v_retval.ba := to_integer(unsigned(ba));
addr := control_word_data(1) & control_word_data(0) & control_word_addr(2) &
control_word_addr(1) & control_word_addr(0);
v_retval.addr := to_integer(unsigned(addr));
return v_retval;
end function;
function program_rdimm_register ( config_rec : in t_addr_cmd_config_rec;
control_word_addr : in std_logic_vector(3 downto 0);
control_word_data : in std_logic_vector(3 downto 0)
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => program_rdimm_register(config_rec, control_word_addr, control_word_data));
return v_retval;
end function;
-- --------------------------------------------------
-- overloaded functions, to simplify use, or provide simplified functionality
-- --------------------------------------------------
-- ----------------------------------------------------
-- Precharge all, defaulting all bits.
-- ----------------------------------------------------
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
v_retval := precharge_all(config_rec, v_retval, ranks);
return v_retval;
end function;
-- ----------------------------------------------------
-- perform DLL reset through mode registers
-- ----------------------------------------------------
function dll_reset ( config_rec : in t_addr_cmd_config_rec;
mode_reg_val : in std_logic_vector;
rank_num : in natural range 0 to 2**c_max_ranks - 1;
reorder_addr_bits : in boolean
) return t_addr_cmd_vector is
variable int_mode_reg : std_logic_vector(mode_reg_val'range);
variable output : t_addr_cmd_vector(0 to config_rec.cmds_per_clk - 1);
begin
int_mode_reg := mode_reg_val;
int_mode_reg(8) := '1'; -- set DLL reset bit.
output := load_mode(config_rec, 0, int_mode_reg, rank_num, reorder_addr_bits);
return output;
end function;
-- -------------------------------------------------------------
-- package configuration functions
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- the following function sets up the odt settings
-- NOTES: supports DDR/DDR2/DDR3 SDRAM memories
-- -------------------------------------------------------------
function set_odt_values (ranks : natural;
ranks_per_slot : natural;
mem_type : in string
) return t_odt_array is
variable v_num_slots : natural;
variable v_cs : natural range 0 to ranks-1;
variable v_odt_values : t_odt_array(0 to ranks-1);
variable v_cs_addr : unsigned(ranks-1 downto 0);
begin
if mem_type = "DDR" then
-- ODT not supported for DDR memory so set default off
for v_cs in 0 to ranks-1 loop
v_odt_values(v_cs).write := 0;
v_odt_values(v_cs).read := 0;
end loop;
elsif mem_type = "DDR2" then
-- odt setting as implemented in the altera high-performance controller for ddr2 memories
assert (ranks rem ranks_per_slot = 0) report ac_report_prefix & "number of ranks per slot must be a multiple of number of ranks" severity failure;
v_num_slots := ranks/ranks_per_slot;
if v_num_slots = 1 then
-- special condition for 1 slot (i.e. DIMM) (2^n, n=0,1,2,... ranks only)
-- set odt on one chip for writes and no odt for reads
for v_cs in 0 to ranks-1 loop
v_odt_values(v_cs).write := 2**v_cs; -- on on the rank being written to
v_odt_values(v_cs).read := 0;
end loop;
else
-- if > 1 slot, set 1 odt enable on neighbouring slot for read and write
-- as an example consider the below for 4 slots with 2 ranks per slot
-- access to CS[0] or CS[1], enable ODT[2] or ODT[3]
-- access to CS[2] or CS[3], enable ODT[0] or ODT[1]
-- access to CS[4] or CS[5], enable ODT[6] or ODT[7]
-- access to CS[6] or CS[7], enable ODT[4] or ODT[5]
-- the logic below implements the above for varying ranks and ranks_per slot
-- under the condition that ranks/ranks_per_slot is integer
for v_cs in 0 to ranks-1 loop
v_cs_addr := to_unsigned(v_cs, ranks);
v_cs_addr(ranks_per_slot-1) := not v_cs_addr(ranks_per_slot-1);
v_odt_values(v_cs).write := 2**to_integer(v_cs_addr);
v_odt_values(v_cs).read := v_odt_values(v_cs).write;
end loop;
end if;
elsif mem_type = "DDR3" then
assert (ranks rem ranks_per_slot = 0) report ac_report_prefix & "number of ranks per slot must be a multiple of number of ranks" severity failure;
v_num_slots := ranks/ranks_per_slot;
if v_num_slots = 1 then
-- special condition for 1 slot (i.e. DIMM) (2^n, n=0,1,2,... ranks only)
-- set odt on one chip for writes and no odt for reads
for v_cs in 0 to ranks-1 loop
v_odt_values(v_cs).write := 2**v_cs; -- on on the rank being written to
v_odt_values(v_cs).read := 0;
end loop;
else
-- if > 1 slot, set 1 odt enable on neighbouring slot for read and write
-- as an example consider the below for 4 slots with 2 ranks per slot
-- access to CS[0] or CS[1], enable ODT[2] or ODT[3]
-- access to CS[2] or CS[3], enable ODT[0] or ODT[1]
-- access to CS[4] or CS[5], enable ODT[6] or ODT[7]
-- access to CS[6] or CS[7], enable ODT[4] or ODT[5]
-- the logic below implements the above for varying ranks and ranks_per slot
-- under the condition that ranks/ranks_per_slot is integer
for v_cs in 0 to ranks-1 loop
v_cs_addr := to_unsigned(v_cs, ranks);
v_cs_addr(ranks_per_slot-1) := not v_cs_addr(ranks_per_slot-1);
v_odt_values(v_cs).write := 2**to_integer(v_cs_addr) + 2**(v_cs); -- turn on a neighbouring slots cs and current rank being written to
v_odt_values(v_cs).read := 2**to_integer(v_cs_addr);
end loop;
end if;
else
report ac_report_prefix & "unknown mem_type specified in the set_odt_values function in addr_cmd_pkg package" severity failure;
end if;
return v_odt_values;
end function;
-- -----------------------------------------------------------
-- set constant values to config_rec
-- ----------------------------------------------------------
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
num_ranks : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec
is
variable v_config_rec : t_addr_cmd_config_rec;
begin
v_config_rec.num_addr_bits := num_addr_bits;
v_config_rec.num_ba_bits := num_ba_bits;
v_config_rec.num_cs_bits := num_cs_bits;
v_config_rec.num_ranks := num_ranks;
v_config_rec.cmds_per_clk := dwidth_ratio/2;
if mem_type = "DDR" then
v_config_rec.mem_type := DDR;
elsif mem_type = "DDR2" then
v_config_rec.mem_type := DDR2;
elsif mem_type = "DDR3" then
v_config_rec.mem_type := DDR3;
else
report ac_report_prefix & "unknown mem_type specified in the set_config_rec function in addr_cmd_pkg package" severity failure;
end if;
return v_config_rec;
end function;
-- The non-levelled sequencer doesn't make a distinction between CS_WIDTH and NUM_RANKS. In this case,
-- just set the two to be the same.
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec
is
begin
return set_config_rec(num_addr_bits, num_ba_bits, num_cs_bits, num_cs_bits, dwidth_ratio, mem_type);
end function;
-- -----------------------------------------------------------
-- unpack and pack address and command signals from and to t_addr_cmd_vector
-- -----------------------------------------------------------
-- -------------------------------------------------------------
-- convert from t_addr_cmd_vector to expanded addr/cmd signals
-- -------------------------------------------------------------
procedure unpack_addr_cmd_vector( addr_cmd_vector : in t_addr_cmd_vector;
config_rec : in t_addr_cmd_config_rec;
addr : out std_logic_vector;
ba : out std_logic_vector;
cas_n : out std_logic_vector;
ras_n : out std_logic_vector;
we_n : out std_logic_vector;
cke : out std_logic_vector;
cs_n : out std_logic_vector;
odt : out std_logic_vector;
rst_n : out std_logic_vector
)
is
variable v_mem_if_ranks : natural range 0 to 2**c_max_ranks - 1;
variable v_vec_len : natural range 1 to 4;
variable v_addr : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_addr_bits - 1 downto 0);
variable v_ba : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ba_bits - 1 downto 0);
variable v_odt : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_cs_n : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_cs_bits - 1 downto 0);
variable v_cke : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_cas_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_ras_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_we_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_rst_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
begin
v_vec_len := config_rec.cmds_per_clk;
v_mem_if_ranks := config_rec.num_ranks;
for v_i in 0 to v_vec_len-1 loop
assert addr_cmd_vector(v_i).addr < 2**config_rec.num_addr_bits report ac_report_prefix &
"value of addr exceeds range of number of address bits in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).ba < 2**config_rec.num_ba_bits report ac_report_prefix &
"value of ba exceeds range of number of bank address bits in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).odt < 2**v_mem_if_ranks report ac_report_prefix &
"value of odt exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).cs_n < 2**config_rec.num_cs_bits report ac_report_prefix &
"value of cs_n exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).cke < 2**v_mem_if_ranks report ac_report_prefix &
"value of cke exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
v_addr((v_i+1)*config_rec.num_addr_bits - 1 downto v_i*config_rec.num_addr_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).addr,config_rec.num_addr_bits));
v_ba((v_i+1)*config_rec.num_ba_bits - 1 downto v_i*config_rec.num_ba_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).ba,config_rec.num_ba_bits));
v_cke((v_i+1)*v_mem_if_ranks - 1 downto v_i*v_mem_if_ranks) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).cke,v_mem_if_ranks));
v_cs_n((v_i+1)*config_rec.num_cs_bits - 1 downto v_i*config_rec.num_cs_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).cs_n,config_rec.num_cs_bits));
v_odt((v_i+1)*v_mem_if_ranks - 1 downto v_i*v_mem_if_ranks) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).odt,v_mem_if_ranks));
if (addr_cmd_vector(v_i).cas_n) then v_cas_n(v_i) := '0'; else v_cas_n(v_i) := '1'; end if;
if (addr_cmd_vector(v_i).ras_n) then v_ras_n(v_i) := '0'; else v_ras_n(v_i) := '1'; end if;
if (addr_cmd_vector(v_i).we_n) then v_we_n(v_i) := '0'; else v_we_n(v_i) := '1'; end if;
if (addr_cmd_vector(v_i).rst_n) then v_rst_n(v_i) := '0'; else v_rst_n(v_i) := '1'; end if;
end loop;
addr := v_addr;
ba := v_ba;
cke := v_cke;
cs_n := v_cs_n;
odt := v_odt;
cas_n := v_cas_n;
ras_n := v_ras_n;
we_n := v_we_n;
rst_n := v_rst_n;
end procedure;
procedure unpack_addr_cmd_vector( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal addr : out std_logic_vector;
signal ba : out std_logic_vector;
signal cas_n : out std_logic_vector;
signal ras_n : out std_logic_vector;
signal we_n : out std_logic_vector;
signal cke : out std_logic_vector;
signal cs_n : out std_logic_vector;
signal odt : out std_logic_vector;
signal rst_n : out std_logic_vector
)
is
variable v_mem_if_ranks : natural range 0 to 2**c_max_ranks - 1;
variable v_vec_len : natural range 1 to 4;
variable v_seq_ac_addr : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_addr_bits - 1 downto 0);
variable v_seq_ac_ba : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ba_bits - 1 downto 0);
variable v_seq_ac_cas_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_seq_ac_ras_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_seq_ac_we_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_seq_ac_cke : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_seq_ac_cs_n : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_cs_bits - 1 downto 0);
variable v_seq_ac_odt : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_seq_ac_rst_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
begin
unpack_addr_cmd_vector (
addr_cmd_vector,
config_rec,
v_seq_ac_addr,
v_seq_ac_ba,
v_seq_ac_cas_n,
v_seq_ac_ras_n,
v_seq_ac_we_n,
v_seq_ac_cke,
v_seq_ac_cs_n,
v_seq_ac_odt,
v_seq_ac_rst_n);
addr <= v_seq_ac_addr;
ba <= v_seq_ac_ba;
cas_n <= v_seq_ac_cas_n;
ras_n <= v_seq_ac_ras_n;
we_n <= v_seq_ac_we_n;
cke <= v_seq_ac_cke;
cs_n <= v_seq_ac_cs_n;
odt <= v_seq_ac_odt;
rst_n <= v_seq_ac_rst_n;
end procedure;
-- -----------------------------------------------------------
-- function to mask each bit of signal signal_name in addr_cmd_
-- -----------------------------------------------------------
-- -----------------------------------------------------------
-- function to mask each bit of signal signal_name in addr_cmd_vector with mask_value
-- -----------------------------------------------------------
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic
) return t_addr_cmd_vector
is
variable v_i : integer;
variable v_addr_cmd_vector : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_addr_cmd_vector := addr_cmd_vector;
for v_i in 0 to (config_rec.cmds_per_clk)-1 loop
case signal_name is
when addr => if (mask_value = '0') then v_addr_cmd_vector(v_i).addr := 0; else v_addr_cmd_vector(v_i).addr := (2 ** config_rec.num_addr_bits) - 1; end if;
when ba => if (mask_value = '0') then v_addr_cmd_vector(v_i).ba := 0; else v_addr_cmd_vector(v_i).ba := (2 ** config_rec.num_ba_bits) - 1; end if;
when cas_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).cas_n := true; else v_addr_cmd_vector(v_i).cas_n := false; end if;
when ras_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).ras_n := true; else v_addr_cmd_vector(v_i).ras_n := false; end if;
when we_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).we_n := true; else v_addr_cmd_vector(v_i).we_n := false; end if;
when cke => if (mask_value = '0') then v_addr_cmd_vector(v_i).cke := 0; else v_addr_cmd_vector(v_i).cke := (2**config_rec.num_ranks) -1; end if;
when cs_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).cs_n := 0; else v_addr_cmd_vector(v_i).cs_n := (2**config_rec.num_cs_bits) -1; end if;
when odt => if (mask_value = '0') then v_addr_cmd_vector(v_i).odt := 0; else v_addr_cmd_vector(v_i).odt := (2**config_rec.num_ranks) -1; end if;
when rst_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).rst_n := true; else v_addr_cmd_vector(v_i).rst_n := false; end if;
when others => report ac_report_prefix & "bit masking not supported for the given signal name" severity failure;
end case;
end loop;
return v_addr_cmd_vector;
end function;
-- -----------------------------------------------------------
-- procedure to mask each bit of signal signal_name in addr_cmd_vector with mask_value
-- -----------------------------------------------------------
procedure mask( config_rec : in t_addr_cmd_config_rec;
signal addr_cmd_vector : inout t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic
)
is
variable v_i : integer;
begin
for v_i in 0 to (config_rec.cmds_per_clk)-1 loop
case signal_name is
when addr => if (mask_value = '0') then addr_cmd_vector(v_i).addr <= 0; else addr_cmd_vector(v_i).addr <= (2 ** config_rec.num_addr_bits) - 1; end if;
when ba => if (mask_value = '0') then addr_cmd_vector(v_i).ba <= 0; else addr_cmd_vector(v_i).ba <= (2 ** config_rec.num_ba_bits) - 1; end if;
when cas_n => if (mask_value = '0') then addr_cmd_vector(v_i).cas_n <= true; else addr_cmd_vector(v_i).cas_n <= false; end if;
when ras_n => if (mask_value = '0') then addr_cmd_vector(v_i).ras_n <= true; else addr_cmd_vector(v_i).ras_n <= false; end if;
when we_n => if (mask_value = '0') then addr_cmd_vector(v_i).we_n <= true; else addr_cmd_vector(v_i).we_n <= false; end if;
when cke => if (mask_value = '0') then addr_cmd_vector(v_i).cke <= 0; else addr_cmd_vector(v_i).cke <= (2**config_rec.num_ranks) -1; end if;
when cs_n => if (mask_value = '0') then addr_cmd_vector(v_i).cs_n <= 0; else addr_cmd_vector(v_i).cs_n <= (2**config_rec.num_cs_bits) -1; end if;
when odt => if (mask_value = '0') then addr_cmd_vector(v_i).odt <= 0; else addr_cmd_vector(v_i).odt <= (2**config_rec.num_ranks) -1; end if;
when rst_n => if (mask_value = '0') then addr_cmd_vector(v_i).rst_n <= true; else addr_cmd_vector(v_i).rst_n <= false; end if;
when others => report ac_report_prefix & "masking not supported for the given signal name" severity failure;
end case;
end loop;
end procedure;
-- -----------------------------------------------------------
-- function to mask a given bit (mask_bit) of signal signal_name in addr_cmd_vector with mask_value
-- -----------------------------------------------------------
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic;
mask_bit : in natural
) return t_addr_cmd_vector
is
variable v_i : integer;
variable v_addr : std_logic_vector(config_rec.num_addr_bits-1 downto 0); -- v_addr is bit vector of address
variable v_ba : std_logic_vector(config_rec.num_ba_bits-1 downto 0); -- v_addr is bit vector of bank address
variable v_vec_len : natural range 0 to 4;
variable v_addr_cmd_vector : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_addr_cmd_vector := addr_cmd_vector;
v_vec_len := config_rec.cmds_per_clk;
for v_i in 0 to v_vec_len-1 loop
case signal_name is
when addr =>
v_addr := std_logic_vector(to_unsigned(v_addr_cmd_vector(v_i).addr,v_addr'length));
v_addr(mask_bit) := mask_value;
v_addr_cmd_vector(v_i).addr := to_integer(unsigned(v_addr));
when ba =>
v_ba := std_logic_vector(to_unsigned(v_addr_cmd_vector(v_i).ba,v_ba'length));
v_ba(mask_bit) := mask_value;
v_addr_cmd_vector(v_i).ba := to_integer(unsigned(v_ba));
when others =>
report ac_report_prefix & "bit masking not supported for the given signal name" severity failure;
end case;
end loop;
return v_addr_cmd_vector;
end function;
--
end ddr_ctrl_ip_phy_alt_mem_phy_addr_cmd_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : iram addressing package for the non-levelling AFI PHY sequencer
-- The iram address package (alt_mem_phy_iram_addr_pkg) is
-- used to define the base addresses used for iram writes
-- during calibration.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ddr_ctrl_ip_phy_alt_mem_phy_iram_addr_pkg IS
constant c_ihi_size : natural := 8;
type t_base_hdr_addresses is record
base_hdr : natural;
rrp : natural;
safe_dummy : natural;
required_addr_bits : natural;
end record;
function defaults return t_base_hdr_addresses;
function rrp_pll_phase_mult (dwidth_ratio : in natural;
dqs_capture : in natural
)
return natural;
function iram_wd_for_full_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural;
function iram_wd_for_one_pin_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural;
function calc_iram_addresses ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
num_ranks : in natural;
dqs_capture : in natural
)
return t_base_hdr_addresses;
--
end ddr_ctrl_ip_phy_alt_mem_phy_iram_addr_pkg;
--
package body ddr_ctrl_ip_phy_alt_mem_phy_iram_addr_pkg IS
-- set some safe default values
function defaults return t_base_hdr_addresses is
variable temp : t_base_hdr_addresses;
begin
temp.base_hdr := 0;
temp.rrp := 0;
temp.safe_dummy := 0;
temp.required_addr_bits := 1;
return temp;
end function;
-- this function determines now many times the PLL phases are swept through per pin
-- i.e. an n * 360 degree phase sweep
function rrp_pll_phase_mult (dwidth_ratio : in natural;
dqs_capture : in natural
)
return natural
is
variable v_output : natural;
begin
if dwidth_ratio = 2 and dqs_capture = 1 then
v_output := 2; -- if dqs_capture then a 720 degree sweep needed in FR
else
v_output := (dwidth_ratio/2);
end if;
return v_output;
end function;
-- function to calculate how many words are required for a rrp sweep over all pins
function iram_wd_for_full_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural
is
variable v_output : natural;
variable v_phase_mul : natural;
begin
-- determine the n * 360 degrees of sweep required
v_phase_mul := rrp_pll_phase_mult(dwidth_ratio, dqs_capture);
-- calculate output size
v_output := dq_pins * (((v_phase_mul * pll_phases) + 31) / 32);
return v_output;
end function;
-- function to calculate how many words are required for a rrp sweep over all pins
function iram_wd_for_one_pin_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural
is
variable v_output : natural;
variable v_phase_mul : natural;
begin
-- determine the n * 360 degrees of sweep required
v_phase_mul := rrp_pll_phase_mult(dwidth_ratio, dqs_capture);
-- calculate output size
v_output := ((v_phase_mul * pll_phases) + 31) / 32;
return v_output;
end function;
-- return iram addresses
function calc_iram_addresses ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
num_ranks : in natural;
dqs_capture : in natural
)
return t_base_hdr_addresses
is
variable working : t_base_hdr_addresses;
variable temp : natural;
variable v_required_words : natural;
begin
working.base_hdr := 0;
working.rrp := working.base_hdr + c_ihi_size;
-- work out required number of address bits
-- + for 1 full rrp calibration
v_required_words := iram_wd_for_full_rrp(dwidth_ratio, pll_phases, dq_pins, dqs_capture) + 2; -- +2 for header + footer
-- * loop per cs
v_required_words := v_required_words * num_ranks;
-- + for 1 rrp_seek result
v_required_words := v_required_words + 3; -- 1 header, 1 word result, 1 footer
-- + 2 mtp_almt passes
v_required_words := v_required_words + 2 * (iram_wd_for_one_pin_rrp(dwidth_ratio, pll_phases, dq_pins, dqs_capture) + 2);
-- + for 2 read_mtp result calculation
v_required_words := v_required_words + 3*2; -- 1 header, 1 word result, 1 footer
-- * possible dwidth_ratio/2 iterations for different ac_nt settings
v_required_words := v_required_words * (dwidth_ratio / 2);
working.safe_dummy := working.rrp + v_required_words;
temp := working.safe_dummy;
working.required_addr_bits := 0;
while (temp >= 1) loop
working.required_addr_bits := working.required_addr_bits + 1;
temp := temp /2;
end loop;
return working;
end function calc_iram_addresses;
--
END ddr_ctrl_ip_phy_alt_mem_phy_iram_addr_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : register package for the non-levelling AFI PHY sequencer
-- The registers package (alt_mem_phy_regs_pkg) is used to
-- combine the definition of the registers for the mmi status
-- registers and functions/procedures applied to the registers
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_record_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_constants_pkg.all;
--
package ddr_ctrl_ip_phy_alt_mem_phy_regs_pkg is
-- a prefix for all report signals to identify phy and sequencer block
--
constant regs_report_prefix : string := "ddr_ctrl_ip_phy_alt_mem_phy_seq (register package) : ";
-- ---------------------------------------------------------------
-- register declarations with associated functions of:
-- default - assign default values
-- write - write data into the reg (from avalon i/f)
-- read - read data from the reg (sent to the avalon i/f)
-- write_clear - clear reg to all zeros
-- ---------------------------------------------------------------
-- TYPE DECLARATIONS
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read Only Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- cal_status
type t_cal_status is record
iram_addr_width : std_logic_vector(3 downto 0);
out_of_mem : std_logic;
contested_access : std_logic;
cal_fail : std_logic;
cal_success : std_logic;
ctrl_err_code : std_logic_vector(7 downto 0);
trefi_failure : std_logic;
int_ac_1t : std_logic;
dqs_capture : std_logic;
iram_present : std_logic;
active_block : std_logic_vector(3 downto 0);
current_stage : std_logic_vector(7 downto 0);
end record;
-- codvw status
type t_codvw_status is record
cal_codvw_phase : std_logic_vector(7 downto 0);
cal_codvw_size : std_logic_vector(7 downto 0);
codvw_trk_shift : std_logic_vector(11 downto 0);
codvw_grt_one_dvw : std_logic;
end record t_codvw_status;
-- test status report
type t_test_status is record
ack_seen : std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
pll_mmi_err : std_logic_vector(1 downto 0);
pll_busy : std_logic;
end record;
-- define all the read only registers :
type t_ro_regs is record
cal_status : t_cal_status;
codvw_status : t_codvw_status;
test_status : t_test_status;
end record;
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read / Write Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Calibration control register
type t_hl_css is record
hl_css : std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
cal_start : std_logic;
end record t_hl_css;
-- Mode register A
type t_mr_register_a is record
mr0 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
mr1 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
end record t_mr_register_a;
-- Mode register B
type t_mr_register_b is record
mr2 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
mr3 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
end record t_mr_register_b;
-- algorithm parameterisation register
type t_parameterisation_reg_a is record
nominal_poa_phase_lead : std_logic_vector(3 downto 0);
maximum_poa_delay : std_logic_vector(3 downto 0);
num_phases_per_tck_pll : std_logic_vector(3 downto 0);
pll_360_sweeps : std_logic_vector(3 downto 0);
nominal_dqs_delay : std_logic_vector(2 downto 0);
extend_octrt_by : std_logic_vector(3 downto 0);
delay_octrt_by : std_logic_vector(3 downto 0);
end record;
-- test signal register
type t_if_test_reg is record
pll_phs_shft_phase_sel : natural range 0 to 15;
pll_phs_shft_up_wc : std_logic;
pll_phs_shft_dn_wc : std_logic;
ac_1t_toggle : std_logic; -- unused
tracking_period_ms : std_logic_vector(7 downto 0); -- 0 = as fast as possible approx in ms
tracking_units_are_10us : std_logic;
end record;
-- define all the read/write registers
type t_rw_regs is record
mr_reg_a : t_mr_register_a;
mr_reg_b : t_mr_register_b;
rw_hl_css : t_hl_css;
rw_param_reg : t_parameterisation_reg_a;
rw_if_test : t_if_test_reg;
end record;
-- >>>>>>>>>>>>>>>>>>>>>>>
-- Group all registers
-- >>>>>>>>>>>>>>>>>>>>>>>
type t_mmi_regs is record
rw_regs : t_rw_regs;
ro_regs : t_ro_regs;
enable_writes : std_logic;
end record;
-- FUNCTION DECLARATIONS
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read Only Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- cal_status
function defaults return t_cal_status;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
USE_IRAM : in std_logic;
dqs_capture : in natural;
int_ac_1t : in std_logic;
trefi_failure : in std_logic;
iram_status : in t_iram_stat;
IRAM_AWIDTH : in natural
) return t_cal_status;
function read (reg : t_cal_status) return std_logic_vector;
-- codvw status
function defaults return t_codvw_status;
function defaults ( dgrb_mmi : t_dgrb_mmi
) return t_codvw_status;
function read (reg : in t_codvw_status) return std_logic_vector;
-- test status report
function defaults return t_test_status;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
pll_mmi : in t_pll_mmi;
rw_if_test : t_if_test_reg
) return t_test_status;
function read (reg : t_test_status) return std_logic_vector;
-- define all the read only registers
function defaults return t_ro_regs;
function defaults (dgrb_mmi : t_dgrb_mmi;
ctrl_mmi : t_ctrl_mmi;
pll_mmi : t_pll_mmi;
rw_if_test : t_if_test_reg;
USE_IRAM : std_logic;
dqs_capture : natural;
int_ac_1t : std_logic;
trefi_failure : std_logic;
iram_status : t_iram_stat;
IRAM_AWIDTH : natural
) return t_ro_regs;
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read / Write Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Calibration control register
-- high level calibration stage set register comprises a bit vector for
-- the calibration stage coding and the 1 control bit.
function defaults return t_hl_css;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_hl_css;
function read (reg : in t_hl_css) return std_logic_vector;
procedure write_clear (signal reg : inout t_hl_css);
-- Mode register A
-- mode registers 0 and 1 (mr and emr1)
function defaults return t_mr_register_a;
function defaults ( mr0 : in std_logic_vector;
mr1 : in std_logic_vector
) return t_mr_register_a;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_a;
function read (reg : in t_mr_register_a) return std_logic_vector;
-- Mode register B
-- mode registers 2 and 3 (emr2 and emr3) - not present in ddr DRAM
function defaults return t_mr_register_b;
function defaults ( mr2 : in std_logic_vector;
mr3 : in std_logic_vector
) return t_mr_register_b;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_b;
function read (reg : in t_mr_register_b) return std_logic_vector;
-- algorithm parameterisation register
function defaults return t_parameterisation_reg_a;
function defaults ( NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural
) return t_parameterisation_reg_a;
function read ( reg : in t_parameterisation_reg_a) return std_logic_vector;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_parameterisation_reg_a;
-- test signal register
function defaults return t_if_test_reg;
function defaults ( TRACKING_INTERVAL_IN_MS : in natural
) return t_if_test_reg;
function read ( reg : in t_if_test_reg) return std_logic_vector;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_if_test_reg;
procedure write_clear (signal reg : inout t_if_test_reg);
-- define all the read/write registers
function defaults return t_rw_regs;
function defaults(
mr0 : in std_logic_vector;
mr1 : in std_logic_vector;
mr2 : in std_logic_vector;
mr3 : in std_logic_vector;
NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural;
TRACKING_INTERVAL_IN_MS : in natural;
C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
)return t_rw_regs;
procedure write_clear (signal regs : inout t_rw_regs);
-- >>>>>>>>>>>>>>>>>>>>>>>
-- Group all registers
-- >>>>>>>>>>>>>>>>>>>>>>>
function defaults return t_mmi_regs;
function v_read (mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector;
function read (signal mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector;
procedure write (mmi_regs : inout t_mmi_regs;
address : in natural;
wdata : in std_logic_vector(31 downto 0));
-- >>>>>>>>>>>>>>>>>>>>>>>
-- functions to communicate register settings to other sequencer blocks
-- >>>>>>>>>>>>>>>>>>>>>>>
function pack_record (ip_regs : t_rw_regs) return t_mmi_pll_reconfig;
function pack_record (ip_regs : t_rw_regs) return t_admin_ctrl;
function pack_record (ip_regs : t_rw_regs) return t_mmi_ctrl;
function pack_record ( ip_regs : t_rw_regs) return t_algm_paramaterisation;
-- >>>>>>>>>>>>>>>>>>>>>>>
-- helper functions
-- >>>>>>>>>>>>>>>>>>>>>>>
function to_t_hl_css_reg (hl_css : t_hl_css ) return t_hl_css_reg;
function pack_ack_seen ( cal_stage_ack_seen : in t_cal_stage_ack_seen
) return std_logic_vector;
-- encoding of stage and active block for register setting
function encode_current_stage (ctrl_cmd_id : t_ctrl_cmd_id) return std_logic_vector;
function encode_active_block (active_block : t_ctrl_active_block) return std_logic_vector;
--
end ddr_ctrl_ip_phy_alt_mem_phy_regs_pkg;
--
package body ddr_ctrl_ip_phy_alt_mem_phy_regs_pkg is
-- >>>>>>>>>>>>>>>>>>>>
-- Read Only Registers
-- >>>>>>>>>>>>>>>>>>>
-- ---------------------------------------------------------------
-- CODVW status report
-- ---------------------------------------------------------------
function defaults return t_codvw_status is
variable temp: t_codvw_status;
begin
temp.cal_codvw_phase := (others => '0');
temp.cal_codvw_size := (others => '0');
temp.codvw_trk_shift := (others => '0');
temp.codvw_grt_one_dvw := '0';
return temp;
end function;
function defaults ( dgrb_mmi : t_dgrb_mmi
) return t_codvw_status is
variable temp: t_codvw_status;
begin
temp := defaults;
temp.cal_codvw_phase := dgrb_mmi.cal_codvw_phase;
temp.cal_codvw_size := dgrb_mmi.cal_codvw_size;
temp.codvw_trk_shift := dgrb_mmi.codvw_trk_shift;
temp.codvw_grt_one_dvw := dgrb_mmi.codvw_grt_one_dvw;
return temp;
end function;
function read (reg : in t_codvw_status) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0);
begin
temp := (others => '0');
temp(31 downto 24) := reg.cal_codvw_phase;
temp(23 downto 16) := reg.cal_codvw_size;
temp(15 downto 4) := reg.codvw_trk_shift;
temp(0) := reg.codvw_grt_one_dvw;
return temp;
end function;
-- ---------------------------------------------------------------
-- Calibration status report
-- ---------------------------------------------------------------
function defaults return t_cal_status is
variable temp: t_cal_status;
begin
temp.iram_addr_width := (others => '0');
temp.out_of_mem := '0';
temp.contested_access := '0';
temp.cal_fail := '0';
temp.cal_success := '0';
temp.ctrl_err_code := (others => '0');
temp.trefi_failure := '0';
temp.int_ac_1t := '0';
temp.dqs_capture := '0';
temp.iram_present := '0';
temp.active_block := (others => '0');
temp.current_stage := (others => '0');
return temp;
end function;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
USE_IRAM : in std_logic;
dqs_capture : in natural;
int_ac_1t : in std_logic;
trefi_failure : in std_logic;
iram_status : in t_iram_stat;
IRAM_AWIDTH : in natural
) return t_cal_status is
variable temp : t_cal_status;
begin
temp := defaults;
temp.iram_addr_width := std_logic_vector(to_unsigned(IRAM_AWIDTH, temp.iram_addr_width'length));
temp.out_of_mem := iram_status.out_of_mem;
temp.contested_access := iram_status.contested_access;
temp.cal_fail := ctrl_mmi.ctrl_calibration_fail;
temp.cal_success := ctrl_mmi.ctrl_calibration_success;
temp.ctrl_err_code := ctrl_mmi.ctrl_err_code;
temp.trefi_failure := trefi_failure;
temp.int_ac_1t := int_ac_1t;
if dqs_capture = 1 then
temp.dqs_capture := '1';
elsif dqs_capture = 0 then
temp.dqs_capture := '0';
else
report regs_report_prefix & " invalid value for dqs_capture constant of " & integer'image(dqs_capture) severity failure;
end if;
temp.iram_present := USE_IRAM;
temp.active_block := encode_active_block(ctrl_mmi.ctrl_current_active_block);
temp.current_stage := encode_current_stage(ctrl_mmi.ctrl_current_stage);
return temp;
end function;
-- read for mmi status register
function read ( reg : t_cal_status
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
output := (others => '0');
output( 7 downto 0) := reg.current_stage;
output(11 downto 8) := reg.active_block;
output(12) := reg.iram_present;
output(13) := reg.dqs_capture;
output(14) := reg.int_ac_1t;
output(15) := reg.trefi_failure;
output(23 downto 16) := reg.ctrl_err_code;
output(24) := reg.cal_success;
output(25) := reg.cal_fail;
output(26) := reg.contested_access;
output(27) := reg.out_of_mem;
output(31 downto 28) := reg.iram_addr_width;
return output;
end function;
-- ---------------------------------------------------------------
-- Test status report
-- ---------------------------------------------------------------
function defaults return t_test_status is
variable temp: t_test_status;
begin
temp.ack_seen := (others => '0');
temp.pll_mmi_err := (others => '0');
temp.pll_busy := '0';
return temp;
end function;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
pll_mmi : in t_pll_mmi;
rw_if_test : t_if_test_reg
) return t_test_status is
variable temp : t_test_status;
begin
temp := defaults;
temp.ack_seen := pack_ack_seen(ctrl_mmi.ctrl_cal_stage_ack_seen);
temp.pll_mmi_err := pll_mmi.err;
temp.pll_busy := pll_mmi.pll_busy or rw_if_test.pll_phs_shft_up_wc or rw_if_test.pll_phs_shft_dn_wc;
return temp;
end function;
-- read for mmi status register
function read ( reg : t_test_status
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
output := (others => '0');
output(31 downto 32-c_hl_ccs_num_stages) := reg.ack_seen;
output( 5 downto 4) := reg.pll_mmi_err;
output(0) := reg.pll_busy;
return output;
end function;
-------------------------------------------------
-- FOR ALL RO REGS:
-------------------------------------------------
function defaults return t_ro_regs is
variable temp: t_ro_regs;
begin
temp.cal_status := defaults;
temp.codvw_status := defaults;
return temp;
end function;
function defaults (dgrb_mmi : t_dgrb_mmi;
ctrl_mmi : t_ctrl_mmi;
pll_mmi : t_pll_mmi;
rw_if_test : t_if_test_reg;
USE_IRAM : std_logic;
dqs_capture : natural;
int_ac_1t : std_logic;
trefi_failure : std_logic;
iram_status : t_iram_stat;
IRAM_AWIDTH : natural
) return t_ro_regs is
variable output : t_ro_regs;
begin
output := defaults;
output.cal_status := defaults(ctrl_mmi, USE_IRAM, dqs_capture, int_ac_1t, trefi_failure, iram_status, IRAM_AWIDTH);
output.codvw_status := defaults(dgrb_mmi);
output.test_status := defaults(ctrl_mmi, pll_mmi, rw_if_test);
return output;
end function;
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read / Write registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- ---------------------------------------------------------------
-- mode register set A
-- ---------------------------------------------------------------
function defaults return t_mr_register_a is
variable temp :t_mr_register_a;
begin
temp.mr0 := (others => '0');
temp.mr1 := (others => '0');
return temp;
end function;
-- apply default mode register settings to register
function defaults ( mr0 : in std_logic_vector;
mr1 : in std_logic_vector
) return t_mr_register_a is
variable temp :t_mr_register_a;
begin
temp := defaults;
temp.mr0 := mr0(temp.mr0'range);
temp.mr1 := mr1(temp.mr1'range);
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_a is
variable temp :t_mr_register_a;
begin
temp.mr0 := wdata_in(c_max_mode_reg_index -1 downto 0);
temp.mr1 := wdata_in(c_max_mode_reg_index -1 + 16 downto 16);
return temp;
end function;
function read (reg : in t_mr_register_a) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0) := (others => '0');
begin
temp(c_max_mode_reg_index -1 downto 0) := reg.mr0;
temp(c_max_mode_reg_index -1 + 16 downto 16) := reg.mr1;
return temp;
end function;
-- ---------------------------------------------------------------
-- mode register set B
-- ---------------------------------------------------------------
function defaults return t_mr_register_b is
variable temp :t_mr_register_b;
begin
temp.mr2 := (others => '0');
temp.mr3 := (others => '0');
return temp;
end function;
-- apply default mode register settings to register
function defaults ( mr2 : in std_logic_vector;
mr3 : in std_logic_vector
) return t_mr_register_b is
variable temp :t_mr_register_b;
begin
temp := defaults;
temp.mr2 := mr2(temp.mr2'range);
temp.mr3 := mr3(temp.mr3'range);
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_b is
variable temp :t_mr_register_b;
begin
temp.mr2 := wdata_in(c_max_mode_reg_index -1 downto 0);
temp.mr3 := wdata_in(c_max_mode_reg_index -1 + 16 downto 16);
return temp;
end function;
function read (reg : in t_mr_register_b) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0) := (others => '0');
begin
temp(c_max_mode_reg_index -1 downto 0) := reg.mr2;
temp(c_max_mode_reg_index -1 + 16 downto 16) := reg.mr3;
return temp;
end function;
-- ---------------------------------------------------------------
-- HL CSS (high level calibration state status)
-- ---------------------------------------------------------------
function defaults return t_hl_css is
variable temp : t_hl_css;
begin
temp.hl_css := (others => '0');
temp.cal_start := '0';
return temp;
end function;
function defaults ( C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
) return t_hl_css is
variable temp: t_hl_css;
begin
temp := defaults;
temp.hl_css := temp.hl_css OR C_HL_STAGE_ENABLE;
return temp;
end function;
function read ( reg : in t_hl_css) return std_logic_vector is
variable temp : std_logic_vector (31 downto 0) := (others => '0');
begin
temp(30 downto 30-c_hl_ccs_num_stages+1) := reg.hl_css;
temp(0) := reg.cal_start;
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0) )return t_hl_css is
variable reg : t_hl_css;
begin
reg.hl_css := wdata_in(30 downto 30-c_hl_ccs_num_stages+1);
reg.cal_start := wdata_in(0);
return reg;
end function;
procedure write_clear (signal reg : inout t_hl_css) is
begin
reg.cal_start <= '0';
end procedure;
-- ---------------------------------------------------------------
-- paramaterisation of sequencer through Avalon interface
-- ---------------------------------------------------------------
function defaults return t_parameterisation_reg_a is
variable temp : t_parameterisation_reg_a;
begin
temp.nominal_poa_phase_lead := (others => '0');
temp.maximum_poa_delay := (others => '0');
temp.pll_360_sweeps := "0000";
temp.num_phases_per_tck_pll := "0011";
temp.nominal_dqs_delay := (others => '0');
temp.extend_octrt_by := "0100";
temp.delay_octrt_by := "0000";
return temp;
end function;
-- reset the paramterisation reg to given values
function defaults ( NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural
) return t_parameterisation_reg_a is
variable temp: t_parameterisation_reg_a;
begin
temp := defaults;
temp.num_phases_per_tck_pll := std_logic_vector(to_unsigned(PLL_STEPS_PER_CYCLE /8 , temp.num_phases_per_tck_pll'high + 1 ));
temp.pll_360_sweeps := std_logic_vector(to_unsigned(pll_360_sweeps , temp.pll_360_sweeps'high + 1 ));
temp.nominal_dqs_delay := std_logic_vector(to_unsigned(NOM_DQS_PHASE_SETTING , temp.nominal_dqs_delay'high + 1 ));
temp.extend_octrt_by := std_logic_vector(to_unsigned(5 , temp.extend_octrt_by'high + 1 ));
temp.delay_octrt_by := std_logic_vector(to_unsigned(6 , temp.delay_octrt_by'high + 1 ));
return temp;
end function;
function read ( reg : in t_parameterisation_reg_a) return std_logic_vector is
variable temp : std_logic_vector (31 downto 0) := (others => '0');
begin
temp( 3 downto 0) := reg.pll_360_sweeps;
temp( 7 downto 4) := reg.num_phases_per_tck_pll;
temp(10 downto 8) := reg.nominal_dqs_delay;
temp(19 downto 16) := reg.nominal_poa_phase_lead;
temp(23 downto 20) := reg.maximum_poa_delay;
temp(27 downto 24) := reg.extend_octrt_by;
temp(31 downto 28) := reg.delay_octrt_by;
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_parameterisation_reg_a is
variable reg : t_parameterisation_reg_a;
begin
reg.pll_360_sweeps := wdata_in( 3 downto 0);
reg.num_phases_per_tck_pll := wdata_in( 7 downto 4);
reg.nominal_dqs_delay := wdata_in(10 downto 8);
reg.nominal_poa_phase_lead := wdata_in(19 downto 16);
reg.maximum_poa_delay := wdata_in(23 downto 20);
reg.extend_octrt_by := wdata_in(27 downto 24);
reg.delay_octrt_by := wdata_in(31 downto 28);
return reg;
end function;
-- ---------------------------------------------------------------
-- t_if_test_reg - additional test support register
-- ---------------------------------------------------------------
function defaults return t_if_test_reg is
variable temp : t_if_test_reg;
begin
temp.pll_phs_shft_phase_sel := 0;
temp.pll_phs_shft_up_wc := '0';
temp.pll_phs_shft_dn_wc := '0';
temp.ac_1t_toggle := '0';
temp.tracking_period_ms := "10000000"; -- 127 ms interval
temp.tracking_units_are_10us := '0';
return temp;
end function;
-- reset the paramterisation reg to given values
function defaults ( TRACKING_INTERVAL_IN_MS : in natural
) return t_if_test_reg is
variable temp: t_if_test_reg;
begin
temp := defaults;
temp.tracking_period_ms := std_logic_vector(to_unsigned(TRACKING_INTERVAL_IN_MS, temp.tracking_period_ms'length));
return temp;
end function;
function read ( reg : in t_if_test_reg) return std_logic_vector is
variable temp : std_logic_vector (31 downto 0) := (others => '0');
begin
temp( 3 downto 0) := std_logic_vector(to_unsigned(reg.pll_phs_shft_phase_sel,4));
temp(4) := reg.pll_phs_shft_up_wc;
temp(5) := reg.pll_phs_shft_dn_wc;
temp(16) := reg.ac_1t_toggle;
temp(15 downto 8) := reg.tracking_period_ms;
temp(20) := reg.tracking_units_are_10us;
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_if_test_reg is
variable reg : t_if_test_reg;
begin
reg.pll_phs_shft_phase_sel := to_integer(unsigned(wdata_in( 3 downto 0)));
reg.pll_phs_shft_up_wc := wdata_in(4);
reg.pll_phs_shft_dn_wc := wdata_in(5);
reg.ac_1t_toggle := wdata_in(16);
reg.tracking_period_ms := wdata_in(15 downto 8);
reg.tracking_units_are_10us := wdata_in(20);
return reg;
end function;
procedure write_clear (signal reg : inout t_if_test_reg) is
begin
reg.ac_1t_toggle <= '0';
reg.pll_phs_shft_up_wc <= '0';
reg.pll_phs_shft_dn_wc <= '0';
end procedure;
-- ---------------------------------------------------------------
-- RW Regs, record of read/write register records (to simplify handling)
-- ---------------------------------------------------------------
function defaults return t_rw_regs is
variable temp : t_rw_regs;
begin
temp.mr_reg_a := defaults;
temp.mr_reg_b := defaults;
temp.rw_hl_css := defaults;
temp.rw_param_reg := defaults;
temp.rw_if_test := defaults;
return temp;
end function;
function defaults(
mr0 : in std_logic_vector;
mr1 : in std_logic_vector;
mr2 : in std_logic_vector;
mr3 : in std_logic_vector;
NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural;
TRACKING_INTERVAL_IN_MS : in natural;
C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
)return t_rw_regs is
variable temp : t_rw_regs;
begin
temp := defaults;
temp.mr_reg_a := defaults(mr0, mr1);
temp.mr_reg_b := defaults(mr2, mr3);
temp.rw_param_reg := defaults(NOM_DQS_PHASE_SETTING,
PLL_STEPS_PER_CYCLE,
pll_360_sweeps);
temp.rw_if_test := defaults(TRACKING_INTERVAL_IN_MS);
temp.rw_hl_css := defaults(C_HL_STAGE_ENABLE);
return temp;
end function;
procedure write_clear (signal regs : inout t_rw_regs) is
begin
write_clear(regs.rw_if_test);
write_clear(regs.rw_hl_css);
end procedure;
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
-- All mmi registers:
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
function defaults return t_mmi_regs is
variable v_mmi_regs : t_mmi_regs;
begin
v_mmi_regs.rw_regs := defaults;
v_mmi_regs.ro_regs := defaults;
v_mmi_regs.enable_writes := '0';
return v_mmi_regs;
end function;
function v_read (mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
output := (others => '0');
case address is
-- status register
when c_regofst_cal_status => output := read (mmi_regs.ro_regs.cal_status);
-- debug access register
when c_regofst_debug_access =>
if (mmi_regs.enable_writes = '1') then
output := c_mmi_access_codeword;
else
output := (others => '0');
end if;
-- test i/f to check which stages have acknowledged a command and pll checks
when c_regofst_test_status => output := read(mmi_regs.ro_regs.test_status);
-- mode registers
when c_regofst_mr_register_a => output := read(mmi_regs.rw_regs.mr_reg_a);
when c_regofst_mr_register_b => output := read(mmi_regs.rw_regs.mr_reg_b);
-- codvw r/o status register
when c_regofst_codvw_status => output := read(mmi_regs.ro_regs.codvw_status);
-- read/write registers
when c_regofst_hl_css => output := read(mmi_regs.rw_regs.rw_hl_css);
when c_regofst_if_param => output := read(mmi_regs.rw_regs.rw_param_reg);
when c_regofst_if_test => output := read(mmi_regs.rw_regs.rw_if_test);
when others => report regs_report_prefix & "MMI registers detected an attempt to read to non-existant register location" severity warning;
-- set illegal addr interrupt.
end case;
return output;
end function;
function read (signal mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
variable v_mmi_regs : t_mmi_regs;
begin
v_mmi_regs := mmi_regs;
output := v_read(v_mmi_regs, address);
return output;
end function;
procedure write (mmi_regs : inout t_mmi_regs;
address : in natural;
wdata : in std_logic_vector(31 downto 0)) is
begin
-- intercept writes to codeword. This needs to be set for iRAM access :
if address = c_regofst_debug_access then
if wdata = c_mmi_access_codeword then
mmi_regs.enable_writes := '1';
else
mmi_regs.enable_writes := '0';
end if;
else
case address is
-- read only registers
when c_regofst_cal_status |
c_regofst_codvw_status |
c_regofst_test_status =>
report regs_report_prefix & "MMI registers detected an attempt to write to read only register number" & integer'image(address) severity failure;
-- read/write registers
when c_regofst_mr_register_a => mmi_regs.rw_regs.mr_reg_a := write(wdata);
when c_regofst_mr_register_b => mmi_regs.rw_regs.mr_reg_b := write(wdata);
when c_regofst_hl_css => mmi_regs.rw_regs.rw_hl_css := write(wdata);
when c_regofst_if_param => mmi_regs.rw_regs.rw_param_reg := write(wdata);
when c_regofst_if_test => mmi_regs.rw_regs.rw_if_test := write(wdata);
when others => -- set illegal addr interrupt.
report regs_report_prefix & "MMI registers detected an attempt to write to non existant register, with expected number" & integer'image(address) severity failure;
end case;
end if;
end procedure;
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
-- the following functions enable register data to be communicated to other sequencer blocks
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
function pack_record ( ip_regs : t_rw_regs
) return t_algm_paramaterisation is
variable output : t_algm_paramaterisation;
begin
-- default assignments
output.num_phases_per_tck_pll := 16;
output.pll_360_sweeps := 1;
output.nominal_dqs_delay := 2;
output.nominal_poa_phase_lead := 1;
output.maximum_poa_delay := 5;
output.odt_enabled := false;
output.num_phases_per_tck_pll := to_integer(unsigned(ip_regs.rw_param_reg.num_phases_per_tck_pll)) * 8;
case ip_regs.rw_param_reg.nominal_dqs_delay is
when "010" => output.nominal_dqs_delay := 2;
when "001" => output.nominal_dqs_delay := 1;
when "000" => output.nominal_dqs_delay := 0;
when "011" => output.nominal_dqs_delay := 3;
when others => report regs_report_prefix &
"there is a unsupported number of DQS taps (" &
natural'image(to_integer(unsigned(ip_regs.rw_param_reg.nominal_dqs_delay))) &
") being advertised as the standard value" severity error;
end case;
case ip_regs.rw_param_reg.nominal_poa_phase_lead is
when "0001" => output.nominal_poa_phase_lead := 1;
when "0010" => output.nominal_poa_phase_lead := 2;
when "0011" => output.nominal_poa_phase_lead := 3;
when "0000" => output.nominal_poa_phase_lead := 0;
when others => report regs_report_prefix &
"there is an unsupported nominal postamble phase lead paramater set (" &
natural'image(to_integer(unsigned(ip_regs.rw_param_reg.nominal_poa_phase_lead))) &
")" severity error;
end case;
if ( (ip_regs.mr_reg_a.mr1(2) = '1')
or (ip_regs.mr_reg_a.mr1(6) = '1')
or (ip_regs.mr_reg_a.mr1(9) = '1')
) then
output.odt_enabled := true;
end if;
output.pll_360_sweeps := to_integer(unsigned(ip_regs.rw_param_reg.pll_360_sweeps));
output.maximum_poa_delay := to_integer(unsigned(ip_regs.rw_param_reg.maximum_poa_delay));
output.extend_octrt_by := to_integer(unsigned(ip_regs.rw_param_reg.extend_octrt_by));
output.delay_octrt_by := to_integer(unsigned(ip_regs.rw_param_reg.delay_octrt_by));
output.tracking_period_ms := to_integer(unsigned(ip_regs.rw_if_test.tracking_period_ms));
return output;
end function;
function pack_record (ip_regs : t_rw_regs) return t_mmi_pll_reconfig is
variable output : t_mmi_pll_reconfig;
begin
output.pll_phs_shft_phase_sel := ip_regs.rw_if_test.pll_phs_shft_phase_sel;
output.pll_phs_shft_up_wc := ip_regs.rw_if_test.pll_phs_shft_up_wc;
output.pll_phs_shft_dn_wc := ip_regs.rw_if_test.pll_phs_shft_dn_wc;
return output;
end function;
function pack_record (ip_regs : t_rw_regs) return t_admin_ctrl is
variable output : t_admin_ctrl := defaults;
begin
output.mr0 := ip_regs.mr_reg_a.mr0;
output.mr1 := ip_regs.mr_reg_a.mr1;
output.mr2 := ip_regs.mr_reg_b.mr2;
output.mr3 := ip_regs.mr_reg_b.mr3;
return output;
end function;
function pack_record (ip_regs : t_rw_regs) return t_mmi_ctrl is
variable output : t_mmi_ctrl := defaults;
begin
output.hl_css := to_t_hl_css_reg (ip_regs.rw_hl_css);
output.calibration_start := ip_regs.rw_hl_css.cal_start;
output.tracking_period_ms := to_integer(unsigned(ip_regs.rw_if_test.tracking_period_ms));
output.tracking_orvd_to_10ms := ip_regs.rw_if_test.tracking_units_are_10us;
return output;
end function;
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
-- Helper functions :
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
function to_t_hl_css_reg (hl_css : t_hl_css
) return t_hl_css_reg is
variable output : t_hl_css_reg := defaults;
begin
output.phy_initialise_dis := hl_css.hl_css(c_hl_css_reg_phy_initialise_dis_bit);
output.init_dram_dis := hl_css.hl_css(c_hl_css_reg_init_dram_dis_bit);
output.write_ihi_dis := hl_css.hl_css(c_hl_css_reg_write_ihi_dis_bit);
output.cal_dis := hl_css.hl_css(c_hl_css_reg_cal_dis_bit);
output.write_btp_dis := hl_css.hl_css(c_hl_css_reg_write_btp_dis_bit);
output.write_mtp_dis := hl_css.hl_css(c_hl_css_reg_write_mtp_dis_bit);
output.read_mtp_dis := hl_css.hl_css(c_hl_css_reg_read_mtp_dis_bit);
output.rrp_reset_dis := hl_css.hl_css(c_hl_css_reg_rrp_reset_dis_bit);
output.rrp_sweep_dis := hl_css.hl_css(c_hl_css_reg_rrp_sweep_dis_bit);
output.rrp_seek_dis := hl_css.hl_css(c_hl_css_reg_rrp_seek_dis_bit);
output.rdv_dis := hl_css.hl_css(c_hl_css_reg_rdv_dis_bit);
output.poa_dis := hl_css.hl_css(c_hl_css_reg_poa_dis_bit);
output.was_dis := hl_css.hl_css(c_hl_css_reg_was_dis_bit);
output.adv_rd_lat_dis := hl_css.hl_css(c_hl_css_reg_adv_rd_lat_dis_bit);
output.adv_wr_lat_dis := hl_css.hl_css(c_hl_css_reg_adv_wr_lat_dis_bit);
output.prep_customer_mr_setup_dis := hl_css.hl_css(c_hl_css_reg_prep_customer_mr_setup_dis_bit);
output.tracking_dis := hl_css.hl_css(c_hl_css_reg_tracking_dis_bit);
return output;
end function;
-- pack the ack seen record element into a std_logic_vector
function pack_ack_seen ( cal_stage_ack_seen : in t_cal_stage_ack_seen
) return std_logic_vector is
variable v_output: std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
variable v_start : natural range 0 to c_hl_ccs_num_stages-1;
begin
v_output := (others => '0');
v_output(c_hl_css_reg_cal_dis_bit ) := cal_stage_ack_seen.cal;
v_output(c_hl_css_reg_phy_initialise_dis_bit ) := cal_stage_ack_seen.phy_initialise;
v_output(c_hl_css_reg_init_dram_dis_bit ) := cal_stage_ack_seen.init_dram;
v_output(c_hl_css_reg_write_ihi_dis_bit ) := cal_stage_ack_seen.write_ihi;
v_output(c_hl_css_reg_write_btp_dis_bit ) := cal_stage_ack_seen.write_btp;
v_output(c_hl_css_reg_write_mtp_dis_bit ) := cal_stage_ack_seen.write_mtp;
v_output(c_hl_css_reg_read_mtp_dis_bit ) := cal_stage_ack_seen.read_mtp;
v_output(c_hl_css_reg_rrp_reset_dis_bit ) := cal_stage_ack_seen.rrp_reset;
v_output(c_hl_css_reg_rrp_sweep_dis_bit ) := cal_stage_ack_seen.rrp_sweep;
v_output(c_hl_css_reg_rrp_seek_dis_bit ) := cal_stage_ack_seen.rrp_seek;
v_output(c_hl_css_reg_rdv_dis_bit ) := cal_stage_ack_seen.rdv;
v_output(c_hl_css_reg_poa_dis_bit ) := cal_stage_ack_seen.poa;
v_output(c_hl_css_reg_was_dis_bit ) := cal_stage_ack_seen.was;
v_output(c_hl_css_reg_adv_rd_lat_dis_bit ) := cal_stage_ack_seen.adv_rd_lat;
v_output(c_hl_css_reg_adv_wr_lat_dis_bit ) := cal_stage_ack_seen.adv_wr_lat;
v_output(c_hl_css_reg_prep_customer_mr_setup_dis_bit) := cal_stage_ack_seen.prep_customer_mr_setup;
v_output(c_hl_css_reg_tracking_dis_bit ) := cal_stage_ack_seen.tracking_setup;
return v_output;
end function;
-- reg encoding of current stage
function encode_current_stage (ctrl_cmd_id : t_ctrl_cmd_id
) return std_logic_vector is
variable output : std_logic_vector(7 downto 0);
begin
case ctrl_cmd_id is
when cmd_idle => output := X"00";
when cmd_phy_initialise => output := X"01";
when cmd_init_dram |
cmd_prog_cal_mr => output := X"02";
when cmd_write_ihi => output := X"03";
when cmd_write_btp => output := X"04";
when cmd_write_mtp => output := X"05";
when cmd_read_mtp => output := X"06";
when cmd_rrp_reset => output := X"07";
when cmd_rrp_sweep => output := X"08";
when cmd_rrp_seek => output := X"09";
when cmd_rdv => output := X"0A";
when cmd_poa => output := X"0B";
when cmd_was => output := X"0C";
when cmd_prep_adv_rd_lat => output := X"0D";
when cmd_prep_adv_wr_lat => output := X"0E";
when cmd_prep_customer_mr_setup => output := X"0F";
when cmd_tr_due => output := X"10";
when others =>
null;
report regs_report_prefix & "unknown cal command (" & t_ctrl_cmd_id'image(ctrl_cmd_id) & ") seen in encode_current_stage function" severity failure;
end case;
return output;
end function;
-- reg encoding of current active block
function encode_active_block (active_block : t_ctrl_active_block
) return std_logic_vector is
variable output : std_logic_vector(3 downto 0);
begin
case active_block is
when idle => output := X"0";
when admin => output := X"1";
when dgwb => output := X"2";
when dgrb => output := X"3";
when proc => output := X"4";
when setup => output := X"5";
when iram => output := X"6";
when others =>
output := X"7";
report regs_report_prefix & "unknown active_block seen in encode_active_block function" severity failure;
end case;
return output;
end function;
--
end ddr_ctrl_ip_phy_alt_mem_phy_regs_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : mmi block for the non-levelling AFI PHY sequencer
-- This is an optional block with an Avalon interface and status
-- register instantiations to enhance the debug capabilities of
-- the sequencer. The format of the block is:
-- a) an Avalon interface which supports different avalon and
-- sequencer clock sources
-- b) mmi status registers (which hold information about the
-- successof the calibration)
-- c) a read interface to the iram to enable debug through the
-- avalon interface.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_record_pkg.all;
--
entity ddr_ctrl_ip_phy_alt_mem_phy_mmi is
generic (
-- physical interface width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DQS_CAPTURE : natural;
DWIDTH_RATIO : natural;
CLOCK_INDEX_WIDTH : natural;
MEM_IF_CLK_PAIR_COUNT : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
ADV_LAT_WIDTH : natural;
RESYNCHRONISE_AVALON_DBG : natural;
AV_IF_ADDR_WIDTH : natural;
MEM_IF_MEMTYPE : string;
-- setup / algorithm information
NOM_DQS_PHASE_SETTING : natural;
SCAN_CLK_DIVIDE_BY : natural;
RDP_ADDR_WIDTH : natural;
PLL_STEPS_PER_CYCLE : natural;
IOE_PHASES_PER_TCK : natural;
IOE_DELAYS_PER_PHS : natural;
MEM_IF_CLK_PS : natural;
-- initial mode register settings
PHY_DEF_MR_1ST : std_logic_vector(15 downto 0);
PHY_DEF_MR_2ND : std_logic_vector(15 downto 0);
PHY_DEF_MR_3RD : std_logic_vector(15 downto 0);
PHY_DEF_MR_4TH : std_logic_vector(15 downto 0);
PRESET_RLAT : natural; -- read latency preset value
CAPABILITIES : natural; -- sequencer capabilities flags
USE_IRAM : std_logic; -- RFU
IRAM_AWIDTH : natural;
TRACKING_INTERVAL_IN_MS : natural;
READ_LAT_WIDTH : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
--synchronous Avalon debug interface (internally re-synchronised to input clock)
dbg_seq_clk : in std_logic;
dbg_seq_rst_n : in std_logic;
dbg_seq_addr : in std_logic_vector(AV_IF_ADDR_WIDTH -1 downto 0);
dbg_seq_wr : in std_logic;
dbg_seq_rd : in std_logic;
dbg_seq_cs : in std_logic;
dbg_seq_wr_data : in std_logic_vector(31 downto 0);
seq_dbg_rd_data : out std_logic_vector(31 downto 0);
seq_dbg_waitrequest : out std_logic;
-- mmi to admin interface
regs_admin_ctrl : out t_admin_ctrl;
admin_regs_status : in t_admin_stat;
trefi_failure : in std_logic;
-- mmi to iram interface
mmi_iram : out t_iram_ctrl;
mmi_iram_enable_writes : out std_logic;
iram_status : in t_iram_stat;
-- mmi to control interface
mmi_ctrl : out t_mmi_ctrl;
ctrl_mmi : in t_ctrl_mmi;
int_ac_1t : in std_logic;
invert_ac_1t : out std_logic;
-- global parameterisation record
parameterisation_rec : out t_algm_paramaterisation;
-- mmi pll interface
pll_mmi : in t_pll_mmi;
mmi_pll : out t_mmi_pll_reconfig;
-- codvw status signals
dgrb_mmi : in t_dgrb_mmi
);
end entity;
library work;
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
-- registers for the mmi status registers and functions/procedures applied to the registers
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_regs_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_iram_addr_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_constants_pkg.all;
--
architecture struct of ddr_ctrl_ip_phy_alt_mem_phy_mmi IS
-- maximum function
function max (a, b : natural) return natural is
begin
if a > b then
return a;
else
return b;
end if;
end function;
-- -------------------------------------------
-- constant definitions
-- -------------------------------------------
constant c_pll_360_sweeps : natural := rrp_pll_phase_mult(DWIDTH_RATIO, MEM_IF_DQS_CAPTURE);
constant c_response_lat : natural := 6;
constant c_codeword : std_logic_vector(31 downto 0) := c_mmi_access_codeword;
constant c_int_iram_start_size : natural := max(IRAM_AWIDTH, 4);
-- enable for ctrl state machine states
constant c_slv_hl_stage_enable : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(CAPABILITIES, 32));
constant c_hl_stage_enable : std_logic_vector(c_hl_ccs_num_stages-1 downto 0) := c_slv_hl_stage_enable(c_hl_ccs_num_stages-1 downto 0);
-- a prefix for all report signals to identify phy and sequencer block
--
constant mmi_report_prefix : string := "ddr_ctrl_ip_phy_alt_mem_phy_seq (mmi) : ";
-- --------------------------------------------
-- internal signals
-- --------------------------------------------
-- internal clock domain register interface signals
signal int_wdata : std_logic_vector(31 downto 0);
signal int_rdata : std_logic_vector(31 downto 0);
signal int_address : std_logic_vector(AV_IF_ADDR_WIDTH-1 downto 0);
signal int_read : std_logic;
signal int_cs : std_logic;
signal int_write : std_logic;
signal waitreq_int : std_logic;
-- register storage
-- contains:
-- read only (ro_regs)
-- read/write (rw_regs)
-- enable_writes flag
signal mmi_regs : t_mmi_regs := defaults;
signal mmi_rw_regs_initialised : std_logic;
-- this counter ensures that the mmi waits for c_response_lat clocks before
-- responding to a new Avalon request
signal waitreq_count : natural range 0 to 15;
signal waitreq_count_is_zero : std_logic;
-- register error signals
signal int_ac_1t_r : std_logic;
signal trefi_failure_r : std_logic;
-- iram ready - calibration complete and USE_IRAM high
signal iram_ready : std_logic;
begin -- architecture struct
-- the following signals are reserved for future use
invert_ac_1t <= '0';
-- --------------------------------------------------------------
-- generate for synchronous avalon interface
-- --------------------------------------------------------------
simply_registered_avalon : if RESYNCHRONISE_AVALON_DBG = 0 generate
begin
process (rst_n, clk)
begin
if rst_n = '0' then
int_wdata <= (others => '0');
int_address <= (others => '0');
int_read <= '0';
int_write <= '0';
int_cs <= '0';
elsif rising_edge(clk) then
int_wdata <= dbg_seq_wr_data;
int_address <= dbg_seq_addr;
int_read <= dbg_seq_rd;
int_write <= dbg_seq_wr;
int_cs <= dbg_seq_cs;
end if;
end process;
seq_dbg_rd_data <= int_rdata;
seq_dbg_waitrequest <= waitreq_int and (dbg_seq_rd or dbg_seq_wr) and dbg_seq_cs;
end generate simply_registered_avalon;
-- --------------------------------------------------------------
-- clock domain crossing for asynchronous mmi interface
-- --------------------------------------------------------------
re_synchronise_avalon : if RESYNCHRONISE_AVALON_DBG = 1 generate
--clock domain crossing signals
signal ccd_new_cmd : std_logic;
signal ccd_new_cmd_ack : std_logic;
signal ccd_cmd_done : std_logic;
signal ccd_cmd_done_ack : std_logic;
signal ccd_rd_data : std_logic_vector(dbg_seq_wr_data'range);
signal ccd_cmd_done_ack_t : std_logic;
signal ccd_cmd_done_ack_2t : std_logic;
signal ccd_cmd_done_ack_3t : std_logic;
signal ccd_cmd_done_t : std_logic;
signal ccd_cmd_done_2t : std_logic;
signal ccd_cmd_done_3t : std_logic;
signal ccd_new_cmd_t : std_logic;
signal ccd_new_cmd_2t : std_logic;
signal ccd_new_cmd_3t : std_logic;
signal ccd_new_cmd_ack_t : std_logic;
signal ccd_new_cmd_ack_2t : std_logic;
signal ccd_new_cmd_ack_3t : std_logic;
signal cmd_pending : std_logic;
signal seq_clk_waitreq_int : std_logic;
begin
process (rst_n, clk)
begin
if rst_n = '0' then
int_wdata <= (others => '0');
int_address <= (others => '0');
int_read <= '0';
int_write <= '0';
int_cs <= '0';
ccd_new_cmd_ack <= '0';
ccd_new_cmd_t <= '0';
ccd_new_cmd_2t <= '0';
ccd_new_cmd_3t <= '0';
elsif rising_edge(clk) then
ccd_new_cmd_t <= ccd_new_cmd;
ccd_new_cmd_2t <= ccd_new_cmd_t;
ccd_new_cmd_3t <= ccd_new_cmd_2t;
if ccd_new_cmd_3t = '0' and ccd_new_cmd_2t = '1' then
int_wdata <= dbg_seq_wr_data;
int_address <= dbg_seq_addr;
int_read <= dbg_seq_rd;
int_write <= dbg_seq_wr;
int_cs <= '1';
ccd_new_cmd_ack <= '1';
elsif ccd_new_cmd_3t = '1' and ccd_new_cmd_2t = '0' then
ccd_new_cmd_ack <= '0';
end if;
if int_cs = '1' and waitreq_int= '0' then
int_cs <= '0';
int_read <= '0';
int_write <= '0';
end if;
end if;
end process;
-- process to generate new cmd
process (dbg_seq_rst_n, dbg_seq_clk)
begin
if dbg_seq_rst_n = '0' then
ccd_new_cmd <= '0';
ccd_new_cmd_ack_t <= '0';
ccd_new_cmd_ack_2t <= '0';
ccd_new_cmd_ack_3t <= '0';
cmd_pending <= '0';
elsif rising_edge(dbg_seq_clk) then
ccd_new_cmd_ack_t <= ccd_new_cmd_ack;
ccd_new_cmd_ack_2t <= ccd_new_cmd_ack_t;
ccd_new_cmd_ack_3t <= ccd_new_cmd_ack_2t;
if ccd_new_cmd = '0' and dbg_seq_cs = '1' and cmd_pending = '0' then
ccd_new_cmd <= '1';
cmd_pending <= '1';
elsif ccd_new_cmd_ack_2t = '1' and ccd_new_cmd_ack_3t = '0' then
ccd_new_cmd <= '0';
end if;
-- use falling edge of cmd_done
if cmd_pending = '1' and ccd_cmd_done_2t = '0' and ccd_cmd_done_3t = '1' then
cmd_pending <= '0';
end if;
end if;
end process;
-- process to take read data back and transfer it across the clock domains
process (rst_n, clk)
begin
if rst_n = '0' then
ccd_cmd_done <= '0';
ccd_rd_data <= (others => '0');
ccd_cmd_done_ack_3t <= '0';
ccd_cmd_done_ack_2t <= '0';
ccd_cmd_done_ack_t <= '0';
elsif rising_edge(clk) then
if ccd_cmd_done_ack_2t = '1' and ccd_cmd_done_ack_3t = '0' then
ccd_cmd_done <= '0';
elsif waitreq_int = '0' then
ccd_cmd_done <= '1';
ccd_rd_data <= int_rdata;
end if;
ccd_cmd_done_ack_3t <= ccd_cmd_done_ack_2t;
ccd_cmd_done_ack_2t <= ccd_cmd_done_ack_t;
ccd_cmd_done_ack_t <= ccd_cmd_done_ack;
end if;
end process;
process (dbg_seq_rst_n, dbg_seq_clk)
begin
if dbg_seq_rst_n = '0' then
ccd_cmd_done_ack <= '0';
ccd_cmd_done_3t <= '0';
ccd_cmd_done_2t <= '0';
ccd_cmd_done_t <= '0';
seq_dbg_rd_data <= (others => '0');
seq_clk_waitreq_int <= '1';
elsif rising_edge(dbg_seq_clk) then
seq_clk_waitreq_int <= '1';
if ccd_cmd_done_2t = '1' and ccd_cmd_done_3t = '0' then
seq_clk_waitreq_int <= '0';
ccd_cmd_done_ack <= '1';
seq_dbg_rd_data <= ccd_rd_data; -- if read
elsif ccd_cmd_done_2t = '0' and ccd_cmd_done_3t = '1' then
ccd_cmd_done_ack <= '0';
end if;
ccd_cmd_done_3t <= ccd_cmd_done_2t;
ccd_cmd_done_2t <= ccd_cmd_done_t;
ccd_cmd_done_t <= ccd_cmd_done;
end if;
end process;
seq_dbg_waitrequest <= seq_clk_waitreq_int and (dbg_seq_rd or dbg_seq_wr) and dbg_seq_cs;
end generate re_synchronise_avalon;
-- register some inputs for speed.
process (rst_n, clk)
begin
if rst_n = '0' then
int_ac_1t_r <= '0';
trefi_failure_r <= '0';
elsif rising_edge(clk) then
int_ac_1t_r <= int_ac_1t;
trefi_failure_r <= trefi_failure;
end if;
end process;
-- mmi not able to write to iram in current instance of mmi block
mmi_iram_enable_writes <= '0';
-- check if iram ready
process (rst_n, clk)
begin
if rst_n = '0' then
iram_ready <= '0';
elsif rising_edge(clk) then
if USE_IRAM = '0' then
iram_ready <= '0';
else
if ctrl_mmi.ctrl_calibration_success = '1' or ctrl_mmi.ctrl_calibration_fail = '1' then
iram_ready <= '1';
else
iram_ready <= '0';
end if;
end if;
end if;
end process;
-- --------------------------------------------------------------
-- single registered process for mmi access.
-- --------------------------------------------------------------
process (rst_n, clk)
variable v_mmi_regs : t_mmi_regs;
begin
if rst_n = '0' then
mmi_regs <= defaults;
mmi_rw_regs_initialised <= '0';
-- this register records whether the c_codeword has been written to address 0x0001
-- once it has, then other writes are accepted.
mmi_regs.enable_writes <= '0';
int_rdata <= (others => '0');
waitreq_int <= '1';
-- clear wait request counter
waitreq_count <= 0;
waitreq_count_is_zero <= '1';
-- iram interface defaults
mmi_iram <= defaults;
elsif rising_edge(clk) then
-- default assignment
waitreq_int <= '1';
write_clear(mmi_regs.rw_regs);
-- only initialise rw_regs once after hard reset
if mmi_rw_regs_initialised = '0' then
mmi_rw_regs_initialised <= '1';
--reset all read/write regs and read path ouput registers and apply default MRS Settings.
mmi_regs.rw_regs <= defaults(PHY_DEF_MR_1ST,
PHY_DEF_MR_2ND,
PHY_DEF_MR_3RD,
PHY_DEF_MR_4TH,
NOM_DQS_PHASE_SETTING,
PLL_STEPS_PER_CYCLE,
c_pll_360_sweeps, -- number of times 360 degrees is swept
TRACKING_INTERVAL_IN_MS,
c_hl_stage_enable);
end if;
-- bit packing input data structures into the ro_regs structure, for reading
mmi_regs.ro_regs <= defaults(dgrb_mmi,
ctrl_mmi,
pll_mmi,
mmi_regs.rw_regs.rw_if_test,
USE_IRAM,
MEM_IF_DQS_CAPTURE,
int_ac_1t_r,
trefi_failure_r,
iram_status,
IRAM_AWIDTH);
-- write has priority over read
if int_write = '1' and int_cs = '1' and waitreq_count_is_zero = '1' and waitreq_int = '1' then
-- mmi local register write
if to_integer(unsigned(int_address(int_address'high downto 4))) = 0 then
v_mmi_regs := mmi_regs;
write(v_mmi_regs, to_integer(unsigned(int_address(3 downto 0))), int_wdata);
if mmi_regs.enable_writes = '1' then
v_mmi_regs.rw_regs.rw_hl_css.hl_css := c_hl_stage_enable or v_mmi_regs.rw_regs.rw_hl_css.hl_css;
end if;
mmi_regs <= v_mmi_regs;
-- handshake for safe transactions
waitreq_int <= '0';
waitreq_count <= c_response_lat;
-- iram write just handshake back (no write supported)
else
waitreq_int <= '0';
waitreq_count <= c_response_lat;
end if;
elsif int_read = '1' and int_cs = '1' and waitreq_count_is_zero = '1' and waitreq_int = '1' then
-- mmi local register read
if to_integer(unsigned(int_address(int_address'high downto 4))) = 0 then
int_rdata <= read(mmi_regs, to_integer(unsigned(int_address(3 downto 0))));
waitreq_count <= c_response_lat;
waitreq_int <= '0'; -- acknowledge read command regardless.
-- iram being addressed
elsif to_integer(unsigned(int_address(int_address'high downto c_int_iram_start_size))) = 1
and iram_ready = '1'
then
mmi_iram.read <= '1';
mmi_iram.addr <= to_integer(unsigned(int_address(IRAM_AWIDTH -1 downto 0)));
if iram_status.done = '1' then
waitreq_int <= '0';
mmi_iram.read <= '0';
waitreq_count <= c_response_lat;
int_rdata <= iram_status.rdata;
end if;
else -- respond and keep the interface from hanging
int_rdata <= x"DEADBEEF";
waitreq_int <= '0';
waitreq_count <= c_response_lat;
end if;
elsif waitreq_count /= 0 then
waitreq_count <= waitreq_count -1;
-- if performing a write, set back to defaults. If not, default anyway
mmi_iram <= defaults;
end if;
if waitreq_count = 1 or waitreq_count = 0 then
waitreq_count_is_zero <= '1'; -- as it will be next clock cycle
else
waitreq_count_is_zero <= '0';
end if;
-- supply iram read data when ready
if iram_status.done = '1' then
int_rdata <= iram_status.rdata;
end if;
end if;
end process;
-- pack the registers into the output data structures
regs_admin_ctrl <= pack_record(mmi_regs.rw_regs);
parameterisation_rec <= pack_record(mmi_regs.rw_regs);
mmi_pll <= pack_record(mmi_regs.rw_regs);
mmi_ctrl <= pack_record(mmi_regs.rw_regs);
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : admin block for the non-levelling AFI PHY sequencer
-- The admin block supports the autonomy of the sequencer from
-- the memory interface controller. In this task admin handles
-- memory initialisation (incl. the setting of mode registers)
-- and memory refresh, bank activation and pre-charge commands
-- (during memory interface calibration). Once calibration is
-- complete admin is 'idle' and control of the memory device is
-- passed to the users chosen memory interface controller. The
-- supported memory types are exclusively DDR, DDR2 and DDR3.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_record_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_addr_cmd_pkg.all;
--
entity ddr_ctrl_ip_phy_alt_mem_phy_admin is
generic (
-- physical interface width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
DWIDTH_RATIO : natural;
CLOCK_INDEX_WIDTH : natural;
MEM_IF_CLK_PAIR_COUNT : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
ADV_LAT_WIDTH : natural;
MEM_IF_DQSN_EN : natural;
MEM_IF_MEMTYPE : string;
-- calibration address information
MEM_IF_CAL_BANK : natural; -- Bank to which calibration data is written
MEM_IF_CAL_BASE_ROW : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural;
NON_OP_EVAL_MD : string; -- non_operational evaluation mode (used when GENERATE_ADDITIONAL_DBG_RTL = 1)
-- timing parameters
MEM_IF_CLK_PS : natural;
TINIT_TCK : natural; -- initial delay
TINIT_RST : natural -- used for DDR3 device support
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- the 2 signals below are unused for non-levelled sequencer (maintained for equivalent interface to levelled sequencer)
mem_ac_swapped_ranks : in std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- addr/cmd interface
seq_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
seq_ac_sel : out std_logic;
-- determined from MR settings
enable_odt : out std_logic;
-- interface to the mmi block
regs_admin_ctrl_rec : in t_admin_ctrl;
admin_regs_status_rec : out t_admin_stat;
trefi_failure : out std_logic;
-- interface to the ctrl block
ctrl_admin : in t_ctrl_command;
admin_ctrl : out t_ctrl_stat;
-- interface with dgrb/dgwb blocks
ac_access_req : in std_logic;
ac_access_gnt : out std_logic;
-- calibration status signals (from ctrl block)
cal_fail : in std_logic;
cal_success : in std_logic;
-- recalibrate request issued
ctl_recalibrate_req : in std_logic
);
end entity;
library work;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_constants_pkg.all;
--
architecture struct of ddr_ctrl_ip_phy_alt_mem_phy_admin is
constant c_max_mode_reg_index : natural := 12;
-- timing below is safe for range 80-400MHz operation - taken from worst case DDR2 (JEDEC JESD79-2E) / DDR3 (JESD79-3B)
-- Note: timings account for worst case use for both full rate and half rate ALTMEMPHY interfaces
constant c_init_prech_delay : natural := 162; -- precharge delay (360ns = tRFC+10ns) (TXPR for DDR3)
constant c_trp_in_clks : natural := 8; -- set equal to trp / tck (trp = 15ns)
constant c_tmrd_in_clks : natural := 4; -- maximum 4 clock cycles (DDR3)
constant c_tmod_in_clks : natural := 8; -- ODT update from MRS command (tmod = 12ns (DDR2))
constant c_trrd_min_in_clks : natural := 4; -- minimum clk cycles between bank activate cmds (10ns)
constant c_trcd_min_in_clks : natural := 8; -- minimum bank activate to read/write cmd (15ns)
-- the 2 constants below are parameterised to MEM_IF_CLK_PS due to the large range of possible clock frequency
constant c_trfc_min_in_clks : natural := (350000/MEM_IF_CLK_PS)/(DWIDTH_RATIO/2) + 2; -- refresh-refresh timing (worst case trfc = 350 ns (DDR3))
constant c_trefi_min_in_clks : natural := (3900000/MEM_IF_CLK_PS)/(DWIDTH_RATIO/2) - 2; -- average refresh interval worst case trefi = 3.9 us (industrial grade devices)
constant c_max_num_stacked_refreshes : natural := 8; -- max no. of stacked refreshes allowed
constant c_max_wait_value : natural := 4; -- delay before moving from s_idle to s_refresh_state
-- DDR3 specific:
constant c_zq_init_duration_clks : natural := 514; -- full rate (worst case) cycle count for tZQCL init
constant c_tzqcs : natural := 66; -- number of full rate clock cycles
-- below is a record which is used to parameterise the address and command signals (addr_cmd) used in this block
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- a prefix for all report signals to identify phy and sequencer block
--
constant admin_report_prefix : string := "ddr_ctrl_ip_phy_alt_mem_phy_seq (admin) : ";
-- state type for admin_state (main state machine of admin block)
type t_admin_state is
(
s_reset, -- reset state
s_run_init_seq, -- run the initialisation sequence (up to but not including MR setting)
s_program_cal_mrs, -- program the mode registers ready for calibration (this is the user settings
-- with some overloads and extra init functionality)
s_idle, -- idle (i.e. maintaining refresh to max)
s_topup_refresh, -- make sure refreshes are maxed out before going on.
s_topup_refresh_done, -- wait for tRFC after refresh command
s_zq_cal_short, -- ZQCAL short command (issued prior to activate) - DDR3 only
s_access_act, -- activate
s_access, -- dgrb, dgwb accesses,
s_access_precharge, -- precharge all memory banks
s_prog_user_mrs, -- program user mode register settings
s_dummy_wait, -- wait before going to s_refresh state
s_refresh, -- issue a memory refresh command
s_refresh_done, -- wait for trfc after refresh command
s_non_operational -- special debug state to toggle interface if calibration fails
);
signal state : t_admin_state; -- admin block state machine
-- state type for ac_state
type t_ac_state is
( s_0 ,
s_1 ,
s_2 ,
s_3 ,
s_4 ,
s_5 ,
s_6 ,
s_7 ,
s_8 ,
s_9 ,
s_10,
s_11,
s_12,
s_13,
s_14);
-- enforce one-hot fsm encoding
attribute syn_encoding : string;
attribute syn_encoding of t_ac_state : TYPE is "one-hot";
signal ac_state : t_ac_state; -- state machine for sub-states of t_admin_state states
signal stage_counter : natural range 0 to 2**18 - 1; -- counter to support memory timing delays
signal stage_counter_zero : std_logic;
signal addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1); -- internal copy of output DRAM addr/cmd signals
signal mem_init_complete : std_logic; -- signifies memory initialisation is complete
signal cal_complete : std_logic; -- calibration complete (equals: cal_success OR cal_fail)
signal int_mr0 : std_logic_vector(regs_admin_ctrl_rec.mr0'range); -- an internal copy of mode register settings
signal int_mr1 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
signal int_mr2 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
signal int_mr3 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
signal refresh_count : natural range c_trefi_min_in_clks downto 0; -- determine when refresh is due
signal refresh_due : std_logic; -- need to do a refresh now
signal refresh_done : std_logic; -- pulse when refresh complete
signal num_stacked_refreshes : natural range 0 to c_max_num_stacked_refreshes - 1; -- can stack upto 8 refreshes (for DDR2)
signal refreshes_maxed : std_logic; -- signal refreshes are maxed out
signal initial_refresh_issued : std_logic; -- to start the refresh counter off
signal ctrl_rec : t_ctrl_command;
-- last state logic
signal command_started : std_logic; -- provides a pulse when admin starts processing a command
signal command_done : std_logic; -- provides a pulse when admin completes processing a command is completed
signal finished_state : std_logic; -- finished current t_admin_state state
signal admin_req_extended : std_logic; -- keep requests for this block asserted until it is an ack is asserted
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS - 1; -- which chip select being programmed at this instance
signal per_cs_init_seen : std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
-- some signals to enable non_operational debug (optimised away if GENERATE_ADDITIONAL_DBG_RTL = 0)
signal nop_toggle_signal : t_addr_cmd_signals;
signal nop_toggle_pin : natural range 0 to MEM_IF_ADDR_WIDTH - 1; -- track which pin in a signal to toggle
signal nop_toggle_value : std_logic;
begin -- architecture struct
-- concurrent assignment of internal addr_cmd to output port seq_ac
process (addr_cmd)
begin
seq_ac <= addr_cmd;
end process;
-- generate calibration complete signal
process (cal_success, cal_fail)
begin
cal_complete <= cal_success or cal_fail;
end process;
-- register the control command record
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_rec <= defaults;
elsif rising_edge(clk) then
ctrl_rec <= ctrl_admin;
end if;
end process;
-- extend the admin block request until ack is asserted
process (clk, rst_n)
begin
if rst_n = '0' then
admin_req_extended <= '0';
elsif rising_edge(clk) then
if ( (ctrl_rec.command_req = '1') and ( curr_active_block(ctrl_rec.command) = admin) ) then
admin_req_extended <= '1';
elsif command_started = '1' then -- this is effectively a copy of command_ack generation
admin_req_extended <= '0';
end if;
end if;
end process;
-- generate the current_cs signal to track which cs accessed by PHY at any instance
process (clk, rst_n)
begin
if rst_n = '0' then
current_cs <= 0;
elsif rising_edge(clk) then
if ctrl_rec.command_req = '1' then
current_cs <= ctrl_rec.command_op.current_cs;
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- refresh logic: DDR/DDR2/DDR3 allows upto 8 refreshes to be "stacked" or queued up.
-- In the idle state, will ensure refreshes are issued when necessary. Then,
-- when an access_request is received, 7 topup refreshes will be done to max out
-- the number of queued refreshes. That way, we know we have the maximum time
-- available before another refresh is due.
-- -----------------------------------------------------------------------------
-- initial_refresh_issued flag: used to sync refresh_count
process (clk, rst_n)
begin
if rst_n = '0' then
initial_refresh_issued <= '0';
elsif rising_edge(clk) then
if cal_complete = '1' then
initial_refresh_issued <= '0';
else
if state = s_refresh_done or
state = s_topup_refresh_done then
initial_refresh_issued <= '1';
end if;
end if;
end if;
end process;
-- refresh timer: used to work out when a refresh is due
process (clk, rst_n)
begin
if rst_n = '0' then
refresh_count <= c_trefi_min_in_clks;
elsif rising_edge(clk) then
if cal_complete = '1' then
refresh_count <= c_trefi_min_in_clks;
else
if refresh_count = 0 or
initial_refresh_issued = '0' or
(refreshes_maxed = '1' and refresh_done = '1') then -- if refresh issued when already maxed
refresh_count <= c_trefi_min_in_clks;
else
refresh_count <= refresh_count - 1;
end if;
end if;
end if;
end process;
-- refresh_due generation: 1 cycle pulse to indicate that c_trefi_min_in_clks has elapsed, and
-- therefore a refresh is due
process (clk, rst_n)
begin
if rst_n = '0' then
refresh_due <= '0';
elsif rising_edge(clk) then
if refresh_count = 0 and cal_complete = '0' then
refresh_due <= '1';
else
refresh_due <= '0';
end if;
end if;
end process;
-- counter to keep track of number of refreshes "stacked". NB: Up to 8
-- refreshes can be stacked.
process (clk, rst_n)
begin
if rst_n = '0' then
num_stacked_refreshes <= 0;
trefi_failure <= '0'; -- default no trefi failure
elsif rising_edge (clk) then
if state = s_reset then
trefi_failure <= '0'; -- default no trefi failure (in restart)
end if;
if cal_complete = '1' then
num_stacked_refreshes <= 0;
else
if refresh_due = '1' and num_stacked_refreshes /= 0 then
num_stacked_refreshes <= num_stacked_refreshes - 1;
elsif refresh_done = '1' and num_stacked_refreshes /= c_max_num_stacked_refreshes - 1 then
num_stacked_refreshes <= num_stacked_refreshes + 1;
end if;
-- debug message if stacked refreshes are depleted and refresh is due
if refresh_due = '1' and num_stacked_refreshes = 0 and initial_refresh_issued = '1' then
report admin_report_prefix & "error refresh is due and num_stacked_refreshes is zero" severity error;
trefi_failure <= '1'; -- persist
end if;
end if;
end if;
end process;
-- generate signal to state if refreshes are maxed out
process (clk, rst_n)
begin
if rst_n = '0' then
refreshes_maxed <= '0';
elsif rising_edge (clk) then
if num_stacked_refreshes < c_max_num_stacked_refreshes - 1 then
refreshes_maxed <= '0';
else
refreshes_maxed <= '1';
end if;
end if;
end process;
-- ----------------------------------------------------
-- Mode register selection
-- -----------------------------------------------------
int_mr0(regs_admin_ctrl_rec.mr0'range) <= regs_admin_ctrl_rec.mr0;
int_mr1(regs_admin_ctrl_rec.mr1'range) <= regs_admin_ctrl_rec.mr1;
int_mr2(regs_admin_ctrl_rec.mr2'range) <= regs_admin_ctrl_rec.mr2;
int_mr3(regs_admin_ctrl_rec.mr3'range) <= regs_admin_ctrl_rec.mr3;
-- -------------------------------------------------------
-- State machine
-- -------------------------------------------------------
process(rst_n, clk)
begin
if rst_n = '0' then
state <= s_reset;
command_done <= '0';
command_started <= '0';
elsif rising_edge(clk) then
-- Last state logic
command_done <= '0';
command_started <= '0';
case state is
when s_reset |
s_non_operational =>
if ctrl_rec.command = cmd_init_dram and admin_req_extended = '1' then
state <= s_run_init_seq;
command_started <= '1';
end if;
when s_run_init_seq =>
if finished_state = '1' then
state <= s_idle;
command_done <= '1';
end if;
when s_program_cal_mrs =>
if finished_state = '1' then
if refreshes_maxed = '0' and mem_init_complete = '1' then -- only refresh if all ranks initialised
state <= s_topup_refresh;
else
state <= s_idle;
end if;
command_done <= '1';
end if;
when s_idle =>
if ac_access_req = '1' then
state <= s_topup_refresh;
elsif ctrl_rec.command = cmd_init_dram and admin_req_extended = '1' then -- start initialisation sequence
state <= s_run_init_seq;
command_started <= '1';
elsif ctrl_rec.command = cmd_prog_cal_mr and admin_req_extended = '1' then -- program mode registers (used for >1 chip select)
state <= s_program_cal_mrs;
command_started <= '1';
-- always enter s_prog_user_mrs via topup refresh
elsif ctrl_rec.command = cmd_prep_customer_mr_setup and admin_req_extended = '1' then
state <= s_topup_refresh;
elsif refreshes_maxed = '0' and mem_init_complete = '1' then -- only refresh once all ranks initialised
state <= s_dummy_wait;
end if;
when s_dummy_wait =>
if finished_state = '1' then
state <= s_refresh;
end if;
when s_topup_refresh =>
if finished_state = '1' then
state <= s_topup_refresh_done;
end if;
when s_topup_refresh_done =>
if finished_state = '1' then -- to ensure trfc is not violated
if refreshes_maxed = '0' then
state <= s_topup_refresh;
elsif ctrl_rec.command = cmd_prep_customer_mr_setup and admin_req_extended = '1' then
state <= s_prog_user_mrs;
command_started <= '1';
elsif ac_access_req = '1' then
if MEM_IF_MEMTYPE = "DDR3" then
state <= s_zq_cal_short;
else
state <= s_access_act;
end if;
else
state <= s_idle;
end if;
end if;
when s_zq_cal_short => -- DDR3 only
if finished_state = '1' then
state <= s_access_act;
end if;
when s_access_act =>
if finished_state = '1' then
state <= s_access;
end if;
when s_access =>
if ac_access_req = '0' then
state <= s_access_precharge;
end if;
when s_access_precharge =>
-- ensure precharge all timer has elapsed.
if finished_state = '1' then
state <= s_idle;
end if;
when s_prog_user_mrs =>
if finished_state = '1' then
state <= s_idle;
command_done <= '1';
end if;
when s_refresh =>
if finished_state = '1' then
state <= s_refresh_done;
end if;
when s_refresh_done =>
if finished_state = '1' then -- to ensure trfc is not violated
if refreshes_maxed = '0' then
state <= s_refresh;
else
state <= s_idle;
end if;
end if;
when others =>
state <= s_reset;
end case;
if cal_complete = '1' then
state <= s_idle;
if GENERATE_ADDITIONAL_DBG_RTL = 1 and cal_success = '0' then
state <= s_non_operational; -- if calibration failed and debug enabled then toggle pins in pre-defined pattern
end if;
end if;
-- if recalibrating then put admin in reset state to
-- avoid issuing refresh commands when not needed
if ctl_recalibrate_req = '1' then
state <= s_reset;
end if;
end if;
end process;
-- --------------------------------------------------
-- process to generate initialisation complete
-- --------------------------------------------------
process (rst_n, clk)
begin
if rst_n = '0' then
mem_init_complete <= '0';
elsif rising_edge(clk) then
if to_integer(unsigned(per_cs_init_seen)) = 2**MEM_IF_NUM_RANKS - 1 then
mem_init_complete <= '1';
else
mem_init_complete <= '0';
end if;
end if;
end process;
-- --------------------------------------------------
-- process to generate addr/cmd.
-- --------------------------------------------------
process(rst_n, clk)
variable v_mr_overload : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
-- required for non_operational state only
variable v_nop_ac_0 : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
variable v_nop_ac_1 : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
begin
if rst_n = '0' then
ac_state <= s_0;
stage_counter <= 0;
stage_counter_zero <= '1';
finished_state <= '0';
seq_ac_sel <= '1';
refresh_done <= '0';
per_cs_init_seen <= (others => '0');
addr_cmd <= int_pup_reset(c_seq_addr_cmd_config);
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
nop_toggle_signal <= addr;
nop_toggle_pin <= 0;
nop_toggle_value <= '0';
end if;
elsif rising_edge(clk) then
finished_state <= '0';
refresh_done <= '0';
-- address / command path control
-- if seq_ac_sel = 1 then sequencer has control of a/c
-- if seq_ac_sel = 0 then memory controller has control of a/c
seq_ac_sel <= '1';
if cal_complete = '1' then
if cal_success = '1' or
GENERATE_ADDITIONAL_DBG_RTL = 0 then -- hand over interface if cal successful or no debug enabled
seq_ac_sel <= '0';
end if;
end if;
-- if recalibration request then take control of a/c path
if ctl_recalibrate_req = '1' then
seq_ac_sel <= '1';
end if;
if state = s_reset then
addr_cmd <= reset(c_seq_addr_cmd_config);
stage_counter <= 0;
elsif state /= s_run_init_seq and
state /= s_non_operational then
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
end if;
if (stage_counter = 1 or stage_counter = 0) then
stage_counter_zero <= '1';
else
stage_counter_zero <= '0';
end if;
if stage_counter_zero /= '1' and state /= s_reset then
stage_counter <= stage_counter -1;
else
stage_counter_zero <= '0';
case state is
when s_run_init_seq =>
per_cs_init_seen <= (others => '0'); -- per cs test
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
case ac_state is
-- JEDEC (JESD79-2E) stage c
when s_0 to s_9 =>
ac_state <= t_ac_state'succ(ac_state);
stage_counter <= (TINIT_TCK/10)+1;
addr_cmd <= maintain_pd_or_sr(c_seq_addr_cmd_config,
deselect(c_seq_addr_cmd_config, addr_cmd),
2**MEM_IF_NUM_RANKS -1);
-- JEDEC (JESD79-2E) stage d
when s_10 =>
ac_state <= s_11;
stage_counter <= c_init_prech_delay;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_11 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
-- finish sequence by going into s_program_cal_mrs state
when others =>
ac_state <= s_0;
end case;
elsif MEM_IF_MEMTYPE = "DDR3" then -- DDR3 specific initialisation sequence
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= TINIT_RST + 1;
addr_cmd <= reset(c_seq_addr_cmd_config);
when s_1 to s_10 =>
ac_state <= t_ac_state'succ(ac_state);
stage_counter <= (TINIT_TCK/10) + 1;
addr_cmd <= maintain_pd_or_sr(c_seq_addr_cmd_config,
deselect(c_seq_addr_cmd_config, addr_cmd),
2**MEM_IF_NUM_RANKS -1);
when s_11 =>
ac_state <= s_12;
stage_counter <= c_init_prech_delay;
addr_cmd <= deselect(c_seq_addr_cmd_config, addr_cmd);
when s_12 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
-- finish sequence by going into s_program_cal_mrs state
when others =>
ac_state <= s_0;
end case;
else
report admin_report_prefix & "unsupported memory type specified" severity error;
end if;
-- end of initialisation sequence
when s_program_cal_mrs =>
if MEM_IF_MEMTYPE = "DDR2" then -- DDR2 style mode register settings
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
-- JEDEC (JESD79-2E) stage d
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- rank
-- JEDEC (JESD79-2E) stage e
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
2, -- mode register number
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage f
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
3, -- mode register number
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage g
when s_4 =>
ac_state <= s_5;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(0) := '0'; -- override DLL enable
v_mr_overload(9 downto 7) := "000"; -- required in JESD79-2E (but not in JESD79-2B)
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage h
when s_5 =>
ac_state <= s_6;
stage_counter <= c_tmod_in_clks;
addr_cmd <= dll_reset(c_seq_addr_cmd_config, -- configuration
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage i
when s_6 =>
ac_state <= s_7;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
-- JEDEC (JESD79-2E) stage j
when s_7 =>
ac_state <= s_8;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
-- JEDEC (JESD79-2E) stage j - second refresh
when s_8 =>
ac_state <= s_9;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
-- JEDEC (JESD79-2E) stage k
when s_9 =>
ac_state <= s_10;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr0(c_max_mode_reg_index downto 3) & "010"; -- override to burst length 4
v_mr_overload(8) := '0'; -- required in JESD79-2E
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage l - wait 200 cycles
when s_10 =>
ac_state <= s_11;
stage_counter <= 200;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
-- JEDEC (JESD79-2E) stage l - OCD default
when s_11 =>
ac_state <= s_12;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(9 downto 7) := "111"; -- OCD calibration default (i.e. OCD unused)
v_mr_overload(0) := '0'; -- override for DLL enable
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage l - OCD cal exit
when s_12 =>
ac_state <= s_13;
stage_counter <= c_tmod_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(9 downto 7) := "000"; -- OCD calibration exit
v_mr_overload(0) := '0'; -- override for DLL enable
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
per_cs_init_seen(current_cs) <= '1';
-- JEDEC (JESD79-2E) stage m - cal finished
when s_13 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
null;
end case;
elsif MEM_IF_MEMTYPE = "DDR" then -- DDR style mode register setting following JEDEC (JESD79E)
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- rank(s)
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(0) := '0'; -- override DLL enable
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmod_in_clks;
addr_cmd <= dll_reset(c_seq_addr_cmd_config, -- configuration
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_4 =>
ac_state <= s_5;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
when s_5 =>
ac_state <= s_6;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
when s_6 =>
ac_state <= s_7;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
when s_7 =>
ac_state <= s_8;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr0(c_max_mode_reg_index downto 3) & "010"; -- override to burst length 4
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_8 =>
ac_state <= s_9;
stage_counter <= 200;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
per_cs_init_seen(current_cs) <= '1';
when s_9 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
null;
end case;
elsif MEM_IF_MEMTYPE = "DDR3" then
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_trp_in_clks;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
ac_state <= s_2;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
2, -- mode register number
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
3, -- mode register number
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(0) := '0'; -- Override for DLL enable
v_mr_overload(12) := '0'; -- output buffer enable.
v_mr_overload(7) := '0'; -- Disable Write levelling
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_4 =>
ac_state <= s_5;
stage_counter <= c_tmod_in_clks;
v_mr_overload := int_mr0(c_max_mode_reg_index downto 0);
v_mr_overload(1 downto 0) := "01"; -- override to on the fly burst length choice
v_mr_overload(7) := '0'; -- test mode not enabled
v_mr_overload(8) := '1'; -- DLL reset
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_5 =>
ac_state <= s_6;
stage_counter <= c_zq_init_duration_clks;
addr_cmd <= ZQCL(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- rank
per_cs_init_seen(current_cs) <= '1';
when s_6 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
else
report admin_report_prefix & "unsupported memory type specified" severity error;
end if;
-- end of s_program_cal_mrs case
when s_prog_user_mrs =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
if MEM_IF_MEMTYPE = "DDR" then -- for DDR memory skip MR2/3 because not present
ac_state <= s_4;
else -- for DDR2/DDR3 all MRs programmed
ac_state <= s_2;
end if;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
2, -- mode register number
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
3, -- mode register number
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
if to_integer(unsigned(int_mr3)) /= 0 then
report admin_report_prefix & " mode register 3 is expected to have a value of 0 but has a value of : " &
integer'image(to_integer(unsigned(int_mr3))) severity warning;
end if;
when s_4 =>
ac_state <= s_5;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
int_mr1(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
if (MEM_IF_DQSN_EN = 0) and (int_mr1(10) = '0') and (MEM_IF_MEMTYPE = "DDR2") then
report admin_report_prefix & "mode register and generic conflict:" & LF &
"* generic MEM_IF_DQSN_EN is set to 'disable' DQSN" & LF &
"* user mode register MEM_IF_MR1 bit 10 is set to 'enable' DQSN" severity warning;
end if;
when s_5 =>
ac_state <= s_6;
stage_counter <= c_tmod_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_6 =>
ac_state <= s_7;
stage_counter <= 1;
when s_7 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
-- end of s_prog_user_mr case
when s_access_precharge =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 10;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_topup_refresh | s_refresh =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
when s_1 =>
ac_state <= s_2;
stage_counter <= 1;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**MEM_IF_NUM_RANKS - 1); -- rank
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_topup_refresh_done | s_refresh_done =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_trfc_min_in_clks;
refresh_done <= '1'; -- ensure trfc not violated
when s_1 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_zq_cal_short =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
when s_1 =>
ac_state <= s_2;
stage_counter <= c_tzqcs;
addr_cmd <= ZQCS(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- all ranks
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_access_act =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_trrd_min_in_clks;
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trcd_min_in_clks;
addr_cmd <= activate(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_ROW, -- row address
2**current_cs); -- rank
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
-- counter to delay transition from s_idle to s_refresh - this is to ensure a refresh command is not sent
-- just as we enter operational state (could cause a trfc violation)
when s_dummy_wait =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_max_wait_value;
when s_1 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_reset =>
stage_counter <= 1;
-- default some s_non_operational signals
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
nop_toggle_signal <= addr;
nop_toggle_pin <= 0;
nop_toggle_value <= '0';
end if;
when s_non_operational => -- if failed then output a recognised pattern to the memory (Only executes if GENERATE_ADDITIONAL_DBG_RTL set)
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
if NON_OP_EVAL_MD = "PIN_FINDER" then -- toggle pins in turn for 200 memory clk cycles
stage_counter <= 200/(DWIDTH_RATIO/2); -- 200 mem_clk cycles
case nop_toggle_signal is
when addr =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, addr, '0');
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, addr, nop_toggle_value, nop_toggle_pin);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
if nop_toggle_pin = MEM_IF_ADDR_WIDTH-1 then
nop_toggle_signal <= ba;
nop_toggle_pin <= 0;
else
nop_toggle_pin <= nop_toggle_pin + 1;
end if;
end if;
when ba =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ba, '0');
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ba, nop_toggle_value, nop_toggle_pin);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
if nop_toggle_pin = MEM_IF_BANKADDR_WIDTH-1 then
nop_toggle_signal <= cas_n;
nop_toggle_pin <= 0;
else
nop_toggle_pin <= nop_toggle_pin + 1;
end if;
end if;
when cas_n =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, cas_n, nop_toggle_value);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
nop_toggle_signal <= ras_n;
end if;
when ras_n =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ras_n, nop_toggle_value);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
nop_toggle_signal <= we_n;
end if;
when we_n =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, we_n, nop_toggle_value);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
nop_toggle_signal <= addr;
end if;
when others =>
report admin_report_prefix & " an attempt to toggle a non addr/cmd pin detected" severity failure;
end case;
elsif NON_OP_EVAL_MD = "SI_EVALUATOR" then -- toggle all addr/cmd pins at fmax
stage_counter <= 0; -- every mem_clk cycle
stage_counter_zero <= '1';
v_nop_ac_0 := mask (c_seq_addr_cmd_config, addr_cmd, addr, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, ba, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, we_n, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, ras_n, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, cas_n, nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, addr_cmd, addr, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, ba, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, we_n, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, ras_n, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, cas_n, not nop_toggle_value);
for i in 0 to DWIDTH_RATIO/2 - 1 loop
if i mod 2 = 0 then
addr_cmd(i) <= v_nop_ac_0(i);
else
addr_cmd(i) <= v_nop_ac_1(i);
end if;
end loop;
if DWIDTH_RATIO = 2 then
nop_toggle_value <= not nop_toggle_value;
end if;
else
report admin_report_prefix & "unknown non-operational evaluation mode " & NON_OP_EVAL_MD severity failure;
end if;
when others =>
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
stage_counter <= 1;
ac_state <= s_0;
end case;
end if;
end if;
end process;
-- -------------------------------------------------------------------
-- output packing of mode register settings and enabling of ODT
-- -------------------------------------------------------------------
process (int_mr0, int_mr1, int_mr2, int_mr3, mem_init_complete)
begin
admin_regs_status_rec.mr0 <= int_mr0;
admin_regs_status_rec.mr1 <= int_mr1;
admin_regs_status_rec.mr2 <= int_mr2;
admin_regs_status_rec.mr3 <= int_mr3;
admin_regs_status_rec.init_done <= mem_init_complete;
enable_odt <= int_mr1(2) or int_mr1(6); -- if ODT enabled in MR settings (i.e. MR1 bits 2 or 6 /= 0)
end process;
-- --------------------------------------------------------------------------------
-- generation of handshake signals with ctrl, dgrb and dgwb blocks (this includes
-- command ack, command done for ctrl and access grant for dgrb/dgwb)
-- --------------------------------------------------------------------------------
process (rst_n, clk)
begin
if rst_n = '0' then
admin_ctrl <= defaults;
ac_access_gnt <= '0';
elsif rising_edge(clk) then
admin_ctrl <= defaults;
ac_access_gnt <= '0';
admin_ctrl.command_ack <= command_started;
admin_ctrl.command_done <= command_done;
if state = s_access then
ac_access_gnt <= '1';
end if;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : inferred ram for the non-levelling AFI PHY sequencer
-- The inferred ram is used in the iram block to store
-- debug information about the sequencer. It is variable in
-- size based on the IRAM_AWIDTH generic and is of size
-- 32 * (2 ** IRAM_ADDR_WIDTH) bits
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_record_pkg.all;
--
entity ddr_ctrl_ip_phy_alt_mem_phy_iram_ram IS
generic (
IRAM_AWIDTH : natural
);
port (
clk : in std_logic;
rst_n : in std_logic;
-- ram ports
addr : in unsigned(IRAM_AWIDTH-1 downto 0);
wdata : in std_logic_vector(31 downto 0);
write : in std_logic;
rdata : out std_logic_vector(31 downto 0)
);
end entity;
--
architecture struct of ddr_ctrl_ip_phy_alt_mem_phy_iram_ram is
-- infer ram
constant c_max_ram_address : natural := 2**IRAM_AWIDTH -1;
-- registered ram signals
signal addr_r : unsigned(IRAM_AWIDTH-1 downto 0);
signal wdata_r : std_logic_vector(31 downto 0);
signal write_r : std_logic;
signal rdata_r : std_logic_vector(31 downto 0);
-- ram storage array
type t_iram is array (0 to c_max_ram_address) of std_logic_vector(31 downto 0);
signal iram_ram : t_iram;
attribute altera_attribute : string;
attribute altera_attribute of iram_ram : signal is "-name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS ""OFF""";
begin -- architecture struct
-- inferred ram instance - standard ram logic
process (clk, rst_n)
begin
if rst_n = '0' then
rdata_r <= (others => '0');
elsif rising_edge(clk) then
if write_r = '1' then
iram_ram(to_integer(addr_r)) <= wdata_r;
end if;
rdata_r <= iram_ram(to_integer(addr_r));
end if;
end process;
-- register i/o for speed
process (clk, rst_n)
begin
if rst_n = '0' then
rdata <= (others => '0');
write_r <= '0';
addr_r <= (others => '0');
wdata_r <= (others => '0');
elsif rising_edge(clk) then
rdata <= rdata_r;
write_r <= write;
addr_r <= addr;
wdata_r <= wdata;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : iram block for the non-levelling AFI PHY sequencer
-- This block is an optional storage of debug information for
-- the sequencer. In the current form the iram stores header
-- information about the arrangement of the sequencer and pass/
-- fail information for per-delay/phase/pin sweeps for the
-- read resynch phase calibration stage. Support for debug of
-- additional commands can be added at a later date
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_record_pkg.all;
-- The altmemphy iram ram (alt_mem_phy_iram_ram) is an inferred ram memory to implement the debug
-- iram ram block
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_iram_ram;
--
entity ddr_ctrl_ip_phy_alt_mem_phy_iram is
generic (
-- physical interface width definitions
MEM_IF_MEMTYPE : string;
FAMILYGROUP_ID : natural;
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
IRAM_AWIDTH : natural;
REFRESH_COUNT_INIT : natural;
PRESET_RLAT : natural;
PLL_STEPS_PER_CYCLE : natural;
CAPABILITIES : natural;
IP_BUILDNUM : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- read interface from mmi block:
mmi_iram : in t_iram_ctrl;
mmi_iram_enable_writes : in std_logic;
--iram status signal (includes read data from iram)
iram_status : out t_iram_stat;
iram_push_done : out std_logic;
-- from ctrl block
ctrl_iram : in t_ctrl_command;
-- from dgrb block
dgrb_iram : in t_iram_push;
-- from admin block
admin_regs_status_rec : in t_admin_stat;
-- current write position in the iram
ctrl_idib_top : in natural range 0 to 2 ** IRAM_AWIDTH - 1;
ctrl_iram_push : in t_ctrl_iram;
-- the following signals are unused and reserved for future use
dgwb_iram : in t_iram_push
);
end entity;
library work;
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
-- registers for the mmi status registers and functions/procedures applied to the registers
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_regs_pkg.all;
--
architecture struct of ddr_ctrl_ip_phy_alt_mem_phy_iram is
-- -------------------------------------------
-- IHI fields
-- -------------------------------------------
-- memory type , Quartus Build No., Quartus release, sequencer architecture version :
signal memtype : std_logic_vector(7 downto 0);
signal ihi_self_description : std_logic_vector(31 downto 0);
signal ihi_self_description_extra : std_logic_vector(31 downto 0);
-- for iram address generation:
signal curr_iram_offset : natural range 0 to 2 ** IRAM_AWIDTH - 1;
-- set read latency for iram_rdata_valid signal control:
constant c_iram_rlat : natural := 3; -- iram read latency (increment if read pipelining added
-- for rdata valid generation:
signal read_valid_ctr : natural range 0 to c_iram_rlat;
signal iram_addr_r : unsigned(IRAM_AWIDTH downto 0);
constant c_ihi_phys_if_desc : std_logic_vector(31 downto 0) := std_logic_vector (to_unsigned(MEM_IF_NUM_RANKS,8) & to_unsigned(MEM_IF_DM_WIDTH,8) & to_unsigned(MEM_IF_DQS_WIDTH,8) & to_unsigned(MEM_IF_DWIDTH,8));
constant c_ihi_timing_info : std_logic_vector(31 downto 0) := X"DEADDEAD";
constant c_ihi_ctrl_ss_word2 : std_logic_vector(31 downto 0) := std_logic_vector (to_unsigned(PRESET_RLAT,16) & X"0000");
-- IDIB header codes
constant c_idib_header_code0 : std_logic_vector(7 downto 0) := X"4A";
constant c_idib_footer_code : std_logic_vector(7 downto 0) := X"5A";
-- encoded Quartus version
-- constant c_quartus_version : natural := 0; -- Quartus 7.2
-- constant c_quartus_version : natural := 1; -- Quartus 8.0
--constant c_quartus_version : natural := 2; -- Quartus 8.1
--constant c_quartus_version : natural := 3; -- Quartus 9.0
--constant c_quartus_version : natural := 4; -- Quartus 9.0sp2
--constant c_quartus_version : natural := 5; -- Quartus 9.1
--constant c_quartus_version : natural := 6; -- Quartus 9.1sp1?
--constant c_quartus_version : natural := 7; -- Quartus 9.1sp2?
constant c_quartus_version : natural := 8; -- Quartus 10.0
-- constant c_quartus_version : natural := 114; -- reserved
-- allow for different variants for debug i/f
constant c_dbg_if_version : natural := 2;
-- sequencer type 1 for levelling, 2 for non-levelling
constant c_sequencer_type : natural := 2;
-- a prefix for all report signals to identify phy and sequencer block
--
constant iram_report_prefix : string := "ddr_ctrl_ip_phy_alt_mem_phy_seq (iram) : ";
-- -------------------------------------------
-- signal and type declarations
-- -------------------------------------------
type t_iram_state is ( s_reset, -- system reset
s_pre_init_ram, -- identify pre-initialisation
s_init_ram, -- zero all locations
s_idle, -- default state
s_word_access_ram, -- mmi access to the iram (post-calibration)
s_word_fetch_ram_rdata, -- sample read data from RAM
s_word_fetch_ram_rdata_r,-- register the sampling of data from RAM (to improve timing)
s_word_complete, -- finalise iram ram write
s_idib_header_write, -- when starting a command
s_idib_header_inc_addr, -- address increment
s_idib_footer_write, -- unique footer to indicate end of data
s_cal_data_read, -- read RAM location (read occurs continuously from idle state)
s_cal_data_read_r,
s_cal_data_modify, -- modify RAM location (read occurs continuously)
s_cal_data_write, -- write modified value back to RAM
s_ihi_header_word0_wr, -- from 0 to 6 writing iram header info
s_ihi_header_word1_wr,
s_ihi_header_word2_wr,
s_ihi_header_word3_wr,
s_ihi_header_word4_wr,
s_ihi_header_word5_wr,
s_ihi_header_word6_wr,
s_ihi_header_word7_wr-- end writing iram header info
);
signal state : t_iram_state;
signal contested_access : std_logic;
signal idib_header_count : std_logic_vector(7 downto 0);
-- register a new cmd request
signal new_cmd : std_logic;
signal cmd_processed : std_logic;
-- signals to control dgrb writes
signal iram_modified_data : std_logic_vector(31 downto 0); -- scratchpad memory for read-modify-write
-- -------------------------------------------
-- physical ram connections
-- -------------------------------------------
-- Note that the iram_addr here is created IRAM_AWIDTH downto 0, and not
-- IRAM_AWIDTH-1 downto 0. This means that the MSB is outside the addressable
-- area of the RAM. The purpose of this is that this shall be our memory
-- overflow bit. It shall be directly connected to the iram_out_of_memory flag
-- 32-bit interface port (read and write)
signal iram_addr : unsigned(IRAM_AWIDTH downto 0);
signal iram_wdata : std_logic_vector(31 downto 0);
signal iram_rdata : std_logic_vector(31 downto 0);
signal iram_write : std_logic;
-- signal generated external to the iram to say when read data is valid
signal iram_rdata_valid : std_logic;
-- The FSM owns local storage that is loaded with the wdata/addr from the
-- requesting sub-block, which is then fed to the iram's wdata/addr in turn
-- until all data has gone across
signal fsm_read : std_logic;
-- -------------------------------------------
-- multiplexed push data
-- -------------------------------------------
signal iram_done : std_logic; -- unused
signal iram_pushdata : std_logic_vector(31 downto 0);
signal pending_push : std_logic; -- push data to RAM
signal iram_wordnum : natural range 0 to 511;
signal iram_bitnum : natural range 0 to 31;
begin -- architecture struct
-- -------------------------------------------
-- iram ram instantiation
-- -------------------------------------------
-- Note that the IRAM_AWIDTH is the physical number of address bits that the RAM has.
-- However, for out of range access detection purposes, an additional bit is added to
-- the various address signals. The iRAM does not register any of its inputs as the addr,
-- wdata etc are registered directly before being driven to it.
-- The dgrb accesses are of format read-modify-write to a single bit of a 32-bit word, the
-- mmi reads and header writes are in 32-bit words
--
ram : entity ddr_ctrl_ip_phy_alt_mem_phy_iram_ram
generic map (
IRAM_AWIDTH => IRAM_AWIDTH
)
port map (
clk => clk,
rst_n => rst_n,
addr => iram_addr(IRAM_AWIDTH-1 downto 0),
wdata => iram_wdata,
write => iram_write,
rdata => iram_rdata
);
-- -------------------------------------------
-- IHI fields
-- asynchronously
-- -------------------------------------------
-- this field identifies the type of memory
memtype <= X"03" when (MEM_IF_MEMTYPE = "DDR3") else
X"02" when (MEM_IF_MEMTYPE = "DDR2") else
X"01" when (MEM_IF_MEMTYPE = "DDR") else
X"10" when (MEM_IF_MEMTYPE = "QDRII") else
X"00" ;
-- this field indentifies the gross level description of the sequencer
ihi_self_description <= memtype
& std_logic_vector(to_unsigned(IP_BUILDNUM,8))
& std_logic_vector(to_unsigned(c_quartus_version,8))
& std_logic_vector(to_unsigned(c_dbg_if_version,8));
-- some extra information for the debug gui - sequencer type and familygroup
ihi_self_description_extra <= std_logic_vector(to_unsigned(FAMILYGROUP_ID,4))
& std_logic_vector(to_unsigned(c_sequencer_type,4))
& x"000000";
-- -------------------------------------------
-- check for contested memory accesses
-- -------------------------------------------
process(clk,rst_n)
begin
if rst_n = '0' then
contested_access <= '0';
elsif rising_edge(clk) then
contested_access <= '0';
if mmi_iram.read = '1' and pending_push = '1' then
report iram_report_prefix & "contested memory accesses to the iram" severity failure;
contested_access <= '1';
end if;
-- sanity checks
if mmi_iram.write = '1' then
report iram_report_prefix & "mmi writes to the iram unsupported for non-levelling AFI PHY sequencer" severity failure;
end if;
if dgwb_iram.iram_write = '1' then
report iram_report_prefix & "dgwb writes to the iram unsupported for non-levelling AFI PHY sequencer" severity failure;
end if;
end if;
end process;
-- -------------------------------------------
-- mux push data and associated signals
-- note: single bit taken for iram_pushdata because 1-bit read-modify-write to
-- a 32-bit word in the ram. This interface style is maintained for future
-- scalability / wider application of the iram block.
-- -------------------------------------------
process(clk,rst_n)
begin
if rst_n = '0' then
iram_done <= '0';
iram_pushdata <= (others => '0');
pending_push <= '0';
iram_wordnum <= 0;
iram_bitnum <= 0;
elsif rising_edge(clk) then
case curr_active_block(ctrl_iram.command) is
when dgrb =>
iram_done <= dgrb_iram.iram_done;
iram_pushdata <= dgrb_iram.iram_pushdata;
pending_push <= dgrb_iram.iram_write;
iram_wordnum <= dgrb_iram.iram_wordnum;
iram_bitnum <= dgrb_iram.iram_bitnum;
when others => -- default dgrb
iram_done <= dgrb_iram.iram_done;
iram_pushdata <= dgrb_iram.iram_pushdata;
pending_push <= dgrb_iram.iram_write;
iram_wordnum <= dgrb_iram.iram_wordnum;
iram_bitnum <= dgrb_iram.iram_bitnum;
end case;
end if;
end process;
-- -------------------------------------------
-- generate write signal for the ram
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_write <= '0';
elsif rising_edge(clk) then
case state is
when s_idle =>
iram_write <= '0';
when s_pre_init_ram |
s_init_ram =>
iram_write <= '1';
when s_ihi_header_word0_wr |
s_ihi_header_word1_wr |
s_ihi_header_word2_wr |
s_ihi_header_word3_wr |
s_ihi_header_word4_wr |
s_ihi_header_word5_wr |
s_ihi_header_word6_wr |
s_ihi_header_word7_wr =>
iram_write <= '1';
when s_idib_header_write =>
iram_write <= '1';
when s_idib_footer_write =>
iram_write <= '1';
when s_cal_data_write =>
iram_write <= '1';
when others =>
iram_write <= '0'; -- default
end case;
end if;
end process;
-- -------------------------------------------
-- generate wdata for the ram
-- -------------------------------------------
process(clk, rst_n)
variable v_current_cs : std_logic_vector(3 downto 0);
variable v_mtp_alignment : std_logic_vector(0 downto 0);
variable v_single_bit : std_logic;
begin
if rst_n = '0' then
iram_wdata <= (others => '0');
elsif rising_edge(clk) then
case state is
when s_pre_init_ram |
s_init_ram =>
iram_wdata <= (others => '0');
when s_ihi_header_word0_wr =>
iram_wdata <= ihi_self_description;
when s_ihi_header_word1_wr =>
iram_wdata <= c_ihi_phys_if_desc;
when s_ihi_header_word2_wr =>
iram_wdata <= c_ihi_timing_info;
when s_ihi_header_word3_wr =>
iram_wdata <= ( others => '0');
iram_wdata(admin_regs_status_rec.mr0'range) <= admin_regs_status_rec.mr0;
iram_wdata(admin_regs_status_rec.mr1'high + 16 downto 16) <= admin_regs_status_rec.mr1;
when s_ihi_header_word4_wr =>
iram_wdata <= ( others => '0');
iram_wdata(admin_regs_status_rec.mr2'range) <= admin_regs_status_rec.mr2;
iram_wdata(admin_regs_status_rec.mr3'high + 16 downto 16) <= admin_regs_status_rec.mr3;
when s_ihi_header_word5_wr =>
iram_wdata <= c_ihi_ctrl_ss_word2;
when s_ihi_header_word6_wr =>
iram_wdata <= std_logic_vector(to_unsigned(IRAM_AWIDTH,32)); -- tbd write the occupancy at end of cal
when s_ihi_header_word7_wr =>
iram_wdata <= ihi_self_description_extra;
when s_idib_header_write =>
-- encode command_op for current operation
v_current_cs := std_logic_vector(to_unsigned(ctrl_iram.command_op.current_cs, 4));
v_mtp_alignment := std_logic_vector(to_unsigned(ctrl_iram.command_op.mtp_almt, 1));
v_single_bit := ctrl_iram.command_op.single_bit;
iram_wdata <= encode_current_stage(ctrl_iram.command) & -- which command being executed (currently this should only be cmd_rrp_sweep (8 bits)
v_current_cs & -- which chip select being processed (4 bits)
v_mtp_alignment & -- currently used MTP alignment (1 bit)
v_single_bit & -- is single bit calibration selected (1 bit) - used during MTP alignment
"00" & -- RFU
idib_header_count & -- unique ID to how many headers have been written (8 bits)
c_idib_header_code0; -- unique ID for headers (8 bits)
when s_idib_footer_write =>
iram_wdata <= c_idib_footer_code & c_idib_footer_code & c_idib_footer_code & c_idib_footer_code;
when s_cal_data_modify =>
-- default don't overwrite
iram_modified_data <= iram_rdata;
-- update iram data based on packing and write modes
if ctrl_iram_push.packing_mode = dq_bitwise then
case ctrl_iram_push.write_mode is
when overwrite_ram =>
iram_modified_data(iram_bitnum) <= iram_pushdata(0);
when or_into_ram =>
iram_modified_data(iram_bitnum) <= iram_pushdata(0) or iram_rdata(0);
when and_into_ram =>
iram_modified_data(iram_bitnum) <= iram_pushdata(0) and iram_rdata(0);
when others =>
report iram_report_prefix & "unidentified write mode of " & t_iram_write_mode'image(ctrl_iram_push.write_mode) &
" specified when generating iram write data" severity failure;
end case;
elsif ctrl_iram_push.packing_mode = dq_wordwise then
case ctrl_iram_push.write_mode is
when overwrite_ram =>
iram_modified_data <= iram_pushdata;
when or_into_ram =>
iram_modified_data <= iram_pushdata or iram_rdata;
when and_into_ram =>
iram_modified_data <= iram_pushdata and iram_rdata;
when others =>
report iram_report_prefix & "unidentified write mode of " & t_iram_write_mode'image(ctrl_iram_push.write_mode) &
" specified when generating iram write data" severity failure;
end case;
else
report iram_report_prefix & "unidentified packing mode of " & t_iram_packing_mode'image(ctrl_iram_push.packing_mode) &
" specified when generating iram write data" severity failure;
end if;
when s_cal_data_write =>
iram_wdata <= iram_modified_data;
when others =>
iram_wdata <= (others => '0');
end case;
end if;
end process;
-- -------------------------------------------
-- generate addr for the ram
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_addr <= (others => '0');
curr_iram_offset <= 0;
elsif rising_edge(clk) then
case (state) is
when s_idle =>
if mmi_iram.read = '1' then -- pre-set mmi read location address
iram_addr <= ('0' & to_unsigned(mmi_iram.addr,IRAM_AWIDTH)); -- Pad MSB
else -- default get next push data location from iram
iram_addr <= to_unsigned(curr_iram_offset + iram_wordnum, IRAM_AWIDTH+1);
end if;
when s_word_access_ram =>
-- calculate the address
if mmi_iram.read = '1' then -- mmi access
iram_addr <= ('0' & to_unsigned(mmi_iram.addr,IRAM_AWIDTH)); -- Pad MSB
end if;
when s_ihi_header_word0_wr =>
iram_addr <= (others => '0');
-- increment address for IHI word writes :
when s_ihi_header_word1_wr |
s_ihi_header_word2_wr |
s_ihi_header_word3_wr |
s_ihi_header_word4_wr |
s_ihi_header_word5_wr |
s_ihi_header_word6_wr |
s_ihi_header_word7_wr =>
iram_addr <= iram_addr + 1;
when s_idib_header_write =>
iram_addr <= '0' & to_unsigned(ctrl_idib_top, IRAM_AWIDTH); -- Always write header at idib_top location
when s_idib_footer_write =>
iram_addr <= to_unsigned(curr_iram_offset + iram_wordnum, IRAM_AWIDTH+1); -- active block communicates where to put the footer with done signal
when s_idib_header_inc_addr =>
iram_addr <= iram_addr + 1;
curr_iram_offset <= to_integer('0' & iram_addr) + 1;
when s_init_ram =>
if iram_addr(IRAM_AWIDTH) = '1' then
iram_addr <= (others => '0'); -- this prevents erroneous out-of-mem flag after initialisation
else
iram_addr <= iram_addr + 1;
end if;
when others =>
iram_addr <= iram_addr;
end case;
end if;
end process;
-- -------------------------------------------
-- generate new cmd signal to register the command_req signal
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
new_cmd <= '0';
elsif rising_edge(clk) then
if ctrl_iram.command_req = '1' then
case ctrl_iram.command is
when cmd_rrp_sweep | -- only prompt new_cmd for commands we wish to write headers for
cmd_rrp_seek |
cmd_read_mtp |
cmd_write_ihi =>
new_cmd <= '1';
when others =>
new_cmd <= '0';
end case;
end if;
if cmd_processed = '1' then
new_cmd <= '0';
end if;
end if;
end process;
-- -------------------------------------------
-- generate read valid signal which takes account of pipelining of reads
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_rdata_valid <= '0';
read_valid_ctr <= 0;
iram_addr_r <= (others => '0');
elsif rising_edge(clk) then
if read_valid_ctr < c_iram_rlat then
iram_rdata_valid <= '0';
read_valid_ctr <= read_valid_ctr + 1;
else
iram_rdata_valid <= '1';
end if;
if to_integer(iram_addr) /= to_integer(iram_addr_r) or
iram_write = '1' then
read_valid_ctr <= 0;
iram_rdata_valid <= '0';
end if;
-- register iram address
iram_addr_r <= iram_addr;
end if;
end process;
-- -------------------------------------------
-- state machine
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
state <= s_reset;
cmd_processed <= '0';
elsif rising_edge(clk) then
cmd_processed <= '0';
case state is
when s_reset =>
state <= s_pre_init_ram;
when s_pre_init_ram =>
state <= s_init_ram;
-- remain in the init_ram state until all the ram locations have been zero'ed
when s_init_ram =>
if iram_addr(IRAM_AWIDTH) = '1' then
state <= s_idle;
end if;
-- default state after reset
when s_idle =>
if pending_push = '1' then
state <= s_cal_data_read;
elsif iram_done = '1' then
state <= s_idib_footer_write;
elsif new_cmd = '1' then
case ctrl_iram.command is
when cmd_rrp_sweep |
cmd_rrp_seek |
cmd_read_mtp => state <= s_idib_header_write;
when cmd_write_ihi => state <= s_ihi_header_word0_wr;
when others => state <= state;
end case;
cmd_processed <= '1';
elsif mmi_iram.read = '1' then
state <= s_word_access_ram;
end if;
-- mmi read accesses
when s_word_access_ram => state <= s_word_fetch_ram_rdata;
when s_word_fetch_ram_rdata => state <= s_word_fetch_ram_rdata_r;
when s_word_fetch_ram_rdata_r => if iram_rdata_valid = '1' then
state <= s_word_complete;
end if;
when s_word_complete => if iram_rdata_valid = '1' then -- return to idle when iram_rdata stable
state <= s_idle;
end if;
-- header write (currently only for cmp_rrp stage)
when s_idib_header_write => state <= s_idib_header_inc_addr;
when s_idib_header_inc_addr => state <= s_idle; -- return to idle to wait for push
when s_idib_footer_write => state <= s_word_complete;
-- push data accesses (only used by the dgrb block at present)
when s_cal_data_read => state <= s_cal_data_read_r;
when s_cal_data_read_r => if iram_rdata_valid = '1' then
state <= s_cal_data_modify;
end if;
when s_cal_data_modify => state <= s_cal_data_write;
when s_cal_data_write => state <= s_word_complete;
-- IHI Header write accesses
when s_ihi_header_word0_wr => state <= s_ihi_header_word1_wr;
when s_ihi_header_word1_wr => state <= s_ihi_header_word2_wr;
when s_ihi_header_word2_wr => state <= s_ihi_header_word3_wr;
when s_ihi_header_word3_wr => state <= s_ihi_header_word4_wr;
when s_ihi_header_word4_wr => state <= s_ihi_header_word5_wr;
when s_ihi_header_word5_wr => state <= s_ihi_header_word6_wr;
when s_ihi_header_word6_wr => state <= s_ihi_header_word7_wr;
when s_ihi_header_word7_wr => state <= s_idle;
when others => state <= state;
end case;
end if;
end process;
-- -------------------------------------------
-- drive read data and responses back.
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_status <= defaults;
iram_push_done <= '0';
idib_header_count <= (others => '0');
fsm_read <= '0';
elsif rising_edge(clk) then
-- defaults
iram_status <= defaults;
iram_status.done <= '0';
iram_status.rdata <= (others => '0');
iram_push_done <= '0';
if state = s_init_ram then
iram_status.out_of_mem <= '0';
else
iram_status.out_of_mem <= iram_addr(IRAM_AWIDTH);
end if;
-- register read flag for 32 bit accesses
if state = s_idle then
fsm_read <= mmi_iram.read;
end if;
if state = s_word_complete then
iram_status.done <= '1';
if fsm_read = '1' then
iram_status.rdata <= iram_rdata;
else
iram_status.rdata <= (others => '0');
end if;
end if;
-- if another access is ever presented while the FSM is busy, set the contested flag
if contested_access = '1' then
iram_status.contested_access <= '1';
end if;
-- set (and keep set) the iram_init_done output once initialisation of the RAM is complete
if (state /= s_init_ram) and (state /= s_pre_init_ram) and (state /= s_reset) then
iram_status.init_done <= '1';
end if;
if state = s_ihi_header_word7_wr then
iram_push_done <= '1';
end if;
-- if completing push or footer write then acknowledge
if state = s_cal_data_modify or state = s_idib_footer_write then
iram_push_done <= '1';
end if;
-- increment IDIB header count each time a header is written
if state = s_idib_header_write then
idib_header_count <= std_logic_vector(unsigned(idib_header_count) + to_unsigned(1,idib_header_count'high +1));
end if;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : data gatherer (read bias) [dgrb] block for the non-levelling
-- AFI PHY sequencer
-- This block handles all calibration commands which require
-- memory read operations.
--
-- These include:
-- Resync phase calibration - sweep of phases, calculation of
-- result and optional storage to iram
-- Postamble calibration - clock cycle calibration of the postamble
-- enable signal
-- Read data valid signal alignment
-- Calculation of advertised read and write latencies
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_record_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_addr_cmd_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_iram_addr_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_constants_pkg.all;
--
entity ddr_ctrl_ip_phy_alt_mem_phy_dgrb is
generic (
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQS_CAPTURE : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
MEM_IF_MEMTYPE : string;
ADV_LAT_WIDTH : natural;
CLOCK_INDEX_WIDTH : natural;
DWIDTH_RATIO : natural;
PRESET_RLAT : natural;
PLL_STEPS_PER_CYCLE : natural; -- number of PLL phase steps per PHY clock cycle
SIM_TIME_REDUCTIONS : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural;
PRESET_CODVW_PHASE : natural;
PRESET_CODVW_SIZE : natural;
-- base column address to which calibration data is written
-- memory at MEM_IF_CAL_BASE_COL - MEM_IF_CAL_BASE_COL + C_CAL_DATA_LEN - 1
-- is assumed to contain the proper data
MEM_IF_CAL_BANK : natural; -- bank to which calibration data is written
MEM_IF_CAL_BASE_COL : natural;
EN_OCT : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- control interface
dgrb_ctrl : out t_ctrl_stat;
ctrl_dgrb : in t_ctrl_command;
parameterisation_rec : in t_algm_paramaterisation;
-- PLL reconfig interface
phs_shft_busy : in std_logic;
seq_pll_inc_dec_n : out std_logic;
seq_pll_select : out std_logic_vector(CLOCK_INDEX_WIDTH - 1 DOWNTO 0);
seq_pll_start_reconfig : out std_logic;
pll_resync_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select resync clock
pll_measure_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select mimic / aka measure clock
-- iram 'push' interface
dgrb_iram : out t_iram_push;
iram_push_done : in std_logic;
-- addr/cmd output for write commands
dgrb_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
-- admin block req/gnt interface
dgrb_ac_access_req : out std_logic;
dgrb_ac_access_gnt : in std_logic;
-- RDV latency controls
seq_rdata_valid_lat_inc : out std_logic;
seq_rdata_valid_lat_dec : out std_logic;
-- POA latency controls
seq_poa_lat_dec_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_poa_lat_inc_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
-- read datapath interface
rdata_valid : in std_logic_vector(DWIDTH_RATIO/2 - 1 downto 0);
rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
doing_rd : out std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
rd_lat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- advertised write latency
wd_lat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- OCT control
seq_oct_value : out std_logic;
dgrb_wdp_ovride : out std_logic;
-- mimic path interface
seq_mmc_start : out std_logic;
mmc_seq_done : in std_logic;
mmc_seq_value : in std_logic;
-- calibration byte lane select (reserved for future use - RFU)
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- odt settings per chip select
odt_settings : in t_odt_array(0 to MEM_IF_NUM_RANKS-1);
-- signal to identify if a/c nt setting is correct (set after wr_lat calculation)
-- NOTE: labelled nt for future scalability to quarter rate interfaces
dgrb_ctrl_ac_nt_good : out std_logic;
-- status signals on calibrated cdvw
dgrb_mmi : out t_dgrb_mmi
);
end entity;
--
architecture struct of ddr_ctrl_ip_phy_alt_mem_phy_dgrb is
-- ------------------------------------------------------------------
-- constant declarations
-- ------------------------------------------------------------------
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- command/result length
constant c_command_result_len : natural := 8;
-- burst characteristics and latency characteristics
constant c_max_read_lat : natural := 2**rd_lat'length - 1; -- maximum read latency in phy clock-cycles
-- training pattern characteristics
constant c_cal_mtp_len : natural := 16;
constant c_cal_mtp : std_logic_vector(c_cal_mtp_len - 1 downto 0) := x"30F5";
constant c_cal_mtp_t : natural := c_cal_mtp_len / DWIDTH_RATIO; -- number of phy-clk cycles required to read BTP
-- read/write latency defaults
constant c_default_rd_lat_slv : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0) := std_logic_vector(to_unsigned(c_default_rd_lat, ADV_LAT_WIDTH));
constant c_default_wd_lat_slv : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0) := std_logic_vector(to_unsigned(c_default_wr_lat, ADV_LAT_WIDTH));
-- tracking reporting parameters
constant c_max_rsc_drift_in_phases : natural := 127; -- this must be a value of < 2^10 - 1 because of the range of signal codvw_trk_shift
-- Returns '1' when boolean b is True; '0' otherwise.
function active_high(b : in boolean) return std_logic is
variable r : std_logic;
begin
if b then
r := '1';
else
r := '0';
end if;
return r;
end function;
-- a prefix for all report signals to identify phy and sequencer block
--
constant dgrb_report_prefix : string := "ddr_ctrl_ip_phy_alt_mem_phy_seq (dgrb) : ";
-- Return the number of clock periods the resync clock should sweep.
--
-- On half-rate systems and in DQS-capture based systems a 720
-- to guarantee the resync window can be properly observed.
function rsc_sweep_clk_periods return natural is
variable v_num_periods : natural;
begin
if DWIDTH_RATIO = 2 then
if MEM_IF_DQS_CAPTURE = 1 then -- families which use DQS capture require a 720 degree sweep for FR to show a window
v_num_periods := 2;
else
v_num_periods := 1;
end if;
elsif DWIDTH_RATIO = 4 then
v_num_periods := 2;
else
report dgrb_report_prefix & "unsupported DWIDTH_RATIO." severity failure;
end if;
return v_num_periods;
end function;
-- window for PLL sweep
constant c_max_phase_shifts : natural := rsc_sweep_clk_periods*PLL_STEPS_PER_CYCLE;
constant c_pll_phs_inc : std_logic := '1';
constant c_pll_phs_dec : std_logic := not c_pll_phs_inc;
-- ------------------------------------------------------------------
-- type declarations
-- ------------------------------------------------------------------
-- dgrb main state machine
type t_dgrb_state is (
-- idle state
s_idle,
-- request access to memory address/command bus from the admin block
s_wait_admin,
-- relinquish address/command bus access
s_release_admin,
-- wind back resync phase to a 'zero' point
s_reset_cdvw,
-- perform resync phase sweep (used for MTP alignment checking and actual RRP sweep)
s_test_phases,
-- processing to when checking MTP alignment
s_read_mtp,
-- processing for RRP (read resync phase) sweep
s_seek_cdvw,
-- clock cycle alignment of read data valid signal
s_rdata_valid_align,
-- calculate advertised read latency
s_adv_rd_lat_setup,
s_adv_rd_lat,
-- calculate advertised write latency
s_adv_wd_lat,
-- postamble clock cycle calibration
s_poa_cal,
-- tracking - setup and periodic update
s_track
);
-- dgrb slave state machine for addr/cmd signals
type t_ac_state is (
-- idle state
s_ac_idle,
-- wait X cycles (issuing NOP command) to flush address/command and DQ buses
s_ac_relax,
-- read MTP pattern
s_ac_read_mtp,
-- read pattern for read data valid alignment
s_ac_read_rdv,
-- read pattern for POA calibration
s_ac_read_poa_mtp,
-- read pattern to calculate advertised write latency
s_ac_read_wd_lat
);
-- dgrb slave state machine for read resync phase calibration
type t_resync_state is (
-- idle state
s_rsc_idle,
-- shift resync phase by one
s_rsc_next_phase,
-- start test sequence for current pin and current phase
s_rsc_test_phase,
-- flush the read datapath
s_rsc_wait_for_idle_dimm, -- wait until no longer driving
s_rsc_flush_datapath, -- flush a/c path
-- sample DQ data to test phase
s_rsc_test_dq,
-- reset rsc phase to a zero position
s_rsc_reset_cdvw,
s_rsc_rewind_phase,
-- calculate the centre of resync window
s_rsc_cdvw_calc,
s_rsc_cdvw_wait, -- wait for calc result
-- set rsc clock phase to centre of data valid window
s_rsc_seek_cdvw,
-- wait until all results written to iram
s_rsc_wait_iram -- only entered if GENERATE_ADDITIONAL_DBG_RTL = 1
);
-- record definitions for window processing
type t_win_processing_status is ( calculating,
valid_result,
no_invalid_phases,
multiple_equal_windows,
no_valid_phases
);
type t_window_processing is record
working_window : std_logic_vector( c_max_phase_shifts - 1 downto 0);
first_good_edge : natural range 0 to c_max_phase_shifts - 1; -- pointer to first detected good edge
current_window_start : natural range 0 to c_max_phase_shifts - 1;
current_window_size : natural range 0 to c_max_phase_shifts - 1;
current_window_centre : natural range 0 to c_max_phase_shifts - 1;
largest_window_start : natural range 0 to c_max_phase_shifts - 1;
largest_window_size : natural range 0 to c_max_phase_shifts - 1;
largest_window_centre : natural range 0 to c_max_phase_shifts - 1;
current_bit : natural range 0 to c_max_phase_shifts - 1;
window_centre_update : std_logic;
last_bit_value : std_logic;
valid_phase_seen : boolean;
invalid_phase_seen : boolean;
first_cycle : boolean;
multiple_eq_windows : boolean;
found_a_good_edge : boolean;
status : t_win_processing_status;
windows_seen : natural range 0 to c_max_phase_shifts/2 - 1;
end record;
-- ------------------------------------------------------------------
-- function and procedure definitions
-- ------------------------------------------------------------------
-- Returns a string representation of a std_logic_vector.
-- Not synthesizable.
function str(v: std_logic_vector) return string is
variable str_value : string (1 to v'length);
variable str_len : integer;
variable c : character;
begin
str_len := 1;
for i in v'range loop
case v(i) is
when '0' => c := '0';
when '1' => c := '1';
when others => c := '?';
end case;
str_value(str_len) := c;
str_len := str_len + 1;
end loop;
return str_value;
end str;
-- functions and procedures for window processing
function defaults return t_window_processing is
variable output : t_window_processing;
begin
output.working_window := (others => '1');
output.last_bit_value := '1';
output.first_good_edge := 0;
output.current_window_start := 0;
output.current_window_size := 0;
output.current_window_centre := 0;
output.largest_window_start := 0;
output.largest_window_size := 0;
output.largest_window_centre := 0;
output.window_centre_update := '1';
output.current_bit := 0;
output.multiple_eq_windows := false;
output.valid_phase_seen := false;
output.invalid_phase_seen := false;
output.found_a_good_edge := false;
output.status := no_valid_phases;
output.first_cycle := false;
output.windows_seen := 0;
return output;
end function defaults;
procedure initialise_window_for_proc ( working : inout t_window_processing ) is
variable v_working_window : std_logic_vector( c_max_phase_shifts - 1 downto 0);
begin
v_working_window := working.working_window;
working := defaults;
working.working_window := v_working_window;
working.status := calculating;
working.first_cycle := true;
working.window_centre_update := '1';
working.windows_seen := 0;
end procedure initialise_window_for_proc;
procedure shift_window (working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts
)
is
begin
if working.working_window(0) = '0' then
working.invalid_phase_seen := true;
else
working.valid_phase_seen := true;
end if;
-- general bit serial shifting of window and incrementing of current bit counter.
if working.current_bit < num_phases - 1 then
working.current_bit := working.current_bit + 1;
else
working.current_bit := 0;
end if;
working.last_bit_value := working.working_window(0);
working.working_window := working.working_window(0) & working.working_window(working.working_window'high downto 1);
--synopsis translate_off
-- for simulation to make it simpler to see IF we are not using all the bits in the window
working.working_window(working.working_window'high) := 'H'; -- for visual debug
--synopsis translate_on
working.working_window(num_phases -1) := working.last_bit_value;
working.first_cycle := false;
end procedure shift_window;
procedure find_centre_of_largest_data_valid_window
( working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts
) is
begin
if working.first_cycle = false then -- not first call to procedure, then handle end conditions
if working.current_bit = 0 and working.found_a_good_edge = false then -- have been all way arround window (circular)
if working.valid_phase_seen = false then
working.status := no_valid_phases;
elsif working.invalid_phase_seen = false then
working.status := no_invalid_phases;
end if;
elsif working.current_bit = working.first_good_edge then -- if have found a good edge then complete a circular sweep to that edge
if working.multiple_eq_windows = true then
working.status := multiple_equal_windows;
else
working.status := valid_result;
end if;
end if;
end if;
-- start of a window condition
if working.last_bit_value = '0' and working.working_window(0) = '1' then
working.current_window_start := working.current_bit;
working.current_window_size := working.current_window_size + 1; -- equivalent to assigning to one because if not in a window then it is set to 0
working.window_centre_update := not working.window_centre_update;
working.current_window_centre := working.current_bit;
if working.found_a_good_edge /= true then -- if have not yet found a good edge then store this value
working.first_good_edge := working.current_bit;
working.found_a_good_edge := true;
end if;
-- end of window conditions
elsif working.last_bit_value = '1' and working.working_window(0) = '0' then
if working.current_window_size > working.largest_window_size then
working.largest_window_size := working.current_window_size;
working.largest_window_start := working.current_window_start;
working.largest_window_centre := working.current_window_centre;
working.multiple_eq_windows := false;
elsif working.current_window_size = working.largest_window_size then
working.multiple_eq_windows := true;
end if;
-- put counter in here because start of window 1 is observed twice
if working.found_a_good_edge = true then
working.windows_seen := working.windows_seen + 1;
end if;
working.current_window_size := 0;
elsif working.last_bit_value = '1' and working.working_window(0) = '1' and (working.found_a_good_edge = true) then --note operand in brackets is excessive but for may provide power savings and makes visual inspection of simulatuion easier
if working.window_centre_update = '1' then
if working.current_window_centre < num_phases -1 then
working.current_window_centre := working.current_window_centre + 1;
else
working.current_window_centre := 0;
end if;
end if;
working.window_centre_update := not working.window_centre_update;
working.current_window_size := working.current_window_size + 1;
end if;
shift_window(working,num_phases);
end procedure find_centre_of_largest_data_valid_window;
procedure find_last_failing_phase
( working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts + 1
) is
begin
if working.first_cycle = false then -- not first call to procedure
if working.current_bit = 0 then -- and working.found_a_good_edge = false then
if working.valid_phase_seen = false then
working.status := no_valid_phases;
elsif working.invalid_phase_seen = false then
working.status := no_invalid_phases;
else
working.status := valid_result;
end if;
end if;
end if;
if working.working_window(1) = '1' and working.working_window(0) = '0' and working.status = calculating then
working.current_window_start := working.current_bit;
end if;
shift_window(working, num_phases); -- shifts window and sets first_cycle = false
end procedure find_last_failing_phase;
procedure find_first_passing_phase
( working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts
) is
begin
if working.first_cycle = false then -- not first call to procedure
if working.current_bit = 0 then -- and working.found_a_good_edge = false then
if working.valid_phase_seen = false then
working.status := no_valid_phases;
elsif working.invalid_phase_seen = false then
working.status := no_invalid_phases;
else
working.status := valid_result;
end if;
end if;
end if;
if working.working_window(0) = '1' and working.last_bit_value = '0' and working.status = calculating then
working.current_window_start := working.current_bit;
end if;
shift_window(working, num_phases); -- shifts window and sets first_cycle = false
end procedure find_first_passing_phase;
-- shift in current pass/fail result to the working window
procedure shift_in(
working : inout t_window_processing;
status : in std_logic;
num_phases : in natural range 1 to c_max_phase_shifts
) is
begin
working.last_bit_value := working.working_window(0);
working.working_window(num_phases-1 downto 0) := (working.working_window(0) and status) & working.working_window(num_phases-1 downto 1);
end procedure;
-- The following function sets the width over which
-- write latency should be repeated on the dq bus
-- the default value is MEM_IF_DQ_PER_DQS
function set_wlat_dq_rep_width return natural is
begin
for i in 1 to MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS loop
if (i*MEM_IF_DQ_PER_DQS) >= ADV_LAT_WIDTH then
return i*MEM_IF_DQ_PER_DQS;
end if;
end loop;
report dgrb_report_prefix & "the specified maximum write latency cannot be fully represented in the given number of DQ pins" & LF &
"** NOTE: This may cause overflow when setting ctl_wlat signal" severity warning;
return MEM_IF_DQ_PER_DQS;
end function;
-- extract PHY 'addr/cmd' to 'wdata_valid' write latency from current read data
function wd_lat_from_rdata(signal rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0))
return std_logic_vector is
variable v_wd_lat : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
begin
v_wd_lat := (others => '0');
if set_wlat_dq_rep_width >= ADV_LAT_WIDTH then
v_wd_lat := rdata(v_wd_lat'high downto 0);
else
v_wd_lat := (others => '0');
v_wd_lat(set_wlat_dq_rep_width - 1 downto 0) := rdata(set_wlat_dq_rep_width - 1 downto 0);
end if;
return v_wd_lat;
end function;
-- check if rdata_valid is correctly aligned
function rdata_valid_aligned(
signal rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
signal rdata_valid : in std_logic_vector(DWIDTH_RATIO/2 - 1 downto 0)
) return std_logic is
variable v_dq_rdata : std_logic_vector(DWIDTH_RATIO - 1 downto 0);
variable v_aligned : std_logic;
begin
-- Look at data from a single DQ pin 0 (DWIDTH_RATIO data bits)
for i in 0 to DWIDTH_RATIO - 1 loop
v_dq_rdata(i) := rdata(i*MEM_IF_DWIDTH);
end loop;
-- Check each alignment (necessary because in the HR case rdata can be in any alignment)
v_aligned := '0';
for i in 0 to DWIDTH_RATIO/2 - 1 loop
if rdata_valid(i) = '1' then
if v_dq_rdata(2*i + 1 downto 2*i) = "00" then
v_aligned := '1';
end if;
end if;
end loop;
return v_aligned;
end function;
-- set severity level for calibration failures
function set_cal_fail_sev_level (
generate_additional_debug_rtl : natural
) return severity_level is
begin
if generate_additional_debug_rtl = 1 then
return warning;
else
return failure;
end if;
end function;
constant cal_fail_sev_level : severity_level := set_cal_fail_sev_level(GENERATE_ADDITIONAL_DBG_RTL);
-- ------------------------------------------------------------------
-- signal declarations
-- rsc = resync - the mechanism of capturing DQ pin data onto a local clock domain
-- trk = tracking - a mechanism to track rsc clock phase with PVT variations
-- poa = postamble - protection circuitry from postamble glitched on DQS
-- ac = memory address / command signals
-- ------------------------------------------------------------------
-- main state machine
signal sig_dgrb_state : t_dgrb_state;
signal sig_dgrb_last_state : t_dgrb_state;
signal sig_rsc_req : t_resync_state; -- tells resync block which state to transition to.
-- centre of data-valid window process
signal sig_cdvw_state : t_window_processing;
-- control signals for the address/command process
signal sig_addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal sig_ac_req : t_ac_state;
signal sig_dimm_driving_dq : std_logic;
signal sig_doing_rd : std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
signal sig_ac_even : std_logic; -- odd/even count of PHY clock cycles.
--
-- sig_ac_even behaviour
--
-- sig_ac_even is always '1' on the cycle a command is issued. It will
-- be '1' on even clock cycles thereafter and '0' otherwise.
--
-- ; ; ; ; ; ;
-- ; _______ ; ; ; ; ;
-- XXXXX / \ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- addr/cmd XXXXXX CMD XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- XXXXX \_______/ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _________ _________ _________
-- sig_ac_even ____| |_________| |_________| |__________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- phy clk
-- count (0) (1) (2) (3) (4)
--
--
-- resync related signals
signal sig_rsc_ack : std_logic;
signal sig_rsc_err : std_logic;
signal sig_rsc_result : std_logic_vector(c_command_result_len - 1 downto 0 );
signal sig_rsc_cdvw_phase : std_logic;
signal sig_rsc_cdvw_shift_in : std_logic;
signal sig_rsc_cdvw_calc : std_logic;
signal sig_rsc_pll_start_reconfig : std_logic;
signal sig_rsc_pll_inc_dec_n : std_logic;
signal sig_rsc_ac_access_req : std_logic; -- High when the resync block requires a training pattern to be read.
-- tracking related signals
signal sig_trk_ack : std_logic;
signal sig_trk_err : std_logic;
signal sig_trk_result : std_logic_vector(c_command_result_len - 1 downto 0 );
signal sig_trk_cdvw_phase : std_logic;
signal sig_trk_cdvw_shift_in : std_logic;
signal sig_trk_cdvw_calc : std_logic;
signal sig_trk_pll_start_reconfig : std_logic;
signal sig_trk_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 DOWNTO 0);
signal sig_trk_pll_inc_dec_n : std_logic;
signal sig_trk_rsc_drift : integer range -c_max_rsc_drift_in_phases to c_max_rsc_drift_in_phases; -- stores total change in rsc phase from first calibration
-- phs_shft_busy could (potentially) be asynchronous
-- triple register it for metastability hardening
-- these signals are the taps on the shift register
signal sig_phs_shft_busy : std_logic;
signal sig_phs_shft_busy_1t : std_logic;
signal sig_phs_shft_start : std_logic;
signal sig_phs_shft_end : std_logic;
-- locally register crl_dgrb to minimise fan out
signal ctrl_dgrb_r : t_ctrl_command;
-- command_op signals
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS - 1;
signal current_mtp_almt : natural range 0 to 1;
signal single_bit_cal : std_logic;
-- codvw status signals (packed into record and sent to mmi block)
signal cal_codvw_phase : std_logic_vector(7 downto 0);
signal codvw_trk_shift : std_logic_vector(11 downto 0);
signal cal_codvw_size : std_logic_vector(7 downto 0);
-- error signal and result from main state machine (operations other than rsc or tracking)
signal sig_cmd_err : std_logic;
signal sig_cmd_result : std_logic_vector(c_command_result_len - 1 downto 0 );
-- signals that the training pattern matched correctly on the last clock
-- cycle.
signal sig_dq_pin_ctr : natural range 0 to MEM_IF_DWIDTH - 1;
signal sig_mtp_match : std_logic;
-- controls postamble match and timing.
signal sig_poa_match_en : std_logic;
signal sig_poa_match : std_logic;
-- postamble signals
signal sig_poa_ack : std_logic; -- '1' for postamble block to acknowledge.
-- calibration byte lane select
signal cal_byte_lanes : std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
signal codvw_grt_one_dvw : std_logic;
begin
doing_rd <= sig_doing_rd;
-- pack record of codvw status signals
dgrb_mmi.cal_codvw_phase <= cal_codvw_phase;
dgrb_mmi.codvw_trk_shift <= codvw_trk_shift;
dgrb_mmi.cal_codvw_size <= cal_codvw_size;
dgrb_mmi.codvw_grt_one_dvw <= codvw_grt_one_dvw;
-- map some internal signals to outputs
dgrb_ac <= sig_addr_cmd;
-- locally register crl_dgrb to minimise fan out
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_dgrb_r <= defaults;
elsif rising_edge(clk) then
ctrl_dgrb_r <= ctrl_dgrb;
end if;
end process;
-- generate the current_cs signal to track which cs accessed by PHY at any instance
current_cs_proc : process (clk, rst_n)
begin
if rst_n = '0' then
current_cs <= 0;
current_mtp_almt <= 0;
single_bit_cal <= '0';
cal_byte_lanes <= (others => '0');
elsif rising_edge(clk) then
if ctrl_dgrb_r.command_req = '1' then
current_cs <= ctrl_dgrb_r.command_op.current_cs;
current_mtp_almt <= ctrl_dgrb_r.command_op.mtp_almt;
single_bit_cal <= ctrl_dgrb_r.command_op.single_bit;
end if;
-- mux byte lane select for given chip select
for i in 0 to MEM_IF_DQS_WIDTH - 1 loop
cal_byte_lanes(i) <= ctl_cal_byte_lanes((current_cs * MEM_IF_DQS_WIDTH) + i);
end loop;
assert ctl_cal_byte_lanes(0) = '1' report dgrb_report_prefix & " Byte lane 0 (chip select 0) disable is not supported - ending simulation" severity failure;
end if;
end process;
-- ------------------------------------------------------------------
-- main state machine for dgrb architecture
--
-- process of commands from control (ctrl) block and overall control of
-- the subsequent calibration processing functions
-- also communicates completion and any errors back to the ctrl block
-- read data valid alignment and advertised latency calculations are
-- included in this block
-- ------------------------------------------------------------------
dgrb_main_block : block
signal sig_count : natural range 0 to 2**8 - 1;
signal sig_wd_lat : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
begin
dgrb_state_proc : process(rst_n, clk)
begin
if rst_n = '0' then
-- initialise state
sig_dgrb_state <= s_idle;
sig_dgrb_last_state <= s_idle;
sig_ac_req <= s_ac_idle;
sig_rsc_req <= s_rsc_idle;
-- set up rd_lat defaults
rd_lat <= c_default_rd_lat_slv;
wd_lat <= c_default_wd_lat_slv;
-- set up rdata_valid latency control defaults
seq_rdata_valid_lat_inc <= '0';
seq_rdata_valid_lat_dec <= '0';
-- reset counter
sig_count <= 0;
-- error signals
sig_cmd_err <= '0';
sig_cmd_result <= (others => '0');
-- sig_wd_lat
sig_wd_lat <= (others => '0');
-- status of the ac_nt alignment
dgrb_ctrl_ac_nt_good <= '1';
elsif rising_edge(clk) then
sig_dgrb_last_state <= sig_dgrb_state;
sig_rsc_req <= s_rsc_idle;
-- set up rdata_valid latency control defaults
seq_rdata_valid_lat_inc <= '0';
seq_rdata_valid_lat_dec <= '0';
-- error signals
sig_cmd_err <= '0';
sig_cmd_result <= (others => '0');
-- register wd_lat output.
wd_lat <= sig_wd_lat;
case sig_dgrb_state is
when s_idle =>
sig_count <= 0;
if ctrl_dgrb_r.command_req = '1' then
if curr_active_block(ctrl_dgrb_r.command) = dgrb then
sig_dgrb_state <= s_wait_admin;
end if;
end if;
sig_ac_req <= s_ac_idle;
when s_wait_admin =>
sig_dgrb_state <= s_wait_admin;
case ctrl_dgrb_r.command is
when cmd_read_mtp => sig_dgrb_state <= s_read_mtp;
when cmd_rrp_reset => sig_dgrb_state <= s_reset_cdvw;
when cmd_rrp_sweep => sig_dgrb_state <= s_test_phases;
when cmd_rrp_seek => sig_dgrb_state <= s_seek_cdvw;
when cmd_rdv => sig_dgrb_state <= s_rdata_valid_align;
when cmd_prep_adv_rd_lat => sig_dgrb_state <= s_adv_rd_lat_setup;
when cmd_prep_adv_wr_lat => sig_dgrb_state <= s_adv_wd_lat;
when cmd_tr_due => sig_dgrb_state <= s_track;
when cmd_poa => sig_dgrb_state <= s_poa_cal;
when others =>
report dgrb_report_prefix & "unknown command" severity failure;
sig_dgrb_state <= s_idle;
end case;
when s_reset_cdvw =>
-- the cdvw proc watches for this state and resets the cdvw
-- state block.
if sig_rsc_ack = '1' then
sig_dgrb_state <= s_release_admin;
else
sig_rsc_req <= s_rsc_reset_cdvw;
end if;
when s_test_phases =>
if sig_rsc_ack = '1' then
sig_dgrb_state <= s_release_admin;
else
sig_rsc_req <= s_rsc_test_phase;
if sig_rsc_ac_access_req = '1' then
sig_ac_req <= s_ac_read_mtp;
else
sig_ac_req <= s_ac_idle;
end if;
end if;
when s_seek_cdvw | s_read_mtp =>
if sig_rsc_ack = '1' then
sig_dgrb_state <= s_release_admin;
else
sig_rsc_req <= s_rsc_cdvw_calc;
end if;
when s_release_admin =>
sig_ac_req <= s_ac_idle;
if dgrb_ac_access_gnt = '0' and sig_dimm_driving_dq = '0' then
sig_dgrb_state <= s_idle;
end if;
when s_rdata_valid_align =>
sig_ac_req <= s_ac_read_rdv;
seq_rdata_valid_lat_dec <= '0';
seq_rdata_valid_lat_inc <= '0';
if sig_dimm_driving_dq = '1' then
-- only do comparison if rdata_valid is all 'ones'
if rdata_valid /= std_logic_vector(to_unsigned(0, DWIDTH_RATIO/2)) then
-- rdata_valid is all ones
if rdata_valid_aligned(rdata, rdata_valid) = '1' then
-- success: rdata_valid and rdata are properly aligned
sig_dgrb_state <= s_release_admin;
else
-- misaligned: bring in rdata_valid by a clock cycle
seq_rdata_valid_lat_dec <= '1';
end if;
end if;
end if;
when s_adv_rd_lat_setup =>
-- wait for sig_doing_rd to go high
sig_ac_req <= s_ac_read_rdv;
if sig_dgrb_state /= sig_dgrb_last_state then
rd_lat <= (others => '0');
sig_count <= 0;
elsif sig_dimm_driving_dq = '1' and sig_doing_rd(MEM_IF_DQS_WIDTH*(DWIDTH_RATIO/2-1)) = '1' then
-- a read has started: start counter
sig_dgrb_state <= s_adv_rd_lat;
end if;
when s_adv_rd_lat =>
sig_ac_req <= s_ac_read_rdv;
if sig_dimm_driving_dq = '1' then
if sig_count >= 2**rd_lat'length then
report dgrb_report_prefix & "maximum read latency exceeded while waiting for rdata_valid" severity cal_fail_sev_level;
sig_cmd_err <= '1';
sig_cmd_result <= std_logic_vector(to_unsigned(C_ERR_MAX_RD_LAT_EXCEEDED,sig_cmd_result'length));
end if;
if rdata_valid /= std_logic_vector(to_unsigned(0, rdata_valid'length)) then
-- have found the read latency
sig_dgrb_state <= s_release_admin;
else
sig_count <= sig_count + 1;
end if;
rd_lat <= std_logic_vector(to_unsigned(sig_count, rd_lat'length));
end if;
when s_adv_wd_lat =>
sig_ac_req <= s_ac_read_wd_lat;
if sig_dgrb_state /= sig_dgrb_last_state then
sig_wd_lat <= (others => '0');
else
if sig_dimm_driving_dq = '1' and rdata_valid /= std_logic_vector(to_unsigned(0, rdata_valid'length)) then
-- construct wd_lat using data from the lowest addresses
-- wd_lat <= rdata(MEM_IF_DQ_PER_DQS - 1 downto 0);
sig_wd_lat <= wd_lat_from_rdata(rdata);
sig_dgrb_state <= s_release_admin;
-- check data integrity
for i in 1 to MEM_IF_DWIDTH/set_wlat_dq_rep_width - 1 loop
-- wd_lat is copied across MEM_IF_DWIDTH bits in fields of width MEM_IF_DQ_PER_DQS.
-- All of these fields must have the same value or it is an error.
-- only check if byte lane not disabled
if cal_byte_lanes((i*set_wlat_dq_rep_width)/MEM_IF_DQ_PER_DQS) = '1' then
if rdata(set_wlat_dq_rep_width - 1 downto 0) /= rdata((i+1)*set_wlat_dq_rep_width - 1 downto i*set_wlat_dq_rep_width) then
-- signal write latency different between DQS groups
report dgrb_report_prefix & "the write latency read from memory is different accross dqs groups" severity cal_fail_sev_level;
sig_cmd_err <= '1';
sig_cmd_result <= std_logic_vector(to_unsigned(C_ERR_WD_LAT_DISAGREEMENT, sig_cmd_result'length));
end if;
end if;
end loop;
-- check if ac_nt alignment is ok
-- in this condition all DWIDTH_RATIO copies of rdata should be identical
dgrb_ctrl_ac_nt_good <= '1';
if DWIDTH_RATIO /= 2 then
for j in 0 to DWIDTH_RATIO/2 - 1 loop
if rdata(j*MEM_IF_DWIDTH + MEM_IF_DQ_PER_DQS - 1 downto j*MEM_IF_DWIDTH) /= rdata((j+2)*MEM_IF_DWIDTH + MEM_IF_DQ_PER_DQS - 1 downto (j+2)*MEM_IF_DWIDTH) then
dgrb_ctrl_ac_nt_good <= '0';
end if;
end loop;
end if;
end if;
end if;
when s_poa_cal =>
-- Request the address/command block begins reading the "M"
-- training pattern here. There is no provision for doing
-- refreshes so this limits the time spent in this state
-- to 9 x tREFI (by the DDR2 JEDEC spec). Instead of the
-- maximum value, a maximum "safe" time in this postamble
-- state is chosen to be tpoamax = 5 x tREFI = 5 x 3.9us.
-- When entering this s_poa_cal state it must be guaranteed
-- that the number of stacked refreshes is at maximum.
--
-- Minimum clock freq supported by DRAM is fck,min=125MHz.
-- Each adjustment to postamble latency requires 16*clock
-- cycles (time to read "M" training pattern twice) so
-- maximum number of adjustments to POA latency (n) is:
--
-- n = (5 x trefi x fck,min) / 16
-- = (5 x 3.9us x 125MHz) / 16
-- ~ 152
--
-- Postamble latency must be adjusted less than 152 cycles
-- to meet this requirement.
--
sig_ac_req <= s_ac_read_poa_mtp;
if sig_poa_ack = '1' then
sig_dgrb_state <= s_release_admin;
end if;
when s_track =>
if sig_trk_ack = '1' then
sig_dgrb_state <= s_release_admin;
end if;
when others => null;
report dgrb_report_prefix & "undefined state" severity failure;
sig_dgrb_state <= s_idle;
end case;
-- default if not calibrating go to idle state via s_release_admin
if ctrl_dgrb_r.command = cmd_idle and
sig_dgrb_state /= s_idle and
sig_dgrb_state /= s_release_admin then
sig_dgrb_state <= s_release_admin;
end if;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- metastability hardening of potentially async phs_shift_busy signal
--
-- Triple register it for metastability hardening. This process
-- creates the shift register. Also add a sig_phs_shft_busy and
-- an sig_phs_shft_busy_1t echo because various other processes find
-- this useful.
-- ------------------------------------------------------------------
phs_shft_busy_reg: block
signal phs_shft_busy_1r : std_logic;
signal phs_shft_busy_2r : std_logic;
signal phs_shft_busy_3r : std_logic;
begin
phs_shift_busy_sync : process (clk, rst_n)
begin
if rst_n = '0' then
sig_phs_shft_busy <= '0';
sig_phs_shft_busy_1t <= '0';
phs_shft_busy_1r <= '0';
phs_shft_busy_2r <= '0';
phs_shft_busy_3r <= '0';
sig_phs_shft_start <= '0';
sig_phs_shft_end <= '0';
elsif rising_edge(clk) then
sig_phs_shft_busy_1t <= phs_shft_busy_3r;
sig_phs_shft_busy <= phs_shft_busy_2r;
-- register the below to reduce fan out on sig_phs_shft_busy and sig_phs_shft_busy_1t
sig_phs_shft_start <= phs_shft_busy_3r or phs_shft_busy_2r;
sig_phs_shft_end <= phs_shft_busy_3r and not(phs_shft_busy_2r);
phs_shft_busy_3r <= phs_shft_busy_2r;
phs_shft_busy_2r <= phs_shft_busy_1r;
phs_shft_busy_1r <= phs_shft_busy;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- PLL reconfig MUX
--
-- switches PLL Reconfig input between tracking and resync blocks
-- ------------------------------------------------------------------
pll_reconf_mux : process (clk, rst_n)
begin
if rst_n = '0' then
seq_pll_inc_dec_n <= '0';
seq_pll_select <= (others => '0');
seq_pll_start_reconfig <= '0';
elsif rising_edge(clk) then
if sig_dgrb_state = s_seek_cdvw or
sig_dgrb_state = s_test_phases or
sig_dgrb_state = s_reset_cdvw then
seq_pll_select <= pll_resync_clk_index;
seq_pll_inc_dec_n <= sig_rsc_pll_inc_dec_n;
seq_pll_start_reconfig <= sig_rsc_pll_start_reconfig;
elsif sig_dgrb_state = s_track then
seq_pll_select <= sig_trk_pll_select;
seq_pll_inc_dec_n <= sig_trk_pll_inc_dec_n;
seq_pll_start_reconfig <= sig_trk_pll_start_reconfig;
else
seq_pll_select <= pll_measure_clk_index;
seq_pll_inc_dec_n <= '0';
seq_pll_start_reconfig <= '0';
end if;
end if;
end process;
-- ------------------------------------------------------------------
-- Centre of data valid window calculation block
--
-- This block handles the sharing of the centre of window calculation
-- logic between the rsc and trk operations. Functions defined in the
-- header of this entity are called to do this.
-- ------------------------------------------------------------------
cdvw_block : block
signal sig_cdvw_calc_1t : std_logic;
begin
-- purpose: manages centre of data valid window calculations
-- type : sequential
-- inputs : clk, rst_n
-- outputs: sig_cdvw_state
cdvw_proc: process (clk, rst_n)
variable v_cdvw_state : t_window_processing;
variable v_start_calc : std_logic;
variable v_shift_in : std_logic;
variable v_phase : std_logic;
begin -- process cdvw_proc
if rst_n = '0' then -- asynchronous reset (active low)
sig_cdvw_state <= defaults;
sig_cdvw_calc_1t <= '0';
elsif rising_edge(clk) then -- rising clock edge
v_cdvw_state := sig_cdvw_state;
case sig_dgrb_state is
when s_track =>
v_start_calc := sig_trk_cdvw_calc;
v_phase := sig_trk_cdvw_phase;
v_shift_in := sig_trk_cdvw_shift_in;
when s_read_mtp | s_seek_cdvw | s_test_phases =>
v_start_calc := sig_rsc_cdvw_calc;
v_phase := sig_rsc_cdvw_phase;
v_shift_in := sig_rsc_cdvw_shift_in;
when others =>
v_start_calc := '0';
v_phase := '0';
v_shift_in := '0';
end case;
if sig_dgrb_state = s_reset_cdvw or (sig_dgrb_state = s_track and sig_dgrb_last_state /= s_track) then
-- reset *C*entre of *D*ata *V*alid *W*indow
v_cdvw_state := defaults;
elsif sig_cdvw_calc_1t /= '1' and v_start_calc = '1' then
initialise_window_for_proc(v_cdvw_state);
elsif v_cdvw_state.status = calculating then
if sig_dgrb_state = s_track then -- ensure 360 degrees sweep
find_centre_of_largest_data_valid_window(v_cdvw_state, PLL_STEPS_PER_CYCLE);
else -- can be a 720 degrees sweep
find_centre_of_largest_data_valid_window(v_cdvw_state, c_max_phase_shifts);
end if;
elsif v_shift_in = '1' then
if sig_dgrb_state = s_track then -- ensure 360 degrees sweep
shift_in(v_cdvw_state, v_phase, PLL_STEPS_PER_CYCLE);
else
shift_in(v_cdvw_state, v_phase, c_max_phase_shifts);
end if;
end if;
sig_cdvw_calc_1t <= v_start_calc;
sig_cdvw_state <= v_cdvw_state;
end if;
end process cdvw_proc;
end block;
-- ------------------------------------------------------------------
-- block for resync calculation.
--
-- This block implements the following:
-- 1) Control logic for the rsc slave state machine
-- 2) Processing of resync operations - through reports form cdvw block and
-- test pattern match blocks
-- 3) Shifting of the resync phase for rsc sweeps
-- 4) Writing of results to iram (optional)
-- ------------------------------------------------------------------
rsc_block : block
signal sig_rsc_state : t_resync_state;
signal sig_rsc_last_state : t_resync_state;
signal sig_num_phase_shifts : natural range c_max_phase_shifts - 1 downto 0;
signal sig_rewind_direction : std_logic;
signal sig_count : natural range 0 to 2**8 - 1;
signal sig_test_dq_expired : std_logic;
signal sig_chkd_all_dq_pins : std_logic;
-- prompts to write data to iram
signal sig_dgrb_iram : t_iram_push; -- internal copy of dgrb to iram control signals
signal sig_rsc_push_rrp_sweep : std_logic; -- push result of a rrp sweep pass (for cmd_rrp_sweep)
signal sig_rsc_push_rrp_pass : std_logic; -- result of a rrp sweep result (for cmd_rrp_sweep)
signal sig_rsc_push_rrp_seek : std_logic; -- write seek results (for cmd_rrp_seek / cmd_read_mtp states)
signal sig_rsc_push_footer : std_logic; -- write a footer
signal sig_dq_pin_ctr_r : natural range 0 to MEM_IF_DWIDTH - 1; -- registered version of dq_pin_ctr
signal sig_rsc_curr_phase : natural range 0 to c_max_phase_shifts - 1; -- which phase is being processed
signal sig_iram_idle : std_logic; -- track if iram currently writing data
signal sig_mtp_match_en : std_logic;
-- current byte lane disabled?
signal sig_curr_byte_ln_dis : std_logic;
signal sig_iram_wds_req : integer; -- words required for a given iram dump (used to locate where to write footer)
begin
-- When using DQS capture or not at full-rate only match on "even" clock cycles.
sig_mtp_match_en <= active_high(sig_ac_even = '1' or MEM_IF_DQS_CAPTURE = 0 or DWIDTH_RATIO /= 2);
-- register current byte lane disable mux for speed
byte_lane_dis: process (clk, rst_n)
begin
if rst_n = '0' then
sig_curr_byte_ln_dis <= '0';
elsif rising_edge(clk) then
sig_curr_byte_ln_dis <= cal_byte_lanes(sig_dq_pin_ctr/MEM_IF_DQ_PER_DQS);
end if;
end process;
-- check if all dq pins checked in rsc sweep
chkd_dq : process (clk, rst_n)
begin
if rst_n = '0' then
sig_chkd_all_dq_pins <= '0';
elsif rising_edge(clk) then
if sig_dq_pin_ctr = 0 then
sig_chkd_all_dq_pins <= '1';
else
sig_chkd_all_dq_pins <= '0';
end if;
end if;
end process;
-- main rsc process
rsc_proc : process (clk, rst_n)
-- these are temporary variables which should not infer FFs and
-- are not guaranteed to be initialized by s_rsc_idle.
variable v_rdata_correct : std_logic;
variable v_phase_works : std_logic;
begin
if rst_n = '0' then
-- initialise signals
sig_rsc_state <= s_rsc_idle;
sig_rsc_last_state <= s_rsc_idle;
sig_dq_pin_ctr <= 0;
sig_num_phase_shifts <= c_max_phase_shifts - 1; -- want c_max_phase_shifts-1 inc / decs of phase
sig_count <= 0;
sig_test_dq_expired <= '0';
v_phase_works := '0';
-- interface to other processes to tell them when we are done.
sig_rsc_ack <= '0';
sig_rsc_err <= '0';
sig_rsc_result <= std_logic_vector(to_unsigned(C_SUCCESS, c_command_result_len));
-- centre of data valid window functions
sig_rsc_cdvw_phase <= '0';
sig_rsc_cdvw_shift_in <= '0';
sig_rsc_cdvw_calc <= '0';
-- set up PLL reconfig interface controls
sig_rsc_pll_start_reconfig <= '0';
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
sig_rewind_direction <= c_pll_phs_dec;
-- True when access to the ac_block is required.
sig_rsc_ac_access_req <= '0';
-- default values on centre and size of data valid window
if SIM_TIME_REDUCTIONS = 1 then
cal_codvw_phase <= std_logic_vector(to_unsigned(PRESET_CODVW_PHASE, 8));
cal_codvw_size <= std_logic_vector(to_unsigned(PRESET_CODVW_SIZE, 8));
else
cal_codvw_phase <= (others => '0');
cal_codvw_size <= (others => '0');
end if;
sig_rsc_push_rrp_sweep <= '0';
sig_rsc_push_rrp_seek <= '0';
sig_rsc_push_rrp_pass <= '0';
sig_rsc_push_footer <= '0';
codvw_grt_one_dvw <= '0';
elsif rising_edge(clk) then
-- default values assigned to some signals
sig_rsc_ack <= '0';
sig_rsc_cdvw_phase <= '0';
sig_rsc_cdvw_shift_in <= '0';
sig_rsc_cdvw_calc <= '0';
sig_rsc_pll_start_reconfig <= '0';
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
sig_rewind_direction <= c_pll_phs_dec;
-- by default don't ask the resync block to read anything
sig_rsc_ac_access_req <= '0';
sig_rsc_push_rrp_sweep <= '0';
sig_rsc_push_rrp_seek <= '0';
sig_rsc_push_rrp_pass <= '0';
sig_rsc_push_footer <= '0';
sig_test_dq_expired <= '0';
-- resync state machine
case sig_rsc_state is
when s_rsc_idle =>
-- initialize those signals we are ready to use.
sig_dq_pin_ctr <= 0;
sig_count <= 0;
if sig_rsc_state = sig_rsc_last_state then -- avoid transition when acknowledging a command has finished
if sig_rsc_req = s_rsc_test_phase then
sig_rsc_state <= s_rsc_test_phase;
elsif sig_rsc_req = s_rsc_cdvw_calc then
sig_rsc_state <= s_rsc_cdvw_calc;
elsif sig_rsc_req = s_rsc_seek_cdvw then
sig_rsc_state <= s_rsc_seek_cdvw;
elsif sig_rsc_req = s_rsc_reset_cdvw then
sig_rsc_state <= s_rsc_reset_cdvw;
else
sig_rsc_state <= s_rsc_idle;
end if;
end if;
when s_rsc_next_phase =>
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
sig_rsc_pll_start_reconfig <= '1';
if sig_phs_shft_start = '1' then
-- PLL phase shift started - so stop requesting a shift
sig_rsc_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
-- PLL phase shift finished - so proceed to flush the datapath
sig_num_phase_shifts <= sig_num_phase_shifts - 1;
sig_rsc_state <= s_rsc_test_phase;
end if;
when s_rsc_test_phase =>
v_phase_works := '1';
-- Note: For single pin single CS calibration set sig_dq_pin_ctr to 0 to
-- ensure that only 1 pin calibrated
sig_rsc_state <= s_rsc_wait_for_idle_dimm;
if single_bit_cal = '1' then
sig_dq_pin_ctr <= 0;
else
sig_dq_pin_ctr <= MEM_IF_DWIDTH-1;
end if;
when s_rsc_wait_for_idle_dimm =>
if sig_dimm_driving_dq = '0' then
sig_rsc_state <= s_rsc_flush_datapath;
end if;
when s_rsc_flush_datapath =>
sig_rsc_ac_access_req <= '1';
if sig_rsc_state /= sig_rsc_last_state then
-- reset variables we are interested in when we first arrive in this state.
sig_count <= c_max_read_lat - 1;
else
if sig_dimm_driving_dq = '1' then
if sig_count = 0 then
sig_rsc_state <= s_rsc_test_dq;
else
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_rsc_test_dq =>
sig_rsc_ac_access_req <= '1';
if sig_rsc_state /= sig_rsc_last_state then
-- reset variables we are interested in when we first arrive in this state.
sig_count <= 2*c_cal_mtp_t;
else
if sig_dimm_driving_dq = '1' then
if (
(sig_mtp_match = '1' and sig_mtp_match_en = '1') or -- have a pattern match
(sig_test_dq_expired = '1') or -- time in this phase has expired.
sig_curr_byte_ln_dis = '0' -- byte lane disabled
) then
v_phase_works := v_phase_works and ((sig_mtp_match and sig_mtp_match_en) or (not sig_curr_byte_ln_dis));
sig_rsc_push_rrp_sweep <= '1';
sig_rsc_push_rrp_pass <= (sig_mtp_match and sig_mtp_match_en) or (not sig_curr_byte_ln_dis);
if sig_chkd_all_dq_pins = '1' then
-- finished checking all dq pins.
-- done checking this phase.
-- shift phase status into
sig_rsc_cdvw_phase <= v_phase_works;
sig_rsc_cdvw_shift_in <= '1';
if sig_num_phase_shifts /= 0 then
-- there are more phases to test so shift to next phase
sig_rsc_state <= s_rsc_next_phase;
else
-- no more phases to check.
-- clean up after ourselves by
-- going into s_rsc_rewind_phase
sig_rsc_state <= s_rsc_rewind_phase;
sig_rewind_direction <= c_pll_phs_dec;
sig_num_phase_shifts <= c_max_phase_shifts - 1;
end if;
else
-- shift to next dq pin
if MEM_IF_DWIDTH > 71 and -- if >= 72 pins then:
(sig_dq_pin_ctr mod 64) = 0 then -- ensure refreshes at least once every 64 pins
sig_rsc_state <= s_rsc_wait_for_idle_dimm;
else -- otherwise continue sweep
sig_rsc_state <= s_rsc_flush_datapath;
end if;
sig_dq_pin_ctr <= sig_dq_pin_ctr - 1;
end if;
else
sig_count <= sig_count - 1;
if sig_count = 1 then
sig_test_dq_expired <= '1';
end if;
end if;
end if;
end if;
when s_rsc_reset_cdvw =>
sig_rsc_state <= s_rsc_rewind_phase;
-- determine the amount to rewind by (may be wind forward depending on tracking behaviour)
if to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift < 0 then
sig_num_phase_shifts <= - (to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift);
sig_rewind_direction <= c_pll_phs_inc;
else
sig_num_phase_shifts <= (to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift);
sig_rewind_direction <= c_pll_phs_dec;
end if;
-- reset the calibrated phase and size to zero (because un-doing prior calibration here)
cal_codvw_phase <= (others => '0');
cal_codvw_size <= (others => '0');
when s_rsc_rewind_phase =>
-- rewinds the resync PLL by sig_num_phase_shifts steps and returns to idle state
if sig_num_phase_shifts = 0 then
-- no more steps to take off, go to next state
sig_num_phase_shifts <= c_max_phase_shifts - 1;
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
sig_rsc_state <= s_rsc_wait_iram;
else
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
end if;
else
sig_rsc_pll_inc_dec_n <= sig_rewind_direction;
-- request a phase shift
sig_rsc_pll_start_reconfig <= '1';
if sig_phs_shft_busy = '1' then
-- inhibit a phase shift if phase shift is busy.
sig_rsc_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_busy_1t = '1' and sig_phs_shft_busy /= '1' then
-- we've just successfully removed a phase step
-- decrement counter
sig_num_phase_shifts <= sig_num_phase_shifts - 1;
sig_rsc_pll_start_reconfig <= '0';
end if;
end if;
when s_rsc_cdvw_calc =>
if sig_rsc_state /= sig_rsc_last_state then
if sig_dgrb_state = s_read_mtp then
report dgrb_report_prefix & "gathered resync phase samples (for mtp alignment " & natural'image(current_mtp_almt) & ") is DGRB_PHASE_SAMPLES: " & str(sig_cdvw_state.working_window) severity note;
else
report dgrb_report_prefix & "gathered resync phase samples DGRB_PHASE_SAMPLES: " & str(sig_cdvw_state.working_window) severity note;
end if;
sig_rsc_cdvw_calc <= '1'; -- begin calculating result
else
sig_rsc_state <= s_rsc_cdvw_wait;
end if;
when s_rsc_cdvw_wait =>
if sig_cdvw_state.status /= calculating then
-- a result has been reached.
if sig_dgrb_state = s_read_mtp then -- if doing mtp alignment then skip setting phase
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
sig_rsc_state <= s_rsc_wait_iram;
else
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
end if;
else
if sig_cdvw_state.status = valid_result then
-- calculation successfully found a
-- data-valid window to seek to.
sig_rsc_state <= s_rsc_seek_cdvw;
sig_rsc_result <= std_logic_vector(to_unsigned(C_SUCCESS, sig_rsc_result'length));
-- If more than one data valid window was seen, then set the result code :
if (sig_cdvw_state.windows_seen > 1) then
report dgrb_report_prefix & "Warning : multiple data-valid windows found, largest chosen." severity note;
codvw_grt_one_dvw <= '1';
else
report dgrb_report_prefix & "data-valid window found successfully." severity note;
end if;
else
-- calculation failed to find a data-valid window.
report dgrb_report_prefix & "couldn't find a data-valid window in resync." severity warning;
sig_rsc_ack <= '1';
sig_rsc_err <= '1';
sig_rsc_state <= s_rsc_idle;
-- set resync result code
case sig_cdvw_state.status is
when no_invalid_phases =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_rsc_result'length));
when multiple_equal_windows =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS, sig_rsc_result'length));
when no_valid_phases =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_rsc_result'length));
when others =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_CRITICAL, sig_rsc_result'length));
end case;
end if;
end if;
-- signal to write a rrp_sweep result to iram
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
sig_rsc_push_rrp_seek <= '1';
end if;
end if;
when s_rsc_seek_cdvw =>
if sig_rsc_state /= sig_rsc_last_state then
-- reset variables we are interested in when we first arrive in this state
sig_count <= sig_cdvw_state.largest_window_centre;
else
if sig_count = 0 or
((MEM_IF_DQS_CAPTURE = 1 and DWIDTH_RATIO = 2) and
sig_count = PLL_STEPS_PER_CYCLE) -- if FR and DQS capture ensure within 0-360 degrees phase
then
-- ready to transition to next state
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
sig_rsc_state <= s_rsc_wait_iram;
else
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
end if;
-- return largest window centre and size in the result
-- perform cal_codvw phase / size update only if a valid result is found
if sig_cdvw_state.status = valid_result then
cal_codvw_phase <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_centre, 8));
cal_codvw_size <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size, 8));
end if;
-- leaving sig_rsc_err or sig_rsc_result at
-- their default values (of success)
else
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
-- request a phase shift
sig_rsc_pll_start_reconfig <= '1';
if sig_phs_shft_start = '1' then
-- inhibit a phase shift if phase shift is busy
sig_rsc_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
-- we've just successfully removed a phase step
-- decrement counter
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_rsc_wait_iram =>
-- hold off check 1 clock cycle to enable last rsc push operations to start
if sig_rsc_state = sig_rsc_last_state then
if sig_iram_idle = '1' then
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
if sig_dgrb_state = s_test_phases or
sig_dgrb_state = s_seek_cdvw or
sig_dgrb_state = s_read_mtp then
sig_rsc_push_footer <= '1';
end if;
end if;
end if;
when others =>
null;
end case;
sig_rsc_last_state <= sig_rsc_state;
end if;
end process;
-- write results to the iram
iram_push: process (clk, rst_n)
begin
if rst_n = '0' then
sig_dgrb_iram <= defaults;
sig_iram_idle <= '0';
sig_dq_pin_ctr_r <= 0;
sig_rsc_curr_phase <= 0;
sig_iram_wds_req <= 0;
elsif rising_edge(clk) then
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
if sig_dgrb_iram.iram_write = '1' and sig_dgrb_iram.iram_done = '1' then
report dgrb_report_prefix & "iram_done and iram_write signals concurrently set - iram contents may be corrupted" severity failure;
end if;
if sig_dgrb_iram.iram_write = '0' and sig_dgrb_iram.iram_done = '0' then
sig_iram_idle <= '1';
else
sig_iram_idle <= '0';
end if;
-- registered sig_dq_pin_ctr to align with rrp_sweep result
sig_dq_pin_ctr_r <= sig_dq_pin_ctr;
-- calculate current phase (registered to align with rrp_sweep result)
sig_rsc_curr_phase <= (c_max_phase_shifts - 1) - sig_num_phase_shifts;
-- serial push of rrp_sweep results into memory
if sig_rsc_push_rrp_sweep = '1' then
-- signal an iram write and track a write pending
sig_dgrb_iram.iram_write <= '1';
sig_iram_idle <= '0';
-- if not single_bit_cal then pack pin phase results in MEM_IF_DWIDTH word blocks
if single_bit_cal = '1' then
sig_dgrb_iram.iram_wordnum <= sig_dq_pin_ctr_r + (sig_rsc_curr_phase/32);
sig_iram_wds_req <= iram_wd_for_one_pin_rrp( DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE); -- note total word requirement
else
sig_dgrb_iram.iram_wordnum <= sig_dq_pin_ctr_r + (sig_rsc_curr_phase/32) * MEM_IF_DWIDTH;
sig_iram_wds_req <= iram_wd_for_full_rrp( DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE); -- note total word requirement
end if;
-- check if current pin and phase passed:
sig_dgrb_iram.iram_pushdata(0) <= sig_rsc_push_rrp_pass;
-- bit offset is modulo phase
sig_dgrb_iram.iram_bitnum <= sig_rsc_curr_phase mod 32;
end if;
-- write result of rrp_calc to iram when completed
if sig_rsc_push_rrp_seek = '1' then -- a result found
sig_dgrb_iram.iram_write <= '1';
sig_iram_idle <= '0';
sig_dgrb_iram.iram_wordnum <= 0;
sig_iram_wds_req <= 1; -- note total word requirement
if sig_cdvw_state.status = valid_result then -- result is valid
sig_dgrb_iram.iram_pushdata <= x"0000" &
std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_centre, 8)) &
std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size, 8));
else -- invalid result (error code communicated elsewhere)
sig_dgrb_iram.iram_pushdata <= x"FFFF" & -- signals an error condition
x"0000";
end if;
end if;
-- when stage finished write footer
if sig_rsc_push_footer = '1' then
sig_dgrb_iram.iram_done <= '1';
sig_iram_idle <= '0';
-- set address location of footer
sig_dgrb_iram.iram_wordnum <= sig_iram_wds_req;
end if;
-- if write completed deassert iram_write and done signals
if iram_push_done = '1' then
sig_dgrb_iram.iram_write <= '0';
sig_dgrb_iram.iram_done <= '0';
end if;
else
sig_iram_idle <= '0';
sig_dq_pin_ctr_r <= 0;
sig_rsc_curr_phase <= 0;
sig_dgrb_iram <= defaults;
end if;
end if;
end process;
-- concurrently assign sig_dgrb_iram to dgrb_iram
dgrb_iram <= sig_dgrb_iram;
end block; -- resync calculation
-- ------------------------------------------------------------------
-- test pattern match block
--
-- This block handles the sharing of logic for test pattern matching
-- which is used in resync and postamble calibration / code blocks
-- ------------------------------------------------------------------
tp_match_block : block
--
-- Ascii Waveforms:
--
-- ; ; ; ; ; ;
-- ____ ____ ____ ____ ____ ____
-- delayed_dqs |____| |____| |____| |____| |____| |____| |____|
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; _______ ; _______ ; _______ ; _______ ; _______ _______
-- XXXXX / \ / \ / \ / \ / \ / \
-- c0,c1 XXXXXX A B X C D X E F X G H X I J X L M X captured data
-- XXXXX \_______/ \_______/ \_______/ \_______/ \_______/ \_______/
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ____; ____; ____ ____ ____ ____ ____
-- 180-resync_clk |____| |____| |____| |____| |____| |____| | 180deg shift from delayed dqs
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; _______ _______ _______ _______ _______ ____
-- XXXXXXXXXX / \ / \ / \ / \ / \ /
-- 180-r0,r1 XXXXXXXXXXX A B X C D X E F X G H X I J X L resync data
-- XXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \_______/ \____
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ____ ____ ____ ____ ____ ____
-- 360-resync_clk ____| |____| |____| |____| |____| |____| |____|
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; _______ ; _______ ; _______ ; _______ ; _______
-- XXXXXXXXXXXXXXX / \ / \ / \ / \ / \
-- 360-r0,r1 XXXXXXXXXXXXXXXX A B X C D X E F X G H X I J X resync data
-- XXXXXXXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \_______/
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ____ ____ ____ ____ ____ ____ ____
-- 540-resync_clk |____| |____| |____| |____| |____| |____| |
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; _______ _______ _______ _______ ____
-- XXXXXXXXXXXXXXXXXXX / \ / \ / \ / \ /
-- 540-r0,r1 XXXXXXXXXXXXXXXXXXXX A B X C D X E F X G H X I resync data
-- XXXXXXXXXXXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \____
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ;____ ____ ____ ____ ____ ____
-- phy_clk |____| |____| |____| |____| |____| |____| |____|
--
-- 0 1 2 3 4 5 6
--
--
-- |<- Aligned Data ->|
-- phy_clk 180-r0,r1 540-r0,r1 sig_mtp_match_en (generated from sig_ac_even)
-- 0 XXXXXXXX XXXXXXXX '1'
-- 1 XXXXXXAB XXXXXXXX '0'
-- 2 XXXXABCD XXXXXXAB '1'
-- 3 XXABCDEF XXXXABCD '0'
-- 4 ABCDEFGH XXABCDEF '1'
-- 5 CDEFGHAB ABCDEFGH '0'
--
-- In DQS-based capture, sweeping resync_clk from 180 degrees to 360
-- does not necessarily result in a failure because the setup/hold
-- requirements are so small. The data comparison needs to fail when
-- the resync_clk is shifted more than 360 degrees. The
-- sig_mtp_match_en signal allows the sequencer to blind itself
-- training pattern matches that occur above 360 degrees.
--
--
--
--
--
-- Asserts sig_mtp_match.
--
-- Data comes in from rdata and is pushed into a two-bit wide shift register.
-- It is a critical assumption that the rdata comes back byte aligned.
--
--
--sig_mtp_match_valid
-- rdata_valid (shift-enable)
-- |
-- |
-- +-----------------------+-----------+------------------+
-- ___ | | |
-- dq(0) >---| \ | Shift Register |
-- dq(1) >---| \ +------+ +------+ +------------------+
-- dq(2) >---| )--->| D(0) |-+->| D(1) |-+->...-+->| D(c_cal_mtp_len - 1) |
-- ... | / +------+ | +------+ | | +------------------+
-- dq(n-1) >---|___/ +-----------++-...-+
-- | || +---+
-- | (==)--------> sig_mtp_match_0t ---->| |-->sig_mtp_match_1t-->sig_mtp_match
-- | || +---+
-- | +-----------++...-+
-- sig_dq_pin_ctr >-+ +------+ | +------+ | | +------------------+
-- | P(0) |-+ | P(1) |-+ ...-+->| P(c_cal_mtp_len - 1) |
-- +------+ +------+ +------------------+
--
--
--
--
signal sig_rdata_current_pin : std_logic_vector(c_cal_mtp_len - 1 downto 0);
-- A fundamental assumption here is that rdata_valid is all
-- ones or all zeros - not both.
signal sig_rdata_valid_1t : std_logic; -- rdata_valid delayed by 1 clock period.
signal sig_rdata_valid_2t : std_logic; -- rdata_valid delayed by 2 clock periods.
begin
rdata_valid_1t_proc : process (clk, rst_n)
begin
if rst_n = '0' then
sig_rdata_valid_1t <= '0';
sig_rdata_valid_2t <= '0';
elsif rising_edge(clk) then
sig_rdata_valid_2t <= sig_rdata_valid_1t;
sig_rdata_valid_1t <= rdata_valid(0);
end if;
end process;
-- MUX data into sig_rdata_current_pin shift register.
rdata_current_pin_proc: process (clk, rst_n)
begin
if rst_n = '0' then
sig_rdata_current_pin <= (others => '0');
elsif rising_edge(clk) then
-- shift old data down the shift register
sig_rdata_current_pin(sig_rdata_current_pin'high - DWIDTH_RATIO downto 0) <=
sig_rdata_current_pin(sig_rdata_current_pin'high downto DWIDTH_RATIO);
-- shift new data into the bottom of the shift register.
for i in 0 to DWIDTH_RATIO - 1 loop
sig_rdata_current_pin(sig_rdata_current_pin'high - DWIDTH_RATIO + 1 + i) <= rdata(i*MEM_IF_DWIDTH + sig_dq_pin_ctr);
end loop;
end if;
end process;
mtp_match_proc : process (clk, rst_n)
begin
if rst_n = '0' then -- * when at least c_max_read_lat clock cycles have passed
sig_mtp_match <= '0';
elsif rising_edge(clk) then
sig_mtp_match <= '0';
if sig_rdata_current_pin = c_cal_mtp then
sig_mtp_match <= '1';
end if;
end if;
end process;
poa_match_proc : process (clk, rst_n)
-- poa_match_Calibration Strategy
--
-- Ascii Waveforms:
--
-- __ __ __ __ __ __ __ __ __
-- clk __| |__| |__| |__| |__| |__| |__| |__| |__| |
--
-- ; ; ; ;
-- _________________
-- rdata_valid ________| |___________________________
--
-- ; ; ; ;
-- _____
-- poa_match_en ______________________________________| |_______________
--
-- ; ; ; ;
-- _____
-- poa_match XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX
--
--
-- Notes:
-- -poa_match is only valid while poa_match_en is asserted.
--
--
--
--
--
--
begin
if rst_n = '0' then
sig_poa_match_en <= '0';
sig_poa_match <= '0';
elsif rising_edge(clk) then
sig_poa_match <= '0';
sig_poa_match_en <= '0';
if sig_rdata_valid_2t = '1' and sig_rdata_valid_1t = '0' then
sig_poa_match_en <= '1';
end if;
if DWIDTH_RATIO = 2 then
if sig_rdata_current_pin(sig_rdata_current_pin'high downto sig_rdata_current_pin'length - 6) = "111100" then
sig_poa_match <= '1';
end if;
elsif DWIDTH_RATIO = 4 then
if sig_rdata_current_pin(sig_rdata_current_pin'high downto sig_rdata_current_pin'length - 8) = "11111100" then
sig_poa_match <= '1';
end if;
else
report dgrb_report_prefix & "unsupported DWIDTH_RATIO" severity failure;
end if;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- Postamble calibration
--
-- Implements the postamble slave state machine and collates the
-- processing data from the test pattern match block.
-- ------------------------------------------------------------------
poa_block : block
-- Postamble Calibration Strategy
--
-- Ascii Waveforms:
--
-- c_read_burst_t c_read_burst_t
-- ;<------->; ;<------->;
-- ; ; ; ;
-- __ / / __
-- mem_dq[0] ___________| |_____\ \________| |___
--
-- ; ; ; ;
-- ; ; ; ;
-- _________ / / _________
-- poa_enable ______| |___\ \_| |___
-- ; ; ; ;
-- ; ; ; ;
-- __ / / ______
-- rdata[0] ___________| |______\ \_______|
-- ; ; ; ;
-- ; ; ; ;
-- ; ; ; ;
-- _ / / _
-- poa_match_en _____________| |___\ \___________| |_
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- / / _
-- poa_match ___________________\ \___________| |_
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _ / /
-- seq_poa_lat_dec _______________| |_\ \_______________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- / /
-- seq_poa_lat_inc ___________________\ \_______________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
--
-- (1) (2)
--
--
-- (1) poa_enable signal is late, and the zeros on mem_dq after (1)
-- are captured.
-- (2) poa_enable signal is aligned. Zeros following (2) are not
-- captured rdata remains at '1'.
--
-- The DQS capture circuit wth the dqs enable asynchronous set.
--
--
--
-- dqs_en_async_preset ----------+
-- |
-- v
-- +---------+
-- +--|Q SET D|----------- gnd
-- | | <O---+
-- | +---------+ |
-- | |
-- | |
-- +--+---. |
-- |AND )--------+------- dqs_bus
-- delayed_dqs -----+---^
--
--
--
-- _____ _____ _____ _____
-- dqs ____| |_____| |_____| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- ; ; ; ; ;
-- ; ; ; ;
-- _____ _____ _____ _____
-- delayed_dqs _______| |_____| |_____| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--
-- ; ; ; ; ;
-- ; ______________________________________________________________
-- dqs_en_async_ _____________________________| |_____
-- preset
-- ; ; ; ; ;
-- ; ; ; ; ;
-- _____ _____ _____
-- dqs_bus _______| |_________________| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--
-- ; ;
-- (1) (2)
--
--
-- Notes:
-- (1) The dqs_bus pulse here comes because the last value of Q
-- is '1' until the first DQS pulse clocks gnd into the FF,
-- brings low the AND gate, and disables dqs_bus. A training
-- pattern could potentially match at this point even though
-- between (1) and (2) there are no dqs_bus triggers. Data
-- is frozen on rdata while awaiting the dqs_bus pulses at
-- (2). For this reason, wait until the first match of the
-- training pattern, and continue reducing latency until it
-- TP no longer matches, then increase latency by one. In
-- this case, dqs_en_async_preset will have its latency
-- reduced by three until the training pattern is not matched,
-- then latency is increased by one.
--
--
--
--
-- Postamble calibration state
type t_poa_state is (
-- decrease poa enable latency by 1 cycle iteratively until 'correct' position found
s_poa_rewind_to_pass,
-- poa cal complete
s_poa_done
);
constant c_poa_lat_cmd_wait : natural := 10; -- Number of clock cycles to wait for lat_inc/lat_dec signal to take effect.
constant c_poa_max_lat : natural := 100; -- Maximum number of allowable latency changes.
signal sig_poa_adjust_count : integer range 0 to 2**8 - 1;
signal sig_poa_state : t_poa_state;
begin
poa_proc : process (clk, rst_n)
begin
if rst_n = '0' then
sig_poa_ack <= '0';
seq_poa_lat_dec_1x <= (others => '0');
seq_poa_lat_inc_1x <= (others => '0');
sig_poa_adjust_count <= 0;
sig_poa_state <= s_poa_rewind_to_pass;
elsif rising_edge(clk) then
sig_poa_ack <= '0';
seq_poa_lat_inc_1x <= (others => '0');
seq_poa_lat_dec_1x <= (others => '0');
if sig_dgrb_state = s_poa_cal then
case sig_poa_state is
when s_poa_rewind_to_pass =>
-- In postamble calibration
--
-- Normally, must wait for sig_dimm_driving_dq to be '1'
-- before reading, but by this point in calibration
-- rdata_valid is assumed to be set up properly. The
-- sig_poa_match_en (derived from rdata_valid) is used
-- here rather than sig_dimm_driving_dq.
if sig_poa_match_en = '1' then
if sig_poa_match = '1' then
sig_poa_state <= s_poa_done;
else
seq_poa_lat_dec_1x <= (others => '1');
end if;
sig_poa_adjust_count <= sig_poa_adjust_count + 1;
end if;
when s_poa_done =>
sig_poa_ack <= '1';
end case;
else
sig_poa_state <= s_poa_rewind_to_pass;
sig_poa_adjust_count <= 0;
end if;
assert sig_poa_adjust_count <= c_poa_max_lat
report dgrb_report_prefix & "Maximum number of postamble latency adjustments exceeded."
severity failure;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- code block for tracking signal generation
--
-- this is used for initial tracking setup (finding a reference window)
-- and periodic tracking operations (PVT compensation on rsc phase)
--
-- A slave trk state machine is described and implemented within the block
-- The mimic path is controlled within this block
-- ------------------------------------------------------------------
trk_block : block
type t_tracking_state is (
-- initialise variables out of reset
s_trk_init,
-- idle state
s_trk_idle,
-- sample data from the mimic path (build window)
s_trk_mimic_sample,
-- 'shift' mimic path phase
s_trk_next_phase,
-- calculate mimic window
s_trk_cdvw_calc,
s_trk_cdvw_wait, -- for results
-- calculate how much mimic window has moved (only entered in periodic tracking)
s_trk_cdvw_drift,
-- track rsc phase (only entered in periodic tracking)
s_trk_adjust_resync,
-- communicate command complete to the master state machine
s_trk_complete
);
signal sig_mmc_seq_done : std_logic;
signal sig_mmc_seq_done_1t : std_logic;
signal mmc_seq_value_r : std_logic;
signal sig_mmc_start : std_logic;
signal sig_trk_state : t_tracking_state;
signal sig_trk_last_state : t_tracking_state;
signal sig_rsc_drift : integer range -c_max_rsc_drift_in_phases to c_max_rsc_drift_in_phases; -- stores total change in rsc phase from first calibration
signal sig_req_rsc_shift : integer range -c_max_rsc_drift_in_phases to c_max_rsc_drift_in_phases; -- stores required shift in rsc phase instantaneously
signal sig_mimic_cdv_found : std_logic;
signal sig_mimic_cdv : integer range 0 to PLL_STEPS_PER_CYCLE; -- centre of data valid window calculated from first mimic-cycle
signal sig_mimic_delta : integer range -PLL_STEPS_PER_CYCLE to PLL_STEPS_PER_CYCLE;
signal sig_large_drift_seen : std_logic;
signal sig_remaining_samples : natural range 0 to 2**8 - 1;
begin
-- advertise the codvw phase shift
process (clk, rst_n)
variable v_length : integer;
begin
if rst_n = '0' then
codvw_trk_shift <= (others => '0');
elsif rising_edge(clk) then
if sig_mimic_cdv_found = '1' then
-- check range
v_length := codvw_trk_shift'length;
codvw_trk_shift <= std_logic_vector(to_signed(sig_rsc_drift, v_length));
else
codvw_trk_shift <= (others => '0');
end if;
end if;
end process;
-- request a mimic sample
mimic_sample_req : process (clk, rst_n)
variable seq_mmc_start_r : std_logic_vector(3 downto 0);
begin
if rst_n = '0' then
seq_mmc_start <= '0';
seq_mmc_start_r := "0000";
elsif rising_edge(clk) then
seq_mmc_start_r(3) := seq_mmc_start_r(2);
seq_mmc_start_r(2) := seq_mmc_start_r(1);
seq_mmc_start_r(1) := seq_mmc_start_r(0);
-- extend sig_mmc_start by one clock cycle
if sig_mmc_start = '1' then
seq_mmc_start <= '1';
seq_mmc_start_r(0) := '1';
elsif ( (seq_mmc_start_r(3) = '1') or (seq_mmc_start_r(2) = '1') or (seq_mmc_start_r(1) = '1') or (seq_mmc_start_r(0) = '1') ) then
seq_mmc_start <= '1';
seq_mmc_start_r(0) := '0';
else
seq_mmc_start <= '0';
end if;
end if;
end process;
-- metastability hardening of async mmc_seq_done signal
mmc_seq_req_sync : process (clk, rst_n)
variable v_mmc_seq_done_1r : std_logic;
variable v_mmc_seq_done_2r : std_logic;
variable v_mmc_seq_done_3r : std_logic;
begin
if rst_n = '0' then
sig_mmc_seq_done <= '0';
sig_mmc_seq_done_1t <= '0';
v_mmc_seq_done_1r := '0';
v_mmc_seq_done_2r := '0';
v_mmc_seq_done_3r := '0';
elsif rising_edge(clk) then
sig_mmc_seq_done_1t <= v_mmc_seq_done_3r;
sig_mmc_seq_done <= v_mmc_seq_done_2r;
mmc_seq_value_r <= mmc_seq_value;
v_mmc_seq_done_3r := v_mmc_seq_done_2r;
v_mmc_seq_done_2r := v_mmc_seq_done_1r;
v_mmc_seq_done_1r := mmc_seq_done;
end if;
end process;
-- collect mimic samples as they arrive
shift_in_mmc_seq_value : process (clk, rst_n)
begin
if rst_n = '0' then
sig_trk_cdvw_shift_in <= '0';
sig_trk_cdvw_phase <= '0';
elsif rising_edge(clk) then
sig_trk_cdvw_shift_in <= '0';
sig_trk_cdvw_phase <= '0';
if sig_mmc_seq_done_1t = '1' and sig_mmc_seq_done = '0' then
sig_trk_cdvw_shift_in <= '1';
sig_trk_cdvw_phase <= mmc_seq_value_r;
end if;
end if;
end process;
-- main tracking state machine
trk_proc : process (clk, rst_n)
begin
if rst_n = '0' then
sig_trk_state <= s_trk_init;
sig_trk_last_state <= s_trk_init;
sig_trk_result <= (others => '0');
sig_trk_err <= '0';
sig_mmc_start <= '0';
sig_trk_pll_select <= (others => '0');
sig_req_rsc_shift <= -c_max_rsc_drift_in_phases;
sig_rsc_drift <= -c_max_rsc_drift_in_phases;
sig_mimic_delta <= -PLL_STEPS_PER_CYCLE;
sig_mimic_cdv_found <= '0';
sig_mimic_cdv <= 0;
sig_large_drift_seen <= '0';
sig_trk_cdvw_calc <= '0';
sig_remaining_samples <= 0;
sig_trk_pll_start_reconfig <= '0';
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
sig_trk_ack <= '0';
elsif rising_edge(clk) then
sig_trk_pll_select <= pll_measure_clk_index;
sig_trk_pll_start_reconfig <= '0';
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
sig_large_drift_seen <= '0';
sig_trk_cdvw_calc <= '0';
sig_trk_ack <= '0';
sig_trk_err <= '0';
sig_trk_result <= (others => '0');
sig_mmc_start <= '0';
-- if no cdv found then reset tracking results
if sig_mimic_cdv_found = '0' then
sig_rsc_drift <= 0;
sig_req_rsc_shift <= 0;
sig_mimic_delta <= 0;
end if;
if sig_dgrb_state = s_track then
-- resync state machine
case sig_trk_state is
when s_trk_init =>
sig_trk_state <= s_trk_idle;
sig_mimic_cdv_found <= '0';
sig_rsc_drift <= 0;
sig_req_rsc_shift <= 0;
sig_mimic_delta <= 0;
when s_trk_idle =>
sig_remaining_samples <= PLL_STEPS_PER_CYCLE; -- ensure a 360 degrees sweep
sig_trk_state <= s_trk_mimic_sample;
when s_trk_mimic_sample =>
if sig_remaining_samples = 0 then
sig_trk_state <= s_trk_cdvw_calc;
else
if sig_trk_state /= sig_trk_last_state then
-- request a sample as soon as we arrive in this state.
-- the default value of sig_mmc_start is zero!
sig_mmc_start <= '1';
end if;
if sig_mmc_seq_done_1t = '1' and sig_mmc_seq_done = '0' then
-- a sample has been collected, go to next PLL phase
sig_remaining_samples <= sig_remaining_samples - 1;
sig_trk_state <= s_trk_next_phase;
end if;
end if;
when s_trk_next_phase =>
sig_trk_pll_start_reconfig <= '1';
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
if sig_phs_shft_start = '1' then
sig_trk_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
sig_trk_state <= s_trk_mimic_sample;
end if;
when s_trk_cdvw_calc =>
if sig_trk_state /= sig_trk_last_state then
-- reset variables we are interested in when we first arrive in this state
sig_trk_cdvw_calc <= '1';
report dgrb_report_prefix & "gathered mimic phase samples DGRB_MIMIC_SAMPLES: " & str(sig_cdvw_state.working_window(sig_cdvw_state.working_window'high downto sig_cdvw_state.working_window'length - PLL_STEPS_PER_CYCLE)) severity note;
else
sig_trk_state <= s_trk_cdvw_wait;
end if;
when s_trk_cdvw_wait =>
if sig_cdvw_state.status /= calculating then
if sig_cdvw_state.status = valid_result then
report dgrb_report_prefix & "mimic window successfully found." severity note;
if sig_mimic_cdv_found = '0' then -- first run of tracking operation
sig_mimic_cdv_found <= '1';
sig_mimic_cdv <= sig_cdvw_state.largest_window_centre;
sig_trk_state <= s_trk_complete;
else -- subsequent tracking operation runs
sig_mimic_delta <= sig_mimic_cdv - sig_cdvw_state.largest_window_centre;
sig_mimic_cdv <= sig_cdvw_state.largest_window_centre;
sig_trk_state <= s_trk_cdvw_drift;
end if;
else
report dgrb_report_prefix & "couldn't find a data-valid window for tracking." severity cal_fail_sev_level;
sig_trk_ack <= '1';
sig_trk_err <= '1';
sig_trk_state <= s_trk_idle;
-- set resync result code
case sig_cdvw_state.status is
when no_invalid_phases =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_INVALID_PHASES, sig_trk_result'length));
when multiple_equal_windows =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS, sig_trk_result'length));
when no_valid_phases =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_trk_result'length));
when others =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_CRITICAL, sig_trk_result'length));
end case;
end if;
end if;
when s_trk_cdvw_drift => -- calculate the drift in rsc phase
-- pipeline stage 1
if abs(sig_mimic_delta) > PLL_STEPS_PER_CYCLE/2 then
sig_large_drift_seen <= '1';
else
sig_large_drift_seen <= '0';
end if;
--pipeline stage 2
if sig_trk_state = sig_trk_last_state then
if sig_large_drift_seen = '1' then
if sig_mimic_delta < 0 then -- anti-clockwise movement
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta + PLL_STEPS_PER_CYCLE;
else -- clockwise movement
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta - PLL_STEPS_PER_CYCLE;
end if;
else
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta;
end if;
sig_trk_state <= s_trk_adjust_resync;
end if;
when s_trk_adjust_resync =>
sig_trk_pll_select <= pll_resync_clk_index;
sig_trk_pll_start_reconfig <= '1';
if sig_trk_state /= sig_trk_last_state then
if sig_req_rsc_shift < 0 then
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
sig_req_rsc_shift <= sig_req_rsc_shift + 1;
sig_rsc_drift <= sig_rsc_drift + 1;
elsif sig_req_rsc_shift > 0 then
sig_trk_pll_inc_dec_n <= c_pll_phs_dec;
sig_req_rsc_shift <= sig_req_rsc_shift - 1;
sig_rsc_drift <= sig_rsc_drift - 1;
else
sig_trk_state <= s_trk_complete;
sig_trk_pll_start_reconfig <= '0';
end if;
else
sig_trk_pll_inc_dec_n <= sig_trk_pll_inc_dec_n; -- maintain current value
end if;
if abs(sig_rsc_drift) = c_max_rsc_drift_in_phases then
report dgrb_report_prefix & " a maximum absolute change in resync_clk of " & integer'image(sig_rsc_drift) & " phases has " & LF &
" occurred (since read resynch phase calibration) during tracking" severity cal_fail_sev_level;
sig_trk_err <= '1';
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_MAX_TRK_SHFT_EXCEEDED, sig_trk_result'length));
end if;
if sig_phs_shft_start = '1' then
sig_trk_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
sig_trk_state <= s_trk_complete;
end if;
when s_trk_complete =>
sig_trk_ack <= '1';
end case;
sig_trk_last_state <= sig_trk_state;
else
sig_trk_state <= s_trk_idle;
sig_trk_last_state <= s_trk_idle;
end if;
end if;
end process;
rsc_drift: process (sig_rsc_drift)
begin
sig_trk_rsc_drift <= sig_rsc_drift; -- communicate tracking shift to rsc process
end process;
end block; -- tracking signals
-- ------------------------------------------------------------------
-- write-datapath (WDP) ` and on-chip-termination (OCT) signal
-- ------------------------------------------------------------------
wdp_oct : process(clk,rst_n)
begin
if rst_n = '0' then
seq_oct_value <= c_set_oct_to_rs;
dgrb_wdp_ovride <= '0';
elsif rising_edge(clk) then
if ((sig_dgrb_state = s_idle) or (EN_OCT = 0)) then
seq_oct_value <= c_set_oct_to_rs;
dgrb_wdp_ovride <= '0';
else
seq_oct_value <= c_set_oct_to_rt;
dgrb_wdp_ovride <= '1';
end if;
end if;
end process;
-- ------------------------------------------------------------------
-- handles muxing of error codes to the control block
-- ------------------------------------------------------------------
ac_handshake_proc : process(rst_n, clk)
begin
if rst_n = '0' then
dgrb_ctrl <= defaults;
elsif rising_edge(clk) then
dgrb_ctrl <= defaults;
if sig_dgrb_state = s_wait_admin and sig_dgrb_last_state = s_idle then
dgrb_ctrl.command_ack <= '1';
end if;
case sig_dgrb_state is
when s_seek_cdvw =>
dgrb_ctrl.command_err <= sig_rsc_err;
dgrb_ctrl.command_result <= sig_rsc_result;
when s_track =>
dgrb_ctrl.command_err <= sig_trk_err;
dgrb_ctrl.command_result <= sig_trk_result;
when others => -- from main state machine
dgrb_ctrl.command_err <= sig_cmd_err;
dgrb_ctrl.command_result <= sig_cmd_result;
end case;
if ctrl_dgrb_r.command = cmd_read_mtp then -- check against command because aligned with command done not command_err
dgrb_ctrl.command_err <= '0';
dgrb_ctrl.command_result <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size,dgrb_ctrl.command_result'length));
end if;
if sig_dgrb_state = s_idle and sig_dgrb_last_state = s_release_admin then
dgrb_ctrl.command_done <= '1';
end if;
end if;
end process;
-- ------------------------------------------------------------------
-- address/command state machine
-- process is commanded to begin reading training patterns.
--
-- implements the address/command slave state machine
-- issues read commands to the memory relative to given calibration
-- stage being implemented
-- burst length is dependent on memory type
-- ------------------------------------------------------------------
ac_block : block
-- override the calibration burst length for DDR3 device support
-- (requires BL8 / on the fly setting in MR in admin block)
function set_read_bl ( memtype: in string ) return natural is
begin
if memtype = "DDR3" then
return 8;
elsif memtype = "DDR" or memtype = "DDR2" then
return c_cal_burst_len;
else
report dgrb_report_prefix & " a calibration burst length choice has not been set for memory type " & memtype severity failure;
end if;
return 0;
end function;
-- parameterisation of the read algorithm by burst length
constant c_poa_addr_width : natural := 6;
constant c_cal_read_burst_len : natural := set_read_bl(MEM_IF_MEMTYPE);
constant c_bursts_per_btp : natural := c_cal_mtp_len / c_cal_read_burst_len;
constant c_read_burst_t : natural := c_cal_read_burst_len / DWIDTH_RATIO;
constant c_max_rdata_valid_lat : natural := 50*(c_cal_read_burst_len / DWIDTH_RATIO); -- maximum latency that rdata_valid can ever have with respect to doing_rd
constant c_rdv_ones_rd_clks : natural := (c_max_rdata_valid_lat + c_read_burst_t) / c_read_burst_t; -- number of cycles to read ones for before a pulse of zeros
-- array of burst training pattern addresses
-- here the MTP is used in this addressing
subtype t_btp_addr is natural range 0 to 2 ** MEM_IF_ADDR_WIDTH - 1;
type t_btp_addr_array is array (0 to c_bursts_per_btp - 1) of t_btp_addr;
-- default values
function defaults return t_btp_addr_array is
variable v_btp_array : t_btp_addr_array;
begin
for i in 0 to c_bursts_per_btp - 1 loop
v_btp_array(i) := 0;
end loop;
return v_btp_array;
end function;
-- load btp array addresses
-- Note: this scales to burst lengths of 2, 4 and 8
-- the settings here are specific to the choice of training pattern and need updating if the pattern changes
function set_btp_addr (mtp_almt : natural ) return t_btp_addr_array is
variable v_addr_array : t_btp_addr_array;
begin
for i in 0 to 8/c_cal_read_burst_len - 1 loop
-- set addresses for xF5 data
v_addr_array((c_bursts_per_btp - 1) - i) := MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5 + i*c_cal_read_burst_len;
-- set addresses for x30 data (based on mtp alignment)
if mtp_almt = 0 then
v_addr_array((c_bursts_per_btp - 1) - (8/c_cal_read_burst_len + i)) := MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0 + i*c_cal_read_burst_len;
else
v_addr_array((c_bursts_per_btp - 1) - (8/c_cal_read_burst_len + i)) := MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1 + i*c_cal_read_burst_len;
end if;
end loop;
return v_addr_array;
end function;
function find_poa_cycle_period return natural is
-- Returns the period over which the postamble reads
-- repeat in c_read_burst_t units.
variable v_num_bursts : natural;
begin
v_num_bursts := 2 ** c_poa_addr_width / c_read_burst_t;
if v_num_bursts * c_read_burst_t < 2**c_poa_addr_width then
v_num_bursts := v_num_bursts + 1;
end if;
v_num_bursts := v_num_bursts + c_bursts_per_btp + 1;
return v_num_bursts;
end function;
function get_poa_burst_addr(burst_count : in natural; mtp_almt : in natural) return t_btp_addr is
variable v_addr : t_btp_addr;
begin
if burst_count = 0 then
if mtp_almt = 0 then
v_addr := c_cal_ofs_x30_almt_1;
elsif mtp_almt = 1 then
v_addr := c_cal_ofs_x30_almt_0;
else
report "Unsupported mtp_almt " & natural'image(mtp_almt) severity failure;
end if;
-- address gets incremented by four if in burst-length four.
v_addr := v_addr + (8 - c_cal_read_burst_len);
else
v_addr := c_cal_ofs_zeros;
end if;
return v_addr;
end function;
signal btp_addr_array : t_btp_addr_array; -- burst training pattern addresses
signal sig_addr_cmd_state : t_ac_state;
signal sig_addr_cmd_last_state : t_ac_state;
signal sig_doing_rd_count : integer range 0 to c_read_burst_t - 1;
signal sig_count : integer range 0 to 2**8 - 1;
signal sig_setup : integer range c_max_read_lat downto 0;
signal sig_burst_count : integer range 0 to c_read_burst_t;
begin
-- handles counts for when to begin burst-reads (sig_burst_count)
-- sets sig_dimm_driving_dq
-- sets dgrb_ac_access_req
dimm_driving_dq_proc : process(rst_n, clk)
begin
if rst_n = '0' then
sig_dimm_driving_dq <= '1';
sig_setup <= c_max_read_lat;
sig_burst_count <= 0;
dgrb_ac_access_req <= '0';
sig_ac_even <= '0';
elsif rising_edge(clk) then
sig_dimm_driving_dq <= '0';
if sig_addr_cmd_state /= s_ac_idle and sig_addr_cmd_state /= s_ac_relax then
dgrb_ac_access_req <= '1';
else
dgrb_ac_access_req <= '0';
end if;
case sig_addr_cmd_state is
when s_ac_read_mtp | s_ac_read_rdv | s_ac_read_wd_lat | s_ac_read_poa_mtp =>
sig_ac_even <= not sig_ac_even;
-- a counter that keeps track of when we are ready
-- to issue a burst read. Issue burst read eigvery
-- time we are at zero.
if sig_burst_count = 0 then
sig_burst_count <= c_read_burst_t - 1;
else
sig_burst_count <= sig_burst_count - 1;
end if;
if dgrb_ac_access_gnt /= '1' then
sig_setup <= c_max_read_lat;
else
-- primes reads
-- signal that dimms are driving dq pins after
-- at least c_max_read_lat clock cycles have passed.
--
if sig_setup = 0 then
sig_dimm_driving_dq <= '1';
elsif dgrb_ac_access_gnt = '1' then
sig_setup <= sig_setup - 1;
end if;
end if;
when s_ac_relax =>
sig_dimm_driving_dq <= '1';
sig_burst_count <= 0;
sig_ac_even <= '0';
when others =>
sig_burst_count <= 0;
sig_ac_even <= '0';
end case;
end if;
end process;
ac_proc : process(rst_n, clk)
begin
if rst_n = '0' then
sig_count <= 0;
sig_addr_cmd_state <= s_ac_idle;
sig_addr_cmd_last_state <= s_ac_idle;
sig_doing_rd_count <= 0;
sig_addr_cmd <= reset(c_seq_addr_cmd_config);
btp_addr_array <= defaults;
sig_doing_rd <= (others => '0');
elsif rising_edge(clk) then
assert c_cal_mtp_len mod c_cal_read_burst_len = 0 report dgrb_report_prefix & "burst-training pattern length must be a multiple of burst-length." severity failure;
assert MEM_IF_CAL_BANK < 2**MEM_IF_BANKADDR_WIDTH report dgrb_report_prefix & "MEM_IF_CAL_BANK out of range." severity failure;
assert MEM_IF_CAL_BASE_COL < 2**MEM_IF_ADDR_WIDTH - 1 - C_CAL_DATA_LEN report dgrb_report_prefix & "MEM_IF_CAL_BASE_COL out of range." severity failure;
sig_addr_cmd <= deselect(c_seq_addr_cmd_config, sig_addr_cmd);
if sig_ac_req /= sig_addr_cmd_state and sig_addr_cmd_state /= s_ac_idle then
-- and dgrb_ac_access_gnt = '1'
sig_addr_cmd_state <= s_ac_relax;
else
sig_addr_cmd_state <= sig_ac_req;
end if;
if sig_doing_rd_count /= 0 then
sig_doing_rd <= (others => '1');
sig_doing_rd_count <= sig_doing_rd_count - 1;
else
sig_doing_rd <= (others => '0');
end if;
case sig_addr_cmd_state is
when s_ac_idle =>
sig_addr_cmd <= defaults(c_seq_addr_cmd_config);
when s_ac_relax =>
-- waits at least c_max_read_lat before returning to s_ac_idle state
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= c_max_read_lat;
else
if sig_count = 0 then
sig_addr_cmd_state <= s_ac_idle;
else
sig_count <= sig_count - 1;
end if;
end if;
when s_ac_read_mtp =>
-- reads 'more'-training pattern
-- issue read commands for proper addresses
-- set burst training pattern (mtp in this case) addresses
btp_addr_array <= set_btp_addr(current_mtp_almt);
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= c_bursts_per_btp - 1; -- counts number of bursts in a training pattern
else
sig_doing_rd <= (others => '1');
-- issue a read command every c_read_burst_t clock cycles
if sig_burst_count = 0 then
-- decide which read command to issue
for i in 0 to c_bursts_per_btp - 1 loop
if sig_count = i then
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
btp_addr_array(i), -- column address
2**current_cs, -- rank
c_cal_read_burst_len, -- burst length
false);
end if;
end loop;
-- Set next value of count
if sig_count = 0 then
sig_count <= c_bursts_per_btp - 1;
else
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_ac_read_poa_mtp =>
-- Postamble rdata/rdata_valid Activity:
--
--
-- (0) (1) (2)
-- ; ; ; ;
-- _________ __ ____________ _____________ _______ _________
-- \ / \ / \ \ \ / \ /
-- (a) rdata[0] 00000000 X 11 X 0000000000 / / 0000000000 X MTP X 00000000
-- _________/ \__/ \____________\ \____________/ \_______/ \_________
-- ; ; ; ;
-- ; ; ; ;
-- _________ / / _________
-- rdata_valid ____| |_____________\ \_____________| |__________
--
-- ;<- (b) ->;<------------(c)------------>; ;
-- ; ; ; ;
--
--
-- This block must issue reads and drive doing_rd to place the above pattern on
-- the rdata and rdata_valid ports. MTP will most likely come back corrupted but
-- the postamble block (poa_block) will make the necessary adjustments to improve
-- matters.
--
-- (a) Read zeros followed by two ones. The two will be at the end of a burst.
-- Assert rdata_valid only during the burst containing the ones.
-- (b) c_read_burst_t clock cycles.
-- (c) Must be greater than but NOT equal to maximum postamble latency clock
-- cycles. Another way: c_min = (max_poa_lat + 1) phy clock cycles. This
-- must also be long enough to allow the postamble block to respond to a
-- the seq_poa_lat_dec_1x signal, but this requirement is less stringent
-- than the first so that we can ignore it.
--
-- The find_poa_cycle_period function should return (b+c)/c_read_burst_t
-- rounded up to the next largest integer.
--
--
-- set burst training pattern (mtp in this case) addresses
btp_addr_array <= set_btp_addr(current_mtp_almt);
-- issue read commands for proper addresses
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= find_poa_cycle_period - 1; -- length of read patter in bursts.
elsif dgrb_ac_access_gnt = '1' then
-- only begin operation once dgrb_ac_access_gnt has been issued
-- otherwise rdata_valid may be asserted when rdasta is not
-- valid.
--
-- *** WARNING: BE SAFE. DON'T LET THIS HAPPEN TO YOU: ***
--
-- ; ; ; ; ; ;
-- ; _______ ; ; _______ ; ; _______
-- XXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX
-- addr/cmd XXXXXX READ XXXXXXXXXXX READ XXXXXXXXXXX READ XXXXXXXXXXX
-- XXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ; _______
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX / \
-- rdata XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX MTP X
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX \_______/
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _________ _________ _________
-- doing_rd ____| |_________| |_________| |__________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- __________________________________________________
-- ac_accesss_gnt ______________|
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _________ _________
-- rdata_valid __________________________________| |_________| |
-- ; ; ; ; ; ;
--
-- (0) (1) (2)
--
--
-- Cmmand and doing_rd issued at (0). The doing_rd signal enters the
-- rdata_valid pipe here so that it will return on rdata_valid with the
-- expected latency (at this point in calibration, rdata_valid and adv_rd_lat
-- should be properly calibrated). Unlike doing_rd, since ac_access_gnt is not
-- asserted the READ command at (0) is never actually issued. This results
-- in the situation at (2) where rdata is undefined yet rdata_valid indicates
-- valid data. The moral of this story is to wait for ac_access_gnt = '1'
-- before issuing commands when it is important that rdata_valid be accurate.
--
--
--
--
if sig_burst_count = 0 then
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
get_poa_burst_addr(sig_count, current_mtp_almt),-- column address
2**current_cs, -- rank
c_cal_read_burst_len, -- burst length
false);
-- Set doing_rd
if sig_count = 0 then
sig_doing_rd <= (others => '1');
sig_doing_rd_count <= c_read_burst_t - 1; -- Extend doing_rd pulse by this many phy_clk cycles.
end if;
-- Set next value of count
if sig_count = 0 then
sig_count <= find_poa_cycle_period - 1; -- read for one period then relax (no read) for same time period
else
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_ac_read_rdv =>
assert c_max_rdata_valid_lat mod c_read_burst_t = 0 report dgrb_report_prefix & "c_max_rdata_valid_lat must be a multiple of c_read_burst_t." severity failure;
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= c_rdv_ones_rd_clks - 1;
else
if sig_burst_count = 0 then
if sig_count = 0 then
-- expecting to read ZEROS
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous valid
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + C_CAL_OFS_ZEROS, -- column
2**current_cs, -- rank
c_cal_read_burst_len, -- burst length
false);
else
-- expecting to read ONES
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + C_CAL_OFS_ONES, -- column address
2**current_cs, -- rank
c_cal_read_burst_len, -- op length
false);
end if;
if sig_count = 0 then
sig_count <= c_rdv_ones_rd_clks - 1;
else
sig_count <= sig_count - 1;
end if;
end if;
if (sig_count = c_rdv_ones_rd_clks - 1 and sig_burst_count = 1) or
(sig_count = 0 and c_read_burst_t = 1) then
-- the last burst read- that was issued was supposed to read only zeros
-- a burst read command will be issued on the next clock cycle
--
-- A long (>= maximim rdata_valid latency) series of burst reads are
-- issued for ONES.
-- Into this stream a single burst read for ZEROs is issued. After
-- the ZERO read command is issued, rdata_valid needs to come back
-- high one clock cycle before the next read command (reading ONES
-- again) is issued. Since the rdata_valid is just a delayed
-- version of doing_rd, doing_rd needs to exhibit the same behaviour.
--
-- for FR (burst length 4): require that doing_rd high 1 clock cycle after cs_n is low
-- ____ ____ ____ ____ ____ ____ ____ ____ ____
-- clk ____| |____| |____| |____| |____| |____| |____| |____| |____|
--
-- ___ _______ _______ _______ _______
-- \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXX
-- addr XXXXXXXXXXX ONES XXXXXXXXXXX ONES XXXXXXXXXXX ZEROS XXXXXXXXXXX ONES XXXXX--> Repeat
-- ___/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXX
--
-- _________ _________ _________ _________ ____
-- cs_n ____| |_________| |_________| |_________| |_________|
--
-- _________
-- doing_rd ________________________________________________________________| |______________
--
--
-- for HR: require that doing_rd high in the same clock cycle as cs_n is low
--
sig_doing_rd(MEM_IF_DQS_WIDTH*(DWIDTH_RATIO/2-1)) <= '1';
end if;
end if;
when s_ac_read_wd_lat =>
-- continuously issues reads on the memory locations
-- containing write latency addr=[2*c_cal_burst_len - (3*c_cal_burst_len - 1)]
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
-- no initialization required here. Must still wait
-- a clock cycle before beginning operations so that
-- we are properly synchronized with
-- dimm_driving_dq_proc.
else
if sig_burst_count = 0 then
if sig_dimm_driving_dq = '1' then
sig_doing_rd <= (others => '1');
end if;
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_wd_lat, -- column
2**current_cs, -- rank
c_cal_read_burst_len,
false);
end if;
end if;
when others =>
report dgrb_report_prefix & "undefined state in addr_cmd_proc" severity error;
sig_addr_cmd_state <= s_ac_idle;
end case;
-- mask odt signal
for i in 0 to (DWIDTH_RATIO/2)-1 loop
sig_addr_cmd(i).odt <= odt_settings(current_cs).read;
end loop;
sig_addr_cmd_last_state <= sig_addr_cmd_state;
end if;
end process;
end block ac_block;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : data gatherer (write bias) [dgwb] block for the non-levelling
-- AFI PHY sequencer
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_record_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_addr_cmd_pkg.all;
--
entity ddr_ctrl_ip_phy_alt_mem_phy_dgwb is
generic (
-- Physical IF width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
DWIDTH_RATIO : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural; -- The sequencer outputs memory control signals of width num_ranks
MEM_IF_MEMTYPE : string;
ADV_LAT_WIDTH : natural;
MEM_IF_CAL_BANK : natural; -- Bank to which calibration data is written
-- Base column address to which calibration data is written.
-- Memory at MEM_IF_CAL_BASE_COL - MEM_IF_CAL_BASE_COL + C_CAL_DATA_LEN - 1
-- is assumed to contain the proper data.
MEM_IF_CAL_BASE_COL : natural
);
port (
-- CLK Reset
clk : in std_logic;
rst_n : in std_logic;
parameterisation_rec : in t_algm_paramaterisation;
-- Control interface :
dgwb_ctrl : out t_ctrl_stat;
ctrl_dgwb : in t_ctrl_command;
-- iRAM 'push' interface :
dgwb_iram : out t_iram_push;
iram_push_done : in std_logic;
-- Admin block req/gnt interface.
dgwb_ac_access_req : out std_logic;
dgwb_ac_access_gnt : in std_logic;
-- WDP interface
dgwb_dqs_burst : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
dgwb_wdata_valid : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
dgwb_wdata : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
dgwb_dm : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 downto 0);
dgwb_dqs : out std_logic_vector( DWIDTH_RATIO - 1 downto 0);
dgwb_wdp_ovride : out std_logic;
-- addr/cmd output for write commands.
dgwb_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
bypassed_rdata : in std_logic_vector(MEM_IF_DWIDTH-1 downto 0);
-- odt settings per chip select
odt_settings : in t_odt_array(0 to MEM_IF_NUM_RANKS-1)
);
end entity;
library work;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_constants_pkg.all;
--
architecture rtl of ddr_ctrl_ip_phy_alt_mem_phy_dgwb is
type t_dgwb_state is (
s_idle,
s_wait_admin,
s_write_btp, -- Writes bit-training pattern
s_write_ones, -- Writes ones
s_write_zeros, -- Writes zeros
s_write_mtp, -- Write more training patterns (requires read to check allignment)
s_write_01_pairs, -- Writes 01 pairs
s_write_1100_step,-- Write step function (half zeros, half ones)
s_write_0011_step,-- Write reversed step function (half ones, half zeros)
s_write_wlat, -- Writes the write latency into a memory address.
s_release_admin
);
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- a prefix for all report signals to identify phy and sequencer block
--
constant dgwb_report_prefix : string := "ddr_ctrl_ip_phy_alt_mem_phy_seq (dgwb) : ";
function dqs_pattern return std_logic_vector is
variable dqs : std_logic_vector( DWIDTH_RATIO - 1 downto 0);
begin
if DWIDTH_RATIO = 2 then
dqs := "10";
elsif DWIDTH_RATIO = 4 then
dqs := "1100";
else
report dgwb_report_prefix & "unsupported DWIDTH_RATIO in function dqs_pattern." severity failure;
end if;
return dqs;
end;
signal sig_addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal sig_dgwb_state : t_dgwb_state;
signal sig_dgwb_last_state : t_dgwb_state;
signal access_complete : std_logic;
signal generate_wdata : std_logic; -- for s_write_wlat only
-- current chip select being processed
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS-1;
begin
dgwb_ac <= sig_addr_cmd;
-- Set IRAM interface to defaults
dgwb_iram <= defaults;
-- Master state machine. Generates state transitions.
master_dgwb_state_block : if True generate
signal sig_ctrl_dgwb : t_ctrl_command; -- registers ctrl_dgwb input.
begin
-- generate the current_cs signal to track which cs accessed by PHY at any instance
current_cs_proc : process (clk, rst_n)
begin
if rst_n = '0' then
current_cs <= 0;
elsif rising_edge(clk) then
if sig_ctrl_dgwb.command_req = '1' then
current_cs <= sig_ctrl_dgwb.command_op.current_cs;
end if;
end if;
end process;
master_dgwb_state_proc : process(rst_n, clk)
begin
if rst_n = '0' then
sig_dgwb_state <= s_idle;
sig_dgwb_last_state <= s_idle;
sig_ctrl_dgwb <= defaults;
elsif rising_edge(clk) then
case sig_dgwb_state is
when s_idle =>
if sig_ctrl_dgwb.command_req = '1' then
if (curr_active_block(sig_ctrl_dgwb.command) = dgwb) then
sig_dgwb_state <= s_wait_admin;
end if;
end if;
when s_wait_admin =>
case sig_ctrl_dgwb.command is
when cmd_write_btp => sig_dgwb_state <= s_write_btp;
when cmd_write_mtp => sig_dgwb_state <= s_write_mtp;
when cmd_was => sig_dgwb_state <= s_write_wlat;
when others =>
report dgwb_report_prefix & "unknown command" severity error;
end case;
if dgwb_ac_access_gnt /= '1' then
sig_dgwb_state <= s_wait_admin;
end if;
when s_write_btp =>
sig_dgwb_state <= s_write_zeros;
when s_write_zeros =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_write_ones;
end if;
when s_write_ones =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_release_admin;
end if;
when s_write_mtp =>
sig_dgwb_state <= s_write_01_pairs;
when s_write_01_pairs =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_write_1100_step;
end if;
when s_write_1100_step =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_write_0011_step;
end if;
when s_write_0011_step =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_release_admin;
end if;
when s_write_wlat =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_release_admin;
end if;
when s_release_admin =>
if dgwb_ac_access_gnt = '0' then
sig_dgwb_state <= s_idle;
end if;
when others =>
report dgwb_report_prefix & "undefined state in addr_cmd_proc" severity error;
sig_dgwb_state <= s_idle;
end case;
sig_dgwb_last_state <= sig_dgwb_state;
sig_ctrl_dgwb <= ctrl_dgwb;
end if;
end process;
end generate;
-- Generates writes
ac_write_block : if True generate
constant C_BURST_T : natural := C_CAL_BURST_LEN / DWIDTH_RATIO; -- Number of phy-clock cycles per burst
constant C_MAX_WLAT : natural := 2**ADV_LAT_WIDTH-1; -- Maximum latency in clock cycles
constant C_MAX_COUNT : natural := C_MAX_WLAT + C_BURST_T + 4*12 - 1; -- up to 12 consecutive writes at 4 cycle intervals
-- The following function sets the width over which
-- write latency should be repeated on the dq bus
-- the default value is MEM_IF_DQ_PER_DQS
function set_wlat_dq_rep_width return natural is
begin
for i in 1 to MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS loop
if (i*MEM_IF_DQ_PER_DQS) >= ADV_LAT_WIDTH then
return i*MEM_IF_DQ_PER_DQS;
end if;
end loop;
report dgwb_report_prefix & "the specified maximum write latency cannot be fully represented in the given number of DQ pins" & LF &
"** NOTE: This may cause overflow when setting ctl_wlat signal" severity warning;
return MEM_IF_DQ_PER_DQS;
end function;
constant C_WLAT_DQ_REP_WIDTH : natural := set_wlat_dq_rep_width;
signal sig_count : natural range 0 to 2**8 - 1;
begin
ac_write_proc : process(rst_n, clk)
begin
if rst_n = '0' then
dgwb_wdp_ovride <= '0';
dgwb_dqs <= (others => '0');
dgwb_dm <= (others => '1');
dgwb_wdata <= (others => '0');
dgwb_dqs_burst <= (others => '0');
dgwb_wdata_valid <= (others => '0');
generate_wdata <= '0'; -- for s_write_wlat only
sig_count <= 0;
sig_addr_cmd <= int_pup_reset(c_seq_addr_cmd_config);
access_complete <= '0';
elsif rising_edge(clk) then
dgwb_wdp_ovride <= '0';
dgwb_dqs <= (others => '0');
dgwb_dm <= (others => '1');
dgwb_wdata <= (others => '0');
dgwb_dqs_burst <= (others => '0');
dgwb_wdata_valid <= (others => '0');
sig_addr_cmd <= deselect(c_seq_addr_cmd_config, sig_addr_cmd);
access_complete <= '0';
generate_wdata <= '0'; -- for s_write_wlat only
case sig_dgwb_state is
when s_idle =>
sig_addr_cmd <= defaults(c_seq_addr_cmd_config);
-- require ones in locations:
-- 1. c_cal_ofs_ones (8 locations)
-- 2. 2nd half of location c_cal_ofs_xF5 (4 locations)
when s_write_ones =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
-- Write ONES to DQ pins
dgwb_wdata <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_count <= 0;
else
-- ensure safe intervals for DDRx memory writes (min 4 mem clk cycles between writes for BC4 DDR3)
if sig_count = 0 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_ones, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 4 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_ones + 4, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 8 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5 + 4, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
end if;
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- require zeros in locations:
-- 1. c_cal_ofs_zeros (8 locations)
-- 2. 1st half of c_cal_ofs_x30_almt_0 (4 locations)
-- 3. 1st half of c_cal_ofs_x30_almt_1 (4 locations)
when s_write_zeros =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
-- Write ZEROS to DQ pins
dgwb_wdata <= (others => '0');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_count <= 0;
else
if sig_count = 0 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_zeros, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 4 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_zeros + 4, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 8 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 12 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
end if;
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- require 0101 pattern in locations:
-- 1. 1st half of location c_cal_ofs_xF5 (4 locations)
when s_write_01_pairs =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_count <= 0;
else
if sig_count = 0 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5, -- address
2**current_cs, -- rank
4, -- burst length
false); -- auto-precharge
end if;
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- Write 01 to pairs of memory addresses
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
if i mod 2 = 0 then
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
else
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
end if;
end loop;
-- require pattern "0011" (or "1100") in locations:
-- 1. 2nd half of c_cal_ofs_x30_almt_0 (4 locations)
when s_write_0011_step =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0 + 4, -- address
2**current_cs, -- rank
4, -- burst length
false); -- auto-precharge
sig_count <= 0;
else
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- Write 0011 step to column addresses. Note that
-- it cannot be determined which at this point. The
-- strategy is to write both alignments and see which
-- one is correct later on.
-- this calculation has 2 parts:
-- a) sig_count mod C_BURST_T is a timewise iterator of repetition of the pattern
-- b) i represents the temporal iterator of the pattern
-- it is required to sum a and b and switch the pattern between 0 and 1 every 2 locations in each dimension
-- Note: the same formulae is used below for the 1100 pattern
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
if ((sig_count mod C_BURST_T) + (i/2)) mod 2 = 0 then
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
else
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
end if;
end loop;
-- require pattern "1100" (or "0011") in locations:
-- 1. 2nd half of c_cal_ofs_x30_almt_1 (4 locations)
when s_write_1100_step =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1 + 4, -- address
2**current_cs, -- rank
4, -- burst length
false); -- auto-precharge
sig_count <= 0;
else
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- Write 1100 step to column addresses. Note that
-- it cannot be determined which at this point. The
-- strategy is to write both alignments and see which
-- one is correct later on.
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
if ((sig_count mod C_BURST_T) + (i/2)) mod 2 = 0 then
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
else
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
end if;
end loop;
when s_write_wlat =>
-- Effect:
-- *Writes the memory latency to an array formed
-- from memory addr=[2*C_CAL_BURST_LEN-(3*C_CAL_BURST_LEN-1)].
-- The write latency is written to pairs of addresses
-- across the given range.
--
-- Example
-- C_CAL_BURST_LEN = 4
-- addr 8 - 9 [WLAT] size = 2*MEM_IF_DWIDTH bits
-- addr 10 - 11 [WLAT] size = 2*MEM_IF_DWIDTH bits
--
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_wdata <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
if sig_dgwb_state /= sig_dgwb_last_state then
sig_addr_cmd <= write(c_seq_addr_cmd_config, -- A/C configuration
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_wd_lat, -- address
2**current_cs, -- rank
8, -- burst length (8 for DDR3 and 4 for DDR/DDR2)
false); -- auto-precharge
sig_count <= 0;
else
-- hold wdata_valid and wdata 2 clock cycles
-- 1 - because ac signal registered at top level of sequencer
-- 2 - because want time to dqs_burst edge which occurs 1 cycle earlier
-- than wdata_valid in an AFI compliant controller
generate_wdata <= '1';
end if;
if generate_wdata = '1' then
for i in 0 to dgwb_wdata'length/C_WLAT_DQ_REP_WIDTH - 1 loop
dgwb_wdata((i+1)*C_WLAT_DQ_REP_WIDTH - 1 downto i*C_WLAT_DQ_REP_WIDTH) <= std_logic_vector(to_unsigned(sig_count, C_WLAT_DQ_REP_WIDTH));
end loop;
-- delay by 1 clock cycle to account for 1 cycle discrepancy
-- between dqs_burst and wdata_valid
if sig_count = C_MAX_COUNT then
access_complete <= '1';
end if;
sig_count <= sig_count + 1;
end if;
when others =>
null;
end case;
-- mask odt signal
for i in 0 to (DWIDTH_RATIO/2)-1 loop
sig_addr_cmd(i).odt <= odt_settings(current_cs).write;
end loop;
end if;
end process;
end generate;
-- Handles handshaking for access to address/command
ac_handshake_proc : process(rst_n, clk)
begin
if rst_n = '0' then
dgwb_ctrl <= defaults;
dgwb_ac_access_req <= '0';
elsif rising_edge(clk) then
dgwb_ctrl <= defaults;
dgwb_ac_access_req <= '0';
if sig_dgwb_state /= s_idle and sig_dgwb_state /= s_release_admin then
dgwb_ac_access_req <= '1';
elsif sig_dgwb_state = s_idle or sig_dgwb_state = s_release_admin then
dgwb_ac_access_req <= '0';
else
report dgwb_report_prefix & "unexpected state in ac_handshake_proc so haven't requested access to address/command." severity warning;
end if;
if sig_dgwb_state = s_wait_admin and sig_dgwb_last_state = s_idle then
dgwb_ctrl.command_ack <= '1';
end if;
if sig_dgwb_state = s_idle and sig_dgwb_last_state = s_release_admin then
dgwb_ctrl.command_done <= '1';
end if;
end if;
end process;
end architecture rtl;
--
-- -----------------------------------------------------------------------------
-- Abstract : ctrl block for the non-levelling AFI PHY sequencer
-- This block is the central control unit for the sequencer. The method
-- of control is to issue commands (prefixed cmd_) to each of the other
-- sequencer blocks to execute. Each command corresponds to a stage of
-- the AFI PHY calibaration stage, and in turn each state represents a
-- command or a supplimentary flow control operation. In addition to
-- controlling the sequencer this block also checks for time out
-- conditions which occur when a different system block is faulty.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_record_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_iram_addr_pkg.all;
--
entity ddr_ctrl_ip_phy_alt_mem_phy_ctrl is
generic (
FAMILYGROUP_ID : natural;
MEM_IF_DLL_LOCK_COUNT : natural;
MEM_IF_MEMTYPE : string;
DWIDTH_RATIO : natural;
IRAM_ADDRESSING : t_base_hdr_addresses;
MEM_IF_CLK_PS : natural;
TRACKING_INTERVAL_IN_MS : natural;
MEM_IF_NUM_RANKS : natural;
MEM_IF_DQS_WIDTH : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural;
SIM_TIME_REDUCTIONS : natural; -- if 0 null, if 1 skip rrp, if 2 rrp for 1 dqs group and 1 cs
ACK_SEVERITY : severity_level
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- calibration status and redo request
ctl_init_success : out std_logic;
ctl_init_fail : out std_logic;
ctl_recalibrate_req : in std_logic; -- acts as a synchronous reset
-- status signals from iram
iram_status : in t_iram_stat;
iram_push_done : in std_logic;
-- standard control signal to all blocks
ctrl_op_rec : out t_ctrl_command;
-- standardised response from all system blocks
admin_ctrl : in t_ctrl_stat;
dgrb_ctrl : in t_ctrl_stat;
dgwb_ctrl : in t_ctrl_stat;
-- mmi to ctrl interface
mmi_ctrl : in t_mmi_ctrl;
ctrl_mmi : out t_ctrl_mmi;
-- byte lane select
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- signals to control the ac_nt setting
dgrb_ctrl_ac_nt_good : in std_logic;
int_ac_nt : out std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0); -- width of 1 for DWIDTH_RATIO =2,4 and 2 for DWIDTH_RATIO = 8
-- the following signals are reserved for future use
ctrl_iram_push : out t_ctrl_iram
);
end entity;
library work;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_constants_pkg.all;
--
architecture struct of ddr_ctrl_ip_phy_alt_mem_phy_ctrl is
-- a prefix for all report signals to identify phy and sequencer block
--
constant ctrl_report_prefix : string := "ddr_ctrl_ip_phy_alt_mem_phy_seq (ctrl) : ";
-- decoder to find the relevant disable bit (from mmi registers) for a given state
function find_dis_bit
(
state : t_master_sm_state;
mmi_ctrl : t_mmi_ctrl
) return std_logic is
variable v_dis : std_logic;
begin
case state is
when s_phy_initialise => v_dis := mmi_ctrl.hl_css.phy_initialise_dis;
when s_init_dram |
s_prog_cal_mr => v_dis := mmi_ctrl.hl_css.init_dram_dis;
when s_write_ihi => v_dis := mmi_ctrl.hl_css.write_ihi_dis;
when s_cal => v_dis := mmi_ctrl.hl_css.cal_dis;
when s_write_btp => v_dis := mmi_ctrl.hl_css.write_btp_dis;
when s_write_mtp => v_dis := mmi_ctrl.hl_css.write_mtp_dis;
when s_read_mtp => v_dis := mmi_ctrl.hl_css.read_mtp_dis;
when s_rrp_reset => v_dis := mmi_ctrl.hl_css.rrp_reset_dis;
when s_rrp_sweep => v_dis := mmi_ctrl.hl_css.rrp_sweep_dis;
when s_rrp_seek => v_dis := mmi_ctrl.hl_css.rrp_seek_dis;
when s_rdv => v_dis := mmi_ctrl.hl_css.rdv_dis;
when s_poa => v_dis := mmi_ctrl.hl_css.poa_dis;
when s_was => v_dis := mmi_ctrl.hl_css.was_dis;
when s_adv_rd_lat => v_dis := mmi_ctrl.hl_css.adv_rd_lat_dis;
when s_adv_wr_lat => v_dis := mmi_ctrl.hl_css.adv_wr_lat_dis;
when s_prep_customer_mr_setup => v_dis := mmi_ctrl.hl_css.prep_customer_mr_setup_dis;
when s_tracking_setup |
s_tracking => v_dis := mmi_ctrl.hl_css.tracking_dis;
when others => v_dis := '1'; -- default change stage
end case;
return v_dis;
end function;
-- decoder to find the relevant command for a given state
function find_cmd
(
state : t_master_sm_state
) return t_ctrl_cmd_id is
begin
case state is
when s_phy_initialise => return cmd_phy_initialise;
when s_init_dram => return cmd_init_dram;
when s_prog_cal_mr => return cmd_prog_cal_mr;
when s_write_ihi => return cmd_write_ihi;
when s_cal => return cmd_idle;
when s_write_btp => return cmd_write_btp;
when s_write_mtp => return cmd_write_mtp;
when s_read_mtp => return cmd_read_mtp;
when s_rrp_reset => return cmd_rrp_reset;
when s_rrp_sweep => return cmd_rrp_sweep;
when s_rrp_seek => return cmd_rrp_seek;
when s_rdv => return cmd_rdv;
when s_poa => return cmd_poa;
when s_was => return cmd_was;
when s_adv_rd_lat => return cmd_prep_adv_rd_lat;
when s_adv_wr_lat => return cmd_prep_adv_wr_lat;
when s_prep_customer_mr_setup => return cmd_prep_customer_mr_setup;
when s_tracking_setup |
s_tracking => return cmd_tr_due;
when others => return cmd_idle;
end case;
end function;
function mcs_rw_state -- returns true for multiple cs read/write states
(
state : t_master_sm_state
) return boolean is
begin
case state is
when s_write_btp | s_write_mtp | s_rrp_sweep =>
return true;
when s_reset | s_phy_initialise | s_init_dram | s_prog_cal_mr | s_write_ihi | s_cal |
s_read_mtp | s_rrp_reset | s_rrp_seek | s_rdv | s_poa |
s_was | s_adv_rd_lat | s_adv_wr_lat | s_prep_customer_mr_setup |
s_tracking_setup | s_tracking | s_operational | s_non_operational =>
return false;
when others =>
--
return false;
end case;
end function;
-- timing parameters
constant c_done_timeout_count : natural := 32768;
constant c_ack_timeout_count : natural := 1000;
constant c_ticks_per_ms : natural := 1000000000/(MEM_IF_CLK_PS*(DWIDTH_RATIO/2));
constant c_ticks_per_10us : natural := 10000000 /(MEM_IF_CLK_PS*(DWIDTH_RATIO/2));
-- local copy of calibration fail/success signals
signal int_ctl_init_fail : std_logic;
signal int_ctl_init_success : std_logic;
-- state machine (master for sequencer)
signal state : t_master_sm_state;
signal last_state : t_master_sm_state;
-- flow control signals for state machine
signal dis_state : std_logic; -- disable state
signal hold_state : std_logic; -- hold in state for 1 clock cycle
signal master_ctrl_op_rec : t_ctrl_command; -- master command record to all sequencer blocks
signal master_ctrl_iram_push : t_ctrl_iram; -- record indicating control details for pushes
signal dll_lock_counter : natural range MEM_IF_DLL_LOCK_COUNT - 1 downto 0; -- to wait for dll to lock
signal iram_init_complete : std_logic;
-- timeout signals to check if a block has 'hung'
signal timeout_counter : natural range c_done_timeout_count - 1 downto 0;
signal timeout_counter_stop : std_logic;
signal timeout_counter_enable : std_logic;
signal timeout_counter_clear : std_logic;
signal cmd_req_asserted : std_logic; -- a command has been issued
signal flag_ack_timeout : std_logic; -- req -> ack timed out
signal flag_done_timeout : std_logic; -- reg -> done timed out
signal waiting_for_ack : std_logic; -- command issued
signal cmd_ack_seen : std_logic; -- command completed
signal curr_ctrl : t_ctrl_stat; -- response for current active block
signal curr_cmd : t_ctrl_cmd_id;
-- store state information based on issued command
signal int_ctrl_prev_stage : t_ctrl_cmd_id;
signal int_ctrl_current_stage : t_ctrl_cmd_id;
-- multiple chip select counter
signal cs_counter : natural range 0 to MEM_IF_NUM_RANKS - 1;
signal reissue_cmd_req : std_logic; -- reissue command request for multiple cs
signal cal_cs_enabled : std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
-- signals to check the ac_nt setting
signal ac_nt_almts_checked : natural range 0 to DWIDTH_RATIO/2-1;
signal ac_nt : std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0);
-- track the mtp alignment setting
signal mtp_almts_checked : natural range 0 to 2;
signal mtp_correct_almt : natural range 0 to 1;
signal mtp_no_valid_almt : std_logic;
signal mtp_both_valid_almt : std_logic;
signal mtp_err : std_logic;
-- tracking timing
signal milisecond_tick_gen_count : natural range 0 to c_ticks_per_ms -1 := c_ticks_per_ms -1;
signal tracking_ms_counter : natural range 0 to 255;
signal tracking_update_due : std_logic;
begin -- architecture struct
-------------------------------------------------------------------------------
-- check if chip selects are enabled
-- this only effects reactive stages (i,e, those requiring memory reads)
-------------------------------------------------------------------------------
process(ctl_cal_byte_lanes)
variable v_cs_enabled : std_logic;
begin
for i in 0 to MEM_IF_NUM_RANKS - 1 loop
-- check if any bytes enabled
v_cs_enabled := '0';
for j in 0 to MEM_IF_DQS_WIDTH - 1 loop
v_cs_enabled := v_cs_enabled or ctl_cal_byte_lanes(i*MEM_IF_DQS_WIDTH + j);
end loop;
-- if any byte enabled set cs as enabled else not
cal_cs_enabled(i) <= v_cs_enabled;
-- sanity checking:
if i = 0 and v_cs_enabled = '0' then
report ctrl_report_prefix & " disabling of chip select 0 is unsupported by the sequencer," & LF &
"-> if this is your intention then please remap CS pins such that CS 0 is not disabled" severity failure;
end if;
end loop;
end process;
-- -----------------------------------------------------------------------------
-- dll lock counter
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
dll_lock_counter <= MEM_IF_DLL_LOCK_COUNT -1;
elsif rising_edge(clk) then
if ctl_recalibrate_req = '1' then
dll_lock_counter <= MEM_IF_DLL_LOCK_COUNT -1;
elsif dll_lock_counter /= 0 then
dll_lock_counter <= dll_lock_counter - 1;
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- timeout counter : this counter is used to determine if an ack, or done has
-- not been received within the expected number of clock cycles of a req being
-- asserted.
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
timeout_counter <= c_done_timeout_count - 1;
elsif rising_edge(clk) then
if timeout_counter_clear = '1' then
timeout_counter <= c_done_timeout_count - 1;
elsif timeout_counter_enable = '1' and state /= s_init_dram then
if timeout_counter /= 0 then
timeout_counter <= timeout_counter - 1;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- register current ctrl signal based on current command
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
curr_ctrl <= defaults;
curr_cmd <= cmd_idle;
elsif rising_edge(clk) then
case curr_active_block(curr_cmd) is
when admin => curr_ctrl <= admin_ctrl;
when dgrb => curr_ctrl <= dgrb_ctrl;
when dgwb => curr_ctrl <= dgwb_ctrl;
when others => curr_ctrl <= defaults;
end case;
curr_cmd <= master_ctrl_op_rec.command;
end if;
end process;
-- -----------------------------------------------------------------------------
-- generation of cmd_ack_seen
-- -----------------------------------------------------------------------------
process (curr_ctrl)
begin
cmd_ack_seen <= curr_ctrl.command_ack;
end process;
-------------------------------------------------------------------------------
-- generation of waiting_for_ack flag (to determine whether ack has timed out)
-------------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
waiting_for_ack <= '0';
elsif rising_edge(clk) then
if cmd_req_asserted = '1' then
waiting_for_ack <= '1';
elsif cmd_ack_seen = '1' then
waiting_for_ack <= '0';
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- generation of timeout flags
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
flag_ack_timeout <= '0';
flag_done_timeout <= '0';
elsif rising_edge(clk) then
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
flag_ack_timeout <= '0';
elsif timeout_counter = 0 and waiting_for_ack = '1' then
flag_ack_timeout <= '1';
end if;
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
flag_done_timeout <= '0';
elsif timeout_counter = 0 and
state /= s_rrp_sweep and -- rrp can take enough cycles to overflow counter so don't timeout
state /= s_init_dram and -- init_dram takes about 200 us, so don't timeout
timeout_counter_clear /= '1' then -- check if currently clearing the timeout (i.e. command_done asserted for s_init_dram or s_rrp_sweep)
flag_done_timeout <= '1';
end if;
end if;
end process;
-- generation of timeout_counter_stop
timeout_counter_stop <= curr_ctrl.command_done;
-- -----------------------------------------------------------------------------
-- generation of timeout_counter_enable and timeout_counter_clear
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
timeout_counter_enable <= '0';
timeout_counter_clear <= '0';
elsif rising_edge(clk) then
if cmd_req_asserted = '1' then
timeout_counter_enable <= '1';
timeout_counter_clear <= '0';
elsif timeout_counter_stop = '1'
or state = s_operational
or state = s_non_operational
or state = s_reset then
timeout_counter_enable <= '0';
timeout_counter_clear <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- assignment to ctrl_mmi record
-------------------------------------------------------------------------------
process (clk, rst_n)
variable v_ctrl_mmi : t_ctrl_mmi;
begin
if rst_n = '0' then
v_ctrl_mmi := defaults;
ctrl_mmi <= defaults;
int_ctrl_prev_stage <= cmd_idle;
int_ctrl_current_stage <= cmd_idle;
elsif rising_edge(clk) then
ctrl_mmi <= v_ctrl_mmi;
v_ctrl_mmi.ctrl_calibration_success := '0';
v_ctrl_mmi.ctrl_calibration_fail := '0';
if (curr_ctrl.command_ack = '1') then
case state is
when s_init_dram => v_ctrl_mmi.ctrl_cal_stage_ack_seen.init_dram := '1';
when s_write_btp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_btp := '1';
when s_write_mtp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_mtp := '1';
when s_read_mtp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.read_mtp := '1';
when s_rrp_reset => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_reset := '1';
when s_rrp_sweep => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_sweep := '1';
when s_rrp_seek => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_seek := '1';
when s_rdv => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rdv := '1';
when s_poa => v_ctrl_mmi.ctrl_cal_stage_ack_seen.poa := '1';
when s_was => v_ctrl_mmi.ctrl_cal_stage_ack_seen.was := '1';
when s_adv_rd_lat => v_ctrl_mmi.ctrl_cal_stage_ack_seen.adv_rd_lat := '1';
when s_adv_wr_lat => v_ctrl_mmi.ctrl_cal_stage_ack_seen.adv_wr_lat := '1';
when s_prep_customer_mr_setup => v_ctrl_mmi.ctrl_cal_stage_ack_seen.prep_customer_mr_setup := '1';
when s_tracking_setup |
s_tracking => v_ctrl_mmi.ctrl_cal_stage_ack_seen.tracking_setup := '1';
when others => null;
end case;
end if;
-- special 'ack' (actually finished) triggers for phy_initialise, writing iram header info and s_cal
if state = s_phy_initialise then
if iram_status.init_done = '1' and dll_lock_counter = 0 then
v_ctrl_mmi.ctrl_cal_stage_ack_seen.phy_initialise := '1';
end if;
end if;
if state = s_write_ihi then
if iram_push_done = '1' then
v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_ihi := '1';
end if;
end if;
if state = s_cal and find_dis_bit(state, mmi_ctrl) = '0' then -- if cal state and calibration not disabled acknowledge
v_ctrl_mmi.ctrl_cal_stage_ack_seen.cal := '1';
end if;
if state = s_operational then
v_ctrl_mmi.ctrl_calibration_success := '1';
end if;
if state = s_non_operational then
v_ctrl_mmi.ctrl_calibration_fail := '1';
end if;
if state /= s_non_operational then
v_ctrl_mmi.ctrl_current_active_block := master_ctrl_iram_push.active_block;
v_ctrl_mmi.ctrl_current_stage := master_ctrl_op_rec.command;
else
v_ctrl_mmi.ctrl_current_active_block := v_ctrl_mmi.ctrl_current_active_block;
v_ctrl_mmi.ctrl_current_stage := v_ctrl_mmi.ctrl_current_stage;
end if;
int_ctrl_prev_stage <= int_ctrl_current_stage;
int_ctrl_current_stage <= v_ctrl_mmi.ctrl_current_stage;
if int_ctrl_prev_stage /= int_ctrl_current_stage then
v_ctrl_mmi.ctrl_current_stage_done := '0';
else
if curr_ctrl.command_done = '1' then
v_ctrl_mmi.ctrl_current_stage_done := '1';
end if;
end if;
v_ctrl_mmi.master_state_r := last_state;
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
v_ctrl_mmi := defaults;
ctrl_mmi <= defaults;
end if;
-- assert error codes here
if curr_ctrl.command_err = '1' then
v_ctrl_mmi.ctrl_err_code := curr_ctrl.command_result;
elsif flag_ack_timeout = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(c_err_ctrl_ack_timeout, v_ctrl_mmi.ctrl_err_code'length));
elsif flag_done_timeout = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(c_err_ctrl_done_timeout, v_ctrl_mmi.ctrl_err_code'length));
elsif mtp_err = '1' then
if mtp_no_valid_almt = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(C_ERR_READ_MTP_NO_VALID_ALMT, v_ctrl_mmi.ctrl_err_code'length));
elsif mtp_both_valid_almt = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(C_ERR_READ_MTP_BOTH_ALMT_PASS, v_ctrl_mmi.ctrl_err_code'length));
end if;
end if;
end if;
end process;
-- check if iram finished init
process(iram_status)
begin
if GENERATE_ADDITIONAL_DBG_RTL = 0 then
iram_init_complete <= '1';
else
iram_init_complete <= iram_status.init_done;
end if;
end process;
-- -----------------------------------------------------------------------------
-- master state machine
-- (this controls the operation of the entire sequencer)
-- the states are summarised as follows:
-- s_reset
-- s_phy_initialise - wait for dll lock and init done flag from iram
-- s_init_dram, -- dram initialisation - reset sequence
-- s_prog_cal_mr, -- dram initialisation - programming mode registers (once per chip select)
-- s_write_ihi - write header information in iRAM
-- s_cal - check if calibration to be executed
-- s_write_btp - write burst training pattern
-- s_write_mtp - write more training pattern
-- s_rrp_reset - read resync phase setup - reset initial conditions
-- s_rrp_sweep - read resync phase setup - sweep phases per chip select
-- s_read_mtp - read training patterns to find correct alignment for 1100 burst
-- (this is a special case of s_rrp_seek with no resych phase setting)
-- s_rrp_seek - read resync phase setup - seek correct alignment
-- s_rdv - read data valid setup
-- s_poa - calibrate the postamble
-- s_was - write datapath setup (ac to write data timing)
-- s_adv_rd_lat - advertise read latency
-- s_adv_wr_lat - advertise write latency
-- s_tracking_setup - perform tracking (1st pass to setup mimic window)
-- s_prep_customer_mr_setup - apply user mode register settings (in admin block)
-- s_tracking - perform tracking (subsequent passes in user mode)
-- s_operational - calibration successful and in user mode
-- s_non_operational - calibration unsuccessful and in user mode
-- -----------------------------------------------------------------------------
process(clk, rst_n)
variable v_seen_ack : boolean;
variable v_dis : std_logic; -- disable bit
begin
if rst_n = '0' then
state <= s_reset;
last_state <= s_reset;
int_ctl_init_success <= '0';
int_ctl_init_fail <= '0';
v_seen_ack := false;
hold_state <= '0';
cs_counter <= 0;
mtp_almts_checked <= 0;
ac_nt <= (others => '1');
ac_nt_almts_checked <= 0;
reissue_cmd_req <= '0';
dis_state <= '0';
elsif rising_edge(clk) then
last_state <= state;
-- check if state_tx required
if curr_ctrl.command_ack = '1' then
v_seen_ack := true;
end if;
-- find disable bit for current state (do once to avoid exit mid-state)
if state /= last_state then
dis_state <= find_dis_bit(state, mmi_ctrl);
end if;
-- Set special conditions:
if state = s_reset or
state = s_operational or
state = s_non_operational then
dis_state <= '1';
end if;
-- override to ensure execution of next state logic
if (state = s_cal) then
dis_state <= '1';
end if;
-- if header writing in iram check finished
if (state = s_write_ihi) then
if iram_push_done = '1' or mmi_ctrl.hl_css.write_ihi_dis = '1' then
dis_state <= '1';
else
dis_state <= '0';
end if;
end if;
-- Special condition for initialisation
if (state = s_phy_initialise) then
if ((dll_lock_counter = 0) and (iram_init_complete = '1')) or
(mmi_ctrl.hl_css.phy_initialise_dis = '1') then
dis_state <= '1';
else
dis_state <= '0';
end if;
end if;
if dis_state = '1' then
v_seen_ack := false;
elsif curr_ctrl.command_done = '1' then
if v_seen_ack = false then
report ctrl_report_prefix & "have not seen ack but have seen command done from " & t_ctrl_active_block'image(curr_active_block(master_ctrl_op_rec.command)) & "_block in state " & t_master_sm_state'image(state) severity warning;
end if;
v_seen_ack := false;
end if;
-- default do not reissue command request
reissue_cmd_req <= '0';
if (hold_state = '1') then
hold_state <= '0';
else
if ((dis_state = '1') or
(curr_ctrl.command_done = '1') or
((cal_cs_enabled(cs_counter) = '0') and (mcs_rw_state(state) = True))) then -- current chip select is disabled and read/write
hold_state <= '1';
-- Only reset the below if making state change
int_ctl_init_success <= '0';
int_ctl_init_fail <= '0';
-- default chip select counter gets reset to zero
cs_counter <= 0;
case state is
when s_reset => state <= s_phy_initialise;
ac_nt <= (others => '1');
mtp_almts_checked <= 0;
ac_nt_almts_checked <= 0;
when s_phy_initialise => state <= s_init_dram;
when s_init_dram => state <= s_prog_cal_mr;
when s_prog_cal_mr => if cs_counter = MEM_IF_NUM_RANKS - 1 then
-- if no debug interface don't write iram header
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
state <= s_write_ihi;
else
state <= s_cal;
end if;
else
cs_counter <= cs_counter + 1;
reissue_cmd_req <= '1';
end if;
when s_write_ihi => state <= s_cal;
when s_cal => if mmi_ctrl.hl_css.cal_dis = '0' then
state <= s_write_btp;
else
state <= s_tracking_setup;
end if;
-- always enter s_cal before calibration so reset some variables here
mtp_almts_checked <= 0;
ac_nt_almts_checked <= 0;
when s_write_btp => if cs_counter = MEM_IF_NUM_RANKS-1 or
SIM_TIME_REDUCTIONS = 2 then
state <= s_write_mtp;
else
cs_counter <= cs_counter + 1;
-- only reissue command if current chip select enabled
if cal_cs_enabled(cs_counter + 1) = '1' then
reissue_cmd_req <= '1';
end if;
end if;
when s_write_mtp => if cs_counter = MEM_IF_NUM_RANKS - 1 or
SIM_TIME_REDUCTIONS = 2 then
if SIM_TIME_REDUCTIONS = 1 then
state <= s_rdv;
else
state <= s_rrp_reset;
end if;
else
cs_counter <= cs_counter + 1;
-- only reissue command if current chip select enabled
if cal_cs_enabled(cs_counter + 1) = '1' then
reissue_cmd_req <= '1';
end if;
end if;
when s_rrp_reset => state <= s_rrp_sweep;
when s_rrp_sweep => if cs_counter = MEM_IF_NUM_RANKS - 1 or
mtp_almts_checked /= 2 or
SIM_TIME_REDUCTIONS = 2 then
if mtp_almts_checked /= 2 then
state <= s_read_mtp;
else
state <= s_rrp_seek;
end if;
else
cs_counter <= cs_counter + 1;
-- only reissue command if current chip select enabled
if cal_cs_enabled(cs_counter + 1) = '1' then
reissue_cmd_req <= '1';
end if;
end if;
when s_read_mtp => if mtp_almts_checked /= 2 then
mtp_almts_checked <= mtp_almts_checked + 1;
end if;
state <= s_rrp_reset;
when s_rrp_seek => state <= s_rdv;
when s_rdv => state <= s_was;
when s_was => state <= s_adv_rd_lat;
when s_adv_rd_lat => state <= s_adv_wr_lat;
when s_adv_wr_lat => if dgrb_ctrl_ac_nt_good = '1' then
state <= s_poa;
else
if ac_nt_almts_checked = (DWIDTH_RATIO/2 - 1) then
state <= s_non_operational;
else
-- switch alignment and restart calibration
ac_nt <= std_logic_vector(unsigned(ac_nt) + 1);
ac_nt_almts_checked <= ac_nt_almts_checked + 1;
if SIM_TIME_REDUCTIONS = 1 then
state <= s_rdv;
else
state <= s_rrp_reset;
end if;
mtp_almts_checked <= 0;
end if;
end if;
when s_poa => state <= s_tracking_setup;
when s_tracking_setup => state <= s_prep_customer_mr_setup;
when s_prep_customer_mr_setup => if cs_counter = MEM_IF_NUM_RANKS - 1 then -- s_prep_customer_mr_setup is always performed over all cs
state <= s_operational;
else
cs_counter <= cs_counter + 1;
reissue_cmd_req <= '1';
end if;
when s_tracking => state <= s_operational;
int_ctl_init_success <= int_ctl_init_success;
int_ctl_init_fail <= int_ctl_init_fail;
when s_operational => int_ctl_init_success <= '1';
int_ctl_init_fail <= '0';
hold_state <= '0';
if tracking_update_due = '1' and mmi_ctrl.hl_css.tracking_dis = '0' then
state <= s_tracking;
hold_state <= '1';
end if;
when s_non_operational => int_ctl_init_success <= '0';
int_ctl_init_fail <= '1';
hold_state <= '0';
if last_state /= s_non_operational then -- print a warning on entering this state
report ctrl_report_prefix & "memory calibration has failed (output from ctrl block)" severity WARNING;
end if;
when others => state <= t_master_sm_state'succ(state);
end case;
end if;
end if;
if flag_done_timeout = '1' -- no done signal from current active block
or flag_ack_timeout = '1' -- or no ack signal from current active block
or curr_ctrl.command_err = '1' -- or an error from current active block
or mtp_err = '1' then -- or an error due to mtp alignment
state <= s_non_operational;
end if;
if mmi_ctrl.calibration_start = '1' then -- restart calibration process
state <= s_cal;
end if;
if ctl_recalibrate_req = '1' then -- restart all incl. initialisation
state <= s_reset;
end if;
end if;
end process;
-- generate output calibration fail/success signals
process(clk, rst_n)
begin
if rst_n = '0' then
ctl_init_fail <= '0';
ctl_init_success <= '0';
elsif rising_edge(clk) then
ctl_init_fail <= int_ctl_init_fail;
ctl_init_success <= int_ctl_init_success;
end if;
end process;
-- assign ac_nt to the output int_ac_nt
process(ac_nt)
begin
int_ac_nt <= ac_nt;
end process;
-- ------------------------------------------------------------------------------
-- find correct mtp_almt from returned data
-- ------------------------------------------------------------------------------
mtp_almt: block
signal dvw_size_a0 : natural range 0 to 255; -- maximum size of command result
signal dvw_size_a1 : natural range 0 to 255;
begin
process (clk, rst_n)
variable v_dvw_a0_small : boolean;
variable v_dvw_a1_small : boolean;
begin
if rst_n = '0' then
mtp_correct_almt <= 0;
dvw_size_a0 <= 0;
dvw_size_a1 <= 0;
mtp_no_valid_almt <= '0';
mtp_both_valid_almt <= '0';
mtp_err <= '0';
elsif rising_edge(clk) then
-- update the dvw sizes
if state = s_read_mtp then
if curr_ctrl.command_done = '1' then
if mtp_almts_checked = 0 then
dvw_size_a0 <= to_integer(unsigned(curr_ctrl.command_result));
else
dvw_size_a1 <= to_integer(unsigned(curr_ctrl.command_result));
end if;
end if;
end if;
-- check dvw size and set mtp almt
if dvw_size_a0 < dvw_size_a1 then
mtp_correct_almt <= 1;
else
mtp_correct_almt <= 0;
end if;
-- error conditions
if mtp_almts_checked = 2 and GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if finished alignment checking (and GENERATE_ADDITIONAL_DBG_RTL set)
-- perform size checks once per dvw
if dvw_size_a0 < 3 then
v_dvw_a0_small := true;
else
v_dvw_a0_small := false;
end if;
if dvw_size_a1 < 3 then
v_dvw_a1_small := true;
else
v_dvw_a1_small := false;
end if;
if v_dvw_a0_small = true and v_dvw_a1_small = true then
mtp_no_valid_almt <= '1';
mtp_err <= '1';
end if;
if v_dvw_a0_small = false and v_dvw_a1_small = false then
mtp_both_valid_almt <= '1';
mtp_err <= '1';
end if;
else
mtp_no_valid_almt <= '0';
mtp_both_valid_almt <= '0';
mtp_err <= '0';
end if;
end if;
end process;
end block;
-- ------------------------------------------------------------------------------
-- process to generate command outputs, based on state, last_state and mmi_ctrl.
-- asynchronously
-- ------------------------------------------------------------------------------
process (state, last_state, mmi_ctrl, reissue_cmd_req, cs_counter, mtp_almts_checked, mtp_correct_almt)
begin
master_ctrl_op_rec <= defaults;
master_ctrl_iram_push <= defaults;
case state is
-- special condition states
when s_reset | s_phy_initialise | s_cal =>
null;
when s_write_ihi =>
if mmi_ctrl.hl_css.write_ihi_dis = '0' then
master_ctrl_op_rec.command <= find_cmd(state);
if state /= last_state then
master_ctrl_op_rec.command_req <= '1';
end if;
end if;
when s_operational | s_non_operational =>
master_ctrl_op_rec.command <= find_cmd(state);
when others => -- default condition for most states
if find_dis_bit(state, mmi_ctrl) = '0' then
master_ctrl_op_rec.command <= find_cmd(state);
if state /= last_state or reissue_cmd_req = '1' then
master_ctrl_op_rec.command_req <= '1';
end if;
else
if state = last_state then -- safe state exit if state disabled mid-calibration
master_ctrl_op_rec.command <= find_cmd(state);
end if;
end if;
end case;
-- for multiple chip select commands assign operand to cs_counter
master_ctrl_op_rec.command_op <= defaults;
master_ctrl_op_rec.command_op.current_cs <= cs_counter;
if state = s_rrp_sweep or state = s_read_mtp or state = s_poa then
if mtp_almts_checked /= 2 or SIM_TIME_REDUCTIONS = 2 then
master_ctrl_op_rec.command_op.single_bit <= '1';
end if;
if mtp_almts_checked /= 2 then
master_ctrl_op_rec.command_op.mtp_almt <= mtp_almts_checked;
else
master_ctrl_op_rec.command_op.mtp_almt <= mtp_correct_almt;
end if;
end if;
-- set write mode and packing mode for iram
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
case state is
when s_rrp_sweep =>
master_ctrl_iram_push.write_mode <= overwrite_ram;
master_ctrl_iram_push.packing_mode <= dq_bitwise;
when s_rrp_seek |
s_read_mtp =>
master_ctrl_iram_push.write_mode <= overwrite_ram;
master_ctrl_iram_push.packing_mode <= dq_wordwise;
when others =>
null;
end case;
end if;
-- set current active block
master_ctrl_iram_push.active_block <= curr_active_block(find_cmd(state));
end process;
-- some concurc_read_burst_trent assignments to outputs
process (master_ctrl_iram_push, master_ctrl_op_rec)
begin
ctrl_iram_push <= master_ctrl_iram_push;
ctrl_op_rec <= master_ctrl_op_rec;
cmd_req_asserted <= master_ctrl_op_rec.command_req;
end process;
-- -----------------------------------------------------------------------------
-- tracking interval counter
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
milisecond_tick_gen_count <= c_ticks_per_ms -1;
tracking_ms_counter <= 0;
tracking_update_due <= '0';
elsif rising_edge(clk) then
if state = s_operational and last_state/= s_operational then
if mmi_ctrl.tracking_orvd_to_10ms = '1' then
milisecond_tick_gen_count <= c_ticks_per_10us -1;
else
milisecond_tick_gen_count <= c_ticks_per_ms -1;
end if;
tracking_ms_counter <= mmi_ctrl.tracking_period_ms;
elsif state = s_operational then
if milisecond_tick_gen_count = 0 and tracking_update_due /= '1' then
if tracking_ms_counter = 0 then
tracking_update_due <= '1';
else
tracking_ms_counter <= tracking_ms_counter -1;
end if;
if mmi_ctrl.tracking_orvd_to_10ms = '1' then
milisecond_tick_gen_count <= c_ticks_per_10us -1;
else
milisecond_tick_gen_count <= c_ticks_per_ms -1;
end if;
elsif milisecond_tick_gen_count /= 0 then
milisecond_tick_gen_count <= milisecond_tick_gen_count -1;
end if;
else
tracking_update_due <= '0';
end if;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : top level for the non-levelling AFI PHY sequencer
-- The top level instances the sub-blocks of the AFI PHY
-- sequencer. In addition a number of multiplexing and high-
-- level control operations are performed. This includes the
-- multiplexing and generation of control signals for: the
-- address and command DRAM interface and pll, oct and datapath
-- latency control signals.
-- -----------------------------------------------------------------------------
--altera message_off 10036
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
entity ddr_ctrl_ip_phy_alt_mem_phy_seq IS
generic (
-- choice of FPGA device family and DRAM type
FAMILY : string;
MEM_IF_MEMTYPE : string;
SPEED_GRADE : string;
FAMILYGROUP_ID : natural;
-- physical interface width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
DWIDTH_RATIO : natural;
CLOCK_INDEX_WIDTH : natural;
MEM_IF_CLK_PAIR_COUNT : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_CS_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
MEM_IF_RANKS_PER_SLOT : natural;
ADV_LAT_WIDTH : natural;
RESYNCHRONISE_AVALON_DBG : natural; -- 0 = false, 1 = true
AV_IF_ADDR_WIDTH : natural;
-- Not used for non-levelled seq
CHIP_OR_DIMM : string;
RDIMM_CONFIG_BITS : string;
-- setup / algorithm information
NOM_DQS_PHASE_SETTING : natural;
SCAN_CLK_DIVIDE_BY : natural;
RDP_ADDR_WIDTH : natural;
PLL_STEPS_PER_CYCLE : natural;
IOE_PHASES_PER_TCK : natural;
IOE_DELAYS_PER_PHS : natural;
MEM_IF_CLK_PS : natural;
WRITE_DESKEW_T10 : natural;
WRITE_DESKEW_HC_T10 : natural;
WRITE_DESKEW_T9NI : natural;
WRITE_DESKEW_HC_T9NI : natural;
WRITE_DESKEW_T9I : natural;
WRITE_DESKEW_HC_T9I : natural;
WRITE_DESKEW_RANGE : natural;
-- initial mode register settings
PHY_DEF_MR_1ST : natural;
PHY_DEF_MR_2ND : natural;
PHY_DEF_MR_3RD : natural;
PHY_DEF_MR_4TH : natural;
MEM_IF_DQSN_EN : natural; -- default off for Cyclone-III
MEM_IF_DQS_CAPTURE_EN : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural; -- 1 signals to include iram and mmi blocks and 0 not to include
SINGLE_DQS_DELAY_CONTROL_CODE : natural; -- reserved for future use
PRESET_RLAT : natural; -- reserved for future use
EN_OCT : natural; -- Does the sequencer use OCT during calibration.
OCT_LAT_WIDTH : natural;
SIM_TIME_REDUCTIONS : natural; -- if 0 null, if 2 rrp for 1 dqs group and 1 cs
FORCE_HC : natural; -- Use to force HardCopy in simulation.
CAPABILITIES : natural; -- advertise capabilities i.e. which ctrl block states to execute (default all on)
TINIT_TCK : natural;
TINIT_RST : natural;
GENERATE_TRACKING_PHASE_STORE : natural; -- reserved for future use
IP_BUILDNUM : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- calibration status and prompt
ctl_init_success : out std_logic;
ctl_init_fail : out std_logic;
ctl_init_warning : out std_logic; -- unused
ctl_recalibrate_req : in std_logic;
-- the following two signals are reserved for future use
mem_ac_swapped_ranks : in std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- pll reconfiguration
seq_pll_inc_dec_n : out std_logic;
seq_pll_start_reconfig : out std_logic;
seq_pll_select : out std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
seq_pll_phs_shift_busy : in std_logic;
pll_resync_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select resync clock
pll_measure_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select mimic/measure clock
-- scanchain associated signals (reserved for future use)
seq_scan_clk : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_dqs_config : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_update : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_din : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_ck : out std_logic_vector(MEM_IF_CLK_PAIR_COUNT - 1 downto 0);
seq_scan_enable_dqs : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_dqsn : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_dq : out std_logic_vector(MEM_IF_DWIDTH - 1 downto 0);
seq_scan_enable_dm : out std_logic_vector(MEM_IF_DM_WIDTH - 1 downto 0);
hr_rsc_clk : in std_logic;
-- address / command interface (note these are mapped internally to the seq_ac record)
seq_ac_addr : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_ADDR_WIDTH - 1 downto 0);
seq_ac_ba : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_BANKADDR_WIDTH - 1 downto 0);
seq_ac_cas_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_ras_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_we_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_cke : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
seq_ac_cs_n : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
seq_ac_odt : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
seq_ac_rst_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_sel : out std_logic;
seq_mem_clk_disable : out std_logic;
-- additional datapath latency (reserved for future use)
seq_ac_add_1t_ac_lat_internal : out std_logic;
seq_ac_add_1t_odt_lat_internal : out std_logic;
seq_ac_add_2t : out std_logic;
-- read datapath interface
seq_rdp_reset_req_n : out std_logic;
seq_rdp_inc_read_lat_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_rdp_dec_read_lat_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
rdata : in std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
-- read data valid (associated signals) interface
seq_rdv_doing_rd : out std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
rdata_valid : in std_logic_vector( DWIDTH_RATIO/2 - 1 downto 0);
seq_rdata_valid_lat_inc : out std_logic;
seq_rdata_valid_lat_dec : out std_logic;
seq_ctl_rlat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- postamble interface (unused for Cyclone-III)
seq_poa_lat_dec_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_poa_lat_inc_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_poa_protection_override_1x : out std_logic;
-- OCT path control
seq_oct_oct_delay : out std_logic_vector(OCT_LAT_WIDTH - 1 downto 0);
seq_oct_oct_extend : out std_logic_vector(OCT_LAT_WIDTH - 1 downto 0);
seq_oct_value : out std_logic;
-- write data path interface
seq_wdp_dqs_burst : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
seq_wdp_wdata_valid : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
seq_wdp_wdata : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
seq_wdp_dm : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 downto 0);
seq_wdp_dqs : out std_logic_vector( DWIDTH_RATIO - 1 downto 0);
seq_wdp_ovride : out std_logic;
seq_dqs_add_2t_delay : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_ctl_wlat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- mimic path interface
seq_mmc_start : out std_logic;
mmc_seq_done : in std_logic;
mmc_seq_value : in std_logic;
-- parity signals (not used for non-levelled PHY)
mem_err_out_n : in std_logic;
parity_error_n : out std_logic;
--synchronous Avalon debug interface (internally re-synchronised to input clock (a generic option))
dbg_seq_clk : in std_logic;
dbg_seq_rst_n : in std_logic;
dbg_seq_addr : in std_logic_vector(AV_IF_ADDR_WIDTH - 1 downto 0);
dbg_seq_wr : in std_logic;
dbg_seq_rd : in std_logic;
dbg_seq_cs : in std_logic;
dbg_seq_wr_data : in std_logic_vector(31 downto 0);
seq_dbg_rd_data : out std_logic_vector(31 downto 0);
seq_dbg_waitrequest : out std_logic
);
end entity;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_record_pkg.all;
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
-- registers for the mmi status registers and functions/procedures applied to the registers
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_regs_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_constants_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_iram_addr_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_addr_cmd_pkg.all;
-- Individually include each of library files for the sub-blocks of the sequencer:
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_admin;
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_mmi;
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_iram;
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_dgrb;
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_dgwb;
--
use work.ddr_ctrl_ip_phy_alt_mem_phy_ctrl;
--
architecture struct of ddr_ctrl_ip_phy_alt_mem_phy_seq IS
attribute altera_attribute : string;
attribute altera_attribute of struct : architecture is "-name MESSAGE_DISABLE 18010";
-- debug signals (similar to those seen in the Quartus v8.0 DDR/DDR2 sequencer)
signal rsu_multiple_valid_latencies_err : std_logic; -- true if >2 valid latency values are detected
signal rsu_grt_one_dvw_err : std_logic; -- true if >1 data valid window is detected
signal rsu_no_dvw_err : std_logic; -- true if no data valid window is detected
signal rsu_codvw_phase : std_logic_vector(11 downto 0); -- set to the phase of the DVW detected if calibration is successful
signal rsu_codvw_size : std_logic_vector(11 downto 0); -- set to the phase of the DVW detected if calibration is successful
signal rsu_read_latency : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0); -- set to the correct read latency if calibration is successful
-- outputs from the dgrb to generate the above rsu_codvw_* signals and report status to the mmi
signal dgrb_mmi : t_dgrb_mmi;
-- admin to mmi interface
signal regs_admin_ctrl_rec : t_admin_ctrl; -- mmi register settings information
signal admin_regs_status_rec : t_admin_stat; -- admin status information
-- odt enable from the admin block based on mr settings
signal enable_odt : std_logic;
-- iram status information (sent to the ctrl block)
signal iram_status : t_iram_stat;
-- dgrb iram write interface
signal dgrb_iram : t_iram_push;
-- ctrl to iram interface
signal ctrl_idib_top : natural; -- current write location in the iram
signal ctrl_active_block : t_ctrl_active_block;
signal ctrl_iram_push : t_ctrl_iram;
signal iram_push_done : std_logic;
signal ctrl_iram_ihi_write : std_logic;
-- local copies of calibration status
signal ctl_init_success_int : std_logic;
signal ctl_init_fail_int : std_logic;
-- refresh period failure flag
signal trefi_failure : std_logic;
-- unified ctrl signal broadcast to all blocks from the ctrl block
signal ctrl_broadcast : t_ctrl_command;
-- standardised status report per block to control block
signal admin_ctrl : t_ctrl_stat;
signal dgwb_ctrl : t_ctrl_stat;
signal dgrb_ctrl : t_ctrl_stat;
-- mmi and ctrl block interface
signal mmi_ctrl : t_mmi_ctrl;
signal ctrl_mmi : t_ctrl_mmi;
-- write datapath override signals
signal dgwb_wdp_override : std_logic;
signal dgrb_wdp_override : std_logic;
-- address/command access request and grant between the dgrb/dgwb blocks and the admin block
signal dgb_ac_access_gnt : std_logic;
signal dgb_ac_access_gnt_r : std_logic;
signal dgb_ac_access_req : std_logic;
signal dgwb_ac_access_req : std_logic;
signal dgrb_ac_access_req : std_logic;
-- per block address/command record (multiplexed in this entity)
signal admin_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal dgwb_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal dgrb_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
-- doing read signal
signal seq_rdv_doing_rd_int : std_logic_vector(seq_rdv_doing_rd'range);
-- local copy of interface to inc/dec latency on rdata_valid and postamble
signal seq_rdata_valid_lat_dec_int : std_logic;
signal seq_rdata_valid_lat_inc_int : std_logic;
signal seq_poa_lat_inc_1x_int : std_logic_vector(MEM_IF_DQS_WIDTH -1 downto 0);
signal seq_poa_lat_dec_1x_int : std_logic_vector(MEM_IF_DQS_WIDTH -1 downto 0);
-- local copy of write/read latency
signal seq_ctl_wlat_int : std_logic_vector(seq_ctl_wlat'range);
signal seq_ctl_rlat_int : std_logic_vector(seq_ctl_rlat'range);
-- parameterisation of dgrb / dgwb / admin blocks from mmi register settings
signal parameterisation_rec : t_algm_paramaterisation;
-- PLL reconfig
signal seq_pll_phs_shift_busy_r : std_logic;
signal seq_pll_phs_shift_busy_ccd : std_logic;
signal dgrb_pll_inc_dec_n : std_logic;
signal dgrb_pll_start_reconfig : std_logic;
signal dgrb_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
signal dgrb_phs_shft_busy : std_logic;
signal mmi_pll_inc_dec_n : std_logic;
signal mmi_pll_start_reconfig : std_logic;
signal mmi_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
signal pll_mmi : t_pll_mmi;
signal mmi_pll : t_mmi_pll_reconfig;
-- address and command 1t setting (unused for Full Rate)
signal int_ac_nt : std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0);
signal dgrb_ctrl_ac_nt_good : std_logic;
-- the following signals are reserved for future use
signal ctl_cal_byte_lanes_r : std_logic_vector(ctl_cal_byte_lanes'range);
signal mmi_setup : t_ctrl_cmd_id;
signal dgwb_iram : t_iram_push;
-- track number of poa / rdv adjustments (reporting only)
signal poa_adjustments : natural;
signal rdv_adjustments : natural;
-- convert input generics from natural to std_logic_vector
constant c_phy_def_mr_1st_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_1ST, 16));
constant c_phy_def_mr_2nd_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_2ND, 16));
constant c_phy_def_mr_3rd_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_3RD, 16));
constant c_phy_def_mr_4th_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_4TH, 16));
-- overrride on capabilities to speed up simulation time
function capabilities_override(capabilities : natural;
sim_time_reductions : natural) return natural is
begin
if sim_time_reductions = 1 then
return 2**c_hl_css_reg_cal_dis_bit; -- disable calibration completely
else
return capabilities;
end if;
end function;
-- set sequencer capabilities
constant c_capabilities_override : natural := capabilities_override(CAPABILITIES, SIM_TIME_REDUCTIONS);
constant c_capabilities : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(c_capabilities_override,32));
-- setup for address/command interface
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- setup for odt signals
-- odt setting as implemented in the altera high-performance controller for ddrx memories
constant c_odt_settings : t_odt_array(0 to MEM_IF_NUM_RANKS-1) := set_odt_values(MEM_IF_NUM_RANKS, MEM_IF_RANKS_PER_SLOT, MEM_IF_MEMTYPE);
-- a prefix for all report signals to identify phy and sequencer block
--
constant seq_report_prefix : string := "ddr_ctrl_ip_phy_alt_mem_phy_seq (top) : ";
-- setup iram configuration
constant c_iram_addresses : t_base_hdr_addresses := calc_iram_addresses(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_NUM_RANKS, MEM_IF_DQS_CAPTURE_EN);
constant c_int_iram_awidth : natural := c_iram_addresses.required_addr_bits;
constant c_preset_cal_setup : t_preset_cal := setup_instant_on(SIM_TIME_REDUCTIONS, FAMILYGROUP_ID, MEM_IF_MEMTYPE, DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, c_phy_def_mr_1st_sl_vector, c_phy_def_mr_2nd_sl_vector, c_phy_def_mr_3rd_sl_vector);
constant c_preset_codvw_phase : natural := c_preset_cal_setup.codvw_phase;
constant c_preset_codvw_size : natural := c_preset_cal_setup.codvw_size;
constant c_tracking_interval_in_ms : natural := 128;
constant c_mem_if_cal_bank : natural := 0; -- location to calibrate to
constant c_mem_if_cal_base_col : natural := 0; -- default all zeros
constant c_mem_if_cal_base_row : natural := 0;
constant c_non_op_eval_md : string := "PIN_FINDER"; -- non_operational evaluation mode (used when GENERATE_ADDITIONAL_DBG_RTL = 1)
begin -- architecture struct
-- ---------------------------------------------------------------
-- tie off unused signals to default values
-- ---------------------------------------------------------------
-- scan chain associated signals
seq_scan_clk <= (others => '0');
seq_scan_enable_dqs_config <= (others => '0');
seq_scan_update <= (others => '0');
seq_scan_din <= (others => '0');
seq_scan_enable_ck <= (others => '0');
seq_scan_enable_dqs <= (others => '0');
seq_scan_enable_dqsn <= (others => '0');
seq_scan_enable_dq <= (others => '0');
seq_scan_enable_dm <= (others => '0');
seq_dqs_add_2t_delay <= (others => '0');
seq_rdp_inc_read_lat_1x <= (others => '0');
seq_rdp_dec_read_lat_1x <= (others => '0');
-- warning flag (not used in non-levelled sequencer)
ctl_init_warning <= '0';
-- parity error flag (not used in non-levelled sequencer)
parity_error_n <= '1';
--
admin: entity ddr_ctrl_ip_phy_alt_mem_phy_admin
generic map
(
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
DWIDTH_RATIO => DWIDTH_RATIO,
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
MEM_IF_CLK_PAIR_COUNT => MEM_IF_CLK_PAIR_COUNT,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
MEM_IF_DQSN_EN => MEM_IF_DQSN_EN,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
MEM_IF_CAL_BANK => c_mem_if_cal_bank,
MEM_IF_CAL_BASE_ROW => c_mem_if_cal_base_row,
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
NON_OP_EVAL_MD => c_non_op_eval_md,
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
TINIT_TCK => TINIT_TCK,
TINIT_RST => TINIT_RST
)
port map
(
clk => clk,
rst_n => rst_n,
mem_ac_swapped_ranks => mem_ac_swapped_ranks,
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
seq_ac => admin_ac,
seq_ac_sel => seq_ac_sel,
enable_odt => enable_odt,
regs_admin_ctrl_rec => regs_admin_ctrl_rec,
admin_regs_status_rec => admin_regs_status_rec,
trefi_failure => trefi_failure,
ctrl_admin => ctrl_broadcast,
admin_ctrl => admin_ctrl,
ac_access_req => dgb_ac_access_req,
ac_access_gnt => dgb_ac_access_gnt,
cal_fail => ctl_init_fail_int,
cal_success => ctl_init_success_int,
ctl_recalibrate_req => ctl_recalibrate_req
);
-- selectively include the debug i/f (iram and mmi blocks)
with_debug_if : if GENERATE_ADDITIONAL_DBG_RTL = 1 generate
signal mmi_iram : t_iram_ctrl;
signal mmi_iram_enable_writes : std_logic;
signal rrp_mem_loc : natural range 0 to 2 ** c_int_iram_awidth - 1;
signal command_req_r : std_logic;
signal ctrl_broadcast_r : t_ctrl_command;
begin
-- register ctrl_broadcast locally
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_broadcast_r <= defaults;
elsif rising_edge(clk) then
ctrl_broadcast_r <= ctrl_broadcast;
end if;
end process;
--
mmi : entity ddr_ctrl_ip_phy_alt_mem_phy_mmi
generic map (
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
DWIDTH_RATIO => DWIDTH_RATIO,
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
MEM_IF_CLK_PAIR_COUNT => MEM_IF_CLK_PAIR_COUNT,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_DQS_CAPTURE => MEM_IF_DQS_CAPTURE_EN,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
RESYNCHRONISE_AVALON_DBG => RESYNCHRONISE_AVALON_DBG,
AV_IF_ADDR_WIDTH => AV_IF_ADDR_WIDTH,
NOM_DQS_PHASE_SETTING => NOM_DQS_PHASE_SETTING,
SCAN_CLK_DIVIDE_BY => SCAN_CLK_DIVIDE_BY,
RDP_ADDR_WIDTH => RDP_ADDR_WIDTH,
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
IOE_PHASES_PER_TCK => IOE_PHASES_PER_TCK,
IOE_DELAYS_PER_PHS => IOE_DELAYS_PER_PHS,
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
PHY_DEF_MR_1ST => c_phy_def_mr_1st_sl_vector,
PHY_DEF_MR_2ND => c_phy_def_mr_2nd_sl_vector,
PHY_DEF_MR_3RD => c_phy_def_mr_3rd_sl_vector,
PHY_DEF_MR_4TH => c_phy_def_mr_4th_sl_vector,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
PRESET_RLAT => PRESET_RLAT,
CAPABILITIES => c_capabilities_override,
USE_IRAM => '1', -- always use iram (generic is rfu)
IRAM_AWIDTH => c_int_iram_awidth,
TRACKING_INTERVAL_IN_MS => c_tracking_interval_in_ms,
READ_LAT_WIDTH => ADV_LAT_WIDTH
)
port map(
clk => clk,
rst_n => rst_n,
dbg_seq_clk => dbg_seq_clk,
dbg_seq_rst_n => dbg_seq_rst_n,
dbg_seq_addr => dbg_seq_addr,
dbg_seq_wr => dbg_seq_wr,
dbg_seq_rd => dbg_seq_rd,
dbg_seq_cs => dbg_seq_cs,
dbg_seq_wr_data => dbg_seq_wr_data,
seq_dbg_rd_data => seq_dbg_rd_data,
seq_dbg_waitrequest => seq_dbg_waitrequest,
regs_admin_ctrl => regs_admin_ctrl_rec,
admin_regs_status => admin_regs_status_rec,
mmi_iram => mmi_iram,
mmi_iram_enable_writes => mmi_iram_enable_writes,
iram_status => iram_status,
mmi_ctrl => mmi_ctrl,
ctrl_mmi => ctrl_mmi,
int_ac_1t => int_ac_nt(0),
invert_ac_1t => open,
trefi_failure => trefi_failure,
parameterisation_rec => parameterisation_rec,
pll_mmi => pll_mmi,
mmi_pll => mmi_pll,
dgrb_mmi => dgrb_mmi
);
--
iram : entity ddr_ctrl_ip_phy_alt_mem_phy_iram
generic map(
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
FAMILYGROUP_ID => FAMILYGROUP_ID,
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
IRAM_AWIDTH => c_int_iram_awidth,
REFRESH_COUNT_INIT => 12,
PRESET_RLAT => PRESET_RLAT,
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
CAPABILITIES => c_capabilities_override,
IP_BUILDNUM => IP_BUILDNUM
)
port map(
clk => clk,
rst_n => rst_n,
mmi_iram => mmi_iram,
mmi_iram_enable_writes => mmi_iram_enable_writes,
iram_status => iram_status,
iram_push_done => iram_push_done,
ctrl_iram => ctrl_broadcast_r,
dgrb_iram => dgrb_iram,
admin_regs_status_rec => admin_regs_status_rec,
ctrl_idib_top => ctrl_idib_top,
ctrl_iram_push => ctrl_iram_push,
dgwb_iram => dgwb_iram
);
-- calculate where current data should go in the iram
process (clk, rst_n)
variable v_words_req : natural range 0 to 2 * MEM_IF_DWIDTH * PLL_STEPS_PER_CYCLE * DWIDTH_RATIO - 1; -- how many words are required
begin
if rst_n = '0' then
ctrl_idib_top <= 0;
command_req_r <= '0';
rrp_mem_loc <= 0;
elsif rising_edge(clk) then
if command_req_r = '0' and ctrl_broadcast_r.command_req = '1' then -- execute once on each command_req assertion
-- default a 'safe location'
ctrl_idib_top <= c_iram_addresses.safe_dummy;
case ctrl_broadcast_r.command is
when cmd_write_ihi => -- reset pointers
rrp_mem_loc <= c_iram_addresses.rrp;
ctrl_idib_top <= 0; -- write header to zero location always
when cmd_rrp_sweep =>
-- add previous space requirement onto the current address
ctrl_idib_top <= rrp_mem_loc;
-- add the current space requirement to v_rrp_mem_loc
-- there are (DWIDTH_RATIO/2) * PLL_STEPS_PER_CYCLE phases swept packed into 32 bit words per pin
-- note: special case for single_bit calibration stages (e.g. read_mtp alignment)
if ctrl_broadcast_r.command_op.single_bit = '1' then
v_words_req := iram_wd_for_one_pin_rrp(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE_EN);
else
v_words_req := iram_wd_for_full_rrp(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE_EN);
end if;
v_words_req := v_words_req + 2; -- add 1 word location for header / footer information
rrp_mem_loc <= rrp_mem_loc + v_words_req;
when cmd_rrp_seek |
cmd_read_mtp =>
-- add previous space requirement onto the current address
ctrl_idib_top <= rrp_mem_loc;
-- require 3 words - header, result and footer
v_words_req := 3;
rrp_mem_loc <= rrp_mem_loc + v_words_req;
when others =>
null;
end case;
end if;
command_req_r <= ctrl_broadcast_r.command_req;
-- if recalibration request then reset iram address
if ctl_recalibrate_req = '1' or mmi_ctrl.calibration_start = '1' then
rrp_mem_loc <= c_iram_addresses.rrp;
end if;
end if;
end process;
end generate; -- with debug interface
-- if no debug interface (iram/mmi block) tie off relevant signals
without_debug_if : if GENERATE_ADDITIONAL_DBG_RTL = 0 generate
constant c_slv_hl_stage_enable : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(c_capabilities_override, 32));
constant c_hl_stage_enable : std_logic_vector(c_hl_ccs_num_stages-1 downto 0) := c_slv_hl_stage_enable(c_hl_ccs_num_stages-1 downto 0);
constant c_pll_360_sweeps : natural := rrp_pll_phase_mult(DWIDTH_RATIO, MEM_IF_DQS_CAPTURE_EN);
signal mmi_regs : t_mmi_regs := defaults;
begin
-- avalon interface signals
seq_dbg_rd_data <= (others => '0');
seq_dbg_waitrequest <= '0';
-- The following registers are generated to simplify the assignments which follow
-- but will be optimised away in synthesis
mmi_regs.rw_regs <= defaults(c_phy_def_mr_1st_sl_vector,
c_phy_def_mr_2nd_sl_vector,
c_phy_def_mr_3rd_sl_vector,
c_phy_def_mr_4th_sl_vector,
NOM_DQS_PHASE_SETTING,
PLL_STEPS_PER_CYCLE,
c_pll_360_sweeps,
c_tracking_interval_in_ms,
c_hl_stage_enable);
mmi_regs.ro_regs <= defaults(dgrb_mmi,
ctrl_mmi,
pll_mmi,
mmi_regs.rw_regs.rw_if_test,
'0', -- do not use iram
MEM_IF_DQS_CAPTURE_EN,
int_ac_nt(0),
trefi_failure,
iram_status,
c_int_iram_awidth);
process(mmi_regs)
begin
-- debug parameterisation signals
regs_admin_ctrl_rec <= pack_record(mmi_regs.rw_regs);
parameterisation_rec <= pack_record(mmi_regs.rw_regs);
mmi_pll <= pack_record(mmi_regs.rw_regs);
mmi_ctrl <= pack_record(mmi_regs.rw_regs);
end process;
-- from the iram
iram_status <= defaults;
iram_push_done <= '0';
end generate; -- without debug interface
--
dgrb : entity ddr_ctrl_ip_phy_alt_mem_phy_dgrb
generic map(
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_DQS_CAPTURE => MEM_IF_DQS_CAPTURE_EN,
DWIDTH_RATIO => DWIDTH_RATIO,
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
PRESET_RLAT => PRESET_RLAT,
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
SIM_TIME_REDUCTIONS => SIM_TIME_REDUCTIONS,
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
PRESET_CODVW_PHASE => c_preset_codvw_phase,
PRESET_CODVW_SIZE => c_preset_codvw_size,
MEM_IF_CAL_BANK => c_mem_if_cal_bank,
MEM_IF_CAL_BASE_COL => c_mem_if_cal_base_col,
EN_OCT => EN_OCT
)
port map(
clk => clk,
rst_n => rst_n,
dgrb_ctrl => dgrb_ctrl,
ctrl_dgrb => ctrl_broadcast,
parameterisation_rec => parameterisation_rec,
phs_shft_busy => dgrb_phs_shft_busy,
seq_pll_inc_dec_n => dgrb_pll_inc_dec_n,
seq_pll_select => dgrb_pll_select,
seq_pll_start_reconfig => dgrb_pll_start_reconfig,
pll_resync_clk_index => pll_resync_clk_index,
pll_measure_clk_index => pll_measure_clk_index,
dgrb_iram => dgrb_iram,
iram_push_done => iram_push_done,
dgrb_ac => dgrb_ac,
dgrb_ac_access_req => dgrb_ac_access_req,
dgrb_ac_access_gnt => dgb_ac_access_gnt_r,
seq_rdata_valid_lat_inc => seq_rdata_valid_lat_inc_int,
seq_rdata_valid_lat_dec => seq_rdata_valid_lat_dec_int,
seq_poa_lat_dec_1x => seq_poa_lat_dec_1x_int,
seq_poa_lat_inc_1x => seq_poa_lat_inc_1x_int,
rdata_valid => rdata_valid,
rdata => rdata,
doing_rd => seq_rdv_doing_rd_int,
rd_lat => seq_ctl_rlat_int,
wd_lat => seq_ctl_wlat_int,
dgrb_wdp_ovride => dgrb_wdp_override,
seq_oct_value => seq_oct_value,
seq_mmc_start => seq_mmc_start,
mmc_seq_done => mmc_seq_done,
mmc_seq_value => mmc_seq_value,
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
odt_settings => c_odt_settings,
dgrb_ctrl_ac_nt_good => dgrb_ctrl_ac_nt_good,
dgrb_mmi => dgrb_mmi
);
--
dgwb : entity ddr_ctrl_ip_phy_alt_mem_phy_dgwb
generic map(
-- Physical IF width definitions
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
DWIDTH_RATIO => DWIDTH_RATIO,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
MEM_IF_CAL_BANK => c_mem_if_cal_bank,
MEM_IF_CAL_BASE_COL => c_mem_if_cal_base_col
)
port map(
clk => clk,
rst_n => rst_n,
parameterisation_rec => parameterisation_rec,
dgwb_ctrl => dgwb_ctrl,
ctrl_dgwb => ctrl_broadcast,
dgwb_iram => dgwb_iram,
iram_push_done => iram_push_done,
dgwb_ac_access_req => dgwb_ac_access_req,
dgwb_ac_access_gnt => dgb_ac_access_gnt_r,
dgwb_dqs_burst => seq_wdp_dqs_burst,
dgwb_wdata_valid => seq_wdp_wdata_valid,
dgwb_wdata => seq_wdp_wdata,
dgwb_dm => seq_wdp_dm,
dgwb_dqs => seq_wdp_dqs,
dgwb_wdp_ovride => dgwb_wdp_override,
dgwb_ac => dgwb_ac,
bypassed_rdata => rdata(DWIDTH_RATIO * MEM_IF_DWIDTH -1 downto (DWIDTH_RATIO-1) * MEM_IF_DWIDTH),
odt_settings => c_odt_settings
);
--
ctrl: entity ddr_ctrl_ip_phy_alt_mem_phy_ctrl
generic map(
FAMILYGROUP_ID => FAMILYGROUP_ID,
MEM_IF_DLL_LOCK_COUNT => 1280/(DWIDTH_RATIO/2),
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
DWIDTH_RATIO => DWIDTH_RATIO,
IRAM_ADDRESSING => c_iram_addresses,
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
TRACKING_INTERVAL_IN_MS => c_tracking_interval_in_ms,
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
SIM_TIME_REDUCTIONS => SIM_TIME_REDUCTIONS,
ACK_SEVERITY => warning
)
port map(
clk => clk,
rst_n => rst_n,
ctl_init_success => ctl_init_success_int,
ctl_init_fail => ctl_init_fail_int,
ctl_recalibrate_req => ctl_recalibrate_req,
iram_status => iram_status,
iram_push_done => iram_push_done,
ctrl_op_rec => ctrl_broadcast,
admin_ctrl => admin_ctrl,
dgrb_ctrl => dgrb_ctrl,
dgwb_ctrl => dgwb_ctrl,
ctrl_iram_push => ctrl_iram_push,
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
dgrb_ctrl_ac_nt_good => dgrb_ctrl_ac_nt_good,
int_ac_nt => int_ac_nt,
mmi_ctrl => mmi_ctrl,
ctrl_mmi => ctrl_mmi
);
-- ------------------------------------------------------------------
-- generate legacy rsu signals
-- ------------------------------------------------------------------
process(rst_n, clk)
begin
if rst_n = '0' then
rsu_multiple_valid_latencies_err <= '0';
rsu_grt_one_dvw_err <= '0';
rsu_no_dvw_err <= '0';
rsu_codvw_phase <= (others => '0');
rsu_codvw_size <= (others => '0');
rsu_read_latency <= (others => '0');
elsif rising_edge(clk) then
if dgrb_ctrl.command_err = '1' then
case to_integer(unsigned(dgrb_ctrl.command_result)) is
when C_ERR_RESYNC_NO_VALID_PHASES =>
rsu_no_dvw_err <= '1';
when C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS =>
rsu_multiple_valid_latencies_err <= '1';
when others => null;
end case;
end if;
rsu_codvw_phase(dgrb_mmi.cal_codvw_phase'range) <= dgrb_mmi.cal_codvw_phase;
rsu_codvw_size(dgrb_mmi.cal_codvw_size'range) <= dgrb_mmi.cal_codvw_size;
rsu_read_latency <= seq_ctl_rlat_int;
rsu_grt_one_dvw_err <= dgrb_mmi.codvw_grt_one_dvw;
-- Reset the flag on a recal request :
if ( ctl_recalibrate_req = '1') then
rsu_grt_one_dvw_err <= '0';
rsu_no_dvw_err <= '0';
rsu_multiple_valid_latencies_err <= '0';
end if;
end if;
end process;
-- ---------------------------------------------------------------
-- top level multiplexing and ctrl functionality
-- ---------------------------------------------------------------
oct_delay_block : block
constant DEFAULT_OCT_DELAY_CONST : integer := - 2; -- higher increases delay by one mem_clk cycle, lower decreases delay by one mem_clk cycle.
constant DEFAULT_OCT_EXTEND : natural := 3;
-- Returns additive latency extracted from mr0 as a natural number.
function decode_cl(mr0 : in std_logic_vector(12 downto 0))
return natural is
variable v_cl : natural range 0 to 2**4 - 1;
begin
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
v_cl := to_integer(unsigned(mr0(6 downto 4)));
elsif MEM_IF_MEMTYPE = "DDR3" then
v_cl := to_integer(unsigned(mr0(6 downto 4))) + 4;
else
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
end if;
return v_cl;
end function;
-- Returns additive latency extracted from mr1 as a natural number.
function decode_al(mr1 : in std_logic_vector(12 downto 0))
return natural is
variable v_al : natural range 0 to 2**4 - 1;
begin
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
v_al := to_integer(unsigned(mr1(5 downto 3)));
elsif MEM_IF_MEMTYPE = "DDR3" then
v_al := to_integer(unsigned(mr1(4 downto 3)));
else
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
end if;
return v_al;
end function;
-- Returns cas write latency extracted from mr2 as a natural number.
function decode_cwl(
mr0 : in std_logic_vector(12 downto 0);
mr2 : in std_logic_vector(12 downto 0)
)
return natural is
variable v_cwl : natural range 0 to 2**4 - 1;
begin
if MEM_IF_MEMTYPE = "DDR" then
v_cwl := 1;
elsif MEM_IF_MEMTYPE = "DDR2" then
v_cwl := decode_cl(mr0) - 1;
elsif MEM_IF_MEMTYPE = "DDR3" then
v_cwl := to_integer(unsigned(mr2(4 downto 3))) + 5;
else
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
end if;
return v_cwl;
end function;
begin
-- Process to work out timings for OCT extension and delay with respect to doing_read. NOTE that it is calculated on the basis of CL, CWL, ctl_wlat
oct_delay_proc : process(clk, rst_n)
variable v_cl : natural range 0 to 2**4 - 1; -- Total read latency.
variable v_cwl : natural range 0 to 2**4 - 1; -- Total write latency
variable oct_delay : natural range 0 to 2**OCT_LAT_WIDTH - 1;
variable v_wlat : natural range 0 to 2**ADV_LAT_WIDTH - 1;
begin
if rst_n = '0' then
seq_oct_oct_delay <= (others => '0');
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
elsif rising_edge(clk) then
if ctl_init_success_int = '1' then
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
v_cl := decode_cl(admin_regs_status_rec.mr0);
v_cwl := decode_cwl(admin_regs_status_rec.mr0, admin_regs_status_rec.mr2);
if SIM_TIME_REDUCTIONS = 1 then
v_wlat := c_preset_cal_setup.wlat;
else
v_wlat := to_integer(unsigned(seq_ctl_wlat_int));
end if;
oct_delay := DWIDTH_RATIO * v_wlat / 2 + (v_cl - v_cwl) + DEFAULT_OCT_DELAY_CONST;
if not (FAMILYGROUP_ID = 2) then -- CIII doesn't support OCT
seq_oct_oct_delay <= std_logic_vector(to_unsigned(oct_delay, OCT_LAT_WIDTH));
end if;
else
seq_oct_oct_delay <= (others => '0');
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
end if;
end if;
end process;
end block;
-- control postamble protection override signal (seq_poa_protection_override_1x)
process(clk, rst_n)
variable v_warning_given : std_logic;
begin
if rst_n = '0' then
seq_poa_protection_override_1x <= '0';
v_warning_given := '0';
elsif rising_edge(clk) then
case ctrl_broadcast.command is
when cmd_rdv |
cmd_rrp_sweep |
cmd_rrp_seek |
cmd_prep_adv_rd_lat |
cmd_prep_adv_wr_lat => seq_poa_protection_override_1x <= '1';
when others => seq_poa_protection_override_1x <= '0';
end case;
end if;
end process;
ac_mux : block
constant c_mem_clk_disable_pipe_len : natural := 3;
signal seen_phy_init_complete : std_logic;
signal mem_clk_disable : std_logic_vector(c_mem_clk_disable_pipe_len - 1 downto 0);
signal ctrl_broadcast_r : t_ctrl_command;
begin
-- register ctrl_broadcast locally
-- #for speed and to reduce fan out
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_broadcast_r <= defaults;
elsif rising_edge(clk) then
ctrl_broadcast_r <= ctrl_broadcast;
end if;
end process;
-- multiplex mem interface control between admin, dgrb and dgwb
process(clk, rst_n)
variable v_seq_ac_mux : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
begin
if rst_n = '0' then
seq_rdv_doing_rd <= (others => '0');
seq_mem_clk_disable <= '1';
mem_clk_disable <= (others => '1');
seen_phy_init_complete <= '0';
seq_ac_addr <= (others => '0');
seq_ac_ba <= (others => '0');
seq_ac_cas_n <= (others => '1');
seq_ac_ras_n <= (others => '1');
seq_ac_we_n <= (others => '1');
seq_ac_cke <= (others => '0');
seq_ac_cs_n <= (others => '1');
seq_ac_odt <= (others => '0');
seq_ac_rst_n <= (others => '0');
elsif rising_edge(clk) then
seq_rdv_doing_rd <= seq_rdv_doing_rd_int;
seq_mem_clk_disable <= mem_clk_disable(c_mem_clk_disable_pipe_len-1);
mem_clk_disable(c_mem_clk_disable_pipe_len-1 downto 1) <= mem_clk_disable(c_mem_clk_disable_pipe_len-2 downto 0);
if dgwb_ac_access_req = '1' and dgb_ac_access_gnt = '1' then
v_seq_ac_mux := dgwb_ac;
elsif dgrb_ac_access_req = '1' and dgb_ac_access_gnt = '1' then
v_seq_ac_mux := dgrb_ac;
else
v_seq_ac_mux := admin_ac;
end if;
if ctl_recalibrate_req = '1' then
mem_clk_disable(0) <= '1';
seen_phy_init_complete <= '0';
elsif ctrl_broadcast_r.command = cmd_init_dram and ctrl_broadcast_r.command_req = '1' then
mem_clk_disable(0) <= '0';
seen_phy_init_complete <= '1';
end if;
if seen_phy_init_complete /= '1' then -- if not initialised the phy hold in reset
seq_ac_addr <= (others => '0');
seq_ac_ba <= (others => '0');
seq_ac_cas_n <= (others => '1');
seq_ac_ras_n <= (others => '1');
seq_ac_we_n <= (others => '1');
seq_ac_cke <= (others => '0');
seq_ac_cs_n <= (others => '1');
seq_ac_odt <= (others => '0');
seq_ac_rst_n <= (others => '0');
else
if enable_odt = '0' then
v_seq_ac_mux := mask(c_seq_addr_cmd_config, v_seq_ac_mux, odt, '0');
end if;
unpack_addr_cmd_vector (
c_seq_addr_cmd_config,
v_seq_ac_mux,
seq_ac_addr,
seq_ac_ba,
seq_ac_cas_n,
seq_ac_ras_n,
seq_ac_we_n,
seq_ac_cke,
seq_ac_cs_n,
seq_ac_odt,
seq_ac_rst_n);
end if;
end if;
end process;
end block;
-- register dgb_ac_access_gnt signal to ensure ODT set correctly in dgrb and dgwb prior to a read or write operation
process(clk, rst_n)
begin
if rst_n = '0' then
dgb_ac_access_gnt_r <= '0';
elsif rising_edge(clk) then
dgb_ac_access_gnt_r <= dgb_ac_access_gnt;
end if;
end process;
-- multiplex access request from dgrb/dgwb to admin block with checking for multiple accesses
process (dgrb_ac_access_req, dgwb_ac_access_req)
begin
dgb_ac_access_req <= '0';
if dgwb_ac_access_req = '1' and dgrb_ac_access_req = '1' then
report seq_report_prefix & "multiple accesses attempted from DGRB and DGWB to admin block via signals dg.b_ac_access_reg " severity failure;
elsif dgwb_ac_access_req = '1' or dgrb_ac_access_req = '1' then
dgb_ac_access_req <= '1';
end if;
end process;
rdv_poa_blk : block
-- signals to control static setup of ctl_rdata_valid signal for instant on mode:
constant c_static_rdv_offset : integer := c_preset_cal_setup.rdv_lat; -- required change in RDV latency (should always be > 0)
signal static_rdv_offset : natural range 0 to abs(c_static_rdv_offset); -- signal to count # RDV shifts
constant c_dly_rdv_set : natural := 7; -- delay between RDV shifts
signal dly_rdv_inc_dec : std_logic; -- 1 = inc, 0 = dec
signal rdv_set_delay : natural range 0 to c_dly_rdv_set; -- signal to delay RDV shifts
-- same for poa protection
constant c_static_poa_offset : integer := c_preset_cal_setup.poa_lat;
signal static_poa_offset : natural range 0 to abs(c_static_poa_offset);
constant c_dly_poa_set : natural := 7;
signal dly_poa_inc_dec : std_logic;
signal poa_set_delay : natural range 0 to c_dly_poa_set;
-- function to abstract increment or decrement checking
function set_inc_dec(offset : integer) return std_logic is
begin
if offset < 0 then
return '1';
else
return '0';
end if;
end function;
begin
-- register postamble and rdata_valid latencies
-- note: postamble unused for Cyclone-III
-- RDV
process(clk, rst_n)
begin
if rst_n = '0' then
if SIM_TIME_REDUCTIONS = 1 then
-- setup offset calc
static_rdv_offset <= abs(c_static_rdv_offset);
dly_rdv_inc_dec <= set_inc_dec(c_static_rdv_offset);
rdv_set_delay <= c_dly_rdv_set;
end if;
seq_rdata_valid_lat_dec <= '0';
seq_rdata_valid_lat_inc <= '0';
elsif rising_edge(clk) then
if SIM_TIME_REDUCTIONS = 1 then -- perform static setup of RDV signal
if ctl_recalibrate_req = '1' then -- second reset condition
-- setup offset calc
static_rdv_offset <= abs(c_static_rdv_offset);
dly_rdv_inc_dec <= set_inc_dec(c_static_rdv_offset);
rdv_set_delay <= c_dly_rdv_set;
else
if static_rdv_offset /= 0 and
rdv_set_delay = 0 then
seq_rdata_valid_lat_dec <= not dly_rdv_inc_dec;
seq_rdata_valid_lat_inc <= dly_rdv_inc_dec;
static_rdv_offset <= static_rdv_offset - 1;
rdv_set_delay <= c_dly_rdv_set;
else -- once conplete pass through internal signals
seq_rdata_valid_lat_dec <= seq_rdata_valid_lat_dec_int;
seq_rdata_valid_lat_inc <= seq_rdata_valid_lat_inc_int;
end if;
if rdv_set_delay /= 0 then
rdv_set_delay <= rdv_set_delay - 1;
end if;
end if;
else -- no static setup
seq_rdata_valid_lat_dec <= seq_rdata_valid_lat_dec_int;
seq_rdata_valid_lat_inc <= seq_rdata_valid_lat_inc_int;
end if;
end if;
end process;
-- count number of RDV adjustments for debug
process(clk, rst_n)
begin
if rst_n = '0' then
rdv_adjustments <= 0;
elsif rising_edge(clk) then
if seq_rdata_valid_lat_dec_int = '1' then
rdv_adjustments <= rdv_adjustments + 1;
end if;
if seq_rdata_valid_lat_inc_int = '1' then
if rdv_adjustments = 0 then
report seq_report_prefix & " read data valid adjustment wrap around detected - more increments than decrements" severity failure;
else
rdv_adjustments <= rdv_adjustments - 1;
end if;
end if;
end if;
end process;
-- POA protection
process(clk, rst_n)
begin
if rst_n = '0' then
if SIM_TIME_REDUCTIONS = 1 then
-- setup offset calc
static_poa_offset <= abs(c_static_poa_offset);
dly_poa_inc_dec <= set_inc_dec(c_static_poa_offset);
poa_set_delay <= c_dly_poa_set;
end if;
seq_poa_lat_dec_1x <= (others => '0');
seq_poa_lat_inc_1x <= (others => '0');
elsif rising_edge(clk) then
if SIM_TIME_REDUCTIONS = 1 then -- static setup
if ctl_recalibrate_req = '1' then -- second reset condition
-- setup offset calc
static_poa_offset <= abs(c_static_poa_offset);
dly_poa_inc_dec <= set_inc_dec(c_static_poa_offset);
poa_set_delay <= c_dly_poa_set;
else
if static_poa_offset /= 0 and
poa_set_delay = 0 then
seq_poa_lat_dec_1x <= (others => not(dly_poa_inc_dec));
seq_poa_lat_inc_1x <= (others => dly_poa_inc_dec);
static_poa_offset <= static_poa_offset - 1;
poa_set_delay <= c_dly_poa_set;
else
seq_poa_lat_inc_1x <= seq_poa_lat_inc_1x_int;
seq_poa_lat_dec_1x <= seq_poa_lat_dec_1x_int;
end if;
if poa_set_delay /= 0 then
poa_set_delay <= poa_set_delay - 1;
end if;
end if;
else -- no static setup
seq_poa_lat_inc_1x <= seq_poa_lat_inc_1x_int;
seq_poa_lat_dec_1x <= seq_poa_lat_dec_1x_int;
end if;
end if;
end process;
-- count POA protection adjustments for debug
process(clk, rst_n)
begin
if rst_n = '0' then
poa_adjustments <= 0;
elsif rising_edge(clk) then
if seq_poa_lat_dec_1x_int(0) = '1' then
poa_adjustments <= poa_adjustments + 1;
end if;
if seq_poa_lat_inc_1x_int(0) = '1' then
if poa_adjustments = 0 then
report seq_report_prefix & " postamble adjustment wrap around detected - more increments than decrements" severity failure;
else
poa_adjustments <= poa_adjustments - 1;
end if;
end if;
end if;
end process;
end block;
-- register output fail/success signals - avoiding optimisation out
process(clk, rst_n)
begin
if rst_n = '0' then
ctl_init_fail <= '0';
ctl_init_success <= '0';
elsif rising_edge(clk) then
ctl_init_fail <= ctl_init_fail_int;
ctl_init_success <= ctl_init_success_int;
end if;
end process;
-- ctl_cal_byte_lanes register
-- seq_rdp_reset_req_n - when ctl_recalibrate_req issued
process(clk,rst_n)
begin
if rst_n = '0' then
seq_rdp_reset_req_n <= '0';
ctl_cal_byte_lanes_r <= (others => '1');
elsif rising_edge(clk) then
ctl_cal_byte_lanes_r <= not ctl_cal_byte_lanes;
if ctl_recalibrate_req = '1' then
seq_rdp_reset_req_n <= '0';
else
if ctrl_broadcast.command = cmd_rrp_sweep or
SIM_TIME_REDUCTIONS = 1 then
seq_rdp_reset_req_n <= '1';
end if;
end if;
end if;
end process;
-- register 1t addr/cmd and odt latency outputs
process(clk, rst_n)
begin
if rst_n = '0' then
seq_ac_add_1t_ac_lat_internal <= '0';
seq_ac_add_1t_odt_lat_internal <= '0';
seq_ac_add_2t <= '0';
elsif rising_edge(clk) then
if SIM_TIME_REDUCTIONS = 1 then
seq_ac_add_1t_ac_lat_internal <= c_preset_cal_setup.ac_1t;
seq_ac_add_1t_odt_lat_internal <= c_preset_cal_setup.ac_1t;
else
seq_ac_add_1t_ac_lat_internal <= int_ac_nt(0);
seq_ac_add_1t_odt_lat_internal <= int_ac_nt(0);
end if;
seq_ac_add_2t <= '0';
end if;
end process;
-- override write datapath signal generation
process(dgwb_wdp_override, dgrb_wdp_override, ctl_init_success_int, ctl_init_fail_int)
begin
if ctl_init_success_int = '0' and ctl_init_fail_int = '0' then -- if calibrating
seq_wdp_ovride <= dgwb_wdp_override or dgrb_wdp_override;
else
seq_wdp_ovride <= '0';
end if;
end process;
-- output write/read latency (override with preset values when sim time reductions equals 1
seq_ctl_wlat <= std_logic_vector(to_unsigned(c_preset_cal_setup.wlat,ADV_LAT_WIDTH)) when SIM_TIME_REDUCTIONS = 1 else seq_ctl_wlat_int;
seq_ctl_rlat <= std_logic_vector(to_unsigned(c_preset_cal_setup.rlat,ADV_LAT_WIDTH)) when SIM_TIME_REDUCTIONS = 1 else seq_ctl_rlat_int;
process (clk, rst_n)
begin
if rst_n = '0' then
seq_pll_phs_shift_busy_r <= '0';
seq_pll_phs_shift_busy_ccd <= '0';
elsif rising_edge(clk) then
seq_pll_phs_shift_busy_r <= seq_pll_phs_shift_busy;
seq_pll_phs_shift_busy_ccd <= seq_pll_phs_shift_busy_r;
end if;
end process;
pll_ctrl: block
-- static resync setup variables for sim time reductions
signal static_rst_offset : natural range 0 to 2*PLL_STEPS_PER_CYCLE;
signal phs_shft_busy_1r : std_logic;
signal pll_set_delay : natural range 100 downto 0; -- wait 100 clock cycles for clk to be stable before setting resync phase
-- pll signal generation
signal mmi_pll_active : boolean;
signal seq_pll_phs_shift_busy_ccd_1t : std_logic;
begin
-- multiplex ppl interface between dgrb and mmi blocks
-- plus static setup of rsc phase to a known 'good' condition
process(clk,rst_n)
begin
if rst_n = '0' then
seq_pll_inc_dec_n <= '0';
seq_pll_start_reconfig <= '0';
seq_pll_select <= (others => '0');
dgrb_phs_shft_busy <= '0';
-- static resync setup variables for sim time reductions
if SIM_TIME_REDUCTIONS = 1 then
static_rst_offset <= c_preset_codvw_phase;
else
static_rst_offset <= 0;
end if;
phs_shft_busy_1r <= '0';
pll_set_delay <= 100;
elsif rising_edge(clk) then
dgrb_phs_shft_busy <= '0';
if static_rst_offset /= 0 and -- not finished decrementing
pll_set_delay = 0 and -- initial reset period over
SIM_TIME_REDUCTIONS = 1 then -- in reduce sim time mode (optimse logic away when not in this mode)
seq_pll_inc_dec_n <= '1';
seq_pll_start_reconfig <= '1';
seq_pll_select <= pll_resync_clk_index;
if seq_pll_phs_shift_busy_ccd = '1' then -- no metastability hardening needed in simulation
-- PLL phase shift started - so stop requesting a shift
seq_pll_start_reconfig <= '0';
end if;
if seq_pll_phs_shift_busy_ccd = '0' and phs_shft_busy_1r = '1' then
-- PLL phase shift finished - so proceed to flush the datapath
static_rst_offset <= static_rst_offset - 1;
seq_pll_start_reconfig <= '0';
end if;
phs_shft_busy_1r <= seq_pll_phs_shift_busy_ccd;
else
if ctrl_iram_push.active_block = ret_dgrb then
seq_pll_inc_dec_n <= dgrb_pll_inc_dec_n;
seq_pll_start_reconfig <= dgrb_pll_start_reconfig;
seq_pll_select <= dgrb_pll_select;
dgrb_phs_shft_busy <= seq_pll_phs_shift_busy_ccd;
else
seq_pll_inc_dec_n <= mmi_pll_inc_dec_n;
seq_pll_start_reconfig <= mmi_pll_start_reconfig;
seq_pll_select <= mmi_pll_select;
end if;
end if;
if pll_set_delay /= 0 then
pll_set_delay <= pll_set_delay - 1;
end if;
if ctl_recalibrate_req = '1' then
pll_set_delay <= 100;
end if;
end if;
end process;
-- generate mmi pll signals
process (clk, rst_n)
begin
if rst_n = '0' then
pll_mmi.pll_busy <= '0';
pll_mmi.err <= (others => '0');
mmi_pll_inc_dec_n <= '0';
mmi_pll_start_reconfig <= '0';
mmi_pll_select <= (others => '0');
mmi_pll_active <= false;
seq_pll_phs_shift_busy_ccd_1t <= '0';
elsif rising_edge(clk) then
if mmi_pll_active = true then
pll_mmi.pll_busy <= '1';
else
pll_mmi.pll_busy <= mmi_pll.pll_phs_shft_up_wc or mmi_pll.pll_phs_shft_dn_wc;
end if;
if pll_mmi.err = "00" and dgrb_pll_start_reconfig = '1' then
pll_mmi.err <= "01";
elsif pll_mmi.err = "00" and mmi_pll_active = true then
pll_mmi.err <= "10";
elsif pll_mmi.err = "00" and dgrb_pll_start_reconfig = '1' and mmi_pll_active = true then
pll_mmi.err <= "11";
end if;
if mmi_pll.pll_phs_shft_up_wc = '1' and mmi_pll_active = false then
mmi_pll_inc_dec_n <= '1';
mmi_pll_select <= std_logic_vector(to_unsigned(mmi_pll.pll_phs_shft_phase_sel,mmi_pll_select'length));
mmi_pll_active <= true;
elsif mmi_pll.pll_phs_shft_dn_wc = '1' and mmi_pll_active = false then
mmi_pll_inc_dec_n <= '0';
mmi_pll_select <= std_logic_vector(to_unsigned(mmi_pll.pll_phs_shft_phase_sel,mmi_pll_select'length));
mmi_pll_active <= true;
elsif seq_pll_phs_shift_busy_ccd_1t = '1' and seq_pll_phs_shift_busy_ccd = '0' then
mmi_pll_start_reconfig <= '0';
mmi_pll_active <= false;
elsif mmi_pll_active = true and mmi_pll_start_reconfig = '0' and seq_pll_phs_shift_busy_ccd = '0' then
mmi_pll_start_reconfig <= '1';
elsif seq_pll_phs_shift_busy_ccd_1t = '0' and seq_pll_phs_shift_busy_ccd = '1' then
mmi_pll_start_reconfig <= '0';
end if;
seq_pll_phs_shift_busy_ccd_1t <= seq_pll_phs_shift_busy_ccd;
end if;
end process;
end block; -- pll_ctrl
--synopsys synthesis_off
reporting : block
function pass_or_fail_report( cal_success : in std_logic;
cal_fail : in std_logic
) return string is
begin
if cal_success = '1' and cal_fail = '1' then
return "unknown state cal_fail and cal_success both high";
end if;
if cal_success = '1' then
return "PASSED";
end if;
if cal_fail = '1' then
return "FAILED";
end if;
return "calibration report run whilst sequencer is still calibrating";
end function;
function is_stage_disabled ( stage_name : in string;
stage_dis : in std_logic
) return string is
begin
if stage_dis = '0' then
return "";
else
return stage_name & " stage is disabled" & LF;
end if;
end function;
function disabled_stages ( capabilities : in std_logic_vector
) return string is
begin
return is_stage_disabled("all calibration", c_capabilities(c_hl_css_reg_cal_dis_bit)) &
is_stage_disabled("initialisation", c_capabilities(c_hl_css_reg_phy_initialise_dis_bit)) &
is_stage_disabled("DRAM initialisation", c_capabilities(c_hl_css_reg_init_dram_dis_bit)) &
is_stage_disabled("iram header write", c_capabilities(c_hl_css_reg_write_ihi_dis_bit)) &
is_stage_disabled("burst training pattern write", c_capabilities(c_hl_css_reg_write_btp_dis_bit)) &
is_stage_disabled("more training pattern (MTP) write", c_capabilities(c_hl_css_reg_write_mtp_dis_bit)) &
is_stage_disabled("check MTP pattern alignment calculation", c_capabilities(c_hl_css_reg_read_mtp_dis_bit)) &
is_stage_disabled("read resynch phase reset stage", c_capabilities(c_hl_css_reg_rrp_reset_dis_bit)) &
is_stage_disabled("read resynch phase sweep stage", c_capabilities(c_hl_css_reg_rrp_sweep_dis_bit)) &
is_stage_disabled("read resynch phase seek stage (set phase)", c_capabilities(c_hl_css_reg_rrp_seek_dis_bit)) &
is_stage_disabled("read data valid window setup", c_capabilities(c_hl_css_reg_rdv_dis_bit)) &
is_stage_disabled("postamble calibration", c_capabilities(c_hl_css_reg_poa_dis_bit)) &
is_stage_disabled("write latency timing calc", c_capabilities(c_hl_css_reg_was_dis_bit)) &
is_stage_disabled("advertise read latency", c_capabilities(c_hl_css_reg_adv_rd_lat_dis_bit)) &
is_stage_disabled("advertise write latency", c_capabilities(c_hl_css_reg_adv_wr_lat_dis_bit)) &
is_stage_disabled("write customer mode register settings", c_capabilities(c_hl_css_reg_prep_customer_mr_setup_dis_bit)) &
is_stage_disabled("tracking", c_capabilities(c_hl_css_reg_tracking_dis_bit));
end function;
function ac_nt_report( ac_nt : in std_logic_vector;
dgrb_ctrl_ac_nt_good : in std_logic;
preset_cal_setup : in t_preset_cal) return string
is
variable v_ac_nt : std_logic_vector(0 downto 0);
begin
if SIM_TIME_REDUCTIONS = 1 then
v_ac_nt(0) := preset_cal_setup.ac_1t;
if v_ac_nt(0) = '1' then
return "-- statically set address and command 1T delay: add 1T delay" & LF;
else
return "-- statically set address and command 1T delay: no 1T delay" & LF;
end if;
else
v_ac_nt(0) := ac_nt(0);
if dgrb_ctrl_ac_nt_good = '1' then
if v_ac_nt(0) = '1' then
return "-- chosen address and command 1T delay: add 1T delay" & LF;
else
return "-- chosen address and command 1T delay: no 1T delay" & LF;
end if;
else
return "-- no valid address and command phase chosen (calibration FAILED)" & LF;
end if;
end if;
end function;
function read_resync_report ( codvw_phase : in std_logic_vector;
codvw_size : in std_logic_vector;
ctl_rlat : in std_logic_vector;
ctl_wlat : in std_logic_vector;
preset_cal_setup : in t_preset_cal) return string
is
begin
if SIM_TIME_REDUCTIONS = 1 then
return "-- read resynch phase static setup (no calibration run) report:" & LF &
" -- statically set centre of data valid window phase : " & natural'image(preset_cal_setup.codvw_phase) & LF &
" -- statically set centre of data valid window size : " & natural'image(preset_cal_setup.codvw_size) & LF &
" -- statically set read latency (ctl_rlat) : " & natural'image(preset_cal_setup.rlat) & LF &
" -- statically set write latency (ctl_wlat) : " & natural'image(preset_cal_setup.wlat) & LF &
" -- note: this mode only works for simulation and sets resync phase" & LF &
" to a known good operating condition for no test bench" & LF &
" delays on mem_dq signal" & LF;
else
return "-- PHY read latency (ctl_rlat) is : " & natural'image(to_integer(unsigned(ctl_rlat))) & LF &
"-- address/command to PHY write latency (ctl_wlat) is : " & natural'image(to_integer(unsigned(ctl_wlat))) & LF &
"-- read resynch phase calibration report:" & LF &
" -- calibrated centre of data valid window phase : " & natural'image(to_integer(unsigned(codvw_phase))) & LF &
" -- calibrated centre of data valid window size : " & natural'image(to_integer(unsigned(codvw_size))) & LF;
end if;
end function;
function poa_rdv_adjust_report( poa_adjust : in natural;
rdv_adjust : in natural;
preset_cal_setup : in t_preset_cal) return string
is
begin
if SIM_TIME_REDUCTIONS = 1 then
return "Statically set poa and rdv (adjustments from reset value):" & LF &
"poa 'dec' adjustments = " & natural'image(preset_cal_setup.poa_lat) & LF &
"rdv 'dec' adjustments = " & natural'image(preset_cal_setup.rdv_lat) & LF;
else
return "poa 'dec' adjustments = " & natural'image(poa_adjust) & LF &
"rdv 'dec' adjustments = " & natural'image(rdv_adjust) & LF;
end if;
end function;
function calibration_report ( capabilities : in std_logic_vector;
cal_success : in std_logic;
cal_fail : in std_logic;
ctl_rlat : in std_logic_vector;
ctl_wlat : in std_logic_vector;
codvw_phase : in std_logic_vector;
codvw_size : in std_logic_vector;
ac_nt : in std_logic_vector;
dgrb_ctrl_ac_nt_good : in std_logic;
preset_cal_setup : in t_preset_cal;
poa_adjust : in natural;
rdv_adjust : in natural) return string
is
begin
return seq_report_prefix & " report..." & LF &
"-----------------------------------------------------------------------" & LF &
"-- **** ALTMEMPHY CALIBRATION has completed ****" & LF &
"-- Status:" & LF &
"-- calibration has : " & pass_or_fail_report(cal_success, cal_fail) & LF &
read_resync_report(codvw_phase, codvw_size, ctl_rlat, ctl_wlat, preset_cal_setup) &
ac_nt_report(ac_nt, dgrb_ctrl_ac_nt_good, preset_cal_setup) &
poa_rdv_adjust_report(poa_adjust, rdv_adjust, preset_cal_setup) &
disabled_stages(capabilities) &
"-----------------------------------------------------------------------";
end function;
begin
-- -------------------------------------------------------
-- calibration result reporting
-- -------------------------------------------------------
process(rst_n, clk)
variable v_reports_written : std_logic;
variable v_cal_request_r : std_logic;
variable v_rewrite_report : std_logic;
begin
if rst_n = '0' then
v_reports_written := '0';
v_cal_request_r := '0';
v_rewrite_report := '0';
elsif Rising_Edge(clk) then
if v_reports_written = '0' then
if ctl_init_success_int = '1' or ctl_init_fail_int = '1' then
v_reports_written := '1';
report calibration_report(c_capabilities,
ctl_init_success_int,
ctl_init_fail_int,
seq_ctl_rlat_int,
seq_ctl_wlat_int,
dgrb_mmi.cal_codvw_phase,
dgrb_mmi.cal_codvw_size,
int_ac_nt,
dgrb_ctrl_ac_nt_good,
c_preset_cal_setup,
poa_adjustments,
rdv_adjustments
) severity note;
end if;
end if;
-- if recalibrate request triggered watch for cal success / fail going low and re-trigger report writing
if ctl_recalibrate_req = '1' and v_cal_request_r = '0' then
v_rewrite_report := '1';
end if;
if v_rewrite_report = '1' and ctl_init_success_int = '0' and ctl_init_fail_int = '0' then
v_reports_written := '0';
v_rewrite_report := '0';
end if;
v_cal_request_r := ctl_recalibrate_req;
end if;
end process;
-- -------------------------------------------------------
-- capabilities vector reporting and coarse PHY setup sanity checks
-- -------------------------------------------------------
process(rst_n, clk)
variable reports_written : std_logic;
begin
if rst_n = '0' then
reports_written := '0';
elsif Rising_Edge(clk) then
if reports_written = '0' then
reports_written := '1';
if MEM_IF_MEMTYPE="DDR" or MEM_IF_MEMTYPE="DDR2" or MEM_IF_MEMTYPE="DDR3" then
if DWIDTH_RATIO = 2 or DWIDTH_RATIO = 4 then
report disabled_stages(c_capabilities) severity note;
else
report seq_report_prefix & "unsupported rate for non-levelling AFI PHY sequencer - only full- or half-rate supported" severity warning;
end if;
else
report seq_report_prefix & "memory type " & MEM_IF_MEMTYPE & " is not supported in non-levelling AFI PHY sequencer" severity failure;
end if;
end if;
end if;
end process;
end block; -- reporting
--synopsys synthesis_on
end architecture struct;
| gpl-2.0 | 8c8fff5a340bb119e40d078e7d9bee0f | 0.441724 | 4.424731 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/8b10_dec_wrap.vhd | 4 | 4,249 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/19/2014
--! Module Name: dec_8b10_wrap
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.centralRouter_package.all;
--! a wrap for 8b10b decoder
entity dec_8b10_wrap is
port (
RESET : in std_logic;
RBYTECLK : in std_logic;
ABCDEIFGHJ_IN : in std_logic_vector (9 downto 0);
HGFEDCBA : out std_logic_vector (7 downto 0);
ISK : out std_logic_vector (1 downto 0);
BUSY : out std_logic
);
end dec_8b10_wrap;
architecture Behavioral of dec_8b10_wrap is
----------------------------------
----------------------------------
COMPONENT dec_8b10b
PORT(
RESET : IN std_logic;
RBYTECLK : IN std_logic;
AI : IN std_logic;
BI : IN std_logic;
CI : IN std_logic;
DI : IN std_logic;
EI : IN std_logic;
II : IN std_logic;
FI : IN std_logic;
GI : IN std_logic;
HI : IN std_logic;
JI : IN std_logic;
KO : OUT std_logic;
HO : OUT std_logic;
GO : OUT std_logic;
FO : OUT std_logic;
EO : OUT std_logic;
DO : OUT std_logic;
CO : OUT std_logic;
BO : OUT std_logic;
AO : OUT std_logic
);
END COMPONENT;
----------------------------------
----------------------------------
signal ISK_falling_edge : std_logic;
signal BUSY_s : std_logic := '0';
signal HGFEDCBA_falling_edge : std_logic_vector(7 downto 0);
signal HGFEDCBA_sig : std_logic_vector(7 downto 0) := (others => '0');
signal ISKcode : std_logic_vector(1 downto 0);
signal ISK_sig : std_logic_vector(1 downto 0) := (others => '0');
signal ISK_comma, ISK_soc, ISK_eoc, ISK_sob, ISK_eob : std_logic;
begin
-- 8b10b decoder
dec_8b10b_INST: dec_8b10b
PORT MAP(
RESET => RESET,
RBYTECLK => RBYTECLK,
AI => ABCDEIFGHJ_IN(9),
BI => ABCDEIFGHJ_IN(8),
CI => ABCDEIFGHJ_IN(7),
DI => ABCDEIFGHJ_IN(6),
EI => ABCDEIFGHJ_IN(5),
II => ABCDEIFGHJ_IN(4),
FI => ABCDEIFGHJ_IN(3),
GI => ABCDEIFGHJ_IN(2),
HI => ABCDEIFGHJ_IN(1),
JI => ABCDEIFGHJ_IN(0),
KO => ISK_falling_edge,
HO => HGFEDCBA_falling_edge(7),
GO => HGFEDCBA_falling_edge(6),
FO => HGFEDCBA_falling_edge(5),
EO => HGFEDCBA_falling_edge(4),
DO => HGFEDCBA_falling_edge(3),
CO => HGFEDCBA_falling_edge(2),
BO => HGFEDCBA_falling_edge(1),
AO => HGFEDCBA_falling_edge(0)
);
------------------------------------------------------------------------------------------------------
ISK_comma <= '1' when (ABCDEIFGHJ_IN = COMMAp or ABCDEIFGHJ_IN = COMMAn) else '0';
ISK_soc <= '1' when (ABCDEIFGHJ_IN = SOCp or ABCDEIFGHJ_IN = SOCn) else '0';
ISK_eoc <= '1' when (ABCDEIFGHJ_IN = EOCp or ABCDEIFGHJ_IN = EOCn) else '0';
ISK_sob <= '1' when (ABCDEIFGHJ_IN = SOBp or ABCDEIFGHJ_IN = SOBn) else '0';
ISK_eob <= '1' when (ABCDEIFGHJ_IN = EOBp or ABCDEIFGHJ_IN = EOBn) else '0';
---
ISKcode(0) <= ((not ISK_soc) and (ISK_eoc xor ISK_comma)) or ISK_sob or ISK_eob;
ISKcode(1) <= ((not ISK_eoc) and (ISK_soc xor ISK_comma)) or ISK_sob or ISK_eob;
------------------------------------------------------------------------------------------------------
process(RBYTECLK)
begin
if RBYTECLK'event and RBYTECLK = '1' then
if ISK_falling_edge = '1' then
ISK_sig <= ISKcode;
else
ISK_sig <= "00";
end if;
end if;
end process;
--
process(RBYTECLK)
begin
if RBYTECLK'event and RBYTECLK = '1' then
HGFEDCBA_sig <= HGFEDCBA_falling_edge;
end if;
end process;
------------------------------------------------------------------------------------------------------
ISK <= ISK_sig;
HGFEDCBA <= HGFEDCBA_sig;
------------------------------------------------------------------------------------------------------
process(RBYTECLK)
begin
if RBYTECLK'event and RBYTECLK = '1' then
if ISK_sob = '1' then
BUSY_s <= '1';
elsif ISK_eob = '1' then
BUSY_s <= '0';
end if;
end if;
end process;
--
BUSY <= BUSY_s;
--
end Behavioral;
| gpl-3.0 | a8ba5c9a2057406af9786a7006953dd6 | 0.498 | 3.273498 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/configuration/cktp_counter.vhd | 1 | 5,201 | ----------------------------------------------------------------------------------
-- Company: NTU Athens - BNL
-- Engineer: Christos Bakalis ([email protected])
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Christos Bakalis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 26.03.2017 18:22:01
-- Design Name:
-- Module Name: cktp_counter - RTL
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description: State machine that counts CKTP pulses sent and stops the CKTP
-- generation depending on a maximum number of pulses that must be sent.
--
-- Dependencies:
--
-- Changelog:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
entity cktp_counter is
Port(
clk_160 : in std_logic;
cktp_start : in std_logic;
cktp_pulse : in std_logic;
cktp_max : in std_logic_vector(15 downto 0);
cktp_inhibit : out std_logic
);
end cktp_counter;
architecture RTL of cktp_counter is
-- state machine signals
type cktp_cnt_state_type is (ST_IDLE, ST_WAIT_FOR_LOW, ST_CNT_CHECK);
signal cktp_cnt_state : cktp_cnt_state_type := ST_IDLE;
signal fsm_enable : std_logic := '0';
signal fsm_enable_i : std_logic := '0';
signal fsm_enable_s : std_logic := '0';
signal cktp_inhibit_fsm : std_logic := '0';
signal inhibit_async_i : std_logic := '0';
signal inhibit_async_s : std_logic := '0';
signal inhibit_async : std_logic := '0';
signal cktp_cnt : unsigned(15 downto 0) := (others => '0');
attribute ASYNC_REG : string;
attribute ASYNC_REG of fsm_enable_i : signal is "TRUE";
attribute ASYNC_REG of fsm_enable_s : signal is "TRUE";
attribute ASYNC_REG of inhibit_async_i : signal is "TRUE";
attribute ASYNC_REG of inhibit_async_s : signal is "TRUE";
begin
-- transmit CKTPs indefinitely if cktp_max is FFFF, inhibit CKTPs if 0000
FSM_enble_proc: process(cktp_max, cktp_start)
begin
if(cktp_start = '1')then
case cktp_max is
when x"FFFF" => fsm_enable <= '0'; inhibit_async <= '0';
when x"0000" => fsm_enable <= '0'; inhibit_async <= '1';
when others => fsm_enable <= '1'; inhibit_async <= '0';
end case;
else
fsm_enable <= '0';
inhibit_async <= '1';
end if;
end process;
-- sync the enable signal
SynProc: process(clk_160)
begin
if(rising_edge(clk_160))then
fsm_enable_i <= fsm_enable;
fsm_enable_s <= fsm_enable_i;
inhibit_async_i <= inhibit_async;
inhibit_async_s <= inhibit_async_i;
end if;
end process;
-- state machine that counts CKTP pulses and asserts the inhibit flag if needed
FSM_CKTP_cnt_proc: process(clk_160)
begin
if(rising_edge(clk_160))then
if(fsm_enable_s = '1')then
case cktp_cnt_state is
-- wait for pulse
when ST_IDLE =>
if(cktp_pulse = '1')then
cktp_cnt_state <= ST_WAIT_FOR_LOW;
else
cktp_cnt_state <= ST_IDLE;
end if;
-- wait for pulse to go low, increment counter and check
when ST_WAIT_FOR_LOW =>
if(cktp_pulse = '0')then
cktp_cnt_state <= ST_CNT_CHECK;
cktp_cnt <= cktp_cnt + 1;
else
cktp_cnt_state <= ST_WAIT_FOR_LOW;
end if;
-- check the counter and assert flag+stay here if limit is reached, and
-- wait to be rest by configuration
when ST_CNT_CHECK =>
if(cktp_cnt <= unsigned(cktp_max))then
cktp_cnt_state <= ST_IDLE;
else
cktp_cnt_state <= ST_CNT_CHECK;
cktp_inhibit_fsm <= '1';
end if;
when others =>
cktp_cnt_state <= ST_IDLE;
cktp_cnt <= (others => '0');
cktp_inhibit_fsm <= '0';
end case;
else
cktp_cnt_state <= ST_IDLE;
cktp_cnt <= (others => '0');
cktp_inhibit_fsm <= '0';
end if;
end if;
end process;
cktp_inhibit <= cktp_inhibit_fsm or inhibit_async_s;
end RTL;
| gpl-3.0 | 7f2f01067bf1215e2df9eb5fcc12432c | 0.549125 | 3.788055 | false | false | false | false |
HackLinux/ION | src/rtl/cpu/ion_alu.vhdl | 1 | 4,566 | --------------------------------------------------------------------------------
-- ion_alu.vhdl -- integer arithmetic ALU, excluding mult/div functionality.
--
--------------------------------------------------------------------------------
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.ION_INTERFACES_PKG.all;
use work.ION_INTERNAL_PKG.all;
entity ION_ALU is
port(
CLK_I : in std_logic;
RESET_I : in std_logic;
-- function selection
AC_I : in t_alu_control;
-- comparison result FLAGS_O
FLAGS_O : out t_alu_flags;
-- data inputs
OP1_I : in std_logic_vector(31 downto 0);
OP2_I : in std_logic_vector(31 downto 0);
-- data result output
RES_O : out std_logic_vector(31 downto 0)
);
end;
architecture rtl of ION_ALU is
subtype t_eword is std_logic_vector(32 downto 0);
signal inp2_neg : t_word;
signal alu_eop1, alu_eop2 : t_eword;
signal sex1, sex2 : std_logic;
signal alu_arith : t_eword;
signal alu_shift : t_word;
signal alu_logic_shift : t_word;
signal alu_logic : t_word;
signal less_than_zero : std_logic;
signal final_mux_sel : std_logic_vector(1 downto 0);
signal alu_temp : t_word;
begin
with AC_I.neg_sel select inp2_neg <=
not OP2_I when "01", -- nor, sub, etc.
OP2_I(15 downto 0) & X"0000" when "10", -- lhi
X"00000000" when "11", -- zero
OP2_I when others; -- straight
sex1 <= OP1_I(31) when AC_I.arith_unsigned='0' else '0';
alu_eop1 <= sex1 & OP1_I;
sex2 <= inp2_neg(31) when (AC_I.arith_unsigned='0') else '0';
alu_eop2 <= sex2 & inp2_neg;
alu_arith <= alu_eop1 + alu_eop2 + AC_I.cy_in;
with AC_I.logic_sel select alu_logic <=
OP1_I and inp2_neg when "00",
OP1_I or inp2_neg when "01",
OP1_I xor inp2_neg when "10",
inp2_neg when others;
shifter : entity work.ION_SHIFTER
port map (
D_I => OP2_I,
A_I => AC_I.shift_amount,
FN_I => AC_I.shift_sel,
R_O => alu_shift
);
with AC_I.use_logic select alu_logic_shift <=
alu_logic when "01",
not alu_logic when "11", -- used only by NOR instruction
alu_shift when others;
final_mux_sel(0) <= AC_I.use_arith when AC_I.use_slt='0' else less_than_zero;
final_mux_sel(1) <= AC_I.use_slt;
with final_mux_sel select alu_temp <=
alu_arith(31 downto 0) when "01",
alu_logic_shift when "00",
X"00000001" when "11",
X"00000000" when others;
less_than_zero <= alu_arith(31) when AC_I.arith_unsigned='1' else alu_arith(32);
FLAGS_O.inp1_lt_zero <= OP1_I(31);
FLAGS_O.inp1_lt_inp2 <= less_than_zero;
FLAGS_O.inp1_eq_inp2 <= '1' when alu_arith(31 downto 0)=X"00000000" else '0';
FLAGS_O.inp1_eq_zero <= '1' when OP1_I(31 downto 0)=X"00000000" else '0';
RES_O <= alu_temp;
end; --architecture rtl
| lgpl-3.0 | 140d7ccfb40bb97fbd0fa38ccd5725ac | 0.527157 | 3.629571 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/centralRouter_package.vhd | 2 | 20,363 | --!-----------------------------------------------------------------------------
--! --
--! Weizmann Institute of Science --
--! Electronics & Data Acquisition Group --
--! --
--!-----------------------------------------------------------------------------
--!
--! unit name: centralRouter package
--!
--! author: [email protected]
--!
--! date: $10/12/2014 $: created
--!
--! version: $Rev 0 $:
--!
--! description: package file for the centralRouter interface
--!
--!-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
package centralRouter_package is
-------------------------------------------------------------------
-- general use type definitions
-------------------------------------------------------------------
type array7_std_logic_vector_15 is array (0 to 6) of std_logic_vector(14 downto 0);
type array8_std_logic_vector_15 is array (0 to 7) of std_logic_vector(14 downto 0);
type array8_std_logic_vector_16 is array (0 to 7) of std_logic_vector(15 downto 0);
type array7_std_logic_vector_8 is array (0 to 6) of std_logic_vector(7 downto 0);
type array8_std_logic_vector_8 is array (0 to 7) of std_logic_vector(7 downto 0);
type array15_std_logic_vector_7 is array (0 to 14) of std_logic_vector(6 downto 0);
type array15_std_logic_vector_8 is array (0 to 14) of std_logic_vector(7 downto 0);
type array15_std_logic_vector_6 is array (0 to 14) of std_logic_vector(5 downto 0);
type array15_std_logic_vector_3 is array (0 to 14) of std_logic_vector(2 downto 0);
-------------------------------------------------------------------
-- EPROC internal type definitions
-------------------------------------------------------------------
type isk_2array_type is array (0 to 1) of std_logic_vector(1 downto 0); -- 2 words of 2bit
type word8b_2array_type is array (0 to 1) of std_logic_vector(7 downto 0); -- 2 words of 8bit
type word10b_2array_type is array (0 to 1) of std_logic_vector(9 downto 0); -- 2 words of 10bit
type word10b_2array_4array_type is array (0 to 3) of word10b_2array_type; -- 4 groups of {2 words of 10bit}, one group per alignment
--
type isk_4array_type is array (0 to 3) of std_logic_vector(1 downto 0); -- 4 words of 2bit
type word8b_4array_type is array (0 to 3) of std_logic_vector(7 downto 0); -- 4 words of 8bit
type word10b_4array_type is array (0 to 3) of std_logic_vector(9 downto 0); -- 4 words of 10bit
type word10b_4array_8array_type is array (0 to 7) of word10b_4array_type; -- 8 groups of {4 words of 10bit}, one group per alignment
--
type isk_8array_type is array (0 to 7) of std_logic_vector(1 downto 0); -- 8 words of 2bit
type word8b_8array_type is array (0 to 7) of std_logic_vector(7 downto 0); -- 8 words of 8bit
type word10b_8array_type is array (0 to 7) of std_logic_vector(9 downto 0); -- 8 words of 10bit
type word10b_8array_16array_type is array (0 to 15) of word10b_8array_type; -- 16 groups of {8 words of 10bit}, one group per alignment
-------------------------------------------------------------------
-- 7 and 5 entry arrays of 16 input lines, 16bit line per EGROUP
-------------------------------------------------------------------
type from1GBTdata_array_type is array (0 to 6) of std_logic_vector(15 downto 0);
type to1GBTdata_array_type is array (0 to 4) of std_logic_vector(15 downto 0);
type to1GBTdataNcode_array_type is array (0 to 4) of std_logic_vector(17 downto 0);
-------------------------------------------------------------------
-- N entry array of 16 output lines, 16bit output line per EGROUP
-------------------------------------------------------------------
type GBTdata_array_type is array ( NATURAL RANGE <>) of std_logic_vector(15 downto 0);
-------------------------------------------------------------------
-- GBT_NUM entry arrays
-------------------------------------------------------------------
type ic_data_array_type is array ( NATURAL RANGE <>) of std_logic_vector(7 downto 0);
type cr_DIN_array_type is array ( NATURAL RANGE <>) of from1GBTdata_array_type;
type cr_DOUT_array_type is array ( NATURAL RANGE <>) of to1GBTdata_array_type;
type cr_8MSbs_array_type is array ( NATURAL RANGE <>) of std_logic_vector(7 downto 0);
type cr_4bit_array_type is array ( NATURAL RANGE <>) of std_logic_vector(3 downto 0);
type TTCin_array_type is array ( NATURAL RANGE <>) of std_logic_vector(9 downto 0);
type DownFifoFull_mon_array_type is array ( NATURAL RANGE <>) of std_logic_vector(58 downto 0);
type fmch_monitor_array_type is array ( NATURAL RANGE <>) of std_logic_vector(7 downto 0);
type busyOut_array_type is array ( NATURAL RANGE <>) of std_logic_vector(56 downto 0);
-------------------------------------------------------------------
-- Central Router configuration register arrays
-------------------------------------------------------------------
type crDownstreamConfig_type is array (0 to 7) of std_logic_vector(63 downto 0);
type crUpstreamConfig_type is array (0 to 5) of std_logic_vector(63 downto 0);
-------------------------------------------------------------------
-- 256-bit fifo out, one per GBT
-------------------------------------------------------------------
type d256b_array_type is array (natural range <>) of std_logic_vector(255 downto 0);
type txrx33b_type is array (natural range <>) of std_logic_vector(32 downto 0);
type GBTdm_data_array_type is array ( NATURAL RANGE <>) of std_logic_vector(255 downto 0);
type GBTdm_dsdata_array_type is array ( NATURAL RANGE <>) of std_logic_vector(31 downto 0);
type d32bit_array_type is array (0 to 255) of std_logic_vector(31 downto 0);
type d32bit_array32_type is array (0 to 31) of std_logic_vector(31 downto 0);
-------------------------------------------------------------------
-- 8 entry array of 8bit input
-------------------------------------------------------------------
type EPROC_FIFO_DIN_array_type is array (0 to 7) of std_logic_vector(7 downto 0);
type EPROC_FIFO_DIN_CODE_array_type is array (0 to 7) of std_logic_vector(1 downto 0);
-------------------------------------------------------------------
-- BLOCK size definition [in 16bit words]
-- chunck can span on part of a BLOCK or on several BLOCKs
-------------------------------------------------------------------
constant BLOCK_WORDn : std_logic_vector(9 downto 0) := "1000000000"; -- = 512 (number of 16-bit words in a block)
constant BLOCK_WORD32n : std_logic_vector(8 downto 0) := "100000000"; -- = 256 (number of 32-bit words in a block)
-------------------------------------------------------------------
-- 8b10b encoding / decoding parameters
-------------------------------------------------------------------
-- 1. 10-bit values
--- comma / idle character
constant COMMAp : std_logic_vector (9 downto 0) := "0011111010"; -- -K.28.5
constant COMMAn : std_logic_vector (9 downto 0) := "1100000101"; -- +K.28.5
--- start-of-chunk and end-of-chunk characters
constant EOCp : std_logic_vector (9 downto 0) := "0011110110"; -- -K.28.6
constant EOCn : std_logic_vector (9 downto 0) := "1100001001"; -- +K.28.6
constant SOCp : std_logic_vector (9 downto 0) := "0011111001"; -- -K.28.1
constant SOCn : std_logic_vector (9 downto 0) := "1100000110"; -- +K.28.1
--- start-of-busy and end-of-busy characters
constant SOBp : std_logic_vector (9 downto 0) := "0011110101"; -- -K.28.2
constant SOBn : std_logic_vector (9 downto 0) := "1100001010"; -- +K.28.2
constant EOBp : std_logic_vector (9 downto 0) := "0011110011"; -- -K.28.3
constant EOBn : std_logic_vector (9 downto 0) := "1100001100"; -- +K.28.3
-- 2. 8-bit values
constant Kchar_comma : std_logic_vector (7 downto 0) := "10111100"; -- K28.5
constant Kchar_eop : std_logic_vector (7 downto 0) := "11011100"; -- K28.6
constant Kchar_sop : std_logic_vector (7 downto 0) := "00111100"; -- K28.1
constant Kchar_sob : std_logic_vector (7 downto 0) := "01011100"; -- K28.2
constant Kchar_eob : std_logic_vector (7 downto 0) := "01111100"; -- K28.3
-------------------------------------------------------------------
-- HDLC encoding / decoding parameters
-------------------------------------------------------------------
constant HDLC_flag : std_logic_vector(7 downto 0) := "01111110";
-------------------------------------------------------------------
-- TTC ToHost Data type
-------------------------------------------------------------------
type TTC_ToHost_data_type is record
FMT : std_logic_vector(7 downto 0); --byte0
LEN : std_logic_vector(7 downto 0); --byte1
reserved0 : std_logic_vector(3 downto 0); --byte2
BCID : std_logic_vector(11 downto 0); --byte2,3
XL1ID : std_logic_vector(7 downto 0); --byte4
L1ID : std_logic_vector(23 downto 0); --byte 5,6,7
orbit : std_logic_vector(31 downto 0); --byte 8,9,10,11
trigger_type : std_logic_vector(15 downto 0); --byte 12,13
reserved1 : std_logic_vector(15 downto 0); --byte 14,15
L0ID : std_logic_vector(31 downto 0); --byte 16,17,18,19
data_rdy : std_logic;
end record;
----------------------------------------------------------------------------------
-- 7 EGROUPs configuration parameters:
----------------------------------------------------------------------------------
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- MATLAB generated parameters, consistent with GBT LINK DATA EMULATOR .coe files
--<< begin
--
-- 1. EPROC_ENA_bits 15 bit vector per EGROUP (15 EPROCs in one EGROUP)
-- [EPROC_IN2 EPROC_IN2 EPROC_IN2 EPROC_IN2 EPROC_IN2 EPROC_IN2 EPROC_IN2 EPROC_IN2 EPROC_IN4 EPROC_IN4 EPROC_IN4 EPROC_IN4 EPROC_IN8 EPROC_IN8 EPROC_IN16]
--
type EPROC_ENA_bits_array_type is array (0 to 7) of std_logic_vector(14 downto 0);
constant EPROC_ENA_bits_array : EPROC_ENA_bits_array_type :=(
"000000000000110",
"000000001111000",
"000000000000001",
"111111110000000",
"110011000101000",
"001100111010000",
"110011000101000",
"100000000000000");
--
-- 2. PATH_ENCODING, 16 bit vector per EGROUP (2 bits per PATH, 8 PATHs in one EGROUP)
-- for each of 8 output paths: "00"=non, "01"=8b10b, "10"=HDLC
--
type EPROC_ENCODING_array_type is array (0 to 7) of std_logic_vector(15 downto 0);
constant PATH_ENCODING_array : EPROC_ENCODING_array_type :=(
"0101010101010101",
"0101010101010101",
"0101010101010101",
"0101010101010101",
"0101010101010101",
"0101010101010101",
"0101010101010101",
"1000000000000000");
--
-- 3. Maximal valid CHUNK length for data truncation
-- per GBT channel, 3MSBs per Eproc type
--
constant MAX_CHUNK_LEN_array : std_logic_vector(11 downto 0) := "000000000000";
--<< end
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
constant zeros17bits : std_logic_vector(16 downto 0) := (others=>'0');
constant zeros21bits : std_logic_vector(20 downto 0) := (others =>'0');
-------------------------------------------------------------------
-- initial conf. constants for the case of {TTC_test_mode = false}
--
-- NOT a TTC test, initial configuration is generated using Matlab,
-- according to the selected options in a gui.
-------------------------------------------------------------------
constant CR_TH_EGROUP0_CTRL_C :std_logic_vector(63 downto 0) :=(
zeros21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(0) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(0)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP1_CTRL_C :std_logic_vector(63 downto 0) :=(
zeros21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(1) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(1)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP2_CTRL_C :std_logic_vector(63 downto 0) :=(
zeros21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(2) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(2)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP3_CTRL_C :std_logic_vector(63 downto 0) :=(
zeros21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(3) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(3)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP4_CTRL_C :std_logic_vector(63 downto 0) :=(
zeros21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(4) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(4)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP5_CTRL_C :std_logic_vector(63 downto 0) :=(
zeros21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(5) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(5)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP6_CTRL_C :std_logic_vector(63 downto 0) :=(
zeros21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(6) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(6)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP7_CTRL_C :std_logic_vector(63 downto 0) :=(
zeros21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(7) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(7)); -- 15 bit: (14 downto 0)
-------------------------------------------------------------------
-- Initial configuration of the from-host path:
-- matched the initial configuration of the to-host path
-- (and the initial contents of the GBT data emulators)
-- this allows for the loop-back test without reconfiguration
-------------------------------------------------------------------
constant CR_FH_EGROUP0_CTRL_C : std_logic_vector(63 downto 0) := (zeros17bits &
"00" & PATH_ENCODING_array(0)(15 downto 14) &
"00" & PATH_ENCODING_array(0)(13 downto 12) &
"00" & PATH_ENCODING_array(0)(11 downto 10) &
"00" & PATH_ENCODING_array(0)(9 downto 8) &
"00" & PATH_ENCODING_array(0)(7 downto 6) &
"00" & PATH_ENCODING_array(0)(5 downto 4) &
"00" & PATH_ENCODING_array(0)(3 downto 2) &
"00" & PATH_ENCODING_array(0)(1 downto 0) &
EPROC_ENA_bits_array(0));
constant CR_FH_EGROUP1_CTRL_C : std_logic_vector(63 downto 0) := (zeros17bits &
"00" & PATH_ENCODING_array(1)(15 downto 14) &
"00" & PATH_ENCODING_array(1)(13 downto 12) &
"00" & PATH_ENCODING_array(1)(11 downto 10) &
"00" & PATH_ENCODING_array(1)(9 downto 8) &
"00" & PATH_ENCODING_array(1)(7 downto 6) &
"00" & PATH_ENCODING_array(1)(5 downto 4) &
"00" & PATH_ENCODING_array(1)(3 downto 2) &
"00" & PATH_ENCODING_array(1)(1 downto 0) &
EPROC_ENA_bits_array(1));
constant CR_FH_EGROUP2_CTRL_C : std_logic_vector(63 downto 0) := (zeros17bits &
"00" & PATH_ENCODING_array(2)(15 downto 14) &
"00" & PATH_ENCODING_array(2)(13 downto 12) &
"00" & PATH_ENCODING_array(2)(11 downto 10) &
"00" & PATH_ENCODING_array(2)(9 downto 8) &
"00" & PATH_ENCODING_array(2)(7 downto 6) &
"00" & PATH_ENCODING_array(2)(5 downto 4) &
"00" & PATH_ENCODING_array(2)(3 downto 2) &
"00" & PATH_ENCODING_array(2)(1 downto 0) &
EPROC_ENA_bits_array(2));
constant CR_FH_EGROUP3_CTRL_C : std_logic_vector(63 downto 0) := (zeros17bits &
"00" & PATH_ENCODING_array(3)(15 downto 14) &
"00" & PATH_ENCODING_array(3)(13 downto 12) &
"00" & PATH_ENCODING_array(3)(11 downto 10) &
"00" & PATH_ENCODING_array(3)(9 downto 8) &
"00" & PATH_ENCODING_array(3)(7 downto 6) &
"00" & PATH_ENCODING_array(3)(5 downto 4) &
"00" & PATH_ENCODING_array(3)(3 downto 2) &
"00" & PATH_ENCODING_array(3)(1 downto 0) &
EPROC_ENA_bits_array(3));
constant CR_FH_EGROUP4_CTRL_C : std_logic_vector(63 downto 0) := (zeros17bits &
"00" & PATH_ENCODING_array(4)(15 downto 14) &
"00" & PATH_ENCODING_array(4)(13 downto 12) &
"00" & PATH_ENCODING_array(4)(11 downto 10) &
"00" & PATH_ENCODING_array(4)(9 downto 8) &
"00" & PATH_ENCODING_array(4)(7 downto 6) &
"00" & PATH_ENCODING_array(4)(5 downto 4) &
"00" & PATH_ENCODING_array(4)(3 downto 2) &
"00" & PATH_ENCODING_array(4)(1 downto 0) &
EPROC_ENA_bits_array(4));
constant CR_FH_EGROUP5_CTRL_C : std_logic_vector(63 downto 0) := (zeros17bits &
"00" & PATH_ENCODING_array(7)(15 downto 14) &
"00" & PATH_ENCODING_array(7)(13 downto 12) &
"00" & PATH_ENCODING_array(7)(11 downto 10) &
"00" & PATH_ENCODING_array(7)(9 downto 8) &
"00" & PATH_ENCODING_array(7)(7 downto 6) &
"00" & PATH_ENCODING_array(7)(5 downto 4) &
"00" & PATH_ENCODING_array(7)(3 downto 2) &
"00" & PATH_ENCODING_array(7)(1 downto 0) &
EPROC_ENA_bits_array(7));
-------------------------------------------------------------------
-- initial configuration of the from- and to-host paths
-- for the case of {TTC_test_mode = true}
-- TTC test mode, normal GBT mode only!
-- Central Router generic 'wideMode' has to be set false.
-- Congifuration of TTC-from-host matches
-- the direct-to-host congifuration.
-- Trom-Host is TTC, to-Host is direct data.
-------------------------------------------------------------------
--
-- egroup0: 8 x EPROCx2s. direct data: TTC-0 (2bit) [B-chan L1A]
constant CR_FH_EGROUP0_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros17bits & x"33333333" & "111111110000000"; -- TTC-0
constant CR_TH_EGROUP0_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros21bits & "000000000000" & "0000000000000000" & "111111110000000";
-- egroup1: 4 x EPROCx4s. direct data: TTC-1 (4bit) [B-chan ECR BCR L1A]
constant CR_FH_EGROUP1_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros17bits & x"03030303" & "000000001111000"; -- TTC-1
constant CR_TH_EGROUP1_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros21bits & "000000000000" & "0000000000000000" & "000000001111000";
-- egroup2: 4 x EPROCx4s. direct data: TTC-2 (4bit) [Brcst[2] ECR BCR L1A]
constant CR_FH_EGROUP2_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros17bits & x"04040404" & "000000001111000"; -- TTC-2
constant CR_TH_EGROUP2_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros21bits & "000000000000" & "0000000000000000" & "000000001111000";
-- egroup3: 2 x EPROCx8s. direct data: TTC-3 (8bit) [B-chan Brcst[5] Brcst[4] Brcst[3] Brcst[2] ECR BCR L1A]
constant CR_FH_EGROUP3_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros17bits & x"00300030" & "000000000000110"; -- TTC-3
constant CR_TH_EGROUP3_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros21bits & "000000000000" & "0000000000000000" & "000000000000110";
-- egroup4: 2 x EPROCx8s. direct data: TTC-4 (8bit) [Brcst[6] Brcst[5] Brcst[4] Brcst[3] Brcst[2] ECR BCR L1A]
constant CR_FH_EGROUP4_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros17bits & x"00400040" & "000000000000110"; -- TTC-4
constant CR_TH_EGROUP4_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros21bits & "000000000000" & "0000000000000000" & "000000000000110";
-- egroup7: 8 x EPROCx2s. direct data: TTC-0 (2bit) [B-chan L1A]
constant CR_FH_EGROUP5_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros17bits & x"33333333" & "111111110000000"; -- TTC-0
constant CR_TH_EGROUP7_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := zeros21bits & "000000000000" & "0000000000000000" & "000000000000110";
--
--
constant CR_TH_EGROUP5_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := (others=>'0');
constant CR_TH_EGROUP6_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := (others=>'0');
--
--
end package centralRouter_package ;
| gpl-3.0 | 93ac66d3111bbc68acbcffbe95dcd05a | 0.566076 | 3.381996 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4088/Elink2FIFO.vhd | 1 | 6,754 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 17/08/2015
--! Module Name: Elink2FIFO
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
--! consists of 1 E-path
entity Elink2FIFO is
generic (
InputDataRate : integer := 80 -- 80 or 160 MHz
);
port (
clk40 : in std_logic;
clk80 : in std_logic;
clk160 : in std_logic;
RSTclk40 : in std_logic;
------
DATA1bitIN : in std_logic;
------
efifoRclk : in std_logic;
efifoRe : in std_logic;
efifoHF : out std_logic; -- half-full flag: 1 KByte block is ready to be read
efifoDout : out std_logic_vector (15 downto 0)
------
);
end Elink2FIFO;
architecture Behavioral of Elink2FIFO is
----------------------------------
----------------------------------
component EPROC_IN2
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
ENA : in std_logic;
ENCODING : in std_logic_vector (1 downto 0);
EDATA_IN : in std_logic_vector (1 downto 0);
DATA_OUT : out std_logic_vector (9 downto 0);
DATA_RDY : out std_logic
);
end component;
----------------------------------
----------------------------------
component EPROC_IN4
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
ENA : in std_logic;
ENCODING : in std_logic_vector (1 downto 0);
EDATA_IN : in std_logic_vector (3 downto 0);
DATA_OUT : out std_logic_vector (9 downto 0);
DATA_RDY : out std_logic
);
end component;
----------------------------------
----------------------------------
component EPROC_FIFO_DRIVER
generic (
GBTid : integer := 0;
egroupID : integer := 0;
epathID : integer := 0
);
port (
bitCLKx4 : in std_logic;
rst : in std_logic;
FIFOrst_state : in std_logic;
maxCLEN : in std_logic_vector (2 downto 0);
DIN : in std_logic_vector (9 downto 0);
DIN_RDY : in std_logic;
xoff : in std_logic;
wordOUT : out std_logic_vector (15 downto 0);
wordOUT_RDY : out std_logic
);
end component;
----------------------------------
----------------------------------
component EPATH_FIFO_WRAP
port (
rst : in std_logic;
FIFO_RESET_STATE : out std_logic;
wr_clk : in std_logic;
rd_clk : in std_logic;
din : in std_logic_vector(15 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(15 downto 0);
full : out std_logic;
almost_full : out std_logic;
empty : out std_logic;
rd_data_count : out std_logic_vector(9 downto 0);
prog_full : out std_logic
);
end component;
----------------------------------
----------------------------------
--
constant maxClen : std_logic_vector (11 downto 0) := (others => '0'); -- no limit on packet size here
signal DATA2bitIN, shreg2bit : std_logic_vector (1 downto 0) := (others => '0');
signal DATA4bitIN, shreg4bit : std_logic_vector (3 downto 0) := (others => '0');
signal DATA_OUT : std_logic_vector(9 downto 0);
signal DATA_RDY, FIFO_RESET_STATE, almost_full, BWORD_RDY : std_logic;
signal BWORD : std_logic_vector(15 downto 0);
----
begin
------------------------------------------------------------
-- E-PATH case 80 MHz
------------------------------------------------------------
InputDataRate80: if InputDataRate = 80 generate
--
process(clk80)
begin
if clk80'event and clk80 = '1' then
shreg2bit <= DATA1bitIN & shreg2bit(1);
end if;
end process;
--
process(clk40)
begin
if clk40'event and clk40 = '1' then
DATA2bitIN <= shreg2bit;
end if;
end process;
---
EPROC_IN2bit: EPROC_IN2
port map (
bitCLK => clk40,
bitCLKx2 => clk80,
bitCLKx4 => clk160,
rst => RSTclk40,
ENA => '1',
ENCODING => "10", -- 8b10b
EDATA_IN => DATA2bitIN,
DATA_OUT => DATA_OUT,
DATA_RDY => DATA_RDY
);
end generate InputDataRate80;
------------------------------------------------------------
-- E-PATH case 160 MHz
------------------------------------------------------------
InputDataRate160: if InputDataRate = 160 generate
--
process(clk160)
begin
if clk160'event and clk160 = '1' then
shreg4bit <= DATA1bitIN & shreg4bit(3 downto 1);
end if;
end process;
--
process(clk40)
begin
if clk40'event and clk40 = '1' then
DATA4bitIN <= shreg4bit;
end if;
end process;
---
EPROC_IN4bit: EPROC_IN4
port map (
bitCLK => clk40,
bitCLKx2 => clk80,
bitCLKx4 => clk160,
rst => RSTclk40,
ENA => '1',
ENCODING => "10", -- 8b10b
EDATA_IN => DATA4bitIN,
DATA_OUT => DATA_OUT,
DATA_RDY => DATA_RDY
);
end generate InputDataRate160;
------------------------------------------------------------
-- EPATH FIFO DRIVER
------------------------------------------------------------
efd: EPROC_FIFO_DRIVER
generic map(
GBTid => 0, -- no use
egroupID => 0, -- no use
epathID => 0 -- no use
)
port map (
bitCLKx4 => clk160,
rst => RSTclk40,
FIFOrst_state => FIFO_RESET_STATE,
maxCLEN => maxClen,
DIN => DATA_OUT,
DIN_RDY => DATA_RDY,
xoff => almost_full,
wordOUT => BWORD, -- block word
wordOUT_RDY => BWORD_RDY
);
------------------------------------------------------------
-- EPATH FIFOs
------------------------------------------------------------
efw: EPATH_FIFO_WRAP
port map (
rst => RSTclk40,
FIFO_RESET_STATE => FIFO_RESET_STATE,
wr_clk => clk160,
rd_clk => efifoRclk,
din => BWORD,
wr_en => BWORD_RDY,
rd_en => efifoRe,
dout => efifoDout,
full => open,
almost_full => almost_full,
empty => open,
rd_data_count => open,
prog_full => efifoHF -- Half-Full - output: 1K block is ready
);
end Behavioral;
| gpl-3.0 | 14ba8ce6a704615d506a889a796aa3b8 | 0.456618 | 3.688695 | false | false | false | false |
GustaMagik/RSA_Security_Token | VHDL_code/ver_A/RSA_Security_Token_Keyboard_Version/mem_array.vhd | 1 | 2,870 |
--Copyright 2017 Gustav Örtenberg
--Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
--
--1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
--
--2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the
--documentation and/or other materials provided with the distribution.
--
--3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this
--software without specific prior written permission.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS
--BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
--GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
--LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use std.textio.ALL;
entity mem_array is
GENERIC(
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 6;
INIT_FILE : string := "RAM.mif");
Port(
ADDR : in STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
DATAIN : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
clk : in std_logic;
WE : in std_logic;
OUTPUT : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0)
);
end mem_array;
architecture dataflow of mem_array is
Type MEMORY_ARRAY is ARRAY (0 to 2**(ADDR_WIDTH)-1) of STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
impure function init_memory_wfile(mif_file_name : in string) return MEMORY_ARRAY is
file mif_file : text open read_mode is mif_file_name;
variable mif_line : line;
variable temp_bv : bit_vector(DATA_WIDTH-1 downto 0);
variable temp_mem : MEMORY_ARRAY;
begin
for i in MEMORY_ARRAY'range loop
readline(mif_file, mif_line);
read(mif_line, temp_bv);
temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
signal memory : MEMORY_ARRAY:=(init_memory_wfile(INIT_FILE));
begin
process(clk, WE)
begin
if (clk'EVENT and clk = '1') then
if (WE = '1') then
memory(to_integer(unsigned(ADDR))) <= DATAIN;
end if;
end if;
end process;
OUTPUT <= memory(to_integer(unsigned(ADDR)));
end dataflow; | bsd-3-clause | 449a82fc63f494a5ff0478a4c9fe2fac | 0.737979 | 3.816489 | false | false | false | false |
tdotu/ra | jk_ff.vhd | 1 | 733 | LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY jk_ff IS
PORT ( clock: IN STD_LOGIC;
j: IN STD_LOGIC;
k: IN STD_LOGIC;
reset: IN STD_LOGIC;
q: OUT STD_LOGIC;
q_neg: OUT STD_LOGIC);
END jk_ff;
ARCHITECTURE behavior OF jk_ff IS
SIGNAL state: STD_LOGIC;
SIGNAL input: STD_LOGIC_VECTOR(1 downto 0);
BEGIN
input <= j & k;
PROCESS(clock, reset) IS BEGIN
IF (reset='1') THEN
state <= '0';
ELSIF(rising_edge(clock)) THEN
CASE(input) IS
WHEN "11" => state <= NOT state;
WHEN "10" => state <= '1';
WHEN "01" => state <= '0';
WHEN "00" => state <= state;
END CASE;
END IF;
END PROCESS;
q <= state;
q_neg <= NOT state;
END behavior; | gpl-3.0 | 7f6f15d892641c921b673e35dd99dc54 | 0.564802 | 2.830116 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/readout/vmm_driver.vhd | 1 | 5,118 | ----------------------------------------------------------------------------------
-- Company: NTU Athens - BNL
-- Engineer: Christos Bakalis ([email protected])
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Christos Bakalis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 25.04.2017 17:45:32
-- Design Name: VMM Driver
-- Module Name: vmm_driver - RTL
-- Project Name: NTUA-BNL VMM3 Readout Firmware
-- Target Devices: Xilinx xc7a200t-2fbg484
-- Tool Versions: Vivado 2016.4
-- Description: This module drives the data from the vmm_readout component
-- to the FIFO2UDP component.
--
-- Dependencies: packet_formation.vhd
--
-- Changelog:
-- 06.06.2017 Simplified the module as the continuous readout mode now uses a buffer
-- as well. (Christos Bakalis)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
entity vmm_driver is
port(
------------------------------------
------ General/PF Interface --------
clk : in std_logic;
drv_enable : in std_logic;
drv_done : out std_logic;
pack_len_drv : out std_logic_vector(11 downto 0);
------------------------------------
----- VMM_RO/FIFO2UDP Interface ----
wr_en_fifo2udp : out std_logic;
rd_en_buff : out std_logic;
vmmWordReady : in std_logic
);
end vmm_driver;
architecture RTL of vmm_driver is
signal wait_cnt : integer range 0 to 15 := 0;
signal packLen_i : unsigned(11 downto 0) := (others => '0');
constant timeout : integer := 15;
type stateType_l0 is (ST_IDLE, ST_WAIT, ST_CHECK_FIFO, ST_RD_LOW, ST_WR_LOW, ST_DONE);
signal state_l0 : stateType_l0 := ST_IDLE;
begin
l0_FSM_drv: process(clk)
begin
if(rising_edge(clk))then
if(drv_enable = '0')then
drv_done <= '0';
wait_cnt <= 0;
rd_en_buff <= '0';
wr_en_fifo2udp <= '0';
packLen_i <= (others => '0');
state_l0 <= ST_IDLE;
else
case state_l0 is
-- reset the counter and begin the process
when ST_IDLE =>
packLen_i <= (others => '0');
state_l0 <= ST_WAIT;
-- stay here for "timeout" cycles for data bus stabilization
when ST_WAIT =>
if(wait_cnt < timeout)then
wait_cnt <= wait_cnt + 1;
state_l0 <= ST_WAIT;
else
wait_cnt <= 0;
state_l0 <= ST_CHECK_FIFO;
end if;
-- read the vmm buffer if there is still data
when ST_CHECK_FIFO =>
if(vmmWordReady = '1')then
rd_en_buff <= '1';
state_l0 <= ST_RD_LOW;
else
rd_en_buff <= '0';
state_l0 <= ST_DONE;
end if;
-- stay here for "timeout" cycles for data bus stabilization
when ST_RD_LOW =>
rd_en_buff <= '0';
if(wait_cnt < timeout)then
wait_cnt <= wait_cnt + 1;
wr_en_fifo2udp <= '0';
state_l0 <= ST_RD_LOW;
else
wait_cnt <= 0;
wr_en_fifo2udp <= '1';
state_l0 <= ST_WR_LOW;
end if;
-- increment the packLen counter
when ST_WR_LOW =>
wr_en_fifo2udp <= '0';
packLen_i <= packLen_i + 1;
state_l0 <= ST_WAIT;
-- stay here until reset by pf
when ST_DONE =>
drv_done <= '1';
when others =>
drv_done <= '0';
wait_cnt <= 0;
rd_en_buff <= '0';
wr_en_fifo2udp <= '0';
packLen_i <= (others => '0');
state_l0 <= ST_IDLE;
end case;
end if;
end if;
end process;
pack_len_drv <= std_logic_vector(packLen_i);
end RTL; | gpl-3.0 | 945c34ce17965601f0485642fbed8ad3 | 0.475186 | 4.068362 | false | false | false | false |
GustaMagik/RSA_Security_Token | VHDL_code/ver_B/RSA_Security_Token_USB_Version/RXD_Controller.vhdl | 1 | 5,705 |
--Copyright 2017 Christoffer Mathiesen, Gustav Örtenberg
--Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
--
--1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
--
--2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the
--documentation and/or other materials provided with the distribution.
--
--3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this
--software without specific prior written permission.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS
--BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
--GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
--LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
entity RXD_Controller is
Generic (Baud_Rate : integer; --Baud of this port
CLOCK_RATE : integer; --Frequency of the CLK. Needed to perform correct sampling
OVERSAMPLES : integer := 4);
Port( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
RXD_PIN : in STD_LOGIC;
RXD_BYTE : out STD_LOGIC_VECTOR(7 downto 0);
VALID_DATA_IN : out STD_LOGIC := '0'
);
end RXD_Controller;
--This module handles reciving of bytes (8 bit) from a serial port (UART)
architecture Behavioral of RXD_Controller is
type STATES is (IDLE, START, DATA, STOP);
signal state : STATES := IDLE;
signal bit_counter : integer range 0 to 8 := 0;
signal middle : STD_LOGIC;
signal over_sampling_done : STD_LOGIC := '0';
signal SAMPLE_COUNTER : integer := 0;
signal SAMPLE_COUNT : integer range 0 to OVERSAMPLES;
signal SAMPLE_NOW : STD_LOGIC;
begin
-- Handle the oversampler
oversampler: process (CLK)
constant RATE_OF_SAMPLING : integer := CLOCK_RATE/BAUD_RATE/OVERSAMPLES; --How many cycles beween each sample
variable CURRENT_SAMPLE_COUNTER : integer := 0;
begin
if rising_edge(CLK) then
SAMPLE_NOW <= '0'; --Default is to NOT sample now
over_sampling_done <= '0'; --Default is that the sampling is not done
middle <= '0'; --Default is that the sample is NOT the middle one
if RESET = '1' then --If reset signal
SAMPLE_COUNTER <= 0;
SAMPLE_COUNT <= 0;--reset counter
elsif STATE = IDLE then
SAMPLE_COUNTER <= 0;
SAMPLE_COUNT <= 0;
--If not reset perform standard behaviour
elsif STATE /= IDLE then --We need sampling in every state but IDLE
CURRENT_SAMPLE_COUNTER := SAMPLE_COUNTER;
if CURRENT_SAMPLE_COUNTER < RATE_OF_SAMPLING then --If less than the sampling rate we are to increase the counter
SAMPLE_COUNTER <= SAMPLE_COUNTER + 1;
else --otherwise we put SAMPLE_NOW to high and reset the counter
SAMPLE_COUNTER <= 0;
SAMPLE_NOW <= '1';
SAMPLE_COUNT <= SAMPLE_COUNT + 1; --count which sample it was
--count the amount of samples done and when the 4th is done
if SAMPLE_COUNT = OVERSAMPLES - 1 then --signal that the oversampling is done
over_sampling_done <= '1';
SAMPLE_COUNT <= 0;
end if;
if SAMPLE_COUNT = OVERSAMPLES/2-1 then --signal that we have done half of the samples
middle <= '1';
end if;
end if;
end if;
end if;
end process;
-- Compute the next state
stateProcess: process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
state <= IDLE;
else
case state is
when IDLE =>
if RXD_PIN = '0' then --Start bit?
STATE <= START;
end if;
when START =>
--check if start bit
if middle = '1' then
if RXD_PIN = '0' then --Start bit confirmed
state <= DATA;
else --Start bit not confirmed
state <= IDLE;
end if;
end if;
when DATA => --Receive data
if bit_counter >= 8 then --All bits accounted for
state <= STOP; --Set stop bit
VALID_DATA_IN <= '1'; --Signal that valid data is on the bus
end if;
when STOP =>
VALID_DATA_IN <= '0'; --Stop signaling as we only want this flag to be high one cycle
if middle = '1' and RXD_PIN = '1' then --when enough time has passed and the pin is reset to IDLE state
state <= IDLE; --go back to IDLE
end if;
when others =>
state <= IDLE;
end case;
end if;
end if;
end process stateProcess;
-- Tracking the bits
bitTracker: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
bit_counter <= 0;
else
if middle = '1' then
if state = START then
bit_counter <= 0;
elsif state = DATA then
bit_counter <= bit_counter + 1;
end if;
end if;
end if;
end if;
end process bitTracker;
-- Controlling the data
readyController: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then --Reset regiseters and signal to known value
RXD_BYTE <= x"00";
else
if middle = '1' then
if state = DATA AND bit_counter < 8 then
RXD_BYTE(bit_counter) <= RXD_PIN;
elsif state = STOP then
end if;
end if;
end if;
end if;
end process readyController;
end Behavioral; | bsd-3-clause | e64ed2f54faa83f1f9fd1e2c9464d664 | 0.694128 | 3.640715 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/sgmii_10_100_1000/ipcore_dir/temac_10_100_1000/example_design/fifo/temac_10_100_1000_ten_100_1g_eth_fifo.vhd | 2 | 9,987 | --------------------------------------------------------------------------------
-- Title : 10/100/1G Ethernet FIFO
-- Version : 1.2
-- Project : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : temac_10_100_1000_ten_100_1g_eth_fifo.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2008 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This is the top level wrapper for the 10/100/1G Ethernet FIFO.
-- The top level wrapper consists of individual FIFOs on the
-- transmitter path and on the receiver path.
--
-- Each path consists of an 8 bit local link to 8 bit client
-- interface FIFO.
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------------------------------------------------
-- The entity declaration for the FIFO
--------------------------------------------------------------------------------
entity temac_10_100_1000_ten_100_1g_eth_fifo is
generic (
FULL_DUPLEX_ONLY : boolean := true); -- If fifo is to be used only in full
-- duplex set to true for optimised implementation
port (
tx_fifo_aclk : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tlast : in std_logic;
tx_axis_fifo_tready : out std_logic;
tx_mac_aclk : in std_logic;
tx_mac_resetn : in std_logic;
tx_axis_mac_tdata : out std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : out std_logic;
tx_axis_mac_tlast : out std_logic;
tx_axis_mac_tready : in std_logic;
tx_axis_mac_tuser : out std_logic;
tx_fifo_overflow : out std_logic;
tx_fifo_status : out std_logic_vector(3 downto 0);
tx_collision : in std_logic;
tx_retransmit : in std_logic;
rx_fifo_aclk : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tlast : out std_logic;
rx_axis_fifo_tready : in std_logic;
rx_mac_aclk : in std_logic;
rx_mac_resetn : in std_logic;
rx_axis_mac_tdata : in std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : in std_logic;
rx_axis_mac_tlast : in std_logic;
rx_axis_mac_tready : out std_logic;
rx_axis_mac_tuser : in std_logic;
rx_fifo_status : out std_logic_vector(3 downto 0);
rx_fifo_overflow : out std_logic
);
end temac_10_100_1000_ten_100_1g_eth_fifo;
architecture RTL of temac_10_100_1000_ten_100_1g_eth_fifo is
component temac_10_100_1000_rx_client_fifo
port (
-- User-side (read-side) AxiStream interface
rx_fifo_aclk : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tlast : out std_logic;
rx_axis_fifo_tready : in std_logic;
-- MAC-side (write-side) AxiStream interface
rx_mac_aclk : in std_logic;
rx_mac_resetn : in std_logic;
rx_axis_mac_tdata : in std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : in std_logic;
rx_axis_mac_tlast : in std_logic;
rx_axis_mac_tready : out std_logic;
rx_axis_mac_tuser : in std_logic;
-- FIFO status and overflow indication,
-- synchronous to write-side (rx_mac_aclk) interface
fifo_status : out std_logic_vector(3 downto 0);
fifo_overflow : out std_logic
);
end component;
component temac_10_100_1000_tx_client_fifo
generic (
FULL_DUPLEX_ONLY : boolean := false);
port (
-- User-side (write-side) AxiStream interface
tx_fifo_aclk : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tlast : in std_logic;
tx_axis_fifo_tready : out std_logic;
-- MAC-side (read-side) AxiStream interface
tx_mac_aclk : in std_logic;
tx_mac_resetn : in std_logic;
tx_axis_mac_tdata : out std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : out std_logic;
tx_axis_mac_tlast : out std_logic;
tx_axis_mac_tready : in std_logic;
tx_axis_mac_tuser : out std_logic;
-- FIFO status and overflow indication,
-- synchronous to write-side (tx_user_aclk) interface
fifo_overflow : out std_logic;
fifo_status : out std_logic_vector(3 downto 0);
-- FIFO collision and retransmission requests from MAC
tx_collision : in std_logic;
tx_retransmit : in std_logic
);
end component;
begin
------------------------------------------------------------------------------
-- Instantiate the Transmitter FIFO
------------------------------------------------------------------------------
tx_fifo_i : temac_10_100_1000_tx_client_fifo
generic map(
FULL_DUPLEX_ONLY => FULL_DUPLEX_ONLY
)
port map(
tx_fifo_aclk => tx_fifo_aclk,
tx_fifo_resetn => tx_fifo_resetn,
tx_axis_fifo_tdata => tx_axis_fifo_tdata,
tx_axis_fifo_tvalid => tx_axis_fifo_tvalid,
tx_axis_fifo_tlast => tx_axis_fifo_tlast,
tx_axis_fifo_tready => tx_axis_fifo_tready,
tx_mac_aclk => tx_mac_aclk,
tx_mac_resetn => tx_mac_resetn,
tx_axis_mac_tdata => tx_axis_mac_tdata,
tx_axis_mac_tvalid => tx_axis_mac_tvalid,
tx_axis_mac_tlast => tx_axis_mac_tlast,
tx_axis_mac_tready => tx_axis_mac_tready,
tx_axis_mac_tuser => tx_axis_mac_tuser,
fifo_overflow => tx_fifo_overflow,
fifo_status => tx_fifo_status,
tx_collision => tx_collision,
tx_retransmit => tx_retransmit
);
------------------------------------------------------------------------------
-- Instantiate the Receiver FIFO
------------------------------------------------------------------------------
rx_fifo_i : temac_10_100_1000_rx_client_fifo
port map(
rx_fifo_aclk => rx_fifo_aclk,
rx_fifo_resetn => rx_fifo_resetn,
rx_axis_fifo_tdata => rx_axis_fifo_tdata,
rx_axis_fifo_tvalid => rx_axis_fifo_tvalid,
rx_axis_fifo_tlast => rx_axis_fifo_tlast,
rx_axis_fifo_tready => rx_axis_fifo_tready,
rx_mac_aclk => rx_mac_aclk,
rx_mac_resetn => rx_mac_resetn,
rx_axis_mac_tdata => rx_axis_mac_tdata,
rx_axis_mac_tvalid => rx_axis_mac_tvalid,
rx_axis_mac_tlast => rx_axis_mac_tlast,
rx_axis_mac_tready => rx_axis_mac_tready,
rx_axis_mac_tuser => rx_axis_mac_tuser,
fifo_status => rx_fifo_status,
fifo_overflow => rx_fifo_overflow
);
end RTL;
| gpl-3.0 | b1f36eb6802410a52ef2ef8bc62836e1 | 0.549715 | 3.884481 | false | false | false | false |
adelapie/noekeon | tb_noekeon.vhd | 2 | 4,969 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_noekeon IS
END tb_noekeon;
ARCHITECTURE behavior OF tb_noekeon IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT noekeon
PORT(
clk : IN std_logic;
rst : IN std_logic;
enc : IN std_logic;
a_0_in : IN std_logic_vector(31 downto 0);
a_1_in : IN std_logic_vector(31 downto 0);
a_2_in : IN std_logic_vector(31 downto 0);
a_3_in : IN std_logic_vector(31 downto 0);
k_0_in : IN std_logic_vector(31 downto 0);
k_1_in : IN std_logic_vector(31 downto 0);
k_2_in : IN std_logic_vector(31 downto 0);
k_3_in : IN std_logic_vector(31 downto 0);
a_0_out : OUT std_logic_vector(31 downto 0);
a_1_out : OUT std_logic_vector(31 downto 0);
a_2_out : OUT std_logic_vector(31 downto 0);
a_3_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal enc : std_logic := '0';
signal a_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_3_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_3_in : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal a_0_out : std_logic_vector(31 downto 0);
signal a_1_out : std_logic_vector(31 downto 0);
signal a_2_out : std_logic_vector(31 downto 0);
signal a_3_out : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: noekeon PORT MAP (
clk => clk,
rst => rst,
enc => enc,
a_0_in => a_0_in,
a_1_in => a_1_in,
a_2_in => a_2_in,
a_3_in => a_3_in,
k_0_in => k_0_in,
k_1_in => k_1_in,
k_2_in => k_2_in,
k_3_in => k_3_in,
a_0_out => a_0_out,
a_1_out => a_1_out,
a_2_out => a_2_out,
a_3_out => a_3_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + clk_period;
rst <= '1';
enc <= '0';
a_0_in <= X"2a78421b";
a_1_in <= X"87c7d092";
a_2_in <= X"4f26113f";
a_3_in <= X"1d1349b2";
k_0_in <= X"b1656851";
k_1_in <= X"699e29fa";
k_2_in <= X"24b70148";
k_3_in <= X"503d2dfc";
wait for clk_period;
rst <= '0';
wait for clk_period*15 + clk_period/2;
assert a_0_out = X"e2f687e0"
report "ENCRYPT ERROR (a_0)" severity FAILURE;
assert a_1_out = X"7b75660f"
report "ENCRYPT ERROR (a_1)" severity FAILURE;
assert a_2_out = X"fc372233"
report "ENCRYPT ERROR (a_2)" severity FAILURE;
assert a_3_out = X"bc47532c"
report "ENCRYPT ERROR (a_3)" severity FAILURE;
wait for clk_period + clk_period/2;
rst <= '1';
enc <= '1';
a_0_in <= X"e2f687e0";
a_1_in <= X"7b75660f";
a_2_in <= X"fc372233";
a_3_in <= X"bc47532c";
k_0_in <= X"b1656851";
k_1_in <= X"699e29fa";
k_2_in <= X"24b70148";
k_3_in <= X"503d2dfc";
wait for clk_period;
rst <= '0';
wait for clk_period*15 + clk_period/2;
assert a_0_out = X"2a78421b"
report "DECRYPT ERROR (a_0)" severity FAILURE;
assert a_1_out = X"87c7d092"
report "DECRYPT ERROR (a_1)" severity FAILURE;
assert a_2_out = X"4f26113f"
report "DECRYPT ERROR (a_2)" severity FAILURE;
assert a_3_out = X"1d1349b2"
report "DECRYPT ERROR (a_3)" severity FAILURE;
wait;
end process;
END;
| gpl-3.0 | dbf07afd6d31ad0092fe49437e8c91ff | 0.560676 | 2.964797 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/UDP_Complete_nomac.vhd | 2 | 10,313 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:38:49 06/13/2011
-- Design Name:
-- Module Name: UDP_Complete_nomac - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - separated RX and TX clocks
-- Revision 0.03 - Added mac_tx_tfirst
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity UDP_Complete_nomac is
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store
);
Port (
-- UDP TX signals
udp_tx_start : in std_logic; -- indicates req to tx UDP
udp_txi : in udp_tx_type; -- UDP tx cxns
udp_tx_result : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
udp_tx_data_out_ready : out std_logic; -- indicates udp_tx is ready to take data
-- UDP RX signals
udp_rx_start : out std_logic; -- indicates receipt of udp header
udp_rxo : out udp_rx_type;
-- IP RX signals
ip_rx_hdr : out ipv4_rx_header_type;
-- system signals
rx_clk : in std_logic;
tx_clk : in std_logic;
reset : in std_logic;
our_ip_address : in std_logic_vector (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
control : in udp_control_type;
-- status signals
arp_pkt_count : out std_logic_vector(7 downto 0); -- count of arp pkts received
ip_pkt_count : out std_logic_vector(7 downto 0); -- number of IP pkts received for us
-- MAC Transmitter
mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx
mac_tx_tvalid : out std_logic; -- tdata is valid
mac_tx_tready : in std_logic; -- mac is ready to accept data
mac_tx_tfirst : out std_logic; -- indicates first byte of frame
mac_tx_tlast : out std_logic; -- indicates last byte of frame
-- MAC Receiver
mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received
mac_rx_tvalid : in std_logic; -- indicates tdata is valid
mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
mac_rx_tlast : in std_logic -- indicates last byte of the trame
);
end UDP_Complete_nomac;
architecture structural of UDP_Complete_nomac is
------------------------------------------------------------------------------
-- Component Declaration for UDP TX
------------------------------------------------------------------------------
COMPONENT UDP_TX
PORT(
-- UDP Layer signals
udp_tx_start : in std_logic; -- indicates req to tx UDP
udp_txi : in udp_tx_type; -- UDP tx cxns
udp_tx_result : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
udp_tx_data_out_ready : out std_logic; -- indicates udp_tx is ready to take data
-- system signals
clk : in STD_LOGIC; -- same clock used to clock mac data and ip data
reset : in STD_LOGIC;
-- IP layer TX signals
ip_tx_start : out std_logic;
ip_tx : out ipv4_tx_type; -- IP tx cxns
ip_tx_result : in std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : in std_logic -- indicates IP TX is ready to take data
);
END COMPONENT;
------------------------------------------------------------------------------
-- Component Declaration for UDP RX
------------------------------------------------------------------------------
COMPONENT UDP_RX
PORT(
-- UDP Layer signals
udp_rx_start : out std_logic; -- indicates receipt of udp header
udp_rxo : out udp_rx_type;
-- system signals
clk : in STD_LOGIC;
reset : in STD_LOGIC;
-- IP layer RX signals
ip_rx_start : in std_logic; -- indicates receipt of ip header
ip_rx : in ipv4_rx_type
);
END COMPONENT;
------------------------------------------------------------------------------
-- Component Declaration for the IP layer
------------------------------------------------------------------------------
component IP_complete_nomac
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store
);
Port (
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
ip_rx : out ipv4_rx_type;
-- system signals
rx_clk : in STD_LOGIC;
tx_clk : in STD_LOGIC;
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
control : in ip_control_type;
-- status signals
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
-- MAC Transmitter
mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx
mac_tx_tvalid : out std_logic; -- tdata is valid
mac_tx_tready : in std_logic; -- mac is ready to accept data
mac_tx_tfirst : out std_logic; -- indicates first byte of frame
mac_tx_tlast : out std_logic; -- indicates last byte of frame
-- MAC Receiver
mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received
mac_rx_tvalid : in std_logic; -- indicates tdata is valid
mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
mac_rx_tlast : in std_logic -- indicates last byte of the trame
);
end component;
-- IP TX connectivity
signal ip_tx_int : ipv4_tx_type;
signal ip_tx_start_int : std_logic;
signal ip_tx_result_int : std_logic_vector (1 downto 0);
signal ip_tx_data_out_ready_int : std_logic;
-- IP RX connectivity
signal ip_rx_int : ipv4_rx_type;
signal ip_rx_start_int : std_logic := '0';
begin
-- output followers
ip_rx_hdr <= ip_rx_int.hdr;
-- Instantiate the UDP TX block
udp_tx_block: UDP_TX
PORT MAP (
-- UDP Layer signals
udp_tx_start => udp_tx_start,
udp_txi => udp_txi,
udp_tx_result => udp_tx_result,
udp_tx_data_out_ready => udp_tx_data_out_ready,
-- system signals
clk => tx_clk,
reset => reset,
-- IP layer TX signals
ip_tx_start => ip_tx_start_int,
ip_tx => ip_tx_int,
ip_tx_result => ip_tx_result_int,
ip_tx_data_out_ready => ip_tx_data_out_ready_int
);
-- Instantiate the UDP RX block
udp_rx_block: UDP_RX
PORT MAP (
-- UDP Layer signals
udp_rxo => udp_rxo,
udp_rx_start => udp_rx_start,
-- system signals
clk => rx_clk,
reset => reset,
-- IP layer RX signals
ip_rx_start => ip_rx_start_int,
ip_rx => ip_rx_int
);
------------------------------------------------------------------------------
-- Instantiate the IP layer
------------------------------------------------------------------------------
IP_block : IP_complete_nomac
generic map (
CLOCK_FREQ => CLOCK_FREQ,
ARP_TIMEOUT => ARP_TIMEOUT,
ARP_MAX_PKT_TMO => ARP_MAX_PKT_TMO,
MAX_ARP_ENTRIES => MAX_ARP_ENTRIES)
PORT MAP (
-- IP interface
ip_tx_start => ip_tx_start_int,
ip_tx => ip_tx_int,
ip_tx_result => ip_tx_result_int,
ip_tx_data_out_ready => ip_tx_data_out_ready_int,
ip_rx_start => ip_rx_start_int,
ip_rx => ip_rx_int,
-- System interface
rx_clk => rx_clk,
tx_clk => tx_clk,
reset => reset,
our_ip_address => our_ip_address,
our_mac_address => our_mac_address,
control => control.ip_controls,
-- status signals
arp_pkt_count => arp_pkt_count,
ip_pkt_count => ip_pkt_count,
-- MAC Transmitter
mac_tx_tdata => mac_tx_tdata,
mac_tx_tvalid => mac_tx_tvalid,
mac_tx_tready => mac_tx_tready,
mac_tx_tfirst => mac_tx_tfirst,
mac_tx_tlast => mac_tx_tlast,
-- MAC Receiver
mac_rx_tdata => mac_rx_tdata,
mac_rx_tvalid => mac_rx_tvalid,
mac_rx_tready => mac_rx_tready,
mac_rx_tlast => mac_rx_tlast
);
end structural;
| gpl-3.0 | 9c965ad825d2ef21d181c791aac4a797 | 0.494425 | 3.600908 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/EPROC_OUT4_direct.vhd | 4 | 3,591 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 05/19/2014
--! Module Name: EPROC_OUT4_direct
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.centralRouter_package.all;
--! direct data mode EPROC_OUT4 module
entity EPROC_OUT4_direct is
port(
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
getDataTrig : out std_logic;
edataIN : in std_logic_vector (9 downto 0);
edataINrdy : in std_logic;
EdataOUT : out std_logic_vector(3 downto 0)
);
end EPROC_OUT4_direct;
architecture Behavioral of EPROC_OUT4_direct is
----------------------------------
----------------------------------
component pulse_pdxx_pwxx
generic(
pd : integer := 0;
pw : integer := 1);
port(
clk : in std_logic;
trigger : in std_logic;
pulseout : out std_logic
);
end component pulse_pdxx_pwxx;
----------------------------------
----------------------------------
component MUX2_Nbit
generic (N : integer := 16);
Port (
data0 : in std_logic_vector((N-1) downto 0);
data1 : in std_logic_vector((N-1) downto 0);
sel : in std_logic;
data_out : out std_logic_vector((N-1) downto 0)
);
end component;
----------------------------------
----------------------------------
constant zeros4bit : std_logic_vector (1 downto 0) := (others=>'0');
signal byte_r : std_logic_vector (7 downto 0);
signal request_cycle_cnt, send_count : std_logic := '0';
signal send_out_trig : std_logic := '0';
signal inp_request_trig, inp_request_trig_out : std_logic;
begin
-------------------------------------------------------------------------------------------
-- input handshaking, request cycle 2 CLKs
-------------------------------------------------------------------------------------------
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if rst = '1' then
request_cycle_cnt <= '0';
else
request_cycle_cnt <= not request_cycle_cnt;
end if;
end if;
end process;
--
inp_request_trig <= request_cycle_cnt;
--
inp_reques1clk: pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(bitCLKx4, inp_request_trig, inp_request_trig_out);
getDataTrig <= inp_request_trig_out;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
send_out_trig <= inp_request_trig;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- sending out 2 bits @ bitCLK
-------------------------------------------------------------------------------------------
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if send_out_trig = '1' then
byte_r <= edataIN(7 downto 0);
end if;
end if;
end process;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if send_out_trig = '1' then
send_count <= '0';
else
send_count <= not send_count;
end if;
end if;
end process;
--
outmux: MUX2_Nbit
generic map (N=>4)
port map (
data0 => byte_r(3 downto 0),
data1 => byte_r(7 downto 4),
sel => send_count,
data_out => EdataOUT
);
--
end Behavioral;
| gpl-3.0 | 0ba9c3aef4d60164056c0489fe0d8975 | 0.47257 | 3.641988 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/MUX8_Nbit.vhd | 4 | 1,674 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 10/07/2014
--! Module Name: MUX8_Nbit
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE,work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
library unisim;
use unisim.vcomponents.all;
--! MUX 8x1, N bit data
entity MUX8_Nbit is
generic (
N : integer := 16);
Port (
data0 : in std_logic_vector((N-1) downto 0);
data1 : in std_logic_vector((N-1) downto 0);
data2 : in std_logic_vector((N-1) downto 0);
data3 : in std_logic_vector((N-1) downto 0);
data4 : in std_logic_vector((N-1) downto 0);
data5 : in std_logic_vector((N-1) downto 0);
data6 : in std_logic_vector((N-1) downto 0);
data7 : in std_logic_vector((N-1) downto 0);
sel : in std_logic_vector(2 downto 0);
data_out : out std_logic_vector((N-1) downto 0)
);
end MUX8_Nbit;
architecture MUX8_Nbit_arc of MUX8_Nbit is
begin
process(data0,data1,data2,data3,data4,data5,data6,data7,sel)
begin
case sel is
when "000" => data_out <= data0;
when "001" => data_out <= data1;
when "010" => data_out <= data2;
when "011" => data_out <= data3;
when "100" => data_out <= data4;
when "101" => data_out <= data5;
when "110" => data_out <= data6;
when "111" => data_out <= data7;
when others =>
end case;
end process;
end MUX8_Nbit_arc;
| gpl-3.0 | 565d62b895b2391957c996cbd404b3e2 | 0.516129 | 3.060329 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4371/Elink2FIFO.vhd | 1 | 5,021 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 17/08/2015
--! Module Name: Elink2FIFO
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.all;
--! consists of 1 E-path
entity Elink2FIFO is
generic (
InputDataRate : integer := 80; -- 80 or 160 MHz
elinkEncoding : std_logic_vector (1 downto 0)
);
port (
clk40 : in std_logic;
clk80 : in std_logic;
clk160 : in std_logic;
rst : in std_logic;
fifo_flush : in std_logic;
------
DATA1bitIN : in std_logic;
------
efifoRclk : in std_logic;
efifoRe : in std_logic;
efifoHF : out std_logic; -- half-full flag: 1 KByte block is ready to be read
efifoDout : out std_logic_vector (15 downto 0)
------
);
end Elink2FIFO;
architecture Behavioral of Elink2FIFO is
--
constant maxClen : std_logic_vector (11 downto 0) := (others => '0'); -- no limit on packet size here
signal DATA2bitIN, shreg2bit : std_logic_vector (1 downto 0) := (others => '0');
signal DATA4bitIN, shreg4bit : std_logic_vector (3 downto 0) := (others => '0');
signal DATA_OUT : std_logic_vector(9 downto 0);
signal DATA_RDY, FIFO_RESET_STATE, almost_full, BWORD_RDY : std_logic;
signal BWORD : std_logic_vector(15 downto 0);
----
begin
------------------------------------------------------------
-- E-PATH case 80 MHz
------------------------------------------------------------
InputDataRate80: if InputDataRate = 80 generate
--
process(clk80)
begin
if clk80'event and clk80 = '1' then
shreg2bit <= DATA1bitIN & shreg2bit(1);
end if;
end process;
--
process(clk40)
begin
if clk40'event and clk40 = '1' then
DATA2bitIN <= shreg2bit;
end if;
end process;
---
EPROC_IN2bit: entity work.EPROC_IN2
port map (
bitCLK => clk40,
bitCLKx2 => clk80,
bitCLKx4 => clk160,
rst => rst,
ENA => '1', -- always enabled here
swap_inputbits => '0', -- when '1', the input bits will be swapped
ENCODING => elinkEncoding, -- 00-direct data / 01-8b10b encoding / 10-HDLC encoding
EDATA_IN => DATA2bitIN, -- @ 40MHz
DATA_OUT => DATA_OUT, -- 10-bit data out
DATA_RDY => DATA_RDY,
busyOut => open -- not in use here
);
end generate InputDataRate80;
------------------------------------------------------------
-- E-PATH case 160 MHz
------------------------------------------------------------
InputDataRate160: if InputDataRate = 160 generate
--
process(clk160)
begin
if clk160'event and clk160 = '1' then
shreg4bit <= DATA1bitIN & shreg4bit(3 downto 1);
end if;
end process;
--
process(clk40)
begin
if clk40'event and clk40 = '1' then
DATA4bitIN <= shreg4bit;
end if;
end process;
---
EPROC_IN4bit: entity work.EPROC_IN4
port map (
bitCLK => clk40,
bitCLKx2 => clk80,
bitCLKx4 => clk160,
rst => rst,
ENA => '1', -- always enabled here
ENCODING => elinkEncoding, -- 00-direct data / 01-8b10b encoding / 10-HDLC encoding
EDATA_IN => DATA4bitIN, -- @ 40MHz
DATA_OUT => DATA_OUT, -- 10-bit data out
DATA_RDY => DATA_RDY,
busyOut => open -- not in use here
);
end generate InputDataRate160;
------------------------------------------------------------
-- EPATH FIFO DRIVER
------------------------------------------------------------
efd: entity work.EPROC_FIFO_DRIVER
generic map(
GBTid => 0, -- no use
egroupID => 0, -- no use
epathID => 0 -- no use
)
port map (
clk40 => clk40,
clk160 => clk160,
rst => rst,
encoding => "10", -- 00-direct data / 01-8b10b encoding / 10-HDLC encoding
maxCLEN => "000", -- 000-not limit on packet length
DIN => DATA_OUT, -- 10-bit data in
DIN_RDY => DATA_RDY,
xoff => almost_full,
timeCntIn => x"00", -- not in use
TimeoutEnaIn => '0', -- not in use
wordOUT => BWORD, -- 16-bit block word
wordOUT_RDY => BWORD_RDY
);
------------------------------------------------------------
-- EPATH FIFOs
------------------------------------------------------------
efw: entity work.EPATH_FIFO_WRAP
port map (
rst => rst,
fifoFlush => fifo_flush,
wr_clk => clk160,
rd_clk => efifoRclk,
din => BWORD,
wr_en => BWORD_RDY,
rd_en => efifoRe,
dout => efifoDout,
almost_full => almost_full,
prog_full => efifoHF -- Half-Full - output: 1Kbyte block is ready
);
end Behavioral;
| gpl-3.0 | eae633510dcc095d770a03c49ac0ffbe | 0.489743 | 3.648983 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4400/EPROC_FIFO_DRIVER.vhd | 1 | 22,779 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 07/13/2014
--! Module Name: EPROC_FIFO_DRIVER
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.all;
use work.centralRouter_package.all;
--! a driver for EPROC FIFO, manages block header and sub-chunk trailer
entity EPROC_FIFO_DRIVER is
generic (
GBTid : integer := 0;
egroupID : integer := 0;
epathID : integer := 0;
toHostTimeoutBitn : integer := 8
);
port (
clk40 : in std_logic;
clk160 : in std_logic;
rst : in std_logic;
----------
encoding : in std_logic_vector (1 downto 0);
maxCLEN : in std_logic_vector (2 downto 0);
---------
DIN : in std_logic_vector (9 downto 0);
DIN_RDY : in std_logic;
----------
xoff : in std_logic;
timeCntIn : in std_logic_vector ((toHostTimeoutBitn-1) downto 0);
TimeoutEnaIn: in std_logic;
----------
wordOUT : out std_logic_vector (15 downto 0);
wordOUT_RDY : out std_logic
);
end EPROC_FIFO_DRIVER;
architecture Behavioral of EPROC_FIFO_DRIVER is
--
signal DIN_r : std_logic_vector (7 downto 0) := (others => '0');
signal DIN_CODE_r : std_logic_vector (1 downto 0) := (others => '0');
signal DIN_s : std_logic_vector (9 downto 0);
signal DIN_RDY_r : std_logic := '0';
---
signal receiving_state, data_shift_trig, trailer_shift_trig, trailer_shift_trig_s,
EOC_error, SOC_error, rst_clen_counter, data16bit_rdy,
data16bit_rdy_shifted, truncating_state, truncation_trailer_sent : std_logic := '0';
signal send_trailer_trig,data_shift_trig_s : std_logic;
signal DIN_prev_is_zeroByte, DIN_is_zeroByte : std_logic := '0';
signal direct_data_mode, direct_data_boundary_detected : std_logic;
signal trailer_trunc_bit, trailer_cerr_bit, first_subchunk, first_subchunk_on : std_logic := '0';
signal trailer_mod_bits : std_logic_vector (1 downto 0);
signal trailer_type_bits : std_logic_vector (2 downto 0) := (others => '0');
signal EOB_MARK, truncateDataFlag, flushed, flush_trig, data_rdy : std_logic;
signal trailer_shift_trigs, trailer_shift_trig0, header_shift_trigs : std_logic;
signal trailer_shift_trig1 : std_logic := '0';
signal data16bit_rdy_code : std_logic_vector (2 downto 0);
signal trailer, trailer0, trailer1, header, data : std_logic_vector (15 downto 0);
signal wordOUT_s : std_logic_vector (15 downto 0) := (others => '0');
signal pathENA, DIN_RDY_s : std_logic := '0';
signal pathENAtrig, blockCountRdy,timeout_trailer_send,xoff_s : std_logic;
--
signal timeCnt_lastClk : std_logic_vector ((toHostTimeoutBitn-1) downto 0);
signal do_transmit_timeout_trailers,timout_ena,truncation_from_timeout,truncating_state_clk40 : std_logic := '0';
signal zero_trailer_send_pulse_count : std_logic_vector (2 downto 0) := (others=>'0');
signal zero_trailer_send_pulse,truncation_from_timeout_trig,timeout_event_clk0,timeout_event_clk1,data_on_input,data_on_input_clk40 : std_logic;
--
constant zero_data_trailer : std_logic_vector(15 downto 0) := "0000000000000000"; -- "000"=null chunk, "00"=no truncation & no cerr, '0', 10 bit length is zero;
constant timeout_trailer : std_logic_vector(15 downto 0) := "1010000000000000"; -- "101"=timeout, "00"=no truncation & no cerr, '0', 10 bit length is zero;
signal work_state : std_logic := '0';
--
begin
------------------------------------------------------------
-- time out counter for triggering the send-out of an
-- incomplete block
------------------------------------------------------------
--data_on_input <= '1' when (DIN_RDY = '1' and DIN(9 downto 8) /= "11" and truncating_state_clk40 = '0') else '0';
--
process(clk160,rst)
begin
if rst = '1' then
data_on_input <= '0';
elsif rising_edge (clk160) then
if DIN_RDY = '1' then
if DIN(9 downto 8) /= "11" then -- data
data_on_input <= not truncating_state_clk40;
else
data_on_input <= '0';
end if;
else
data_on_input <= '0';
end if;
end if;
end process;
--
tcdc: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>5) port map(clk160, data_on_input, data_on_input_clk40);
--
process(clk40,rst)
begin
if rst = '1' then
timeCnt_lastClk <= (others=>'1');
truncating_state_clk40 <= '0';
work_state <= '0';
elsif rising_edge (clk40) then
truncating_state_clk40 <= truncating_state; -- cdc
--
if timeCntIn(0) = '1' then
work_state <= '1';
end if;
--
if (data_on_input_clk40 = '1' or TimeoutEnaIn = '0' or timout_ena = '0') and work_state = '1' then
timeCnt_lastClk <= timeCntIn; -- [valid data] or [disabled timeout] re-set counter cycle start point
end if;
end if;
end process;
--
--
process(clk40,rst)
begin
if rst = '1' then
timeout_event_clk0 <= '0';
elsif rising_edge (clk40) then --
if timeCnt_lastClk = timeCntIn then
timeout_event_clk0 <= '1';
else
timeout_event_clk0 <= '0';
end if;
end if;
end process;
--
t0: entity work.pulse_pdxx_pwxx generic map(pd=>1,pw=>1) port map(clk40, timeout_event_clk0, timeout_event_clk1);
--
truncation_from_timeout <= timeout_event_clk0;
p0: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(clk160, truncation_from_timeout, truncation_from_timeout_trig);
--
--
process(clk160,rst)
begin
if rst = '1' then
do_transmit_timeout_trailers <= '0';
elsif rising_edge (clk160) then
if timeout_event_clk1 = '1' then --timeCnt_lastClk = timeCntIn and timout_ena = '1' and TimeoutEnaIn = '1' then
do_transmit_timeout_trailers <= '1';
elsif (data_on_input = '1' or EOB_MARK = '1') then
do_transmit_timeout_trailers <= '0';
end if;
end if;
end process;
--
--
p1: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(clk160, do_transmit_timeout_trailers, timeout_trailer_send);
xoff_s <= xoff or truncation_from_timeout;
--
process(clk160,rst)
begin
if rst = '1' then
timout_ena <= '0';
elsif rising_edge (clk160) then
if do_transmit_timeout_trailers = '1' then
timout_ena <= '0';
elsif receiving_state = '1' then
timout_ena <= '1';
end if;
end if;
end process;
--
---------------------------------------------
-- CLK1: register the input
---------------------------------------------
process(clk160)
begin
if rising_edge (clk160) then
if DIN_RDY = '1' then
DIN_s <= DIN;
DIN_RDY_s <= '1';
else
DIN_RDY_s <= '0';
end if;
end if;
end process;
-- for the direct data case:
-- register the input byte comparator result
-- for the direct data case to detect zeros as data delimeter
direct_data_mode <= not(encoding(1) or encoding(0));
--
process(clk160)
begin
if rising_edge (clk160) then
if DIN_RDY = '1' then
if DIN(7 downto 0) = "00000000" then
DIN_is_zeroByte <= '1';
else
DIN_is_zeroByte <= '0';
end if;
end if;
end if;
end process;
-- pipeline the input byte comparator result
process(clk160)
begin
if rising_edge (clk160) then
if DIN_RDY = '1' then
DIN_prev_is_zeroByte <= DIN_is_zeroByte;
end if;
end if;
end process;
--
direct_data_boundary_detected <= '1' when (DIN_is_zeroByte = '1' and DIN_prev_is_zeroByte = '1') else '0';
--
---------------------------------------------
-- initial enabling of the path:
-- enabled after reset on the first
-- valid input symbol (must be comma!)
-- the first symbol is then lost! as we are sending
-- a bloack header when it is detected
---------------------------------------------
process(clk160)
begin
if rising_edge (clk160) then
if rst = '1' then
pathENA <= '0';
elsif DIN_RDY_s = '1' then --
pathENA <= '1';
end if;
end if;
end process;
-- trigger to restart the block counter
pathENA1clk: entity work.pulse_pdxx_pwxx GENERIC MAP(pd=>0,pw=>1) PORT MAP(clk160, pathENA, pathENAtrig);
---------------------------------------------
-- CLK2:
---------------------------------------------
--
DIN_RDY_r <= (DIN_RDY_s and (not truncateDataFlag)) or truncation_from_timeout_trig; --and pathENA; --blockCountRdy;
DIN_r <= DIN_s(7 downto 0);
--
process(direct_data_mode, direct_data_boundary_detected, DIN_s(9 downto 8), truncateDataFlag)
begin
if direct_data_mode = '1' then
DIN_CODE_r <= direct_data_boundary_detected & '0'; -- "10"=soc, "00"=data
else
if truncateDataFlag = '0' then
DIN_CODE_r <= DIN_s(9 downto 8);
else
DIN_CODE_r <= "00";
end if;
end if;
end process;
--
-----------------------------------------------------------
-- clock 3
-- case of the input word code:
-- "00" => data, "01" => EOC, "10" => SOC, "11" => COMMA
-----------------------------------------------------------
process(clk160, rst)
begin
if rst = '1' then
--
receiving_state <= '0';
trailer_trunc_bit <= '1';
trailer_cerr_bit <= '1';
trailer_type_bits <= "000"; -- not a legal code
data_shift_trig <= '0';
trailer_shift_trig <= '0';
EOC_error <= '0';
SOC_error <= '0';
rst_clen_counter <= '0';
first_subchunk_on <= '0';
truncating_state <= '0';
--
elsif rising_edge (clk160) then
if DIN_RDY_r = '1' then
case (DIN_CODE_r) is
when "00" => -- data
--
data_shift_trig <= (receiving_state) and (not truncateDataFlag); -- shift-in data if in the receiving state
-- if block filled up after that, chunk trailer and block header will be shifted-in as well
trailer_trunc_bit <= truncateDataFlag; -- truncation mark in case of CLEN_error
trailer_cerr_bit <= truncateDataFlag; -- CLEN_error is '1' in case of receiving data after CLEN is reached
trailer_type_bits <= (not (truncateDataFlag or first_subchunk)) & truncateDataFlag & first_subchunk; -- 001_first, 011_whole, 100_middle, 010_last
trailer_shift_trig <= truncateDataFlag and receiving_state; -- send a trailer once when CLEN value is reached (SOC will rst the chunk-len-counter)
receiving_state <= receiving_state and (not truncateDataFlag); -- switching off receiving in case of truncateDataFlag, waiting for SOC now
EOC_error <= '0';
SOC_error <= not receiving_state; -- if current state is not 'receiving', flag an error, do nothing
rst_clen_counter <= '0';
first_subchunk_on <= '0';
truncating_state <= truncateDataFlag and receiving_state; -- truncation trailer is sent in this 'case' (once)
--
when "01" => -- EOC
--
trailer_shift_trig <= receiving_state or do_transmit_timeout_trailers; -- if '1' => correct state, shift-in a trailer, if not, do nothing
-- sending a trailer is including padding with zeros ('flush') in case of even word count (should be flagged somewhere...)
trailer_trunc_bit <= '0'; -- no truncation, proper ending
trailer_cerr_bit <= '0';
trailer_type_bits <= do_transmit_timeout_trailers & '1' & first_subchunk; -- 'last sub-chunk' or 'whole sub-chunk' mark
EOC_error <= not receiving_state; -- if current state was not 'receiving', flag an error, do nothing
receiving_state <= '0';
--
truncating_state <= truncating_state;
rst_clen_counter <= '0';
first_subchunk_on <= '0';
data_shift_trig <= '0';
SOC_error <= '0';
--
when "10" => -- SOC
--
trailer_shift_trig <= (receiving_state and (not direct_data_mode)) or (truncateDataFlag and (not truncation_trailer_sent)); -- if '1' => incorrect state, shift-in a trailer to finish the unfinished chunk
-- sending a trailer is including padding with zeros ('flush') in case of even word count (should be flagged somewhere...)
trailer_trunc_bit <= '1'; -- truncation mark in case of sending a trailer (this is when EOC was not received)
trailer_cerr_bit <= '1';
trailer_type_bits <= "01" & (first_subchunk or truncateDataFlag); -- 'last sub-chunk' or 'whole sub-chunk' mark
SOC_error <= receiving_state; -- if current state was already 'receiving', flag an error
receiving_state <= not truncateDataFlag; --'1';
rst_clen_counter <= '1';
first_subchunk_on <= '1';
truncating_state <= truncateDataFlag and (not truncation_trailer_sent); -- truncation trailer is sent in this 'case' (once)
--
data_shift_trig <= '0';
EOC_error <= '0';
--
when "11" => -- COMMA
--
-- do nothing
receiving_state <= receiving_state;
truncating_state <= truncating_state;
trailer_trunc_bit <= '0';
trailer_cerr_bit <= '0';
trailer_type_bits <= "000";
data_shift_trig <= '0';
trailer_shift_trig <= '0';
EOC_error <= '0';
SOC_error <= '0';
rst_clen_counter <= '0';
first_subchunk_on <= '0';
--
when others =>
end case;
else
receiving_state <= receiving_state;
trailer_trunc_bit <= trailer_trunc_bit;
trailer_cerr_bit <= trailer_cerr_bit;
trailer_type_bits <= trailer_type_bits; --"000";
truncating_state <= truncating_state;
data_shift_trig <= '0';
trailer_shift_trig <= '0';
EOC_error <= '0';
SOC_error <= '0';
rst_clen_counter <= '0';
first_subchunk_on <= '0';
end if;
end if;
end process;
-----------------------------------------------------------
-- truncation trailer should be only sent once (the first one)
-----------------------------------------------------------
process(clk160)
begin
if rising_edge (clk160) then
if truncateDataFlag = '0' then
truncation_trailer_sent <= '0';
else -- truncateDataFlag = '1':
if trailer_shift_trig = '1' then
truncation_trailer_sent <= '1'; -- latch, send only one truncation trailer
end if;
end if;
end if;
end process;
--
-----------------------------------------------------------
-- clock3, writing to the shift register
-- data8bit ready pulse
-----------------------------------------------------------
process(clk160)
begin
if rising_edge (clk160) then -- first, try to flush the shift register
trailer_shift_trig_s <= trailer_shift_trig and (not EOB_MARK); -- this trailer is a result of {eoc} or {soc without eoc} or {max clen violation}
end if;
end process;
--
send_trailer_trig <= trailer_shift_trig_s or EOB_MARK; -- or truncation_from_timeout_trig;
data_shift_trig_s <= data_shift_trig;
flush_trig <= trailer_shift_trig;-- and (not truncateDataFlag); -- no need for flush in truncation case
--
DATA_shift_r: entity work.reg8to16bit -- only for data or 'flush' padding
PORT MAP(
rst => rst,
clk => clk160,
flush => flush_trig, --trailer_shift_trig,
din => DIN_r,
din_rdy => data_shift_trig_s,
-----
flushed => flushed,
dout => data,
dout_rdy => data_rdy
);
-----------------------------------------------------------
-- clock
-- BLOCK_WORD_COUNTER
-----------------------------------------------------------
BLOCK_WORD_COUNTER_inst: entity work.BLOCK_WORD_COUNTER
generic map (GBTid=>GBTid, egroupID=>egroupID, epathID=>epathID)
port map (
CLK => clk160,
RESET => rst,
RESTART => pathENAtrig,
BW_RDY => data16bit_rdy, -- counts everything that is written to EPROC FIFO
EOB_MARK => EOB_MARK, -- End-Of-Block: 'send the chunk trailer' trigger
BLOCK_HEADER_OUT => header,
BLOCK_HEADER_OUT_RDY => header_shift_trigs,
BLOCK_COUNT_RDY => blockCountRdy
);
--
process(clk160)
begin
if rising_edge (clk160) then
if first_subchunk_on = '1' or rst = '1' then
first_subchunk <= '1';
elsif EOB_MARK = '1' then
first_subchunk <= '0';
end if;
end if;
end process;
-----------------------------------------------------------
-- Sub-Chunk Data manager
-- sends a trailer in 2 clocks (current clock and the next)
-----------------------------------------------------------
--
trailer_mod_bits <= trailer_trunc_bit & trailer_cerr_bit;
--
SCDataMANAGER_inst: entity work.SCDataMANAGER
PORT MAP(
CLK => clk160,
rst => rst,
xoff => xoff_s,
maxCLEN => maxCLEN,
rstCLENcount => rst_clen_counter,
truncateCdata => truncateDataFlag, -- out, next data will be truncated, a trailer will be sent instead
trailerMOD => trailer_mod_bits, -- in, keeps its value till the next DIN_RDY_s
trailerTYPE => trailer_type_bits, -- in, keeps its value till the next DIN_RDY_s
trailerRSRVbit => xoff_s,
-------
trailerSENDtrig => send_trailer_trig,
dataCNTena => data_shift_trig_s, -- counts data Bytes (not 16-bit words)data_rdy, -- counts only data (or 'flush' padding), no header, no trailer
-------
trailerOUT => trailer0,
trailerOUTrdy => trailer_shift_trig0
);
--
--
process(clk160)
begin
if rising_edge (clk160) then
trailer_shift_trig1 <= flushed;
trailer1 <= trailer0;
end if;
end process;
--
trailer_shift_trigs <= (trailer_shift_trig0 and (not flushed)) or trailer_shift_trig1;
--
process(trailer_shift_trig1, trailer1, trailer0)
begin
if trailer_shift_trig1 = '1' then
trailer <= trailer1;
else
trailer <= trailer0;
end if;
end process;
-----------------------------------------------------------
-- 16 bit output MUX, goes to a EPROC FIFO
-----------------------------------------------------------
--process(clk160)
--begin
-- if clk160'event and clk160 = '0' then
-- data16bit_rdy_shifted <= data16bit_rdy;
-- end if;
--end process;
--
data16bit_rdy <= data_rdy or trailer_shift_trigs or header_shift_trigs or timeout_trailer_send or zero_trailer_send_pulse;
data16bit_rdy_code(0) <= (not trailer_shift_trigs) and (data_rdy xor header_shift_trigs);
data16bit_rdy_code(1) <= (not header_shift_trigs) and (data_rdy xor trailer_shift_trigs);
data16bit_rdy_code(2) <= do_transmit_timeout_trailers;
--
--process(data16bit_rdy_code, data, header, trailer)
process(clk160)
begin
if rising_edge (clk160) then
case (data16bit_rdy_code) is
when "001" => -- header
wordOUT_s <= header;
when "010" => -- trailer
wordOUT_s <= trailer;
when "011" => -- data
wordOUT_s <= data;
when "100" => -- time-out trailer
if timeout_trailer_send = '1' then
wordOUT_s <= timeout_trailer;
else
wordOUT_s <= zero_data_trailer;
end if;
when "101" => -- time-out trailer
if timeout_trailer_send = '1' then
wordOUT_s <= timeout_trailer;
else
wordOUT_s <= zero_data_trailer;
end if;
when "110" => -- time-out trailer
if timeout_trailer_send = '1' then
wordOUT_s <= timeout_trailer;
else
wordOUT_s <= zero_data_trailer;
end if;
when "111" => -- time-out trailer
if timeout_trailer_send = '1' then
wordOUT_s <= timeout_trailer;
else
wordOUT_s <= zero_data_trailer;
end if;
when others =>
--wordOUT_s <= (others => '0');
end case;
end if;
end process;
--
--
process(clk160)
begin
if rising_edge (clk160) then
if do_transmit_timeout_trailers = '0' then
zero_trailer_send_pulse_count <= (others=>'0');
else
zero_trailer_send_pulse_count <= zero_trailer_send_pulse_count + 1;
end if;
end if;
end process;
--
zero_trailer_send_pulse <= '1' when (zero_trailer_send_pulse_count = "111") else '0';
--
--
process(clk160)
begin
if rising_edge (clk160) then
if rst = '1' then
wordOUT_RDY <= '0';
else
wordOUT_RDY <= data16bit_rdy;-- or data16bit_rdy_shifted;
end if;
end if;
end process;
--
wordOUT <= wordOUT_s;
end Behavioral;
| gpl-3.0 | 915dac31b67a619b80dd5c6e5ab89092 | 0.51486 | 3.862812 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4371/FIFO2Elink.vhd | 1 | 5,127 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 17/08/2015
--! Module Name: FIFO2Elink
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.all;
--! consists of 1 E-path
entity FIFO2Elink is
generic (
OutputDataRate : integer := 80; -- 80 or 160 MHz
elinkEncoding : std_logic_vector (1 downto 0)
);
port (
clk40 : in std_logic;
clk80 : in std_logic;
clk160 : in std_logic;
rst : in std_logic;
fifo_flush : in std_logic;
------
efifoDin : in std_logic_vector (17 downto 0); -- [data_code,2bit][data,16bit]
efifoWe : in std_logic;
efifoPfull : out std_logic;
efifoWclk : in std_logic;
------
DATA1bitOUT : out std_logic
------
);
end FIFO2Elink;
architecture Behavioral of FIFO2Elink is
----
signal efifoRE, doutRdy : std_logic;
signal efifoDout : std_logic_vector(9 downto 0);
signal dout2bit : std_logic_vector(1 downto 0);
signal bitCount1,dout2bit_r : std_logic := '0';
signal dout4bit, dout4bit_r : std_logic_vector(3 downto 0);
signal bitCount2 : std_logic_vector(1 downto 0) := "00";
----
begin
------------------------------------------------------------
-- EPATH_FIFO
------------------------------------------------------------
UEF: entity work.upstreamEpathFifoWrap
port map(
rst => rst,
fifoFLUSH => fifo_flush,
---
wr_clk => efifoWclk,
wr_en => efifoWe,
din => efifoDin,
---
rd_clk => clk160,
rd_en => efifoRE,
dout => efifoDout,
doutRdy => doutRdy,
---
full => open,
empty => open,
prog_full => efifoPfull
);
--
------------------------------------------------------------
-- E-PATH case 80 MHz
------------------------------------------------------------
OutputDataRate80: if OutputDataRate = 80 generate
EPROC_OUT2bit: entity work.EPROC_OUT2
port map(
bitCLK => clk40,
bitCLKx2 => clk80,
bitCLKx4 => clk160,
rst => rst,
ENA => '1', -- always enabled here
swap_outbits => '0', -- when '1', the output bits will be swapped
getDataTrig => efifoRE,
ENCODING => ("00" & elinkEncoding), -- 0000-direct data / 0001-8b10b encoding / 0010-HDLC encoding / others are used for TTC formats
EDATA_OUT => dout2bit, -- @ 40MHz
TTCin => "00", -- not in use here
DATA_IN => efifoDout, -- 10-bit data in
DATA_RDY => doutRdy
);
-------------------------------------------
-- serialization of the 2-bit data output:
-------------------------------------------
process(clk80)
begin
if clk80'event and clk80 = '1' then
bitCount1 <= not bitCount1;
end if;
end process;
--
process(clk80)
begin
if clk80'event and clk80 = '1' then
if bitCount1 = '0' then
dout2bit_r <= dout2bit(1);
end if;
end if;
end process;
---
process(clk80)
begin
if clk80'event and clk80 = '1' then
if bitCount1 = '0' then
DATA1bitOUT <= dout2bit(0);
else
DATA1bitOUT <= dout2bit_r;
end if;
end if;
end process;
---
end generate OutputDataRate80;
------------------------------------------------------------
-- E-PATH case 160 MHz
------------------------------------------------------------
OutputDataRate160: if OutputDataRate = 160 generate
EPROC_OUT4bit: entity work.EPROC_OUT4
PORT MAP(
bitCLK => clk40,
bitCLKx2 => clk80,
bitCLKx4 => clk160,
rst => rst,
ENA => '1', -- always enabled here
getDataTrig => efifoRE,
ENCODING => ("00" & elinkEncoding), -- 0000-direct data / 0001-8b10b encoding / 0010-HDLC encoding / others are used for TTC formats
EDATA_OUT => dout4bit, -- @ 40MHz
TTCin => "00000", -- not in use here
DATA_IN => efifoDout, -- 10-bit data in
DATA_RDY => doutRdy
);
-------------------------------------------
-- serialization of the 4-bit data output:
-------------------------------------------
process(clk160)
begin
if clk160'event and clk160 = '1' then
bitCount2 <= bitCount2 + 1;
end if;
end process;
--
process(clk160)
begin
if clk160'event and clk160 = '1' then
if bitCount2 = "00" then
dout4bit_r <= dout4bit;
end if;
end if;
end process;
---
process(clk80)
begin
if clk160'event and clk160 = '1' then
case bitCount2 is
when "00" => DATA1bitOUT <= dout4bit(0);
when "01" => DATA1bitOUT <= dout4bit_r(1);
when "10" => DATA1bitOUT <= dout4bit_r(2);
when "11" => DATA1bitOUT <= dout4bit_r(3);
when others =>
end case;
end if;
end process;
---
end generate OutputDataRate160;
end Behavioral;
| gpl-3.0 | d29a3b0b062006142a2ee2c0f0ab4a1d | 0.491516 | 3.643923 | false | false | false | false |
GustaMagik/RSA_Security_Token | VHDL_code/ver_A/RSA_Security_Token_Keyboard_Version/Security_Token_Top.vhdl | 1 | 18,594 |
--Copyright 2017 Christoffer Mathiesen, Gustav Örtenberg
--Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
--
--1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
--
--2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the
--documentation and/or other materials provided with the distribution.
--
--3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this
--software without specific prior written permission.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS
--BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
--GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
--LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Library IEEE;
Use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_MISC.ALL;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;
Use IEEE.NUMERIC_STD.all;
Use work.all;
-----------------------------------Top_Module----------------------------------
--This module house all submodules that make up the 'koddosa' which is a
--challenge-response system that takes in 6 hexadecimal charracters and returns
--12 "alpha-numerical" + '!' + '"' characters via the attached LCD.
--The flow of the program is:
--PowerOn->Init->PIN->Input_from_HexKeyboard->RSA-encryption->Partition and ASCII
--encode the RSA-encrypted bitString->Print on LCD->endOfProgram.
--If a wrong PIN is input 3 times in a row the program freezes at a blank screen
-------------------------------------------------------------------------------
Entity Security_Token_Top is
Generic( PIN_LENGTH : Integer := 4; --Variable length of PIN
PIN_PSWRD : STD_LOGIC_VECTOR := x"ABCD"; --PIN, should have the same amount of numbers as PIN_LENGTH
MAX_TRIES : Integer := 3; --Number of tries. 3 means one initial and 2 retries
KEY_LENGTH : Integer := 72; --Key length in bits, preferably mod 8 = 0 and mod 6 = 0
RSA_E : STD_LOGIC_VECTOR := x"08_37_F8_0B_8B_52_EF_32_C1"; --Exponent of the RSA
RSA_N : STD_LOGIC_VECTOR := x"CD_E5_68_77_70_51_D6_07_37"; --Modulus of the RSA
MESSAGE_LENGTH : Integer := 6; --Number of keyboard presses. Must be less than KEY_LENGTH/4 - 2
--String pointers
INIT_FILE : string := "mem.mif";
STRING_PTR_0 : unsigned := to_unsigned(0,6);
STRING_PTR_1 : unsigned := to_unsigned(10,6);
STRING_PTR_2 : unsigned := to_unsigned(21,6);
STRING_PTR_3 : unsigned := to_unsigned(38,6)
);
Port ( clk : in STD_LOGIC;
--aresetn: in STD_LOGIC := '1';
Hex_in : in STD_LOGIC_VECTOR(3 downto 0);
Hex_out : out STD_LOGIC_VECTOR (3 downto 0);
LCD_RS : out STD_LOGIC;
LCD_RW : out STD_LOGIC;
LCD_E : out STD_LOGIC;
LCD_DB : out STD_LOGIC_VECTOR (7 downto 0)
);
end Security_Token_Top;
architecture behav of Security_Token_Top is
function MemSize (X : integer) --Function to determine how big the RAM addr-vector should be
return integer is
variable TMP : integer;
variable POWER : integer := 1;
variable RET : integer := 0;
begin
TMP := X/6;
while (POWER < TMP) loop
POWER := POWER * 2;
RET := RET + 1;
end loop;
return RET;
end MemSize;
function ASCII_MEM_SIZE(X : integer) --Function to determine how big the TMP-MEM should be. If mod 6 /= 0 we need one extra cell for the overflow
return integer is
begin
if (X mod 6 = 0) then
return X/6 - 1;
else
return X/6;
end if;
end ASCII_MEM_SIZE;
constant LCD_CLEAR : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant LCD_PRINT : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant LCD_CHANGE: STD_LOGIC_VECTOR (1 downto 0) := "10";
constant PASSWORD : STD_LOGIC_VECTOR (PIN_LENGTH * 4 - 1 downto 0) := PIN_PSWRD;
constant KEY_LENGTH_BYTES : Integer := KEY_LENGTH / 8;
constant RAM_MAX_ADDR: unsigned(MemSize(KEY_LENGTH)-1 downto 0) := (others => '1');
constant ROM_MAX_ADDR: unsigned(5 downto 0) := (others => '1');
Type MEMORY_ARRAY is ARRAY (0 to ASCII_MEM_SIZE(KEY_LENGTH)) of STD_LOGIC_VECTOR(5 downto 0); --Mem array to store the ASCII temporarily. In cases
type PRG_STATE is (INIT, PRINT_MSG_1, GET_INPUT, PIN, LOCK, RSA, BYTE_TO_6, PRINT_MSG_2,PRINT_MSG_3, CLEAR_RAM);
type LCD_SELECT is (SELECT_ASCII, SELECT_ROM, SELECT_RAM);
Signal STATE : PRG_STATE := INIT;
Signal bit6_mem : MEMORY_ARRAY;
Signal WRONG_PIN_COUNTER : unsigned(1 downto 0) := (others => '0'); --if max tries more than 3, change this vector
Signal In_data : STD_LOGIC_VECTOR(3 downto 0); --From Keyboard
signal In_data_e, LCD_INPUT, INPUT_ASCII : STD_LOGIC_VECTOR (7 downto 0) := x"00";
Signal RDY, DO_CMD, RDY_CMD, WRITE_BACK, PIN_CORRECT : STD_LOGIC := '0';
Signal flag, WE, Read_RAM, INPUT_LSB, no_print : STD_LOGIC := '0';
Signal ROM_ADDR : UNSIGNED (5 downto 0) := (others => '0');
Signal RAM_ADDR : UNSIGNED (MemSize(KEY_LENGTH)-1 downto 0) := (others => '0');
Signal ROM_DATA, RAM_DATA_IN, RAM_DATA_OUT, ASCII_ENCODED : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
Signal Input_counter : UNSIGNED (5 downto 0) := (others => '0');
Signal MODE_SELECT : STD_LOGIC_VECTOR (1 downto 0) := LCD_CLEAR;
Signal TMP_INPUT : STD_LOGIC_VECTOR (3 downto 0);
Signal RSA_RESET, RSA_DONE, RSA_WE : STD_LOGIC := '0';
Signal RSA_START_ADDR, RSA_MEM_ADDR : STD_LOGIC_VECTOR (MemSize(KEY_LENGTH)-1 downto 0) := (others => '0');
Signal RSA_MEM_DATA_IN, RSA_MEM_DATA_OUT : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
Signal SPLITTER_DATA_IN : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
Signal SPLITTER_DATA_OUT : STD_LOGIC_VECTOR (5 downto 0) := (others => '0');
Signal SPLITTER_INC_ADDR : STD_LOGIC_VECTOR (0 downto 0) := (others => '0');
Signal SPLITTER_ACTIVE, SPLITTER_RESET : STD_LOGIC := '0';
Signal LCD_INPUT_SELECT : LCD_SELECT := SELECT_ROM;
component Keyboard
Port ( Row_Input : in STD_LOGIC_VECTOR (3 downto 0);
Col_Input_A : out STD_LOGIC_VECTOR (3 downto 0) := (others => '1');
Output : out STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
RDY : out STD_LOGIC := '0';
CLK : in STD_LOGIC;
ARESETN : in STD_LOGIC
);
end component;
component byte_to_six_bit_splitter
Port ( DATA_IN : in STD_LOGIC_VECTOR (7 downto 0);
DATA_OUT : out STD_LOGIC_VECTOR (5 downto 0);
INC_ADDR : out STD_LOGIC;
ACTIVE : in STD_LOGIC;
CLK : in STD_LOGIC;
RESET : in STD_LOGIC
);
end component;
component LCD
Port ( INPUT : in STD_LOGIC_VECTOR (7 downto 0); --ASCII IN
CLK : in STD_LOGIC; --FPGA Clock (100MHz)
ARESETN : in STD_LOGIC; --RESET
DATA_BUS : out STD_LOGIC_VECTOR (7 downto 0); --DB 7 downto DB 0
RW : out STD_LOGIC := '0'; --RW signal (unused as of now)
RS : out STD_LOGIC; --RS signal
E : out STD_LOGIC; --E (200Hz)
MODE_SELECT : in STD_LOGIC_VECTOR (1 downto 0); --SELECT WHAT THE SCREEN IS TO DO
RDY_CMD : out STD_LOGIC := '0'; --Tell ouside world that the ready for the command
DO_CMD : in STD_LOGIC); --Outside world tell module to do the current command
end component;
component ascii_encoder is
Port(input : in STD_LOGIC_VECTOR (7 downto 0);
output : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component mem_array is
GENERIC(
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := MemSize(KEY_LENGTH));
Port(
ADDR : in STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
DATAIN : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
clk : in std_logic;
WE : in std_logic;
OUTPUT : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0)
);
end component;
component mem_array_ROM is
GENERIC(
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 6;
INIT_FILE : string := INIT_FILE);
Port(
ADDR : in STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
OUTPUT : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0)
);
end component;
component RSA_Controller is
Generic( i : integer := KEY_LENGTH;
mem_addr_width : integer := MemSize(KEY_LENGTH)-1;
e_val : STD_LOGIC_VECTOR := RSA_E;
N_val : STD_LOGIC_VECTOR := RSA_N);
Port(clk : in STD_LOGIC;
resetN : in STD_LOGIC;
done : out STD_LOGIC;
mem_we : out STD_LOGIC;
input_addr: in STD_LOGIC_VECTOR (5 downto 0);
mem_addr : out STD_LOGIC_VECTOR(5 downto 0);
mem_data : in STD_LOGIC_VECTOR(7 downto 0);
data_out : out STD_LOGIC_VECTOR(7 downto 0)
);
end component;
begin
SPLITT: byte_to_six_bit_splitter port map(
DATA_IN => SPLITTER_DATA_IN,
DATA_OUT => SPLITTER_DATA_OUT,
INC_ADDR => SPLITTER_INC_ADDR(0),
ACTIVE => SPLITTER_ACTIVE,
CLK => CLK,
RESET => SPLITTER_RESET
);
RSA_MODULE: RSA_Controller port map(
clk => clk,
resetN => RSA_RESET,
done => RSA_DONE,
mem_we => RSA_WE,
input_addr => RSA_START_ADDR,
mem_addr => RSA_MEM_ADDR,
mem_data => RSA_MEM_DATA_IN,
data_out => RSA_MEM_DATA_OUT
);
ASCII: ascii_encoder port map (
input => INPUT_ASCII,
output => ASCII_ENCODED
);
SCREEN: LCD port map (
INPUT => LCD_INPUT,
CLK => clk,
ARESETN => '1',
DATA_BUS => LCD_DB,
RW => LCD_RW,
RS => LCD_RS,
E => LCD_E,
MODE_SELECT => MODE_SELECT,
RDY_CMD => RDY_CMD,
DO_CMD => DO_CMD
);
KBD : Keyboard port map (
Row_Input => Hex_in,
Col_Input_A => Hex_out,
Output => In_data,
RDY => RDY,
CLK => clk,
ARESETN => '1'
);
ROM:
mem_array_ROM port map(
ADDR => STD_LOGIC_VECTOR(ROM_ADDR),
OUTPUT => ROM_DATA
);
RAM:
mem_array port map(
ADDR => STD_LOGIC_VECTOR(RAM_ADDR),
DATAIN => RAM_DATA_IN,
clk => CLK,
WE => WE,
OUTPUT => RAM_DATA_OUT);
RSA_MEM_DATA_IN <= RAM_DATA_OUT;
with STATE select
RAM_DATA_IN <=
In_data_e when GET_INPUT,
RSA_MEM_DATA_OUT when RSA,
In_data_e when others;
with LCD_INPUT_SELECT select
LCD_INPUT <=
ROM_DATA when SELECT_ROM,
RAM_DATA_OUT when SELECT_RAM,
ASCII_ENCODED when SELECT_ASCII,
ROM_DATA when others;
--State changes
process(clk)
begin
if rising_edge(clk) then
if WE = '1' then
WE <= '0';
end if;
--If we are telling the screen to do a command and RDY_CMD goes to 0
--it means that the screen is working on it. Thus we should stop
--telling the screen to do commands.
if RDY_CMD = '0' and DO_CMD = '1' then
DO_CMD <= '0';
else
case STATE is
------------------------------------------------------------------------------
when INIT =>
if RDY_CMD = '1' and DO_CMD = '0' then --Wait for the LCD to be ready
STATE <= PIN;
ROM_ADDR <= STRING_PTR_0 - 1;
WE <= '0';
end if;
------------------------------------------------------------------------------
when PIN =>
if flag = '0' then
if RDY_CMD = '1' and DO_CMD = '0' then
LCD_INPUT_SELECT <= SELECT_ROM;
MODE_SELECT <= LCD_PRINT;
DO_CMD <= '1';
if ROM_DATA = x"00" and ROM_ADDR /= ROM_MAX_ADDR then --char is '\0' (and not the last rom addr)
MODE_SELECT <= LCD_CHANGE;
Input_counter <= to_unsigned(PIN_LENGTH, 6);
RAM_ADDR <= (others => '0');
PIN_CORRECT <= '1';
flag <= '1';
else
ROM_ADDR <= ROM_ADDR + 1;
end if;
end if;
elsif RDY_CMD = '1' and DO_CMD = '0' then
if Input_counter = 0 and PIN_CORRECT = '1' then
MODE_SELECT <= LCD_CLEAR;
flag <= '0';
DO_CMD <= '1';
STATE <= PRINT_MSG_1;
ROM_ADDR <= STRING_PTR_2 - 1;
WRONG_PIN_COUNTER <= (others => '0');
elsif Input_counter = 0 and PIN_CORRECT = '0' then
MODE_SELECT <= LCD_CLEAR;
STATE <= PRINT_MSG_3;
ROM_ADDR <= STRING_PTR_1 - 1;
DO_CMD <= '1';
WRONG_PIN_COUNTER <= WRONG_PIN_COUNTER + 1;
elsif RDY = '1' then
if PASSWORD(to_integer(input_counter * 4 - 1) downto to_integer(input_counter * 4 - 4)) /= In_data then -- if the current number was wrong the entire pin is wrong
PIN_CORRECT <= '0';
end if;
Input_counter <= Input_counter - 1;
end if;
end if;
when PRINT_MSG_3 =>
if WRONG_PIN_COUNTER < MAX_TRIES then
if RDY_CMD = '1' and DO_CMD = '0' then
LCD_INPUT_SELECT <= SELECT_ROM;
MODE_SELECT <= LCD_PRINT;
DO_CMD <= '1';
if ROM_DATA /= x"00" or ROM_ADDR = STRING_PTR_1 - 1 then --char is not '\0', continue printing
ROM_ADDR <= ROM_ADDR + 1;
elsif RDY = '1' then
MODE_SELECT <= LCD_CLEAR;
STATE <= CLEAR_RAM;
Input_counter <= (others => '0');
RAM_ADDR <= (others => '0');
else
DO_CMD <= '0';
end if;
end if;
end if;
------------------------------------------------------------------------------
when PRINT_MSG_1 =>
if RDY_CMD = '1' and DO_CMD = '0' then
LCD_INPUT_SELECT <= SELECT_ROM;
MODE_SELECT <= LCD_PRINT;
DO_CMD <= '1';
if ROM_DATA /= x"00" or ROM_ADDR = STRING_PTR_2 - 1 then --char is not '\0', continue printing
ROM_ADDR <= ROM_ADDR + 1;
else
MODE_SELECT <= LCD_CHANGE;
STATE <= GET_INPUT;
Input_counter <= (others => '0');
RAM_ADDR <= (others => '0');
end if;
end if;
------------------------------------------------------------------------------
when GET_INPUT =>
if RDY_CMD = '1' and DO_CMD = '0' then
if Input_counter = MESSAGE_LENGTH/2 then --All the inputs have been put
Input_counter <= (others => '0');
STATE <= RSA;
ROM_ADDR <= ROM_ADDR;
MODE_SELECT <= LCD_CLEAR;
RAM_ADDR <= (others => '0');
DO_CMD <= '1';
INPUT_LSB <= '0';
elsif RDY = '1' then
LCD_INPUT_SELECT <= SELECT_ASCII; --Print the pushed number
MODE_SELECT <= LCD_PRINT;
WE <= '0';
INPUT_ASCII <= ("0000" & In_data);
DO_CMD <= '1';
if INPUT_LSB = '0' then --Put the number correctly into memory
tmp_input <= In_data;
else
In_data_e <= (tmp_input & In_data);
RAM_ADDR <= input_counter;
Input_counter <= Input_counter + 1;
WE <= '1';
end if;
INPUT_LSB <= NOT INPUT_LSB;
end if;
end if;
------------------------------------------------------------------------------
when RSA =>
WE <= RSA_WE;
RSA_RESET <= '1';
RSA_START_ADDR <= (others => '0'); --placeholder
RAM_ADDR <= (unsigned(RSA_MEM_ADDR));
if RSA_DONE = '1' then
RSA_RESET <= '0';
STATE <= BYTE_TO_6;
--SPLITTER_ACTIVE <= '1';
RAM_ADDR <= (others => '0');
end if;
------------------------------------------------------------------------------
when BYTE_TO_6 => --translate the number into an array of bytes of maximum 6 byte length
SPLITTER_DATA_IN <= RAM_DATA_OUT;
if RAM_ADDR < KEY_LENGTH/6 then
In_data_e <= "00" & bit6_mem(to_integer(unsigned(RAM_ADDR)));
end if;
if flag = '0' then --Give one cycle to get splitter to have a chance to catch up
RAM_ADDR <= (others => '0');
RAM_ADDR(0) <= '1';
SPLITTER_ACTIVE <= '1';
flag <= '1';
elsif WRITE_BACK = '0' then --Create all the 6 bit numbers and save them temporarily
RAM_ADDR <= RAM_ADDR + unsigned(SPLITTER_INC_ADDR);
if input_counter > 0 then
bit6_mem(to_integer(input_counter)-1) <= SPLITTER_DATA_OUT;
end if;
input_counter <= input_counter + 1;
if input_counter = KEY_LENGTH/6 then --all the numbers have been made
WRITE_BACK <= '1';
SPLITTER_ACTIVE <= '1';
RAM_ADDR <= (others => '1');
end if;
else --Write the converted numbers back to memory
if RAM_ADDR = RAM_MAX_ADDR then
In_data_e <= "00" & bit6_mem(0);
elsif RAM_ADDR < KEY_LENGTH/6 - 1 then
In_data_e <= "00" & bit6_mem(to_integer(unsigned(RAM_ADDR + 1)));
end if;
RAM_ADDR <= RAM_ADDR + 1;
WE <= '1';
if RAM_ADDR = KEY_LENGTH/6 -1 then --Write back complete
flag <= '0';
WRITE_BACK <= '0';
WE <= '0';
input_counter <= (others => '0');
RAM_ADDR <= (others => '1');
SPLITTER_ACTIVE <= '0';
STATE <= PRINT_MSG_2;
ROM_ADDR <= STRING_PTR_3 - 1;
end if;
end if;
------------------------------------------------------------------------------
when PRINT_MSG_2 =>
if RDY_CMD = '1' and DO_CMD = '0' then
INPUT_ASCII <= RAM_DATA_OUT;
MODE_SELECT <= LCD_PRINT;
DO_CMD <= '1';
if flag = '0' then
LCD_INPUT_SELECT <= SELECT_ROM;
if ROM_DATA /= x"00" or ROM_ADDR = STRING_PTR_3 - 1 then --char is not '\0', continue printing
ROM_ADDR <= ROM_ADDR + 1;
else
MODE_SELECT <= LCD_CHANGE;
Input_counter <= (others => '0');
RAM_ADDR <= to_unsigned(KEY_LENGTH/6-1,6);
flag <= '1';
LCD_INPUT_SELECT <= SELECT_ASCII;
MODE_SELECT <= LCD_CHANGE;
end if;
else
if RAM_ADDR /= RAM_MAX_ADDR then
RAM_ADDR <= RAM_ADDR - 1;
elsif RDY = '1' then
STATE <= CLEAR_RAM;
MODE_SELECT <= LCD_CLEAR;
ROM_ADDR <= STRING_PTR_0 - 1;
RAM_ADDR <= (others => '0');
flag <= '0';
else
DO_CMD <= '0';
end if;
end if;
end if;
------------------------------------------------------------------------------
when CLEAR_RAM =>
RAM_ADDR <= RAM_ADDR + 1;
In_data_e <= (others => '0');
WE <= '1';
flag <= '1';
if RAM_ADDR = 0 and flag = '1' then
STATE <= INIT;
flag <= '0';
RAM_ADDR <= (others => '0');
WE<= '0';
Input_counter <= (others => '0');
end if;
when others =>
--kill me
end case;
end if;
end if;
end process;
end behav;
| bsd-3-clause | 242ee5c6faaf401895f873bfed566a49 | 0.571797 | 3.170332 | false | false | false | false |
GustaMagik/RSA_Security_Token | VHDL_code/ver_B/RSA_Security_Token_USB_Version/mem_array_ROM.vhdl | 1 | 2,621 |
--Copyright 2017 Gustav Örtenberg
--Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
--
--1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
--
--2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the
--documentation and/or other materials provided with the distribution.
--
--3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this
--software without specific prior written permission.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS
--BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
--GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
--LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use std.textio.ALL;
entity mem_array_ROM is
GENERIC(
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 6;
INIT_FILE : string := "mem.mif");
Port(
ADDR : in STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
OUTPUT : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0)
);
end mem_array_ROM;
architecture dataflow of mem_array_ROM is
Type MEMORY_ARRAY is ARRAY (0 to 2**(ADDR_WIDTH)-1) of STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
impure function init_memory_wfile(mif_file_name : in string) return MEMORY_ARRAY is
file mif_file : text open read_mode is mif_file_name;
variable mif_line : line;
variable temp_bv : bit_vector(DATA_WIDTH-1 downto 0);
variable temp_mem : MEMORY_ARRAY;
begin
for i in MEMORY_ARRAY'range loop
readline(mif_file, mif_line);
read(mif_line, temp_bv);
temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
constant memory : MEMORY_ARRAY :=(init_memory_wfile(INIT_FILE));
begin
OUTPUT <= memory(to_integer(unsigned(ADDR)));
end dataflow; | bsd-3-clause | 9b88a0848ec1d9b1be09af0f2aa18d79 | 0.749714 | 3.983283 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/configuration/udp_data_in_handler.vhd | 1 | 26,418 | -----------------------------------------------------------------------------------------
-- Company: NTU Athens - BNL
-- Engineer: Christos Bakalis ([email protected])
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Christos Bakalis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 30.01.2017
-- Design Name: UDP Data Handler
-- Module Name: udp_data_handler - RTL
-- Project Name: MMFE8 - NTUA
-- Target Devices: Artix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2016.2
-- Description: Module that samples the data coming from the UDP/Ethernet
-- and issues the corresponding FPGA commands depending on the payload and
-- the incoming port. It also serializes the data of the VMM configuration.
-- Dependencies: MMFE8 NTUA Project
--
-- Changelog:
-- 31.01.2017 The serialization now starts with a signal coming from the master FSM
-- and the MUX select signal is being reset between packets. (Christos Bakalis)
-- 08.02.2017 Broke down the processes into two sub-components. (Christos Bakalis)
-- 27.02.2017 Changes to integrate with new flow_fsm clock (125 Mhz). (Christos Bakalis)
-- 07.03.2017 Added CKBC/CKTP configuration functionality. (Christos Bakalis)
-- 14.03.2017 FPGA register address configuration scheme deployed. (Christos Bakalis)
-- 17.03.2017 Added configuration-inhibit signal which is high if flow_fsm is not in
-- IDLE state. Change if fpga_glbl_rst is added again. (Christos Bakalis)
-- 28.03.2017 Module now samples the header data as well. (Christos Bakalis)
--
-----------------------------------------------------------------------------------------
library UNISIM;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use UNISIM.VCOMPONENTS.all;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity udp_data_in_handler is
port(
------------------------------------
------- General Interface ----------
clk_125 : in std_logic;
clk_40 : in std_logic;
inhibit_conf : in std_logic;
rst : in std_logic;
rst_fifo_init : in std_logic;
state_o : out std_logic_vector(2 downto 0);
valid_o : out std_logic;
------------------------------------
-------- FPGA Config Interface -----
latency : out std_logic_vector(15 downto 0);
serial_number : out std_logic_vector(31 downto 0);
daq_on : out std_logic;
ext_trigger : out std_logic;
ckbcMode : out std_logic;
fpga_rst : out std_logic;
------------------------------------
-------- UDP Interface -------------
udp_rx : in udp_rx_type;
------------------------------------
---------- AXI4SPI Interface -------
flash_busy : in std_logic;
newIP_rdy : out std_logic;
myIP_set : out std_logic_vector(31 downto 0);
myMAC_set : out std_logic_vector(47 downto 0);
destIP_set : out std_logic_vector(31 downto 0);
------------------------------------
-------- CKTP/CKBC Interface -------
ckbc_freq : out std_logic_vector(7 downto 0);
cktk_max_num : out std_logic_vector(7 downto 0);
cktp_max_num : out std_logic_vector(15 downto 0);
cktp_skew : out std_logic_vector(7 downto 0);
cktp_period : out std_logic_vector(15 downto 0);
cktp_width : out std_logic_vector(7 downto 0);
ckbc_max_num : out std_logic_vector(7 downto 0);
------------------------------------
------ VMM Config Interface --------
vmm_bitmask : out std_logic_vector(7 downto 0);
vmmConf_came : out std_logic;
vmmConf_rdy : out std_logic;
vmmConf_done : out std_logic;
vmm_sck : out std_logic;
vmm_cs : out std_logic;
vmm_cfg_bit : out std_logic;
top_rdy : in std_logic;
------------------------------------
---------- XADC Interface ----------
xadc_busy : in std_logic;
xadc_rdy : out std_logic;
vmm_id_xadc : out std_logic_vector(15 downto 0);
xadc_sample_size : out std_logic_vector(10 downto 0);
xadc_delay : out std_logic_vector(17 downto 0)
);
end udp_data_in_handler;
architecture RTL of udp_data_in_handler is
COMPONENT fpga_config_block
PORT(
-----------------------------------
------- General Interface ----------
clk_125 : in std_logic;
rst : in std_logic;
rst_fifo_init : in std_logic;
cnt_bytes : in unsigned(7 downto 0);
user_din_udp : in std_logic_vector(7 downto 0);
------------------------------------
-------- UDP Interface -------------
udp_rx : in udp_rx_type;
------------------------------------
---------- XADC Interface ----------
xadc_conf : in std_logic;
xadcPacket_rdy : out std_logic;
vmm_id_xadc : out std_logic_vector(15 downto 0);
xadc_sample_size : out std_logic_vector(10 downto 0);
xadc_delay : out std_logic_vector(17 downto 0);
------------------------------------
---------- AXI4SPI Interface -------
flash_conf : in std_logic;
flashPacket_rdy : out std_logic;
myIP_set : out std_logic_vector(31 downto 0);
myMAC_set : out std_logic_vector(47 downto 0);
destIP_set : out std_logic_vector(31 downto 0);
------------------------------------
-------- CKTP/CKBC Interface -------
ckbc_freq : out std_logic_vector(7 downto 0);
cktk_max_num : out std_logic_vector(7 downto 0);
cktp_max_num : out std_logic_vector(15 downto 0);
cktp_skew : out std_logic_vector(7 downto 0);
cktp_period : out std_logic_vector(15 downto 0);
cktp_width : out std_logic_vector(7 downto 0);
ckbc_max_num : out std_logic_vector(7 downto 0);
------------------------------------
-------- FPGA Config Interface -----
fpga_conf : in std_logic;
fpga_rst : out std_logic;
fpgaPacket_rdy : out std_logic;
latency : out std_logic_vector(15 downto 0);
tr_delay_limit : out std_logic_vector(15 downto 0);
daq_on : out std_logic;
ext_trigger : out std_logic;
ckbcMode : out std_logic
);
END COMPONENT;
COMPONENT vmm_config_block
PORT(
------------------------------------
------- General Interface ----------
clk_125 : in std_logic;
clk_40 : in std_logic;
rst : in std_logic;
rst_fifo : in std_logic;
cnt_bytes : in unsigned(7 downto 0);
------------------------------------
--------- FIFO/UDP Interface -------
user_din_udp : in std_logic_vector(7 downto 0);
user_valid_udp : in std_logic;
user_last_udp : in std_logic;
------------------------------------
------ VMM Config Interface --------
vmmConf_rdy : out std_logic;
vmmConf_done : out std_logic;
vmm_sck : out std_logic;
vmm_cs : out std_logic;
vmm_cfg_bit : out std_logic;
vmm_conf : in std_logic;
top_rdy : in std_logic;
init_ser : in std_logic
);
END COMPONENT;
COMPONENT CDCC
GENERIC(
NUMBER_OF_BITS : integer := 8); -- number of signals to be synced
PORT(
clk_src : in std_logic; -- input clk (source clock)
clk_dst : in std_logic; -- input clk (dest clock)
data_in : in std_logic_vector(NUMBER_OF_BITS - 1 downto 0); -- data to be synced
data_out_s : out std_logic_vector(NUMBER_OF_BITS - 1 downto 0) -- synced data to clk_dst
);
END COMPONENT;
signal user_data_prv : std_logic_vector(7 downto 0) := (others => '0');
signal command : std_logic_vector(15 downto 0) := (others => '0');
signal user_valid_prv : std_logic := '0';
signal user_last_prv : std_logic := '0';
signal cnt_bytes : unsigned(7 downto 0) := (others => '0');
signal conf_state : unsigned(2 downto 0) := (others => '0');
signal sample_hdr : std_logic := '0';
signal vmm_conf : std_logic := '0';
signal vmm_ser_done : std_logic := '0';
signal vmmSer_done_s125 : std_logic := '0';
signal vmm_conf_rdy : std_logic := '0';
signal fpga_conf : std_logic := '0';
signal flash_conf : std_logic := '0';
signal xadc_conf : std_logic := '0';
signal rst_fifo : std_logic := '0';
signal rst_fifo_vmmConf : std_logic := '0';
signal rst_fifo_s40 : std_logic := '0';
signal xadcPacket_rdy : std_logic := '0';
signal flashPacket_rdy : std_logic := '0';
signal fpgaPacket_rdy : std_logic := '0';
signal init_ser : std_logic := '0';
signal init_ser_s40 : std_logic := '0';
signal top_rdy_s40 : std_logic := '0';
signal fpga_rst_i : std_logic := '0';
type masterFSM is (ST_IDLE, ST_CHK_PORT, ST_COUNT, ST_WAIT_FOR_BUSY, ST_WAIT_FOR_IDLE, ST_RESET_FIFO, ST_WAIT_FOR_SCK_FSM, ST_ERROR);
signal st_master : masterFSM := ST_IDLE;
---- Uncomment the following to add signals to ILA debugging core
-----------------------------------------------------------------
attribute mark_debug : string;
attribute keep : string;
--attribute mark_debug of latency : signal is "true";
--attribute mark_debug of fpga_rst_conf : signal is "true";
--attribute mark_debug of daq_on : signal is "true";
--attribute mark_debug of ext_trigger : signal is "true";
--attribute mark_debug of udp_rx.data.data_in : signal is "true";
--attribute mark_debug of udp_rx.data.data_in_valid : signal is "true";
--attribute mark_debug of udp_rx.data.data_in_last : signal is "true";
--attribute mark_debug of udp_rx.hdr.dst_port : signal is "true";
--attribute mark_debug of flash_busy : signal is "true";
--attribute mark_debug of newIP_rdy : signal is "true";
--attribute mark_debug of myIP_set : signal is "true";
--attribute mark_debug of myMAC_set : signal is "true";
--attribute mark_debug of destIP_set : signal is "true";
--attribute mark_debug of vmmConf_rdy : signal is "true";
--attribute mark_debug of vmmConf_done : signal is "true";
--attribute mark_debug of vmm_cktk : signal is "true";
--attribute mark_debug of vmm_cfg_bit : signal is "true";
--attribute mark_debug of top_rdy : signal is "true";
--attribute mark_debug of xadc_busy : signal is "true";
--attribute mark_debug of xadc_rdy : signal is "true";
--attribute mark_debug of vmm_id_xadc : signal is "true";
--attribute mark_debug of xadc_sample_size : signal is "true";
--attribute mark_debug of xadc_delay : signal is "true";
--attribute mark_debug of conf_state : signal is "true";
--attribute keep of conf_state : signal is "true";
--attribute mark_debug of user_data_prv : signal is "true";
--attribute mark_debug of user_valid_prv : signal is "true";
--attribute mark_debug of user_valid_fifo : signal is "true";
--attribute mark_debug of user_last_prv : signal is "true";
--attribute mark_debug of cnt_bytes : signal is "true";
--attribute mark_debug of wait_cnt : signal is "true";
--attribute mark_debug of vmm_ser_done : signal is "true";
--attribute mark_debug of vmm_conf_rdy : signal is "true";
--attribute mark_debug of fpga_conf : signal is "true";
--attribute mark_debug of flash_conf : signal is "true";
--attribute mark_debug of sel_vmm_data : signal is "true";
--attribute mark_debug of xadc_conf : signal is "true";
--attribute mark_debug of rst_fifo : signal is "true";
--attribute mark_debug of xadcPacket_rdy : signal is "true";
--attribute mark_debug of flashPacket_rdy : signal is "true";
--attribute mark_debug of fpgaPacket_rdy : signal is "true";
--attribute mark_debug of fpga_conf_1of2 : signal is "true";
--attribute mark_debug of fpga_conf_2of2 : signal is "true";
--attribute mark_debug of rd_ena : signal is "true";
--attribute mark_debug of fifo_full : signal is "true";
--attribute mark_debug of fifo_empty : signal is "true";
--------------- List of Processes/FSMs ----------------
-------------------------------------------------------
--- 1. delay_din (clk_125)
--- 2. master_handling_FSM (clk_125)
--- 3. sample_header_proc (clk_125)
-------------------------------------------------------
-------------------------------------------------------
begin
-- delay the input data for correct sampling by the sub-processes
delay_din: process(clk_125)
begin
if(rising_edge(clk_125))then
user_data_prv <= udp_rx.data.data_in;
user_valid_prv <= udp_rx.data.data_in_valid;
user_last_prv <= udp_rx.data.data_in_last;
end if;
end process;
-- Central configuarion FSM that checks for the first valid pulse
-- and for the UDP port, in order to initialize the byte counter
-- that the sub-processes will use to sample the configuration data
master_handling_FSM: process(clk_125)
begin
if(rising_edge(clk_125))then
if(rst = '1')then
cnt_bytes <= (others => '0');
vmm_conf <= '0';
fpga_conf <= '0';
flash_conf <= '0';
xadc_conf <= '0';
sample_hdr <= '0';
init_ser <= '0';
rst_fifo <= '1';
st_master <= ST_IDLE;
else
case st_master is
-- wait for valid signal to initialize counter. ignore inhibit flag if FPGA configuration
when ST_IDLE =>
conf_state <= "000";
vmm_conf <= '0';
fpga_conf <= '0';
flash_conf <= '0';
xadc_conf <= '0';
rst_fifo <= '0';
if(udp_rx.data.data_in_valid = '1' and inhibit_conf = '0')then
cnt_bytes <= cnt_bytes + 1;
sample_hdr <= '1';
st_master <= ST_CHK_PORT;
elsif(udp_rx.data.data_in_valid = '1' and inhibit_conf = '1' and
(udp_rx.hdr.dst_port = x"1777" or udp_rx.hdr.dst_port = x"19C8"))then
cnt_bytes <= cnt_bytes + 1;
sample_hdr <= '1';
st_master <= ST_CHK_PORT;
else
cnt_bytes <= (others => '0');
sample_hdr <= '0';
st_master <= ST_IDLE;
end if;
-- check the port and activate the corresponding sub-process
when ST_CHK_PORT =>
conf_state <= "001";
cnt_bytes <= cnt_bytes + 1;
case udp_rx.hdr.dst_port is
when x"1778" => -- VMM CONF
vmm_conf <= '1';
st_master <= ST_COUNT;
when x"19C8" => -- FPGA CONF
fpga_conf <= '1';
st_master <= ST_COUNT;
when x"1777" => -- FPGA CONF
fpga_conf <= '1';
st_master <= ST_COUNT;
when x"19CC" => -- FLASH CONF
flash_conf <= '1';
st_master <= ST_COUNT;
when x"19D0" => -- XADC CONF
xadc_conf <= '1';
st_master <= ST_COUNT;
when others => -- Unknown Port
st_master <= ST_ERROR;
end case;
-- keep counting and wait for configuration packets to be formed
when ST_COUNT =>
conf_state <= "010";
cnt_bytes <= cnt_bytes + 1;
if(xadcPacket_rdy = '1' or flashPacket_rdy = '1' or fpgaPacket_rdy = '1' or vmm_conf_rdy = '1')then
st_master <= ST_WAIT_FOR_BUSY;
else
st_master <= ST_COUNT;
end if;
-- stop counting and wait for corresponding sub-module to get the init signal
-- or wait for sub-process to finish
when ST_WAIT_FOR_BUSY =>
conf_state <= "011";
if(xadcPacket_rdy = '1' and xadc_busy = '1')then
xadc_conf <= '0';
st_master <= ST_WAIT_FOR_IDLE;
elsif(flashPacket_rdy = '1' and flash_busy = '1')then
flash_conf <= '0';
st_master <= ST_WAIT_FOR_IDLE;
elsif(fpgaPacket_rdy = '1' and udp_rx.data.data_in_valid = '0')then -- no need to wait, jump to idle state
st_master <= ST_IDLE;
elsif(vmm_conf_rdy = '1')then -- initialize serialization
init_ser <= '1';
vmm_conf <= '0';
st_master <= ST_RESET_FIFO;
else
st_master <= ST_WAIT_FOR_BUSY;
end if;
-- wait for corresponding sub-module to finish processing
when ST_WAIT_FOR_IDLE =>
conf_state <= "100";
if(xadc_busy = '0' and flash_busy = '0' and udp_rx.data.data_in_valid = '0')then
st_master <= ST_IDLE;
else
st_master <= ST_WAIT_FOR_IDLE;
end if;
-- create a reset signal of adequate length. release the reset
-- only when flow_fsm and sck_fsm are in the appropriate states
when ST_RESET_FIFO =>
conf_state <= "101";
if(vmmSer_done_s125 = '1' and top_rdy = '0')then -- flow_fsm is back to IDLE + serialization has finished => reset
rst_fifo <= '1';
init_ser <= '0';
st_master <= ST_WAIT_FOR_SCK_FSM;
else
rst_fifo <= '0'; -- serialization not finished or flow_fsm is not in IDLE, wait
init_ser <= '1';
st_master <= ST_RESET_FIFO;
end if;
-- wait for SCK FSM to latch the reset signal
when ST_WAIT_FOR_SCK_FSM =>
conf_state <= "110";
if(vmmSer_done_s125 = '0' and udp_rx.data.data_in_valid = '0')then
rst_fifo <= '0';
st_master <= ST_IDLE;
else
rst_fifo <= '1';
st_master <= ST_WAIT_FOR_SCK_FSM;
end if;
-- stay here until the UDP packet passes
when ST_ERROR =>
conf_state <= "111";
if(udp_rx.data.data_in_valid = '0')then
st_master <= ST_IDLE;
else
st_master <= ST_ERROR;
end if;
when others =>
st_master <= ST_IDLE;
end case;
end if;
end if;
end process;
-- process that samples the header data from the UDP packet
sample_header_proc: process(clk_125)
begin
if(rising_edge(clk_125))then
if(sample_hdr = '1')then
case cnt_bytes is
---- sample s/n
when "00000001" => --1
serial_number(31 downto 24) <= user_data_prv;
when "00000010" => --2
serial_number(23 downto 16) <= user_data_prv;
when "00000011" => --3
serial_number(15 downto 8) <= user_data_prv;
when "00000100" => --4
serial_number(7 downto 0) <= user_data_prv;
-- sample bitmask
when "00000110" => --6
vmm_bitmask <= user_data_prv;
-- sample command
when "00000111" => --7
command(15 downto 8) <= user_data_prv;
when "00001000" => --8
command(7 downto 0) <= user_data_prv;
when others => null;
end case;
else null;
end if;
end if;
end process;
fpga_config_logic: fpga_config_block
port map(
-----------------------------------
------- General Interface ----------
clk_125 => clk_125,
rst => rst,
rst_fifo_init => rst_fifo_init,
cnt_bytes => cnt_bytes,
user_din_udp => user_data_prv,
------------------------------------
-------- UDP Interface -------------
udp_rx => udp_rx,
------------------------------------
---------- XADC Interface ----------
xadc_conf => xadc_conf,
xadcPacket_rdy => xadcPacket_rdy,
vmm_id_xadc => vmm_id_xadc,
xadc_sample_size => xadc_sample_size,
xadc_delay => xadc_delay,
------------------------------------
---------- AXI4SPI Interface -------
flash_conf => flash_conf,
flashPacket_rdy => flashPacket_rdy,
myIP_set => myIP_set,
myMAC_set => myMAC_set,
destIP_set => destIP_set,
------------------------------------
-------- CKTP/CKBC Interface -------
ckbc_freq => ckbc_freq,
cktk_max_num => cktk_max_num,
cktp_max_num => cktp_max_num,
cktp_skew => cktp_skew,
cktp_period => cktp_period,
cktp_width => cktp_width,
ckbc_max_num => ckbc_max_num,
------------------------------------
-------- FPGA Config Interface -----
fpga_conf => fpga_conf,
fpga_rst => fpga_rst_i,
fpgaPacket_rdy => fpgaPacket_rdy,
latency => latency,
tr_delay_limit => open,
daq_on => daq_on,
ext_trigger => ext_trigger,
ckbcMode => ckbcMode
);
vmm_config_logic: vmm_config_block
port map(
------------------------------------
------- General Interface ----------
clk_125 => clk_125,
clk_40 => clk_40,
rst => rst,
rst_fifo => rst_fifo_s40,
cnt_bytes => cnt_bytes,
------------------------------------
--------- FIFO/UDP Interface -------
user_din_udp => user_data_prv,
user_valid_udp => user_valid_prv,
user_last_udp => user_last_prv,
------------------------------------
------ VMM Config Interface --------
vmmConf_rdy => vmm_conf_rdy,
vmmConf_done => vmm_ser_done,
vmm_sck => vmm_sck,
vmm_cs => vmm_cs,
vmm_cfg_bit => vmm_cfg_bit,
vmm_conf => vmm_conf,
top_rdy => top_rdy_s40,
init_ser => init_ser_s40
);
xadc_rdy <= xadcPacket_rdy;
newIP_rdy <= flashPacket_rdy;
vmmConf_rdy <= init_ser;
vmmConf_done <= vmmSer_done_s125;
state_o <= std_logic_vector(conf_state);
valid_o <= user_valid_prv;
vmmConf_came <= vmm_conf;
rst_fifo_vmmConf<= rst_fifo or rst_fifo_init;
glbl_rst_buf: BUFG port map (O => fpga_rst, I => fpga_rst_i);
---------------------------------------------------------
--------- Clock Domain Crossing Sync Block --------------
---------------------------------------------------------
CDCC_125to40: CDCC
generic map(NUMBER_OF_BITS => 3)
port map(
clk_src => clk_125,
clk_dst => clk_40,
data_in(0) => init_ser,
data_in(1) => rst_fifo_vmmConf,
data_in(2) => top_rdy,
data_out_s(0) => init_ser_s40,
data_out_s(1) => rst_fifo_s40,
data_out_s(2) => top_rdy_s40
);
CDCC_40to125: CDCC
generic map(NUMBER_OF_BITS => 1)
port map(
clk_src => clk_40,
clk_dst => clk_125,
data_in(0) => vmm_ser_done,
data_out_s(0) => vmmSer_done_s125
);
---------------------------------------------------------
---------------------------------------------------------
---------------------------------------------------------
end RTL; | gpl-3.0 | aaac58b3b821e81d712c04fd9e534baf | 0.46756 | 4.122659 | false | false | false | false |
adelapie/noekeon | round_f.vhd | 2 | 4,995 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity round_f is
port(enc : in std_logic;
rc_in : in std_logic_vector(31 downto 0);
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end round_f;
architecture Behavioral of round_f is
signal a_0_in_s : std_logic_vector(31 downto 0);
signal theta_0_s : std_logic_vector(31 downto 0);
signal theta_1_s : std_logic_vector(31 downto 0);
signal theta_2_s : std_logic_vector(31 downto 0);
signal theta_3_s : std_logic_vector(31 downto 0);
signal pi_1_1_s : std_logic_vector(31 downto 0);
signal pi_1_2_s : std_logic_vector(31 downto 0);
signal pi_1_3_s : std_logic_vector(31 downto 0);
signal gamma_0_s : std_logic_vector(31 downto 0);
signal gamma_1_s : std_logic_vector(31 downto 0);
signal gamma_2_s : std_logic_vector(31 downto 0);
signal gamma_3_s : std_logic_vector(31 downto 0);
signal pi_2_1_s : std_logic_vector(31 downto 0);
signal pi_2_2_s : std_logic_vector(31 downto 0);
signal pi_2_3_s : std_logic_vector(31 downto 0);
component theta is
port(a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component pi_1 is
port(a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component gamma is
port(a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component pi_2 is
port(a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
signal a_0_aux_s : std_logic_vector(31 downto 0);
begin
a_0_in_s <= (a_0_in xor rc_in) when enc = '0' else a_0_in;
THETA_0 : theta port map (a_0_in_s,
a_1_in,
a_2_in,
a_3_in,
k_0_in,
k_1_in,
k_2_in,
k_3_in,
theta_0_s,
theta_1_s,
theta_2_s,
theta_3_s);
PI_1_0 : pi_1 port map (theta_1_s,
theta_2_s,
theta_3_s,
pi_1_1_s,
pi_1_2_s,
pi_1_3_s);
a_0_aux_s <= (theta_0_s xor rc_in) when enc = '1' else theta_0_s;
GAMMA_0 : gamma port map (a_0_aux_s,
pi_1_1_s,
pi_1_2_s,
pi_1_3_s,
gamma_0_s,
gamma_1_s,
gamma_2_s,
gamma_3_s);
PI_2_0 : pi_2 port map (gamma_1_s,
gamma_2_s,
gamma_3_s,
pi_2_1_s,
pi_2_2_s,
pi_2_3_s);
a_0_out <= gamma_0_s;
a_1_out <= pi_2_1_s;
a_2_out <= pi_2_2_s;
a_3_out <= pi_2_3_s;
end Behavioral;
| gpl-3.0 | 4388afd5e2514bbc8504e544c110e3fa | 0.605606 | 2.675415 | false | false | false | false |
GustaMagik/RSA_Security_Token | VHDL_code/ver_A/RSA_Security_Token_Keyboard_Version/byte_to_six_bit_splitter.vhdl | 1 | 4,526 |
--Copyright 2017 Christoffer Mathiesen, Gustav Örtenberg
--Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
--
--1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
--
--2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the
--documentation and/or other materials provided with the distribution.
--
--3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this
--software without specific prior written permission.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS
--BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
--GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
--LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
----------------------------------------------------------------------------------
--This module splices memory(arrays) of 8 bits into 6 bit(arrays)
--When on the third byte it has to take a cycle to output the remaining
--6 bits. Then it loops.
--Active as long as the input flag ACTICVE = '1'
--Asks the above module to increment the address pointer with INC_ADDR;
----------------------------------------------------------------------------------
entity byte_to_six_bit_splitter is
Port ( DATA_IN : in STD_LOGIC_VECTOR (7 downto 0);
DATA_OUT : out STD_LOGIC_VECTOR (5 downto 0);
INC_ADDR : out STD_LOGIC := '0';
ACTIVE : in STD_LOGIC;
CLK : in STD_LOGIC;
RESET : in STD_LOGIC);
end byte_to_six_bit_splitter;
architecture Behavioral of byte_to_six_bit_splitter is
type Current is (WAIT_1, SIX_TWO, FOUR_FOUR, TWO_SIX, INTERMISSION);
signal State : Current := SIX_TWO;
signal TMP : STD_LOGIC_VECTOR (5 downto 0) := (others => '0');
begin
process (clk)
Begin
if rising_edge(clk) then
if ACTIVE = '1' then --and RESET = '0' then --State changes
case State is
when INTERMISSION =>
State <= SIX_TWO;
when SIX_TWO =>
State <= FOUR_FOUR;
when FOUR_FOUR =>
State <= TWO_SIX;
when TWO_SIX =>
State <= INTERMISSION; --Pause to give fourth 6-bit
when others =>
State <= SIX_TWO;
end case;
else
State <= SIX_TWO;
-- elsif RESET = '1' then
--TMP <= (others => '0');
-- State <= SIX_TWO;
--INC_ADDR <= '0';
end if;
end if;
end process;
process (State, clk)
Begin
if rising_edge(clk) then
case State is
when SIX_TWO =>
DATA_OUT <= DATA_IN(5 downto 0); --Output the 6 MSB of data in
TMP(1 downto 0)<= DATA_IN(7 downto 6); --Store the 2 LSB of data in
INC_ADDR <= '1'; --Tell the above module to inc the RAM address
when FOUR_FOUR =>
DATA_OUT <= DATA_IN(3 downto 0) & TMP(1 downto 0); --Output the stored 2 bits as MSB and the 4 MSB of data in as LSB
TMP(3 downto 0)<= DATA_IN(7 downto 4); --Store the 4 LSB of data in
INC_ADDR <= '0'; --Tell the above module to inc the RAM address
when TWO_SIX =>
DATA_OUT <= DATA_IN(1 downto 0) & TMP(3 downto 0); --Output the stored 4 bits as MSB and the 2 MSB of data in as LSB
TMP <= DATA_IN(7 downto 2); --Store the 6 LSB of data in
INC_ADDR <= '1'; --Tell the above module to inc the RAM address
when INTERMISSION =>
DATA_OUT <= TMP; --Output the stored 6 bits as the complete vector
INC_ADDR <= '1'; --Tell the above module to NOT inc the RAM address
when others =>
INC_ADDR <= '1';
end case;
end if;
end process;
end Behavioral;
| bsd-3-clause | 27ab8075b5776870d55039d752de5972 | 0.654441 | 3.703764 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4400/EPROC_IN2_DEC8b10b.vhd | 1 | 5,730 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 05/19/2014
--! Module Name: EPROC_IN2_DEC8b10b
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.all;
use work.all;
use work.centralRouter_package.all;
--! 8b10b decoder for EPROC_IN2 module
entity EPROC_IN2_DEC8b10b is
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
edataIN : in std_logic_vector (1 downto 0);
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic;
busyOut : out std_logic
);
end EPROC_IN2_DEC8b10b;
architecture Behavioral of EPROC_IN2_DEC8b10b is
signal EDATAbitstreamSREG : std_logic_vector (11 downto 0) := (others=>'0'); -- 12 bit (2 x 5 = 10, plus 2 more)
signal word10b_align_array, word10b_align_array_r : word10b_2array_type;
signal word10b : std_logic_vector (9 downto 0) := (others=>'0');
signal comma_valid_bits_or, word10b_align_rdy_r : std_logic;
signal align_select, word10b_rdy : std_logic := '0';
signal comma_valid_bits : std_logic_vector (1 downto 0);
signal alignment_sreg : std_logic_vector (4 downto 0) := (others=>'0');
begin
-------------------------------------------------------------------------------------------
--live bitstream
-- input shift register
-------------------------------------------------------------------------------------------
process(bitCLK, rst)
begin
if rst = '1' then
EDATAbitstreamSREG <= (others => '0');
elsif rising_edge(bitCLK) then
EDATAbitstreamSREG <= edataIN & EDATAbitstreamSREG(11 downto 2);
end if;
end process;
--
-------------------------------------------------------------------------------------------
--clock0
-- input shift register mapping into 10 bit registers
-------------------------------------------------------------------------------------------
input_map: for I in 0 to 1 generate -- 1 10bit-word per alignment, 2 possible alignments
--word10b_align_array(I) <= EDATAbitstreamSREG((I+9) downto (I+0)); -- 10 bit word, alligned to bit I
word10b_align_array(I) <= EDATAbitstreamSREG(I+0)&EDATAbitstreamSREG(I+1)&EDATAbitstreamSREG(I+2)&EDATAbitstreamSREG(I+3)&EDATAbitstreamSREG(I+4)&
EDATAbitstreamSREG(I+5)&EDATAbitstreamSREG(I+6)&EDATAbitstreamSREG(I+7)&EDATAbitstreamSREG(I+8)&EDATAbitstreamSREG(I+9); -- 10 bit word, alligned to bit I
end generate input_map;
--
-------------------------------------------------------------------------------------------
--clock0
-- K28.5 comma test
-------------------------------------------------------------------------------------------
comma_test: for I in 0 to 1 generate -- 1 10bit-word per alignment, comma is valid if two first words have comma...
comma_valid_bits(I) <= '1' when (word10b_align_array(I) = COMMAp or word10b_align_array(I) = COMMAn) else '0';
end generate comma_test;
--
comma_valid_bits_or <= comma_valid_bits(1) or comma_valid_bits(0);
--
-------------------------------------------------------------------------------------------
--clock1
-- alignment selector state
-------------------------------------------------------------------------------------------
process(bitCLK, rst)
begin
if rst = '1' then
alignment_sreg <= "00000";
elsif rising_edge(bitCLK) then
if comma_valid_bits_or = '1' then
alignment_sreg <= "10000";
else
alignment_sreg <= alignment_sreg(0) & alignment_sreg(4 downto 1);
end if;
end if;
end process;
--
input_reg1: process(bitCLK)
begin
if rising_edge(bitCLK) then
word10b_align_array_r <= word10b_align_array;
end if;
end process;
--
word10b_align_rdy_r <= alignment_sreg(4);
--
process(bitCLK, rst)
begin
if rst = '1' then
align_select <= '0';
elsif rising_edge(bitCLK) then
if comma_valid_bits_or = '1' then
align_select <= (not comma_valid_bits(0)) and comma_valid_bits(1);
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
--clock2
-- alignment selected
-------------------------------------------------------------------------------------------
--
input_reg2: process(bitCLK)
begin
if rising_edge(bitCLK) then
word10b_rdy <= word10b_align_rdy_r;
end if;
end process;
--
process(bitCLK)
begin
if rising_edge(bitCLK) then
case (align_select) is
when '0' => -- bit0 word got comma => align to bit0
word10b <= word10b_align_array_r(0);
when '1' => -- bit1 word got comma => align to bit1
word10b <= word10b_align_array_r(1);
when others =>
end case;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- at this stage: word10b and word10b_rdy are aligned @ bitCLK
-------------------------------------------------------------------------------------------
EPROC_IN2_ALIGN_BLOCK_inst: entity work.EPROC_IN2_ALIGN_BLOCK
port map(
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst,
bytes => word10b,
bytes_rdy => word10b_rdy,
dataOUT => dataOUT,
dataOUTrdy => dataOUTrdy,
busyOut => busyOut
);
end Behavioral;
| gpl-3.0 | 3e68ebdfaa264a2b143d30992aeab26f | 0.478185 | 4.001397 | false | false | false | false |
rkrajnc/minimig-mist | rtl/tg68k/TG68KdotC_Kernel.vhd | 1 | 110,234 | ------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- Copyright (c) 2009-2013 Tobias Gubener --
-- Patches by MikeJ, Till Harbaum, Rok Krajnk, ... --
-- Subdesign fAMpIGA by TobiFlex --
-- --
-- This source file is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published --
-- by the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This source file is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS For A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- optimize Register file
-- to do 68010:
-- (MOVEC)
-- BKPT
-- RTD
-- MOVES
--
-- to do 68020:
-- (CALLM)
-- (RETM)
-- CAS, CAS2
-- CHK2
-- CMP2
-- cpXXX Coprozessor stuff
-- TRAPcc
-- done 020:
-- PACK, UNPK
-- Bitfields
-- address modes
-- long bra
-- DIVS.L, DIVU.L
-- LINK long
-- MULS.L, MULU.L
-- extb.l
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.ALL;
use work.TG68K_Pack.ALL;
entity TG68KdotC_Kernel is
generic (
SR_Read : integer := 0; --0=>user, 1=>privileged, 2=>switchable with CPU(0)
VBR_Stackframe : integer := 0; --0=>no, 1=>yes/extended, 2=>switchable with CPU(0)
extAddr_Mode : integer := 0; --0=>no, 1=>yes, 2=>switchable with CPU(1)
MUL_Mode : integer := 0; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
DIV_Mode : integer := 0; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
BitField : integer := 0 --0=>no, 1=>yes, 2=>switchable with CPU(1)
);
port (
clk : in std_logic;
nReset : in std_logic; --low active
clkena_in : in std_logic := '1';
data_in : in std_logic_vector(15 downto 0);
IPL : in std_logic_vector( 2 downto 0) := "111";
IPL_autovector : in std_logic := '1'; -- ACTIVE LOW
berr : in std_logic :='0'; -- only 68000 Stackpointer dummy
CPU : in std_logic_vector( 1 downto 0) := "00"; -- 00->68000 01->68010 11->68020(only some parts - yet)
addr_out : out std_logic_vector(31 downto 0);
data_write : out std_logic_vector(15 downto 0);
nWr : out std_logic;
nUDS : out std_logic;
nLDS : out std_logic;
busstate : out std_logic_vector(1 downto 0); -- 00-> fetch code 10->read data 11->write data 01->no memaccess
nResetOut : out std_logic;
FC : out std_logic_vector(2 downto 0);
clr_berr : out std_logic;
-- for debug
skipFetch : out std_logic;
regin_out : out std_logic_vector(31 downto 0);
CACR_out : out std_logic_vector( 3 downto 0);
VBR_out : out std_logic_vector(31 downto 0)
);
end TG68KdotC_Kernel;
--nBS : std_logic_vector(3 downto 0); -- nBS0 is 31..24 3 is 7..0, active LOW
--SIZ : std_logic_vector(1 downto 0);
--ACK for 16/32 bit transfer?
architecture logic of TG68KdotC_Kernel is
signal syncReset : std_logic_vector(3 downto 0);
signal Reset : std_logic;
signal clkena_lw : std_logic;
signal TG68_PC : std_logic_vector(31 downto 0);
signal tmp_TG68_PC : std_logic_vector(31 downto 0);
signal TG68_PC_add : std_logic_vector(31 downto 0);
signal PC_dataa : std_logic_vector(31 downto 0);
signal PC_datab : std_logic_vector(31 downto 0);
signal memaddr : std_logic_vector(31 downto 0);
signal state : std_logic_vector(1 downto 0);
signal datatype : std_logic_vector(1 downto 0);
signal set_datatype : std_logic_vector(1 downto 0);
signal exe_datatype : std_logic_vector(1 downto 0);
signal setstate : std_logic_vector(1 downto 0);
signal opcode : std_logic_vector(15 downto 0);
signal exe_opcode : std_logic_vector(15 downto 0);
signal exe_pc : std_logic_vector(31 downto 0);
signal last_opc_pc : std_logic_vector(31 downto 0);
signal sndOPC : std_logic_vector(15 downto 0);
signal last_opc_read : std_logic_vector(15 downto 0);
signal reg_QA : std_logic_vector(31 downto 0);
signal reg_QB : std_logic_vector(31 downto 0);
signal Wwrena : bit;
signal Lwrena : bit;
signal Bwrena : bit;
signal Regwrena_now : bit;
signal rf_dest_addr : std_logic_vector(3 downto 0);
signal rf_source_addr : std_logic_vector(3 downto 0);
signal rf_source_addrd : std_logic_vector(3 downto 0);
type regfile_t is ARRAY(0 TO 15) OF std_logic_vector(31 downto 0);
signal regfile : regfile_t := (OTHERS => (OTHERS => '0')); -- mikej stops sim X issues;
signal RDindex_A : integer range 0 TO 15;
signal RDindex_B : integer range 0 TO 15;
signal WR_AReg : std_logic;
signal addr : std_logic_vector(31 downto 0);
signal memaddr_reg : std_logic_vector(31 downto 0);
signal memaddr_delta : std_logic_vector(31 downto 0);
signal use_base : bit;
signal ea_data : std_logic_vector(31 downto 0);
signal OP1out : std_logic_vector(31 downto 0);
signal OP2out : std_logic_vector(31 downto 0);
signal OP1outbrief : std_logic_vector(15 downto 0);
signal OP1in : std_logic_vector(31 downto 0);
signal ALUout : std_logic_vector(31 downto 0);
signal data_write_tmp : std_logic_vector(31 downto 0);
signal data_write_muxin : std_logic_vector(31 downto 0);
signal data_write_mux : std_logic_vector(47 downto 0);
signal nextpass : bit;
signal setnextpass : bit;
signal setdispbyte : bit;
signal setdisp : bit;
signal regdirectsource : bit; -- checken !!!
signal addsub_q : std_logic_vector(31 downto 0);
signal briefdata : std_logic_vector(31 downto 0);
signal c_out : std_logic_vector(2 downto 0);
signal mem_address : std_logic_vector(31 downto 0);
signal memaddr_a : std_logic_vector(31 downto 0);
signal TG68_PC_brw : bit;
signal TG68_PC_word : bit;
signal getbrief : bit;
signal brief : std_logic_vector(15 downto 0);
signal dest_areg : std_logic;
signal source_areg : std_logic;
signal data_is_source : bit;
signal store_in_tmp : bit;
signal write_back : bit;
signal exec_write_back : bit;
signal setstackaddr : bit;
signal writePC : bit;
signal writePCbig : bit;
signal set_writePCbig : bit;
signal setopcode : bit;
signal decodeOPC : bit;
signal execOPC : bit;
signal setexecOPC : bit;
signal endOPC : bit;
signal setendOPC : bit;
signal Flags : std_logic_vector(7 downto 0); -- ...XNZVC
signal FlagsSR : std_logic_vector(7 downto 0) := (others => '0'); -- T.S..III
signal SRin : std_logic_vector(7 downto 0);
signal exec_DIRECT : bit;
signal exec_tas : std_logic;
signal set_exec_tas : std_logic;
signal exe_condition : std_logic;
signal ea_only : bit;
signal source_lowbits : bit;
signal source_2ndHbits : bit;
signal source_2ndLbits : bit;
signal dest_2ndHbits : bit;
signal dest_hbits : bit;
signal rot_bits : std_logic_vector(1 downto 0);
signal set_rot_bits : std_logic_vector(1 downto 0);
signal rot_cnt : std_logic_vector(5 downto 0);
signal set_rot_cnt : std_logic_vector(5 downto 0);
signal movem_actiond : bit;
signal movem_regaddr : std_logic_vector(3 downto 0);
signal movem_mux : std_logic_vector(3 downto 0);
signal movem_presub : bit;
signal movem_run : bit;
signal ea_calc_b : std_logic_vector(31 downto 0);
signal set_direct_data : bit;
signal use_direct_data : bit;
signal direct_data : bit;
signal set_V_Flag : bit;
signal set_vectoraddr : bit;
signal writeSR : bit;
signal trap_berr : bit;
signal trap_illegal : bit;
signal trap_addr_error : bit;
signal trap_priv : bit;
signal trap_trace : bit;
signal trap_1010 : bit;
signal trap_1111 : bit;
signal trap_trap : bit;
signal trap_trapv : bit;
signal trap_interrupt : bit;
signal trapmake : bit;
signal trapd : bit;
signal trap_SR : std_logic_vector(7 downto 0);
signal make_trace : std_logic;
signal make_berr : std_logic;
signal set_stop : bit;
signal stop : bit;
signal trap_vector : std_logic_vector(31 downto 0);
signal trap_vector_vbr : std_logic_vector(31 downto 0);
signal USP : std_logic_vector(31 downto 0);
signal illegal_write_mode : bit;
signal illegal_read_mode : bit;
signal illegal_byteaddr : bit;
signal IPL_nr : std_logic_vector(2 downto 0);
signal rIPL_nr : std_logic_vector(2 downto 0);
signal IPL_vec : std_logic_vector(7 downto 0);
signal interrupt : bit;
signal setinterrupt : bit;
signal SVmode : std_logic;
signal preSVmode : std_logic;
signal Suppress_Base : bit;
signal set_Suppress_Base : bit;
signal set_Z_error : bit;
signal Z_error : bit;
signal ea_build_now : bit;
signal build_logical : bit;
signal build_bcd : bit;
signal data_read : std_logic_vector(31 downto 0);
signal bf_ext_in : std_logic_vector(7 downto 0);
signal bf_ext_out : std_logic_vector(7 downto 0);
signal byte : bit;
signal long_start : bit;
signal long_start_alu : bit;
signal non_aligned : std_logic;
signal long_done : bit;
signal memmask : std_logic_vector(5 downto 0);
signal set_memmask : std_logic_vector(5 downto 0);
signal memread : std_logic_vector(3 downto 0);
signal wbmemmask : std_logic_vector(5 downto 0);
signal memmaskmux : std_logic_vector(5 downto 0);
signal oddout : std_logic;
signal set_oddout : std_logic;
signal PCbase : std_logic;
signal set_PCbase : std_logic;
signal last_data_read : std_logic_vector(31 downto 0);
signal last_data_in : std_logic_vector(31 downto 0);
signal bf_offset : std_logic_vector(31 downto 0);
signal bf_offset_l : std_logic_vector(4 downto 0);
signal bf_loffset : std_logic_vector(4 downto 0);
signal bf_width : std_logic_vector(4 downto 0);
signal bf_bhits : std_logic_vector(5 downto 0);
signal alu_bf_width : std_logic_vector(4 downto 0);
signal alu_bf_offset : std_logic_vector(31 downto 0);
signal alu_bf_loffset : std_logic_vector(4 downto 0);
signal movec_data : std_logic_vector(31 downto 0);
signal VBR : std_logic_vector(31 downto 0);
signal CACR : std_logic_vector(3 downto 0);
signal DFC : std_logic_vector(2 downto 0);
signal SFC : std_logic_vector(2 downto 0);
signal set : bit_vector(lastOpcBit downto 0);
signal set_exec : bit_vector(lastOpcBit downto 0);
signal exec : bit_vector(lastOpcBit downto 0);
signal exec_d : rTG68K_opc;
signal micro_state : micro_states;
signal next_micro_state : micro_states;
signal regin : std_logic_vector(31 downto 0);
begin
ALU : TG68K_ALU
generic map(
MUL_Mode => MUL_Mode, --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
DIV_Mode => DIV_Mode --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
)
port map(
clk => clk, --: in std_logic;
Reset => Reset, --: in std_logic;
clkena_lw => clkena_lw, --: in std_logic:='1';
execOPC => execOPC, --: in bit;
exe_condition => exe_condition, --: in std_logic;
exec_tas => exec_tas, --: in std_logic;
long_start => long_start_alu, --: in bit;
non_aligned => non_aligned,
movem_presub => movem_presub, --: in bit;
set_stop => set_stop, --: in bit;
Z_error => Z_error, --: in bit;
rot_bits => rot_bits, --: in std_logic_vector(1 downto 0);
exec => exec, --: in bit_vector(lastOpcBit downto 0);
OP1out => OP1out, --: in std_logic_vector(31 downto 0);
OP2out => OP2out, --: in std_logic_vector(31 downto 0);
reg_QA => reg_QA, --: in std_logic_vector(31 downto 0);
reg_QB => reg_QB, --: in std_logic_vector(31 downto 0);
opcode => opcode, --: in std_logic_vector(15 downto 0);
datatype => datatype, --: in std_logic_vector(1 downto 0);
exe_opcode => exe_opcode, --: in std_logic_vector(15 downto 0);
exe_datatype => exe_datatype, --: in std_logic_vector(1 downto 0);
sndOPC => sndOPC, --: in std_logic_vector(15 downto 0);
last_data_read => last_data_read(15 downto 0), --: in std_logic_vector(31 downto 0);
data_read => data_read(15 downto 0), --: in std_logic_vector(31 downto 0);
FlagsSR => FlagsSR, --: in std_logic_vector(7 downto 0);
micro_state => micro_state, --: in micro_states;
bf_ext_in => bf_ext_in,
bf_ext_out => bf_ext_out,
bf_width => alu_bf_width,
bf_offset => alu_bf_offset,
bf_loffset => alu_bf_loffset,
set_V_Flag_out => set_V_Flag, --: buffer bit;
Flags_out => Flags, --: buffer std_logic_vector(8 downto 0);
c_out_out => c_out, --: buffer std_logic_vector(2 downto 0);
addsub_q_out => addsub_q, --: buffer std_logic_vector(31 downto 0);
ALUout => ALUout --: buffer std_logic_vector(31 downto 0)
);
long_start_alu <= to_bit(not memmaskmux(3));
process (memmaskmux)
begin
non_aligned <= '0';
if (memmaskmux(5 downto 4) = "01") or (memmaskmux(5 downto 4) = "10") then
non_aligned <= '1';
end if;
end process;
-----------------------------------------------------------------------------
-- Bus control
-----------------------------------------------------------------------------
nWr <= '0' when state = "11" else '1';
busstate <= state;
nResetOut <= '0' when exec(opcRESET) = '1' else '1';
-- does shift for byte access. note active low me
-- should produce address error on 68000
memmaskmux <= memmask when addr(0) = '1' else memmask(4 downto 0) & '1';
nUDS <= memmaskmux(5);
nLDS <= memmaskmux(4);
clkena_lw <= '1' when clkena_in = '1' and memmaskmux(3) = '1' else '0'; -- step
clr_berr <= '1' WHEN setopcode='1' AND trap_berr='1' ELSE '0';
process (clk, nReset)
begin
if nReset = '0' then
syncReset <= "0000";
Reset <= '1';
elsif rising_edge(clk) then
if clkena_in = '1' then
syncReset <= syncReset(2 downto 0) & '1';
Reset <= not syncReset(3);
end if;
end if;
end process;
process (clk, long_done, last_data_in, data_in, byte, addr, long_start, memmaskmux, memread, memmask, data_read)
begin
if memmaskmux(4) = '0' then
data_read <= last_data_in(15 downto 0) & data_in;
else
data_read <= last_data_in(23 downto 0) & data_in(15 downto 8);
end if;
if memread(0) = '1' or (memread(1 downto 0) = "10" and memmaskmux(4) = '1') then
data_read(31 downto 16) <= (others => data_read(15));
end if;
if rising_edge(clk) then
if clkena_lw = '1' and state = "10" then
if memmaskmux(4) = '0' then
bf_ext_in <= last_data_in(23 downto 16);
else
bf_ext_in <= last_data_in(31 downto 24);
end if;
end if;
if Reset = '1' then
last_data_read <= (others => '0');
elsif clkena_in = '1' then
if state = "00" or exec(update_ld) = '1' then
last_data_read <= data_read;
if state(1) = '0' and memmask(1) = '0' then
last_data_read(31 downto 16) <= last_opc_read;
elsif state(1) = '0' or memread(1) = '1' then
last_data_read(31 downto 16) <= (others => data_in(15));
end if;
end if;
last_data_in <= last_data_in(15 downto 0) & data_in(15 downto 0);
end if;
end if;
long_start <= to_bit(not memmask(1));
long_done <= to_bit(not memread(1));
end process;
process (byte, long_start, reg_QB, data_write_tmp, exec, data_read, data_write_mux, memmaskmux, bf_ext_out,
data_write_muxin, memmask, oddout, addr)
begin
if exec(write_reg) = '1' then
data_write_muxin <= reg_QB; -- 32 bits
else
data_write_muxin <= data_write_tmp;
end if;
if BitField = 0 then
if oddout = addr(0) then
data_write_mux <= "XXXXXXXX" & "XXXXXXXX" & data_write_muxin;
else
data_write_mux <= "XXXXXXXX" & data_write_muxin & "XXXXXXXX";
end if;
else
if oddout = addr(0) then
data_write_mux <= "XXXXXXXX" & bf_ext_out & data_write_muxin;
else
data_write_mux <= bf_ext_out & data_write_muxin & "XXXXXXXX";
end if;
end if;
if memmaskmux(1) = '0' then
data_write <= data_write_mux(47 downto 32);
elsif memmaskmux(3) = '0' then
data_write <= data_write_mux(31 downto 16);
else
data_write <= data_write_mux(15 downto 0);
end if;
if exec(mem_byte) = '1' then --movep
data_write(7 downto 0) <= data_write_tmp(15 downto 8);
end if;
end process;
-----------------------------------------------------------------------------
-- Registerfile
-----------------------------------------------------------------------------
process (clk, regfile, RDindex_A, RDindex_B, exec)
begin
reg_QA <= regfile(RDindex_A);
reg_QB <= regfile(RDindex_B);
if rising_edge(clk) then
if clkena_lw = '1' then
rf_source_addrd <= rf_source_addr;
WR_AReg <= rf_dest_addr(3);
RDindex_A <= conv_integer(rf_dest_addr(3 downto 0));
RDindex_B <= conv_integer(rf_source_addr(3 downto 0));
if Wwrena = '1' then
regfile(RDindex_A) <= regin;
end if;
if exec(to_USP) = '1' then
USP <= reg_QA;
end if;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Write Reg
-----------------------------------------------------------------------------
process (OP1in, reg_QA, Regwrena_now, Bwrena, Lwrena, exe_datatype, WR_AReg, movem_actiond, exec, ALUout, memaddr, memaddr_a, ea_only, USP, movec_data)
begin
regin <= ALUout;
if exec(save_memaddr) = '1' then -- only used for movem
regin <= memaddr;
elsif exec(get_ea_now) = '1' and ea_only = '1' then
regin <= memaddr_a;
elsif exec(from_USP) = '1' then
regin <= USP;
elsif exec(movec_rd) = '1' then
regin <= movec_data;
end if;
if Bwrena = '1' then
regin(15 downto 8) <= reg_QA(15 downto 8);
end if;
if Lwrena = '0' then
regin(31 downto 16) <= reg_QA(31 downto 16);
end if;
Bwrena <= '0';
Wwrena <= '0';
Lwrena <= '0';
if exec(presub) = '1' or exec(postadd) = '1' or exec(changeMode) = '1' then -- -(An)+
Wwrena <= '1';
Lwrena <= '1';
elsif Regwrena_now = '1' then --dbcc
Wwrena <= '1';
elsif exec(Regwrena) = '1' then --read (mem)
Wwrena <= '1';
case exe_datatype is
when "00" => --BYTE
Bwrena <= '1';
when "01" => --WorD
if WR_AReg = '1' or movem_actiond = '1' then
Lwrena <= '1';
end if;
when others => --LONG
Lwrena <= '1';
end case;
end if;
end process;
-----------------------------------------------------------------------------
-- set dest regaddr
-----------------------------------------------------------------------------
process (opcode, rf_source_addrd, brief, setstackaddr, dest_hbits, dest_areg, data_is_source, sndOPC, exec, set, dest_2ndHbits)
begin
if exec(movem_action) = '1' then
rf_dest_addr <= rf_source_addrd;
elsif set(briefext) = '1' then
rf_dest_addr <= brief(15 downto 12);
elsif set(get_bfoffset) = '1' then
rf_dest_addr <= sndOPC(9 downto 6);
elsif dest_2ndHbits = '1' then
rf_dest_addr <= sndOPC(15 downto 12);
elsif set(write_reminder) = '1' then
rf_dest_addr <= sndOPC(3 downto 0);
elsif setstackaddr = '1' then
rf_dest_addr <= "1111";
elsif dest_hbits = '1' then
rf_dest_addr <= dest_areg & opcode(11 downto 9);
else
if opcode(5 downto 3) = "000" or data_is_source = '1' then
rf_dest_addr <= dest_areg & opcode(2 downto 0);
else
rf_dest_addr <= '1' & opcode(2 downto 0);
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- set source regaddr
-----------------------------------------------------------------------------
process (opcode, movem_presub, movem_regaddr, source_lowbits, source_areg, sndOPC, exec, set, source_2ndLbits, source_2ndHbits)
begin
if exec(movem_action) = '1' or set(movem_action) = '1' then
if movem_presub = '1' then
rf_source_addr <= movem_regaddr Xor "1111";
else
rf_source_addr <= movem_regaddr;
end if;
elsif source_2ndLbits = '1' then
rf_source_addr <= sndOPC(3 downto 0);
elsif source_2ndHbits = '1' then
rf_source_addr <= sndOPC(15 downto 12);
elsif source_lowbits = '1' then
rf_source_addr <= source_areg & opcode(2 downto 0);
elsif exec(linksp) = '1' then
rf_source_addr <= "1111";
else
rf_source_addr <= source_areg & opcode(11 downto 9);
end if;
end process;
-----------------------------------------------------------------------------
-- set OP1out
-----------------------------------------------------------------------------
process (reg_QA, store_in_tmp, ea_data, long_start, addr, exec, memmaskmux)
begin
OP1out <= reg_QA;
if exec(OP1out_zero) = '1' then
OP1out <= (others => '0');
elsif exec(ea_data_OP1) = '1' and store_in_tmp = '1' then
OP1out <= ea_data;
elsif exec(opcPACK) = '1' then
OP1out <= data_write_tmp;
elsif exec(movem_action) = '1' or memmaskmux(3) = '0' or exec(OP1addr) = '1' then
OP1out <= addr;
end if;
end process;
-----------------------------------------------------------------------------
-- set OP2out
-----------------------------------------------------------------------------
process ( OP2out, reg_QB, exe_opcode, exe_datatype, execOPC, exec, use_direct_data, store_in_tmp, data_write_tmp, ea_data)
begin
OP2out(15 downto 0) <= reg_QB(15 downto 0);
OP2out(31 downto 16) <= (others => OP2out(15));
if exec(OP2out_one) = '1' then
OP2out(15 downto 0) <= "1111111111111111";
elsif exec(opcEXT) = '1' then
if exe_opcode(6) = '0' or exe_opcode(8) = '1' then --ext.w
OP2out(15 downto 8) <= (others => OP2out(7));
end if;
elsif (use_direct_data = '1' and exec(opcPACK) = '0') or (exec(exg) = '1' and execOPC = '1') or exec(get_bfoffset) = '1' then
OP2out <= data_write_tmp;
elsif (exec(ea_data_OP1) = '0' and store_in_tmp = '1') or exec(ea_data_OP2) = '1' then
OP2out <= ea_data;
elsif exec(opcMOVEQ) = '1' then
OP2out(7 downto 0) <= exe_opcode(7 downto 0);
OP2out(15 downto 8) <= (others => exe_opcode(7));
elsif exec(opcADDQ) = '1' then
OP2out(2 downto 0) <= exe_opcode(11 downto 9);
if exe_opcode(11 downto 9) = "000" then
OP2out(3) <= '1';
else
OP2out(3) <= '0';
end if;
OP2out(15 downto 4) <= (others => '0');
elsif exe_datatype = "10" then
OP2out(31 downto 16) <= reg_QB(31 downto 16);
end if;
end process;
-----------------------------------------------------------------------------
-- handle EA_data, data_write
-----------------------------------------------------------------------------
process (clk)
begin
if rising_edge(clk) then
if Reset = '1' then
store_in_tmp <= '0';
exec_write_back <= '0';
direct_data <= '0';
use_direct_data <= '0';
Z_error <= '0';
elsif clkena_lw = '1' then
direct_data <= '0';
if state = "11" then
exec_write_back <= '0';
elsif setstate = "10" and write_back = '1' then
exec_write_back <= '1';
end if;
if set_direct_data = '1' then
direct_data <= '1';
if set_exec(opcPACK) = '1' then
use_direct_data <= '0';
else
use_direct_data <= '1';
end if;
elsif endOPC = '1' then
use_direct_data <= '0';
end if;
exec_DIRECT <= set_exec(opcMOVE);
if endOPC = '1' then
store_in_tmp <= '0';
Z_error <= '0';
else
if set_Z_error = '1' then
Z_error <= '1';
end if;
if set_exec(opcMOVE) = '1' and state = "11" then
use_direct_data <= '1';
end if;
if state = "10" then
store_in_tmp <= '1';
end if;
if direct_data = '1' and state = "00" then
store_in_tmp <= '1';
end if;
end if;
if state = "10" then
ea_data <= data_read;
elsif exec(get_2ndOPC)='1' or set_PCbase='1' THEN --TH cmpi (d16,PC) fix
ea_data <= addr;
elsif exec(store_ea_data) = '1' or (direct_data = '1' and state = "00") then
ea_data <= last_data_read;
end if;
if writePC = '1' then
data_write_tmp <= TG68_PC;
elsif exec(writePC_add) = '1' then
data_write_tmp <= TG68_PC_add;
elsif micro_state=trap00 THEN
data_write_tmp <= exe_pc; --TH
elsif micro_state = trap0 then
-- this is only active for 010+ since in 000 writePC is
-- true in state trap0
if trap_trace='1' then
-- stack frame format #2
data_write_tmp(15 downto 0) <= "0010" & trap_vector(11 downto 0); --TH
else
data_write_tmp(15 downto 0) <= "0000" & trap_vector(11 downto 0);
end if;
elsif exec(hold_dwr) = '1' then
data_write_tmp <= data_write_tmp;
elsif exec(exg) = '1' then
data_write_tmp <= OP1out;
elsif exec(get_ea_now) = '1' and ea_only = '1' then -- ist for pea
data_write_tmp <= addr;
elsif execOPC = '1' or micro_state = pack2 then
data_write_tmp <= ALUout;
elsif (exec_DIRECT = '1' and state = "10") then
data_write_tmp <= data_read;
if exec(movepl) = '1' then
data_write_tmp(31 downto 8) <= data_write_tmp(23 downto 0);
end if;
elsif exec(movepl) = '1' then
data_write_tmp(15 downto 0) <= reg_QB(31 downto 16);
elsif direct_data = '1' then
data_write_tmp <= last_data_read;
elsif writeSR = '1' then
data_write_tmp(15 downto 0) <= trap_SR(7 downto 0) & Flags(7 downto 0);
else
data_write_tmp <= OP2out;
end if;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- brief
-----------------------------------------------------------------------------
process (brief, OP1out, OP1outbrief, cpu)
begin
if brief(11) = '1' then
OP1outbrief <= OP1out(31 downto 16);
else
OP1outbrief <= (others => OP1out(15));
end if;
briefdata <= OP1outbrief & OP1out(15 downto 0);
if extAddr_Mode = 1 or (cpu(1) = '1' and extAddr_Mode = 2) then
case brief(10 downto 9) is -- mikej SCALE factor
when "00" => briefdata <= OP1outbrief & OP1out(15 downto 0);
when "01" => briefdata <= OP1outbrief(14 downto 0) & OP1out(15 downto 0) & '0';
when "10" => briefdata <= OP1outbrief(13 downto 0) & OP1out(15 downto 0) & "00";
when "11" => briefdata <= OP1outbrief(12 downto 0) & OP1out(15 downto 0) & "000";
when others => NULL;
end case;
end if;
end process;
-----------------------------------------------------------------------------
-- MEM_IO
-----------------------------------------------------------------------------
process (clk, setdisp, memaddr_a, briefdata, memaddr_delta, setdispbyte, datatype, interrupt, rIPL_nr, IPL_vec,
memaddr_reg, reg_QA, use_base, VBR, last_data_read, trap_vector, exec, set, cpu)
begin
if rising_edge(clk) then
if clkena_lw = '1' then
trap_vector(31 downto 12) <= (others => '0');
if trap_berr='1' then
trap_vector(11 downto 0) <= X"008";
end IF;
if trap_addr_error = '1' then
trap_vector(11 downto 0) <= X"00C";
end if;
if trap_illegal = '1' then
trap_vector(11 downto 0) <= X"010";
end if;
if z_error = '1' then
trap_vector(11 downto 0) <= X"014";
end if;
if exec(trap_chk) = '1' then
trap_vector(11 downto 0) <= X"018";
end if;
if trap_trapv = '1' then
trap_vector(11 downto 0) <= X"01C";
end if;
if trap_priv = '1' then
trap_vector(11 downto 0) <= X"020";
end if;
if trap_trace = '1' then
trap_vector(11 downto 0) <= X"024";
end if;
if trap_1010 = '1' then
trap_vector(11 downto 0) <= X"028";
end if;
if trap_1111 = '1' then
trap_vector(11 downto 0) <= X"02C";
end if;
if trap_trap = '1' then
trap_vector(11 downto 0) <= x"0" & "10" & opcode(3 downto 0) & "00";
end if;
if trap_interrupt = '1' then
trap_vector(11 downto 0) <= "00" & IPL_vec & "00"; --TH
end if;
-- TH TODO: non-autovector IRQs
end if;
end if;
--
if VBR_Stackframe = 0 or (cpu(0) = '0' and VBR_Stackframe = 2) then
trap_vector_vbr <= trap_vector;
else
trap_vector_vbr <= trap_vector + VBR;
end if;
memaddr_a(4 downto 0) <= "00000";
memaddr_a(7 downto 5) <= (others => memaddr_a(4));
memaddr_a(15 downto 8) <= (others => memaddr_a(7));
memaddr_a(31 downto 16) <= (others => memaddr_a(15));
if setdisp = '1' then
if exec(briefext) = '1' then
memaddr_a <= briefdata + memaddr_delta;
elsif setdispbyte = '1' then
memaddr_a(7 downto 0) <= last_data_read(7 downto 0);
else
memaddr_a <= last_data_read;
end if;
elsif set(presub) = '1' then
if set(longaktion) = '1' then
memaddr_a(4 downto 0) <= "11100";
elsif datatype = "00" and set(use_SP) = '0' then
memaddr_a(4 downto 0) <= "11111";
else
memaddr_a(4 downto 0) <= "11110";
end if;
elsif interrupt = '1' then
memaddr_a(4 downto 0) <= '1' & rIPL_nr & '0';
end if;
if rising_edge(clk) then
if clkena_in = '1' then
if exec(get_2ndOPC) = '1' or (state = "10" and memread(0) = '1') then
tmp_TG68_PC <= addr;
end if;
use_base <= '0';
if memmaskmux(3) = '0' then
memaddr_delta <= addsub_q;
elsif exec(mem_addsub) = '1' then
memaddr_delta <= addsub_q;
elsif state = "01" and exec_write_back = '1' then
memaddr_delta <= tmp_TG68_PC;
elsif exec(direct_delta) = '1' then
memaddr_delta <= data_read;
elsif exec(ea_to_pc) = '1' and setstate = "00" then
memaddr_delta <= addr;
elsif set(addrlong) = '1' then
memaddr_delta <= last_data_read;
elsif setstate = "00" then
memaddr_delta <= TG68_PC_add;
elsif exec(dispouter) = '1' then
memaddr_delta <= ea_data + memaddr_a;
elsif set_vectoraddr = '1' then
memaddr_delta <= trap_vector_vbr;
else
memaddr_delta <= memaddr_a;
if interrupt = '0' and Suppress_Base = '0' then
-- if interrupt='0' and Suppress_Base='0' and setstate(1)='1' then
use_base <= '1';
end if;
end if;
-- only used for movem address update
--if (long_done = '0' and state(1) = '1') or movem_presub = '0' then
if ((memread(0) = '1') and state(1) = '1') or movem_presub = '0' then -- fix for unaligned movem mikej
memaddr <= addr;
end if;
end if;
end if;
-- if access done, and not aligned, don't increment
addr <= memaddr_reg + memaddr_delta;
addr_out <= memaddr_reg + memaddr_delta;
if use_base = '0' then
memaddr_reg <= (others => '0');
else
memaddr_reg <= reg_QA;
end if;
end process;
-----------------------------------------------------------------------------
-- PC Calc + fetch opcode
-----------------------------------------------------------------------------
PROCESS (clk, IPL, setstate, state, exec_write_back, set_direct_data, next_micro_state, stop, make_trace, make_berr, IPL_nr, FlagsSR, set_rot_cnt, opcode, writePCbig, set_exec, exec,
PC_dataa, PC_datab, setnextpass, last_data_read, TG68_PC_brw, TG68_PC_word, Z_error, trap_trap, trap_trapv, interrupt, tmp_TG68_PC, TG68_PC)
begin
PC_dataa <= TG68_PC;
if TG68_PC_brw = '1' then
PC_dataa <= tmp_TG68_PC;
end if;
PC_datab(2 downto 0) <= (others => '0');
PC_datab(3) <= PC_datab(2);
PC_datab( 7 downto 4) <= (others => PC_datab(3));
PC_datab(15 downto 8) <= (others => PC_datab(7));
PC_datab(31 downto 16) <= (others => PC_datab(15));
if interrupt = '1' then
PC_datab(2 downto 1) <= "11";
end if;
if exec(writePC_add) = '1' then
if writePCbig = '1' then
PC_datab(3) <= '1';
PC_datab(1) <= '1';
else
PC_datab(2) <= '1';
end if;
if trap_trap = '1' or trap_trapv = '1' or exec(trap_chk) = '1' or Z_error = '1' then
PC_datab(1) <= '1';
end if;
elsif state = "00" then
PC_datab(1) <= '1';
end if;
if TG68_PC_brw = '1' then
if TG68_PC_word = '1' then
PC_datab <= last_data_read;
else
PC_datab(7 downto 0) <= opcode(7 downto 0);
end if;
end if;
TG68_PC_add <= PC_dataa + PC_datab;
setopcode <= '0';
setendOPC <= '0';
setinterrupt <= '0';
if setstate = "00" and next_micro_state = idle and setnextpass = '0' and (exec_write_back = '0' or state = "11") and set_rot_cnt = "000001" and set_exec(opcCHK) = '0' then
setendOPC <= '1';
if FlagsSR(2 downto 0)<IPL_nr or IPL_nr="111" or make_trace='1' or make_berr='1' then
setinterrupt <= '1';
elsif stop = '0' then
setopcode <= '1';
end if;
end if;
setexecOPC <= '0';
if setstate = "00" and next_micro_state = idle and set_direct_data = '0' and (exec_write_back = '0' or state = "10") then
setexecOPC <= '1';
end if;
IPL_nr <= not IPL;
if rising_edge(clk) then
if Reset = '1' then
state <= "01";
opcode <= X"2E79"; --move $0,a7
trap_interrupt <= '0';
interrupt <= '0';
last_opc_read <= X"4EF9"; --jmp nn.l
TG68_PC <= X"00000004";
decodeOPC <= '0';
endOPC <= '0';
TG68_PC_word <= '0';
execOPC <= '0';
stop <= '0';
rot_cnt <= "000001";
byte <= '0';
-- IPL_nr <= "000";
trap_trace <= '0';
trap_berr <= '0';
writePCbig <= '0';
-- recall_last <= '0';
Suppress_Base <= '0';
memmask <= "111111";
else
-- IPL_nr <= not IPL;
if clkena_in = '1' then
-- MIKEJ
memmask <= memmask(3 downto 0) & "11";
memread <= memread(1 downto 0) & memmaskmux(5 downto 4);
-- if wbmemmask(5 downto 4)="11" then
-- wbmemmask <= memmask;
-- end if;
if exec(directPC) = '1' then
TG68_PC <= data_read;
elsif exec(ea_to_pc) = '1' then
TG68_PC <= addr;
elsif (state = "00" or TG68_PC_brw = '1') and stop = '0' then
TG68_PC <= TG68_PC_add;
end if;
end if;
if clkena_lw = '1' then
interrupt <= setinterrupt;
decodeOPC <= setopcode;
endOPC <= setendOPC;
execOPC <= setexecOPC;
exe_datatype <= set_datatype;
exe_opcode <= opcode;
if trap_berr = '0' then
make_berr <= (berr or make_berr);
else
make_berr <= '0';
end if;
stop <= set_stop or (stop and not setinterrupt);
if setinterrupt = '1' then
make_berr <= '0';
trap_berr <= '0';
if make_trace = '1' then
trap_trace <= '1';
elsif make_berr='1' THEN
trap_berr <= '1';
else
rIPL_nr <= IPL_nr;
IPL_vec <= "00011" & IPL_nr; -- TH
trap_interrupt <= '1';
end if;
end if;
if micro_state = trap0 and IPL_autovector = '0' then
IPL_vec <= last_data_read(7 downto 0); -- TH
end if;
if state = "00" then
last_opc_read <= data_read(15 downto 0);
last_opc_pc <= tg68_pc;
end if;
if setopcode = '1' then
trap_interrupt <= '0';
trap_trace <= '0';
TG68_PC_word <= '0';
trap_berr <= '0';
elsif opcode(7 downto 0) = "00000000" or opcode(7 downto 0) = "11111111" or data_is_source = '1' then
TG68_PC_word <= '1';
end if;
if exec(get_bfoffset) = '1' then
alu_bf_width <= bf_width;
alu_bf_loffset <= bf_loffset;
alu_bf_offset <= bf_offset;
end if;
byte <= '0';
memread <= "1111";
FC(1) <= not setstate(1) or (PCbase and not setstate(0));
FC(0) <= setstate(1) and (not PCbase or setstate(0));
if interrupt = '1' then
FC(1 downto 0) <= "11";
end if;
if (state = "10" and write_back = '1' and setstate /= "10") or set_rot_cnt /= "000001" or (stop = '1' and interrupt = '0') or set_exec(opcCHK) = '1' then
state <= "01";
memmask <= "111111";
elsif execOPC = '1' and exec_write_back = '1' then
state <= "11";
FC(1 downto 0) <= "01";
memmask <= wbmemmask;
if datatype = "00" then
byte <= '1';
end if;
else
state <= setstate;
if setstate = "01" then
memmask <= "111111";
wbmemmask <= "111111";
elsif exec(get_bfoffset) = '1' then
memmask <= set_memmask;
wbmemmask <= set_memmask;
oddout <= set_oddout;
elsif set(longaktion) = '1' then
memmask <= "100001";
wbmemmask <= "100001";
oddout <= '0';
elsif set_datatype = "00" and setstate(1) = '1' then
memmask <= "101111";
wbmemmask <= "101111";
if set(mem_byte) = '1' then
oddout <= '0';
else
oddout <= '1';
end if;
else
memmask <= "100111";
wbmemmask <= "100111";
oddout <= '0';
end if;
end if;
if decodeOPC = '1' then
rot_bits <= set_rot_bits;
writePCbig <= '0';
else
writePCbig <= set_writePCbig or writePCbig;
end if;
if decodeOPC = '1' or exec(ld_rot_cnt) = '1' or rot_cnt /= "000001" then
rot_cnt <= set_rot_cnt;
end if;
if setstate(1) = '1' and set_datatype = "00" then
byte <= '1';
end if;
if set_Suppress_Base = '1' then
Suppress_Base <= '1';
elsif setstate(1) = '1' or (ea_only = '1' and set(get_ea_now) = '1') then
Suppress_Base <= '0';
end if;
if getbrief = '1' then
if state(1) = '1' then
brief <= last_opc_read(15 downto 0);
else
brief <= data_read(15 downto 0);
end if;
end if;
if setopcode='1' and berr='0' then
if state = "00" then
opcode <= data_read(15 downto 0);
exe_pc <= tg68_pc;
else
opcode <= last_opc_read(15 downto 0);
exe_pc <= last_opc_pc;
end if;
nextpass <= '0';
elsif setinterrupt = '1' then
opcode(15 downto 12) <= X"7"; --moveq
opcode(8 downto 6) <= "001"; --word
nextpass <= '0';
else
-- if setnextpass='1' or (regdirectsource='1' and state="00") then
if setnextpass = '1' or regdirectsource = '1' then
nextpass <= '1';
end if;
end if;
if decodeOPC = '1' or interrupt = '1' then
trap_SR <= FlagsSR;
end if;
end if;
end if;
end if;
if rising_edge(clk) then
if Reset = '1' then
PCbase <= '1';
elsif clkena_lw = '1' then
PCbase <= set_PCbase or PCbase;
if setexecOPC = '1' or (state(1) = '1' and movem_run = '0') then
PCbase <= '0';
end if;
end if;
if clkena_lw = '1' then
exec <= set;
exec_tas <= '0';
exec(subidx) <= set(presub) or set(subidx);
if setexecOPC = '1' then
exec <= set_exec or set;
exec_tas <= set_exec_tas;
end if;
exec(get_2ndOPC) <= set(get_2ndOPC) or setopcode;
end if;
end if;
end process;
------------------------------------------------------------------------------
--prepare Bitfield Parameters
------------------------------------------------------------------------------
process (clk, Reset, sndOPC, reg_QA, reg_QB, bf_width, bf_offset, bf_offset_l, bf_bhits, opcode, setstate)
begin
-- the ALU needs the full real offset to return the correct result for
-- bfffo
if sndOPC(11) = '1' then
bf_offset <= reg_QA;
else
bf_offset <= (others => '0');
bf_offset(4 downto 0) <= sndOPC(10 downto 6);
end if;
-- offset within long word
bf_offset_l <= bf_offset(4 downto 0);
if sndOPC(5) = '1' then
bf_width <= reg_QB(4 downto 0) - 1;
else
bf_width <= sndOPC(4 downto 0) - 1;
end if;
bf_bhits <= ('0' & bf_width) + ('0' & bf_offset_l);
set_oddout <= not bf_bhits(3);
bf_loffset <= 31 - bf_bhits(4 downto 0);
if opcode(4 downto 3) /= "00" then
-- memory is being read with byte precision, thus offset
-- bit 2:0 are only used in the alu
bf_loffset(4 downto 3) <= "00";
bf_offset_l(4 downto 3) <= "00";
end if;
case bf_bhits(5 downto 3) is
when "000" =>
set_memmask <= "101111";
when "001" =>
set_memmask <= "100111";
when "010" =>
set_memmask <= "100011";
when "011" =>
set_memmask <= "100001";
when others =>
set_memmask <= "100000";
end case;
if setstate = "00" then
set_memmask <= "100111";
end if;
end process;
------------------------------------------------------------------------------
--SR op
------------------------------------------------------------------------------
process (clk, Reset, FlagsSR, last_data_read, OP2out, exec)
begin
if exec(andisR) = '1' then
SRin <= FlagsSR and last_data_read(15 downto 8);
elsif exec(eorisR) = '1' then
SRin <= FlagsSR Xor last_data_read(15 downto 8);
elsif exec(orisR) = '1' then
SRin <= FlagsSR or last_data_read(15 downto 8);
else
SRin <= OP2out(15 downto 8);
end if;
if rising_edge(clk) then
if Reset = '1' then
FlagsSR(5) <= '1';
FlagsSR(2 downto 0) <= "111";
FC(2) <= '1';
SVmode <= '1';
preSVmode <= '1';
make_trace <= '0';
elsif clkena_lw = '1' then
if setopcode = '1' then
make_trace <= FlagsSR(7);
if set(changeMode) = '1' then
SVmode <= not SVmode;
else
SVmode <= preSVmode;
end if;
end if;
if set(changeMode) = '1' then
preSVmode <= not preSVmode;
FlagsSR(5) <= not preSVmode;
FC(2) <= not preSVmode;
end if;
if micro_state = trap3 then
FlagsSR(7) <= '0';
end if;
if trap_trace = '1' and state = "10" then
make_trace <= '0';
end if;
if exec(directSR) = '1' or set_stop = '1' then
FlagsSR <= data_read(15 downto 8);
end if;
if interrupt = '1' and trap_interrupt = '1' then
FlagsSR(2 downto 0) <= rIPL_nr;
end if;
-- if exec(to_CCR)='1' and exec(to_SR)='1' then
if exec(to_SR) = '1' then
FlagsSR(7 downto 0) <= SRin; --SR
FC(2) <= SRin(5);
-- end if;
elsif exec(update_FC) = '1' then
FC(2) <= FlagsSR(5);
end if;
if interrupt = '1' then
FC(2) <= '1';
end if;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- decode opcode
-----------------------------------------------------------------------------
process(clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state, decodeOPC, state, setexecOPC, Flags, FlagsSR, direct_data, build_logical,
build_bcd, set_Z_error, trapd, movem_run, last_data_read, set, set_V_Flag, z_error, trap_trace, trap_interrupt,
SVmode, preSVmode, stop, long_done, ea_only, setstate, execOPC, exec_write_back, exe_datatype,
datatype, interrupt, c_out, trapmake, rot_cnt, brief, addr,
long_start, set_datatype, sndOPC, set_exec, exec, ea_build_now, reg_QA, reg_QB, make_berr, trap_berr)
begin
TG68_PC_brw <= '0';
setstate <= "00";
Regwrena_now <= '0';
movem_presub <= '0';
setnextpass <= '0';
regdirectsource <= '0';
setdisp <= '0';
setdispbyte <= '0';
getbrief <= '0';
dest_areg <= '0';
source_areg <= '0';
data_is_source <= '0';
write_back <= '0';
setstackaddr <= '0';
writePC <= '0';
ea_build_now <= '0';
set_rot_bits <= "XX";
set_rot_cnt <= "000001";
dest_hbits <= '0';
source_lowbits <= '0';
source_2ndHbits <= '0';
source_2ndLbits <= '0';
dest_2ndHbits <= '0';
ea_only <= '0';
set_direct_data <= '0';
set_exec_tas <= '0';
trap_illegal <= '0';
trap_addr_error <= '0';
trap_priv <= '0';
trap_1010 <= '0';
trap_1111 <= '0';
trap_trap <= '0';
trap_trapv <= '0';
trapmake <= '0';
set_vectoraddr <= '0';
writeSR <= '0';
set_stop <= '0';
illegal_write_mode <= '0';
illegal_read_mode <= '0';
illegal_byteaddr <= '0';
set_Z_error <= '0';
next_micro_state <= idle;
build_logical <= '0';
build_bcd <= '0';
skipFetch <= make_berr;
set_writePCbig <= '0';
-- set_recall_last <= '0';
set_Suppress_Base <= '0';
set_PCbase <= '0';
if rot_cnt /= "000001" then
set_rot_cnt <= rot_cnt - 1;
end if;
set_datatype <= datatype;
set <= (others => '0');
set_exec <= (others => '0');
set(update_ld) <= '0';
-- odd_start <= '0';
------------------------------------------------------------------------------
--Sourcepass
------------------------------------------------------------------------------
case opcode(7 downto 6) is
when "00" => datatype <= "00"; --Byte
when "01" => datatype <= "01"; --Word
when others => datatype <= "10"; --Long
end case;
if trapmake = '1' and trapd = '0' then
next_micro_state <= trap0;
if VBR_Stackframe = 0 or (cpu(0) = '0' and VBR_Stackframe = 2) then
set(writePC_add) <= '1';
-- set_datatype <= "10";
end if;
if preSVmode = '0' then
set(changeMode) <= '1';
end if;
setstate <= "01";
end if;
if interrupt='1' and trap_berr='1' THEN
next_micro_state <= trap0;
if preSVmode='0' THEN
set(changeMode) <= '1';
end if;
setstate <= "01";
end if;
if micro_state = int1 or (interrupt = '1' and trap_trace = '1') then
if trap_trace='1' AND (VBR_Stackframe=1 or (cpu(0)='1' AND VBR_Stackframe=2)) then
next_micro_state <= trap00; --TH
else
next_micro_state <= trap0;
end if;
-- if cpu(0)='0' then
-- set_datatype <= "10";
-- end if;
if preSVmode = '0' then
set(changeMode) <= '1';
end if;
setstate <= "01";
end if;
if setexecOPC = '1' and FlagsSR(5) /= preSVmode then
set(changeMode) <= '1';
-- setstate <= "01";
-- next_micro_state <= nop;
end if;
if interrupt = '1' and trap_interrupt = '1' then
-- skipFetch <= '1';
next_micro_state <= int1;
set(update_ld) <= '1';
setstate <= "10";
end if;
if set(changeMode) = '1' then
set(to_USP) <= '1';
set(from_USP) <= '1';
setstackaddr <= '1';
end if;
if ea_only = '0' and set(get_ea_now) = '1' then
setstate <= "10";
-- set_recall_last <= '1';
-- set(update_ld) <= '0';
end if;
if setstate(1) = '1' and set_datatype(1) = '1' then
set(longaktion) <= '1';
end if;
if (ea_build_now = '1' and decodeOPC = '1') or exec(ea_build) = '1' then
case opcode(5 downto 3) is --source
when "010" | "011" | "100" => -- -(An)+
set(get_ea_now) <= '1';
setnextpass <= '1';
if opcode(3) = '1' then --(An)+
set(postadd) <= '1';
if opcode(2 downto 0) = "111" then
set(use_SP) <= '1';
end if;
end if;
if opcode(5) = '1' then -- -(An)
set(presub) <= '1';
if opcode(2 downto 0) = "111" then
set(use_SP) <= '1';
end if;
end if;
when "101" => --(d16,An)
next_micro_state <= ld_dAn1;
when "110" => --(d8,An,Xn)
next_micro_state <= ld_AnXn1;
getbrief <= '1';
when "111" =>
case opcode(2 downto 0) is
when "000" => --(xxxx).w
next_micro_state <= ld_nn;
when "001" => --(xxxx).l
set(longaktion) <= '1';
next_micro_state <= ld_nn;
when "010" => --(d16,PC)
next_micro_state <= ld_dAn1;
set(dispouter) <= '1';
set_Suppress_Base <= '1';
set_PCbase <= '1';
when "011" => --(d8,PC,Xn)
next_micro_state <= ld_AnXn1;
getbrief <= '1';
set(dispouter) <= '1';
set_Suppress_Base <= '1';
set_PCbase <= '1';
when "100" => --#data
setnextpass <= '1';
set_direct_data <= '1';
if datatype = "10" then
set(longaktion) <= '1';
end if;
when others => NULL;
end case;
when others => NULL;
end case;
end if;
------------------------------------------------------------------------------
--prepere opcode
------------------------------------------------------------------------------
case opcode(15 downto 12) is
-- 0000 ----------------------------------------------------------------------------
when "0000" =>
if opcode(8) = '1' and opcode(5 downto 3) = "001" then --movep
datatype <= "00"; --Byte
set(use_SP) <= '1'; --addr+2
set(no_Flags) <= '1';
if opcode(7) = '0' then --to register
set_exec(Regwrena) <= '1';
set_exec(opcMOVE) <= '1';
set(movepl) <= '1';
end if;
if decodeOPC = '1' then
if opcode(6) = '1' then
set(movepl) <= '1';
end if;
if opcode(7) = '0' then
set_direct_data <= '1'; -- to register
end if;
next_micro_state <= movep1;
end if;
if setexecOPC = '1' then
dest_hbits <= '1';
end if;
else
if opcode(8) = '1' or opcode(11 downto 9) = "100" then --Bits
set_exec(opcBITS) <= '1';
set_exec(ea_data_OP1) <= '1';
if opcode(7 downto 6) /= "00" then
if opcode(5 downto 4) = "00" then
set_exec(Regwrena) <= '1';
end if;
write_back <= '1';
end if;
if opcode(5 downto 4) = "00" then
datatype <= "10"; --Long
else
datatype <= "00"; --Byte
end if;
if opcode(8) = '0' then
if decodeOPC = '1' then
next_micro_state <= nop;
set(get_2ndOPC) <= '1';
set(ea_build) <= '1';
end if;
else
ea_build_now <= '1';
end if;
elsif opcode(11 downto 9) = "111" then --MOVES not in 68000
trap_illegal <= '1';
-- trap_addr_error <= '1';
trapmake <= '1';
else --andi, ...xxxi
if opcode(11 downto 9) = "000" then --orI
set_exec(opcor) <= '1';
end if;
if opcode(11 downto 9) = "001" then --andI
set_exec(opcand) <= '1';
end if;
if opcode(11 downto 9) = "010" or opcode(11 downto 9) = "011" then --SUBI, ADDI
set_exec(opcADD) <= '1';
end if;
if opcode(11 downto 9) = "101" then --EorI
set_exec(opcEor) <= '1';
end if;
if opcode(11 downto 9) = "110" then --CMPI
set_exec(opcCMP) <= '1';
end if;
if opcode(7) = '0' and opcode(5 downto 0) = "111100" and (set_exec(opcand) or set_exec(opcor) or set_exec(opcEor)) = '1' then --SR
if decodeOPC = '1' and SVmode = '0' and opcode(6) = '1' then --SR
trap_priv <= '1';
trapmake <= '1';
else
set(no_Flags) <= '1';
if decodeOPC = '1' then
if opcode(6) = '1' then
set(to_SR) <= '1';
end if;
set(to_CCR) <= '1';
set(andisR) <= set_exec(opcand);
set(eorisR) <= set_exec(opcEor);
set(orisR) <= set_exec(opcor);
setstate <= "01";
next_micro_state <= nopnop;
end if;
end if;
else
if decodeOPC = '1' then
next_micro_state <= andi;
set(ea_build) <= '1';
set_direct_data <= '1';
if datatype = "10" then
set(longaktion) <= '1';
end if;
end if;
if opcode(5 downto 4) /= "00" then
set_exec(ea_data_OP1) <= '1';
end if;
if opcode(11 downto 9) /= "110" then --CMPI
if opcode(5 downto 4) = "00" then
set_exec(Regwrena) <= '1';
end if;
write_back <= '1';
end if;
if opcode(10 downto 9) = "10" then --CMPI, SUBI
set(addsub) <= '1';
end if;
end if;
end if;
end if;
-- 0001, 0010, 0011 -----------------------------------------------------------------
when "0001" | "0010" | "0011" => --move.b, move.l, move.w
set_exec(opcMOVE) <= '1';
ea_build_now <= '1';
if opcode(8 downto 6) = "001" then
set(no_Flags) <= '1';
end if;
if opcode(5 downto 4) = "00" then --Dn, An
if opcode(8 downto 7) = "00" then
set_exec(Regwrena) <= '1';
end if;
end if;
case opcode(13 downto 12) is
when "01" => datatype <= "00"; --Byte
when "10" => datatype <= "10"; --Long
when others => datatype <= "01"; --Word
end case;
source_lowbits <= '1'; -- Dn=> An=>
if opcode(3) = '1' then
source_areg <= '1';
end if;
if nextpass = '1' or opcode(5 downto 4) = "00" then
dest_hbits <= '1';
if opcode(8 downto 6) /= "000" then
dest_areg <= '1';
end if;
end if;
-- if setstate="10" then
-- set(update_ld) <= '0';
-- end if;
--
if micro_state = idle and (nextpass = '1' or (opcode(5 downto 4) = "00" and decodeOPC = '1')) then
case opcode(8 downto 6) is --destination
when "000" | "001" => --Dn,An
set_exec(Regwrena) <= '1';
when "010" | "011" | "100" => --destination -(an)+
if opcode(6) = '1' then --(An)+
set(postadd) <= '1';
if opcode(11 downto 9) = "111" then
set(use_SP) <= '1';
end if;
end if;
if opcode(8) = '1' then -- -(An)
set(presub) <= '1';
if opcode(11 downto 9) = "111" then
set(use_SP) <= '1';
end if;
end if;
setstate <= "11";
next_micro_state <= nop;
if nextpass = '0' then
set(write_reg) <= '1';
end if;
when "101" => --(d16,An)
next_micro_state <= st_dAn1;
-- getbrief <= '1';
when "110" => --(d8,An,Xn)
next_micro_state <= st_AnXn1;
getbrief <= '1';
when "111" =>
case opcode(11 downto 9) is
when "000" => --(xxxx).w
next_micro_state <= st_nn;
when "001" => --(xxxx).l
set(longaktion) <= '1';
next_micro_state <= st_nn;
when others => NULL;
end case;
when others => NULL;
end case;
end if;
---- 0100 ----------------------------------------------------------------------------
when "0100" => --rts_group
if opcode(8) = '1' then --lea
if opcode(6) = '1' then --lea
if opcode(7) = '1' then
source_lowbits <= '1';
-- if opcode(5 downto 3)="000" and opcode(10)='0' then --ext
if opcode(5 downto 4) = "00" then --extb.l
set_exec(opcEXT) <= '1';
set_exec(opcMOVE) <= '1';
set_exec(Regwrena) <= '1';
-- if opcode(6)='0' then
-- datatype <= "01"; --WorD
-- end if;
else
source_areg <= '1';
ea_only <= '1';
set_exec(Regwrena) <= '1';
set_exec(opcMOVE) <= '1';
set(no_Flags) <= '1';
if opcode(5 downto 3) = "010" then --lea (Am),An
dest_areg <= '1';
dest_hbits <= '1';
else
ea_build_now <= '1';
end if;
if set(get_ea_now) = '1' then
setstate <= "01";
set_direct_data <= '1';
end if;
if setexecOPC = '1' then
dest_areg <= '1';
dest_hbits <= '1';
end if;
end if;
else
trap_illegal <= '1';
trapmake <= '1';
end if;
else --chk
IF opcode(7)='1' AND opcode(5 downto 0) /= "111111" THEN
datatype <= "01"; --Word
set(trap_chk) <= '1';
if (c_out(1) = '0' or OP1out(15) = '1' or OP2out(15) = '1') and exec(opcCHK) = '1' then
trapmake <= '1';
end if;
elsif cpu(1) = '1' then --chk long for 68020
datatype <= "10"; --Long
set(trap_chk) <= '1';
if (c_out(2) = '1' or OP1out(31) = '1' or OP2out(31) = '1') and exec(opcCHK) = '1' then
trapmake <= '1';
end if;
else
trap_illegal <= '1'; -- chk long for 68020
trapmake <= '1';
end if;
if opcode(7) = '1' or cpu(1) = '1' then
if (nextpass = '1' or opcode(5 downto 4) = "00") and exec(opcCHK) = '0' and micro_state = idle then
set_exec(opcCHK) <= '1';
end if;
ea_build_now <= '1';
set(addsub) <= '1';
if setexecOPC = '1' then
dest_hbits <= '1';
source_lowbits <= '1';
end if;
end if;
end if;
else
case opcode(11 downto 9) is
when "000" =>
if opcode(7 downto 6) = "11" then --move from SR
if SR_Read = 0 or (cpu(0) = '0' and SR_Read = 2) or SVmode = '1' then
-- if SVmode='1' then
ea_build_now <= '1';
set_exec(opcMOVESR) <= '1';
datatype <= "01";
write_back <= '1'; -- 68000 also reads first
if cpu(0) = '1' and state = "10" then
skipFetch <= '1';
end if;
if opcode(5 downto 4) = "00" then
set_exec(Regwrena) <= '1';
end if;
else
trap_priv <= '1';
trapmake <= '1';
end if;
else --negx
ea_build_now <= '1';
set_exec(use_XZFlag) <= '1';
write_back <= '1';
set_exec(opcADD) <= '1';
set(addsub) <= '1';
source_lowbits <= '1';
if opcode(5 downto 4) = "00" then
set_exec(Regwrena) <= '1';
end if;
if setexecOPC = '1' then
set(OP1out_zero) <= '1';
end if;
end if;
when "001" =>
if opcode(7 downto 6) = "11" then --move from CCR 68010
if SR_Read = 1 or (cpu(0) = '1' and SR_Read = 2) then
ea_build_now <= '1';
set_exec(opcMOVECCR) <= '1';
--datatype <= "00"; -- WRONG, should be WORD zero extended.
datatype <= "01"; -- WRONG, should be WORD zero extended.
write_back <= '1'; -- 68000 also reads first
if opcode(5 downto 4) = "00" then
set_exec(Regwrena) <= '1';
end if;
else
trap_illegal <= '1';
trapmake <= '1';
end if;
else --clr
ea_build_now <= '1';
write_back <= '1';
set_exec(opcand) <= '1';
if cpu(0) = '1' and state = "10" then
skipFetch <= '1';
end if;
if setexecOPC = '1' then
set(OP1out_zero) <= '1';
end if;
if opcode(5 downto 4) = "00" then
set_exec(Regwrena) <= '1';
end if;
end if;
when "010" =>
ea_build_now <= '1';
if opcode(7 downto 6) = "11" then --move to CCR
datatype <= "01";
source_lowbits <= '1';
if (decodeOPC = '1' and opcode(5 downto 4) = "00") or state = "10" or direct_data = '1' then
set(to_CCR) <= '1';
end if;
else --neg
write_back <= '1';
set_exec(opcADD) <= '1';
set(addsub) <= '1';
source_lowbits <= '1';
if opcode(5 downto 4) = "00" then
set_exec(Regwrena) <= '1';
end if;
if setexecOPC = '1' then
set(OP1out_zero) <= '1';
end if;
end if;
when "011" => --not, move toSR
if opcode(7 downto 6) = "11" then --move to SR
if SVmode = '1' then
ea_build_now <= '1';
datatype <= "01";
source_lowbits <= '1';
if (decodeOPC = '1' and opcode(5 downto 4) = "00") or state = "10" or direct_data = '1' then
set(to_SR) <= '1';
set(to_CCR) <= '1';
end if;
if exec(to_SR) = '1' or (decodeOPC = '1' and opcode(5 downto 4) = "00") or state = "10" or direct_data = '1' then
setstate <= "01";
end if;
else
trap_priv <= '1';
trapmake <= '1';
end if;
else --not
ea_build_now <= '1';
write_back <= '1';
set_exec(opcEor) <= '1';
set_exec(ea_data_OP1) <= '1';
if opcode(5 downto 3) = "000" then
set_exec(Regwrena) <= '1';
end if;
if setexecOPC = '1' then
set(OP2out_one) <= '1';
end if;
end if;
when "100" | "110" =>
if opcode(7) = '1' then --movem, ext
if opcode(5 downto 3) = "000" and opcode(10) = '0' then --ext
source_lowbits <= '1';
set_exec(opcEXT) <= '1';
set_exec(opcMOVE) <= '1';
set_exec(Regwrena) <= '1';
if opcode(6) = '0' then
datatype <= "01"; --WorD
end if;
else --movem
-- if opcode(11 downto 7)="10001" or opcode(11 downto 7)="11001" then --MOVEM
ea_only <= '1';
set(no_Flags) <= '1';
if opcode(6) = '0' then
datatype <= "01"; --Word transfer
end if;
if (opcode(5 downto 3) = "100" or opcode(5 downto 3) = "011") and state = "01" then -- -(An), (An)+
set_exec(save_memaddr) <= '1';
set_exec(Regwrena) <= '1';
end if;
if opcode(5 downto 3) = "100" then -- -(An)
movem_presub <= '1';
set(subidx) <= '1';
end if;
if state = "10" then
set(Regwrena) <= '1';
set(opcMOVE) <= '1';
end if;
if decodeOPC = '1' then
set(get_2ndOPC) <= '1';
if opcode(5 downto 3) = "010" or opcode(5 downto 3) = "011" or opcode(5 downto 3) = "100" then
next_micro_state <= movem1;
else
next_micro_state <= nop;
set(ea_build) <= '1';
end if;
end if;
if set(get_ea_now) = '1' then
if movem_run = '1' then
set(movem_action) <= '1';
if opcode(10) = '0' then
setstate <= "11";
set(write_reg) <= '1';
else
setstate <= "10";
end if;
next_micro_state <= movem2;
set(mem_addsub) <= '1';
else
setstate <= "01";
end if;
end if;
end if;
else
if opcode(10) = '1' then --MUL.L, DIV.L 68020
-- if cpu(1)='1' then
if (opcode(6) = '1' and (DIV_Mode = 1 or (cpu(1) = '1' and DIV_Mode = 2))) or
(opcode(6) = '0' and (MUL_Mode = 1 or (cpu(1) = '1' and MUL_Mode = 2))) then
if decodeOPC = '1' then
next_micro_state <= nop;
set(get_2ndOPC) <= '1';
set(ea_build) <= '1';
end if;
if (micro_state = idle and nextpass = '1') or (opcode(5 downto 4) = "00" and exec(ea_build) = '1') then
setstate <= "01";
dest_2ndHbits <= '1';
source_2ndLbits <= '1';
if opcode(6) = '1' then
next_micro_state <= div1;
else
next_micro_state <= mul1;
set(ld_rot_cnt) <= '1';
end if;
end if;
if z_error = '0' and set_V_Flag = '0' and set(opcDIVU) = '1' then
set(Regwrena) <= '1';
end if;
source_lowbits <= '1';
if nextpass = '1' or (opcode(5 downto 4) = "00" and decodeOPC = '1') then
dest_hbits <= '1';
end if;
datatype <= "10";
else
trap_illegal <= '1';
trapmake <= '1';
end if;
else --pea, swap
if opcode(6) = '1' then
datatype <= "10";
if opcode(5 downto 3) = "000" then --swap
set_exec(opcSWAP) <= '1';
set_exec(Regwrena) <= '1';
elsif opcode(5 downto 3) = "001" then --bkpt
else --pea
ea_only <= '1';
ea_build_now <= '1';
if nextpass = '1' and micro_state = idle then
set(presub) <= '1';
setstackaddr <= '1';
setstate <= "11";
next_micro_state <= nop;
end if;
if set(get_ea_now) = '1' then
setstate <= "01";
end if;
end if;
else
if opcode(5 downto 3) = "001" then --link.l
datatype <= "10";
set_exec(opcADD) <= '1'; --for displacement
set_exec(Regwrena) <= '1';
set(no_Flags) <= '1';
if decodeOPC = '1' then
set(linksp) <= '1';
set(longaktion) <= '1';
next_micro_state <= link1;
set(presub) <= '1';
setstackaddr <= '1';
set(mem_addsub) <= '1';
source_lowbits <= '1';
source_areg <= '1';
set(store_ea_data) <= '1';
end if;
else --nbcd
ea_build_now <= '1';
set_exec(use_XZFlag) <= '1';
write_back <= '1';
set_exec(opcADD) <= '1';
set_exec(opcSBCD) <= '1';
source_lowbits <= '1';
if opcode(5 downto 4) = "00" then
set_exec(Regwrena) <= '1';
end if;
if setexecOPC = '1' then
set(OP1out_zero) <= '1';
end if;
end if;
end if;
end if;
end if;
--
when "101" => --tst, tas 4aFC - illegal
if opcode(7 downto 2) = "111111" then --illegal
trap_illegal <= '1';
trapmake <= '1';
else
ea_build_now <= '1';
if setexecOPC = '1' then
source_lowbits <= '1';
if opcode(3) = '1' then --MC68020...
source_areg <= '1';
end if;
end if;
set_exec(opcMOVE) <= '1';
if opcode(7 downto 6) = "11" then --tas
set_exec_tas <= '1';
write_back <= '1';
datatype <= "00"; --Byte
if opcode(5 downto 4) = "00" then
set_exec(Regwrena) <= '1';
end if;
end if;
end if;
---- when "110"=>
when "111" => --4EXX
--
-- ea_only <= '1';
-- ea_build_now <= '1';
-- if nextpass='1' and micro_state=idle then
-- set(presub) <= '1';
-- setstackaddr <='1';
-- set(mem_addsub) <= '1';
-- setstate <="11";
-- next_micro_state <= nop;
-- end if;
-- if set(get_ea_now)='1' then
-- setstate <="01";
-- end if;
--
if opcode(7) = '1' then --jsr, jmp
datatype <= "10";
ea_only <= '1';
ea_build_now <= '1';
if exec(ea_to_pc) = '1' then
next_micro_state <= nop;
end if;
if nextpass = '1' and micro_state = idle and opcode(6) = '0' then
set(presub) <= '1';
setstackaddr <= '1';
setstate <= "11";
next_micro_state <= nopnop;
end if;
-- achtung buggefahr
if micro_state = ld_AnXn1 and brief(8) = '0' then --JMP/JSR n(Ax,Dn)
skipFetch <= '1';
end if;
if state = "00" then
writePC <= '1';
end if;
set(hold_dwr) <= '1';
if set(get_ea_now) = '1' then --jsr
if exec(longaktion) = '0' or long_done = '1' then
skipFetch <= '1';
end if;
setstate <= "01";
set(ea_to_pc) <= '1';
end if;
else --
case opcode(6 downto 0) is
when "1000000" | "1000001" | "1000010" | "1000011" | "1000100" | "1000101" | "1000110" | "1000111" | --trap
"1001000" | "1001001" | "1001010" | "1001011" | "1001100" | "1001101" | "1001110" | "1001111" => --trap
trap_trap <= '1';
trapmake <= '1';
when "1010000" | "1010001" | "1010010" | "1010011" | "1010100" | "1010101" | "1010110" | "1010111" => --link
datatype <= "10";
set_exec(opcADD) <= '1'; --for displacement
set_exec(Regwrena) <= '1';
set(no_Flags) <= '1';
if decodeOPC = '1' then
next_micro_state <= link1;
set(presub) <= '1';
setstackaddr <= '1';
set(mem_addsub) <= '1';
source_lowbits <= '1';
source_areg <= '1';
set(store_ea_data) <= '1';
end if;
when "1011000" | "1011001" | "1011010" | "1011011" | "1011100" | "1011101" | "1011110" | "1011111" => --unlink
datatype <= "10";
set_exec(Regwrena) <= '1';
set_exec(opcMOVE) <= '1';
set(no_Flags) <= '1';
if decodeOPC = '1' then
setstate <= "01";
next_micro_state <= unlink1;
set(opcMOVE) <= '1';
set(Regwrena) <= '1';
setstackaddr <= '1';
source_lowbits <= '1';
source_areg <= '1';
end if;
when "1100000" | "1100001" | "1100010" | "1100011" | "1100100" | "1100101" | "1100110" | "1100111" => --move An,USP
if SVmode = '1' then
-- set(no_Flags) <= '1';
set(to_USP) <= '1';
source_lowbits <= '1';
source_areg <= '1';
datatype <= "10";
else
trap_priv <= '1';
trapmake <= '1';
end if;
when "1101000" | "1101001" | "1101010" | "1101011" | "1101100" | "1101101" | "1101110" | "1101111" => --move USP,An
if SVmode = '1' then
-- set(no_Flags) <= '1';
set(from_USP) <= '1';
datatype <= "10";
set_exec(Regwrena) <= '1';
else
trap_priv <= '1';
trapmake <= '1';
end if;
when "1110000" => --reset
if SVmode = '0' then
trap_priv <= '1';
trapmake <= '1';
else
set(opcRESET) <= '1';
if decodeOPC = '1' then
set(ld_rot_cnt) <= '1';
set_rot_cnt <= "000000";
end if;
end if;
when "1110001" => --nop
when "1110010" => --stop
if SVmode = '0' then
trap_priv <= '1';
trapmake <= '1';
else
if decodeOPC = '1' then
setnextpass <= '1';
set_stop <= '1';
end if;
if stop = '1' then
skipFetch <= '1';
end if;
end if;
when "1110011" | "1110111" => --rte/rtr
if SVmode = '1' or opcode(2) = '1' then
if decodeOPC = '1' then
setstate <= "10";
set(postadd) <= '1';
setstackaddr <= '1';
if opcode(2) = '1' then
set(directCCR) <= '1';
else
set(directSR) <= '1';
end if;
next_micro_state <= rte1;
end if;
else
trap_priv <= '1';
trapmake <= '1';
end if;
when "1110101" => --rts
datatype <= "10";
if decodeOPC = '1' then
setstate <= "10";
set(postadd) <= '1';
setstackaddr <= '1';
set(direct_delta) <= '1';
set(directPC) <= '1';
next_micro_state <= nopnop;
end if;
when "1110110" => --trapv
if decodeOPC = '1' then
setstate <= "01";
end if;
if Flags(1) = '1' and state = "01" then
trap_trapv <= '1';
trapmake <= '1';
end if;
when "1111010" | "1111011" => --movec
if VBR_Stackframe = 0 or (cpu(0) = '0' and VBR_Stackframe = 2) then
trap_illegal <= '1';
trapmake <= '1';
elsif SVmode = '0' then
trap_priv <= '1';
trapmake <= '1';
else
datatype <= "10"; --Long
if last_data_read(11 downto 0) = X"800" then
set(from_USP) <= '1';
if opcode(0) = '1' then
set(to_USP) <= '1';
end if;
end if;
if opcode(0) = '0' then
set_exec(movec_rd) <= '1';
else
set_exec(movec_wr) <= '1';
end if;
if decodeOPC = '1' then
next_micro_state <= movec1;
getbrief <= '1';
end if;
end if;
when others =>
trap_illegal <= '1';
trapmake <= '1';
end case;
end if;
when others => NULL;
end case;
end if;
--
---- 0101 ----------------------------------------------------------------------------
when "0101" => --subq, addq
if opcode(7 downto 6) = "11" then --dbcc
if opcode(5 downto 3) = "001" then --dbcc
if decodeOPC = '1' then
next_micro_state <= dbcc1;
set(OP2out_one) <= '1';
data_is_source <= '1';
end if;
else --Scc
datatype <= "00"; --Byte
ea_build_now <= '1';
write_back <= '1';
set_exec(opcScc) <= '1';
if cpu(0) = '1' and state = "10" then
skipFetch <= '1';
end if;
if opcode(5 downto 4) = "00" then
set_exec(Regwrena) <= '1';
end if;
end if;
else --addq, subq
ea_build_now <= '1';
if opcode(5 downto 3) = "001" then
set(no_Flags) <= '1';
end if;
if opcode(8) = '1' then
set(addsub) <= '1';
end if;
write_back <= '1';
set_exec(opcADDQ) <= '1';
set_exec(opcADD) <= '1';
set_exec(ea_data_OP1) <= '1';
if opcode(5 downto 4) = "00" then
set_exec(Regwrena) <= '1';
end if;
end if;
--
---- 0110 ----------------------------------------------------------------------------
when "0110" => --bra,bsr,bcc
datatype <= "10";
if micro_state = idle then
if opcode(11 downto 8) = "0001" then --bsr
set(presub) <= '1';
setstackaddr <= '1';
if opcode(7 downto 0) = "11111111" then
next_micro_state <= bsr2;
set(longaktion) <= '1';
elsif opcode(7 downto 0) = "00000000" then
next_micro_state <= bsr2;
else
next_micro_state <= bsr1;
setstate <= "11";
writePC <= '1';
end if;
else --bra
if opcode(7 downto 0) = "11111111" then
next_micro_state <= bra1;
set(longaktion) <= '1';
elsif opcode(7 downto 0) = "00000000" then
next_micro_state <= bra1;
else
setstate <= "01";
next_micro_state <= bra1;
end if;
end if;
end if;
-- 0111 ----------------------------------------------------------------------------
when "0111" => --moveq
-- if opcode(8)='0' then -- Cloanto's Amiga Forver ROMs have mangled movq instructions with a 1 here...
if trap_interrupt = '0' and trap_trace = '0' then
datatype <= "10"; --Long
set_exec(Regwrena) <= '1';
set_exec(opcMOVEQ) <= '1';
set_exec(opcMOVE) <= '1';
dest_hbits <= '1';
end if;
-- else
-- trap_illegal <= '1';
-- trapmake <= '1';
-- end if;
---- 1000 ----------------------------------------------------------------------------
when "1000" => --or
if opcode(7 downto 6) = "11" then --divu, divs
if DIV_Mode /= 3 then
if opcode(5 downto 4) = "00" then --Dn, An
regdirectsource <= '1';
end if;
if (micro_state = idle and nextpass = '1') or (opcode(5 downto 4) = "00" and decodeOPC = '1') then
setstate <= "01";
next_micro_state <= div1;
end if;
ea_build_now <= '1';
if z_error = '0' and set_V_Flag = '0' then
set_exec(Regwrena) <= '1';
end if;
source_lowbits <= '1';
if nextpass = '1' or (opcode(5 downto 4) = "00" and decodeOPC = '1') then
dest_hbits <= '1';
end if;
datatype <= "01";
else
trap_illegal <= '1';
trapmake <= '1';
end if;
elsif opcode(8) = '1' and opcode(5 downto 4) = "00" then --sbcd, pack , unpack
if opcode(7 downto 6) = "00" then --sbcd
build_bcd <= '1';
set_exec(opcADD) <= '1';
set_exec(opcSBCD) <= '1';
elsif cpu(1) = '1' and (opcode(7 downto 6) = "01" or opcode(7 downto 6) = "10") then --pack, unpack
datatype <= "01"; --Word
set_exec(opcPACK) <= '1';
set(no_Flags) <= '1'; -- this command modifies no flags
-- immediate value is kept in op1
-- source value is in op2
if opcode(3) = '0' then -- R/M bit = 0 -> Dy->Dy, 1 -(Ax),-(Ay)
dest_hbits <= '1'; -- dest register is encoded in bits 9-11
source_lowbits <= '1'; -- source register is encoded in bits 0-2
set_exec(Regwrena) <= '1'; -- write result into register
set_exec(ea_data_OP1) <= '1'; -- immediate value goes into op2
set(hold_dwr) <= '1';
-- pack writes a byte only
if opcode(7 downto 6) = "01" then
datatype <= "00"; --Byte
else
datatype <= "01"; --Word
end if;
if decodeOPC = '1' then
next_micro_state <= nop;
set_direct_data <= '1';
end if;
else
set_exec(ea_data_OP1) <= '1';
source_lowbits <= '1'; -- source register is encoded in bits 0-2
if decodeOPC = '1' then
-- first step: read source value
if opcode(7 downto 6) = "10" then -- UNPK reads a byte
datatype <= "00"; -- Byte
end if;
set_direct_data <= '1';
setstate <= "10";
set(update_ld) <= '1';
set(presub) <= '1';
next_micro_state <= pack1;
dest_areg <= '1'; --???
end if;
end if;
else
trap_illegal <= '1';
trapmake <= '1';
end if;
else --or
set_exec(opcor) <= '1';
build_logical <= '1';
end if;
---- 1001, 1101 -----------------------------------------------------------------------
when "1001" | "1101" => --sub, add
set_exec(opcADD) <= '1';
ea_build_now <= '1';
if opcode(14) = '0' then
set(addsub) <= '1';
end if;
if opcode(7 downto 6) = "11" then -- --adda, suba
if opcode(8) = '0' then --adda.w, suba.w
datatype <= "01"; --Word
end if;
set_exec(Regwrena) <= '1';
source_lowbits <= '1';
if opcode(3) = '1' then
source_areg <= '1';
end if;
set(no_Flags) <= '1';
if setexecOPC = '1' then
dest_areg <= '1';
dest_hbits <= '1';
end if;
else
if opcode(8) = '1' and opcode(5 downto 4) = "00" then --addx, subx
build_bcd <= '1';
else --sub, add
build_logical <= '1';
end if;
end if;
--
---- 1010 ----------------------------------------------------------------------------
when "1010" => --Trap 1010
trap_1010 <= '1';
trapmake <= '1';
---- 1011 ----------------------------------------------------------------------------
when "1011" => --eor, cmp
ea_build_now <= '1';
if opcode(7 downto 6) = "11" then --CMPA
if opcode(8) = '0' then --cmpa.w
datatype <= "01"; --Word
set_exec(opcCPMAW) <= '1';
end if;
set_exec(opcCMP) <= '1';
if setexecOPC = '1' then
source_lowbits <= '1';
if opcode(3) = '1' then
source_areg <= '1';
end if;
dest_areg <= '1';
dest_hbits <= '1';
end if;
set(addsub) <= '1';
else
if opcode(8) = '1' then
if opcode(5 downto 3) = "001" then --cmpm
set_exec(opcCMP) <= '1';
if decodeOPC = '1' then
setstate <= "10";
set(update_ld) <= '1';
set(postadd) <= '1';
next_micro_state <= cmpm;
end if;
set_exec(ea_data_OP1) <= '1';
set(addsub) <= '1';
else --Eor
build_logical <= '1';
set_exec(opcEor) <= '1';
end if;
else --CMP
build_logical <= '1';
set_exec(opcCMP) <= '1';
set(addsub) <= '1';
end if;
end if;
--
---- 1100 ----------------------------------------------------------------------------
when "1100" => --and, exg
if opcode(7 downto 6) = "11" then --mulu, muls
if MUL_Mode /= 3 then
if opcode(5 downto 4) = "00" then --Dn, An
regdirectsource <= '1';
end if;
if (micro_state = idle and nextpass = '1') or (opcode(5 downto 4) = "00" and decodeOPC = '1') then
setstate <= "01";
set(ld_rot_cnt) <= '1';
next_micro_state <= mul1;
end if;
ea_build_now <= '1';
set_exec(Regwrena) <= '1';
source_lowbits <= '1';
if (nextpass = '1') or (opcode(5 downto 4) = "00" and decodeOPC = '1') then
dest_hbits <= '1';
end if;
datatype <= "01";
else
trap_illegal <= '1';
trapmake <= '1';
end if;
elsif opcode(8) = '1' and opcode(5 downto 4) = "00" then --exg, abcd
if opcode(7 downto 6) = "00" then --abcd
build_bcd <= '1';
set_exec(opcADD) <= '1';
set_exec(opcABCD) <= '1';
else --exg
datatype <= "10";
set(Regwrena) <= '1';
set(exg) <= '1';
if opcode(6) = '1' and opcode(3) = '1' then
dest_areg <= '1';
source_areg <= '1';
end if;
if decodeOPC = '1' then
setstate <= "01";
else
dest_hbits <= '1';
end if;
end if;
else --and
set_exec(opcand) <= '1';
build_logical <= '1';
end if;
--
---- 1110 ----------------------------------------------------------------------------
when "1110" => --rotation / bitfield
if opcode(7 downto 6) = "11" then
if opcode(11) = '0' then
set_exec(opcROT) <= '1';
ea_build_now <= '1';
datatype <= "01";
set_rot_bits <= opcode(10 downto 9);
set_exec(ea_data_OP1) <= '1';
write_back <= '1';
else --bitfield
if BitField = 0 or (cpu(1) = '0' and BitField = 2) then
trap_illegal <= '1';
trapmake <= '1';
else
if decodeOPC = '1' then
next_micro_state <= nop;
set(get_2ndOPC) <= '1';
set(ea_build) <= '1';
end if;
set_exec(opcBF) <= '1';
-- BFCLR, BFSET, BFINS, BFCHG, BFFFO, BFTST
if opcode(10) = '1' or opcode(8) = '0' then
set_exec(opcBFwb) <= '1';
-- BFFFO operating on memory
if opcode(10 downto 8) = "101" and opcode(4 downto 3) /= "00" then
set_exec(ea_data_OP2) <= '1';
end if;
set_exec(ea_data_OP1) <= '1';
end if;
-- BFCHG, BFCLR, BFSET, BFINS
if opcode(10 downto 8) = "010" or opcode(10 downto 8) = "100" or
opcode(10 downto 8) = "110" or opcode(10 downto 8) = "111" then
write_back <= '1';
end if;
ea_only <= '1';
-- BFEXTU, BFEXTS, BFFFO
if opcode(10 downto 8) = "001" or opcode(10 downto 8) = "011" or
opcode(10 downto 8) = "101" then
set_exec(Regwrena) <= '1';
end if;
-- register destination
if opcode(4 downto 3) = "00" then
-- bftst doesn't write
if opcode(10 downto 8) /= "000" then
set_exec(Regwrena) <= '1';
end if;
if exec(ea_build) = '1' then
dest_2ndHbits <= '1';
source_2ndLbits <= '1';
set(get_bfoffset) <= '1';
setstate <= "01";
end if;
end if;
if set(get_ea_now) = '1' then
setstate <= "01";
end if;
if exec(get_ea_now) = '1' then
dest_2ndHbits <= '1';
source_2ndLbits <= '1';
set(get_bfoffset) <= '1';
setstate <= "01";
set(mem_addsub) <= '1';
next_micro_state <= bf1;
end if;
if setexecOPC = '1' then
if opcode(10 downto 8) = "111" then --BFINS
source_2ndHbits <= '1';
elsif opcode(10 downto 8)="001" or opcode(10 downto 8)="011" or
opcode(10 downto 8)="101" THEN
--BFEXTU, BFEXTS, BFFFO
source_lowbits <= '1';
dest_2ndHbits <= '1';
end if;
end if;
end if;
end if;
else
set_exec(opcROT) <= '1';
set_rot_bits <= opcode(4 downto 3);
data_is_source <= '1';
set_exec(Regwrena) <= '1';
if decodeOPC = '1' then
if opcode(5) = '1' then
next_micro_state <= rota1;
set(ld_rot_cnt) <= '1';
setstate <= "01";
else
set_rot_cnt(2 downto 0) <= opcode(11 downto 9);
if opcode(11 downto 9) = "000" then
set_rot_cnt(3) <= '1';
else
set_rot_cnt(3) <= '0';
end if;
end if;
end if;
end if;
--
---- ----------------------------------------------------------------------------
when others =>
trap_1111 <= '1';
trapmake <= '1';
end case;
-- use for and, or, Eor, CMP
if build_logical = '1' then
ea_build_now <= '1';
if set_exec(opcCMP) = '0' and (opcode(8) = '0' or opcode(5 downto 4) = "00" ) then
set_exec(Regwrena) <= '1';
end if;
if opcode(8) = '1' then
write_back <= '1';
set_exec(ea_data_OP1) <= '1';
else
source_lowbits <= '1';
if opcode(3) = '1' then --use for cmp
source_areg <= '1';
end if;
if setexecOPC = '1' then
dest_hbits <= '1';
end if;
end if;
end if;
-- use for ABCD, SBCD
if build_bcd = '1' then
set_exec(use_XZFlag) <= '1';
set_exec(ea_data_OP1) <= '1';
write_back <= '1';
source_lowbits <= '1';
if opcode(3) = '1' then
if decodeOPC = '1' then
setstate <= "10";
set(update_ld) <= '1';
set(presub) <= '1';
next_micro_state <= op_AxAy;
dest_areg <= '1'; --???
end if;
else
dest_hbits <= '1';
set_exec(Regwrena) <= '1';
end if;
end if;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
if set_Z_error = '1' then -- divu by zero
trapmake <= '1'; --wichtig for USP
if trapd = '0' then
writePC <= '1';
end if;
end if;
-----------------------------------------------------------------------------
-- execute microcode
-----------------------------------------------------------------------------
if rising_edge(clk) THEN
if Reset='1' THEN
micro_state <= ld_nn;
elsif clkena_lw='1' THEN
trapd <= trapmake;
micro_state <= next_micro_state;
end if;
end if;
case micro_state is
when ld_nn => -- (nnnn).w/l=>
set(get_ea_now) <= '1';
setnextpass <= '1';
set(addrlong) <= '1';
when st_nn => -- =>(nnnn).w/l
setstate <= "11";
set(addrlong) <= '1';
next_micro_state <= nop;
when ld_dAn1 => -- d(An)=>, --d(PC)=>
set(get_ea_now) <= '1';
setdisp <= '1'; --word
setnextpass <= '1';
when ld_AnXn1 => -- d(An,Xn)=>, --d(PC,Xn)=>
if brief(8) = '0' or extAddr_Mode = 0 or (cpu(1) = '0' and extAddr_Mode = 2) then
-- mikej brief extension word only
setdisp <= '1'; --byte
setdispbyte <= '1';
setstate <= "01";
set(briefext) <= '1';
next_micro_state <= ld_AnXn2;
else
if brief(7) = '1' then --suppress Base
set_suppress_base <= '1';
elsif exec(dispouter) = '1' then
set(dispouter) <= '1';
end if;
if brief(5) = '0' then --NULL Base Displacement
setstate <= "01";
else --WorD Base Displacement
if brief(4) = '1' then
set(longaktion) <= '1'; --LONG Base Displacement
end if;
end if;
next_micro_state <= ld_229_1;
end if;
when ld_AnXn2 =>
set(get_ea_now) <= '1';
setdisp <= '1'; --brief
setnextpass <= '1';
-------------------------------------------------------------------------------------
when ld_229_1 => -- (bd,An,Xn)=>, --(bd,PC,Xn)=>
if brief(5) = '1' then --Base Displacement
setdisp <= '1'; --add last_data_read
end if;
if brief(6) = '0' and brief(2) = '0' then --Preindex or Index
set(briefext) <= '1';
setstate <= "01";
if brief(1 downto 0) = "00" then
next_micro_state <= ld_AnXn2;
else
next_micro_state <= ld_229_2;
end if;
else
if brief(1 downto 0) = "00" then
set(get_ea_now) <= '1';
setnextpass <= '1';
else
setstate <= "10";
set(longaktion) <= '1';
next_micro_state <= ld_229_3;
end if;
end if;
when ld_229_2 => -- (bd,An,Xn)=>, --(bd,PC,Xn)=>
setdisp <= '1'; -- add Index
setstate <= "10";
set(longaktion) <= '1';
next_micro_state <= ld_229_3;
when ld_229_3 => -- (bd,An,Xn)=>, --(bd,PC,Xn)=>
set_suppress_base <= '1';
set(dispouter) <= '1';
if brief(1) = '0' then --NULL Outer Displacement
setstate <= "01";
else --WORD Outer Displacement
if brief(0) = '1' then
set(longaktion) <= '1'; --LONG Outer Displacement
end if;
end if;
next_micro_state <= ld_229_4;
when ld_229_4 => -- (bd,An,Xn)=>, --(bd,PC,Xn)=>
if brief(1) = '1' then -- Outer Displacement
setdisp <= '1'; --add last_data_read
end if;
if brief(6) = '0' and brief(2) = '1' then --Postindex
set(briefext) <= '1';
setstate <= "01";
next_micro_state <= ld_AnXn2;
else
set(get_ea_now) <= '1';
setnextpass <= '1';
end if;
----------------------------------------------------------------------------------------
when st_dAn1 => -- =>d(An)
setstate <= "11";
setdisp <= '1'; --word
next_micro_state <= nop;
when st_AnXn1 => -- =>d(An,Xn)
if brief(8) = '0' or extAddr_Mode = 0 or (cpu(1) = '0' and extAddr_Mode = 2) then
setdisp <= '1'; --byte
setdispbyte <= '1';
setstate <= "01";
set(briefext) <= '1';
next_micro_state <= st_AnXn2;
else
if brief(7) = '1' then --suppress Base
set_suppress_base <= '1';
-- elsif exec(dispouter)='1' then
-- set(dispouter) <= '1';
end if;
if brief(5) = '0' then --NULL Base Displacement
setstate <= "01";
else --WorD Base Displacement
if brief(4) = '1' then
set(longaktion) <= '1'; --LONG Base Displacement
end if;
end if;
next_micro_state <= st_229_1;
end if;
when st_AnXn2 =>
setstate <= "11";
setdisp <= '1'; --brief
next_micro_state <= nop;
-------------------------------------------------------------------------------------
when st_229_1 => -- (bd,An,Xn)=>, --(bd,PC,Xn)=>
if brief(5) = '1' then --Base Displacement
setdisp <= '1'; --add last_data_read
end if;
if brief(6) = '0' and brief(2) = '0' then --Preindex or Index
set(briefext) <= '1';
setstate <= "01";
if brief(1 downto 0) = "00" then
next_micro_state <= st_AnXn2;
else
next_micro_state <= st_229_2;
end if;
else
if brief(1 downto 0) = "00" then
setstate <= "11";
next_micro_state <= nop;
else
set(hold_dwr) <= '1';
setstate <= "10";
set(longaktion) <= '1';
next_micro_state <= st_229_3;
end if;
end if;
when st_229_2 => -- (bd,An,Xn)=>, --(bd,PC,Xn)=>
setdisp <= '1'; -- add Index
set(hold_dwr) <= '1';
setstate <= "10";
set(longaktion) <= '1';
next_micro_state <= st_229_3;
when st_229_3 => -- (bd,An,Xn)=>, --(bd,PC,Xn)=>
set(hold_dwr) <= '1';
set_suppress_base <= '1';
set(dispouter) <= '1';
if brief(1) = '0' then --NULL Outer Displacement
setstate <= "01";
else --WorD Outer Displacement
if brief(0) = '1' then
set(longaktion) <= '1'; --LONG Outer Displacement
end if;
end if;
next_micro_state <= st_229_4;
when st_229_4 => -- (bd,An,Xn)=>, --(bd,PC,Xn)=>
set(hold_dwr) <= '1';
if brief(1) = '1' then -- Outer Displacement
setdisp <= '1'; --add last_data_read
end if;
if brief(6) = '0' and brief(2) = '1' then --Postindex
set(briefext) <= '1';
setstate <= "01";
next_micro_state <= st_AnXn2;
else
setstate <= "11";
next_micro_state <= nop;
end if;
----------------------------------------------------------------------------------------
when bra1 => --bra
if exe_condition = '1' then
TG68_PC_brw <= '1'; --pc+0000
next_micro_state <= nop;
skipFetch <= '1';
end if;
when bsr1 => --bsr short
TG68_PC_brw <= '1';
next_micro_state <= nop;
when bsr2 => --bsr
if long_start = '0' then
TG68_PC_brw <= '1';
end if;
skipFetch <= '1';
set(longaktion) <= '1';
writePC <= '1';
setstate <= "11";
next_micro_state <= nopnop;
setstackaddr <= '1';
when nopnop => --bsr
next_micro_state <= nop;
when dbcc1 => --dbcc
if exe_condition = '0' then
Regwrena_now <= '1';
if c_out(1) = '1' then
skipFetch <= '1';
next_micro_state <= nop;
TG68_PC_brw <= '1';
end if;
end if;
when movem1 => --movem
if last_data_read(15 downto 0) /= X"0000" then
setstate <= "01";
if opcode(5 downto 3) = "100" then
set(mem_addsub) <= '1';
end if;
next_micro_state <= movem2;
end if;
when movem2 => --movem
if movem_run = '0' then
setstate <= "01";
else
set(movem_action) <= '1';
set(mem_addsub) <= '1';
next_micro_state <= movem2;
if opcode(10) = '0' then
setstate <= "11";
set(write_reg) <= '1';
else
setstate <= "10";
end if;
end if;
when andi => --andi
if opcode(5 downto 4) /= "00" then
setnextpass <= '1';
end if;
when op_AxAy => -- op -(Ax),-(Ay)
set_direct_data <= '1';
set(presub) <= '1';
dest_hbits <= '1';
dest_areg <= '1';
setstate <= "10";
when cmpm => -- cmpm (Ay)+,(Ax)+
set_direct_data <= '1';
set(postadd) <= '1';
dest_hbits <= '1';
dest_areg <= '1';
setstate <= "10";
when link1 => -- link
setstate <= "11";
source_areg <= '1';
set(opcMOVE) <= '1';
set(Regwrena) <= '1';
next_micro_state <= link2;
when link2 => -- link
setstackaddr <= '1';
set(ea_data_OP2) <= '1';
when unlink1 => -- unlink
setstate <= "10";
setstackaddr <= '1';
set(postadd) <= '1';
next_micro_state <= unlink2;
when unlink2 => -- unlink
set(ea_data_OP2) <= '1';
when trap00 => -- TRAP format #2
next_micro_state <= trap0;
set(presub) <= '1';
setstackaddr <='1';
setstate <= "11";
datatype <= "10";
when trap0 => -- TRAP
set(presub) <= '1';
setstackaddr <= '1';
setstate <= "11";
if VBR_Stackframe = 1 or (cpu(0) = '1' and VBR_Stackframe = 2) then --68010
set(writePC_add) <= '1';
datatype <= "01";
-- set_datatype <= "10";
next_micro_state <= trap1;
else
if trap_interrupt='1' or trap_trace='1' or trap_berr='1' THEN
writePC <= '1';
end if;
datatype <= "10";
next_micro_state <= trap2;
end if;
when trap1 => -- TRAP
-- additional word for 68020
if trap_interrupt = '1' or trap_trace = '1' then
writePC <= '1';
end if;
set(presub) <= '1';
setstackaddr <= '1';
setstate <= "11";
datatype <= "10";
next_micro_state <= trap2;
when trap2 => -- TRAP
set(presub) <= '1';
setstackaddr <= '1';
setstate <= "11";
datatype <= "01";
writeSR <= '1';
if trap_berr='1' THEN
next_micro_state <= trap4;
else
next_micro_state <= trap3;
end if;
when trap3 => -- TRAP
set_vectoraddr <= '1';
datatype <= "10";
set(direct_delta) <= '1';
set(directPC) <= '1';
setstate <= "10";
next_micro_state <= nopnop;
when trap4 => -- TRAP
set(presub) <= '1';
setstackaddr <='1';
setstate <= "11";
datatype <= "01";
writeSR <= '1';
next_micro_state <= trap5;
when trap5 => -- TRAP
set(presub) <= '1';
setstackaddr <='1';
setstate <= "11";
datatype <= "10";
writeSR <= '1';
next_micro_state <= trap6;
when trap6 => -- TRAP
set(presub) <= '1';
setstackaddr <='1';
setstate <= "11";
datatype <= "01";
writeSR <= '1';
next_micro_state <= trap3;
-- return from exception - RTE
-- fetch PC and status register from stack
-- 010+ fetches another word containing
-- the 12 bit vector offset and the
-- frame format. If the frame format is
-- 2 another two words have to be taken
-- from the stack
when rte1 => -- RTE
datatype <= "10";
setstate <= "10";
set(postadd) <= '1';
setstackaddr <= '1';
if VBR_Stackframe = 0 or (cpu(0) = '0' and VBR_Stackframe = 2) then
set(direct_delta) <= '1';
end if;
set(directPC) <= '1';
next_micro_state <= rte2;
when rte2 => -- RTE
datatype <= "01";
set(update_FC) <= '1';
if VBR_Stackframe = 1 or (cpu(0) = '1' and VBR_Stackframe = 2) then
-- 010+ reads another word
setstate <= "10";
set(postadd) <= '1';
setstackaddr <= '1';
next_micro_state <= rte3;
else
next_micro_state <= nop;
end if;
when rte3 => -- RTE
setstate <= "01"; -- idle state to wait
-- for input data to
-- arrive
next_micro_state <= rte4;
WHEN rte4 => -- RTE
-- check for stack frame format #2
if last_data_in(15 downto 12)="0010" then
-- read another 32 bits in this case
setstate <= "10"; -- read
datatype <= "10"; -- long word
set(postadd) <= '1';
setstackaddr <= '1';
next_micro_state <= rte5;
else
datatype <= "01";
next_micro_state <= nop;
end if;
WHEN rte5 => -- RTE
next_micro_state <= nop;
when movec1 => -- MOVEC
set(briefext) <= '1';
set_writePCbig <= '1';
if (brief(11 downto 0) = X"000" or brief(11 downto 0) = X"001" or brief(11 downto 0) = X"800" or brief(11 downto 0) = X"801") or
(cpu(1) = '1' and (brief(11 downto 0) = X"002" or brief(11 downto 0) = X"802" or brief(11 downto 0) = X"803" or brief(11 downto 0) = X"804")) then
if opcode(0) = '0' then
set(Regwrena) <= '1';
end if;
-- elsif brief(11 downto 0)=X"800"or brief(11 downto 0)=X"001" or brief(11 downto 0)=X"000" then
-- trap_addr_error <= '1';
-- trapmake <= '1';
else
trap_illegal <= '1';
trapmake <= '1';
end if;
when movep1 => -- MOVEP d(An)
setdisp <= '1';
set(mem_addsub) <= '1';
set(mem_byte) <= '1';
set(OP1addr) <= '1';
if opcode(6) = '1' then
set(movepl) <= '1';
end if;
if opcode(7) = '0' then
setstate <= "10";
else
setstate <= "11";
end if;
next_micro_state <= movep2;
when movep2 =>
if opcode(6) = '1' then
set(mem_addsub) <= '1';
set(OP1addr) <= '1';
end if;
if opcode(7) = '0' then
setstate <= "10";
else
setstate <= "11";
end if;
next_micro_state <= movep3;
when movep3 =>
if opcode(6) = '1' then
set(mem_addsub) <= '1';
set(OP1addr) <= '1';
set(mem_byte) <= '1';
if opcode(7) = '0' then
setstate <= "10";
else
setstate <= "11";
end if;
next_micro_state <= movep4;
else
datatype <= "01"; --Word
end if;
when movep4 =>
if opcode(7) = '0' then
setstate <= "10";
else
setstate <= "11";
end if;
next_micro_state <= movep5;
when movep5 =>
datatype <= "10"; --Long
when mul1 => -- mulu
if opcode(15) = '1' or MUL_Mode = 0 then
set_rot_cnt <= "001110";
else
set_rot_cnt <= "011110";
end if;
setstate <= "01";
next_micro_state <= mul2;
when mul2 => -- mulu
setstate <= "01";
if rot_cnt = "00001" then
next_micro_state <= mul_end1;
else
next_micro_state <= mul2;
end if;
when mul_end1 => -- mulu
datatype <= "10";
set(opcMULU) <= '1';
if opcode(15) = '0' and (MUL_Mode = 1 or MUL_Mode = 2) then
dest_2ndHbits <= '1';
source_2ndLbits <= '1';--???
set(write_lowlong) <= '1';
if sndOPC(10) = '1' then
setstate <= "01";
next_micro_state <= mul_end2;
end if;
set(Regwrena) <= '1';
end if;
datatype <= "10";
when mul_end2 => -- divu
set(write_reminder) <= '1';
set(Regwrena) <= '1';
set(opcMULU) <= '1';
when div1 => -- divu
setstate <= "01";
next_micro_state <= div2;
when div2 => -- divu
if (OP2out(31 downto 16) = x"0000" or opcode(15) = '1' or DIV_Mode = 0) and OP2out(15 downto 0) = x"0000" then --div zero
set_Z_error <= '1';
else
next_micro_state <= div3;
end if;
set(ld_rot_cnt) <= '1';
setstate <= "01";
when div3 => -- divu
if opcode(15) = '1' or DIV_Mode = 0 then
set_rot_cnt <= "001101";
else
set_rot_cnt <= "011101";
end if;
setstate <= "01";
next_micro_state <= div4;
when div4 => -- divu
setstate <= "01";
if rot_cnt = "00001" then
next_micro_state <= div_end1;
else
next_micro_state <= div4;
end if;
when div_end1 => -- divu
if opcode(15) = '0' and (DIV_Mode = 1 or DIV_Mode = 2) then
set(write_reminder) <= '1';
next_micro_state <= div_end2;
setstate <= "01";
end if;
set(opcDIVU) <= '1';
datatype <= "10";
when div_end2 => -- divu
dest_2ndHbits <= '1';
source_2ndLbits <= '1';--???
set(opcDIVU) <= '1';
when rota1 =>
if OP2out(5 downto 0) /= "000000" then
set_rot_cnt <= OP2out(5 downto 0);
else
set_exec(rot_nop) <= '1';
end if;
when bf1 =>
setstate <= "10";
when pack1 =>
-- result computation
if opcode(7 downto 6) = "10" then -- UNPK reads a byte
datatype <= "00"; -- Byte
end if;
set(ea_data_OP2) <= '1';
set(opcPACK) <= '1';
next_micro_state <= pack2;
when pack2 =>
-- write result
if opcode(7 downto 6) = "01" then -- PACK writes a byte
datatype <= "00";
end if;
set(presub) <= '1';
setstate <= "11";
dest_hbits <= '1';
dest_areg <= '1';
next_micro_state <= pack3;
when pack3 =>
-- this is just to keep datatype == 00
-- for byte writes
-- write result
if opcode(7 downto 6) = "01" then -- PACK writes a byte
datatype <= "00";
end if;
when others => NULL;
end case;
end process;
-----------------------------------------------------------------------------
-- MOVEC
-----------------------------------------------------------------------------
process (clk, VBR, CACR, brief)
begin
-- all other hexa codes should give illegal isntruction exception
if rising_edge(clk) then
if Reset = '1' then
VBR <= (others => '0');
CACR <= (others => '0');
elsif clkena_lw = '1' and exec(movec_wr) = '1' then
case brief(11 downto 0) is
when X"000" => NULL; -- SFC -- 68010+
when X"001" => NULL; -- DFC -- 68010+
when X"002" => CACR <= reg_QA(3 downto 0); -- 68020+
when X"800" => NULL; -- USP -- 68010+
when X"801" => VBR <= reg_QA; -- 68010+
when X"802" => NULL; -- CAAR -- 68020+
when X"803" => NULL; -- MSP -- 68020+
when X"804" => NULL; -- isP -- 68020+
when others => NULL;
end case;
end if;
end if;
movec_data <= (others => '0');
case brief(11 downto 0) is
when X"002" => movec_data <= "0000000000000000000000000000" & (CACR AND "0011");
when X"801" => --if VBR_Stackframe=1 or (cpu(0)='1' and VBR_Stackframe=2) then
movec_data <= VBR;
--end if;
when others => NULL;
end case;
end process;
CACR_out <= CACR;
VBR_out <= VBR;
-----------------------------------------------------------------------------
-- Conditions
-----------------------------------------------------------------------------
process (exe_opcode, Flags)
begin
case exe_opcode(11 downto 8) is
when X"0" => exe_condition <= '1';
when X"1" => exe_condition <= '0';
when X"2" => exe_condition <= not Flags(0) and not Flags(2);
when X"3" => exe_condition <= Flags(0) or Flags(2);
when X"4" => exe_condition <= not Flags(0);
when X"5" => exe_condition <= Flags(0);
when X"6" => exe_condition <= not Flags(2);
when X"7" => exe_condition <= Flags(2);
when X"8" => exe_condition <= not Flags(1);
when X"9" => exe_condition <= Flags(1);
when X"a" => exe_condition <= not Flags(3);
when X"b" => exe_condition <= Flags(3);
when X"c" => exe_condition <= (Flags(3) and Flags(1)) or (not Flags(3) and not Flags(1));
when X"d" => exe_condition <= (Flags(3) and not Flags(1)) or (not Flags(3) and Flags(1));
when X"e" => exe_condition <= (Flags(3) and Flags(1) and not Flags(2)) or (not Flags(3) and not Flags(1) and not Flags(2));
when X"f" => exe_condition <= (Flags(3) and not Flags(1)) or (not Flags(3) and Flags(1)) or Flags(2);
when others => NULL;
end case;
end process;
-----------------------------------------------------------------------------
-- Movem
-----------------------------------------------------------------------------
process (clk)
begin
if rising_edge(clk) then
if clkena_lw = '1' then
movem_actiond <= exec(movem_action);
if decodeOPC = '1' then
sndOPC <= data_read(15 downto 0);
elsif exec(movem_action) = '1' or set(movem_action) = '1' then
case movem_regaddr is
when "0000" => sndOPC(0) <= '0';
when "0001" => sndOPC(1) <= '0';
when "0010" => sndOPC(2) <= '0';
when "0011" => sndOPC(3) <= '0';
when "0100" => sndOPC(4) <= '0';
when "0101" => sndOPC(5) <= '0';
when "0110" => sndOPC(6) <= '0';
when "0111" => sndOPC(7) <= '0';
when "1000" => sndOPC(8) <= '0';
when "1001" => sndOPC(9) <= '0';
when "1010" => sndOPC(10) <= '0';
when "1011" => sndOPC(11) <= '0';
when "1100" => sndOPC(12) <= '0';
when "1101" => sndOPC(13) <= '0';
when "1110" => sndOPC(14) <= '0';
when "1111" => sndOPC(15) <= '0';
when others => NULL;
end case;
end if;
end if;
end if;
end process;
process (sndOPC, movem_mux)
begin
movem_regaddr <= "0000";
movem_run <= '1';
if sndOPC(3 downto 0) = "0000" then
if sndOPC(7 downto 4) = "0000" then
movem_regaddr(3) <= '1';
if sndOPC(11 downto 8) = "0000" then
if sndOPC(15 downto 12) = "0000" then
movem_run <= '0';
end if;
movem_regaddr(2) <= '1';
movem_mux <= sndOPC(15 downto 12);
else
movem_mux <= sndOPC(11 downto 8);
end if;
else
movem_mux <= sndOPC(7 downto 4);
movem_regaddr(2) <= '1';
end if;
else
movem_mux <= sndOPC(3 downto 0);
end if;
if movem_mux(1 downto 0) = "00" then
movem_regaddr(1) <= '1';
if movem_mux(2) = '0' then
movem_regaddr(0) <= '1';
end if;
else
if movem_mux(0) = '0' then
movem_regaddr(0) <= '1';
end if;
end if;
end process;
exec_d.opcMOVE <= exec(opcMOVE);
exec_d.opcMOVEQ <= exec(opcMOVEQ);
exec_d.opcMOVESR <= exec(opcMOVESR);
exec_d.opcMOVECCR <= exec(opcMOVECCR);
exec_d.opcADD <= exec(opcADD);
exec_d.opcADDQ <= exec(opcADDQ);
exec_d.opcor <= exec(opcor);
exec_d.opcand <= exec(opcand);
exec_d.opcEor <= exec(opcEor);
exec_d.opcCMP <= exec(opcCMP);
exec_d.opcROT <= exec(opcROT);
exec_d.opcCPMAW <= exec(opcCPMAW);
exec_d.opcEXT <= exec(opcEXT);
exec_d.opcABCD <= exec(opcABCD);
exec_d.opcSBCD <= exec(opcSBCD);
exec_d.opcBITS <= exec(opcBITS);
exec_d.opcSWAP <= exec(opcSWAP);
exec_d.opcScc <= exec(opcScc);
exec_d.andisR <= exec(andisR);
exec_d.eorisR <= exec(eorisR);
exec_d.orisR <= exec(orisR);
exec_d.opcMULU <= exec(opcMULU);
exec_d.opcDIVU <= exec(opcDIVU);
exec_d.dispouter <= exec(dispouter);
exec_d.rot_nop <= exec(rot_nop);
exec_d.ld_rot_cnt <= exec(ld_rot_cnt);
exec_d.writePC_add <= exec(writePC_add);
exec_d.ea_data_OP1 <= exec(ea_data_OP1);
exec_d.ea_data_OP2 <= exec(ea_data_OP2);
exec_d.use_XZFlag <= exec(use_XZFlag);
exec_d.get_bfoffset <= exec(get_bfoffset);
exec_d.save_memaddr <= exec(save_memaddr);
exec_d.opcCHK <= exec(opcCHK);
exec_d.movec_rd <= exec(movec_rd);
exec_d.movec_wr <= exec(movec_wr);
exec_d.Regwrena <= exec(Regwrena);
exec_d.update_FC <= exec(update_FC);
exec_d.linksp <= exec(linksp);
exec_d.movepl <= exec(movepl);
exec_d.update_ld <= exec(update_ld);
exec_d.OP1addr <= exec(OP1addr);
exec_d.write_reg <= exec(write_reg);
exec_d.changeMode <= exec(changeMode);
exec_d.ea_build <= exec(ea_build);
exec_d.trap_chk <= exec(trap_chk);
exec_d.store_ea_data <= exec(store_ea_data);
exec_d.addrlong <= exec(addrlong);
exec_d.postadd <= exec(postadd);
exec_d.presub <= exec(presub);
exec_d.subidx <= exec(subidx);
exec_d.no_Flags <= exec(no_Flags);
exec_d.use_SP <= exec(use_SP);
exec_d.to_CCR <= exec(to_CCR);
exec_d.to_SR <= exec(to_SR);
exec_d.OP2out_one <= exec(OP2out_one);
exec_d.OP1out_zero <= exec(OP1out_zero);
exec_d.mem_addsub <= exec(mem_addsub);
exec_d.addsub <= exec(addsub);
exec_d.directPC <= exec(directPC);
exec_d.direct_delta <= exec(direct_delta);
exec_d.directSR <= exec(directSR);
exec_d.directCCR <= exec(directCCR);
exec_d.exg <= exec(exg);
exec_d.get_ea_now <= exec(get_ea_now);
exec_d.ea_to_pc <= exec(ea_to_pc);
exec_d.hold_dwr <= exec(hold_dwr);
exec_d.to_USP <= exec(to_USP);
exec_d.from_USP <= exec(from_USP);
exec_d.write_lowlong <= exec(write_lowlong);
exec_d.write_reminder <= exec(write_reminder);
exec_d.movem_action <= exec(movem_action);
exec_d.briefext <= exec(briefext);
exec_d.get_2ndOPC <= exec(get_2ndOPC);
exec_d.mem_byte <= exec(mem_byte);
exec_d.longaktion <= exec(longaktion);
exec_d.opcRESET <= exec(opcRESET);
exec_d.opcBF <= exec(opcBF);
exec_d.opcBFwb <= exec(opcBFwb);
exec_d.opcPACK <= exec(opcPACK);
--when the instruction has completed, the decremented address
--register contains the address of the last operand stored. For
--the MC68020, MC68030, and MC68040, if the addressing
--register is also moved to memory, the value written is the
--initial register value decremented by the size of the oper-
--ation. The MC68000 writes the initial register value
--(not decremented).
regin_out <= regin;
end;
| gpl-3.0 | 48e44f4780f1ebcfdd8d5e72270091be | 0.496771 | 3.166552 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/MMFE8_1VMM/sources_1/readout/FIFO2UDP.vhd | 1 | 9,705 | ----------------------------------------------------------------------------------
-- Company: NTU ATHNENS - BNL
-- Engineer: Panagiotis Gkountoumis
--
-- Create Date: 18.04.2016 13:00:21
-- Design Name:
-- Module Name: config_logic - Behavioral
-- Project Name: MMFE8
-- Target Devices: Arix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2016.2
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity FIFO2UDP is
Port (
clk_200 : in std_logic;
clk_125 : in std_logic;
daq_data_in : in std_logic_vector(63 downto 0);
fifo_data_out : out std_logic_vector (7 downto 0);
udp_txi : out udp_tx_type;
udp_tx_start : out std_logic;
re_out : out std_logic;
control : out std_logic;
udp_tx_data_out_ready : in std_logic;
wr_en : in std_logic;
end_packet : in std_logic;
global_reset : in std_logic;
packet_length_in : in integer;
reset_DAQ_FIFO : in std_logic;
sending_o : out std_logic
);
end FIFO2UDP;
architecture Behavioral of FIFO2UDP is
signal count : integer := 0;
signal i : integer := 0;
signal count_length : integer := 0;
signal packet_length_int : integer := 0;
signal daq_fifo_re : std_logic := '0';
signal fifo_empty : std_logic := '0';
signal prog_fifo_empty : std_logic := '0';
signal daq_out : std_logic_vector(255 downto 0);
signal data_out : std_logic_vector(7 downto 0) := x"00";
signal data_out_valid : std_logic := '0';
signal packet_length : integer := 0;
signal daq_data_in_int : std_logic_vector(63 downto 0);
signal data_out_last : std_logic := '0';
signal sending : std_logic := '0';
signal end_packet_synced : std_logic := '0';
signal udp_tx_start_int : std_logic := '0';
signal wr_en_int : std_logic := '0';
signal is_trailer : integer := 0;
signal temp_buffer : std_logic_vector(63 downto 0) := (others=> '0');
signal daq_data_out : std_logic_vector(7 downto 0) := x"00";
type tx_state is (HEADER, EN_RE, WAIT_ONE, DATA, TRAILER, LAST, IDLE);
signal state : tx_state;
component readout_fifo is
port(
rst : in std_logic;
wr_clk : in std_logic;
rd_clk : in std_logic;
din : in std_logic_vector(63 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(7 downto 0);
full : out std_logic;
empty : out std_logic;
prog_empty : out std_logic
);
end component;
begin
daq_FIFO_instance: readout_fifo
port map(
rst => reset_DAQ_FIFO,
wr_clk => clk_200,
rd_clk => clk_125,
din => daq_data_in,
wr_en => wr_en,
rd_en => daq_fifo_re,
dout => daq_data_out,
full => open,
empty => fifo_empty,
prog_empty => prog_fifo_empty
);
synced_end_packet: process (clk_125)
begin
if clk_125'event and clk_125 = '1' then
end_packet_synced <= end_packet;
end if;
end process;
process (clk_125, count, state, udp_tx_data_out_ready, fifo_empty, prog_fifo_empty, data_out_valid, end_packet_synced)
begin
if clk_125'event and clk_125 = '1' then
if global_reset = '1' then
sending <= '0';
data_out_last <= '0';
data_out_valid <= '0';
udp_tx_start_int <= '0';
elsif end_packet_synced = '1' and sending = '0' then
packet_length <= (packet_length_in * 8) + 4;
count_length <= packet_length_in * 8;
state <= HEADER;
sending <= '1';
else
end if;
if sending = '1' then
if count = 0 then
count <= count + 1;
data_out_last <= '0';
data_out_valid <= '0';
data_out <= (others => '0');
udp_tx_start_int <= '0';
elsif count = 1 then
udp_tx_start_int <= '1';
udp_txi.hdr.dst_ip_addr <= x"c0a80010"; -- set a generic ip adrress (192.168.0.255)
udp_txi.hdr.src_port <= x"19CB"; -- set src and dst ports
udp_txi.hdr.dst_port <= x"1778"; -- x"6af0";
udp_txi.hdr.data_length <= std_logic_vector(to_unsigned(packet_length, udp_txi.hdr.data_length'length));
daq_fifo_re <= '0';
udp_txi.hdr.checksum <= x"0000";
count <= count + 1;
elsif count = 2 then
if udp_tx_data_out_ready = '1' then
udp_tx_start_int <= '0';
daq_fifo_re <= '1';
count <= count + 1;
else
end if;
elsif count = 3 then
if udp_tx_data_out_ready = '1' then
count_length <= count_length - 1;
udp_tx_start_int <= '0';
count <= count + 1;
data_out <= daq_data_out;
end if;
elsif count = 4 then
if udp_tx_data_out_ready = '1' then
if count_length = 1 then
daq_fifo_re <= '0';
elsif count_length = 0 then
count <= count + 1;
daq_fifo_re <= '0';
end if;
count_length <= count_length - 1;
udp_tx_start_int <= '0';
data_out_valid <= '1';
control <= '0';
data_out_last <= '0';
data_out <= daq_data_out;
else
daq_fifo_re <= '0';
end if;
elsif count >= 5 and count <= 7 then
if udp_tx_data_out_ready = '1' then
daq_fifo_re <= '0';
udp_tx_start_int <= '0';
data_out_last <= '0';
data_out <= x"ff";
count <= count + 1;
end if;
elsif count = 8 then
if udp_tx_data_out_ready = '1' then
daq_fifo_re <= '0';
udp_tx_start_int <= '0';
data_out_last <= '1';
data_out <= x"ff";
count <= count + 1;
end if;
elsif count = 9 then
count <= count + 1;
data_out_last <= '0';
data_out_valid <= '0';
data_out <= (others => '0');
udp_tx_start_int <= '0';
else
count <= 0;
count_length <= 0;
data_out_last <= '0';
data_out_valid <= '0';
udp_tx_start_int <= '0';
sending <= '0';
end if;
end if;
end if;
end process;
udp_tx_start <= udp_tx_start_int;
udp_txi.data.data_out_last <= data_out_last;
udp_txi.data.data_out_valid <= data_out_valid ;
udp_txi.data.data_out <= data_out;
packet_length_int <= packet_length_in;
daq_data_in_int <= daq_data_in;
wr_en_int <= wr_en;
sending_o <= sending;
end Behavioral; | gpl-3.0 | 66a836de96a8904572df25e2c7c623a9 | 0.369191 | 4.397372 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/configuration/ckbc_gen.vhd | 1 | 8,677 | ----------------------------------------------------------------------------------
-- Company: Westf??lische Hochschule
-- Engineer: Pia Piekarek ([email protected])
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Pia Piekarek
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 13.01.2017 11:56:04
-- Design Name:
-- Module Name: ckbc_gen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description: CKBC Generator
--
-- Dependencies:
--
-- Changelog:
-- 20.02.2017 Changed the FSM to create a multicycle path. Changed the input clock
-- frequency to 160 Mhz. (Christos Bakalis)
-- 12.03.2017 Removed FSM. (Christos Bakalis)
-- 31.03.2017 Added CKBC for readout mode. (Christos Bakalis)
-- 25.06.2017 Fix for CKBC strobbing mode. Allowing greater values that 7 in order
-- to allow a default to 32. CKBC minimum should no less than 12. (Paris)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ckbc_gen is
port(
clk_160 : in std_logic;
duty_cycle : in std_logic_vector(7 downto 0);
freq : in std_logic_vector(5 downto 0);
readout_mode : in std_logic;
enable_ro_ckbc : in std_logic;
ready : in std_logic;
ckbc_ro_out : out std_logic;
ckbc_out : out std_logic;
ckbc_max_num : in std_logic_vector(7 downto 0)
);
end ckbc_gen;
architecture Behavioral of ckbc_gen is
signal t_high : unsigned(16 downto 0) := to_unsigned(0,17);
signal t_low : unsigned(16 downto 0) := to_unsigned(0,17);
signal count : unsigned(7 downto 0) := to_unsigned(0,8);
signal p_high : unsigned(16 downto 0) := to_unsigned(0,17); --number of clock cycles while high
signal p_low : unsigned(16 downto 0) := to_unsigned(0,17); --number of clock cycles while low
signal ready_i : std_logic := '0';
signal ready_sync : std_logic := '0';
type ckbc_ro_type is (ST_IDLE, ST_SEND, ST_WAIT);
type ckbc_cnt_type is (ST_IDLE, ST_WAIT_CKBC, ST_WAIT_ENABLE, ST_INCR);
signal state : ckbc_ro_type := ST_IDLE;
signal state_cnt : ckbc_cnt_type := ST_IDLE;
signal ckbc_inhibit : std_logic := '0';
signal readout_mode_i : std_logic := '0';
signal readout_mode_s : std_logic := '0';
signal count_ro : unsigned(7 downto 0) := to_unsigned(0,8);
signal ckbc_max_cnt : unsigned(6 downto 0) := to_unsigned(0,7);
signal ckbc_ro : std_logic := '0';
constant ckbc_max_limit : integer := 32;
attribute ASYNC_REG : string;
attribute ASYNC_REG of ready_i : signal is "TRUE";
attribute ASYNC_REG of ready_sync : signal is "TRUE";
attribute ASYNC_REG of readout_mode_i : signal is "TRUE";
attribute ASYNC_REG of readout_mode_s : signal is "TRUE";
begin
-- 2 FF synchronizer
sync_ready: process(clk_160)
begin
if(rising_edge(clk_160))then
ready_i <= ready;
ready_sync <= ready_i;
readout_mode_i <= readout_mode;
readout_mode_s <= readout_mode_i;
end if;
end process;
clocking_proc: process(clk_160)
begin
if (rising_edge(clk_160)) then
if(ready_sync = '0') then
ckbc_out <= '0';
count <= to_unsigned(0,8);
else
if(count < (p_high+p_low)) then
if(count < p_high)then
ckbc_out <= '1';
elsif (count < (p_high+p_low)) then
ckbc_out <= '0';
end if;
count <= count + 1;
elsif (p_high >= 1 and p_low >= 1) then
count <= to_unsigned(1,8);
ckbc_out <= '1';
end if;
end if;
end if;
end process;
readout_mode_proc: process(clk_160)
begin
if(rising_edge(clk_160))then
if(readout_mode_s = '1')then
case state is
-- wait for enable signal to go high
when ST_IDLE =>
if(enable_ro_ckbc = '1')then
state <= ST_SEND;
else
state <= ST_IDLE;
end if;
-- send two CKBC pulses
when ST_SEND =>
if(ckbc_inhibit = '0')then
if(count_ro < (p_high+p_low)) then
if(count_ro < p_high)then
ckbc_ro <= '1';
elsif (count_ro < (p_high+p_low)) then
ckbc_ro <= '0';
end if;
count_ro <= count_ro + 1;
elsif (p_high >= 1 and p_low >= 1) then
count_ro <= to_unsigned(1,8);
ckbc_ro <= '1';
end if;
else
count_ro <= (others => '0');
state <= ST_WAIT;
ckbc_ro <= '0';
end if;
-- wait for inhibit to go low
when ST_WAIT =>
if(ckbc_inhibit = '0')then
state <= ST_IDLE;
else
state <= ST_WAIT;
end if;
when others => state <= ST_IDLE;
end case;
else
ckbc_ro <= '0';
count_ro <= (others => '0');
state <= ST_IDLE;
end if;
end if;
end process;
count_ckbc_proc: process(clk_160)
begin
if(rising_edge(clk_160))then
if(readout_mode_s = '1')then
case state_cnt is
when ST_IDLE =>
if(ckbc_ro = '1')then
state_cnt <= ST_WAIT_CKBC;
else
state_cnt <= ST_IDLE;
end if;
when ST_WAIT_CKBC =>
if(ckbc_ro = '0')then
state_cnt <= ST_INCR;
ckbc_max_cnt <= ckbc_max_cnt + 1;
else
state_cnt <= ST_WAIT_CKBC;
end if;
when ST_INCR =>
if (ckbc_max_cnt = unsigned(ckbc_max_num)) then
ckbc_inhibit <= '1';
state_cnt <= ST_WAIT_ENABLE;
else
state_cnt <= ST_IDLE;
end if;
when ST_WAIT_ENABLE =>
if(enable_ro_ckbc = '0')then
state_cnt <= ST_IDLE;
ckbc_inhibit <= '0';
else
state_cnt <= ST_WAIT_ENABLE;
end if;
ckbc_max_cnt <= (others => '0');
when others =>
ckbc_inhibit <= '0';
state_cnt <= ST_IDLE;
ckbc_max_cnt <= (others => '0');
end case;
else
ckbc_inhibit <= '0';
state_cnt <= ST_IDLE;
ckbc_max_cnt <= (others => '0');
end if;
end if;
end process;
t_high_proc: process(freq)
begin
case freq is
when "101000" => -- 40
t_high <= to_unsigned(6250,17);
t_low <= to_unsigned(18750,17);
when "010100" => -- 20
t_high <= to_unsigned(12500,17);
t_low <= to_unsigned(37500,17);
when "001010" => -- 10
t_high <= to_unsigned(18750,17);
t_low <= to_unsigned(81250,17);
when others =>
t_high <= to_unsigned(6250,17);
t_low <= to_unsigned(18750,17);
end case;
end process;
p_high <= (t_high / to_unsigned(6250, 16)); -- input clock period: 160 Mhz = 6.250 ns
p_low <= (t_low / to_unsigned(6250, 16));
ckbc_ro_out <= ckbc_ro;
end Behavioral;
| gpl-3.0 | 3d06c5726314c7584ef4d7a95f0d1a2a | 0.48496 | 3.800701 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/EPROC_IN4_DEC8b10b.vhd | 1 | 8,245 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/22/2014
--! Module Name: EPROC_IN4_DEC8b10b
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.ALL;
use work.all;
use work.centralRouter_package.all;
--! 8b10b decoder for EPROC_IN4 module
entity EPROC_IN4_DEC8b10b is
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
edataIN : in std_logic_vector (3 downto 0);
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic;
busyOut : out std_logic
);
end EPROC_IN4_DEC8b10b;
architecture Behavioral of EPROC_IN4_DEC8b10b is
----------------------------------
----------------------------------
component KcharTest is
port (
clk : in std_logic;
encoded10in : in std_logic_vector (9 downto 0);
KcharCode : out std_logic_vector (1 downto 0)
);
end component KcharTest;
----------------------------------
----------------------------------
signal EDATAbitstreamSREG : std_logic_vector (23 downto 0) := (others=>'0'); -- 24 bit (4 x 5 = 20, plus 4 more)
signal word10bx2_align_array, word10bx2_align_array_r : word10b_2array_4array_type;
signal word10b_array, word10b_array_s : word10b_2array_type;
signal isk_array : isk_2array_type;
signal comma_valid_bits_or, word10bx2_align_rdy_r,
word10b_array_rdy, word10b_array_rdy_s : std_logic;
signal align_select : std_logic_vector (1 downto 0) := (others=>'0');
signal comma_valid_bits : std_logic_vector (3 downto 0);
signal alignment_sreg : std_logic_vector (4 downto 0) := (others=>'0');
begin
-------------------------------------------------------------------------------------------
--live bitstream
-- 24 bit input shift register
-------------------------------------------------------------------------------------------
process(bitCLK, rst)
begin
if rst = '1' then
EDATAbitstreamSREG <= (others => '0');
elsif bitCLK'event and bitCLK = '1' then
EDATAbitstreamSREG <= edataIN & EDATAbitstreamSREG(23 downto 4);
end if;
end process;
--
-------------------------------------------------------------------------------------------
--clock0
-- input shift register mapping into 10 bit registers
-------------------------------------------------------------------------------------------
input_map: for I in 0 to 3 generate -- 2 10bit-words per alignment, 4 possible alignments
--word10bx2_align_array(I)(0) <= EDATAbitstreamSREG((I+9) downto (I+0)); -- 1st 10 bit word, alligned to bit I
--word10bx2_align_array(I)(1) <= EDATAbitstreamSREG((I+19) downto (I+10)); -- 2nd 10 bit word, alligned to bit I
word10bx2_align_array(I)(0) <= EDATAbitstreamSREG(I+0)&EDATAbitstreamSREG(I+1)&EDATAbitstreamSREG(I+2)&EDATAbitstreamSREG(I+3)&EDATAbitstreamSREG(I+4)&
EDATAbitstreamSREG(I+5)&EDATAbitstreamSREG(I+6)&EDATAbitstreamSREG(I+7)&EDATAbitstreamSREG(I+8)&EDATAbitstreamSREG(I+9); -- 1st 10 bit word, alligned to bit I
word10bx2_align_array(I)(1) <= EDATAbitstreamSREG(I+10)&EDATAbitstreamSREG(I+11)&EDATAbitstreamSREG(I+12)&EDATAbitstreamSREG(I+13)&EDATAbitstreamSREG(I+14)&
EDATAbitstreamSREG(I+15)&EDATAbitstreamSREG(I+16)&EDATAbitstreamSREG(I+17)&EDATAbitstreamSREG(I+18)&EDATAbitstreamSREG(I+19); -- 2nd 10 bit word, alligned to bit I
end generate input_map;
--
-------------------------------------------------------------------------------------------
--clock0
-- K28.5 comma test
-------------------------------------------------------------------------------------------
comma_test: for I in 0 to 3 generate -- 2 10bit-words per alignment, comma is valid if two first words have comma
comma_valid_bits(I) <= '1' when ((word10bx2_align_array(I)(0) = COMMAp or word10bx2_align_array(I)(0) = COMMAn) and
(word10bx2_align_array(I)(1) = COMMAp or word10bx2_align_array(I)(1) = COMMAn)) else '0';
end generate comma_test;
--
comma_valid_bits_or <= comma_valid_bits(3) or comma_valid_bits(2) or comma_valid_bits(1) or comma_valid_bits(0);
--
-------------------------------------------------------------------------------------------
--clock1
-- alignment selector state
-------------------------------------------------------------------------------------------
process(bitCLK, rst)
begin
if rst = '1' then
alignment_sreg <= "00000";
elsif bitCLK'event and bitCLK = '1' then
if comma_valid_bits_or = '1' then
alignment_sreg <= "10000";
else
alignment_sreg <= alignment_sreg(0) & alignment_sreg(4 downto 1);
end if;
end if;
end process;
--
input_reg1: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10bx2_align_array_r <= word10bx2_align_array;
end if;
end process;
--
word10bx2_align_rdy_r <= alignment_sreg(4);
--
process(bitCLK, rst)
begin
if rst = '1' then
align_select <= "00";
elsif bitCLK'event and bitCLK = '1' then
if comma_valid_bits_or = '1' then
align_select(0) <= (not comma_valid_bits(0)) and (
comma_valid_bits(1) or ( (not comma_valid_bits(1)) and (not comma_valid_bits(2)) and (
comma_valid_bits(3)
)));
align_select(1) <= (not comma_valid_bits(0)) and (not comma_valid_bits(1)) and
(comma_valid_bits(2) or comma_valid_bits(3));
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
--clock2
-- alignment selected
-------------------------------------------------------------------------------------------
--
input_reg2: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10b_array_rdy <= word10bx2_align_rdy_r;
end if;
end process;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
case (align_select) is
when "00" => -- bit0 word got comma => align to bit0
word10b_array <= word10bx2_align_array_r(0);
when "01" => -- bit1 word got comma => align to bit1
word10b_array <= word10bx2_align_array_r(1);
when "10" => -- bit2 word got comma => align to bit2
word10b_array <= word10bx2_align_array_r(2);
when "11" => -- bit3 word got comma => align to bit3
word10b_array <= word10bx2_align_array_r(3);
when others =>
end case;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- 8b10b K-characters codes: COMMA/SOC/EOC/DATA
-------------------------------------------------------------------------------------------
KcharTests: for I in 0 to 1 generate
KcharTestn: KcharTest
port map(
clk => bitCLK,
encoded10in => word10b_array(I),
KcharCode => isk_array(I)
);
end generate KcharTests;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10b_array_s <= word10b_array;
word10b_array_rdy_s <= word10b_array_rdy;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- 2 words get aligned and ready as 10 bit word (data 8 bit and data code 2 bit)
-------------------------------------------------------------------------------------------
EPROC_IN4_ALIGN_BLOCK_inst: entity work.EPROC_IN4_ALIGN_BLOCK
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst,
bytes => word10b_array_s,
bytes_rdy => word10b_array_rdy_s,
dataOUT => dataOUT,
dataOUTrdy => dataOUTrdy,
busyOut => busyOut
);
end Behavioral;
| gpl-3.0 | a634953a4fc31ea54477b7b9400c4c66 | 0.491935 | 3.840242 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/DSP_Package/DSP_Package.vhd | 1 | 10,672 | --------------------------------------------------------------------------------------------------
-- Digital Signal Processing package
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- PACKAGE
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package dsp_pkg is
--Definitions for coefficients
constant NUM_COEF_BITS : positive := 16;
subtype coefficient is signed(NUM_COEF_BITS-1 downto 0);
type coefficient_array is array (natural range <>) of coefficient;
--Definitions for signal data
constant NUM_SIG_BITS : positive := 16;
subtype sig is signed(NUM_SIG_BITS-1 downto 0);
subtype summed_sig is signed(NUM_SIG_BITS downto 0); --for when 2 sigs are added together
constant NUM_SUMMED_SIG_BITS : positive := NUM_SIG_BITS+1;
type sig_array is array (natural range <>) of sig;
--Types for fir signal data - for use for internal FIR calculations
--The size is based on the number of bits needed for calculation. The multiplication of
--coefficient and signal is 16-bits + 16-bits. The cumulative addtion of N taps will need
--require a log2(N) addtional bits. Allowing for up to 256 taps, the full size will be
--16 + 16 + log2(256) or 40 bits
constant MAX_TAPS : positive := 256;
constant NUM_ADDED_TAPS_BITS : positive := 8; --log2(256)
constant NUM_FIR_BITS : positive := NUM_COEF_BITS + NUM_SIG_BITS + NUM_ADDED_TAPS_BITS;
subtype fir_sig is signed(NUM_FIR_BITS-1 downto 0);
type fir_sig_array is array (natural range <>) of fir_sig;
--Coefficients for FIR filters
constant ZERO_COEF : coefficient := x"0000";
constant PASS_THRU : coefficient_array := (x"0000", x"0000", x"0000",
x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"7FFF",
x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000",
x"0000", x"0000");
constant LOW_PASS_21 : coefficient_array := (x"0000", x"0070", x"0000",
x"fe7b", x"0000", x"0453", x"0000", x"f512", x"0000", x"27c2", x"4010",
x"27c2", x"0000", x"f512", x"0000", x"0453", x"0000", x"fe7b", x"0000",
x"0070", x"0000");
constant HIGH_PASS_21 : coefficient_array := (x"0000", x"ff90", x"0000",
x"0185", x"0000", x"fbad", x"0000", x"0aee", x"0000", x"d83e", x"4010",
x"d83e", x"0000", x"0aee", x"0000", x"fbad", x"0000", x"0185", x"0000",
x"ff90", x"0000");
constant LOW_PASS_41 : coefficient_array := (x"0000", x"ffdb", x"0000",
x"0042", x"0000", x"ff7f", x"0000", x"00ee", x"0000", x"fe66", x"0000",
x"02a1", x"0000", x"fbc8", x"0000", x"06ef", x"0000", x"f330", x"0000",
x"2872", x"4010", x"2872", x"0000", x"f330", x"0000", x"06ef", x"0000",
x"fbc8", x"0000", x"02a1", x"0000", x"fe66", x"0000", x"00ee", x"0000",
x"ff7f", x"0000", x"0042", x"0000", x"ffdb", x"0000");
constant HIGH_PASS_41 : coefficient_array := (x"0000", x"0025", x"0000",
x"ffbe", x"0000", x"0081", x"0000", x"ff12", x"0000", x"019a", x"0000",
x"fd5f", x"0000", x"0438", x"0000", x"f911", x"0000", x"0cd0", x"0000",
x"d78e", x"4010", x"d78e", x"0000", x"0cd0", x"0000", x"f911", x"0000",
x"0438", x"0000", x"fd5f", x"0000", x"019a", x"0000", x"ff12", x"0000",
x"0081", x"0000", x"ffbe", x"0000", x"0025", x"0000");
constant LOW_PASS_101 : coefficient_array := (x"0000", x"0000", x"0000",
x"ffff", x"0000", x"0003", x"0000", x"fffb", x"0000", x"0009", x"0000",
x"fff2", x"0000", x"0015", x"0000", x"ffe1", x"0000", x"002c", x"0000",
x"ffc2", x"0000", x"0054", x"0000", x"ff90", x"0000", x"0092", x"0000",
x"ff43", x"0000", x"00f2", x"0000", x"fecd", x"0000", x"0183", x"0000",
x"fe19", x"0000", x"0267", x"0000", x"fcf0", x"0000", x"03fd", x"0000",
x"fa9c", x"0000", x"07d5", x"0000", x"f29f", x"0000", x"28a3", x"4010",
x"28a3", x"0000", x"f29f", x"0000", x"07d5", x"0000", x"fa9c", x"0000",
x"03fd", x"0000", x"fcf0", x"0000", x"0267", x"0000", x"fe19", x"0000",
x"0183", x"0000", x"fecd", x"0000", x"00f2", x"0000", x"ff43", x"0000",
x"0092", x"0000", x"ff90", x"0000", x"0054", x"0000", x"ffc2", x"0000",
x"002c", x"0000", x"ffe1", x"0000", x"0015", x"0000", x"fff2", x"0000",
x"0009", x"0000", x"fffb", x"0000", x"0003", x"0000", x"ffff", x"0000",
x"0000", x"0000");
constant HIGH_PASS_101 : coefficient_array := (x"0000", x"0000", x"0000",
x"0001", x"0000", x"fffd", x"0000", x"0005", x"0000", x"fff7", x"0000",
x"000e", x"0000", x"ffeb", x"0000", x"001f", x"0000", x"ffd4", x"0000",
x"003e", x"0000", x"ffac", x"0000", x"0070", x"0000", x"ff6e", x"0000",
x"00bd", x"0000", x"ff0e", x"0000", x"0133", x"0000", x"fe7d", x"0000",
x"01e7", x"0000", x"fd99", x"0000", x"0310", x"0000", x"fc03", x"0000",
x"0564", x"0000", x"f82b", x"0000", x"0d61", x"0000", x"d75d", x"4010",
x"d75d", x"0000", x"0d61", x"0000", x"f82b", x"0000", x"0564", x"0000",
x"fc03", x"0000", x"0310", x"0000", x"fd99", x"0000", x"01e7", x"0000",
x"fe7d", x"0000", x"0133", x"0000", x"ff0e", x"0000", x"00bd", x"0000",
x"ff6e", x"0000", x"0070", x"0000", x"ffac", x"0000", x"003e", x"0000",
x"ffd4", x"0000", x"001f", x"0000", x"ffeb", x"0000", x"000e", x"0000",
x"fff7", x"0000", x"0005", x"0000", x"fffd", x"0000", x"0001", x"0000",
x"0000", x"0000");
constant PR_ANALYSIS_LOW : coefficient_array := (x"0a71", x"2378", x"3882",
x"2c62", x"02c3", x"e702", x"f433", x"0de2", x"0c3f", x"f7f0", x"f50c",
x"04e9", x"096d", x"fcde", x"f7f6", x"021f", x"06d3", x"fe78", x"fa36",
x"012f", x"04e8", x"ff05", x"fbdc", x"00dd", x"037a", x"ff35", x"fd1a",
x"00bf", x"0263", x"ff4b", x"fe0f", x"00aa", x"018e", x"ff61", x"fec6",
x"0095", x"00ef", x"ff7b", x"ff4d", x"0077", x"0080", x"ff99", x"ffaa",
x"0055", x"0039", x"ffb9", x"ffdc", x"003e", x"0018", x"ffa9", x"0041",
x"ffed");
constant PR_ANALYSIS_HIGH : coefficient_array := (x"0013", x"0041", x"0057",
x"0018", x"ffc2", x"ffdc", x"0047", x"0039", x"ffab", x"ffaa", x"0067",
x"0080", x"ff89", x"ff4d", x"0085", x"00ef", x"ff6b", x"fec6", x"009f",
x"018e", x"ff56", x"fe0f", x"00b5", x"0263", x"ff41", x"fd1a", x"00cb",
x"037a", x"ff23", x"fbdc", x"00fb", x"04e8", x"fed1", x"fa36", x"0188",
x"06d3", x"fde1", x"f7f6", x"0322", x"096d", x"fb17", x"f50c", x"0810",
x"0c3f", x"f21e", x"f433", x"18fe", x"02c3", x"d39e", x"3882", x"dc88",
x"0a71");
constant PR_SYNTHESIS_LOW : coefficient_array := (x"ffda", x"0083", x"ff51",
x"0030", x"007d", x"ffb7", x"ff72", x"0072", x"00ab", x"ff53", x"ff32",
x"0100", x"00ef", x"fe99", x"fef6", x"01de", x"012a", x"fd8b", x"fec2",
x"031d", x"0155", x"fc1e", x"fe96", x"04c7", x"017e", x"fa34", x"fe6a",
x"06f5", x"01bb", x"f7b7", x"fe09", x"09d0", x"025e", x"f46b", x"fcf0",
x"0da7", x"043f", x"efec", x"f9bc", x"12da", x"09d3", x"ea17", x"efe0",
x"187e", x"1bc5", x"e865", x"ce04", x"0587", x"58c4", x"7105", x"46f0",
x"14e3");
constant PR_SYNTHESIS_HIGH : coefficient_array := (x"14e3", x"b910", x"7105",
x"a73c", x"0587", x"31fc", x"e865", x"e43b", x"187e", x"1020", x"ea17",
x"f62d", x"12da", x"0644", x"efec", x"fbc1", x"0da7", x"0310", x"f46b",
x"fda2", x"09d0", x"01f7", x"f7b7", x"fe45", x"06f5", x"0196", x"fa34",
x"fe82", x"04c7", x"016a", x"fc1e", x"feab", x"031d", x"013e", x"fd8b",
x"fed6", x"01de", x"010a", x"fe99", x"ff11", x"0100", x"00ce", x"ff53",
x"ff55", x"0072", x"008e", x"ffb7", x"ff83", x"0030", x"00af", x"0083",
x"0026");
--Function declarations
-- type slice_type is array(natural range <>) of integer;
function slice_coefficient_array ( original_array : coefficient_array;
num_cuts : integer;
cut : integer;
front_load : integer) return coefficient_array;
end package;
--------------------------------------------------------------------------------------------------
-- PACKAGE BODY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package body dsp_pkg is
--This function slices a coefficient array into the polyphase slice of that array.
--The original array is the coefficient array to be sliced
--num_cuts is the number of sub-arrays that can be created
--cut is the 1-based identifier of the cut desired (e.g. when num_cuts is 2, cut can be 1 or 2)
--front_load can be 0 or 1. 0 indicates that the coeffs will be back loaded (padded 0's in the
-- front. 1 indicates that coefs will be front loaded (padded 0's in the back)
function slice_coefficient_array ( original_array : coefficient_array;
num_cuts : integer;
cut : integer;
front_load : integer) return coefficient_array is
constant slice_len : integer := (original_array'length - cut + num_cuts) / num_cuts;
constant result_len : integer := (original_array'length - 1 + num_cuts) / num_cuts;
constant slice_starter : integer := result_len-slice_len;
variable result : coefficient_array(1 to result_len)
:= (others => (others => '0'));
begin
for index in 1 to slice_len loop
if(front_load = 1) then
result(index) := original_array(cut-1 + ((index-1)*num_cuts));
else
result(index+slice_starter) := original_array(cut-1 + ((index-1)*num_cuts));
end if;
end loop;
return result;
end function;
end package body; | mit | ca8bb66074cecbcc3a75c6bcd0e41bc7 | 0.502999 | 2.875 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/Pulse_Gen/tb_pulse_gen.vhd | 1 | 1,611 | --------------------------------------------------------------------------------------------------
-- Pulse Generator Testbench
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tb_clockgen_pkg.all;
use work.pulse_gen_pkg.all;
entity tb_pulse_gen is
end tb_pulse_gen;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture rtl of tb_pulse_gen is
signal clk : std_logic;
signal rst : std_logic;
signal pulse : std_logic;
begin
--Instantiate clock generator
clk_gen : tb_clockgen
generic map(PERIOD => 10ns,
DUTY_CYCLE => 0.50)
port map( clk => clk);
--Unit under test
uut : pulse_gen
generic map(CLKS_PER_PULSE => 20)
port map( clk => clk,
rst => rst,
pulse => pulse);
--main process
main : process
begin
rst <= '1';
wait until rising_edge(clk);
wait until falling_edge(clk);
rst <= '0';
wait;
end process;
end rtl;
| mit | c4b4c3c6ad1caf275e21608c80fe8de4 | 0.348231 | 5.479592 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/EPROC_OUT8_ENC8b10b.vhd | 2 | 6,773 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 05/19/2014
--! Module Name: EPROC_OUT8_ENC8b10b
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.centralRouter_package.all;
--! 8b10b encoder for EPROC_OUT8 module
entity EPROC_OUT8_ENC8b10b is
port(
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
getDataTrig : out std_logic;
edataIN : in std_logic_vector (9 downto 0);
edataINrdy : in std_logic;
EdataOUT : out std_logic_vector(7 downto 0) -- ready on every bitCLK
);
end EPROC_OUT8_ENC8b10b;
architecture Behavioral of EPROC_OUT8_ENC8b10b is
----------------------------------
----------------------------------
component pulse_pdxx_pwxx
generic(
pd : integer := 0;
pw : integer := 1);
port(
clk : in std_logic;
trigger : in std_logic;
pulseout : out std_logic
);
end component pulse_pdxx_pwxx;
----------------------------------
----------------------------------
component enc8b10_wrap
port (
clk : in std_logic;
rst : in std_logic;
dataCode : in std_logic_vector (1 downto 0); -- 00"data, 01"eop, 10"sop, 11"comma
dataIN : in std_logic_vector (7 downto 0);
dataINrdy : in std_logic;
encDataOut : out std_logic_vector (9 downto 0);
encDataOutrdy : out std_logic
);
end component enc8b10_wrap;
----------------------------------
----------------------------------
component MUX8_Nbit
generic (N : integer := 16);
Port (
data0 : in std_logic_vector((N-1) downto 0);
data1 : in std_logic_vector((N-1) downto 0);
data2 : in std_logic_vector((N-1) downto 0);
data3 : in std_logic_vector((N-1) downto 0);
data4 : in std_logic_vector((N-1) downto 0);
data5 : in std_logic_vector((N-1) downto 0);
data6 : in std_logic_vector((N-1) downto 0);
data7 : in std_logic_vector((N-1) downto 0);
sel : in std_logic_vector(2 downto 0);
data_out : out std_logic_vector((N-1) downto 0)
);
end component MUX8_Nbit;
----------------------------------
----------------------------------
constant zeros8bit : std_logic_vector (7 downto 0) := (others=>'0');
signal enc10bit, enc10bit0, enc10bit1, enc10bit2, enc10bit3 : std_logic_vector (9 downto 0);
signal enc10bit_x4_r : std_logic_vector (39 downto 0) := (others=>'0');
signal request_cycle_cnt, send_count : std_logic_vector (2 downto 0) := (others=>'0');
signal send_out_trig : std_logic := '0';
signal inp_request_trig, inp_request_trig_out, enc10bitRdy : std_logic;
signal word_cnt : std_logic_vector (1 downto 0) := (others=>'0');
begin
-------------------------------------------------------------------------------------------
-- input handshaking, request cycle 5 CLKs, request is 2 clks wide, 2 bytes at a time
-------------------------------------------------------------------------------------------
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if rst = '1' then
request_cycle_cnt <= (others=>'0');
else
if inp_request_trig = '1' then -- meaning request_cycle_cnt = "100"
request_cycle_cnt <= (others=>'0');
else
request_cycle_cnt <= request_cycle_cnt + 1;
end if;
end if;
end if;
end process;
--
inp_request_trig <= '1' when (request_cycle_cnt = "100") else '0';
--
inp_reques1clk: pulse_pdxx_pwxx generic map(pd=>0,pw=>4) port map(bitCLKx4, inp_request_trig, inp_request_trig_out);
getDataTrig <= inp_request_trig_out;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
send_out_trig <= inp_request_trig; -- slow clock output trigger
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- 8b10b encoding
-------------------------------------------------------------------------------------------
enc8b10bx: enc8b10_wrap
port map (
clk => bitCLKx4,
rst => rst,
dataCode => edataIN(9 downto 8), -- 00"data, 01"eop, 10"sop, 11"comma
dataIN => edataIN(7 downto 0),
dataINrdy => edataINrdy, -- one? CLKx4 after inp_request_trig_out
encDataOut => enc10bit,
encDataOutrdy => enc10bitRdy
);
-------------------------------------------------------------------------------------------
-- sending out 8 bits @ bitCLK
-------------------------------------------------------------------------------------------
process(bitCLKx4)
begin
if bitCLKx4'event and bitCLKx4 = '1' then
if enc10bitRdy = '1' then
word_cnt <= word_cnt + 1;
else
word_cnt <= (others=>'0');
end if;
end if;
end process;
--
process(bitCLKx4)
begin
if bitCLKx4'event and bitCLKx4 = '1' then
if enc10bitRdy = '1' then
if word_cnt = "00" then
enc10bit0 <= enc10bit;
elsif word_cnt = "01" then
enc10bit1 <= enc10bit;
elsif word_cnt = "10" then
enc10bit2 <= enc10bit;
elsif word_cnt = "11" then
enc10bit3 <= enc10bit;
end if;
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- slow clock logic
-------------------------------------------------------------------------------------------
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if send_out_trig = '1' then
send_count <= (others=>'0');
else
send_count <= send_count + 1;
end if;
end if;
end process;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if rst = '1' then
enc10bit_x4_r <= (others=>'0');
elsif send_out_trig = '1' then
enc10bit_x4_r <= enc10bit3 & enc10bit2 & enc10bit1 & enc10bit0;
end if;
end if;
end process;
--
outmux: MUX8_Nbit
generic map (N=>8)
port map (
data0 => enc10bit_x4_r(7 downto 0),
data1 => enc10bit_x4_r(15 downto 8),
data2 => enc10bit_x4_r(23 downto 16),
data3 => enc10bit_x4_r(31 downto 24),
data4 => enc10bit_x4_r(39 downto 32),
data5 => zeros8bit,
data6 => zeros8bit,
data7 => zeros8bit,
sel => send_count,
data_out => EdataOUT
);
--
end Behavioral;
| gpl-3.0 | aae5b8d4249a757549e87c1ac13fe4e8 | 0.479108 | 3.476899 | false | false | false | false |
GustaMagik/RSA_Security_Token | VHDL_code/ver_B/RSA_Security_Token_USB_Version/Keyboard.vhdl | 1 | 6,110 |
--Copyright 2017 Christoffer Mathiesen, Gustav Örtenberg
--Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
--
--1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
--
--2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the
--documentation and/or other materials provided with the distribution.
--
--3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this
--software without specific prior written permission.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS
--BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
--GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
--LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Library IEEE;
Use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_MISC.ALL;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;
Use IEEE.NUMERIC_STD.all;
Use work.all;
Entity Keyboard is
Port ( Row_Input : in STD_LOGIC_VECTOR (3 downto 0);
Col_Output : out STD_LOGIC_VECTOR (3 downto 0) := (others => '1');
Output : out STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
RDY : out STD_LOGIC := '0';
CLK : in STD_LOGIC;
ARESETN : in STD_LOGIC
);
end Keyboard;
--This is a translator for the Keypad v3.0 to hex
--To be connected to the outside world. First it debounces the signal.
--It's to be connected to a 16-button keyboard with pins 4 rows and 4 columns
--To parse the button presses this module first drives all col-pins with high value.
--When a high value is detected on any of the input row-pins it scans over the columns
--one by one (with 500 cycles delay) and detects high values on the row pins. If only one
--button was pressed it's parsed as a vector defined in the case-statement below, and
--the RDY-bit is set high to signal valid input.
--Any parsing besides the accepted ones gives output 0 and the RDY-bit to 0
architecture Behaviour of Keyboard is
signal input_debounced : STD_LOGIC_VECTOR (3 downto 0);
signal counter : unsigned (31 downto 0) := (others => '0');
signal translated : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
Begin
Process (CLK)
Begin
if rising_edge(CLK) then
input_debounced <= Row_Input;
IF ARESETN = '1' THEN
if input_debounced = "0000" and counter = "0000" then
--counter <= "0000";
RDY <= '0';
translated <= (others => '0');
else
if counter = to_unsigned(0, 32) then Col_Output <= "0001";
elsif counter = to_unsigned(500, 32) then --Wait for 500 cycles fom previous step
if input_debounced /= "0000" then
translated <= STD_LOGIC_VECTOR(input_debounced) & "0001";
end if;
Col_Output <= "0010";
elsif counter = to_unsigned(1000, 32) then--Wait for 500 cycles fom previous step
if input_debounced /= "0000" then
translated <= translated or STD_LOGIC_VECTOR(input_debounced) & "0010";
end if;
Col_Output <= "0100";
elsif counter = to_unsigned(1500, 32) then --Wait for 500 cycles fom previous step
if input_debounced /= "0000" then
translated <= translated or STD_LOGIC_VECTOR(input_debounced) & "0100";
end if;
Col_Output <= "1000";
elsif counter = to_unsigned(2000, 32) then --Wait for 500 cycles fom previous step
if input_debounced /= "0000" then
translated <= translated or STD_LOGIC_VECTOR(input_debounced) & "1000";
end if;
Col_Output <= "1111";
else --do nothing
end if;
if counter /= to_unsigned(4000, 32) then --Wait for 2000 cycles fom previous step
counter <= counter + 1;
elsif input_debounced = "0000" then --Wait for release of button
counter <= (others => '0');
--
--Case for translations. In order of magnitude.
-- Input is in the format 7 downto 4 row, 3 downto 0 col.
-- I.e. the vector 0100 0001 is row 3, col 1
Translate: case translated is
when "10000010" => RDY <= '1'; --0
Output <= "0000";
when "00010001" => RDY <= '1'; --1
Output <= "0001";
when "00010010" => RDY <= '1'; --2
Output <= "0010";
when "00010100" => RDY <= '1'; --3
Output <= "0011";
when "00100001" => RDY <= '1'; --4
Output <= "0100";
when "00100010" => RDY <= '1'; --5
Output <= "0101";
when "00100100" => RDY <= '1'; --6
Output <= "0110";
when "01000001" => RDY <= '1'; --7
Output <= "0111";
when "01000010" => RDY <= '1'; --8
Output <= "1000";
when "01000100" => RDY <= '1'; --9
Output <= "1001";
when "00011000" => RDY <= '1'; --A
Output <= "1010";
when "00101000" => RDY <= '1'; --B
Output <= "1011";
when "01001000" => RDY <= '1'; --C
Output <= "1100";
when "10001000" => RDY <= '1'; --D
Output <= "1101";
when "10000100" => RDY <= '1'; --E
Output <= "1110";
when "10000001" => RDY <= '1'; --F
Output <= "1111";
when others => RDY <= '0'; --Others
Output <= "0000";
end case Translate;
end if;
end if;
elsif ARESETN = '0' then
RDY <= '0';
Output <= (others => '0'); --Reset
translated <= (others => '0');
counter <= (others => '0');
END IF;
end if;
end process;
end Behaviour;
| bsd-3-clause | 9ffa3457054701b706a13fea0edda736 | 0.634534 | 3.511494 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/EPROC_IN4.vhd | 1 | 4,275 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/22/2014
--! Module Name: EPROC_IN4
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.ALL;
use work.all;
--! E-link processor, 4bit input
entity EPROC_IN4 is
generic (
do_generate : boolean := true;
includeNoEncodingCase : boolean := true
);
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
ENA : in std_logic;
ENCODING : in std_logic_vector (1 downto 0);
EDATA_IN : in std_logic_vector (3 downto 0);
DATA_OUT : out std_logic_vector (9 downto 0);
DATA_RDY : out std_logic;
busyOut : out std_logic
);
end EPROC_IN4;
architecture Behavioral of EPROC_IN4 is
constant zeros10array : std_logic_vector (9 downto 0) := (others=>'0');
--
signal DATA_OUT_direct,DATA_OUT_8b10b_case,DATA_OUT_HDLC_case,DATA_OUT_s : std_logic_vector (9 downto 0);
signal DATA_RDY_direct,DATA_RDY_8b10b_case,DATA_RDY_HDLC_case,DATA_RDY_sig : std_logic;
---
signal RESTART_sig, rst_case00, rst_case01 : std_logic;
---
begin
gen_enabled: if do_generate = true generate
RESTART_sig <= rst or (not ENA); -- comes from clk40 domain
-------------------------------------------------------------------------------------------
-- ENCODING case "00": direct data, no delimeter...
-------------------------------------------------------------------------------------------
direct_data_enabled: if includeNoEncodingCase = true generate
rst_case00 <= RESTART_sig or (ENCODING(1) or ENCODING(0));
EPROC_IN4_direct_inst: entity work.EPROC_IN4_direct
port map(
bitCLK => bitCLK,
bitCLKx4 => bitCLKx4,
rst => rst_case00,
edataIN => EDATA_IN,
dataOUT => DATA_OUT_direct,
dataOUTrdy => DATA_RDY_direct
);
end generate direct_data_enabled;
--
direct_data_disabled: if includeNoEncodingCase = false generate
DATA_RDY_direct <= '0';
DATA_OUT_direct <= (others=>'0');
end generate direct_data_disabled;
--
-------------------------------------------------------------------------------------------
-- ENCODING case "01": DEC8b10b
-------------------------------------------------------------------------------------------
rst_case01 <= RESTART_sig or (ENCODING(1) or (not ENCODING(0)));
--
EPROC_IN4_DEC8b10b_inst: entity work.EPROC_IN4_DEC8b10b
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case01,
edataIN => EDATA_IN,
dataOUT => DATA_OUT_8b10b_case,
dataOUTrdy => DATA_RDY_8b10b_case,
busyOut => busyOut
);
-------------------------------------------------------------------------------------------
-- ENCODING case "10": HDLC
-------------------------------------------------------------------------------------------
-- TBD
DATA_OUT_HDLC_case <= (others=>'0');
DATA_RDY_HDLC_case <= '0';
-------------------------------------------------------------------------------------------
-- output data/rdy according to the encoding settings
-------------------------------------------------------------------------------------------
DATA_OUT_MUX4_10bit: entity work.MUX4_Nbit
generic map(N=>10)
port map(
data0 => DATA_OUT_direct,
data1 => DATA_OUT_8b10b_case,
data2 => DATA_OUT_HDLC_case,
data3 => zeros10array,
sel => ENCODING,
data_out => DATA_OUT_s
);
DATA_RDY_MUX4: entity work.MUX4
port map(
data0 => DATA_RDY_direct,
data1 => DATA_RDY_8b10b_case,
data2 => DATA_RDY_HDLC_case,
data3 => '0',
sel => ENCODING,
data_out => DATA_RDY_sig
);
DATA_RDY <= DATA_RDY_sig;
DATA_OUT <= DATA_OUT_s;
--------------------
end generate gen_enabled;
--
--
gen_disabled: if do_generate = false generate
DATA_OUT <= (others=>'0');
DATA_RDY <= '0';
busyOut <= '0';
end generate gen_disabled;
end Behavioral;
| gpl-3.0 | 3cde7d722f0969e5c54a3f96704a5ab4 | 0.474152 | 3.779841 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4400/EPROC_IN8.vhd | 1 | 3,937 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/25/2014
--! Module Name: EPROC_IN8
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.ALL;
use work.all;
--! E-link processor, 8bit input
entity EPROC_IN8 is
generic (do_generate : boolean := true);
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
ENA : in std_logic;
ENCODING : in std_logic_vector (1 downto 0);
EDATA_IN : in std_logic_vector (7 downto 0);
DATA_OUT : out std_logic_vector (9 downto 0);
DATA_RDY : out std_logic;
busyOut : out std_logic
);
end EPROC_IN8;
architecture Behavioral of EPROC_IN8 is
constant zeros10array : std_logic_vector (9 downto 0) := (others=>'0');
signal DATA_OUT_direct,DATA_OUT_8b10b_case,DATA_OUT_HDLC_case,DATA_OUT_s : std_logic_vector (9 downto 0);
signal DATA_RDY_direct,DATA_RDY_8b10b_case,DATA_RDY_HDLC_case,DATA_RDY_sig : std_logic;
signal RESTART_sig, rst_case00, rst_case01 : std_logic;
---
begin
gen_enabled: if do_generate = true generate
RESTART_sig <= rst or (not ENA); -- comes from clk40 domain
-------------------------------------------------------------------------------------------
-- ENCODING case "00": direct data, no delimeter...
-------------------------------------------------------------------------------------------
rst_case00 <= RESTART_sig or (ENCODING(1) or ENCODING(0));
--
EPROC_IN8_direct_inst: entity work.EPROC_IN8_direct
port map(
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case00,
edataIN => EDATA_IN,
dataOUT => DATA_OUT_direct,
dataOUTrdy => DATA_RDY_direct
);
-------------------------------------------------------------------------------------------
-- ENCODING case "01": DEC8b10b
-------------------------------------------------------------------------------------------
rst_case01 <= RESTART_sig or (ENCODING(1) or (not ENCODING(0)));
--
EPROC_IN8_DEC8b10b_inst: entity work.EPROC_IN8_DEC8b10b
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case01,
edataIN => EDATA_IN,
dataOUT => DATA_OUT_8b10b_case,
dataOUTrdy => DATA_RDY_8b10b_case,
busyOut => busyOut
);
-------------------------------------------------------------------------------------------
-- ENCODING case "10": HDLC
-------------------------------------------------------------------------------------------
-- TBD
DATA_OUT_HDLC_case <= (others=>'0');
DATA_RDY_HDLC_case <= '0';
-------------------------------------------------------------------------------------------
-- output data/rdy according to the encoding settings
-------------------------------------------------------------------------------------------
DATA_OUT_MUX4_10bit: entity work.MUX4_Nbit
generic map(N=>10)
port map(
data0 => DATA_OUT_direct,
data1 => DATA_OUT_8b10b_case,
data2 => DATA_OUT_HDLC_case,
data3 => zeros10array,
sel => ENCODING,
data_out => DATA_OUT_s
);
DATA_RDY_MUX4: entity work.MUX4
port map(
data0 => DATA_RDY_direct,
data1 => DATA_RDY_8b10b_case,
data2 => DATA_RDY_HDLC_case,
data3 => '0',
sel => ENCODING,
data_out => DATA_RDY_sig
);
DATA_RDY <= DATA_RDY_sig;
DATA_OUT <= DATA_OUT_s;
--------------------
end generate gen_enabled;
--
--
gen_disabled: if do_generate = false generate
DATA_OUT <= (others=>'0');
DATA_RDY <= '0';
busyOut <= '0';
end generate gen_disabled;
end Behavioral;
| gpl-3.0 | 12ac0fd402999a8ff56e020dc668eab0 | 0.457709 | 3.778311 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/EPROC_IN8.vhd | 1 | 4,272 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/25/2014
--! Module Name: EPROC_IN8
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.ALL;
use work.all;
--! E-link processor, 8bit input
entity EPROC_IN8 is
generic (
do_generate : boolean := true;
includeNoEncodingCase : boolean := true
);
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
ENA : in std_logic;
ENCODING : in std_logic_vector (1 downto 0);
EDATA_IN : in std_logic_vector (7 downto 0);
DATA_OUT : out std_logic_vector (9 downto 0);
DATA_RDY : out std_logic;
busyOut : out std_logic
);
end EPROC_IN8;
architecture Behavioral of EPROC_IN8 is
constant zeros10array : std_logic_vector (9 downto 0) := (others=>'0');
signal DATA_OUT_direct,DATA_OUT_8b10b_case,DATA_OUT_HDLC_case,DATA_OUT_s : std_logic_vector (9 downto 0);
signal DATA_RDY_direct,DATA_RDY_8b10b_case,DATA_RDY_HDLC_case,DATA_RDY_sig : std_logic;
signal RESTART_sig, rst_case00, rst_case01 : std_logic;
---
begin
gen_enabled: if do_generate = true generate
RESTART_sig <= rst or (not ENA); -- comes from clk40 domain
-------------------------------------------------------------------------------------------
-- ENCODING case "00": direct data, no delimeter...
-------------------------------------------------------------------------------------------
direct_data_enabled: if includeNoEncodingCase = true generate
rst_case00 <= RESTART_sig or (ENCODING(1) or ENCODING(0));
EPROC_IN8_direct_inst: entity work.EPROC_IN8_direct
port map(
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case00,
edataIN => EDATA_IN,
dataOUT => DATA_OUT_direct,
dataOUTrdy => DATA_RDY_direct
);
end generate direct_data_enabled;
--
direct_data_disabled: if includeNoEncodingCase = false generate
DATA_RDY_direct <= '0';
DATA_OUT_direct <= (others=>'0');
end generate direct_data_disabled;
--
-------------------------------------------------------------------------------------------
-- ENCODING case "01": DEC8b10b
-------------------------------------------------------------------------------------------
rst_case01 <= RESTART_sig or (ENCODING(1) or (not ENCODING(0)));
--
EPROC_IN8_DEC8b10b_inst: entity work.EPROC_IN8_DEC8b10b
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case01,
edataIN => EDATA_IN,
dataOUT => DATA_OUT_8b10b_case,
dataOUTrdy => DATA_RDY_8b10b_case,
busyOut => busyOut
);
-------------------------------------------------------------------------------------------
-- ENCODING case "10": HDLC
-------------------------------------------------------------------------------------------
-- TBD
DATA_OUT_HDLC_case <= (others=>'0');
DATA_RDY_HDLC_case <= '0';
-------------------------------------------------------------------------------------------
-- output data/rdy according to the encoding settings
-------------------------------------------------------------------------------------------
DATA_OUT_MUX4_10bit: entity work.MUX4_Nbit
generic map(N=>10)
port map(
data0 => DATA_OUT_direct,
data1 => DATA_OUT_8b10b_case,
data2 => DATA_OUT_HDLC_case,
data3 => zeros10array,
sel => ENCODING,
data_out => DATA_OUT_s
);
DATA_RDY_MUX4: entity work.MUX4
port map(
data0 => DATA_RDY_direct,
data1 => DATA_RDY_8b10b_case,
data2 => DATA_RDY_HDLC_case,
data3 => '0',
sel => ENCODING,
data_out => DATA_RDY_sig
);
DATA_RDY <= DATA_RDY_sig;
DATA_OUT <= DATA_OUT_s;
--------------------
end generate gen_enabled;
--
--
gen_disabled: if do_generate = false generate
DATA_OUT <= (others=>'0');
DATA_RDY <= '0';
busyOut <= '0';
end generate gen_disabled;
end Behavioral;
| gpl-3.0 | 9724f48b34945073deecf30a6e350644 | 0.475421 | 3.793961 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/sgmii_10_100_1000/ipcore_dir/temac_10_100_1000/example_design/fifo/temac_10_100_1000_rx_client_fifo.vhd | 2 | 37,025 | --------------------------------------------------------------------------------
-- Title : Receiver FIFO with AxiStream interfaces
-- Version : 1.3
-- Project : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : temac_10_100_1000_rx_client_fifo.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2008 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This is the receiver side FIFO for the design example
-- of the Tri-Mode Ethernet MAC core. AxiStream interfaces are used.
--
-- The FIFO is created from 2 Block RAMs of size 2048
-- words of 8-bits per word, giving a total frame memory capacity
-- of 4096 bytes.
--
-- Frame data received from the MAC receiver is written into the
-- FIFO on the rx_mac_aclk. An end-of-frame marker is written to
-- the BRAM parity bit on the last byte of data stored for a frame.
-- This acts as frame deliniation.
--
-- The rx_axis_mac_tvalid, rx_axis_mac_tlast, and rx_axis_mac_tuser signals
-- qualify the frame. A frame which ends with rx_axis_mac_tuser asserted
-- indicates a bad frame and will cause the FIFO write address
-- pointer to be reset to the base address of that frame. In this
-- way the bad frame will be overwritten with the next received
-- frame and is therefore dropped from the FIFO.
--
-- Frames will also be dropped from the FIFO if an overflow occurs.
-- If there is not enough memory capacity in the FIFO to store the
-- whole of an incoming frame, the write address pointer will be
-- reset and the overflow signal asserted.
--
-- When there is at least one complete frame in the FIFO,
-- the 8-bit AxiStream read interface's rx_axis_fifo_tvalid signal will
-- be enabled allowing data to be read from the FIFO.
--
-- The FIFO has been designed to operate with different clocks
-- on the write and read sides. The read clock (user side) should
-- always operate at an equal or faster frequency than the write
-- clock (MAC side).
--
-- The FIFO is designed to work with a minimum frame length of 8
-- bytes.
--
-- The FIFO memory size can be increased by expanding the rd_addr
-- and wr_addr signal widths, to address further BRAMs.
--
-- Requirements :
-- * Minimum frame size of 8 bytes
-- * Spacing between good/bad frame signaling (encoded by
-- rx_axis_mac_tvalid, rx_axis_mac_tlast, rx_axis_mac_tuser), is at least 64
-- clock cycles
-- * Write AxiStream clock is 125MHz downto 1.25MHz
-- * Read AxiStream clock equal to or faster than write clock,
-- and downto 20MHz
--
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library unimacro;
use unimacro.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
-- The entity declaration for the Receiver FIFO
--------------------------------------------------------------------------------
entity temac_10_100_1000_rx_client_fifo is
port (
-- User-side (read-side) AxiStream interface
rx_fifo_aclk : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0) := (others => '0');
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tlast : out std_logic;
rx_axis_fifo_tready : in std_logic;
-- MAC-side (write-side) AxiStream interface
rx_mac_aclk : in std_logic;
rx_mac_resetn : in std_logic;
rx_axis_mac_tdata : in std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : in std_logic;
rx_axis_mac_tlast : in std_logic;
rx_axis_mac_tready : out std_logic;
rx_axis_mac_tuser : in std_logic;
-- FIFO status and overflow indication,
-- synchronous to write-side (rx_mac_aclk) interface
fifo_status : out std_logic_vector(3 downto 0);
fifo_overflow : out std_logic
);
end temac_10_100_1000_rx_client_fifo;
architecture RTL of temac_10_100_1000_rx_client_fifo is
------------------------------------------------------------------------------
-- Component declaration for the synchronisation flip-flop pair
------------------------------------------------------------------------------
component temac_10_100_1000_sync_block
port (
clk : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Define internal signals
------------------------------------------------------------------------------
signal VCC : std_logic;
signal GND_BUS : std_logic_vector(8 downto 0);
signal GND : std_logic_vector(0 downto 0);
-- Encoded read state machine states
type rd_state_typ is (WAIT_s,
QUEUE1_s,
QUEUE2_s,
QUEUE3_s,
QUEUE_SOF_s,
SOF_s,
DATA_s,
EOF_s);
signal rd_state : rd_state_typ;
signal rd_nxt_state : rd_state_typ;
-- Encoded write state machine states
type wr_state_typ is (IDLE_s,
FRAME_s,
GF_s,
BF_s,
OVFLOW_s);
signal wr_state : wr_state_typ;
signal wr_nxt_state : wr_state_typ;
type data_pipe is array (0 to 1) of std_logic_vector(7 downto 0);
type cntl_pipe_long is array(0 to 2) of std_logic;
type cntl_pipe_short is array(0 to 1) of std_logic;
signal wr_en : std_logic;
signal wr_en_u : std_logic;
signal wr_en_u_bram : std_logic_vector(0 downto 0);
signal wr_en_l : std_logic;
signal wr_en_l_bram : std_logic_vector(0 downto 0);
signal wr_addr : unsigned(11 downto 0);
signal wr_addr_inc : std_logic;
signal wr_start_addr_load : std_logic;
signal wr_addr_reload : std_logic;
signal wr_start_addr : unsigned(11 downto 0);
signal wr_eof_data_bram : std_logic_vector(8 downto 0);
signal wr_data_bram : std_logic_vector(7 downto 0);
signal wr_data_pipe : data_pipe;
signal wr_dv_pipe : cntl_pipe_long;
signal wr_gfbf_pipe : cntl_pipe_short;
signal wr_gf : std_logic;
signal wr_bf : std_logic;
signal wr_eof_bram_pipe : cntl_pipe_short;
signal wr_eof_bram : std_logic;
signal frame_in_fifo : std_logic;
signal rd_addr : unsigned(11 downto 0);
signal rd_addr_inc : std_logic;
signal rd_addr_reload : std_logic;
signal rd_eof_data_bram_u : std_logic_vector(8 downto 0);
signal rd_eof_data_bram_l : std_logic_vector(8 downto 0);
signal rd_data_bram_u : std_logic_vector(7 downto 0);
signal rd_data_bram_l : std_logic_vector(7 downto 0);
signal rd_data_pipe_u : std_logic_vector(7 downto 0) := (others => '0');
signal rd_data_pipe_l : std_logic_vector(7 downto 0) := (others => '0');
signal rd_data_pipe : std_logic_vector(7 downto 0) := (others => '0');
signal rd_valid_pipe : std_logic_vector(1 downto 0);
signal rd_eof_bram_u : std_logic_vector(0 downto 0);
signal rd_eof_bram_l : std_logic_vector(0 downto 0);
signal rd_en : std_logic;
signal rd_bram_u : std_logic;
signal rd_bram_u_reg : std_logic;
signal rd_pull_frame : std_logic;
signal rd_eof : std_logic;
signal rd_addr_slv : std_logic_vector(10 downto 0);
signal wr_addr_slv : std_logic_vector(10 downto 0);
signal wr_store_frame_tog : std_logic := '0';
signal rd_store_frame_sync : std_logic;
signal rd_store_frame_delay : std_logic := '0';
signal rd_store_frame : std_logic;
signal rd_frames : unsigned(8 downto 0);
signal wr_fifo_full : std_logic;
signal old_rd_addr : std_logic_vector(1 downto 0);
signal update_addr_tog : std_logic;
signal update_addr_tog_sync : std_logic;
signal update_addr_tog_sync_reg : std_logic;
signal wr_rd_addr : unsigned(11 downto 0);
signal wr_addr_diff_in : unsigned(12 downto 0);
signal wr_addr_diff : unsigned(11 downto 0);
signal wr_fifo_status : unsigned(3 downto 0);
signal rx_axis_fifo_tlast_int : std_logic;
signal doa_l_unused : std_logic_vector(8 downto 0);
signal doa_u_unused : std_logic_vector(8 downto 0);
signal rx_fifo_reset : std_logic;
signal rx_mac_reset : std_logic;
--------------------------------------------------------------------------------
-- Begin FIFO architecture
--------------------------------------------------------------------------------
begin
VCC <= '1';
GND_BUS <= (others => '0');
GND(0) <= GND_BUS(0);
-- invert reset sense as architecture is optimised for active high resets
rx_fifo_reset <= not rx_fifo_resetn;
rx_mac_reset <= not rx_mac_resetn;
------------------------------------------------------------------------------
-- Read state machines and control
------------------------------------------------------------------------------
-- Read state machine.
-- States are WAIT, QUEUE1, QUEUE2, QUEUE3, QUEUE_SOF, SOF, DATA, EOF.
-- Clock state to next state.
clock_rds_p : process(rx_fifo_aclk)
begin
if (rx_fifo_aclk'event and rx_fifo_aclk = '1') then
if rx_fifo_reset = '1' then
rd_state <= WAIT_s;
else
rd_state <= rd_nxt_state;
end if;
end if;
end process clock_rds_p;
rx_axis_fifo_tlast <= rx_axis_fifo_tlast_int;
-- Decode next state, combinatorial.
next_rds_p : process(rd_state, frame_in_fifo, rd_eof, rx_axis_fifo_tready,
rx_axis_fifo_tlast_int, rd_valid_pipe)
begin
case rd_state is
when WAIT_s =>
-- Wait until there is a full frame in the FIFO, then
-- start to load the pipeline.
if frame_in_fifo = '1' and rx_axis_fifo_tlast_int = '0' then
rd_nxt_state <= QUEUE1_s;
else
rd_nxt_state <= WAIT_s;
end if;
-- Load the output pipeline, which takes three clock cycles.
when QUEUE1_s =>
rd_nxt_state <= QUEUE2_s;
when QUEUE2_s =>
rd_nxt_state <= QUEUE3_s;
when QUEUE3_s =>
rd_nxt_state <= QUEUE_SOF_s;
when QUEUE_SOF_s =>
-- The pipeline is full and the frame output starts now.
rd_nxt_state <= DATA_s;
when SOF_s =>
-- A new frame begins immediately following end of last frame.
if rx_axis_fifo_tready = '1' then
rd_nxt_state <= DATA_s;
else
rd_nxt_state <= SOF_s;
end if;
when DATA_s =>
-- Read data from the FIFO. When the EOF marker is detected from
-- the BRAM output, move to the EOF state.
if rx_axis_fifo_tready = '1' and rd_eof = '1' then
rd_nxt_state <= EOF_s;
else
rd_nxt_state <= DATA_s;
end if;
when EOF_s =>
-- Hold in this state until tready is asserted and the EOF
-- marker (tlast) is accepted on interface.
-- If there is another frame in the FIFO, then it will already be
-- queued into the pipeline so so move straight to SOF state.
if rx_axis_fifo_tready = '1' then
if rd_valid_pipe(1) = '1' then
rd_nxt_state <= SOF_s;
else
rd_nxt_state <= WAIT_s;
end if;
else
rd_nxt_state <= EOF_s;
end if;
when others =>
rd_nxt_state <= WAIT_s;
end case;
end process next_rds_p;
-- Detect if frame_in_fifo was high 3 reads ago.
-- This is used to ensure we only treat data in the pipeline as valid if
-- frame_in_fifo goes high at or before the EOF marker of the current frame.
-- It may be that there is valid data (i.e a partial frame has been written)
-- but until the end of that frame we do not know if it is a good frame.
rd_valid_pipe_p : process(rx_fifo_aclk)
begin
if (rx_fifo_aclk'event and rx_fifo_aclk = '1') then
if (rx_axis_fifo_tready = '1') then
rd_valid_pipe <= rd_valid_pipe(0) & frame_in_fifo;
end if;
end if;
end process rd_valid_pipe_p;
-- Decode tlast signal from EOF marker.
rd_ll_decode_p : process(rx_fifo_aclk)
begin
if (rx_fifo_aclk'event and rx_fifo_aclk = '1') then
if rx_fifo_reset = '1' then
rx_axis_fifo_tlast_int <= '0';
elsif rx_axis_fifo_tready = '1' then
-- Assert tlast signal when the EOF marker has been detected, and
-- continue to drive it until it has been accepted on the interface.
case rd_state is
when EOF_s =>
rx_axis_fifo_tlast_int <= '1';
when others =>
rx_axis_fifo_tlast_int <= '0';
end case;
end if;
end if;
end process rd_ll_decode_p;
-- Decode the tvalid output based on state.
rd_ll_src_p : process(rx_fifo_aclk)
begin
if (rx_fifo_aclk'event and rx_fifo_aclk = '1') then
if rx_fifo_reset = '1' then
rx_axis_fifo_tvalid <= '0';
else
case rd_state is
when QUEUE_SOF_s =>
rx_axis_fifo_tvalid <= '1';
when SOF_s =>
rx_axis_fifo_tvalid <= '1';
when DATA_s =>
rx_axis_fifo_tvalid <= '1';
when EOF_s =>
rx_axis_fifo_tvalid <= '1';
when others =>
if rx_axis_fifo_tready = '1' then
rx_axis_fifo_tvalid <= '0';
end if;
end case;
end if;
end if;
end process rd_ll_src_p;
-- Decode internal control signals.
-- rd_en is used to enable the BRAM read and load the output pipeline.
rd_en_p : process(rd_state, rx_axis_fifo_tready)
begin
case rd_state is
when WAIT_s =>
rd_en <= '0';
when QUEUE1_s =>
rd_en <= '1';
when QUEUE2_s =>
rd_en <= '1';
when QUEUE3_s =>
rd_en <= '1';
when QUEUE_SOF_s =>
rd_en <= '1';
when others =>
rd_en <= rx_axis_fifo_tready;
end case;
end process rd_en_p;
-- When the BRAM is being read, enable the read address to be incremented.
rd_addr_inc <= rd_en;
-- When the current frame is done, and if there is no frame in the FIFO, then
-- the FIFO must wait until a new frame is written in. This requires the read
-- address to be moved back to where the new frame will be written. The
-- pipeline is then reloaded using the QUEUE states.
p_rd_addr_reload : process (rx_fifo_aclk)
begin
if rx_fifo_aclk'event and rx_fifo_aclk = '1' then
if rx_fifo_reset = '1' then
rd_addr_reload <= '0';
else
if rd_state = EOF_s and rd_nxt_state = WAIT_s then
rd_addr_reload <= '1';
else
rd_addr_reload <= '0';
end if;
end if;
end if;
end process p_rd_addr_reload;
-- Data is available if there is at least one frame stored in the FIFO.
p_rd_avail : process (rx_fifo_aclk)
begin
if rx_fifo_aclk'event and rx_fifo_aclk = '1' then
if rx_fifo_reset = '1' then
frame_in_fifo <= '0';
else
if rd_frames /= (rd_frames'range => '0') then
frame_in_fifo <= '1';
else
frame_in_fifo <= '0';
end if;
end if;
end if;
end process p_rd_avail;
-- When a frame has been stored we need to synchronize that event to the
-- read clock domain for frame count store.
resync_wr_store_frame_tog : temac_10_100_1000_sync_block
port map (
clk => rx_fifo_aclk,
data_in => wr_store_frame_tog,
data_out => rd_store_frame_sync
);
p_delay_rd_store : process (rx_fifo_aclk)
begin
if rx_fifo_aclk'event and rx_fifo_aclk = '1' then
rd_store_frame_delay <= rd_store_frame_sync;
end if;
end process p_delay_rd_store;
-- Edge detect of the resynchronized frame count. This creates a pulse
-- when a new frame has been stored.
p_sync_rd_store : process (rx_fifo_aclk)
begin
if rx_fifo_aclk'event and rx_fifo_aclk = '1' then
if rx_fifo_reset = '1' then
rd_store_frame <= '0';
else
-- Edge detector
if (rd_store_frame_delay xor rd_store_frame_sync) = '1' then
rd_store_frame <= '1';
else
rd_store_frame <= '0';
end if;
end if;
end if;
end process p_sync_rd_store;
-- This creates a pulse when a new frame has begun to be output.
p_rd_pull_frame : process (rx_fifo_aclk)
begin
if rx_fifo_aclk'event and rx_fifo_aclk = '1' then
if rx_fifo_reset = '1' then
rd_pull_frame <= '0';
else
if rd_state = SOF_s and rd_nxt_state /= SOF_s then
rd_pull_frame <= '1';
elsif rd_state = QUEUE_SOF_s and rd_nxt_state /= QUEUE_SOF_s then
rd_pull_frame <= '1';
else
rd_pull_frame <= '0';
end if;
end if;
end if;
end process p_rd_pull_frame;
-- Up/down counter to monitor the number of frames stored within the FIFO.
-- Note:
-- * increments at the end of a frame write cycle
-- * decrements at the beginning of a frame read cycle
p_rd_frames : process (rx_fifo_aclk)
begin
if rx_fifo_aclk'event and rx_fifo_aclk = '1' then
if rx_fifo_reset = '1' then
rd_frames <= (others => '0');
else
-- A frame is written to the FIFO in this cycle, and no frame is being
-- read out on the same cycle.
if rd_store_frame = '1' and rd_pull_frame = '0' then
rd_frames <= rd_frames + 1;
-- A frame is being read out on this cycle and no frame is being
-- written on the same cycle.
elsif rd_store_frame = '0' and rd_pull_frame = '1' then
rd_frames <= rd_frames - 1;
end if;
end if;
end if;
end process p_rd_frames;
------------------------------------------------------------------------------
-- Write state machines and control
------------------------------------------------------------------------------
-- Write state machine.
-- States are IDLE, FRAME, GF, BF, OVFLOW.
-- Clock state to next state.
clock_wrs_p : process(rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
if rx_mac_reset = '1' then
wr_state <= IDLE_s;
else
wr_state <= wr_nxt_state;
end if;
end if;
end process clock_wrs_p;
-- Decode next state, combinatorial.
next_wrs_p : process(wr_state, wr_dv_pipe(1), wr_gf, wr_bf, wr_fifo_full)
begin
case wr_state is
when IDLE_s =>
-- There is data in incoming pipeline when dv_pipe(1) goes high.
if wr_dv_pipe(1) = '1' then
wr_nxt_state <= FRAME_s;
else
wr_nxt_state <= IDLE_s;
end if;
when FRAME_s =>
-- If FIFO is full then go to overflow state.
-- If the good or bad flag is detected, then the end of the frame
-- has been reached and the gf or bf state is visited before idle.
-- Otherwise remain in frame state while data is written to FIFO.
if wr_fifo_full = '1' then
wr_nxt_state <= OVFLOW_s;
elsif wr_gf = '1' then
wr_nxt_state <= GF_s;
elsif wr_bf = '1' then
wr_nxt_state <= BF_s;
else
wr_nxt_state <= FRAME_s;
end if;
when GF_s =>
-- Return to idle and wait for next frame.
wr_nxt_state <= IDLE_s;
when BF_s =>
-- Return to idle and wait for next frame.
wr_nxt_state <= IDLE_s;
when OVFLOW_s =>
-- Wait until the good or bad flag received.
if wr_gf = '1' or wr_bf = '1' then
wr_nxt_state <= IDLE_s;
else
wr_nxt_state <= OVFLOW_s;
end if;
when others =>
wr_nxt_state <= IDLE_s;
end case;
end process next_wrs_p;
-- Decode control signals, combinatorial.
-- wr_en is used to enable the BRAM write and loading of the input pipeline.
wr_en <= wr_dv_pipe(2) when wr_state = FRAME_s else '0';
-- The upper and lower signals are used to distinguish between the upper and
-- lower BRAMs.
wr_en_l <= wr_en and not(wr_addr(11));
wr_en_u <= wr_en and wr_addr(11);
wr_en_l_bram(0) <= wr_en_l;
wr_en_u_bram(0) <= wr_en_u;
-- Increment the write address when we are receiving valid frame data.
wr_addr_inc <= wr_dv_pipe(2) when wr_state = FRAME_s else '0';
-- If the FIFO overflows or a frame is to be dropped, we need to move the
-- write address back to the start of the frame. This allows the data to be
-- overwritten.
wr_addr_reload <= '1' when wr_state = BF_s or wr_state = OVFLOW_s else '0';
-- The start address is saved when in the idle state.
wr_start_addr_load <= '1' when wr_state = IDLE_s else '0';
-- We need to know when a frame is stored, in order to increment the count of
-- frames stored in the FIFO.
p_wr_store_tog : process (rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
if wr_state = GF_s then
wr_store_frame_tog <= not wr_store_frame_tog;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- Address counters
------------------------------------------------------------------------------
-- Write address is incremented when data is being written into the FIFO.
wr_addr_p : process(rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
if rx_mac_reset = '1' then
wr_addr <= (others => '0');
else
if wr_addr_reload = '1' then
wr_addr <= wr_start_addr;
elsif wr_addr_inc = '1' then
wr_addr <= wr_addr + 1;
end if;
end if;
end if;
end process wr_addr_p;
-- Store the start address.
wr_staddr_p : process(rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
if rx_mac_reset = '1' then
wr_start_addr <= (others => '0');
else
if wr_start_addr_load = '1' then
wr_start_addr <= wr_addr;
end if;
end if;
end if;
end process wr_staddr_p;
-- Read address is incremented when data is being read from the FIFO.
rd_addr_p : process(rx_fifo_aclk)
begin
if (rx_fifo_aclk'event and rx_fifo_aclk = '1') then
if rx_fifo_reset = '1' then
rd_addr <= (others => '0');
else
if rd_addr_reload = '1' then
rd_addr <= rd_addr - 3;
elsif rd_addr_inc = '1' then
rd_addr <= rd_addr + 1;
end if;
end if;
end if;
end process rd_addr_p;
-- Which BRAM is read from is dependant on the upper bit of the address
-- space. This needs to be registered to give the correct timing.
rd_bram_p : process(rx_fifo_aclk)
begin
if (rx_fifo_aclk'event and rx_fifo_aclk = '1') then
if rx_fifo_reset = '1' then
rd_bram_u <= '0';
rd_bram_u_reg <= '0';
elsif rd_addr_inc = '1' then
rd_bram_u <= rd_addr(11);
rd_bram_u_reg <= rd_bram_u;
end if;
end if;
end process rd_bram_p;
------------------------------------------------------------------------------
-- Data pipelines
------------------------------------------------------------------------------
-- Register data inputs to BRAM.
-- No resets to allow for SRL16 target.
reg_din_p : process(rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
wr_data_pipe(0) <= rx_axis_mac_tdata;
wr_data_pipe(1) <= wr_data_pipe(0);
wr_data_bram <= wr_data_pipe(1);
end if;
end process reg_din_p;
-- The valid input enables BRAM write and is a condition for other signals.
reg_dv_p : process(rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
wr_dv_pipe(0) <= rx_axis_mac_tvalid;
wr_dv_pipe(1) <= wr_dv_pipe(0);
wr_dv_pipe(2) <= wr_dv_pipe(1);
end if;
end process reg_dv_p;
-- End of frame flag set when tlast and tvalid are asserted together.
reg_eof_p : process(rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
wr_eof_bram_pipe(0) <= rx_axis_mac_tlast;
wr_eof_bram_pipe(1) <= wr_eof_bram_pipe(0);
wr_eof_bram <= wr_eof_bram_pipe(1) and wr_dv_pipe(1);
end if;
end process reg_eof_p;
-- Upon arrival of EOF flag, the frame is good if tuser signal
-- is low, and bad if tuser signal is high.
reg_gf_p : process(rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
wr_gfbf_pipe(0) <= rx_axis_mac_tuser;
wr_gfbf_pipe(1) <= wr_gfbf_pipe(0);
wr_gf <= (not wr_gfbf_pipe(1)) and wr_eof_bram_pipe(1) and wr_dv_pipe(1);
wr_bf <= wr_gfbf_pipe(1) and wr_eof_bram_pipe(1) and wr_dv_pipe(1);
end if;
end process reg_gf_p;
-- The MAC's RX path cannot be helpd off, so the tready signal is always high.
reg_ready_p : process(rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
if (rx_mac_reset = '1') then
rx_axis_mac_tready <= '0';
else
rx_axis_mac_tready <= '1';
end if;
end if;
end process reg_ready_p;
-- Register data outputs from BRAM.
-- No resets to allow for SRL16 target.
reg_dout_p : process(rx_fifo_aclk)
begin
if (rx_fifo_aclk'event and rx_fifo_aclk = '1') then
if rd_en = '1' then
rd_data_pipe_u <= rd_data_bram_u;
rd_data_pipe_l <= rd_data_bram_l;
if rd_bram_u_reg = '1' then
rd_data_pipe <= rd_data_pipe_u;
else
rd_data_pipe <= rd_data_pipe_l;
end if;
rx_axis_fifo_tdata <= rd_data_pipe;
end if;
end if;
end process reg_dout_p;
reg_eofout_p : process(rx_fifo_aclk)
begin
if (rx_fifo_aclk'event and rx_fifo_aclk = '1') then
if rd_en = '1' then
if rd_bram_u = '1' then
rd_eof <= rd_eof_bram_u(0);
else
rd_eof <= rd_eof_bram_l(0);
end if;
end if;
end if;
end process reg_eofout_p;
------------------------------------------------------------------------------
-- Overflow functionality
------------------------------------------------------------------------------
-- to minimise the number of read address updates the bottom 6 bits of the
-- read address are not passed across and the write domain will only sample
-- them when bits 5 and 4 of the read address transition from 01 to 10.
-- Since this is for full detection this just means that if the read stops
-- the write will hit full up to 64 locations early
-- need to use two bits and look for an increment transition as reload can cause
-- a decrement on this boundary (decrement is only by 3 so above bit 2 should be safe)
p_rd_addr_tog : process (rx_fifo_aclk)
begin
if rx_fifo_aclk'event and rx_fifo_aclk = '1' then
if rx_fifo_reset = '1' then
old_rd_addr <= (others => '0');
update_addr_tog <= '0';
else
old_rd_addr <= std_logic_vector(rd_addr(5 downto 4));
if rd_addr(5 downto 4) = "10" and old_rd_addr = "01" then
update_addr_tog <= not update_addr_tog;
end if;
end if;
end if;
end process p_rd_addr_tog;
sync_rd_addr_tog: temac_10_100_1000_sync_block
port map (
clk => rx_mac_aclk,
data_in => update_addr_tog,
data_out => update_addr_tog_sync
);
-- Obtain the difference between write and read pointers.
p_sample_addr : process (rx_mac_aclk)
begin
if rx_mac_aclk'event and rx_mac_aclk = '1' then
if rx_mac_reset = '1' then
update_addr_tog_sync_reg <= '0';
wr_rd_addr <= (others => '0');
else
update_addr_tog_sync_reg <= update_addr_tog_sync;
if update_addr_tog_sync_reg /= update_addr_tog_sync then
wr_rd_addr <= rd_addr(11 downto 6) & "000000";
end if;
end if;
end if;
end process p_sample_addr;
wr_addr_diff_in <= ('0' & wr_rd_addr) - ('0' & wr_addr);
-- Obtain the difference between write and read pointers.
p_addr_diff : process (rx_mac_aclk)
begin
if rx_mac_aclk'event and rx_mac_aclk = '1' then
if rx_mac_reset = '1' then
wr_addr_diff <= (others => '0');
else
wr_addr_diff <= wr_addr_diff_in(11 downto 0);
end if;
end if;
end process p_addr_diff;
-- Detect when the FIFO is full.
-- The FIFO is considered to be full if the write address pointer is
-- within 0 to 3 of the read address pointer.
p_wr_full : process (rx_mac_aclk)
begin
if rx_mac_aclk'event and rx_mac_aclk = '1' then
if rx_mac_reset = '1' then
wr_fifo_full <= '0';
else
if wr_addr_diff(11 downto 4) = 0
and wr_addr_diff(3 downto 2) /= "00" then
wr_fifo_full <= '1';
else
wr_fifo_full <= '0';
end if;
end if;
end if;
end process p_wr_full;
-- Decode the overflow indicator output.
fifo_overflow <= '1' when wr_state = OVFLOW_s else '0';
------------------------------------------------------------------------------
-- FIFO status signals
------------------------------------------------------------------------------
-- The FIFO status is four bits which represents the occupancy of the FIFO
-- in sixteenths. To generate this signal we therefore only need to compare
-- the 4 most significant bits of the write address pointer with the 4 most
-- significant bits of the read address pointer.
p_wr_fifo_status : process (rx_mac_aclk)
begin
if rx_mac_aclk'event and rx_mac_aclk = '1' then
if rx_mac_reset = '1' then
wr_fifo_status <= "0000";
else
if wr_addr_diff = (wr_addr_diff'range => '0') then
wr_fifo_status <= "0000";
else
wr_fifo_status(3) <= not wr_addr_diff(11);
wr_fifo_status(2) <= not wr_addr_diff(10);
wr_fifo_status(1) <= not wr_addr_diff(9);
wr_fifo_status(0) <= not wr_addr_diff(8);
end if;
end if;
end if;
end process p_wr_fifo_status;
fifo_status <= std_logic_vector(wr_fifo_status);
wr_addr_slv <= std_logic_vector(wr_addr(10 downto 0));
rd_addr_slv <= std_logic_vector(rd_addr(10 downto 0));
------------------------------------------------------------------------------
-- Instantiate FIFO block memory
------------------------------------------------------------------------------
wr_eof_data_bram(8) <= wr_eof_bram;
wr_eof_data_bram(7 downto 0) <= wr_data_bram;
-- Block RAM for lower address space (rx_addr(11) = '0')
rd_eof_bram_l(0) <= rd_eof_data_bram_l(8);
rd_data_bram_l <= rd_eof_data_bram_l(7 downto 0);
ramgen_l : BRAM_TDP_MACRO
generic map (
DEVICE => "7SERIES",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9,
READ_WIDTH_A => 9,
READ_WIDTH_B => 9)
port map (
DOA => doa_l_unused,
DOB => rd_eof_data_bram_l,
ADDRA => wr_addr_slv,
ADDRB => rd_addr_slv,
CLKA => rx_mac_aclk,
CLKB => rx_fifo_aclk,
DIA => wr_eof_data_bram,
DIB => GND_BUS(8 downto 0),
ENA => VCC,
ENB => rd_en,
REGCEA => VCC,
REGCEB => VCC,
RSTA => rx_mac_reset,
RSTB => rx_fifo_reset,
WEA => wr_en_l_bram,
WEB => GND
);
-- Block RAM for lower address space (rx_addr(11) = '0')
rd_eof_bram_u(0) <= rd_eof_data_bram_u(8);
rd_data_bram_u <= rd_eof_data_bram_u(7 downto 0);
ramgen_u : BRAM_TDP_MACRO
generic map (
DEVICE => "7SERIES",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9,
READ_WIDTH_A => 9,
READ_WIDTH_B => 9)
port map (
DOA => doa_u_unused,
DOB => rd_eof_data_bram_u,
ADDRA => wr_addr_slv,
ADDRB => rd_addr_slv,
CLKA => rx_mac_aclk,
CLKB => rx_fifo_aclk,
DIA => wr_eof_data_bram,
DIB => GND_BUS(8 downto 0),
ENA => VCC,
ENB => rd_en,
REGCEA => VCC,
REGCEB => VCC,
RSTA => rx_mac_reset,
RSTB => rx_fifo_reset,
WEA => wr_en_u_bram,
WEB => GND
);
end RTL;
| gpl-3.0 | 96d57c9dc50c7898227ebad5aa744bb5 | 0.524619 | 3.749367 | false | false | false | false |
gyurco/ZX_Spectrum-128K_MIST | tzxplayer.vhd | 1 | 19,585 | ---------------------------------------------------------------------------------
-- TZX player
-- by György Szombathelyi
-- basic idea for the structure based on c1530 tap player by darfpga
--
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
USE IEEE.NUMERIC_STD.ALL;
entity tzxplayer is
generic (
TZX_MS : integer := 64000; -- CE periods for one milliseconds
-- Default: ZX Spectrum
NORMAL_PILOT_LEN : integer := 2168;
NORMAL_SYNC1_LEN : integer := 667;
NORMAL_SYNC2_LEN : integer := 735;
NORMAL_ZERO_LEN : integer := 855;
NORMAL_ONE_LEN : integer := 1710;
HEADER_PILOT_PULSES : integer := 8063; -- this is the header length
NORMAL_PILOT_PULSES : integer := 3223 -- this is the non-header length
-- Amstrad CPC
--NORMAL_PILOT_LEN : integer := 2000;
--NORMAL_SYNC1_LEN : integer := 855;
--NORMAL_SYNC2_LEN : integer := 855;
--NORMAL_ZERO_LEN : integer := 855;
--NORMAL_ONE_LEN : integer := 1710;
--HEADER_PILOT_PULSES : integer := 4095; -- no difference between header and data pilot lengths
--NORMAL_PILOT_PULSES : integer := 4095
);
port(
clk : in std_logic;
ce : in std_logic;
restart_tape : in std_logic;
host_tap_in : in unsigned(7 downto 0); -- 8bits fifo input
tzx_req : buffer std_logic; -- request for new byte (edge trigger)
tzx_ack : in std_logic; -- new data available
loop_start : out std_logic; -- active for one clock if a loop starts
loop_next : out std_logic; -- active for one clock at the next iteration
stop : out std_logic; -- tape should be stopped
stop48k : out std_logic; -- tape should be stopped in 48k mode
cass_read : out std_logic; -- tape read signal
cass_motor : in std_logic; -- 1 = tape motor is powered
cass_running : out std_logic -- tape is running
);
end tzxplayer;
architecture struct of tzxplayer is
signal tap_fifo_do : unsigned( 7 downto 0);
signal tick_cnt : unsigned(16 downto 0);
signal wave_cnt : unsigned(23 downto 0);
signal wave_period : std_logic;
signal wave_inverted : std_logic;
signal skip_bytes : std_logic;
signal playing : std_logic; -- 1 = tap or wav file is playing
signal bit_cnt : unsigned(2 downto 0);
type tzx_state_t is (
TZX_HEADER,
TZX_NEWBLOCK,
TZX_LOOP_START,
TZX_LOOP_END,
TZX_PAUSE,
TZX_PAUSE2,
TZX_STOP48K,
TZX_HWTYPE,
TZX_TEXT,
TZX_MESSAGE,
TZX_ARCHIVE_INFO,
TZX_CUSTOM_INFO,
TZX_GLUE,
TZX_TONE,
TZX_PULSES,
TZX_DATA,
TZX_NORMAL,
TZX_TURBO,
TZX_PLAY_TONE,
TZX_PLAY_SYNC1,
TZX_PLAY_SYNC2,
TZX_PLAY_TAPBLOCK,
TZX_PLAY_TAPBLOCK2,
TZX_PLAY_TAPBLOCK3,
TZX_PLAY_TAPBLOCK4,
TZX_DIRECT,
TZX_DIRECT2,
TZX_DIRECT3);
signal tzx_state: tzx_state_t;
signal tzx_offset : unsigned( 7 downto 0);
signal pause_len : unsigned(15 downto 0);
signal ms_counter : unsigned(15 downto 0);
signal pilot_l : unsigned(15 downto 0);
signal sync1_l : unsigned(15 downto 0);
signal sync2_l : unsigned(15 downto 0);
signal zero_l : unsigned(15 downto 0);
signal one_l : unsigned(15 downto 0);
signal pilot_pulses : unsigned(15 downto 0);
signal last_byte_bits : unsigned( 3 downto 0);
signal data_len : unsigned(23 downto 0);
signal pulse_len : unsigned(15 downto 0);
signal end_period : std_logic;
signal cass_motor_D : std_logic;
signal motor_counter : unsigned(21 downto 0);
signal loop_iter : unsigned(15 downto 0);
signal data_len_dword : unsigned(31 downto 0);
begin
cass_read <= wave_period;
cass_running <= playing;
tap_fifo_do <= host_tap_in;
process(clk)
begin
if rising_edge(clk) then
if restart_tape = '1' then
tzx_offset <= (others => '0');
tzx_state <= TZX_HEADER;
pulse_len <= (others => '0');
motor_counter <= (others => '0');
wave_period <= '0';
playing <= '0';
tzx_req <= tzx_ack;
loop_start <= '0';
loop_next <= '0';
loop_iter <= (others => '0');
wave_inverted <= '0';
else
-- simulate tape motor momentum
-- don't change the playing state if the motor is switched in 50 ms
-- Opera Soft K17 protection needs this!
cass_motor_D <= cass_motor;
if cass_motor_D /= cass_motor then
motor_counter <= to_unsigned(50*TZX_MS, motor_counter'length);
elsif motor_counter /= 0 then
if ce = '1' then motor_counter <= motor_counter - 1; end if;
else
playing <= cass_motor;
end if;
if playing = '0' then
--cass_read <= '1';
end if;
if pulse_len /= 0 then
if ce = '1' then
tick_cnt <= tick_cnt + 3500;
if tick_cnt >= (TZX_MS - 3500) then
tick_cnt <= tick_cnt + 3500 - TZX_MS;
wave_cnt <= wave_cnt + 1;
if wave_cnt = pulse_len - 1 then
wave_cnt <= (others => '0');
if wave_period = end_period then
pulse_len <= (others => '0');
else
wave_period <= not wave_period;
end if;
end if;
end if;
end if;
else
wave_cnt <= (others => '0');
tick_cnt <= (others => '0');
end if;
loop_start <= '0';
loop_next <= '0';
stop <= '0';
stop48k <= '0';
if playing = '1' and pulse_len = 0 and tzx_req = tzx_ack then
tzx_req <= not tzx_ack; -- default request for new data
case tzx_state is
when TZX_HEADER =>
wave_period <= '1';
wave_inverted <= '0';
tzx_offset <= tzx_offset + 1;
if tzx_offset = x"0A" then -- skip 9 bytes, offset lags 1
tzx_state <= TZX_NEWBLOCK;
end if;
when TZX_NEWBLOCK =>
tzx_offset <= (others=>'0');
ms_counter <= (others=>'0');
case tap_fifo_do is
when x"10" => tzx_state <= TZX_NORMAL;
when x"11" => tzx_state <= TZX_TURBO;
when x"12" => tzx_state <= TZX_TONE;
when x"13" => tzx_state <= TZX_PULSES;
when x"14" => tzx_state <= TZX_DATA;
when x"15" => tzx_state <= TZX_DIRECT;
when x"18" => null; -- CSW recording (not implemented)
when x"19" => null; -- Generalized data block (not implemented)
when x"20" => tzx_state <= TZX_PAUSE;
when x"21" => tzx_state <= TZX_TEXT; -- Group start
when x"22" => null; -- Group end
when x"23" => null; -- Jump to block (not implemented)
when x"24" => tzx_state <= TZX_LOOP_START;
when x"25" => tzx_state <= TZX_LOOP_END;
when x"26" => null; -- Call sequence (not implemented)
when x"27" => null; -- Return from sequence (not implemented)
when x"28" => null; -- Select block (not implemented)
when x"2A" => tzx_state <= TZX_STOP48K;
when x"2B" => null; -- Set signal level (not implemented)
when x"30" => tzx_state <= TZX_TEXT;
when x"31" => tzx_state <= TZX_MESSAGE;
when x"32" => tzx_state <= TZX_ARCHIVE_INFO;
when x"33" => tzx_state <= TZX_HWTYPE;
when x"35" => tzx_state <= TZX_CUSTOM_INFO;
when x"5A" => tzx_state <= TZX_GLUE;
when others => null;
end case;
when TZX_LOOP_START =>
tzx_offset <= tzx_offset + 1;
if tzx_offset = x"00" then loop_iter( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"01" then
loop_iter(15 downto 8) <= tap_fifo_do;
tzx_state <= TZX_NEWBLOCK;
loop_start <= '1';
end if;
when TZX_LOOP_END =>
if loop_iter > 1 then
loop_iter <= loop_iter - 1;
loop_next <= '1';
else
tzx_req <= tzx_ack; -- don't request new byte
end if;
tzx_state <= TZX_NEWBLOCK;
when TZX_PAUSE =>
tzx_offset <= tzx_offset + 1;
if tzx_offset = x"00" then
pause_len(7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"01" then
pause_len(15 downto 8) <= tap_fifo_do;
tzx_state <= TZX_PAUSE2;
if pause_len(7 downto 0) = 0 and tap_fifo_do = 0 then
stop <= '1';
end if;
end if;
when TZX_PAUSE2 =>
tzx_req <= tzx_ack; -- don't request new byte
if ms_counter /= 0 then
if ce = '1' then
ms_counter <= ms_counter - 1;
-- Set pulse level to low after 1 ms
if ms_counter = 1 then
wave_inverted <= '0';
wave_period <= '0';
end_period <= '0';
end if;
end if;
elsif pause_len /= 0 then
pause_len <= pause_len - 1;
ms_counter <= to_unsigned(TZX_MS, ms_counter'length);
else
tzx_state <= TZX_NEWBLOCK;
end if;
when TZX_STOP48K =>
tzx_offset <= tzx_offset + 1;
if tzx_offset = x"03" then
stop48k <= '1';
tzx_state <= TZX_NEWBLOCK;
end if;
when TZX_HWTYPE =>
tzx_offset <= tzx_offset + 1;
-- 0, 1-3, 1-3, ...
if tzx_offset = x"00" then data_len( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"03" then
if data_len(7 downto 0) = x"01" then
tzx_state <= TZX_NEWBLOCK;
else
data_len(7 downto 0) <= data_len(7 downto 0) - 1;
tzx_offset <= x"01";
end if;
end if;
when TZX_MESSAGE =>
-- skip display time, then then same as TEXT DESRCRIPTION
tzx_state <= TZX_TEXT;
when TZX_TEXT =>
tzx_offset <= tzx_offset + 1;
if tzx_offset = x"00" then data_len( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = data_len(7 downto 0) then
tzx_state <= TZX_NEWBLOCK;
end if;
when TZX_ARCHIVE_INFO =>
tzx_offset <= tzx_offset + 1;
if tzx_offset = x"00" then data_len( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"01" then data_len(15 downto 8) <= tap_fifo_do;
else
tzx_offset <= x"02";
data_len <= data_len - 1;
if data_len = 1 then
tzx_state <= TZX_NEWBLOCK;
end if;
end if;
when TZX_CUSTOM_INFO =>
tzx_offset <= tzx_offset + 1;
if tzx_offset = x"10" then data_len_dword( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"11" then data_len_dword(15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"12" then data_len_dword(23 downto 16) <= tap_fifo_do;
elsif tzx_offset = x"13" then data_len_dword(31 downto 24) <= tap_fifo_do;
elsif tzx_offset = x"14" then
tzx_offset <= x"14";
if data_len_dword = 1 then
tzx_state <= TZX_NEWBLOCK;
else
data_len_dword <= data_len_dword - 1;
end if;
end if;
when TZX_GLUE =>
tzx_offset <= tzx_offset + 1;
if tzx_offset = x"08" then
tzx_state <= TZX_NEWBLOCK;
end if;
when TZX_TONE =>
tzx_offset <= tzx_offset + 1;
-- 0, 1, 2, 3, 4, 4, 4, ...
if tzx_offset = x"00" then pilot_l( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"01" then pilot_l(15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"02" then pilot_pulses( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"03" then
tzx_req <= tzx_ack; -- don't request new byte
pilot_pulses(15 downto 8) <= tap_fifo_do;
else
tzx_offset <= x"04";
tzx_req <= tzx_ack; -- don't request new byte
if pilot_pulses = 0 then
tzx_req <= not tzx_ack; -- default request for new data
tzx_state <= TZX_NEWBLOCK;
else
pilot_pulses <= pilot_pulses - 1;
if wave_inverted = '0' then
wave_period <= not wave_period;
end_period <= not wave_period; -- request pulse
else
wave_inverted <= '0';
end_period <= wave_period;
end if;
pulse_len <= pilot_l;
end if;
end if;
when TZX_PULSES =>
tzx_offset <= tzx_offset + 1;
-- 0, 1-2+3, 1-2+3, ...
if tzx_offset = x"00" then data_len( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"01" then one_l( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"02" then
tzx_req <= tzx_ack; -- don't request new byte
if wave_inverted = '0' then
wave_period <= not wave_period;
end_period <= not wave_period; -- request pulse
else
wave_inverted <= '0';
end_period <= wave_period;
end if;
pulse_len <= tap_fifo_do & one_l( 7 downto 0);
elsif tzx_offset = x"03" then
if data_len(7 downto 0) = x"01" then
tzx_state <= TZX_NEWBLOCK;
else
data_len(7 downto 0) <= data_len(7 downto 0) - 1;
tzx_offset <= x"01";
end if;
end if;
when TZX_DATA =>
tzx_offset <= tzx_offset + 1;
if tzx_offset = x"00" then zero_l ( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"01" then zero_l (15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"02" then one_l ( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"03" then one_l (15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"04" then last_byte_bits <= tap_fifo_do(3 downto 0);
elsif tzx_offset = x"05" then pause_len( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"06" then pause_len(15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"07" then data_len ( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"08" then data_len (15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"09" then
data_len (23 downto 16) <= tap_fifo_do;
tzx_state <= TZX_PLAY_TAPBLOCK;
end if;
when TZX_NORMAL =>
tzx_offset <= tzx_offset + 1;
if tzx_offset = x"00" then pause_len( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"01" then pause_len(15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"02" then data_len ( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"03" then
data_len(15 downto 8) <= tap_fifo_do;
data_len(23 downto 16) <= (others => '0');
elsif tzx_offset = x"04" then
-- this is the first data byte to determine if it's a header or data block (on Speccy)
tzx_req <= tzx_ack; -- don't request new byte
pilot_l <= to_unsigned(NORMAL_PILOT_LEN, pilot_l'length);
sync1_l <= to_unsigned(NORMAL_SYNC1_LEN, sync1_l'length);
sync2_l <= to_unsigned(NORMAL_SYNC2_LEN, sync2_l'length);
zero_l <= to_unsigned(NORMAL_ZERO_LEN, zero_l'length);
one_l <= to_unsigned(NORMAL_ONE_LEN, one_l'length);
if tap_fifo_do = 0 then
pilot_pulses <= to_unsigned(HEADER_PILOT_PULSES, pilot_pulses'length);
else
pilot_pulses <= to_unsigned(NORMAL_PILOT_PULSES, pilot_pulses'length);
end if;
last_byte_bits <= "1000";
tzx_state <= TZX_PLAY_TONE;
end if;
when TZX_TURBO =>
tzx_offset <= tzx_offset + 1;
if tzx_offset = x"00" then pilot_l( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"01" then pilot_l(15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"02" then sync1_l( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"03" then sync1_l(15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"04" then sync2_l( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"05" then sync2_l(15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"06" then zero_l ( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"07" then zero_l (15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"08" then one_l ( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"09" then one_l (15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"0A" then pilot_pulses( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"0B" then pilot_pulses(15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"0C" then last_byte_bits <= tap_fifo_do(3 downto 0);
elsif tzx_offset = x"0D" then pause_len( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"0E" then pause_len(15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"0F" then data_len ( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"10" then data_len (15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"11" then
data_len (23 downto 16) <= tap_fifo_do;
tzx_state <= TZX_PLAY_TONE;
end if;
when TZX_PLAY_TONE =>
tzx_req <= tzx_ack; -- don't request new byte
if wave_inverted = '0' then
wave_period <= not wave_period;
end_period <= not wave_period; -- request pulse
else
end_period <= wave_period;
wave_inverted <= '0';
end if;
pulse_len <= pilot_l;
if pilot_pulses = 1 then
tzx_state <= TZX_PLAY_SYNC1;
else
pilot_pulses <= pilot_pulses - 1;
end if;
when TZX_PLAY_SYNC1 =>
tzx_req <= tzx_ack; -- don't request new byte
wave_period <= not wave_period;
end_period <= not wave_period; -- request pulse
pulse_len <= sync1_l;
tzx_state <= TZX_PLAY_SYNC2;
when TZX_PLAY_SYNC2 =>
tzx_req <= tzx_ack; -- don't request new byte
wave_period <= not wave_period;
end_period <= not wave_period; -- request pulse
pulse_len <= sync2_l;
tzx_state <= TZX_PLAY_TAPBLOCK;
when TZX_PLAY_TAPBLOCK =>
tzx_req <= tzx_ack; -- don't request new byte
bit_cnt <= "111";
tzx_state <= TZX_PLAY_TAPBLOCK2;
when TZX_PLAY_TAPBLOCK2 =>
tzx_req <= tzx_ack; -- don't request new byte
bit_cnt <= bit_cnt - 1;
if bit_cnt = "000" or (data_len = 1 and ((bit_cnt = (8 - last_byte_bits)) or (last_byte_bits = 0))) then
data_len <= data_len - 1;
tzx_state <= TZX_PLAY_TAPBLOCK3;
end if;
if wave_inverted = '0' then
wave_period <= not wave_period;
end_period <= wave_period; -- request full period
else
end_period <= not wave_period;
wave_inverted <= '0';
end if;
if tap_fifo_do(to_integer(bit_cnt)) = '0' then
pulse_len <= zero_l;
else
pulse_len <= one_l;
end if;
when TZX_PLAY_TAPBLOCK3 =>
if data_len = 0 then
wave_period <= not wave_period;
wave_inverted <= '1';
tzx_state <= TZX_PAUSE2;
else
tzx_state <= TZX_PLAY_TAPBLOCK4;
end if;
when TZX_PLAY_TAPBLOCK4 =>
tzx_req <= tzx_ack; -- don't request new byte
tzx_state <= TZX_PLAY_TAPBLOCK2;
when TZX_DIRECT =>
tzx_offset <= tzx_offset + 1;
if tzx_offset = x"00" then zero_l ( 7 downto 0) <= tap_fifo_do; -- here this is used for one bit, too
elsif tzx_offset = x"01" then zero_l (15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"02" then pause_len ( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"03" then pause_len (15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"04" then last_byte_bits <= tap_fifo_do(3 downto 0);
elsif tzx_offset = x"05" then data_len( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"06" then data_len(15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"07" then
data_len(23 downto 16) <= tap_fifo_do;
tzx_state <= TZX_DIRECT2;
bit_cnt <= "111";
end if;
when TZX_DIRECT2 =>
tzx_req <= tzx_ack; -- don't request new byte
bit_cnt <= bit_cnt - 1;
if bit_cnt = "000" or (data_len = 1 and ((bit_cnt = (8 - last_byte_bits)) or (last_byte_bits = 0))) then
data_len <= data_len - 1;
tzx_state <= TZX_DIRECT3;
end if;
pulse_len <= zero_l;
wave_period <= tap_fifo_do(to_integer(bit_cnt));
end_period <= tap_fifo_do(to_integer(bit_cnt));
when TZX_DIRECT3 =>
if data_len = 0 then
wave_inverted <= '0';
tzx_state <= TZX_PAUSE2;
else
tzx_state <= TZX_DIRECT2;
end if;
when others => null;
end case;
end if; -- play tzx
end if;
end if; -- clk
end process;
end struct;
| gpl-2.0 | a0ce4e1ee83186f8cd53a23ed77590d4 | 0.564696 | 2.963232 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/Multirate/interpolator.vhd | 1 | 3,337 | --------------------------------------------------------------------------------------------------
-- Interpolator
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- PACKAGE
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.dsp_pkg.all;
package interpolator_pkg is
component interpolator is
generic( h : coefficient_array);
port( clk_high : in std_logic;
clk_low : in std_logic;
rst : in std_logic;
sig_low : in sig;
sig_high : out sig);
end component;
end package;
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dsp_pkg.all;
use work.muxer_pkg.all;
use work.multichannel_fir_filter_pkg.all;
entity interpolator is
generic( h : coefficient_array);
port( clk_high : in std_logic;
clk_low : in std_logic;
rst : in std_logic;
sig_low : in sig;
sig_high : out sig);
end interpolator;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture behave of interpolator is
constant H0 : coefficient_array(1 to (h'length+1)/2)
:= slice_coefficient_array(h, 2, 1, 1);
constant H1 : coefficient_array(1 to (h'length+1)/2)
:= slice_coefficient_array(h, 2, 2, 1);
signal filtered1 : fir_sig;
signal filtered2 : fir_sig;
signal combined : fir_sig;
begin
--Low pass the input signal using the multichannel approach
low_pass : multichannel_fir_filter
generic map(h0 => H0,
h1 => H1,
INIT_SEL => b"10")
port map( clk => clk_low,
clk_2x => clk_high,
rst => rst,
x1 => sig_low,
x2 => sig_low,
y1 => filtered1,
y2 => filtered2);
--Mux the poly-phase filter results into one signal
--NOTE: If this design were to ever support interpolation factor > 2, the mux would need to
--select the input signals in descending order
mux_sigs : muxer
generic map(INIT_SEL => std_logic_vector(rotate_left(unsigned'(b"01"), h'length)))
port map(clk => clk_low,
clk_2x => clk_high,
rst => rst,
sig1 => std_logic_vector(filtered1),
sig2 => std_logic_vector(filtered2),
fir_sig(sigs) => combined);
sig_high <= combined(30 downto 15);
end behave;
| mit | d1c2f188fbbf23ea5be7430fa7d1cc93 | 0.396764 | 4.864431 | false | false | false | false |
adelapie/noekeon | tb_round_f.vhd | 2 | 4,118 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_round_f IS
END tb_round_f;
ARCHITECTURE behavior OF tb_round_f IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT round_f
PORT(
enc : in std_logic;
rc_in : IN std_logic_vector(31 downto 0);
a_0_in : IN std_logic_vector(31 downto 0);
a_1_in : IN std_logic_vector(31 downto 0);
a_2_in : IN std_logic_vector(31 downto 0);
a_3_in : IN std_logic_vector(31 downto 0);
k_0_in : IN std_logic_vector(31 downto 0);
k_1_in : IN std_logic_vector(31 downto 0);
k_2_in : IN std_logic_vector(31 downto 0);
k_3_in : IN std_logic_vector(31 downto 0);
a_0_out : OUT std_logic_vector(31 downto 0);
a_1_out : OUT std_logic_vector(31 downto 0);
a_2_out : OUT std_logic_vector(31 downto 0);
a_3_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal enc : std_logic := '0';
signal rc_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal a_3_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_0_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal k_3_in : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal a_0_out : std_logic_vector(31 downto 0);
signal a_1_out : std_logic_vector(31 downto 0);
signal a_2_out : std_logic_vector(31 downto 0);
signal a_3_out : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: round_f PORT MAP (
enc => enc,
rc_in => rc_in,
a_0_in => a_0_in,
a_1_in => a_1_in,
a_2_in => a_2_in,
a_3_in => a_3_in,
k_0_in => k_0_in,
k_1_in => k_1_in,
k_2_in => k_2_in,
k_3_in => k_3_in,
a_0_out => a_0_out,
a_1_out => a_1_out,
a_2_out => a_2_out,
a_3_out => a_3_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
rc_in <= X"00000080";
a_0_in <= X"61396c93";
a_1_in <= X"637434b8";
a_2_in <= X"fc6559a9";
a_3_in <= X"5b643f2c";
k_0_in <= X"1c1c1c1c";
k_1_in <= X"1c1c1c1c";
k_2_in <= X"1c1c1c1c";
k_3_in <= X"1c1c1c1c";
wait for clk_period;
assert a_0_out = X"febb00d0"
report "ROUND ERROR (a_0)" severity FAILURE;
assert a_1_out = X"074ee42e"
report "ROUND ERROR (a_1)" severity FAILURE;
assert a_2_out = X"dde647ab"
report "ROUND ERROR (a_2)" severity FAILURE;
assert a_3_out = X"3207ef78"
report "ROUND ERROR (a_3)" severity FAILURE;
wait;
end process;
END;
| gpl-3.0 | 3f5c0dffbeaf39a5c220202a922cb771 | 0.567023 | 2.977585 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/readout/artReadout.vhd | 1 | 8,525 | ----------------------------------------------------------------------------------
-- Company: NTU ATHENS - BNL
-- Engineer: Paris Moschovakos
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Paris Moschovakos
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 2.6.2017
-- Design Name:
-- Module Name: art.vhd - Behavioral
-- Project Name:
-- Target Devices: Artix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2017.1
--
-- Changelog:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity artReadout is
Generic( is_mmfe8 : std_logic;
artEnabled : std_logic);
Port (
clk : in std_logic;
clk_art : in std_logic;
trigger : in std_logic;
artData : in std_logic_vector(8 downto 1);
vmmArtData125 : out std_logic_vector(5 downto 0);
vmmArtReady : out std_logic
);
end artReadout;
architecture Behavioral of artReadout is
signal enableReadout125 : std_logic := '0';
signal enableReadout125_160 : std_logic := '0';
signal enableReadout160 : std_logic := '0';
signal vmmArtReady160 : std_logic := '0';
signal vmmArtReady160_125 : std_logic := '0';
signal vmmArtReady125 : std_logic := '0';
signal artData_i : std_logic := '0';
signal artDataBuffed : std_logic := '0';
signal vmmArtData160_125 : std_logic_vector(5 downto 0) := ( others => '0' );
signal vmmArtData : unsigned(5 downto 0) := ( others => '0' );
signal artCounter : unsigned(3 downto 0) := ( others => '0' );
type stateType is (S1, S2, S3, S4);
signal state : stateType := S1;
signal stateReadout : stateType := S1;
-- Debugging
signal probe0_out : std_logic_vector(127 downto 0);
signal debug1 : std_logic_vector(1 downto 0) := b"00";
signal debug2 : std_logic_vector(1 downto 0) := b"00";
-- ASYNC_REG attributes
attribute ASYNC_REG : string;
attribute ASYNC_REG of vmmArtReady160 : signal is "TRUE";
attribute ASYNC_REG of vmmArtReady160_125 : signal is "TRUE";
attribute ASYNC_REG of enableReadout125 : signal is "TRUE";
attribute ASYNC_REG of enableReadout125_160 : signal is "TRUE";
attribute ASYNC_REG of artData_i : signal is "TRUE";
attribute ASYNC_REG of artData : signal is "TRUE";
attribute ASYNC_REG of vmmArtData160_125 : signal is "TRUE";
attribute ASYNC_REG of vmmArtData125 : signal is "TRUE";
-------------------------------------------------------------------
-- Keep signals for ILA
-----------------------------------------------------------------
-- attribute mark_debug : string;
-- attribute mark_debug of artData : signal is "true";
-- attribute mark_debug of trigger : signal is "true";
-- attribute mark_debug of artCounter : signal is "true";
-- attribute mark_debug of vmmArtReady160 : signal is "true";
-- attribute mark_debug of enableReadout160 : signal is "true";
-- attribute mark_debug of artDataBuffed : signal is "true";
-- attribute mark_debug of debug1 : signal is "true";
-- attribute mark_debug of debug2 : signal is "true";
-- attribute mark_debug of vmmArtReady125 : signal is "true";
component ila_art
port(
clk : in std_logic;
probe0 : in std_logic_vector(127 downto 0)
);
end component;
function reverse_any_vector (a: in std_logic_vector)
return std_logic_vector is
variable result: std_logic_vector(a'RANGE);
alias aa: std_logic_vector(a'REVERSE_RANGE) is a;
begin
for i in aa'RANGE loop
result(i) := aa(i);
end loop;
return result;
end; -- function reverse_any_vector
begin
Proc: process(clk)
begin
if (rising_edge(clk)) then
case state is
when S1 =>
debug1 <= b"00";
if trigger = '1' and artEnabled = '1' then
state <= S2;
end if;
when S2 =>
debug1 <= b"01";
enableReadout125 <= '1';
if vmmArtReady125 = '1' then
state <= S3;
end if;
--start reading out ART data
--when finish move to S3
when S3 =>
debug1 <= b"10";
enableReadout125 <= '0';
state <= S1;
when others =>
enableReadout125 <= '0';
-- reset
end case;
end if;
end process;
readoutProc: process(clk_art)
begin
if rising_edge(clk_art) then
if (enableReadout160 = '1') then
case stateReadout is
when S1 =>
--reset
debug2 <= b"00";
artCounter <= ( others => '0' );
vmmArtReady160 <= '0';
if artDataBuffed = '1' then
stateReadout <= S2;
end if;
when S2 =>
debug2 <= b"01";
if artCounter /= 7 then
artCounter <= artCounter + 1;
vmmArtData <= shift_left(vmmArtData, 1);
vmmArtData(0) <= artDataBuffed;
else
stateReadout <= S3;
end if;
when S3 =>
debug2 <= b"10";
vmmArtReady160 <= '1';
artCounter <= artCounter - 1;
if artCounter = 0 then
stateReadout <= S1;
end if;
when others =>
artCounter <= ( others => '0' );
vmmArtReady160 <= '0';
end case;
end if;
end if;
end process;
-- synchronize Art data
data_pipe: process(clk_art)
begin
if(rising_edge(clk_art))then
artData_i <= artData(1);
artDataBuffed <= artData_i;
end if;
end process;
to125Synchronizer: process(clk) --125
begin
if rising_edge(clk) then
vmmArtReady160_125 <= vmmArtReady160;
vmmArtReady125 <= vmmArtReady160_125;
vmmArtData160_125 <= std_logic_vector(vmmArtData);
vmmArtData125 <= vmmArtData160_125;
end if;
end process;
to160Synchronizer: process(clk_art) --40
begin
if rising_edge (clk_art) then
enableReadout125_160 <= enableReadout125;
enableReadout160 <= enableReadout125_160;
end if;
end process;
vmmArtReady <= vmmArtReady125;
--ilaArt: ila_art
--port map
-- (
-- clk => clk_art,
-- probe0 => probe0_out
-- );
probe0_out(0) <= artData(1);
probe0_out(1) <= trigger;
probe0_out(5 downto 2) <= std_logic_vector(artCounter); --4
probe0_out(6) <= enableReadout160;
probe0_out(12 downto 7) <= std_logic_vector(vmmArtData);
probe0_out(13) <= vmmArtReady125;
probe0_out(15 downto 14) <= debug1;
probe0_out(17 downto 16) <= debug2;
probe0_out(18) <= artDataBuffed;
probe0_out(19) <= vmmArtReady160;
probe0_out(127 downto 20) <= (others => '0');
end Behavioral; | gpl-3.0 | 40b8036cb6b9284436ee3bd4e1187547 | 0.520938 | 4.158537 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/MMFE8_1VMM/sources_1/readout/packet_formation.vhd | 1 | 7,971 | ----------------------------------------------------------------------------------
-- Company: NTU ATHNENS - BNL
-- Engineer: Paris Moschovakos
--
-- Create Date: 18.04.2016 13:00:21
-- Design Name:
-- Module Name: packet_formation.vhd - Behavioral
-- Project Name: MMFE8
-- Target Devices: Arix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2016.2
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 1.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity packet_formation is
Port(
clk_200 : in std_logic;
newCycle : in std_logic;
eventCounter: in std_logic_vector(31 downto 0);
trigVmmRo : out std_logic;
vmmWord : in std_logic_vector(63 downto 0);
vmmWordReady: in std_logic;
vmmEventDone: in std_logic;
packLen : out integer;
dataout : out std_logic_vector(63 downto 0);
wrenable : out std_logic;
end_packet : out std_logic;
udp_busy : in std_logic;
tr_hold : out std_logic
);
end packet_formation;
architecture Behavioral of packet_formation is
signal header : std_logic_vector(63 downto 0) := ( others => '0' );
signal vmmId : std_logic_vector(7 downto 0) := x"01"; --( others => '0' );
signal globBcid : std_logic_vector(15 downto 0) := x"FFFF"; --( others => '0' );
signal globBcid_i : std_logic_vector(15 downto 0);
signal precCnt : std_logic_vector(7 downto 0) := x"00"; --( others => '0' );
signal eventCounter_i : std_logic_vector(31 downto 0) := ( others => '0' );
signal wait_Cnt : integer := 0;
signal packetCounter : integer := 0;
signal daqFIFO_wr_en : std_logic := '0';
signal daqFIFO_wr_en_i : std_logic := '0';
signal daqFIFO_din : std_logic_vector(63 downto 0) := ( others => '0' );
signal daqFIFO_din_i : std_logic_vector(63 downto 0) := ( others => '0' );
signal triggerVmmReadout_i : std_logic := '0';
signal vmmWord_i : std_logic_vector(63 downto 0) := ( others => '0' );
signal packLen_i : integer := 0;
signal packLen_cnt : integer := 0;
signal end_packet_int : std_logic := '0';
type stateType is (waitingForNewCycle, S2, captureEventID, setEventID, sendHeaderStep1, sendHeaderStep2, triggerVmmReadout,
waitForData, sendVmmDataStep1, sendVmmDataStep2, formTrailer, sendTrailer, packetDone, isTriggerOff);
signal state : stateType;
-----------------------------------------------------------------
begin
packetCaptureProc: process(clk_200, newCycle, vmmEventDone)
begin
-- Upon a signal from trigger capture the current global BCID
if rising_edge(clk_200) then
case state is
when waitingForNewCycle =>
triggerVmmReadout_i <= '0';
if newCycle = '1' then
tr_hold <= '1'; -- Prevent new triggers
daqFIFO_wr_en <= '0';
packLen_cnt <= 0;
packetCounter <= packetCounter + 1; -- Signal to count packets for debugging
state <= S2;
else
tr_hold <= '0';
end if;
when S2 => -- wait for the header elements to be formed
state <= captureEventID;
when captureEventID => -- Form Header
header(63 downto 0) <= eventCounter & precCnt & globBcid & vmmId;
-- 32 & 8 & 16 & 8
state <= setEventID;
when setEventID =>
daqFIFO_wr_en <= '0';
daqFIFO_din <= header;
state <= sendHeaderStep1;
when sendHeaderStep1 =>
daqFIFO_wr_en <= '1';
packLen_cnt <= packLen_cnt + 1;
state <= sendHeaderStep2;
when sendHeaderStep2 =>
daqFIFO_wr_en <= '0';
state <= triggerVmmReadout;
when triggerVmmReadout => -- Creates an 125ns pulse to trigger the readout
if wait_Cnt /= 25 then
wait_Cnt <= wait_cnt + 1;
triggerVmmReadout_i <= '1';
else
triggerVmmReadout_i <= '0';
wait_Cnt <= 0;
state <= waitForData;
end if;
when waitForData =>
if vmmWordReady = '1' then
daqFIFO_din <= vmmWord_i;
daqFIFO_wr_en <= '0';
state <= sendVmmDataStep1;
elsif vmmEventDone = '1' then
daqFIFO_wr_en <= '0';
daqFIFO_din <= x"FFFFFFFF" & std_logic_vector(to_unsigned(packetCounter, 16)) & x"FF" & std_logic_vector(to_unsigned(packLen_cnt, 8)); -- 8 bit
state <= sendTrailer;
end if;
when sendVmmDataStep1 =>
daqFIFO_wr_en <= '1';
packLen_cnt <= packLen_cnt + 1;
state <= sendVmmDataStep2;
when sendVmmDataStep2 =>
daqFIFO_wr_en <= '0';
state <= formTrailer;
when formTrailer =>
if (vmmEventDone = '1') then
daqFIFO_wr_en <= '0';
daqFIFO_din <= x"FFFFFFFF" & std_logic_vector(to_unsigned(packetCounter, 16)) & x"FF" & std_logic_vector(to_unsigned(packLen_cnt, 8)); -- 8 bit
state <= sendTrailer;
elsif (vmmEventDone = '0' and vmmWordReady = '0') then
state <= waitForData;
else -- (vmmWordReady = '1') then
state <= formTrailer;
end if;
when sendTrailer =>
if udp_busy /= '1' then
daqFIFO_wr_en <= '0';
packLen_i <= packLen_cnt;
state <= packetDone;
end if;
when packetDone => -- Wait for FIFO2UDP
if wait_Cnt /= 10 then
wait_Cnt <= wait_cnt + 1;
end_packet_int <= '1';
daqFIFO_wr_en <= '0';
else
wait_Cnt <= 0;
state <= isTriggerOff;
end if;
when isTriggerOff => -- Wait for whatever ongoing trigger pulse to go to 0
end_packet_int <= '0';
tr_hold <= '0'; -- Allow new triggers
if newCycle /= '1' then
state <= waitingForNewCycle;
end if;
when others =>
state <= waitingForNewCycle;
end case;
end if;
end process;
eventCounter_i <= eventCounter;
globBcid_i <= globBcid;
daqFIFO_wr_en_i <= daqFIFO_wr_en;
vmmWord_i <= vmmWord;
dataout <= daqFIFO_din;
wrenable <= daqFIFO_wr_en_i;
packLen <= packLen_i;
end_packet <= end_packet_int;
trigVmmRo <= triggerVmmReadout_i;
end Behavioral; | gpl-3.0 | 2e1cd7b3e393bff9a4cf8d8ff50a6ce9 | 0.451135 | 4.664131 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/Reduce/reduce.vhd | 1 | 10,762 | ----------------------------------------------------------------------------------------------------
-- Reduce
----------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
----------------------------------------------------------------------------------------------------
-- PACKAGE
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package reduce_pkg is
component reduce_and is
port( data : in std_logic_vector;
result: out std_logic);
end component;
component reduce_or is
port( data : in std_logic_vector;
result: out std_logic);
end component;
component reduce_xor is
port( data : in std_logic_vector;
result: out std_logic);
end component;
component reduce_nand is
port( data : in std_logic_vector;
result: out std_logic);
end component;
component reduce_nor is
port( data : in std_logic_vector;
result: out std_logic);
end component;
component reduce_xnor is
port( data : in std_logic_vector;
result: out std_logic);
end component;
end package;
----------------------------------------------------------------------------------------------------
-- ENTITY
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.reduce_pkg.all;
--Reduce module
--This module takes a bit vector and reduces it to a single value using a single gate type. This
--module can take any sized input vector to reduce to a single-bit output value. This module was
--implemented to optimize for latency. Only the and/or/xor gates are supported. This module
--provides the foundation for all the reduce operations presented in the reduce package.
entity reduce is
generic( gate : string);
port( data : in std_logic_vector;
result: out std_logic);
end reduce;
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.reduce_pkg.all;
--Reduce-and takes an input vector of any length and returns a value based on and'ing all the bits
--together. An and gate returns a 1 when both inputs are 1, similarly a reduce-and gate will return
--a 1 when all inputs are 1, 0 otherwise.
entity reduce_and is
port( data : in std_logic_vector;
result: out std_logic);
end reduce_and;
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.reduce_pkg.all;
--Reduce-or takes an input vector of any length and returns a value based on or'ing all the bits
--together. An or gate returns a 0 when neither input is 1, similarly a reduce-or gate will return
--a 0 when none of the inputs are 1, 1 otherwise.
entity reduce_or is
port( data : in std_logic_vector;
result: out std_logic);
end reduce_or;
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.reduce_pkg.all;
--Reduce-xor takes an input vector of any length and returns a value based on xor'ing all the bits
--together. This particular reductions is useful when you want to know when a bit-vector has an
--even or odd number of 1's in the vector. This reduce operation returns a 1 when there are an odd
--number of 1's in the vector, 0 otherwise.
entity reduce_xor is
port( data : in std_logic_vector;
result: out std_logic);
end reduce_xor;
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.reduce_pkg.all;
--Reduce-nand takes an input vector of any length and returns a value based on and'ing all the bits
--together. An nand gate returns a 1 when both inputs are 0, similarly a reduce-nand gate will
--return a 1 when all inputs are 0, 1 otherwise.
entity reduce_nand is
port( data : in std_logic_vector;
result: out std_logic);
end reduce_nand;
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.reduce_pkg.all;
--Reduce-nor takes an input vector of any length and returns a value based on nor'ing all the bits
--together. An nor gate returns a 1 when neither input is 0, similarly a reduce-or gate will return
--a 1 when none of the inputs are 1, 1 otherwise.
entity reduce_nor is
port( data : in std_logic_vector;
result: out std_logic);
end reduce_nor;
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.reduce_pkg.all;
--Reduce-xnor is technically not a legitimate reduction operation. This is because the xnor is not
--an operation that satisfies the associative property. Therefore this operation is the invert of
--result of the reduce-xor operation. This reduce operation returns a 1 when there are an even
--number of 1's in the vector, 0 otherwise.
entity reduce_xnor is
port( data : in std_logic_vector;
result: out std_logic);
end reduce_xnor;
----------------------------------------------------------------------------------------------------
-- ARCHITECTURE
----------------------------------------------------------------------------------------------------
architecture recursiveTree of reduce is
constant dlength : positive := data'length;
begin
base_case : if(dlength = 1) generate
result <= data(data'low);
end generate;
recurse_case : if(dlength > 1) generate
constant halflen : positive := dlength/2;
signal lower_half : std_logic_vector(1 to halflen);
signal upper_half : std_logic_vector(1 to dlength - halflen);
signal lower_result: std_logic;
signal upper_result: std_logic;
begin
--Separate the input vector into lower and upper halves
lower_copy: for tap in lower_half'range generate
lower_half(tap) <= data(tap-1+data'low);
end generate;
upper_copy: for tap in upper_half'range generate
upper_half(tap) <= data(tap-1+data'low+halflen);
end generate;
--Reduce the lower and upper halves recursively
reduce_lower : entity work.reduce
generic map(gate => gate)
port map( data => lower_half,
result=> lower_result);
reduce_higher : entity work.reduce
generic map(gate => gate)
port map( data => upper_half,
result=> upper_result);
--Reduce the results of the lower and upper halves
reduce_and : if(gate = "and") generate
result <= lower_result and upper_result;
end generate;
reduce_or : if(gate = "or") generate
result <= lower_result or upper_result;
end generate;
reduce_xor : if(gate = "xor") generate
result <= lower_result xor upper_result;
end generate;
end generate;
end recursiveTree;
----------------------------------------------------------------------------------------------------
architecture implement of reduce_and is
component reduce is
generic( gate : string);
port( data : in std_logic_vector;
result: out std_logic);
end component;
begin
reduce_imp : reduce
generic map(gate => "and")
port map( data => data,
result=> result);
end implement;
----------------------------------------------------------------------------------------------------
architecture implement of reduce_or is
component reduce is
generic( gate : string);
port( data : in std_logic_vector;
result: out std_logic);
end component;
begin
reduce_imp : reduce
generic map(gate => "or")
port map( data => data,
result=> result);
end implement;
----------------------------------------------------------------------------------------------------
architecture implement of reduce_xor is
component reduce is
generic( gate : string);
port( data : in std_logic_vector;
result: out std_logic);
end component;
begin
reduce_imp : reduce
generic map(gate => "xor")
port map( data => data,
result=> result);
end implement;
----------------------------------------------------------------------------------------------------
architecture implement of reduce_nand is
signal inverted : std_logic;
component reduce is
generic( gate : string);
port( data : in std_logic_vector;
result: out std_logic);
end component;
begin
reduce_imp : reduce
generic map(gate => "or")
port map( data => data,
result=> inverted);
result <= not inverted;
end implement;
----------------------------------------------------------------------------------------------------
architecture implement of reduce_nor is
signal inverted : std_logic;
component reduce is
generic( gate : string);
port( data : in std_logic_vector;
result: out std_logic);
end component;
begin
reduce_imp : reduce
generic map(gate => "and")
port map( data => data,
result=> inverted);
result <= not inverted;
end implement;
----------------------------------------------------------------------------------------------------
architecture implement of reduce_xnor is
signal inverted : std_logic;
component reduce is
generic( gate : string);
port( data : in std_logic_vector;
result: out std_logic);
end component;
begin
reduce_imp : reduce
generic map(gate => "xor")
port map( data => data,
result=> inverted);
result <= not inverted;
end implement;
| mit | b5dc37124292c831417af360018f2126 | 0.501208 | 4.755634 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/Elink2FIFO.vhd | 2 | 8,311 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 17/08/2015
--! Module Name: Elink2FIFO
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.all;
--! consists of 1 E-path
entity Elink2FIFO is
generic (
InputDataRate : integer := 80; -- 80 / 160 / 320 / 640 MHz
elinkEncoding : std_logic_vector (1 downto 0); -- 00-direct data / 01-8b10b encoding / 10-HDLC encoding
serialized_input : boolean := true
);
port (
clk40 : in std_logic;
clk80 : in std_logic;
clk160 : in std_logic;
clk320 : in std_logic;
rst : in std_logic;
fifo_flush : in std_logic;
------
DATA1bitIN : in std_logic := '0';
elink2bit : in std_logic_vector (1 downto 0) := (others=>'0'); -- 2 bits @ clk40, can interface 2-bit of GBT frame
elink4bit : in std_logic_vector (3 downto 0) := (others=>'0'); -- 4 bits @ clk40, can interface 4-bit of GBT frame
elink8bit : in std_logic_vector (7 downto 0) := (others=>'0'); -- 8 bits @ clk40, can interface 8-bit of GBT frame
-- 640 Mbps e-link can't come in as a serial input yet (additional clock is needed)
elink16bit : in std_logic_vector (15 downto 0) := (others=>'0'); -- 16 bits @ clk40, can interface 16-bit of GBT frame
------
efifoRclk : in std_logic;
efifoRe : in std_logic;
efifoHF : out std_logic; -- half-full flag: 1 KByte block is ready to be read
efifoDout : out std_logic_vector (15 downto 0)
------
);
end Elink2FIFO;
architecture Behavioral of Elink2FIFO is
--
constant maxClen : std_logic_vector (11 downto 0) := (others => '0'); -- no limit on packet size here
signal DATA2bitIN, shreg2bit : std_logic_vector (1 downto 0) := (others => '0');
signal DATA4bitIN, shreg4bit : std_logic_vector (3 downto 0) := (others => '0');
signal DATA8bitIN, shreg8bit : std_logic_vector (7 downto 0) := (others => '0');
signal DATA_OUT : std_logic_vector(9 downto 0);
signal DATA_RDY, FIFO_RESET_STATE, almost_full, BWORD_RDY : std_logic;
signal BWORD : std_logic_vector(15 downto 0);
----
begin
------------------------------------------------------------
-- E-PATH case 80 MHz
------------------------------------------------------------
InputDataRate80: if InputDataRate = 80 generate
--
actual_elink_case: if serialized_input = true generate
process(clk80)
begin
if rising_edge(clk80) then
shreg2bit <= DATA1bitIN & shreg2bit(1);
end if;
end process;
--
process(clk40)
begin
if rising_edge(clk40) then
DATA2bitIN <= shreg2bit;
end if;
end process;
end generate actual_elink_case;
--
--
GBT_frame_case: if serialized_input = false generate
process(clk40)
begin
if rising_edge(clk40) then
DATA2bitIN <= elink2bit;
end if;
end process;
end generate GBT_frame_case;
--
EPROC_IN2bit: entity work.EPROC_IN2
port map (
bitCLK => clk40,
bitCLKx2 => clk80,
bitCLKx4 => clk160,
rst => rst,
ENA => '1', -- always enabled here
swap_inputbits => '0', -- when '1', the input bits will be swapped
ENCODING => elinkEncoding, -- 00-direct data / 01-8b10b encoding / 10-HDLC encoding
EDATA_IN => DATA2bitIN, -- @ 40MHz
DATA_OUT => DATA_OUT, -- 10-bit data out
DATA_RDY => DATA_RDY,
busyOut => open -- not in use here
);
end generate InputDataRate80;
------------------------------------------------------------
-- E-PATH case 160 MHz
------------------------------------------------------------
InputDataRate160: if InputDataRate = 160 generate
--
actual_elink_case: if serialized_input = true generate
process(clk160)
begin
if rising_edge(clk160) then
shreg4bit <= DATA1bitIN & shreg4bit(3 downto 1);
end if;
end process;
--
process(clk40)
begin
if rising_edge(clk40) then
DATA4bitIN <= shreg4bit;
end if;
end process;
end generate actual_elink_case;
--
--
GBT_frame_case: if serialized_input = false generate
process(clk40)
begin
if rising_edge(clk40) then
DATA4bitIN <= elink4bit;
end if;
end process;
end generate GBT_frame_case;
--
EPROC_IN4bit: entity work.EPROC_IN4
port map (
bitCLK => clk40,
bitCLKx2 => clk80,
bitCLKx4 => clk160,
rst => rst,
ENA => '1', -- always enabled here
ENCODING => elinkEncoding, -- 00-direct data / 01-8b10b encoding / 10-HDLC encoding
EDATA_IN => DATA4bitIN, -- @ 40MHz
DATA_OUT => DATA_OUT, -- 10-bit data out
DATA_RDY => DATA_RDY,
busyOut => open -- not in use here
);
end generate InputDataRate160;
------------------------------------------------------------
-- E-PATH case 320 MHz
------------------------------------------------------------
InputDataRate320: if InputDataRate = 320 generate
--
actual_elink_case: if serialized_input = true generate
process(clk320)
begin
if rising_edge(clk320) then
shreg8bit <= DATA1bitIN & shreg8bit(7 downto 1);
end if;
end process;
--
process(clk40)
begin
if rising_edge(clk40) then
DATA8bitIN <= shreg8bit;
end if;
end process;
end generate actual_elink_case;
--
--
GBT_frame_case: if serialized_input = false generate
process(clk40)
begin
if rising_edge(clk40) then
DATA8bitIN <= elink8bit;
end if;
end process;
end generate GBT_frame_case;
--
EPROC_IN8bit: entity work.EPROC_IN8
port map (
bitCLK => clk40,
bitCLKx2 => clk80,
bitCLKx4 => clk160,
rst => rst,
ENA => '1', -- always enabled here
ENCODING => elinkEncoding, -- 00-direct data / 01-8b10b encoding / 10-HDLC encoding
EDATA_IN => DATA8bitIN, -- @ 40MHz
DATA_OUT => DATA_OUT, -- 10-bit data out
DATA_RDY => DATA_RDY,
busyOut => open -- not in use here
);
end generate InputDataRate320;
------------------------------------------------------------
-- E-PATH case 640 MHz
------------------------------------------------------------
InputDataRate640: if InputDataRate = 640 generate
--
EPROC_IN16bit: entity work.EPROC_IN16
port map (
bitCLK => clk40,
bitCLKx2 => clk80,
bitCLKx4 => clk160,
rst => rst,
ENA => '1', -- always enabled here
ENCODING => elinkEncoding, -- 00-direct data / 01-8b10b encoding / 10-HDLC encoding
EDATA_IN => elink16bit, -- @ 40MHz
DATA_OUT => DATA_OUT, -- 10-bit data out
DATA_RDY => DATA_RDY,
busyOut => open -- not in use here
);
--
end generate InputDataRate640;
------------------------------------------------------------
-- EPATH FIFO DRIVER
------------------------------------------------------------
efd: entity work.EPROC_FIFO_DRIVER
generic map(
GBTid => 0, -- no use
egroupID => 0, -- no use
epathID => 0 -- no use
)
port map (
clk40 => clk40,
clk160 => clk160,
rst => rst,
encoding => "10", -- 00-direct data / 01-8b10b encoding / 10-HDLC encoding
maxCLEN => "000", -- 000-not limit on packet length
DIN => DATA_OUT, -- 10-bit data in
DIN_RDY => DATA_RDY,
xoff => almost_full,
timeCntIn => x"00", -- not in use
TimeoutEnaIn => '0', -- not in use
wordOUT => BWORD, -- 16-bit block word
wordOUT_RDY => BWORD_RDY
);
------------------------------------------------------------
-- EPATH FIFOs
------------------------------------------------------------
efw: entity work.EPATH_FIFO_WRAP
port map (
rst => rst,
fifoFlush => fifo_flush,
wr_clk => clk160,
rd_clk => efifoRclk,
din => BWORD,
wr_en => BWORD_RDY,
rd_en => efifoRe,
dout => efifoDout,
almost_full => almost_full,
prog_full => efifoHF -- Half-Full - output: 1Kbyte block is ready
);
end Behavioral;
| gpl-3.0 | 32d07e59dde5fef9c2b082f1900777f5 | 0.5299 | 3.527589 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/configuration/vmm_config_block.vhd | 1 | 8,476 | ----------------------------------------------------------------------------------------
-- Company: NTU Athens - BNL
-- Engineer: Christos Bakalis ([email protected])
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Christos Bakalis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 30.01.2017
-- Design Name: VMM Configuration Block
-- Module Name: vmm_config_block - RTL
-- Project Name: MMFE8 - NTUA
-- Target Devices: Artix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2016.2
-- Description: Module that stores the data coming from the UDP/Ethernet for VMM
-- configuration using a FIFO serializer. It also drives the SCK and CS signals.
-- Dependencies: MMFE8 NTUA Project
--
-- Changelog:
-- 16.02.2017 Modified the serialization FSM for VMM3 configuration. (Christos Bakalis)
-- 28.03.2017 VMM_ID is now sampled one level above. (Christos Bakalis)
--
----------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity vmm_config_block is
port(
------------------------------------
------- General Interface ----------
clk_125 : in std_logic;
clk_40 : in std_logic;
rst : in std_logic;
rst_fifo : in std_logic;
cnt_bytes : in unsigned(7 downto 0);
------------------------------------
--------- FIFO/UDP Interface -------
user_din_udp : in std_logic_vector(7 downto 0); --prv
user_valid_udp : in std_logic; --prv
user_last_udp : in std_logic; --prv
------------------------------------
------ VMM Config Interface --------
vmmConf_rdy : out std_logic;
vmmConf_done : out std_logic;
vmm_sck : out std_logic;
vmm_cs : out std_logic;
vmm_cfg_bit : out std_logic;
vmm_conf : in std_logic;
top_rdy : in std_logic;
init_ser : in std_logic
);
end vmm_config_block;
architecture RTL of vmm_config_block is
COMPONENT vmm_conf_buffer
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
signal rd_ena : std_logic := '0';
signal fifo_full : std_logic := '0';
signal fifo_empty : std_logic := '0';
signal sel_vmm_data : std_logic := '0';
signal wait_cnt : unsigned(1 downto 0) := (others => '0');
signal bit_cnt : unsigned(6 downto 0) := (others => '0');
signal user_valid_fifo : std_logic := '0';
signal vmm_cs_i : std_logic := '1';
type confFSM is (ST_IDLE, ST_RD_HIGH, ST_RD_LOW, ST_CKTK_LOW, ST_DONE);
signal st_conf : confFSM := ST_IDLE;
begin
-- sub-process that drives the data into the FIFO used for VMM configuration.
-- it also detects the 'last' pulse sent from the UDP block to initialize the
-- VMM config data serialization
VMM_conf_proc: process(clk_125)
begin
if(rising_edge(clk_125))then
if(rst = '1')then
sel_vmm_data <= '0';
vmmConf_rdy <= '0';
else
if(vmm_conf = '1' and user_last_udp = '0')then
case cnt_bytes is
when "00001000" => --8
sel_vmm_data <= '1'; -- select the correct data at the MUX
when others => null;
end case;
elsif(vmm_conf = '1' and user_last_udp = '1')then -- 'last' pulse detected, signal master FSM
vmmConf_rdy <= '1';
else
vmmConf_rdy <= '0';
sel_vmm_data <= '0';
end if;
end if;
end if;
end process;
-- FSM that reads the data from the serializing FIFO and asserts the SCK pulse
-- after the bit has passed safely into the vmm configuration bus. serialization
-- starts only after the assertion of the 'last' signal from the UDP block (see VMM_conf_proc)
VMM_conf_SCK_FSM: process(clk_40)
begin
if(rising_edge(clk_40))then
if(rst = '1' or rst_fifo = '1')then
st_conf <= ST_IDLE;
vmmConf_done <= '0';
rd_ena <= '0';
wait_cnt <= (others => '0');
bit_cnt <= (others => '0');
vmm_sck <= '0';
vmm_cs_i <= '1';
else
case st_conf is
-- wait for flow_fsm and master_conf_FSM
when ST_IDLE =>
vmmConf_done <= '0';
vmm_cs_i <= '1';
if(top_rdy = '1' and init_ser = '1')then
st_conf <= ST_RD_HIGH;
else
st_conf <= ST_IDLE;
end if;
-- assert the rd_ena signal if there is still data in the buffer. also check for 96-bit counter
when ST_RD_HIGH =>
if(fifo_empty = '0' and bit_cnt /= "1100000")then
rd_ena <= '1';
bit_cnt <= bit_cnt + 1;
vmm_cs_i <= '0';
st_conf <= ST_RD_LOW;
elsif(fifo_empty = '0' and bit_cnt = "1100000")then -- 96 bits sent, pull cs high and return to this state
rd_ena <= '0';
bit_cnt <= (others => '0');
vmm_cs_i <= '1';
st_conf <= ST_RD_HIGH;
else
rd_ena <= '0';
bit_cnt <= (others => '0');
st_conf <= ST_DONE;
end if;
-- wait for the FIFO to pass the bit as there is
-- some latency (see 'embedded registers' at FIFO generator)
when ST_RD_LOW =>
rd_ena <= '0';
if(wait_cnt = "11")then
wait_cnt <= (others => '0');
vmm_sck <= '1';
st_conf <= ST_CKTK_LOW;
else
wait_cnt <= wait_cnt + 1;
vmm_sck <= '0';
st_conf <= ST_RD_LOW;
end if;
-- ground CKTK and then check if there is more data left
when ST_CKTK_LOW =>
vmm_sck <= '0';
st_conf <= ST_RD_HIGH;
-- stay here until reset by master config FSM
when ST_DONE =>
vmmConf_done <= '1';
vmm_cs_i <= '1';
st_conf <= ST_DONE;
when others =>
st_conf <= ST_IDLE;
end case;
end if;
end if;
end process;
-- MUX that drives the VMM configuration data into the FIFO
FIFO_valid_MUX: process(sel_vmm_data, user_valid_udp)
begin
case sel_vmm_data is
when '0' => user_valid_fifo <= '0';
when '1' => user_valid_fifo <= user_valid_udp;
when others => user_valid_fifo <= '0';
end case;
end process;
-- FIFO that serializes the VMM data
FIFO_serializer: vmm_conf_buffer
PORT MAP(
rst => rst_fifo,
wr_clk => clk_125,
rd_clk => clk_40,
din => user_din_udp,
wr_en => user_valid_fifo,
rd_en => rd_ena,
dout(0) => vmm_cfg_bit,
full => fifo_full,
empty => fifo_empty
);
vmm_cs <= vmm_cs_i;
end RTL; | gpl-3.0 | 93b16f55a398427853244bb78a7574f8 | 0.489618 | 3.865025 | false | true | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/ICMP_RX.vhd | 1 | 13,307 | ----------------------------------------------------------------------------------
-- Company: NTU Athens - BNL
-- Engineer: Christos Bakalis ([email protected])
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Christos Bakalis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 03.02.2017
-- Design Name: ICMP Receiver
-- Module Name: ICMP_RX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions: Vivado 2016.2
-- Description: Handles simple ICMP RX
--
-- Dependencies:
--
-- Changelog:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
entity ICMP_RX is
port (
-- ICMP Layer signals
icmp_rx_start : out std_logic; -- indicates receipt of icmp header
icmp_rxo : out icmp_rx_type;
-- system signals
clk : in std_logic;
reset : in std_logic;
-- IP layer RX signals
ip_rx_start : in std_logic; -- indicates receipt of ip header
ip_rx : in ipv4_rx_type
);
end ICMP_RX;
architecture Behavioral of ICMP_RX is
type rx_state_type is (IDLE, ICMP_HDR, ICMP_PAYLOAD, WAIT_END, ERR);
type rx_event_type is (NO_EVENT, DATA);
type count_mode_type is (RST, INCR, HOLD);
type settable_count_mode_type is (RST, INCR, SET_VAL, HOLD);
type set_clr_type is (SET, CLR, HOLD);
-- state variables
signal rx_state : rx_state_type;
signal rx_count : unsigned (15 downto 0);
signal icmp_type : std_logic_vector (7 downto 0);
signal icmp_code : std_logic_vector (7 downto 0);
signal icmp_chksum : std_logic_vector (15 downto 0);
signal icmp_ident : std_logic_vector (15 downto 0);
signal icmp_seqNum : std_logic_vector (15 downto 0);
signal icmp_rx_start_reg : std_logic; -- indicates start of user data
signal src_ip_addr : std_logic_vector (31 downto 0); -- captured from IP hdr
-- rx control signals
signal next_rx_state : rx_state_type;
signal set_rx_state : std_logic;
signal rx_event : rx_event_type;
signal rx_count_mode : settable_count_mode_type;
signal rx_count_val : unsigned (15 downto 0);
signal set_type : std_logic;
signal set_code : std_logic;
signal set_chksum_h : std_logic;
signal set_chksum_l : std_logic;
signal set_ident_h : std_logic;
signal set_ident_l : std_logic;
signal set_seq_h : std_logic;
signal set_seq_l : std_logic;
signal set_icmp_rx_start : set_clr_type;
signal dataval : std_logic_vector (7 downto 0);
signal set_src_ip : std_logic;
signal set_data_last : std_logic;
-- ICMP datagram header format
--
-- 0 8 16 31
-- --------------------------------------------------------------------------------------------
-- | Type | Code | Checksum |
-- | | | |
-- --------------------------------------------------------------------------------------------
-- | Identifier | Sequence Number |
-- | | |
-- --------------------------------------------------------------------------------------------
-- | Payload |
-- | |
-- --------------------------------------------------------------------------------------------
-- | .... |
-- | |
-- --------------------------------------------------------------------------------------------
--
-- Type = 8 and Code = 0 (echo request)
-- Type = 0 and Code = 0 (echo reply)
begin
-----------------------------------------------------------------------
-- combinatorial process to implement FSM and determine control signals
-----------------------------------------------------------------------
rx_combinatorial : process (
-- input signals
ip_rx, ip_rx_start,
-- state variables
rx_state, rx_count, icmp_type, icmp_code, icmp_chksum, icmp_ident, icmp_seqNum, icmp_rx_start_reg, src_ip_addr,
-- control signals
next_rx_state, set_rx_state, rx_event, rx_count_mode, rx_count_val,
set_type, set_code, set_chksum_h, set_chksum_l, set_ident_h, set_ident_l, set_seq_h, set_seq_l, set_data_last,
set_icmp_rx_start, dataval, set_src_ip
)
begin
-- set output followers
icmp_rx_start <= icmp_rx_start_reg;
icmp_rxo.hdr.src_ip_addr <= src_ip_addr;
icmp_rxo.hdr.icmp_type <= icmp_type;
icmp_rxo.hdr.icmp_code <= icmp_code;
icmp_rxo.hdr.icmp_chksum <= icmp_chksum;
icmp_rxo.hdr.icmp_ident <= icmp_ident;
icmp_rxo.hdr.icmp_seqNum <= icmp_seqNum;
-- transfer data upstream if in user data phase
if rx_state = ICMP_PAYLOAD then
icmp_rxo.payload.data_in <= ip_rx.data.data_in;
icmp_rxo.payload.data_in_valid <= ip_rx.data.data_in_valid;
icmp_rxo.payload.data_in_last <= set_data_last;
else
icmp_rxo.payload.data_in <= (others => '0');
icmp_rxo.payload.data_in_valid <= '0';
icmp_rxo.payload.data_in_last <= '0';
end if;
-- set signal defaults
next_rx_state <= IDLE;
set_rx_state <= '0';
rx_event <= NO_EVENT;
rx_count_mode <= RST;
set_type <= '0';
set_code <= '0';
set_chksum_h <= '0';
set_chksum_l <= '0';
set_ident_h <= '0';
set_ident_l <= '0';
set_seq_h <= '0';
set_seq_l <= '0';
set_icmp_rx_start <= CLR;
dataval <= (others => '0');
set_src_ip <= '0';
rx_count_val <= (others => '0');
set_data_last <= '0';
-- determine event (if any)
if ip_rx.data.data_in_valid = '1' then
rx_event <= DATA;
dataval <= ip_rx.data.data_in;
end if;
-- RX FSM
case rx_state is
when IDLE =>
rx_count_mode <= RST;
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if ip_rx.hdr.protocol = x"01" then -- ICMP protocol
rx_count_mode <= INCR;
set_src_ip <= '1';
set_type <= '1';
next_rx_state <= ICMP_HDR;
set_rx_state <= '1';
else -- non-ICMP protocol - ignore this pkt
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
end case;
when ICMP_HDR =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if rx_count = x"0007" then
rx_count_mode <= SET_VAL;
rx_count_val <= x"0001";
next_rx_state <= ICMP_PAYLOAD;
set_rx_state <= '1';
else
rx_count_mode <= INCR;
end if;
-- handle early frame termination
if ip_rx.data.data_in_last = '1' then
next_rx_state <= IDLE;
set_rx_state <= '1';
else
case rx_count is
when x"0000" => set_type <= '1'; -- set ICMP type
when x"0001" => set_code <= '1'; -- set ICMP code
when x"0002" => set_chksum_h <= '1'; -- set checksum (1st byte)
when x"0003" => set_chksum_l <= '1'; -- set checksum (2nd byte)
when x"0004" => set_ident_h <= '1'; -- set identifier (1st byte)
when x"0005" => set_ident_l <= '1'; -- set identifier (2nd byte)
when x"0006" => set_seq_h <= '1'; -- set sequence number (1st byte)
when x"0007" => set_seq_l <= '1'; -- set sequence number (2nd byte)
set_icmp_rx_start <= SET; -- indicate frame received
when others => -- ignore other bytes in icmp header
end case;
end if;
end case;
when ICMP_PAYLOAD =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
-- note: data/payload gets transfered upstream as part of "output followers" processing
if ip_rx.data.data_in_last = '1' then -- no early frame termination check
next_rx_state <= IDLE;
set_icmp_rx_start <= CLR;
rx_count_mode <= RST;
set_rx_state <= '1';
set_data_last <= '1';
else
rx_count_mode <= INCR;
set_rx_state <= '0';
end if;
end case;
when ERR =>
if ip_rx.data.data_in_last = '0' then
next_rx_state <= WAIT_END;
set_rx_state <= '1';
else
next_rx_state <= IDLE;
set_rx_state <= '1';
end if;
when WAIT_END =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if ip_rx.data.data_in_last = '1' then
next_rx_state <= IDLE;
set_rx_state <= '1';
end if;
end case;
end case;
end process;
-----------------------------------------------------------------------------
-- sequential process to action control signals and change states and outputs
-----------------------------------------------------------------------------
rx_sequential : process (clk, reset)
begin
if rising_edge(clk) then
if reset = '1' then
-- reset state variables
rx_state <= IDLE;
rx_count <= x"0000";
icmp_type <= (others => '0');
icmp_code <= (others => '0');
icmp_chksum <= (others => '0');
icmp_ident <= (others => '0');
icmp_seqNum <= (others => '0');
icmp_rx_start_reg <= '0';
src_ip_addr <= (others => '0');
else
-- Next rx_state processing
if set_rx_state = '1' then
rx_state <= next_rx_state;
else
rx_state <= rx_state;
end if;
-- rx_count processing
case rx_count_mode is
when RST => rx_count <= x"0000";
when INCR => rx_count <= rx_count + 1;
when SET_VAL => rx_count <= rx_count_val;
when HOLD => rx_count <= rx_count;
end case;
-- ICMP datafields capture
if (set_type = '1') then icmp_type(7 downto 0) <= dataval; end if;
if (set_code = '1') then icmp_code(7 downto 0) <= dataval; end if;
if (set_chksum_h = '1') then icmp_chksum(15 downto 8) <= dataval; end if;
if (set_chksum_l = '1') then icmp_chksum(7 downto 0) <= dataval; end if;
if (set_ident_h = '1') then icmp_ident(15 downto 8) <= dataval; end if;
if (set_ident_l = '1') then icmp_ident(7 downto 0) <= dataval; end if;
if (set_seq_h = '1') then icmp_seqNum(15 downto 8) <= dataval; end if;
if (set_seq_l = '1') then icmp_seqNum(7 downto 0) <= dataval; end if;
case set_icmp_rx_start is
when SET => icmp_rx_start_reg <= '1';
when CLR => icmp_rx_start_reg <= '0';
when HOLD => icmp_rx_start_reg <= icmp_rx_start_reg;
end case;
-- capture src IP address
if set_src_ip = '1' then
src_ip_addr <= ip_rx.hdr.src_ip_addr;
else
src_ip_addr <= src_ip_addr;
end if;
end if;
end if;
end process;
end Behavioral; | gpl-3.0 | e44875376ff765062c14b6c849f75dc3 | 0.44796 | 4.008133 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/readout/trigger.vhd | 1 | 23,528 | ----------------------------------------------------------------------------------
-- Company: NTU ATHENS - BNL
-- Engineer: Paris Moschovakos
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Paris Moschovakos
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 18.05.2016
-- Design Name:
-- Module Name: trigger.vhd - Behavioral
-- Project Name: MMFE8
-- Target Devices: Artix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2016.2
--
-- Changelog:
-- 18.08.2016 Added tr_hold signal to hold trigger when reading out (Reid Pinkham)
-- 26.02.2017 Moved to a global clock domain @125MHz (Paris)
-- 27.02.2017 Synced trout (Paris)
-- 31.03.2017 Added 2 ckbc mode, requests 2 CKBC upon ext trigger (Paris)
-- 06.04.2017 Configurable latency was added for the 2 CKBC mode (Paris)
-- 28.04.2017 Added two processes that assert the level0 signal. (Christos Bakalis)
--
----------------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
use UNISIM.VComponents.all;
entity trigger is
Generic ( vmmReadoutMode : STD_LOGIC);
Port (
clk : in STD_LOGIC;
ckbc : in STD_LOGIC;
clk_art : in STD_LOGIC;
rst_trig : in STD_LOGIC;
ckbcMode : in STD_LOGIC;
request2ckbc : out STD_LOGIC;
cktp_enable : in std_logic;
cktp_pulse_width: in STD_LOGIC_VECTOR(4 downto 0);
CKTP_raw : in STD_LOGIC;
pfBusy : in STD_LOGIC;
tren : in STD_LOGIC;
tr_hold : in STD_LOGIC;
trmode : in STD_LOGIC;
trext : in STD_LOGIC;
level_0 : out STD_LOGIC;
accept_wr : out STD_LOGIC;
reset : in STD_LOGIC;
event_counter : out STD_LOGIC_VECTOR(31 DOWNTO 0);
tr_out : out STD_LOGIC;
trraw_synced125 : out STD_LOGIC;
latency : in STD_LOGIC_VECTOR(15 DOWNTO 0)
);
end trigger;
architecture Behavioral of trigger is
-- Signals
signal event_counter_i : std_logic_vector(31 downto 0) := ( others => '0' );
signal tr_out_i : std_logic := '0';
signal mode : std_logic := '0';
signal trint_pre : std_logic := '0';
signal trext_pre : std_logic := '0';
signal trext_stage1 : std_logic := '0';
signal trext_ff_synced : std_logic := '0';
signal tren_buff : std_logic := '0'; -- buffered enable signal
signal tr_out_i_stage1 : std_logic := '0';
signal tr_out_i_ff_synced : std_logic := '0';
signal trext_stage_resynced : std_logic := '0';
signal trext_ff_resynced : std_logic := '0';
signal tren_buff_stage1 : std_logic := '0';
signal tren_buff_ff_synced : std_logic := '0';
signal mode_stage1 : std_logic := '0';
signal mode_ff_synced : std_logic := '0';
signal ckbcMode_stage1 : std_logic := '0';
signal ckbcMode_ff_synced : std_logic := '0';
signal trmode_stage1 : std_logic := '0';
signal trmode_ff_synced : std_logic := '0';
signal accept_wr_i : std_logic := '0';
signal accept_wr_i_stage1 : std_logic := '0';
signal accept_wr_synced125 : std_logic := '0';
signal trraw_synced125_i : std_logic := '0';
signal pfBusy_stage1 : std_logic := '0';
signal pfBusy_stage_synced : std_logic := '0';
signal trint_stage_synced : std_logic := '0';
signal trint_stage_synced125: std_logic := '0';
signal trint_ff_synced125 : std_logic := '0';
signal flag_sent_stage1 : std_logic := '0';
signal flag_sent_synced : std_logic := '0';
signal cktp_width_final : std_logic_vector(11 downto 0) := "000101000000"; --4 * 80 = 320
signal trint : std_logic := '0';
signal cnt : integer range 0 to 7 := 0;
signal level_0_req : std_logic := '0';
signal level_0_25ns : std_logic := '0';
signal flag_sent : std_logic := '0';
-- Special Readout Mode
signal request2ckbc_i : std_logic := '0';
signal trigLatencyCnt : integer range 0 to 255 := 0;
signal trigLatency : integer := 140;
type stateType is (waitingForTrigger, waitingForLatency, waitingForLatency_1, waitingForLatency_2, issueRequest, checkTrigger);
signal state : stateType := waitingForTrigger;
signal state_l0 : stateType := waitingForTrigger;
---------------------------------------------------------------------------------------------- Uncomment for hold window Start
-- signal hold_state : std_logic_vector(3 downto 0);
-- signal hold_cnt : std_logic_vector(31 downto 0);
-- signal start : std_logic;
-- signal hold : std_logic;
-- signal state : std_logic_vector(2 downto 0) := ( others => '0' );
---------------------------------------------------------------------------------------------- Uncomment for hold window End
-- Debugging
signal probe0_out : std_logic_vector(63 downto 0);
-- Attributes
---------------------------------------------------------------------------------------------- Uncomment for hold window Start
-- constant delay : std_logic_vector(31 downto 0) := x"00000002"; -- Number of 200 MHz clock cycles to hold trigger in hex
---------------------------------------------------------------------------------------------- Uncomment for hold window End
attribute keep : string;
attribute keep of tren : signal is "true";
attribute keep of tren_buff : signal is "true";
attribute keep of tr_out_i : signal is "true";
attribute keep of trmode : signal is "true";
attribute keep of trint : signal is "true";
-------------------------------------------------------------------
-- Mark debug signals for ILA
-------------------------------------------------------------------
attribute mark_debug : string;
-- attribute mark_debug of event_counter_i : signal is "true";
-- attribute mark_debug of tr_out_i : signal is "true";
-- attribute mark_debug of tren : signal is "true";
-- attribute mark_debug of trmode : signal is "true";
-- attribute mark_debug of trint : signal is "true";
-- attribute mark_debug of mode : signal is "true";
-- attribute mark_debug of trint_pre : signal is "true";
-- attribute mark_debug of trext_pre : signal is "true";
-- attribute mark_debug of tr_out_i_ff_synced : signal is "true";
-- attribute mark_debug of trext : signal is "true";
-- attribute mark_debug of tren_buff : signal is "true";
-------------------------------------------------------------------
-- Async Regs
-------------------------------------------------------------------
attribute ASYNC_REG : string;
attribute ASYNC_REG of tr_out_i_stage1 : signal is "true";
attribute ASYNC_REG of tr_out_i_ff_synced : signal is "true";
attribute ASYNC_REG of trext_stage_resynced : signal is "true";
attribute ASYNC_REG of trext_ff_resynced : signal is "true";
attribute ASYNC_REG of trext_stage1 : signal is "true";
attribute ASYNC_REG of trext_ff_synced : signal is "true";
attribute ASYNC_REG of tren_buff_stage1 : signal is "true";
attribute ASYNC_REG of tren_buff_ff_synced : signal is "true";
attribute ASYNC_REG of mode_stage1 : signal is "true";
attribute ASYNC_REG of mode_ff_synced : signal is "true";
attribute ASYNC_REG of trmode_stage1 : signal is "true";
attribute ASYNC_REG of trmode_ff_synced : signal is "true";
attribute ASYNC_REG of accept_wr_i_stage1 : signal is "true";
attribute ASYNC_REG of accept_wr_synced125 : signal is "true";
attribute ASYNC_REG of pfBusy_stage1 : signal is "true";
attribute ASYNC_REG of pfBusy_stage_synced : signal is "true";
attribute ASYNC_REG of flag_sent_stage1 : signal is "true";
attribute ASYNC_REG of flag_sent_synced : signal is "true";
attribute ASYNC_REG of ckbcMode_stage1 : signal is "true";
attribute ASYNC_REG of ckbcMode_ff_synced : signal is "true";
-- Components if any
component ila_trigger
port(
clk : in std_logic;
probe0 : in std_logic_vector(63 downto 0)
);
end component;
component trint_gen
generic(vmmReadoutMode : std_logic);
port(
clk_160 : in std_logic;
clk_125 : in std_logic;
cktp_start : in std_logic;
cktp_pulse : in std_logic;
ckbc_mode : in std_logic;
cktp_width : in std_logic_vector(11 downto 0);
trint : out std_logic
);
end component;
begin
-- Processes
---------------------------------------------------------------------------------------------- Uncomment for hold window Start
--holdDelay: process (clk, reset, start, tr_out_i, trext, trint) -- state machine to manage delay
--begin
-- if (reset = '1') then
-- hold <= '0';
-- state <= ( others => '0' );
-- elsif rising_edge(clk) then
-- case state is
-- when "000" => -- Idle
-- if (start = '1') then -- wait for start signal
-- state <= "001";
-- else
-- state <= "000";
-- end if;
-- when "001" => -- st1
-- if (tr_out_i = '0') then -- trigger returned to zero, start the count
-- hold <= '1';
-- hold_cnt <= ( others => '0' ); -- reset the counter
-- state <= "010";
-- else
-- state <= "001";
-- end if;
-- when "010" => -- st2
-- if (hold_cnt = delay) then -- reached end of deadtime
-- if ((trext = '0' and mode = '1') or (trint = '0' and mode = '0')) then -- No current trigger
-- hold <= '0';
-- state <= "000";
-- else
-- state <= "011";
-- end if;
-- hold_cnt <= ( others => '0');
-- else
-- hold_cnt <= hold_cnt + '1';
-- end if;
-- when "011" => -- st3
-- if ((trext = '0' and mode = '1') or (trint = '0' and mode = '0')) then -- wait until missed trigger ends
-- state <= "000";
-- hold <= '0';
-- else
-- state <= "011";
-- end if;
-- when others =>
-- state <= "000";
-- end case ;
-- end if;
--end process;
--triggerLatch: process (tr_out_i, hold)
--begin
-- if (tr_out_i = '1' and hold = '0') then -- start of trigger
-- start <= '1';
-- else -- Release the start command
-- start <= '0';
-- end if;
--end process;
---------------------------------------------------------------------------------------------- Uncomment for hold window End
generate_2ckbc: if (vmmReadoutMode = '0') generate
trReadoutMode2CkbcDelayedRequest: process(clk_art)
begin
if rising_edge(clk_art) then
if(rst_trig = '1')then
request2ckbc_i <= '0';
trigLatencyCnt <= 0;
state <= waitingForTrigger;
else
case state is
when waitingForTrigger =>
request2ckbc_i <= '0';
if tren_buff_ff_synced = '1' and tr_out_i = '1' and ckbcMode_ff_synced = '1' then
trigLatencyCnt <= 0;
state <= waitingForLatency;
end if;
when waitingForLatency =>
if trigLatencyCnt < trigLatency then
trigLatencyCnt <= trigLatencyCnt + 1;
else
state <= issueRequest;
end if;
when issueRequest =>
request2ckbc_i <= '1';
state <= waitingForTrigger;
when others =>
request2ckbc_i <= '0';
trigLatencyCnt <= 0;
state <= waitingForTrigger;
end case;
end if;
end if;
end process;
end generate generate_2ckbc;
generate_level0: if (vmmReadoutMode = '1') generate
-- asserts level0 accept signal at the VMMs with a maximum of ~1.6 us latency
level0Asserter: process(clk_art)
begin
if(rising_edge(clk_art))then
if(rst_trig = '1')then
level_0_req <= '0';
trigLatencyCnt <= 0;
accept_wr_i <= '0';
state_l0 <= waitingForTrigger;
else
case state_l0 is
when waitingForTrigger =>
level_0_req <= '0';
accept_wr_i <= '0';
trigLatencyCnt <= 0;
-- proceed only if pf is @ idle
if((trext_ff_synced = '1' and trmode_ff_synced = '1' and pfBusy_stage_synced = '0') or
(trint = '1' and trmode_ff_synced = '0' and pfBusy_stage_synced = '0'))then
state_l0 <= waitingForLatency_1;
else
state_l0 <= waitingForTrigger;
end if;
when waitingForLatency_1 => -- open the acceptance window for the level-0 buffer
if trigLatencyCnt < trigLatency - 30 then
trigLatencyCnt <= trigLatencyCnt + 1;
state_l0 <= waitingForLatency_1;
else
accept_wr_i <= '1';
state_l0 <= waitingForLatency_2;
end if;
when waitingForLatency_2 =>
if trigLatencyCnt < trigLatency then
trigLatencyCnt <= trigLatencyCnt + 1;
state_l0 <= waitingForLatency_2;
else
trigLatencyCnt <= 0;
state_l0 <= issueRequest;
end if;
when issueRequest =>
level_0_req <= '1';
accept_wr_i <= '0';
if(flag_sent_synced = '1')then
state_l0 <= checkTrigger;
else
state_l0 <= issueRequest;
end if;
when checkTrigger =>
level_0_req <= '0';
if((trext_ff_synced = '0' and trmode_ff_synced = '1') or
(trint = '0' and trmode_ff_synced = '0'))then
state_l0 <= waitingForTrigger;
else
state_l0 <= checkTrigger;
end if;
when others =>
level_0_req <= '0';
trigLatencyCnt <= 0;
accept_wr_i <= '0';
state_l0 <= waitingForTrigger;
end case;
end if;
end if;
end process;
-- process that ensures a one-CKBC-width level0 pulse is asserted
level0_40_proc: process(ckbc)
begin
if(rising_edge(ckbc))then
if(flag_sent = '1' and level_0_req = '1')then null; -- wait
elsif(flag_sent = '1' and level_0_req = '0')then -- reset everything
level_0_25ns <= '0';
flag_sent <= '0';
elsif(level_0_25ns = '1')then -- level_0 to VMMs has a width of 25ns
level_0_25ns <= '0';
flag_sent <= '1';
elsif(level_0_req = '1')then -- level_0 latched from level0Asserter
level_0_25ns <= '1';
else
level_0_25ns <= '0';
flag_sent <= '0';
end if;
end if;
end process;
end generate generate_level0;
trenAnd: process(clk)
begin
if rising_edge(clk) then
if (tren = '1' and tr_hold = '0') then -- No hold command, trigger enabled
tren_buff <= '1';
else
tren_buff <= '0';
end if;
end if;
end process;
changeModeCommandProc: process (clk)
begin
if rising_edge(clk) then
if tren_buff = '1' then
if trmode = '0' then -- Internal trigger
mode <= '0';
else -- External trigger
mode <= '1';
end if;
end if;
end if;
end process;
triggerDistrSignalProc: process (clk_art, reset)
begin
if reset = '1' then
tr_out_i <= '0';
elsif rising_edge(clk_art) then
if mode_ff_synced = '0' then
if (tren_buff_ff_synced = '1' and trmode_ff_synced = '0' and trint = '1') then
tr_out_i <= '1';
elsif (trmode_ff_synced = '0' and trint = '0') then
tr_out_i <= '0';
else
tr_out_i <= '0';
end if;
else
if (tren_buff_ff_synced = '1' and trmode_ff_synced = '1' and trext_ff_synced = '1') then
tr_out_i <= '1';
elsif (trmode_ff_synced = '1' and trext_ff_synced = '0') then
tr_out_i <= '0';
else
tr_out_i <= '0';
end if;
end if;
end if;
end process;
troutSyncToFpgaLogic: process(clk)
begin
if rising_edge(clk) then
tr_out_i_stage1 <= tr_out_i;
tr_out_i_ff_synced <= tr_out_i_stage1;
trext_stage_resynced <= trext_ff_synced;
trext_ff_resynced <= trext_stage_resynced;
trint_stage_synced125 <= trint;
trint_ff_synced125 <= trint_stage_synced125;
accept_wr_i_stage1 <= accept_wr_i;
accept_wr_synced125 <= accept_wr_i_stage1;
end if;
end process;
externalTriggerSynchronizer160: process(clk_art)
begin
if rising_edge(clk_art) then
trext_stage1 <= trext;
trext_ff_synced <= trext_stage1;
tren_buff_stage1 <= tren_buff;
tren_buff_ff_synced <= tren_buff_stage1;
mode_stage1 <= mode;
mode_ff_synced <= mode_stage1;
trmode_stage1 <= trmode;
trmode_ff_synced <= trmode_stage1;
pfBusy_stage1 <= pfBusy;
pfBusy_stage_synced <= pfBusy_stage1;
flag_sent_stage1 <= flag_sent;
flag_sent_synced <= flag_sent_stage1;
ckbcMode_stage1 <= ckbcMode;
ckbcMode_ff_synced <= ckbcMode_stage1;
end if;
end process;
eventCounterProc: process (clk_art, reset)
begin
if reset = '1' then
event_counter_i <= x"00000000";
else
if rising_edge(clk_art) then
if mode_ff_synced = '0' then
if (tren_buff_ff_synced = '1' and trmode_ff_synced = '0' and trint = '1' and trint_pre = '0') then
event_counter_i <= event_counter_i + 1;
trint_pre <= '1';
elsif (trmode_ff_synced = '0' and trint = '0') then
event_counter_i <= event_counter_i;
trint_pre <= '0';
else
event_counter_i <= event_counter_i;
end if;
else
if (tren_buff_ff_synced = '1' and trmode_ff_synced = '1' and trext_ff_synced = '1' and trext_pre = '0') then
event_counter_i <= event_counter_i + 1;
trext_pre <= '1';
elsif (trmode_ff_synced = '1' and trext_ff_synced = '0') then
event_counter_i <= event_counter_i;
trext_pre <= '0';
else
event_counter_i <= event_counter_i;
end if;
end if;
end if;
end if;
end process;
triggerRawMux:process (trext_ff_resynced, trint_ff_synced125, trmode, reset)
begin
if reset = '1' then
trraw_synced125_i <= '0';
else
if trmode = '1' then
trraw_synced125_i <= trext_ff_resynced;
elsif trmode = '0' then
trraw_synced125_i <= trint_ff_synced125;
end if;
end if;
end process;
-- Signal assignments
event_counter <= event_counter_i;
tr_out <= tr_out_i_ff_synced;
request2ckbc <= request2ckbc_i;
trraw_synced125 <= trraw_synced125_i;
trigLatency <= to_integer(unsigned(latency));
accept_wr <= accept_wr_synced125;
level_0 <= level_0_25ns;
cktp_width_final <= std_logic_vector(unsigned(cktp_pulse_width)*"1010000"); -- input x 80
-- Instantiations if any
cktp_trint_module: trint_gen
generic map(vmmReadoutMode => vmmReadoutMode)
port map(
clk_160 => clk_art,
clk_125 => clk,
cktp_start => cktp_enable,
cktp_pulse => CKTP_raw,
ckbc_mode => ckbcMode_ff_synced,
cktp_width => cktp_width_final,
trint => trint -- synced to 160 Mhz
);
--ilaTRIG: ila_trigger
--port map(
-- clk => clk_art,
-- probe0 => probe0_out
-- );
probe0_out(0) <= tr_out_i_ff_synced;
probe0_out(1) <= trext;
probe0_out(2) <= trmode;
probe0_out(3) <= trint;
probe0_out(4) <= mode;
probe0_out(5) <= trint_pre;
probe0_out(6) <= trext_pre;
probe0_out(7) <= tren_buff;
probe0_out(8) <= request2ckbc_i;
probe0_out(9) <= trext_ff_synced;
probe0_out(63 downto 10) <= (others => '0');
end Behavioral; | gpl-3.0 | f521929d734230c57e0a53c8c560cbb8 | 0.478281 | 4.071293 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/enc_8b10.vhd | 4 | 9,805 | -------------------------------------------------------------------------------
--
-- Title : 8b/10b Encoder
-- Design : 8-bit to 10-bit Encoder
-- Project : 8000 - 8b10b_encdec
-- Author : Ken Boyette
-- Company : Critia Computer, Inc.
--
-------------------------------------------------------------------------------
--
-- File : 8b10b_enc.vhd
-- Version : 1.0
-- Generated : 09.15.2006
-- By : Itf2Vhdl ver. 1.20
--
-------------------------------------------------------------------------------
--
-- Description :
-- This module provides 8-bit to 10-bit encoding.
-- It accepts 8-bit parallel data input and generates 10-bit encoded data
-- output in accordance with the 8b/10b standard. This coding method was
-- described in the 1983 IBM publication "A DC-Balanced, Partitioned-Block,
-- 8B/10B Transmission Code" by A.X. Widmer and P.A. Franaszek and was granted
-- a U.S. Patent #4,486,739 in 1984 which has now expired.
--
-- The parallel 8-bit Binary input represent 256 possible values, called
-- characters.
-- The bits are identified as:
-- HI, GI, FI, EI, DI, CI, BI, AI (Most Significant to Least)
-- The output is a 10-bit encoded character whose bits are identified as:
-- AO, BO, CO, DO, EO, IO, FO, GO, HO, AJO (Least Significant to Most)
-- An additional 12 output characters, K, are defined for command and
-- synchronization use.
-- KI, is used to indicate that the input is for a special character.
-- All inputs and outputs are synchronous with an externally supplied
-- byte rate clock BYTECLK.
-- The encoded output is valid one clock after the input.
-- There is a reset input, RESET, to reset the logic. The next rising
-- BYTECLK after RESET is deasserted latches valid input data.
--
-- Note: This VHDL structure closely follows the discrete logic defined
-- in the original article and the subsequent patent.
-- The Figures referenced are those in the patent.
-------------------------------------------------------------------------------
-- This program is licensed under the GPL.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity enc_8b10b is
port(
RESET : in std_logic ; -- Global asynchronous reset (active high)
clk : in std_logic ;
ena : in std_logic ;
--enaFall : in std_logic ;
--SBYTECLK : in std_logic ; -- Master synchronous send byte clock
KI : in std_logic ; -- Control (K) input(active high)
AI, BI, CI, DI, EI, FI, GI, HI : in std_logic ; -- Unencoded input data
JO, HO, GO, FO, IO, EO, DO, CO, BO, AO : out std_logic -- Encoded out
);
end enc_8b10b;
architecture behavioral of enc_8b10b is
-- Signals to tie things together
signal XLRESET, LRESET : std_logic ; -- Local synchronized RESET
signal L40, L04, L13, L31, L22 : std_logic ; -- Figure 3 Signals
signal F4, G4, H4, K4, S, FNEG : std_logic ; -- Figure 4 Signals
signal PD1S6, ND1S6, PD0S6, ND0S6 : std_logic ; -- Figure 5 Signals
signal ND1S4, ND0S4, PD1S4, PD0S4 : std_logic ; -- ...Figure 5
signal COMPLS4, COMPLS6, NDL6 : std_logic ; -- Figure 6 Signals
signal PDL6, LPDL6, PDL4, LPDL4 : std_logic ; -- Figure 6
signal NAO, NBO, NCO, NDO, NEO, NIO : std_logic ; -- Figure 7 Signals
signal NFO, NGO, NHO, NJO, SINT : std_logic ; -- Figure 8
begin
-- PROCESS: SYNCRST; Synchronize and delay RESET one clock for startup
SYNCRST1: process (clk)--(RESET, SBYTECLK)
begin
if clk'event and clk = '1' then --if SBYTECLK'event and SBYTECLK = '1' then
if ena = '1' then
XLRESET <= RESET ;
end if ;
end if ;
end process SYNCRST1 ;
SYNCRST2: process (clk)--(XLRESET, SBYTECLK)
begin
if clk'event and clk = '0' then --if SBYTECLK'event and SBYTECLK = '0' then
if ena = '1' then
LRESET <= XLRESET ;
end if ;
end if ;
end process SYNCRST2 ;
--
-- 5b Input Function (Reference: Figure 3)
--
-- Four 1's
L40 <= AI and BI and CI and DI ; -- 1,1,1,1
-- Four 0's
L04 <= not AI and not BI and not CI and not DI ; -- 0,0,0,0
-- One 1 and three 0's
L13 <= (not AI and not BI and not CI and DI) -- 0,0,0,1
or (not AI and not BI and CI and not DI) -- 0,0,1,0
or (not AI and BI and not CI and not DI) -- 0,1,0,0
or (AI and not BI and not CI and not DI) ; -- 1,0,0,0
-- Three 1's and one 0
L31 <= (AI and BI and CI and not DI) -- 1,1,1,0
or (AI and BI and not CI and DI) -- 1,1,0,1
or (AI and not BI and CI and DI) -- 1,0,1,1
or (not AI and BI and CI and DI) ; -- 0,1,1,1
-- Two 1's and two 0's
L22 <= (not AI and not BI and CI and DI) -- 0,0,1,1
or (not AI and BI and CI and not DI) -- 0,1,1,0
or (AI and BI and not CI and not DI) -- 1,1,0,0
or (AI and not BI and not CI and DI) -- 1,0,0,1
or (not AI and BI and not CI and DI) -- 0,1,0,1
or (AI and not BI and CI and not DI) ; -- 1,0,1,0
--
-- 3b Input Function (Reference: Figure 4)
--
-- PROCESS: FN3B; Latch 3b and K inputs
FN3B: process (clk)--(SBYTECLK, FI, GI, HI, KI)
begin -- Falling edge of clock latches F,G,H,K inputs
if clk'event and clk = '0' then --if SBYTECLK'event and SBYTECLK = '0' then
if ena = '1' then
F4 <= FI ;
G4 <= GI ;
H4 <= HI ;
K4 <= KI ;
end if;
end if;
end process FN3B;
-- PROCESS: FNS; Create and latch "S" function
FNS: process (clk, LRESET)--(LRESET, SBYTECLK, PDL6, L31, DI, EI, NDL6, L13)
begin
if LRESET = '1' then
S <= '0' ;
elsif clk'event and clk = '1' then --elsif SBYTECLK'event and SBYTECLK = '1' then
if ena = '1' then
S <= (PDL6 and L31 and DI and not EI)
or (NDL6 and L13 and EI and not DI) ;
end if;
end if;
end process FNS ;
-- Intermediate term for "F4 is Not Equal to G4"
FNEG <= F4 xor G4 ;
--
-- Disparity Control - Figure 5
--
PD1S6 <= (not L22 and not L31 and not EI)
or (L13 and DI and EI) ;
ND1S6 <= (L31 and not DI and not EI)
or (EI and not L22 and not L13)
or K4 ;
PD0S6 <= (not L22 and not L13 and EI)
or K4 ;
ND0S6 <= (not L22 and not L31 and not EI)
or (L13 and DI and EI) ;
ND1S4 <= (F4 and G4);
ND0S4 <= (not F4 and not G4);
PD1S4 <= (not F4 and not G4)
or (FNEG and K4) ;
PD0S4 <= (F4 and G4 and H4) ;
--
-- Disparity Control - Figure 6
--
PDL6 <= (PD0S6 and not COMPLS6)
or (COMPLS6 and ND0S6)
or (not ND0S6 and not PD0S6 and LPDL4) ;
NDL6 <= not PDL6 ;
PDL4 <= (LPDL6 and not PD0S4 and not ND0S4)
or (ND0S4 and COMPLS4)
or (not COMPLS4 and PD0S4) ;
-- PROCESS: CMPLS4; Disparity determines complimenting S4
CMPLS4: process (clk, LRESET)--(LRESET, SBYTECLK, PDL6)
begin
if LRESET = '1' then
LPDL6 <= '0' ;
elsif clk'event and clk = '1' then --elsif SBYTECLK'event and SBYTECLK = '1' then -- Rising edge
if ena = '1' then
LPDL6 <= PDL6 ; -- .. latches S4
end if;
end if;
end process CMPLS4 ;
COMPLS4 <= (PD1S4 and not LPDL6)
xor (ND1S4 and LPDL6) ;
-- PROCESS: CMPLS6; Disparity determines complimenting S6
CMPLS6: process (clk, LRESET)--(LRESET, SBYTECLK, PDL4)
begin
if LRESET = '1' then
LPDL4 <= '0' ;
elsif clk'event and clk = '0' then --elsif SBYTECLK'event and SBYTECLK = '0' then -- Falling edge
if ena = '1' then
LPDL4 <= PDL4 ; -- .. latches S6
end if;
end if;
end process CMPLS6;
COMPLS6 <= (ND1S6 and LPDL4)
xor (PD1S6 and not LPDL4) ;
--
-- 5b/6b Encoder - Figure 7
--
-- Logic for non-complimented (Normal) A,B,C,D,E,I outputs
NAO <= AI ;
NBO <= L04
or (BI and not L40) ;
NCO <= CI
or L04
or (L13 and DI and EI) ;
NDO <= (DI and not L40) ;
NEO <= (EI and not (L13 and DI and EI))
or (L13 and not EI) ;
NIO <= (L22 and not EI)
or (L04 and EI)
or (L13 and not DI and EI)
or (L40 and EI)
or (L22 and KI) ;
-- PROCESS: ENC5B6B; Generate and latch LS 6 encoded bits
ENC5B6B: process (clk, LRESET)--(LRESET, SBYTECLK, COMPLS6, NAO, NBO, NCO, NDO, NEO, NIO)
begin
if LRESET = '1' then
AO <= '0' ;
BO <= '0' ;
CO <= '0' ;
DO <= '0' ;
EO <= '0' ;
IO <= '0' ;
elsif clk'event and clk = '1' then --elsif SBYTECLK'event and SBYTECLK = '1' then
if ena = '1' then
AO <= COMPLS6 XOR NAO ; -- Least significant bit 0
BO <= COMPLS6 XOR NBO ;
CO <= COMPLS6 XOR NCO ;
DO <= COMPLS6 XOR NDO ;
EO <= COMPLS6 XOR NEO ;
IO <= COMPLS6 XOR NIO ; -- Most significant bit 6
end if;
end if;
end process ENC5B6B;
--
-- 3b/4b Encoder - Figure 8
--
-- Logic for the non-complimented F,G,H,J outputs
SINT <= (S and F4 and G4 and H4)
or (K4 and F4 and G4 and H4) ;
NFO <= (F4 and not SINT) ;
NGO <= G4
or (not F4 and not G4 and not H4) ;
NHO <= H4 ;
NJO <= SINT
or (FNEG and not H4) ;
-- PROCESS: ENC3B4B; Generate and latch MS 4 encoded bits
ENC3B4B: process (clk, LRESET)--(LRESET, SBYTECLK, COMPLS4, NFO, NGO, NHO, NJO)
begin
if LRESET = '1' then
FO <= '0' ;
GO <= '0' ;
HO <= '0' ;
JO <= '0' ;
elsif clk'event and clk = '0' then --elsif SBYTECLK'event and SBYTECLK ='0' then
if ena = '1' then
FO <= COMPLS4 XOR NFO ; -- Least significant bit 7
GO <= COMPLS4 XOR NGO ;
HO <= COMPLS4 XOR NHO ;
JO <= COMPLS4 XOR NJO ; -- Most significant bit 10
end if;
end if;
end process ENC3B4B ;
end behavioral; | gpl-3.0 | 9488dcfff7fd453af89b3cbb4ba1643b | 0.558899 | 2.906046 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4400/EPROC_IN4.vhd | 1 | 3,940 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/22/2014
--! Module Name: EPROC_IN4
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.ALL;
use work.all;
--! E-link processor, 4bit input
entity EPROC_IN4 is
generic (do_generate : boolean := true);
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
ENA : in std_logic;
ENCODING : in std_logic_vector (1 downto 0);
EDATA_IN : in std_logic_vector (3 downto 0);
DATA_OUT : out std_logic_vector (9 downto 0);
DATA_RDY : out std_logic;
busyOut : out std_logic
);
end EPROC_IN4;
architecture Behavioral of EPROC_IN4 is
constant zeros10array : std_logic_vector (9 downto 0) := (others=>'0');
--
signal DATA_OUT_direct,DATA_OUT_8b10b_case,DATA_OUT_HDLC_case,DATA_OUT_s : std_logic_vector (9 downto 0);
signal DATA_RDY_direct,DATA_RDY_8b10b_case,DATA_RDY_HDLC_case,DATA_RDY_sig : std_logic;
---
signal RESTART_sig, rst_case00, rst_case01 : std_logic;
---
begin
gen_enabled: if do_generate = true generate
RESTART_sig <= rst or (not ENA); -- comes from clk40 domain
-------------------------------------------------------------------------------------------
-- ENCODING case "00": direct data, no delimeter...
-------------------------------------------------------------------------------------------
rst_case00 <= RESTART_sig or (ENCODING(1) or ENCODING(0));
--
EPROC_IN4_direct_inst: entity work.EPROC_IN4_direct
port map(
bitCLK => bitCLK,
bitCLKx4 => bitCLKx4,
rst => rst_case00,
edataIN => EDATA_IN,
dataOUT => DATA_OUT_direct,
dataOUTrdy => DATA_RDY_direct
);
-------------------------------------------------------------------------------------------
-- ENCODING case "01": DEC8b10b
-------------------------------------------------------------------------------------------
rst_case01 <= RESTART_sig or (ENCODING(1) or (not ENCODING(0)));
--
EPROC_IN4_DEC8b10b_inst: entity work.EPROC_IN4_DEC8b10b
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case01,
edataIN => EDATA_IN,
dataOUT => DATA_OUT_8b10b_case,
dataOUTrdy => DATA_RDY_8b10b_case,
busyOut => busyOut
);
-------------------------------------------------------------------------------------------
-- ENCODING case "10": HDLC
-------------------------------------------------------------------------------------------
-- TBD
DATA_OUT_HDLC_case <= (others=>'0');
DATA_RDY_HDLC_case <= '0';
-------------------------------------------------------------------------------------------
-- output data/rdy according to the encoding settings
-------------------------------------------------------------------------------------------
DATA_OUT_MUX4_10bit: entity work.MUX4_Nbit
generic map(N=>10)
port map(
data0 => DATA_OUT_direct,
data1 => DATA_OUT_8b10b_case,
data2 => DATA_OUT_HDLC_case,
data3 => zeros10array,
sel => ENCODING,
data_out => DATA_OUT_s
);
DATA_RDY_MUX4: entity work.MUX4
port map(
data0 => DATA_RDY_direct,
data1 => DATA_RDY_8b10b_case,
data2 => DATA_RDY_HDLC_case,
data3 => '0',
sel => ENCODING,
data_out => DATA_RDY_sig
);
DATA_RDY <= DATA_RDY_sig;
DATA_OUT <= DATA_OUT_s;
--------------------
end generate gen_enabled;
--
--
gen_disabled: if do_generate = false generate
DATA_OUT <= (others=>'0');
DATA_RDY <= '0';
busyOut <= '0';
end generate gen_disabled;
end Behavioral;
| gpl-3.0 | 4940de2931243b57c37a7814406be906 | 0.456345 | 3.763133 | false | false | false | false |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/synth/ZynqDesign_rst_processing_system7_0_100M_0.vhd | 1 | 6,758 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY ZynqDesign_rst_processing_system7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END ZynqDesign_rst_processing_system7_0_100M_0;
ARCHITECTURE ZynqDesign_rst_processing_system7_0_100M_0_arch OF ZynqDesign_rst_processing_system7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ZynqDesign_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ZynqDesign_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2013.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ZynqDesign_rst_processing_system7_0_100M_0_arch : ARCHITECTURE IS "ZynqDesign_rst_processing_system7_0_100M_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ZynqDesign_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "ZynqDesign_rst_processing_system7_0_100M_0,proc_sys_reset,{x_ipProduct=Vivado 2013.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END ZynqDesign_rst_processing_system7_0_100M_0_arch;
| mit | 1f0be96589e796beb9a47f7ad7e6621e | 0.719148 | 3.508827 | false | false | false | false |
GustaMagik/RSA_Security_Token | VHDL_code/ver_B/RSA_Security_Token_USB_Version/rsa_512/trunk/rtl/rsa_top.vhd | 1 | 17,279 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:01:04 12/13/2009
-- Design Name:
-- Module Name: rsa_top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- synthesis translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.all;
-- synthesis translate_on
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rsa_top is
port(
clk : in std_logic;
reset : in std_logic;
valid_in : in std_logic;
start_in : in std_logic;
x : in std_logic_vector(15 downto 0); -- estos 3 son x^y mod m
y : in std_logic_vector(15 downto 0);
m : in std_logic_vector(15 downto 0);
r_c : in std_logic_vector(15 downto 0); --constante de montgomery r^2 mod m
s : out std_logic_vector( 15 downto 0);
valid_out : out std_logic;
bit_size : in std_logic_vector(15 downto 0) --tamano bit del exponente y (log2(y))
);
end rsa_top;
architecture Behavioral of rsa_top is
component n_c_core
port (clk : in std_logic;
m_lsw : in std_logic_vector(15 downto 0);
ce : in std_logic;
n_c : out std_logic_vector(15 downto 0);
done : out std_logic
);
end component;
--Multiplicador de Montgomery que sera instanciado 2 veces
component montgomery_mult
port(
clk : in std_logic;
reset : in std_logic;
valid_in : in std_logic;
a : in std_logic_vector(15 downto 0);
b : in std_logic_vector(15 downto 0);
n : in std_logic_vector(15 downto 0);
s_prev : in std_logic_vector(15 downto 0);
n_c : in std_logic_vector(15 downto 0);
s : out std_logic_vector( 15 downto 0);
valid_out : out std_logic -- es le valid out TODO : cambiar nombre
);
end component;
--Memoria para guardar el exponente y el modulo
component Mem_b
port (
clka : in std_logic;
wea : in std_logic_vector(0 downto 0);
addra : in std_logic_vector(5 downto 0);
dina : in std_logic_vector(15 downto 0);
douta : out std_logic_vector(15 downto 0));
end component;
--fifos para los resultados de las mult parciales
component res_out_fifo
port (
clk : in std_logic;
rst : in std_logic;
din : in std_logic_vector(31 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(31 downto 0);
full : out std_logic;
empty : out std_logic);
end component;
signal valid_in_mon_1, valid_in_mon_2, valid_out_mon_1, valid_out_mon_2, fifo_1_rd, fifo_1_wr : std_logic;
signal a_mon_1, b_mon_1, n_mon_1, s_p_mon_1, s_out_mon_1, a_mon_2, b_mon_2, n_mon_2, s_p_mon_2, s_out_mon_2, fifo_1_in, fifo_2_in, fifo_1_out, exp_out, n_out : std_logic_vector(15 downto 0);
signal fifo_out, fifo_in : std_logic_vector(31 downto 0);
signal addr_exp, addr_n, next_addr_exp, next_addr_n : std_logic_vector(5 downto 0);
type state_type is (wait_start, prepare_data, wait_constants, writting_cts_fifo, processing_data_0, processing_data_1, wait_results, transition, prepare_next, writting_results, final_mult, show_final, prepare_final, wait_final);
signal state, next_state : state_type;
signal w_numb, next_w_numb : std_logic_vector(7 downto 0);
--Señales registradas
signal n_c_reg, next_n_c_reg : std_logic_vector(15 downto 0);
--Cuenta los datos que se van metiendo al multiplicador para generar el padding por si solo.
signal count_input, next_count_input, bit_counter, next_bit_counter : std_logic_vector(15 downto 0);
signal bsize_reg, next_bsize_reg : std_logic_vector (15 downto 0);
signal write_b_n : std_logic_vector(0 downto 0);
signal n_c_o : std_logic_vector(15 downto 0);
signal n_c : std_logic_vector(15 downto 0);
signal n_c_load : std_logic;
begin
n_c1 : n_c_core
port map (
clk => clk,
m_lsw => m,
ce => start_in,
n_c => n_c_o,
done => n_c_load
);
mon_1 : montgomery_mult port map(
clk => clk,
reset => reset,
valid_in => valid_in_mon_1,
a => a_mon_1,
b => b_mon_1,
n => n_mon_1,
s_prev => s_p_mon_1,
n_c => n_c_reg,
s => s_out_mon_1,
valid_out => valid_out_mon_1
);
mon_2 : montgomery_mult port map(
clk => clk,
reset => reset,
valid_in => valid_in_mon_2,
a => a_mon_2,
b => b_mon_2,
n => n_mon_2,
s_prev => s_p_mon_2,
n_c => n_c_reg,
s => s_out_mon_2,
valid_out => valid_out_mon_2
);
fifo_mon_out : res_out_fifo
port map (
clk => clk,
rst => reset,
din => fifo_in,
wr_en => fifo_1_wr,
rd_en => fifo_1_rd,
dout => fifo_out
);
exp : Mem_b port map (
clka => clk,
wea => write_b_n,
addra => addr_exp,
dina => y,
douta => exp_out);
n_mod : Mem_b port map (
clka => clk,
wea => write_b_n,
addra => addr_n,
dina => m,
douta => n_out);
process(clk, reset)
begin
if(clk = '1' and clk'event) then
if(reset = '1')then
state <= wait_start;
n_c_reg <= (others => '0');
w_numb <= (others => '0');
count_input <= (others => '0');
addr_exp <= (others => '0');
addr_n <= (others => '0');
bit_counter <= (others => '0');
bsize_reg <= (others => '0');
n_c <= (others => '0');
else
if(n_c_load = '1') then
n_c <= n_c_o;
end if;
state <= next_state;
n_c_reg <= next_n_c_reg;
w_numb <= next_w_numb;
count_input <= next_count_input;
addr_exp <= next_addr_exp;
addr_n <= next_addr_n;
bit_counter <= next_bit_counter;
bsize_reg <= next_bsize_reg;
end if;
end if;
end process;
process(state, bsize_reg, n_c_reg, valid_in, x, n_c, r_c, m, y, w_numb, count_input, addr_exp, addr_n, s_out_mon_1, s_out_mon_2, bit_size, valid_out_mon_1, bit_counter, exp_out, fifo_out, n_out)
variable mask : std_logic_vector(3 downto 0);
begin
--Registers update
next_state <= state;
next_n_c_reg <= n_c_reg;
next_w_numb <= w_numb;
next_count_input <= count_input;
next_bsize_reg <= bsize_reg;
--Entradas de los montgomerys.
valid_in_mon_1 <= '0';
valid_in_mon_2 <= '0';
a_mon_1 <= (others => '0');
b_mon_1 <= (others => '0');
n_mon_1 <= (others => '0');
a_mon_2 <= (others => '0');
b_mon_2 <= (others => '0');
n_mon_2 <= (others => '0');
s_p_mon_1 <= (others => '0');
s_p_mon_2 <= (others => '0');
--Control de las fifos
fifo_1_rd <= '0';
fifo_in <= (others => '0');
fifo_1_wr <= '0';
--Control de memorias de exp y modulo
write_b_n <= b"0";
next_addr_exp <= addr_exp;
next_addr_n <= addr_n;
next_bit_counter <= bit_counter;
--Outputs
valid_out <= '0';
s <= (others => '0');
case state is
when wait_start =>
valid_in_mon_1 <= valid_in;
valid_in_mon_2 <= valid_in;
if(valid_in = '1') then
a_mon_1 <= x;
b_mon_1 <= r_c;
n_mon_1 <= m;
a_mon_2 <= x"0001";
b_mon_2 <= r_c;
n_mon_2 <= m;
next_w_numb <= x"23"; --Se extiende en 3 para poder usar las multiplicaciones modulares
next_n_c_reg <= n_c;
next_state <= prepare_data;
next_count_input <= x"0001";
write_b_n <= b"1"; --Notificamos que hay que guardar el exponente y modulo
next_addr_exp <= "000001";
next_addr_n <= "000001";
next_bsize_reg <= bit_size-1;
end if;
when prepare_data =>
next_count_input <= count_input+1;
valid_in_mon_1 <= '1';
valid_in_mon_2 <= '1';
--Esto es solo mientras los datos en la entrada son validos, cuando no lo son
--se meten 0s para la extension de 3 palabras en los montgomerys
if(valid_in = '1') then
a_mon_1 <= x;
b_mon_1 <= r_c;
n_mon_1 <= m;
b_mon_2 <= r_c;
n_mon_2 <= m;
write_b_n <= b"1";
next_addr_exp <= addr_exp+1;
next_addr_n <= addr_n+1;
end if;
if(count_input = w_numb) then
next_state <= wait_constants;
next_addr_n <= (others => '0');
next_addr_exp <= bsize_reg(9 downto 4);
--Decodificador para establecer la mascara
mask := bsize_reg(3 downto 0);
case (mask) is
when "0000" => next_bit_counter <= "0000000000000001";
when "0001" => next_bit_counter <= "0000000000000010";
when "0010" => next_bit_counter <= "0000000000000100";
when "0011" => next_bit_counter <= "0000000000001000";
when "0100" => next_bit_counter <= "0000000000010000";
when "0101" => next_bit_counter <= "0000000000100000";
when "0110" => next_bit_counter <= "0000000001000000";
when "0111" => next_bit_counter <= "0000000010000000";
when "1000" => next_bit_counter <= "0000000100000000";
when "1001" => next_bit_counter <= "0000001000000000";
when "1010" => next_bit_counter <= "0000010000000000";
when "1011" => next_bit_counter <= "0000100000000000";
when "1100" => next_bit_counter <= "0001000000000000";
when "1101" => next_bit_counter <= "0010000000000000";
when "1110" => next_bit_counter <= "0100000000000000";
when "1111" => next_bit_counter <= "1000000000000000";
when others =>
end case;
next_count_input <= (others => '0');
end if;
--Esperamos los valores validos de la salida de los montgomery
when wait_constants =>
--Comienzo a escribir en la fifo de datos
if(valid_out_mon_1 = '1') then
fifo_1_wr <= '1';
fifo_in <= s_out_mon_1 & s_out_mon_2;
next_count_input <= count_input+1;
next_state <= writting_cts_fifo;
end if;
--Escribimos las dos constantes iniciales en las fifos
when writting_cts_fifo =>
fifo_1_wr <= valid_out_mon_1;
next_count_input <= count_input+1;
if(count_input < x"20") then
fifo_in <= s_out_mon_1 & s_out_mon_2;
end if;
--Pedimos el siguiente input para la multiplicacion
if(valid_out_mon_1 = '0') then
next_count_input <= (others => '0');
next_state <= transition;
end if;
when transition =>
next_count_input <= count_input+1;
if(count_input > 2) then
next_count_input <= (others => '0');
--fifo_1_rd <= '1';
--next_addr_n <= addr_n+1;
if((bit_counter and exp_out) = x"0000") then
next_state <= processing_data_0;
else
next_state <= processing_data_1;
end if;
end if;
--se van ejecutando las multiplicaciones sucesivas
when processing_data_1 =>
if(count_input > x"0000")then
valid_in_mon_1 <= '1';
valid_in_mon_2 <= '1';
end if;
fifo_1_rd <= '1';
a_mon_1 <= fifo_out(31 downto 16);
b_mon_1 <= fifo_out(15 downto 0);
n_mon_1 <= n_out;
a_mon_2 <= fifo_out(31 downto 16);
b_mon_2 <= fifo_out(31 downto 16);
n_mon_2 <= n_out;
next_addr_n <= addr_n+1;
next_count_input <= count_input +1;
--Cuando llego al final cambio de estado a esperar resultados
if(count_input = w_numb) then
next_state <= wait_results;
end if;
when processing_data_0 =>
if(count_input > x"0000")then
valid_in_mon_1 <= '1';
valid_in_mon_2 <= '1';
end if;
fifo_1_rd <= '1';
a_mon_1 <= fifo_out(15 downto 0);
b_mon_1 <= fifo_out(15 downto 0);
n_mon_1 <= n_out;
a_mon_2 <= fifo_out(31 downto 16);
b_mon_2 <= fifo_out(15 downto 0);
n_mon_2 <= n_out;
next_addr_n <= addr_n+1;
next_count_input <= count_input +1;
--Cuando llego al final cambio de estado a esperar resultados
if(count_input = w_numb) then
next_state <= wait_results;
next_count_input <= (others => '0');
end if;
when wait_results =>
--Comienzo a escribir en la fifo de datos
if(valid_out_mon_1 = '1') then
fifo_1_wr <= '1';
fifo_in <= s_out_mon_2 & s_out_mon_1;
next_count_input <= x"0001";
next_state <= writting_results;
end if;
when writting_results =>
next_addr_n <= (others => '0');
fifo_1_wr <= valid_out_mon_1;
next_count_input <= count_input+1;
if(count_input < x"20") then
fifo_in <= s_out_mon_2 & s_out_mon_1;
end if;
--Pedimos el siguiente input para la multiplicacion
if(valid_out_mon_1 = '0') then
next_count_input <= (others => '0');
next_state <= prepare_next;
--Calculo del siguiente bit del exponente
--Shifto uno la mascara
next_bit_counter <= '0'&bit_counter(15 downto 1);
if(bit_counter = x"0001")
then
next_addr_exp <= addr_exp -1;
next_bit_counter <= "1000000000000000";
end if;
if((bit_counter = x"0001") and addr_exp = "000000000")
then
next_state <= final_mult;
next_count_input <= (others => '0');
next_addr_exp <= (others => '0');
end if;
end if;
when prepare_next =>
next_state <= transition;
next_count_input <= (others => '0');
fifo_1_rd <= '0';
when final_mult =>
next_count_input <= count_input+1;
if(count_input > 2) then
next_count_input <= (others => '0');
next_state <= prepare_final;
end if;
when prepare_final =>
if(count_input > x"0000")then
valid_in_mon_1 <= '1';
end if;
fifo_1_rd <= '1';
a_mon_1 <= fifo_out(15 downto 0);
if(count_input = x"0001") then
b_mon_1 <= x"0001";
end if;
n_mon_1 <= n_out;
next_addr_n <= addr_n+1;
next_count_input <= count_input +1;
--Cuando llego al final cambio de estado a esperar resultados
if(count_input = w_numb) then
next_state <= wait_final;
next_count_input <= (others => '0');
end if;
when wait_final =>
if(valid_out_mon_1 = '1') then
valid_out <= '1';
s <= s_out_mon_1;
next_state <= show_final;
next_count_input <= count_input +1;
end if;
when show_final =>
valid_out <= '1';
s <= s_out_mon_1;
next_count_input <= count_input +1;
--Cuando llego al final cambio de estado a esperar resultados
if(count_input = x"20") then
valid_out <= '0';
next_state <= wait_start;
end if;
end case;
end process;
end Behavioral;
| bsd-3-clause | 15a2e6b022f3d0844134e87af1d30224 | 0.476243 | 3.485778 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/Reduce/tb_reduce.vhd | 1 | 2,743 | ----------------------------------------------------------------------------------------------------
-- Reduce Test-bench
----------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
----------------------------------------------------------------------------------------------------
-- ENTITY
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tb_clockgen_pkg.all;
use work.reduce_pkg.all;
--This module is a test-bench for simulating the reduce operation
entity tb_reduce is
end tb_reduce;
----------------------------------------------------------------------------------------------------
-- ARCHITECTURE
----------------------------------------------------------------------------------------------------
architecture sim of tb_reduce is
signal rst : std_logic;
signal clk : std_logic;
signal count_data : std_logic_vector(2 downto 0);
signal result_and : std_logic;
signal result_or : std_logic;
signal result_xor : std_logic;
signal result_nand : std_logic;
signal result_nor : std_logic;
signal result_xnor : std_logic;
begin
--Instantiate clock generator
clk1 : tb_clockgen
generic map(PERIOD => 30ns,
DUTY_CYCLE => 0.50)
port map( clk => clk);
--count_process
counter: process(clk, rst)
variable counter : unsigned(count_data'range) := (others => '0');
begin
if(rst = '1') then
counter := (others => '0');
else
if(rising_edge(clk)) then
counter := counter + 1;
end if;
end if;
count_data <= std_logic_vector(counter);
end process;
--UUT
reduce_and_test : reduce_and
port map(data => count_data,
result => result_and);
reduce_or_test : reduce_or
port map(data => count_data,
result => result_or);
reduce_xor_test : reduce_xor
port map(data => count_data,
result => result_xor);
reduce_nand_test : reduce_nand
port map(data => count_data,
result => result_nand);
reduce_nor_test : reduce_nor
port map(data => count_data,
result => result_nor);
reduce_xnor_test : reduce_xnor
port map(data => count_data,
result => result_xnor);
--Main Process
main: process
begin
rst <= '1';
wait for 50ns;
rst <= '0';
wait;
end process;
end sim;
| mit | 76c2ee9c59ae00f68c9bf2f0a562c3df | 0.43128 | 4.641286 | false | true | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4088/EPROC_IN2_direct.vhd | 1 | 3,427 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 04/13/2015
--! Module Name: EPROC_IN2_direct
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.centralRouter_package.all;
--! direct data driver for EPROC_IN2 module
entity EPROC_IN2_direct is
port (
bitCLK : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
edataIN : in std_logic_vector (1 downto 0);
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic
);
end EPROC_IN2_direct;
architecture Behavioral of EPROC_IN2_direct is
----------------------------------
----------------------------------
component pulse_pdxx_pwxx
generic(
pd : integer := 0;
pw : integer := 1);
port(
clk : in std_logic;
trigger : in std_logic;
pulseout : out std_logic
);
end component pulse_pdxx_pwxx;
----------------------------------
----------------------------------
signal word10b : std_logic_vector (9 downto 0) := "1100000000"; -- comma
signal word8b : std_logic_vector (7 downto 0) := (others=>'0');
signal inpcount : std_logic_vector (1 downto 0) := (others=>'0');
signal word8bRdy, word10bRdy : std_logic := '0';
begin
-------------------------------------------------------------------------------------------
-- input counter 0 to 3
-------------------------------------------------------------------------------------------
input_count: process(bitCLK, rst)
begin
if rst = '1' then
inpcount <= (others=>'0');
elsif bitCLK'event and bitCLK = '1' then
inpcount <= inpcount + 1;
end if;
end process;
-------------------------------------------------------------------------------------------
-- input mapping
-------------------------------------------------------------------------------------------
input_map: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
case inpcount is
when "00" => word8b(1 downto 0) <= edataIN;
when "01" => word8b(3 downto 2) <= edataIN;
when "10" => word8b(5 downto 4) <= edataIN;
when "11" => word8b(7 downto 6) <= edataIN;
when others =>
end case;
end if;
end process;
-------------------------------------------------------------------------------------------
-- output (code = "00" = data)
-------------------------------------------------------------------------------------------
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if inpcount = "11" then
word8bRdy <= '1';
else
word8bRdy <= '0';
end if;
end if;
end process;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if word8bRdy = '1' then
word10b <= "00" & word8b; -- data
word10bRdy <= '1';
else
word10bRdy <= '0';
end if;
end if;
end process;
dataOUT <= word10b;
dataOUTrdy_pulse: pulse_pdxx_pwxx GENERIC MAP(pd=>0,pw=>1) PORT MAP(bitCLKx4, word10bRdy, dataOUTrdy);
end Behavioral;
| gpl-3.0 | f4a034273394d7d7fad93ba3406e8618 | 0.42136 | 4.246592 | false | false | false | false |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_processing_system7_0_0/synth/ZynqDesign_processing_system7_0_0.vhd | 1 | 65,847 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
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-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:processing_system7:5.3
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY ZynqDesign_processing_system7_0_0 IS
PORT (
USB0_PORT_INDCTL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
USB0_VBUS_PWRSELECT : OUT STD_LOGIC;
USB0_VBUS_PWRFAULT : IN STD_LOGIC;
M_AXI_GP0_ARVALID : OUT STD_LOGIC;
M_AXI_GP0_AWVALID : OUT STD_LOGIC;
M_AXI_GP0_BREADY : OUT STD_LOGIC;
M_AXI_GP0_RREADY : OUT STD_LOGIC;
M_AXI_GP0_WLAST : OUT STD_LOGIC;
M_AXI_GP0_WVALID : OUT STD_LOGIC;
M_AXI_GP0_ARID : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
M_AXI_GP0_AWID : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
M_AXI_GP0_WID : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
M_AXI_GP0_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_GP0_ARLOCK : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_GP0_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_GP0_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_GP0_AWLOCK : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_GP0_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_GP0_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_GP0_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_GP0_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_GP0_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_GP0_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_GP0_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_GP0_ARLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_GP0_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_GP0_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_GP0_AWLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_GP0_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_GP0_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_GP0_ACLK : IN STD_LOGIC;
M_AXI_GP0_ARREADY : IN STD_LOGIC;
M_AXI_GP0_AWREADY : IN STD_LOGIC;
M_AXI_GP0_BVALID : IN STD_LOGIC;
M_AXI_GP0_RLAST : IN STD_LOGIC;
M_AXI_GP0_RVALID : IN STD_LOGIC;
M_AXI_GP0_WREADY : IN STD_LOGIC;
M_AXI_GP0_BID : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
M_AXI_GP0_RID : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
M_AXI_GP0_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_GP0_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_GP0_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
FCLK_CLK0 : OUT STD_LOGIC;
FCLK_RESET0_N : OUT STD_LOGIC;
MIO : INOUT STD_LOGIC_VECTOR(53 DOWNTO 0);
DDR_CAS_n : INOUT STD_LOGIC;
DDR_CKE : INOUT STD_LOGIC;
DDR_Clk_n : INOUT STD_LOGIC;
DDR_Clk : INOUT STD_LOGIC;
DDR_CS_n : INOUT STD_LOGIC;
DDR_DRSTB : INOUT STD_LOGIC;
DDR_ODT : INOUT STD_LOGIC;
DDR_RAS_n : INOUT STD_LOGIC;
DDR_WEB : INOUT STD_LOGIC;
DDR_BankAddr : INOUT STD_LOGIC_VECTOR(2 DOWNTO 0);
DDR_Addr : INOUT STD_LOGIC_VECTOR(14 DOWNTO 0);
DDR_VRN : INOUT STD_LOGIC;
DDR_VRP : INOUT STD_LOGIC;
DDR_DM : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0);
DDR_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DDR_DQS_n : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0);
DDR_DQS : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0);
PS_SRSTB : INOUT STD_LOGIC;
PS_CLK : INOUT STD_LOGIC;
PS_PORB : INOUT STD_LOGIC
);
END ZynqDesign_processing_system7_0_0;
ARCHITECTURE ZynqDesign_processing_system7_0_0_arch OF ZynqDesign_processing_system7_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ZynqDesign_processing_system7_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT processing_system7_v5_3_processing_system7 IS
GENERIC (
C_EN_EMIO_ENET0 : INTEGER;
C_EN_EMIO_ENET1 : INTEGER;
C_EN_EMIO_TRACE : INTEGER;
C_INCLUDE_TRACE_BUFFER : INTEGER;
C_TRACE_BUFFER_FIFO_SIZE : INTEGER;
USE_TRACE_DATA_EDGE_DETECTOR : INTEGER;
C_TRACE_BUFFER_CLOCK_DELAY : INTEGER;
C_EMIO_GPIO_WIDTH : INTEGER;
C_INCLUDE_ACP_TRANS_CHECK : INTEGER;
C_USE_DEFAULT_ACP_USER_VAL : INTEGER;
C_S_AXI_ACP_ARUSER_VAL : INTEGER;
C_S_AXI_ACP_AWUSER_VAL : INTEGER;
C_M_AXI_GP0_ID_WIDTH : INTEGER;
C_M_AXI_GP0_ENABLE_STATIC_REMAP : INTEGER;
C_M_AXI_GP1_ID_WIDTH : INTEGER;
C_M_AXI_GP1_ENABLE_STATIC_REMAP : INTEGER;
C_S_AXI_GP0_ID_WIDTH : INTEGER;
C_S_AXI_GP1_ID_WIDTH : INTEGER;
C_S_AXI_ACP_ID_WIDTH : INTEGER;
C_S_AXI_HP0_ID_WIDTH : INTEGER;
C_S_AXI_HP0_DATA_WIDTH : INTEGER;
C_S_AXI_HP1_ID_WIDTH : INTEGER;
C_S_AXI_HP1_DATA_WIDTH : INTEGER;
C_S_AXI_HP2_ID_WIDTH : INTEGER;
C_S_AXI_HP2_DATA_WIDTH : INTEGER;
C_S_AXI_HP3_ID_WIDTH : INTEGER;
C_S_AXI_HP3_DATA_WIDTH : INTEGER;
C_M_AXI_GP0_THREAD_ID_WIDTH : INTEGER;
C_M_AXI_GP1_THREAD_ID_WIDTH : INTEGER;
C_NUM_F2P_INTR_INPUTS : INTEGER;
C_DQ_WIDTH : INTEGER;
C_DQS_WIDTH : INTEGER;
C_DM_WIDTH : INTEGER;
C_MIO_PRIMITIVE : INTEGER;
C_PS7_SI_REV : STRING;
C_FCLK_CLK0_BUF : STRING;
C_FCLK_CLK1_BUF : STRING;
C_FCLK_CLK2_BUF : STRING;
C_FCLK_CLK3_BUF : STRING;
C_PACKAGE_NAME : STRING
);
PORT (
CAN0_PHY_TX : OUT STD_LOGIC;
CAN0_PHY_RX : IN STD_LOGIC;
CAN1_PHY_TX : OUT STD_LOGIC;
CAN1_PHY_RX : IN STD_LOGIC;
ENET0_GMII_TX_EN : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ENET0_GMII_TX_ER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ENET0_MDIO_MDC : OUT STD_LOGIC;
ENET0_MDIO_O : OUT STD_LOGIC;
ENET0_MDIO_T : OUT STD_LOGIC;
ENET0_PTP_DELAY_REQ_RX : OUT STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : OUT STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : OUT STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : OUT STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : OUT STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : OUT STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : OUT STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : OUT STD_LOGIC;
ENET0_SOF_RX : OUT STD_LOGIC;
ENET0_SOF_TX : OUT STD_LOGIC;
ENET0_GMII_TXD : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
ENET0_GMII_COL : IN STD_LOGIC;
ENET0_GMII_CRS : IN STD_LOGIC;
ENET0_GMII_RX_CLK : IN STD_LOGIC;
ENET0_GMII_RX_DV : IN STD_LOGIC;
ENET0_GMII_RX_ER : IN STD_LOGIC;
ENET0_GMII_TX_CLK : IN STD_LOGIC;
ENET0_MDIO_I : IN STD_LOGIC;
ENET0_EXT_INTIN : IN STD_LOGIC;
ENET0_GMII_RXD : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ENET1_GMII_TX_EN : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ENET1_GMII_TX_ER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ENET1_MDIO_MDC : OUT STD_LOGIC;
ENET1_MDIO_O : OUT STD_LOGIC;
ENET1_MDIO_T : OUT STD_LOGIC;
ENET1_PTP_DELAY_REQ_RX : OUT STD_LOGIC;
ENET1_PTP_DELAY_REQ_TX : OUT STD_LOGIC;
ENET1_PTP_PDELAY_REQ_RX : OUT STD_LOGIC;
ENET1_PTP_PDELAY_REQ_TX : OUT STD_LOGIC;
ENET1_PTP_PDELAY_RESP_RX : OUT STD_LOGIC;
ENET1_PTP_PDELAY_RESP_TX : OUT STD_LOGIC;
ENET1_PTP_SYNC_FRAME_RX : OUT STD_LOGIC;
ENET1_PTP_SYNC_FRAME_TX : OUT STD_LOGIC;
ENET1_SOF_RX : OUT STD_LOGIC;
ENET1_SOF_TX : OUT STD_LOGIC;
ENET1_GMII_TXD : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
ENET1_GMII_COL : IN STD_LOGIC;
ENET1_GMII_CRS : IN STD_LOGIC;
ENET1_GMII_RX_CLK : IN STD_LOGIC;
ENET1_GMII_RX_DV : IN STD_LOGIC;
ENET1_GMII_RX_ER : IN STD_LOGIC;
ENET1_GMII_TX_CLK : IN STD_LOGIC;
ENET1_MDIO_I : IN STD_LOGIC;
ENET1_EXT_INTIN : IN STD_LOGIC;
ENET1_GMII_RXD : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
GPIO_I : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
GPIO_O : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
GPIO_T : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
I2C0_SDA_I : IN STD_LOGIC;
I2C0_SDA_O : OUT STD_LOGIC;
I2C0_SDA_T : OUT STD_LOGIC;
I2C0_SCL_I : IN STD_LOGIC;
I2C0_SCL_O : OUT STD_LOGIC;
I2C0_SCL_T : OUT STD_LOGIC;
I2C1_SDA_I : IN STD_LOGIC;
I2C1_SDA_O : OUT STD_LOGIC;
I2C1_SDA_T : OUT STD_LOGIC;
I2C1_SCL_I : IN STD_LOGIC;
I2C1_SCL_O : OUT STD_LOGIC;
I2C1_SCL_T : OUT STD_LOGIC;
PJTAG_TCK : IN STD_LOGIC;
PJTAG_TMS : IN STD_LOGIC;
PJTAG_TD_I : IN STD_LOGIC;
PJTAG_TD_T : OUT STD_LOGIC;
PJTAG_TD_O : OUT STD_LOGIC;
SDIO0_CLK : OUT STD_LOGIC;
SDIO0_CLK_FB : IN STD_LOGIC;
SDIO0_CMD_O : OUT STD_LOGIC;
SDIO0_CMD_I : IN STD_LOGIC;
SDIO0_CMD_T : OUT STD_LOGIC;
SDIO0_DATA_I : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
SDIO0_DATA_O : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
SDIO0_DATA_T : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
SDIO0_LED : OUT STD_LOGIC;
SDIO0_CDN : IN STD_LOGIC;
SDIO0_WP : IN STD_LOGIC;
SDIO0_BUSPOW : OUT STD_LOGIC;
SDIO0_BUSVOLT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
SDIO1_CLK : OUT STD_LOGIC;
SDIO1_CLK_FB : IN STD_LOGIC;
SDIO1_CMD_O : OUT STD_LOGIC;
SDIO1_CMD_I : IN STD_LOGIC;
SDIO1_CMD_T : OUT STD_LOGIC;
SDIO1_DATA_I : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
SDIO1_DATA_O : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
SDIO1_DATA_T : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
SDIO1_LED : OUT STD_LOGIC;
SDIO1_CDN : IN STD_LOGIC;
SDIO1_WP : IN STD_LOGIC;
SDIO1_BUSPOW : OUT STD_LOGIC;
SDIO1_BUSVOLT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
SPI0_SCLK_I : IN STD_LOGIC;
SPI0_SCLK_O : OUT STD_LOGIC;
SPI0_SCLK_T : OUT STD_LOGIC;
SPI0_MOSI_I : IN STD_LOGIC;
SPI0_MOSI_O : OUT STD_LOGIC;
SPI0_MOSI_T : OUT STD_LOGIC;
SPI0_MISO_I : IN STD_LOGIC;
SPI0_MISO_O : OUT STD_LOGIC;
SPI0_MISO_T : OUT STD_LOGIC;
SPI0_SS_I : IN STD_LOGIC;
SPI0_SS_O : OUT STD_LOGIC;
SPI0_SS1_O : OUT STD_LOGIC;
SPI0_SS2_O : OUT STD_LOGIC;
SPI0_SS_T : OUT STD_LOGIC;
SPI1_SCLK_I : IN STD_LOGIC;
SPI1_SCLK_O : OUT STD_LOGIC;
SPI1_SCLK_T : OUT STD_LOGIC;
SPI1_MOSI_I : IN STD_LOGIC;
SPI1_MOSI_O : OUT STD_LOGIC;
SPI1_MOSI_T : OUT STD_LOGIC;
SPI1_MISO_I : IN STD_LOGIC;
SPI1_MISO_O : OUT STD_LOGIC;
SPI1_MISO_T : OUT STD_LOGIC;
SPI1_SS_I : IN STD_LOGIC;
SPI1_SS_O : OUT STD_LOGIC;
SPI1_SS1_O : OUT STD_LOGIC;
SPI1_SS2_O : OUT STD_LOGIC;
SPI1_SS_T : OUT STD_LOGIC;
UART0_DTRN : OUT STD_LOGIC;
UART0_RTSN : OUT STD_LOGIC;
UART0_TX : OUT STD_LOGIC;
UART0_CTSN : IN STD_LOGIC;
UART0_DCDN : IN STD_LOGIC;
UART0_DSRN : IN STD_LOGIC;
UART0_RIN : IN STD_LOGIC;
UART0_RX : IN STD_LOGIC;
UART1_DTRN : OUT STD_LOGIC;
UART1_RTSN : OUT STD_LOGIC;
UART1_TX : OUT STD_LOGIC;
UART1_CTSN : IN STD_LOGIC;
UART1_DCDN : IN STD_LOGIC;
UART1_DSRN : IN STD_LOGIC;
UART1_RIN : IN STD_LOGIC;
UART1_RX : IN STD_LOGIC;
TTC0_WAVE0_OUT : OUT STD_LOGIC;
TTC0_WAVE1_OUT : OUT STD_LOGIC;
TTC0_WAVE2_OUT : OUT STD_LOGIC;
TTC0_CLK0_IN : IN STD_LOGIC;
TTC0_CLK1_IN : IN STD_LOGIC;
TTC0_CLK2_IN : IN STD_LOGIC;
TTC1_WAVE0_OUT : OUT STD_LOGIC;
TTC1_WAVE1_OUT : OUT STD_LOGIC;
TTC1_WAVE2_OUT : OUT STD_LOGIC;
TTC1_CLK0_IN : IN STD_LOGIC;
TTC1_CLK1_IN : IN STD_LOGIC;
TTC1_CLK2_IN : IN STD_LOGIC;
WDT_CLK_IN : IN STD_LOGIC;
WDT_RST_OUT : OUT STD_LOGIC;
TRACE_CLK : IN STD_LOGIC;
TRACE_CTL : OUT STD_LOGIC;
TRACE_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
USB0_PORT_INDCTL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
USB0_VBUS_PWRSELECT : OUT STD_LOGIC;
USB0_VBUS_PWRFAULT : IN STD_LOGIC;
USB1_PORT_INDCTL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
USB1_VBUS_PWRSELECT : OUT STD_LOGIC;
USB1_VBUS_PWRFAULT : IN STD_LOGIC;
SRAM_INTIN : IN STD_LOGIC;
M_AXI_GP0_ARVALID : OUT STD_LOGIC;
M_AXI_GP0_AWVALID : OUT STD_LOGIC;
M_AXI_GP0_BREADY : OUT STD_LOGIC;
M_AXI_GP0_RREADY : OUT STD_LOGIC;
M_AXI_GP0_WLAST : OUT STD_LOGIC;
M_AXI_GP0_WVALID : OUT STD_LOGIC;
M_AXI_GP0_ARID : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
M_AXI_GP0_AWID : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
M_AXI_GP0_WID : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
M_AXI_GP0_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_GP0_ARLOCK : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_GP0_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_GP0_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_GP0_AWLOCK : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_GP0_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_GP0_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_GP0_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_GP0_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_GP0_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_GP0_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_GP0_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_GP0_ARLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_GP0_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_GP0_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_GP0_AWLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_GP0_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_GP0_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_GP0_ACLK : IN STD_LOGIC;
M_AXI_GP0_ARREADY : IN STD_LOGIC;
M_AXI_GP0_AWREADY : IN STD_LOGIC;
M_AXI_GP0_BVALID : IN STD_LOGIC;
M_AXI_GP0_RLAST : IN STD_LOGIC;
M_AXI_GP0_RVALID : IN STD_LOGIC;
M_AXI_GP0_WREADY : IN STD_LOGIC;
M_AXI_GP0_BID : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
M_AXI_GP0_RID : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
M_AXI_GP0_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_GP0_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_GP0_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_GP1_ARVALID : OUT STD_LOGIC;
M_AXI_GP1_AWVALID : OUT STD_LOGIC;
M_AXI_GP1_BREADY : OUT STD_LOGIC;
M_AXI_GP1_RREADY : OUT STD_LOGIC;
M_AXI_GP1_WLAST : OUT STD_LOGIC;
M_AXI_GP1_WVALID : OUT STD_LOGIC;
M_AXI_GP1_ARID : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
M_AXI_GP1_AWID : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
M_AXI_GP1_WID : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
M_AXI_GP1_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_GP1_ARLOCK : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_GP1_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_GP1_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_GP1_AWLOCK : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_GP1_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_GP1_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_GP1_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_GP1_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_GP1_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_GP1_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_GP1_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_GP1_ARLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_GP1_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_GP1_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_GP1_AWLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_GP1_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_GP1_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_GP1_ACLK : IN STD_LOGIC;
M_AXI_GP1_ARREADY : IN STD_LOGIC;
M_AXI_GP1_AWREADY : IN STD_LOGIC;
M_AXI_GP1_BVALID : IN STD_LOGIC;
M_AXI_GP1_RLAST : IN STD_LOGIC;
M_AXI_GP1_RVALID : IN STD_LOGIC;
M_AXI_GP1_WREADY : IN STD_LOGIC;
M_AXI_GP1_BID : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
M_AXI_GP1_RID : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
M_AXI_GP1_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_GP1_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_GP1_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_GP0_ARREADY : OUT STD_LOGIC;
S_AXI_GP0_AWREADY : OUT STD_LOGIC;
S_AXI_GP0_BVALID : OUT STD_LOGIC;
S_AXI_GP0_RLAST : OUT STD_LOGIC;
S_AXI_GP0_RVALID : OUT STD_LOGIC;
S_AXI_GP0_WREADY : OUT STD_LOGIC;
S_AXI_GP0_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_GP0_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_GP0_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_GP0_BID : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
S_AXI_GP0_RID : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
S_AXI_GP0_ACLK : IN STD_LOGIC;
S_AXI_GP0_ARVALID : IN STD_LOGIC;
S_AXI_GP0_AWVALID : IN STD_LOGIC;
S_AXI_GP0_BREADY : IN STD_LOGIC;
S_AXI_GP0_RREADY : IN STD_LOGIC;
S_AXI_GP0_WLAST : IN STD_LOGIC;
S_AXI_GP0_WVALID : IN STD_LOGIC;
S_AXI_GP0_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_GP0_ARLOCK : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_GP0_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_GP0_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_GP0_AWLOCK : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_GP0_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_GP0_ARPROT : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_GP0_AWPROT : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_GP0_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_GP0_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_GP0_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_GP0_ARCACHE : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_GP0_ARLEN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_GP0_ARQOS : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_GP0_AWCACHE : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_GP0_AWLEN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_GP0_AWQOS : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_GP0_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_GP0_ARID : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
S_AXI_GP0_AWID : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
S_AXI_GP0_WID : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
S_AXI_GP1_ARREADY : OUT STD_LOGIC;
S_AXI_GP1_AWREADY : OUT STD_LOGIC;
S_AXI_GP1_BVALID : OUT STD_LOGIC;
S_AXI_GP1_RLAST : OUT STD_LOGIC;
S_AXI_GP1_RVALID : OUT STD_LOGIC;
S_AXI_GP1_WREADY : OUT STD_LOGIC;
S_AXI_GP1_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_GP1_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_GP1_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_GP1_BID : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
S_AXI_GP1_RID : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
S_AXI_GP1_ACLK : IN STD_LOGIC;
S_AXI_GP1_ARVALID : IN STD_LOGIC;
S_AXI_GP1_AWVALID : IN STD_LOGIC;
S_AXI_GP1_BREADY : IN STD_LOGIC;
S_AXI_GP1_RREADY : IN STD_LOGIC;
S_AXI_GP1_WLAST : IN STD_LOGIC;
S_AXI_GP1_WVALID : IN STD_LOGIC;
S_AXI_GP1_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_GP1_ARLOCK : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_GP1_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_GP1_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_GP1_AWLOCK : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_GP1_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_GP1_ARPROT : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_GP1_AWPROT : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_GP1_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_GP1_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_GP1_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_GP1_ARCACHE : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_GP1_ARLEN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_GP1_ARQOS : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_GP1_AWCACHE : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_GP1_AWLEN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_GP1_AWQOS : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_GP1_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_GP1_ARID : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
S_AXI_GP1_AWID : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
S_AXI_GP1_WID : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
S_AXI_ACP_ARREADY : OUT STD_LOGIC;
S_AXI_ACP_AWREADY : OUT STD_LOGIC;
S_AXI_ACP_BVALID : OUT STD_LOGIC;
S_AXI_ACP_RLAST : OUT STD_LOGIC;
S_AXI_ACP_RVALID : OUT STD_LOGIC;
S_AXI_ACP_WREADY : OUT STD_LOGIC;
S_AXI_ACP_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ACP_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ACP_BID : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ACP_RID : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ACP_RDATA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
S_AXI_ACP_ACLK : IN STD_LOGIC;
S_AXI_ACP_ARVALID : IN STD_LOGIC;
S_AXI_ACP_AWVALID : IN STD_LOGIC;
S_AXI_ACP_BREADY : IN STD_LOGIC;
S_AXI_ACP_RREADY : IN STD_LOGIC;
S_AXI_ACP_WLAST : IN STD_LOGIC;
S_AXI_ACP_WVALID : IN STD_LOGIC;
S_AXI_ACP_ARID : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ACP_ARPROT : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ACP_AWID : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ACP_AWPROT : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ACP_WID : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ACP_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ACP_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ACP_ARCACHE : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ACP_ARLEN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ACP_ARQOS : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ACP_AWCACHE : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ACP_AWLEN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ACP_AWQOS : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ACP_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ACP_ARLOCK : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ACP_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ACP_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ACP_AWLOCK : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ACP_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ACP_ARUSER : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
S_AXI_ACP_AWUSER : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
S_AXI_ACP_WDATA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
S_AXI_ACP_WSTRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_HP0_ARREADY : OUT STD_LOGIC;
S_AXI_HP0_AWREADY : OUT STD_LOGIC;
S_AXI_HP0_BVALID : OUT STD_LOGIC;
S_AXI_HP0_RLAST : OUT STD_LOGIC;
S_AXI_HP0_RVALID : OUT STD_LOGIC;
S_AXI_HP0_WREADY : OUT STD_LOGIC;
S_AXI_HP0_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_HP0_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_HP0_BID : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
S_AXI_HP0_RID : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
S_AXI_HP0_RDATA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
S_AXI_HP0_RCOUNT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_HP0_WCOUNT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_HP0_RACOUNT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_HP0_WACOUNT : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
S_AXI_HP0_ACLK : IN STD_LOGIC;
S_AXI_HP0_ARVALID : IN STD_LOGIC;
S_AXI_HP0_AWVALID : IN STD_LOGIC;
S_AXI_HP0_BREADY : IN STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : IN STD_LOGIC;
S_AXI_HP0_RREADY : IN STD_LOGIC;
S_AXI_HP0_WLAST : IN STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : IN STD_LOGIC;
S_AXI_HP0_WVALID : IN STD_LOGIC;
S_AXI_HP0_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_HP0_ARLOCK : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_HP0_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_HP0_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_HP0_AWLOCK : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_HP0_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_HP0_ARPROT : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_HP0_AWPROT : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_HP0_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_HP0_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_HP0_ARCACHE : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_HP0_ARLEN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_HP0_ARQOS : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_HP0_AWCACHE : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_HP0_AWLEN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_HP0_AWQOS : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_HP0_ARID : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
S_AXI_HP0_AWID : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
S_AXI_HP0_WID : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
S_AXI_HP0_WDATA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
S_AXI_HP0_WSTRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_HP1_ARREADY : OUT STD_LOGIC;
S_AXI_HP1_AWREADY : OUT STD_LOGIC;
S_AXI_HP1_BVALID : OUT STD_LOGIC;
S_AXI_HP1_RLAST : OUT STD_LOGIC;
S_AXI_HP1_RVALID : OUT STD_LOGIC;
S_AXI_HP1_WREADY : OUT STD_LOGIC;
S_AXI_HP1_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_HP1_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_HP1_BID : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
S_AXI_HP1_RID : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
S_AXI_HP1_RDATA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
S_AXI_HP1_RCOUNT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_HP1_WCOUNT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_HP1_RACOUNT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_HP1_WACOUNT : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
S_AXI_HP1_ACLK : IN STD_LOGIC;
S_AXI_HP1_ARVALID : IN STD_LOGIC;
S_AXI_HP1_AWVALID : IN STD_LOGIC;
S_AXI_HP1_BREADY : IN STD_LOGIC;
S_AXI_HP1_RDISSUECAP1_EN : IN STD_LOGIC;
S_AXI_HP1_RREADY : IN STD_LOGIC;
S_AXI_HP1_WLAST : IN STD_LOGIC;
S_AXI_HP1_WRISSUECAP1_EN : IN STD_LOGIC;
S_AXI_HP1_WVALID : IN STD_LOGIC;
S_AXI_HP1_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_HP1_ARLOCK : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_HP1_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_HP1_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_HP1_AWLOCK : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_HP1_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_HP1_ARPROT : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_HP1_AWPROT : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_HP1_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_HP1_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_HP1_ARCACHE : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_HP1_ARLEN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_HP1_ARQOS : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_HP1_AWCACHE : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_HP1_AWLEN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_HP1_AWQOS : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_HP1_ARID : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
S_AXI_HP1_AWID : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
S_AXI_HP1_WID : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
S_AXI_HP1_WDATA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
S_AXI_HP1_WSTRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_HP2_ARREADY : OUT STD_LOGIC;
S_AXI_HP2_AWREADY : OUT STD_LOGIC;
S_AXI_HP2_BVALID : OUT STD_LOGIC;
S_AXI_HP2_RLAST : OUT STD_LOGIC;
S_AXI_HP2_RVALID : OUT STD_LOGIC;
S_AXI_HP2_WREADY : OUT STD_LOGIC;
S_AXI_HP2_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_HP2_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_HP2_BID : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
S_AXI_HP2_RID : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
S_AXI_HP2_RDATA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
S_AXI_HP2_RCOUNT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_HP2_WCOUNT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_HP2_RACOUNT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_HP2_WACOUNT : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
S_AXI_HP2_ACLK : IN STD_LOGIC;
S_AXI_HP2_ARVALID : IN STD_LOGIC;
S_AXI_HP2_AWVALID : IN STD_LOGIC;
S_AXI_HP2_BREADY : IN STD_LOGIC;
S_AXI_HP2_RDISSUECAP1_EN : IN STD_LOGIC;
S_AXI_HP2_RREADY : IN STD_LOGIC;
S_AXI_HP2_WLAST : IN STD_LOGIC;
S_AXI_HP2_WRISSUECAP1_EN : IN STD_LOGIC;
S_AXI_HP2_WVALID : IN STD_LOGIC;
S_AXI_HP2_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_HP2_ARLOCK : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_HP2_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_HP2_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_HP2_AWLOCK : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_HP2_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_HP2_ARPROT : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_HP2_AWPROT : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_HP2_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_HP2_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_HP2_ARCACHE : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_HP2_ARLEN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_HP2_ARQOS : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_HP2_AWCACHE : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_HP2_AWLEN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_HP2_AWQOS : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_HP2_ARID : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
S_AXI_HP2_AWID : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
S_AXI_HP2_WID : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
S_AXI_HP2_WDATA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
S_AXI_HP2_WSTRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_HP3_ARREADY : OUT STD_LOGIC;
S_AXI_HP3_AWREADY : OUT STD_LOGIC;
S_AXI_HP3_BVALID : OUT STD_LOGIC;
S_AXI_HP3_RLAST : OUT STD_LOGIC;
S_AXI_HP3_RVALID : OUT STD_LOGIC;
S_AXI_HP3_WREADY : OUT STD_LOGIC;
S_AXI_HP3_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_HP3_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_HP3_BID : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
S_AXI_HP3_RID : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
S_AXI_HP3_RDATA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
S_AXI_HP3_RCOUNT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_HP3_WCOUNT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_HP3_RACOUNT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_HP3_WACOUNT : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
S_AXI_HP3_ACLK : IN STD_LOGIC;
S_AXI_HP3_ARVALID : IN STD_LOGIC;
S_AXI_HP3_AWVALID : IN STD_LOGIC;
S_AXI_HP3_BREADY : IN STD_LOGIC;
S_AXI_HP3_RDISSUECAP1_EN : IN STD_LOGIC;
S_AXI_HP3_RREADY : IN STD_LOGIC;
S_AXI_HP3_WLAST : IN STD_LOGIC;
S_AXI_HP3_WRISSUECAP1_EN : IN STD_LOGIC;
S_AXI_HP3_WVALID : IN STD_LOGIC;
S_AXI_HP3_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_HP3_ARLOCK : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_HP3_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_HP3_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_HP3_AWLOCK : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_HP3_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_HP3_ARPROT : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_HP3_AWPROT : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_HP3_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_HP3_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_HP3_ARCACHE : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_HP3_ARLEN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_HP3_ARQOS : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_HP3_AWCACHE : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_HP3_AWLEN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_HP3_AWQOS : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_HP3_ARID : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
S_AXI_HP3_AWID : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
S_AXI_HP3_WID : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
S_AXI_HP3_WDATA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
S_AXI_HP3_WSTRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
IRQ_P2F_DMAC_ABORT : OUT STD_LOGIC;
IRQ_P2F_DMAC0 : OUT STD_LOGIC;
IRQ_P2F_DMAC1 : OUT STD_LOGIC;
IRQ_P2F_DMAC2 : OUT STD_LOGIC;
IRQ_P2F_DMAC3 : OUT STD_LOGIC;
IRQ_P2F_DMAC4 : OUT STD_LOGIC;
IRQ_P2F_DMAC5 : OUT STD_LOGIC;
IRQ_P2F_DMAC6 : OUT STD_LOGIC;
IRQ_P2F_DMAC7 : OUT STD_LOGIC;
IRQ_P2F_SMC : OUT STD_LOGIC;
IRQ_P2F_QSPI : OUT STD_LOGIC;
IRQ_P2F_CTI : OUT STD_LOGIC;
IRQ_P2F_GPIO : OUT STD_LOGIC;
IRQ_P2F_USB0 : OUT STD_LOGIC;
IRQ_P2F_ENET0 : OUT STD_LOGIC;
IRQ_P2F_ENET_WAKE0 : OUT STD_LOGIC;
IRQ_P2F_SDIO0 : OUT STD_LOGIC;
IRQ_P2F_I2C0 : OUT STD_LOGIC;
IRQ_P2F_SPI0 : OUT STD_LOGIC;
IRQ_P2F_UART0 : OUT STD_LOGIC;
IRQ_P2F_CAN0 : OUT STD_LOGIC;
IRQ_P2F_USB1 : OUT STD_LOGIC;
IRQ_P2F_ENET1 : OUT STD_LOGIC;
IRQ_P2F_ENET_WAKE1 : OUT STD_LOGIC;
IRQ_P2F_SDIO1 : OUT STD_LOGIC;
IRQ_P2F_I2C1 : OUT STD_LOGIC;
IRQ_P2F_SPI1 : OUT STD_LOGIC;
IRQ_P2F_UART1 : OUT STD_LOGIC;
IRQ_P2F_CAN1 : OUT STD_LOGIC;
IRQ_F2P : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Core0_nFIQ : IN STD_LOGIC;
Core0_nIRQ : IN STD_LOGIC;
Core1_nFIQ : IN STD_LOGIC;
Core1_nIRQ : IN STD_LOGIC;
DMA0_DATYPE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
DMA0_DAVALID : OUT STD_LOGIC;
DMA0_DRREADY : OUT STD_LOGIC;
DMA1_DATYPE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
DMA1_DAVALID : OUT STD_LOGIC;
DMA1_DRREADY : OUT STD_LOGIC;
DMA2_DATYPE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
DMA2_DAVALID : OUT STD_LOGIC;
DMA2_DRREADY : OUT STD_LOGIC;
DMA3_DATYPE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
DMA3_DAVALID : OUT STD_LOGIC;
DMA3_DRREADY : OUT STD_LOGIC;
DMA0_ACLK : IN STD_LOGIC;
DMA0_DAREADY : IN STD_LOGIC;
DMA0_DRLAST : IN STD_LOGIC;
DMA0_DRVALID : IN STD_LOGIC;
DMA1_ACLK : IN STD_LOGIC;
DMA1_DAREADY : IN STD_LOGIC;
DMA1_DRLAST : IN STD_LOGIC;
DMA1_DRVALID : IN STD_LOGIC;
DMA2_ACLK : IN STD_LOGIC;
DMA2_DAREADY : IN STD_LOGIC;
DMA2_DRLAST : IN STD_LOGIC;
DMA2_DRVALID : IN STD_LOGIC;
DMA3_ACLK : IN STD_LOGIC;
DMA3_DAREADY : IN STD_LOGIC;
DMA3_DRLAST : IN STD_LOGIC;
DMA3_DRVALID : IN STD_LOGIC;
DMA0_DRTYPE : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
DMA1_DRTYPE : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
DMA2_DRTYPE : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
DMA3_DRTYPE : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
FCLK_CLK0 : OUT STD_LOGIC;
FCLK_CLK1 : OUT STD_LOGIC;
FCLK_CLK2 : OUT STD_LOGIC;
FCLK_CLK3 : OUT STD_LOGIC;
FCLK_CLKTRIG0_N : IN STD_LOGIC;
FCLK_CLKTRIG1_N : IN STD_LOGIC;
FCLK_CLKTRIG2_N : IN STD_LOGIC;
FCLK_CLKTRIG3_N : IN STD_LOGIC;
FCLK_RESET0_N : OUT STD_LOGIC;
FCLK_RESET1_N : OUT STD_LOGIC;
FCLK_RESET2_N : OUT STD_LOGIC;
FCLK_RESET3_N : OUT STD_LOGIC;
FTMD_TRACEIN_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
FTMD_TRACEIN_VALID : IN STD_LOGIC;
FTMD_TRACEIN_CLK : IN STD_LOGIC;
FTMD_TRACEIN_ATID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
FTMT_F2P_TRIG : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
FTMT_F2P_TRIGACK : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
FTMT_F2P_DEBUG : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
FTMT_P2F_TRIGACK : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
FTMT_P2F_TRIG : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
FTMT_P2F_DEBUG : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
FPGA_IDLE_N : IN STD_LOGIC;
EVENT_EVENTO : OUT STD_LOGIC;
EVENT_STANDBYWFE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
EVENT_STANDBYWFI : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
EVENT_EVENTI : IN STD_LOGIC;
DDR_ARB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
MIO : INOUT STD_LOGIC_VECTOR(53 DOWNTO 0);
DDR_CAS_n : INOUT STD_LOGIC;
DDR_CKE : INOUT STD_LOGIC;
DDR_Clk_n : INOUT STD_LOGIC;
DDR_Clk : INOUT STD_LOGIC;
DDR_CS_n : INOUT STD_LOGIC;
DDR_DRSTB : INOUT STD_LOGIC;
DDR_ODT : INOUT STD_LOGIC;
DDR_RAS_n : INOUT STD_LOGIC;
DDR_WEB : INOUT STD_LOGIC;
DDR_BankAddr : INOUT STD_LOGIC_VECTOR(2 DOWNTO 0);
DDR_Addr : INOUT STD_LOGIC_VECTOR(14 DOWNTO 0);
DDR_VRN : INOUT STD_LOGIC;
DDR_VRP : INOUT STD_LOGIC;
DDR_DM : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0);
DDR_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DDR_DQS_n : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0);
DDR_DQS : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0);
PS_SRSTB : INOUT STD_LOGIC;
PS_CLK : INOUT STD_LOGIC;
PS_PORB : INOUT STD_LOGIC
);
END COMPONENT processing_system7_v5_3_processing_system7;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ZynqDesign_processing_system7_0_0_arch: ARCHITECTURE IS "processing_system7_v5_3_processing_system7,Vivado 2013.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ZynqDesign_processing_system7_0_0_arch : ARCHITECTURE IS "ZynqDesign_processing_system7_0_0,processing_system7_v5_3_processing_system7,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ZynqDesign_processing_system7_0_0_arch: ARCHITECTURE IS "ZynqDesign_processing_system7_0_0,processing_system7_v5_3_processing_system7,{x_ipProduct=Vivado 2013.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=processing_system7,x_ipVersion=5.3,x_ipCoreRevision=1,x_ipLanguage=VHDL,C_EN_EMIO_ENET0=0,C_EN_EMIO_ENET1=0,C_EN_EMIO_TRACE=0,C_INCLUDE_TRACE_BUFFER=0,C_TRACE_BUFFER_FIFO_SIZE=128,USE_TRACE_DATA_EDGE_DETECTOR=0,C_TRACE_BUFFER_CLOCK_DELAY=12,C_EMIO_GPIO_WIDTH=64,C_INCLUDE_ACP_TRANS_CHECK=0,C_USE_DEFAULT_ACP_USER_VAL=0,C_S_AXI_ACP_ARUSER_VAL=31,C_S_AXI_ACP_AWUSER_VAL=31,C_M_AXI_GP0_ID_WIDTH=12,C_M_AXI_GP0_ENABLE_STATIC_REMAP=0,C_M_AXI_GP1_ID_WIDTH=12,C_M_AXI_GP1_ENABLE_STATIC_REMAP=0,C_S_AXI_GP0_ID_WIDTH=6,C_S_AXI_GP1_ID_WIDTH=6,C_S_AXI_ACP_ID_WIDTH=3,C_S_AXI_HP0_ID_WIDTH=6,C_S_AXI_HP0_DATA_WIDTH=64,C_S_AXI_HP1_ID_WIDTH=6,C_S_AXI_HP1_DATA_WIDTH=64,C_S_AXI_HP2_ID_WIDTH=6,C_S_AXI_HP2_DATA_WIDTH=64,C_S_AXI_HP3_ID_WIDTH=6,C_S_AXI_HP3_DATA_WIDTH=64,C_M_AXI_GP0_THREAD_ID_WIDTH=12,C_M_AXI_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=1,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=true,C_FCLK_CLK1_BUF=false,C_FCLK_CLK2_BUF=false,C_FCLK_CLK3_BUF=false,C_PACKAGE_NAME=clg484}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF USB0_PORT_INDCTL: SIGNAL IS "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL";
ATTRIBUTE X_INTERFACE_INFO OF USB0_VBUS_PWRSELECT: SIGNAL IS "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT";
ATTRIBUTE X_INTERFACE_INFO OF USB0_VBUS_PWRFAULT: SIGNAL IS "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_GP0_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_GP0_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_GP0_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_GP0_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_GP0_WLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_GP0_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_GP0_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_GP0_AWID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_GP0_WID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_GP0_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_GP0_ARLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_GP0_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_GP0_AWBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_GP0_AWLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_GP0_AWSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_GP0_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_GP0_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_GP0_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_GP0_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_GP0_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_GP0_ARCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_GP0_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_GP0_ARQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_GP0_AWCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_GP0_AWLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_GP0_AWQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_GP0_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_GP0_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_GP0_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_GP0_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_GP0_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_GP0_RLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_GP0_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_GP0_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_GP0_BID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_GP0_RID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_GP0_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_GP0_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_GP0_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA";
ATTRIBUTE X_INTERFACE_INFO OF FCLK_CLK0: SIGNAL IS "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK";
ATTRIBUTE X_INTERFACE_INFO OF FCLK_RESET0_N: SIGNAL IS "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST";
ATTRIBUTE X_INTERFACE_INFO OF MIO: SIGNAL IS "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO";
ATTRIBUTE X_INTERFACE_INFO OF DDR_CAS_n: SIGNAL IS "xilinx.com:interface:ddrx:1.0 DDR CAS_N";
ATTRIBUTE X_INTERFACE_INFO OF DDR_CKE: SIGNAL IS "xilinx.com:interface:ddrx:1.0 DDR CKE";
ATTRIBUTE X_INTERFACE_INFO OF DDR_Clk_n: SIGNAL IS "xilinx.com:interface:ddrx:1.0 DDR CK_N";
ATTRIBUTE X_INTERFACE_INFO OF DDR_Clk: SIGNAL IS "xilinx.com:interface:ddrx:1.0 DDR CK_P";
ATTRIBUTE X_INTERFACE_INFO OF DDR_CS_n: SIGNAL IS "xilinx.com:interface:ddrx:1.0 DDR CS_N";
ATTRIBUTE X_INTERFACE_INFO OF DDR_DRSTB: SIGNAL IS "xilinx.com:interface:ddrx:1.0 DDR RESET_N";
ATTRIBUTE X_INTERFACE_INFO OF DDR_ODT: SIGNAL IS "xilinx.com:interface:ddrx:1.0 DDR ODT";
ATTRIBUTE X_INTERFACE_INFO OF DDR_RAS_n: SIGNAL IS "xilinx.com:interface:ddrx:1.0 DDR RAS_N";
ATTRIBUTE X_INTERFACE_INFO OF DDR_WEB: SIGNAL IS "xilinx.com:interface:ddrx:1.0 DDR WE_N";
ATTRIBUTE X_INTERFACE_INFO OF DDR_BankAddr: SIGNAL IS "xilinx.com:interface:ddrx:1.0 DDR BA";
ATTRIBUTE X_INTERFACE_INFO OF DDR_Addr: SIGNAL IS "xilinx.com:interface:ddrx:1.0 DDR ADDR";
ATTRIBUTE X_INTERFACE_INFO OF DDR_VRN: SIGNAL IS "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN";
ATTRIBUTE X_INTERFACE_INFO OF DDR_VRP: SIGNAL IS "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP";
ATTRIBUTE X_INTERFACE_INFO OF DDR_DM: SIGNAL IS "xilinx.com:interface:ddrx:1.0 DDR DM";
ATTRIBUTE X_INTERFACE_INFO OF DDR_DQ: SIGNAL IS "xilinx.com:interface:ddrx:1.0 DDR DQ";
ATTRIBUTE X_INTERFACE_INFO OF DDR_DQS_n: SIGNAL IS "xilinx.com:interface:ddrx:1.0 DDR DQS_N";
ATTRIBUTE X_INTERFACE_INFO OF DDR_DQS: SIGNAL IS "xilinx.com:interface:ddrx:1.0 DDR DQS_P";
ATTRIBUTE X_INTERFACE_INFO OF PS_SRSTB: SIGNAL IS "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB";
ATTRIBUTE X_INTERFACE_INFO OF PS_CLK: SIGNAL IS "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK";
ATTRIBUTE X_INTERFACE_INFO OF PS_PORB: SIGNAL IS "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB";
BEGIN
U0 : processing_system7_v5_3_processing_system7
GENERIC MAP (
C_EN_EMIO_ENET0 => 0,
C_EN_EMIO_ENET1 => 0,
C_EN_EMIO_TRACE => 0,
C_INCLUDE_TRACE_BUFFER => 0,
C_TRACE_BUFFER_FIFO_SIZE => 128,
USE_TRACE_DATA_EDGE_DETECTOR => 0,
C_TRACE_BUFFER_CLOCK_DELAY => 12,
C_EMIO_GPIO_WIDTH => 64,
C_INCLUDE_ACP_TRANS_CHECK => 0,
C_USE_DEFAULT_ACP_USER_VAL => 0,
C_S_AXI_ACP_ARUSER_VAL => 31,
C_S_AXI_ACP_AWUSER_VAL => 31,
C_M_AXI_GP0_ID_WIDTH => 12,
C_M_AXI_GP0_ENABLE_STATIC_REMAP => 0,
C_M_AXI_GP1_ID_WIDTH => 12,
C_M_AXI_GP1_ENABLE_STATIC_REMAP => 0,
C_S_AXI_GP0_ID_WIDTH => 6,
C_S_AXI_GP1_ID_WIDTH => 6,
C_S_AXI_ACP_ID_WIDTH => 3,
C_S_AXI_HP0_ID_WIDTH => 6,
C_S_AXI_HP0_DATA_WIDTH => 64,
C_S_AXI_HP1_ID_WIDTH => 6,
C_S_AXI_HP1_DATA_WIDTH => 64,
C_S_AXI_HP2_ID_WIDTH => 6,
C_S_AXI_HP2_DATA_WIDTH => 64,
C_S_AXI_HP3_ID_WIDTH => 6,
C_S_AXI_HP3_DATA_WIDTH => 64,
C_M_AXI_GP0_THREAD_ID_WIDTH => 12,
C_M_AXI_GP1_THREAD_ID_WIDTH => 12,
C_NUM_F2P_INTR_INPUTS => 1,
C_DQ_WIDTH => 32,
C_DQS_WIDTH => 4,
C_DM_WIDTH => 4,
C_MIO_PRIMITIVE => 54,
C_PS7_SI_REV => "PRODUCTION",
C_FCLK_CLK0_BUF => "true",
C_FCLK_CLK1_BUF => "false",
C_FCLK_CLK2_BUF => "false",
C_FCLK_CLK3_BUF => "false",
C_PACKAGE_NAME => "clg484"
)
PORT MAP (
CAN0_PHY_RX => '0',
CAN1_PHY_RX => '0',
ENET0_GMII_COL => '0',
ENET0_GMII_CRS => '0',
ENET0_GMII_RX_CLK => '0',
ENET0_GMII_RX_DV => '0',
ENET0_GMII_RX_ER => '0',
ENET0_GMII_TX_CLK => '0',
ENET0_MDIO_I => '0',
ENET0_EXT_INTIN => '0',
ENET0_GMII_RXD => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
ENET1_GMII_COL => '0',
ENET1_GMII_CRS => '0',
ENET1_GMII_RX_CLK => '0',
ENET1_GMII_RX_DV => '0',
ENET1_GMII_RX_ER => '0',
ENET1_GMII_TX_CLK => '0',
ENET1_MDIO_I => '0',
ENET1_EXT_INTIN => '0',
ENET1_GMII_RXD => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
GPIO_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
I2C0_SDA_I => '0',
I2C0_SCL_I => '0',
I2C1_SDA_I => '0',
I2C1_SCL_I => '0',
PJTAG_TCK => '0',
PJTAG_TMS => '0',
PJTAG_TD_I => '0',
SDIO0_CLK_FB => '0',
SDIO0_CMD_I => '0',
SDIO0_DATA_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
SDIO0_CDN => '0',
SDIO0_WP => '0',
SDIO1_CLK_FB => '0',
SDIO1_CMD_I => '0',
SDIO1_DATA_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
SDIO1_CDN => '0',
SDIO1_WP => '0',
SPI0_SCLK_I => '0',
SPI0_MOSI_I => '0',
SPI0_MISO_I => '0',
SPI0_SS_I => '0',
SPI1_SCLK_I => '0',
SPI1_MOSI_I => '0',
SPI1_MISO_I => '0',
SPI1_SS_I => '0',
UART0_CTSN => '0',
UART0_DCDN => '0',
UART0_DSRN => '0',
UART0_RIN => '0',
UART0_RX => '0',
UART1_CTSN => '0',
UART1_DCDN => '0',
UART1_DSRN => '0',
UART1_RIN => '0',
UART1_RX => '0',
TTC0_CLK0_IN => '0',
TTC0_CLK1_IN => '0',
TTC0_CLK2_IN => '0',
TTC1_CLK0_IN => '0',
TTC1_CLK1_IN => '0',
TTC1_CLK2_IN => '0',
WDT_CLK_IN => '0',
TRACE_CLK => '0',
USB0_PORT_INDCTL => USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT,
USB1_VBUS_PWRFAULT => '0',
SRAM_INTIN => '0',
M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY => M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY => M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST => M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID => M_AXI_GP0_WVALID,
M_AXI_GP0_ARID => M_AXI_GP0_ARID,
M_AXI_GP0_AWID => M_AXI_GP0_AWID,
M_AXI_GP0_WID => M_AXI_GP0_WID,
M_AXI_GP0_ARBURST => M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK => M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE => M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST => M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK => M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE => M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT => M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT => M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR => M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR => M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA => M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE => M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN => M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS => M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE => M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN => M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS => M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB => M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK => M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID => M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST => M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID => M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY => M_AXI_GP0_WREADY,
M_AXI_GP0_BID => M_AXI_GP0_BID,
M_AXI_GP0_RID => M_AXI_GP0_RID,
M_AXI_GP0_BRESP => M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP => M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA => M_AXI_GP0_RDATA,
M_AXI_GP1_ACLK => '0',
M_AXI_GP1_ARREADY => '0',
M_AXI_GP1_AWREADY => '0',
M_AXI_GP1_BVALID => '0',
M_AXI_GP1_RLAST => '0',
M_AXI_GP1_RVALID => '0',
M_AXI_GP1_WREADY => '0',
M_AXI_GP1_BID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
M_AXI_GP1_RID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
M_AXI_GP1_BRESP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
M_AXI_GP1_RRESP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
M_AXI_GP1_RDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_GP0_ACLK => '0',
S_AXI_GP0_ARVALID => '0',
S_AXI_GP0_AWVALID => '0',
S_AXI_GP0_BREADY => '0',
S_AXI_GP0_RREADY => '0',
S_AXI_GP0_WLAST => '0',
S_AXI_GP0_WVALID => '0',
S_AXI_GP0_ARBURST => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
S_AXI_GP0_ARLOCK => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
S_AXI_GP0_ARSIZE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
S_AXI_GP0_AWBURST => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
S_AXI_GP0_AWLOCK => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
S_AXI_GP0_AWSIZE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
S_AXI_GP0_ARPROT => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
S_AXI_GP0_AWPROT => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
S_AXI_GP0_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_GP0_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_GP0_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_GP0_ARCACHE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_GP0_ARLEN => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_GP0_ARQOS => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_GP0_AWCACHE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_GP0_AWLEN => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_GP0_AWQOS => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_GP0_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_GP0_ARID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
S_AXI_GP0_AWID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
S_AXI_GP0_WID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
S_AXI_GP1_ACLK => '0',
S_AXI_GP1_ARVALID => '0',
S_AXI_GP1_AWVALID => '0',
S_AXI_GP1_BREADY => '0',
S_AXI_GP1_RREADY => '0',
S_AXI_GP1_WLAST => '0',
S_AXI_GP1_WVALID => '0',
S_AXI_GP1_ARBURST => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
S_AXI_GP1_ARLOCK => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
S_AXI_GP1_ARSIZE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
S_AXI_GP1_AWBURST => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
S_AXI_GP1_AWLOCK => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
S_AXI_GP1_AWSIZE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
S_AXI_GP1_ARPROT => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
S_AXI_GP1_AWPROT => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
S_AXI_GP1_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_GP1_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_GP1_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_GP1_ARCACHE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_GP1_ARLEN => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_GP1_ARQOS => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_GP1_AWCACHE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_GP1_AWLEN => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_GP1_AWQOS => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_GP1_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_GP1_ARID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
S_AXI_GP1_AWID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
S_AXI_GP1_WID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
S_AXI_ACP_ACLK => '0',
S_AXI_ACP_ARVALID => '0',
S_AXI_ACP_AWVALID => '0',
S_AXI_ACP_BREADY => '0',
S_AXI_ACP_RREADY => '0',
S_AXI_ACP_WLAST => '0',
S_AXI_ACP_WVALID => '0',
S_AXI_ACP_ARID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
S_AXI_ACP_ARPROT => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
S_AXI_ACP_AWID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
S_AXI_ACP_AWPROT => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
S_AXI_ACP_WID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
S_AXI_ACP_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_ACP_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_ACP_ARCACHE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_ACP_ARLEN => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_ACP_ARQOS => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_ACP_AWCACHE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_ACP_AWLEN => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_ACP_AWQOS => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_ACP_ARBURST => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
S_AXI_ACP_ARLOCK => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
S_AXI_ACP_ARSIZE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
S_AXI_ACP_AWBURST => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
S_AXI_ACP_AWLOCK => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
S_AXI_ACP_AWSIZE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
S_AXI_ACP_ARUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
S_AXI_ACP_AWUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
S_AXI_ACP_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
S_AXI_ACP_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
S_AXI_HP0_ACLK => '0',
S_AXI_HP0_ARVALID => '0',
S_AXI_HP0_AWVALID => '0',
S_AXI_HP0_BREADY => '0',
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RREADY => '0',
S_AXI_HP0_WLAST => '0',
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WVALID => '0',
S_AXI_HP0_ARBURST => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
S_AXI_HP0_ARLOCK => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
S_AXI_HP0_ARSIZE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
S_AXI_HP0_AWBURST => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
S_AXI_HP0_AWLOCK => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
S_AXI_HP0_AWSIZE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
S_AXI_HP0_ARPROT => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
S_AXI_HP0_AWPROT => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
S_AXI_HP0_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_HP0_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_HP0_ARCACHE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_HP0_ARLEN => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_HP0_ARQOS => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_HP0_AWCACHE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_HP0_AWLEN => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_HP0_AWQOS => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_HP0_ARID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
S_AXI_HP0_AWID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
S_AXI_HP0_WID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
S_AXI_HP0_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
S_AXI_HP0_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
S_AXI_HP1_ACLK => '0',
S_AXI_HP1_ARVALID => '0',
S_AXI_HP1_AWVALID => '0',
S_AXI_HP1_BREADY => '0',
S_AXI_HP1_RDISSUECAP1_EN => '0',
S_AXI_HP1_RREADY => '0',
S_AXI_HP1_WLAST => '0',
S_AXI_HP1_WRISSUECAP1_EN => '0',
S_AXI_HP1_WVALID => '0',
S_AXI_HP1_ARBURST => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
S_AXI_HP1_ARLOCK => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
S_AXI_HP1_ARSIZE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
S_AXI_HP1_AWBURST => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
S_AXI_HP1_AWLOCK => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
S_AXI_HP1_AWSIZE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
S_AXI_HP1_ARPROT => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
S_AXI_HP1_AWPROT => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
S_AXI_HP1_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_HP1_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_HP1_ARCACHE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_HP1_ARLEN => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_HP1_ARQOS => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_HP1_AWCACHE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_HP1_AWLEN => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_HP1_AWQOS => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_HP1_ARID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
S_AXI_HP1_AWID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
S_AXI_HP1_WID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
S_AXI_HP1_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
S_AXI_HP1_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
S_AXI_HP2_ACLK => '0',
S_AXI_HP2_ARVALID => '0',
S_AXI_HP2_AWVALID => '0',
S_AXI_HP2_BREADY => '0',
S_AXI_HP2_RDISSUECAP1_EN => '0',
S_AXI_HP2_RREADY => '0',
S_AXI_HP2_WLAST => '0',
S_AXI_HP2_WRISSUECAP1_EN => '0',
S_AXI_HP2_WVALID => '0',
S_AXI_HP2_ARBURST => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
S_AXI_HP2_ARLOCK => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
S_AXI_HP2_ARSIZE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
S_AXI_HP2_AWBURST => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
S_AXI_HP2_AWLOCK => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
S_AXI_HP2_AWSIZE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
S_AXI_HP2_ARPROT => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
S_AXI_HP2_AWPROT => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
S_AXI_HP2_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_HP2_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_HP2_ARCACHE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_HP2_ARLEN => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_HP2_ARQOS => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_HP2_AWCACHE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_HP2_AWLEN => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_HP2_AWQOS => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_HP2_ARID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
S_AXI_HP2_AWID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
S_AXI_HP2_WID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
S_AXI_HP2_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
S_AXI_HP2_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
S_AXI_HP3_ACLK => '0',
S_AXI_HP3_ARVALID => '0',
S_AXI_HP3_AWVALID => '0',
S_AXI_HP3_BREADY => '0',
S_AXI_HP3_RDISSUECAP1_EN => '0',
S_AXI_HP3_RREADY => '0',
S_AXI_HP3_WLAST => '0',
S_AXI_HP3_WRISSUECAP1_EN => '0',
S_AXI_HP3_WVALID => '0',
S_AXI_HP3_ARBURST => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
S_AXI_HP3_ARLOCK => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
S_AXI_HP3_ARSIZE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
S_AXI_HP3_AWBURST => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
S_AXI_HP3_AWLOCK => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
S_AXI_HP3_AWSIZE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
S_AXI_HP3_ARPROT => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
S_AXI_HP3_AWPROT => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
S_AXI_HP3_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_HP3_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_HP3_ARCACHE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_HP3_ARLEN => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_HP3_ARQOS => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_HP3_AWCACHE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_HP3_AWLEN => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_HP3_AWQOS => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_HP3_ARID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
S_AXI_HP3_AWID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
S_AXI_HP3_WID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
S_AXI_HP3_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
S_AXI_HP3_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
IRQ_F2P => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
Core0_nFIQ => '0',
Core0_nIRQ => '0',
Core1_nFIQ => '0',
Core1_nIRQ => '0',
DMA0_ACLK => '0',
DMA0_DAREADY => '0',
DMA0_DRLAST => '0',
DMA0_DRVALID => '0',
DMA1_ACLK => '0',
DMA1_DAREADY => '0',
DMA1_DRLAST => '0',
DMA1_DRVALID => '0',
DMA2_ACLK => '0',
DMA2_DAREADY => '0',
DMA2_DRLAST => '0',
DMA2_DRVALID => '0',
DMA3_ACLK => '0',
DMA3_DAREADY => '0',
DMA3_DRLAST => '0',
DMA3_DRVALID => '0',
DMA0_DRTYPE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
DMA1_DRTYPE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
DMA2_DRTYPE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
DMA3_DRTYPE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
FCLK_CLK0 => FCLK_CLK0,
FCLK_CLKTRIG0_N => '0',
FCLK_CLKTRIG1_N => '0',
FCLK_CLKTRIG2_N => '0',
FCLK_CLKTRIG3_N => '0',
FCLK_RESET0_N => FCLK_RESET0_N,
FTMD_TRACEIN_DATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
FTMD_TRACEIN_VALID => '0',
FTMD_TRACEIN_CLK => '0',
FTMD_TRACEIN_ATID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
FTMT_F2P_TRIG => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
FTMT_F2P_DEBUG => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
FTMT_P2F_TRIGACK => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
FPGA_IDLE_N => '0',
EVENT_EVENTI => '0',
DDR_ARB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
MIO => MIO,
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_Clk_n => DDR_Clk_n,
DDR_Clk => DDR_Clk,
DDR_CS_n => DDR_CS_n,
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_WEB => DDR_WEB,
DDR_BankAddr => DDR_BankAddr,
DDR_Addr => DDR_Addr,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
DDR_DM => DDR_DM,
DDR_DQ => DDR_DQ,
DDR_DQS_n => DDR_DQS_n,
DDR_DQS => DDR_DQS,
PS_SRSTB => PS_SRSTB,
PS_CLK => PS_CLK,
PS_PORB => PS_PORB
);
END ZynqDesign_processing_system7_0_0_arch;
| mit | 6fa9349a142dcd606ad7e5f8e5fca609 | 0.627819 | 2.749582 | false | false | false | false |
azeemshaikh38/PipelinedProcessorWithInterrupts | Processor/ALU_new.vhd | 1 | 11,238 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
entity ALU is
port (
A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0);
operation : in std_logic_vector(4 downto 0);
Raddr1 : in std_logic_vector(3 downto 0);
Raddr2 : in std_logic_vector(3 downto 0);
Memaddr_in : in std_logic_vector(7 downto 0);
MemAddr_out : out std_logic_vector(7 downto 0);
Raddr : out std_logic_vector(3 downto 0);
op : out std_logic_vector(1 downto 0);
result : out std_logic_vector(7 downto 0);
branch : out std_logic;
branch_offset : out std_logic_vector(7 downto 0);
mem_rd_en : out std_logic;
reg_wr_en : out std_logic;
mem_wr_en : out std_logic
);
end entity;
architecture struct of ALU is
begin
process(A, B, operation, Raddr1, Raddr2, Memaddr_in)
begin
case operation is
when conv_std_logic_vector(0, 5) => --nop
MemAddr_out <= X"00";
Raddr <= X"0";
op <= "00";
result <= X"00";
branch <= '0';
branch_offset <= X"00";
mem_wr_en <= '0';
mem_rd_en <= '0';
reg_wr_en <= '0';
when conv_std_logic_vector(1, 5) => --Add immediate
MemAddr_out <= X"00";
Raddr <= Raddr1;
op <= "01";
result <= A + MemAddr_in;
branch <= '0';
branch_offset <= X"00";
reg_wr_en <= '1';
mem_rd_en <= '0';
mem_wr_en <= '0';
when conv_std_logic_vector(2, 5) => --Add
MemAddr_out <= X"00";
Raddr <= Raddr1;
op <= "01";
result <= A + B;
branch <= '0';
branch_offset <= X"00";
reg_wr_en <= '1';
mem_rd_en <= '0';
mem_wr_en <= '0';
when conv_std_logic_vector(3, 5) => --Sub
MemAddr_out <= X"00";
Raddr <= Raddr1;
op <= "01";
result <= A - B;
branch <= '0';
branch_offset <= X"00";
reg_wr_en <= '1';
mem_rd_en <= '0';
mem_wr_en <= '0';
when conv_std_logic_vector(4, 5) => --Incr
MemAddr_out <= X"00";
Raddr <= Raddr1;
op <= "01";
result <= A + 1;
branch <= '0';
branch_offset <= X"00";
reg_wr_en <= '1';
mem_rd_en <= '0';
mem_wr_en <= '0';
when conv_std_logic_vector(5, 5) => --Decr
MemAddr_out <= X"00";
Raddr <= Raddr1;
op <= "01";
result <= A - 1;
branch <= '0';
branch_offset <= X"00";
reg_wr_en <= '1';
mem_rd_en <= '0';
mem_wr_en <= '0';
when conv_std_logic_vector(6, 5) => --Shift left
MemAddr_out <= X"00";
Raddr <= Raddr1;
op <= "01";
--result <= shl((unsigned(A); 1);
result <= X"00";
branch <= '0';
branch_offset <= X"00";
reg_wr_en <= '1';
mem_rd_en <= '0';
mem_wr_en <= '0';
when conv_std_logic_vector(7, 5) => --Shift right
MemAddr_out <= X"00";
Raddr <= Raddr1;
op <= "01";
--result <= conv_std_logic_vector((unsigned(A) srl 1), 8);
result <= X"00";
branch <= '0';
branch_offset <= X"00";
reg_wr_en <= '1';
mem_rd_en <= '0';
mem_wr_en <= '0';
when conv_std_logic_vector(8, 5) => --Not
MemAddr_out <= X"00";
Raddr <= Raddr1;
op <= "01";
result <= not(A);
branch <= '0';
branch_offset <= X"00";
reg_wr_en <= '1';
mem_rd_en <= '0';
mem_wr_en <= '0';
when conv_std_logic_vector(9, 5) => --Nor
MemAddr_out <= X"00";
Raddr <= Raddr1;
op <= "01";
result <= A nor B;
branch <= '0';
branch_offset <= X"00";
reg_wr_en <= '1';
mem_rd_en <= '0';
mem_wr_en <= '0';
when conv_std_logic_vector(10, 5) => --Nand
MemAddr_out <= X"00";
Raddr <= Raddr1;
op <= "01";
result <= A nand B;
branch <= '0';
branch_offset <= X"00";
reg_wr_en <= '1';
mem_rd_en <= '0';
mem_wr_en <= '0';
when conv_std_logic_vector(11, 5) => --Xor
MemAddr_out <= X"00";
Raddr <= Raddr1;
op <= "01";
result <= A xor B;
branch <= '0';
branch_offset <= X"00";
reg_wr_en <= '1';
mem_rd_en <= '0';
mem_wr_en <= '0';
when conv_std_logic_vector(12, 5) => --And
MemAddr_out <= X"00";
Raddr <= Raddr1;
op <= "01";
result <= A and B;
branch <= '0';
branch_offset <= X"00";
reg_wr_en <= '1';
mem_rd_en <= '0';
mem_wr_en <= '0';
when conv_std_logic_vector(13, 5) => --Or
MemAddr_out <= X"00";
Raddr <= Raddr1;
op <= "01";
result <= A or B;
branch <= '0';
branch_offset <= X"00";
reg_wr_en <= '1';
mem_rd_en <= '0';
mem_wr_en <= '0';
when conv_std_logic_vector(14, 5) => --Clear
MemAddr_out <= X"00";
Raddr <= Raddr1;
op <= "01";
result <= X"00";
branch <= '0';
branch_offset <= X"00";
reg_wr_en <= '1';
mem_rd_en <= '0';
mem_wr_en <= '0';
when conv_std_logic_vector(15, 5) => --Set
MemAddr_out <= X"00";
Raddr <= Raddr1;
op <= "01";
result <= X"FF";
branch <= '0';
branch_offset <= X"00";
reg_wr_en <= '1';
mem_rd_en <= '0';
mem_wr_en <= '0';
when conv_std_logic_vector(16, 5) => --Set if less than
if (A < B) then
MemAddr_out <= X"00";
Raddr <= Raddr1;
op <= "01";
result <= X"FF";
reg_wr_en <= '1';
else
MemAddr_out <= X"00";
Raddr <= Raddr1;
op <= "01";
result <= A;
reg_wr_en <= '0';
end if;
branch <= '0';
branch_offset <= X"00";
mem_rd_en <= '0';
mem_wr_en <= '0';
when conv_std_logic_vector(17, 5) => --Move
MemAddr_out <= X"00";
Raddr <= Raddr1;
op <= "01";
result <= B;
branch <= '0';
branch_offset <= X"00";
reg_wr_en <= '1';
mem_rd_en <= '0';
mem_wr_en <= '0';
when conv_std_logic_vector(18, 5) => --Enable Interrupt
MemAddr_out <= X"00";
Raddr <= X"0";
op <= "01";
result <= A xor B;
branch <= '0';
branch_offset <= X"00";
reg_wr_en <= '0';
mem_rd_en <= '0';
mem_wr_en <= '0';
when conv_std_logic_vector(19, 5) => --Load Indirect
MemAddr_out <= B;
Raddr <= Raddr1;
op <= "10";
result <= X"00";
branch <= '0';
branch_offset <= X"00";
reg_wr_en <= '1';
mem_rd_en <= '1';
mem_wr_en <= '0';
when conv_std_logic_vector(20, 5) => --Store Indirect
MemAddr_out <= B;
Raddr <= Raddr1;
op <= "11";
result <= A;
branch <= '0';
branch_offset <= X"00";
reg_wr_en <= '0';
mem_rd_en <= '0';
mem_wr_en <= '1';
when conv_std_logic_vector(21, 5) => --Load Register
report "ALU Load Register " & integer'image(conv_integer(MemAddr_in)) & " " & integer'image(conv_integer(Raddr1));
MemAddr_out <= MemAddr_in;
Raddr <= Raddr1;
op <= "10";
result <= X"00";
branch <= '0';
branch_offset <= X"00";
reg_wr_en <= '1';
mem_rd_en <= '1';
mem_wr_en <= '0';
when conv_std_logic_vector(22, 5) => --Store Register
MemAddr_out <= MemAddr_in;
Raddr <= Raddr1;
op <= "11";
result <= A;
branch <= '0';
branch_offset <= X"00";
reg_wr_en <= '0';
mem_rd_en <= '0';
mem_wr_en <= '1';
when conv_std_logic_vector(23, 5) => --Jump
MemAddr_out <= X"00";
Raddr <= X"0";
op <= "00";
result <= X"00";
branch <= '1';
branch_offset <= MemAddr_in;
reg_wr_en <= '0';
mem_rd_en <= '0';
mem_wr_en <= '0';
when conv_std_logic_vector(24, 5) => --Branch if Zero
if (A = X"00") then
MemAddr_out <= X"00";
Raddr <= X"0";
op <= "00";
result <= X"00";
branch <= '1';
branch_offset <= MemAddr_in;
else
MemAddr_out <= X"00";
Raddr <= X"0";
op <= "00";
result <= X"00";
branch <= '0';
branch_offset <= X"00";
end if;
reg_wr_en <= '0';
mem_rd_en <= '0';
mem_wr_en <= '0';
when conv_std_logic_vector(25, 5) => --Branch if not Zero
if (A /= X"00") then
MemAddr_out <= X"00";
Raddr <= X"0";
op <= "00";
result <= X"00";
branch <= '1';
branch_offset <= MemAddr_in;
else
MemAddr_out <= X"00";
Raddr <= X"0";
op <= "00";
result <= X"00";
branch <= '0';
branch_offset <= X"00";
end if;
reg_wr_en <= '0';
mem_rd_en <= '0';
mem_wr_en <= '0';
when conv_std_logic_vector(26, 5) => --Return from interrupt
MemAddr_out <= X"00";
Raddr <= X"0";
op <= "00";
result <= X"00";
branch <= '1';
branch_offset <= X"00";
reg_wr_en <= '0';
mem_rd_en <= '0';
mem_wr_en <= '0';
when others => --Default
MemAddr_out <= X"00";
Raddr <= X"0";
op <= "00";
result <= X"00";
branch <= '0';
branch_offset <= X"00";
reg_wr_en <= '0';
mem_rd_en <= '0';
mem_wr_en <= '0';
end case;
end process;
end architecture;
| unlicense | c2ede8d3883d1b9dc460db8b2e2d5572 | 0.377736 | 3.322886 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/Filter_Bank/tb_reconstruction.vhd | 1 | 3,399 | --------------------------------------------------------------------------------------------------
-- Reconstruction Testbench
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tb_clockgen_pkg.all;
use work.tb_read_csv_pkg.all;
use work.tb_write_csv_pkg.all;
use work.dsp_pkg.all;
use work.reconstruction_pkg.all;
--This module is a test-bench for simulating the fir filter
entity tb_reconstruction is
end tb_reconstruction;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture sim of tb_reconstruction is
constant INPUT_FILE1 : string
:= "X:\Education\Masters Thesis\matlab\fir_filters\chirp_decomp_low.csv";
constant INPUT_FILE2 : string
:= "X:\Education\Masters Thesis\matlab\fir_filters\chirp_decomp_high.csv";
constant OUTPUT_FILE : string
:= "X:\Education\Masters Thesis\matlab\fir_filters\chirp_reconstructed.csv";
signal rst : std_logic := '0';
signal clk_10ns : std_logic := '0';
signal clk_20ns : std_logic := '0';
signal sig_in1 : sig := (others => '0');
signal sig_in2 : sig := (others => '0');
signal sig_out : sig := (others => '0');
begin
--Instantiate clock generator
clk1 : tb_clockgen
generic map(PERIOD => 10ns,
DUTY_CYCLE => 0.50)
port map( clk => clk_10ns);
clk2 : tb_clockgen
generic map(PERIOD => 20ns,
DUTY_CYCLE => 0.50)
port map( clk => clk_20ns);
--Instantiate file reader
reader1 : tb_read_csv
generic map(FILENAME => INPUT_FILE1)
port map( clk => clk_20ns,
sig(data) => sig_in1);
--Instantiate file reader
reader2 : tb_read_csv
generic map(FILENAME => INPUT_FILE2)
port map( clk => clk_20ns,
sig(data) => sig_in2);
--Instantiate unit under test
uut : entity work.reconstruction(behave)
generic map(low_pass => NYQUIST_LOW_BANK,
high_pass => NYQUIST_HIGH_BANK)
port map( clk_low => clk_20ns,
clk_high => clk_10ns,
rst => rst,
x_low => sig_in1,
x_high => sig_in2,
y => sig_out);
--Instantiate a file writer
writer : tb_write_csv
generic map(FILENAME => OUTPUT_FILE)
port map( clk => clk_10ns,
data => std_logic_vector(sig_out));
--Main Process
--TODO: Add a check for end of file, once reached terminate simulation.
main: process
begin
rst <= '1';
wait for 36ns;
rst <= '0';
wait;
end process;
end sim;
| mit | 404e150c7acfab9793063719d96bb79a | 0.440718 | 4.448953 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/imports/arpv2.vhd | 2 | 13,310 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 12:00:04 05/31/2011
-- Design Name:
-- Module Name: arpv2 - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple IP lookup in 1-deep cache and arp store
-- request cache fill through ARP protocol if required
-- Handle ARP protocol
-- Respond to ARP requests and replies
-- Ignore pkts that are not ARP
-- Ignore pkts that are not addressed to us
--
-- structural decomposition includes
-- arp TX block - encoding of ARP protocol
-- arp RX block - decoding of ARP protocol
-- arp REQ block - sequencing requests for resolution
-- arp STORE block - storing address resolution entries (indexed by IP addr)
-- arp sync block - sync between master RX clock and TX clock domains
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.arp_types.all;
entity arpv2 is
generic (
no_default_gateway : boolean := true; -- set to false if communicating with devices accessed
-- though a "default gateway or router"
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error
MAX_ARP_ENTRIES : integer := 255 -- max entries in the arp store
);
port (
-- lookup request signals
arp_req_req : in arp_req_req_type;
arp_req_rslt : out arp_req_rslt_type;
-- MAC layer RX signals
data_in_clk : in std_logic;
reset : in std_logic;
data_in : in std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
data_in_valid : in std_logic; -- indicates data_in valid on clock
data_in_last : in std_logic; -- indicates last data in frame
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
data_out_clk : in std_logic;
data_out_ready : in std_logic; -- indicates system ready to consume data
data_out_valid : out std_logic; -- indicates data out is valid
data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
-- system signals
our_mac_address : in std_logic_vector (47 downto 0);
our_ip_address : in std_logic_vector (31 downto 0);
nwk_gateway : in std_logic_vector (31 downto 0) := (others => '0'); -- IP address of default gateway
nwk_mask : in std_logic_vector (31 downto 0) := (others => '0'); -- Net mask
control : in arp_control_type;
req_count : out std_logic_vector(7 downto 0) -- count of arp pkts received
);
end arpv2;
architecture structural of arpv2 is
component arp_req
generic (
no_default_gateway : boolean := true;
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5 -- # wrong nwk pkts received before set error
);
port (
-- lookup request signals
arp_req_req : in arp_req_req_type; -- request for a translation from IP to MAC
arp_req_rslt : out arp_req_rslt_type; -- the result
-- external arp store signals
arp_store_req : out arp_store_rdrequest_t; -- requesting a lookup or store
arp_store_result : in arp_store_result_t; -- the result
-- network request signals
arp_nwk_req : out arp_nwk_request_t; -- requesting resolution via the network
arp_nwk_result : in arp_nwk_result_t; -- the result
-- system signals
clear_cache : in std_logic; -- clear the internal cache
nwk_gateway : in std_logic_vector(31 downto 0); -- IP address of default gateway
nwk_mask : in std_logic_vector(31 downto 0); -- Net mask
clk : in std_logic;
reset : in std_logic
);
end component;
component arp_tx
port(
-- control signals
send_I_have : in std_logic; -- pulse will be latched
arp_entry : in arp_entry_t; -- arp target for I_have req (will be latched)
send_who_has : in std_logic; -- pulse will be latched
ip_entry : in std_logic_vector (31 downto 0); -- ip target for who_has req (will be latched)
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
data_out_ready : in std_logic; -- indicates system ready to consume data
data_out_valid : out std_logic; -- indicates data out is valid
data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
data_out : out std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
-- system signals
our_mac_address : in std_logic_vector (47 downto 0);
our_ip_address : in std_logic_vector (31 downto 0);
tx_clk : in std_logic;
reset : in std_logic
);
end component;
component arp_rx
port(
-- MAC layer RX signals
data_in : in std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
data_in_valid : in std_logic; -- indicates data_in valid on clock
data_in_last : in std_logic; -- indicates last data in frame
-- ARP output signals
recv_who_has : out std_logic; -- pulse will be latched
arp_entry_for_who_has : out arp_entry_t; -- target for who_has msg (Iie, who to reply to)
recv_I_have : out std_logic; -- pulse will be latched
arp_entry_for_I_have : out arp_entry_t; -- arp target for I_have msg
-- control and status signals
req_count : out std_logic_vector(7 downto 0); -- count of arp pkts received
-- system signals
our_ip_address : in std_logic_vector (31 downto 0);
rx_clk : in std_logic;
reset : in std_logic
);
end component;
component arp_store_br
generic (
MAX_ARP_ENTRIES : integer := 255 -- max entries in the store
);
port (
-- read signals
read_req : in arp_store_rdrequest_t; -- requesting a lookup or store
read_result : out arp_store_result_t; -- the result
-- write signals
write_req : in arp_store_wrrequest_t; -- requesting a lookup or store
-- control and status signals
clear_store : in std_logic; -- erase all entries
entry_count : out unsigned(7 downto 0); -- how many entries currently in store
-- system signals
clk : in std_logic;
reset : in std_logic
);
end component;
component arp_sync
port (
-- REQ to TX
arp_nwk_req : in arp_nwk_request_t; -- request for a translation from IP to MAC
send_who_has : out std_logic;
ip_entry : out std_logic_vector (31 downto 0);
-- RX to TX
recv_who_has : in std_logic; -- this is for us, we will respond
arp_entry_for_who_has : in arp_entry_t;
send_I_have : out std_logic;
arp_entry : out arp_entry_t;
-- RX to REQ
I_have_received : in std_logic;
nwk_result_status : out arp_nwk_rslt_t;
-- System Signals
rx_clk : in std_logic;
tx_clk : in std_logic;
reset : in std_logic
);
end component;
-- interconnect REQ -> ARP_TX
signal arp_nwk_req_int : arp_nwk_request_t; -- tx req from REQ
signal send_I_have_int : std_logic;
signal arp_entry_int : arp_entry_t;
signal send_who_has_int : std_logic;
signal ip_entry_int : std_logic_vector (31 downto 0);
-- interconnect REQ <-> ARP_STORE
signal arp_store_req_int : arp_store_rdrequest_t; -- lookup request
signal arp_store_result_int : arp_store_result_t; -- lookup result
-- interconnect ARP_RX -> REQ
signal nwk_result_status_int : arp_nwk_rslt_t; -- response from a TX req
-- interconnect ARP_RX -> ARP_STORE
signal recv_I_have_int : std_logic; -- path to store new arp entry
signal arp_entry_for_I_have_int : arp_entry_t;
-- interconnect ARP_RX -> ARP_TX
signal recv_who_has_int : std_logic; -- path for reply when we can anser
signal arp_entry_for_who_has_int : arp_entry_t; -- target for who_has msg (ie, who to reply to)
begin
req : arp_req
generic map (
no_default_gateway => no_default_gateway,
CLOCK_FREQ => CLOCK_FREQ,
ARP_TIMEOUT => ARP_TIMEOUT,
ARP_MAX_PKT_TMO => ARP_MAX_PKT_TMO
)
port map (
-- lookup request signals
arp_req_req => arp_req_req,
arp_req_rslt => arp_req_rslt,
-- external arp store signals
arp_store_req => arp_store_req_int,
arp_store_result => arp_store_result_int,
-- network request signals
arp_nwk_req => arp_nwk_req_int,
arp_nwk_result.status => nwk_result_status_int,
arp_nwk_result.entry => arp_entry_for_I_have_int,
-- system signals
clear_cache => control.clear_cache,
nwk_gateway => nwk_gateway,
nwk_mask => nwk_mask,
clk => data_in_clk,
reset => reset
);
sync : arp_sync port map (
-- REQ to TX
arp_nwk_req => arp_nwk_req_int,
send_who_has => send_who_has_int,
ip_entry => ip_entry_int,
-- RX to TX
recv_who_has => recv_who_has_int,
arp_entry_for_who_has => arp_entry_for_who_has_int,
send_I_have => send_I_have_int,
arp_entry => arp_entry_int,
-- RX to REQ
I_have_received => recv_I_have_int,
nwk_result_status => nwk_result_status_int,
-- system
rx_clk => data_in_clk,
tx_clk => data_out_clk,
reset => reset
);
tx : arp_tx port map (
-- control signals
send_I_have => send_I_have_int,
arp_entry => arp_entry_int,
send_who_has => send_who_has_int,
ip_entry => ip_entry_int,
-- MAC layer TX signals
mac_tx_req => mac_tx_req,
mac_tx_granted => mac_tx_granted,
data_out_ready => data_out_ready,
data_out_valid => data_out_valid,
data_out_first => data_out_first,
data_out_last => data_out_last,
data_out => data_out,
-- system signals
our_ip_address => our_ip_address,
our_mac_address => our_mac_address,
tx_clk => data_out_clk,
reset => reset
);
rx : arp_rx port map (
-- MAC layer RX signals
data_in => data_in,
data_in_valid => data_in_valid,
data_in_last => data_in_last,
-- ARP output signals
recv_who_has => recv_who_has_int,
arp_entry_for_who_has => arp_entry_for_who_has_int,
recv_I_have => recv_I_have_int,
arp_entry_for_I_have => arp_entry_for_I_have_int,
-- control and status signals
req_count => req_count,
-- system signals
our_ip_address => our_ip_address,
rx_clk => data_in_clk,
reset => reset
);
store : arp_store_br
generic map (
MAX_ARP_ENTRIES => MAX_ARP_ENTRIES
)
port map (
-- read signals
read_req => arp_store_req_int,
read_result => arp_store_result_int,
-- write signals
write_req.req => recv_I_have_int,
write_req.entry => arp_entry_for_I_have_int,
-- control and status signals
clear_store => control.clear_cache,
entry_count => open,
-- system signals
clk => data_in_clk,
reset => reset
);
end structural;
| gpl-3.0 | 4319cfa74fc0e69cc4f51314b1846c57 | 0.559279 | 3.68596 | false | false | false | false |
cbakalis/vmm_boards_firmware | sources/sources_1/configuration/axi_quad_top.vhd | 1 | 52,216 | ----------------------------------------------------------------------------------
-- Company: University of Washington
-- Engineer: Lev Kurilenko
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Lev Kurilenko
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 08/18/2016 11:27:16 AM
-- Design Name:
-- Module Name: AXI4_SPI_top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Micron SPI Flash Documentation (n25q256 1.8V): https://www.micron.com/~/media/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_256mb_1_8v.pdf
-- axi_quad_spi Documentation: http://www.xilinx.com/support/documentation/ip_documentation/axi_quad_spi/v3_2/pg153-axi-quad-spi.pdf
----------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity AXI4_SPI is
port(
clk_200 : in std_logic;
clk_125 : in std_logic;
clk_50 : in std_logic;
myIP : out std_logic_vector(31 downto 0); -- Signal going out to mmfe8_top and used as main IP
myMAC : out std_logic_vector(47 downto 0); -- Signal going out to mmfe8_top and used as main MAC
destIP : out std_logic_vector(31 downto 0); -- Signal going out to mmfe8_top and used as main destIP
default_IP : in std_logic_vector(31 downto 0);
default_MAC : in std_logic_vector(47 downto 0);
default_destIP : in std_logic_vector(31 downto 0);
myIP_set : in std_logic_vector(31 downto 0); -- Signal coming from config_logic. Used to set myIP
myMAC_set : in std_logic_vector(47 downto 0); -- Signal coming from config_logic. Used to set myMAC
destIP_set : in std_logic_vector(31 downto 0); -- Signal coming from config_logic. Used to set destIP
newip_start : in std_logic; -- Flag that initiates the process for setting newIP
flash_busy : out std_logic; -- Flag that indicates the module is busy setting IP
-- refer to Micron documentation for the signals below: https://www.micron.com/~/media/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_256mb_1_8v.pdf
io0_i : IN STD_LOGIC; -- Signals for DQ0 (MOSI)
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
io1_i : IN STD_LOGIC; -- Signals for DQ1 (MISO)
io1_o : OUT STD_LOGIC;
io1_t : OUT STD_LOGIC;
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0); -- Slave Select
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_t : OUT STD_LOGIC
--SPI_CLK : in std_logic
);
end AXI4_SPI;
architecture Behavioral of AXI4_SPI is
-------------------------------------------------
-- Flow FSM signals
-------------------------------------------------
type state_spi is (SETUP, IDLE, WAIT_WRITE, WRITE, FINISH_WRITE, WAIT_READ, READ, FINISH_READ);
signal spi_state : state_spi; -- State machine that handles the signals necessary to perform a single write to or read to and from a core register in the axi_quad_spi
type state_spi_control is (CLEAR_FIFO, WRITE_CMD_ADDR_DATA, ASSERT_SS, DEASSERT_INHIB, CLEAR_SS, ASSERT_INHIB, READ_SPI_DATA, RESET);
signal spi_state_control : state_spi_control; -- State machine that handles the higher level flow (above spi_state) in order to execute a proper transaction via the axi_quad_spi (Nested within spi_state = IDLE)
type config_ip_state is (IDLE, CHECK_IP_SET, SET_IP, NEW_IP, RESET);
signal ip_config_state : config_ip_state; -- State machine that handles Dynamic IP Configuration. Can be though of as wrapper that allows proper function of Dynamic IP Configuration
type spi_write_state is (WRITE_ENABLE, SUBSECTOR_ERASE, PAGE_PROGRAM, RESET);
signal write_spi_state : spi_write_state; -- State machine nested within ip_config_state = NEW_IP. Handles the necessary logic in order to execute a write to the SPI Flash. (Specific logic flow needed)
-------------------------------------------------
-- FSM Automation signals
-------------------------------------------------
signal araddr_set : std_logic_vector(6 downto 0); -- Sets read address for registers in axi_quad_spi
signal awaddr_set : std_logic_vector(6 downto 0); -- Sets write address for registers in axi_quad_spi
signal wdata_set : std_logic_vector(31 downto 0); -- Sets write data for registers in axi_quad_spi
signal byte_transfer_counter : integer := 0; -- Counts how many bytes are being transferred/read to or from Rx or Tx FIFO in axi_quad_spi
signal page_prog_counter : integer := 0; -- Used to see what page program iteration (command to SPI Flash) FSM is at
signal set_ip_counter : integer := 0; -- Counter used to delay some signals within FSM for proper transactions
signal check_ip_counter : integer := 0; -- Counts how many times the check_ip_flag was checked
shared variable cmdaddrdata : bit_vector(79 downto 0); -- Stores command, address, and data needed for transactions with the SPI Flash
signal start_transaction : std_logic := '0'; -- Flag that initiates a transaction with the SPI Flash
signal transaction_finished : std_logic := '1'; -- Flag letting the FSM know that transaction is finished
signal second_transaction : std_logic := '0'; -- Flag used when performing 2 transaction to read the proper data from SPI Flash
signal page_prog : std_logic := '0'; -- Page program flag lets the spi_write_state = WRITE_ENABLE state know whether to perform a SUBESCTOR_ERASE or a PAGE_PROGRAM
signal system_start : std_logic := '0'; -- Flag used to check if the system has just started. Used to configure the proper IP, MAC, and destIP
-------------------------------------------------
-- Dynamic IP signals
-------------------------------------------------
signal cmdaddrdata_set : std_logic_vector(79 downto 0);
signal byte_count_set : std_logic_vector(31 downto 0);
signal ip_set_flag : std_logic_vector(7 downto 0) := x"FF";
signal new_ip_set : std_logic := '0';
signal set_default_ip : std_logic := '0';
-------------------------------------------------
-- Debugging Signals
-------------------------------------------------
signal read_out : std_logic_vector(244 downto 0);
-------------------------------------------------
-- Quad SPI Signals
-- refer to quad_spi_documentation: http://www.xilinx.com/support/documentation/ip_documentation/axi_quad_spi/v3_2/pg153-axi-quad-spi.pdf
-------------------------------------------------
signal ip2intc_irpt : std_logic:= '0';
signal spi_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0):=(others => '0');
signal spi_arready : std_logic:= '0';
signal spi_rresp : STD_LOGIC_VECTOR(1 DOWNTO 0):=(others => '0');
signal spi_rvalid : std_logic:= '1';
signal spi_counter : integer := 0;
signal spi_slct_cmd : integer := 0;
signal spi_cnt : STD_LOGIC_VECTOR(31 DOWNTO 0):=(others => '0');
signal spi_awready : std_logic := '1';
signal spi_bresp : STD_LOGIC_vector(1 downto 0) := "00";
signal spi_bvalid : std_logic := '0';
signal spi_awaddr : std_logic_vector(6 downto 0) := "0000000";
signal spi_wdata : std_logic_vector(31 downto 0) := x"00000000";
signal spi_wstrb : std_logic_vector(3 downto 0) := "0000";
signal spi_aresetn : std_logic := '0';
signal spi_awvalid : std_logic := '0';
signal spi_wvalid : std_logic := '0';
signal spi_bready : std_logic := '0';
signal spi_wready : std_logic := '0';
signal spi_arvalid : std_logic := '0';
signal spi_rready : std_logic := '0';
signal spi_araddr : std_logic_vector(6 downto 0) := "0000000";
signal spi_state_is : std_logic_vector(3 downto 0) := "0000";
signal spi_state_control_is : std_logic_vector(3 downto 0) := "0000";
signal spi_ip_config_state_is : std_logic_vector(3 downto 0) := "0000";
signal write_spi_state_is : std_logic_vector(3 downto 0) := "0000";
signal startupe2_eos : std_logic;
-------------------------------------------------------------------
-- CDCC signals
-------------------------------------------------------------------
signal flash_busy_i : std_logic := '0';
signal myIP_i : std_logic_vector(31 downto 0) := (others => '0');
signal myMAC_i : std_logic_vector(47 downto 0) := (others => '0');
signal destIP_i : std_logic_vector(31 downto 0) := (others => '0');
signal newIP_start_s50 : std_logic := '0';
signal myIP_set_s50 : std_logic_vector(31 downto 0) := (others => '0');
signal myMAC_set_s50 : std_logic_vector(47 downto 0) := (others => '0');
signal destIP_set_s50 : std_logic_vector(31 downto 0) := (others => '0');
-------------------------------------------------------------------
-- Keep signals for ILA
-------------------------------------------------------------------
-- attribute keep : string;
-- attribute dont_touch : string;
-------------------------------------------------------------------
-- Other
-------------------------------------------------------------------
-- attribute keep of ip_set_flag : signal is "TRUE";
-- attribute dont_touch of ip_set_flag : signal is "TRUE";
-- attribute keep of spi_arready : signal is "TRUE";
-- attribute dont_touch of spi_arready : signal is "TRUE";
-- attribute keep of spi_rresp : signal is "TRUE";
-- attribute dont_touch of spi_rresp : signal is "TRUE";
-- attribute keep of spi_rvalid : signal is "TRUE";
-- attribute dont_touch of spi_rvalid : signal is "TRUE";
-- attribute keep of spi_cnt : signal is "TRUE";
-- attribute dont_touch of spi_cnt : signal is "TRUE";
-- attribute keep of spi_awready : signal is "TRUE";
-- attribute dont_touch of spi_awready : signal is "TRUE";
-- attribute keep of spi_bresp : signal is "TRUE";
-- attribute dont_touch of spi_bresp : signal is "TRUE";
-- attribute keep of spi_bvalid : signal is "TRUE";
-- attribute dont_touch of spi_bvalid : signal is "TRUE";
-- attribute keep of spi_awaddr : signal is "TRUE";
-- attribute dont_touch of spi_awaddr : signal is "TRUE";
-- attribute keep of spi_wdata : signal is "TRUE";
-- attribute dont_touch of spi_wdata : signal is "TRUE";
-- attribute keep of spi_wstrb : signal is "TRUE";
-- attribute dont_touch of spi_wstrb : signal is "TRUE";
-- attribute keep of spi_aresetn : signal is "TRUE";
-- attribute dont_touch of spi_aresetn : signal is "TRUE";
-- attribute keep of spi_awvalid : signal is "TRUE";
-- attribute dont_touch of spi_awvalid : signal is "TRUE";
-- attribute keep of spi_wvalid : signal is "TRUE";
-- attribute dont_touch of spi_wvalid : signal is "TRUE";
-- attribute keep of spi_bready : signal is "TRUE";
-- attribute dont_touch of spi_bready : signal is "TRUE";
-- attribute keep of spi_wready : signal is "TRUE";
-- attribute dont_touch of spi_wready : signal is "TRUE";
-- attribute keep of spi_arvalid : signal is "TRUE";
-- attribute dont_touch of spi_arvalid : signal is "TRUE";
-- attribute keep of spi_rready : signal is "TRUE";
-- attribute dont_touch of spi_rready : signal is "TRUE";
-- attribute keep of spi_araddr : signal is "TRUE";
-- attribute dont_touch of spi_araddr : signal is "TRUE";
-- attribute keep of spi_rdata : signal is "TRUE";
-- attribute dont_touch of spi_rdata : signal is "TRUE";
-- attribute keep of araddr_set : signal is "TRUE";
-- attribute dont_touch of araddr_set : signal is "TRUE";
-- attribute keep of awaddr_set : signal is "TRUE";
-- attribute dont_touch of awaddr_set : signal is "TRUE";
-- attribute keep of wdata_set : signal is "TRUE";
-- attribute dont_touch of wdata_set : signal is "TRUE";
-- attribute keep of spi_state_control_is : signal is "TRUE";
-- attribute dont_touch of spi_state_control_is : signal is "TRUE";
-- attribute keep of io0_i : signal is "TRUE";
-- attribute dont_touch of io0_i : signal is "TRUE";
-- attribute keep of io0_o : signal is "TRUE";
-- attribute dont_touch of io0_o : signal is "TRUE";
-- attribute keep of io0_t : signal is "TRUE";
-- attribute dont_touch of io0_t : signal is "TRUE";
-- attribute keep of io1_i : signal is "TRUE";
-- attribute dont_touch of io1_i : signal is "TRUE";
-- attribute keep of io1_o : signal is "TRUE";
-- attribute dont_touch of io1_o : signal is "TRUE";
-- attribute keep of io1_t : signal is "TRUE";
-- attribute dont_touch of io1_t : signal is "TRUE";
-- attribute keep of ss_i : signal is "TRUE";
-- attribute dont_touch of ss_i : signal is "TRUE";
-- attribute keep of ss_o : signal is "TRUE";
-- attribute dont_touch of ss_o : signal is "TRUE";
-- attribute keep of ss_t : signal is "TRUE";
-- attribute dont_touch of ss_t : signal is "TRUE";
-- attribute keep of cmdaddrdata_set : signal is "TRUE";
-- attribute dont_touch of cmdaddrdata_set : signal is "TRUE";
-- attribute keep of cmdaddrdata : variable is "TRUE";
-- attribute dont_touch of cmdaddrdata : variable is "TRUE";
-- attribute keep of start_transaction : signal is "TRUE";
-- attribute dont_touch of start_transaction : signal is "TRUE";
-- attribute keep of transaction_finished : signal is "TRUE";
-- attribute dont_touch of transaction_finished : signal is "TRUE";
-- attribute keep of spi_ip_config_state_is : signal is "TRUE";
-- attribute dont_touch of spi_ip_config_state_is : signal is "TRUE";
-- attribute keep of newip_start : signal is "TRUE";
-- attribute dont_touch of newip_start : signal is "TRUE";
-- attribute keep of write_spi_state_is : signal is "TRUE";
-- attribute dont_touch of write_spi_state_is : signal is "TRUE";
-- attribute keep of byte_transfer_counter : signal is "true";
-- attribute keep of set_ip_counter : signal is "true";
-- attribute keep of page_prog_counter : signal is "true";
-- attribute keep of second_transaction : signal is "true";
-- attribute keep of page_prog : signal is "true";
-- attribute keep of system_start : signal is "true";
-- attribute keep of check_ip_counter : signal is "true";
-- attribute keep of set_default_ip : signal is "true";
-- attribute keep of myIP_set : signal is "true";
-- attribute keep of myMAC_set : signal is "true";
-- attribute keep of destIP_set : signal is "true";
-- attribute dont_touch of myIP_set : signal is "true";
-- attribute dont_touch of myMAC_set : signal is "true";
-- attribute dont_touch of destIP_set : signal is "true";
component ila_spi_flash
PORT ( clk : IN std_logic;
probe0 : IN std_logic_vector(244 DOWNTO 0)
);
end component;
component CDCC
generic(
NUMBER_OF_BITS : integer := 8); -- number of signals to be synced
port(
clk_src : in std_logic; -- input clk (source clock)
clk_dst : in std_logic; -- input clk (dest clock)
data_in : in std_logic_vector(NUMBER_OF_BITS - 1 downto 0); -- data to be synced
data_out_s : out std_logic_vector(NUMBER_OF_BITS - 1 downto 0) -- synced data to clk_dst
);
end component;
-- component vio_0
-- PORT ( clk : IN std_logic;
-- probe_out0 : OUT std_logic;
-- probe_out1 : OUT std_logic;
-- probe_out2 : OUT std_logic_vector(79 DOWNTO 0);
-- probe_out3 : OUT std_logic_vector(31 DOWNTO 0);
-- probe_out4 : OUT std_logic;
-- probe_out5 : OUT std_logic
-- );
-- end component;
component axi_quad_spi_0 is
Port (
ext_spi_clk : in std_logic;
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
io0_i : in std_logic;
io0_o : out std_logic;
io0_t : out std_logic;
io1_i : in std_logic;
io1_o : out std_logic;
io1_t : out std_logic;
ss_i : in STD_LOGIC_VECTOR ( 0 to 0 );
ss_o : out STD_LOGIC_VECTOR ( 0 to 0 );
ss_t : out std_logic;
ip2intc_irpt : out std_logic;
cfgclk : out std_logic;
cfgmclk : out std_logic;
eos : out std_logic;
preq : out std_logic
);
end component;
begin
axi_SPI: axi_quad_spi_0
Port map(
ext_spi_clk => clk_50, --V22
--ext_spi_clk => SPI_CLK, --V22
s_axi_aclk => clk_50,
s_axi_aresetn => spi_aresetn,
s_axi_awaddr => spi_awaddr,
s_axi_awvalid => spi_wvalid,
s_axi_awready => spi_awready,
s_axi_wdata => spi_wdata,
s_axi_wstrb => spi_wstrb,
s_axi_wvalid => spi_wvalid,
s_axi_wready => spi_wready,
s_axi_bresp => spi_bresp,
s_axi_bvalid => spi_bvalid,
s_axi_bready => spi_bready,
s_axi_araddr => spi_araddr,
s_axi_arvalid => spi_arvalid,
s_axi_arready => spi_arready,
s_axi_rdata => spi_rdata,
s_axi_rresp => spi_rresp,
s_axi_rvalid => spi_rvalid,
s_axi_rready => spi_rready,
io0_i => io0_i,
io0_o => io0_o,
io0_t => io0_t,
io1_i => io1_i,
io1_o => io1_o,
io1_t => io1_t,
ss_i => ss_i,
ss_o => ss_o,
ss_t => ss_t,
ip2intc_irpt => ip2intc_irpt,
cfgclk => open,
cfgmclk => open,
eos => startupe2_eos,
preq => open
);
spi_ip_config: process(clk_50) -- Process that handles Dynamic IP Configuration
begin
if rising_edge(clk_50) then
case ip_config_state is -- State machine that handles Dynamic IP Configuration. Can be though of as wrapper that allows proper function of Dynamic IP Configuration
when IDLE =>
spi_ip_config_state_is <= "0000";
flash_busy_i <= '0';
if (system_start = '0') then -- Checked when system is started to set IP
ip_config_state <= CHECK_IP_SET;
elsif (newip_start_s50 = '1') then -- This is set when UDP dest port 6604 receives data
ip_config_state <= NEW_IP;
else
ip_config_state <= IDLE;
end if;
when CHECK_IP_SET =>
spi_ip_config_state_is <= "0001";
flash_busy_i <= '1';
cmdaddrdata_set <= x"03F0_0000_0000_0000_0000"; -- Command to read ipset_flag in address x"F0_0000"
byte_count_set <= x"0000_0004"; -- Byte count required for proper read: 4 bytes (starts at 0)
set_ip_counter <= 0;
start_transaction <= '0';
if (transaction_finished = '1') then -- Checks if ipset_flag = x"01" and sets the flag accordingly
if (ip_set_flag = x"01") then
system_start <= '1';
ip_config_state <= SET_IP;
check_ip_counter <= 0;
elsif ((ip_set_flag /= x"01") and (check_ip_counter > 5)) then -- Must iterate
ip_config_state <= IDLE;
set_default_ip <= '1';
system_start <= '1';
check_ip_counter <= 0;
else
start_transaction <= '1';
check_ip_counter <= check_ip_counter + 1;
end if;
end if;
when SET_IP => -- Performs necessary operations to read SPI Flash and set the current IP, MAC, and destIP
spi_ip_config_state_is <= "0010";
if ( set_ip_counter <= 50) then
set_ip_counter <= set_ip_counter + 1;
end if;
if ((transaction_finished = '1') and (set_ip_counter < 10)) then
second_transaction <= '0';
cmdaddrdata_set <= x"03F0_0001_0000_0000_0000";
byte_count_set <= x"0000_000F";
start_transaction <= '1';
elsif ((transaction_finished = '1') and (set_ip_counter >= 40)) then
second_transaction <= '1';
cmdaddrdata_set <= x"03F0_000D_0000_0000_0000";
byte_count_set <= x"0000_0005";
set_ip_counter <= set_ip_counter + 1;
start_transaction <= '1';
if( set_ip_counter = 70) then
ip_config_state <= RESET;
set_ip_counter <= 0;
end if;
else
start_transaction <= '0';
end if;
when NEW_IP => -- Writes new IP, MAC, and destIP into SPI Flash and sets the new IP as the current active IP, MAC, and destIP
spi_ip_config_state_is <= "0011";
flash_busy_i <= '1';
case write_spi_state is -- State machine nested within ip_config_state = NEW_IP. Handles the necessary logic in order to execute a write to the SPI Flash. (Uses logic flow described in Micron Documentation)
when WRITE_ENABLE =>
write_spi_state_is <= "0000";
start_transaction <= '0';
if (set_ip_counter < 3) then --Wait 3 Clock cycles before beginning next transaction
set_ip_counter <= set_ip_counter + 1;
elsif ((transaction_finished = '1') and (set_ip_counter = 3)) then
cmdaddrdata_set <= x"0600_0000_0000_0000_0000"; --SPI WRITE ENABLE
byte_count_set <= x"0000_0000";
start_transaction <= '1';
set_ip_counter <= 0;
if (page_prog = '0') then
write_spi_state <= SUBSECTOR_ERASE;
page_prog <= '1';
elsif (page_prog = '1') then
write_spi_state <= PAGE_PROGRAM;
end if;
end if;
when SUBSECTOR_ERASE =>
write_spi_state_is <= "0001";
start_transaction <= '0';
if (set_ip_counter < 3) then --Wait 3 Clock cycles before beginning next transaction
set_ip_counter <= set_ip_counter + 1;
elsif ((transaction_finished = '1') and (set_ip_counter = 3)) then
cmdaddrdata_set <= x"20F0_0000_0000_0000_0000"; --SPI SUBSECTOR ERASE 4kB
byte_count_set <= x"0000_0003";
start_transaction <= '1';
set_ip_counter <= 0;
write_spi_state <= WRITE_ENABLE;
end if;
when PAGE_PROGRAM =>
write_spi_state_is <= "0010";
start_transaction <= '0';
if (set_ip_counter < 3) then --Wait 3 Clock cycles before beginning next transaction
set_ip_counter <= set_ip_counter + 1;
elsif ((transaction_finished = '1') and (set_ip_counter = 3)) then
set_ip_counter <= 0;
if (page_prog_counter = 0) then
page_prog_counter <= page_prog_counter + 1;
--myIP_set -- 32 bits
--myMAC_set -- 48 bits
--destIP_set -- 32 bits
cmdaddrdata_set(79 downto 40) <= x"02F0_0000_01"; --SPI PAGE PROGRAM 256 BYTES
cmdaddrdata_set(39 downto 8) <= myIP_set_s50(31 downto 0);
cmdaddrdata_set(7 downto 0) <= myMAC_set_s50(47 downto 40);
byte_count_set <= x"0000_0009";
write_spi_state <= WRITE_ENABLE; -- Write enable must be issued before every write operation
start_transaction <= '1';
elsif (page_prog_counter = 1) then
page_prog_counter <= page_prog_counter + 1;
cmdaddrdata_set(79 downto 48) <= x"02F0_0006"; --SPI PAGE PROGRAM 256 BYTES
cmdaddrdata_set(47 downto 8) <= myMAC_set_s50(39 downto 0);
cmdaddrdata_set(7 downto 0) <= destIP_set_s50(31 downto 24);
byte_count_set <= x"0000_0009";
write_spi_state <= WRITE_ENABLE; -- Write enable must be issued before every write operation
start_transaction <= '1';
elsif (page_prog_counter = 2) then
page_prog_counter <= page_prog_counter + 1;
cmdaddrdata_set(79 downto 48) <= x"02F0_000C"; --SPI PAGE PROGRAM 256 BYTES
cmdaddrdata_set(47 downto 24) <= destIP_set_s50(23 downto 0);
cmdaddrdata_set(23 downto 0) <= x"0000_00";
byte_count_set <= x"0000_0006";
start_transaction <= '1';
elsif (page_prog_counter = 3) then
page_prog_counter <= 0;
write_spi_state <= RESET;
page_prog <= '0';
set_default_ip <= '0';
system_start <= '0'; -- This will 'reset' the system_start flag and the FSM will check for the IP in SPI Flash again
end if;
end if;
when RESET =>
write_spi_state_is <= "0011";
start_transaction <= '0';
set_ip_counter <= set_ip_counter + 1;
if( set_ip_counter = 10) then
ip_config_state <= RESET;
set_ip_counter <= 0;
write_spi_state <= WRITE_ENABLE;
end if;
end case;
when RESET =>
page_prog_counter <= 0;
start_transaction <= '0';
spi_ip_config_state_is <= "0100";
if (transaction_finished = '1') then
cmdaddrdata_set <= x"0000_0000_0000_0000_0000";
byte_count_set <= x"0000_0000";
ip_config_state <= IDLE;
end if;
when others =>
spi_ip_config_state_is <= "0101";
ip_config_state <= RESET;
end case;
end if;
end process;
spi_read_write_core_registers: process(clk_50) -- State machine that handles the signals necessary to write to or read from a core register
begin
if rising_edge(clk_50) then
if (set_default_ip = '1') then
myIP_i <= default_IP;
myMAC_i <= default_MAC;
destIP_i <= default_destIP;
end if;
case spi_state is -- State machine that handles the signals necessary to perform a single write to or read to and from a core register in the axi_quad_spi
when SETUP =>
spi_aresetn <= '0';
if (start_transaction = '1') then
transaction_finished <= '0';
spi_state <= IDLE;
spi_counter <= 0;
spi_aresetn <= '1';
end if;
when IDLE =>
spi_awvalid <= '0';
spi_wvalid <= '0';
spi_bready <= '0';
spi_counter <= 0;
spi_rready <= '0';
spi_state_is <= "0000";
case spi_state_control is -- State machine that handles the higher level flow (above spi_state) in order to execute a proper transaction via the axi_quad_spi (Nested within spi_state = IDLE)
when CLEAR_FIFO => -- Clear Rx and Tx FIFO's in axi_quad_spi
spi_state_control_is <= "0000";
araddr_set <= "1100100"; --x"64";
awaddr_set <= "1100000"; --x"60";
wdata_set <= x"00000186";
spi_state <= WAIT_WRITE;
spi_state_control <= WRITE_CMD_ADDR_DATA;
byte_transfer_counter <= to_integer(unsigned(byte_count_set));
cmdaddrdata := to_bitvector(cmdaddrdata_set);
when WRITE_CMD_ADDR_DATA => -- Write the command, address, and data into the Tx FIFO in axi_quad_spi
spi_state_control_is <= "0001";
araddr_set <= "1110100"; --x"74";
awaddr_set <= "1101000"; --x"68";
wdata_set <= x"000000" & to_stdlogicvector(cmdaddrdata(79 downto 72));
byte_transfer_counter <= byte_transfer_counter - 1;
cmdaddrdata := cmdaddrdata sll 8;
spi_state <= WAIT_WRITE;
if (byte_transfer_counter = 0) then
spi_state_control <= ASSERT_SS;
end if;
when ASSERT_SS => -- Assert Slave Select by writing x"00" into the x"70" registers in axi_quad_spi
spi_state_control_is <= "0010";
araddr_set <= "1100100"; --x"64"
awaddr_set <= "1110000"; --x"70";
wdata_set <= x"00000000";
spi_state <= WAIT_WRITE;
spi_state_control <= DEASSERT_INHIB;
when DEASSERT_INHIB => -- Deassert inhibit bit in order to allow the Master (FPGA) to communicate with the Slave (SPI Flash)
spi_state_control_is <= "0011";
araddr_set <= "1100100"; --x"64"
awaddr_set <= "1100000"; --x"60";
wdata_set <= x"00000086";
spi_counter <= 0;
spi_state <= WAIT_WRITE;
spi_state_control <= CLEAR_SS;
when CLEAR_SS => -- Clear Slave Select by pulling the SS line high after 400 clock cycles (default)
spi_state_control_is <= "0100";
araddr_set <= "1100100"; --x"64"
awaddr_set <= "1110000"; --x"70";
spi_counter <= spi_counter + 1;
if (spi_counter > 400) then
wdata_set <= x"00000001";
spi_counter <= 0;
spi_state <= WAIT_WRITE;
spi_state_control <= ASSERT_INHIB;
end if;
when ASSERT_INHIB => -- Assert inhibit bit in order to inhibit the Master (FPGA) to communicate with the Slave (SPI Flash)
spi_state_control_is <= "0101";
araddr_set <= "1111000"; --x"78"
awaddr_set <= "1100000"; --x"60";
wdata_set <= x"00000186";
spi_counter <= spi_counter + 1;
if((cmdaddrdata_set(79 downto 72) = x"20") and (spi_counter = 25_000_000)) then -- Need to wait 0.5 s for successful SUBSECTOR_ERASE operation after SS is pulled high
spi_state <= WAIT_WRITE;
spi_state_control <= READ_SPI_DATA;
byte_transfer_counter <= to_integer(unsigned(byte_count_set)) + 1;
spi_counter <= 0;
elsif ((cmdaddrdata_set(79 downto 72) = x"02") and (spi_counter = 7500))then -- Need to wait 0.15 ms for successful PAGE_PROGRAM operation after SS is pulled high
spi_state <= WAIT_WRITE;
spi_state_control <= READ_SPI_DATA;
byte_transfer_counter <= to_integer(unsigned(byte_count_set)) + 1;
spi_counter <= 0;
elsif ((cmdaddrdata_set(79 downto 72) /= x"20") and (cmdaddrdata_set(79 downto 72) /= x"02")) then
spi_state <= WAIT_WRITE;
spi_state_control <= READ_SPI_DATA;
byte_transfer_counter <= to_integer(unsigned(byte_count_set)) + 1;
spi_counter <= 0;
end if;
when READ_SPI_DATA => -- Read SPI data in the Rx FIFO in axi_quad_spi
spi_state_control_is <= "0110";
araddr_set <= "1101100"; --x"6C";
awaddr_set <= "1111111"; --x"7F"; --Address does not exist. Just there so core registers are not written too
wdata_set <= x"00000000"; --Dummy data
byte_transfer_counter <= byte_transfer_counter - 1; --Read occupancy register
spi_state <= WAIT_READ;
if ((ip_config_state = CHECK_IP_SET) and (byte_transfer_counter = 0)) then
ip_set_flag <= spi_rdata(7 downto 0);
end if;
if (ip_config_state = SET_IP) then
if (second_transaction = '0') then
if ((byte_transfer_counter >= 8) and (byte_transfer_counter <= 11)) then
myIP_i((byte_transfer_counter-8)*8+7 downto (byte_transfer_counter-8)*8) <= spi_rdata(7 downto 0);
elsif ((byte_transfer_counter >= 2) and (byte_transfer_counter <= 7)) then
myMAC_i((byte_transfer_counter-2)*8+7 downto (byte_transfer_counter-2)*8) <= spi_rdata(7 downto 0);
elsif ((byte_transfer_counter >= 0) and (byte_transfer_counter <= 1)) then
destIP_i((byte_transfer_counter+2)*8+7 downto (byte_transfer_counter+2)*8) <= spi_rdata(7 downto 0);
end if;
elsif (second_transaction = '1') then
if ((byte_transfer_counter >= 0) and (byte_transfer_counter <= 1)) then
destIP_i((byte_transfer_counter)*8+7 downto (byte_transfer_counter)*8) <= spi_rdata(7 downto 0);
end if;
end if;
end if;
if (byte_transfer_counter = 0) then
spi_state_control <= RESET;
end if;
when RESET =>
spi_state_control_is <= "0111";
transaction_finished <= '1';
spi_state <= SETUP;
spi_state_control <= CLEAR_FIFO;
--end if;
when others =>
araddr_set <= "0000000";
awaddr_set <= "0000000";
wdata_set <= x"00000000";
transaction_finished <= '1';
spi_state_control_is <= "1111"; --Error State
spi_state <= SETUP;
spi_state_control <= CLEAR_FIFO;
end case;
when WAIT_WRITE => -- State for writing to the axi_quad_spi register
spi_state_is <= "0001";
spi_counter <= spi_counter + 1;
spi_wstrb <= "0000";
if spi_counter = 5 then
spi_state <= WRITE;
spi_counter <= 0;
end if;
when WRITE => -- State for writing to the axi_quad_spi register
spi_state_is <= "0010";
spi_awaddr <= awaddr_set;
spi_wdata <= wdata_set;
spi_awvalid <= '1';
spi_wvalid <= '1';
spi_wstrb <= "1111";
spi_bready <= '1';
if spi_awready = '1' or spi_wready = '1' then
spi_state <= FINISH_WRITE;
spi_wstrb <= "0000";
spi_awaddr <= "0000000";
spi_wdata <= x"00000000";
spi_awvalid <= '0';
spi_wvalid <= '0';
end if;
when FINISH_WRITE => -- State for writing to the axi_quad_spi register
spi_state_is <= "0011";
spi_awaddr <= "0000000";
spi_wdata <= x"00000000";
spi_awvalid <= '0';
spi_wvalid <= '0';
if spi_bvalid = '1' then
spi_bready <= '0';
spi_state <= IDLE;
end if;
when WAIT_READ => -- State for reading from the axi_quad_spi register
spi_state_is <= "0100";
spi_counter <= spi_counter + 1;
if spi_counter = 10 then
spi_state <= READ;
spi_counter <= 0;
end if;
when READ => -- State for reading from the axi_quad_spi register
spi_state_is <= "0101";
spi_counter <= spi_counter + 1;
spi_araddr <= araddr_set;
spi_arvalid <= '1';
spi_rready <= '1';
if spi_counter = 10 then
spi_state <= FINISH_READ;
spi_counter <= 0;
end if;
when FINISH_READ => -- State for reading from the axi_quad_spi register
spi_state_is <= "0110";
if spi_arready = '1' then
spi_araddr <= "0000000";
spi_arvalid <= '0';
spi_arvalid <= '0';
spi_counter <= 0;
end if;
spi_state <= IDLE;
end case;
end if;
end process;
--spi_cnt <= std_logic_vector(to_unsigned(spi_counter, spi_cnt'length));
spi_cnt <= std_logic_vector(to_unsigned(spi_counter, 32));
---------------------------------------------------------
--------- Clock Domain Crossing Sync Block --------------
---------------------------------------------------------
-- sync output signals to 125 Mhz clock
CDCC_50to125: CDCC
generic map(NUMBER_OF_BITS => 113)
port map(
clk_src => clk_50,
clk_dst => clk_125,
data_in(112) => flash_busy_i,
data_in(111 downto 80) => myIP_i,
data_in(79 downto 32) => myMAC_i,
data_in(31 downto 0) => destIP_i,
data_out_s(112) => flash_busy,
data_out_s(111 downto 80) => myIP,
data_out_s(79 downto 32) => myMAC,
data_out_s(31 downto 0) => destIP
);
-- sync input signals to 50 Mhz clock
CDCC_125to50: CDCC
generic map(NUMBER_OF_BITS => 113)
port map(
clk_src => clk_125,
clk_dst => clk_50,
data_in(112) => newIP_start,
data_in(111 downto 80) => myIP_set,
data_in(79 downto 32) => myMAC_set,
data_in(31 downto 0) => destIP_set,
data_out_s(112) => newIP_start_s50,
data_out_s(111 downto 80) => myIP_set_s50,
data_out_s(79 downto 32) => myMAC_set_s50,
data_out_s(31 downto 0) => destIP_set_s50
);
---------------------------------------------------------
---------------------------------------------------------
---------------------------------------------------------
--ila_top: ila_spi_flash
-- port map (
-- clk => clk_50,
-- probe0 => read_out
-- );
-- read_out(31 downto 0) <= spi_rdata;
-- read_out(38 downto 32) <= (others => '0');
-- read_out(40 downto 39) <= spi_rresp;
-- read_out(41) <= spi_awready;
-- read_out(43 downto 42) <= spi_bresp;
-- read_out(44) <= spi_bvalid;
-- read_out(45) <= spi_awvalid;
-- read_out(46) <= spi_wvalid;
-- read_out(47) <= spi_aresetn;
-- read_out(51 downto 48) <= spi_wstrb;
-- read_out(83 downto 52) <= spi_wdata;
-- read_out(90 downto 84) <= spi_awaddr;
-- read_out(91) <= spi_bready;
-- read_out(92) <= spi_wready;
-- read_out(93) <= spi_arvalid;
-- read_out(94) <= spi_rready;
-- read_out(98 downto 95) <= spi_state_is;
-- read_out(99) <= spi_rvalid;
-- read_out(100) <= spi_arready;
-- read_out(107 downto 101) <= spi_araddr;
-- read_out(108) <= '0';
-- read_out(109) <= '0';
-- read_out(110) <= '0';
-- read_out(114 downto 111) <= spi_state_control_is;
-- read_out(115) <= transaction_finished;
-- read_out(119 downto 116) <= spi_ip_config_state_is;
-- read_out(127 downto 120) <= ip_set_flag;
-- read_out(128) <= newip_start;
-- read_out(208 downto 129) <= cmdaddrdata_set;
-- read_out(212 downto 209) <= write_spi_state_is;
-- read_out(244 downto 213) <= spi_cnt;
--vio_top: vio_0
-- port map (
-- clk => clk_200,
-- probe_out0 => start_vio,
-- probe_out1 => system_start_vio,
-- probe_out2 => cmdaddrdata_vio,
-- probe_out3 => byte_count_vio,
-- probe_out4 => new_ip_vio,
-- probe_out5 => set_ip_vio
-- );
end Behavioral;
| gpl-3.0 | 12c5edc3959c1bc684045d2e87436005 | 0.430596 | 4.574733 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/FIR_Filter/fir_filter.vhd | 1 | 2,979 | --------------------------------------------------------------------------------------------------
-- FIR Filter
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- PACKAGE
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.dsp_pkg.all;
package fir_filter_pkg is
--FIR filter component declaration
component fir_filter is
generic( h : coefficient_array);
port( clk : in std_logic;
rst : in std_logic;
x : in sig;
y : out fir_sig);
end component;
end package;
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.dsp_pkg.all;
use work.fir_tap_pkg.all;
entity fir_filter is
generic( h : coefficient_array);
port( clk : in std_logic;
rst : in std_logic;
x : in sig;
y : out fir_sig);
end fir_filter;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture behave of fir_filter is
signal x_chain : sig_array(h'range) := (others => (others => '0'));
signal running_sum : fir_sig_array(h'range) := (others => (others => '0'));
begin
filter_loop : for tap in h'low to h'high generate
begin
head_tap_gen : if tap = h'low generate
head_tap : fir_tap
port map(clk => clk,
rst => rst,
coef => h(tap),
sig_in => x,
sig_out => x_chain(tap),
sum_in => (others => '0'),
sum_out => running_sum(tap));
end generate; --if head tap
tail_taps_gen : if tap /= h'low generate
tail_tap : fir_tap
port map(clk => clk,
rst => rst,
coef => h(tap),
sig_in => x_chain(tap-1),
sig_out => x_chain(tap),
sum_in => running_sum(tap-1),
sum_out => running_sum(tap));
end generate; --if tail taps
end generate;
--output end of the running sum
y <= running_sum(h'high);
end behave;
| mit | ccb23bd8a3768561e88f8a0eaed22c6f | 0.330312 | 5.153979 | false | false | false | false |
gyurco/ZX_Spectrum-128K_MIST | sp0256.vhd | 1 | 13,381 | ---------------------------------------------------------------------------------
-- sp0256 by Dar ([email protected]) (14/04/2018)
-- http://darfpga.blogspot.fr
---------------------------------------------------------------------------------
-- Educational use only
-- Do not redistribute synthetized file with roms
-- Do not redistribute roms whatever the form
-- Use at your own risk
---------------------------------------------------------------------------------
--
-- SP0256-al2 prom decoding scheme and speech synthesis algorithm are from :
--
-- Copyright Joseph Zbiciak, all rights reserved.
-- Copyright tim lindner, all rights reserved.
--
-- See C source code and license in sp0256.c from MAME source
--
-- VHDL code is by Dar.
--
---------------------------------------------------------------------------------
--
-- One allophone is made of N parts (called here after lines), each part has a
-- 16 bytes descriptor. One descriptor (for one part) contains one repeat value
-- one amplitude value, one period value and 2x6 filtering coefficients.
--
-- for line_cnt from 0 to nb_line-1 (part)
-- for line_rpt from 0 to line_rpt-1 (repeat)
-- for per_cnt from 0 to line_per-1 (period)
-- produce 1 sample
--
-- One sample is the output of the 6 stages filter. Each filter stage is fed by
-- the output of the previous stage, the first stage is fed by the source sample
--
-- when line_per != 0 source sample is set to amplitude value only once at the
-- begin of each repeat (per_cnt==0) then source sample is set to 0
--
-- when line_per == 0 source sample is set to amplitude value only at the begin
-- of each repeat (per_cnt==0) then source sample sign is toggled (+/-) when then
-- random noise generator lsb equal 1. In that case actual line_per is set to 64
--
--
-- Sound sample frequency is 10kHz. I make a 25 stages linear state machine
-- running at 250kHz that produce one sound sample per cycle.
--
-- As long as one allophones is available the state machine runs permanently and
-- there is zero latency between allophones.
--
-- During one (each) cycle the state machine:
--
-- - fetch new allophone or go on with current one if not finished
-- - get allophone first line descriptor address from rom entry table
-- - get allophone nb_line from rom entry table and jump to first line address
-- - get allophone line_rpt from rom current line descriptor
-- - get allophone amplitude from rom current line descriptor
-- manage source amplitude, reset filter if needed
-- - get allophone line_per from rom current line descriptor
-- - address filter coefficients F/B within rom current line descriptor,
-- feed filter input, update filter state with computation output
-- - rescale last filter stage output to audio output
-- - manage per_cnt, rpt_cnt, line_cnt and random noise generator
--
-- Filter computation:
--
-- Filter coefficients F or B index is get from rom current line descriptor
-- (address managed by state machine), value is converted thru coeff_array
-- table. Coefficient index has a sign bit to be managed:
--
-- if index sign bit = 0, filter coefficient <= -coeff_array(index)
-- if index sign bit = 1, filter coefficient <= coeff_array(-index)
--
-- During one state machine cycle each filter is updated once.
-- One filter update require two state machine steps:
--
-- step 1
-- sum_in1 <= filter input
-- sum_in2 <= filter coefficient F * filter state z1 / 256
-- sum_out <= sum_in1 + sum_in2
-- step 2
-- sum_in1 <= sum_out
-- sum_in2 <= filter coefficient B * filter state z2 / 512
-- sum_out <= sum_in1 + sum_in2
-- filter state z1 <= sum_in1 + sum_in2
-- filter state z2 <= filter state z1
--
-- (sum_out will be limited to -32768/+32767)
--
-- Audio output scaling to 10bits unsigned:
--
-- what :
-- Last filter output is limited to -8192/+8191
-- Then divided by 16 => -512/+511
-- Then offset by 512 => 0/1023
--
-- how:
-- if X > 8191, Y <= 1023
-- elsif X < -8192, Y <= 0
-- else Y <= (X/16)+512
--
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity sp0256 is
port
(
clock : in std_logic;
clock_250k_en : in std_logic;
reset : in std_logic;
input_rdy : out std_logic;
allophone : in std_logic_vector(5 downto 0);
trig_allophone : in std_logic;
audio_out : out std_logic_vector(9 downto 0)
);
end sp0256;
architecture syn of sp0256 is
signal clock_n : std_logic;
signal rom_addr : std_logic_vector(11 downto 0);
signal rom_do : std_logic_vector( 7 downto 0);
signal stage : integer range 0 to 24; -- stage counter 0-24;
signal allophone_latch : std_logic_vector(5 downto 0);
signal allo_entry : std_logic_vector(7 downto 0);
signal allo_addr_lsb, allo_addr_msb : std_logic_vector(7 downto 0);
signal allo_nb_line : std_logic_vector(7 downto 0);
signal line_rpt, line_per : std_logic_vector(7 downto 0);
signal line_amp_lsb, line_amp_msb : std_logic_vector(7 downto 0);
signal amp, filter, coeff : signed(15 downto 0);
signal sum_in2 : signed(31 downto 0);
signal sum_in1,sum_out_ul : signed(15 downto 0);
signal sum_out : signed(15 downto 0);
signal divider : std_logic;
signal audio : signed(15 downto 0);
signal is_noise : std_logic;
signal noise_rng : std_logic_vector(15 downto 0) := X"0001";
signal f0_z1,f0_z2 : signed(15 downto 0);
signal f1_z1,f1_z2 : signed(15 downto 0);
signal f2_z1,f2_z2 : signed(15 downto 0);
signal f3_z1,f3_z2 : signed(15 downto 0);
signal f4_z1,f4_z2 : signed(15 downto 0);
signal f5_z1,f5_z2 : signed(15 downto 0);
signal input_rdy_in : std_logic;
signal sound_on : std_logic := '0';
signal trig_allophone_r : std_logic;
signal line_cnt, rpt_cnt, per_cnt : std_logic_vector(7 downto 0);
signal coeff_idx : std_logic_vector(6 downto 0);
type coeff_array_t is array(0 to 127) of integer range 0 to 511;
signal coeff_array : coeff_array_t := (
0, 9, 17, 25, 33, 41, 49, 57,
65, 73, 81, 89, 97, 105, 113, 121,
129, 137, 145, 153, 161, 169, 177, 185,
193, 201, 209, 217, 225, 233, 241, 249,
257, 265, 273, 281, 289, 297, 301, 305,
309, 313, 317, 321, 325, 329, 333, 337,
341, 345, 349, 353, 357, 361, 365, 369,
373, 377, 381, 385, 389, 393, 397, 401,
405, 409, 413, 417, 421, 425, 427, 429,
431, 433, 435, 437, 439, 441, 443, 445,
447, 449, 451, 453, 455, 457, 459, 461,
463, 465, 467, 469, 471, 473, 475, 477,
479, 481, 482, 483, 484, 485, 486, 487,
488, 489, 490, 491, 492, 493, 494, 495,
496, 497, 498, 499, 500, 501, 502, 503,
504, 505, 506, 507, 508, 509, 510, 511);
begin
input_rdy <= input_rdy_in;
-- stage counter : Fs=250k/25 = 10kHz
process (clock, reset)
begin
if reset='1' then
stage <= 0;
elsif rising_edge(clock) then
if clock_250k_en = '1' then
if stage >= 24 then
stage <= 0;
else
stage <= stage + 1;
end if;
end if;
end if;
end process;
process (clock, reset)
begin
if reset='1' then
input_rdy_in <= '1';
sound_on <= '0';
noise_rng <= X"0001";
elsif rising_edge(clock) then
trig_allophone_r <= trig_allophone;
if trig_allophone = '1' and trig_allophone_r = '0' then
input_rdy_in <= '0';
allophone_latch <= allophone;
end if;
if clock_250k_en = '1' then
if sound_on = '0' then
if stage = 0 and input_rdy_in = '0' then
allo_entry <= allophone_latch*"11";
rom_addr <= X"0"&(allophone_latch*"11");
line_cnt <= (others => '0');
rpt_cnt <= (others => '0');
per_cnt <= (others => '0');
sound_on <= '1';
input_rdy_in <= '1';
end if;
else -- sound is on
case stage is
when 0 =>
rom_addr <= X"0"&allo_entry;
when 1 =>
allo_addr_msb <= rom_do;
rom_addr <= rom_addr + '1';
when 2 =>
allo_addr_lsb <= rom_do;
rom_addr <= rom_addr + '1';
when 3 =>
allo_nb_line <= rom_do - '1';
rom_addr <= (allo_addr_lsb +line_cnt) & X"0";
when 4 =>
line_rpt <= rom_do - '1';
rom_addr <= rom_addr + '1';
when 5 =>
line_amp_msb <= rom_do;
rom_addr <= rom_addr + '1';
when 6 =>
if per_cnt = X"00" then
amp <= signed(line_amp_msb & rom_do);
else
if is_noise = '1' then
if noise_rng(0) = '1' then
amp <= -amp;
end if;
else
amp <= (others => '0');
end if;
end if;
if per_cnt = X"00"then
f0_z1 <= (others => '0'); f0_z2 <= (others => '0');
f1_z1 <= (others => '0'); f1_z2 <= (others => '0');
f2_z1 <= (others => '0'); f2_z2 <= (others => '0');
f3_z1 <= (others => '0'); f3_z2 <= (others => '0');
f4_z1 <= (others => '0'); f4_z2 <= (others => '0');
f5_z1 <= (others => '0'); f5_z2 <= (others => '0');
end if;
rom_addr <= rom_addr + '1';
when 7 =>
if rom_do = X"00" then
line_per <= X"40";
is_noise <= '1';
else
line_per <= rom_do - '1';
is_noise <= '0';
end if;
sum_in1 <= amp;
filter <= f0_z1;
divider <= '0';
rom_addr <= rom_addr + '1';
when 8 =>
sum_in1 <= sum_out;
filter <= f0_z2;
divider <= '1';
rom_addr <= rom_addr + '1';
when 9 =>
f0_z1 <= sum_out;
f0_z2 <= f0_z1;
sum_in1 <= sum_out;
filter <= f1_z1;
divider <= '0';
rom_addr <= rom_addr + '1';
when 10 =>
sum_in1 <= sum_out;
filter <= f1_z2;
divider <= '1';
rom_addr <= rom_addr + '1';
when 11 =>
f1_z1 <= sum_out;
f1_z2 <= f1_z1;
sum_in1 <= sum_out;
filter <= f2_z1;
divider <= '0';
rom_addr <= rom_addr + '1';
when 12 =>
sum_in1 <= sum_out;
filter <= f2_z2;
divider <= '1';
rom_addr <= rom_addr + '1';
when 13 =>
f2_z1 <= sum_out;
f2_z2 <= f2_z1;
sum_in1 <= sum_out;
filter <= f3_z1;
divider <= '0';
rom_addr <= rom_addr + '1';
when 14 =>
sum_in1 <= sum_out;
filter <= f3_z2;
divider <= '1';
rom_addr <= rom_addr + '1';
when 15 =>
f3_z1 <= sum_out;
f3_z2 <= f3_z1;
sum_in1 <= sum_out;
filter <= f4_z1;
divider <= '0';
rom_addr <= rom_addr + '1';
when 16 =>
sum_in1 <= sum_out;
filter <= f4_z2;
divider <= '1';
rom_addr <= rom_addr + '1';
when 17 =>
f4_z1 <= sum_out;
f4_z2 <= f4_z1;
sum_in1 <= sum_out;
filter <= f5_z1;
divider <= '0';
rom_addr <= rom_addr + '1';
when 18 =>
sum_in1 <= sum_out;
filter <= f5_z2;
divider <= '1';
rom_addr <= rom_addr + '1';
when 19 =>
f5_z1 <= sum_out;
f5_z2 <= f5_z1;
if sum_out > 510*16 then
audio <= to_signed(1023,16);
elsif sum_out < -510*16 then
audio <= to_signed(0,16);
else
audio <= (sum_out/16)+X"0200";
end if;
when 20 =>
if per_cnt >= line_per then
per_cnt <= (others => '0');
if rpt_cnt >= line_rpt then
rpt_cnt <= (others => '0');
if line_cnt >= allo_nb_line then
line_cnt <= (others => '0');
sound_on <= '0';
else
line_cnt <= line_cnt + '1';
end if;
is_noise <= '0';
else
rpt_cnt <= rpt_cnt + '1';
end if;
else
per_cnt <= per_cnt + '1';
end if;
if noise_rng(0) = '1' then
noise_rng <= ('0' & noise_rng(15 downto 1) ) xor X"4001";
else
noise_rng <= '0' & noise_rng(15 downto 1);
end if;
when others => null;
end case;
end if;
end if;
end if;
end process;
audio_out <= std_logic_vector(unsigned(audio(9 downto 0)));
-- filter computation
coeff_idx <= rom_do(6 downto 0) when rom_do(7)='0' else
not(rom_do(6 downto 0)) + '1';
coeff <= -to_signed(coeff_array(to_integer(unsigned(coeff_idx))),16) when rom_do(7)='0' else
to_signed(coeff_array(to_integer(unsigned(coeff_idx))),16);
sum_in2 <= (filter * coeff) / 256 when divider = '0' else
(filter * coeff) / 512 ;
sum_out_ul <= sum_in1 + sum_in2(15 downto 0);
sum_out <= to_signed( 32767,16) when sum_out_ul > 32767 else
to_signed(-32768,16) when sum_out_ul < -32768 else
sum_out_ul;
-- sp0256-al2 prom (decoded)
sp0256_al2_decoded : entity work.sp0256_al2_decoded
port map(
clk => clock,
addr => rom_addr,
data => rom_do
);
end syn;
| gpl-2.0 | 34d67c96aa2e8814aa79539557686769 | 0.52582 | 3.030118 | false | false | false | false |
HackLinux/ION | src/rtl/buses/ion_wishbone_arbiter.vhdl | 1 | 6,016 | --------------------------------------------------------------------------------
-- ion_wishbone_arbiter.vhdl -- Simple arbiter for ION refill ports.
--------------------------------------------------------------------------------
--
-- This is not a general purpose WB arbiter; it is meant to share a single
-- external memory interface between the two refill ports of the ION core,
-- data and code.
--
-- The data port is given priority: when a cycle is requested on the data port,
-- it will be given control as as soon as any ongoing cycle on the code
-- port is finished (as signalled by deassertion of the WB CYC signal).
-- The data port will lose control as soon as its cycle is over.
-- This scheme has no memory: the above is the only rule.
-- This works because both ports will have gaps between successive refills,
-- and because the ports are not going to lock each other: if the code bus
-- starved, the data cache would eventually stop issuing data cycles.
--
-- REFERENCES
-- [1] ion_design_notes.pdf -- ION project design notes.
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.ION_INTERFACES_PKG.all;
use work.ION_INTERNAL_PKG.all;
entity ION_WISHBONE_ARBITER is
port(
CLK_I : in std_logic;
RESET_I : in std_logic;
-- Connect to core code refill port.
CODE_MOSI_I : in t_wishbone_mosi;
CODE_MISO_O : out t_wishbone_miso;
-- Connect to core data refill port.
DATA_MOSI_I : in t_wishbone_mosi;
DATA_MISO_O : out t_wishbone_miso;
-- Connect to memory interface.
MEM_MOSI_0 : out t_wishbone_mosi;
MEM_MISO_I : in t_wishbone_miso
);
end;
architecture rtl of ION_WISHBONE_ARBITER is
signal data_port_selected : std_logic;
begin
----------------------------------------------------------------------------
-- Arbitration state machine.
-- Perhaps calling this a "state machine" is giving it too much credit
-- but the simplicity is intended.
-- We know there are going to be inactive gaps in both buses as cache hits
-- are served; we rely on those gaps to switch masters.
selection_register:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if RESET_I='1' then
data_port_selected <= '0';
else
if data_port_selected = '0' then
-- Select data port as soon as there is a data cycle pending
-- AND the code port is inactive.
-- (So we won't break an ongoing CODE cycle.)
if DATA_MOSI_I.cyc = '1' and CODE_MOSI_I.cyc = '0' then
data_port_selected <= '1';
end if;
else
-- Deselect data port as soon as an ongoing data cycle ends.
-- (So we won't break an ongoing DATA cycle.)
if DATA_MOSI_I.cyc = '0' then
data_port_selected <= '0';
end if;
end if;
end if;
end if;
end process selection_register;
----------------------------------------------------------------------------
-- Bus multiplexors.
-- The memory MOSI is multiplexed according to the selected master port.
with data_port_selected select MEM_MOSI_0 <=
DATA_MOSI_I when '1',
CODE_MOSI_I when others;
-- The DATA master port MISO will be connected to the memory MISO as long
-- as it is selected, otherwise it is stalled.
with data_port_selected select DATA_MISO_O.ack <=
MEM_MISO_I.ack when '1',
'0' when others;
with data_port_selected select DATA_MISO_O.stall <=
MEM_MISO_I.stall when '1',
'1' when others;
DATA_MISO_O.dat <= MEM_MISO_I.dat;
-- The CODE master port MISO will be connected to the memory MISO as long
-- as it is selected, otherwise it is stalled.
with data_port_selected select CODE_MISO_O.ack <=
MEM_MISO_I.ack when '0',
'0' when others;
with data_port_selected select CODE_MISO_O.stall <=
MEM_MISO_I.stall when '0',
'1' when others;
CODE_MISO_O.dat <= MEM_MISO_I.dat;
end architecture rtl;
| lgpl-3.0 | 0bfc4b4692df1bd2a166bd23dd704205 | 0.524767 | 4.692668 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/EPROC_OUT2.vhd | 1 | 5,653 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 18/03/2015
--! Module Name: EPROC_OUT2
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee,work;
use ieee.std_logic_1164.all;
use work.all;
--! E-link processor, 2bit output
entity EPROC_OUT2 is
generic (
do_generate : boolean := true;
includeNoEncodingCase : boolean := true
);
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
ENA : in std_logic;
swap_outbits : in std_logic;
getDataTrig : out std_logic; -- @ bitCLKx4
ENCODING : in std_logic_vector (3 downto 0);
EDATA_OUT : out std_logic_vector (1 downto 0);
TTCin : in std_logic_vector (1 downto 0);
DATA_IN : in std_logic_vector (9 downto 0);
DATA_RDY : in std_logic
);
end EPROC_OUT2;
architecture Behavioral of EPROC_OUT2 is
constant zeros2bit : std_logic_vector (1 downto 0) := (others=>'0');
signal EdataOUT_ENC8b10b_case, EdataOUT_direct_case, EdataOUT_HDLC_case, EdataOUT_TTC0_case : std_logic_vector (1 downto 0);
signal rst_s, rst_case000, rst_case001, rst_case010, rst_case011 : std_logic;
signal getDataTrig_ENC8b10b_case, getDataTrig_direct_case, getDataTrig_HDLC_case, getDataTrig_TTC_case : std_logic;
signal edata_out_s : std_logic_vector (1 downto 0);
begin
gen_enabled: if do_generate = true generate
rst_s <= rst or (not ENA);
-------------------------------------------------------------------------------------------
-- case 0: direct data, no delimeter...
-------------------------------------------------------------------------------------------
direct_data_enabled: if includeNoEncodingCase = true generate
rst_case000 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "000")) else '1';
direct_case: entity work.EPROC_OUT2_direct
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case000,
getDataTrig => getDataTrig_direct_case,
edataIN => DATA_IN,
edataINrdy => DATA_RDY,
EdataOUT => EdataOUT_direct_case
);
end generate direct_data_enabled;
--
direct_data_disabled: if includeNoEncodingCase = false generate
EdataOUT_direct_case <= (others=>'0');
end generate direct_data_disabled;
--
-------------------------------------------------------------------------------------------
-- case 1: DEC8b10b
-------------------------------------------------------------------------------------------
rst_case001 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "001")) else '1';
--
ENC8b10b_case: entity work.EPROC_OUT2_ENC8b10b
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case001,
getDataTrig => getDataTrig_ENC8b10b_case,
edataIN => DATA_IN,
edataINrdy => DATA_RDY,
EdataOUT => EdataOUT_ENC8b10b_case
);
--
-------------------------------------------------------------------------------------------
-- case 2: HDLC
-------------------------------------------------------------------------------------------
rst_case010 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "010")) else '1';
--
HDLC_case: entity work.EPROC_OUT2_HDLC
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case010,
getDataTrig => getDataTrig_HDLC_case, -- output, data request
edataIN => DATA_IN,
edataINrdy => DATA_RDY,
EdataOUT => EdataOUT_HDLC_case
);
--
-------------------------------------------------------------------------------------------
-- case 3: TTC-0
-------------------------------------------------------------------------------------------
rst_case011 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "011")) else '1';
--
getDataTrig_TTC_case <= '0'; --'1' when (ENCODING(2 downto 0) = "011") else '0';
--
ttc_r: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if rst_case011 = '1' then
EdataOUT_TTC0_case <= zeros2bit;
else
EdataOUT_TTC0_case <= TTCin;
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- output data and busy according to the encoding settings
-------------------------------------------------------------------------------------------
dataOUTmux: entity work.MUX4_Nbit
generic map (N=>2)
port map(
data0 => EdataOUT_direct_case,
data1 => EdataOUT_ENC8b10b_case,
data2 => EdataOUT_HDLC_case,
data3 => EdataOUT_TTC0_case,
sel => ENCODING(1 downto 0),
data_out => edata_out_s
);
--
getDataTrig <= ENA and (getDataTrig_TTC_case or getDataTrig_HDLC_case or getDataTrig_ENC8b10b_case or getDataTrig_direct_case);
--
end generate gen_enabled;
--
--
gen_disabled: if do_generate = false generate
edata_out_s <= (others=>'0');
getDataTrig <= '0';
end generate gen_disabled;
--
out_sel: process(swap_outbits,edata_out_s)
begin
if swap_outbits = '1' then
EDATA_OUT <= edata_out_s(0) & edata_out_s(1);
else
EDATA_OUT <= edata_out_s;
end if;
end process;
--
end Behavioral;
| gpl-3.0 | 84e3a3d5b98277fc185bfb0e1d3b1bff | 0.479745 | 3.858703 | false | false | false | false |
GustaMagik/RSA_Security_Token | VHDL_code/ver_B/RSA_Security_Token_USB_Version/rsa_512/trunk/rtl/montgomery_step.vhd | 1 | 8,248 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:40:41 11/01/2009
-- Design Name:
-- Module Name: module_with_fifo - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity montgomery_step is
port(
clk : in std_logic;
reset : in std_logic;
valid_in : in std_logic;
a : in std_logic_vector(15 downto 0);
b : in std_logic_vector(15 downto 0);
n : in std_logic_vector(15 downto 0);
s_prev : in std_logic_vector(15 downto 0);
n_c : in std_logic_vector(15 downto 0);
s : out std_logic_vector( 15 downto 0);
valid_out : out std_logic; -- es le valid out TODO : cambiar nombre
busy : out std_logic;
b_req : out std_logic;
a_out : out std_logic_vector(15 downto 0);
n_out : out std_logic_vector(15 downto 0); --señal que indica que el modulo está ocupado y no puede procesar nuevas peticiones
c_step : out std_logic; --genera un pulso cuando termina su computo para avisar al modulo superior
stop : in std_logic
);
end montgomery_step;
architecture Behavioral of montgomery_step is
component pe_wrapper
port(
clk : in std_logic;
reset : in std_logic;
ab_valid : in std_logic;
valid_in : in std_logic;
a : in std_logic_vector(15 downto 0);
b : in std_logic_vector(15 downto 0);
n : in std_logic_vector(15 downto 0);
s_prev : in std_logic_vector(15 downto 0);
n_c : in std_logic_vector(15 downto 0);
s : out std_logic_vector( 15 downto 0);
data_ready : out std_logic;
fifo_req : out std_logic;
m_val : out std_logic;
reset_the_PE : in std_logic); -- estamos preparados para aceptar el siguiente dato
end component;
--Inputs
signal ab_valid : std_logic;
signal valid_mont, fifo_read, m_val, valid_mont_out, reset_pe : std_logic;
--Outputs
--definimos los estados
type state_type is (wait_valid, wait_m, mont_proc, getting_results, prep_m, b_stable);
signal state, next_state : state_type;
signal counter, next_counter : std_logic_vector(7 downto 0); -- cuenta las palabras que han salido para ir cortando
--Señales nuevas
signal mont_input_a, mont_input_n, mont_input_s : std_logic_vector(15 downto 0);
signal reg_constant, next_reg_constant, next_reg_input, reg_input : std_logic_vector(47 downto 0);
signal reg_out, reg_out_1, reg_out_2, reg_out_3, reg_out_4 : std_logic_vector(31 downto 0);
signal next_reg_out : std_logic_vector(31 downto 0);
--Cadena de registros hacia fuera
signal reg_input_1, reg_input_2, reg_input_3, reg_input_4, reg_input_5 : std_logic_vector(47 downto 0);
begin
mont : pe_wrapper port map (
clk => clk,
reset => reset,
ab_valid => ab_valid,
a => mont_input_a,
b => b,
n => mont_input_n,
s_prev => mont_input_s,
n_c => n_c,
s => s,
valid_in => valid_mont,
data_ready => valid_mont_out,
m_val => m_val,
reset_the_PE => reset_pe
);
process(clk, reset)
begin
if(clk = '1' and clk'event) then
if(reset = '1')then
state <= wait_valid;
counter <= (others => '0');
reg_constant <= (others => '0');
reg_input <= (others => '0');
reg_input_1 <= (others => '0');
reg_input_2 <= (others => '0');
reg_input_3 <= (others => '0');
reg_input_4 <= (others => '0');
reg_out <= (others => '0');
reg_out_1 <= (others => '0');
reg_out_2 <= (others => '0');
reg_out_3 <= (others => '0');
reg_out_4 <= (others => '0');
else
reg_input <= next_reg_input;
reg_input_1 <= reg_input;
reg_input_2 <= reg_input_1;
reg_input_3 <= reg_input_2;
reg_input_4 <= reg_input_3;
reg_input_5 <= reg_input_4;
reg_out <= reg_input_4(47 downto 32) & reg_input_4(31 downto 16);
reg_out_1 <= reg_out;
reg_out_2 <= reg_out_1;
reg_out_3 <= reg_out_2;
reg_out_4 <= reg_out_3;
state <= next_state;
counter <= next_counter;
reg_constant <= next_reg_constant;
end if;
end if;
end process;
process(state, valid_in, m_val, a, n, s_prev, counter, valid_mont_out, stop, reg_constant, reg_input_5, reg_out_4)
begin
--reset_fifo <= '0';
next_reg_input <= a&n&s_prev; --Propagación de la entrada TODO add variable
--next_reg_out <= a&n; --Vamos retrasando la entrada TODO add variable
a_out <= reg_out_4(31 downto 16);
n_out <= reg_out_4(15 downto 0);
next_state <= state;
next_counter <= counter;
--write_fifos <= valid_in;
ab_valid <= '0';
valid_mont <= '0';
valid_out <= '0';
reset_pe <= '0';
busy <= '1';
b_req <= '0';
c_step <= '0';
--Todo esto es nuevo
mont_input_a <= (others => '0');
mont_input_n <= (others => '0');
mont_input_s <= (others => '0');
next_reg_constant <= reg_constant;
case state is
when wait_valid =>
busy <= '0'; --esperamos la peticion
reset_pe <= '1';
if(valid_in = '1') then
b_req <= '1'; --Solicitamos al modulo externo la b
next_state <= b_stable;
next_reg_constant <= a&n&s_prev; --TODO add variable
end if;
when b_stable =>
next_state <= prep_m;
when prep_m =>
mont_input_a <= reg_constant(47 downto 32); --TODO add this to sensitivity
mont_input_n <= reg_constant(31 downto 16);
mont_input_s <= reg_constant(15 downto 0);
ab_valid <= '1';
next_state <= wait_m;
when wait_m =>
--Mantenemos las entradas para que nos calcule m correctamente
mont_input_a <= reg_constant(47 downto 32); --TODO add this to sensitivity
mont_input_n <= reg_constant(31 downto 16);
mont_input_s <= reg_constant(15 downto 0);
if (m_val = '1') then
valid_mont <= '1';
next_state <= mont_proc;
mont_input_a <= reg_input_5(47 downto 32);
mont_input_n <= reg_input_5(31 downto 16);
mont_input_s <= reg_input_5(15 downto 0);
end if;
when mont_proc =>
valid_mont <= '1';
mont_input_a <= reg_input_5(47 downto 32);
mont_input_n <= reg_input_5(31 downto 16);
mont_input_s <= reg_input_5(15 downto 0);
if(valid_mont_out = '1') then
next_counter <= x"00";
next_state <= getting_results;
end if;
when getting_results =>
valid_out <= '1';
next_counter <= counter+1;
valid_mont <= '1';
mont_input_a <= reg_input_5(47 downto 32);
mont_input_n <= reg_input_5(31 downto 16);
mont_input_s <= reg_input_5(15 downto 0);
if(counter = (x"22")) then
next_state <= wait_valid;
c_step <= '1';
reset_pe <= '1';
end if;
end case;
if(stop = '1') then
next_state <= wait_valid;
--reset_fifo <= '1';
reset_pe <= '1';
end if;
end process;
end Behavioral;
| bsd-3-clause | 3ae715e3c3fb853d5d565b1b0772d4e0 | 0.510427 | 3.388661 | false | false | false | false |
cbakalis/vmm_boards_firmware | miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/EPROC_OUT4.vhd | 1 | 5,436 | ----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 18/03/2015
--! Module Name: EPROC_OUT4
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee,work;
use ieee.std_logic_1164.all;
use work.all;
--! E-link processor, 4bit output
entity EPROC_OUT4 is
generic (
do_generate : boolean := true;
includeNoEncodingCase : boolean := true
);
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
ENA : in std_logic;
getDataTrig : out std_logic; -- @ bitCLKx4
ENCODING : in std_logic_vector (3 downto 0);
EDATA_OUT : out std_logic_vector (3 downto 0);
TTCin : in std_logic_vector (4 downto 0);
DATA_IN : in std_logic_vector (9 downto 0);
DATA_RDY : in std_logic
);
end EPROC_OUT4;
architecture Behavioral of EPROC_OUT4 is
constant zeros4bit : std_logic_vector (3 downto 0) := (others=>'0');
signal EdataOUT_ENC8b10b_case, EdataOUT_direct_case, EdataOUT_HDLC_case, EdataOUT_TTC1_case, EdataOUT_TTC2_case : std_logic_vector (3 downto 0);
signal rst_s, rst_case000, rst_case001, rst_case010, rst_case011 : std_logic;
signal getDataTrig_ENC8b10b_case, getDataTrig_direct_case, getDataTrig_HDLC_case, getDataTrig_TTC_cases : std_logic;
begin
gen_enabled: if do_generate = true generate
rst_s <= rst or (not ENA);
-------------------------------------------------------------------------------------------
-- case 0: direct data, no delimeter...
-------------------------------------------------------------------------------------------
direct_data_enabled: if includeNoEncodingCase = true generate
rst_case000 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "000")) else '1';
direct_case: entity work.EPROC_OUT4_direct
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case000,
getDataTrig => getDataTrig_direct_case,
edataIN => DATA_IN,
edataINrdy => DATA_RDY,
EdataOUT => EdataOUT_direct_case
);
end generate direct_data_enabled;
--
direct_data_disabled: if includeNoEncodingCase = false generate
EdataOUT_direct_case <= (others=>'0');
end generate direct_data_disabled;
--
-------------------------------------------------------------------------------------------
-- case 1: DEC8b10b
-------------------------------------------------------------------------------------------
rst_case001 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "001")) else '1';
--
ENC8b10b_case: entity work.EPROC_OUT4_ENC8b10b
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case001,
getDataTrig => getDataTrig_ENC8b10b_case,
edataIN => DATA_IN,
edataINrdy => DATA_RDY,
EdataOUT => EdataOUT_ENC8b10b_case
);
--
-------------------------------------------------------------------------------------------
-- case 2: HDLC
-------------------------------------------------------------------------------------------
rst_case010 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "010")) else '1';
--
getDataTrig_HDLC_case <= '0'; --'1' when (ENCODING(2 downto 0) = "010") else '0';
EdataOUT_HDLC_case <= (others=>'0'); --<---TBD
--
-------------------------------------------------------------------------------------------
-- case 3&4: TTC-1 & TTC-2
-------------------------------------------------------------------------------------------
rst_case011 <= '0' when ((rst_s = '0') and ((ENCODING(2 downto 0) = "011") or (ENCODING(2 downto 0) = "100"))) else '1';
--
getDataTrig_TTC_cases <= '0'; --'1' when ((ENCODING(2 downto 0) = "011") or (ENCODING(2 downto 0) = "100")) else '0';
--
ttc_r: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if rst_case011 = '1' then
EdataOUT_TTC1_case <= zeros4bit;
EdataOUT_TTC2_case <= zeros4bit;
else
EdataOUT_TTC1_case <= TTCin(1) & TTCin(3 downto 2) & TTCin(0);
EdataOUT_TTC2_case <= TTCin(4 downto 2) & TTCin(0);
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- output data and busy according to the encoding settings
-------------------------------------------------------------------------------------------
dataOUTmux: entity work.MUX8_Nbit
generic map (N=>4)
port map(
data0 => EdataOUT_direct_case,
data1 => EdataOUT_ENC8b10b_case,
data2 => EdataOUT_HDLC_case,
data3 => EdataOUT_TTC1_case,
data4 => EdataOUT_TTC2_case,
data5 => zeros4bit,
data6 => zeros4bit,
data7 => zeros4bit,
sel => ENCODING(2 downto 0),
data_out => EDATA_OUT
);
--
getDataTrig <= ENA and (getDataTrig_TTC_cases or getDataTrig_HDLC_case or getDataTrig_ENC8b10b_case or getDataTrig_direct_case);
--
end generate gen_enabled;
--
--
gen_disabled: if do_generate = false generate
EDATA_OUT <= (others=>'0');
getDataTrig <= '0';
end generate gen_disabled;
end Behavioral;
| gpl-3.0 | fccfe27423824bca2d25a2cb25c4c8e9 | 0.481972 | 3.801399 | false | false | false | false |
djmatt/VHDL-Lib | VHDL/Scrambler/scrambler.vhd | 1 | 3,594 | ----------------------------------------------------------------------------------------------------
-- Data Scrambler
----------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
----------------------------------------------------------------------------------------------------
-- PACKAGE
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package scrambler_pkg is
component scrambler is
port( clk : in std_logic;
rst : in std_logic;
poly_mask : in std_logic_vector;
seed : in std_logic_vector;
unscrambled_datain : in std_logic_vector;
scrambled_dataout : out std_logic_vector);
end component;
end package;
----------------------------------------------------------------------------------------------------
-- ENTITY
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.lfsr_pkg.all;
--This entity uses an LFSR to scramble the data. When using a descrambler, ensure the same
--polynomial is used.
entity scrambler is
port( --Process clock. Every clock cycle unscrambled data in is processed through the
--scrambler producing scrambled data out.
clk : in std_logic;
--Asynchronous reset. While high: resets the LFSR to the seed value and sets the
--poly_mask used for the feedback polynomial
rst : in std_logic;
--Place '1's in the bits where the polynomial calls for taps. Read up on LFSR's before
--selecting a polynomial, not all choices will yield "good" random numbers.
--(e.g. X^5 + X^3 + 1 would be poly_mask(4 downto 0) <= "10100";)
poly_mask : in std_logic_vector;
--Must be identical in length to poly_mask. Initial value of the shift register. Is
--only set during rst = '1'. DO NOT SET TO ALL '0's
seed : in std_logic_vector;
--Data to be scrambled
unscrambled_datain : in std_logic_vector;
--Scrambled data
scrambled_dataout : out std_logic_vector);
end scrambler;
----------------------------------------------------------------------------------------------------
-- ARCHITECTURE
----------------------------------------------------------------------------------------------------
architecture behave of scrambler is
signal feedback_to_lfsr : std_logic_vector(unscrambled_datain'range);
signal feedback_from_lfsr : std_logic_vector(unscrambled_datain'range);
begin
--Use this lfsr to generate random patterns to scramble the data with
scrambling_lfsr : entity work.lfsr(structural)
port map( clk => clk,
rst => rst,
poly_mask => poly_mask,
seed => seed,
feedin => feedback_to_lfsr,
feedout => feedback_from_lfsr);
--Scramble the data by xor'ing the data with feedback from the LFSR
feedback_to_lfsr <= feedback_from_lfsr xor unscrambled_datain;
--Feedback to the LFSR is the scrambled data.
scrambled_dataout <= feedback_to_lfsr;
end behave;
| mit | 1c40ae6dc8af8ce079338754ffe187b0 | 0.448804 | 5.364179 | false | false | false | false |
GustaMagik/RSA_Security_Token | VHDL_code/ver_B/RSA_Security_Token_USB_Version/rsa_512/trunk/rtl/pe.vhd | 1 | 5,123 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:36:31 10/27/2009
-- Design Name:
-- Module Name: PE - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity pe is
port ( clk : in std_logic;
reset : in std_logic;
a_j : in std_logic_vector(15 downto 0);
b_i : in std_logic_vector(15 downto 0);
s_prev : in std_logic_vector(15 downto 0); --entrada de la s anterior para la suma
m : in std_logic_vector(15 downto 0);
n_j : in std_logic_vector(15 downto 0);
s_next : out std_logic_vector(15 downto 0); --salida con la siguiente s
aj_bi : out std_logic_vector(15 downto 0); --salida de multiplicador reutilizado para calcular a*b
ab_valid_in : in std_logic; --indica que los datos de entrada en el multiplicador son validos
valid_in : in std_logic; --todas las entradas son validas, y la m está calculada
ab_valid_out : out std_logic; --indica que la multiplicacion de un a y b validos se ha realizado con exito
valid_out : out std_logic;
fifo_req : out std_logic); --peticion de las siguientes entradas a, b, s, m
end pe;
architecture Behavioral of pe is
signal prod_aj_bi, next_prod_aj_bi, mult_aj_bi : std_logic_vector(31 downto 0); -- registros para la primera mult
signal prod_nj_m, next_prod_nj_m, mult_nj_m, mult_nj_m_reg : std_logic_vector(31 downto 0);
signal sum_1, next_sum_1 : std_logic_vector(31 downto 0);
signal sum_2, next_sum_2 : std_logic_vector(31 downto 0);
signal ab_valid_reg, valid_out_reg, valid_out_reg2, valid_out_reg3 : std_logic;
signal n_reg, next_n_reg, s_prev_reg, next_s_prev_reg, ab_out_reg : std_logic_vector(15 downto 0);
--signal prod_aj_bi_out, next_prod_aj_bi_out : std_logic_vector(15 downto 0);
begin
mult_aj_bi <= a_j * b_i;
mult_nj_m <= n_reg *m;
process(clk, reset)
begin
if(clk = '1' and clk'event)
then
if(reset = '1') then
prod_aj_bi <= (others => '0');
prod_nj_m <= (others => '0');
sum_1 <= (others => '0');
sum_2 <= (others => '0');
ab_valid_reg <= '0';
n_reg <= (others => '0');
valid_out_reg <= '0';
valid_out_reg2 <= '0';
valid_out_reg3 <= '0';
s_prev_reg <= (others => '0');
else
--prod_aj_bi_out <= next_prod_aj_bi_out;
prod_aj_bi <= next_prod_aj_bi;
prod_nj_m <= next_prod_nj_m;
sum_1 <= next_sum_1;
sum_2 <= next_sum_2;
ab_valid_reg <= ab_valid_in;
ab_out_reg <= mult_aj_bi(15 downto 0);
n_reg <= next_n_reg;
valid_out_reg <= valid_in; --registramos el valid out para sacarle al tiempo de los datos validos
valid_out_reg2 <= valid_out_reg;
valid_out_reg3 <= valid_out_reg2;
s_prev_reg <= next_s_prev_reg;
--mult_nj_m_reg <= mult_nj_m;
end if;
end if;
end process;
process(s_prev, prod_aj_bi, prod_nj_m, sum_1, sum_2, mult_aj_bi, mult_nj_m, valid_in, ab_valid_reg, n_j, n_reg, valid_out_reg3, s_prev_reg, ab_out_reg)
begin
ab_valid_out <= ab_valid_reg;
aj_bi <= ab_out_reg(15 downto 0); --Sacamos uno de los dos registros de la multiplicacion fuera para el calculo de la constante
s_next <= sum_2(15 downto 0); --salida de la pipe
fifo_req <= valid_in;
valid_out <= valid_out_reg3;
next_sum_1 <= sum_1;
next_sum_2 <= sum_2;
next_prod_nj_m <= prod_nj_m;
next_prod_aj_bi <= prod_aj_bi;
next_n_reg <= n_reg;
next_s_prev_reg <= s_prev_reg;
if(valid_in = '1') then
next_s_prev_reg <= s_prev;
next_n_reg <= n_j;
next_prod_aj_bi <= mult_aj_bi;
next_prod_nj_m <= mult_nj_m; --registramos la multiplicacion de n_j,m
next_sum_1 <= prod_aj_bi+sum_1(31 downto 16)+s_prev_reg;
next_sum_2 <= prod_nj_m+sum_2(31 downto 16) + sum_1(15 downto 0);
else
next_s_prev_reg <= (others => '0');
next_n_reg <= (others => '0');
next_prod_aj_bi <= (others => '0');
next_prod_nj_m <= (others => '0');
next_sum_1 <= (others => '0');
next_sum_2 <= (others => '0');
end if;
end process;
end Behavioral;
| bsd-3-clause | 018d1fd3c54006d303875cb0a497df4d | 0.524693 | 3.12378 | false | false | false | false |
GustaMagik/RSA_Security_Token | VHDL_code/ver_A/RSA_Security_Token_Keyboard_Version/RSA_Controller.vhd | 1 | 7,150 |
--Copyright 2017 Christoffer Mathiesen, Gustav Örtenberg
--Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
--
--1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
--
--2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the
--documentation and/or other materials provided with the distribution.
--
--3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this
--software without specific prior written permission.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS
--BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
--GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
--LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.NUMERIC_STD.ALL;
----------------------------RSA_Top_Module-----------------------------
--
-----------------------------------------------------------------------
Entity RSA_Controller is
Generic( i : integer;
Mem_addr_width : integer;
e_val : STD_LOGIC_VECTOR;
N_val : STD_LOGIC_VECTOR);--length of crypto in bits
Port(clk : in STD_LOGIC;
resetN : in STD_LOGIC;
done : out STD_LOGIC;
mem_we : out STD_LOGIC;
input_addr: in STD_LOGIC_VECTOR (mem_addr_width downto 0);
mem_addr : out STD_LOGIC_VECTOR(mem_addr_width downto 0) := (others => '0');
mem_data : in STD_LOGIC_VECTOR(7 downto 0);
data_out : out STD_LOGIC_VECTOR(7 downto 0)
);
end RSA_Controller;
architecture Behavioral of RSA_Controller is
function CounterSize (X : integer)
return integer is
variable POWER : integer := 1;
variable RET : integer := 0;
begin
while (POWER < X) loop
POWER := POWER * 2;
RET := RET + 1;
end loop;
return RET;
end CounterSize;
type CMD is (GET_MSG, CTxCT, CTxMSG, WRITE_ENCRYPTED, COMPLETE);
signal state : CMD := COMPLETE;
signal mult_operator1, mult_operator2, ct, res, msg : STD_LOGIC_VECTOR( i-1 downto 0);
signal do_mult, reset, mult_done, first, second, third : STD_LOGIC;
signal mem_addr_saved : unsigned(5 downto 0) := (others => '0');
signal counter : unsigned (4 downto 0) := (others => '0');
signal itteration : unsigned (CounterSize(i)-1 downto 0) := (others => '0');
constant e : STD_LOGIC_VECTOR(i-1 downto 0) := e_val;
constant i_byte : integer := i/8;
signal resetN_s : STD_LOGIC;
component modmult is
Generic (MPWID : integer := i);
Port ( mpand : in std_logic_vector(MPWID-1 downto 0);
mplier : in std_logic_vector(MPWID-1 downto 0);
modulus : in std_logic_vector(MPWID-1 downto 0);
product : out std_logic_vector(MPWID-1 downto 0);
clk : in std_logic;
ds : in std_logic;
reset : in std_logic;
ready : out std_logic);
end component;
begin
Mod_Multiplier: modmult Port map (
clk => clk,
mpand => mult_operator1,
mplier => mult_operator2,
modulus => N_val,
product => res,
ds => do_mult,
reset => resetN_s,
ready => mult_done
);
resetN_s <= NOT resetN;
rsa:process(clk)
begin
if(rising_edge(clk)) then
if(resetN = '0') then
--Reset all the operators to initial values
mult_operator1 <= (others => '0');
mult_operator2 <= (others => '0');
ct <= (others => '0');
ct(0) <= '1';
counter <= (others => '0');
itteration <= (others => '0');
msg <= (others => '0');
--Reset all flags to inital value
do_mult <= '0';
done <= '0';
mem_we <= '0';
first <= '0';
second <= '0';
third <= '0';
state <= GET_MSG;
--reset memory_pointers
mem_addr_saved <= unsigned(input_addr);
mem_addr <= (others => '0');
else
case state is
when GET_MSG =>
reset <= '0';
counter <= counter + 1;
mem_addr <= STD_LOGIC_VECTOR(mem_addr_saved + counter + 1);
if counter > 0 then
msg((to_integer(counter*8 - 1)) downto (to_integer(counter*8 - 8))) <= mem_data;
if(counter = i_byte) then
state <= CTxCT;
itteration <= (others => '1');
counter <= (others => '0');
mem_addr <= STD_LOGIC_VECTOR(mem_addr_saved);
end if;
end if;
when CTxCT =>
if first = '0' then
do_mult <= '1';
first <= '1';
itteration <= itteration + 1;
else
do_mult <= '0';
second <= '1';
end if;
if first = '0' then
mult_operator1 <= ct;
mult_operator2 <= ct;
--reset <= '0';
elsif mult_done = '1' and second = '1' and third = '1' then
first <= '0';
do_mult <= '0';
second <= '0';
third <= '0';
ct <= res;
--e <= e srl 1;
if e(to_integer(i-1-itteration)) = '0' then
state <= CTxCT;
if itteration = i-1 then
state <= WRITE_ENCRYPTED;
end if;
else
state <= CTxMSG;
end if;
elsif mult_done = '1' and second = '1' and third = '0' then
third <= '1';
do_mult <= '0';
end if;
when CTxMSG =>
if first = '0' then
do_mult <= '1';
first <= '1';
else
second <= '1';
do_mult <= '0';
end if;
if first = '0' then
mult_operator1 <= ct;
mult_operator2 <= msg;
--reset <= '0';
elsif mult_done = '1' and second = '1' and third = '1' then
first <= '0';
second <= '0';
third <= '0';
counter <= (others => '0');
do_mult <= '0';
ct <= res;
if itteration = i-1 then
state <= WRITE_ENCRYPTED;
counter <= (others => '0');
else
state <= CTxCT;
end if;
elsif mult_done = '1' and second = '1' and third = '0' then
third <= '1';
do_mult <= '0';
end if;
when WRITE_ENCRYPTED =>
if first = '0' then
ct <= res;
first <= '1';
mem_we <= '1';
else
counter <= counter + 1;
data_out <= ct(to_integer(counter)*8 + 7 downto to_integer(counter)*8);
mem_addr <= STD_LOGIC_VECTOR(mem_addr_saved + counter + 1);
if(counter = i_byte-1) then
state <= COMPLETE;
end if;
end if;
when others =>
done <= '1';
mem_we <= '0';
end case;
end if;
end if;
end process;
end Behavioral;
| bsd-3-clause | 61c402e94144d5ea69e07a3947ffe6d3 | 0.580979 | 3.281322 | false | false | false | false |
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