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AfterRace/SoC_Project | vivado/project/project.srcs/sources_1/bd/week1/ip/week1_zed_audio_0_0/synth/week1_zed_audio_0_0.vhd | 1 | 4,933 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:zed_audio:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY week1_zed_audio_0_0 IS
PORT (
clk_100 : IN STD_LOGIC;
AC_ADR0 : OUT STD_LOGIC;
AC_ADR1 : OUT STD_LOGIC;
AC_GPIO0 : OUT STD_LOGIC;
AC_GPIO1 : IN STD_LOGIC;
AC_GPIO2 : IN STD_LOGIC;
AC_GPIO3 : IN STD_LOGIC;
hphone_l : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
hphone_l_valid : IN STD_LOGIC;
hphone_r : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
hphone_r_valid_dummy : IN STD_LOGIC;
line_in_l : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
line_in_r : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
new_sample : OUT STD_LOGIC;
sample_clk_48k : OUT STD_LOGIC;
AC_MCLK : OUT STD_LOGIC;
AC_SCK : OUT STD_LOGIC;
AC_SDA : INOUT STD_LOGIC
);
END week1_zed_audio_0_0;
ARCHITECTURE week1_zed_audio_0_0_arch OF week1_zed_audio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF week1_zed_audio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT audio_top IS
PORT (
clk_100 : IN STD_LOGIC;
AC_ADR0 : OUT STD_LOGIC;
AC_ADR1 : OUT STD_LOGIC;
AC_GPIO0 : OUT STD_LOGIC;
AC_GPIO1 : IN STD_LOGIC;
AC_GPIO2 : IN STD_LOGIC;
AC_GPIO3 : IN STD_LOGIC;
hphone_l : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
hphone_l_valid : IN STD_LOGIC;
hphone_r : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
hphone_r_valid_dummy : IN STD_LOGIC;
line_in_l : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
line_in_r : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
new_sample : OUT STD_LOGIC;
sample_clk_48k : OUT STD_LOGIC;
AC_MCLK : OUT STD_LOGIC;
AC_SCK : OUT STD_LOGIC;
AC_SDA : INOUT STD_LOGIC
);
END COMPONENT audio_top;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF week1_zed_audio_0_0_arch: ARCHITECTURE IS "audio_top,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF week1_zed_audio_0_0_arch : ARCHITECTURE IS "week1_zed_audio_0_0,audio_top,{}";
BEGIN
U0 : audio_top
PORT MAP (
clk_100 => clk_100,
AC_ADR0 => AC_ADR0,
AC_ADR1 => AC_ADR1,
AC_GPIO0 => AC_GPIO0,
AC_GPIO1 => AC_GPIO1,
AC_GPIO2 => AC_GPIO2,
AC_GPIO3 => AC_GPIO3,
hphone_l => hphone_l,
hphone_l_valid => hphone_l_valid,
hphone_r => hphone_r,
hphone_r_valid_dummy => hphone_r_valid_dummy,
line_in_l => line_in_l,
line_in_r => line_in_r,
new_sample => new_sample,
sample_clk_48k => sample_clk_48k,
AC_MCLK => AC_MCLK,
AC_SCK => AC_SCK,
AC_SDA => AC_SDA
);
END week1_zed_audio_0_0_arch;
| lgpl-3.0 | 560c0058574b2835fe57ae2f033a17c6 | 0.684776 | 3.488685 | false | false | false | false |
rpereira-dev/ENSIIE | UE/S3/microarchi/bus_ia/wrapper_ss.vhd | 1 | 7,914 | -------------------------------------------------------------------------------
--
-- Ce bloc est le wrapper dans le bus ia
--
-- Ce module transfert tous les messages (????,addrsrc,addrdest,data) venant de
-- busin.
--
-- data est stocké dans un registre
--
-- Si addrdest==MYADDR, data est transmis sur busv
-- Sinon, tout le message est transféré sur busout
--
-- Du coté busin, il suit le protocole "poignée de main" (signaux: busin,
-- busin_valid, busin_eated).
--
-- Du coté busout, il suit le protocole "poignée de main" (signaux: busout,
-- busout_valid, busout_eated).
--
-- Du coté busSS, la configuration du 7-segment programmable est envoyé
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY wrapper_ss IS
GENERIC(
MYADDR : STD_LOGIC_VECTOR(7 downto 0) := "00001011" -- 11
);
PORT(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
-- interface busin
busin : in STD_LOGIC_VECTOR(43 downto 0);
busin_valid : in STD_LOGIC;
busin_eated : out STD_LOGIC;
-- interface busout
busout : out STD_LOGIC_VECTOR(43 downto 0);
busout_valid : out STD_LOGIC;
busout_eated : in STD_LOGIC;
-- les 32 valeurs du 7 segments R_SSurées (7 * 32 = 224) + N sur 6 bits
busSS : out STD_LOGIC_VECTOR(229 downto 0)
);
END wrapper_ss;
ARCHITECTURE montage OF wrapper_ss IS
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
-- Registre de transfert entre busin et busout
type T_CMD_tft is (INIT, NOOP);
signal CMD_tft : T_CMD_tft ;
signal R_tft : STD_LOGIC_VECTOR (43 downto 0);
type T_CMD_msg is (LOAD, NOOP);
signal CMD_msg : T_CMD_msg ;
-- registre stockant les 32 valeurs du 7 segments R_SSurées (7 * 32 = 224)
signal R_SS : STD_LOGIC_VECTOR(229 downto 0);
-------------------------------------------------------------------------------
-- Partie Contrôle
-------------------------------------------------------------------------------
-- adresse destination
alias busin_addrdest : STD_LOGIC_VECTOR(7 downto 0) is busin(31 downto 24);
type STATE_TYPE is (
ST_READ_BUSIN, ST_WRITE_OUT, ST_LOAD_MSG
);
signal state : STATE_TYPE;
BEGIN
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
PROCESS (reset, clk)
BEGIN
-- si on reset
IF reset = '1' THEN
-- R_SSure le serpentin pour qu'il soit vide
R_SS <= (5 => '1', others => '0');
ELSIF clk'event AND clk = '1' THEN
-- commandes de transfert bus ia
-- si l'on doit lire le message, on le stocke
-- dans le registre 'R_tft'
IF CMD_tft = INIT THEN
R_tft <= busin ;
END IF;
IF CMD_msg = LOAD THEN
-- switch l'id du message
CASE R_tft(23 downto 22) IS
-- clr(s)
WHEN "00" =>
R_SS <= (5 => '1', others => '0');
-- si commande set-N(n)
WHEN "01" =>
R_SS(229 downto 224) <= R_tft(5 downto 0);
-- si commande set-val(i, v)
WHEN "10" =>
-- switch l'id de la frame
CASE unsigned(R_tft(5 downto 0)) IS
WHEN to_unsigned(1, 6) =>
R_SS( 6 downto 0) <= R_tft(12 downto 6);
WHEN to_unsigned(2, 6) =>
R_SS( 13 downto 7) <= R_tft(12 downto 6);
WHEN to_unsigned(3, 6) =>
R_SS( 20 downto 14) <= R_tft(12 downto 6);
WHEN to_unsigned(4, 6) =>
R_SS( 27 downto 21) <= R_tft(12 downto 6);
WHEN to_unsigned(5, 6) =>
R_SS( 34 downto 28) <= R_tft(12 downto 6);
WHEN to_unsigned(6, 6) =>
R_SS( 41 downto 35) <= R_tft(12 downto 6);
WHEN to_unsigned(7, 6) =>
R_SS( 48 downto 42) <= R_tft(12 downto 6);
WHEN to_unsigned(8, 6) =>
R_SS( 55 downto 49) <= R_tft(12 downto 6);
WHEN to_unsigned(9, 6) =>
R_SS( 62 downto 56) <= R_tft(12 downto 6);
WHEN to_unsigned(10, 6) =>
R_SS( 69 downto 63) <= R_tft(12 downto 6);
WHEN to_unsigned(11, 6) =>
R_SS( 76 downto 70) <= R_tft(12 downto 6);
WHEN to_unsigned(12, 6) =>
R_SS( 83 downto 77) <= R_tft(12 downto 6);
WHEN to_unsigned(13, 6) =>
R_SS( 90 downto 84) <= R_tft(12 downto 6);
WHEN to_unsigned(14, 6) =>
R_SS( 97 downto 91) <= R_tft(12 downto 6);
WHEN to_unsigned(15, 6) =>
R_SS( 104 downto 98) <= R_tft(12 downto 6);
WHEN to_unsigned(16, 6) =>
R_SS( 111 downto 105) <= R_tft(12 downto 6);
WHEN to_unsigned(17, 6) =>
R_SS( 118 downto 112) <= R_tft(12 downto 6);
WHEN to_unsigned(18, 6) =>
R_SS( 125 downto 119) <= R_tft(12 downto 6);
WHEN to_unsigned(19, 6) =>
R_SS( 132 downto 126) <= R_tft(12 downto 6);
WHEN to_unsigned(20, 6) =>
R_SS( 139 downto 133) <= R_tft(12 downto 6);
WHEN to_unsigned(21, 6) =>
R_SS( 146 downto 140) <= R_tft(12 downto 6);
WHEN to_unsigned(22, 6) =>
R_SS( 153 downto 147) <= R_tft(12 downto 6);
WHEN to_unsigned(23, 6) =>
R_SS( 160 downto 154) <= R_tft(12 downto 6);
WHEN to_unsigned(24, 6) =>
R_SS( 167 downto 161) <= R_tft(12 downto 6);
WHEN to_unsigned(25, 6) =>
R_SS( 174 downto 168) <= R_tft(12 downto 6);
WHEN to_unsigned(26, 6) =>
R_SS( 181 downto 175) <= R_tft(12 downto 6);
WHEN to_unsigned(27, 6) =>
R_SS( 188 downto 182) <= R_tft(12 downto 6);
WHEN to_unsigned(28, 6) =>
R_SS( 195 downto 189) <= R_tft(12 downto 6);
WHEN to_unsigned(29, 6) =>
R_SS( 202 downto 196) <= R_tft(12 downto 6);
WHEN to_unsigned(30, 6) =>
R_SS( 209 downto 203) <= R_tft(12 downto 6);
WHEN to_unsigned(31, 6) =>
R_SS( 216 downto 210) <= R_tft(12 downto 6);
WHEN to_unsigned(32, 6) =>
R_SS( 223 downto 217) <= R_tft(12 downto 6);
WHEN others =>
-- ne rien faire (erreur utilisateur)
-- TODO : envoyer un signal d'erreur
END CASE;
WHEN "11" =>
-- ne rien faire, la commande d'id 2 d'existe pas => erreur utilisateur
END CASE;
END IF ;
END IF;
END PROCESS;
-- sortie
busSS <= R_SS;
busout <= R_tft;
-------------------------------------------------------------------------------
-- Partie Contrôle
-------------------------------------------------------------------------------
-- Inputs: busin_valid, busout_eated, busin_addrdest
-- Outputs: busin_eated, busout_valid, CMD_tft
-------------------------------------------------------------------------------
-- fonction de transitition
PROCESS (reset,clk)
BEGIN
IF reset = '1' THEN
state <= ST_READ_BUSIN;
ELSIF clk'event AND clk = '1' THEN
CASE state IS
WHEN ST_READ_BUSIN =>
IF busin_valid='1' THEN
IF busin_addrdest = MYADDR THEN
state <= ST_LOAD_MSG ;
ELSE
state <= ST_WRITE_OUT ;
END IF ;
END IF ;
WHEN ST_WRITE_OUT =>
IF busout_eated = '1' THEN
state <= ST_READ_BUSIN;
END IF ;
WHEN ST_LOAD_MSG =>
state <= ST_READ_BUSIN;
END CASE;
END IF;
END PROCESS;
-- fonction de sortie
with state select busin_eated <=
'1' when ST_READ_BUSIN,
'0' when others;
with state select busout_valid <=
'1' when ST_WRITE_OUT,
'0' when others
;
with state select CMD_tft <=
INIT when ST_READ_BUSIN,
NOOP when others
;
with state select CMD_msg <=
LOAD when ST_LOAD_MSG,
NOOP when others
;
end montage;
| gpl-3.0 | 7241a220fa4a3e1ec05795f3f829a7d4 | 0.492721 | 3.239951 | false | false | false | false |
boztalay/OldProjects | FPGA/testytest/ipcore_dir/FIFO.vhd | 1 | 5,657 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file FIFO.vhd when simulating
-- the core, FIFO. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY FIFO IS
port (
din: IN std_logic_VECTOR(15 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(15 downto 0);
empty: OUT std_logic;
full: OUT std_logic);
END FIFO;
ARCHITECTURE FIFO_a OF FIFO IS
-- synthesis translate_off
component wrapped_FIFO
port (
din: IN std_logic_VECTOR(15 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(15 downto 0);
empty: OUT std_logic;
full: OUT std_logic);
end component;
-- Configuration specification
for all : wrapped_FIFO use entity XilinxCoreLib.fifo_generator_v5_1(behavioral)
generic map(
c_has_int_clk => 0,
c_rd_freq => 1,
c_wr_response_latency => 1,
c_has_srst => 0,
c_enable_rst_sync => 1,
c_has_rd_data_count => 0,
c_din_width => 16,
c_has_wr_data_count => 0,
c_full_flags_rst_val => 1,
c_implementation_type => 2,
c_family => "spartan3",
c_use_embedded_reg => 0,
c_has_wr_rst => 0,
c_wr_freq => 1,
c_use_dout_rst => 1,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 0,
c_dout_width => 16,
c_msgon_val => 1,
c_rd_depth => 16,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_error_injection_type => 0,
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 4,
c_has_wr_ack => 0,
c_use_ecc => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 4,
c_use_fwft_data_count => 0,
c_has_almost_empty => 0,
c_rd_data_count_width => 4,
c_enable_rlocs => 0,
c_wr_pntr_width => 4,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 4,
c_preload_regs => 1,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 14,
c_wr_depth => 16,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_thresh_assert_val => 4,
c_has_valid => 0,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 15,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "512x36",
c_count_type => 0,
c_prog_full_type => 0,
c_memory_type => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_FIFO
port map (
din => din,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
dout => dout,
empty => empty,
full => full);
-- synthesis translate_on
END FIFO_a;
| mit | 12594964db579585cc201915f70d78cb | 0.54163 | 3.491975 | false | false | false | false |
AfterRace/SoC_Project | vivado/project/project.srcs/sources_1/bd/week1/hdl/week1_wrapper.vhd | 1 | 4,187 | --Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.1 (lin64) Build 1215546 Mon Apr 27 19:07:21 MDT 2015
--Date : Thu May 12 11:41:56 2016
--Host : fx6 running 64-bit openSUSE Leap 42.1 (x86_64)
--Command : generate_target week1_wrapper.bd
--Design : week1_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity week1_wrapper is
port (
AC_ADR0 : out STD_LOGIC;
AC_ADR1 : out STD_LOGIC;
AC_GPIO0 : out STD_LOGIC;
AC_GPIO1 : in STD_LOGIC;
AC_GPIO2 : in STD_LOGIC;
AC_GPIO3 : in STD_LOGIC;
AC_MCLK : out STD_LOGIC;
AC_SCK : out STD_LOGIC;
AC_SDA : inout STD_LOGIC;
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC
);
end week1_wrapper;
architecture STRUCTURE of week1_wrapper is
component week1 is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
AC_ADR0 : out STD_LOGIC;
AC_ADR1 : out STD_LOGIC;
AC_GPIO0 : out STD_LOGIC;
AC_GPIO1 : in STD_LOGIC;
AC_GPIO2 : in STD_LOGIC;
AC_GPIO3 : in STD_LOGIC;
AC_MCLK : out STD_LOGIC;
AC_SCK : out STD_LOGIC;
AC_SDA : inout STD_LOGIC
);
end component week1;
begin
week1_i: component week1
port map (
AC_ADR0 => AC_ADR0,
AC_ADR1 => AC_ADR1,
AC_GPIO0 => AC_GPIO0,
AC_GPIO1 => AC_GPIO1,
AC_GPIO2 => AC_GPIO2,
AC_GPIO3 => AC_GPIO3,
AC_MCLK => AC_MCLK,
AC_SCK => AC_SCK,
AC_SDA => AC_SDA,
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb
);
end STRUCTURE;
| lgpl-3.0 | 50ad96bb11e6c52298c70be06fc0b464 | 0.580607 | 2.975835 | false | false | false | false |
bargei/NoC264 | NoC264_3x3/inverse_transform.vhd | 2 | 4,066 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.math_real.all;
entity inverse_transform is
generic(
in_sample_width : integer := 16;
out_sample_width : integer := 8
);
port(
transform_block : in std_logic_vector((16*in_sample_width)-1 downto 0);
inv_transform_block : out std_logic_vector((16*out_sample_width)-1 downto 0);
sign_mask : out std_logic_vector(15 downto 0)
);
end entity inverse_transform;
architecture initial of inverse_transform is
--- TYPES -----------------------------------------------------------------
type block_type is array(15 downto 0) of integer;
--- SIGNALS ---------------------------------------------------------------
signal input_block : block_type;
signal intermediate_block : block_type;
signal output_block : block_type;
signal inv_block : block_type;
--- CONSTANTS -------------------------------------------------------------
begin
-- parse the input into integers
parse: for i in 15 downto 0 generate
constant lower_index : integer := i * in_sample_width;
constant upper_index : integer := lower_index + in_sample_width - 1;
begin
input_block(i) <= to_integer(signed( transform_block(upper_index downto lower_index) ));
end generate;
--the inverse transform
g0: for i in 3 downto 0 generate
constant col_0_index : integer := i * 4;
constant col_1_index : integer := col_0_index + 1;
constant col_2_index : integer := col_0_index + 2;
constant col_3_index : integer := col_0_index + 3;
constant idx : integer := col_0_index;
constant row_0_index : integer := i;
constant row_1_index : integer := i + 4;
constant row_2_index : integer := i + 8;
constant row_3_index : integer := i + 12;
begin
intermediate_block(col_0_index) <= input_block(idx) + input_block(idx + 1) + input_block(idx + 2) + input_block(idx + 3)/2;
intermediate_block(col_1_index) <= input_block(idx) + input_block(idx + 1)/2 - input_block(idx + 2) - input_block(idx + 3);
intermediate_block(col_2_index) <= input_block(idx) - input_block(idx + 1)/2 - input_block(idx + 2) + input_block(idx + 3);
intermediate_block(col_3_index) <= input_block(idx) - input_block(idx + 1) + input_block(idx + 2) - input_block(idx + 3)/2;
inv_block(row_0_index) <= (intermediate_block(i) + intermediate_block(i+8) + intermediate_block(i+4) + intermediate_block(i+12)/2 + 32)/64;
inv_block(row_1_index) <= (intermediate_block(i) - intermediate_block(i+8) + intermediate_block(i+4)/2 - intermediate_block(i+12) + 32)/64;
inv_block(row_2_index) <= (intermediate_block(i) - intermediate_block(i+8) - intermediate_block(i+4)/2 + intermediate_block(i+12) + 32)/64;
inv_block(row_3_index) <= (intermediate_block(i) + intermediate_block(i+8) - intermediate_block(i+4) - intermediate_block(i+12)/2 + 32)/64;
end generate;
--format the output
output: for i in 15 downto 0 generate
constant lower_index : integer := i * out_sample_width;
constant upper_index : integer := lower_index + out_sample_width - 1;
begin
--output_block(i) <= inv_block(i) when inv_block(i)<(2**(out_sample_width-1)) and inv_block(i)>(-1*(2**(out_sample_width-1))) else
-- (2**(out_sample_width-1)-1) when inv_block(i)>(-1*(2**(out_sample_width-1))) else
-- (-1*(2**(out_sample_width-1)));
output_block(i) <= abs(inv_block(i));
sign_mask(i) <= '1' when inv_block(i) < 0 else '0';
inv_transform_block(upper_index downto lower_index) <= std_logic_vector(to_unsigned(output_block(i), out_sample_width));
end generate;
end architecture initial; | mit | 719da8115053009ae33cf26a4aee34ce | 0.560994 | 3.551092 | false | false | false | false |
DaveyPocket/btrace448 | btrace/raygen.vhd | 1 | 3,716 | -- Btrace 448
-- Ray Generator
--
-- Bradley Boccuzzi
-- 2016
-- !Remove from project
library ieee;
library ieee_proposed;
use ieee.std_logic_1164.all;
use ieee_proposed.fixed_pkg.all;
use ieee.std_logic_unsigned.all;
use work.btrace_pack.all;
entity raygenn is
generic(int, fraction: integer := 16);
port(clk, rst: in std_logic;
set_cam: in std_logic;
inc_x, inc_y: in std_logic;
clr_x, clr_y: in std_logic;
direction: out vector;
origin: out point;
--mv_x, mv_y, mv_z: out std_logic_vector((int+fraction)-1 downto 0);
-- TODO: remove fudge values for below pixel x and y coordinates
p_x, p_y: out std_logic_vector(9 downto 0);
last_x, last_y: out std_logic);
end raygenn;
architecture arch of raygenn is
--- Constant declarations
-- Integers
constant hsize: integer := 9;
constant vsize: integer := 8;
constant hsize_cat: integer := 32;
constant vsize_cat: integer := 32;
-- Other types
constant camera_point: point := (x"00000000", x"00000000", x"FF000000");
constant h_init: std_logic_vector(hsize-1 downto 0) := (others => '0');
constant v_init: std_logic_vector(vsize-1 downto 0) := (others => '0');
-- Signal declarations (do not change these)
signal camera_reg_out: point;
signal houtput: std_logic_vector(hsize-1 downto 0);
signal voutput: std_logic_vector(vsize-1 downto 0);
signal hout_cat: std_logic_vector(hsize_cat-1 downto 0);
signal vout_cat: std_logic_vector(vsize_cat-1 downto 0);
signal vector_x: std_logic_vector(hsize_cat-1 downto 0);
signal vector_y: std_logic_vector(vsize_cat-1 downto 0);
-- TODO fix this
signal vector_z: std_logic_vector(31 downto 0);
signal vvx, vvy: std_logic_vector(31 downto 0);
constant zeros: sfixed(15 downto -16) := (others => '0');
signal sub16: sfixed(16 downto -16) := (others => '0');
begin
--
--- Component instantiation
--
-- Camera coordinate register (input: point_type, output: point_type)
camera_coord: entity work.point_reg port map(clk, rst, set_cam, camera_point, camera_reg_out);
-- Horizontal counter (X) (initializes to zero, output std_logic_vector(hsize-1 downto 0))
hc: entity work.counter generic map(hsize) port map(clk, rst, clr_x, inc_x, '0', h_init, houtput);
-- Vertical counter (Y) (initializes to zero, output std_logic_vector(vsize-1 downto 0))
vc: entity work.counter generic map(vsize) port map(clk, rst, clr_y, inc_y, '0', v_init, voutput);
--- Subtractors
-- Horizontal coordinate subractor ()
subx: entity work.sub generic map(hsize_cat) port map(hout_cat, std_logic_vector(camera_reg_out.x), vector_x);
-- Vertical coordinate subtractor ()
suby: entity work.sub generic map(vsize_cat) port map(vout_cat, std_logic_vector(camera_reg_out.y), vector_y);
subz: entity work.sub generic map(32) port map(x"00000000", std_logic_vector(camera_reg_out.z), vector_z);
--
--- Concurrent statements
--
-- TODO remove fudge values
-- hout_cat (Concatenates 'integer' houtput with zero fractional portion)
hout_cat <= "0000000"&houtput&x"0000";
-- vout_cat (Concatenates 'integer' voutput with zero fractional portion)
vout_cat <= "00000000"&voutput&x"0000";
direction.m_x <= to_sfixed(vector_x, 15, -16);
direction.m_y <= to_sfixed(vector_y, 15, -16);
sub16 <= zeros - camera_point.z;
direction.m_z <= sub16(15 downto -16);
-- Unbounded issue below
--origin.x <= "010100000" - to_ufixed(hout_cat, 15, -16);
--origin.y <= "01111000" - to_ufixed(vout_cat, 15, -16);
origin.x <= to_sfixed(hout_cat, 15, -16);
origin.y <= to_sfixed(vout_cat, 15, -16);
origin.z <= x"00000000";
-- Pixel coordinates
p_x <= '0' & houtput;
p_y <= "00" & voutput;
last_x <= '1' when houtput = "100111111" else '0';
last_y <= '1' when voutput = x"EF" else '0';
end arch;
| gpl-3.0 | 812a5fc68ba69af34487cd25dd8f1407 | 0.687029 | 2.843152 | false | false | false | false |
boztalay/OldProjects | FPGA/LCD_Control/mROM.vhd | 1 | 1,823 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:06:19 10/24/2009
-- Design Name:
-- Module Name: mROM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mROM is
Port ( enable : in STD_LOGIC;
address : in STD_LOGIC_VECTOR (4 downto 0);
data_out : out STD_LOGIC_VECTOR (7 downto 0));
end mROM;
architecture Behavioral of mROM is
begin
mROM: process (address) is
type mROM_array is array (31 downto 0) of
STD_LOGIC_VECTOR (7 downto 0);
variable mROM: mROM_array := (0 => "00111000",
1 => "00001111",
2 => "00000001",
3 => "01001001", --'I'
4 => "01110100", --'t'
5 => "00100000", --' '
6 => "01110111", --'w'
7 => "01101111", --'o'
8 => "01110010", --'r'
9 => "01101011", --'k'
10 => "01110011", --'s'
11 => "00100001", --'!'
12 => "00100000", --' '
13 => "00111010", --':'
14 => "01000100", --'D'
others => "00000000"); --Ready to begin write cycles
begin
data_out <= mROM(conv_integer(unsigned(address)));
end process;
end Behavioral;
| mit | eca380be7492c1833d9a547a79160629 | 0.472847 | 3.821803 | false | false | false | false |
AfterRace/SoC_Project | vivado/project/project.srcs/sources_1/bd/week1/ip/week1_AXI_to_audio_0_0/synth/week1_AXI_to_audio_0_0.vhd | 1 | 8,913 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:AXI_to_audio:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY week1_AXI_to_audio_0_0 IS
PORT (
audio_out_l : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
audio_out_r : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
audio_out_valid : OUT STD_LOGIC;
audio_in_valid_irq : IN STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END week1_AXI_to_audio_0_0;
ARCHITECTURE week1_AXI_to_audio_0_0_arch OF week1_AXI_to_audio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF week1_AXI_to_audio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT AXI_to_audio_v1_0 IS
GENERIC (
C_S00_AXI_DATA_WIDTH : INTEGER; -- Width of S_AXI data bus
C_S00_AXI_ADDR_WIDTH : INTEGER -- Width of S_AXI address bus
);
PORT (
audio_out_l : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
audio_out_r : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
audio_out_valid : OUT STD_LOGIC;
audio_in_valid_irq : IN STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END COMPONENT AXI_to_audio_v1_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF week1_AXI_to_audio_0_0_arch: ARCHITECTURE IS "AXI_to_audio_v1_0,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF week1_AXI_to_audio_0_0_arch : ARCHITECTURE IS "week1_AXI_to_audio_0_0,AXI_to_audio_v1_0,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S00_AXI_RST RST";
BEGIN
U0 : AXI_to_audio_v1_0
GENERIC MAP (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 4
)
PORT MAP (
audio_out_l => audio_out_l,
audio_out_r => audio_out_r,
audio_out_valid => audio_out_valid,
audio_in_valid_irq => audio_in_valid_irq,
s00_axi_awaddr => s00_axi_awaddr,
s00_axi_awprot => s00_axi_awprot,
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => s00_axi_wdata,
s00_axi_wstrb => s00_axi_wstrb,
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => s00_axi_araddr,
s00_axi_arprot => s00_axi_arprot,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn
);
END week1_AXI_to_audio_0_0_arch;
| lgpl-3.0 | a8138abccdfdb8d2d25ef7374ec7de11 | 0.702345 | 3.180942 | false | false | false | false |
boztalay/OldProjects | FPGA/testytest/memory.vhd | 1 | 10,901 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity memory is
Port (
clk80 : in std_logic;
rst : in std_logic;
cam_vs : in STD_LOGIC;
vid_vs : in STD_LOGIC;
empty : out STD_LOGIC;
full : out STD_LOGIC;
CQ_write_en : in STD_LOGIC;
-- CQ_write_clk : in STD_LOGIC;
CQ_data_in : in STD_LOGIC_VECTOR(15 downto 0);
VQ_read_en : in STD_LOGIC;
-- VQ_read_clk : in STD_LOGIC;
VQ_data_out : out STD_LOGIC_VECTOR(15 downto 0);
RAM_addr : out std_logic_vector(22 downto 0);
RAM_data_out : out std_logic_vector(15 downto 0);
RAM_data_in : in std_logic_vector(15 downto 0);
RAM_oe : out std_logic;
RAM_we : out std_logic;
RAM_adv : out std_logic;
RAM_clk_en : out std_logic;
RAM_ub : out std_logic;
RAM_lb : out std_logic;
RAM_ce : out std_logic;
RAM_cre : out std_logic;
RAM_wait : in std_logic;
led : out std_logic_vector(7 downto 0)
);
end memory;
architecture Behavioral of memory is
type state_type is (start, cfgmem, cfgmem_wait, cfgmem_done, cfgReadAry, cfgReadAry_wait, waitstate,
mem_write_init, mem_write_init_wait_high, mem_write_init_wait, mem_write_data,
mem_write_end, mem_read_init, mem_read_init_wait_high, mem_read_init_wait,
mem_read_data, mem_read_end);
signal state, next_state : state_type;
signal RAM_addr_s : std_logic_vector(22 downto 0);
signal RAM_oe_s : std_logic;
signal latency_cnt : integer;
signal data_in_reg : std_logic_vector(15 downto 0);
signal CQ_empty : STD_LOGIC;
signal CQ_read_en : STD_LOGIC;
signal CQ_data_out : STD_LOGIC_VECTOR(15 downto 0);
signal VQ_full : STD_LOGIC;
signal VQ_write_en : STD_LOGIC;
signal VQ_data_in : STD_LOGIC_VECTOR(15 downto 0);
signal write_addr_reg : STD_LOGIC_VECTOR(22 downto 0);
signal write_addr_inc : STD_LOGIC;
signal read_addr_reg : STD_LOGIC_VECTOR(22 downto 0);
signal read_addr_inc : STD_LOGIC;
signal RAM_data_in_reg : STD_LOGIC_VECTOR(15 downto 0);
signal VQ_data_in_reg : STD_LOGIC_VECTOR(15 downto 0);
signal VQ_write_en_reg : STD_LOGIC;
signal CQ_read_en_reg : STD_LOGIC;
----Queue component delcaration
--component FIFO
-- port (
-- din: IN std_logic_VECTOR(15 downto 0);
-- rd_clk: IN std_logic;
-- rd_en: IN std_logic;
-- rst: IN std_logic;
-- wr_clk: IN std_logic;
-- wr_en: IN std_logic;
-- dout: OUT std_logic_VECTOR(15 downto 0);
-- empty: OUT std_logic;
-- full: OUT std_logic);
--end component;
--
---- Synplicity black box declaration
--attribute syn_black_box : boolean;
--attribute syn_black_box of FIFO: component is true;
component fifo is
port(
CLR : in std_logic;
CLK : in std_logic;
RD : in std_logic;
WR : in std_logic;
DATA : in std_logic_vector(15 downto 0);
EMPTY : out std_logic;
FULL : out std_logic;
Q : out std_logic_vector(15 downto 0)
);
end component;
begin
RAM_oe <= RAM_oe_s;
RAM_addr <= RAM_addr_s;
empty <= CQ_empty;
full <= VQ_full;
CQ : fifo
port map (
clr => rst,
clk => clk80,
rd => CQ_read_en,
wr => CQ_write_en,
data => CQ_data_in,
empty => CQ_empty,
q => CQ_data_out);
VQ : fifo
port map (
clr => rst,
clk => clk80,
rd => VQ_read_en,
wr => VQ_write_en,
data => VQ_data_in,
full => VQ_full,
q => VQ_data_out);
----The camera queue
--CQ : FIFO
-- port map (
-- din => CQ_data_in,
-- rd_clk => clk80,
-- rd_en => CQ_read_en_reg,
-- rst => rst,
-- wr_clk => CQ_write_clk,
-- wr_en => CQ_write_en,
-- dout => CQ_data_out,
-- empty => CQ_empty);
--
----The video queue
--VQ : FIFO
-- port map (
-- din => VQ_data_in_reg,
-- rd_clk => VQ_read_clk,
-- rd_en => VQ_read_en,
-- rst => rst,
-- wr_clk => clk80,
-- wr_en => VQ_write_en_reg,
-- dout => VQ_data_out,
-- full => VQ_full);
RAM_control_SM: process(clk80, rst)
begin
if rst='1' then
state <= start;
latency_cnt <= 0;
elsif clk80'event and clk80='1' then
if state /= next_state then
latency_cnt <= 1;
else
latency_cnt <= latency_cnt + 1;
end if;
state <= next_state;
end if;
end process;
RAM_control_NextState: process(state, latency_cnt, RAM_wait)
begin
case state is
--Configuring the memory
when start =>
next_state <= cfgMem;
when cfgmem =>
if latency_cnt < 7 then
next_state <= cfgmem;
else
next_state <= cfgMem_wait;
end if;
when cfgmem_wait =>
--wait is active high (default)
if latency_cnt < 7 then
next_state <= cfgMem_wait;
else
next_state <= cfgmem_done;
end if;
when cfgmem_done =>
if latency_cnt < 4 then
next_state <= cfgmem_done;
else
next_state <= cfgReadAry;
end if;
when cfgReadAry =>
if latency_cnt < 7 then
next_state <= cfgReadAry;
else
next_state <= cfgReadAry_wait;
end if;
when cfgReadAry_wait =>
if latency_cnt < 7 then
next_state <= cfgReadAry_wait;
else
next_state <= waitstate;
end if;
when waitstate =>
if latency_cnt < 7 then
next_state <= waitstate;
else
next_state <= mem_write_init;
end if;
--Initiate a write to memory
when mem_write_init =>
next_state <= mem_write_init_wait_high;
when mem_write_init_wait_high =>
if RAM_wait = '1' then
next_state <= mem_write_init_wait;
else
next_state <= mem_write_init_wait_high;
end if;
when mem_write_init_wait =>
if RAM_wait = '1' then
next_state <= mem_write_init_wait;
else
next_state <= mem_write_data;
end if;
--Write data
when mem_write_data =>
if CQ_empty = '1' then
next_state <= mem_write_end;
else
next_state <= mem_write_data;
end if;
when mem_write_end =>
if latency_cnt <= 2 then
next_state <= mem_write_end;
else
next_state <= mem_read_init;
end if;
--Initiate a read from memory
when mem_read_init =>
next_state <= mem_read_init_wait_high;
when mem_read_init_wait_high =>
if RAM_wait = '1' then
next_state <= mem_read_init_wait;
else
next_state <= mem_read_init_wait_high;
end if;
when mem_read_init_wait =>
if RAM_wait = '1' then
next_state <= mem_read_init_wait;
else
next_state <= mem_read_data;
end if;
--Read data from memory
when mem_read_data =>
if VQ_full = '1' then
next_state <= mem_read_end;
else
next_state <= mem_read_data;
end if;
when mem_read_end =>
if latency_cnt <= 2 then
next_state <= mem_read_end;
else
next_state <= mem_write_init;
end if;
when others => null;
end case;
end process;
RAM_controller: process(state, RAM_data_in, latency_cnt)
begin
RAM_clk_en <= '1';
RAM_oe_s <= '1';
RAM_we <= '1';
RAM_adv <= '1';
RAM_ub <= '0';
RAM_lb <= '0';
RAM_ce <= '1';
RAM_cre <= '0';
RAM_addr_s <= (others => '0');
RAM_data_out <= (others => '0');
CQ_read_en <= '0';
VQ_write_en <= '0';
VQ_data_in <= (others => '0');
write_addr_inc <= '0';
read_addr_inc <= '0';
case state is
--Configure the memory
when start =>
RAM_clk_en <= '0';
when cfgmem =>
RAM_clk_en <= '0';
RAM_addr_s <= "00010000001110100011111";
RAM_cre <= '1';
RAM_adv <= '0';
RAM_ce <= '0';
RAM_we <= '0';
when cfgmem_wait =>
--wait is active high (default)
RAM_clk_en <= '0';
RAM_addr_s <= "00010000001110100011111";
RAM_ce <= '0';
when cfgmem_done =>
RAM_clk_en <= '0';
RAM_ce <= '1';
when cfgReadAry =>
RAM_clk_en <= '0';
RAM_ce <= '0';
RAM_adv <= '0';
RAM_oe_s <= '0';
when cfgReadAry_wait =>
RAM_clk_en <= '0';
RAM_ce <= '0';
RAM_adv <= '0';
RAM_oe_s <= '0';
if latency_cnt >= 3 then
RAM_adv <= '1';
end if;
when waitstate =>
--Initiate a write to memory
when mem_write_init =>
RAM_addr_s <= write_addr_reg;
RAM_ce <= '0';
RAM_adv <= '0';
RAM_we <= '0';
when mem_write_init_wait_high =>
RAM_ce <= '0';
when mem_write_init_wait =>
RAM_ce <= '0';
if RAM_wait = '1' then
CQ_read_en <= '1';
end if;
--Write data
when mem_write_data =>
RAM_ce <= '0';
RAM_data_out <= CQ_data_out;
write_addr_inc <= '1';
if CQ_empty = '0' then
CQ_read_en <= '1';
end if;
when mem_write_end =>
--All taken care of in defaults
--Initiate a read from memory
when mem_read_init =>
RAM_addr_s <= read_addr_reg;
RAM_ce <= '0';
RAM_adv <= '0';
when mem_read_init_wait_high =>
RAM_ce <= '0';
RAM_oe_s <= '0';
when mem_read_init_wait =>
RAM_ce <= '0';
RAM_oe_s <= '0';
--Read data
when mem_read_data =>
RAM_ce <= '0';
if VQ_full = '0' then
VQ_data_in <= RAM_data_in_reg;
VQ_write_en <= '1';
read_addr_inc <= '1';
end if;
when mem_read_end =>
--Taken care of up top in defaults
when others => null;
end case;
end process;
datainreg: process (clk80, rst)
begin
if rst='1' then
RAM_data_in_reg <= (others => '0');
elsif clk80'event and clk80='1' then
RAM_data_in_reg <= RAM_data_in;
end if;
end process;
address_regs: process (clk80, rst, cam_vs, vid_vs)
begin
if rst = '1' then
write_addr_reg <= (others => '0');
read_addr_reg <= (others => '0');
elsif cam_vs = '1' then --syncs high
write_addr_reg <= (others => '0');
elsif vid_vs = '0' then
read_addr_reg <= (others => '0');
elsif falling_edge(clk80) then
if write_addr_inc = '1' then
write_addr_reg <= write_addr_reg + 1;
end if;
if read_addr_inc = '1' then
read_addr_reg <= read_addr_reg + 1;
end if;
end if;
end process;
fifo_regs: process (clk80, rst)
begin
if rst = '1' then
CQ_read_en_reg <= '0';
VQ_write_en_reg <= '0';
VQ_data_in_reg <= (others => '0');
elsif falling_edge(clk80) then
CQ_read_en_reg <= CQ_read_en;
VQ_write_en_reg <= VQ_write_en;
VQ_data_in_reg <= VQ_data_in;
end if;
end process;
end Behavioral;
| mit | 29a0b834364f97f7c7dad68221ff6b88 | 0.532887 | 2.843245 | false | false | false | false |
AfterRace/SoC_Project | vivado/project/project.srcs/sources_1/ipshared/user.org/zed_audio_v1_0/8de2dafc/hdl/adau1761_configuraiton_data.vhd | 2 | 15,645 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]<
--
-- Module Name: adau1761_configuraiton_data - Behavioral
-- Description: A script for the I3C2, which sends out I2c transactions to configure
-- the ADAU1761 codec.
--
-- See i3c2program for original source for script
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity adau1761_configuraiton_data is
Port ( clk : in STD_LOGIC;
address : in STD_LOGIC_VECTOR (9 downto 0);
data : out STD_LOGIC_VECTOR (8 downto 0));
end adau1761_configuraiton_data;
architecture Behavioral of adau1761_configuraiton_data is
begin
process(clk)
begin
if rising_edge(clk) then
case address is
when "0000000000" => data <= "011101111";
when "0000000001" => data <= "101110110";
when "0000000010" => data <= "101000000";
when "0000000011" => data <= "100000000";
when "0000000100" => data <= "100001110";
when "0000000101" => data <= "011111111";
when "0000000110" => data <= "101110110";
when "0000000111" => data <= "101000000";
when "0000001000" => data <= "100000010";
when "0000001001" => data <= "100000000";
when "0000001010" => data <= "101111101";
when "0000001011" => data <= "100000000";
when "0000001100" => data <= "100001100";
when "0000001101" => data <= "100100011";
when "0000001110" => data <= "100000001";
when "0000001111" => data <= "011111111";
when "0000010000" => data <= "011101111";
when "0000010001" => data <= "101110110";
when "0000010010" => data <= "101000000";
when "0000010011" => data <= "100000000";
when "0000010100" => data <= "100001111";
when "0000010101" => data <= "011111111";
when "0000010110" => data <= "011101111";
when "0000010111" => data <= "101110110";
when "0000011000" => data <= "101000000";
when "0000011001" => data <= "100010101";
when "0000011010" => data <= "100000001";
when "0000011011" => data <= "011111111";
when "0000011100" => data <= "101110110";
when "0000011101" => data <= "101000000";
when "0000011110" => data <= "100001010";
when "0000011111" => data <= "100000001";
when "0000100000" => data <= "011111111";
when "0000100001" => data <= "101110110";
when "0000100010" => data <= "101000000";
when "0000100011" => data <= "100001011";
when "0000100100" => data <= "100000101";
when "0000100101" => data <= "011111111";
when "0000100110" => data <= "101110110";
when "0000100111" => data <= "101000000";
when "0000101000" => data <= "100001100";
when "0000101001" => data <= "100000001";
when "0000101010" => data <= "011111111";
when "0000101011" => data <= "101110110";
when "0000101100" => data <= "101000000";
when "0000101101" => data <= "100001101";
when "0000101110" => data <= "100000101";
when "0000101111" => data <= "011111111";
when "0000110000" => data <= "101110110";
when "0000110001" => data <= "101000000";
when "0000110010" => data <= "100011100";
when "0000110011" => data <= "100100001";
when "0000110100" => data <= "011111111";
when "0000110101" => data <= "101110110";
when "0000110110" => data <= "101000000";
when "0000110111" => data <= "100011110";
when "0000111000" => data <= "101000001";
when "0000111001" => data <= "011111111";
when "0000111010" => data <= "101110110";
when "0000111011" => data <= "101000000";
when "0000111100" => data <= "100100011";
when "0000111101" => data <= "111100111";
when "0000111110" => data <= "011111111";
when "0000111111" => data <= "101110110";
when "0001000000" => data <= "101000000";
when "0001000001" => data <= "100100100";
when "0001000010" => data <= "111100111";
when "0001000011" => data <= "011111111";
when "0001000100" => data <= "101110110";
when "0001000101" => data <= "101000000";
when "0001000110" => data <= "100100101";
when "0001000111" => data <= "111100111";
when "0001001000" => data <= "011111111";
when "0001001001" => data <= "101110110";
when "0001001010" => data <= "101000000";
when "0001001011" => data <= "100100110";
when "0001001100" => data <= "111100111";
when "0001001101" => data <= "011111111";
when "0001001110" => data <= "101110110";
when "0001001111" => data <= "101000000";
when "0001010000" => data <= "100011001";
when "0001010001" => data <= "100000011";
when "0001010010" => data <= "011111111";
when "0001010011" => data <= "101110110";
when "0001010100" => data <= "101000000";
when "0001010101" => data <= "100101001";
when "0001010110" => data <= "100000011";
when "0001010111" => data <= "011111111";
when "0001011000" => data <= "101110110";
when "0001011001" => data <= "101000000";
when "0001011010" => data <= "100101010";
when "0001011011" => data <= "100000011";
when "0001011100" => data <= "011111111";
when "0001011101" => data <= "101110110";
when "0001011110" => data <= "101000000";
when "0001011111" => data <= "111110010";
when "0001100000" => data <= "100000001";
when "0001100001" => data <= "011111111";
when "0001100010" => data <= "101110110";
when "0001100011" => data <= "101000000";
when "0001100100" => data <= "111110011";
when "0001100101" => data <= "100000001";
when "0001100110" => data <= "011111111";
when "0001100111" => data <= "101110110";
when "0001101000" => data <= "101000000";
when "0001101001" => data <= "111111001";
when "0001101010" => data <= "101111111";
when "0001101011" => data <= "011111111";
when "0001101100" => data <= "101110110";
when "0001101101" => data <= "101000000";
when "0001101110" => data <= "111111010";
when "0001101111" => data <= "100000011";
when "0001110000" => data <= "011111111";
when "0001110001" => data <= "000010011";
when "0001110010" => data <= "011111110";
when "0001110011" => data <= "011111110";
when "0001110100" => data <= "011111110";
when "0001110101" => data <= "011111110";
when "0001110110" => data <= "011111110";
when "0001110111" => data <= "011111110";
when "0001111000" => data <= "101110110";
when "0001111001" => data <= "101000000";
when "0001111010" => data <= "100011100";
when "0001111011" => data <= "100100000";
when "0001111100" => data <= "011111111";
when "0001111101" => data <= "101110110";
when "0001111110" => data <= "101000000";
when "0001111111" => data <= "100011110";
when "0010000000" => data <= "101000000";
when "0010000001" => data <= "011111111";
when "0010000010" => data <= "011101111";
when "0010000011" => data <= "011101111";
when "0010000100" => data <= "011101111";
when "0010000101" => data <= "011101111";
when "0010000110" => data <= "010100000";
when "0010000111" => data <= "010100001";
when "0010001000" => data <= "011101111";
when "0010001001" => data <= "011101111";
when "0010001010" => data <= "101110110";
when "0010001011" => data <= "101000000";
when "0010001100" => data <= "100011100";
when "0010001101" => data <= "100100001";
when "0010001110" => data <= "011111111";
when "0010001111" => data <= "101110110";
when "0010010000" => data <= "101000000";
when "0010010001" => data <= "100011110";
when "0010010010" => data <= "101000001";
when "0010010011" => data <= "011111111";
when "0010010100" => data <= "011111110";
when "0010010101" => data <= "011111110";
when "0010010110" => data <= "011111110";
when "0010010111" => data <= "011111110";
when "0010011000" => data <= "010000000";
when "0010011001" => data <= "000010100";
when "0010011010" => data <= "010000001";
when "0010011011" => data <= "000011001";
when "0010011100" => data <= "000010011";
when "0010011101" => data <= "011111110";
when "0010011110" => data <= "011111110";
when "0010011111" => data <= "011111110";
when "0010100000" => data <= "101110110";
when "0010100001" => data <= "101000000";
when "0010100010" => data <= "100011100";
when "0010100011" => data <= "100100000";
when "0010100100" => data <= "011111111";
when "0010100101" => data <= "101110110";
when "0010100110" => data <= "101000000";
when "0010100111" => data <= "100011110";
when "0010101000" => data <= "101000000";
when "0010101001" => data <= "011111111";
when "0010101010" => data <= "011101111";
when "0010101011" => data <= "011101111";
when "0010101100" => data <= "011101111";
when "0010101101" => data <= "011101111";
when "0010101110" => data <= "010110000";
when "0010101111" => data <= "010100001";
when "0010110000" => data <= "011101111";
when "0010110001" => data <= "011101111";
when "0010110010" => data <= "101110110";
when "0010110011" => data <= "101000000";
when "0010110100" => data <= "100011100";
when "0010110101" => data <= "100100001";
when "0010110110" => data <= "011111111";
when "0010110111" => data <= "101110110";
when "0010111000" => data <= "101000000";
when "0010111001" => data <= "100011110";
when "0010111010" => data <= "101000001";
when "0010111011" => data <= "011111111";
when "0010111100" => data <= "011111110";
when "0010111101" => data <= "011111110";
when "0010111110" => data <= "011111110";
when "0010111111" => data <= "011111110";
when "0011000000" => data <= "010010000";
when "0011000001" => data <= "000001111";
when "0011000010" => data <= "010000001";
when "0011000011" => data <= "000011110";
when "0011000100" => data <= "000011000";
when "0011000101" => data <= "011111110";
when "0011000110" => data <= "011111110";
when "0011000111" => data <= "011111110";
when "0011001000" => data <= "101110110";
when "0011001001" => data <= "101000000";
when "0011001010" => data <= "100011100";
when "0011001011" => data <= "100100000";
when "0011001100" => data <= "011111111";
when "0011001101" => data <= "101110110";
when "0011001110" => data <= "101000000";
when "0011001111" => data <= "100011110";
when "0011010000" => data <= "101000000";
when "0011010001" => data <= "011111111";
when "0011010010" => data <= "011101111";
when "0011010011" => data <= "011101111";
when "0011010100" => data <= "011101111";
when "0011010101" => data <= "011101111";
when "0011010110" => data <= "010100000";
when "0011010111" => data <= "010110001";
when "0011011000" => data <= "011101111";
when "0011011001" => data <= "011101111";
when "0011011010" => data <= "101110110";
when "0011011011" => data <= "101000000";
when "0011011100" => data <= "100011100";
when "0011011101" => data <= "100100001";
when "0011011110" => data <= "011111111";
when "0011011111" => data <= "101110110";
when "0011100000" => data <= "101000000";
when "0011100001" => data <= "100011110";
when "0011100010" => data <= "101000001";
when "0011100011" => data <= "011111111";
when "0011100100" => data <= "011111110";
when "0011100101" => data <= "011111110";
when "0011100110" => data <= "011111110";
when "0011100111" => data <= "011111110";
when "0011101000" => data <= "010000000";
when "0011101001" => data <= "000000000";
when "0011101010" => data <= "010010001";
when "0011101011" => data <= "000001111";
when "0011101100" => data <= "000011101";
when "0011101101" => data <= "011111110";
when "0011101110" => data <= "011111110";
when "0011101111" => data <= "011111110";
when "0011110000" => data <= "101110110";
when "0011110001" => data <= "101000000";
when "0011110010" => data <= "100011100";
when "0011110011" => data <= "100100000";
when "0011110100" => data <= "011111111";
when "0011110101" => data <= "101110110";
when "0011110110" => data <= "101000000";
when "0011110111" => data <= "100011110";
when "0011111000" => data <= "101000000";
when "0011111001" => data <= "011111111";
when "0011111010" => data <= "011101111";
when "0011111011" => data <= "011101111";
when "0011111100" => data <= "011101111";
when "0011111101" => data <= "011101111";
when "0011111110" => data <= "010110000";
when "0011111111" => data <= "010110001";
when "0100000000" => data <= "011101111";
when "0100000001" => data <= "011101111";
when "0100000010" => data <= "101110110";
when "0100000011" => data <= "101000000";
when "0100000100" => data <= "100011100";
when "0100000101" => data <= "100100001";
when "0100000110" => data <= "011111111";
when "0100000111" => data <= "101110110";
when "0100001000" => data <= "101000000";
when "0100001001" => data <= "100011110";
when "0100001010" => data <= "101000001";
when "0100001011" => data <= "011111111";
when "0100001100" => data <= "011111110";
when "0100001101" => data <= "011111110";
when "0100001110" => data <= "011111110";
when "0100001111" => data <= "011111110";
when "0100010000" => data <= "010010000";
when "0100010001" => data <= "000011001";
when "0100010010" => data <= "010010001";
when "0100010011" => data <= "000010100";
when "0100010100" => data <= "000100010";
when others => data <= (others =>'0');
end case;
end if;
end process;
end Behavioral;
| lgpl-3.0 | 82a66bd290d22cb835734c6504c2944f | 0.511985 | 4.787332 | false | false | false | false |
DaveyPocket/btrace448 | core/dff.vhd | 1 | 499 | -- Btrace 448
-- D-Type Flip-Flop
--
-- Bradley Boccuzzi
-- 2016
-- TODO Make set/reset
library ieee;
use ieee.std_logic_1164.all;
entity dff is
port(D, clk, set, rst, clr: in std_logic;
Q: out std_logic);
end dff;
architecture sequential of dff is
begin
process(clk, set, rst)
begin
if rst = '1' then
Q <= '0';
elsif rising_edge(clk) then
if clr = '1' then
Q <= '0';
elsif set = '1' then
Q <= '1';
else
Q <= D;
end if;
end if;
end process;
end sequential;
| gpl-3.0 | d653bcfb8a75e26cc157b3a8613ad746 | 0.603206 | 2.626316 | false | false | false | false |
peladex/RHD2132_FPGA | src/params_reg_bank/params_reg_bank.vhd | 1 | 6,323 | -----------------------------------------------------------------------------------------------------------------------
-- Author:
--
-- Create Date: 13/11/2016 -- dd/mm/yyyy
-- Module Name: params_reg_bank
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Banco de registros para almacenar los parametros de configuracion de los chips.
-- Las entradas input_* son de 8 bits y permiten modificar el parametro a configurar
-- Las saludas output_* son de 16 bits y representan el comando que se debe enviar al
-- chip para cargar el parametro de confiuracion.
-- El comando a enviar es:
-- WRITE(R,D) Write data D to register R
--
-- MSB LSB
-- | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
-- | 1 | 0 | R[5]| R[4]| R[3]| R[2]| R[1]| R[0]| D[7]| D[6]| D[5]| D[4]| D[3]| D[2]| D[1]| D[0] |
--
--
-----------------------------------------------------------------------------------------------------------------------
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY params_reg_bank IS
PORT(
clk : in std_logic;
rst : in std_logic;
-- chip 1 --
input_chip_1 : in std_logic_vector(7 downto 0);
select_chip_1 : in std_logic_vector(6 downto 0);
output_chip_1 : out std_logic_vector(15 downto 0);
wren_chip_1 : in std_logic;
-- chip 2 --
input_chip_2 : in std_logic_vector(7 downto 0);
select_chip_2 : in std_logic_vector(6 downto 0);
output_chip_2 : out std_logic_vector(15 downto 0);
wren_chip_1 : in std_logic
);
END test_maquina_control;
ARCHITECTURE behav of params_reg_bank IS
-- signals
signal chip_1_reg_00 : std_logic_vector(7 downto 0); --adr: 00
signal chip_1_reg_01 : std_logic_vector(7 downto 0); --adr: 01
signal chip_1_reg_02 : std_logic_vector(7 downto 0); --adr: 02
signal chip_1_reg_03 : std_logic_vector(7 downto 0); --adr: 03
signal chip_1_reg_04 : std_logic_vector(7 downto 0); --adr: 04
signal chip_1_reg_05 : std_logic_vector(7 downto 0); --adr: 05
signal chip_1_reg_06 : std_logic_vector(7 downto 0); --adr: 06
signal chip_1_reg_07 : std_logic_vector(7 downto 0); --adr: 07
signal chip_1_reg_08 : std_logic_vector(7 downto 0); --adr: 08
signal chip_1_reg_09 : std_logic_vector(7 downto 0); --adr: 09
signal chip_1_reg_10 : std_logic_vector(7 downto 0); --adr: 10
signal chip_1_reg_11 : std_logic_vector(7 downto 0); --adr: 11
signal chip_1_reg_12 : std_logic_vector(7 downto 0); --adr: 12
signal chip_1_reg_13 : std_logic_vector(7 downto 0); --adr: 13
signal chip_1_reg_14 : std_logic_vector(7 downto 0); --adr: 14
signal chip_1_reg_15 : std_logic_vector(7 downto 0); --adr: 15
signal chip_1_reg_16 : std_logic_vector(7 downto 0); --adr: 16
signal chip_1_reg_17 : std_logic_vector(7 downto 0); --adr: 17
signal chip_2_reg_00 : std_logic_vector(7 downto 0); --adr: 20
signal chip_2_reg_01 : std_logic_vector(7 downto 0); --adr: 21
signal chip_2_reg_02 : std_logic_vector(7 downto 0); --adr: 22
signal chip_2_reg_03 : std_logic_vector(7 downto 0); --adr: 23
signal chip_2_reg_04 : std_logic_vector(7 downto 0); --adr: 24
signal chip_2_reg_05 : std_logic_vector(7 downto 0); --adr: 25
signal chip_2_reg_06 : std_logic_vector(7 downto 0); --adr: 26
signal chip_2_reg_07 : std_logic_vector(7 downto 0); --adr: 27
signal chip_2_reg_08 : std_logic_vector(7 downto 0); --adr: 28
signal chip_2_reg_09 : std_logic_vector(7 downto 0); --adr: 29
signal chip_2_reg_10 : std_logic_vector(7 downto 0); --adr: 30
signal chip_2_reg_11 : std_logic_vector(7 downto 0); --adr: 31
signal chip_2_reg_12 : std_logic_vector(7 downto 0); --adr: 32
signal chip_2_reg_13 : std_logic_vector(7 downto 0); --adr: 33
signal chip_2_reg_14 : std_logic_vector(7 downto 0); --adr: 34
signal chip_2_reg_15 : std_logic_vector(7 downto 0); --adr: 35
signal chip_2_reg_16 : std_logic_vector(7 downto 0); --adr: 36
signal chip_2_reg_17 : std_logic_vector(7 downto 0); --adr: 37
BEGIN
read_write_reg_bank_1 : process()
begin
if rst = '1' then
-- default value --
chip_1_reg_00 => X"DE";
chip_1_reg_01 => X"60";
chip_1_reg_02 => X"28";
chip_1_reg_03 => X"00";
chip_1_reg_04 => X"00";
chip_1_reg_05 => X"00";
chip_1_reg_06 => X"00";
chip_1_reg_07 => X"00";
chip_1_reg_08 => X"26";
chip_1_reg_09 => X"1A";
chip_1_reg_10 => X"05";
chip_1_reg_11 => X"1F";
chip_1_reg_12 => X"16";
chip_1_reg_13 => X"7C";
chip_1_reg_14 => X"FF";
chip_1_reg_15 => X"FF";
chip_1_reg_16 => X"FF";
chip_1_reg_17 => X"FF";
elsif m_clk'event and m_clk = '1' then
if wren_chip_1 = '1' then
case select_chip_1
else
end if;
end if;
end process;
read_write_reg_bank_2 : process()
begin
if rst = '1' then
-- default value --
chip_2_reg_00 => X"DE";
chip_2_reg_01 => X"60";
chip_2_reg_02 => X"28";
chip_2_reg_03 => X"00";
chip_2_reg_04 => X"00";
chip_2_reg_05 => X"00";
chip_2_reg_06 => X"00";
chip_2_reg_07 => X"00";
chip_2_reg_08 => X"26";
chip_2_reg_09 => X"1A";
chip_2_reg_10 => X"05";
chip_2_reg_11 => X"1F";
chip_2_reg_12 => X"16";
chip_2_reg_13 => X"7C";
chip_2_reg_14 => X"FF";
chip_2_reg_15 => X"FF";
chip_2_reg_16 => X"FF";
chip_2_reg_17 => X"FF";
elsif m_clk'event and m_clk = '1' then
if wren_chip_1 = '1' then
case select_chip_1
else
end if;
end if;
end process;
END behav;
| gpl-3.0 | 0b7dafbacdad5c3dfc33ba2993e10346 | 0.504666 | 2.916513 | false | false | false | false |
peladex/RHD2132_FPGA | quartus/test_spi_de0/gen_pulso.vhd | 1 | 2,770 | LIBRARY ieee ;
USE ieee.std_logic_1164.all;
package PK_GEN_PULSO is
component GEN_PULSO is
port(
clk : in std_logic; -- clk
reset : in std_logic; -- reset
input : in std_logic; -- input
edge_detected : out std_logic -- edge_detected: pulso a 1 cuando
-- se detecta flanco en input
);
end component;
end PK_GEN_PULSO;
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
entity GEN_PULSO is
port(
clk : in std_logic; -- clk
reset : in std_logic; -- reset
input : in std_logic; -- input
edge_detected : out std_logic -- edge_detected: pulso a 1 cuando
-- se detecta flanco en input
);
end;
architecture BEHAV of GEN_PULSO is
-- states
type state_type IS
(st_espero0, st_espero1, st_flanco_detectado);
attribute enum_encoding : string;
attribute enum_encoding of state_type : type is "one-hot"; -- "default", "sequential", "gray", "johnson", or "one-hot"
signal STATE, NXSTATE : state_type;
-- info sobre codificación: http://quartushelp.altera.com/13.0/mergedProjects/hdl/vhdl/vhdl_file_dir_enum_encoding.htm
--- CONSTANT st_espero0 : std_logic_vector(1 DOWNTO 0):= "00";
--- CONSTANT st_espero1 : std_logic_vector(1 DOWNTO 0):= "01";
--- CONSTANT st_flanco_detectado : std_logic_vector(1 DOWNTO 0):= "11";
--- signal STATE, NXSTATE : std_logic_vector(1 DOWNTO 0);
begin
-- Process donde se genera la salida
-- dependiente de estado y entrada
-- y proximo estado.
combin: process (STATE, input)
begin
case STATE is
when st_espero0 =>
if input ='1' then
NXSTATE <= st_espero0;
else
NXSTATE <= st_espero1;
end if;
edge_detected <= '0';
when st_espero1 =>
if input ='0' then
NXSTATE <= st_espero1;
else
NXSTATE <= st_flanco_detectado;
end if;
edge_detected <= '0';
when st_flanco_detectado =>
if input ='0' then
NXSTATE <= st_espero1;
else
NXSTATE <= st_espero0;
end if;
edge_detected <= '1';
when others =>
NXSTATE <= st_espero1;
edge_detected <= '0';
end case;
end process;
-- Process donde se generan los FF
-- sensibles a flanco
-- de subida de la máquina de estado
sync:process (clk,reset,STATE)
begin
if reset = '1' then
STATE <= st_espero1;
elsif clk'event and clk = '1' then
STATE <= NXSTATE;
end if;
end process;
end BEHAV;
| gpl-3.0 | 83fc0ea9f6a60cb581e79c9351ac1475 | 0.541381 | 3.864525 | false | false | false | false |
rpereira-dev/ENSIIE | UE/S3/microarchi/bus_ia/wrapper_hinit.vhd | 1 | 4,489 | -------------------------------------------------------------------------------
--
-- Ce bloc est le wrapper dans le bus ia
--
-- Ce module transfert tous les messages (????,addrsrc,addrdest,data) venant de
-- busin.
--
-- data est stocké dans un registre
--
-- Si addrdest==MYADDR, data est transmis sur busv
-- Sinon, tout le message est transféré sur busout
--
-- Du coté busin, il suit le protocole "poignée de main" (signaux: busin,
-- busin_valid, busin_eated).
--
-- Du coté busout, il suit le protocole "poignée de main" (signaux: busout,
-- busout_valid, busout_eated).
--
-- Du coté busmsg, la valeur du message est transmise
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY wrapper_hinit IS
GENERIC(
MYADDR : STD_LOGIC_VECTOR(7 downto 0) := "00001010" -- 10
);
PORT(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
-- interface busin
busin : in STD_LOGIC_VECTOR(43 downto 0);
busin_valid : in STD_LOGIC;
busin_eated : out STD_LOGIC;
-- interface busout
busout : out STD_LOGIC_VECTOR(43 downto 0);
busout_valid : out STD_LOGIC;
busout_eated : in STD_LOGIC;
-- N : nombre de clock à attendre pour générer un tick
busN : out STD_LOGIC_VECTOR(23 downto 0)
);
END wrapper_hinit;
ARCHITECTURE montage OF wrapper_hinit IS
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
-- Registre de transfert entre busin et busout
type T_CMD_tft is (INIT, NOOP);
signal CMD_tft : T_CMD_tft ;
signal R_tft : STD_LOGIC_VECTOR (43 downto 0);
type T_CMD_msg is (LOAD, NOOP);
signal CMD_msg : T_CMD_msg ;
-- registre stockant V (nombre de master clock à attendre avant de générer un tick)
signal R_N : STD_LOGIC_VECTOR(23 downto 0);
-------------------------------------------------------------------------------
-- Partie Contrôle
-------------------------------------------------------------------------------
-- adresse destination
alias busin_addrdest : STD_LOGIC_VECTOR(7 downto 0) is busin(31 downto 24);
type STATE_TYPE is (
ST_READ_BUSIN, ST_WRITE_OUT, ST_LOAD_N
);
signal state : STATE_TYPE;
BEGIN
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
PROCESS (reset, clk)
BEGIN
-- si on reset
IF reset = '1' THEN
-- 5 000 000 <=> 100 ticks par secondes
R_N <= "010011000100101101000000";
ELSIF clk'event AND clk = '1' THEN
-- commandes de transfert bus ia
-- si l'on doit lire le message, on le stocke
-- dans le registre 'R_tft'
IF CMD_tft = INIT THEN
R_tft <= busin ;
END IF;
-- on charge la valeur de 'N'
IF CMD_msg = LOAD THEN
R_N <= R_tft(23 downto 0);
END IF ;
END IF;
END PROCESS;
-- sortie
busN <= R_N;
busout <= R_tft;
-------------------------------------------------------------------------------
-- Partie Contrôle
-------------------------------------------------------------------------------
-- Inputs: busin_valid, busout_eated, busin_addrdest
-- Outputs: busin_eated, busout_valid, CMD_tft
-------------------------------------------------------------------------------
-- fonction de transitition
PROCESS (reset,clk)
BEGIN
IF reset = '1' THEN
state <= ST_READ_BUSIN;
ELSIF clk'event AND clk = '1' THEN
CASE state IS
WHEN ST_READ_BUSIN =>
IF busin_valid='1' THEN
IF busin_addrdest = MYADDR THEN
state <= ST_LOAD_N;
ELSE
state <= ST_WRITE_OUT ;
END IF ;
END IF ;
WHEN ST_WRITE_OUT =>
IF busout_eated = '1' THEN
state <= ST_READ_BUSIN;
END IF ;
WHEN ST_LOAD_N =>
state <= ST_READ_BUSIN;
END CASE;
END IF;
END PROCESS;
-- fonction de sortie
with state select busin_eated <=
'1' when ST_READ_BUSIN,
'0' when others
;
with state select busout_valid <=
'1' when ST_WRITE_OUT,
'0' when others
;
with state select CMD_tft <=
INIT when ST_READ_BUSIN,
NOOP when others
;
with state select CMD_msg <=
LOAD when ST_LOAD_N,
NOOP when others
;
end montage;
| gpl-3.0 | 3a033b16ccdec9a53bae791a4e91bd79 | 0.493626 | 3.760303 | false | false | false | false |
DaveyPocket/btrace448 | core/vga/outputInterface.vhd | 1 | 1,183 | -- Btrace 448
-- Output Interface
--
-- Bradley Boccuzzi
-- 2016
library ieee;
use ieee.std_logic_1164.all;
entity outputInterface is
port(clk, rst: in std_logic;
get_pixel: out std_logic; -- Status signal
pixel_x, pixel_y: out std_logic_vector(9 downto 0); -- Address read signal
din: in std_logic_vector(11 downto 0); -- RGB in 1
overlay: in std_logic_vector(11 downto 0);-- RGB in 2
en_overlay: in std_logic;
hsync, vsync: out std_logic;
rgb: out std_logic_vector(11 downto 0));
end outputInterface;
architecture arch of outputInterface is
signal video_on, p_tick: std_logic;
signal s_rgb: std_logic_vector(11 downto 0);
begin
-- VGA sync generator
vga_sync_dev: entity work.vga_sync port map(clk, rst, hsync, vsync, video_on, p_tick, pixel_x, pixel_y);
-- Pixel buffer
process(clk, rst)
begin
if rst = '1' then
s_rgb <= (others => '0');
elsif rising_edge(clk) then
s_rgb <= din;
end if;
end process;
-- Concurrent signal assignment
get_pixel <= p_tick;
--rgb <= s_rgb when overlay else x"000";
rgb <= s_rgb when ((video_on = '1') and (en_overlay = '0')) else
overlay when ((video_on and en_overlay) = '1') else x"000";
end arch;
| gpl-3.0 | 9aab023d10e3641eb897ae68cc82e44f | 0.67033 | 2.871359 | false | false | false | false |
boztalay/OldProjects | FPGA/Subsystems/Subsys_Adder/Subsys_Adder.vhd | 1 | 3,141 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 03:30:43 04/10/2009
-- Design Name:
-- Module Name: Subsys_Adder - Behavioral
-- Project Name: 3-Bit Adder
-- Target Devices:
-- Tool versions:
-- Description: A system that is able to store two 3-bit numbers, add them, and display their result in hexadecimal
-- on a 7-segment display
--
-- Dependencies: Comp_4bitRegister.vhd, Comp_FullAdder.vhd, Comp_7segDecoder.vhd, Comp_Dflipflop.vhd,
-- Gate_Nand.vhd, Gate_And.vhd Gate_Or.vhd, Gate_Xor.vhd, Gate_Inv.vhd, Gate_Buf.vhd
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Subsys_Adder is
Port ( N1 : in STD_LOGIC_VECTOR (3 downto 0);
N2 : in STD_LOGIC_VECTOR (3 downto 0);
CLK1 : in STD_LOGIC;
CLK2 : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR (6 downto 0);
ano : out STD_LOGIC_VECTOR (3 downto 0));
end Subsys_Adder;
architecture Behavioral of Subsys_Adder is
component Comp_4bitRegister is
Port ( D1 : in STD_LOGIC;
D2 : in STD_LOGIC;
D3 : in STD_LOGIC;
D4 : in STD_LOGIC;
CLK : in STD_LOGIC;
Q1 : out STD_LOGIC;
Q2 : out STD_LOGIC;
Q3 : out STD_LOGIC;
Q4 : out STD_LOGIC);
end component;
component Comp_FullAdder is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end component;
component Comp_7segDecoder is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
seg : out STD_LOGIC_VECTOR (6 downto 0));
end component;
signal S1 : STD_LOGIC;
signal S2 : STD_LOGIC;
signal S3 : STD_LOGIC;
signal S4 : STD_LOGIC;
signal S5 : STD_LOGIC;
signal S6 : STD_LOGIC;
signal S7 : STD_LOGIC;
signal S8 : STD_LOGIC;
signal S9 : STD_LOGIC;
signal S10 : STD_LOGIC;
signal S11 : STD_LOGIC;
signal S12 : STD_LOGIC;
signal S13 : STD_LOGIC_VECTOR (3 downto 0);
signal S14 : STD_LOGIC;
signal S15 : STD_LOGIC;
signal S16 : STD_LOGIC;
signal S17 : STD_LOGIC;
begin
S13(0) <= S14;
S13(1) <= S15;
S13(2) <= S16;
S13(3) <= S17;
G1: Comp_4bitRegister port map (N1(0), N1(1), N1(2), N1(3), CLK1, S1, S2, S3);
G2: Comp_4bitRegister port map (N2(0), N2(1), N2(2), N2(3), CLK1, S4, S5, S6);
G3: Comp_FullAdder port map (S1, S4, '0', S9, S7);
G4: Comp_FullAdder port map (S2, S5, S7, S10, S8);
G5: Comp_FullAdder port map (S3, S6, S8, S11, S12);
G6: Comp_4bitRegister port map (S9, S10, S11, S12, CLK2, S14, S15, S16, S17);
G7: Comp_7segDecoder port map (S13, seg);
ano <= "1110";
end Behavioral;
| mit | b80fcc50dbeacff655d32852038d3bcf | 0.578478 | 2.982906 | false | false | false | false |
fkolacek/FIT-VUT | INP2/fpga/rom.vhd | 1 | 1,702 | -- rom.vhd : ROM memory
-- Copyright (C) 2011 Brno University of Technology,
-- Faculty of Information Technology
-- Author(s): Zdenek Vasicek <vasicek AT fit.vutbr.cz>
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_arith.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity rom is
generic (
INIT : string := ""
);
port (
CLK : in std_logic; -- clock
EN : in std_logic;
ADDR : in std_logic_vector(11 downto 0); -- address
DATA : out std_logic_vector(7 downto 0) -- data
);
end rom;
-- ----------------------------------------------------------------------------
-- Architecture declaration
-- ----------------------------------------------------------------------------
architecture behavioral of rom is
type t_ram is array (0 to 2**12-1) of std_logic_vector(7 downto 0);
function str2vec(arg: string; size: integer) return t_ram is
variable result: t_ram := (others => (others => '0'));
begin
for i in arg'range loop
result(i-1) := conv_std_logic_vector(character'pos(arg(i)), 8);
end loop;
return result;
end;
constant mem: t_ram := str2vec(INIT, 2*2048);
signal dout : std_logic_vector(7 downto 0) := (others => '0');
begin
process (CLK)
begin
if (CLK'event) and (CLK = '1') then
if (EN = '1') then
dout <= mem(conv_integer(ADDR));
end if;
end if;
end process;
DATA <= dout;
end behavioral;
| apache-2.0 | 60c76693f09cd4c63391a77cb3e77c6f | 0.474148 | 4.121065 | false | false | false | false |
DaveyPocket/btrace448 | math/dot.vhd | 1 | 643 | -- Btrace 448
-- Dot Product Unit
--
-- Bradley Boccuzzi
-- 2016
library ieee;
library ieee_proposed;
use ieee.std_logic_1164.all;
use ieee_proposed.fixed_pkg.all;
use ieee.std_logic_signed.all;
use work.btrace_pack.all;
entity dot is
generic(int, frac: integer := 16);
port(v1, v2: in vector;
result: out sfixed((2*int)-1 downto -(2*frac)));
end dot;
architecture arch of dot is
signal r1, r2, r3: sfixed((2*int)-1 downto -(2*frac));
signal cr: sfixed((2*int)+1 downto -(2*frac));
begin
r1 <= v1.m_x * v2.m_x;
r2 <= v1.m_y * v2.m_y;
r3 <= v1.m_z * v2.m_z;
cr <= r1 + r2 + r3;
result <= cr((2*int)-1 downto -(2*frac));
end arch;
| gpl-3.0 | 85e1e9622660af3ee5185bdc1798cad5 | 0.640747 | 2.381481 | false | false | false | false |
boztalay/OldProjects | FPGA/LCD_Control/TestCPU1_iRAM.vhd | 1 | 5,761 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 00:30:19 10/03/2009
-- Design Name:
-- Module Name: TestCPU1_iROM - Behavioral
-- Project Name: Test CPU 1
-- Target Devices:
-- Tool versions:
-- Description: The instruction ROM for Test CPU 1
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TestCPU1_iROM is
Port ( addr : in STD_LOGIC_VECTOR (10 downto 0);
data_out : out STD_LOGIC_VECTOR (15 downto 0));
end TestCPU1_iROM;
architecture Behavioral of TestCPU1_iROM is
begin
iROM: process (addr) is
type iROM_array is array (2047 downto 0) of
STD_LOGIC_VECTOR (15 downto 0);
variable iROM: iROM_array := (0 => "0000000000000000", --null
1 => "0001001000011001", --addi r2, r0, 25 --loading r2 with value
2 => "0000001001001000", --add r2, r2, r2
3 => "0000001001001000", --add r2, r2, r2
4 => "0000001001001000", --add r2, r2, r2
5 => "0000001001001000", --add r2, r2, r2
6 => "0000001001001000", --add r2, r2, r2
7 => "0001001001010001", --addi r2, r2,17
8 => "0000001001001000", --add r2, r2, r2
9 => "0000001001001000", --add r2, r2, r2
10 => "0000001001001000", --add r2, r2, r2
11 => "0001001100001111", --addi r3, r0, 15 --loading r3 with value
12 => "0001010000011001", --addi r4, r0, 25 --loading r4 with value
13 => "0000010010010000", --add r4, r4, r4
14 => "0000010010010000", --add r4, r4, r4
15 => "0000010010010000", --add r4, r4, r4
16 => "0000010010010000", --add r4, r4, r4
17 => "0001010110100001", --addi r5, r5, 1 --begin waiting for 20ms
18 => "0010000010101000", --cp r5, r2
19 => "0100000000010101", --bz r0, 21
20 => "0100100000010001", --jp 17
21 => "1000000000000001", --opin 0, 1 --RS = '0' (r1 = 0) sending set function
22 => "1000000000000010", --opin 0, 2 --RW = '0' //leaving at '0' for the rest
23 => "1000000000100000", --opin 1, 0 --E = '1'
24 => "1000000000100011", --opin 1, 3 --DBe = '1'
25 => "1000000000000000", --opin 0, 0 --E = '0'
26 => "1000000000000011", --opin 0, 3 --DBe = '0'
27 => "0001011011000001", --addi r6, r6, 1 --begin waiting for 40us
28 => "0010000011001100", --cp r6, r3
29 => "0100000000011111", --bz r0, 31
30 => "0100100000011011", --jp 27
31 => "0001000100100001", --addi r1, r1 --increment message ROM address
32 => "1000000000100000", --opin 1, 0 --E = '1' (r1 = 1) sending display set
33 => "1000000000100011", --opin 1, 3 --DBe = '1'
34 => "1000000000000000", --opin 0, 0 --E = '0'
35 => "1000000000000011", --opin 0, 3 --DBe = '0'
36 => "0001011111100001", --addi r7, r7, 1 --begin waiting for 40us
37 => "0010000011101100", --cp r7, r3
38 => "0100000000101000", --bz r0, 40
39 => "0100100000100100", --jp 36
40 => "0001000100100001", --addi r1, r1 --increment message ROM address
41 => "1000000000100000", --opin 1, 0 --E = '1' (r1 = 2) sending display clear
42 => "1000000000100011", --opin 1, 3 --DBe = '1'
43 => "1000000000000000", --opin 0, 0 --E = '0'
44 => "1000000000000011", --opin 0, 3 --DBe = '0'
45 => "0001011100000000", --addi r7, r0, 0 --reset r7
46 => "0001011111100001", --addi r7, r7, 1 --begin waiting for 1.60ms
47 => "0010000011110000", --cp r7, r4
48 => "0100000000110010", --bz r0, 50
49 => "0100100000101110", --jp 46
50 => "1000000000100001", --opin 1, 1 --RS = '1' begin writing, leave RS = 1
51 => "0001011100001110", --addi r7, r0, 14
52 => "0001000100100001", --addi r1, r1 --increment message ROM address //begin writing message
53 => "1000000000100000", --opin 1, 0 --E = '1'
54 => "1000000000100011", --opin 1, 3 --DBe = '1'
55 => "1000000000000000", --opin 0, 0 --E = '0'
56 => "1000000000000011", --opin 0, 3 --DBe = '0'
57 => "0001011000000000", --addi r6, r0, 0 --reset r6
58 => "0001011011000001", --addi r6, r6, 1 --pause for 40us
59 => "0010000011001100", --cp r6, r3
60 => "0100000000111110", --bz r0, 62
61 => "0100100000111010", --jp 58 --end pause
62 => "0010000011100100", --cp r1, r7
63 => "0100000001000001", --bz 65
64 => "0100100000110100", --jp 52 --loop until r1 = 14
65 => "0100100001000010", --jp 66 --loop forever
66 => "0100100001000001", --jp 65
others => "0000000000000000");
begin
data_out <= iROM(conv_integer(unsigned(addr)));
end process;
end Behavioral;
| mit | 914d279a81e15ddfc20b25110b94d509 | 0.497136 | 3.582711 | false | true | false | false |
freecores/line_codes | bench/vhdl/smlt_hdb1_enc.vhd | 1 | 921 |
-- smlttion for HDB1 encoder.
entity smlt_hdb1_enc is
end smlt_hdb1_enc;
architecture behaviour of smlt_hdb1_enc is
--data type:
component hdb1_enc
port (
clr_bar,
clk : in bit;
e : in bit;
s0, s1: out bit);
end component;
--binding:
for a: hdb1_enc use entity work.hdb1_enc;
--declaring the signals present in this architecture:
signal CLK, E, S0, S1, clrb: bit;
signal inpute: bit_vector(0 to 24);
begin --architecture.
a: hdb1_enc port map
( clr_bar => clrb, clk => CLK, e => E, s0 => S0,
s1 => S1 );
inpute <= "0101011000101100101000011";
process begin
clrb <= '1';
for i in 0 to 24 loop
E <= inpute(i);
CLK <= '0';
wait for 9 ns;
CLK <= '1';
wait for 1 ns;
end loop;
wait;
end process;
end behaviour;
| gpl-2.0 | eee2fdfd84f3982ef1baf96b91ef96c4 | 0.521173 | 3.15411 | false | false | false | false |
rpereira-dev/ENSIIE | UE/S3/microarchi/bus_ia/h10.vhd | 1 | 2,616 | -------------------------------------------------------------------------------
-- Ce module prends un fil en entrée, 1 si c'est un tick, 0 sinon
-- Sa sortie vaut successivement 0 puis 1 tous les 10 ticks
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
-- diode h10
ENTITY h10 IS
PORT(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
T : in STD_LOGIC;
S : out STD_LOGIC
);
END h10;
ARCHITECTURE montage OF h10 IS
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
TYPE T_CMD IS (INIT, COUNT, NOOP);
-- la commande courante
signal CMD : T_CMD;
-- registre de comptagne 10 => 9 => ... => 0 => 10 => ...
signal C : unsigned(3 downto 0);
signal R : STD_LOGIC ;
-- boolean vaux 1 si C est à 0, 0 sinon
signal C_IS_ZERO: STD_LOGIC;
-------------------------------------------------------------------------------
-- Partie Contrôle
-------------------------------------------------------------------------------
type STATE_TYPE is (
ST_INIT, ST_COUNT
);
signal state : STATE_TYPE;
begin
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
process (reset, clk)
begin
IF reset = '1' THEN
C <= to_unsigned(10, 4);
R <= '1';
ELSIF clk'event and clk = '1' then
IF CMD = INIT THEN
C <= to_unsigned(10, 4);
R <= not(R);
ELSIF CMD = COUNT AND T = '1' THEN
C <= C - 1;
END IF;
end if;
end process;
C_IS_ZERO <= '1' WHEN C = 0 ELSE '0' ;
S <= R ;
-------------------------------------------------------------------------------
-- Partie Contrôle
-------------------------------------------------------------------------------
-- Inputs: T
-- Outputs: S, CMD
-------------------------------------------------------------------------------
-- fonction de transitition
process (reset, clk)
begin
if reset = '1' then
state <= ST_INIT;
elsif clk'event and clk = '1' then
case state is
when ST_INIT =>
state <= ST_COUNT ;
when ST_COUNT =>
IF C_IS_ZERO = '1' THEN
state <= ST_INIT ;
END IF ;
end case;
end if;
end process;
-- fonction de sortie
with state select CMD <=
INIT when ST_INIT,
COUNT when ST_COUNT
;
end montage;
| gpl-3.0 | babaec185bd61b51a99badac3a2b1c18 | 0.372797 | 4.285714 | false | false | false | false |
rpereira-dev/ENSIIE | UE/S3/microarchi/bus_ia/serpentinantihoraire.vhd | 1 | 906 | -------------------------------------------------------------------------------
-- Ce bloc est un registre contenant la configuration a transmettre au
-- serpentin programmable, pour qu'il affiche un serpentin tournant dans
-- le sens anti-horaire.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
entity serpentinantihoraire is
port(
Config : OUT STD_LOGIC_VECTOR(229 downto 0)
);
end serpentinantihoraire;
architecture montage of serpentinantihoraire is
begin
-- boucle sur 6 frames
Config(229 downto 224) <= "000110";
-- les frames
Config( 6 downto 0) <= "0011101";
Config( 13 downto 7) <= "0111001";
Config( 20 downto 14) <= "1110001";
Config( 27 downto 21) <= "1100011";
Config( 34 downto 28) <= "1000111";
Config( 41 downto 35) <= "0001111";
end montage;
| gpl-3.0 | 5563622f6162b81e33cd8d0b92c6a82e | 0.569536 | 3.93913 | false | true | false | false |
fkolacek/FIT-VUT | INP2/fpga/top.vhd | 1 | 12,641 | -- top.vhd : TOP level entity, BrainFuck microcontroller
-- Copyright (C) 2011 Brno University of Technology,
-- Faculty of Information Technology
-- Author(s): Zdenek Vasicek
--
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_ARITH.ALL;
use IEEE.std_logic_UNSIGNED.ALL;
architecture main of tlv_bare_ifc is
-- displej
signal lcd_data : std_logic_vector(7 downto 0);
signal lcd_we, lcd_busy : std_logic;
signal rom_addr : std_logic_vector(11 downto 0);
signal rom_dout : std_logic_vector(7 downto 0);
signal rom_en : std_logic;
signal ram_addr: std_logic_vector(9 downto 0);
signal ram_rdata: std_logic_vector(7 downto 0);
signal ram_wdata: std_logic_vector(7 downto 0);
signal ram_rdwr: std_logic;
signal ram_en : std_logic;
signal in_data : std_logic_vector(7 downto 0);
signal in_req : std_logic;
signal kb_ack : std_logic;
signal in_vld : std_logic := '0';
signal timer : integer range 0 to 20000;
signal cpu_rst : std_logic;
signal cpu_en : std_logic := '0';
component cpu is
port (
RESET : in std_logic;
CLK : in std_logic;
EN : in std_logic;
-- ROM mem
CODE_ADDR : out std_logic_vector(11 downto 0);
CODE_DATA : in std_logic_vector(7 downto 0);
CODE_EN : out std_logic;
-- RAM mem
DATA_ADDR : out std_logic_vector(9 downto 0);
DATA_WDATA : out std_logic_vector(7 downto 0);
DATA_RDATA : in std_logic_vector(7 downto 0);
DATA_RDWR : out std_logic;
DATA_EN : out std_logic;
-- INPUT
IN_DATA : in std_logic_vector(7 downto 0);
IN_VLD : in std_logic;
IN_REQ : out std_logic;
-- OUTPUT
OUT_DATA : out std_logic_vector(7 downto 0);
OUT_BUSY : in std_logic;
OUT_WE : out std_logic
);
end component;
begin
-- ================================================
-- Procesor
-- ================================================
bfcpu: cpu
port map(
--Ridici signaly
RESET => cpu_rst, -- Reset
CLK => CLK, -- Hodiny
EN => cpu_en, -- povoleni cinnosti
--ROM
CODE_ADDR => rom_addr,
CODE_DATA => rom_dout,
CODE_EN => rom_en,
--RAM
DATA_ADDR => ram_addr,
DATA_RDATA => ram_rdata,
DATA_WDATA => ram_wdata,
DATA_RDWR => ram_rdwr,
DATA_EN => ram_en,
--INPUT
IN_DATA => in_data,
IN_VLD => in_vld,
IN_REQ => in_req,
--OUTPUT
OUT_DATA => lcd_data,
OUT_BUSY => lcd_busy,
OUT_WE => lcd_we
);
-- ================================================
-- Pamet programu
-- ================================================
rom_mem: entity work.rom
generic map (
-- Inicializace obsahu pameti ROM (pamet programu obsahujici kod v jazyce BrainFuck),
-- odkomentovat vzdy pouze jeden radek nastavujici generickou promennou INIT
-- Vyuziti programu pro overeni cinnosti:
-- [1] - overeni vystupu
-- [2], [5] - overeni jednoduche while smycky a vystupu
-- [3] - overeni vstupu a vystupu
-- [4] - overeni vstupu a vystupu, vlozene komentare
-- [6], [7], [8] - overeni korektni funkce vnorenych smycek, vstupu a vystupu
-- vypis xkolac12
INIT => "++++++++++[>++++++++++++>+++++++++++>+++++<<<-]>.>---.++++.---.-----------.++.>-.+." & nul
-- [1] Vypis textu na displej
-- INIT => "+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++.+.+.+.+.+.+.+.+.+.+.+." & nul
-- [2] Vypis textu na displej
-- INIT => "++++++++++[>+++++++>+++>+++++<<<-]>+++.+++++.++.>>-----.+++++.--.+.+.-----.<<++++++++++++++++++++++++++++++++.++.---.-----.>>+++++." & nul
-- [3] Vypis znaku stisknutych na klavesnici na displej (vypise se max. 10 znaku, pote se program ukonci)
-- INIT => "++++++++++[>,.<-] 10x opakovat nacteni znaku a zapis na display" & nul
-- [4] Vypis znaku stisknutych na klavesnici na displej (vypisuje se dokud neni stisknuta klavesa * nebo # (tzn. konec radku))
-- INIT => "+[->,[>+>+<<-] nacteni vstupu do bunky 1 kopirovani nactene hodnoty do bunky 2 a 3 +>---------- odecteni 10 od bunky 2 [>.<[-]<<+>>>[-]< pokud byla hodnota bunky 2 rozdilna od 0 vypis na display znulovani bunky 2 znulovani bunky 3]<<]" & nul
-- [5] Vypis druhych mocnin od 0 do 10000
-- INIT => "++++[>+++++<-]>[<+++++>-]+<+[ >[>+>+<<-]++>>[<<+>>-]>>>[-]++>[-]+ >>>+[[-]++++++>>>]<<<[[<++++++++<++>>-]+<.<[>----<-]<] <<[>>>>>[>>>[-]+++++++++<[>-<-]+++++++++>[-[<->-]+[<<<]]<[>+<-]>]<<-]<<-][Outputs square numbers from 0 to 10000.Daniel B Cristofani (cristofdathevanetdotcom)http://www.hevanet.com/cristofd/brainfuck/]" & nul
-- [6] Vypis prvocisel (vypis prvocisel na displej az do maxima zadaneho na klavesnici; postup: zadat cislo, potvrdit klavesou #)
-- INIT => "+[->,----------[<+>-------------------------------------->[>+>+<<-]>>[<<+>>-]<>>>+++++++++[<<<[>+>+<<-]>>[<<+>>-]<[<<+>>-]>>-]<<<[-]<<[>+<-]]<]>>[<<+>>-]<<>+<-[>+[>+>+<<-]>>[<<+>>-]<>+<-->>>>>>>>+<<<<<<<<[>+<-<[>>>+>+<<<<-]>>>>[<<<<+>>>>-]<<<>[>>+>+<<<-]>>>[<<<+>>>-]<<<<>>>[>+>+<<-]>>[<<+>>-]<<<[>>>>>+<<<[>+>+<<-]>>[<<+>>-]<[>>[-]<<-]>>[<<<<[>+>+<<-]>>[<<+>>-]<>>>-]<<<-<<-]+>>[<<[-]>>-]<<>[-]<[>>>>>>[-]<<<<<<-]<<>>[-]>[-]<<<]>>>>>>>>[-<<<<<<<[-]<<[>>+>+<<<-]>>>[<<<+>>>-]<<<>>[>+<-]>[[>+>+<<-]>>[<<+>>-]<>+++++++++<[>>>+<<[>+>[-]<<-]>[<+>-]>[<<++++++++++>>-]<<-<-]+++++++++>[<->-]<[>+<-]<[>+<-]<[>+<-]>>>[<<<+>>>-]<>+++++++++<[>>>+<<[>+>[-]<<-]>[<+>-]>[<<++++++++++>>>+<-]<<-<-]>>>>[<<<<+>>>>-]<<<<>[-]<<+>]<[[>+<-]+++++++[<+++++++>-]<-><.[-]>>[<<+>>-]<<-]>++++[<++++++++>-]<.[-]>>>>>>>]<<<<<<<<>[-]<[-]<<-]++++++++++.[-]" & nul
-- [7] Faktorizace cisla (rozklad cisla zadaneho na klavesnici na prvocisla a zobrazeni na displej; postup: zadat cislo, potvrdit klavesou #; overeni viz http://www.numberempire.com/numberfactorizer.php)
-- INIT => ">>>>>>>>>>>>>>>>>>>>>>>>>>>>>>-<<<<<<<<<+[-[>>>>>>>>>>][-]<<<<<<<<<<[[->>>>>>>>>>+<<<<<<<<<<]<<<<<<<<<<]>>>>>>>>>>,----------]>>>>>>>>>>[------------------------------------->>>>>>>>>->]<[+>[>>>>>>>>>+>]<-<<<<<<<<<<]-[>++++++++++++++++++++++++++++++++++++++++++++++++.------------------------------------------------<<<<<<<<<<<]++++++++++++++++++++++++++++++++++++++++++++++++++++++++++.--------------------------.[-]>>>>>>>>>>>>++<<<<+[[-]>>[>>>>[-]>[-]>[-]>[-]>[-]>[-]<<<<<<<[->>>+>+<<<<]>>>>>>>>]<<<<<<<<<<[>>>>>>[-<<<<+>>>>]<<<<<<<<<<<<<<<<]>>>>>>>>>>[>[->>>+>>+<<<<<]>>>>>>>>>]<<<<<<<<<<[>>>>>>[-<<<<<+>>>>>]<<<<<<<<<<<<<<<<]>>>>>>>>>>[>>>[-]>>>[-]>[-]>>>]<<<<<<<<<<[<<<<<<<<<<]>>>>>>>>>[-]>>>>>>>+<<<<<<<<[+]+[->>[>>>>>>[->++<]>>>>]<<<<<<<<<<[>>>>>>>>[-]>[-]<<<<[->>>++<<<]<<<<<<<<<<<<<<<]>>>>>>>>>>[>>>>>>>>[->+<[->+<[->+<[->+<[->+<[->+<[->+<[->+<[->+<[->--------->>>>>>>>>+<<<<<<<<<<[->+<]]]]]]]]]]]>>]<<<<<<<<<<[>>>>>>>>>[-<+<<<+>>>>]<<<<<<<<<<<<<<<<<<<]>>>>>>>>>>[>>>>>>>[-<+>[-<+>[-<+>[-<+>[-<+>[-<+>[-<+>[-<+>[-<+>[-<--------->>>>>>>>>>>+<<<<<<<<<<[-<+>]]]]]]]]]]]>>>]<<<<<<<<<<[>>>>[->>>+>>+<<<<<]<<<<<<<<<<<<<<]>>>>>>>>>>[>>>>>>>[-<<<+>>>]>>>]<<<<<<<<<<[>>>>>>>>[->-<]>[<<<<<<<<<[<[-]>>>>>>>>>>[-<<<<<<<<<<+>>>>>>>>>>]<<<<<<<<<<<<<<<<<<<]>>>>>>>>>>>>>>>>>>>]<<<<<<<<<<<<<<<<<<<]>>>>>>>>>[+[+[+[+[+[+[+[+[+[+[[-]<+>]]]]]]]]]]]<]>>>>>>>>[<<<<<<[>>>>>>>>[-]>[-]<<<<<[->>>+>+<<<<]>>>>>>]<<<<<<<<<<[>>>>>>>>[-<<<<+>>>>]<<<[->>>+>+<<<<]<<<<<<<<<<<<<<<]>>>>>>>>>>[>>>>>>>>>[-<<<<+>>>>]>]<<<<<<<<<<[>>>>>>>>[-<->]<<<<<<<<<<<<<<<<<<]>>>>>>>>>>[>>>>>>>[->+<[->+<[->+<[->+<[->+<[->+<[->+<[->+<[->+<[->+<[++++++++++[+>-<]>>>>>>>>>>-<<<<<<<<<<]]]]]]]]]]]>>>]>>>>>>>+[[-]<<<<<<<<<<<<<<<<<[>>>>[-]>>>>[-<<<<+>>>>]<<[->>+<<]<<<<<<<<<<<<<<<<]>>>>>>>>>>[>>>>>>>>[->+<<<+>>]>>]<<<<<<<<<<[>>>[->>>>>>+<<<<<<]<<<<<<<<<<<<<]>>>>>>>>>>[>>>>>>>>>[-<<<<<<+>>>>>>[-<<<<<<+>>>>>>[-<<<<<<+>>>>>>[-<<<<<<+>>>>>>[-<<<<<<+>>>>>>[-<<<<<<+>>>>>>[-<<<<<<+>>>>>>[-<<<<<<+>>>>>>[-<<<<<<+>>>>>>[-<<<<<<--------->>>>>>>>>>>>>>>>+<<<<<<<<<<[-<<<<<<+>>>>>>]]]]]]]]]]]>]>>>>>>>]<<<<<<<<<<<<<<<<<[<<<<<<<<<<]>>>>>>>>>>[>>>>>>>>[-]<<[->+<]<[->>>+<<<]>>>>>]<<<<<<<<<<[+>>>>>>>[-<<<<<<<+>>>>>>>[-<<<<<<<->>>>>>+>[-<<<<<<<+>>>>>>>[-<<<<<<<->>>>>>+>[-<<<<<<<+>>>>>>>[-<<<<<<<->>>>>>+>[-<<<<<<<+>>>>>>>[-<<<<<<<->>>>>>+>[-<<<<<<<+>>>>>>>]]]]]]]]]<<<<<<<[->>>>>>>+<<<<<<<]-<<<<<<<<<<]>>>>>>>[-<<<<<<<<<<<+>>>>>>>>>>>]>>>[>>>>>>>[-<<<<<<<<<<<+++++>>>>>>>>>>>]>>>]<<<<<<<<<<[+>>>>>>>>[-<<<<<<<<+>>>>>>>>[-<<<<<<<<->>>>>+>>>[-<<<<<<<<+>>>>>>>>[-<<<<<<<<->>>>>+>>>[-<<<<<<<<+>>>>>>>>[-<<<<<<<<->>>>>+>>>[-<<<<<<<<+>>>>>>>>[-<<<<<<<<->>>>>+>>>[-<<<<<<<<+>>>>>>>>]]]]]]]]]<<<<<<<<[->>>>>>>>+<<<<<<<<]-<<<<<<<<<<]>>>>>>>>[-<<<<<<<<<<<<<+>>>>>>>>>>>>>]>>[>>>>>>>>[-<<<<<<<<<<<<<+++++>>>>>>>>>>>>>]>>]<<<<<<<<<<[<<<<<<<<<<]>>>>>>>>>>>>>>>>]<<<<<<[>>>[->>>>+>+<<<<<]>>>>>>>]<<<<<<<<<<[>>>>>>>[-<<<<+>>>>]<<<<<[->>>>>+>>+<<<<<<<]<<<<<<<<<<<<]>>>>>>>>>>[>>>>>>>[-<<<<<+>>>>>]>>>]<<<<<<<<<<[>>>>>>>>>[-<->]<[<<<<<<<<[<<[-]>>>>>>>>>>[-<<<<<<<<<<+>>>>>>>>>>]<<<<<<<<<<<<<<<<<<]>>>>>>>>>>>>>>>>>>]<<<<<<<<<<<<<<<<<<]>>>>>>>>[>-<[+[+[+[+[+[+[+[+[+[[-]>+<]]]]]]]]]]]>+[[-]<[-]+>>>>+>>>>>>>>[>>>>>>>>>>]<<<<<<<<<<[<<<<<<[<<<<[<<<<<<<<<<]>>>>+<<<<<<<<<<]<<<<]>>>>>>>>>>>>>>>>>>>>[>>>>>>>>>>]<<<<<<<<<<[<<<<<<<<<<]>>>>-[[+]>>>>>>>>-<<[>[-]>>[-<<+>>]>>>>>>>]<<<<<<<<<<[+>>[>>>>>>>>+>>]<<-<<<<<<<<<<]-[>>++++++++++++++++++++++++++++++++++++++++++++++++.------------------------------------------------<<<<<<<<<<<<]++++++++++++++++++++++++++++++++.[-]>>>>]>>>>>>[>>[->>>>>+<<<<<[->>>>>+<<<<<[->>>>>+<<<<<[->>>>>+<<<<<[->>>>>+<<<<<[->>>>>+<<<<<[->>>>>+<<<<<[->>>>>+<<<<<[->>>>>+<<<<<[->>>>>--------->>>>>+<<<<<<<<<<[->>>>>+<<<<<]]]]]]]]]]]>>>>>>>>]<<<<<<<<<<[>>>>>>>[-<<<<<+>>>>>]<<<<<<<<<<<<<<<<<]>>>>>>>>>]<]>>[>>>>>>>>>>]<<<<<<<<<<[+>[>>>>>>>>>+>]<-<<<<<<<<<<]-[>++++++++++++++++++++++++++++++++++++++++++++++++.<<<<<<<<<<<]++++++++++." & nul
-- [8] Prevod binarniho cisla na ASCII (ocekava na klavesnici zadane 8-bitove binarni cisla, tj. obsahujici znaky 0 / 1)
-- INIT => ">,[>>>++++++++[<[<++>-]<+[>+<-]<-[-[-<]>]>[-<]<,>>>-]<.[-]<<]"
)
port map (
CLK => CLK,
EN => rom_en,
ADDR => rom_addr,
DATA => rom_dout
);
-- ================================================
-- Pamet dat
-- ================================================
ram_mem: entity work.ram
port map(
CLK => CLK,
-- RAM
ADDR => ram_addr,
RDATA => ram_rdata,
WDATA => ram_wdata,
EN => ram_en,
RDWR => ram_rdwr
);
-- ================================================
-- Radic LCD displeje
-- ================================================
lcd_u : entity work.lcd_controller
generic map (
-- pragma translate off
-- Pouze pro ucely simulace se zkrati trvani prikazu zapisu na displej.
-- Pri synteze se pouzije vychozi hodnota nastavena v radici.
CMDLEN => 1000,
-- pragma translate on
-- Pro FITkit s dvouradkovym displejem nastavit na True, jinak False
-- Pro ucely simulace je tato promenna ignorovana, nebot simulacni model je napsan pouze pro jednoradkovy displej
LCD2x16 => True
)
port map(
CLK => CLK,
RST => cpu_rst,
-- user interface
DATA_IN => lcd_data,
WRITE_EN => lcd_we,
BUSY => lcd_busy,
-- lcd interface
DISPLAY_RS => LRS,
DISPLAY_RW => LRW,
DISPLAY_EN => LE,
DISPLAY_DATA => LD
);
-- ================================================
-- Radic klavesnice
-- ================================================
kb_u : entity work.kb_controller
port map(
CLK => CLK,
RST => RESET,
-- user interface
DATA => in_data,
DATA_VLD => in_vld,
DATA_REQ => in_req,
REQ_ACK => kb_ack,
-- lcd interface
KB_IN => KIN,
KB_OUT => KOUT
);
--pokud se ceka na stisk tlacitka, rozsvitit diodu D4
LEDF <= not kb_ack;
-- ================================================
-- Osetreni nulovani a povoleni cinnosti
-- ================================================
-- Protoze pamet nelze inicializovat na nuly,
-- nesmime dovolit vicenasobny reset procesoru
process (RESET, CLK)
begin
if (RESET = '1') then
timer <= 0;
elsif (CLK'event) and (CLK = '1') then
if (timer = 20000) then -- po cca 1ms po resetu povolime cinnost CPU
cpu_en <= '1';
else
timer <= timer + 1;
end if;
end if;
end process;
cpu_rst <= RESET when cpu_en = '0' else
'0';
end main;
| apache-2.0 | 7b381a31ebe53bfe32e3da19a4b70a9d | 0.309786 | 3.882371 | false | false | false | false |
rpereira-dev/ENSIIE | UE/S3/microarchi/tp2/tp2.vhd | 1 | 1,090 | -- includes
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
-- prototypage
ENTITY tp2 IS
PORT (
e : IN STD_LOGIC_VECTOR (3 downto 0) ; -- 2^4 = 16, codes les entiers de 0 à 9
s : OUT STD_LOGIC_VECTOR (6 downto 0) ; -- 1 bit par segment (abcdefg)_2, bit de poids faible 'à droite'
err : OUT STD_LOGIC
);
END tp2;
-- architecture
ARCHITECTURE arch OF tp2 IS
BEGIN
WITH e SELECT s <=
"0000001" WHEN "0000", -- 0 => abcdef-
"1001111" WHEN "0001", -- 1 => -bc----
"0010010" WHEN "0010",
"0000110" WHEN "0011",
"1001100" WHEN "0100",
"0100100" WHEN "0101",
"0100000" WHEN "0110",
"0001101" WHEN "0111",
"0000000" WHEN "1000",
"0000100" WHEN "1001",
"0110000" WHEN OTHERS -- >= 10 => affiches 'E'
;
WITH e SELECT err <=
'0' WHEN "0000", -- diode eteinte
'0' WHEN "0001", -- diode eteinte
'0' WHEN "0010",
'0' WHEN "0011",
'0' WHEN "0100",
'0' WHEN "0101",
'0' WHEN "0110",
'0' WHEN "0111",
'0' WHEN "1000",
'0' WHEN "1001",
'1' WHEN OTHERS -- diode allumée (>= 10)
;
END arch ; | gpl-3.0 | babd5ec5eb7a1d0e87690c5241264b1b | 0.576817 | 2.690594 | false | false | false | false |
peladex/RHD2132_FPGA | src/interconnect/interconnect.vhd | 1 | 2,578 | -----------------------------------------------------------------------------------------------------------------------
-- Author:
--
-- Create Date: 09/11/2016 -- dd/mm/yyyy
-- Module Name: interconnect
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- ...
--
-----------------------------------------------------------------------------------------------------------------------
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
LIBRARY lpm;
USE lpm.lpm_components.ALL;
ENTITY interconnect IS
PORT(
---- master_control interface ----
di_1_i : in std_logic_vector(15 downto 0);
do_1_o : out std_logic_vector(15 downto 0);
wren_1_i : in std_logic; --triggers spi cycle
drdy_1_o : out std_logic;
rdreq_1_i : in std_logic;
di_2_i : in std_logic_vector(15 downto 0);
do_2_o : out std_logic_vector(15 downto 0);
wren_2_i : in std_logic; --triggers spi cycle
drdy_2_o : out std_logic;
rdreq_2_i : in std_logic;
---- spi 1 interface ----
s1_do_o : out std_logic_vector(15 downto 0);
s1_di_i : in std_logic_vector(15 downto 0);
s1_wren_o : out std_logic;
s1_drdy_i : in std_logic;
---- spi 2 interface ----
s2_do_o : out std_logic_vector(15 downto 0);
s2_di_i : in std_logic_vector(15 downto 0);
s2_wren_o : out std_logic;
s2_drdy_i : in std_logic;
---- fifo 1 interface ----
f1_do_o : out std_logic_vector(15 downto 0);
f1_wren_o : out std_logic;
---- fifo 2 interface ----
f2_do_o : out std_logic_vector(15 downto 0);
f2_wren_o : out std_logic
);
END interconnect;
ARCHITECTURE behav OF interconnect IS
BEGIN
-- If rdreq_1_o is high data is feed to the master control, if it is low
-- data is stored in the corresponding fifo.
switch_data_1: process(rdreq_1_i, s1_di_i, s1_drdy_i)
begin
if rdreq_1_i = '1' then
do_1_o <= s1_di_i;
f1_do_o <= X"0000";
f1_wren_o <= '0';
else
do_1_o <= X"0000";
f1_do_o <= s1_di_i;
f1_wren_o <= s1_drdy_i;
end if;
end process;
switch_data_2: process(rdreq_2_i, s2_di_i, s2_drdy_i)
begin
if rdreq_2_i = '1' then
do_2_o <= s2_di_i;
f2_do_o <= X"0000";
f2_wren_o <= '0';
else
do_2_o <= X"0000";
f2_do_o <= s2_di_i;
f2_wren_o <= s2_drdy_i;
end if;
end process;
-- fixed signals
drdy_1_o <= s1_drdy_i;
drdy_2_o <= s2_drdy_i;
s1_do_o <= di_1_i;
s1_wren_o <= wren_1_i;
s2_do_o <= di_2_i;
s2_wren_o <= wren_2_i;
END behav; | gpl-3.0 | 5d84a3f70afdf1adc449d1ce96e53963 | 0.525213 | 2.585757 | false | false | false | false |
boztalay/OldProjects | FPGA/Key_test/Keyboard.vhd | 1 | 2,610 | ----------------------------------------------------------------------------------
--Ben Oztalay, 2009-2010
--
--Module Title: Keyboard
--Module Description:
-- This is a simple module that eases the interface with a keyboard. It takes the
-- PS/2 bus clock and data pins as inputs, as well as an acknowledgment signal. The
-- outputs are the 8-bit scan code and a signal that tells the host device that
-- the scan code is ready. Every 11 clock cycles, when the entire packet has been sent,
-- the code_ready output is driven high, and stays high until the acknowledgement
-- input is raised to '1'. It doesn't take scan codes while the code_ready output
-- is high.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Keyboard is
Port ( key_clock : in STD_LOGIC;
key_data : in STD_LOGIC;
acknowledge : in STD_LOGIC;
scan_code : out STD_LOGIC_VECTOR (7 to 0);
code_ready : out STD_LOGIC);
end Keyboard;
architecture Behavioral of Keyboard is
--//Components\\--
component Gen_Shift_Reg_Falling is
generic (size : integer);
Port ( clock : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
data_in : in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR ((size-1) downto 0));
end component;
--\\Components//--
--//Signals\\--
signal code_ready_sig : STD_LOGIC;
signal enable : STD_LOGIC;
signal reg_out : STD_LOGIC_VECTOR(10 downto 0);
--\\Signals//--
begin
count_chk : process (key_clock, acknowledge, enable) is
variable count : integer := 0;
variable ready : STD_LOGIC := '0';
begin
if enable = '1' then
if falling_edge(key_clock) then
count := count + 1;
if count = 11 then
count := 0;
ready := '1';
end if;
end if;
end if;
if (ready = '1') and (acknowledge = '1') then
ready := '0';
end if;
code_ready_sig <= ready;
end process;
shift_reg : Gen_Shift_Reg_Falling generic map (size => 11)
port map (clock => key_clock,
enable => enable,
reset => '0',
data_in => key_data,
data_out => reg_out);
enable <= (not (key_clock and code_ready_sig));
code_ready <= code_ready_sig;
scan_code <= regout(2) & regout(3) & regout(4) & regout(5) & regout(6) & regout(7) & regout(8) & regout(9);
end Behavioral;
| mit | 011dd68d4491c07b1856a7fd19fe8ace | 0.555939 | 3.609959 | false | false | false | false |
AfterRace/SoC_Project | vivado/project/project.srcs/sources_1/ipshared/user.org/zed_audio_v1_0/8de2dafc/hdl/i2c.vhd | 2 | 2,657 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Description: A controller to send I2C commands to the ADAU1761 codec
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity i2c is
Port ( clk : in STD_LOGIC;
i2c_sda_i : IN std_logic;
i2c_sda_o : OUT std_logic;
i2c_sda_t : OUT std_logic;
i2c_scl : out STD_LOGIC;
sw : in std_logic_vector(1 downto 0);
active : out std_logic_vector(1 downto 0));
end i2c;
architecture Behavioral of i2c is
COMPONENT i3c2
Generic( clk_divide : STD_LOGIC_VECTOR (7 downto 0));
PORT(
clk : IN std_logic;
i2c_sda_i : IN std_logic;
i2c_sda_o : OUT std_logic;
i2c_sda_t : OUT std_logic;
i2c_scl : OUT std_logic;
inst_data : IN std_logic_vector(8 downto 0);
inputs : IN std_logic_vector(15 downto 0);
inst_address : OUT std_logic_vector(9 downto 0);
debug_sda : OUT std_logic;
debug_scl : OUT std_logic;
outputs : OUT std_logic_vector(15 downto 0);
reg_addr : OUT std_logic_vector(4 downto 0);
reg_data : OUT std_logic_vector(7 downto 0);
reg_write : OUT std_logic;
error : OUT std_logic
);
END COMPONENT;
COMPONENT adau1761_configuraiton_data
PORT(
clk : IN std_logic;
address : IN std_logic_vector(9 downto 0);
data : OUT std_logic_vector(8 downto 0)
);
END COMPONENT;
signal inst_address : std_logic_vector(9 downto 0);
signal inst_data : std_logic_vector(8 downto 0);
signal sw_full :std_logic_vector(15 downto 0) := (others => '0');
signal active_full : std_logic_vector(15 downto 0) := (others => '0');
begin
sw_full(1 downto 0) <= sw;
active <= active_full(1 downto 0);
Inst_adau1761_configuraiton_data: adau1761_configuraiton_data PORT MAP(
clk => clk,
address => inst_address,
data => inst_data
);
Inst_i3c2: i3c2 GENERIC MAP (
clk_divide => "01111000" -- 120 (48,000/120 = 400kHz I2C clock)
) PORT MAP(
clk => clk,
inst_address => inst_address,
inst_data => inst_data,
i2c_scl => i2c_scl,
i2c_sda_i => i2c_sda_i,
i2c_sda_o => i2c_sda_o,
i2c_sda_t => i2c_sda_t,
inputs => sw_full,
outputs => active_full,
reg_addr => open,
reg_data => open,
reg_write => open,
debug_scl => open,
debug_sda => open,
error => open
);
end Behavioral; | lgpl-3.0 | 45245bf724124e19a0c63c4c1bdb7372 | 0.541212 | 3.078795 | false | false | false | false |
AfterRace/SoC_Project | vivado/project/project.srcs/sources_1/ipshared/user.org/axi_to_audio_v1_0/6d2e43c7/hdl/AXI_to_audio_v1_0_S00_AXI.vhd | 2 | 16,181 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AXI_to_audio_v1_0_S00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
-- Users to add ports here
audio_out_l : out std_logic_vector(23 downto 0);
audio_out_r : out std_logic_vector(23 downto 0);
audio_out_valid : out std_logic;
audio_in_valid_irq : in std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end AXI_to_audio_v1_0_S00_AXI;
architecture arch_imp of AXI_to_audio_v1_0_S00_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 1;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 4
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
-- Declaration of user logic
component audio_bridge
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
audio_in_l : in STD_LOGIC_VECTOR (23 downto 0);
audio_in_r : in STD_LOGIC_VECTOR (23 downto 0);
audio_in_valid : in STD_LOGIC;
audio_out_l : out STD_LOGIC_VECTOR (23 downto 0);
audio_out_r : out STD_LOGIC_VECTOR (23 downto 0);
audio_out_valid : out STD_LOGIC);
end component audio_bridge;
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"00" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"11" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"00" =>
reg_data_out <= slv_reg0;
when b"01" =>
reg_data_out <= slv_reg1;
when b"10" =>
reg_data_out <= slv_reg2;
when b"11" =>
reg_data_out <= slv_reg3;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
-- Add user logic here
audio_bridge_0 : audio_bridge
port map(
audio_out_valid => audio_out_valid,
audio_out_l => audio_out_l,
audio_out_r => audio_out_r,
audio_in_valid => audio_in_valid_irq,
audio_in_l => slv_reg0(23 downto 0),
audio_in_r => slv_reg1(23 downto 0),
rst => S_AXI_ARESETN,
clk => S_AXI_ACLK
);
-- User logic ends
end arch_imp;
| lgpl-3.0 | a9eaaf5176c12d6c1fe6201b40eef6da | 0.609604 | 3.45674 | false | false | false | false |
DaveyPocket/btrace448 | btrace/raygen_TB.vhd | 1 | 1,200 | -- Btrace 448
-- Ray Generator - Test Bench
--
-- Bradley Boccuzzi
-- 2016
-- !Remove from project
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity raygen_TB is
end raygen_TB;
architecture arch of raygen_TB is
constant clkPd: time := 20 ns;
constant int, fraction: integer := 16;
signal clk, rst: std_logic := '0';
signal set_cam: std_logic := '0';
signal inc_x, inc_y: std_logic := '0';
signal clr_x, clr_y: std_logic := '0';
signal mv_x, mv_y, mv_z: std_logic_vector((int+fraction)-1 downto 0);
begin
uut: entity work.raygen generic map(int, fraction) port map(clk, rst, set_cam, inc_x, inc_y, clr_x, clr_y, mv_x, mv_y, mv_z);
clkProc: process
begin
wait for clkPd/2;
clk <= '1';
wait for clkPd/2;
clk <= '0';
end process clkProc;
mainTB: process
begin
wait for clkPd/3;
rst <= '1';
wait for clkPd/2;
rst <= '0';
wait for clkPd/2;
rst <= '0';
set_cam <= '1';
wait for clkPd;
set_cam <= '0';
for i in 0 to 3 loop
inc_x <= '1';
wait for clkPd;
inc_x <= '0';
wait for clkPd;
end loop;
inc_y <= '1';
clr_x <= '1';
wait for clkPd;
inc_y <= '0';
clr_x <= '0';
wait;
end process mainTB;
end arch;
| gpl-3.0 | 1de515193b7f4747db2dbf30fd34bb6d | 0.610833 | 2.505219 | false | false | false | false |
DaveyPocket/btrace448 | btrace/object_reg.vhd | 1 | 690 | -- Btrace 448
-- Object Register
--
-- Bradley Boccuzzi
-- 2016
library ieee;
library ieee_proposed;
use ieee.std_logic_1164.all;
use ieee_proposed.fixed_pkg.all;
use work.btrace_pack.all;
entity object_reg is
port(clk, rst, en: in std_logic;
Din: in object;
Dout: out object);
end object_reg;
architecture arch of object_reg is
constant zero_point: point := ((others => '0'), (others => '0'), (others => '0'));
constant zero_object: object := (zero_point, (others => '0'), (others => '0'));
begin
process(clk, rst)
begin
if rst = '1' then
Dout <= zero_object;
elsif rising_edge(clk) then
if en = '1' then
Dout <= Din;
end if;
end if;
end process;
end arch;
| gpl-3.0 | 2564773a3a29fcc64c8e4dcaf94b8a07 | 0.646377 | 2.875 | false | false | false | false |
freecores/line_codes | bench/vhdl/smlt_ami_enc.vhd | 1 | 912 |
-- smlttion for AMI encoder.
entity smlt_ami_enc is
end smlt_ami_enc;
architecture behaviour of smlt_ami_enc is
--data type:
component ami_enc
port (
clr_bar,
clk : in bit;
e : in bit;
s0, s1: out bit);
end component;
--binding:
for a: ami_enc use entity work.ami_enc;
--declaring the signals present in this architecture:
signal CLK, E, S0, S1, clrb: bit;
signal inpute: bit_vector(0 to 26);
begin --architecture.
a: ami_enc port map
( clr_bar => clrb, clk => CLK, e => E, s0 => S0,
s1 => S1 );
inpute <= "000101011000101100101000111";
process begin
clrb <= '1';
for i in 0 to 26 loop
E <= inpute(i);
CLK <= '0';
wait for 9 ns;
CLK <= '1';
wait for 1 ns;
end loop;
wait;
end process;
end behaviour;
| gpl-2.0 | 351a1760199f81e419e30cec24b21372 | 0.519737 | 3.188811 | false | false | false | false |
fkolacek/FIT-VUT | INP2/fpga/sim/tb.vhd | 1 | 3,382 | -- tb.vhd : FPGA top level testbench
-- Copyright (C) 2011 Brno University of Technology,
-- Faculty of Information Technology
-- Author(s): Zdenek Vasicek <vasicek AT fit.vutbr.cz>
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use ieee.numeric_std.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity testbench is
end entity testbench;
-- ----------------------------------------------------------------------------
-- Architecture declaration
-- ----------------------------------------------------------------------------
architecture behavioral of testbench is
signal smclk : std_logic := '1';
signal ledf : std_logic;
signal p3m : std_logic_vector(7 downto 0) := (others=>'Z');
signal afbus : std_logic_vector(11 downto 0) :=(others =>'Z');
signal xbus : std_logic_vector(45 downto 0) :=(others =>'Z');
signal rdbus : std_logic_vector(7 downto 0) :=(others =>'Z');
signal ldbus : std_logic_vector(7 downto 0) :=(others =>'Z');
signal lrs, lrw, le : std_logic;
signal ispi_clk : std_logic:='1';
signal ispi_cs : std_logic:='1';
signal ispi_di : std_logic:='0';
signal ispi_do : std_logic:='0';
begin
-- ==========================================
-- Top-level entita reprezentujici cele FPGA
-- ==========================================
uut: entity work.fpga
port map(
SMCLK => smclk,
ACLK => '0',
FCLK => '0',
LEDF => ledf,
SPI_CLK => ispi_clk,
SPI_CS => '1',
SPI_FPGA_CS => ispi_cs,
SPI_DI => ispi_di,
SPI_DO => ispi_do,
KIN => open,
KOUT => (others => '0'),
LE => le,
LRW => lrw,
LRS => lrs,
LD => ldbus,
RA => open,
RD => rdbus,
RDQM => open,
RCS => open,
RRAS => open,
RCAS => open,
RWE => open,
RCKE => open,
RCLK => open,
P3M => p3m,
AFBUS => afbus,
X => xbus
);
-- ==========================================
-- LCD display model
-- ==========================================
lcd: entity work.lcd
port map(
LRS => lrs,
LRW => lrw,
LE => le,
LD => ldbus
);
-- ==========================================================================
-- Clock generator 7.4MHz
-- ==========================================================================
smclk <= not smclk after 67.5 ns;
-- ==========================================================================
-- Reset generator
-- ==========================================================================
p3m(0) <= '1', '0' after 500 ns;
-- ==========================================================================
-- SPI clock generator (SMCLK/4)
-- ==========================================================================
ispi_clk <= not ispi_clk after 4*67.5 ns;
end architecture behavioral;
| apache-2.0 | c035c75f618c8bbb6119348ebdded974 | 0.355411 | 4.684211 | false | false | false | false |
peladex/RHD2132_FPGA | quartus/test_spi_comm/test_spi_slaves.vhd | 1 | 5,242 | -----------------------------------------------------------------------------------------------------------------------
-- Author:
--
-- Create Date: 09/11/2016 -- dd/mm/yyyy
-- Module Name: test_spi_slaves
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Este bloque instancia dos bloques spi escalvos tal que la salida de datos de uno esta conectada a la entrada
-- de datos del otro. Lo mismo sucede con la salida que indica un dato valido y la entrada write enable. Por lo tanto,
-- si un bloque recibe un dato, en el proximo ciclo spi ese dato sera enviado por el otro bloque spi.
--
-----------------------------------------------------------------------------------------------------------------------
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
LIBRARY lpm;
USE lpm.lpm_components.ALL;
ENTITY test_spi_slaves IS
PORT(
m_clk : in std_logic; -- master clock
m_reset : in std_logic; -- master reset
---- serial interface 1 ----
slave1_ssel_i : in std_logic := 'X'; -- spi bus slave select line
slave1_sck_i : in std_logic := 'X'; -- spi bus sck
slave1_mosi_i : in std_logic := 'X'; -- spi bus mosi output
slave1_miso_o : out std_logic := 'X'; -- spi bus spi_miso_i input
---- serial interface 2 ----
slave2_ssel_i : in std_logic := 'X'; -- spi bus slave select line
slave2_sck_i : in std_logic := 'X'; -- spi bus sck
slave2_mosi_i : in std_logic := 'X'; -- spi bus mosi output
slave2_miso_o : out std_logic := 'X' -- spi bus spi_miso_i input
);
END test_spi_slaves;
ARCHITECTURE synth OF test_spi_slaves IS
---- COMPONENTS
COMPONENT spi_slave IS
Generic (
N : positive := 16; -- 32bit serial word length is default
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
CPHA : std_logic := '0'; -- CPOL = clock polarity, CPHA = clock phase.
PREFETCH : positive := 2); -- prefetch lookahead cycles
Port (
clk_i : in std_logic := 'X'; -- internal interface clock (clocks di/do registers)
spi_ssel_i : in std_logic := 'X'; -- spi bus slave select line
spi_sck_i : in std_logic := 'X'; -- spi bus sck clock (clocks the shift register core)
spi_mosi_i : in std_logic := 'X'; -- spi bus mosi input
spi_miso_o : out std_logic := 'X'; -- spi bus spi_miso_o output
di_req_o : out std_logic; -- preload lookahead data request line
di_i : in std_logic_vector (N-1 downto 0) := (others => 'X'); -- parallel load data in (clocked in on rising edge of clk_i)
wren_i : in std_logic := 'X'; -- user data write enable
wr_ack_o : out std_logic; -- write acknowledge
do_valid_o : out std_logic; -- do_o data valid strobe, valid during one clk_i rising edge.
do_o : out std_logic_vector (N-1 downto 0); -- parallel output (clocked out on falling clk_i)
--- debug ports: can be removed for the application circuit ---
do_transfer_o : out std_logic; -- debug: internal transfer driver
wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher
rx_bit_next_o : out std_logic; -- debug: internal rx bit
state_dbg_o : out std_logic_vector (3 downto 0); -- debug: internal state register
sh_reg_dbg_o : out std_logic_vector (N-1 downto 0) -- debug: internal shift register
);
END COMPONENT;
---- SIGNALS
SIGNAL sg_slave1_di, sg_slave2_di : std_logic_vector(15 downto 0);
SIGNAL sg_slave1_wren, sg_slave2_wren : std_logic;
BEGIN
---- INSTANCES
SLAVE_1: spi_slave PORT MAP (
clk_i => m_clk,
spi_ssel_i => slave1_ssel_i,
spi_sck_i => slave1_sck_i,
spi_mosi_i => slave1_mosi_i,
spi_miso_o => slave1_miso_o,
di_i => sg_slave1_di,
wren_i => sg_slave1_wren,
do_valid_o => sg_slave2_wren,
do_o => sg_slave2_di
);
SLAVE_2: spi_slave PORT MAP (
clk_i => m_clk,
spi_ssel_i => slave2_ssel_i,
spi_sck_i => slave2_sck_i,
spi_mosi_i => slave2_mosi_i,
spi_miso_o => slave2_miso_o,
di_i => sg_slave2_di,
wren_i => sg_slave2_wren,
do_valid_o => sg_slave1_wren,
do_o => sg_slave1_di
);
END synth; | gpl-3.0 | 544b7db8847c73b2f85c1bd28c13d4fe | 0.471385 | 3.977238 | false | false | false | false |
AfterRace/SoC_Project | vivado/project/project.srcs/sources_1/bd/week1/hdl/week1.vhd | 1 | 225,972 | --Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.1 (lin64) Build 1215546 Mon Apr 27 19:07:21 MDT 2015
--Date : Thu May 12 11:41:56 2016
--Host : fx6 running 64-bit openSUSE Leap 42.1 (x86_64)
--Command : generate_target week1.bd
--Design : week1
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_QJRQ3J is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m00_couplers_imp_QJRQ3J;
architecture STRUCTURE of m00_couplers_imp_QJRQ3J is
signal m00_couplers_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(3 downto 0) <= m00_couplers_to_m00_couplers_ARADDR(3 downto 0);
M_AXI_arprot(2 downto 0) <= m00_couplers_to_m00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid(0) <= m00_couplers_to_m00_couplers_ARVALID(0);
M_AXI_awaddr(3 downto 0) <= m00_couplers_to_m00_couplers_AWADDR(3 downto 0);
M_AXI_awprot(2 downto 0) <= m00_couplers_to_m00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid(0) <= m00_couplers_to_m00_couplers_AWVALID(0);
M_AXI_bready(0) <= m00_couplers_to_m00_couplers_BREADY(0);
M_AXI_rready(0) <= m00_couplers_to_m00_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m00_couplers_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m00_couplers_to_m00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m00_couplers_to_m00_couplers_WVALID(0);
S_AXI_arready(0) <= m00_couplers_to_m00_couplers_ARREADY(0);
S_AXI_awready(0) <= m00_couplers_to_m00_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m00_couplers_to_m00_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m00_couplers_to_m00_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m00_couplers_to_m00_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m00_couplers_to_m00_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m00_couplers_to_m00_couplers_RVALID(0);
S_AXI_wready(0) <= m00_couplers_to_m00_couplers_WREADY(0);
m00_couplers_to_m00_couplers_ARADDR(3 downto 0) <= S_AXI_araddr(3 downto 0);
m00_couplers_to_m00_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m00_couplers_to_m00_couplers_ARREADY(0) <= M_AXI_arready(0);
m00_couplers_to_m00_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m00_couplers_to_m00_couplers_AWADDR(3 downto 0) <= S_AXI_awaddr(3 downto 0);
m00_couplers_to_m00_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m00_couplers_to_m00_couplers_AWREADY(0) <= M_AXI_awready(0);
m00_couplers_to_m00_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m00_couplers_to_m00_couplers_BREADY(0) <= S_AXI_bready(0);
m00_couplers_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m00_couplers_to_m00_couplers_BVALID(0) <= M_AXI_bvalid(0);
m00_couplers_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m00_couplers_to_m00_couplers_RREADY(0) <= S_AXI_rready(0);
m00_couplers_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m00_couplers_to_m00_couplers_RVALID(0) <= M_AXI_rvalid(0);
m00_couplers_to_m00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_m00_couplers_WREADY(0) <= M_AXI_wready(0);
m00_couplers_to_m00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m00_couplers_to_m00_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m01_couplers_imp_1RWPDFB is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m01_couplers_imp_1RWPDFB;
architecture STRUCTURE of m01_couplers_imp_1RWPDFB is
signal m01_couplers_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_m01_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_m01_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(3 downto 0) <= m01_couplers_to_m01_couplers_ARADDR(3 downto 0);
M_AXI_arprot(2 downto 0) <= m01_couplers_to_m01_couplers_ARPROT(2 downto 0);
M_AXI_arvalid(0) <= m01_couplers_to_m01_couplers_ARVALID(0);
M_AXI_awaddr(3 downto 0) <= m01_couplers_to_m01_couplers_AWADDR(3 downto 0);
M_AXI_awprot(2 downto 0) <= m01_couplers_to_m01_couplers_AWPROT(2 downto 0);
M_AXI_awvalid(0) <= m01_couplers_to_m01_couplers_AWVALID(0);
M_AXI_bready(0) <= m01_couplers_to_m01_couplers_BREADY(0);
M_AXI_rready(0) <= m01_couplers_to_m01_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m01_couplers_to_m01_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m01_couplers_to_m01_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m01_couplers_to_m01_couplers_WVALID(0);
S_AXI_arready(0) <= m01_couplers_to_m01_couplers_ARREADY(0);
S_AXI_awready(0) <= m01_couplers_to_m01_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m01_couplers_to_m01_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m01_couplers_to_m01_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m01_couplers_to_m01_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m01_couplers_to_m01_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m01_couplers_to_m01_couplers_RVALID(0);
S_AXI_wready(0) <= m01_couplers_to_m01_couplers_WREADY(0);
m01_couplers_to_m01_couplers_ARADDR(3 downto 0) <= S_AXI_araddr(3 downto 0);
m01_couplers_to_m01_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m01_couplers_to_m01_couplers_ARREADY(0) <= M_AXI_arready(0);
m01_couplers_to_m01_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m01_couplers_to_m01_couplers_AWADDR(3 downto 0) <= S_AXI_awaddr(3 downto 0);
m01_couplers_to_m01_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m01_couplers_to_m01_couplers_AWREADY(0) <= M_AXI_awready(0);
m01_couplers_to_m01_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m01_couplers_to_m01_couplers_BREADY(0) <= S_AXI_bready(0);
m01_couplers_to_m01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m01_couplers_to_m01_couplers_BVALID(0) <= M_AXI_bvalid(0);
m01_couplers_to_m01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m01_couplers_to_m01_couplers_RREADY(0) <= S_AXI_rready(0);
m01_couplers_to_m01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m01_couplers_to_m01_couplers_RVALID(0) <= M_AXI_rvalid(0);
m01_couplers_to_m01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m01_couplers_to_m01_couplers_WREADY(0) <= M_AXI_wready(0);
m01_couplers_to_m01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m01_couplers_to_m01_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m02_couplers_imp_1WKUKB2 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m02_couplers_imp_1WKUKB2;
architecture STRUCTURE of m02_couplers_imp_1WKUKB2 is
signal m02_couplers_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_m02_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m02_couplers_to_m02_couplers_ARREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_ARVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_m02_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m02_couplers_to_m02_couplers_AWREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_AWVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_BREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_BVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_RREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_RVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_WREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_m02_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(3 downto 0) <= m02_couplers_to_m02_couplers_ARADDR(3 downto 0);
M_AXI_arprot(2 downto 0) <= m02_couplers_to_m02_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= m02_couplers_to_m02_couplers_ARVALID;
M_AXI_awaddr(3 downto 0) <= m02_couplers_to_m02_couplers_AWADDR(3 downto 0);
M_AXI_awprot(2 downto 0) <= m02_couplers_to_m02_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= m02_couplers_to_m02_couplers_AWVALID;
M_AXI_bready <= m02_couplers_to_m02_couplers_BREADY;
M_AXI_rready <= m02_couplers_to_m02_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m02_couplers_to_m02_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m02_couplers_to_m02_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m02_couplers_to_m02_couplers_WVALID;
S_AXI_arready <= m02_couplers_to_m02_couplers_ARREADY;
S_AXI_awready <= m02_couplers_to_m02_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m02_couplers_to_m02_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m02_couplers_to_m02_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m02_couplers_to_m02_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m02_couplers_to_m02_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m02_couplers_to_m02_couplers_RVALID;
S_AXI_wready <= m02_couplers_to_m02_couplers_WREADY;
m02_couplers_to_m02_couplers_ARADDR(3 downto 0) <= S_AXI_araddr(3 downto 0);
m02_couplers_to_m02_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m02_couplers_to_m02_couplers_ARREADY <= M_AXI_arready;
m02_couplers_to_m02_couplers_ARVALID <= S_AXI_arvalid;
m02_couplers_to_m02_couplers_AWADDR(3 downto 0) <= S_AXI_awaddr(3 downto 0);
m02_couplers_to_m02_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m02_couplers_to_m02_couplers_AWREADY <= M_AXI_awready;
m02_couplers_to_m02_couplers_AWVALID <= S_AXI_awvalid;
m02_couplers_to_m02_couplers_BREADY <= S_AXI_bready;
m02_couplers_to_m02_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m02_couplers_to_m02_couplers_BVALID <= M_AXI_bvalid;
m02_couplers_to_m02_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m02_couplers_to_m02_couplers_RREADY <= S_AXI_rready;
m02_couplers_to_m02_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m02_couplers_to_m02_couplers_RVALID <= M_AXI_rvalid;
m02_couplers_to_m02_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m02_couplers_to_m02_couplers_WREADY <= M_AXI_wready;
m02_couplers_to_m02_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m02_couplers_to_m02_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m03_couplers_imp_LVBNAE is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 6 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 6 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m03_couplers_imp_LVBNAE;
architecture STRUCTURE of m03_couplers_imp_LVBNAE is
signal m03_couplers_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 6 downto 0 );
signal m03_couplers_to_m03_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m03_couplers_to_m03_couplers_ARREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_ARVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 6 downto 0 );
signal m03_couplers_to_m03_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m03_couplers_to_m03_couplers_AWREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_AWVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_BREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_BVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_RREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_RVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_WREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_m03_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(6 downto 0) <= m03_couplers_to_m03_couplers_ARADDR(6 downto 0);
M_AXI_arprot(2 downto 0) <= m03_couplers_to_m03_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= m03_couplers_to_m03_couplers_ARVALID;
M_AXI_awaddr(6 downto 0) <= m03_couplers_to_m03_couplers_AWADDR(6 downto 0);
M_AXI_awprot(2 downto 0) <= m03_couplers_to_m03_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= m03_couplers_to_m03_couplers_AWVALID;
M_AXI_bready <= m03_couplers_to_m03_couplers_BREADY;
M_AXI_rready <= m03_couplers_to_m03_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m03_couplers_to_m03_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m03_couplers_to_m03_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m03_couplers_to_m03_couplers_WVALID;
S_AXI_arready <= m03_couplers_to_m03_couplers_ARREADY;
S_AXI_awready <= m03_couplers_to_m03_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m03_couplers_to_m03_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m03_couplers_to_m03_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m03_couplers_to_m03_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m03_couplers_to_m03_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m03_couplers_to_m03_couplers_RVALID;
S_AXI_wready <= m03_couplers_to_m03_couplers_WREADY;
m03_couplers_to_m03_couplers_ARADDR(6 downto 0) <= S_AXI_araddr(6 downto 0);
m03_couplers_to_m03_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m03_couplers_to_m03_couplers_ARREADY <= M_AXI_arready;
m03_couplers_to_m03_couplers_ARVALID <= S_AXI_arvalid;
m03_couplers_to_m03_couplers_AWADDR(6 downto 0) <= S_AXI_awaddr(6 downto 0);
m03_couplers_to_m03_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m03_couplers_to_m03_couplers_AWREADY <= M_AXI_awready;
m03_couplers_to_m03_couplers_AWVALID <= S_AXI_awvalid;
m03_couplers_to_m03_couplers_BREADY <= S_AXI_bready;
m03_couplers_to_m03_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m03_couplers_to_m03_couplers_BVALID <= M_AXI_bvalid;
m03_couplers_to_m03_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m03_couplers_to_m03_couplers_RREADY <= S_AXI_rready;
m03_couplers_to_m03_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m03_couplers_to_m03_couplers_RVALID <= M_AXI_rvalid;
m03_couplers_to_m03_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m03_couplers_to_m03_couplers_WREADY <= M_AXI_wready;
m03_couplers_to_m03_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m03_couplers_to_m03_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m04_couplers_imp_1NBU6D8 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m04_couplers_imp_1NBU6D8;
architecture STRUCTURE of m04_couplers_imp_1NBU6D8 is
signal m04_couplers_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_m04_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m04_couplers_to_m04_couplers_ARREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_ARVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_m04_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m04_couplers_to_m04_couplers_AWREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_AWVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_BREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_m04_couplers_BVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_RREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_m04_couplers_RVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_WREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_m04_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(3 downto 0) <= m04_couplers_to_m04_couplers_ARADDR(3 downto 0);
M_AXI_arprot(2 downto 0) <= m04_couplers_to_m04_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= m04_couplers_to_m04_couplers_ARVALID;
M_AXI_awaddr(3 downto 0) <= m04_couplers_to_m04_couplers_AWADDR(3 downto 0);
M_AXI_awprot(2 downto 0) <= m04_couplers_to_m04_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= m04_couplers_to_m04_couplers_AWVALID;
M_AXI_bready <= m04_couplers_to_m04_couplers_BREADY;
M_AXI_rready <= m04_couplers_to_m04_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m04_couplers_to_m04_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m04_couplers_to_m04_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m04_couplers_to_m04_couplers_WVALID;
S_AXI_arready <= m04_couplers_to_m04_couplers_ARREADY;
S_AXI_awready <= m04_couplers_to_m04_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m04_couplers_to_m04_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m04_couplers_to_m04_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m04_couplers_to_m04_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m04_couplers_to_m04_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m04_couplers_to_m04_couplers_RVALID;
S_AXI_wready <= m04_couplers_to_m04_couplers_WREADY;
m04_couplers_to_m04_couplers_ARADDR(3 downto 0) <= S_AXI_araddr(3 downto 0);
m04_couplers_to_m04_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m04_couplers_to_m04_couplers_ARREADY <= M_AXI_arready;
m04_couplers_to_m04_couplers_ARVALID <= S_AXI_arvalid;
m04_couplers_to_m04_couplers_AWADDR(3 downto 0) <= S_AXI_awaddr(3 downto 0);
m04_couplers_to_m04_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m04_couplers_to_m04_couplers_AWREADY <= M_AXI_awready;
m04_couplers_to_m04_couplers_AWVALID <= S_AXI_awvalid;
m04_couplers_to_m04_couplers_BREADY <= S_AXI_bready;
m04_couplers_to_m04_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m04_couplers_to_m04_couplers_BVALID <= M_AXI_bvalid;
m04_couplers_to_m04_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m04_couplers_to_m04_couplers_RREADY <= S_AXI_rready;
m04_couplers_to_m04_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m04_couplers_to_m04_couplers_RVALID <= M_AXI_rvalid;
m04_couplers_to_m04_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m04_couplers_to_m04_couplers_WREADY <= M_AXI_wready;
m04_couplers_to_m04_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m04_couplers_to_m04_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m05_couplers_imp_U0DM50 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 6 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 6 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m05_couplers_imp_U0DM50;
architecture STRUCTURE of m05_couplers_imp_U0DM50 is
signal m05_couplers_to_m05_couplers_ARADDR : STD_LOGIC_VECTOR ( 6 downto 0 );
signal m05_couplers_to_m05_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m05_couplers_to_m05_couplers_ARREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_ARVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_AWADDR : STD_LOGIC_VECTOR ( 6 downto 0 );
signal m05_couplers_to_m05_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m05_couplers_to_m05_couplers_AWREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_AWVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_BREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_m05_couplers_BVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_RREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_m05_couplers_RVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_WREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m05_couplers_to_m05_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(6 downto 0) <= m05_couplers_to_m05_couplers_ARADDR(6 downto 0);
M_AXI_arprot(2 downto 0) <= m05_couplers_to_m05_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= m05_couplers_to_m05_couplers_ARVALID;
M_AXI_awaddr(6 downto 0) <= m05_couplers_to_m05_couplers_AWADDR(6 downto 0);
M_AXI_awprot(2 downto 0) <= m05_couplers_to_m05_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= m05_couplers_to_m05_couplers_AWVALID;
M_AXI_bready <= m05_couplers_to_m05_couplers_BREADY;
M_AXI_rready <= m05_couplers_to_m05_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m05_couplers_to_m05_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m05_couplers_to_m05_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m05_couplers_to_m05_couplers_WVALID;
S_AXI_arready <= m05_couplers_to_m05_couplers_ARREADY;
S_AXI_awready <= m05_couplers_to_m05_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m05_couplers_to_m05_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m05_couplers_to_m05_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m05_couplers_to_m05_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m05_couplers_to_m05_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m05_couplers_to_m05_couplers_RVALID;
S_AXI_wready <= m05_couplers_to_m05_couplers_WREADY;
m05_couplers_to_m05_couplers_ARADDR(6 downto 0) <= S_AXI_araddr(6 downto 0);
m05_couplers_to_m05_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m05_couplers_to_m05_couplers_ARREADY <= M_AXI_arready;
m05_couplers_to_m05_couplers_ARVALID <= S_AXI_arvalid;
m05_couplers_to_m05_couplers_AWADDR(6 downto 0) <= S_AXI_awaddr(6 downto 0);
m05_couplers_to_m05_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m05_couplers_to_m05_couplers_AWREADY <= M_AXI_awready;
m05_couplers_to_m05_couplers_AWVALID <= S_AXI_awvalid;
m05_couplers_to_m05_couplers_BREADY <= S_AXI_bready;
m05_couplers_to_m05_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m05_couplers_to_m05_couplers_BVALID <= M_AXI_bvalid;
m05_couplers_to_m05_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m05_couplers_to_m05_couplers_RREADY <= S_AXI_rready;
m05_couplers_to_m05_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m05_couplers_to_m05_couplers_RVALID <= M_AXI_rvalid;
m05_couplers_to_m05_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m05_couplers_to_m05_couplers_WREADY <= M_AXI_wready;
m05_couplers_to_m05_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m05_couplers_to_m05_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m06_couplers_imp_YRXD0T is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m06_couplers_imp_YRXD0T;
architecture STRUCTURE of m06_couplers_imp_YRXD0T is
signal m06_couplers_to_m06_couplers_ARADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m06_couplers_to_m06_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m06_couplers_to_m06_couplers_ARREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_ARVALID : STD_LOGIC;
signal m06_couplers_to_m06_couplers_AWADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m06_couplers_to_m06_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m06_couplers_to_m06_couplers_AWREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_AWVALID : STD_LOGIC;
signal m06_couplers_to_m06_couplers_BREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_m06_couplers_BVALID : STD_LOGIC;
signal m06_couplers_to_m06_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_RREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_m06_couplers_RVALID : STD_LOGIC;
signal m06_couplers_to_m06_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_WREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m06_couplers_to_m06_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(3 downto 0) <= m06_couplers_to_m06_couplers_ARADDR(3 downto 0);
M_AXI_arprot(2 downto 0) <= m06_couplers_to_m06_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= m06_couplers_to_m06_couplers_ARVALID;
M_AXI_awaddr(3 downto 0) <= m06_couplers_to_m06_couplers_AWADDR(3 downto 0);
M_AXI_awprot(2 downto 0) <= m06_couplers_to_m06_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= m06_couplers_to_m06_couplers_AWVALID;
M_AXI_bready <= m06_couplers_to_m06_couplers_BREADY;
M_AXI_rready <= m06_couplers_to_m06_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m06_couplers_to_m06_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m06_couplers_to_m06_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m06_couplers_to_m06_couplers_WVALID;
S_AXI_arready <= m06_couplers_to_m06_couplers_ARREADY;
S_AXI_awready <= m06_couplers_to_m06_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m06_couplers_to_m06_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m06_couplers_to_m06_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m06_couplers_to_m06_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m06_couplers_to_m06_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m06_couplers_to_m06_couplers_RVALID;
S_AXI_wready <= m06_couplers_to_m06_couplers_WREADY;
m06_couplers_to_m06_couplers_ARADDR(3 downto 0) <= S_AXI_araddr(3 downto 0);
m06_couplers_to_m06_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m06_couplers_to_m06_couplers_ARREADY <= M_AXI_arready;
m06_couplers_to_m06_couplers_ARVALID <= S_AXI_arvalid;
m06_couplers_to_m06_couplers_AWADDR(3 downto 0) <= S_AXI_awaddr(3 downto 0);
m06_couplers_to_m06_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m06_couplers_to_m06_couplers_AWREADY <= M_AXI_awready;
m06_couplers_to_m06_couplers_AWVALID <= S_AXI_awvalid;
m06_couplers_to_m06_couplers_BREADY <= S_AXI_bready;
m06_couplers_to_m06_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m06_couplers_to_m06_couplers_BVALID <= M_AXI_bvalid;
m06_couplers_to_m06_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m06_couplers_to_m06_couplers_RREADY <= S_AXI_rready;
m06_couplers_to_m06_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m06_couplers_to_m06_couplers_RVALID <= M_AXI_rvalid;
m06_couplers_to_m06_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m06_couplers_to_m06_couplers_WREADY <= M_AXI_wready;
m06_couplers_to_m06_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m06_couplers_to_m06_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_2QEUYC is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_2QEUYC;
architecture STRUCTURE of s00_couplers_imp_2QEUYC is
component week1_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component week1_auto_pc_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= auto_pc_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= auto_pc_to_s00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_s00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= auto_pc_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_s00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= s00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(11 downto 0) <= s00_couplers_to_auto_pc_BID(11 downto 0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(11 downto 0) <= s00_couplers_to_auto_pc_RID(11 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= s00_couplers_to_auto_pc_WREADY;
auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_s00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0);
s00_couplers_to_auto_pc_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0);
s00_couplers_to_auto_pc_ARLOCK(1 downto 0) <= S_AXI_arlock(1 downto 0);
s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0);
s00_couplers_to_auto_pc_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0);
s00_couplers_to_auto_pc_AWLOCK(1 downto 0) <= S_AXI_awlock(1 downto 0);
s00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
s00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
s00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
s00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_auto_pc_WID(11 downto 0) <= S_AXI_wid(11 downto 0);
s00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
s00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component week1_auto_pc_0
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => auto_pc_to_s00_couplers_ARPROT(2 downto 0),
m_axi_arready => auto_pc_to_s00_couplers_ARREADY,
m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_s00_couplers_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => auto_pc_to_s00_couplers_AWPROT(2 downto 0),
m_axi_awready => auto_pc_to_s00_couplers_AWREADY,
m_axi_awvalid => auto_pc_to_s00_couplers_AWVALID,
m_axi_bready => auto_pc_to_s00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_s00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_s00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_s00_couplers_RDATA(31 downto 0),
m_axi_rready => auto_pc_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_s00_couplers_WDATA(31 downto 0),
m_axi_wready => auto_pc_to_s00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_s00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_s00_couplers_WVALID,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => s00_couplers_to_auto_pc_ARID(11 downto 0),
s_axi_arlen(3 downto 0) => s00_couplers_to_auto_pc_ARLEN(3 downto 0),
s_axi_arlock(1 downto 0) => s00_couplers_to_auto_pc_ARLOCK(1 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => s00_couplers_to_auto_pc_ARREADY,
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => s00_couplers_to_auto_pc_AWID(11 downto 0),
s_axi_awlen(3 downto 0) => s00_couplers_to_auto_pc_AWLEN(3 downto 0),
s_axi_awlock(1 downto 0) => s00_couplers_to_auto_pc_AWLOCK(1 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => s00_couplers_to_auto_pc_AWREADY,
s_axi_awsize(2 downto 0) => s00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => s00_couplers_to_auto_pc_AWVALID,
s_axi_bid(11 downto 0) => s00_couplers_to_auto_pc_BID(11 downto 0),
s_axi_bready => s00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => s00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => s00_couplers_to_auto_pc_RID(11 downto 0),
s_axi_rlast => s00_couplers_to_auto_pc_RLAST,
s_axi_rready => s00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => s00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wid(11 downto 0) => s00_couplers_to_auto_pc_WID(11 downto 0),
s_axi_wlast => s00_couplers_to_auto_pc_WLAST,
s_axi_wready => s00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => s00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity week1_processing_system7_0_axi_periph_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_ACLK : in STD_LOGIC;
M01_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_araddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M01_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M01_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M02_ACLK : in STD_LOGIC;
M02_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_araddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M02_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M02_AXI_arready : in STD_LOGIC;
M02_AXI_arvalid : out STD_LOGIC;
M02_AXI_awaddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M02_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M02_AXI_awready : in STD_LOGIC;
M02_AXI_awvalid : out STD_LOGIC;
M02_AXI_bready : out STD_LOGIC;
M02_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_bvalid : in STD_LOGIC;
M02_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_rready : out STD_LOGIC;
M02_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_rvalid : in STD_LOGIC;
M02_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_wready : in STD_LOGIC;
M02_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M02_AXI_wvalid : out STD_LOGIC;
M03_ACLK : in STD_LOGIC;
M03_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M03_AXI_araddr : out STD_LOGIC_VECTOR ( 6 downto 0 );
M03_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M03_AXI_arready : in STD_LOGIC;
M03_AXI_arvalid : out STD_LOGIC;
M03_AXI_awaddr : out STD_LOGIC_VECTOR ( 6 downto 0 );
M03_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M03_AXI_awready : in STD_LOGIC;
M03_AXI_awvalid : out STD_LOGIC;
M03_AXI_bready : out STD_LOGIC;
M03_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_bvalid : in STD_LOGIC;
M03_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_rready : out STD_LOGIC;
M03_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_rvalid : in STD_LOGIC;
M03_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_wready : in STD_LOGIC;
M03_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M03_AXI_wvalid : out STD_LOGIC;
M04_ACLK : in STD_LOGIC;
M04_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M04_AXI_araddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M04_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M04_AXI_arready : in STD_LOGIC;
M04_AXI_arvalid : out STD_LOGIC;
M04_AXI_awaddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M04_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M04_AXI_awready : in STD_LOGIC;
M04_AXI_awvalid : out STD_LOGIC;
M04_AXI_bready : out STD_LOGIC;
M04_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M04_AXI_bvalid : in STD_LOGIC;
M04_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_rready : out STD_LOGIC;
M04_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M04_AXI_rvalid : in STD_LOGIC;
M04_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_wready : in STD_LOGIC;
M04_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M04_AXI_wvalid : out STD_LOGIC;
M05_ACLK : in STD_LOGIC;
M05_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M05_AXI_araddr : out STD_LOGIC_VECTOR ( 6 downto 0 );
M05_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M05_AXI_arready : in STD_LOGIC;
M05_AXI_arvalid : out STD_LOGIC;
M05_AXI_awaddr : out STD_LOGIC_VECTOR ( 6 downto 0 );
M05_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M05_AXI_awready : in STD_LOGIC;
M05_AXI_awvalid : out STD_LOGIC;
M05_AXI_bready : out STD_LOGIC;
M05_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M05_AXI_bvalid : in STD_LOGIC;
M05_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_rready : out STD_LOGIC;
M05_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M05_AXI_rvalid : in STD_LOGIC;
M05_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_wready : in STD_LOGIC;
M05_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M05_AXI_wvalid : out STD_LOGIC;
M06_ACLK : in STD_LOGIC;
M06_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M06_AXI_araddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M06_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M06_AXI_arready : in STD_LOGIC;
M06_AXI_arvalid : out STD_LOGIC;
M06_AXI_awaddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
M06_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M06_AXI_awready : in STD_LOGIC;
M06_AXI_awvalid : out STD_LOGIC;
M06_AXI_bready : out STD_LOGIC;
M06_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M06_AXI_bvalid : in STD_LOGIC;
M06_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_rready : out STD_LOGIC;
M06_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M06_AXI_rvalid : in STD_LOGIC;
M06_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_wready : in STD_LOGIC;
M06_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M06_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC
);
end week1_processing_system7_0_axi_periph_0;
architecture STRUCTURE of week1_processing_system7_0_axi_periph_0 is
component week1_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 223 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 20 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 223 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 223 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 20 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 223 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 6 downto 0 )
);
end component week1_xbar_0;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M01_ACLK_1 : STD_LOGIC;
signal M01_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M02_ACLK_1 : STD_LOGIC;
signal M02_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M03_ACLK_1 : STD_LOGIC;
signal M03_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M04_ACLK_1 : STD_LOGIC;
signal M04_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M05_ACLK_1 : STD_LOGIC;
signal M05_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M06_ACLK_1 : STD_LOGIC;
signal M06_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 6 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 6 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 6 downto 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 6 downto 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_ACLK_net : STD_LOGIC;
signal processing_system7_0_axi_periph_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s00_couplers_to_xbar_BREADY : STD_LOGIC;
signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC;
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_WVALID : STD_LOGIC;
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_ARPROT : STD_LOGIC_VECTOR ( 5 downto 3 );
signal xbar_to_m01_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_AWPROT : STD_LOGIC_VECTOR ( 5 downto 3 );
signal xbar_to_m01_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 4 );
signal xbar_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_ARPROT : STD_LOGIC_VECTOR ( 8 downto 6 );
signal xbar_to_m02_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m02_couplers_ARVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_AWPROT : STD_LOGIC_VECTOR ( 8 downto 6 );
signal xbar_to_m02_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m02_couplers_AWVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_BVALID : STD_LOGIC;
signal xbar_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m02_couplers_RREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_RVALID : STD_LOGIC;
signal xbar_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_WREADY : STD_LOGIC;
signal xbar_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 11 downto 8 );
signal xbar_to_m02_couplers_WVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_ARPROT : STD_LOGIC_VECTOR ( 11 downto 9 );
signal xbar_to_m03_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m03_couplers_ARVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_AWPROT : STD_LOGIC_VECTOR ( 11 downto 9 );
signal xbar_to_m03_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m03_couplers_AWVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_BVALID : STD_LOGIC;
signal xbar_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m03_couplers_RREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_RVALID : STD_LOGIC;
signal xbar_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_WREADY : STD_LOGIC;
signal xbar_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 15 downto 12 );
signal xbar_to_m03_couplers_WVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_ARPROT : STD_LOGIC_VECTOR ( 14 downto 12 );
signal xbar_to_m04_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m04_couplers_ARVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_AWPROT : STD_LOGIC_VECTOR ( 14 downto 12 );
signal xbar_to_m04_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m04_couplers_AWVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_BREADY : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m04_couplers_BVALID : STD_LOGIC;
signal xbar_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m04_couplers_RREADY : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m04_couplers_RVALID : STD_LOGIC;
signal xbar_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_WREADY : STD_LOGIC;
signal xbar_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 19 downto 16 );
signal xbar_to_m04_couplers_WVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m05_couplers_ARADDR : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_ARPROT : STD_LOGIC_VECTOR ( 17 downto 15 );
signal xbar_to_m05_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m05_couplers_ARVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_AWADDR : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_AWPROT : STD_LOGIC_VECTOR ( 17 downto 15 );
signal xbar_to_m05_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m05_couplers_AWVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_BREADY : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m05_couplers_BVALID : STD_LOGIC;
signal xbar_to_m05_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m05_couplers_RREADY : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m05_couplers_RVALID : STD_LOGIC;
signal xbar_to_m05_couplers_WDATA : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_WREADY : STD_LOGIC;
signal xbar_to_m05_couplers_WSTRB : STD_LOGIC_VECTOR ( 23 downto 20 );
signal xbar_to_m05_couplers_WVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m06_couplers_ARADDR : STD_LOGIC_VECTOR ( 223 downto 192 );
signal xbar_to_m06_couplers_ARPROT : STD_LOGIC_VECTOR ( 20 downto 18 );
signal xbar_to_m06_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m06_couplers_ARVALID : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_AWADDR : STD_LOGIC_VECTOR ( 223 downto 192 );
signal xbar_to_m06_couplers_AWPROT : STD_LOGIC_VECTOR ( 20 downto 18 );
signal xbar_to_m06_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m06_couplers_AWVALID : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_BREADY : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m06_couplers_BVALID : STD_LOGIC;
signal xbar_to_m06_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m06_couplers_RREADY : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m06_couplers_RVALID : STD_LOGIC;
signal xbar_to_m06_couplers_WDATA : STD_LOGIC_VECTOR ( 223 downto 192 );
signal xbar_to_m06_couplers_WREADY : STD_LOGIC;
signal xbar_to_m06_couplers_WSTRB : STD_LOGIC_VECTOR ( 27 downto 24 );
signal xbar_to_m06_couplers_WVALID : STD_LOGIC_VECTOR ( 6 to 6 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1(0) <= M00_ARESETN(0);
M00_AXI_araddr(3 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_ARADDR(3 downto 0);
M00_AXI_arprot(2 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0);
M00_AXI_arvalid(0) <= m00_couplers_to_processing_system7_0_axi_periph_ARVALID(0);
M00_AXI_awaddr(3 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_AWADDR(3 downto 0);
M00_AXI_awprot(2 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0);
M00_AXI_awvalid(0) <= m00_couplers_to_processing_system7_0_axi_periph_AWVALID(0);
M00_AXI_bready(0) <= m00_couplers_to_processing_system7_0_axi_periph_BREADY(0);
M00_AXI_rready(0) <= m00_couplers_to_processing_system7_0_axi_periph_RREADY(0);
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M00_AXI_wstrb(3 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M00_AXI_wvalid(0) <= m00_couplers_to_processing_system7_0_axi_periph_WVALID(0);
M01_ACLK_1 <= M01_ACLK;
M01_ARESETN_1(0) <= M01_ARESETN(0);
M01_AXI_araddr(3 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_ARADDR(3 downto 0);
M01_AXI_arprot(2 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0);
M01_AXI_arvalid(0) <= m01_couplers_to_processing_system7_0_axi_periph_ARVALID(0);
M01_AXI_awaddr(3 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_AWADDR(3 downto 0);
M01_AXI_awprot(2 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0);
M01_AXI_awvalid(0) <= m01_couplers_to_processing_system7_0_axi_periph_AWVALID(0);
M01_AXI_bready(0) <= m01_couplers_to_processing_system7_0_axi_periph_BREADY(0);
M01_AXI_rready(0) <= m01_couplers_to_processing_system7_0_axi_periph_RREADY(0);
M01_AXI_wdata(31 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M01_AXI_wstrb(3 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M01_AXI_wvalid(0) <= m01_couplers_to_processing_system7_0_axi_periph_WVALID(0);
M02_ACLK_1 <= M02_ACLK;
M02_ARESETN_1(0) <= M02_ARESETN(0);
M02_AXI_araddr(3 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_ARADDR(3 downto 0);
M02_AXI_arprot(2 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0);
M02_AXI_arvalid <= m02_couplers_to_processing_system7_0_axi_periph_ARVALID;
M02_AXI_awaddr(3 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_AWADDR(3 downto 0);
M02_AXI_awprot(2 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0);
M02_AXI_awvalid <= m02_couplers_to_processing_system7_0_axi_periph_AWVALID;
M02_AXI_bready <= m02_couplers_to_processing_system7_0_axi_periph_BREADY;
M02_AXI_rready <= m02_couplers_to_processing_system7_0_axi_periph_RREADY;
M02_AXI_wdata(31 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M02_AXI_wstrb(3 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M02_AXI_wvalid <= m02_couplers_to_processing_system7_0_axi_periph_WVALID;
M03_ACLK_1 <= M03_ACLK;
M03_ARESETN_1(0) <= M03_ARESETN(0);
M03_AXI_araddr(6 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_ARADDR(6 downto 0);
M03_AXI_arprot(2 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0);
M03_AXI_arvalid <= m03_couplers_to_processing_system7_0_axi_periph_ARVALID;
M03_AXI_awaddr(6 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_AWADDR(6 downto 0);
M03_AXI_awprot(2 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0);
M03_AXI_awvalid <= m03_couplers_to_processing_system7_0_axi_periph_AWVALID;
M03_AXI_bready <= m03_couplers_to_processing_system7_0_axi_periph_BREADY;
M03_AXI_rready <= m03_couplers_to_processing_system7_0_axi_periph_RREADY;
M03_AXI_wdata(31 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M03_AXI_wstrb(3 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M03_AXI_wvalid <= m03_couplers_to_processing_system7_0_axi_periph_WVALID;
M04_ACLK_1 <= M04_ACLK;
M04_ARESETN_1(0) <= M04_ARESETN(0);
M04_AXI_araddr(3 downto 0) <= m04_couplers_to_processing_system7_0_axi_periph_ARADDR(3 downto 0);
M04_AXI_arprot(2 downto 0) <= m04_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0);
M04_AXI_arvalid <= m04_couplers_to_processing_system7_0_axi_periph_ARVALID;
M04_AXI_awaddr(3 downto 0) <= m04_couplers_to_processing_system7_0_axi_periph_AWADDR(3 downto 0);
M04_AXI_awprot(2 downto 0) <= m04_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0);
M04_AXI_awvalid <= m04_couplers_to_processing_system7_0_axi_periph_AWVALID;
M04_AXI_bready <= m04_couplers_to_processing_system7_0_axi_periph_BREADY;
M04_AXI_rready <= m04_couplers_to_processing_system7_0_axi_periph_RREADY;
M04_AXI_wdata(31 downto 0) <= m04_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M04_AXI_wstrb(3 downto 0) <= m04_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M04_AXI_wvalid <= m04_couplers_to_processing_system7_0_axi_periph_WVALID;
M05_ACLK_1 <= M05_ACLK;
M05_ARESETN_1(0) <= M05_ARESETN(0);
M05_AXI_araddr(6 downto 0) <= m05_couplers_to_processing_system7_0_axi_periph_ARADDR(6 downto 0);
M05_AXI_arprot(2 downto 0) <= m05_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0);
M05_AXI_arvalid <= m05_couplers_to_processing_system7_0_axi_periph_ARVALID;
M05_AXI_awaddr(6 downto 0) <= m05_couplers_to_processing_system7_0_axi_periph_AWADDR(6 downto 0);
M05_AXI_awprot(2 downto 0) <= m05_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0);
M05_AXI_awvalid <= m05_couplers_to_processing_system7_0_axi_periph_AWVALID;
M05_AXI_bready <= m05_couplers_to_processing_system7_0_axi_periph_BREADY;
M05_AXI_rready <= m05_couplers_to_processing_system7_0_axi_periph_RREADY;
M05_AXI_wdata(31 downto 0) <= m05_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M05_AXI_wstrb(3 downto 0) <= m05_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M05_AXI_wvalid <= m05_couplers_to_processing_system7_0_axi_periph_WVALID;
M06_ACLK_1 <= M06_ACLK;
M06_ARESETN_1(0) <= M06_ARESETN(0);
M06_AXI_araddr(3 downto 0) <= m06_couplers_to_processing_system7_0_axi_periph_ARADDR(3 downto 0);
M06_AXI_arprot(2 downto 0) <= m06_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0);
M06_AXI_arvalid <= m06_couplers_to_processing_system7_0_axi_periph_ARVALID;
M06_AXI_awaddr(3 downto 0) <= m06_couplers_to_processing_system7_0_axi_periph_AWADDR(3 downto 0);
M06_AXI_awprot(2 downto 0) <= m06_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0);
M06_AXI_awvalid <= m06_couplers_to_processing_system7_0_axi_periph_AWVALID;
M06_AXI_bready <= m06_couplers_to_processing_system7_0_axi_periph_BREADY;
M06_AXI_rready <= m06_couplers_to_processing_system7_0_axi_periph_RREADY;
M06_AXI_wdata(31 downto 0) <= m06_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M06_AXI_wstrb(3 downto 0) <= m06_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M06_AXI_wvalid <= m06_couplers_to_processing_system7_0_axi_periph_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready <= processing_system7_0_axi_periph_to_s00_couplers_ARREADY;
S00_AXI_awready <= processing_system7_0_axi_periph_to_s00_couplers_AWREADY;
S00_AXI_bid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0);
S00_AXI_bresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= processing_system7_0_axi_periph_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0);
S00_AXI_rlast <= processing_system7_0_axi_periph_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= processing_system7_0_axi_periph_to_s00_couplers_RVALID;
S00_AXI_wready <= processing_system7_0_axi_periph_to_s00_couplers_WREADY;
m00_couplers_to_processing_system7_0_axi_periph_ARREADY(0) <= M00_AXI_arready(0);
m00_couplers_to_processing_system7_0_axi_periph_AWREADY(0) <= M00_AXI_awready(0);
m00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_BVALID(0) <= M00_AXI_bvalid(0);
m00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_RVALID(0) <= M00_AXI_rvalid(0);
m00_couplers_to_processing_system7_0_axi_periph_WREADY(0) <= M00_AXI_wready(0);
m01_couplers_to_processing_system7_0_axi_periph_ARREADY(0) <= M01_AXI_arready(0);
m01_couplers_to_processing_system7_0_axi_periph_AWREADY(0) <= M01_AXI_awready(0);
m01_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_BVALID(0) <= M01_AXI_bvalid(0);
m01_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_RVALID(0) <= M01_AXI_rvalid(0);
m01_couplers_to_processing_system7_0_axi_periph_WREADY(0) <= M01_AXI_wready(0);
m02_couplers_to_processing_system7_0_axi_periph_ARREADY <= M02_AXI_arready;
m02_couplers_to_processing_system7_0_axi_periph_AWREADY <= M02_AXI_awready;
m02_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M02_AXI_bresp(1 downto 0);
m02_couplers_to_processing_system7_0_axi_periph_BVALID <= M02_AXI_bvalid;
m02_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M02_AXI_rdata(31 downto 0);
m02_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M02_AXI_rresp(1 downto 0);
m02_couplers_to_processing_system7_0_axi_periph_RVALID <= M02_AXI_rvalid;
m02_couplers_to_processing_system7_0_axi_periph_WREADY <= M02_AXI_wready;
m03_couplers_to_processing_system7_0_axi_periph_ARREADY <= M03_AXI_arready;
m03_couplers_to_processing_system7_0_axi_periph_AWREADY <= M03_AXI_awready;
m03_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M03_AXI_bresp(1 downto 0);
m03_couplers_to_processing_system7_0_axi_periph_BVALID <= M03_AXI_bvalid;
m03_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M03_AXI_rdata(31 downto 0);
m03_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M03_AXI_rresp(1 downto 0);
m03_couplers_to_processing_system7_0_axi_periph_RVALID <= M03_AXI_rvalid;
m03_couplers_to_processing_system7_0_axi_periph_WREADY <= M03_AXI_wready;
m04_couplers_to_processing_system7_0_axi_periph_ARREADY <= M04_AXI_arready;
m04_couplers_to_processing_system7_0_axi_periph_AWREADY <= M04_AXI_awready;
m04_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M04_AXI_bresp(1 downto 0);
m04_couplers_to_processing_system7_0_axi_periph_BVALID <= M04_AXI_bvalid;
m04_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M04_AXI_rdata(31 downto 0);
m04_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M04_AXI_rresp(1 downto 0);
m04_couplers_to_processing_system7_0_axi_periph_RVALID <= M04_AXI_rvalid;
m04_couplers_to_processing_system7_0_axi_periph_WREADY <= M04_AXI_wready;
m05_couplers_to_processing_system7_0_axi_periph_ARREADY <= M05_AXI_arready;
m05_couplers_to_processing_system7_0_axi_periph_AWREADY <= M05_AXI_awready;
m05_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M05_AXI_bresp(1 downto 0);
m05_couplers_to_processing_system7_0_axi_periph_BVALID <= M05_AXI_bvalid;
m05_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M05_AXI_rdata(31 downto 0);
m05_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M05_AXI_rresp(1 downto 0);
m05_couplers_to_processing_system7_0_axi_periph_RVALID <= M05_AXI_rvalid;
m05_couplers_to_processing_system7_0_axi_periph_WREADY <= M05_AXI_wready;
m06_couplers_to_processing_system7_0_axi_periph_ARREADY <= M06_AXI_arready;
m06_couplers_to_processing_system7_0_axi_periph_AWREADY <= M06_AXI_awready;
m06_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M06_AXI_bresp(1 downto 0);
m06_couplers_to_processing_system7_0_axi_periph_BVALID <= M06_AXI_bvalid;
m06_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M06_AXI_rdata(31 downto 0);
m06_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M06_AXI_rresp(1 downto 0);
m06_couplers_to_processing_system7_0_axi_periph_RVALID <= M06_AXI_rvalid;
m06_couplers_to_processing_system7_0_axi_periph_WREADY <= M06_AXI_wready;
processing_system7_0_axi_periph_ACLK_net <= ACLK;
processing_system7_0_axi_periph_ARESETN_net(0) <= ARESETN(0);
processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
processing_system7_0_axi_periph_to_s00_couplers_BREADY <= S00_AXI_bready;
processing_system7_0_axi_periph_to_s00_couplers_RREADY <= S00_AXI_rready;
processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0) <= S00_AXI_wid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WLAST <= S00_AXI_wlast;
processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WVALID <= S00_AXI_wvalid;
m00_couplers: entity work.m00_couplers_imp_QJRQ3J
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN(0) => M00_ARESETN_1(0),
M_AXI_araddr(3 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_ARADDR(3 downto 0),
M_AXI_arprot(2 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0),
M_AXI_arready(0) => m00_couplers_to_processing_system7_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_ARVALID(0),
M_AXI_awaddr(3 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_AWADDR(3 downto 0),
M_AXI_awprot(2 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0),
M_AXI_awready(0) => m00_couplers_to_processing_system7_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m00_couplers_to_processing_system7_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m00_couplers_to_processing_system7_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m00_couplers_to_processing_system7_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_WVALID(0),
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(3 downto 0) => xbar_to_m00_couplers_ARADDR(3 downto 0),
S_AXI_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
S_AXI_arready(0) => xbar_to_m00_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(3 downto 0) => xbar_to_m00_couplers_AWADDR(3 downto 0),
S_AXI_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
S_AXI_awready(0) => xbar_to_m00_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bready(0) => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wready(0) => xbar_to_m00_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid(0) => xbar_to_m00_couplers_WVALID(0)
);
m01_couplers: entity work.m01_couplers_imp_1RWPDFB
port map (
M_ACLK => M01_ACLK_1,
M_ARESETN(0) => M01_ARESETN_1(0),
M_AXI_araddr(3 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_ARADDR(3 downto 0),
M_AXI_arprot(2 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0),
M_AXI_arready(0) => m01_couplers_to_processing_system7_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_ARVALID(0),
M_AXI_awaddr(3 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_AWADDR(3 downto 0),
M_AXI_awprot(2 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0),
M_AXI_awready(0) => m01_couplers_to_processing_system7_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m01_couplers_to_processing_system7_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m01_couplers_to_processing_system7_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m01_couplers_to_processing_system7_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m01_couplers_to_processing_system7_0_axi_periph_WVALID(0),
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(3 downto 0) => xbar_to_m01_couplers_ARADDR(35 downto 32),
S_AXI_arprot(2 downto 0) => xbar_to_m01_couplers_ARPROT(5 downto 3),
S_AXI_arready(0) => xbar_to_m01_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m01_couplers_ARVALID(1),
S_AXI_awaddr(3 downto 0) => xbar_to_m01_couplers_AWADDR(35 downto 32),
S_AXI_awprot(2 downto 0) => xbar_to_m01_couplers_AWPROT(5 downto 3),
S_AXI_awready(0) => xbar_to_m01_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m01_couplers_AWVALID(1),
S_AXI_bready(0) => xbar_to_m01_couplers_BREADY(1),
S_AXI_bresp(1 downto 0) => xbar_to_m01_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m01_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m01_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m01_couplers_RREADY(1),
S_AXI_rresp(1 downto 0) => xbar_to_m01_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m01_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m01_couplers_WDATA(63 downto 32),
S_AXI_wready(0) => xbar_to_m01_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m01_couplers_WSTRB(7 downto 4),
S_AXI_wvalid(0) => xbar_to_m01_couplers_WVALID(1)
);
m02_couplers: entity work.m02_couplers_imp_1WKUKB2
port map (
M_ACLK => M02_ACLK_1,
M_ARESETN(0) => M02_ARESETN_1(0),
M_AXI_araddr(3 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_ARADDR(3 downto 0),
M_AXI_arprot(2 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0),
M_AXI_arready => m02_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => m02_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(3 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_AWADDR(3 downto 0),
M_AXI_awprot(2 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0),
M_AXI_awready => m02_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => m02_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => m02_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m02_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m02_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m02_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m02_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m02_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(3 downto 0) => xbar_to_m02_couplers_ARADDR(67 downto 64),
S_AXI_arprot(2 downto 0) => xbar_to_m02_couplers_ARPROT(8 downto 6),
S_AXI_arready => xbar_to_m02_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m02_couplers_ARVALID(2),
S_AXI_awaddr(3 downto 0) => xbar_to_m02_couplers_AWADDR(67 downto 64),
S_AXI_awprot(2 downto 0) => xbar_to_m02_couplers_AWPROT(8 downto 6),
S_AXI_awready => xbar_to_m02_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m02_couplers_AWVALID(2),
S_AXI_bready => xbar_to_m02_couplers_BREADY(2),
S_AXI_bresp(1 downto 0) => xbar_to_m02_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m02_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m02_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m02_couplers_RREADY(2),
S_AXI_rresp(1 downto 0) => xbar_to_m02_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m02_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m02_couplers_WDATA(95 downto 64),
S_AXI_wready => xbar_to_m02_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m02_couplers_WSTRB(11 downto 8),
S_AXI_wvalid => xbar_to_m02_couplers_WVALID(2)
);
m03_couplers: entity work.m03_couplers_imp_LVBNAE
port map (
M_ACLK => M03_ACLK_1,
M_ARESETN(0) => M03_ARESETN_1(0),
M_AXI_araddr(6 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_ARADDR(6 downto 0),
M_AXI_arprot(2 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0),
M_AXI_arready => m03_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => m03_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(6 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_AWADDR(6 downto 0),
M_AXI_awprot(2 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0),
M_AXI_awready => m03_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => m03_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => m03_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m03_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m03_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m03_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m03_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m03_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(6 downto 0) => xbar_to_m03_couplers_ARADDR(102 downto 96),
S_AXI_arprot(2 downto 0) => xbar_to_m03_couplers_ARPROT(11 downto 9),
S_AXI_arready => xbar_to_m03_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m03_couplers_ARVALID(3),
S_AXI_awaddr(6 downto 0) => xbar_to_m03_couplers_AWADDR(102 downto 96),
S_AXI_awprot(2 downto 0) => xbar_to_m03_couplers_AWPROT(11 downto 9),
S_AXI_awready => xbar_to_m03_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m03_couplers_AWVALID(3),
S_AXI_bready => xbar_to_m03_couplers_BREADY(3),
S_AXI_bresp(1 downto 0) => xbar_to_m03_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m03_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m03_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m03_couplers_RREADY(3),
S_AXI_rresp(1 downto 0) => xbar_to_m03_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m03_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m03_couplers_WDATA(127 downto 96),
S_AXI_wready => xbar_to_m03_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m03_couplers_WSTRB(15 downto 12),
S_AXI_wvalid => xbar_to_m03_couplers_WVALID(3)
);
m04_couplers: entity work.m04_couplers_imp_1NBU6D8
port map (
M_ACLK => M04_ACLK_1,
M_ARESETN(0) => M04_ARESETN_1(0),
M_AXI_araddr(3 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_ARADDR(3 downto 0),
M_AXI_arprot(2 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0),
M_AXI_arready => m04_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => m04_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(3 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_AWADDR(3 downto 0),
M_AXI_awprot(2 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0),
M_AXI_awready => m04_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => m04_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => m04_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m04_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m04_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m04_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m04_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m04_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(3 downto 0) => xbar_to_m04_couplers_ARADDR(131 downto 128),
S_AXI_arprot(2 downto 0) => xbar_to_m04_couplers_ARPROT(14 downto 12),
S_AXI_arready => xbar_to_m04_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m04_couplers_ARVALID(4),
S_AXI_awaddr(3 downto 0) => xbar_to_m04_couplers_AWADDR(131 downto 128),
S_AXI_awprot(2 downto 0) => xbar_to_m04_couplers_AWPROT(14 downto 12),
S_AXI_awready => xbar_to_m04_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m04_couplers_AWVALID(4),
S_AXI_bready => xbar_to_m04_couplers_BREADY(4),
S_AXI_bresp(1 downto 0) => xbar_to_m04_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m04_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m04_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m04_couplers_RREADY(4),
S_AXI_rresp(1 downto 0) => xbar_to_m04_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m04_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m04_couplers_WDATA(159 downto 128),
S_AXI_wready => xbar_to_m04_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m04_couplers_WSTRB(19 downto 16),
S_AXI_wvalid => xbar_to_m04_couplers_WVALID(4)
);
m05_couplers: entity work.m05_couplers_imp_U0DM50
port map (
M_ACLK => M05_ACLK_1,
M_ARESETN(0) => M05_ARESETN_1(0),
M_AXI_araddr(6 downto 0) => m05_couplers_to_processing_system7_0_axi_periph_ARADDR(6 downto 0),
M_AXI_arprot(2 downto 0) => m05_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0),
M_AXI_arready => m05_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => m05_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(6 downto 0) => m05_couplers_to_processing_system7_0_axi_periph_AWADDR(6 downto 0),
M_AXI_awprot(2 downto 0) => m05_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0),
M_AXI_awready => m05_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => m05_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => m05_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m05_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m05_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m05_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m05_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m05_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m05_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m05_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m05_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m05_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m05_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(6 downto 0) => xbar_to_m05_couplers_ARADDR(166 downto 160),
S_AXI_arprot(2 downto 0) => xbar_to_m05_couplers_ARPROT(17 downto 15),
S_AXI_arready => xbar_to_m05_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m05_couplers_ARVALID(5),
S_AXI_awaddr(6 downto 0) => xbar_to_m05_couplers_AWADDR(166 downto 160),
S_AXI_awprot(2 downto 0) => xbar_to_m05_couplers_AWPROT(17 downto 15),
S_AXI_awready => xbar_to_m05_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m05_couplers_AWVALID(5),
S_AXI_bready => xbar_to_m05_couplers_BREADY(5),
S_AXI_bresp(1 downto 0) => xbar_to_m05_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m05_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m05_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m05_couplers_RREADY(5),
S_AXI_rresp(1 downto 0) => xbar_to_m05_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m05_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m05_couplers_WDATA(191 downto 160),
S_AXI_wready => xbar_to_m05_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m05_couplers_WSTRB(23 downto 20),
S_AXI_wvalid => xbar_to_m05_couplers_WVALID(5)
);
m06_couplers: entity work.m06_couplers_imp_YRXD0T
port map (
M_ACLK => M06_ACLK_1,
M_ARESETN(0) => M06_ARESETN_1(0),
M_AXI_araddr(3 downto 0) => m06_couplers_to_processing_system7_0_axi_periph_ARADDR(3 downto 0),
M_AXI_arprot(2 downto 0) => m06_couplers_to_processing_system7_0_axi_periph_ARPROT(2 downto 0),
M_AXI_arready => m06_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => m06_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(3 downto 0) => m06_couplers_to_processing_system7_0_axi_periph_AWADDR(3 downto 0),
M_AXI_awprot(2 downto 0) => m06_couplers_to_processing_system7_0_axi_periph_AWPROT(2 downto 0),
M_AXI_awready => m06_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => m06_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => m06_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m06_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m06_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m06_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m06_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m06_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m06_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m06_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m06_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m06_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m06_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(3 downto 0) => xbar_to_m06_couplers_ARADDR(195 downto 192),
S_AXI_arprot(2 downto 0) => xbar_to_m06_couplers_ARPROT(20 downto 18),
S_AXI_arready => xbar_to_m06_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m06_couplers_ARVALID(6),
S_AXI_awaddr(3 downto 0) => xbar_to_m06_couplers_AWADDR(195 downto 192),
S_AXI_awprot(2 downto 0) => xbar_to_m06_couplers_AWPROT(20 downto 18),
S_AXI_awready => xbar_to_m06_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m06_couplers_AWVALID(6),
S_AXI_bready => xbar_to_m06_couplers_BREADY(6),
S_AXI_bresp(1 downto 0) => xbar_to_m06_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m06_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m06_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m06_couplers_RREADY(6),
S_AXI_rresp(1 downto 0) => xbar_to_m06_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m06_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m06_couplers_WDATA(223 downto 192),
S_AXI_wready => xbar_to_m06_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m06_couplers_WSTRB(27 downto 24),
S_AXI_wvalid => xbar_to_m06_couplers_WVALID(6)
);
s00_couplers: entity work.s00_couplers_imp_2QEUYC
port map (
M_ACLK => processing_system7_0_axi_periph_ACLK_net,
M_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arvalid => s00_couplers_to_xbar_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready => s00_couplers_to_xbar_AWREADY(0),
M_AXI_awvalid => s00_couplers_to_xbar_AWVALID,
M_AXI_bready => s00_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_xbar_BVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rready => s00_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_xbar_RVALID(0),
M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wready => s00_couplers_to_xbar_WREADY(0),
M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid => s00_couplers_to_xbar_WVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0),
S_AXI_arlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0),
S_AXI_arlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0),
S_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0),
S_AXI_arready => processing_system7_0_axi_periph_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => processing_system7_0_axi_periph_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0),
S_AXI_awlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0),
S_AXI_awlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0),
S_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready => processing_system7_0_axi_periph_to_s00_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => processing_system7_0_axi_periph_to_s00_couplers_AWVALID,
S_AXI_bid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0),
S_AXI_bready => processing_system7_0_axi_periph_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => processing_system7_0_axi_periph_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0),
S_AXI_rlast => processing_system7_0_axi_periph_to_s00_couplers_RLAST,
S_AXI_rready => processing_system7_0_axi_periph_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => processing_system7_0_axi_periph_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0),
S_AXI_wlast => processing_system7_0_axi_periph_to_s00_couplers_WLAST,
S_AXI_wready => processing_system7_0_axi_periph_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => processing_system7_0_axi_periph_to_s00_couplers_WVALID
);
xbar: component week1_xbar_0
port map (
aclk => processing_system7_0_axi_periph_ACLK_net,
aresetn => processing_system7_0_axi_periph_ARESETN_net(0),
m_axi_araddr(223 downto 192) => xbar_to_m06_couplers_ARADDR(223 downto 192),
m_axi_araddr(191 downto 160) => xbar_to_m05_couplers_ARADDR(191 downto 160),
m_axi_araddr(159 downto 128) => xbar_to_m04_couplers_ARADDR(159 downto 128),
m_axi_araddr(127 downto 96) => xbar_to_m03_couplers_ARADDR(127 downto 96),
m_axi_araddr(95 downto 64) => xbar_to_m02_couplers_ARADDR(95 downto 64),
m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arprot(20 downto 18) => xbar_to_m06_couplers_ARPROT(20 downto 18),
m_axi_arprot(17 downto 15) => xbar_to_m05_couplers_ARPROT(17 downto 15),
m_axi_arprot(14 downto 12) => xbar_to_m04_couplers_ARPROT(14 downto 12),
m_axi_arprot(11 downto 9) => xbar_to_m03_couplers_ARPROT(11 downto 9),
m_axi_arprot(8 downto 6) => xbar_to_m02_couplers_ARPROT(8 downto 6),
m_axi_arprot(5 downto 3) => xbar_to_m01_couplers_ARPROT(5 downto 3),
m_axi_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arready(6) => xbar_to_m06_couplers_ARREADY,
m_axi_arready(5) => xbar_to_m05_couplers_ARREADY,
m_axi_arready(4) => xbar_to_m04_couplers_ARREADY,
m_axi_arready(3) => xbar_to_m03_couplers_ARREADY,
m_axi_arready(2) => xbar_to_m02_couplers_ARREADY,
m_axi_arready(1) => xbar_to_m01_couplers_ARREADY(0),
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY(0),
m_axi_arvalid(6) => xbar_to_m06_couplers_ARVALID(6),
m_axi_arvalid(5) => xbar_to_m05_couplers_ARVALID(5),
m_axi_arvalid(4) => xbar_to_m04_couplers_ARVALID(4),
m_axi_arvalid(3) => xbar_to_m03_couplers_ARVALID(3),
m_axi_arvalid(2) => xbar_to_m02_couplers_ARVALID(2),
m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(223 downto 192) => xbar_to_m06_couplers_AWADDR(223 downto 192),
m_axi_awaddr(191 downto 160) => xbar_to_m05_couplers_AWADDR(191 downto 160),
m_axi_awaddr(159 downto 128) => xbar_to_m04_couplers_AWADDR(159 downto 128),
m_axi_awaddr(127 downto 96) => xbar_to_m03_couplers_AWADDR(127 downto 96),
m_axi_awaddr(95 downto 64) => xbar_to_m02_couplers_AWADDR(95 downto 64),
m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awprot(20 downto 18) => xbar_to_m06_couplers_AWPROT(20 downto 18),
m_axi_awprot(17 downto 15) => xbar_to_m05_couplers_AWPROT(17 downto 15),
m_axi_awprot(14 downto 12) => xbar_to_m04_couplers_AWPROT(14 downto 12),
m_axi_awprot(11 downto 9) => xbar_to_m03_couplers_AWPROT(11 downto 9),
m_axi_awprot(8 downto 6) => xbar_to_m02_couplers_AWPROT(8 downto 6),
m_axi_awprot(5 downto 3) => xbar_to_m01_couplers_AWPROT(5 downto 3),
m_axi_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awready(6) => xbar_to_m06_couplers_AWREADY,
m_axi_awready(5) => xbar_to_m05_couplers_AWREADY,
m_axi_awready(4) => xbar_to_m04_couplers_AWREADY,
m_axi_awready(3) => xbar_to_m03_couplers_AWREADY,
m_axi_awready(2) => xbar_to_m02_couplers_AWREADY,
m_axi_awready(1) => xbar_to_m01_couplers_AWREADY(0),
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY(0),
m_axi_awvalid(6) => xbar_to_m06_couplers_AWVALID(6),
m_axi_awvalid(5) => xbar_to_m05_couplers_AWVALID(5),
m_axi_awvalid(4) => xbar_to_m04_couplers_AWVALID(4),
m_axi_awvalid(3) => xbar_to_m03_couplers_AWVALID(3),
m_axi_awvalid(2) => xbar_to_m02_couplers_AWVALID(2),
m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bready(6) => xbar_to_m06_couplers_BREADY(6),
m_axi_bready(5) => xbar_to_m05_couplers_BREADY(5),
m_axi_bready(4) => xbar_to_m04_couplers_BREADY(4),
m_axi_bready(3) => xbar_to_m03_couplers_BREADY(3),
m_axi_bready(2) => xbar_to_m02_couplers_BREADY(2),
m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(13 downto 12) => xbar_to_m06_couplers_BRESP(1 downto 0),
m_axi_bresp(11 downto 10) => xbar_to_m05_couplers_BRESP(1 downto 0),
m_axi_bresp(9 downto 8) => xbar_to_m04_couplers_BRESP(1 downto 0),
m_axi_bresp(7 downto 6) => xbar_to_m03_couplers_BRESP(1 downto 0),
m_axi_bresp(5 downto 4) => xbar_to_m02_couplers_BRESP(1 downto 0),
m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(6) => xbar_to_m06_couplers_BVALID,
m_axi_bvalid(5) => xbar_to_m05_couplers_BVALID,
m_axi_bvalid(4) => xbar_to_m04_couplers_BVALID,
m_axi_bvalid(3) => xbar_to_m03_couplers_BVALID,
m_axi_bvalid(2) => xbar_to_m02_couplers_BVALID,
m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID(0),
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
m_axi_rdata(223 downto 192) => xbar_to_m06_couplers_RDATA(31 downto 0),
m_axi_rdata(191 downto 160) => xbar_to_m05_couplers_RDATA(31 downto 0),
m_axi_rdata(159 downto 128) => xbar_to_m04_couplers_RDATA(31 downto 0),
m_axi_rdata(127 downto 96) => xbar_to_m03_couplers_RDATA(31 downto 0),
m_axi_rdata(95 downto 64) => xbar_to_m02_couplers_RDATA(31 downto 0),
m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0),
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rready(6) => xbar_to_m06_couplers_RREADY(6),
m_axi_rready(5) => xbar_to_m05_couplers_RREADY(5),
m_axi_rready(4) => xbar_to_m04_couplers_RREADY(4),
m_axi_rready(3) => xbar_to_m03_couplers_RREADY(3),
m_axi_rready(2) => xbar_to_m02_couplers_RREADY(2),
m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1),
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(13 downto 12) => xbar_to_m06_couplers_RRESP(1 downto 0),
m_axi_rresp(11 downto 10) => xbar_to_m05_couplers_RRESP(1 downto 0),
m_axi_rresp(9 downto 8) => xbar_to_m04_couplers_RRESP(1 downto 0),
m_axi_rresp(7 downto 6) => xbar_to_m03_couplers_RRESP(1 downto 0),
m_axi_rresp(5 downto 4) => xbar_to_m02_couplers_RRESP(1 downto 0),
m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(6) => xbar_to_m06_couplers_RVALID,
m_axi_rvalid(5) => xbar_to_m05_couplers_RVALID,
m_axi_rvalid(4) => xbar_to_m04_couplers_RVALID,
m_axi_rvalid(3) => xbar_to_m03_couplers_RVALID,
m_axi_rvalid(2) => xbar_to_m02_couplers_RVALID,
m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID(0),
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
m_axi_wdata(223 downto 192) => xbar_to_m06_couplers_WDATA(223 downto 192),
m_axi_wdata(191 downto 160) => xbar_to_m05_couplers_WDATA(191 downto 160),
m_axi_wdata(159 downto 128) => xbar_to_m04_couplers_WDATA(159 downto 128),
m_axi_wdata(127 downto 96) => xbar_to_m03_couplers_WDATA(127 downto 96),
m_axi_wdata(95 downto 64) => xbar_to_m02_couplers_WDATA(95 downto 64),
m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32),
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wready(6) => xbar_to_m06_couplers_WREADY,
m_axi_wready(5) => xbar_to_m05_couplers_WREADY,
m_axi_wready(4) => xbar_to_m04_couplers_WREADY,
m_axi_wready(3) => xbar_to_m03_couplers_WREADY,
m_axi_wready(2) => xbar_to_m02_couplers_WREADY,
m_axi_wready(1) => xbar_to_m01_couplers_WREADY(0),
m_axi_wready(0) => xbar_to_m00_couplers_WREADY(0),
m_axi_wstrb(27 downto 24) => xbar_to_m06_couplers_WSTRB(27 downto 24),
m_axi_wstrb(23 downto 20) => xbar_to_m05_couplers_WSTRB(23 downto 20),
m_axi_wstrb(19 downto 16) => xbar_to_m04_couplers_WSTRB(19 downto 16),
m_axi_wstrb(15 downto 12) => xbar_to_m03_couplers_WSTRB(15 downto 12),
m_axi_wstrb(11 downto 8) => xbar_to_m02_couplers_WSTRB(11 downto 8),
m_axi_wstrb(7 downto 4) => xbar_to_m01_couplers_WSTRB(7 downto 4),
m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid(6) => xbar_to_m06_couplers_WVALID(6),
m_axi_wvalid(5) => xbar_to_m05_couplers_WVALID(5),
m_axi_wvalid(4) => xbar_to_m04_couplers_WVALID(4),
m_axi_wvalid(3) => xbar_to_m03_couplers_WVALID(3),
m_axi_wvalid(2) => xbar_to_m02_couplers_WVALID(2),
m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID,
s_axi_bready(0) => s00_couplers_to_xbar_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rready(0) => s00_couplers_to_xbar_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity week1 is
port (
AC_ADR0 : out STD_LOGIC;
AC_ADR1 : out STD_LOGIC;
AC_GPIO0 : out STD_LOGIC;
AC_GPIO1 : in STD_LOGIC;
AC_GPIO2 : in STD_LOGIC;
AC_GPIO3 : in STD_LOGIC;
AC_MCLK : out STD_LOGIC;
AC_SCK : out STD_LOGIC;
AC_SDA : inout STD_LOGIC;
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of week1 : entity is "week1,IP_Integrator,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=week1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=23,numReposBlks=14,numNonXlnxBlks=9,numHierBlks=9,maxHierDepth=0,da_axi4_cnt=7,da_ps7_cnt=1,synth_mode=Global}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of week1 : entity is "week1.hwdef";
end week1;
architecture STRUCTURE of week1 is
component week1_zed_audio_0_0 is
port (
clk_100 : in STD_LOGIC;
AC_ADR0 : out STD_LOGIC;
AC_ADR1 : out STD_LOGIC;
AC_GPIO0 : out STD_LOGIC;
AC_GPIO1 : in STD_LOGIC;
AC_GPIO2 : in STD_LOGIC;
AC_GPIO3 : in STD_LOGIC;
hphone_l : in STD_LOGIC_VECTOR ( 23 downto 0 );
hphone_l_valid : in STD_LOGIC;
hphone_r : in STD_LOGIC_VECTOR ( 23 downto 0 );
hphone_r_valid_dummy : in STD_LOGIC;
line_in_l : out STD_LOGIC_VECTOR ( 23 downto 0 );
line_in_r : out STD_LOGIC_VECTOR ( 23 downto 0 );
new_sample : out STD_LOGIC;
sample_clk_48k : out STD_LOGIC;
AC_MCLK : out STD_LOGIC;
AC_SCK : out STD_LOGIC;
AC_SDA : inout STD_LOGIC
);
end component week1_zed_audio_0_0;
component week1_audio_to_AXI_0_1 is
port (
audio_in_l : in STD_LOGIC_VECTOR ( 23 downto 0 );
audio_in_r : in STD_LOGIC_VECTOR ( 23 downto 0 );
audio_in_valid : in STD_LOGIC;
audio_out_valid_irq : out STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
end component week1_audio_to_AXI_0_1;
component week1_AXI_to_audio_0_0 is
port (
audio_out_l : out STD_LOGIC_VECTOR ( 23 downto 0 );
audio_out_r : out STD_LOGIC_VECTOR ( 23 downto 0 );
audio_out_valid : out STD_LOGIC;
audio_in_valid_irq : in STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
end component week1_AXI_to_audio_0_0;
component week1_processing_system7_0_0 is
port (
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component week1_processing_system7_0_0;
component week1_rst_processing_system7_0_100M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component week1_rst_processing_system7_0_100M_0;
component week1_xlconstant_0_1 is
port (
dout : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component week1_xlconstant_0_1;
component week1_AXI_to_audio_0_1 is
port (
audio_out_l : out STD_LOGIC_VECTOR ( 23 downto 0 );
audio_out_r : out STD_LOGIC_VECTOR ( 23 downto 0 );
audio_out_valid : out STD_LOGIC;
audio_in_valid_irq : in STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
end component week1_AXI_to_audio_0_1;
component week1_audio_mixer_0_0 is
port (
audio_mixed_a_b_left_out : out STD_LOGIC_VECTOR ( 23 downto 0 );
audio_mixed_a_b_right_out : out STD_LOGIC_VECTOR ( 23 downto 0 );
audio_channel_a_left_in : in STD_LOGIC_VECTOR ( 23 downto 0 );
audio_channel_a_right_in : in STD_LOGIC_VECTOR ( 23 downto 0 );
audio_channel_b_left_in : in STD_LOGIC_VECTOR ( 23 downto 0 );
audio_channel_b_right_in : in STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component week1_audio_mixer_0_0;
component week1_FILTER_IIR_0_0 is
port (
AUDIO_OUT_L : out STD_LOGIC_VECTOR ( 23 downto 0 );
AUDIO_OUT_R : out STD_LOGIC_VECTOR ( 23 downto 0 );
FILTER_DONE : out STD_LOGIC;
SAMPLE_TRIG : in STD_LOGIC;
AUDIO_IN_L : in STD_LOGIC_VECTOR ( 23 downto 0 );
AUDIO_IN_R : in STD_LOGIC_VECTOR ( 23 downto 0 );
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
end component week1_FILTER_IIR_0_0;
component week1_Volume_Pregain_0_0 is
port (
OUT_VOLCTRL_L : out STD_LOGIC_VECTOR ( 23 downto 0 );
OUT_VOLCTRL_R : out STD_LOGIC_VECTOR ( 23 downto 0 );
OUT_RDY : out STD_LOGIC;
IN_SIG_L : in STD_LOGIC_VECTOR ( 23 downto 0 );
IN_SIG_R : in STD_LOGIC_VECTOR ( 23 downto 0 );
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
end component week1_Volume_Pregain_0_0;
component week1_FILTER_IIR_0_1 is
port (
AUDIO_OUT_L : out STD_LOGIC_VECTOR ( 23 downto 0 );
AUDIO_OUT_R : out STD_LOGIC_VECTOR ( 23 downto 0 );
FILTER_DONE : out STD_LOGIC;
SAMPLE_TRIG : in STD_LOGIC;
AUDIO_IN_L : in STD_LOGIC_VECTOR ( 23 downto 0 );
AUDIO_IN_R : in STD_LOGIC_VECTOR ( 23 downto 0 );
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
end component week1_FILTER_IIR_0_1;
component week1_Volume_Pregain_0_1 is
port (
OUT_VOLCTRL_L : out STD_LOGIC_VECTOR ( 23 downto 0 );
OUT_VOLCTRL_R : out STD_LOGIC_VECTOR ( 23 downto 0 );
OUT_RDY : out STD_LOGIC;
IN_SIG_L : in STD_LOGIC_VECTOR ( 23 downto 0 );
IN_SIG_R : in STD_LOGIC_VECTOR ( 23 downto 0 );
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
end component week1_Volume_Pregain_0_1;
signal AC_GPIO1_1 : STD_LOGIC;
signal AC_GPIO2_1 : STD_LOGIC;
signal AC_GPIO3_1 : STD_LOGIC;
signal AXI_to_audio_0_audio_out_l : STD_LOGIC_VECTOR ( 23 downto 0 );
signal AXI_to_audio_0_audio_out_r : STD_LOGIC_VECTOR ( 23 downto 0 );
signal AXI_to_audio_0_audio_out_valid : STD_LOGIC;
signal AXI_to_audio_1_audio_out_l : STD_LOGIC_VECTOR ( 23 downto 0 );
signal AXI_to_audio_1_audio_out_r : STD_LOGIC_VECTOR ( 23 downto 0 );
signal FILTER_IIR_0_AUDIO_OUT_L : STD_LOGIC_VECTOR ( 23 downto 0 );
signal FILTER_IIR_0_AUDIO_OUT_R : STD_LOGIC_VECTOR ( 23 downto 0 );
signal FILTER_IIR_1_AUDIO_OUT_L : STD_LOGIC_VECTOR ( 23 downto 0 );
signal FILTER_IIR_1_AUDIO_OUT_R : STD_LOGIC_VECTOR ( 23 downto 0 );
signal GND_1 : STD_LOGIC;
signal Net : STD_LOGIC;
signal VCC_1 : STD_LOGIC;
signal Volume_Pregain_0_OUT_RDY : STD_LOGIC;
signal Volume_Pregain_0_OUT_VOLCTRL_L : STD_LOGIC_VECTOR ( 23 downto 0 );
signal Volume_Pregain_0_OUT_VOLCTRL_R : STD_LOGIC_VECTOR ( 23 downto 0 );
signal Volume_Pregain_1_OUT_RDY : STD_LOGIC;
signal Volume_Pregain_1_OUT_VOLCTRL_L : STD_LOGIC_VECTOR ( 23 downto 0 );
signal Volume_Pregain_1_OUT_VOLCTRL_R : STD_LOGIC_VECTOR ( 23 downto 0 );
signal audio_mixer_0_audio_mixed_a_b_left_out : STD_LOGIC_VECTOR ( 23 downto 0 );
signal audio_mixer_0_audio_mixed_a_b_right_out : STD_LOGIC_VECTOR ( 23 downto 0 );
signal audio_to_AXI_0_audio_out_valid_irq : STD_LOGIC;
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_BREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_BVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_RLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_RVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_WLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M02_AXI_ARADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_AWADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_ARADDR : STD_LOGIC_VECTOR ( 6 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_AWADDR : STD_LOGIC_VECTOR ( 6 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_ARADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_AWADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_ARADDR : STD_LOGIC_VECTOR ( 6 downto 0 );
signal processing_system7_0_axi_periph_M05_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M05_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_AWADDR : STD_LOGIC_VECTOR ( 6 downto 0 );
signal processing_system7_0_axi_periph_M05_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M05_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M05_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M05_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M05_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M05_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M05_AXI_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_ARADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M06_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M06_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_AWADDR : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M06_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_M06_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M06_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M06_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M06_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M06_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M06_AXI_WVALID : STD_LOGIC;
signal rst_processing_system7_0_100M_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_processing_system7_0_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 0 to 0 );
signal zed_audio_0_AC_ADR0 : STD_LOGIC;
signal zed_audio_0_AC_ADR1 : STD_LOGIC;
signal zed_audio_0_AC_GPIO0 : STD_LOGIC;
signal zed_audio_0_AC_MCLK : STD_LOGIC;
signal zed_audio_0_AC_SCK : STD_LOGIC;
signal zed_audio_0_line_in_l : STD_LOGIC_VECTOR ( 23 downto 0 );
signal zed_audio_0_line_in_r : STD_LOGIC_VECTOR ( 23 downto 0 );
signal zed_audio_0_new_sample : STD_LOGIC;
signal NLW_AXI_to_audio_1_audio_out_valid_UNCONNECTED : STD_LOGIC;
signal NLW_FILTER_IIR_0_FILTER_DONE_UNCONNECTED : STD_LOGIC;
signal NLW_FILTER_IIR_1_FILTER_DONE_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_rst_processing_system7_0_100M_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_rst_processing_system7_0_100M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_rst_processing_system7_0_100M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_zed_audio_0_sample_clk_48k_UNCONNECTED : STD_LOGIC;
begin
AC_ADR0 <= zed_audio_0_AC_ADR0;
AC_ADR1 <= zed_audio_0_AC_ADR1;
AC_GPIO0 <= zed_audio_0_AC_GPIO0;
AC_GPIO1_1 <= AC_GPIO1;
AC_GPIO2_1 <= AC_GPIO2;
AC_GPIO3_1 <= AC_GPIO3;
AC_MCLK <= zed_audio_0_AC_MCLK;
AC_SCK <= zed_audio_0_AC_SCK;
AXI_to_audio_0: component week1_AXI_to_audio_0_0
port map (
audio_in_valid_irq => xlconstant_0_dout(0),
audio_out_l(23 downto 0) => AXI_to_audio_0_audio_out_l(23 downto 0),
audio_out_r(23 downto 0) => AXI_to_audio_0_audio_out_r(23 downto 0),
audio_out_valid => AXI_to_audio_0_audio_out_valid,
s00_axi_aclk => processing_system7_0_FCLK_CLK0,
s00_axi_araddr(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARADDR(3 downto 0),
s00_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s00_axi_arprot(2 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARPROT(2 downto 0),
s00_axi_arready => processing_system7_0_axi_periph_M01_AXI_ARREADY,
s00_axi_arvalid => processing_system7_0_axi_periph_M01_AXI_ARVALID(0),
s00_axi_awaddr(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWADDR(3 downto 0),
s00_axi_awprot(2 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWPROT(2 downto 0),
s00_axi_awready => processing_system7_0_axi_periph_M01_AXI_AWREADY,
s00_axi_awvalid => processing_system7_0_axi_periph_M01_AXI_AWVALID(0),
s00_axi_bready => processing_system7_0_axi_periph_M01_AXI_BREADY(0),
s00_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_BRESP(1 downto 0),
s00_axi_bvalid => processing_system7_0_axi_periph_M01_AXI_BVALID,
s00_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_RDATA(31 downto 0),
s00_axi_rready => processing_system7_0_axi_periph_M01_AXI_RREADY(0),
s00_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_RRESP(1 downto 0),
s00_axi_rvalid => processing_system7_0_axi_periph_M01_AXI_RVALID,
s00_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_WDATA(31 downto 0),
s00_axi_wready => processing_system7_0_axi_periph_M01_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => processing_system7_0_axi_periph_M01_AXI_WVALID(0)
);
AXI_to_audio_1: component week1_AXI_to_audio_0_1
port map (
audio_in_valid_irq => xlconstant_0_dout(0),
audio_out_l(23 downto 0) => AXI_to_audio_1_audio_out_l(23 downto 0),
audio_out_r(23 downto 0) => AXI_to_audio_1_audio_out_r(23 downto 0),
audio_out_valid => NLW_AXI_to_audio_1_audio_out_valid_UNCONNECTED,
s00_axi_aclk => processing_system7_0_FCLK_CLK0,
s00_axi_araddr(3 downto 0) => processing_system7_0_axi_periph_M02_AXI_ARADDR(3 downto 0),
s00_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s00_axi_arprot(2 downto 0) => processing_system7_0_axi_periph_M02_AXI_ARPROT(2 downto 0),
s00_axi_arready => processing_system7_0_axi_periph_M02_AXI_ARREADY,
s00_axi_arvalid => processing_system7_0_axi_periph_M02_AXI_ARVALID,
s00_axi_awaddr(3 downto 0) => processing_system7_0_axi_periph_M02_AXI_AWADDR(3 downto 0),
s00_axi_awprot(2 downto 0) => processing_system7_0_axi_periph_M02_AXI_AWPROT(2 downto 0),
s00_axi_awready => processing_system7_0_axi_periph_M02_AXI_AWREADY,
s00_axi_awvalid => processing_system7_0_axi_periph_M02_AXI_AWVALID,
s00_axi_bready => processing_system7_0_axi_periph_M02_AXI_BREADY,
s00_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_BRESP(1 downto 0),
s00_axi_bvalid => processing_system7_0_axi_periph_M02_AXI_BVALID,
s00_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_RDATA(31 downto 0),
s00_axi_rready => processing_system7_0_axi_periph_M02_AXI_RREADY,
s00_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_RRESP(1 downto 0),
s00_axi_rvalid => processing_system7_0_axi_periph_M02_AXI_RVALID,
s00_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_WDATA(31 downto 0),
s00_axi_wready => processing_system7_0_axi_periph_M02_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M02_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => processing_system7_0_axi_periph_M02_AXI_WVALID
);
FILTER_IIR_0: component week1_FILTER_IIR_0_0
port map (
AUDIO_IN_L(23 downto 0) => Volume_Pregain_0_OUT_VOLCTRL_L(23 downto 0),
AUDIO_IN_R(23 downto 0) => Volume_Pregain_0_OUT_VOLCTRL_R(23 downto 0),
AUDIO_OUT_L(23 downto 0) => FILTER_IIR_0_AUDIO_OUT_L(23 downto 0),
AUDIO_OUT_R(23 downto 0) => FILTER_IIR_0_AUDIO_OUT_R(23 downto 0),
FILTER_DONE => NLW_FILTER_IIR_0_FILTER_DONE_UNCONNECTED,
SAMPLE_TRIG => Volume_Pregain_0_OUT_RDY,
s00_axi_aclk => processing_system7_0_FCLK_CLK0,
s00_axi_araddr(6 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARADDR(6 downto 0),
s00_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s00_axi_arprot(2 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARPROT(2 downto 0),
s00_axi_arready => processing_system7_0_axi_periph_M03_AXI_ARREADY,
s00_axi_arvalid => processing_system7_0_axi_periph_M03_AXI_ARVALID,
s00_axi_awaddr(6 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWADDR(6 downto 0),
s00_axi_awprot(2 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWPROT(2 downto 0),
s00_axi_awready => processing_system7_0_axi_periph_M03_AXI_AWREADY,
s00_axi_awvalid => processing_system7_0_axi_periph_M03_AXI_AWVALID,
s00_axi_bready => processing_system7_0_axi_periph_M03_AXI_BREADY,
s00_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_BRESP(1 downto 0),
s00_axi_bvalid => processing_system7_0_axi_periph_M03_AXI_BVALID,
s00_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_RDATA(31 downto 0),
s00_axi_rready => processing_system7_0_axi_periph_M03_AXI_RREADY,
s00_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_RRESP(1 downto 0),
s00_axi_rvalid => processing_system7_0_axi_periph_M03_AXI_RVALID,
s00_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_WDATA(31 downto 0),
s00_axi_wready => processing_system7_0_axi_periph_M03_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M03_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => processing_system7_0_axi_periph_M03_AXI_WVALID
);
FILTER_IIR_1: component week1_FILTER_IIR_0_1
port map (
AUDIO_IN_L(23 downto 0) => Volume_Pregain_1_OUT_VOLCTRL_L(23 downto 0),
AUDIO_IN_R(23 downto 0) => Volume_Pregain_1_OUT_VOLCTRL_R(23 downto 0),
AUDIO_OUT_L(23 downto 0) => FILTER_IIR_1_AUDIO_OUT_L(23 downto 0),
AUDIO_OUT_R(23 downto 0) => FILTER_IIR_1_AUDIO_OUT_R(23 downto 0),
FILTER_DONE => NLW_FILTER_IIR_1_FILTER_DONE_UNCONNECTED,
SAMPLE_TRIG => Volume_Pregain_1_OUT_RDY,
s00_axi_aclk => processing_system7_0_FCLK_CLK0,
s00_axi_araddr(6 downto 0) => processing_system7_0_axi_periph_M05_AXI_ARADDR(6 downto 0),
s00_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s00_axi_arprot(2 downto 0) => processing_system7_0_axi_periph_M05_AXI_ARPROT(2 downto 0),
s00_axi_arready => processing_system7_0_axi_periph_M05_AXI_ARREADY,
s00_axi_arvalid => processing_system7_0_axi_periph_M05_AXI_ARVALID,
s00_axi_awaddr(6 downto 0) => processing_system7_0_axi_periph_M05_AXI_AWADDR(6 downto 0),
s00_axi_awprot(2 downto 0) => processing_system7_0_axi_periph_M05_AXI_AWPROT(2 downto 0),
s00_axi_awready => processing_system7_0_axi_periph_M05_AXI_AWREADY,
s00_axi_awvalid => processing_system7_0_axi_periph_M05_AXI_AWVALID,
s00_axi_bready => processing_system7_0_axi_periph_M05_AXI_BREADY,
s00_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M05_AXI_BRESP(1 downto 0),
s00_axi_bvalid => processing_system7_0_axi_periph_M05_AXI_BVALID,
s00_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M05_AXI_RDATA(31 downto 0),
s00_axi_rready => processing_system7_0_axi_periph_M05_AXI_RREADY,
s00_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M05_AXI_RRESP(1 downto 0),
s00_axi_rvalid => processing_system7_0_axi_periph_M05_AXI_RVALID,
s00_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M05_AXI_WDATA(31 downto 0),
s00_axi_wready => processing_system7_0_axi_periph_M05_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M05_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => processing_system7_0_axi_periph_M05_AXI_WVALID
);
GND: unisim.vcomponents.GND
port map (
G => GND_1
);
VCC: unisim.vcomponents.VCC
port map (
P => VCC_1
);
Volume_Pregain_0: component week1_Volume_Pregain_0_0
port map (
IN_SIG_L(23 downto 0) => AXI_to_audio_0_audio_out_l(23 downto 0),
IN_SIG_R(23 downto 0) => AXI_to_audio_0_audio_out_r(23 downto 0),
OUT_RDY => Volume_Pregain_0_OUT_RDY,
OUT_VOLCTRL_L(23 downto 0) => Volume_Pregain_0_OUT_VOLCTRL_L(23 downto 0),
OUT_VOLCTRL_R(23 downto 0) => Volume_Pregain_0_OUT_VOLCTRL_R(23 downto 0),
s00_axi_aclk => processing_system7_0_FCLK_CLK0,
s00_axi_araddr(3 downto 0) => processing_system7_0_axi_periph_M04_AXI_ARADDR(3 downto 0),
s00_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s00_axi_arprot(2 downto 0) => processing_system7_0_axi_periph_M04_AXI_ARPROT(2 downto 0),
s00_axi_arready => processing_system7_0_axi_periph_M04_AXI_ARREADY,
s00_axi_arvalid => processing_system7_0_axi_periph_M04_AXI_ARVALID,
s00_axi_awaddr(3 downto 0) => processing_system7_0_axi_periph_M04_AXI_AWADDR(3 downto 0),
s00_axi_awprot(2 downto 0) => processing_system7_0_axi_periph_M04_AXI_AWPROT(2 downto 0),
s00_axi_awready => processing_system7_0_axi_periph_M04_AXI_AWREADY,
s00_axi_awvalid => processing_system7_0_axi_periph_M04_AXI_AWVALID,
s00_axi_bready => processing_system7_0_axi_periph_M04_AXI_BREADY,
s00_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M04_AXI_BRESP(1 downto 0),
s00_axi_bvalid => processing_system7_0_axi_periph_M04_AXI_BVALID,
s00_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M04_AXI_RDATA(31 downto 0),
s00_axi_rready => processing_system7_0_axi_periph_M04_AXI_RREADY,
s00_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M04_AXI_RRESP(1 downto 0),
s00_axi_rvalid => processing_system7_0_axi_periph_M04_AXI_RVALID,
s00_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M04_AXI_WDATA(31 downto 0),
s00_axi_wready => processing_system7_0_axi_periph_M04_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M04_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => processing_system7_0_axi_periph_M04_AXI_WVALID
);
Volume_Pregain_1: component week1_Volume_Pregain_0_1
port map (
IN_SIG_L(23 downto 0) => AXI_to_audio_1_audio_out_l(23 downto 0),
IN_SIG_R(23 downto 0) => AXI_to_audio_1_audio_out_r(23 downto 0),
OUT_RDY => Volume_Pregain_1_OUT_RDY,
OUT_VOLCTRL_L(23 downto 0) => Volume_Pregain_1_OUT_VOLCTRL_L(23 downto 0),
OUT_VOLCTRL_R(23 downto 0) => Volume_Pregain_1_OUT_VOLCTRL_R(23 downto 0),
s00_axi_aclk => processing_system7_0_FCLK_CLK0,
s00_axi_araddr(3 downto 0) => processing_system7_0_axi_periph_M06_AXI_ARADDR(3 downto 0),
s00_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s00_axi_arprot(2 downto 0) => processing_system7_0_axi_periph_M06_AXI_ARPROT(2 downto 0),
s00_axi_arready => processing_system7_0_axi_periph_M06_AXI_ARREADY,
s00_axi_arvalid => processing_system7_0_axi_periph_M06_AXI_ARVALID,
s00_axi_awaddr(3 downto 0) => processing_system7_0_axi_periph_M06_AXI_AWADDR(3 downto 0),
s00_axi_awprot(2 downto 0) => processing_system7_0_axi_periph_M06_AXI_AWPROT(2 downto 0),
s00_axi_awready => processing_system7_0_axi_periph_M06_AXI_AWREADY,
s00_axi_awvalid => processing_system7_0_axi_periph_M06_AXI_AWVALID,
s00_axi_bready => processing_system7_0_axi_periph_M06_AXI_BREADY,
s00_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M06_AXI_BRESP(1 downto 0),
s00_axi_bvalid => processing_system7_0_axi_periph_M06_AXI_BVALID,
s00_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M06_AXI_RDATA(31 downto 0),
s00_axi_rready => processing_system7_0_axi_periph_M06_AXI_RREADY,
s00_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M06_AXI_RRESP(1 downto 0),
s00_axi_rvalid => processing_system7_0_axi_periph_M06_AXI_RVALID,
s00_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M06_AXI_WDATA(31 downto 0),
s00_axi_wready => processing_system7_0_axi_periph_M06_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M06_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => processing_system7_0_axi_periph_M06_AXI_WVALID
);
audio_mixer_0: component week1_audio_mixer_0_0
port map (
audio_channel_a_left_in(23 downto 0) => FILTER_IIR_0_AUDIO_OUT_L(23 downto 0),
audio_channel_a_right_in(23 downto 0) => FILTER_IIR_0_AUDIO_OUT_R(23 downto 0),
audio_channel_b_left_in(23 downto 0) => FILTER_IIR_1_AUDIO_OUT_L(23 downto 0),
audio_channel_b_right_in(23 downto 0) => FILTER_IIR_1_AUDIO_OUT_R(23 downto 0),
audio_mixed_a_b_left_out(23 downto 0) => audio_mixer_0_audio_mixed_a_b_left_out(23 downto 0),
audio_mixed_a_b_right_out(23 downto 0) => audio_mixer_0_audio_mixed_a_b_right_out(23 downto 0)
);
audio_to_AXI_0: component week1_audio_to_AXI_0_1
port map (
audio_in_l(23 downto 0) => zed_audio_0_line_in_l(23 downto 0),
audio_in_r(23 downto 0) => zed_audio_0_line_in_r(23 downto 0),
audio_in_valid => zed_audio_0_new_sample,
audio_out_valid_irq => audio_to_AXI_0_audio_out_valid_irq,
s00_axi_aclk => processing_system7_0_FCLK_CLK0,
s00_axi_araddr(3 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(3 downto 0),
s00_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s00_axi_arprot(2 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARPROT(2 downto 0),
s00_axi_arready => processing_system7_0_axi_periph_M00_AXI_ARREADY,
s00_axi_arvalid => processing_system7_0_axi_periph_M00_AXI_ARVALID(0),
s00_axi_awaddr(3 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(3 downto 0),
s00_axi_awprot(2 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWPROT(2 downto 0),
s00_axi_awready => processing_system7_0_axi_periph_M00_AXI_AWREADY,
s00_axi_awvalid => processing_system7_0_axi_periph_M00_AXI_AWVALID(0),
s00_axi_bready => processing_system7_0_axi_periph_M00_AXI_BREADY(0),
s00_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
s00_axi_bvalid => processing_system7_0_axi_periph_M00_AXI_BVALID,
s00_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
s00_axi_rready => processing_system7_0_axi_periph_M00_AXI_RREADY(0),
s00_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
s00_axi_rvalid => processing_system7_0_axi_periph_M00_AXI_RVALID,
s00_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
s00_axi_wready => processing_system7_0_axi_periph_M00_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M00_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => processing_system7_0_axi_periph_M00_AXI_WVALID(0)
);
processing_system7_0: component week1_processing_system7_0_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
ENET0_PTP_DELAY_REQ_RX => NLW_processing_system7_0_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_DELAY_REQ_TX => NLW_processing_system7_0_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_RX => NLW_processing_system7_0_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_TX => NLW_processing_system7_0_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_RX => NLW_processing_system7_0_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_TX => NLW_processing_system7_0_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_RX => NLW_processing_system7_0_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_TX => NLW_processing_system7_0_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET0_SOF_RX => NLW_processing_system7_0_ENET0_SOF_RX_UNCONNECTED,
ENET0_SOF_TX => NLW_processing_system7_0_ENET0_SOF_TX_UNCONNECTED,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
IRQ_F2P(0) => audio_to_AXI_0_audio_out_valid_irq,
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
M_AXI_GP0_ARADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => processing_system7_0_M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => processing_system7_0_M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => processing_system7_0_M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => processing_system7_0_M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => processing_system7_0_M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => processing_system7_0_M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => processing_system7_0_M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => processing_system7_0_M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => processing_system7_0_M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => processing_system7_0_M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => processing_system7_0_M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => processing_system7_0_M_AXI_GP0_WVALID,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED,
TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED,
TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB0_VBUS_PWRFAULT => GND_1,
USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED
);
processing_system7_0_axi_periph: entity work.week1_processing_system7_0_axi_periph_0
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M00_AXI_araddr(3 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(3 downto 0),
M00_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARPROT(2 downto 0),
M00_AXI_arready(0) => processing_system7_0_axi_periph_M00_AXI_ARREADY,
M00_AXI_arvalid(0) => processing_system7_0_axi_periph_M00_AXI_ARVALID(0),
M00_AXI_awaddr(3 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(3 downto 0),
M00_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWPROT(2 downto 0),
M00_AXI_awready(0) => processing_system7_0_axi_periph_M00_AXI_AWREADY,
M00_AXI_awvalid(0) => processing_system7_0_axi_periph_M00_AXI_AWVALID(0),
M00_AXI_bready(0) => processing_system7_0_axi_periph_M00_AXI_BREADY(0),
M00_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid(0) => processing_system7_0_axi_periph_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
M00_AXI_rready(0) => processing_system7_0_axi_periph_M00_AXI_RREADY(0),
M00_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid(0) => processing_system7_0_axi_periph_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
M00_AXI_wready(0) => processing_system7_0_axi_periph_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid(0) => processing_system7_0_axi_periph_M00_AXI_WVALID(0),
M01_ACLK => processing_system7_0_FCLK_CLK0,
M01_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M01_AXI_araddr(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARADDR(3 downto 0),
M01_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARPROT(2 downto 0),
M01_AXI_arready(0) => processing_system7_0_axi_periph_M01_AXI_ARREADY,
M01_AXI_arvalid(0) => processing_system7_0_axi_periph_M01_AXI_ARVALID(0),
M01_AXI_awaddr(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWADDR(3 downto 0),
M01_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWPROT(2 downto 0),
M01_AXI_awready(0) => processing_system7_0_axi_periph_M01_AXI_AWREADY,
M01_AXI_awvalid(0) => processing_system7_0_axi_periph_M01_AXI_AWVALID(0),
M01_AXI_bready(0) => processing_system7_0_axi_periph_M01_AXI_BREADY(0),
M01_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_BRESP(1 downto 0),
M01_AXI_bvalid(0) => processing_system7_0_axi_periph_M01_AXI_BVALID,
M01_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_RDATA(31 downto 0),
M01_AXI_rready(0) => processing_system7_0_axi_periph_M01_AXI_RREADY(0),
M01_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_RRESP(1 downto 0),
M01_AXI_rvalid(0) => processing_system7_0_axi_periph_M01_AXI_RVALID,
M01_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_WDATA(31 downto 0),
M01_AXI_wready(0) => processing_system7_0_axi_periph_M01_AXI_WREADY,
M01_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_WSTRB(3 downto 0),
M01_AXI_wvalid(0) => processing_system7_0_axi_periph_M01_AXI_WVALID(0),
M02_ACLK => processing_system7_0_FCLK_CLK0,
M02_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M02_AXI_araddr(3 downto 0) => processing_system7_0_axi_periph_M02_AXI_ARADDR(3 downto 0),
M02_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_M02_AXI_ARPROT(2 downto 0),
M02_AXI_arready => processing_system7_0_axi_periph_M02_AXI_ARREADY,
M02_AXI_arvalid => processing_system7_0_axi_periph_M02_AXI_ARVALID,
M02_AXI_awaddr(3 downto 0) => processing_system7_0_axi_periph_M02_AXI_AWADDR(3 downto 0),
M02_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_M02_AXI_AWPROT(2 downto 0),
M02_AXI_awready => processing_system7_0_axi_periph_M02_AXI_AWREADY,
M02_AXI_awvalid => processing_system7_0_axi_periph_M02_AXI_AWVALID,
M02_AXI_bready => processing_system7_0_axi_periph_M02_AXI_BREADY,
M02_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_BRESP(1 downto 0),
M02_AXI_bvalid => processing_system7_0_axi_periph_M02_AXI_BVALID,
M02_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_RDATA(31 downto 0),
M02_AXI_rready => processing_system7_0_axi_periph_M02_AXI_RREADY,
M02_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_RRESP(1 downto 0),
M02_AXI_rvalid => processing_system7_0_axi_periph_M02_AXI_RVALID,
M02_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_WDATA(31 downto 0),
M02_AXI_wready => processing_system7_0_axi_periph_M02_AXI_WREADY,
M02_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M02_AXI_WSTRB(3 downto 0),
M02_AXI_wvalid => processing_system7_0_axi_periph_M02_AXI_WVALID,
M03_ACLK => processing_system7_0_FCLK_CLK0,
M03_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M03_AXI_araddr(6 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARADDR(6 downto 0),
M03_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARPROT(2 downto 0),
M03_AXI_arready => processing_system7_0_axi_periph_M03_AXI_ARREADY,
M03_AXI_arvalid => processing_system7_0_axi_periph_M03_AXI_ARVALID,
M03_AXI_awaddr(6 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWADDR(6 downto 0),
M03_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWPROT(2 downto 0),
M03_AXI_awready => processing_system7_0_axi_periph_M03_AXI_AWREADY,
M03_AXI_awvalid => processing_system7_0_axi_periph_M03_AXI_AWVALID,
M03_AXI_bready => processing_system7_0_axi_periph_M03_AXI_BREADY,
M03_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_BRESP(1 downto 0),
M03_AXI_bvalid => processing_system7_0_axi_periph_M03_AXI_BVALID,
M03_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_RDATA(31 downto 0),
M03_AXI_rready => processing_system7_0_axi_periph_M03_AXI_RREADY,
M03_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_RRESP(1 downto 0),
M03_AXI_rvalid => processing_system7_0_axi_periph_M03_AXI_RVALID,
M03_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_WDATA(31 downto 0),
M03_AXI_wready => processing_system7_0_axi_periph_M03_AXI_WREADY,
M03_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M03_AXI_WSTRB(3 downto 0),
M03_AXI_wvalid => processing_system7_0_axi_periph_M03_AXI_WVALID,
M04_ACLK => processing_system7_0_FCLK_CLK0,
M04_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M04_AXI_araddr(3 downto 0) => processing_system7_0_axi_periph_M04_AXI_ARADDR(3 downto 0),
M04_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_M04_AXI_ARPROT(2 downto 0),
M04_AXI_arready => processing_system7_0_axi_periph_M04_AXI_ARREADY,
M04_AXI_arvalid => processing_system7_0_axi_periph_M04_AXI_ARVALID,
M04_AXI_awaddr(3 downto 0) => processing_system7_0_axi_periph_M04_AXI_AWADDR(3 downto 0),
M04_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_M04_AXI_AWPROT(2 downto 0),
M04_AXI_awready => processing_system7_0_axi_periph_M04_AXI_AWREADY,
M04_AXI_awvalid => processing_system7_0_axi_periph_M04_AXI_AWVALID,
M04_AXI_bready => processing_system7_0_axi_periph_M04_AXI_BREADY,
M04_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M04_AXI_BRESP(1 downto 0),
M04_AXI_bvalid => processing_system7_0_axi_periph_M04_AXI_BVALID,
M04_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M04_AXI_RDATA(31 downto 0),
M04_AXI_rready => processing_system7_0_axi_periph_M04_AXI_RREADY,
M04_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M04_AXI_RRESP(1 downto 0),
M04_AXI_rvalid => processing_system7_0_axi_periph_M04_AXI_RVALID,
M04_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M04_AXI_WDATA(31 downto 0),
M04_AXI_wready => processing_system7_0_axi_periph_M04_AXI_WREADY,
M04_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M04_AXI_WSTRB(3 downto 0),
M04_AXI_wvalid => processing_system7_0_axi_periph_M04_AXI_WVALID,
M05_ACLK => processing_system7_0_FCLK_CLK0,
M05_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M05_AXI_araddr(6 downto 0) => processing_system7_0_axi_periph_M05_AXI_ARADDR(6 downto 0),
M05_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_M05_AXI_ARPROT(2 downto 0),
M05_AXI_arready => processing_system7_0_axi_periph_M05_AXI_ARREADY,
M05_AXI_arvalid => processing_system7_0_axi_periph_M05_AXI_ARVALID,
M05_AXI_awaddr(6 downto 0) => processing_system7_0_axi_periph_M05_AXI_AWADDR(6 downto 0),
M05_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_M05_AXI_AWPROT(2 downto 0),
M05_AXI_awready => processing_system7_0_axi_periph_M05_AXI_AWREADY,
M05_AXI_awvalid => processing_system7_0_axi_periph_M05_AXI_AWVALID,
M05_AXI_bready => processing_system7_0_axi_periph_M05_AXI_BREADY,
M05_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M05_AXI_BRESP(1 downto 0),
M05_AXI_bvalid => processing_system7_0_axi_periph_M05_AXI_BVALID,
M05_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M05_AXI_RDATA(31 downto 0),
M05_AXI_rready => processing_system7_0_axi_periph_M05_AXI_RREADY,
M05_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M05_AXI_RRESP(1 downto 0),
M05_AXI_rvalid => processing_system7_0_axi_periph_M05_AXI_RVALID,
M05_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M05_AXI_WDATA(31 downto 0),
M05_AXI_wready => processing_system7_0_axi_periph_M05_AXI_WREADY,
M05_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M05_AXI_WSTRB(3 downto 0),
M05_AXI_wvalid => processing_system7_0_axi_periph_M05_AXI_WVALID,
M06_ACLK => processing_system7_0_FCLK_CLK0,
M06_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M06_AXI_araddr(3 downto 0) => processing_system7_0_axi_periph_M06_AXI_ARADDR(3 downto 0),
M06_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_M06_AXI_ARPROT(2 downto 0),
M06_AXI_arready => processing_system7_0_axi_periph_M06_AXI_ARREADY,
M06_AXI_arvalid => processing_system7_0_axi_periph_M06_AXI_ARVALID,
M06_AXI_awaddr(3 downto 0) => processing_system7_0_axi_periph_M06_AXI_AWADDR(3 downto 0),
M06_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_M06_AXI_AWPROT(2 downto 0),
M06_AXI_awready => processing_system7_0_axi_periph_M06_AXI_AWREADY,
M06_AXI_awvalid => processing_system7_0_axi_periph_M06_AXI_AWVALID,
M06_AXI_bready => processing_system7_0_axi_periph_M06_AXI_BREADY,
M06_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M06_AXI_BRESP(1 downto 0),
M06_AXI_bvalid => processing_system7_0_axi_periph_M06_AXI_BVALID,
M06_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M06_AXI_RDATA(31 downto 0),
M06_AXI_rready => processing_system7_0_axi_periph_M06_AXI_RREADY,
M06_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M06_AXI_RRESP(1 downto 0),
M06_AXI_rvalid => processing_system7_0_axi_periph_M06_AXI_RVALID,
M06_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M06_AXI_WDATA(31 downto 0),
M06_AXI_wready => processing_system7_0_axi_periph_M06_AXI_WREADY,
M06_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M06_AXI_WSTRB(3 downto 0),
M06_AXI_wvalid => processing_system7_0_axi_periph_M06_AXI_WVALID,
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
S00_AXI_arid(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
S00_AXI_arlen(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
S00_AXI_arlock(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
S00_AXI_arprot(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
S00_AXI_arready => processing_system7_0_M_AXI_GP0_ARREADY,
S00_AXI_arsize(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
S00_AXI_arvalid => processing_system7_0_M_AXI_GP0_ARVALID,
S00_AXI_awaddr(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
S00_AXI_awid(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
S00_AXI_awlen(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
S00_AXI_awlock(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
S00_AXI_awprot(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
S00_AXI_awready => processing_system7_0_M_AXI_GP0_AWREADY,
S00_AXI_awsize(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
S00_AXI_awvalid => processing_system7_0_M_AXI_GP0_AWVALID,
S00_AXI_bid(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
S00_AXI_bready => processing_system7_0_M_AXI_GP0_BREADY,
S00_AXI_bresp(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
S00_AXI_bvalid => processing_system7_0_M_AXI_GP0_BVALID,
S00_AXI_rdata(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
S00_AXI_rid(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
S00_AXI_rlast => processing_system7_0_M_AXI_GP0_RLAST,
S00_AXI_rready => processing_system7_0_M_AXI_GP0_RREADY,
S00_AXI_rresp(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
S00_AXI_rvalid => processing_system7_0_M_AXI_GP0_RVALID,
S00_AXI_wdata(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
S00_AXI_wid(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
S00_AXI_wlast => processing_system7_0_M_AXI_GP0_WLAST,
S00_AXI_wready => processing_system7_0_M_AXI_GP0_WREADY,
S00_AXI_wstrb(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
S00_AXI_wvalid => processing_system7_0_M_AXI_GP0_WVALID
);
rst_processing_system7_0_100M: component week1_rst_processing_system7_0_100M_0
port map (
aux_reset_in => VCC_1,
bus_struct_reset(0) => NLW_rst_processing_system7_0_100M_bus_struct_reset_UNCONNECTED(0),
dcm_locked => VCC_1,
ext_reset_in => processing_system7_0_FCLK_RESET0_N,
interconnect_aresetn(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
mb_debug_sys_rst => GND_1,
mb_reset => NLW_rst_processing_system7_0_100M_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
peripheral_reset(0) => NLW_rst_processing_system7_0_100M_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => processing_system7_0_FCLK_CLK0
);
xlconstant_0: component week1_xlconstant_0_1
port map (
dout(0) => xlconstant_0_dout(0)
);
zed_audio_0: component week1_zed_audio_0_0
port map (
AC_ADR0 => zed_audio_0_AC_ADR0,
AC_ADR1 => zed_audio_0_AC_ADR1,
AC_GPIO0 => zed_audio_0_AC_GPIO0,
AC_GPIO1 => AC_GPIO1_1,
AC_GPIO2 => AC_GPIO2_1,
AC_GPIO3 => AC_GPIO3_1,
AC_MCLK => zed_audio_0_AC_MCLK,
AC_SCK => zed_audio_0_AC_SCK,
AC_SDA => AC_SDA,
clk_100 => processing_system7_0_FCLK_CLK0,
hphone_l(23 downto 0) => audio_mixer_0_audio_mixed_a_b_left_out(23 downto 0),
hphone_l_valid => AXI_to_audio_0_audio_out_valid,
hphone_r(23 downto 0) => audio_mixer_0_audio_mixed_a_b_right_out(23 downto 0),
hphone_r_valid_dummy => AXI_to_audio_0_audio_out_valid,
line_in_l(23 downto 0) => zed_audio_0_line_in_l(23 downto 0),
line_in_r(23 downto 0) => zed_audio_0_line_in_r(23 downto 0),
new_sample => zed_audio_0_new_sample,
sample_clk_48k => NLW_zed_audio_0_sample_clk_48k_UNCONNECTED
);
end STRUCTURE;
| lgpl-3.0 | f1fbabf9c91961ef7172e98e90c5c391 | 0.689183 | 2.820631 | false | false | false | false |
AfterRace/SoC_Project | vivado/project/project.srcs/sources_1/bd/week1/ip/week1_AXI_to_audio_0_1/synth/week1_AXI_to_audio_0_1.vhd | 1 | 8,913 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
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-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
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-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:AXI_to_audio:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY week1_AXI_to_audio_0_1 IS
PORT (
audio_out_l : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
audio_out_r : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
audio_out_valid : OUT STD_LOGIC;
audio_in_valid_irq : IN STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END week1_AXI_to_audio_0_1;
ARCHITECTURE week1_AXI_to_audio_0_1_arch OF week1_AXI_to_audio_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF week1_AXI_to_audio_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT AXI_to_audio_v1_0 IS
GENERIC (
C_S00_AXI_DATA_WIDTH : INTEGER; -- Width of S_AXI data bus
C_S00_AXI_ADDR_WIDTH : INTEGER -- Width of S_AXI address bus
);
PORT (
audio_out_l : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
audio_out_r : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
audio_out_valid : OUT STD_LOGIC;
audio_in_valid_irq : IN STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC
);
END COMPONENT AXI_to_audio_v1_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF week1_AXI_to_audio_0_1_arch: ARCHITECTURE IS "AXI_to_audio_v1_0,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF week1_AXI_to_audio_0_1_arch : ARCHITECTURE IS "week1_AXI_to_audio_0_1,AXI_to_audio_v1_0,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S00_AXI_RST RST";
BEGIN
U0 : AXI_to_audio_v1_0
GENERIC MAP (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 4
)
PORT MAP (
audio_out_l => audio_out_l,
audio_out_r => audio_out_r,
audio_out_valid => audio_out_valid,
audio_in_valid_irq => audio_in_valid_irq,
s00_axi_awaddr => s00_axi_awaddr,
s00_axi_awprot => s00_axi_awprot,
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => s00_axi_wdata,
s00_axi_wstrb => s00_axi_wstrb,
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => s00_axi_araddr,
s00_axi_arprot => s00_axi_arprot,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn
);
END week1_AXI_to_audio_0_1_arch;
| lgpl-3.0 | 840b1b7f173ab3f4192e00e1f8b052b5 | 0.702345 | 3.180942 | false | false | false | false |
peladex/RHD2132_FPGA | src/maquina_control/Maquina_de_control.vhd | 1 | 16,606 | LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
PACKAGE pk_Maquina_de_Control IS
COMPONENT Maquina_de_Control IS
PORT(
CLK : IN STD_LOGIC; --Reset activo por ALTO!
RESET : IN STD_LOGIC; -- @ff:No me gusta agrupar aca! jaja
--senales de trigger de funciones
reg_func_in : IN STD_LOGIC_VECTOR(7 downto 0);
reg_func_out : OUT STD_LOGIC_VECTOR(7 downto 0);
---- load_param
reg_load_param_1 : IN STD_LOGIC_VECTOR(15 downto 0); -- @ff: Salida del banco de registros con configuracion del chip 1
selec_load_param_1 : OUT STD_LOGIC_VECTOR(7 downto 0); -- @ff: Selector del banco de registros (18 registros) del chip 1
--send_command
reg_send_com_in : IN STD_LOGIC_VECTOR(15 downto 0);
--Senales de comunicacion con bloque convertidor a SPI
reg_envio_out : OUT STD_LOGIC_VECTOR(15 downto 0); -- Registro donde mando el comando pronto para enviar.
ack_in : IN STD_LOGIC; -- ACK de que llego el dato al convertidor SPI. LO CONSIDERO UN PULSO DE UN CLK
WE_out : OUT STD_LOGIC -- Senal de control que indica que esta pronto para enviar el dato
);
END COMPONENT;
END PACKAGE;
-----------------------------------------------------------
----- Primer nivel de maquina de estado
-----------------------------------------------------------
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY Maquina_de_Control IS
PORT(
CLK : IN STD_LOGIC; --Reset activo por ALTO!
RESET : IN STD_LOGIC; -- @ff:No me gusta agrupar aca! jaja
--senales de trigger de funciones
reg_func_in : IN STD_LOGIC_VECTOR(7 downto 0);
reg_func_out : OUT STD_LOGIC_VECTOR(7 downto 0);
---- load_param
reg_load_param_1 : IN STD_LOGIC_VECTOR(15 downto 0); -- @ff: Salida del banco de registros con configuracion del chip 1
selec_load_param_1 : OUT STD_LOGIC_VECTOR(7 downto 0); -- @ff: Selector del banco de registros (18 registros) del chip 1
--send_command
reg_send_com_in : IN STD_LOGIC_VECTOR(15 downto 0);
--Senales de comunicacion con bloque convertidor a SPI
reg_envio_out : OUT STD_LOGIC_VECTOR(15 downto 0); -- Registro donde mando el comando pronto para enviar.
ack_in : IN STD_LOGIC; -- ACK de que llego el dato al convertidor SPI. LO CONSIDERO UN PULSO DE UN CLK
WE_out : OUT STD_LOGIC; -- Senal de control que indica que esta pronto para enviar el dato
--- debug signals ---
dbg_cont_CLK : OUT STD_LOGIC_vector (7 downto 0);
dbg_cont_comand : OUT STD_LOGIC_vector (7 downto 0)
);
END Maquina_de_Control;
ARCHITECTURE func of Maquina_de_Control IS
constant cte_end_cont_CLK: integer := 14; --Constate que me indica el numero de pulsos final del ciclo de envio al SPI
constant cte_comando_dummy: std_logic_vector (15 downto 0):= X"0E80"; --Dummy: Read(40) --> 11RRRRRR00000000 --> 40d = 101000
signal sg_cont_CLK : STD_LOGIC_vector (7 downto 0);--:="00000"; -- @ff: No es necesario inicilizar
signal sg_cont_comand : STD_LOGIC_vector (7 downto 0);--:="00000"; -- @ff: Cambio a 8 bits por comodidad
--signal sg_proceso : STD_LOGIC:='0'; --Senal que me indica que estoy recorriendo una rama de la maquina de estados
signal sg_reg_envio_out : STD_LOGIC_VECTOR(15 downto 0);
-- Declaracion de estados
type state_type IS
(st_IDLE,
st_LOAD_PARAM, st_LOAD_PARAM_wren, st_LOAD_PARAM_waitACK, st_LOAD_PARAM_cuento,
st_START,
st_STOP,
st_SEND_COMMAND, st_SEND_COMMAND_wren, st_SEND_COMMAND_waitACK, st_SEND_COMMAND_cuento,
st_CALIBRATE); --st_GET_TEMP por el momento no lo pongo
attribute enum_encoding : string;
attribute enum_encoding of state_type : type is "one-hot"; -- @ff: hot hot hot
signal STATE, NXSTATE : state_type; -- @ff: inicializo con reset!! := st_IDLE; --Inicializo en IDLE
BEGIN
----------------------------------------------------------------------------------------------------------
---- MAQUINA DE ESTADOS ----------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------------
-- Proceso que asocia senales de salida a los estados
Maquina_de_estados:process (STATE, ack_in, reg_func_in, sg_cont_CLK, sg_cont_comand,reg_send_com_in )
begin
--reg_func_out <= "11111111"; -- @ff: Esto no tiene sentido aca adentro
--if sg_proceso='0' then -- @ff: Esto me parece que no se necesita, por ahora lo saco
-- case reg_func_in is -- @ff: Se diferencia primero segun el estado actual
case STATE is
----------------------------------------------------------------------------------------------------------
---- Estado PADRE/MADRE ----------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------------
when st_IDLE =>
case reg_func_in is -- @ff: Ahora si puedo saltar de estado segun el valor del registro
when X"00" => -- @ff: Lo pongo es hexa es mas entendible
NXSTATE <= st_IDLE;
--sg_proceso<='0';
when X"01" =>
NXSTATE <= st_LOAD_PARAM;
--sg_proceso<='1';
when X"02" =>
NXSTATE <= st_START;
--sg_proceso<='1';
when X"04" =>
NXSTATE <= st_STOP;
--sg_proceso<='1';
when X"08" =>
NXSTATE <= st_SEND_COMMAND;
--sg_proceso<='1';
when X"10" =>
NXSTATE <= st_CALIBRATE;
--sg_proceso<='1';
when others =>
NXSTATE <= st_IDLE; --En transiciones o casos no especificados vuelvo a idle
--sg_proceso<='0';
end case;
-- outputs
WE_out <= '0'; -- @ff: Las salidas tienen que tener valor en todos los estados sino las latchea!
--else --sg_proceso='1'
--case STATE is
----- @ff: Aca continua el case STATE inicial (agrego un estado) -----
----------------------------------------------------------------------------------------------------------
---- Rama SEND_COMMAND -----------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------------
-- @ff: Creo que no es sano cargar el dato a la salida al mismo tiempo que mandas
-- el wren. Tenes que mandar el wren por lo menos un flanco despues. Por esto
-- cargo el dato en el estado Idle y doy el wren en el siguiente estado.
--
-- Ademas, por lo que te dije de los contadores y los registros cambie un poco
-- la cosa. Es muy tentador hacer esto: "sg_cont_CLK <= "00000" pero asi nomas
-- no significa nada. Hay que definir los registros y demas, lo hago mas abajo.
-- @ff: Este estado me da el delay que necesito entre cargar el dato y el wren.
-- En este estado se reinicia el contador de comandos enviados.
when st_SEND_COMMAND =>
NXSTATE <= st_SEND_COMMAND_wren;
-- outputs
WE_out <= '0';
-- @ff: Este estado manda el pulso en WE_out
-- En este estado se reinicia el contador clocks
when st_SEND_COMMAND_wren =>
--reg_envio_out <= reg_send_com_in;
--sg_cont_CLK <= "00000"; -- Inicio los contadores
--sg_cont_comand <= "00000";
--if ack_in = '1' then -- Cuando llega ACK
-- NXSTATE <= st_SEND_COMMAND_cuento;
--else
-- NXSTATE <= st_SEND_COMMAND;
--end if;
NXSTATE <= st_SEND_COMMAND_waitACK;
-- outputs
WE_out <= '1';
-- @ff: Este estado espera por el ack del bloque spi. Si el ack que llega es el ultimo
-- entonces vuelve al estado IDLE.
when st_SEND_COMMAND_waitACK =>
if ack_in='1' then
if sg_cont_comand < 3 then -- Si me llega a contar y todavia no termine con los dummys vuelvo a contar
NXSTATE <= st_SEND_COMMAND_cuento;
else
NXSTATE <= st_IDLE; -- @ff: Para volver a idle alguien tiene que limpiar el contenido de reg_func_in
end if;
else -- ack_in='0' -- Espero hasta que llegue ACK
NXSTATE <= st_SEND_COMMAND_waitACK;
end if;
-- outputs
WE_out <= '0';
-- @ff: Este estado espera
-- En este estado se reinicia el contador clocks
when st_SEND_COMMAND_cuento =>
--sg_cont_CLK <= sg_cont_CLK + 1;
if (sg_cont_CLK < cte_end_cont_CLK) then --Si es menor a los CLKS q indica la cte sigo contando
NXSTATE <= st_SEND_COMMAND_cuento;
else
--sg_cont_comand <= sg_cont_comand + 1; -- Incremento el contador de datos enviados
NXSTATE <= st_SEND_COMMAND_wren;
end if;
-- outputs
WE_out <= '0';
-- when st_SEND_COMMAND_envio =>
-- reg_envio_out<= cte_comando_dummy; -- Envio el comando al registro de envio y reinicio el contador de CLK SPI
-- WE_out<='1';
-- if (ack_in='1')and (sg_cont_comand<2) then -- Si me llega a contar y todavia no termine con los dummys vuelvo a contar
-- NXSTATE <= st_SEND_COMMAND_cuento;
-- sg_cont_CLK<="00000";
-- elsif (ack_in='0')and (sg_cont_comand<2) then -- Espero hasta q me llegue el ACK
-- NXSTATE <= st_SEND_COMMAND_envio;
-- elsif (ack_in='1')and (sg_cont_comand=2) then -- Una vez haya mandado los dummys vuelvo a idle
-- NXSTATE <= st_idle;
-- reg_func_out<="00000000";
-- sg_proceso<='0';
-- else
-- NXSTATE <= st_SEND_COMMAND_envio;
-- end if;
----------------------------------------------------------------------------------------------------------
---- Rama st_LOAD_PARAM ----------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------------
when st_LOAD_PARAM =>
NXSTATE <= st_LOAD_PARAM_wren;
-- outputs
WE_out <= '0';
when st_LOAD_PARAM_wren =>
NXSTATE <= st_LOAD_PARAM_waitACK;
-- outputs
WE_out <= '1';
when st_LOAD_PARAM_waitACK =>
if ack_in='1' then
if sg_cont_comand < X"14" then
NXSTATE <= st_LOAD_PARAM_cuento;
else
NXSTATE <= st_IDLE;
end if;
else -- ack_in='0'
NXSTATE <= st_LOAD_PARAM_waitACK;
end if;
-- outputs
WE_out <= '0';
when st_LOAD_PARAM_cuento =>
if (sg_cont_CLK < cte_end_cont_CLK) then
NXSTATE <= st_LOAD_PARAM_cuento;
else
NXSTATE <= st_LOAD_PARAM_wren;
end if;
-- outputs
WE_out <= '0';
----------------------------------------------------------------------------------------------------------
---- Others ----------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------------
when others =>
NXSTATE <= st_IDLE;
-- outputs
WE_out <= '0';
--reg_func_out<= "00000001";
end case;
--end if;
end process;
-- Proceso que sincroniza los estados
sincronismo:process (clk, reset, STATE, NXSTATE)
begin
if reset = '1' then
STATE <= st_IDLE;
elsif clk'event and clk = '1' then
STATE <= NXSTATE;
end if;
end process;
--Boton de Reset -- @ff: Que es esto?
----------------------------------------------------------------------------------------------------------
---- Salidas -------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------------
reg_envio_out <= sg_reg_envio_out;
reg_func_out <= X"00"; -- @ff: Esto iria conectado al registro que guarda el valor de retorno del coamndo enviado, por ahora lo manod a cero.
-- @ff: Los registros estan ordenados del 0 al 17 y luego de enviar un comando se incrementa el contador
-- de comandos en uno. Por lo tanto el selector del comandos coincide con el contador de comandos.
selec_load_param_1 <= sg_cont_comand;
--- dbg ---
dbg_cont_CLK <= sg_cont_CLK;
dbg_cont_comand <= sg_cont_comand;
--- dbg ---
----------------------------------------------------------------------------------------------------------
---- registros -------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------------
-- Contador de flancos de reloj
p_cont_CLK : process (reset, clk, STATE)
begin
if reset = '1' then
sg_cont_CLK <= X"00";
elsif clk'event and clk = '1' then
if (STATE = st_SEND_COMMAND_wren) or (STATE = st_LOAD_PARAM_wren) then
sg_cont_CLK <= X"00";
elsif (STATE = st_SEND_COMMAND_cuento) or (STATE = st_LOAD_PARAM_cuento)then
sg_cont_CLK <= sg_cont_CLK + 1;
--elsif --otros estados en lsoq ue uso el contador...
end if;
end if;
end process;
-- Contador de comandos enviados
p_cont_comand : process (reset, clk, STATE)
begin
if reset = '1' then
sg_cont_comand <= X"00";
elsif clk'event and clk = '1' then
if (STATE = st_SEND_COMMAND) or (STATE = st_LOAD_PARAM) then
sg_cont_comand <= X"00";
elsif (STATE = st_SEND_COMMAND_wren) or (STATE = st_LOAD_PARAM_wren) then
sg_cont_comand <= sg_cont_comand + 1;
--elsif --otros estados en los que uso el contador...
end if;
end if;
end process;
-- Registro que guarda el comando a enviar
p_reg_envio_out : process (reset, clk, STATE, NXSTATE)
begin
if reset = '1' then
sg_reg_envio_out <= X"0000";
elsif clk'event and clk = '1' then
--- Send command ---
if (STATE = st_IDLE) and (reg_func_in = X"08") then
sg_reg_envio_out <= reg_send_com_in;
elsif (STATE = st_SEND_COMMAND_waitACK) and (ack_in = '1') then -- @ff: cargo el dummy antes de empezar a contar clks
sg_reg_envio_out <= cte_comando_dummy;
--- Load param ---
elsif (STATE = st_IDLE) and (reg_func_in = X"01") then
sg_reg_envio_out <= reg_load_param_1;
elsif (STATE = st_LOAD_PARAM_waitACK) and (ack_in = '1') and (sg_cont_comand < X"12") then
sg_reg_envio_out <= reg_load_param_1;
elsif (STATE = st_LOAD_PARAM_waitACK) and (ack_in = '1') and (sg_cont_comand >= X"11") then
sg_reg_envio_out <= cte_comando_dummy;
--elsif --otros estados en los que uso el registro...
end if;
end if;
end process;
end func;
| gpl-3.0 | 7fee26f751a55f3a9e6c199d6d854e21 | 0.46164 | 4.28874 | false | false | false | false |
UdayanSinha/Code_Blocks | VHDL/Projects/work/alu.vhd | 1 | 2,907 | LIBRARY IEEE; -- These lines informs the compiler that the library IEEE is used
USE IEEE.std_logic_1164.all; -- contains the definition for the std_logic type plus some useful conversion functions
ENTITY alu IS
GENERIC (size: INTEGER);
PORT(a, b: IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
ctrl: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q: OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0);
cout:OUT STD_LOGIC);
END alu;
architecture structural OF alu IS
--define building blocks of the ALU
COMPONENT nand_gate_busInput IS
GENERIC(size: INTEGER);
PORT (a:IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
b:IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
q:OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0));
END COMPONENT;
COMPONENT nor_gate_busInput IS
GENERIC(size: INTEGER);
PORT(a:IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
b:IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
q:OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0));
END COMPONENT;
COMPONENT add_subb IS
GENERIC(size: INTEGER);
PORT(a, b: IN STD_LOGIC_VECTOR(size-1 DOWNTO 0); --std_logic_vector defines array of 8 elements with indexed from 0 to 7; can use bit_vector as well
add_sub: IN STD_LOGIC;
cout: OUT STD_LOGIC;
sum: OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0));
END COMPONENT;
COMPONENT mux_2x1_busInput IS
GENERIC(size: INTEGER);
PORT(a, b: IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
ctrl: IN STD_LOGIC;
q: OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0));
END COMPONENT;
--define internal signals
SIGNAL i1, i2: STD_LOGIC_VECTOR(size-1 DOWNTO 0); --input signals
SIGNAL nand_result, nor_result, add_sub_result: STD_LOGIC_VECTOR(size-1 DOWNTO 0); --output of each block
SIGNAL carry: STD_LOGIC; --ALU cout
SIGNAL add_sub_select: STD_LOGIC; --addition subtraction selector
SIGNAL address: STD_LOGIC_VECTOR(1 DOWNTO 0); --ALU mux selector
SIGNAL mux1_out, mux2_out, mux3_out: STD_LOGIC_VECTOR(size-1 DOWNTO 0); --mux outputs
BEGIN
--define internal signal connections with I/O ports
i1<=a;
i2<=b;
cout<=carry;
address(1)<=ctrl(1);
address(0)<=ctrl(0);
add_sub_select<=NOT(address(1)) AND address(0);
q<=mux3_out;
--connect the blocks
NAND_UNIT: nand_gate_busInput GENERIC MAP(size) PORT MAP(a=>i1, b=>i2, q=>nand_result);
NOR_UNIT: nor_gate_busInput GENERIC MAP(size) PORT MAP(a=>i1, b=>i2, q=>nor_result);
ADD_SUB_UNIT: add_subb GENERIC MAP(size) PORT MAP(a=>i1, b=>i2, add_sub=>add_sub_select, cout=>carry, sum=>add_sub_result);
MUX1: mux_2x1_busInput GENERIC MAP(size) PORT MAP(a=>add_sub_result, b=>add_sub_result, ctrl=>address(0), q=>mux1_out);
MUX2: mux_2x1_busInput GENERIC MAP(size) PORT MAP(a=>nand_result, b=>nor_result, ctrl=>address(0), q=>mux2_out);
MUX3: mux_2x1_busInput GENERIC MAP(size) PORT MAP(a=>mux1_out, b=>mux2_out, ctrl=>address(1), q=>mux3_out);
end structural; | mit | f8f27d0e57768eb6428795d39f60aa68 | 0.672171 | 3.105769 | false | false | false | false |
dhmeves/ece-485 | ece-485-project-1/encoder_behav.vhd | 1 | 3,815 | library ieee;
use ieee.std_logic_1164.all;
entity encoder_behav is
port(
input : in std_logic_vector(5 downto 0);
output : out std_logic_vector(2 downto 0)
);
end entity encoder_behav;
architecture behav of encoder_behav is
begin
process(input)
begin
case input is
when "000001" => output <= "000";
when "000010" => output <= "001";
when "000100" => output <= "010";
when "001000" => output <= "011";
when "010000" => output <= "100";
when "100000" => output <= "101";
when others => output <= "XXX";
end case;
end process;
end behav;
library ieee;
use ieee.std_logic_1164.all;
entity encoder_behav_test_bench is
end encoder_behav_test_bench;
architecture behavior of encoder_behav_test_bench is
-- Component Declaration for the Encoder Behavioral Model Test Bench
component encoder_behav
port(
input : in std_logic_vector(5 downto 0);
output : out std_logic_vector(2 downto 0)
);
end component;
-- inputs
signal input : std_logic_vector(5 downto 0) := (others => '0');
-- outputs
signal output : std_logic_vector(2 downto 0);
begin
-- Instantiate the Encoder Test Bench
test_bench: encoder_behav port map (
input => input,
output => output
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 50 ns.
wait for 50 ns;
input <= "000000";
wait for 50 ns;
input <= "000001";
wait for 50 ns;
input <= "000010";
wait for 50 ns;
input <= "000011";
wait for 50 ns;
input <= "000100";
wait for 50 ns;
input <= "000101";
wait for 50 ns;
input <= "000110";
wait for 50 ns;
input <= "000111";
wait for 50 ns;
input <= "001000";
wait for 50 ns;
input <= "001001";
wait for 50 ns;
input <= "001010";
wait for 50 ns;
input <= "001011";
wait for 50 ns;
input <= "001100";
wait for 50 ns;
input <= "001101";
wait for 50 ns;
input <= "001110";
wait for 50 ns;
input <= "001111";
wait for 50 ns;
input <= "010000";
wait for 50 ns;
input <= "010001";
wait for 50 ns;
input <= "010010";
wait for 50 ns;
input <= "010011";
wait for 50 ns;
input <= "010100";
wait for 50 ns;
input <= "010101";
wait for 50 ns;
input <= "010110";
wait for 50 ns;
input <= "010111";
wait for 50 ns;
input <= "011000";
wait for 50 ns;
input <= "011001";
wait for 50 ns;
input <= "011010";
wait for 50 ns;
input <= "011011";
wait for 50 ns;
input <= "011100";
wait for 50 ns;
input <= "011101";
wait for 50 ns;
input <= "011110";
wait for 50 ns;
input <= "011111";
wait for 50 ns;
input <= "100000";
wait for 50 ns;
input <= "100001";
wait for 50 ns;
input <= "100010";
wait for 50 ns;
input <= "100011";
wait for 50 ns;
input <= "100100";
wait for 50 ns;
input <= "100101";
wait for 50 ns;
input <= "100110";
wait for 50 ns;
input <= "100111";
wait for 50 ns;
input <= "101000";
wait for 50 ns;
input <= "101001";
wait for 50 ns;
input <= "101010";
wait for 50 ns;
input <= "101011";
wait for 50 ns;
input <= "101100";
wait for 50 ns;
input <= "101101";
wait for 50 ns;
input <= "101110";
wait for 50 ns;
input <= "101111";
wait for 50 ns;
input <= "110000";
wait for 50 ns;
input <= "110001";
wait for 50 ns;
input <= "110010";
wait for 50 ns;
input <= "110011";
wait for 50 ns;
input <= "110100";
wait for 50 ns;
input <= "110101";
wait for 50 ns;
input <= "110110";
wait for 50 ns;
input <= "110111";
wait for 50 ns;
input <= "111000";
wait for 50 ns;
input <= "111001";
wait for 50 ns;
input <= "111010";
wait for 50 ns;
input <= "111011";
wait for 50 ns;
input <= "111100";
wait for 50 ns;
input <= "111101";
wait for 50 ns;
input <= "111110";
wait for 50 ns;
input <= "111111";
wait;
end process;
end; | gpl-3.0 | 39d72c5793010112f78a93f175a2de22 | 0.602883 | 2.90556 | false | false | false | false |
esar/hdmilight-v2 | fpga/ambilight.vhd | 1 | 18,127 | ----------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Stephen Robinson
--
-- This file is part of HDMI-Light
--
-- HDMI-Light is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- HDMI-Light is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file names COPING).
-- If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ambilight is
Port ( vidclk : in STD_LOGIC;
viddata_r : in STD_LOGIC_VECTOR (7 downto 0);
viddata_g : in STD_LOGIC_VECTOR (7 downto 0);
viddata_b : in STD_LOGIC_VECTOR (7 downto 0);
hblank : in STD_LOGIC;
vblank : in STD_LOGIC;
dataenable : in STD_LOGIC;
cfgclk : in STD_LOGIC;
cfgwe : in STD_LOGIC;
cfgaddr : in STD_LOGIC_VECTOR (15 downto 0);
cfgdatain : in STD_LOGIC_VECTOR (7 downto 0);
cfgdataout : out STD_LOGIC_VECTOR (7 downto 0);
output : out STD_LOGIC_VECTOR(7 downto 0);
formatChanged : out std_logic);
end ambilight;
architecture Behavioral of ambilight is
signal ce2 : std_logic;
signal ce4 : std_logic;
signal hblank_delayed : std_logic;
signal vblank_delayed : std_logic;
signal dataenable_delayed : std_logic;
signal ravg : std_logic_vector(7 downto 0);
signal gavg : std_logic_vector(7 downto 0);
signal bavg : std_logic_vector(7 downto 0);
signal lineBufferAddr : std_logic_vector(6 downto 0);
signal lineBufferData : std_logic_vector(23 downto 0);
signal yPos : std_logic_vector(5 downto 0);
signal lineReady : std_logic;
signal lightCfgWe : std_logic;
signal lightCfgAddr : std_logic_vector(11 downto 0);
signal lightCfgDin : std_logic_vector(7 downto 0);
signal lightCfgDout : std_logic_vector(7 downto 0);
signal resultAddr : std_logic_vector(7 downto 0);
signal resultData : std_logic_vector(31 downto 0);
signal resultLatched : std_logic_vector(31 downto 0);
signal resultCfgDout : std_logic_vector(7 downto 0);
signal statusLatched : std_logic_vector(7 downto 0);
signal vblank_cfgclk : std_logic_vector(1 downto 0);
signal vblanklast : std_logic;
signal startDistribution : std_logic;
signal delayedStartDistribution : std_logic;
signal delayedResultVblank : std_logic;
signal delayedResultAddr : std_logic_vector(7 downto 0);
signal delayedResultData : std_logic_vector(31 downto 0);
signal driverReady : std_logic_vector(7 downto 0);
signal driverStart : std_logic_vector(7 downto 0);
signal driverData : std_logic_vector(23 downto 0);
signal outputMapAddr : std_logic_vector(11 downto 0);
signal outputMapData : std_logic_vector(15 downto 0);
signal outputMapCfgWr : std_logic;
signal outputMapCfgAddr : std_logic_vector(12 downto 0);
signal outputMapCfgDin : std_logic_vector(7 downto 0);
signal outputMapCfgDout : std_logic_vector(7 downto 0);
signal areaResultR : std_logic_vector(7 downto 0);
signal areaResultG : std_logic_vector(7 downto 0);
signal areaResultB : std_logic_vector(7 downto 0);
signal colourCoefAddr : std_logic_vector(8 downto 0);
signal colourCoefData : std_logic_vector(63 downto 0);
signal colourCoefCfgWr : std_logic;
signal colourCoefCfgAddr : std_logic_vector(11 downto 0);
signal colourCoefCfgDin : std_logic_vector(7 downto 0);
signal colourCoefCfgDout : std_logic_vector(7 downto 0);
signal gammaTableRAddr : std_logic_vector(10 downto 0);
signal gammaTableRData : std_logic_vector(7 downto 0);
signal gammaTableRCfgWr : std_logic;
signal gammaTableRCfgAddr : std_logic_vector(10 downto 0);
signal gammaTableRCfgDin : std_logic_vector(7 downto 0);
signal gammaTableRCfgDout : std_logic_vector(7 downto 0);
signal gammaTableGAddr : std_logic_vector(10 downto 0);
signal gammaTableGData : std_logic_vector(7 downto 0);
signal gammaTableGCfgWr : std_logic;
signal gammaTableGCfgAddr : std_logic_vector(10 downto 0);
signal gammaTableGCfgDin : std_logic_vector(7 downto 0);
signal gammaTableGCfgDout : std_logic_vector(7 downto 0);
signal gammaTableBAddr : std_logic_vector(10 downto 0);
signal gammaTableBData : std_logic_vector(7 downto 0);
signal gammaTableBCfgWr : std_logic;
signal gammaTableBCfgAddr : std_logic_vector(10 downto 0);
signal gammaTableBCfgDin : std_logic_vector(7 downto 0);
signal gammaTableBCfgDout : std_logic_vector(7 downto 0);
signal resultDelayCfgAddr : std_logic_vector(2 downto 0);
signal resultDelayCfgDin : std_logic_vector(7 downto 0);
signal resultDelayCfgDout : std_logic_vector(7 downto 0);
signal resultDelayCfgWe : std_logic;
signal resultDelayFrameCount : std_logic_vector(7 downto 0);
signal resultDelayTickCount : std_logic_vector(23 downto 0);
signal resultDelayTemporalSmoothingRatio : std_logic_vector(8 downto 0);
signal formatCfgDout : std_logic_vector( 7 downto 0);
signal formatXSize : std_logic_vector(11 downto 0);
signal formatXPreActive : std_logic_vector(11 downto 0);
signal formatXPostActive : std_logic_vector(11 downto 0);
signal formatYSize : std_logic_vector(10 downto 0);
signal formatYPreActive : std_logic_vector(10 downto 0);
signal formatYPostActive : std_logic_vector(10 downto 0);
signal storeResult : std_logic;
signal storeResultDelayed : std_logic;
signal resultLatchAddr : std_logic_vector(31 downto 0);
signal delayedResultLatched : std_logic_vector(31 downto 0);
signal driverResultLatched : std_logic_vector(31 downto 0);
signal resultCfgWe : std_logic;
signal cfgArea : std_logic;
signal cfgOutput : std_logic;
signal cfgCoef : std_logic;
signal cfgGammaR : std_logic;
signal cfgGammaG : std_logic;
signal cfgGammaB : std_logic;
signal cfgResult : std_logic;
signal cfgStatus : std_logic;
signal cfgDelay : std_logic;
signal cfgFormat : std_logic;
signal cfgVect : std_logic_vector(9 downto 0);
signal disabledOutput : std_logic_vector(7 downto 0);
begin
hscale4 : entity work.hscale4 port map(vidclk, hblank, vblank, dataenable, viddata_r, viddata_g, viddata_b,
hblank_delayed, vblank_delayed, dataenable_delayed, ce2, ce4, ravg, gavg, bavg);
scaler : entity work.scaler port map(vidclk, ce2, dataenable_delayed, vblank_delayed, ravg, gavg, bavg,
lineBufferAddr, lineBufferData, lineReady, yPos);
lightAverager : entity work.lightAverager port map(vidclk, ce2, lineReady, yPos,
lineBufferAddr, lineBufferData,
cfgclk, lightCfgWe, lightCfgAddr, lightCfgDin, lightCfgDout,
cfgclk, resultAddr, resultData);
formatDetector : entity work.formatDetector port map(vidclk, ce2, hblank_delayed, vblank_delayed, dataenable_delayed, ravg, gavg, bavg,
cfgclk, x"10",
formatXSize, formatXPreActive, formatXPostActive,
formatYSize, formatYPreActive, formatYPostActive,
formatChanged);
process(cfgclk)
begin
if(rising_edge(cfgclk)) then
vblank_cfgclk <= vblank_cfgclk(0) & vblank;
end if;
end process;
process(cfgclk)
begin
if(rising_edge(cfgclk)) then
startDistribution <= '0';
if(vblank_cfgclk(1) = '1' and vblanklast = '0') then
startDistribution <= '1';
end if;
vblanklast <= vblank_cfgclk(1);
end if;
end process;
resultDelay : entity work.resultDelay port map(cfgclk,
startDistribution, resultAddr, resultData,
delayedStartDistribution, delayedResultAddr, delayedResultData,
resultDelayFrameCount, resultDelayTickCount, resultDelayTemporalSmoothingRatio);
areaResultR <= delayedResultData(23 downto 16);
areaResultG <= delayedResultData(15 downto 8);
areaResultB <= delayedResultData(7 downto 0);
resultDistributor : entity work.resultDistributor port map(
cfgclk, delayedStartDistribution,
driverReady, driverStart, driverData,
outputMapAddr, outputMapData,
delayedResultAddr, areaResultR, areaResultG, areaResultB,
colourCoefAddr, colourCoefData,
gammaTableRAddr, gammaTableRData,
gammaTableGAddr, gammaTableGData,
gammaTableBAddr, gammaTableBData
);
ws2811Driver0 : entity work.ws2811Driver port map(cfgclk, driverReady(0), driverStart(0), driverData, output(0));
ws2811Driver1 : entity work.ws2811Driver port map(cfgclk, driverReady(1), driverStart(1), driverData, output(1));
ws2811Driver2 : entity work.ws2811Driver port map(cfgclk, driverReady(2), driverStart(2), driverData, output(2));
ws2811Driver3 : entity work.ws2811Driver port map(cfgclk, driverReady(3), driverStart(3), driverData, output(3));
ws2811Driver4 : entity work.ws2811Driver port map(cfgclk, driverReady(4), driverStart(4), driverData, output(4));
ws2811Driver5 : entity work.ws2811Driver port map(cfgclk, driverReady(5), driverStart(5), driverData, output(5));
ws2811Driver6 : entity work.ws2811Driver port map(cfgclk, driverReady(6), driverStart(6), driverData, output(6));
ws2811Driver7 : entity work.ws2811Driver port map(cfgclk, driverReady(7), driverStart(7), driverData, output(7));
--output(0) <= delayedStartDistribution;
--output(1) <= startDistribution;
--output(2) <= vblank;
--output(3) <= hblank;
--output(4) <= dataenable;
--output(5) <= '1';
outputMapRam : entity work.outputconfigRam
port map(
a_clk => cfgclk,
a_wr => outputMapCfgWr,
a_addr => outputMapCfgAddr,
a_din => outputMapCfgDin,
a_dout => outputMapCfgDout,
b_clk => cfgclk,
b_addr => outputMapAddr,
b_data => outputMapData
);
colourCoefRam : entity work.colourTransformerConfigRam PORT MAP(
a_clk => cfgclk,
a_wr => colourCoefCfgWr,
a_addr => colourCoefCfgAddr,
a_din => colourCoefCfgDin,
a_dout => colourCoefCfgDout,
b_clk => cfgclk,
b_addr => colourCoefAddr,
b_data => colourCoefData
);
gammaTableRRam : entity work.blockram
generic map(
DATA => 8,
ADDR => 11
)
port map(
a_clk => cfgclk,
a_en => '1',
a_wr => gammaTableRCfgWr,
a_rst => '0',
a_addr => gammaTableRCfgAddr,
a_din => gammaTableRCfgDin,
a_dout => gammaTableRCfgDout,
b_clk => cfgclk,
b_en => '1',
b_wr => '0',
b_rst => '0',
b_addr => gammaTableRAddr,
b_din => (others => '0'),
b_dout => gammaTableRData
);
gammaTableGRam : entity work.blockram
generic map(
DATA => 8,
ADDR => 11
)
port map(
a_clk => cfgclk,
a_en => '1',
a_wr => gammaTableGCfgWr,
a_rst => '0',
a_addr => gammaTableGCfgAddr,
a_din => gammaTableGCfgDin,
a_dout => gammaTableGCfgDout,
b_clk => cfgclk,
b_en => '1',
b_wr => '0',
b_rst => '0',
b_addr => gammaTableGAddr,
b_din => (others => '0'),
b_dout => gammaTableGData
);
gammaTableBRam : entity work.blockram
generic map(
DATA => 8,
ADDR => 11
)
port map(
a_clk => cfgclk,
a_en => '1',
a_wr => gammaTableBCfgWr,
a_rst => '0',
a_addr => gammaTableBCfgAddr,
a_din => gammaTableBCfgDin,
a_dout => gammaTableBCfgDout,
b_clk => cfgclk,
b_en => '1',
b_wr => '0',
b_rst => '0',
b_addr => gammaTableBAddr,
b_din => (others => '0'),
b_dout => gammaTableBData
);
resultDelayRegisters : entity work.resultDelayRegisters
port map(
clk => cfgclk,
addr => resultDelayCfgAddr,
din => resultDelayCfgDin,
dout => resultDelayCfgDout,
we => resultDelayCfgWe,
frameCount => resultDelayFrameCount,
tickCount => resultDelayTickCount,
temporalSmoothingRatio => resultDelayTemporalSmoothingRatio
);
process(cfgclk)
begin
if(rising_edge(cfgclk)) then
storeResult <= '0';
storeResultDelayed <= '0';
if(resultAddr = resultLatchAddr(7 downto 0)) then
storeResult <= '1';
end if;
if(delayedResultAddr = resultLatchAddr(7 downto 0)) then
storeResultDelayed <= '1';
end if;
end if;
end process;
process(cfgclk)
begin
if(rising_edge(cfgclk)) then
statusLatched <= "000000" & hblank & vblank;
if(storeResult = '1') then
resultLatched <= resultData;
end if;
if(storeResultDelayed = '1') then
delayedResultLatched <= delayedResultData;
end if;
if(outputMapAddr = resultLatchAddr(11 downto 0) and driverStart /= "00000000") then
driverResultLatched <= "00000000" & driverData;
end if;
end if;
end process;
process(cfgclk)
begin
if(rising_edge(cfgclk)) then
if(resultCfgWe = '1') then
if(cfgaddr(10 downto 0) = "00000000000") then
resultLatchAddr(7 downto 0) <= cfgdatain;
elsif(cfgaddr(10 downto 0) = "00000000001") then
resultLatchAddr(15 downto 8) <= cfgdatain;
end if;
end if;
end if;
end process;
with cfgaddr(3 downto 0) select resultCfgDout <=
resultLatchAddr( 7 downto 0) when "0000",
resultLatchAddr(15 downto 8) when "0001",
"00000000" when "0010",
"00000000" when "0011",
resultLatched(7 downto 0) when "0100",
resultLatched(15 downto 8) when "0101",
resultLatched(23 downto 16) when "0110",
resultLatched(31 downto 24) when "0111",
delayedResultLatched( 7 downto 0) when "1000",
delayedResultLatched(15 downto 8) when "1001",
delayedResultLatched(23 downto 16) when "1010",
delayedResultLatched(31 downto 24) when "1011",
driverResultLatched( 7 downto 0) when "1100",
driverResultLatched(15 downto 8) when "1101",
driverResultLatched(23 downto 16) when "1110",
driverResultLatched(31 downto 24) when "1111";
with cfgaddr(3 downto 0) select formatCfgDout <=
formatXSize( 7 downto 0) when "0000",
"0000" & formatXSize(11 downto 8) when "0001",
formatXPreActive( 7 downto 0) when "0010",
"0000" & formatXPreActive(11 downto 8) when "0011",
formatXPostActive( 7 downto 0) when "0100",
"0000" & formatXPostActive(11 downto 8) when "0101",
formatYSize( 7 downto 0) when "0110",
"00000" & formatYSize(10 downto 8) when "0111",
formatYPreActive( 7 downto 0) when "1000",
"00000" & formatYPreActive(10 downto 8) when "1001",
formatYPostActive( 7 downto 0) when "1010",
"00000" & formatYPostActive(10 downto 8) when "1011",
"00000000" when others;
cfgOutput <= '1' when cfgaddr(15 downto 11) = "00000" or -- 0x0000 - 0x1FFF
cfgaddr(15 downto 11) = "00001" or
cfgaddr(15 downto 11) = "00010" or
cfgaddr(15 downto 11) = "00011" else '0';
cfgCoef <= '1' when cfgaddr(15 downto 11) = "00100" or -- 0x2000 - 0x2FFF
cfgaddr(15 downto 11) = "00101" else '0';
cfgArea <= '1' when cfgaddr(15 downto 11) = "00110" or -- 0x3000 - 0x3FFF
cfgaddr(15 downto 11) = "00111" else '0';
cfgGammaR <= '1' when cfgaddr(15 downto 11) = "01000" else '0'; -- 0x4000 - 0x47FF
cfgGammaG <= '1' when cfgaddr(15 downto 11) = "01001" else '0'; -- 0x4800 - 0x4FFF
cfgGammaB <= '1' when cfgaddr(15 downto 11) = "01010" else '0'; -- 0x5000 - 0x57FF
cfgResult <= '1' when cfgaddr(15 downto 11) = "01011" else '0'; -- 0x5800 - 0x5FFF
cfgStatus <= '1' when cfgaddr(15 downto 11) = "01100" else '0'; -- 0x6000 - 0x67FF
cfgDelay <= '1' when cfgaddr(15 downto 3) = "0110100000000" else '0'; -- 0x6800 - 0x6FFF
cfgFormat <= '1' when cfgaddr(15 downto 11) = "01110" else '0'; -- 0x7000 - 0x77FF
cfgVect <= cfgOutput & cfgCoef & cfgArea & cfgGammaR & cfgGammaG & cfgGammaB & cfgResult & cfgStatus & cfgDelay & cfgFormat;
with cfgVect select cfgdataout <=
outputMapCfgDout when "1000000000",
colourCoefCfgDout when "0100000000",
lightCfgDout when "0010000000",
gammaTableRCfgDout when "0001000000",
gammaTableGCfgDout when "0000100000",
gammaTableBCfgDout when "0000010000",
resultCfgDout when "0000001000",
statusLatched when "0000000100",
resultDelayCfgDout when "0000000010",
formatCfgDout when "0000000001",
"00000000" when others;
outputMapCfgWr <= cfgwe when cfgOutput = '1' else '0';
colourCoefCfgWr <= cfgwe when cfgCoef = '1' else '0';
lightCfgWe <= cfgwe when cfgArea = '1' else '0';
gammaTableRCfgWr <= cfgwe when cfgGammaR = '1' else '0';
gammaTableGCfgWr <= cfgwe when cfgGammaG = '1' else '0';
gammaTableBCfgWr <= cfgwe when cfgGammaB = '1' else '0';
resultDelayCfgWe <= cfgwe when cfgDelay = '1' else '0';
resultCfgWe <= cfgwe when cfgResult = '1' else '0';
outputMapCfgDin <= cfgdatain;
colourCoefCfgDin <= cfgdatain;
lightCfgDin <= cfgdatain;
gammaTableRCfgDin <= cfgdatain;
gammaTableGCfgDin <= cfgdatain;
gammaTableBCfgDin <= cfgdatain;
resultDelayCfgDin <= cfgdatain;
outputMapCfgAddr <= cfgaddr(12 downto 0);
colourCoefCfgAddr <= cfgaddr(11 downto 0);
lightCfgAddr <= cfgaddr(11 downto 0);
gammaTableRCfgAddr <= cfgaddr(10 downto 0);
gammaTableGCfgAddr <= cfgaddr(10 downto 0);
gammaTableBCfgAddr <= cfgaddr(10 downto 0);
resultDelayCfgAddr <= cfgaddr(2 downto 0);
end Behavioral;
| gpl-2.0 | bf402efb626c79e71d8cc6684f2c54ca | 0.666409 | 3.618886 | false | false | false | false |
freecores/gpib_controller | vhdl/test/RegsGpibFasade_test.vhd | 1 | 7,222 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Author: Andrzej Paluch
--
-- Create Date: 16:22:23 02/04/2012
-- Design Name:
-- Module Name: RegsGpibFasade_test.vhd
-- Project Name: proto1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: RegsGpibFasade
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
use work.wrapperComponents.ALL;
ENTITY RegsGpibFasade_test IS
END RegsGpibFasade_test;
ARCHITECTURE behavior OF RegsGpibFasade_test IS
component gpibCableEmulator is port (
-- interface signals
DIO_1 : in std_logic_vector (7 downto 0);
output_valid_1 : in std_logic;
DIO_2 : in std_logic_vector (7 downto 0);
output_valid_2 : in std_logic;
DIO : out std_logic_vector (7 downto 0);
-- attention
ATN_1 : in std_logic;
ATN_2 : in std_logic;
ATN : out std_logic;
-- data valid
DAV_1 : in std_logic;
DAV_2 : in std_logic;
DAV : out std_logic;
-- not ready for data
NRFD_1 : in std_logic;
NRFD_2 : in std_logic;
NRFD : out std_logic;
-- no data accepted
NDAC_1 : in std_logic;
NDAC_2 : in std_logic;
NDAC : out std_logic;
-- end or identify
EOI_1 : in std_logic;
EOI_2 : in std_logic;
EOI : out std_logic;
-- service request
SRQ_1 : in std_logic;
SRQ_2 : in std_logic;
SRQ : out std_logic;
-- interface clear
IFC_1 : in std_logic;
IFC_2 : in std_logic;
IFC : out std_logic;
-- remote enable
REN_1 : in std_logic;
REN_2 : in std_logic;
REN : out std_logic
);
end component;
--Inputs
signal reset : std_logic := '0';
signal clk : std_logic := '0';
signal DI : std_logic_vector(7 downto 0) := (others => '0');
signal ATN_in : std_logic := '0';
signal DAV_in : std_logic := '0';
signal NRFD_in : std_logic := '0';
signal NDAC_in : std_logic := '0';
signal EOI_in : std_logic := '0';
signal SRQ_in : std_logic := '0';
signal IFC_in : std_logic := '0';
signal REN_in : std_logic := '0';
signal data_in : std_logic_vector(15 downto 0) := (others => '0');
signal reg_addr : std_logic_vector(14 downto 0) := (others => '0');
signal strobe_read : std_logic := '0';
signal strobe_write : std_logic := '0';
--Outputs
signal DO : std_logic_vector(7 downto 0);
signal output_valid : std_logic;
signal ATN_out : std_logic;
signal DAV_out : std_logic;
signal NRFD_out : std_logic;
signal NDAC_out : std_logic;
signal EOI_out : std_logic;
signal SRQ_out : std_logic;
signal IFC_out : std_logic;
signal REN_out : std_logic;
signal data_out : std_logic_vector(15 downto 0);
signal interrupt_line : std_logic;
signal debug1 : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: RegsGpibFasade PORT MAP (
reset => reset,
clk => clk,
DI => DI,
DO => DO,
output_valid => output_valid,
ATN_in => ATN_in,
ATN_out => ATN_out,
DAV_in => DAV_in,
DAV_out => DAV_out,
NRFD_in => NRFD_in,
NRFD_out => NRFD_out,
NDAC_in => NDAC_in,
NDAC_out => NDAC_out,
EOI_in => EOI_in,
EOI_out => EOI_out,
SRQ_in => SRQ_in,
SRQ_out => SRQ_out,
IFC_in => IFC_in,
IFC_out => IFC_out,
REN_in => REN_in,
REN_out => REN_out,
data_in => data_in,
data_out => data_out,
reg_addr => reg_addr,
strobe_read => strobe_read,
strobe_write => strobe_write,
interrupt_line => interrupt_line,
debug1 => debug1
);
gce: gpibCableEmulator port map (
-- interface signals
DIO_1 => DO,
output_valid_1 => output_valid,
DIO_2 => "00000000",
output_valid_2 => '0',
DIO => DI,
-- attention
ATN_1 => ATN_out,
ATN_2 => '0',
ATN => ATN_in,
-- data valid
DAV_1 => DAV_out,
DAV_2 => '0',
DAV => DAV_in,
-- not ready for data
NRFD_1 => NRFD_out,
NRFD_2 => '0',
NRFD => NRFD_in,
-- no data accepted
NDAC_1 => NDAC_out,
NDAC_2 => '0',
NDAC => NDAC_in,
-- end or identify
EOI_1 => EOI_out,
EOI_2 => '0',
EOI => EOI_in,
-- service request
SRQ_1 => SRQ_out,
SRQ_2 => '0',
SRQ => SRQ_in,
-- interface clear
IFC_1 => IFC_out,
IFC_2 => '0',
IFC => IFC_in,
-- remote enable
REN_1 => REN_out,
REN_2 => '0',
REN => REN_in
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process begin
-- hold reset state for 10 clock cycles
reset <= '1';
wait for clk_period*10;
reset <= '0';
wait for clk_period*10;
-- set rsc
reg_addr <= "000000000000111";
data_in <= "0000000001000000";
wait for clk_period*2;
strobe_write <= '1';
wait for clk_period*2;
strobe_write <= '0';
wait for clk_period*20;
-- set sic
data_in <= "0000000011000000";
wait for clk_period*2;
strobe_write <= '1';
wait for clk_period*2;
strobe_write <= '0';
wait for clk_period*20;
-- reset sic
data_in <= "0000000001000000";
wait for clk_period*2;
strobe_write <= '1';
wait for clk_period*2;
strobe_write <= '0';
wait for clk_period*20;
-- enable writer
reg_addr <= "000000000001010";
data_in <= "0000000000000010";
wait for clk_period*2;
strobe_write <= '1';
wait for clk_period*2;
strobe_write <= '0';
-- self address to listen
reg_addr <= "000000000001101";
data_in <= "0000000000100001";
wait for clk_period*2;
strobe_write <= '1';
wait for clk_period*2;
strobe_write <= '0';
-- self address to listen again
reg_addr <= "000000000001101";
data_in <= "0000000000100011";
wait for clk_period*2;
strobe_write <= '1';
wait for clk_period*2;
strobe_write <= '0';
wait for clk_period*10;
wait;
end process;
END;
| gpl-3.0 | 521af91f47c75eca08ca947b3c19b021 | 0.612296 | 3.092934 | false | false | false | false |
freecores/gpib_controller | vhdl/test/gpibReaderTest.vhd | 1 | 12,210 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Author: Andrzej Paluch
--
-- Create Date: 23:21:05 10/21/2011
-- Design Name:
-- Module Name: /windows/h/projekty/elektronika/USB_to_HPIB/usbToHpib/test_scr//gpibInterfaceTest.vhd
-- Project Name: usbToHpib
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: gpibInterface
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use work.gpibComponents.all;
use work.helperComponents.all;
ENTITY gpibReaderTest IS
END gpibReaderTest;
ARCHITECTURE behavior OF gpibReaderTest IS
-- Component Declaration for the Unit Under Test (UUT)
component gpibCableEmulator is port (
-- interface signals
DIO_1 : in std_logic_vector (7 downto 0);
output_valid_1 : in std_logic;
DIO_2 : in std_logic_vector (7 downto 0);
output_valid_2 : in std_logic;
DIO : out std_logic_vector (7 downto 0);
-- attention
ATN_1 : in std_logic;
ATN_2 : in std_logic;
ATN : out std_logic;
-- data valid
DAV_1 : in std_logic;
DAV_2 : in std_logic;
DAV : out std_logic;
-- not ready for data
NRFD_1 : in std_logic;
NRFD_2 : in std_logic;
NRFD : out std_logic;
-- no data accepted
NDAC_1 : in std_logic;
NDAC_2 : in std_logic;
NDAC : out std_logic;
-- end or identify
EOI_1 : in std_logic;
EOI_2 : in std_logic;
EOI : out std_logic;
-- service request
SRQ_1 : in std_logic;
SRQ_2 : in std_logic;
SRQ : out std_logic;
-- interface clear
IFC_1 : in std_logic;
IFC_2 : in std_logic;
IFC : out std_logic;
-- remote enable
REN_1 : in std_logic;
REN_2 : in std_logic;
REN : out std_logic
);
end component;
-- inputs common
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal T1 : std_logic_vector(7 downto 0) := "00000100";
-- inputs 1
signal data_1 : std_logic_vector(7 downto 0) := (others => '0');
signal status_byte_1 : std_logic_vector(7 downto 0) := (others => '0');
signal rdy_1 : std_logic := '0';
signal nba_1 : std_logic := '0';
signal ltn_1 : std_logic := '0';
signal lun_1 : std_logic := '0';
signal lon_1 : std_logic := '0';
signal ton_1 : std_logic := '0';
signal endOf_1 : std_logic := '0';
signal gts_1 : std_logic := '0';
signal rpp_1 : std_logic := '0';
signal tcs_1 : std_logic := '0';
signal tca_1 : std_logic := '0';
signal sic_1 : std_logic := '0';
signal rsc_1 : std_logic := '0';
signal sre_1 : std_logic := '0';
signal rtl_1 : std_logic := '0';
signal rsv_1 : std_logic := '0';
signal ist_1 : std_logic := '0';
signal lpe_1 : std_logic := '0';
-- inputs 2
signal data_2 : std_logic_vector(7 downto 0) := (others => '0');
signal status_byte_2 : std_logic_vector(7 downto 0) := (others => '0');
signal rdy_2 : std_logic := '0';
signal nba_2 : std_logic := '0';
signal ltn_2 : std_logic := '0';
signal lun_2 : std_logic := '0';
signal lon_2 : std_logic := '0';
signal ton_2 : std_logic := '0';
signal endOf_2 : std_logic := '0';
signal gts_2 : std_logic := '0';
signal rpp_2 : std_logic := '0';
signal tcs_2 : std_logic := '0';
signal tca_2 : std_logic := '0';
signal sic_2 : std_logic := '0';
signal rsc_2 : std_logic := '0';
signal sre_2 : std_logic := '0';
signal rtl_2 : std_logic := '0';
signal rsv_2 : std_logic := '0';
signal ist_2 : std_logic := '0';
signal lpe_2 : std_logic := '0';
-- outputs 1
signal dvd_1 : std_logic;
signal wnc_1 : std_logic;
signal tac_1 : std_logic;
signal cwrc_1 : std_logic;
signal cwrd_1 : std_logic;
signal clr_1 : std_logic;
signal trg_1 : std_logic;
signal atl_1 : std_logic;
signal att_1 : std_logic;
signal mla_1 : std_logic;
signal lsb_1 : std_logic;
signal spa_1 : std_logic;
signal ppr_1 : std_logic;
signal sreq_1 : std_logic;
signal isLocal_1 : std_logic;
signal currentSecAddr_1 : std_logic_vector (4 downto 0);
-- outputs 2
signal dvd_2 : std_logic;
signal wnc_2 : std_logic;
signal tac_2 : std_logic;
signal cwrc_2 : std_logic;
signal cwrd_2 : std_logic;
signal clr_2 : std_logic;
signal trg_2 : std_logic;
signal atl_2 : std_logic;
signal att_2 : std_logic;
signal mla_2 : std_logic;
signal lsb_2 : std_logic;
signal spa_2 : std_logic;
signal ppr_2 : std_logic;
signal sreq_2 : std_logic;
signal isLocal_2 : std_logic;
signal currentSecAddr_2 : std_logic_vector (4 downto 0);
-- common
signal DO : std_logic_vector (7 downto 0);
signal DI_1 : std_logic_vector (7 downto 0);
signal output_valid_1 : std_logic;
signal DI_2 : std_logic_vector (7 downto 0);
signal output_valid_2 : std_logic;
signal ATN_1, ATN_2, ATN : std_logic;
signal DAV_1, DAV_2, DAV : std_logic;
signal NRFD_1, NRFD_2, NRFD : std_logic;
signal NDAC_1, NDAC_2, NDAC : std_logic;
signal EOI_1, EOI_2, EOI : std_logic;
signal SRQ_1, SRQ_2, SRQ : std_logic;
signal IFC_1, IFC_2, IFC : std_logic;
signal REN_1, REN_2, REN : std_logic;
-- gpib reader
signal buf_interrupt : std_logic;
signal data_available : std_logic;
signal last_byte_addr : std_logic_vector (3 downto 0);
signal end_of_stream : std_logic;
signal byte_addr : std_logic_vector (3 downto 0);
signal data_out : std_logic_vector (7 downto 0);
signal reset_buffer : std_logic := '0';
signal dataSecAddr : std_logic_vector (4 downto 0);
-- Clock period definitions
constant clk_period : time := 2ps;
BEGIN
-- Instantiate the Unit Under Test (UUT)
gpib1: gpibInterface PORT MAP (
clk => clk,
reset => reset,
isLE => '0',
isTE => '0',
lpeUsed => '0',
fixedPpLine => "000",
eosUsed => '0',
eosMark => "00000000",
myListAddr => "00001",
myTalkAddr => "00001",
secAddrMask => (others => '0'),
data => data_1,
status_byte => status_byte_1,
T1 => T1,
rdy => rdy_1,
nba => nba_1,
ltn => ltn_1,
lun => lun_1,
lon => lon_1,
ton => ton_1,
endOf => endOf_1,
gts => gts_1,
rpp => rpp_1,
tcs => tcs_1,
tca => tca_1,
sic => sic_1,
rsc => rsc_1,
sre => sre_1,
rtl => rtl_1,
rsv => rsv_1,
ist => ist_1,
lpe => lpe_1,
dvd => dvd_1,
wnc => wnc_1,
tac => tac_1,
cwrc => cwrc_1,
cwrd => cwrd_1,
clr => clr_1,
trg => trg_1,
atl => atl_1,
att => att_1,
mla => mla_1,
lsb => lsb_1,
spa => spa_1,
ppr => ppr_1,
sreq => sreq_1,
isLocal => isLocal_1,
currentSecAddr => currentSecAddr_1,
DI => DO,
DO => DI_1,
output_valid => output_valid_1,
ATN_in => ATN,
ATN_out => ATN_1,
DAV_in => DAV,
DAV_out => DAV_1,
NRFD_in => NRFD,
NRFD_out => NRFD_1,
NDAC_in => NDAC,
NDAC_out => NDAC_1,
EOI_in => EOI,
EOI_out => EOI_1,
SRQ_in => SRQ,
SRQ_out => SRQ_1,
IFC_in => IFC,
IFC_out => IFC_1,
REN_in => REN,
REN_out => REN_1
);
-- Instantiate the Unit Under Test (UUT)
gpib2: gpibInterface PORT MAP (
clk => clk,
reset => reset,
isLE => '0',
isTE => '0',
lpeUsed => '0',
fixedPpLine => "000",
eosUsed => '0',
eosMark => "00000000",
myListAddr => "00010",
myTalkAddr => "00010",
secAddrMask => (others => '0'),
data => data_2,
status_byte => status_byte_2,
T1 => T1,
rdy => rdy_2,
nba => nba_2,
ltn => ltn_2,
lun => lun_2,
lon => lon_2,
ton => ton_2,
endOf => endOf_2,
gts => gts_2,
rpp => rpp_2,
tcs => tcs_2,
tca => tca_2,
sic => sic_2,
rsc => rsc_2,
sre => sre_2,
rtl => rtl_2,
rsv => rsv_2,
ist => ist_2,
lpe => lpe_2,
dvd => dvd_2,
wnc => wnc_2,
tac => tac_2,
cwrc => cwrc_2,
cwrd => cwrd_2,
clr => clr_2,
trg => trg_2,
atl => atl_2,
att => att_2,
mla => mla_2,
lsb => lsb_2,
spa => spa_2,
ppr => ppr_2,
sreq => sreq_2,
isLocal => isLocal_2,
currentSecAddr => currentSecAddr_2,
DI => DO,
DO => DI_2,
output_valid => output_valid_2,
ATN_in => ATN,
ATN_out => ATN_2,
DAV_in => DAV,
DAV_out => DAV_2,
NRFD_in => NRFD,
NRFD_out => NRFD_2,
NDAC_in => NDAC,
NDAC_out => NDAC_2,
EOI_in => EOI,
EOI_out => EOI_2,
SRQ_in => SRQ,
SRQ_out => SRQ_2,
IFC_in => IFC,
IFC_out => IFC_2,
REN_in => REN,
REN_out => REN_2
);
ce: gpibCableEmulator port map (
-- interface signals
DIO_1 => DI_1,
output_valid_1 => output_valid_1,
DIO_2 => DI_2,
output_valid_2 => output_valid_2,
DIO => DO,
-- attention
ATN_1 => ATN_1, ATN_2 => ATN_2, ATN => ATN,
DAV_1 => DAV_1, DAV_2 => DAV_2, DAV => DAV,
NRFD_1 => NRFD_1, NRFD_2 => NRFD_2, NRFD => NRFD,
NDAC_1 => NDAC_1, NDAC_2 => NDAC_2, NDAC => NDAC,
EOI_1 => EOI_1, EOI_2 => EOI_2, EOI => EOI,
SRQ_1 => SRQ_1, SRQ_2 => SRQ_2, SRQ => SRQ,
IFC_1 => IFC_1, IFC_2 => IFC_2, IFC => IFC,
REN_1 => REN_1, REN_2 => REN_2, REN => REN
);
gr: gpibReader generic map(ADDR_WIDTH => 4) port map(
clk => clk, reset => reset,
------------------------------------------------------------------------
------ GPIB interface --------------------------------------------------
------------------------------------------------------------------------
data_in => DO, dvd => dvd_2, atl => atl_2, lsb => lsb_2, rdy => rdy_2,
------------------------------------------------------------------------
------ external interface ----------------------------------------------
------------------------------------------------------------------------
isLE => '0', secAddr => (others => '0'), dataSecAddr => dataSecAddr,
buf_interrupt => buf_interrupt, data_available => data_available,
last_byte_addr => last_byte_addr, end_of_stream => end_of_stream,
byte_addr => byte_addr, data_out => data_out,
reset_buffer => reset_buffer
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 10 clock periods.
reset <= '1';
wait for clk_period*10;
reset <= '0';
wait for clk_period*10;
-- requests system control
rsc_1 <= '1';
-- interface clear
sic_1 <= '1';
wait until IFC_1 = '1';
sic_1 <= '0';
wait until IFC_1 = '0';
-- address gpib2 to listen
data_1 <= "00100010";
nba_1 <= '1';
wait until DAV='1';
nba_1 <= '0';
wait for clk_period*20;
-- address gpib1 to talk
data_1 <= "01000001";
wait for clk_period*1;
nba_1 <= '1';
wait until DAV='1';
nba_1 <= '0';
wait for clk_period*30;
gts_1 <= '1';
wait until ATN='0';
-- send data to gpib2
data_1 <= "10101010";
nba_1 <= '1';
wait until wnc_1='1';
nba_1 <= '0';
wait for clk_period*3;
-- send end data to gpib2
data_1 <= "10101010";
endOf_1 <= '1';
nba_1 <= '1';
wait until wnc_1='1';
nba_1 <= '0';
--wait until wnc_1='0';
wait until buf_interrupt = '1';
byte_addr <= "0000";
wait for clk_period*1;
assert data_out = "10101010";
byte_addr <= "0001";
wait for clk_period*1;
assert data_out = "10101010";
report "$$$ END OF TEST - reader $$$";
wait;
end process;
END;
| gpl-3.0 | 452b3ecd16c87b5605a9555f059e5b85 | 0.573546 | 2.812716 | false | false | false | false |
freecores/gpib_controller | vhdl/src/gpib/if_func_L_LE.vhd | 1 | 4,880 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: if_func_L_LE
-- Date: 01:04:57 10/01/2011
-- Author: Andrzej Paluch
--------------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
use work.utilPkg.all;
entity if_func_L_LE is
port(
-- clock
clk : in std_logic; -- clock
-- function settings
isLE : in std_logic;
-- local commands
pon : in std_logic; -- power on
ltn : in std_logic; -- listen
lun : in std_logic; -- local unlisten
lon : in std_logic; -- listen only
-- state inputs
ACDS : in std_logic; -- accept data state (AH)
CACS : in std_logic; -- controller active state (C)
TPAS : in std_logic; -- talker primary address state (T)
-- remote commands
ATN : in std_logic; -- attention
IFC : in std_logic; -- interface clear
MLA : in std_logic; -- my listen address
MTA : in std_logic; -- my talk address
UNL : in std_logic; -- unlisten
PCG : in std_logic; -- primary command group
MSA : in std_logic; -- my secondary address
-- reported states
LACS : out std_logic; -- listener active state
LADS : out std_logic; -- listener addressed state
LPAS : out std_logic -- listener primary addressed state
;debug1 : out std_logic
);
end if_func_L_LE;
architecture Behavioral of if_func_L_LE is
-- states
type LE_STATE_1 is (
-- listener idle state
ST_LIDS,
-- listener addressed state
ST_LADS,
-- listener active state
ST_LACS
);
-- states
type LE_STATE_2 is (
-- listener primary idle state
ST_LPIS,
-- listener primary addressed state
ST_LPAS
);
-- current state
signal current_state_1 : LE_STATE_1;
signal current_state_2 : LE_STATE_2;
-- predicates
signal event0, event1, event2, event3, event4 : boolean;
begin
debug1 <= to_stdl(current_state_1 = ST_LACS) or
to_stdl(current_state_1 = ST_LADS);
-- state machine process - L_STATE_1
process(pon, clk) begin
if pon = '1' then
current_state_1 <= ST_LIDS;
elsif rising_edge(clk) then
case current_state_1 is
------------------
when ST_LIDS =>
if event0 then
-- no state change
elsif event1 then
current_state_1 <= ST_LADS;
end if;
------------------
when ST_LADS =>
if event0 then
current_state_1 <= ST_LIDS;
elsif event2 then
current_state_1 <= ST_LIDS;
elsif ATN='0' then
current_state_1 <= ST_LACS;
end if;
------------------
when ST_LACS =>
if event0 then
current_state_1 <= ST_LIDS;
elsif ATN='1' then
current_state_1 <= ST_LADS;
end if;
------------------
when others =>
current_state_1 <= ST_LIDS;
end case;
end if;
end process;
-- state machine process - L_STATE_2
process(pon, clk) begin
if pon = '1' then
current_state_2 <= ST_LPIS;
elsif rising_edge(clk) then
case current_state_2 is
------------------
when ST_LPIS =>
if event0 then
-- no state change
elsif event3 then
current_state_2 <= ST_LPAS;
end if;
------------------
when ST_LPAS =>
if event0 then
current_state_2 <= ST_LPIS;
elsif event4 then
current_state_2 <= ST_LPIS;
end if;
------------------
when others =>
current_state_2 <= ST_LPIS;
end case;
end if;
end process;
-- events
event0 <= IFC='1';
event1 <= (isLE='1' and (
lon='1' or (ltn='1' and CACS='1') or
(MSA='1' and current_state_2=ST_LPAS and ACDS='1')
)) or
(isLE='0' and (
lon='1' or (MLA='1' and ACDS='1') or (ltn='1' and CACS='1')
));
event2 <= (isLE='1' and (
(UNL='1' and ACDS='1') or
(lun='1' and CACS='1') or
(MSA='1' and TPAS='1' and ACDS='1')
)) or
(isLE='0' and (
(UNL='1' and ACDS='1') or
(MTA='1' and ACDS='1') or
(lun='1' and CACS='1')
));
event3 <= MLA='1' and ACDS='1';
event4 <= PCG='1' and MLA='0' and ACDS='1';
LACS <= to_stdl(current_state_1 = ST_LACS);
LADS <= to_stdl(current_state_1 = ST_LADS);
LPAS <= to_stdl(current_state_2 = ST_LPAS);
end Behavioral;
| gpl-3.0 | 7d5d9630af2e497685360b92338294b1 | 0.578279 | 3.187459 | false | false | false | false |
autosub-team/autosub | src/tests/testTasksVHDL/testsubmissions/fsm/fsm_beh.vhdl | 2 | 2,700 | library IEEE;
use IEEE.std_logic_1164.all;
use work.fsm_pkg.all;
architecture behavior of fsm is
signal internal_state,internal_state_next : fsm_state;
signal internal_output,internal_output_next: std_logic_vector(1 downto 0);
begin
--Next State Logic and Next Output Logic----
nextState_nextOutput : process(internal_state, INPUT)
begin
internal_state_next<= internal_state;
internal_output_next<=internal_output;
case internal_state is
when START =>
if INPUT = "00" then
internal_state_next <= S3;
internal_output_next <= "01";
end if;
when S0 =>
if INPUT = "01" then
internal_state_next <= S1;
internal_output_next <= "01";
end if;
when S1 =>
if INPUT = "10" then
internal_state_next <= S2;
internal_output_next <= "10";
end if;
if INPUT = "01" then
internal_state_next <= S1;
internal_output_next <= "01";
end if;
if INPUT = "00" then
internal_state_next <= S3;
internal_output_next <= "01";
end if;
if INPUT = "11" then
internal_state_next <= S0;
internal_output_next <= "10" ;
end if;
when S2 =>
if INPUT = "01" then
internal_state_next <= S1;
internal_output_next <= "01" ;
end if;
if INPUT = "11" then
internal_state_next <= S3;
internal_output_next <= "11" ;
end if;
when S3 =>
if INPUT = "11" then
internal_state_next <= S1;
internal_output_next <= "01" ;
end if;
if INPUT = "10" then
internal_state_next <= S2;
internal_output_next <= "01" ;
end if;
when others=>
null;
end case;
end process nextState_nextOutput;
--Sync and Reset Logic--
sync_proc : process(clk, rst)
begin
if(rising_edge(CLK)) then
if RST = '1' then
internal_state <= START;
internal_output <= "00";
else
internal_state <= internal_state_next;
internal_output <= internal_output_next;
end if;
end if;
end process sync_proc;
OUTPUT <= internal_output;
STATE <= internal_state;
end behavior;
| gpl-2.0 | 5d3890223173dd766d6069d29b8022bb | 0.462593 | 4.440789 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | filtering_algorithm_RTL/source/vhdl/divider_top.vhd | 1 | 6,175 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: divider_top - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.filtering_algorithm_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity divider_top is
generic (
ROUND : boolean := false
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
dividend : in data_type_ext;
divisor : in coord_type;
rdy : out std_logic;
quotient : out data_type;
divide_by_zero : out std_logic
);
end divider_top;
architecture Behavioral of divider_top is
constant QUOTIENT_BITWIDTH : integer := COORD_BITWIDTH_EXT;
constant FRACTIONAL_BITWIDTH : integer := COORD_BITWIDTH_EXT-COORD_BITWIDTH;
type divider_result_type is array(0 to D-1) of std_logic_vector(QUOTIENT_BITWIDTH+FRACTIONAL_BITWIDTH-1 downto 0);
type quotient_type is array(0 to D-1) of std_logic_vector(QUOTIENT_BITWIDTH-1 downto 0);
component divider
port (
aclk : IN std_logic;
s_axis_divisor_tvalid : IN std_logic;
--s_axis_divisor_tready : OUT std_logic;
s_axis_divisor_tdata : IN std_logic_vector(COORD_BITWIDTH-1 DOWNTO 0);
s_axis_dividend_tvalid : IN std_logic;
--s_axis_dividend_tready : OUT std_logic;
s_axis_dividend_tdata : IN std_logic_vector(COORD_BITWIDTH_EXT-1 DOWNTO 0);
m_axis_dout_tvalid : OUT std_logic;
m_axis_dout_tdata : OUT std_logic_vector(QUOTIENT_BITWIDTH+FRACTIONAL_BITWIDTH-1 DOWNTO 0)
--m_axis_dout_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
end component;
component divider_v3_0
port (
clk : IN std_logic;
sclr : IN std_logic;
s_axis_divisor_tvalid : IN std_logic;
divisor : IN std_logic_vector(COORD_BITWIDTH-1 DOWNTO 0);
dividend : IN std_logic_vector(COORD_BITWIDTH_EXT-1 DOWNTO 0);
quotient: OUT std_logic_vector(QUOTIENT_BITWIDTH-1 DOWNTO 0);
fractional : OUT std_logic_vector(FRACTIONAL_BITWIDTH-1 downto 0)
);
end component;
component dsp_round
generic (
BITWIDTH_IN : integer := 32;
BITWIDTH_OUT : integer := 32
);
port (
sclr : in std_logic;
nd : in std_logic;
AB_IN : in std_logic_vector (BITWIDTH_IN-1 downto 0);
CARRYIN_IN : in std_logic;
CLK_IN : in std_logic;
C_IN : in std_logic_vector (BITWIDTH_IN-1 downto 0);
P_OUT : out std_logic_vector (BITWIDTH_OUT-1 downto 0);
rdy : out std_logic
);
end component;
signal tmp_divisor : coord_type;
signal divider_result : divider_result_type;
signal tmp_quotient : quotient_type;
signal divider_valid : std_logic_vector(0 to D-1);
signal tmp_divide_by_zero : std_logic_vector(0 to D-1);
signal round_valid : std_logic_vector(0 to D-1);
signal c_in_const : std_logic_vector(COORD_BITWIDTH_EXT-1 downto 0);
begin
c_in_const(QUOTIENT_BITWIDTH-1 downto QUOTIENT_BITWIDTH-FRACTIONAL_BITWIDTH-1) <= (others => '0');
c_in_const(QUOTIENT_BITWIDTH-FRACTIONAL_BITWIDTH-2 downto 0) <= (others => '1');
tmp_divisor <= std_logic_vector(to_unsigned(1,COORD_BITWIDTH)) WHEN divisor = std_logic_vector(to_unsigned(0,COORD_BITWIDTH)) ELSE divisor;
G_DIV : for I in 0 to D-1 generate
divider_inst : divider
port map (
aclk => clk,
s_axis_divisor_tvalid => nd,
--s_axis_divisor_tready => open,
s_axis_divisor_tdata => tmp_divisor,
s_axis_dividend_tvalid => nd,
--s_axis_dividend_tready => open,
s_axis_dividend_tdata => dividend(I),
m_axis_dout_tvalid => divider_valid(I),
m_axis_dout_tdata => divider_result(I)
--m_axis_dout_tuser(0) => tmp_divide_by_zero(I)
);
tmp_quotient(I) <= divider_result(I)(QUOTIENT_BITWIDTH+FRACTIONAL_BITWIDTH-1 downto FRACTIONAL_BITWIDTH);
G_ROUND : if ROUND = true generate
dsp_round_inst : dsp_round
generic map (
BITWIDTH_IN => COORD_BITWIDTH_EXT,
BITWIDTH_OUT => COORD_BITWIDTH
)
port map (
sclr => sclr,
nd => divider_valid(I),
AB_IN => divider_result(I)(COORD_BITWIDTH_EXT-1 downto 0),
CARRYIN_IN => divider_result(I)(COORD_BITWIDTH_EXT-1), -- round towards zero
CLK_IN => clk,
C_IN => c_in_const,
P_OUT => quotient(I),
rdy => round_valid(I)
);
end generate G_ROUND;
G_NO_ROUND : if ROUND = false generate
quotient(I) <= divider_result(I)(QUOTIENT_BITWIDTH-1 downto FRACTIONAL_BITWIDTH);
end generate G_NO_ROUND;
end generate G_DIV;
G_NO_ROUND_1 : if ROUND = false generate
rdy <= divider_valid(0);
end generate G_NO_ROUND_1;
G_ROUND_1 : if ROUND = true generate
rdy <= round_valid(0);
end generate G_ROUND_1;
divide_by_zero <= '0';--tmp_divide_by_zero(0);
end Behavioral;
| bsd-3-clause | f2a4a58b9c703b4b14aa58ee5a6dc65a | 0.547368 | 4.054498 | false | false | false | false |
tomoasleep/vhdl_test_script | examples/state_machine_subtype.vhd | 1 | 1,406 | library ieee;
use ieee.std_logic_1164.all;
library work;
use work.const_state.all;
use work.const_order.all;
use work.const_state2.all;
-- DOCTEST DEPENDENCIES: state_machine_lib.vhd
entity state_machine is
port(
input: in std_logic;
reset: in std_logic;
state: out state_type;
clk : in std_logic
);
end state_machine;
architecture behave of state_machine is
signal current_state: state_type;
begin
main: process(clk) begin
if rising_edge(clk) then
case reset is
when '1' =>
current_state <= STATE_E;
when others =>
case current_state is
when STATE_E =>
current_state <= STATE_F;
when STATE_F =>
case input is
when ORDER_A =>
current_state <= STATE_G;
when others =>
current_state <= STATE_E;
end case;
when STATE_G =>
case input is
when ORDER_B =>
current_state <= STATE_H;
when others =>
current_state <= STATE_E;
end case;
when STATE_H =>
current_state <= STATE_E;
when others =>
current_state <= STATE_E;
end case;
end case;
end if;
end process;
state <= current_state;
end behave;
| mit | d636e570f1ac01135c784f54ddaa7d96 | 0.507824 | 4.172107 | false | false | false | false |
pavsa/hackrf-spectrum-analyzer | src/hackrf-sweep/lib/hackrf/firmware/cpld/sgpio_if/top.vhd | 12 | 5,535 | --
-- Copyright 2012 Jared Boone
-- Copyright 2013 Benjamin Vernoux
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity top is
Port(
HOST_DATA : inout std_logic_vector(7 downto 0);
HOST_CAPTURE : out std_logic;
HOST_DISABLE : in std_logic;
HOST_DIRECTION : in std_logic;
HOST_DECIM_SEL : in std_logic_vector(2 downto 0);
HOST_Q_INVERT : in std_logic;
DA : in std_logic_vector(7 downto 0);
DD : out std_logic_vector(9 downto 0);
CODEC_CLK : in std_logic;
CODEC_X2_CLK : in std_logic
);
end top;
architecture Behavioral of top is
signal codec_clk_i : std_logic;
signal adc_data_i : std_logic_vector(7 downto 0);
signal dac_data_o : std_logic_vector(9 downto 0);
signal host_clk_i : std_logic;
type transfer_direction is (from_adc, to_dac);
signal transfer_direction_i : transfer_direction;
signal host_data_enable_i : std_logic;
signal host_data_capture_o : std_logic;
signal data_from_host_i : std_logic_vector(7 downto 0);
signal data_to_host_o : std_logic_vector(7 downto 0);
signal decimate_count : std_logic_vector(2 downto 0) := "111";
signal decimate_sel_i : std_logic_vector(2 downto 0);
signal decimate_en : std_logic;
signal q_invert : std_logic;
signal rx_q_invert_mask : std_logic_vector(7 downto 0);
signal tx_q_invert_mask : std_logic_vector(7 downto 0);
begin
------------------------------------------------
-- Codec interface
adc_data_i <= DA(7 downto 0);
DD(9 downto 0) <= dac_data_o;
------------------------------------------------
-- Clocks
codec_clk_i <= CODEC_CLK;
BUFG_host : BUFG
port map (
O => host_clk_i,
I => CODEC_X2_CLK
);
------------------------------------------------
-- SGPIO interface
HOST_DATA <= data_to_host_o when transfer_direction_i = from_adc
else (others => 'Z');
data_from_host_i <= HOST_DATA;
HOST_CAPTURE <= host_data_capture_o;
host_data_enable_i <= not HOST_DISABLE;
transfer_direction_i <= to_dac when HOST_DIRECTION = '1'
else from_adc;
decimate_sel_i <= HOST_DECIM_SEL;
------------------------------------------------
decimate_en <= '1' when decimate_count = "111" else '0';
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if codec_clk_i = '1' then
if decimate_count = "111" or host_data_enable_i = '0' then
decimate_count <= decimate_sel_i;
else
decimate_count <= decimate_count + 1;
end if;
end if;
end if;
end process;
q_invert <= HOST_Q_INVERT;
rx_q_invert_mask <= X"80" when q_invert = '1' else X"7f";
tx_q_invert_mask <= X"7F" when q_invert = '1' else X"80";
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if codec_clk_i = '1' then
-- I: non-inverted between MAX2837 and MAX5864
data_to_host_o <= adc_data_i xor X"80";
else
-- Q: inverted between MAX2837 and MAX5864
data_to_host_o <= adc_data_i xor rx_q_invert_mask;
end if;
end if;
end process;
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if transfer_direction_i = to_dac then
if codec_clk_i = '1' then
dac_data_o <= (data_from_host_i xor tx_q_invert_mask) & tx_q_invert_mask(0) & tx_q_invert_mask(0);
else
dac_data_o <= (data_from_host_i xor X"80") & "00";
end if;
else
dac_data_o <= (dac_data_o'high => '0', others => '1');
end if;
end if;
end process;
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if transfer_direction_i = to_dac then
if codec_clk_i = '1' then
host_data_capture_o <= host_data_enable_i;
end if;
else
if codec_clk_i = '0' then
host_data_capture_o <= host_data_enable_i and decimate_en;
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 94f6e2872ec2152abd96e472784afa11 | 0.520325 | 3.780738 | false | false | false | false |
tsotnep/vhdl_soc_audio_mixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/adau1761_audio_v1_00_a/hdl/vhdl/user_logic.vhd | 2 | 12,862 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Tue May 20 11:28:03 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 2;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
clk_100 : IN std_logic;
clk_48_o : OUT std_logic;
AC_GPIO1 : IN std_logic;
AC_GPIO2 : IN std_logic;
AC_GPIO3 : IN std_logic;
AC_SDA_I : IN std_logic;
AC_SDA_O : OUT std_logic;
AC_SDA_T : OUT std_logic;
--AUDIO ports to top layer
AUDIO_OUT_L : OUT STD_LOGIC_VECTOR(23 downto 0);
AUDIO_OUT_R : OUT STD_LOGIC_VECTOR(23 downto 0);
AUDIO_IN_L : IN STD_LOGIC_VECTOR(23 downto 0);
AUDIO_IN_R : IN STD_LOGIC_VECTOR(23 downto 0);
--AC_SDA : INOUT std_logic;
AC_ADR0 : OUT std_logic;
AC_ADR1 : OUT std_logic;
AC_GPIO0 : OUT std_logic;
AC_MCLK : OUT std_logic;
AC_SCK : OUT std_logic;
new_sample : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
COMPONENT adau1761 is
PORT(
clk_100 : IN std_logic;
clk_48_o : OUT std_logic;
AC_GPIO1 : IN std_logic;
AC_GPIO2 : IN std_logic;
AC_GPIO3 : IN std_logic;
AC_SDA_I : IN std_logic;
AC_SDA_O : OUT std_logic;
AC_SDA_T : OUT std_logic;
AUDIO_OUT_L :OUT STD_LOGIC_VECTOR(23 downto 0);
AUDIO_OUT_R :OUT STD_LOGIC_VECTOR(23 downto 0);
AUDIO_IN_L :IN STD_LOGIC_VECTOR(23 downto 0);
AUDIO_IN_R :IN STD_LOGIC_VECTOR(23 downto 0);
--AC_SDA : INOUT std_logic;
AC_ADR0 : OUT std_logic;
AC_ADR1 : OUT std_logic;
AC_GPIO0 : OUT std_logic;
AC_MCLK : OUT std_logic;
AC_SCK : OUT std_logic;
new_sample : out std_logic;
sw : in STD_LOGIC_VECTOR(7 downto 0)
);
END COMPONENT;
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg_write_sel : std_logic_vector(1 downto 0);
signal slv_reg_read_sel : std_logic_vector(1 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal AUDIO_OUT_L_s : std_logic_vector(23 downto 0);
signal AUDIO_OUT_R_s : std_logic_vector(23 downto 0);
signal AUDIO_IN_L_s : std_logic_vector(23 downto 0);
signal AUDIO_IN_R_s : std_logic_vector(23 downto 0);
signal clk_48_s : std_logic;
begin
--USER logic implementation added here
AUDIO_IN_L_s <= AUDIO_IN_L;
AUDIO_IN_R_s <= AUDIO_IN_R;
clk_48_o <= clk_48_s;
AUDIO_OUT_L <= AUDIO_OUT_L_s; -- AUDIO_OUT data to the next buffer
AUDIO_OUT_R <= AUDIO_OUT_R_s;
--
adau1761_internal: adau1761 PORT MAP (
clk_100 => clk_100,
clk_48_o => clk_48_s,
AC_ADR0 => AC_ADR0,
AC_ADR1 => AC_ADR1,
AC_GPIO0 => AC_GPIO0,
AC_GPIO1 => AC_GPIO1,
AC_GPIO2 => AC_GPIO2,
AC_GPIO3 => AC_GPIO3,
AC_MCLK => AC_MCLK,
AC_SCK => AC_SCK,
AC_SDA_I => AC_SDA_I,
AC_SDA_O => AC_SDA_O,
AC_SDA_T => AC_SDA_T,
--AC_SDA => AC_SDA,
new_sample => new_sample,
AUDIO_OUT_L => AUDIO_OUT_L_s,
AUDIO_OUT_R => AUDIO_OUT_R_s,
AUDIO_IN_L => AUDIO_IN_L_s,
AUDIO_IN_R => AUDIO_IN_R_s,
sw=> "00000001"
);
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(1 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(1 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1);
--clk_48_o <= clk_48_s;
-- slv_reg0(23 downto 0) <= AUDIO_OUT_R_s; -- AUDIO_OUT data to AXI bus
-- slv_reg1(23 downto 0) <= AUDIO_OUT_L_s;
-- AUDIO_OUT_L <= AUDIO_OUT_R_s; -- AUDIO_OUT data to the next buffer
-- AUDIO_OUT_R <= AUDIO_OUT_L_s;
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
else
case slv_reg_write_sel is
when "10" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "01" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg1(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1 ) is
begin
case slv_reg_read_sel is
when "10" => slv_ip2bus_data <= slv_reg0;
when "01" => slv_ip2bus_data <= slv_reg1;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
| mit | b0e5c552fabbf3fec3a3a484c4a3d74d | 0.493158 | 3.834824 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | lloyds_algorithm_RTL/simulation/testbench.vhd | 1 | 11,099 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: testbench - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.all;
use ieee.math_real.all;
use STD.textio.all;
use work.lloyds_algorithm_pkg.all;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
constant MY_N : integer := 128; --N
constant MY_K : integer := 4; -- K
file my_input_node : TEXT open READ_MODE is "../../simulation/data_points_N128_K4_D3_s0.75.mat";
file my_input_cntr : TEXT open READ_MODE is "../../simulation/initial_centres_N128_K4_D3_s0.75_1.mat";
--file my_input_node : TEXT open READ_MODE is "../../simulation/data_points_N16384_K256_D3_s0.20.mat";
--file my_input_cntr : TEXT open READ_MODE is "../../simulation/initial_centres_N16384_K256_D3_s0.20_1.mat";
--file my_input_node : TEXT open READ_MODE is "../../simulation/data_points_N16384_K128_D3_s0.00.mat";
--file my_input_cntr : TEXT open READ_MODE is "../../simulation/initial_centres_N16384_K128_D3_s0.00_1.mat";
-- Clock period definitions
constant CLK_PERIOD : time := 10 ns;
constant RESET_CYCLES : integer := 20;
constant INIT_CYCLES : integer := MY_N;
type state_type is (readfile, reset, init, processing, processing_done);
type file_node_data_array_type is array(0 to D-1, 0 to MY_N-1) of integer;
type file_cntr_data_array_type is array(0 to D-1, 0 to MY_K-1) of integer;
-- Component Declaration for the Unit Under Test (UUT)
component lloyds_algorithm_top
port (
clk : in std_logic;
sclr : in std_logic;
start : in std_logic;
-- initial parameters
n : in node_index_type;
k : in centre_index_type;
-- init node and centre memory
wr_init_node : in std_logic;
wr_node_address_init : in node_address_type;
wr_node_data_init : in node_data_type;
wr_init_pos : in std_logic;
wr_centre_list_pos_address_init : in centre_index_type;
wr_centre_list_pos_data_init : in data_type;
-- outputs
valid : out std_logic;
clusters_out : out data_type;
distortion_out : out coord_type_ext;
-- processing done
rdy : out std_logic
);
end component;
--Inputs
signal clk : std_logic;
signal sclr : std_logic := '1';
signal start : std_logic := '0';
-- initial parameters
signal n : node_index_type;
signal k : centre_index_type;
-- init node and centre memory
signal wr_init_node : std_logic := '0';
signal wr_node_address_init : node_address_type;
signal wr_node_data_init : node_data_type;
signal wr_init_pos : std_logic := '0';
signal wr_centre_list_pos_address_init : centre_index_type;
signal wr_centre_list_pos_data_init : data_type;
-- Outputs
signal valid : std_logic;
signal clusters_out : data_type;
signal distortion_out : coord_type_ext;
signal rdy : std_logic;
-- file io
signal file_node_data_array : file_node_data_array_type;
signal file_cntr_data_array : file_cntr_data_array_type;
signal read_file_done : std_logic := '0';
-- Operation
signal state : state_type := readfile;
signal reset_counter : integer := 0;
signal init_counter : integer := 0;
signal reset_counter_done : std_logic := '0';
signal init_counter_done : std_logic := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut : lloyds_algorithm_top
port map (
clk => clk,
sclr => sclr,
start => start ,
-- initial parameters
n => n,
k => k,
-- init node and centre memory
wr_init_node => wr_init_node,
wr_node_address_init => wr_node_address_init,
wr_node_data_init => wr_node_data_init,
wr_init_pos => wr_init_pos,
wr_centre_list_pos_address_init => wr_centre_list_pos_address_init,
wr_centre_list_pos_data_init => wr_centre_list_pos_data_init,
-- outputs
valid => valid,
clusters_out => clusters_out,
distortion_out => distortion_out,
-- final result available
rdy => rdy
);
-- Clock process definitions
clk_process : process
begin
clk <= '1';
wait for CLK_PERIOD/2;
clk <= '0';
wait for CLK_PERIOD/2;
end process;
fsm_proc : process(clk)
begin
if rising_edge(clk) then
if state = readfile AND read_file_done = '1' then
state <= reset;
elsif state = reset AND reset_counter_done = '1' then
state <= init;
elsif state = init AND init_counter_done = '1' then
state <= processing;
elsif state = processing AND rdy = '1' then
state <= processing_done;
end if;
end if;
end process fsm_proc;
counter_proc : process(clk)
begin
if rising_edge(clk) then
if state = reset then
reset_counter <= reset_counter+1;
end if;
if state = init then
init_counter <= init_counter+1;
end if;
end if;
end process counter_proc;
reset_counter_done <= '1' WHEN reset_counter = RESET_CYCLES-1 ELSE '0';
init_counter_done <= '1' WHEN init_counter = INIT_CYCLES-1 ELSE '0';
reset_proc : process(state)
begin
if state = reset then
sclr <= '1';
else
sclr <= '0';
end if;
end process reset_proc;
init_proc : process(state, init_counter)
variable centre_pos : data_type;
variable node : node_data_type;
begin
if state = init then
-- centre_positions_memory
if init_counter < MY_K then
for I in 0 to D-1 loop
centre_pos(I) := std_logic_vector(to_signed(file_cntr_data_array(I,init_counter),COORD_BITWIDTH));
end loop;
wr_init_pos <= '1';
wr_centre_list_pos_address_init <= to_unsigned(init_counter,INDEX_BITWIDTH);
wr_centre_list_pos_data_init <= centre_pos;
else
wr_init_pos <= '0';
end if;
-- tree_node_memory
if init_counter < MY_N then
for I in 0 to D-1 loop
node.position(I) := std_logic_vector(to_signed(file_node_data_array(I,init_counter),COORD_BITWIDTH));
end loop;
wr_init_node <= '1';
wr_node_address_init <= std_logic_vector(to_unsigned(init_counter,NODE_POINTER_BITWIDTH));
wr_node_data_init <= node;
else
wr_init_node <= '0';
end if;
else
wr_init_node <= '0';
wr_init_pos <= '0';
end if;
end process init_proc;
processing_proc : process(state, init_counter_done)
begin
if state = init AND init_counter_done = '1' then
start <= '1';
k <= to_unsigned(MY_K-1,INDEX_BITWIDTH);
n <= to_unsigned(MY_N-1,NODE_POINTER_BITWIDTH);
else
start <= '0';
end if;
end process processing_proc;
-- read tree data and initial centres from file
read_file : process
variable my_line : LINE;
variable my_input_line : LINE;
variable tmp_line_counter_node : integer;
variable tmp_file_line_counter_node : integer;
variable tmp_line_counter_cntr : integer;
variable tmp_file_line_counter_cntr : integer;
variable tmp_d : integer;
variable tmp_file_data_node : file_node_data_array_type;
variable tmp_file_data_cntr : file_cntr_data_array_type;
begin
write(my_line, string'("reading input files"));
writeline(output, my_line);
tmp_line_counter_node := 0;
tmp_file_line_counter_node := 0;
tmp_d := 0;
loop
exit when endfile(my_input_node) OR tmp_line_counter_node = D*MY_N;
readline(my_input_node, my_input_line);
read(my_input_line,tmp_file_data_node(tmp_d,tmp_file_line_counter_node));
-- if tmp_line_counter_node < MY_N then
-- read(my_input_line,tmp_file_data_node(0,tmp_line_counter_node));
-- else
-- read(my_input_line,tmp_file_data_node(1,tmp_line_counter_node-MY_N));
-- end if;
tmp_line_counter_node := tmp_line_counter_node+1;
tmp_file_line_counter_node := tmp_file_line_counter_node+1;
if tmp_file_line_counter_node = MY_N then
tmp_d := tmp_d +1;
tmp_file_line_counter_node := 0;
end if;
end loop;
file_node_data_array <= tmp_file_data_node;
write(my_line, string'("Number of lines:"));
writeline(output, my_line);
write(my_line, tmp_line_counter_node);
writeline(output, my_line);
-- reading centres now
tmp_line_counter_cntr := 0;
tmp_file_line_counter_cntr := 0;
tmp_d := 0;
loop
exit when endfile(my_input_cntr) OR tmp_line_counter_cntr = D*MY_K;
readline(my_input_cntr, my_input_line);
read(my_input_line,tmp_file_data_cntr(tmp_d,tmp_file_line_counter_cntr));
-- if tmp_line_counter_cntr < MY_K then
-- read(my_input_line,tmp_file_data_cntr(0,tmp_line_counter_cntr));
-- else
-- read(my_input_line,tmp_file_data_cntr(1,tmp_line_counter_cntr-MY_K));
-- end if;
tmp_line_counter_cntr := tmp_line_counter_cntr+1;
tmp_file_line_counter_cntr := tmp_file_line_counter_cntr+1;
if tmp_file_line_counter_cntr = MY_K then
tmp_d := tmp_d +1;
tmp_file_line_counter_cntr := 0;
end if;
end loop;
file_cntr_data_array <= tmp_file_data_cntr;
write(my_line, string'("Number of lines:"));
writeline(output, my_line);
write(my_line, tmp_line_counter_cntr);
writeline(output, my_line);
read_file_done <= '1';
wait; -- one shot at time zero,
end process read_file;
END;
| bsd-3-clause | 3c8b32eb2ac95269bd15e34dcb887cdc | 0.532931 | 3.715768 | false | false | false | false |
Nooxet/embedded_bruteforce | brutus_system/pcores/bajsd_v1_00_a/hdl/vhdl/comp.vhd | 1 | 3,033 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Gabbe
--
-- Create Date: 09:40:15 09/17/2014
-- Design Name:
-- Module Name: comp - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity comp is
port(
clk : in std_logic;
rstn : in std_logic; -- active low
i_hash_0, i_hash_1, i_hash_2, i_hash_3 : in unsigned(31 downto 0); -- hash from md5
i_cmp_hash : in std_logic_vector(127 downto 0); -- hash we are going to crack
i_start : in std_logic; -- 1 when we should read i_cmp_hash
o_equal : out std_logic -- 1 if we found the matching hash, else 0
);
end comp;
architecture Behavioral of comp is
-- the register signals --
signal cmp_hash_c, cmp_hash_n : std_logic_vector(127 downto 0);
-- for delaying equal signal, to controller --
--signal eq_c, eq_n : std_logic;
begin
-- the only signals which are clocked in this block are the register signals --
clk_proc: process(clk)
begin
if rising_edge(clk) then
if rstn = '0' then
cmp_hash_c <= (others => '0');
--eq_c <= '0';
else
cmp_hash_c <= cmp_hash_n;
--eq_c <= eq_n;
end if;
end if;
end process;
-- data path --
data_proc: process(i_start, i_cmp_hash, i_hash_0, i_hash_1, i_hash_2, i_hash_3, cmp_hash_c)--, eq_c)
-- the i_hash_1-3 have to be converted to little endian --
variable little_endian_0, little_endian_1, little_endian_2, little_endian_3 : unsigned(31 downto 0);
begin
-- defaults --
--eq_n <= eq_c;
-- converts the md5-hashes to little endian --
little_endian_0 := i_hash_0(7 downto 0) & i_hash_0(15 downto 8) & i_hash_0(23 downto 16) & i_hash_0(31 downto 24);
little_endian_1 := i_hash_1(7 downto 0) & i_hash_1(15 downto 8) & i_hash_1(23 downto 16) & i_hash_1(31 downto 24);
little_endian_2 := i_hash_2(7 downto 0) & i_hash_2(15 downto 8) & i_hash_2(23 downto 16) & i_hash_2(31 downto 24);
little_endian_3 := i_hash_3(7 downto 0) & i_hash_3(15 downto 8) & i_hash_3(23 downto 16) & i_hash_3(31 downto 24);
-- sets the register value --
if i_start = '1' then
cmp_hash_n <= i_cmp_hash;
else
cmp_hash_n <= cmp_hash_c;
end if;
-- have we found a matching hash or not? --
if (little_endian_0 & little_endian_1 & little_endian_2 & little_endian_3) = unsigned(cmp_hash_c) then
--eq_n <= '1';
o_equal <= '1'; --TEST
else
--eq_n <= '0';
o_equal <= '0'; --TEST
end if;
end process;
--o_equal <= eq_c;
end Behavioral;
| mit | bab5d7ac530920b2ac53f44a57c654fc | 0.600725 | 2.927606 | false | false | false | false |
mithro/HDMI2USB | hdl/jpeg_encoder/design/r_divider.vhd | 5 | 6,166 | --------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2009 --
-- --
--------------------------------------------------------------------------------
-- --
-- Title : DIVIDER --
-- Design : Divider using reciprocal table --
-- Author : Michal Krepa --
-- --
--------------------------------------------------------------------------------
-- --
-- File : R_DIVIDER.VHD --
-- Created : Wed 18-03-2009 --
-- --
--------------------------------------------------------------------------------
-- --
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
--------------------------------------------------------------------------------
-- MAIN DIVIDER top level
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.All;
use IEEE.NUMERIC_STD.all;
entity r_divider is
port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
a : in STD_LOGIC_VECTOR(11 downto 0);
d : in STD_LOGIC_VECTOR(7 downto 0);
q : out STD_LOGIC_VECTOR(11 downto 0)
) ;
end r_divider ;
architecture rtl of r_divider is
signal romr_datao : std_logic_vector(15 downto 0):=(others => '0');
signal romr_addr : std_logic_vector(7 downto 0):=(others => '0');
signal dividend : signed(11 downto 0):=(others => '0');
signal dividend_d1 : unsigned(11 downto 0):=(others => '0');
signal reciprocal : unsigned(15 downto 0):=(others => '0');
signal mult_out : unsigned(27 downto 0):=(others => '0');
signal mult_out_s : signed(11 downto 0):=(others => '0');
signal signbit : std_logic:='0';
signal signbit_d1 : std_logic:='0';
signal signbit_d2 : std_logic:='0';
signal signbit_d3 : std_logic:='0';
signal round : std_logic:='0';
begin
U_ROMR : entity work.ROMR
generic map
(
ROMADDR_W => 8,
ROMDATA_W => 16
)
port map
(
addr => romr_addr,
clk => CLK,
datao => romr_datao
);
romr_addr <= d;
reciprocal <= unsigned(romr_datao);
dividend <= signed(a);
signbit <= dividend(dividend'high);
rdiv : process(clk,rst)
begin
if rst = '1' then
mult_out <= (others => '0');
mult_out_s <= (others => '0');
dividend_d1 <= (others => '0');
q <= (others => '0');
signbit_d1 <= '0';
signbit_d2 <= '0';
signbit_d3 <= '0';
round <= '0';
elsif clk = '1' and clk'event then
signbit_d1 <= signbit;
signbit_d2 <= signbit_d1;
signbit_d3 <= signbit_d2;
if signbit = '1' then
dividend_d1 <= unsigned(0-dividend);
else
dividend_d1 <= unsigned(dividend);
end if;
mult_out <= dividend_d1 * reciprocal;
if signbit_d2 = '0' then
mult_out_s <= resize(signed(mult_out(27 downto 16)),mult_out_s'length);
else
mult_out_s <= resize(0-signed(mult_out(27 downto 16)),mult_out_s'length);
end if;
round <= mult_out(15);
if signbit_d3 = '0' then
if round = '1' then
q <= std_logic_vector(mult_out_s + 1);
else
q <= std_logic_vector(mult_out_s);
end if;
else
if round = '1' then
q <= std_logic_vector(mult_out_s - 1);
else
q <= std_logic_vector(mult_out_s);
end if;
end if;
end if;
end process;
end rtl;
| bsd-2-clause | af6209573fc81d0587b68053f3b8c2c8 | 0.430587 | 4.66062 | false | false | false | false |
esar/hdmilight-v2 | fpga/resultDelay.vhd | 1 | 6,767 | ----------------------------------------------------------------------------------
--
-- Copyright (C) 2014 Stephen Robinson
--
-- This file is part of HDMI-Light
--
-- HDMI-Light is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- HDMI-Light is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file names COPING).
-- If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity resultDelay is
Port ( clk : in STD_LOGIC;
in_vblank : in STD_LOGIC;
in_addr : out STD_LOGIC_VECTOR (7 downto 0);
in_data : in STD_LOGIC_VECTOR (31 downto 0);
out_vblank : out STD_LOGIC;
out_addr : in STD_LOGIC_VECTOR (7 downto 0);
out_data : out STD_LOGIC_VECTOR (31 downto 0);
delayFrames : in std_logic_vector(7 downto 0);
delayTicks : in std_logic_vector(23 downto 0);
temporalSmoothingRatio : in std_logic_vector(8 downto 0)
);
end resultDelay;
architecture Behavioral of resultDelay is
signal lastvblank : std_logic;
signal start : std_logic;
signal enable : std_logic;
signal count : std_logic_vector(10 downto 0);
signal tickcount : std_logic_vector(23 downto 0);
signal count_ram_in : std_logic_vector(2 downto 0) := "000";
signal count_ram_in_prev : std_logic_vector(2 downto 0);
signal count_ram_out : std_logic_vector(2 downto 0);
signal done : std_logic;
signal lastdone : std_logic;
signal coef : std_logic_vector(9 downto 0);
signal Rin : std_logic_vector(7 downto 0);
signal Gin : std_logic_vector(7 downto 0);
signal Bin : std_logic_vector(7 downto 0);
signal Rprod : std_logic_vector(35 downto 0);
signal Gprod : std_logic_vector(35 downto 0);
signal Bprod : std_logic_vector(35 downto 0);
signal Radd : std_logic_vector(35 downto 0) := (others => '0');
signal Gadd : std_logic_vector(35 downto 0) := (others => '0');
signal Badd : std_logic_vector(35 downto 0) := (others => '0');
signal ram_wr_in : std_logic;
signal ram_addr_in : std_logic_vector(10 downto 0);
signal ram_data_in : std_logic_vector(31 downto 0);
signal ram_addr_out : std_logic_vector(10 downto 0);
signal ram_data_out : std_logic_vector(31 downto 0);
begin
delayRam : entity work.blockram
GENERIC MAP(
ADDR => 11,
DATA => 32
)
PORT MAP (
a_clk => clk,
a_en => '1',
a_wr => ram_wr_in,
a_rst => '0',
a_addr => ram_addr_in,
a_din => ram_data_in,
a_dout => open,
b_clk => clk,
b_en => '1',
b_wr => '0',
b_rst => '0',
b_addr => ram_addr_out,
b_din => (others=> '0'),
b_dout => ram_data_out
);
-- generate start pulse when incoming vblank goes high
process(clk)
begin
if(rising_edge(clk)) then
if(in_vblank = '1' and lastvblank = '0') then
start <= '1';
else
start <= '0';
end if;
lastvblank <= in_vblank;
end if;
end process;
-- increment write address once per frame (when we get the start pulse)
process(clk)
begin
if(rising_edge(clk)) then
if(start = '1') then
count_ram_in_prev <= count_ram_in;
count_ram_in <= std_logic_vector(unsigned(count_ram_in) + 1);
end if;
end if;
end process;
-- set the read address to the write address minus the required delay (in whole frames)
count_ram_out <= std_logic_vector(unsigned(count_ram_in) - unsigned(delayFrames(2 downto 0)));
-- counter for copying the 256 values from the current set of results to the delay ram
-- while applying temporal smoothing. There are four counts per item copied:
-- 1) start read of incoming value and prev value
-- 2) multiply incoming value with ratio
-- 3) multiply previous value with inverse ratio
-- 4) write result
process(clk)
begin
if(rising_edge(clk)) then
if(start = '1') then
count <= (others => '0');
elsif(enable = '1') then
count <= std_logic_vector(unsigned(count) + 1);
else
count <= count;
end if;
end if;
end process;
-- select the inputs for the multiplies
coef <= std_logic_vector(512 - unsigned('0' & temporalSmoothingRatio)) when count(1 downto 0) = "01" else ('0' & temporalSmoothingRatio);
with count(1 downto 0) select Rin <=
in_data( 7 downto 0) when "01",
ram_data_out( 7 downto 0) when "10",
(others => '0') when others;
with count(1 downto 0) select Gin <=
in_data(15 downto 8) when "01",
ram_data_out(15 downto 8) when "10",
(others => '0') when others;
with count(1 downto 0) select Bin <=
in_data(23 downto 16) when "01",
ram_data_out(23 downto 16) when "10",
(others => '0') when others;
Radd <= (others => '0') when count(1 downto 0) /= "10" else Rprod;
Gadd <= (others => '0') when count(1 downto 0) /= "10" else Gprod;
Badd <= (others => '0') when count(1 downto 0) /= "10" else Bprod;
process(clk)
begin
if(rising_edge(clk)) then
Rprod <= std_logic_vector(unsigned("0" & Rin & "000000000") * unsigned("00000000" & coef) + unsigned(Radd));
Gprod <= std_logic_vector(unsigned("0" & Gin & "000000000") * unsigned("00000000" & coef) + unsigned(Gadd));
Bprod <= std_logic_vector(unsigned("0" & Bin & "000000000") * unsigned("00000000" & coef) + unsigned(Badd));
end if;
end process;
-- counter for tick delay, start counting down toward zero when copying of current results finishes
process(clk)
begin
if(rising_edge(clk)) then
if(enable = '1') then
tickcount <= delayTicks;
elsif(unsigned(tickcount) /= 0) then
tickcount <= std_logic_vector(unsigned(tickcount) - 1);
end if;
end if;
end process;
enable <= not count(10);
-- signal out_vblank after copy has finished and tickcount has reached zero
done <= '1' when unsigned(tickcount) = 0 and enable = '0' else '0';
process(clk)
begin
if(rising_edge(clk)) then
out_vblank <= '0';
if(done = '1' and lastdone = '0') then
out_vblank <= '1';
end if;
lastdone <= done;
end if;
end process;
in_addr <= count(9 downto 2);
ram_addr_in <= count_ram_in & count(9 downto 2);
ram_data_in <= "00000000" & Bprod(25 downto 18) & Gprod(25 downto 18) & Rprod(25 downto 18);
ram_wr_in <= '1' when count(1 downto 0) = "11" else '0';
ram_addr_out <= (count_ram_in_prev & count(9 downto 2)) when enable = '1' else (count_ram_out & out_addr);
out_data <= ram_data_out;
end Behavioral;
| gpl-2.0 | 9318a87f0767338190675a2f3451205a | 0.640904 | 3.191981 | false | false | false | false |
freecores/gpib_controller | vhdl/test/gpib_DT_Test.vhd | 1 | 13,686 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Author: Andrzej Paluch
--
-- Create Date: 23:21:05 10/21/2011
-- Design Name:
-- Module Name: /windows/h/projekty/elektronika/USB_to_HPIB/usbToHpib/test_scr//gpibInterfaceTest.vhd
-- Project Name: usbToHpib
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: gpibInterface
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use work.gpibComponents.all;
use work.helperComponents.all;
ENTITY gpib_DT_Test IS
END gpib_DT_Test;
ARCHITECTURE behavior OF gpib_DT_Test IS
-- Component Declaration for the Unit Under Test (UUT)
component gpibCableEmulator is port (
-- interface signals
DIO_1 : in std_logic_vector (7 downto 0);
output_valid_1 : in std_logic;
DIO_2 : in std_logic_vector (7 downto 0);
output_valid_2 : in std_logic;
DIO : out std_logic_vector (7 downto 0);
-- attention
ATN_1 : in std_logic;
ATN_2 : in std_logic;
ATN : out std_logic;
-- data valid
DAV_1 : in std_logic;
DAV_2 : in std_logic;
DAV : out std_logic;
-- not ready for data
NRFD_1 : in std_logic;
NRFD_2 : in std_logic;
NRFD : out std_logic;
-- no data accepted
NDAC_1 : in std_logic;
NDAC_2 : in std_logic;
NDAC : out std_logic;
-- end or identify
EOI_1 : in std_logic;
EOI_2 : in std_logic;
EOI : out std_logic;
-- service request
SRQ_1 : in std_logic;
SRQ_2 : in std_logic;
SRQ : out std_logic;
-- interface clear
IFC_1 : in std_logic;
IFC_2 : in std_logic;
IFC : out std_logic;
-- remote enable
REN_1 : in std_logic;
REN_2 : in std_logic;
REN : out std_logic
);
end component;
-- inputs common
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal T1 : std_logic_vector(7 downto 0) := "00000100";
-- inputs 1
signal data_1 : std_logic_vector(7 downto 0) := (others => '0');
signal status_byte_1 : std_logic_vector(7 downto 0) := (others => '0');
signal rdy_1 : std_logic := '0';
signal nba_1 : std_logic := '0';
signal ltn_1 : std_logic := '0';
signal lun_1 : std_logic := '0';
signal lon_1 : std_logic := '0';
signal ton_1 : std_logic := '0';
signal endOf_1 : std_logic := '0';
signal gts_1 : std_logic := '0';
signal rpp_1 : std_logic := '0';
signal tcs_1 : std_logic := '0';
signal tca_1 : std_logic := '0';
signal sic_1 : std_logic := '0';
signal rsc_1 : std_logic := '0';
signal sre_1 : std_logic := '0';
signal rtl_1 : std_logic := '0';
signal rsv_1 : std_logic := '0';
signal ist_1 : std_logic := '0';
signal lpe_1 : std_logic := '0';
-- inputs 2
signal data_2 : std_logic_vector(7 downto 0) := (others => '0');
signal status_byte_2 : std_logic_vector(7 downto 0) := (others => '0');
signal rdy_2 : std_logic := '0';
signal nba_2 : std_logic := '0';
signal ltn_2 : std_logic := '0';
signal lun_2 : std_logic := '0';
signal lon_2 : std_logic := '0';
signal ton_2 : std_logic := '0';
signal endOf_2 : std_logic := '0';
signal gts_2 : std_logic := '0';
signal rpp_2 : std_logic := '0';
signal tcs_2 : std_logic := '0';
signal tca_2 : std_logic := '0';
signal sic_2 : std_logic := '0';
signal rsc_2 : std_logic := '0';
signal sre_2 : std_logic := '0';
signal rtl_2 : std_logic := '0';
signal rsv_2 : std_logic := '0';
signal ist_2 : std_logic := '0';
signal lpe_2 : std_logic := '0';
-- outputs 1
signal dvd_1 : std_logic;
signal wnc_1 : std_logic;
signal tac_1 : std_logic;
signal cwrc_1 : std_logic;
signal cwrd_1 : std_logic;
signal clr_1 : std_logic;
signal trg_1 : std_logic;
signal atl_1 : std_logic;
signal att_1 : std_logic;
signal mla_1 : std_logic;
signal lsb_1 : std_logic;
signal spa_1 : std_logic;
signal ppr_1 : std_logic;
signal sreq_1 : std_logic;
signal isLocal_1 : std_logic;
signal currentSecAddr_1 : std_logic_vector (4 downto 0);
-- outputs 2
signal dvd_2 : std_logic;
signal wnc_2 : std_logic;
signal tac_2 : std_logic;
signal cwrc_2 : std_logic;
signal cwrd_2 : std_logic;
signal clr_2 : std_logic;
signal trg_2 : std_logic;
signal atl_2 : std_logic;
signal att_2 : std_logic;
signal mla_2 : std_logic;
signal lsb_2 : std_logic;
signal spa_2 : std_logic;
signal ppr_2 : std_logic;
signal sreq_2 : std_logic;
signal isLocal_2 : std_logic;
signal currentSecAddr_2 : std_logic_vector (4 downto 0);
-- common
signal DO : std_logic_vector (7 downto 0);
signal DI_1 : std_logic_vector (7 downto 0);
signal output_valid_1 : std_logic;
signal DI_2 : std_logic_vector (7 downto 0);
signal output_valid_2 : std_logic;
signal ATN_1, ATN_2, ATN : std_logic;
signal DAV_1, DAV_2, DAV : std_logic;
signal NRFD_1, NRFD_2, NRFD : std_logic;
signal NDAC_1, NDAC_2, NDAC : std_logic;
signal EOI_1, EOI_2, EOI : std_logic;
signal SRQ_1, SRQ_2, SRQ : std_logic;
signal IFC_1, IFC_2, IFC : std_logic;
signal REN_1, REN_2, REN : std_logic;
-- gpib reader
signal buf_interrupt : std_logic;
signal data_available : std_logic;
signal last_byte_addr : std_logic_vector (3 downto 0);
signal end_of_stream : std_logic;
signal byte_addr : std_logic_vector (3 downto 0);
signal data_out : std_logic_vector (7 downto 0);
signal reset_buffer : std_logic := '0';
signal dataSecAddr : std_logic_vector (4 downto 0);
-- gpib writer
signal w_last_byte_addr : std_logic_vector (3 downto 0)
:= (others => '0');
signal w_end_of_stream : std_logic := '0';
signal w_data_available : std_logic := '0';
signal w_buf_interrupt : std_logic;
signal w_data_in : std_logic_vector (7 downto 0);
signal w_byte_addr : std_logic_vector (3 downto 0);
signal w_reset_buffer : std_logic := '0';
type WR_BUF_TYPE is
array (0 to 15) of std_logic_vector (7 downto 0);
signal w_write_buffer : WR_BUF_TYPE;
-- Clock period definitions
constant clk_period : time := 2ps;
BEGIN
-- Instantiate the Unit Under Test (UUT)
gpib1: gpibInterface PORT MAP (
clk => clk,
reset => reset,
isLE => '0',
isTE => '0',
lpeUsed => '0',
fixedPpLine => "000",
eosUsed => '0',
eosMark => "00000000",
myListAddr => "00001",
myTalkAddr => "00001",
secAddrMask => (others => '0'),
data => data_1,
status_byte => status_byte_1,
T1 => T1,
rdy => rdy_1,
nba => nba_1,
ltn => ltn_1,
lun => lun_1,
lon => lon_1,
ton => ton_1,
endOf => endOf_1,
gts => gts_1,
rpp => rpp_1,
tcs => tcs_1,
tca => tca_1,
sic => sic_1,
rsc => rsc_1,
sre => sre_1,
rtl => rtl_1,
rsv => rsv_1,
ist => ist_1,
lpe => lpe_1,
dvd => dvd_1,
wnc => wnc_1,
tac => tac_1,
cwrc => cwrc_1,
cwrd => cwrd_1,
clr => clr_1,
trg => trg_1,
atl => atl_1,
att => att_1,
mla => mla_1,
lsb => lsb_1,
spa => spa_1,
ppr => ppr_1,
sreq => sreq_1,
isLocal => isLocal_1,
currentSecAddr => currentSecAddr_1,
DI => DO,
DO => DI_1,
output_valid => output_valid_1,
ATN_in => ATN,
ATN_out => ATN_1,
DAV_in => DAV,
DAV_out => DAV_1,
NRFD_in => NRFD,
NRFD_out => NRFD_1,
NDAC_in => NDAC,
NDAC_out => NDAC_1,
EOI_in => EOI,
EOI_out => EOI_1,
SRQ_in => SRQ,
SRQ_out => SRQ_1,
IFC_in => IFC,
IFC_out => IFC_1,
REN_in => REN,
REN_out => REN_1
);
-- Instantiate the Unit Under Test (UUT)
gpib2: gpibInterface PORT MAP (
clk => clk,
reset => reset,
isLE => '0',
isTE => '0',
lpeUsed => '0',
fixedPpLine => "000",
eosUsed => '0',
eosMark => "00000000",
myListAddr => "00010",
myTalkAddr => "00010",
secAddrMask => (others => '0'),
data => data_2,
status_byte => status_byte_2,
T1 => T1,
rdy => rdy_2,
nba => nba_2,
ltn => ltn_2,
lun => lun_2,
lon => lon_2,
ton => ton_2,
endOf => endOf_2,
gts => gts_2,
rpp => rpp_2,
tcs => tcs_2,
tca => tca_2,
sic => sic_2,
rsc => rsc_2,
sre => sre_2,
rtl => rtl_2,
rsv => rsv_2,
ist => ist_2,
lpe => lpe_2,
dvd => dvd_2,
wnc => wnc_2,
tac => tac_2,
cwrc => cwrc_2,
cwrd => cwrd_2,
clr => clr_2,
trg => trg_2,
atl => atl_2,
att => att_2,
mla => mla_2,
lsb => lsb_2,
spa => spa_2,
ppr => ppr_2,
sreq => sreq_2,
isLocal => isLocal_2,
currentSecAddr => currentSecAddr_2,
DI => DO,
DO => DI_2,
output_valid => output_valid_2,
ATN_in => ATN,
ATN_out => ATN_2,
DAV_in => DAV,
DAV_out => DAV_2,
NRFD_in => NRFD,
NRFD_out => NRFD_2,
NDAC_in => NDAC,
NDAC_out => NDAC_2,
EOI_in => EOI,
EOI_out => EOI_2,
SRQ_in => SRQ,
SRQ_out => SRQ_2,
IFC_in => IFC,
IFC_out => IFC_2,
REN_in => REN,
REN_out => REN_2
);
ce: gpibCableEmulator port map (
-- interface signals
DIO_1 => DI_1,
output_valid_1 => output_valid_1,
DIO_2 => DI_2,
output_valid_2 => output_valid_2,
DIO => DO,
-- attention
ATN_1 => ATN_1, ATN_2 => ATN_2, ATN => ATN,
DAV_1 => DAV_1, DAV_2 => DAV_2, DAV => DAV,
NRFD_1 => NRFD_1, NRFD_2 => NRFD_2, NRFD => NRFD,
NDAC_1 => NDAC_1, NDAC_2 => NDAC_2, NDAC => NDAC,
EOI_1 => EOI_1, EOI_2 => EOI_2, EOI => EOI,
SRQ_1 => SRQ_1, SRQ_2 => SRQ_2, SRQ => SRQ,
IFC_1 => IFC_1, IFC_2 => IFC_2, IFC => IFC,
REN_1 => REN_1, REN_2 => REN_2, REN => REN
);
gr: gpibReader generic map (ADDR_WIDTH => 4) port map (
clk => clk, reset => reset,
------------------------------------------------------------------------
------ GPIB interface --------------------------------------------------
------------------------------------------------------------------------
data_in => DO, dvd => dvd_2, atl => atl_2, lsb => lsb_2, rdy => rdy_2,
------------------------------------------------------------------------
------ external interface ----------------------------------------------
------------------------------------------------------------------------
isLE => '0', secAddr => (others => '0'), dataSecAddr => dataSecAddr,
buf_interrupt => buf_interrupt, data_available => data_available,
last_byte_addr => last_byte_addr, end_of_stream => end_of_stream,
byte_addr => byte_addr, data_out => data_out,
reset_buffer => reset_buffer
);
w_data_in <= w_write_buffer(conv_integer(w_byte_addr));
gw: gpibWriter generic map (ADDR_WIDTH => 4) port map (
clk => clk, reset => reset,
------------------------------------------------------------------------
------ GPIB interface --------------------------------------------------
------------------------------------------------------------------------
data_out => data_1, wnc => wnc_1, spa => spa_1, nba => nba_1,
endOf => endOf_1, att => att_1, cwrc => cwrc_1,
------------------------------------------------------------------------
------ external interface ----------------------------------------------
------------------------------------------------------------------------
isTE => '0', secAddr => (others => '0'), dataSecAddr => (others => '0'),
last_byte_addr => w_last_byte_addr, end_of_stream => w_end_of_stream,
data_available => w_data_available, buf_interrupt => w_buf_interrupt,
data_in => w_data_in, byte_addr => w_byte_addr,
reset_buffer => w_reset_buffer
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 10 clock periods.
reset <= '1';
wait for clk_period*10;
reset <= '0';
wait for clk_period*10;
-- requests system control
rsc_1 <= '1';
-- interface clear
sic_1 <= '1';
wait until IFC_1 = '1';
sic_1 <= '0';
wait until IFC_1 = '0';
assert trg_1 = '0';
assert trg_2 = '0';
-- send GET (device clear)
w_write_buffer(0) <= "00001000";
w_last_byte_addr <= "0000";
w_data_available <= '1';
wait until w_buf_interrupt='1';
assert trg_1 = '0';
assert trg_2 = '0';
w_reset_buffer <= '1';
wait for clk_period*2;
w_reset_buffer <= '0';
-- gpib2 to listen
w_write_buffer(0) <= "00100010";
w_last_byte_addr <= "0000";
w_data_available <= '1';
wait until w_buf_interrupt='1';
assert trg_1 = '0';
assert trg_2 = '0';
w_reset_buffer <= '1';
wait for clk_period*2;
w_reset_buffer <= '0';
-- send GET
w_write_buffer(0) <= "00001000";
w_last_byte_addr <= "0000";
w_data_available <= '1';
wait until w_buf_interrupt='1';
assert trg_1 = '0';
assert trg_2 = '1';
report "$$$ END OF TEST - DT (device trigger) $$$";
wait;
end process;
END;
| gpl-3.0 | 9213a5ec656342042d552534b424f079 | 0.561304 | 2.876419 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | filtering_algorithm_RTL/source/vhdl/filtering_algorithm_single.vhd | 1 | 24,146 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: filtering_alogrithm_single - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.filtering_algorithm_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity filtering_alogrithm_single is
port (
clk : in std_logic;
sclr : in std_logic;
start : in std_logic;
-- initial parameters
k : in centre_index_type;
root_address : in node_address_type;
-- init node and centre memory
wr_init_cent : in std_logic;
wr_centre_list_address_init : in centre_list_address_type;
wr_centre_list_data_init : in centre_index_type;
wr_init_node : in std_logic;
wr_node_address_init : in node_address_type;
wr_node_data_init : in node_data_type;
wr_init_pos : in std_logic;
wr_centre_list_pos_address_init : in centre_index_type;
wr_centre_list_pos_data_init : in data_type;
-- access centre buffer
rdo_centre_buffer : in std_logic;
centre_buffer_addr : in centre_index_type;
valid : out std_logic;
wgtCent_out : out data_type_ext;
sum_sq_out : out coord_type_ext;
count_out : out coord_type;
-- processing done
rdy : out std_logic
);
end filtering_alogrithm_single;
architecture Behavioral of filtering_alogrithm_single is
constant STACK_LAT : integer := 3;
type state_type is (idle, init, processing_phase1, processing_phase2, done);
type schedule_state_type is (free, busy, wait_cycle);
type node_addr_delay_type is array(0 to STACK_LAT-1) of node_address_type;
type centre_list_addr_delay_type is array(0 to STACK_LAT-1) of centre_list_address_type;
type k_delay_type is array(0 to STACK_LAT-1) of centre_index_type;
component memory_mgmt
port (
clk : in std_logic;
sclr : in std_logic;
rd : in std_logic;
rd_node_addr : in node_address_type;
rd_centre_list_address : in centre_list_address_type;
rd_k : in centre_index_type;
wr_cent_nd : in std_logic;
wr_cent : in std_logic;
wr_centre_list_address : in centre_list_address_type;
wr_centre_list_data : in centre_index_type;
wr_init_cent : in std_logic;
wr_centre_list_address_init : in centre_list_address_type;
wr_centre_list_data_init : in centre_index_type;
wr_init_node : in std_logic;
wr_node_address_init : in node_address_type;
wr_node_data_init : in node_data_type;
wr_init_pos : in std_logic;
wr_centre_list_pos_address_init : in centre_index_type;
wr_centre_list_pos_data_init : in data_type;
valid : out std_logic;
rd_node_data : out node_data_type;
rd_centre_list_data : out centre_index_type;
rd_centre_list_pos_data : out data_type;
last_centre : out std_logic;
item_read_twice : out std_logic;
rd_centre_list_address_out : out centre_list_address_type
);
end component;
component process_tree_node
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
u_in : in node_data_type;
centre_positions_in : in data_type;
centre_indices_in : in centre_index_type;
update_centre_buffer : out std_logic;
final_index_out : out centre_index_type;
sum_sq_out : out coord_type_ext;
rdy : out std_logic;
dead_end : out std_logic;
u_out : out node_data_type;
k_out : out centre_index_type;
centre_index_rdy : out std_logic;
centre_index_wr : out std_logic;
centre_indices_out : out centre_index_type
);
end component;
component centre_buffer_mgmt
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
init : in std_logic;
addr_in_init : in centre_index_type;
request_rdo : in std_logic;
addr_in : in centre_index_type;
wgtCent_in : in data_type_ext;
sum_sq_in : in coord_type_ext;
count_in : in coord_type;
valid : out std_logic;
wgtCent_out : out data_type_ext;
sum_sq_out : out coord_type_ext;
count_out : out coord_type
);
end component;
component stack_top
port (
clk : in STD_LOGIC;
sclr : in STD_LOGIC;
push : in std_logic;
pop : in std_logic;
node_addr_in_1 : in node_address_type;
node_addr_in_2 : in node_address_type;
cntr_addr_in_1 : in centre_list_address_type;
cntr_addr_in_2 : in centre_list_address_type;
k_in_1 : in centre_index_type;
k_in_2 : in centre_index_type;
node_addr_out : out node_address_type;
cntr_addr_out : out centre_list_address_type;
k_out : out centre_index_type;
empty : out std_logic;
valid : out std_logic
);
end component;
component allocator
generic (
MEMORY_SIZE : integer := 1024
);
port (
clk : in std_logic;
sclr : in std_logic;
alloc : in std_logic;
free : in std_logic;
address_in : in std_logic_vector(integer(ceil(log2(real(MEMORY_SIZE))))-1 downto 0);
rdy : out std_logic;
address_out : out std_logic_vector(integer(ceil(log2(real(MEMORY_SIZE))))-1 downto 0);
heap_full : out std_logic
);
end component;
-- fsm
signal state : state_type;
signal start_processing : std_logic;
signal processing_done : std_logic;
signal processing_counter_enable : std_logic;
signal processing_done_value : unsigned(INDEX_BITWIDTH+1-1 downto 0);
signal processing_done_counter : unsigned(INDEX_BITWIDTH+1-1 downto 0);
-- memory mgmt
signal memory_mgmt_rd : std_logic;
signal memory_data_valid : std_logic;
signal memory_mgmt_last_centre : std_logic;
signal memory_mgmt_item_read_twice : std_logic;
--signal memory_data_valid_reg : std_logic;
signal rd_node_addr : node_address_type;
signal rd_centre_list_address : centre_list_address_type;
signal rd_k : centre_index_type;
signal rd_node_data : node_data_type;
signal rd_centre_indices : centre_index_type;
signal rd_centre_positions : data_type;
signal rd_centre_list_address_out : centre_list_address_type;
signal rd_centre_list_address_out_reg : centre_list_address_type;
-- process_tree_node
signal ptn_update_centre_buffer : std_logic;
signal ptn_final_index_out : centre_index_type;
signal ptn_sum_sq_out : coord_type_ext;
signal ptn_rdy : std_logic;
signal ptn_dead_end : std_logic;
signal ptn_u_out : node_data_type;
signal ptn_k_out : centre_index_type;
signal ptn_centre_index_rdy : std_logic;
signal ptn_centre_index_rdy_reg : std_logic;
signal ptn_centre_index_wr : std_logic;
signal ptn_centre_indices_out : centre_index_type;
-- centre buffer mgmt
signal tmp_addr : centre_index_type;
-- stack
signal stack_push : std_logic;
signal stack_push_reg : std_logic;
signal stack_pop : std_logic;
signal node_stack_addr_in_1 : node_address_type;
signal node_stack_addr_in_2 : node_address_type;
signal cntr_stack_addr_in : centre_list_address_type;
signal cntr_stack_addr_in_reg : centre_list_address_type;
signal cntr_stack_k_in : centre_index_type;
signal stack_valid : std_logic;
signal stack_empty : std_logic;
signal node_stack_addr_out : node_address_type;
signal cntr_stack_addr_out : centre_list_address_type;
signal cntr_stack_k_out : centre_index_type;
-- scheduler
signal schedule_state : schedule_state_type;
signal schedule_counter : centre_index_type;
signal schedule_counter_done : std_logic;
signal schedule_k_reg : centre_index_type;
signal schedule_next : std_logic;
-- allocator
signal allocator_free : std_logic;
signal allocator_free_1 : std_logic;
signal allocator_free_2 : std_logic;
signal allocator_free_reg : std_logic;
signal allocator_free_address : centre_list_address_type;
signal allocator_alloc : std_logic;
signal allocator_rdy : std_logic;
signal allocator_address_out : centre_list_address_type;
signal allocator_address_out_reg : centre_list_address_type;
signal allocator_heap_full : std_logic;
-- debug and stats (not synthesised)
signal debug_u_left : node_address_type;
signal debug_u_right : node_address_type;
signal first_start : std_logic := '0';
signal visited_nodes : unsigned(31 downto 0);
signal cycle_count : unsigned(31 downto 0);
signal debug_stack_counter : unsigned(31 downto 0);
signal debug_max_stack_counter : unsigned(31 downto 0);
begin
G_NOSYNTH_0 : if SYNTHESIS = false generate
-- some statistics
vn_counter_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
visited_nodes <= (others=> '0');
elsif ptn_rdy = '1' then
visited_nodes <= visited_nodes+1;
end if;
if start = '1' then
first_start <= '1'; -- latch the first start assertion
end if;
if first_start = '0' then
cycle_count <= (others=> '0');
else -- count cycles for all iterations
cycle_count <= cycle_count+1;
end if;
if sclr = '1' then
debug_stack_counter <= (others=>'0');
debug_max_stack_counter <= (others=>'0');
else
if debug_max_stack_counter < debug_stack_counter then
debug_max_stack_counter <= debug_stack_counter;
end if;
if stack_push = '1' AND stack_pop = '0' then
debug_stack_counter <= debug_stack_counter+2;
elsif stack_push = '0' AND stack_pop = '1' then
debug_stack_counter <= debug_stack_counter-1;
end if;
end if;
end if;
end process vn_counter_proc;
end generate G_NOSYNTH_0;
fsm_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
-- state <= idle;
--elsif state = idle AND wr_init_pos = '1' then
state <= init;
elsif state = init AND start = '1' then
state <= processing_phase1;
elsif state = processing_phase1 AND ptn_rdy = '1' then
state <= processing_phase2;
elsif state = processing_phase2 AND processing_done = '1' then
state <= done;
elsif state = done then
state <= init;
end if;
end if;
end process fsm_proc;
start_processing <= '1' WHEN state = init AND start = '1' ELSE '0';
-- scheduler (decides when the next item is popped from stack)
scheduler_proc : process(clk)
--variable var_schedule_next : std_logic;
--variable var_counter_done : std_logic;
begin
if rising_edge(clk) then
--var_schedule_next := '0';
if schedule_state = busy AND stack_valid = '1' then
schedule_k_reg <= cntr_stack_k_out;
elsif schedule_state = free then
schedule_k_reg <= (others => '1');
end if;
if sclr = '1' then
schedule_state <= free;
elsif schedule_state = free AND schedule_next = '1' then
schedule_state <= busy;
elsif schedule_state = busy AND schedule_counter_done = '1' then
schedule_state <= free;
end if;
if sclr = '1' OR schedule_state = free then
schedule_counter <= to_unsigned(0,INDEX_BITWIDTH);
elsif schedule_state = busy AND schedule_counter_done = '0' then
schedule_counter <= schedule_counter+1;
end if;
end if;
end process scheduler_proc;
schedule_next <= '1' WHEN schedule_state = free AND stack_empty = '0' AND stack_push = '0' AND stack_push_reg = '0' ELSE '0';
schedule_counter_done <= '1' WHEN (stack_valid = '1' AND schedule_counter >= cntr_stack_k_out) OR (stack_valid = '0' AND schedule_counter >= schedule_k_reg) ELSE '0';
memory_mgmt_rd <= stack_valid WHEN state = processing_phase2 ELSE start_processing;
rd_node_addr <= root_address WHEN start_processing = '1' ELSE
node_stack_addr_out;
rd_centre_list_address <= std_logic_vector(to_unsigned(0,CNTR_POINTER_BITWIDTH)) WHEN start_processing = '1' ELSE
cntr_stack_addr_out;
rd_k <= k WHEN start_processing = '1' ELSE
cntr_stack_k_out;
memory_mgmt_inst : memory_mgmt
port map (
clk => clk,
sclr => sclr,
rd => memory_mgmt_rd,
rd_node_addr => rd_node_addr,
rd_centre_list_address => rd_centre_list_address,
rd_k => rd_k,
wr_cent_nd => ptn_centre_index_rdy,
wr_cent => ptn_centre_index_wr,
wr_centre_list_address => allocator_address_out,
wr_centre_list_data => ptn_centre_indices_out,
wr_init_cent => wr_init_cent,
wr_centre_list_address_init => wr_centre_list_address_init,
wr_centre_list_data_init => wr_centre_list_data_init,
wr_init_node => wr_init_node,
wr_node_address_init => wr_node_address_init,
wr_node_data_init => wr_node_data_init,
wr_init_pos => wr_init_pos,
wr_centre_list_pos_address_init => wr_centre_list_pos_address_init,
wr_centre_list_pos_data_init => wr_centre_list_pos_data_init,
valid => memory_data_valid,
rd_node_data => rd_node_data,
rd_centre_list_data => rd_centre_indices,
rd_centre_list_pos_data => rd_centre_positions,
last_centre => memory_mgmt_last_centre,
item_read_twice => memory_mgmt_item_read_twice,
rd_centre_list_address_out => rd_centre_list_address_out
);
process_tree_node_inst : process_tree_node
port map (
clk => clk,
sclr => sclr,
nd => memory_data_valid,
u_in => rd_node_data,
centre_positions_in => rd_centre_positions,
centre_indices_in => rd_centre_indices,
update_centre_buffer => ptn_update_centre_buffer,
final_index_out => ptn_final_index_out,
sum_sq_out => ptn_sum_sq_out,
rdy => ptn_rdy,
dead_end => ptn_dead_end,
u_out => ptn_u_out,
k_out => ptn_k_out,
centre_index_rdy => ptn_centre_index_rdy,
centre_index_wr => ptn_centre_index_wr,
centre_indices_out => ptn_centre_indices_out
);
debug_u_left <= ptn_u_out.left;
debug_u_right <= ptn_u_out.right;
tmp_addr <= ptn_final_index_out WHEN rdo_centre_buffer = '0' ELSE centre_buffer_addr;
centre_buffer_mgmt_inst : centre_buffer_mgmt
port map (
clk => clk,
sclr => sclr,
init => wr_init_pos,
addr_in_init => wr_centre_list_pos_address_init,
nd => ptn_update_centre_buffer,
request_rdo => rdo_centre_buffer,
addr_in => tmp_addr,
wgtCent_in => ptn_u_out.wgtCent,
sum_sq_in => ptn_sum_sq_out,
count_in => ptn_u_out.count,
valid => valid,
wgtCent_out => wgtCent_out,
sum_sq_out => sum_sq_out,
count_out => count_out
);
-- used to prevent pops right after a push
stack_push_reg_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
stack_push_reg <= '0';
else
stack_push_reg <= stack_push;
end if;
end if;
end process stack_push_reg_proc;
stack_pop <= schedule_next;
stack_push <= ptn_rdy AND NOT(ptn_dead_end);
node_stack_addr_in_1 <= ptn_u_out.right;
node_stack_addr_in_2 <= ptn_u_out.left;
stack_top_inst : stack_top
port map(
clk => clk,
sclr => sclr,
push => stack_push,
pop => stack_pop,
node_addr_in_1 => node_stack_addr_in_1,
node_addr_in_2 => node_stack_addr_in_2,
cntr_addr_in_1 => cntr_stack_addr_in,
cntr_addr_in_2 => cntr_stack_addr_in,
k_in_1 => cntr_stack_k_in,
k_in_2 => cntr_stack_k_in,
node_addr_out => node_stack_addr_out,
cntr_addr_out => cntr_stack_addr_out,
k_out => cntr_stack_k_out,
empty => stack_empty,
valid => stack_valid
);
G_NO_DYN_ALLOC : if DYN_ALLOC = false generate
-- generate a unique address for each centre list written to memory
inc_centre_list_addr_proc : process(clk)
variable new_cntr_stack_addr_in : unsigned(CNTR_POINTER_BITWIDTH-1 downto 0);
begin
if rising_edge(clk) then
if sclr = '1' then
cntr_stack_addr_in <= std_logic_vector(to_unsigned(1,CNTR_POINTER_BITWIDTH));
else
if ptn_rdy = '1' AND ptn_dead_end = '0' then
new_cntr_stack_addr_in := unsigned(cntr_stack_addr_in)+1;
cntr_stack_addr_in <= std_logic_vector(new_cntr_stack_addr_in);
end if;
end if;
end if;
end process inc_centre_list_addr_proc;
cntr_stack_k_in <= ptn_k_out;
allocator_address_out <= cntr_stack_addr_in;
end generate G_NO_DYN_ALLOC;
G_DYN_ALLOC : if DYN_ALLOC = true generate
allocator_ctrl_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
ptn_centre_index_rdy_reg <= '0';
allocator_free_reg <= '0';
else
ptn_centre_index_rdy_reg <= ptn_centre_index_rdy;
if allocator_free_1 = '1' AND allocator_free_2 = '1' then --two free requests at the same time?
allocator_free_reg <= '1';
else
allocator_free_reg <= '0';
end if;
end if;
if allocator_rdy = '1' then
allocator_address_out_reg <= allocator_address_out;
end if ;
rd_centre_list_address_out_reg <= rd_centre_list_address_out;
end if;
end process allocator_ctrl_proc;
allocator_free_1 <= ptn_rdy AND ptn_dead_end;
allocator_free_2 <= memory_mgmt_last_centre AND memory_mgmt_item_read_twice;
allocator_free_address <= allocator_address_out_reg WHEN (allocator_free_1 = '1' AND allocator_free_2 = '0') OR (allocator_free_1 = '1' AND allocator_free_2 = '1') ELSE
rd_centre_list_address_out WHEN allocator_free_1 = '0' AND allocator_free_2 = '1' ELSE
rd_centre_list_address_out_reg;
allocator_free <= allocator_free_1 OR allocator_free_2 OR allocator_free_reg;
allocator_alloc <= ptn_centre_index_rdy AND NOT(ptn_centre_index_rdy_reg); -- first cycle only --ptn_rdy AND NOT(ptn_dead_end);
allocator_inst : allocator
generic map (
MEMORY_SIZE => HEAP_SIZE
)
port map (
clk => clk,
sclr => wr_init_node,--sclr,
alloc => allocator_alloc,
free => allocator_free,
address_in => allocator_free_address,
rdy => allocator_rdy,
address_out => allocator_address_out,
heap_full => allocator_heap_full
);
cntr_stack_addr_in <= allocator_address_out_reg;
cntr_stack_k_in <= k WHEN allocator_address_out_reg = std_logic_vector(to_unsigned(0,CNTR_POINTER_BITWIDTH)) ELSE ptn_k_out;
end generate G_DYN_ALLOC;
processing_done_counter_proc : process(clk)
begin
if rising_edge(clk) then
if start_processing = '1' then
processing_done_value <= k+to_unsigned(38+100,INDEX_BITWIDTH+1);
end if;
if sclr = '1' OR state = processing_phase1 OR state = done then
processing_counter_enable <= '0';
else
if state = processing_phase2 AND ptn_rdy = '1' then
processing_counter_enable <= '1';
end if;
end if;
if sclr = '1' OR state = processing_phase1 then
processing_done_counter <= (others => '0');
elsif processing_counter_enable = '1' AND ptn_rdy = '0' then
processing_done_counter <= processing_done_counter+1;
elsif processing_counter_enable = '1' AND ptn_rdy = '1' then
processing_done_counter <= (others => '0');
end if;
end if;
end process processing_done_counter_proc;
-- output
processing_done <= '1' WHEN processing_done_counter = processing_done_value ELSE '0';
rdy <= processing_done;
end Behavioral;
| bsd-3-clause | 4916e1b5eccf5ece64f54936383a0511 | 0.518968 | 4.050663 | false | false | false | false |
leekeith/riscy_vee | reg_x.vhd | 1 | 600 | library ieee;
use ieee.std_logic_1164.all;
use ieee.Numeric_std.all;
entity reg_x is
port(
clk : in std_logic;
rst_n : in std_logic;
sel : in std_logic;
w_enable : in std_logic;
r_enable : in std_logic;
d_in : in std_logic_vector(31 downto 0);
d_out : out std_logic_vector(31 downto 0)
);
end reg_x;
architecture desc of reg_x is
begin
process (clk, rst_n)
begin
if rst_n = '0' then
d_out <= x"00000000";
elsif clk'event and clk = '1' and sel = '1' then
if w_enable = '1' then
d_out <= d_in;
end if;
end if;
end process;
end desc; | gpl-3.0 | 86b7eb4a07ab1e2e63ceb6a2e608c383 | 0.598333 | 2.409639 | false | false | false | false |
UdayanSinha/Code_Blocks | VHDL/Projects/work/int_to_7seg_pack.vhd | 1 | 641 | LIBRARY IEEE; -- These lines informs the compiler that the library IEEE is used
USE IEEE.std_logic_1164.all; -- contains the definition for the std_logic type plus some useful conversion functions
PACKAGE int_to_7seg_pack IS
TYPE logic_vector_array IS ARRAY (0 TO 9) OF STD_LOGIC_VECTOR (7 DOWNTO 0);
END PACKAGE int_to_7seg_pack;
PACKAGE BODY int_to_7seg_pack IS
PROCEDURE int_to_bcd(SIGNAL int_val : IN INTEGER; SIGNAL bcd2, bcd1, bcd0: OUT INTEGER) IS
VARIABLE temp: INTEGER:=int_val;
BEGIN
bcd0<=temp MOD 10;
temp:=temp/10;
bcd1<=temp MOD 10;
bcd2<=temp/10;
END int_to_bcd;
END int_to_7seg_pack; | mit | 22db28c56bfc7bd38e96ec40de32f596 | 0.708268 | 3.142157 | false | false | false | false |
freecores/gpib_controller | vhdl/src/wrapper/gpibBusReg.vhd | 1 | 2,023 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: gpibBusReg
-- Date:2011-11-13
-- Author: Andrzej Paluch
--
-- Description ${cursor}
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity gpibBusReg is
port (
data_out : out std_logic_vector (15 downto 0);
------------------------------------------------
-- interface signals
DIO : in std_logic_vector (7 downto 0);
-- attention
ATN : in std_logic;
-- data valid
DAV : in std_logic;
-- not ready for data
NRFD : in std_logic;
-- no data accepted
NDAC : in std_logic;
-- end or identify
EOI : in std_logic;
-- service request
SRQ : in std_logic;
-- interface clear
IFC : in std_logic;
-- remote enable
REN : in std_logic
);
end gpibBusReg;
architecture arch of gpibBusReg is
begin
data_out(7 downto 0) <= DIO;
data_out(8) <= ATN;
data_out(9) <= DAV;
data_out(10) <= NRFD;
data_out(11) <= NDAC;
data_out(12) <= EOI;
data_out(13) <= SRQ;
data_out(14) <= IFC;
data_out(15) <= REN;
end arch;
| gpl-3.0 | 50de70250d2ab278749a9b13b8344fae | 0.591201 | 3.625448 | false | false | false | false |
RickvanLoo/Synthesizer | input_data_demux.vhd | 1 | 1,009 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
ENTITY input_data_demux IS
PORT(
ADDR, DATA : in std_logic_vector(7 downto 0);
CLK : in std_logic;
RESET : in std_logic;
NOTE_ON, NOTE_OFF: out std_logic_vector(7 downto 0); --Note ON/OFF 0x80(off), 0xFF(on)
WAV_SELECT : out std_logic_vector(7 downto 0)
);
END input_data_demux;
ARCHITECTURE behav of input_data_demux is
BEGIN
process(CLK,RESET)
variable cooleshit : std_logic;
begin
if reset = '0' then
NOTE_ON <= (others => '0');
NOTE_OFF <= (others => '0');
WAV_SELECT <= (others => '0');
elsif rising_edge(CLK) then
case ADDR is
when X"80" => NOTE_OFF <= DATA;
NOTE_ON <= (others => '0');
when X"FF" => NOTE_ON <= DATA;
NOTE_OFF <= (others => '0');
when X"AA" => WAV_SELECT <= DATA;
when others => NOTE_ON <= (others => '0');
NOTE_OFF <= (others => '0');
end case;
end if;
end process;
END behav; | mit | ea4a7755dadbdb362db6382aa5a303eb | 0.565907 | 2.850282 | false | false | false | false |
Nooxet/embedded_bruteforce | vhdl/pre_process.vhd | 1 | 2,393 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Niklas Aldén
--
-- Create Date: 14:02:44 09/16/2014
-- Design Name:
-- Module Name: pre_process - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity pre_process is
Port ( i_data : in STD_LOGIC_VECTOR (47 downto 0);
i_length : in STD_LOGIC_VECTOR (2 downto 0);
o_data_0 : out unsigned (31 downto 0);
o_data_1 : out unsigned (31 downto 0);
o_length : out STD_LOGIC_VECTOR (7 downto 0)
);
end pre_process;
architecture Behavioral of pre_process is
begin
data_path : process(i_length, i_data)
begin
if i_length = "001" then --1
o_data_0 <= x"000080" & unsigned(i_data(7 downto 0));
o_data_1 <= (others => '0');
o_length <= x"08";
elsif i_length = "010" then --2
o_data_0 <= x"0080" & unsigned(i_data(15 downto 0));
o_data_1 <= (others => '0');
o_length <= x"10";
elsif i_length = "011" then --3
o_data_0 <= x"80" & unsigned(i_data(23 downto 0));
o_data_1 <= (others => '0');
o_length <= x"18";
elsif i_length = "100" then --4
o_data_0 <= unsigned(i_data(31 downto 0));
o_data_1 <= x"00000080";
o_length <= x"20";
elsif i_length = "101" then --5
o_data_0 <= unsigned(i_data(31 downto 0));
o_data_1 <= x"000080" & unsigned(i_data(39 downto 32));
o_length <= x"28";
elsif i_length = "110" then --6
o_data_0 <= unsigned(i_data(31 downto 0));
o_data_1 <= x"0080" & unsigned(i_data(47 downto 32));
o_length <= x"30";
else --0
o_data_0 <= x"00000080";
o_data_1 <= (others => '0');
o_length <= x"00";
end if;
end process;
end Behavioral;
| mit | 63aea4f9f4865babd176ae2ea67a37af | 0.529461 | 3.169536 | false | false | false | false |
esar/hdmilight-v2 | fpga/test_ambilight.vhd | 1 | 5,119 | ----------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Stephen Robinson
--
-- This file is part of HDMI-Light
--
-- HDMI-Light is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- HDMI-Light is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file names COPING).
-- If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY test_ambilight IS
END test_ambilight;
ARCHITECTURE behavior OF test_ambilight IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ambilight
PORT(
vidclk : IN std_logic;
viddata_r : IN std_logic_vector(7 downto 0);
viddata_g : IN std_logic_vector(7 downto 0);
viddata_b : IN std_logic_vector(7 downto 0);
hblank : IN std_logic;
vblank : IN std_logic;
cfgclk : IN std_logic;
cfgwe : IN std_logic;
cfgaddr : IN std_logic_vector(13 downto 0);
cfgdatain : IN std_logic_vector(7 downto 0);
cfgdataout : OUT std_logic_vector(7 downto 0);
output : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal vidclk : std_logic := '0';
signal viddata_r : std_logic_vector(7 downto 0) := (others => '0');
signal viddata_g : std_logic_vector(7 downto 0) := (others => '0');
signal viddata_b : std_logic_vector(7 downto 0) := (others => '0');
signal hblank : std_logic := '0';
signal vblank : std_logic := '0';
signal cfgclk : std_logic := '0';
signal cfgwe : std_logic := '0';
signal cfgaddr : std_logic_vector(13 downto 0) := (others => '0');
signal cfgdatain : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal cfgdataout : std_logic_vector(7 downto 0);
signal output : std_logic_vector(7 downto 0);
-- Clock period definitions
constant vidclk_period : time := 10 ns;
constant cfgclk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ambilight PORT MAP (
vidclk => vidclk,
viddata_r => viddata_r,
viddata_g => viddata_g,
viddata_b => viddata_b,
hblank => hblank,
vblank => vblank,
cfgclk => cfgclk,
cfgwe => cfgwe,
cfgaddr => cfgaddr,
cfgdatain => cfgdatain,
cfgdataout => cfgdataout,
output => output
);
-- Clock process definitions
vidclk_process :process
begin
vidclk <= '0';
wait for vidclk_period/2;
vidclk <= '1';
wait for vidclk_period/2;
end process;
cfgclk_process :process
begin
cfgclk <= '0';
wait for cfgclk_period/2;
cfgclk <= '1';
wait for cfgclk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for vidclk_period*10;
cfgaddr <= "00000000000000";
wait for cfgclk_period*2;
cfgdatain <= x"00";
cfgwe <= '1';
wait for cfgclk_period*2;
cfgaddr <= "00000000000001";
wait for cfgclk_period*2;
cfgdatain <= x"07";
cfgwe <= '1';
wait for cfgclk_period*2;
cfgaddr <= "00000000000010";
wait for cfgclk_period*2;
cfgdatain <= x"00";
cfgwe <= '1';
wait for cfgclk_period*2;
cfgaddr <= "00000000000011";
wait for cfgclk_period*2;
cfgdatain <= x"07";
cfgwe <= '1';
wait for cfgclk_period*2;
cfgaddr <= "00000000000100";
wait for cfgclk_period*2;
cfgdatain <= x"06";
cfgwe <= '1';
wait for cfgclk_period*2;
cfgwe <= '0';
wait for cfgclk_period;
for field in 0 to 10 loop
-- vblank = hBlank = 1
hblank <= '1';
vblank <= '1';
for y in 0 to 20 loop
for x in 0 to 820 loop
viddata_r <= x"00";
viddata_g <= x"00";
viddata_b <= x"00";
wait for vidclk_period;
end loop;
end loop;
for y in 0 to 288 loop
-- vBlank = hBlank = 0
hblank <= '0';
vblank <= '0';
-- line of video, 720 pixels in total
for x in 0 to 720 loop
viddata_r <= x"aa";
viddata_g <= x"00";
viddata_b <= x"00";
wait for vidclk_period;
end loop;
-- hBlank = 1
hblank <= '1';
-- blank data
for x in 0 to 100 loop
viddata_r <= x"00";
viddata_g <= x"00";
viddata_b <= x"00";
wait for vidclk_period;
end loop;
end loop;
end loop;
wait;
end process;
END;
| gpl-2.0 | 2ac6f9b46b2e26f11710a552c69c959d | 0.583903 | 3.599859 | false | false | false | false |
mithro/HDMI2USB | ipcore_dir/edidram/simulation/bmg_tb_pkg.vhd | 6 | 6,006 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_2 Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_tb_pkg.vhd
--
-- Description:
-- BMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END BMG_TB_PKG;
PACKAGE BODY BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END BMG_TB_PKG;
| bsd-2-clause | ecf24c32fb1d4e04a4d49b4655f60b65 | 0.577589 | 4.609363 | false | false | false | false |
RickvanLoo/Synthesizer | spi_read.vhd | 1 | 1,295 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY spi_read IS
PORT (
SCLK : IN std_logic;
CLK : IN std_logic;
RESET : IN std_logic;
SDATA : IN std_logic;
CS : IN std_logic;
dig0, dig1, dig2, dig3 : OUT std_logic_vector(6 DOWNTO 0); -- show key pressed on display dig2 en dig3 (resp high & low).
ADDR, DATA : OUT std_logic_vector(7 downto 0)
);
END spi_read;
ARCHITECTURE behav OF spi_read is
component spi_async IS
PORT ( SCLK : IN std_logic;
RESET : IN std_logic;
SDATA : IN std_logic;
CS : IN std_logic;
BYTE0, BYTE1 : OUT std_logic_vector(7 downto 0);
dig0, dig1, dig2, dig3 : OUT std_logic_vector(6 DOWNTO 0) -- show key pressed on display dig2 en dig3 (resp high & low).
);
END component;
component spi_seperate IS
PORT ( CLK : IN std_logic;
RESET : IN std_logic;
BYTE0, BYTE1 : IN std_logic_vector(7 downto 0);
ADDR, DATA : OUT std_logic_vector(7 downto 0)
);
END component;
signal aBYTE0, aBYTE1 : std_logic_vector(7 downto 0);
BEGIN
G1: spi_async port map(SCLK=>SCLK, RESET=>RESET, SDATA=>SDATA, CS=>CS, BYTE0=>aBYTE0, BYTE1=>aBYTE1, dig0=>dig0, dig1=>dig1, dig2=>dig2, dig3=>dig3);
G2: spi_seperate port map(CLK=>CLK, RESET=>RESET, BYTE0=>aBYTE0, BYTE1=>aBYTE1, ADDR=>ADDR, DATA=>DATA);
END behav; | mit | 7b4e34f68df978732261b86eea45ecce | 0.672587 | 2.67562 | false | false | false | false |
freecores/gpib_controller | vhdl/src/wrapper/ReaderControlReg0.vhd | 1 | 2,514 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: ReaderControlReg0
-- Date:2011-11-10
-- Author: Andrzej Paluch
--
-- Description ${cursor}
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.utilPkg.all;
use work.helperComponents.all;
entity ReaderControlReg0 is
port (
clk : in std_logic;
reset : in std_logic;
strobe : in std_logic;
data_in : in std_logic_vector (15 downto 0);
data_out : out std_logic_vector (15 downto 0);
------------------- gpib -------------------------
-- buffer ready interrupt
buf_interrupt : in std_logic;
-- at least one byte available
data_available : in std_logic;
-- indicates end of stream
end_of_stream : in std_logic;
-- resets buffer
reset_buffer : out std_logic;
-- secondary address of data
dataSecAddr : in std_logic_vector (4 downto 0)
);
end ReaderControlReg0;
architecture arch of ReaderControlReg0 is
signal i_reset_buffer : std_logic;
signal t_in, t_out : std_logic;
begin
data_out(0) <= buf_interrupt;
data_out(1) <= data_available;
data_out(2) <= end_of_stream;
data_out(3) <= i_reset_buffer;
data_out(8 downto 4) <= dataSecAddr;
data_out(15 downto 9) <= "0000000";
reset_buffer <= i_reset_buffer;
process (reset, strobe) begin
if reset = '1' then
t_in <= '0';
elsif rising_edge(strobe) then
if data_in(3) = '1' then
t_in <= not t_out;
end if;
end if;
end process;
spg: SinglePulseGenerator generic map (WIDTH => 3) port map(
reset => reset, clk => clk,
t_in => t_in, t_out => t_out,
pulse => i_reset_buffer
);
end arch;
| gpl-3.0 | d6201160814f0fcaf04ea1bd7d7b791a | 0.614161 | 3.581197 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | lloyds_algorithm_RTL/source/vhdl/lloyds_algorithm_wrapper.vhd | 1 | 5,718 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: lloyds_algorithm_wrapper - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.lloyds_algorithm_pkg.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity lloyds_algorithm_wrapper is
port (
clk : in std_logic;
sclr : in std_logic;
start : in std_logic;
select_input : in std_logic;
-- initial parameters
k : in unsigned(INDEX_BITWIDTH-1 downto 0);
n : in unsigned(NODE_POINTER_BITWIDTH-1 downto 0);
-- init node and centre memory
wr_init_nd : in std_logic;
wr_data_init : in std_logic_vector(D*COORD_BITWIDTH-1 downto 0);
wr_address_init : in std_logic_vector(NODE_POINTER_BITWIDTH-1 downto 0);
-- outputs
valid : out std_logic;
clusters_out : out data_type;
distortion_out : out coord_type_ext;
-- processing done
rdy : out std_logic
);
end lloyds_algorithm_wrapper;
architecture Behavioral of lloyds_algorithm_wrapper is
component lloyds_algorithm_top
port (
clk : in std_logic;
sclr : in std_logic;
start : in std_logic;
-- initial parameters
n : in node_index_type;
k : in centre_index_type;
-- init node and centre memory
wr_init_node : in std_logic;
wr_node_address_init : in node_address_type;
wr_node_data_init : in node_data_type;
wr_init_pos : in std_logic;
wr_centre_list_pos_address_init : in centre_index_type;
wr_centre_list_pos_data_init : in data_type;
-- outputs
valid : out std_logic;
clusters_out : out data_type;
distortion_out : out coord_type_ext;
-- processing done
rdy : out std_logic
);
end component;
signal tmp_clk : std_logic;
signal reg_sclr : std_logic;
signal reg_start : std_logic;
-- initial parameters
signal reg_k : centre_index_type;
signal reg_n : node_index_type;
-- init node and centre memory
signal reg_wr_init_node : std_logic;
signal reg_wr_node_address_init : node_address_type;
signal reg_wr_node_data_init : node_data_type;
signal reg_wr_init_pos : std_logic;
signal reg_wr_centre_list_pos_address_init : centre_index_type;
signal reg_wr_centre_list_pos_data_init : data_type;
-- outputs
signal tmp_valid : std_logic;
signal reg_valid : std_logic;
signal tmp_clusters_out : data_type;
signal reg_clusters_out : data_type;
signal tmp_distortion_out : coord_type_ext;
signal reg_distortion_out : coord_type_ext;
-- processing done
signal tmp_rdy : std_logic ;
signal reg_rdy : std_logic ;
begin
ClkBuffer: IBUFG
port map (
I => clk,
O => tmp_clk
);
input_reg : process(tmp_clk)
begin
if rising_edge(tmp_clk) then
if select_input = '0' then
reg_wr_init_node <= wr_init_nd;
reg_wr_init_pos <= '0';
else
reg_wr_init_node <= '0';
reg_wr_init_pos <= wr_init_nd;
end if;
reg_wr_node_address_init <= wr_address_init(NODE_POINTER_BITWIDTH-1 downto 0);
reg_wr_node_data_init <= stdlogic_2_nodedata(wr_data_init);
reg_wr_centre_list_pos_address_init <= unsigned(wr_address_init(INDEX_BITWIDTH-1 downto 0));
reg_wr_centre_list_pos_data_init <= stdlogic_2_datapoint(wr_data_init(D*COORD_BITWIDTH-1 downto 0));
reg_sclr <= sclr;
reg_start <= start;
reg_k <= k;
reg_n <= n;
end if;
end process input_reg;
lloyds_algorithm_top_inst : lloyds_algorithm_top
port map (
clk => tmp_clk,
sclr => reg_sclr,
start => reg_start,
-- initial parameters
n => reg_n,
k => reg_k,
-- init node and centre memory
wr_init_node => reg_wr_init_node,
wr_node_address_init => reg_wr_node_address_init,
wr_node_data_init => reg_wr_node_data_init,
wr_init_pos => reg_wr_init_pos,
wr_centre_list_pos_address_init => reg_wr_centre_list_pos_address_init,
wr_centre_list_pos_data_init => reg_wr_centre_list_pos_data_init,
-- outputs
valid => tmp_valid,
clusters_out => tmp_clusters_out,
distortion_out => tmp_distortion_out,
-- processing done
rdy => tmp_rdy
);
output_reg : process(tmp_clk)
begin
if rising_edge(tmp_clk) then
reg_valid <= tmp_valid;
reg_clusters_out <= tmp_clusters_out;
reg_distortion_out <= tmp_distortion_out;
reg_rdy <= tmp_rdy;
end if;
end process output_reg;
valid <= reg_valid;
clusters_out <= reg_clusters_out;
distortion_out <= reg_distortion_out;
rdy <= reg_rdy;
end Behavioral;
| bsd-3-clause | 2229fb66d6fd657c9a589942c230fc72 | 0.539699 | 3.929897 | false | false | false | false |
mithro/HDMI2USB | ipcore_dir/edidram/simulation/checker.vhd | 6 | 5,607 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_2 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
| bsd-2-clause | 623cde8b17e5f6a5c8bd3253f49edb67 | 0.589085 | 4.254173 | false | false | false | false |
Nooxet/embedded_bruteforce | brutus_system/ISE/fsl_test/tb_fsl_brutus.vhd | 1 | 3,936 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:57:56 09/29/2014
-- Design Name:
-- Module Name: C:/Users/ael10jso/Xilinx/embedded_bruteforce/brutus_system/ISE/fsl_test/tb_fsl_brutus.vhd
-- Project Name: fsl_test
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: brutus
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_fsl_brutus IS
END tb_fsl_brutus;
ARCHITECTURE behavior OF tb_fsl_brutus IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT brutus
PORT(
FSL_Clk : IN std_logic;
FSL_Rst : IN std_logic;
FSL_S_Clk : IN std_logic;
FSL_S_Read : OUT std_logic;
FSL_S_Data : IN std_logic_vector(0 to 31);
FSL_S_Control : IN std_logic;
FSL_S_Exists : IN std_logic;
FSL_M_Clk : IN std_logic;
FSL_M_Write : OUT std_logic;
FSL_M_Data : OUT std_logic_vector(0 to 31);
FSL_M_Control : OUT std_logic;
FSL_M_Full : IN std_logic
);
END COMPONENT;
--Inputs
signal FSL_Clk : std_logic := '0';
signal FSL_Rst : std_logic := '0';
signal FSL_S_Clk : std_logic := '0';
signal FSL_S_Data : std_logic_vector(0 to 31) := (others => '0');
signal FSL_S_Control : std_logic := '0';
signal FSL_S_Exists : std_logic := '0';
signal FSL_M_Clk : std_logic := '0';
signal FSL_M_Full : std_logic := '0';
--Outputs
signal FSL_S_Read : std_logic;
signal FSL_M_Write : std_logic;
signal FSL_M_Data : std_logic_vector(0 to 31);
signal FSL_M_Control : std_logic;
-- Clock period definitions
constant FSL_Clk_period : time := 10 ns;
constant FSL_S_Clk_period : time := 10 ns;
constant FSL_M_Clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: brutus PORT MAP (
FSL_Clk => FSL_Clk,
FSL_Rst => FSL_Rst,
FSL_S_Clk => FSL_S_Clk,
FSL_S_Read => FSL_S_Read,
FSL_S_Data => FSL_S_Data,
FSL_S_Control => FSL_S_Control,
FSL_S_Exists => FSL_S_Exists,
FSL_M_Clk => FSL_M_Clk,
FSL_M_Write => FSL_M_Write,
FSL_M_Data => FSL_M_Data,
FSL_M_Control => FSL_M_Control,
FSL_M_Full => FSL_M_Full
);
-- Clock process definitions
FSL_Clk_process :process
begin
FSL_Clk <= '0';
wait for FSL_Clk_period/2;
FSL_Clk <= '1';
wait for FSL_Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
FSL_Rst <= '1';
wait for FSL_Clk_period*10;
FSL_Rst <= '0';
FSL_S_Data <= x"12345678";
FSL_S_Exists <= '1';
wait until FSL_S_Read = '1';
wait for FSL_Clk_period;
FSL_S_Data <= x"87654321";
FSL_S_Exists <= '1';
wait until FSL_S_Read = '1';
wait for FSL_Clk_period;
FSL_S_Data <= x"12345678";
FSL_S_Exists <= '1';
wait until FSL_S_Read = '1';
wait for FSL_Clk_period;
FSL_S_Data <= x"87654321";
FSL_S_Exists <= '1';
wait until FSL_S_Read = '1';
wait for FSL_Clk_period;
FSL_S_Exists <= '0';
wait;
end process;
END;
| mit | f20aea6f28089e19dd363f2977a31bdc | 0.574187 | 3.236842 | false | true | false | false |
mithro/HDMI2USB | ipcore_dir/ddr2ram/user_design/sim/memc3_tb_top.vhd | 6 | 29,617 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : memc3_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:56 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is top level module for test bench. which instantiates
-- init_mem_pattern_ctr and mcb_traffic_gen modules for each user
-- port.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc3_tb_top is
generic
(
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_MEM_BURST_LEN : integer := 8;
C_SIMULATION : string := "FALSE";
C_MEM_NUM_COL_BITS : integer := 11;
C_NUM_DQ_PINS : integer := 8;
C_SMALL_DEVICE : string := "FALSE";
C_p2_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
C_p2_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p2_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
C_p2_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
C_p2_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100";
C_p3_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000500";
C_p3_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p3_END_ADDRESS : std_logic_vector(31 downto 0) := X"000006ff";
C_p3_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff800";
C_p3_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000500"
);
port
(
clk0 : in std_logic;
rst0 : in std_logic;
calib_done : in std_logic;
p2_mcb_cmd_en_o : out std_logic;
p2_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p2_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p2_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p2_mcb_cmd_full_i : in std_logic;
p2_mcb_rd_en_o : out std_logic;
p2_mcb_rd_data_i : in std_logic_vector(31 downto 0);
p2_mcb_rd_empty_i : in std_logic;
p2_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
p3_mcb_cmd_en_o : out std_logic;
p3_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p3_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p3_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p3_mcb_cmd_full_i : in std_logic;
p3_mcb_wr_en_o : out std_logic;
p3_mcb_wr_mask_o : out std_logic_vector(3 downto 0);
p3_mcb_wr_data_o : out std_logic_vector(31 downto 0);
p3_mcb_wr_full_i : in std_logic;
p3_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_error : out std_logic;
cmp_data : out std_logic_vector(31 downto 0);
cmp_data_valid : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(127 downto 0)
);
end memc3_tb_top;
architecture arc of memc3_tb_top is
function ERROR_DQWIDTH (val_i : integer) return integer is
begin
if (val_i = 4) then
return 1;
else
return val_i/8;
end if;
end function ERROR_DQWIDTH;
constant DQ_ERROR_WIDTH : integer := ERROR_DQWIDTH(C_NUM_DQ_PINS);
component init_mem_pattern_ctr IS
generic (
FAMILY : string;
BEGIN_ADDRESS : std_logic_vector(31 downto 0);
END_ADDRESS : std_logic_vector(31 downto 0);
DWIDTH : integer;
CMD_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_MODE : std_logic_vector(3 downto 0);
PORT_MODE : string
);
PORT (
clk_i : in std_logic;
rst_i : in std_logic;
mcb_cmd_bl_i : in std_logic_vector(5 downto 0);
mcb_cmd_en_i : in std_logic;
mcb_cmd_instr_i : in std_logic_vector(2 downto 0);
mcb_init_done_i : in std_logic;
mcb_wr_en_i : in std_logic;
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
vio_bl_mode_value : in STD_LOGIC_VECTOR(1 downto 0);
vio_fixed_bl_value : in STD_LOGIC_VECTOR(5 downto 0);
cmp_error : in std_logic;
run_traffic_o : out std_logic;
start_addr_o : out std_logic_vector(31 downto 0);
end_addr_o : out std_logic_vector(31 downto 0);
cmd_seed_o : out std_logic_vector(31 downto 0);
data_seed_o : out std_logic_vector(31 downto 0);
load_seed_o : out std_logic;
addr_mode_o : out std_logic_vector(2 downto 0);
instr_mode_o : out std_logic_vector(3 downto 0);
bl_mode_o : out std_logic_vector(1 downto 0);
data_mode_o : out std_logic_vector(3 downto 0);
mode_load_o : out std_logic;
fixed_bl_o : out std_logic_vector(5 downto 0);
fixed_instr_o : out std_logic_vector(2 downto 0);
fixed_addr_o : out std_logic_vector(31 downto 0)
);
end component;
component mcb_traffic_gen is
generic (
FAMILY : string;
SIMULATION : string;
MEM_BURST_LEN : integer;
PORT_MODE : string;
DATA_PATTERN : string;
CMD_PATTERN : string;
ADDR_WIDTH : integer;
CMP_DATA_PIPE_STAGES : integer;
MEM_COL_WIDTH : integer;
NUM_DQ_PINS : integer;
DQ_ERROR_WIDTH : integer;
DWIDTH : integer;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_EADDR : std_logic_vector(31 downto 0);
PRBS_SADDR : std_logic_vector(31 downto 0)
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
run_traffic_i : in std_logic;
manual_clear_error : in std_logic;
-- *** runtime parameter ***
start_addr_i : in std_logic_vector(31 downto 0);
end_addr_i : in std_logic_vector(31 downto 0);
cmd_seed_i : in std_logic_vector(31 downto 0);
data_seed_i : in std_logic_vector(31 downto 0);
load_seed_i : in std_logic;
addr_mode_i : in std_logic_vector(2 downto 0);
instr_mode_i : in std_logic_vector(3 downto 0);
bl_mode_i : in std_logic_vector(1 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
mode_load_i : in std_logic;
-- fixed pattern inputs interface
fixed_bl_i : in std_logic_vector(5 downto 0);
fixed_instr_i : in std_logic_vector(2 downto 0);
fixed_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0);
bram_cmd_i : in std_logic_vector(38 downto 0);
bram_valid_i : in std_logic;
bram_rdy_o : out std_logic;
--///////////////////////////////////////////////////////////////////////////
-- MCB INTERFACE
-- interface to mcb command port
mcb_cmd_en_o : out std_logic;
mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
mcb_cmd_addr_o : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
mcb_cmd_full_i : in std_logic;
-- interface to mcb wr data port
mcb_wr_en_o : out std_logic;
mcb_wr_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
mcb_wr_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
mcb_wr_data_end_o : OUT std_logic;
mcb_wr_full_i : in std_logic;
mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
-- interface to mcb rd data port
mcb_rd_en_o : out std_logic;
mcb_rd_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
mcb_rd_empty_i : in std_logic;
mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
--///////////////////////////////////////////////////////////////////////////
-- status feedback
counts_rst : in std_logic;
wr_data_counts : out std_logic_vector(47 downto 0);
rd_data_counts : out std_logic_vector(47 downto 0);
cmp_data : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_error : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(64 + (2 * DWIDTH - 1) downto 0);
mem_rd_data : out std_logic_vector(DWIDTH - 1 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end component;
-- Function to determine the number of data patterns to be generated
function DATA_PATTERN_CALC return string is
begin
if (C_SMALL_DEVICE = "FALSE") then
return "DGEN_ALL";
else
return "DGEN_ADDR";
end if;
end function;
constant FAMILY : string := "SPARTAN6";
constant DATA_PATTERN : string := DATA_PATTERN_CALC;
constant CMD_PATTERN : string := "CGEN_ALL";
constant ADDR_WIDTH : integer := 30;
constant CMP_DATA_PIPE_STAGES : integer := 0;
constant PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00007000";
constant PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFF8000";
constant PRBS_SADDR : std_logic_vector(31 downto 0) := X"00005000";
constant PRBS_EADDR : std_logic_vector(31 downto 0) := X"00007fff";
constant BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000";
constant END_ADDRESS : std_logic_vector(31 downto 0) := X"00000fff";
constant DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant p2_DWIDTH : integer := 32;
constant p3_DWIDTH : integer := 32;
constant p2_PORT_MODE : string := "RD_MODE";
constant p3_PORT_MODE : string := "WR_MODE";
signal p0_mcb_cmd_addr_o_int : std_logic_vector(ADDR_WIDTH - 1 DOWNTO 0);
signal p0_mcb_cmd_bl_o_int : std_logic_vector(5 DOWNTO 0);
signal p0_mcb_cmd_en_o_int : std_logic;
signal p0_mcb_cmd_instr_o_int : std_logic_vector(2 DOWNTO 0);
signal p0_mcb_wr_en_o_int : std_logic;
--p2 Signal declarations
signal p2_tg_run_traffic : std_logic;
signal p2_tg_start_addr : std_logic_vector(31 downto 0);
signal p2_tg_end_addr : std_logic_vector(31 downto 0);
signal p2_tg_cmd_seed : std_logic_vector(31 downto 0);
signal p2_tg_data_seed : std_logic_vector(31 downto 0);
signal p2_tg_load_seed : std_logic;
signal p2_tg_addr_mode : std_logic_vector(2 downto 0);
signal p2_tg_instr_mode : std_logic_vector(3 downto 0);
signal p2_tg_bl_mode : std_logic_vector(1 downto 0);
signal p2_tg_data_mode : std_logic_vector(3 downto 0);
signal p2_tg_mode_load : std_logic;
signal p2_tg_fixed_bl : std_logic_vector(5 downto 0);
signal p2_tg_fixed_instr : std_logic_vector(2 downto 0);
signal p2_tg_fixed_addr : std_logic_vector(31 downto 0);
signal p2_error_status : std_logic_vector(64 + (2*p2_DWIDTH - 1) downto 0);
signal p2_error : std_logic;
signal p2_cmp_error : std_logic;
signal p2_cmp_data : std_logic_vector(p2_DWIDTH-1 downto 0);
signal p2_cmp_data_valid : std_logic;
signal p2_mcb_cmd_en_o_int : std_logic;
signal p2_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
signal p2_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
signal p2_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
signal p2_mcb_wr_en_o_int : std_logic;
--p3 Signal declarations
signal p3_tg_run_traffic : std_logic;
signal p3_tg_start_addr : std_logic_vector(31 downto 0);
signal p3_tg_end_addr : std_logic_vector(31 downto 0);
signal p3_tg_cmd_seed : std_logic_vector(31 downto 0);
signal p3_tg_data_seed : std_logic_vector(31 downto 0);
signal p3_tg_load_seed : std_logic;
signal p3_tg_addr_mode : std_logic_vector(2 downto 0);
signal p3_tg_instr_mode : std_logic_vector(3 downto 0);
signal p3_tg_bl_mode : std_logic_vector(1 downto 0);
signal p3_tg_data_mode : std_logic_vector(3 downto 0);
signal p3_tg_mode_load : std_logic;
signal p3_tg_fixed_bl : std_logic_vector(5 downto 0);
signal p3_tg_fixed_instr : std_logic_vector(2 downto 0);
signal p3_tg_fixed_addr : std_logic_vector(31 downto 0);
signal p3_error_status : std_logic_vector(64 + (2*p3_DWIDTH - 1) downto 0);
signal p3_error : std_logic;
signal p3_cmp_error : std_logic;
signal p3_cmp_data : std_logic_vector(p3_DWIDTH-1 downto 0);
signal p3_cmp_data_valid : std_logic;
signal p3_mcb_cmd_en_o_int : std_logic;
signal p3_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
signal p3_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
signal p3_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
signal p3_mcb_wr_en_o_int : std_logic;
signal p2_mcb_wr_en_o : std_logic;
signal p2_mcb_wr_full_i : std_logic;
signal p2_mcb_wr_data_o : std_logic_vector(31 downto 0);
signal p2_mcb_wr_mask_o : std_logic_vector(3 downto 0);
signal p2_mcb_wr_fifo_counts : std_logic_vector(6 downto 0);
signal p3_mcb_rd_en_o : std_logic;
signal p3_mcb_rd_empty_i : std_logic;
signal p3_mcb_rd_fifo_counts : std_logic_vector(6 downto 0);
signal p3_mcb_rd_data_i : std_logic_vector(31 downto 0);
--signal cmp_data : std_logic_vector(31 downto 0);
begin
cmp_error <= p2_cmp_error or p3_cmp_error;
error <= p2_error or p3_error;
error_status <= p2_error_status;
cmp_data <= p2_cmp_data(31 downto 0);
cmp_data_valid <= p2_cmp_data_valid;
p2_mcb_cmd_en_o <= p2_mcb_cmd_en_o_int;
p2_mcb_cmd_instr_o <= p2_mcb_cmd_instr_o_int;
p2_mcb_cmd_bl_o <= p2_mcb_cmd_bl_o_int;
p2_mcb_cmd_addr_o <= p2_mcb_cmd_addr_o_int;
p2_mcb_wr_en_o <= p2_mcb_wr_en_o_int;
init_mem_pattern_ctr_p2 :init_mem_pattern_ctr
generic map
(
DWIDTH => p2_DWIDTH,
FAMILY => FAMILY,
BEGIN_ADDRESS => C_p3_BEGIN_ADDRESS,
END_ADDRESS => C_p3_END_ADDRESS,
CMD_SEED_VALUE => X"56456783",
DATA_SEED_VALUE => X"12345678",
DATA_MODE => C_p3_DATA_MODE,
PORT_MODE => p2_PORT_MODE
)
port map
(
clk_i => clk0,
rst_i => rst0,
mcb_cmd_en_i => p3_mcb_cmd_en_o_int,
mcb_cmd_instr_i => p3_mcb_cmd_instr_o_int,
mcb_cmd_bl_i => p3_mcb_cmd_bl_o_int,
mcb_wr_en_i => p3_mcb_wr_en_o_int,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_bl_mode_value => "10",--vio_bl_mode_value,
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
mcb_init_done_i => calib_done,
cmp_error => p2_error,
run_traffic_o => p2_tg_run_traffic,
start_addr_o => p2_tg_start_addr,
end_addr_o => p2_tg_end_addr ,
cmd_seed_o => p2_tg_cmd_seed ,
data_seed_o => p2_tg_data_seed ,
load_seed_o => p2_tg_load_seed ,
addr_mode_o => p2_tg_addr_mode ,
instr_mode_o => p2_tg_instr_mode ,
bl_mode_o => p2_tg_bl_mode ,
data_mode_o => p2_tg_data_mode ,
mode_load_o => p2_tg_mode_load ,
fixed_bl_o => p2_tg_fixed_bl ,
fixed_instr_o => p2_tg_fixed_instr,
fixed_addr_o => p2_tg_fixed_addr
);
m_traffic_gen_p2 : mcb_traffic_gen
generic map(
MEM_BURST_LEN => C_MEM_BURST_LEN,
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
NUM_DQ_PINS => C_NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
PORT_MODE => p2_PORT_MODE,
DWIDTH => p2_DWIDTH,
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
FAMILY => FAMILY,
SIMULATION => "FALSE",
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => "CGEN_ALL",
ADDR_WIDTH => 30,
PRBS_SADDR_MASK_POS => C_p3_PRBS_SADDR_MASK_POS,
PRBS_EADDR_MASK_POS => C_p3_PRBS_EADDR_MASK_POS,
PRBS_SADDR => C_p3_BEGIN_ADDRESS,
PRBS_EADDR => C_p3_END_ADDRESS
)
port map
(
clk_i => clk0,
rst_i => rst0,
run_traffic_i => p2_tg_run_traffic,
manual_clear_error => rst0,
-- runtime parameter
start_addr_i => p2_tg_start_addr ,
end_addr_i => p2_tg_end_addr ,
cmd_seed_i => p2_tg_cmd_seed ,
data_seed_i => p2_tg_data_seed ,
load_seed_i => p2_tg_load_seed,
addr_mode_i => p2_tg_addr_mode,
instr_mode_i => p2_tg_instr_mode ,
bl_mode_i => p2_tg_bl_mode ,
data_mode_i => p2_tg_data_mode ,
mode_load_i => p2_tg_mode_load ,
-- fixed pattern inputs interface
fixed_bl_i => p2_tg_fixed_bl,
fixed_instr_i => p2_tg_fixed_instr,
fixed_addr_i => p2_tg_fixed_addr,
fixed_data_i => (others => '0'),
-- BRAM interface.
bram_cmd_i => (others => '0'),
bram_valid_i => '0',
bram_rdy_o => open,
-- MCB INTERFACE
mcb_cmd_en_o => p2_mcb_cmd_en_o_int,
mcb_cmd_instr_o => p2_mcb_cmd_instr_o_int,
mcb_cmd_bl_o => p2_mcb_cmd_bl_o_int,
mcb_cmd_addr_o => p2_mcb_cmd_addr_o_int,
mcb_cmd_full_i => p2_mcb_cmd_full_i,
mcb_wr_en_o => p2_mcb_wr_en_o_int,
mcb_wr_mask_o => p2_mcb_wr_mask_o,
mcb_wr_data_o => p2_mcb_wr_data_o,
mcb_wr_data_end_o => open,
mcb_wr_full_i => p2_mcb_wr_full_i,
mcb_wr_fifo_counts => p2_mcb_wr_fifo_counts,
mcb_rd_en_o => p2_mcb_rd_en_o,
mcb_rd_data_i => p2_mcb_rd_data_i,
mcb_rd_empty_i => p2_mcb_rd_empty_i,
mcb_rd_fifo_counts => p2_mcb_rd_fifo_counts,
-- status feedback
counts_rst => rst0,
wr_data_counts => open,
rd_data_counts => open,
cmp_data => p2_cmp_data,
cmp_data_valid => p2_cmp_data_valid,
cmp_error => p2_cmp_error,
error => p2_error,
error_status => p2_error_status,
mem_rd_data => open,
dq_error_bytelane_cmp => open,
cumlative_dq_lane_error => open
);
p3_mcb_cmd_en_o <= p3_mcb_cmd_en_o_int;
p3_mcb_cmd_instr_o <= p3_mcb_cmd_instr_o_int;
p3_mcb_cmd_bl_o <= p3_mcb_cmd_bl_o_int;
p3_mcb_cmd_addr_o <= p3_mcb_cmd_addr_o_int;
p3_mcb_wr_en_o <= p3_mcb_wr_en_o_int;
init_mem_pattern_ctr_p3 :init_mem_pattern_ctr
generic map
(
DWIDTH => p3_DWIDTH,
FAMILY => FAMILY,
BEGIN_ADDRESS => C_p3_BEGIN_ADDRESS,
END_ADDRESS => C_p3_END_ADDRESS,
CMD_SEED_VALUE => X"56456783",
DATA_SEED_VALUE => X"12345678",
DATA_MODE => C_p3_DATA_MODE,
PORT_MODE => p3_PORT_MODE
)
port map
(
clk_i => clk0,
rst_i => rst0,
mcb_cmd_en_i => p3_mcb_cmd_en_o_int,
mcb_cmd_instr_i => p3_mcb_cmd_instr_o_int,
mcb_cmd_bl_i => p3_mcb_cmd_bl_o_int,
mcb_wr_en_i => p3_mcb_wr_en_o_int,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_bl_mode_value => "10",--vio_bl_mode_value,
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
mcb_init_done_i => calib_done,
cmp_error => p3_error,
run_traffic_o => p3_tg_run_traffic,
start_addr_o => p3_tg_start_addr,
end_addr_o => p3_tg_end_addr ,
cmd_seed_o => p3_tg_cmd_seed ,
data_seed_o => p3_tg_data_seed ,
load_seed_o => p3_tg_load_seed ,
addr_mode_o => p3_tg_addr_mode ,
instr_mode_o => p3_tg_instr_mode ,
bl_mode_o => p3_tg_bl_mode ,
data_mode_o => p3_tg_data_mode ,
mode_load_o => p3_tg_mode_load ,
fixed_bl_o => p3_tg_fixed_bl ,
fixed_instr_o => p3_tg_fixed_instr,
fixed_addr_o => p3_tg_fixed_addr
);
m_traffic_gen_p3 : mcb_traffic_gen
generic map(
MEM_BURST_LEN => C_MEM_BURST_LEN,
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
NUM_DQ_PINS => C_NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
PORT_MODE => p3_PORT_MODE,
DWIDTH => p3_DWIDTH,
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
FAMILY => FAMILY,
SIMULATION => "FALSE",
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => "CGEN_ALL",
ADDR_WIDTH => 30,
PRBS_SADDR_MASK_POS => C_p3_PRBS_SADDR_MASK_POS,
PRBS_EADDR_MASK_POS => C_p3_PRBS_EADDR_MASK_POS,
PRBS_SADDR => C_p3_BEGIN_ADDRESS,
PRBS_EADDR => C_p3_END_ADDRESS
)
port map
(
clk_i => clk0,
rst_i => rst0,
run_traffic_i => p3_tg_run_traffic,
manual_clear_error => rst0,
-- runtime parameter
start_addr_i => p3_tg_start_addr ,
end_addr_i => p3_tg_end_addr ,
cmd_seed_i => p3_tg_cmd_seed ,
data_seed_i => p3_tg_data_seed ,
load_seed_i => p3_tg_load_seed,
addr_mode_i => p3_tg_addr_mode,
instr_mode_i => p3_tg_instr_mode ,
bl_mode_i => p3_tg_bl_mode ,
data_mode_i => p3_tg_data_mode ,
mode_load_i => p3_tg_mode_load ,
-- fixed pattern inputs interface
fixed_bl_i => p3_tg_fixed_bl,
fixed_instr_i => p3_tg_fixed_instr,
fixed_addr_i => p3_tg_fixed_addr,
fixed_data_i => (others => '0'),
-- BRAM interface.
bram_cmd_i => (others => '0'),
bram_valid_i => '0',
bram_rdy_o => open,
-- MCB INTERFACE
mcb_cmd_en_o => p3_mcb_cmd_en_o_int,
mcb_cmd_instr_o => p3_mcb_cmd_instr_o_int,
mcb_cmd_bl_o => p3_mcb_cmd_bl_o_int,
mcb_cmd_addr_o => p3_mcb_cmd_addr_o_int,
mcb_cmd_full_i => p3_mcb_cmd_full_i,
mcb_wr_en_o => p3_mcb_wr_en_o_int,
mcb_wr_mask_o => p3_mcb_wr_mask_o,
mcb_wr_data_o => p3_mcb_wr_data_o,
mcb_wr_data_end_o => open,
mcb_wr_full_i => p3_mcb_wr_full_i,
mcb_wr_fifo_counts => p3_mcb_wr_fifo_counts,
mcb_rd_en_o => p3_mcb_rd_en_o,
mcb_rd_data_i => p3_mcb_rd_data_i,
mcb_rd_empty_i => p3_mcb_rd_empty_i,
mcb_rd_fifo_counts => p3_mcb_rd_fifo_counts,
-- status feedback
counts_rst => rst0,
wr_data_counts => open,
rd_data_counts => open,
cmp_data => p3_cmp_data,
cmp_data_valid => p3_cmp_data_valid,
cmp_error => p3_cmp_error,
error => p3_error,
error_status => p3_error_status,
mem_rd_data => open,
dq_error_bytelane_cmp => open,
cumlative_dq_lane_error => open
);
end architecture;
| bsd-2-clause | 6b18fe9325d6ddb4ad2916f31bfa3cce | 0.502077 | 3.283117 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | lloyds_algorithm_HLS/rtl/simulation/testbench.vhd | 1 | 13,209 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- testbench - behavior
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.all;
use ieee.math_real.all;
use STD.textio.all;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
constant MY_N : integer := 128;
constant MY_K : integer := 4;
constant D : integer := 3;
-- bit width defs
constant COORD_BITWIDTH : integer := 16;
constant COORD_BITWIDTH_EXT : integer := 32;
constant INDEX_BITWIDTH : integer := 8;
constant NODE_POINTER_BITWIDTH : integer := 15;
-- input data
file my_input_node : TEXT open READ_MODE is "../../../simulation/data_points_N128_K4_D3_s0.75.mat";
file my_input_cntr : TEXT open READ_MODE is "../../../simulation/initial_centres_N128_K4_D3_s0.75_1.mat";
--file my_input_node : TEXT open READ_MODE is "../../../simulation/data_points_N16384_K128_D3_s0.20.mat";
--file my_input_cntr : TEXT open READ_MODE is "../../../simulation/initial_centres_N16384_K128_D3_s0.20_1.mat";
-- Clock period definitions
constant CLK_PERIOD : time := 10 ns;
constant RESET_CYCLES : integer := 20;
constant INIT_CYCLES : integer := MY_N;
type state_type is (readfile, reset, start_processing, processing, processing_done);
type file_node_data_array_type is array(0 to D-1, 0 to MY_N-1) of integer;
type file_cntr_data_array_type is array(0 to D-1, 0 to MY_K-1) of integer;
subtype coord_type is std_logic_vector(COORD_BITWIDTH-1 downto 0);
type data_type is array(0 to D-1) of coord_type;
subtype coord_type_ext is std_logic_vector(COORD_BITWIDTH_EXT-1 downto 0);
type data_type_ext is array(0 to D-1) of coord_type_ext;
function stdlogic_2_datapoint(c : std_logic_vector) return data_type is
variable result : data_type;
begin
for I in 0 to D-1 loop
result(I) := c((I+1)*COORD_BITWIDTH-1 downto I*COORD_BITWIDTH);
end loop;
return result;
end stdlogic_2_datapoint;
function datapoint_2_stdlogic(c : data_type) return std_logic_vector is
variable result : std_logic_vector(D*COORD_BITWIDTH-1 downto 0);
begin
for I in 0 to D-1 loop
result((I+1)*COORD_BITWIDTH-1 downto I*COORD_BITWIDTH) := std_logic_vector(c(I));
end loop;
return result;
end datapoint_2_stdlogic;
-- Component Declaration for the Unit Under Test (UUT)
component lloyds_algorithm_top is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
data_value_V_dout : IN STD_LOGIC_VECTOR (D*COORD_BITWIDTH-1 downto 0);
data_value_V_empty_n : IN STD_LOGIC;
data_value_V_read : OUT STD_LOGIC;
cntr_pos_init_value_V_dout : IN STD_LOGIC_VECTOR (D*COORD_BITWIDTH-1 downto 0);
cntr_pos_init_value_V_empty_n : IN STD_LOGIC;
cntr_pos_init_value_V_read : OUT STD_LOGIC;
n_V : IN STD_LOGIC_VECTOR (NODE_POINTER_BITWIDTH-1 downto 0);
k_V : IN STD_LOGIC_VECTOR (INDEX_BITWIDTH-1 downto 0);
distortion_out_V_din : OUT STD_LOGIC_VECTOR (COORD_BITWIDTH_EXT-1 downto 0);
distortion_out_V_full_n : IN STD_LOGIC;
distortion_out_V_write : OUT STD_LOGIC;
clusters_out_value_V_din : OUT STD_LOGIC_VECTOR (D*COORD_BITWIDTH-1 downto 0);
clusters_out_value_V_full_n : IN STD_LOGIC;
clusters_out_value_V_write : OUT STD_LOGIC
);
end component;
--Inputs
signal ap_clk : std_logic;
signal ap_rst : std_logic := '1';
signal ap_start : std_logic := '0';
signal data_value_V_dout : std_logic_vector (D*COORD_BITWIDTH-1 downto 0);
signal node_type_data_value_V_dout : data_type;
signal data_value_V_empty_n : std_logic := '1';
signal cntr_pos_init_value_V_dout : std_logic_vector (D*COORD_BITWIDTH-1 downto 0);
signal data_type_cntr_pos_init_value_V_dout : data_type;
signal cntr_pos_init_value_V_empty_n : std_logic := '1';
signal n_V : std_logic_vector (NODE_POINTER_BITWIDTH-1 downto 0);
signal k_V : std_logic_vector (INDEX_BITWIDTH-1 downto 0);
signal root_V : std_logic_vector (NODE_POINTER_BITWIDTH-1 downto 0);
signal distortion_out_V_full_n : std_logic := '1';
signal clusters_out_value_V_full_n : std_logic := '1';
-- Outputs
signal ap_done : std_logic;
signal ap_idle : std_logic;
signal data_value_V_read : std_logic;
signal cntr_pos_init_value_V_read : std_logic;
signal distortion_out_V_din : std_logic_vector (COORD_BITWIDTH_EXT-1 downto 0);
signal distortion_out_V_write : std_logic;
signal clusters_out_value_V_din : std_logic_vector (D*COORD_BITWIDTH-1 downto 0);
signal data_type_clusters_out_value_V_din : data_type;
signal clusters_out_value_V_write : std_logic;
-- file io
signal file_node_data_array : file_node_data_array_type;
signal file_cntr_data_array : file_cntr_data_array_type;
signal read_file_done : std_logic := '0';
-- Operation
signal state : state_type := readfile;
signal reset_counter : integer := 0;
signal init_node_counter : integer := 0;
signal init_cntr_counter : integer := 0;
signal cycle_counter : integer := 0;
signal reset_counter_done : std_logic := '0';
signal init_counter_done : std_logic := '0';
BEGIN
-- PARALLEL_UNITS == 1 always in testbench!!!
-- Instantiate the Unit Under Test (UUT)
uut : lloyds_algorithm_top
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => ap_start,
ap_done => ap_done,
ap_idle => ap_idle,
data_value_V_dout => data_value_V_dout,
data_value_V_empty_n => data_value_V_empty_n,
data_value_V_read => data_value_V_read,
cntr_pos_init_value_V_dout => cntr_pos_init_value_V_dout,
cntr_pos_init_value_V_empty_n => cntr_pos_init_value_V_empty_n,
cntr_pos_init_value_V_read => cntr_pos_init_value_V_read,
n_V => n_V,
k_V => k_V,
distortion_out_V_din => distortion_out_V_din,
distortion_out_V_full_n => distortion_out_V_full_n,
distortion_out_V_write => distortion_out_V_write,
clusters_out_value_V_din => clusters_out_value_V_din,
clusters_out_value_V_full_n => clusters_out_value_V_full_n,
clusters_out_value_V_write => clusters_out_value_V_write
);
data_type_clusters_out_value_V_din <= stdlogic_2_datapoint(clusters_out_value_V_din);
-- Clock process definitions
clk_process : process
begin
ap_clk <= '1';
wait for CLK_PERIOD/2;
ap_clk <= '0';
wait for CLK_PERIOD/2;
end process;
fsm_proc : process(ap_clk)
begin
if rising_edge(ap_clk) then
if state = readfile AND read_file_done = '1' then
state <= reset;
elsif state = reset AND reset_counter_done = '1' then
state <= start_processing;
elsif state = start_processing then
state <= processing;
elsif state = processing AND ap_done = '1' then
state <= processing_done;
end if;
end if;
end process fsm_proc;
ap_start <= '1' WHEN state = start_processing ELSE '0';
counter_proc : process(ap_clk)
begin
if rising_edge(ap_clk) then
if state = reset then
reset_counter <= reset_counter+1;
end if;
if data_value_V_read = '1' then
init_node_counter <= init_node_counter+1;
end if;
if cntr_pos_init_value_V_read = '1' then
init_cntr_counter <= init_cntr_counter+1;
end if;
if state = processing then
cycle_counter <= cycle_counter+1;
end if;
end if;
end process counter_proc;
reset_counter_done <= '1' WHEN reset_counter = RESET_CYCLES-1 ELSE '0';
reset_proc : process(state)
begin
if state = reset then
ap_rst <= '1';
else
ap_rst <= '0';
end if;
end process reset_proc;
n_V <= std_logic_vector(to_unsigned(MY_N-1,NODE_POINTER_BITWIDTH));
k_V <= std_logic_vector(to_unsigned(MY_K-1,INDEX_BITWIDTH));
init_proc : process(state, init_node_counter, init_cntr_counter)
variable centre_pos : data_type;
variable node : data_type;
begin
-- tree_node_memory
if init_node_counter < MY_N then
for I in 0 to D-1 loop
node(I) := std_logic_vector(to_signed(file_node_data_array(I,init_node_counter),COORD_BITWIDTH));
end loop;
data_value_V_dout <= datapoint_2_stdlogic(node);
node_type_data_value_V_dout <= node;
end if;
if init_cntr_counter < My_K then
for I in 0 to D-1 loop
centre_pos(I) := std_logic_vector(to_signed(file_cntr_data_array(I,init_cntr_counter),COORD_BITWIDTH));
end loop;
cntr_pos_init_value_V_dout <= datapoint_2_stdlogic(centre_pos);
data_type_cntr_pos_init_value_V_dout <= centre_pos;
end if;
end process init_proc;
-- read tree data and initial centres from file
read_file : process
variable my_line : LINE;
variable my_input_line : LINE;
variable tmp_line_counter_node : integer;
variable tmp_file_line_counter_node : integer;
variable tmp_line_counter_cntr : integer;
variable tmp_file_line_counter_cntr : integer;
variable tmp_d : integer;
variable tmp_file_data_node : file_node_data_array_type;
variable tmp_file_data_cntr : file_cntr_data_array_type;
begin
write(my_line, string'("reading input files"));
writeline(output, my_line);
tmp_line_counter_node := 0;
tmp_file_line_counter_node := 0;
tmp_d := 0;
loop
exit when endfile(my_input_node) OR tmp_line_counter_node = D*MY_N;
readline(my_input_node, my_input_line);
read(my_input_line,tmp_file_data_node(tmp_d,tmp_file_line_counter_node));
-- if tmp_line_counter_node < MY_N then
-- read(my_input_line,tmp_file_data_node(0,tmp_line_counter_node));
-- else
-- read(my_input_line,tmp_file_data_node(1,tmp_line_counter_node-MY_N));
-- end if;
tmp_line_counter_node := tmp_line_counter_node+1;
tmp_file_line_counter_node := tmp_file_line_counter_node+1;
if tmp_file_line_counter_node = MY_N then
tmp_d := tmp_d +1;
tmp_file_line_counter_node := 0;
end if;
end loop;
file_node_data_array <= tmp_file_data_node;
write(my_line, string'("Number of lines:"));
writeline(output, my_line);
write(my_line, tmp_line_counter_node);
writeline(output, my_line);
-- reading centres now
tmp_line_counter_cntr := 0;
tmp_file_line_counter_cntr := 0;
tmp_d := 0;
loop
exit when endfile(my_input_cntr) OR tmp_line_counter_cntr = D*MY_K;
readline(my_input_cntr, my_input_line);
read(my_input_line,tmp_file_data_cntr(tmp_d,tmp_file_line_counter_cntr));
-- if tmp_line_counter_cntr < MY_K then
-- read(my_input_line,tmp_file_data_cntr(0,tmp_line_counter_cntr));
-- else
-- read(my_input_line,tmp_file_data_cntr(1,tmp_line_counter_cntr-MY_K));
-- end if;
tmp_line_counter_cntr := tmp_line_counter_cntr+1;
tmp_file_line_counter_cntr := tmp_file_line_counter_cntr+1;
if tmp_file_line_counter_cntr = MY_K then
tmp_d := tmp_d +1;
tmp_file_line_counter_cntr := 0;
end if;
end loop;
file_cntr_data_array <= tmp_file_data_cntr;
write(my_line, string'("Number of lines:"));
writeline(output, my_line);
write(my_line, tmp_line_counter_cntr);
writeline(output, my_line);
read_file_done <= '1';
wait; -- one shot at time zero,
end process read_file;
END;
| bsd-3-clause | 632a27009cae5a7ab178b8cabd57f9cc | 0.562041 | 3.513966 | false | false | false | false |
mithro/HDMI2USB | ipcore_dir/rgbfifo.vhd | 3 | 10,341 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file rgbfifo.vhd when simulating
-- the core, rgbfifo. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY rgbfifo IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END rgbfifo;
ARCHITECTURE rgbfifo_a OF rgbfifo IS
-- synthesis translate_off
COMPONENT wrapped_rgbfifo
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_rgbfifo USE ENTITY XilinxCoreLib.fifo_generator_v9_2(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 1,
c_count_type => 0,
c_data_count_width => 12,
c_default_value => "BlankString",
c_din_width => 8,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 8,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 0,
c_has_almost_empty => 1,
c_has_almost_full => 1,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 1,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 0,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "2kx9",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 2047,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 2046,
c_prog_full_type => 0,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 12,
c_rd_depth => 2048,
c_rd_freq => 1,
c_rd_pntr_width => 11,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 1,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 12,
c_wr_depth => 2048,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 11,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_rgbfifo
PORT MAP (
clk => clk,
rst => rst,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
almost_full => almost_full,
empty => empty,
almost_empty => almost_empty,
valid => valid
);
-- synthesis translate_on
END rgbfifo_a;
| bsd-2-clause | f79aa5f6a8741f5975e0627b1685b280 | 0.537956 | 3.364021 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | lloyds_algorithm_RTL/source/vhdl/dsp_round.vhd | 1 | 5,498 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: dsp_round - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity dsp_round is
generic (
BITWIDTH_IN : integer := 32;
BITWIDTH_OUT : integer := 32
);
port (
sclr : in std_logic;
nd : in std_logic;
AB_IN : in std_logic_vector (BITWIDTH_IN-1 downto 0);
CARRYIN_IN : in std_logic;
CLK_IN : in std_logic;
C_IN : in std_logic_vector (BITWIDTH_IN-1 downto 0);
P_OUT : out std_logic_vector (BITWIDTH_OUT-1 downto 0);
rdy : out std_logic
);
end dsp_round;
architecture BEHAVIORAL of dsp_round is
constant LAT : integer := 2;
signal GND_ALUMODE : std_logic;
signal GND_BUS_3 : std_logic_vector (2 downto 0);
signal GND_BUS_18 : std_logic_vector (17 downto 0);
signal GND_BUS_30 : std_logic_vector (29 downto 0);
signal GND_BUS_48 : std_logic_vector (47 downto 0);
signal GND_OPMODE : std_logic;
signal VCC_OPMODE : std_logic;
signal ab_in_ext : std_logic_vector(47 downto 0);
signal c_in_ext : std_logic_vector(47 downto 0);
signal p_out_ext : std_logic_vector(47 downto 0);
signal delay_line : std_logic_vector(0 to LAT-1);
begin
GND_ALUMODE <= '0';
GND_BUS_3(2 downto 0) <= "000";
GND_BUS_18(17 downto 0) <= "000000000000000000";
GND_BUS_30(29 downto 0) <= "000000000000000000000000000000";
GND_BUS_48(47 downto 0) <=
"000000000000000000000000000000000000000000000000";
GND_OPMODE <= '0';
VCC_OPMODE <= '1';
ab_in_ext(47 downto BITWIDTH_IN) <= (others => AB_IN(BITWIDTH_IN-1));
ab_in_ext(BITWIDTH_IN-1 downto 0) <= AB_IN;
c_in_ext(47 downto BITWIDTH_IN) <= (others => C_IN(BITWIDTH_IN-1));
c_in_ext(BITWIDTH_IN-1 downto 0) <= C_IN;
DSP48E_INST : DSP48E
generic map( ACASCREG => 1,
ALUMODEREG => 0,
AREG => 1,
AUTORESET_PATTERN_DETECT => FALSE,
AUTORESET_PATTERN_DETECT_OPTINV => "MATCH",
A_INPUT => "DIRECT",
BCASCREG => 1,
BREG => 1,
B_INPUT => "DIRECT",
CARRYINREG => 1,
CARRYINSELREG => 0,
CREG => 1,
MASK => x"3FFFFFFFFFFF",
MREG => 1,
MULTCARRYINREG => 1,
OPMODEREG => 0,
PATTERN => x"000000000000",
PREG => 1,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
SEL_ROUNDING_MASK => "SEL_MASK",
USE_MULT => "NONE",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48")
port map (A(29 downto 0)=>ab_in_ext(47 downto 18),
ACIN(29 downto 0)=>GND_BUS_30(29 downto 0),
ALUMODE(3)=>GND_ALUMODE,
ALUMODE(2)=>GND_ALUMODE,
ALUMODE(1)=>GND_ALUMODE,
ALUMODE(0)=>GND_ALUMODE,
B(17 downto 0)=>ab_in_ext(17 downto 0),
BCIN(17 downto 0)=>GND_BUS_18(17 downto 0),
C(47 downto 0)=>c_in_ext(47 downto 0),
CARRYCASCIN=>GND_ALUMODE,
CARRYIN=>CARRYIN_IN,
CARRYINSEL(2 downto 0)=>GND_BUS_3(2 downto 0),
CEALUMODE=>VCC_OPMODE,
CEA1=>VCC_OPMODE,
CEA2=>VCC_OPMODE,
CEB1=>VCC_OPMODE,
CEB2=>VCC_OPMODE,
CEC=>VCC_OPMODE,
CECARRYIN=>VCC_OPMODE,
CECTRL=>VCC_OPMODE,
CEM=>VCC_OPMODE,
CEMULTCARRYIN=>VCC_OPMODE,
CEP=>VCC_OPMODE,
CLK=>CLK_IN,
MULTSIGNIN=>GND_ALUMODE,
OPMODE(6)=>GND_OPMODE,
OPMODE(5)=>VCC_OPMODE,
OPMODE(4)=>VCC_OPMODE,
OPMODE(3)=>GND_OPMODE,
OPMODE(2)=>GND_OPMODE,
OPMODE(1)=>VCC_OPMODE,
OPMODE(0)=>VCC_OPMODE,
PCIN(47 downto 0)=>GND_BUS_48(47 downto 0),
RSTA=>GND_ALUMODE,
RSTALLCARRYIN=>GND_ALUMODE,
RSTALUMODE=>GND_ALUMODE,
RSTB=>GND_ALUMODE,
RSTC=>GND_ALUMODE,
RSTCTRL=>GND_ALUMODE,
RSTM=>GND_ALUMODE,
RSTP=>GND_ALUMODE,
ACOUT=>open,
BCOUT=>open,
CARRYCASCOUT=>open,
CARRYOUT=>open,
MULTSIGNOUT=>open,
OVERFLOW=>open,
P(47 downto 0)=>p_out_ext(47 downto 0),
PATTERNBDETECT=>open,
PATTERNDETECT=>open,
PCOUT=>open,
UNDERFLOW=>open);
P_OUT <= p_out_ext(BITWIDTH_IN-1 downto BITWIDTH_IN-BITWIDTH_OUT);
delay_line_proc : process(CLK_IN)
begin
if rising_edge(CLK_IN) then
if sclr = '1' then
delay_line <= (others => '0');
else
delay_line(0) <= nd;
delay_line(1 to LAT-1) <= delay_line(0 to LAT-2);
end if;
end if;
end process delay_line_proc;
rdy <= delay_line(LAT-1);
end BEHAVIORAL;
| bsd-3-clause | f1f2606a4a5506070156a37de7828156 | 0.497817 | 3.913167 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | filtering_algorithm_RTL/source/vhdl/stack_top.vhd | 1 | 4,201 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: stack_top - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.filtering_algorithm_pkg.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity stack_top is
port (
clk : in STD_LOGIC;
sclr : in STD_LOGIC;
push : in std_logic;
pop : in std_logic;
node_addr_in_1 : in node_address_type;
node_addr_in_2 : in node_address_type;
cntr_addr_in_1 : in centre_list_address_type;
cntr_addr_in_2 : in centre_list_address_type;
k_in_1 : in centre_index_type;
k_in_2 : in centre_index_type;
node_addr_out : out node_address_type;
cntr_addr_out : out centre_list_address_type;
k_out : out centre_index_type;
empty : out std_logic;
valid : out std_logic
);
end stack_top;
architecture Behavioral of stack_top is
type state_type is (one, two);
component node_stack_mgmt
port (
clk : in STD_LOGIC;
sclr : in STD_LOGIC;
push : in std_logic;
pop : in std_logic;
node_addr_in : in node_address_type;
node_addr_out : out node_address_type;
empty : out std_logic;
valid : out std_logic
);
end component;
component centre_stack_mgmt
port (
clk : in STD_LOGIC;
sclr : in STD_LOGIC;
push : in std_logic;
pop : in std_logic;
cntr_addr_in : in centre_list_address_type;
k_in : in centre_index_type;
cntr_addr_out : out centre_list_address_type;
k_out : out centre_index_type;
empty : out std_logic;
valid : out std_logic
);
end component;
signal state : state_type;
signal tmp_push : std_logic;
signal node_addr_reg : node_address_type;
signal cntr_addr_reg : centre_list_address_type;
signal k_reg : centre_index_type;
signal tmp_cntr_addr_in : centre_list_address_type;
signal tmp_k_in : centre_index_type;
signal tmp_node_addr_in : node_address_type;
begin
fsm_proc : process(clk)
begin
if rising_edge(clk) then
if sclr ='1' then
state <= one;
elsif state = one AND push = '1' then
state <= two;
elsif state = two then
state <= one;
end if;
end if;
end process fsm_proc;
input_reg_proc : process(clk)
begin
if rising_edge(clk) then
node_addr_reg <= node_addr_in_2;
cntr_addr_reg <= cntr_addr_in_2;
k_reg <= k_in_2;
end if;
end process input_reg_proc;
tmp_node_addr_in <= node_addr_in_1 WHEN state = one ELSE node_addr_reg;
tmp_cntr_addr_in <= cntr_addr_in_1 WHEN state = one ELSE cntr_addr_reg;
tmp_k_in <= k_in_1 WHEN state = one ELSE k_reg;
tmp_push <= '1' WHEN push = '1' OR state = two ELSE '0';
node_stack_mgmt_inst : node_stack_mgmt
port map (
clk => clk,
sclr => sclr,
push => tmp_push,
pop => pop,
node_addr_in => tmp_node_addr_in,
node_addr_out => node_addr_out,
empty => empty,
valid => valid
);
centre_stack_mgmt_inst : centre_stack_mgmt
port map (
clk => clk,
sclr => sclr,
push => tmp_push,
pop => pop,
cntr_addr_in => tmp_cntr_addr_in,
k_in => tmp_k_in,
cntr_addr_out => cntr_addr_out,
k_out => k_out,
empty => open,
valid => open
);
end Behavioral;
| bsd-3-clause | 8c3330e0749ea599258f747d17f34750 | 0.516306 | 3.788097 | false | false | false | false |
tomoasleep/vhdl_test_script | examples/alu_generic.vhd | 1 | 1,077 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity alu is
generic(hoge : std_logic := '1');
port (
a, b : in std_logic_vector(31 downto 0);
control : in std_logic_vector(2 downto 0);
output : out std_logic_vector(31 downto 0);
fuga : out std_logic;
zero : out std_logic);
end alu;
architecture behave of alu is
signal bb : std_logic_vector(31 downto 0);
signal c : std_logic;
signal o0, o1, o2, o3 : std_logic_vector(31 downto 0);
signal out_buf : std_logic_vector(31 downto 0);
begin -- behave
c <= control(2);
bb <= not b when control(2) = '1' else b;
o0 <= a and bb;
o1 <= a or b;
o2 <= a + bb + c;
o3 <= x"0000000" & "000" & o2(31);
fuga <= hoge;
out_buf <= o0 when control(1 downto 0) = "00" else
o1 when control(1 downto 0) = "01" else
o2 when control(1 downto 0) = "10" else
o3 when control(1 downto 0) = "11";
output <= out_buf;
zero <= '1' when out_buf = x"00000000" else '0';
end behave;
| mit | abc6ef55b054ce217fbf08a8318ff383 | 0.589601 | 2.856764 | false | false | false | false |
freecores/gpib_controller | vhdl/src/wrapper/RegsGpibFasade.vhd | 1 | 18,325 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: RegsGpibFasade
-- Date:2011-11-17
-- Author: Andrzej Paluch
--
-- Description ${cursor}
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.gpibComponents.all;
use work.helperComponents.all;
use work.wrapperComponents.all;
entity RegsGpibFasade is
port (
reset : std_logic;
clk : in std_logic;
-----------------------------------------------------------------------
------------ GPIB interface signals -----------------------------------
-----------------------------------------------------------------------
DI : in std_logic_vector (7 downto 0);
DO : out std_logic_vector (7 downto 0);
output_valid : out std_logic;
-- attention
ATN_in : in std_logic;
ATN_out : out std_logic;
-- data valid
DAV_in : in std_logic;
DAV_out : out std_logic;
-- not ready for data
NRFD_in : in std_logic;
NRFD_out : out std_logic;
-- no data accepted
NDAC_in : in std_logic;
NDAC_out : out std_logic;
-- end or identify
EOI_in : in std_logic;
EOI_out : out std_logic;
-- service request
SRQ_in : in std_logic;
SRQ_out : out std_logic;
-- interface clear
IFC_in : in std_logic;
IFC_out : out std_logic;
-- remote enable
REN_in : in std_logic;
REN_out : out std_logic;
-----------------------------------------------------------------------
---------------- registers access -------------------------------------
-----------------------------------------------------------------------
data_in : in std_logic_vector(15 downto 0);
data_out : out std_logic_vector(15 downto 0);
reg_addr : in std_logic_vector(14 downto 0);
strobe_read : in std_logic;
strobe_write : in std_logic;
-----------------------------------------------------------------------
---------------- additional lines -------------------------------------
-----------------------------------------------------------------------
interrupt_line : out std_logic
;debug1 : out std_logic
;debug2 : out std_logic
);
end RegsGpibFasade;
architecture arch of RegsGpibFasade is
constant MEM_NATIVE_DATA_WIDTH : integer := 16;
-- gpib
signal g_isLE, g_isTE : std_logic;
signal g_lpeUsed : std_logic;
signal g_fixedPpLine : std_logic_vector (2 downto 0);
signal g_eosUsed : std_logic;
signal g_eosMark : std_logic_vector (7 downto 0);
signal g_myListAddr, g_myTalkAddr : std_logic_vector (4 downto 0);
signal g_secAddrMask : std_logic_vector (31 downto 0);
signal g_data : std_logic_vector (7 downto 0);
signal g_status_byte : std_logic_vector (7 downto 0);
signal g_T1 : std_logic_vector (7 downto 0);
signal g_rdy, g_nba, g_ltn, g_lun, g_lon, g_ton, g_endOf, g_gts, g_rpp,
g_tcs, g_tca, g_sic, g_rsc, g_sre, g_rtl, g_rsv, g_ist, g_lpe, g_dvd,
g_wnc, g_tac, g_lac, g_cwrc, g_cwrd, g_clr, g_trg, g_atl, g_att, g_mla,
g_lsb, g_spa, g_ppr, g_sreq, g_isLocal : std_logic;
signal g_currentSecAddr : std_logic_vector (4 downto 0);
signal g_output_valid : std_logic;
signal g_ATN_out : std_logic;
-- reader
signal r_isLE : std_logic;
signal r_dataSecAddr : std_logic_vector (4 downto 0);
signal r_buf_interrupt : std_logic;
signal r_data_available : std_logic;
signal r_end_of_stream : std_logic;
signal r_reset_buffer : std_logic;
signal r_strobe : std_logic;
signal r_fifo_full : std_logic;
signal r_fifo_ready_to_write : std_logic;
signal r_at_least_one_byte_in_fifo : std_logic;
-- writer
signal w_isTE : std_logic;
signal w_dataSecAddr : std_logic_vector (4 downto 0);
signal w_end_of_stream : std_logic;
signal w_data_available : std_logic;
signal w_buf_interrupt : std_logic;
signal w_reset_buffer : std_logic;
-- serial poll coordinator
signal s_rec_stb : std_logic;
signal s_stb_received : std_logic;
-- reader fifo
signal rm_reset : std_logic;
signal rm_byte_in : std_logic_vector(7 downto 0);
signal rm_byte_out : std_logic_vector(15 downto 0);
-------------- fifo --------------------
signal rm_availableBytesCount : std_logic_vector(10 downto 0);
signal rm_strobe_read : std_logic;
-- writer fifo
signal wm_reset : std_logic;
signal wm_write_strobe : std_logic;
signal wm_data_in : std_logic_vector(15 downto 0);
signal wm_byte_in : std_logic_vector(7 downto 0);
signal wm_ready_to_read : std_logic;
signal wm_bytesAvailable : std_logic;
signal wm_availableBytesCount : std_logic_vector(10 downto 0);
signal wm_bufferFull : std_logic;
signal wm_ready_to_write : std_logic;
signal wm_strobe_read : std_logic;
-- settings reg
signal set0_strobe : std_logic;
signal set0_data_in, set0_data_out :
std_logic_vector((MEM_NATIVE_DATA_WIDTH-1) downto 0);
signal set1_strobe : std_logic;
signal set1_data_in, set1_data_out :
std_logic_vector((MEM_NATIVE_DATA_WIDTH-1) downto 0);
signal set0_isLE_TE : std_logic;
signal set1_myAddr : std_logic_vector(4 downto 0);
-- sec addr mask reg
signal sec0_strobe : std_logic;
signal sec0_data_in, sec0_data_out :
std_logic_vector((MEM_NATIVE_DATA_WIDTH-1) downto 0);
signal sec0_secAddrMask :
std_logic_vector ((MEM_NATIVE_DATA_WIDTH-1) downto 0);
signal sec1_strobe : std_logic;
signal sec1_data_in, sec1_data_out :
std_logic_vector((MEM_NATIVE_DATA_WIDTH-1) downto 0);
signal sec1_secAddrMask :
std_logic_vector ((MEM_NATIVE_DATA_WIDTH-1) downto 0);
-- gpib bus reg
signal gbs_data_out : std_logic_vector ((MEM_NATIVE_DATA_WIDTH-1) downto 0);
-- event reg
signal ev_strobe : std_logic;
signal ev_data_in, ev_data_out :
std_logic_vector((MEM_NATIVE_DATA_WIDTH-1) downto 0);
-- gpib status
signal gs_data_out : std_logic_vector ((MEM_NATIVE_DATA_WIDTH-1) downto 0);
-- gpib control reg
signal gc_strobe : std_logic;
signal gc_data_in, gc_data_out :
std_logic_vector((MEM_NATIVE_DATA_WIDTH-1) downto 0);
-- reader control reg
signal rc0_strobe : std_logic;
signal rc0_data_in, rc0_data_out :
std_logic_vector((MEM_NATIVE_DATA_WIDTH-1) downto 0);
signal rc1_data_out :
std_logic_vector((MEM_NATIVE_DATA_WIDTH-1) downto 0);
-- writer control reg
signal wc0_strobe : std_logic;
signal wc0_data_in, wc0_data_out :
std_logic_vector((MEM_NATIVE_DATA_WIDTH-1) downto 0);
signal wc0_status_byte : std_logic_vector (6 downto 0);
signal wc1_strobe : std_logic;
signal wc1_data_in, wc1_data_out :
std_logic_vector((MEM_NATIVE_DATA_WIDTH-1) downto 0);
begin
debug1 <= g_nba;
debug2 <= g_wnc;
-- settings reg
g_isLE <= set0_isLE_TE;
g_isTE <= set0_isLE_TE;
r_isLE <= set0_isLE_TE;
w_isTE <= set0_isLE_TE;
g_myListAddr <= set1_myAddr;
g_myTalkAddr <= set1_myAddr;
-- sec addr reg
g_secAddrMask (15 downto 0) <= sec0_secAddrMask;
g_secAddrMask (31 downto 16) <= sec1_secAddrMask;
g_status_byte(7) <= wc0_status_byte(6);
g_status_byte(6) <= '0';
g_status_byte(5 downto 0) <= wc0_status_byte(5 downto 0);
-- writer fifo
wm_reset <= w_reset_buffer;
-- reader fifo
rm_reset <= r_reset_buffer;
gpib: gpibInterface port map (
clk => clk, reset => reset,
-- application interface
isLE => g_isLE, isTE => g_isTE, lpeUsed => g_lpeUsed,
fixedPpLine => g_fixedPpLine, eosUsed => g_eosUsed,
eosMark => g_eosMark, myListAddr => g_myListAddr,
myTalkAddr => g_myTalkAddr, secAddrMask => g_secAddrMask,
data => g_data, status_byte => g_status_byte, T1 => g_T1,
rdy => g_rdy, nba => g_nba, ltn => g_ltn, lun => g_lun, lon => g_lon,
ton => g_ton, endOf => g_endOf, gts => g_gts, rpp => g_rpp,
tcs => g_tcs, tca => g_tca, sic => g_sic, rsc => g_rsc, sre => g_sre,
rtl => g_rtl, rsv => g_rsv, ist => g_ist, lpe => g_lpe,
dvd => g_dvd, wnc => g_wnc, tac => g_tac, lac => g_lac, cwrc => g_cwrc,
cwrd => g_cwrd, clr => g_clr, trg => g_trg, atl => g_atl, att => g_att,
mla => g_mla, lsb => g_lsb, spa => g_spa, ppr => g_ppr, sreq => g_sreq,
isLocal => g_isLocal, currentSecAddr => g_currentSecAddr,
DI => DI, DO => DO, output_valid => g_output_valid,
ATN_in => ATN_in, ATN_out => g_ATN_out, DAV_in => DAV_in,
DAV_out => DAV_out, NRFD_in => NRFD_in, NRFD_out => NRFD_out,
NDAC_in => NDAC_in, NDAC_out => NDAC_out, EOI_in => EOI_in,
EOI_out => EOI_out, SRQ_in => SRQ_in, SRQ_out => SRQ_out,
IFC_in => IFC_in, IFC_out => IFC_out, REN_in => REN_in,
REN_out => REN_out, debug1 => open
);
reader: gpibReader port map (
clk => clk, reset => reset,
------------------------------------------------------------------------
------ GPIB interface --------------------------------------------------
------------------------------------------------------------------------
data_in => DI, dvd => g_dvd, lac => g_lac, lsb => g_lsb,
rdy => g_rdy,
------------------------------------------------------------------------
------ external interface ----------------------------------------------
------------------------------------------------------------------------
isLE => r_isLE, secAddr => g_currentSecAddr,
dataSecAddr => r_dataSecAddr, buf_interrupt => r_buf_interrupt,
end_of_stream => r_end_of_stream,
reset_reader => r_reset_buffer,
------------------ fifo --------------------------------------
fifo_full => r_fifo_full, fifo_ready_to_write => r_fifo_ready_to_write,
at_least_one_byte_in_fifo => r_at_least_one_byte_in_fifo,
data_out => rm_byte_in, fifo_strobe => r_strobe
);
writer: gpibWriter port map (
clk => clk, reset => reset,
------------------------------------------------------------------------
------ GPIB interface --------------------------------------------------
------------------------------------------------------------------------
data_out => g_data, wnc => g_wnc, spa => g_spa, nba => g_nba,
endOf => g_endOf, tac => g_tac, cwrc => g_cwrc,
------------------------------------------------------------------------
------ external interface ----------------------------------------------
------------------------------------------------------------------------
isTE => w_isTE,
secAddr => g_currentSecAddr, dataSecAddr => w_dataSecAddr,
buf_interrupt => w_buf_interrupt, end_of_stream => w_end_of_stream,
reset_writer => w_reset_buffer,
writer_enable => w_data_available,
---------------- fifo ---------------------------
availableFifoBytesCount => wm_availableBytesCount,
fifo_read_strobe => wm_strobe_read,
fifo_ready_to_read => wm_ready_to_read,
fifo_data_in => wm_byte_in
);
spc: SerialPollCoordinator port map (
clk => clk, reset => reset,
DAC => NDAC_in, rec_stb => s_rec_stb, ATN_in => g_ATN_out,
ATN_out => ATN_out, output_valid_in => g_output_valid,
output_valid_out => output_valid, stb_received => s_stb_received
);
readerFifo: Fifo8b port map (
reset => reset, clk => clk,
-------------- fifo --------------------
bytesAvailable => r_at_least_one_byte_in_fifo,
availableBytesCount => rm_availableBytesCount,
bufferFull => r_fifo_full,
resetFifo => rm_reset,
----------------------------------------
data_in => rm_byte_in, ready_to_write => r_fifo_ready_to_write,
strobe_write => r_strobe,
----------------------------------------
data_out => rm_byte_out(7 downto 0), ready_to_read => r_data_available,
strobe_read => rm_strobe_read
);
writerFifo: Fifo8b port map (
reset => reset, clk => clk,
-------------- fifo --------------------
bytesAvailable => wm_bytesAvailable,
availableBytesCount => wm_availableBytesCount,
bufferFull => wm_bufferFull,
resetFifo => wm_reset,
----------------------------------------
data_in => wm_data_in(7 downto 0),
ready_to_write => wm_ready_to_write,
strobe_write => wm_write_strobe,
----------------------------------------
data_out => wm_byte_in,
ready_to_read => wm_ready_to_read,
strobe_read => wm_strobe_read
);
--Clk2x_0: Clk2x port map (
-- reset => reset,
-- clk => clk,
-- clk2x => clk2x
--);
set0: SettingsReg0 port map (
reset => reset,
strobe => set0_strobe, data_in => set0_data_in,
data_out => set0_data_out,
------------- gpib -----------------------------
isLE_TE => set0_isLE_TE, lpeUsed => g_lpeUsed,
fixedPpLine => g_fixedPpLine, eosUsed => g_eosUsed,
eosMark => g_eosMark, lon => g_lon, ton => g_ton
);
set1: SettingsReg1 port map (
reset => reset,
strobe => set1_strobe, data_in => set1_data_in,
data_out => set1_data_out,
-- gpib
myAddr => set1_myAddr, T1 => g_T1
);
sec0: SecAddrReg port map (
reset => reset,
strobe => sec0_strobe, data_in => sec0_data_in,
data_out => sec0_data_out,
-- gpib
secAddrMask => sec0_secAddrMask
);
sec1: SecAddrReg port map (
reset => reset,
strobe => sec1_strobe, data_in => sec1_data_in,
data_out => sec1_data_out,
-- gpib
secAddrMask => sec1_secAddrMask
);
gbs: gpibBusReg port map (
data_out => gbs_data_out,
----------- gpib ---------------------------------
DIO => DI, ATN => ATN_in, DAV => DAV_in, NRFD => NRFD_in,
NDAC => NDAC_in, EOI => EOI_in, SRQ => SRQ_in, IFC => IFC_in,
REN => REN_in
);
ev: EventReg port map (
reset => reset, clk => clk,
strobe => ev_strobe, data_in => ev_data_in, data_out => ev_data_out,
-------------------- gpib device ---------------------
isLocal => g_isLocal, in_buf_ready => r_buf_interrupt,
out_buf_ready => w_buf_interrupt, clr => g_clr, trg => g_trg,
att => g_att, atl => g_atl, spa => g_spa,
-------------------- gpib controller ---------------------
cwrc => g_cwrc, cwrd => g_cwrd, srq => g_sreq, ppr => g_ppr,
-- stb received
stb_received => s_stb_received,
REN => REN_in, ATN => ATN_in, IFC => IFC_in
);
gs: GpibStatusReg port map (
data_out => gs_data_out,
--------------------- gpib ---------------------
currentSecAddr => g_currentSecAddr,
att => g_att, tac => g_tac, atl => g_atl, lac => g_lac,
cwrc => g_cwrc, cwrd => g_cwrd, spa => g_spa,
isLocal => g_isLocal
);
gc: gpibControlReg port map (
reset => reset,
strobe => gc_strobe, data_in => gc_data_in,
data_out => gc_data_out,
------------------ gpib ------------------------
ltn => g_ltn, lun => g_lun, rtl => g_rtl, rsv => g_rsv,
ist => g_ist, lpe => g_lpe,
------------------------------------------------
rsc => g_rsc, sic => g_sic, sre => g_sre, gts => g_gts,
tcs => g_tcs, tca => g_tca, rpp => g_rpp, rec_stb => s_rec_stb
);
rc0: ReaderControlReg0 port map (
clk => clk, reset => reset,
strobe => rc0_strobe, data_in => rc0_data_in, data_out => rc0_data_out,
------------------- gpib -------------------------
buf_interrupt => r_buf_interrupt, data_available => r_data_available,
end_of_stream => r_end_of_stream, reset_buffer => r_reset_buffer,
dataSecAddr => r_dataSecAddr
);
rc1: ReaderControlReg1 port map (
data_out => rc1_data_out,
------------------ gpib --------------------
bytes_available_in_fifo => rm_availableBytesCount
);
wc0: WriterControlReg0 port map (
clk => clk, reset => reset,
strobe => wc0_strobe, data_in => wc0_data_in, data_out => wc0_data_out,
------------------- gpib -------------------------
buf_interrupt => w_buf_interrupt, data_available => w_data_available,
end_of_stream => w_end_of_stream, reset_buffer => w_reset_buffer,
dataSecAddr => w_dataSecAddr, status_byte => wc0_status_byte
);
wc1: WriterControlReg1 port map (
reset => reset,
strobe => wc1_strobe, data_in => wc1_data_in,
data_out => wc1_data_out,
------------------ gpib --------------------
bytes_available_in_fifo => wm_availableBytesCount
);
ig: InterruptGenerator port map (
reset => reset, clk => clk, interrupt => interrupt_line,
-------------------- gpib device ---------------------
isLocal => g_isLocal, in_buf_ready => r_buf_interrupt,
out_buf_ready => w_buf_interrupt, clr => g_clr, trg => g_trg,
att => g_att, atl => g_atl, spa => g_spa, cwrc => g_cwrc,
cwrd => g_cwrd, srq => g_sreq, ppr => g_ppr,
stb_received => s_stb_received, REN => REN_in, ATN => ATN_in,
IFC => IFC_in
);
rml: RegMultiplexer generic map (ADDR_WIDTH => 15) port map (
strobe_read => strobe_read, strobe_write => strobe_write,
data_in => data_in, data_out => data_out,
--------------------------------------------------------
reg_addr => reg_addr,
--------------------------------------------------------
reg_strobe_0 => set0_strobe,
reg_in_0 => set0_data_in, reg_out_0 => set0_data_out,
reg_strobe_1 => set1_strobe,
reg_in_1 => set1_data_in, reg_out_1 => set1_data_out,
reg_strobe_2 => sec0_strobe,
reg_in_2 => sec0_data_in, reg_out_2 => sec0_data_out,
reg_strobe_3 => sec1_strobe,
reg_in_3 => sec1_data_in, reg_out_3 => sec1_data_out,
--reg_strobe_4 =>
--reg_in_4 =>
reg_out_4 => gbs_data_out,
reg_strobe_5 => ev_strobe,
reg_in_5 => ev_data_in, reg_out_5 => ev_data_out,
--reg_strobe_6 =>
--reg_in_6 =>
reg_out_6 => gs_data_out,
reg_strobe_7 => gc_strobe,
reg_in_7 => gc_data_in, reg_out_7 => gc_data_out,
reg_strobe_8 => rc0_strobe,
reg_in_8 => rc0_data_in, reg_out_8 => rc0_data_out,
--reg_strobe_9 => rc1_strobe,
--reg_in_9 => rc1_data_in,
reg_out_9 => rc1_data_out,
reg_strobe_10 => wc0_strobe,
reg_in_10 => wc0_data_in, reg_out_10 => wc0_data_out,
reg_strobe_11 => wc1_strobe,
reg_in_11 => wc1_data_in, reg_out_11 => wc1_data_out,
reg_strobe_other0 => rm_strobe_read,
--reg_in_other0 => ,
reg_out_other0 => rm_byte_out,
reg_strobe_other1 => wm_write_strobe,
reg_in_other1 => wm_data_in,
reg_out_other1 => "0000000000000000"
);
end arch;
| gpl-3.0 | 034dabbf0dbd3129c57e6b652c666f97 | 0.553288 | 3.118618 | false | false | false | false |
kb3gtn/mojo_modulator | vhdl/src/uart_db_interface.vhd | 3 | 7,380 | -------------------------------------------------------------------------------
-- uart_db_interface.vhd
--
-- This block is a state machine that interfaces that
-- translates the uart data stream into write/read commands
-- with the data bus master.
--
-- Note: There is a design simplification going on in this code..
-- There is an assumption that the databus actions occur much faster than
-- we can push uart data into this state machine.
--
-- In the case for slow uarts (sub 200 kbps) and system clock faster than 20 MHz
-- and slave latencies only a few clocks, this is assured.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity uart_db_interface is
port (
i_clk : in std_logic; -- input system clock
i_srst : in std_logic; -- sync reset to system clock
-- uart interface
i_rx_data : in std_logic_vector( 7 downto 0); -- data from uart
i_rx_data_valid : in std_logic; -- valid data from uart
o_rx_read_ack : out std_logic; -- tell uart we have read byte.
o_tx_send : out std_logic_vector( 7 downto 0); -- tx_send data
o_tx_send_wstrb : out std_logic; -- write data strobe
i_tx_send_busy : in std_logic; -- uart is busy tx, don't write anything.. (stall)
-- databus master interface
o_db_cmd_wstrb : out std_logic; -- write command strobe
o_db_cmd_out : out std_logic_vector( 7 downto 0); -- cmd to databus master
o_db_cmd_data_out : out std_logic_vector( 7 downto 0); -- write data to databus master
i_db_cmd_data_in : in std_logic_vector( 7 downto 0); -- read data from databus master
i_db_cmd_rdy : in std_logic -- db is ready to process a cmd / previous cmd is complete.
);
end entity;
architecture b of uart_db_interface is
-----------------------------------------------------------
-- signals
-----------------------------------------------------------
signal cmd_state : std_logic;
signal cmd_in : std_logic_vector( 7 downto 0);
signal write_data : std_logic_vector( 7 downto 0);
signal cmd_rdy_re : std_logic; -- rising edge detected
signal cmd_rdy_d1 : std_logic; -- delayed 1
signal rx_data_valid_re : std_logic;
signal rx_data_Valid_d1 : std_logic;
begin
o_db_cmd_out <= cmd_in;
o_db_cmd_data_out <= write_data;
cmd_done_detect : process( i_clk )
begin
if ( rising_edge( i_clk ) ) then
if ( i_srst = '1' ) then
-- in reset
cmd_rdy_re <= '0';
cmd_rdy_d1 <= i_db_cmd_rdy;
else
cmd_rdy_d1 <= i_db_cmd_rdy;
if ( cmd_rdy_d1 = '0' and i_db_cmd_rdy = '1' ) then
cmd_rdy_re <= '1';
else
cmd_rdy_re <= '0';
end if;
end if;
end if;
end process;
uart_rd_sm : process( i_clk )
begin
if ( rising_edge( i_clk ) ) then
if ( i_srst = '1' ) then
-- in reset
o_tx_send <= (others=>'0');
o_tx_send_wstrb <= '0';
else
-- for a read command completion do...
if ( cmd_in(7) = '1' and cmd_rdy_re = '1' ) then
-- there is an assumption that tx fifo is always
-- ready for data.
-- in the usage case here this is safe because
-- commands are rate limited by the uart input rate.
-- we are guaranteed that we will send data at the
-- serial link rate, since it takes 1 uart bytes to get
-- 1 read byte back to the uart...
o_tx_send <= i_db_cmd_data_in;
o_tx_send_wstrb <= '1';
else
o_tx_send_wstrb <= '0';
end if;
end if;
end if;
end process;
-- detect rising edge on data_valid
rx_valid_re_det : process(i_clk)
begin
if ( rising_edge(i_clk) ) then
rx_data_valid_d1 <= i_rx_data_valid;
if ( rx_data_valid_d1 = '0' and i_rx_data_valid = '1' ) then
rx_data_valid_re <= '1';
else
rx_data_Valid_re <= '0';
end if;
end if;
end process;
uart_intf_sm : process (i_clk)
begin
if ( rising_edge( i_clk ) ) then
if ( i_srst = '1' ) then
-- in reset
cmd_state <= '0'; -- '0' -- get address '1' -- get data (if write cmd)
o_db_cmd_wstrb <= '0';
cmd_in <= (others=>'0');
else
-- only do stuff if i_db_cmd_rdy is a '1'
-- if busy, just wait.
if ( i_db_cmd_rdy = '1' ) then
-- uart rx takes priority over uart tx
if ( rx_data_valid_re = '1' ) then
-- we have input data to read..
o_rx_read_ack <= '1';
-- cmd_state 0 -- first byte in command (reads only have 1 byte)
-- writes have 2 bytes, address and data.
if ( cmd_state = '0' ) then
-- process input cmd
cmd_in <= i_rx_data;
if ( i_rx_data(7) = '0' ) then
-- this is a write cmd,
-- next byte received will be data..
cmd_state <= '1'; -- get data next cycle
o_db_cmd_wstrb <= '0';
else
-- this is a read cmd, only 1 byte command is needed.
-- next byte received will be another command
cmd_state <= '0';
-- issue read to databus master
o_db_cmd_wstrb <= '1';
end if;
else
-- get data cycle on write command
-- processing input data
write_data <= i_rx_data;
-- issue cmd to databus master.
o_db_cmd_wstrb <= '1';
cmd_state <= '0'; -- reset back to cmd_state 0, start of next command
end if; -- cmd_state
else
-- not reading any data..
o_db_cmd_wstrb <= '0';
o_rx_read_ack <= '0';
end if; -- data_valid
else
o_db_cmd_wstrb <= '0';
o_rx_read_ack <= '0';
end if; -- cmd_rdy
end if; -- reset
end if; -- clk_rising
end process;
end architecture;
| apache-2.0 | 81a6b092dc3a3f8ac8b6b73f2611e694 | 0.424797 | 4.280742 | false | false | false | false |
autosub-team/autosub | src/tests/testTasksVHDL/testsubmissions/arithmetic/arithmetic_beh.vhdl | 2 | 2,046 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
architecture behavior of arithmetic is
constant N : integer := 15;
type solution is record
--The inputs
O: std_logic_vector(N-1 downto 0);
C: std_logic;
V: std_logic;
VALID: std_logic;
end record;
impure function do_operation(dummy:std_logic) return solution is
variable sol: solution;
subtype EXT_TYPE is signed(N-1 downto 0);
variable I1_EXT :EXT_TYPE := RESIZE(signed(I1),N);
variable I2_EXT :EXT_TYPE := RESIZE(signed(I2),N);
variable O_EXT :EXT_TYPE;
variable SIGNS : std_logic_vector(2 downto 0);
variable CARIES : std_logic_vector(1 downto 0); -- CIN, COUT
variable I1_SIGN : std_logic ;
variable I2_SIGN : std_logic ;
variable O_SIGN : std_logic ;
variable CF :std_logic;
variable VF :std_logic;
variable one :EXT_TYPE := (0=>'1',others=>'0');
begin
O_EXT := I1_EXT+I2_EXT;
I1_SIGN := I1_EXT(N-1);
I2_SIGN := I2_EXT(N-1);
O_SIGN := O_EXT(N-1);
SIGNS := (O_SIGN, I1_SIGN, I2_SIGN);
case SIGNS is
when "001" => CARIES := "11";
when "010" => CARIES := "11";
when "011" => CARIES := "10";
when "100" => CARIES := "01";
when "111" => CARIES := "11";
when others => CARIES := "00";
end case;
--ADD
CF := CARIES(1); --COUT
VF := CARIES(1) xor CARIES(0);--last two caries not same -> overflow
sol.O := std_logic_vector(O_EXT);
sol.C := CF;
sol.V := VF;
--comp2
sol.VALID := not VF;
return sol;
end do_operation;
begin
process (I1,I2)
variable solCalc : solution;
begin
solCalc:= do_operation('1');
O<=solCalc.O;
V<=solCalc.V;
C<=solCalc.C;
VALID<=solCalc.VALID;
end process;
end behavior;
| gpl-2.0 | bfdfe4a4b7048c971fd53b5077da837c | 0.514174 | 3.491468 | false | false | false | false |
Nooxet/embedded_bruteforce | brutus_system/hdl/system_microblaze_0_bram_block_wrapper.vhd | 1 | 3,083 | -------------------------------------------------------------------------------
-- system_microblaze_0_bram_block_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library microblaze_0_bram_block_elaborate_v1_00_a;
use microblaze_0_bram_block_elaborate_v1_00_a.all;
entity system_microblaze_0_bram_block_wrapper is
port (
BRAM_Rst_A : in std_logic;
BRAM_Clk_A : in std_logic;
BRAM_EN_A : in std_logic;
BRAM_WEN_A : in std_logic_vector(0 to 3);
BRAM_Addr_A : in std_logic_vector(0 to 31);
BRAM_Din_A : out std_logic_vector(0 to 31);
BRAM_Dout_A : in std_logic_vector(0 to 31);
BRAM_Rst_B : in std_logic;
BRAM_Clk_B : in std_logic;
BRAM_EN_B : in std_logic;
BRAM_WEN_B : in std_logic_vector(0 to 3);
BRAM_Addr_B : in std_logic_vector(0 to 31);
BRAM_Din_B : out std_logic_vector(0 to 31);
BRAM_Dout_B : in std_logic_vector(0 to 31)
);
attribute x_core_info : STRING;
attribute keep_hierarchy : STRING;
attribute x_core_info of system_microblaze_0_bram_block_wrapper : entity is "microblaze_0_bram_block_elaborate_v1_00_a";
attribute keep_hierarchy of system_microblaze_0_bram_block_wrapper : entity is "yes";
end system_microblaze_0_bram_block_wrapper;
architecture STRUCTURE of system_microblaze_0_bram_block_wrapper is
component microblaze_0_bram_block_elaborate is
generic (
C_MEMSIZE : integer;
C_PORT_DWIDTH : integer;
C_PORT_AWIDTH : integer;
C_NUM_WE : integer;
C_FAMILY : string
);
port (
BRAM_Rst_A : in std_logic;
BRAM_Clk_A : in std_logic;
BRAM_EN_A : in std_logic;
BRAM_WEN_A : in std_logic_vector(0 to C_NUM_WE-1);
BRAM_Addr_A : in std_logic_vector(0 to C_PORT_AWIDTH-1);
BRAM_Din_A : out std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Dout_A : in std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Rst_B : in std_logic;
BRAM_Clk_B : in std_logic;
BRAM_EN_B : in std_logic;
BRAM_WEN_B : in std_logic_vector(0 to C_NUM_WE-1);
BRAM_Addr_B : in std_logic_vector(0 to C_PORT_AWIDTH-1);
BRAM_Din_B : out std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Dout_B : in std_logic_vector(0 to C_PORT_DWIDTH-1)
);
end component;
begin
microblaze_0_bram_block : microblaze_0_bram_block_elaborate
generic map (
C_MEMSIZE => 16#8000#,
C_PORT_DWIDTH => 32,
C_PORT_AWIDTH => 32,
C_NUM_WE => 4,
C_FAMILY => "spartan6"
)
port map (
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_Din_A => BRAM_Din_A,
BRAM_Dout_A => BRAM_Dout_A,
BRAM_Rst_B => BRAM_Rst_B,
BRAM_Clk_B => BRAM_Clk_B,
BRAM_EN_B => BRAM_EN_B,
BRAM_WEN_B => BRAM_WEN_B,
BRAM_Addr_B => BRAM_Addr_B,
BRAM_Din_B => BRAM_Din_B,
BRAM_Dout_B => BRAM_Dout_B
);
end architecture STRUCTURE;
| mit | 0fd5e9fc7259ba8441bce06d02f5be78 | 0.590658 | 2.984511 | false | false | false | false |
Nooxet/embedded_bruteforce | brutus_system/hdl/system_rs232_uart_1_wrapper.vhd | 1 | 3,833 | -------------------------------------------------------------------------------
-- system_rs232_uart_1_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library axi_uartlite_v1_02_a;
use axi_uartlite_v1_02_a.all;
entity system_rs232_uart_1_wrapper is
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
Interrupt : out std_logic;
S_AXI_AWADDR : in std_logic_vector(3 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(3 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
RX : in std_logic;
TX : out std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of system_rs232_uart_1_wrapper : entity is "axi_uartlite_v1_02_a";
end system_rs232_uart_1_wrapper;
architecture STRUCTURE of system_rs232_uart_1_wrapper is
component axi_uartlite is
generic (
C_FAMILY : STRING;
C_INSTANCE : STRING;
C_S_AXI_ACLK_FREQ_HZ : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_BAUDRATE : INTEGER;
C_DATA_BITS : INTEGER;
C_USE_PARITY : INTEGER;
C_ODD_PARITY : INTEGER
);
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
Interrupt : out std_logic;
S_AXI_AWADDR : in std_logic_vector(3 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_WSTRB : in std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(3 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
RX : in std_logic;
TX : out std_logic
);
end component;
begin
RS232_Uart_1 : axi_uartlite
generic map (
C_FAMILY => "spartan6",
C_INSTANCE => "RS232_Uart_1",
C_S_AXI_ACLK_FREQ_HZ => 50000000,
C_S_AXI_DATA_WIDTH => 32,
C_BAUDRATE => 9600,
C_DATA_BITS => 8,
C_USE_PARITY => 0,
C_ODD_PARITY => 1
)
port map (
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
Interrupt => Interrupt,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
RX => RX,
TX => TX
);
end architecture STRUCTURE;
| mit | fdcf0ebc22d27e2298442fdf4d9c88ef | 0.577094 | 3.042063 | false | false | false | false |
mithro/HDMI2USB | ipcore_dir/cmdfifo/simulation/cmdfifo_rng.vhd | 3 | 3,884 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: cmdfifo_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY cmdfifo_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF cmdfifo_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
| bsd-2-clause | 13892b6448113a5dbc65da9cb27a2555 | 0.637745 | 4.378805 | false | false | false | false |
RickvanLoo/Synthesizer | spi_seperate.vhd | 1 | 664 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY spi_seperate IS
PORT ( CLK : IN std_logic;
RESET : IN std_logic;
BYTE0, BYTE1 : IN std_logic_vector(7 downto 0);
ADDR, DATA : OUT std_logic_vector(7 downto 0)
);
END spi_seperate;
ARCHITECTURE behav of spi_seperate is
BEGIN
process(CLK,RESET)
begin
if reset = '0' then
ADDR <= (others => '0');
DATA <= (others => '0');
elsif rising_edge(clk) then
if BYTE0(7) = '1' then
ADDR <= BYTE0;
else
DATA <= BYTE0;
end if;
if BYTE1(7) = '1' then
ADDR <= BYTE1;
else
DATA <= BYTE1;
end if;
end if;
end process;
END behav; | mit | fd119974708387188256aff982a9bf35 | 0.603916 | 2.73251 | false | false | false | false |
mithro/HDMI2USB | ipcore_dir/rawUVCfifo/simulation/rawUVCfifo_synth.vhd | 3 | 11,513 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rawUVCfifo_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.rawUVCfifo_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY rawUVCfifo_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF rawUVCfifo_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL valid : STD_LOGIC;
SIGNAL almost_full : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL prog_full : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(24-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(24-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(24-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(24-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_i <= WR_CLK;
rd_clk_i <= RD_CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
almost_full_i <= almost_full;
fg_dg_nv: rawUVCfifo_dgen
GENERIC MAP (
C_DIN_WIDTH => 24,
C_DOUT_WIDTH => 24,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: rawUVCfifo_dverif
GENERIC MAP (
C_DOUT_WIDTH => 24,
C_DIN_WIDTH => 24,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: rawUVCfifo_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 24,
C_DIN_WIDTH => 24,
C_WR_PNTR_WIDTH => 6,
C_RD_PNTR_WIDTH => 6,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
rawUVCfifo_inst : rawUVCfifo_exdes
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
VALID => valid,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| bsd-2-clause | 3f3dbd7d45fbd596172f7d930ccc5bac | 0.456006 | 4.033987 | false | false | false | false |
mithro/HDMI2USB | ipcore_dir/rgbfifo/simulation/rgbfifo_pkg.vhd | 3 | 11,419 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rgbfifo_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE rgbfifo_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT rgbfifo_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT rgbfifo_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT rgbfifo_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT rgbfifo_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT rgbfifo_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT rgbfifo_exdes IS
PORT (
CLK : IN std_logic;
VALID : OUT std_logic;
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(8-1 DOWNTO 0);
DOUT : OUT std_logic_vector(8-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END rgbfifo_pkg;
PACKAGE BODY rgbfifo_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END rgbfifo_pkg;
| bsd-2-clause | b9973871ade91bcfc632d294d2b16d00 | 0.504072 | 3.988474 | false | false | false | false |
Nooxet/embedded_bruteforce | brutus_system/pcores/bajsd_v1_00_a - Copy/hdl/vhdl/tb_pre_proc.vhd | 1 | 3,124 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:08:22 09/17/2014
-- Design Name:
-- Module Name: H:/Documents/md5_test/tb_pre_proc.vhd
-- Project Name: md5_test
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: pre_process
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY tb_pre_proc IS
END tb_pre_proc;
ARCHITECTURE behavior OF tb_pre_proc IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT pre_process
PORT(
i_data : IN std_logic_vector(47 downto 0);
i_length : IN std_logic_vector(2 downto 0);
o_data_0 : OUT unsigned(31 downto 0);
o_data_1 : OUT unsigned(31 downto 0);
o_length : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
signal clock : std_logic := '0';
--Inputs
signal i_data : std_logic_vector(47 downto 0) := (others => '0');
signal i_length : std_logic_vector(2 downto 0) := (others => '0');
--Outputs
signal o_data_0 : unsigned(31 downto 0);
signal o_data_1 : unsigned(31 downto 0);
signal o_length : std_logic_vector(7 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: pre_process PORT MAP (
i_data => i_data,
i_length => i_length,
o_data_0 => o_data_0,
o_data_1 => o_data_1,
o_length => o_length
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
i_data <= x"000000000061";--a
i_length <= "001";
wait for clock_period;
i_data <= x"000000006261";--ab
i_length <= "010";
wait for clock_period;
i_data <= x"000000636261";--abc
i_length <= "011";
wait for clock_period;
i_data <= x"000064636261";--abcd
i_length <= "100";
wait for clock_period;
i_data <= x"006564636261";--abcde
i_length <= "101";
wait for clock_period;
i_data <= x"666564636261";--abcdef
i_length <= "110";
wait for clock_period;
-- insert stimulus here
wait;
end process;
END;
| mit | 5566627f83c9de157d0cee3374787c6e | 0.59379 | 3.594937 | false | true | false | false |
FelixWinterstein/Vivado-KMeans | lloyds_algorithm_RTL/source/vhdl/madd.vhd | 1 | 5,232 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: madd - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
-- calculates a*b+c
entity madd is -- latency = mul core latency + 1 if add incl
generic (
MUL_LATENCY : integer := 3;
A_BITWIDTH : integer := 16;
B_BITWIDTH : integer := 16;
INCLUDE_ADD : boolean := false;
C_BITWIDTH : integer := 16;
RES_BITWIDTH : integer := 16
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
a : in std_logic_vector(A_BITWIDTH-1 downto 0);
b : in std_logic_vector(B_BITWIDTH-1 downto 0);
c : in std_logic_vector(C_BITWIDTH-1 downto 0);
res : out std_logic_vector(RES_BITWIDTH-1 downto 0);
rdy : out std_logic
);
end madd;
architecture Behavioral of madd is
constant INT_BITWIDTH : integer := A_BITWIDTH+B_BITWIDTH+1;
type data_delay_type is array(0 to MUL_LATENCY-1) of std_logic_vector(C_BITWIDTH-1 downto 0);
function sext(val : std_logic_vector; length : integer) return std_logic_vector is
variable val_msb : std_logic;
variable result : std_logic_vector(length-1 downto 0);
begin
val_msb := val(val'length-1);
result(val'length-1 downto 0) := val;
result(length-1 downto val'length) := (others => val_msb);
return result;
end sext;
component mul
port (
clk : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(A_BITWIDTH-1 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(B_BITWIDTH DOWNTO 0);
p : OUT STD_LOGIC_VECTOR(A_BITWIDTH+B_BITWIDTH-1 DOWNTO 0)
);
end component;
component addorsub is
generic (
A_BITWIDTH : integer := 16;
B_BITWIDTH : integer := 16;
RES_BITWIDTH : integer := 16
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
sub : in std_logic;
a : in std_logic_vector(A_BITWIDTH-1 downto 0);
b : in std_logic_vector(B_BITWIDTH-1 downto 0);
res : out std_logic_vector(RES_BITWIDTH-1 downto 0);
rdy : out std_logic
);
end component;
signal tmp_pout : std_logic_vector(A_BITWIDTH+B_BITWIDTH-1 downto 0);
signal pout : std_logic_vector(INT_BITWIDTH-1 downto 0);
signal summand_1 : signed(INT_BITWIDTH-1 downto 0);
signal summand_2 : signed(INT_BITWIDTH-1 downto 0);
signal sum_reg : signed(INT_BITWIDTH-1 downto 0);
signal delay_line : std_logic_vector(0 to MUL_LATENCY+1-1);
signal data_delay_line : data_delay_type;
begin
-- compensate mul latency
delay_line_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
delay_line <= (others => '0');
else
delay_line(0) <= nd;
delay_line(1 to MUL_LATENCY+1-1) <= delay_line(0 to MUL_LATENCY+1-2);
end if;
end if;
end process delay_line_proc;
G_N_ADD : if INCLUDE_ADD = false generate
mul_inst : mul
port map (
clk => clk,
a => a,
b => b,
p => tmp_pout
);
pout <= sext(tmp_pout,INT_BITWIDTH);
res <= pout(INT_BITWIDTH-1 downto INT_BITWIDTH-RES_BITWIDTH);
rdy <= delay_line(MUL_LATENCY-1);
end generate G_N_ADD;
G_ADD : if INCLUDE_ADD = true generate
mul_inst : mul
port map (
clk => clk,
a => a,
b => b,
p => tmp_pout
);
data_delay_proc : process(clk)
begin
if rising_edge(clk) then
data_delay_line(0) <= c;
data_delay_line(1 to MUL_LATENCY-1) <= data_delay_line(0 to MUL_LATENCY-2);
end if;
end process data_delay_proc;
summand_1 <= signed(sext(data_delay_line(MUL_LATENCY-1),INT_BITWIDTH));
summand_2 <= signed(sext(tmp_pout,INT_BITWIDTH));
sum_reg_proc : process(clk)
begin
if rising_edge(clk) then
sum_reg <= summand_1 + summand_2;
end if;
end process sum_reg_proc;
res <= std_logic_vector(sum_reg(INT_BITWIDTH-1 downto INT_BITWIDTH-RES_BITWIDTH));
rdy <= delay_line(MUL_LATENCY+1-1);
end generate G_ADD;
end Behavioral;
| bsd-3-clause | 6741210153629416ef5e975926f430eb | 0.528096 | 3.963636 | false | false | false | false |
Nooxet/embedded_bruteforce | brutus_system/ISE/fuck_vga/vga_ctrl.vhd | 1 | 2,285 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:29:32 10/15/2014
-- Design Name:
-- Module Name: vga_ctrl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vga_ctrl is
port (
clk : in std_logic;
rst : in std_logic;
hsync : out std_logic;
vsync : out std_logic;
gr : out std_logic_vector(2 downto 0);
re : out std_logic_vector(2 downto 0);
bl : out std_logic_vector(1 downto 0)
);
end vga_ctrl;
architecture Behavioral of vga_ctrl is
constant HD : integer := 640; -- h display
constant HF : integer := 16; -- h front porch
constant HB : integer := 48; -- h back porch
constant HR : integer := 96; -- h retrace
constant HT : integer := 799; -- h total
constant VD : integer := 480; -- v display
constant VF : integer := 11; -- v front porch
constant VB : integer := 31; -- v back porch
constant VR : integer := 2; -- v retrace
constant VT : integer := 524; -- v total
signal clk_div_c, clk_div_n : unsigned(1 downto 0); -- mod 4
signal h_count_c, h_count_n, v_count_c, v_count_n : unsigned(9 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
clk_div_c <= (others => '0');
h_count_c <= (others => '0');
v_count_c <= (others => '0');
else
clk_div_c <= clk_div_n;
h_count_c <= h_count_n;
v_count_c <= v_count_n;
end if;
end if;
end process;
clk_div_n <= clk_div_c + 1;
h_proc: process(clk_div_c, h_count_c)
begin
h_count_n <= h_count_c;
if (clk_div_c = "11") then
h_count_n <= h_count_c + 1;
if h_count_c = HT then
h_count_n <= (others => '0');
end if;
end if;
end process;
v_proc: process(clk_div_c, h_count_c, v_count_c)
begin
v_count_n <= v_count_c;
if (clk_div_c = "11" and h_count_c = HT) then
v_count_n <= v_count_c + 1;
if v_count_c = VT then
v_count_n <= (others => '0');
end if;
end if;
end process;
--
end Behavioral; | mit | 5771c9b522be411aaed8daedb230d53d | 0.550547 | 2.803681 | false | false | false | false |
freecores/gpib_controller | vhdl/src/gpib/SecAddrSaver.vhd | 1 | 1,875 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: SecAddrSaver
-- Date:2011-11-11
-- Author: Andrzej Paluch
--
-- Description ${cursor}
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity SecAddrSaver is
port (
reset : in std_logic;
------------------- gpib ----------------------
TADS : in std_logic;
TPAS : in std_logic;
LADS : in std_logic;
LPAS : in std_logic;
MSA_Dec : in std_logic;
DI : in std_logic_vector(4 downto 0);
currentSecAddr : out std_logic_vector(4 downto 0)
);
end SecAddrSaver;
architecture arch of SecAddrSaver is
signal goToSecAddressed : std_logic;
begin
goToSecAddressed <= MSA_Dec and ((TADS and TPAS) or (LADS and LPAS));
-- save secondary address
process (reset, goToSecAddressed) begin
if(reset = '1') then
currentSecAddr <= (others => '0');
elsif rising_edge(goToSecAddressed) then
currentSecAddr <= DI(4 downto 0);
end if;
end process;
end arch;
| gpl-3.0 | c7fdeda8c8572b9edd6b9f606efa21ea | 0.610133 | 3.922594 | false | false | false | false |
mithro/HDMI2USB | ipcore_dir/ddr2ram/example_design/rtl/example_top.vhd | 3 | 40,751 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : example_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:56 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is the design top level. which instantiates top wrapper,
-- test bench top and infrastructure modules.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity example_top is
generic
(
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 3200;
-- Memory data transfer clock period.
C3_RST_ACT_LOW : integer := 0;
-- # = 1 for active low reset,
-- # = 0 for active high reset.
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
-- input clock type DIFFERENTIAL or SINGLE_ENDED.
C3_CALIB_SOFT_IP : string := "TRUE";
-- # = TRUE, Enables the soft calibration logic,
-- # = FALSE, Disables the soft calibration logic.
C3_SIMULATION : string := "FALSE";
-- # = TRUE, Simulating the design. Useful to reduce the simulation time,
-- # = FALSE, Implementing the design.
C3_HW_TESTING : string := "FALSE";
-- Determines the address space accessed by the traffic generator,
-- # = FALSE, Smaller address space,
-- # = TRUE, Large address space.
DEBUG_EN : integer := 0;
-- # = 1, Enable debug signals/controls,
-- = 0, Disable debug signals/controls.
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
-- The order in which user address is provided to the memory controller,
-- ROW_BANK_COLUMN or BANK_ROW_COLUMN.
C3_NUM_DQ_PINS : integer := 16;
-- External memory data width.
C3_MEM_ADDR_WIDTH : integer := 13;
-- External memory address width.
C3_MEM_BANKADDR_WIDTH : integer := 3
-- External memory bank address width.
);
port
(
calib_done : out std_logic;
error : out std_logic;
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_i : in std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic
);
end example_top;
architecture arc of example_top is
component memc3_infrastructure is
generic (
C_RST_ACT_LOW : integer;
C_INPUT_CLK_TYPE : string;
C_CLKOUT0_DIVIDE : integer;
C_CLKOUT1_DIVIDE : integer;
C_CLKOUT2_DIVIDE : integer;
C_CLKOUT3_DIVIDE : integer;
C_CLKFBOUT_MULT : integer;
C_DIVCLK_DIVIDE : integer;
C_INCLK_PERIOD : integer
);
port (
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk : in std_logic;
sys_rst_i : in std_logic;
clk0 : out std_logic;
rst0 : out std_logic;
async_rst : out std_logic;
sysclk_2x : out std_logic;
sysclk_2x_180 : out std_logic;
pll_ce_0 : out std_logic;
pll_ce_90 : out std_logic;
pll_lock : out std_logic;
mcb_drp_clk : out std_logic
);
end component;
component memc3_wrapper is
generic (
C_MEMCLK_PERIOD : integer;
C_CALIB_SOFT_IP : string;
C_SIMULATION : string;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(5 downto 0);
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_MEM_ADDR_ORDER : string;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_DDR3_ODS : string;
C_MEM_DDR3_RTT : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_DDR3_DYN_WRT_ODT : string;
C_MEM_MOBILE_PA_SR : string;
C_MEM_MDDR_ODS : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_LDQSP_TAP_DELAY_VAL : integer;
C_LDQSN_TAP_DELAY_VAL : integer;
C_UDQSP_TAP_DELAY_VAL : integer;
C_UDQSN_TAP_DELAY_VAL : integer;
C_DQ0_TAP_DELAY_VAL : integer;
C_DQ1_TAP_DELAY_VAL : integer;
C_DQ2_TAP_DELAY_VAL : integer;
C_DQ3_TAP_DELAY_VAL : integer;
C_DQ4_TAP_DELAY_VAL : integer;
C_DQ5_TAP_DELAY_VAL : integer;
C_DQ6_TAP_DELAY_VAL : integer;
C_DQ7_TAP_DELAY_VAL : integer;
C_DQ8_TAP_DELAY_VAL : integer;
C_DQ9_TAP_DELAY_VAL : integer;
C_DQ10_TAP_DELAY_VAL : integer;
C_DQ11_TAP_DELAY_VAL : integer;
C_DQ12_TAP_DELAY_VAL : integer;
C_DQ13_TAP_DELAY_VAL : integer;
C_DQ14_TAP_DELAY_VAL : integer;
C_DQ15_TAP_DELAY_VAL : integer
);
port (
mcb3_dram_dq : inout std_logic_vector((C_NUM_DQ_PINS-1) downto 0);
mcb3_dram_a : out std_logic_vector((C_MEM_ADDR_WIDTH-1) downto 0);
mcb3_dram_ba : out std_logic_vector((C_MEM_BANKADDR_WIDTH-1) downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
calib_done : out std_logic;
async_rst : in std_logic;
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
mcb_drp_clk : in std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 downto 0);
p2_cmd_bl : in std_logic_vector(5 downto 0);
p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 downto 0);
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 downto 0);
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 downto 0);
p3_cmd_bl : in std_logic_vector(5 downto 0);
p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 downto 0);
p3_wr_data : in std_logic_vector(31 downto 0);
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 downto 0);
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
component memc3_tb_top is
generic (
C_SIMULATION : string;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_NUM_DQ_PINS : integer;
C_MEM_BURST_LEN : integer;
C_MEM_NUM_COL_BITS : integer;
C_SMALL_DEVICE : string;
C_p2_BEGIN_ADDRESS : std_logic_vector(31 downto 0);
C_p2_DATA_MODE : std_logic_vector(3 downto 0);
C_p2_END_ADDRESS : std_logic_vector(31 downto 0);
C_p2_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
C_p2_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0);
C_p3_BEGIN_ADDRESS : std_logic_vector(31 downto 0);
C_p3_DATA_MODE : std_logic_vector(3 downto 0);
C_p3_END_ADDRESS : std_logic_vector(31 downto 0);
C_p3_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
C_p3_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0)
);
port (
error : out std_logic;
calib_done : in std_logic;
clk0 : in std_logic;
rst0 : in std_logic;
cmp_error : out std_logic;
cmp_data_valid : out std_logic;
vio_modify_enable : in std_logic;
error_status : out std_logic_vector(127 downto 0);
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_data : out std_logic_vector(31 downto 0);
p2_mcb_cmd_en_o : out std_logic;
p2_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p2_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p2_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p2_mcb_cmd_full_i : in std_logic;
p2_mcb_rd_en_o : out std_logic;
p2_mcb_rd_data_i : in std_logic_vector(31 downto 0);
p2_mcb_rd_empty_i : in std_logic;
p2_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
p3_mcb_cmd_en_o : out std_logic;
p3_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p3_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p3_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p3_mcb_cmd_full_i : in std_logic;
p3_mcb_wr_en_o : out std_logic;
p3_mcb_wr_mask_o : out std_logic_vector(3 downto 0);
p3_mcb_wr_data_o : out std_logic_vector(31 downto 0);
p3_mcb_wr_full_i : in std_logic;
p3_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0)
);
end component;
function c3_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is
begin
if (C3_HW_TESTING = "FALSE") then
return val1;
else
return val2;
end if;
end function;
constant C3_CLKOUT0_DIVIDE : integer := 1;
constant C3_CLKOUT1_DIVIDE : integer := 1;
constant C3_CLKOUT2_DIVIDE : integer := 16;
constant C3_CLKOUT3_DIVIDE : integer := 8;
constant C3_CLKFBOUT_MULT : integer := 2;
constant C3_DIVCLK_DIVIDE : integer := 1;
constant C3_INCLK_PERIOD : integer := ((C3_MEMCLK_PERIOD * C3_CLKFBOUT_MULT) / (C3_DIVCLK_DIVIDE * C3_CLKOUT0_DIVIDE * 2));
constant C3_ARB_NUM_TIME_SLOTS : integer := 12;
constant C3_ARB_TIME_SLOT_0 : bit_vector(5 downto 0) := o"23";
constant C3_ARB_TIME_SLOT_1 : bit_vector(5 downto 0) := o"32";
constant C3_ARB_TIME_SLOT_2 : bit_vector(5 downto 0) := o"23";
constant C3_ARB_TIME_SLOT_3 : bit_vector(5 downto 0) := o"32";
constant C3_ARB_TIME_SLOT_4 : bit_vector(5 downto 0) := o"23";
constant C3_ARB_TIME_SLOT_5 : bit_vector(5 downto 0) := o"32";
constant C3_ARB_TIME_SLOT_6 : bit_vector(5 downto 0) := o"23";
constant C3_ARB_TIME_SLOT_7 : bit_vector(5 downto 0) := o"32";
constant C3_ARB_TIME_SLOT_8 : bit_vector(5 downto 0) := o"23";
constant C3_ARB_TIME_SLOT_9 : bit_vector(5 downto 0) := o"32";
constant C3_ARB_TIME_SLOT_10 : bit_vector(5 downto 0) := o"23";
constant C3_ARB_TIME_SLOT_11 : bit_vector(5 downto 0) := o"32";
constant C3_MEM_TRAS : integer := 42500;
constant C3_MEM_TRCD : integer := 12500;
constant C3_MEM_TREFI : integer := 7800000;
constant C3_MEM_TRFC : integer := 127500;
constant C3_MEM_TRP : integer := 12500;
constant C3_MEM_TWR : integer := 15000;
constant C3_MEM_TRTP : integer := 7500;
constant C3_MEM_TWTR : integer := 7500;
constant C3_MEM_TYPE : string := "DDR2";
constant C3_MEM_DENSITY : string := "1Gb";
constant C3_MEM_BURST_LEN : integer := 4;
constant C3_MEM_CAS_LATENCY : integer := 5;
constant C3_MEM_NUM_COL_BITS : integer := 10;
constant C3_MEM_DDR1_2_ODS : string := "FULL";
constant C3_MEM_DDR2_RTT : string := "50OHMS";
constant C3_MEM_DDR2_DIFF_DQS_EN : string := "YES";
constant C3_MEM_DDR2_3_PA_SR : string := "FULL";
constant C3_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
constant C3_MEM_DDR3_CAS_LATENCY : integer := 6;
constant C3_MEM_DDR3_ODS : string := "DIV6";
constant C3_MEM_DDR3_RTT : string := "DIV2";
constant C3_MEM_DDR3_CAS_WR_LATENCY : integer := 5;
constant C3_MEM_DDR3_AUTO_SR : string := "ENABLED";
constant C3_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
constant C3_MEM_MOBILE_PA_SR : string := "FULL";
constant C3_MEM_MDDR_ODS : string := "FULL";
constant C3_MC_CALIB_BYPASS : string := "NO";
constant C3_MC_CALIBRATION_MODE : string := "CALIBRATION";
constant C3_MC_CALIBRATION_DELAY : string := "HALF";
constant C3_SKIP_IN_TERM_CAL : integer := 0;
constant C3_SKIP_DYNAMIC_CAL : integer := 0;
constant C3_LDQSP_TAP_DELAY_VAL : integer := 0;
constant C3_LDQSN_TAP_DELAY_VAL : integer := 0;
constant C3_UDQSP_TAP_DELAY_VAL : integer := 0;
constant C3_UDQSN_TAP_DELAY_VAL : integer := 0;
constant C3_DQ0_TAP_DELAY_VAL : integer := 0;
constant C3_DQ1_TAP_DELAY_VAL : integer := 0;
constant C3_DQ2_TAP_DELAY_VAL : integer := 0;
constant C3_DQ3_TAP_DELAY_VAL : integer := 0;
constant C3_DQ4_TAP_DELAY_VAL : integer := 0;
constant C3_DQ5_TAP_DELAY_VAL : integer := 0;
constant C3_DQ6_TAP_DELAY_VAL : integer := 0;
constant C3_DQ7_TAP_DELAY_VAL : integer := 0;
constant C3_DQ8_TAP_DELAY_VAL : integer := 0;
constant C3_DQ9_TAP_DELAY_VAL : integer := 0;
constant C3_DQ10_TAP_DELAY_VAL : integer := 0;
constant C3_DQ11_TAP_DELAY_VAL : integer := 0;
constant C3_DQ12_TAP_DELAY_VAL : integer := 0;
constant C3_DQ13_TAP_DELAY_VAL : integer := 0;
constant C3_DQ14_TAP_DELAY_VAL : integer := 0;
constant C3_DQ15_TAP_DELAY_VAL : integer := 0;
constant C3_SMALL_DEVICE : string := "FALSE"; -- The parameter is set to TRUE for all packages of xc6slx9 device
-- as most of them cannot fit the complete example design when the
-- Chip scope modules are enabled
constant C3_p2_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
constant C3_p2_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C3_p2_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000002ff", x"02ffffff");
constant C3_p2_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffffc00", x"fc000000");
constant C3_p2_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
constant C3_p3_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000500", x"05000000");
constant C3_p3_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C3_p3_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000006ff", x"06ffffff");
constant C3_p3_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffff800", x"f8000000");
constant C3_p3_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000500", x"05000000");
signal c3_sys_clk_p : std_logic;
signal c3_sys_clk_n : std_logic;
signal c3_error : std_logic;
signal c3_calib_done : std_logic;
signal c3_clk0 : std_logic;
signal c3_rst0 : std_logic;
signal c3_async_rst : std_logic;
signal c3_sysclk_2x : std_logic;
signal c3_sysclk_2x_180 : std_logic;
signal c3_pll_ce_0 : std_logic;
signal c3_pll_ce_90 : std_logic;
signal c3_pll_lock : std_logic;
signal c3_mcb_drp_clk : std_logic;
signal c3_cmp_error : std_logic;
signal c3_cmp_data_valid : std_logic;
signal c3_vio_modify_enable : std_logic;
signal c3_error_status : std_logic_vector(127 downto 0);
signal c3_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c3_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal c3_cmp_data : std_logic_vector(31 downto 0);
signal c3_p2_cmd_en : std_logic;
signal c3_p2_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p2_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p2_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p2_cmd_empty : std_logic;
signal c3_p2_cmd_full : std_logic;
signal c3_p2_rd_en : std_logic;
signal c3_p2_rd_data : std_logic_vector(31 downto 0);
signal c3_p2_rd_full : std_logic;
signal c3_p2_rd_empty : std_logic;
signal c3_p2_rd_count : std_logic_vector(6 downto 0);
signal c3_p2_rd_overflow : std_logic;
signal c3_p2_rd_error : std_logic;
signal c3_p3_cmd_en : std_logic;
signal c3_p3_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p3_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p3_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p3_cmd_empty : std_logic;
signal c3_p3_cmd_full : std_logic;
signal c3_p3_wr_en : std_logic;
signal c3_p3_wr_mask : std_logic_vector(3 downto 0);
signal c3_p3_wr_data : std_logic_vector(31 downto 0);
signal c3_p3_wr_full : std_logic;
signal c3_p3_wr_empty : std_logic;
signal c3_p3_wr_count : std_logic_vector(6 downto 0);
signal c3_p3_wr_underrun : std_logic;
signal c3_p3_wr_error : std_logic;
signal c3_selfrefresh_enter : std_logic;
signal c3_selfrefresh_mode : std_logic;
begin
error <= c3_error;
calib_done <= c3_calib_done;
c3_sys_clk_p <= '0';
c3_sys_clk_n <= '0';
c3_selfrefresh_enter <= '0';
memc3_infrastructure_inst : memc3_infrastructure
generic map
(
C_RST_ACT_LOW => C3_RST_ACT_LOW,
C_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
C_CLKOUT0_DIVIDE => C3_CLKOUT0_DIVIDE,
C_CLKOUT1_DIVIDE => C3_CLKOUT1_DIVIDE,
C_CLKOUT2_DIVIDE => C3_CLKOUT2_DIVIDE,
C_CLKOUT3_DIVIDE => C3_CLKOUT3_DIVIDE,
C_CLKFBOUT_MULT => C3_CLKFBOUT_MULT,
C_DIVCLK_DIVIDE => C3_DIVCLK_DIVIDE,
C_INCLK_PERIOD => C3_INCLK_PERIOD
)
port map
(
sys_clk_p => c3_sys_clk_p,
sys_clk_n => c3_sys_clk_n,
sys_clk => c3_sys_clk,
sys_rst_i => c3_sys_rst_i,
clk0 => c3_clk0,
rst0 => c3_rst0,
async_rst => c3_async_rst,
sysclk_2x => c3_sysclk_2x,
sysclk_2x_180 => c3_sysclk_2x_180,
pll_ce_0 => c3_pll_ce_0,
pll_ce_90 => c3_pll_ce_90,
pll_lock => c3_pll_lock,
mcb_drp_clk => c3_mcb_drp_clk
);
-- wrapper instantiation
memc3_wrapper_inst : memc3_wrapper
generic map
(
C_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C_CALIB_SOFT_IP => C3_CALIB_SOFT_IP,
C_SIMULATION => C3_SIMULATION,
C_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C3_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => C3_ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => C3_ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => C3_ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => C3_ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => C3_ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => C3_ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => C3_ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => C3_ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => C3_ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => C3_ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => C3_ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => C3_ARB_TIME_SLOT_11,
C_MEM_TRAS => C3_MEM_TRAS,
C_MEM_TRCD => C3_MEM_TRCD,
C_MEM_TREFI => C3_MEM_TREFI,
C_MEM_TRFC => C3_MEM_TRFC,
C_MEM_TRP => C3_MEM_TRP,
C_MEM_TWR => C3_MEM_TWR,
C_MEM_TRTP => C3_MEM_TRTP,
C_MEM_TWTR => C3_MEM_TWTR,
C_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C_MEM_TYPE => C3_MEM_TYPE,
C_MEM_DENSITY => C3_MEM_DENSITY,
C_MEM_BURST_LEN => C3_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C3_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C3_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C3_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C3_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C3_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C3_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C3_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C3_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C3_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C3_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C3_MEM_DDR3_AUTO_SR,
C_MEM_DDR3_DYN_WRT_ODT => C3_MEM_DDR3_DYN_WRT_ODT,
C_MEM_MOBILE_PA_SR => C3_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C3_MEM_MDDR_ODS,
C_MC_CALIB_BYPASS => C3_MC_CALIB_BYPASS,
C_MC_CALIBRATION_MODE => C3_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C3_MC_CALIBRATION_DELAY,
C_SKIP_IN_TERM_CAL => C3_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C3_SKIP_DYNAMIC_CAL,
C_LDQSP_TAP_DELAY_VAL => C3_LDQSP_TAP_DELAY_VAL,
C_LDQSN_TAP_DELAY_VAL => C3_LDQSN_TAP_DELAY_VAL,
C_UDQSP_TAP_DELAY_VAL => C3_UDQSP_TAP_DELAY_VAL,
C_UDQSN_TAP_DELAY_VAL => C3_UDQSN_TAP_DELAY_VAL,
C_DQ0_TAP_DELAY_VAL => C3_DQ0_TAP_DELAY_VAL,
C_DQ1_TAP_DELAY_VAL => C3_DQ1_TAP_DELAY_VAL,
C_DQ2_TAP_DELAY_VAL => C3_DQ2_TAP_DELAY_VAL,
C_DQ3_TAP_DELAY_VAL => C3_DQ3_TAP_DELAY_VAL,
C_DQ4_TAP_DELAY_VAL => C3_DQ4_TAP_DELAY_VAL,
C_DQ5_TAP_DELAY_VAL => C3_DQ5_TAP_DELAY_VAL,
C_DQ6_TAP_DELAY_VAL => C3_DQ6_TAP_DELAY_VAL,
C_DQ7_TAP_DELAY_VAL => C3_DQ7_TAP_DELAY_VAL,
C_DQ8_TAP_DELAY_VAL => C3_DQ8_TAP_DELAY_VAL,
C_DQ9_TAP_DELAY_VAL => C3_DQ9_TAP_DELAY_VAL,
C_DQ10_TAP_DELAY_VAL => C3_DQ10_TAP_DELAY_VAL,
C_DQ11_TAP_DELAY_VAL => C3_DQ11_TAP_DELAY_VAL,
C_DQ12_TAP_DELAY_VAL => C3_DQ12_TAP_DELAY_VAL,
C_DQ13_TAP_DELAY_VAL => C3_DQ13_TAP_DELAY_VAL,
C_DQ14_TAP_DELAY_VAL => C3_DQ14_TAP_DELAY_VAL,
C_DQ15_TAP_DELAY_VAL => C3_DQ15_TAP_DELAY_VAL
)
port map
(
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udm => mcb3_dram_udm,
calib_done => c3_calib_done,
async_rst => c3_async_rst,
sysclk_2x => c3_sysclk_2x,
sysclk_2x_180 => c3_sysclk_2x_180,
pll_ce_0 => c3_pll_ce_0,
pll_ce_90 => c3_pll_ce_90,
pll_lock => c3_pll_lock,
mcb_drp_clk => c3_mcb_drp_clk,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
p2_cmd_clk => c3_clk0,
p2_cmd_en => c3_p2_cmd_en,
p2_cmd_instr => c3_p2_cmd_instr,
p2_cmd_bl => c3_p2_cmd_bl,
p2_cmd_byte_addr => c3_p2_cmd_byte_addr,
p2_cmd_empty => c3_p2_cmd_empty,
p2_cmd_full => c3_p2_cmd_full,
p2_rd_clk => c3_clk0,
p2_rd_en => c3_p2_rd_en,
p2_rd_data => c3_p2_rd_data,
p2_rd_full => c3_p2_rd_full,
p2_rd_empty => c3_p2_rd_empty,
p2_rd_count => c3_p2_rd_count,
p2_rd_overflow => c3_p2_rd_overflow,
p2_rd_error => c3_p2_rd_error,
p3_cmd_clk => c3_clk0,
p3_cmd_en => c3_p3_cmd_en,
p3_cmd_instr => c3_p3_cmd_instr,
p3_cmd_bl => c3_p3_cmd_bl,
p3_cmd_byte_addr => c3_p3_cmd_byte_addr,
p3_cmd_empty => c3_p3_cmd_empty,
p3_cmd_full => c3_p3_cmd_full,
p3_wr_clk => c3_clk0,
p3_wr_en => c3_p3_wr_en,
p3_wr_mask => c3_p3_wr_mask,
p3_wr_data => c3_p3_wr_data,
p3_wr_full => c3_p3_wr_full,
p3_wr_empty => c3_p3_wr_empty,
p3_wr_count => c3_p3_wr_count,
p3_wr_underrun => c3_p3_wr_underrun,
p3_wr_error => c3_p3_wr_error,
selfrefresh_enter => c3_selfrefresh_enter,
selfrefresh_mode => c3_selfrefresh_mode
);
memc3_tb_top_inst : memc3_tb_top
generic map
(
C_SIMULATION => C3_SIMULATION,
C_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C_MEM_BURST_LEN => C3_MEM_BURST_LEN,
C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS,
C_SMALL_DEVICE => C3_SMALL_DEVICE,
C_p2_BEGIN_ADDRESS => C3_p2_BEGIN_ADDRESS,
C_p2_DATA_MODE => C3_p2_DATA_MODE,
C_p2_END_ADDRESS => C3_p2_END_ADDRESS,
C_p2_PRBS_EADDR_MASK_POS => C3_p2_PRBS_EADDR_MASK_POS,
C_p2_PRBS_SADDR_MASK_POS => C3_p2_PRBS_SADDR_MASK_POS,
C_p3_BEGIN_ADDRESS => C3_p3_BEGIN_ADDRESS,
C_p3_DATA_MODE => C3_p3_DATA_MODE,
C_p3_END_ADDRESS => C3_p3_END_ADDRESS,
C_p3_PRBS_EADDR_MASK_POS => C3_p3_PRBS_EADDR_MASK_POS,
C_p3_PRBS_SADDR_MASK_POS => C3_p3_PRBS_SADDR_MASK_POS
)
port map
(
error => c3_error,
calib_done => c3_calib_done,
clk0 => c3_clk0,
rst0 => c3_rst0,
cmp_error => c3_cmp_error,
cmp_data_valid => c3_cmp_data_valid,
vio_modify_enable => c3_vio_modify_enable,
error_status => c3_error_status,
vio_data_mode_value => c3_vio_data_mode_value,
vio_addr_mode_value => c3_vio_addr_mode_value,
cmp_data => c3_cmp_data,
p2_mcb_cmd_en_o => c3_p2_cmd_en,
p2_mcb_cmd_instr_o => c3_p2_cmd_instr,
p2_mcb_cmd_bl_o => c3_p2_cmd_bl,
p2_mcb_cmd_addr_o => c3_p2_cmd_byte_addr,
p2_mcb_cmd_full_i => c3_p2_cmd_full,
p2_mcb_rd_en_o => c3_p2_rd_en,
p2_mcb_rd_data_i => c3_p2_rd_data,
p2_mcb_rd_empty_i => c3_p2_rd_empty,
p2_mcb_rd_fifo_counts => c3_p2_rd_count,
p3_mcb_cmd_en_o => c3_p3_cmd_en,
p3_mcb_cmd_instr_o => c3_p3_cmd_instr,
p3_mcb_cmd_bl_o => c3_p3_cmd_bl,
p3_mcb_cmd_addr_o => c3_p3_cmd_byte_addr,
p3_mcb_cmd_full_i => c3_p3_cmd_full,
p3_mcb_wr_en_o => c3_p3_wr_en,
p3_mcb_wr_mask_o => c3_p3_wr_mask,
p3_mcb_wr_data_o => c3_p3_wr_data,
p3_mcb_wr_full_i => c3_p3_wr_full,
p3_mcb_wr_fifo_counts => c3_p3_wr_count
);
end arc;
| bsd-2-clause | d27e27e2e3947220cfe7195a551694b6 | 0.459841 | 3.426469 | false | false | false | false |
esar/hdmilight-v2 | fpga/avr/register_file.vhd | 3 | 19,800 | -------------------------------------------------------------------------------
--
-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
--
-- This code is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file named COPYING).
-- If not, see http://www.gnu.org/licenses/.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Module Name: RegisterFile - Behavioral
-- Create Date: 12:43:34 10/28/2009
-- Description: a register file (16 register pairs) of a CPU.
--
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.common.ALL;
entity register_file is
port ( I_CLK : in std_logic;
I_AMOD : in std_logic_vector( 5 downto 0);
I_COND : in std_logic_vector( 3 downto 0);
I_DDDDD : in std_logic_vector( 4 downto 0);
I_DIN : in std_logic_vector(15 downto 0);
I_FLAGS : in std_logic_vector( 7 downto 0);
I_IMM : in std_logic_vector(15 downto 0);
I_RRRR : in std_logic_vector( 4 downto 1);
I_WE_01 : in std_logic;
I_WE_D : in std_logic_vector( 1 downto 0);
I_WE_F : in std_logic;
I_WE_M : in std_logic;
I_WE_XYZS : in std_logic;
Q_ADR : out std_logic_vector(15 downto 0);
Q_CC : out std_logic;
Q_D : out std_logic_vector(15 downto 0);
Q_FLAGS : out std_logic_vector( 7 downto 0);
Q_R : out std_logic_vector(15 downto 0);
Q_S : out std_logic_vector( 7 downto 0);
Q_Z : out std_logic_vector(15 downto 0));
end register_file;
architecture Behavioral of register_file is
component reg_16
port ( I_CLK : in std_logic;
I_D : in std_logic_vector(15 downto 0);
I_WE : in std_logic_vector( 1 downto 0);
Q : out std_logic_vector(15 downto 0));
end component;
signal R_R00 : std_logic_vector(15 downto 0);
signal R_R02 : std_logic_vector(15 downto 0);
signal R_R04 : std_logic_vector(15 downto 0);
signal R_R06 : std_logic_vector(15 downto 0);
signal R_R08 : std_logic_vector(15 downto 0);
signal R_R10 : std_logic_vector(15 downto 0);
signal R_R12 : std_logic_vector(15 downto 0);
signal R_R14 : std_logic_vector(15 downto 0);
signal R_R16 : std_logic_vector(15 downto 0);
signal R_R18 : std_logic_vector(15 downto 0);
signal R_R20 : std_logic_vector(15 downto 0);
signal R_R22 : std_logic_vector(15 downto 0);
signal R_R24 : std_logic_vector(15 downto 0);
signal R_R26 : std_logic_vector(15 downto 0);
signal R_R28 : std_logic_vector(15 downto 0);
signal R_R30 : std_logic_vector(15 downto 0);
signal R_SP : std_logic_vector(15 downto 0); -- stack pointer
component status_reg is
port ( I_CLK : in std_logic;
I_COND : in std_logic_vector ( 3 downto 0);
I_DIN : in std_logic_vector ( 7 downto 0);
I_FLAGS : in std_logic_vector ( 7 downto 0);
I_WE_F : in std_logic;
I_WE_SR : in std_logic;
Q : out std_logic_vector ( 7 downto 0);
Q_CC : out std_logic);
end component;
signal S_FLAGS : std_logic_vector( 7 downto 0);
signal L_ADR : std_logic_vector(15 downto 0);
signal L_BASE : std_logic_vector(15 downto 0);
signal L_DDDD : std_logic_vector( 4 downto 1);
signal L_DSP : std_logic_vector(15 downto 0);
signal L_DX : std_logic_vector(15 downto 0);
signal L_DY : std_logic_vector(15 downto 0);
signal L_DZ : std_logic_vector(15 downto 0);
signal L_PRE : std_logic_vector(15 downto 0);
signal L_POST : std_logic_vector(15 downto 0);
signal L_S : std_logic_vector(15 downto 0);
signal L_WE_SP_AMOD : std_logic;
signal L_WE : std_logic_vector(31 downto 0);
signal L_WE_A : std_logic;
signal L_WE_D : std_logic_vector(31 downto 0);
signal L_WE_D2 : std_logic_vector( 1 downto 0);
signal L_WE_DD : std_logic_vector(31 downto 0);
signal L_WE_IO : std_logic_vector(31 downto 0);
signal L_WE_MISC : std_logic_vector(31 downto 0);
signal L_WE_X : std_logic;
signal L_WE_Y : std_logic;
signal L_WE_Z : std_logic;
signal L_WE_SP : std_logic_vector( 1 downto 0);
signal L_WE_SR : std_logic;
signal L_XYZS : std_logic_vector(15 downto 0);
begin
r00: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE( 1 downto 0), I_D => I_DIN, Q => R_R00);
r02: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE( 3 downto 2), I_D => I_DIN, Q => R_R02);
r04: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE( 5 downto 4), I_D => I_DIN, Q => R_R04);
r06: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE( 7 downto 6), I_D => I_DIN, Q => R_R06);
r08: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE( 9 downto 8), I_D => I_DIN, Q => R_R08);
r10: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE(11 downto 10), I_D => I_DIN, Q => R_R10);
r12: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE(13 downto 12), I_D => I_DIN, Q => R_R12);
r14: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE(15 downto 14), I_D => I_DIN, Q => R_R14);
r16: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE(17 downto 16), I_D => I_DIN, Q => R_R16);
r18: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE(19 downto 18), I_D => I_DIN, Q => R_R18);
r20: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE(21 downto 20), I_D => I_DIN, Q => R_R20);
r22: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE(23 downto 22), I_D => I_DIN, Q => R_R22);
r24: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE(25 downto 24), I_D => I_DIN, Q => R_R24);
r26: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE(27 downto 26), I_D => L_DX, Q => R_R26);
r28: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE(29 downto 28), I_D => L_DY, Q => R_R28);
r30: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE(31 downto 30), I_D => L_DZ, Q => R_R30);
sp: reg_16 port map(I_CLK => I_CLK, I_WE => L_WE_SP, I_D => L_DSP, Q => R_SP);
sr: status_reg
port map( I_CLK => I_CLK,
I_COND => I_COND,
I_DIN => I_DIN(7 downto 0),
I_FLAGS => I_FLAGS,
I_WE_F => I_WE_F,
I_WE_SR => L_WE_SR,
Q => S_FLAGS,
Q_CC => Q_CC);
-- The output of the register selected by L_ADR.
--
process(R_R00, R_R02, R_R04, R_R06, R_R08, R_R10, R_R12, R_R14,
R_R16, R_R18, R_R20, R_R22, R_R24, R_R26, R_R28, R_R30,
R_SP, S_FLAGS, L_ADR(6 downto 1))
begin
case L_ADR(6 downto 1) is
when "000000" => L_S <= R_R00;
when "000001" => L_S <= R_R02;
when "000010" => L_S <= R_R04;
when "000011" => L_S <= R_R06;
when "000100" => L_S <= R_R08;
when "000101" => L_S <= R_R10;
when "000110" => L_S <= R_R12;
when "000111" => L_S <= R_R14;
when "001000" => L_S <= R_R16;
when "001001" => L_S <= R_R18;
when "001010" => L_S <= R_R20;
when "001011" => L_S <= R_R22;
when "001100" => L_S <= R_R24;
when "001101" => L_S <= R_R26;
when "001110" => L_S <= R_R28;
when "001111" => L_S <= R_R30;
when "101110" => L_S <= R_SP ( 7 downto 0) & X"00"; -- SPL
when others => L_S <= S_FLAGS & R_SP (15 downto 8); -- SR/SPH
end case;
end process;
-- The output of the register pair selected by I_DDDDD.
--
process(R_R00, R_R02, R_R04, R_R06, R_R08, R_R10, R_R12, R_R14,
R_R16, R_R18, R_R20, R_R22, R_R24, R_R26, R_R28, R_R30,
I_DDDDD(4 downto 1))
begin
case I_DDDDD(4 downto 1) is
when "0000" => Q_D <= R_R00;
when "0001" => Q_D <= R_R02;
when "0010" => Q_D <= R_R04;
when "0011" => Q_D <= R_R06;
when "0100" => Q_D <= R_R08;
when "0101" => Q_D <= R_R10;
when "0110" => Q_D <= R_R12;
when "0111" => Q_D <= R_R14;
when "1000" => Q_D <= R_R16;
when "1001" => Q_D <= R_R18;
when "1010" => Q_D <= R_R20;
when "1011" => Q_D <= R_R22;
when "1100" => Q_D <= R_R24;
when "1101" => Q_D <= R_R26;
when "1110" => Q_D <= R_R28;
when others => Q_D <= R_R30;
end case;
end process;
-- The output of the register pair selected by I_RRRR.
--
process(R_R00, R_R02, R_R04, R_R06, R_R08, R_R10, R_R12, R_R14,
R_R16, R_R18, R_R20, R_R22, R_R24, R_R26, R_R28, R_R30, I_RRRR)
begin
case I_RRRR is
when "0000" => Q_R <= R_R00;
when "0001" => Q_R <= R_R02;
when "0010" => Q_R <= R_R04;
when "0011" => Q_R <= R_R06;
when "0100" => Q_R <= R_R08;
when "0101" => Q_R <= R_R10;
when "0110" => Q_R <= R_R12;
when "0111" => Q_R <= R_R14;
when "1000" => Q_R <= R_R16;
when "1001" => Q_R <= R_R18;
when "1010" => Q_R <= R_R20;
when "1011" => Q_R <= R_R22;
when "1100" => Q_R <= R_R24;
when "1101" => Q_R <= R_R26;
when "1110" => Q_R <= R_R28;
when others => Q_R <= R_R30;
end case;
end process;
-- the base value of the X/Y/Z/SP register as per I_AMOD.
--
process(I_AMOD(2 downto 0), I_IMM, R_SP, R_R26, R_R28, R_R30)
begin
case I_AMOD(2 downto 0) is
when AS_SP => L_BASE <= R_SP;
when AS_Z => L_BASE <= R_R30;
when AS_Y => L_BASE <= R_R28;
when AS_X => L_BASE <= R_R26;
when AS_IMM => L_BASE <= I_IMM;
when others => L_BASE <= X"0000";
end case;
end process;
-- the value of the X/Y/Z/SP register after a potential PRE-inc/decrement
-- (by 1 or 2) and POST-inc/decrement (by 1 or 2).
--
process(I_AMOD, I_IMM)
begin
case I_AMOD is
when AMOD_Xq | AMOD_Yq | AMOD_Zq =>
L_PRE <= I_IMM; L_POST <= X"0000";
when AMOD_Xi | AMOD_Yi | AMOD_Zi =>
L_PRE <= X"0000"; L_POST <= X"0001";
when AMOD_dX | AMOD_dY | AMOD_dZ =>
L_PRE <= X"FFFF"; L_POST <= X"FFFF";
when AMOD_iSP =>
L_PRE <= X"0001"; L_POST <= X"0001";
when AMOD_iiSP=>
L_PRE <= X"0001"; L_POST <= X"0002";
when AMOD_SPd =>
L_PRE <= X"0000"; L_POST <= X"FFFF";
when AMOD_SPdd=>
L_PRE <= X"FFFF"; L_POST <= X"FFFE";
when others =>
L_PRE <= X"0000"; L_POST <= X"0000";
end case;
end process;
L_XYZS <= L_BASE + L_POST;
L_ADR <= L_BASE + L_PRE;
L_WE_A <= I_WE_M when (L_ADR(15 downto 5) = "00000000000") else '0';
L_WE_SR <= I_WE_M when (L_ADR = X"005F") else '0';
L_WE_SP_AMOD <= I_WE_XYZS when (I_AMOD(2 downto 0) = AS_SP) else '0';
L_WE_SP(1) <= I_WE_M when (L_ADR = X"005E") else L_WE_SP_AMOD;
L_WE_SP(0) <= I_WE_M when (L_ADR = X"005D") else L_WE_SP_AMOD;
L_DX <= L_XYZS when (L_WE_MISC(26) = '1') else I_DIN;
L_DY <= L_XYZS when (L_WE_MISC(28) = '1') else I_DIN;
L_DZ <= L_XYZS when (L_WE_MISC(30) = '1') else I_DIN;
L_DSP <= L_XYZS when (I_AMOD(3 downto 0) = AM_WS) else I_DIN;
-- the WE signals for the differen registers.
--
-- case 1: write to an 8-bit register addressed by DDDDD.
--
-- I_WE_D(0) = '1' and I_DDDDD matches,
--
L_WE_D( 0) <= I_WE_D(0) when (I_DDDDD = "00000") else '0';
L_WE_D( 1) <= I_WE_D(0) when (I_DDDDD = "00001") else '0';
L_WE_D( 2) <= I_WE_D(0) when (I_DDDDD = "00010") else '0';
L_WE_D( 3) <= I_WE_D(0) when (I_DDDDD = "00011") else '0';
L_WE_D( 4) <= I_WE_D(0) when (I_DDDDD = "00100") else '0';
L_WE_D( 5) <= I_WE_D(0) when (I_DDDDD = "00101") else '0';
L_WE_D( 6) <= I_WE_D(0) when (I_DDDDD = "00110") else '0';
L_WE_D( 7) <= I_WE_D(0) when (I_DDDDD = "00111") else '0';
L_WE_D( 8) <= I_WE_D(0) when (I_DDDDD = "01000") else '0';
L_WE_D( 9) <= I_WE_D(0) when (I_DDDDD = "01001") else '0';
L_WE_D(10) <= I_WE_D(0) when (I_DDDDD = "01010") else '0';
L_WE_D(11) <= I_WE_D(0) when (I_DDDDD = "01011") else '0';
L_WE_D(12) <= I_WE_D(0) when (I_DDDDD = "01100") else '0';
L_WE_D(13) <= I_WE_D(0) when (I_DDDDD = "01101") else '0';
L_WE_D(14) <= I_WE_D(0) when (I_DDDDD = "01110") else '0';
L_WE_D(15) <= I_WE_D(0) when (I_DDDDD = "01111") else '0';
L_WE_D(16) <= I_WE_D(0) when (I_DDDDD = "10000") else '0';
L_WE_D(17) <= I_WE_D(0) when (I_DDDDD = "10001") else '0';
L_WE_D(18) <= I_WE_D(0) when (I_DDDDD = "10010") else '0';
L_WE_D(19) <= I_WE_D(0) when (I_DDDDD = "10011") else '0';
L_WE_D(20) <= I_WE_D(0) when (I_DDDDD = "10100") else '0';
L_WE_D(21) <= I_WE_D(0) when (I_DDDDD = "10101") else '0';
L_WE_D(22) <= I_WE_D(0) when (I_DDDDD = "10110") else '0';
L_WE_D(23) <= I_WE_D(0) when (I_DDDDD = "10111") else '0';
L_WE_D(24) <= I_WE_D(0) when (I_DDDDD = "11000") else '0';
L_WE_D(25) <= I_WE_D(0) when (I_DDDDD = "11001") else '0';
L_WE_D(26) <= I_WE_D(0) when (I_DDDDD = "11010") else '0';
L_WE_D(27) <= I_WE_D(0) when (I_DDDDD = "11011") else '0';
L_WE_D(28) <= I_WE_D(0) when (I_DDDDD = "11100") else '0';
L_WE_D(29) <= I_WE_D(0) when (I_DDDDD = "11101") else '0';
L_WE_D(30) <= I_WE_D(0) when (I_DDDDD = "11110") else '0';
L_WE_D(31) <= I_WE_D(0) when (I_DDDDD = "11111") else '0';
--
-- case 2: write to a 16-bit register pair addressed by DDDD.
--
-- I_WE_DD(1) = '1' and L_DDDD matches,
--
L_DDDD <= I_DDDDD(4 downto 1);
L_WE_D2 <= I_WE_D(1) & I_WE_D(1);
L_WE_DD( 1 downto 0) <= L_WE_D2 when (L_DDDD = "0000") else "00";
L_WE_DD( 3 downto 2) <= L_WE_D2 when (L_DDDD = "0001") else "00";
L_WE_DD( 5 downto 4) <= L_WE_D2 when (L_DDDD = "0010") else "00";
L_WE_DD( 7 downto 6) <= L_WE_D2 when (L_DDDD = "0011") else "00";
L_WE_DD( 9 downto 8) <= L_WE_D2 when (L_DDDD = "0100") else "00";
L_WE_DD(11 downto 10) <= L_WE_D2 when (L_DDDD = "0101") else "00";
L_WE_DD(13 downto 12) <= L_WE_D2 when (L_DDDD = "0110") else "00";
L_WE_DD(15 downto 14) <= L_WE_D2 when (L_DDDD = "0111") else "00";
L_WE_DD(17 downto 16) <= L_WE_D2 when (L_DDDD = "1000") else "00";
L_WE_DD(19 downto 18) <= L_WE_D2 when (L_DDDD = "1001") else "00";
L_WE_DD(21 downto 20) <= L_WE_D2 when (L_DDDD = "1010") else "00";
L_WE_DD(23 downto 22) <= L_WE_D2 when (L_DDDD = "1011") else "00";
L_WE_DD(25 downto 24) <= L_WE_D2 when (L_DDDD = "1100") else "00";
L_WE_DD(27 downto 26) <= L_WE_D2 when (L_DDDD = "1101") else "00";
L_WE_DD(29 downto 28) <= L_WE_D2 when (L_DDDD = "1110") else "00";
L_WE_DD(31 downto 30) <= L_WE_D2 when (L_DDDD = "1111") else "00";
--
-- case 3: write to an 8-bit register pair addressed by an I/O address.
--
-- L_WE_A = '1' and L_ADR(4 downto 0) matches
--
L_WE_IO( 0) <= L_WE_A when (L_ADR(4 downto 0) = "00000") else '0';
L_WE_IO( 1) <= L_WE_A when (L_ADR(4 downto 0) = "00001") else '0';
L_WE_IO( 2) <= L_WE_A when (L_ADR(4 downto 0) = "00010") else '0';
L_WE_IO( 3) <= L_WE_A when (L_ADR(4 downto 0) = "00011") else '0';
L_WE_IO( 4) <= L_WE_A when (L_ADR(4 downto 0) = "00100") else '0';
L_WE_IO( 5) <= L_WE_A when (L_ADR(4 downto 0) = "00101") else '0';
L_WE_IO( 6) <= L_WE_A when (L_ADR(4 downto 0) = "00110") else '0';
L_WE_IO( 7) <= L_WE_A when (L_ADR(4 downto 0) = "00111") else '0';
L_WE_IO( 8) <= L_WE_A when (L_ADR(4 downto 0) = "01000") else '0';
L_WE_IO( 9) <= L_WE_A when (L_ADR(4 downto 0) = "01001") else '0';
L_WE_IO(10) <= L_WE_A when (L_ADR(4 downto 0) = "01010") else '0';
L_WE_IO(11) <= L_WE_A when (L_ADR(4 downto 0) = "01011") else '0';
L_WE_IO(12) <= L_WE_A when (L_ADR(4 downto 0) = "01100") else '0';
L_WE_IO(13) <= L_WE_A when (L_ADR(4 downto 0) = "01101") else '0';
L_WE_IO(14) <= L_WE_A when (L_ADR(4 downto 0) = "01110") else '0';
L_WE_IO(15) <= L_WE_A when (L_ADR(4 downto 0) = "01111") else '0';
L_WE_IO(16) <= L_WE_A when (L_ADR(4 downto 0) = "10000") else '0';
L_WE_IO(17) <= L_WE_A when (L_ADR(4 downto 0) = "10001") else '0';
L_WE_IO(18) <= L_WE_A when (L_ADR(4 downto 0) = "10010") else '0';
L_WE_IO(19) <= L_WE_A when (L_ADR(4 downto 0) = "10011") else '0';
L_WE_IO(20) <= L_WE_A when (L_ADR(4 downto 0) = "10100") else '0';
L_WE_IO(21) <= L_WE_A when (L_ADR(4 downto 0) = "10101") else '0';
L_WE_IO(22) <= L_WE_A when (L_ADR(4 downto 0) = "10110") else '0';
L_WE_IO(23) <= L_WE_A when (L_ADR(4 downto 0) = "10111") else '0';
L_WE_IO(24) <= L_WE_A when (L_ADR(4 downto 0) = "11000") else '0';
L_WE_IO(25) <= L_WE_A when (L_ADR(4 downto 0) = "11001") else '0';
L_WE_IO(26) <= L_WE_A when (L_ADR(4 downto 0) = "11010") else '0';
L_WE_IO(27) <= L_WE_A when (L_ADR(4 downto 0) = "11011") else '0';
L_WE_IO(28) <= L_WE_A when (L_ADR(4 downto 0) = "11100") else '0';
L_WE_IO(29) <= L_WE_A when (L_ADR(4 downto 0) = "11101") else '0';
L_WE_IO(30) <= L_WE_A when (L_ADR(4 downto 0) = "11110") else '0';
L_WE_IO(31) <= L_WE_A when (L_ADR(4 downto 0) = "11111") else '0';
-- case 4 special cases.
-- 4a. WE_01 for register pair 0/1 (multiplication opcode).
-- 4b. I_WE_XYZS for X (register pairs 26/27) and I_AMOD matches
-- 4c. I_WE_XYZS for Y (register pairs 28/29) and I_AMOD matches
-- 4d. I_WE_XYZS for Z (register pairs 30/31) and I_AMOD matches
--
L_WE_X <= I_WE_XYZS when (I_AMOD(3 downto 0) = AM_WX) else '0';
L_WE_Y <= I_WE_XYZS when (I_AMOD(3 downto 0) = AM_WY) else '0';
L_WE_Z <= I_WE_XYZS when (I_AMOD(3 downto 0) = AM_WZ) else '0';
L_WE_MISC <= L_WE_Z & L_WE_Z & -- -Z and Z+ address modes r30
L_WE_Y & L_WE_Y & -- -Y and Y+ address modes r28
L_WE_X & L_WE_X & -- -X and X+ address modes r26
X"000000" & -- never r24 - r02
I_WE_01 & I_WE_01; -- multiplication result r00
L_WE <= L_WE_D or L_WE_DD or L_WE_IO or L_WE_MISC;
Q_S <= L_S( 7 downto 0) when (L_ADR(0) = '0') else L_S(15 downto 8);
Q_FLAGS <= S_FLAGS;
Q_Z <= R_R30;
Q_ADR <= L_ADR;
end Behavioral;
| gpl-2.0 | 767bcda5a1e2ea4cccb00edb482fe980 | 0.490354 | 2.635432 | false | false | false | false |
alonho/game_of_life_vhdl | cell_test.vhdl | 2 | 2,111 | entity cell_test is
end cell_test;
architecture arch of cell_test is
component cell
generic (
start_alive : integer range 0 to 1 := 0
);
port (
clock, left, right,
upper_left, upper, upper_right,
lower_left, lower, lower_right : in integer range 0 to 1;
alive : inout integer range 0 to 1 := start_alive
);
end component;
for cell_1: cell use entity work.cell;
signal clock, alive, upper_left, upper, upper_right, left, right,
lower_left, lower, lower_right : integer range 0 to 1;
begin
cell_1: cell port map (
alive => alive, clock => clock, left => left, right => right,
upper_left => upper_left, upper => upper, upper_right => upper_right,
lower_left => lower_left, lower => lower, lower_right => lower_right
);
process
begin
clock <= 1 - clock;
wait for 1 ns;
assert alive = 0
report "cell should start as dead" severity error;
left <= 1;
right <= 1;
clock <= 1 - clock;
wait for 1 ns;
assert alive = 0
report "cell should stay dead with only two neighbors" severity error;
lower <= 1;
clock <= 1 - clock;
wait for 1 ns;
assert alive = 1
report "cell should come to life" severity error;
clock <= 1 - clock;
wait for 1 ns;
assert alive = 1
report "cell should stay alive" severity error;
upper <= 1;
clock <= 1 - clock;
wait for 1 ns;
assert alive = 0
report "cell should die from over-population" severity error;
upper <= 0;
clock <= 1 - clock;
wait for 1 ns;
assert alive = 1
report "cell should come to life" severity error;
lower <= 0;
clock <= 1 - clock;
wait for 1 ns;
assert alive = 1
report "cell should stay alive" severity error;
left <= 0;
clock <= 1 - clock;
wait for 1 ns;
assert alive = 0
report "cell should die from under-population" severity error;
wait;
end process;
end arch;
| bsd-3-clause | 3324cd44f9c6218b2cdcf958731df6d0 | 0.566556 | 4.091085 | false | false | false | false |
Nooxet/embedded_bruteforce | brutus_system/pcores/ready4hood_v1_00_a/hdl/vhdl/controller.vhd | 2 | 5,222 | ----------------------------------------------------------------------------------
-- Engineer: Noxet && Niklas
--
-- Create Date: 14:56:58 09/22/2014
-- Module Name: controller - Behavioral
-- Description:
-- The Brutus system controller
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity controller is
generic (
N : integer := 1
);
port (
clk : in std_logic;
rstn : in std_logic;
i_fsl_data_recv : in std_logic;
i_fsl_hash : in std_logic_vector(127 downto 0);
i_comp_eq : in std_logic; -- check if password was found
i_sg_done : in std_logic; -- string generator done signal
i_sg_string : in std_logic_vector(47 downto 0); -- current potential password
i_md5_done : in std_logic; -- done signal from the main MD5 core
o_passwd_hash : out std_logic_vector(127 downto 0); -- hash from FSL
o_pw_found : out std_logic; -- flag to indicate password found
-- o_pw_nfound : out ---
o_passwd : out std_logic_vector(47 downto 0); -- password string, send to user
o_start_sg_comp : out std_logic; -- start signals to sg and comp
o_start_md5 : out std_logic; -- start signal to MD5 cores
o_halt_sg : out std_logic; -- halt signal to sg
o_demux_sel : out std_logic_vector(N-1 downto 0); --
o_mux_sel : out std_logic_vector(N-1 downto 0) -- select signals to DEMUX/MUX
);
end controller;
architecture Behavioral of controller is
type states is (wait_fsl, calc_md5, wait_md5, comp_md5, send_fsl);
signal state_c, state_n : states;
signal dm_count_c, dm_count_n : unsigned(N-1 downto 0); -- DEMUX selector counter
signal m_count_c, m_count_n : unsigned(N-1 downto 0); -- MUX selector counter
type pw_buff_array is array(N-1 downto 0) of std_logic_vector(47 downto 0);
signal pw_buff_c, pw_buff_n : pw_buff_array;
begin
clk_proc: process(clk)
begin
if rising_edge(clk) then
if rstn = '0' then
state_c <= wait_fsl;
dm_count_c <= (others => '0');
m_count_c <= (others => '0');
pw_buff_c <= (others => (others => '0'));
else
state_c <= state_n;
dm_count_c <= dm_count_n;
m_count_c <= m_count_n;
pw_buff_c <= pw_buff_n;
end if;
end if;
end process;
fsm_proc: process(state_c, i_fsl_data_recv, i_comp_eq, i_sg_done, i_md5_done, i_sg_string, pw_buff_c, m_count_c, dm_count_c)
begin
-- defaults --
o_start_sg_comp <= '0';
o_start_md5 <= '0';
o_halt_sg <= '0';
dm_count_n <= dm_count_c;
m_count_n <= m_count_c;
o_passwd <= (others => '0');
o_pw_found <= '0';
pw_buff_n <= pw_buff_c;
state_n <= state_c;
case state_c is
-- KOLLA IFALL SG ÄR FÄRDIG, ISÅFALL HOPPA TILL /DEV/NULL --
when wait_fsl =>
dm_count_n <= (others => '0');
m_count_n <= (others => '0');
if i_fsl_data_recv = '1' then
state_n <= calc_md5;
o_start_sg_comp <= '1';
end if;
when calc_md5 =>
o_start_md5 <= '1'; -- start MD5 cores
dm_count_n <= dm_count_c + 1;
pw_buff_n(to_integer(dm_count_c)) <= i_sg_string; -- buffer the sg passwords
if dm_count_c = N-1 then -- should be N-1? CHECK THIS, we now
-- halt everything...
dm_count_n <= (others => '0');
o_halt_sg <= '1'; -- halt the sg while crunching MD5 hashes
state_n <= wait_md5;
end if;
-- wait for the main MD5 core to be finished
when wait_md5 =>
o_halt_sg <= '1'; -- halt until done
if i_md5_done = '1' then
state_n <= comp_md5;
end if;
when comp_md5 => -- rename to a better name
-- o_halt_sg <= '1'; -- TEST
m_count_n <= m_count_c + 1;
if i_comp_eq = '1' then
o_passwd <= pw_buff_c(to_integer(m_count_c));
o_pw_found <= '1';
state_n <= wait_fsl; -- back to init state
elsif m_count_c = N-1 then
m_count_n <= (others => '0');
state_n <= calc_md5; -- if pwd not found, calculate next hash
end if;
when others => null;
end case;
end process;
-- pass through signal --
o_passwd_hash <= i_fsl_hash;
o_demux_sel <= std_logic_vector(dm_count_c);
o_mux_sel <= std_logic_vector(m_count_c);
end Behavioral;
| mit | 9ee3e39b500fdf9dc4490105a95b3ba3 | 0.459977 | 3.598897 | false | false | false | false |
freecores/gpib_controller | vhdl/src/wrapper/SettingsReg1.vhd | 1 | 1,993 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: SettingsReg0
-- Date:2011-11-09
-- Author: Andrzej Paluch
--
-- Description ${cursor}
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity SettingsReg1 is
port (
reset : in std_logic;
strobe : in std_logic;
data_in : in std_logic_vector (15 downto 0);
data_out : out std_logic_vector (15 downto 0);
-- gpib
myAddr : out std_logic_vector (4 downto 0);
T1 : out std_logic_vector (7 downto 0)
);
end SettingsReg1;
architecture arch of SettingsReg1 is
signal inner_buf : std_logic_vector (15 downto 0);
begin
inner_buf(15 downto 13) <= "000";
data_out <= inner_buf;
myAddr <= inner_buf(4 downto 0);
T1 <= inner_buf(12 downto 5);
process (reset, strobe) begin
if reset = '1' then
-- default 132*Tclk = 2uS and addr=1
inner_buf(12 downto 0) <= "1000010000001";
elsif rising_edge(strobe) then
inner_buf(12 downto 0) <= data_in(12 downto 0);
end if;
end process;
end arch;
| gpl-3.0 | 419ad984071d6974a9051cc833d0e563 | 0.622679 | 3.704461 | false | false | false | false |
tsotnep/vhdl_soc_audio_mixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/superip_v1_00_a/hdl/vhdl/superip_internal.vhd | 1 | 8,693 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity superip_internal is
port(
-- Outputs
Mux3_BalanceORMux2_Left_out : out std_logic_vector(23 downto 0);
Mux3_BalanceORMux2_Right_out : out std_logic_vector(23 downto 0);
slv_reg26 : out STD_LOGIC_VECTOR(31 downto 0);
slv_reg28 : out STD_LOGIC_VECTOR(31 downto 0);
slv_reg29 : out STD_LOGIC_VECTOR(31 downto 0);
slv_reg30 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg31 : in STD_LOGIC_VECTOR(31 downto 0);
-- Inputs
CLK_48_in : in std_logic;
CLK_100M_in : in std_logic;
Audio_Left_in : in std_logic_vector(23 downto 0);
Audio_Right_in : in std_logic_vector(23 downto 0);
SAMPLE_TRIG : in std_logic;
-- REGISTERS
slv_reg0 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg1 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg2 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg3 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg4 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg5 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg6 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg7 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg8 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg9 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg10 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg11 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg12 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg13 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg14 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg15 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg16 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg17 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg18 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg19 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg20 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg21 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg22 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg23 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg24 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg25 : in STD_LOGIC_VECTOR(31 downto 0);
--register 26 is output, flags go there
slv_reg27 : in STD_LOGIC_VECTOR(31 downto 0)
);
end entity superip_internal;
architecture RTL of superip_internal is
-- Internals
signal Mux3_BalanceORMux2_Left : std_logic_vector(23 downto 0);
signal Mux3_BalanceORMux2_Right : std_logic_vector(23 downto 0);
signal Mux2_FilterORMux1_Left : std_logic_vector(23 downto 0);
signal Mux2_FilterORMux1_Right : std_logic_vector(23 downto 0);
signal Mux1_VolCtrlORAudio_Left_out : std_logic_vector(23 downto 0);
signal Mux1_VolCtrlORAudio_Right_out : std_logic_vector(23 downto 0);
signal Filter_Left_out : std_logic_vector(23 downto 0);
signal Filter_Right_out : std_logic_vector(23 downto 0);
signal OUT_VOLCTRL_L : signed(23 downto 0);
signal OUT_VOLCTRL_R : signed(23 downto 0);
signal Balance_L_OUT : signed(23 downto 0);
signal Balance_R_OUT : signed(23 downto 0);
-- Outputs Register 26
ALIAS VolCtrl_RDY_L : STD_LOGIC is slv_reg26(0);
ALIAS VolCtrl_RDY_R : STD_LOGIC is slv_reg26(1);
ALIAS Filter_ready_out : STD_LOGIC is slv_reg26(2);
ALIAS READY_BAL : STD_LOGIC is slv_reg26(3);
-- Inputs Register 27
ALIAS HP_SW : STD_LOGIC is slv_reg27(0); --1 will enable it
ALIAS BP_SW : STD_LOGIC is slv_reg27(4); --1 will enable it
ALIAS LP_SW : STD_LOGIC is slv_reg27(8); --1 will enable it
ALIAS Reset_in : STD_LOGIC is slv_reg27(16);--1 will reset everything
ALIAS sample_trigger_en : STD_LOGIC is slv_reg27(20);--1 will set filter to wait for SAMPLE_TRIG from audioIP, otherwise, its constantly calculating
ALIAS bus_frames_en : std_logic is slv_reg27(31);--1 will
-- inputs register 25
signal Mux_Select_in : std_logic_vector(2 downto 0);
--slv_reg25(0) -> Mux1:= Volctrl or rawAudio; 0 for Volctrl pass
--slv_reg25(4) -> Mux2:= Filter or Mux1; 0 for Filter pass
--slv_reg25(8) -> mux3:= Balance or Mux2 0 for Balance pass
-- inputs register 24
ALIAS Reset_Filter : STD_LOGIC is slv_reg24(0); --1 will reset filter only, we use this because its unstable
begin
Mux_Select_in <= slv_reg25(8) & slv_reg25(4) & slv_reg25(0);
slv_reg28 <= x"00" & Mux3_BalanceORMux2_Left; --this goes out, and should arrive in mixerboard
slv_reg29 <= x"00" & Mux3_BalanceORMux2_Right; --this goes out, and should arrive in mixerboard
Mux_Frames_or_internal : process(Mux3_BalanceORMux2_Left, Mux3_BalanceORMux2_Right, slv_reg27(31), slv_reg30(23 downto 0), slv_reg31(23 downto 0))
begin
if bus_frames_en = '0' then --tsotne: I changed this, it was 0 before
Mux3_BalanceORMux2_Left_out <= Mux3_BalanceORMux2_Left;
Mux3_BalanceORMux2_Right_out <= Mux3_BalanceORMux2_Right;
else
Mux3_BalanceORMux2_Left_out <= slv_reg30(23 downto 0); --this is input from mixerIP,
Mux3_BalanceORMux2_Right_out <= slv_reg31(23 downto 0);
end if;
end process;
Tester_inst : entity work.Tester
port map(
Audio_Left_in => Audio_Left_in,
Audio_Right_in => Audio_Right_in,
VolCtrl_Left_out_in => std_logic_vector(OUT_VOLCTRL_L),
VolCtrl_Right_out_in => std_logic_vector(OUT_VOLCTRL_R),
Mux1_VolCtrlORAudio_Left_out => Mux1_VolCtrlORAudio_Left_out,
Mux1_VolCtrlORAudio_Right_out => Mux1_VolCtrlORAudio_Right_out,
Filter_Left_out_in => Filter_Left_out,
Filter_Right_out_in => Filter_Right_out,
Mux2_FilterORMux1_Left_out => Mux2_FilterORMux1_Left,
Mux2_FilterORMux1_Right_out => Mux2_FilterORMux1_Right,
Balance_Left_out_in => std_logic_vector(Balance_L_OUT),
Balance_Right_out_in => std_logic_vector(Balance_R_OUT),
Mux3_BalanceORMux2_Left_out => Mux3_BalanceORMux2_Left,
Mux3_BalanceORMux2_Right_out => Mux3_BalanceORMux2_Right,
Mux_Select_in => Mux_Select_in
);
VolCtrl_inst : entity work.VolCtrl
generic map(
INTBIT_WIDTH => 24,
FRACBIT_WIDTH => 8
)
port map(
OUT_VOLCTRL_L => OUT_VOLCTRL_L,
OUT_VOLCTRL_R => OUT_VOLCTRL_R,
OUT_RDY_L => VolCtrl_RDY_L,
OUT_RDY_R => VolCtrl_RDY_R,
IN_SIG_L => signed(Audio_Left_in),
IN_SIG_R => signed(Audio_Right_in),
IN_COEF_L => signed(slv_reg15),
IN_COEF_R => signed(slv_reg16),
RESET => Reset_in,
CLK_48 => CLK_48_in,
CLK_100M => CLK_100M_in
);
filter_Comp : entity work.Filter_Top_Level
port map(
slv_reg0 => slv_reg0,
slv_reg1 => slv_reg1,
slv_reg2 => slv_reg2,
slv_reg3 => slv_reg3,
slv_reg4 => slv_reg4,
slv_reg5 => slv_reg5,
slv_reg6 => slv_reg6,
slv_reg7 => slv_reg7,
slv_reg8 => slv_reg8,
slv_reg9 => slv_reg9,
slv_reg10 => slv_reg10,
slv_reg11 => slv_reg11,
slv_reg12 => slv_reg12,
slv_reg13 => slv_reg13,
slv_reg14 => slv_reg14,
CLK_48 => CLK_48_in,
RST => Reset_Filter,
SAMPLE_TRIG => SAMPLE_TRIG,
sample_trigger_en => sample_trigger_en,
HP_SW => HP_SW,
BP_SW => BP_SW,
LP_SW => LP_SW,
AUDIO_IN_L => Mux1_VolCtrlORAudio_Left_out,
AUDIO_IN_R => Mux1_VolCtrlORAudio_Right_out,
AUDIO_OUT_L => Filter_Left_out,
AUDIO_OUT_R => Filter_Right_out,
FILTER_DONE => Filter_ready_out
);
Balance_inst : entity work.Balance
generic map(
INTBIT_WIDTH => 24,
FRACBIT_WIDTH => 8,
N => 32,
Attenuation_Const => 11
)
port map(
CLK_BAL => CLK_48_in,
RESET_BAL => Reset_in,
POINTER => to_integer(signed(slv_reg17)),
CH_L_IN => signed(Mux2_FilterORMux1_Left),
CH_R_IN => signed(Mux2_FilterORMux1_Right),
CH_L_OUT => Balance_L_OUT,
CH_R_OUT => Balance_R_OUT,
READY_BAL => READY_BAL
);
end architecture RTL;
| mit | 5b44411969f0e46ddef495203af44873 | 0.576901 | 3.063073 | false | false | false | false |
freecores/gpib_controller | vhdl/src/gpib/commandEncoder.vhd | 1 | 4,032 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: if_func_C
-- Date: 23:00:30 10/04/2011
-- Author: Andrzej Paluch
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.utilPkg.all;
entity commandEcoder is
port (
-- data
data : in std_logic_vector (7 downto 0);
-- status byte
status_byte : in std_logic_vector (7 downto 0);
-- PPR command data
ppBitValue : in std_logic;
ppLineNumber : in std_logic_vector (2 downto 0);
-- func states
APRS : in std_logic; -- affirmative poll response state
CACS : in std_logic; -- controller active state (C)
-- commands
ATN : in std_logic;
END_OF : in std_logic;
IDY : in std_logic;
DAC : in std_logic;
RFD : in std_logic;
DAV : in std_logic;
IFC : in std_logic;
REN : in std_logic;
SRQ : in std_logic; -- request for service
DAB : in std_logic;
EOS : in std_logic;
RQS : in std_logic; -- part of STB
STB : in std_logic;
TCT : in std_logic;
PPR : in std_logic;
-------------------------------------------
-- data lines -----------------------------
-------------------------------------------
DO : out std_logic_vector (7 downto 0);
output_valid : out std_logic;
-------------------------------------------
-- control lines --------------------------
-------------------------------------------
-- DAV line
DAV_line : out std_logic;
-- NRFD line
NRFD_line : out std_logic;
-- NDAC line
NDAC_line : out std_logic;
-- ATN line
ATN_line : out std_logic;
-- EOI line
EOI_line : out std_logic;
-- SRQ line
SRQ_line : out std_logic;
-- IFC line
IFC_line : out std_logic;
-- REN line
REN_line : out std_logic
);
end commandEcoder;
architecture arch of commandEcoder is
signal modified_status_byte : std_logic_vector (7 downto 0);
signal PPR_resp : std_logic_vector (7 downto 0);
begin
ATN_line <= (ATN or IDY) and not END_OF;
EOI_line <= END_OF or IDY;
DAV_line <= DAV;
NRFD_line <= not RFD;
NDAC_line <= not DAC;
SRQ_line <= SRQ;
IFC_line <= IFC;
REN_line <= REN;
output_valid <= STB or DAB or EOS or TCT or PPR or CACS;
DO <=
data when DAB='1' or EOS='1' or CACS='1' else
"00001001" when TCT='1' else
PPR_resp when PPR='1' else
modified_status_byte when STB='1' else
"00000000";
-- modifies status byte
process (status_byte, APRS) begin
modified_status_byte <= status_byte;
modified_status_byte(6) <= APRS;
end process;
-- sets PPR response
process (ppBitValue, ppLineNumber) begin
PPR_resp <= "00000000";
case ppLineNumber is
------------------
when "000" =>
PPR_resp(0) <= ppBitValue;
------------------
when "001" =>
PPR_resp(1) <= ppBitValue;
------------------
when "010" =>
PPR_resp(2) <= ppBitValue;
------------------
when "011" =>
PPR_resp(3) <= ppBitValue;
------------------
when "100" =>
PPR_resp(4) <= ppBitValue;
------------------
when "101" =>
PPR_resp(5) <= ppBitValue;
------------------
when "110" =>
PPR_resp(6) <= ppBitValue;
------------------
when others =>
PPR_resp(7) <= ppBitValue;
end case;
end process;
end arch;
| gpl-3.0 | 109dc80a788ce192a697fa6d12f33312 | 0.548859 | 3.46988 | false | false | false | false |
RickvanLoo/Synthesizer | synth.vhd | 1 | 5,714 | LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY synth IS
GENERIC(lut_bit_width : integer := 8;
pa_bit_width : integer := 32
);
PORT (
-- Main FPGA pins
clk : IN std_logic;
reset : IN std_logic;
-- SPI Connection
SCLK : IN std_logic;
SDATA : IN std_logic;
CS : IN std_logic;
-- debug outputs
dig0, dig1 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); -- show key pressed on display
dig2, dig3 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); -- show key pressed on display
-- audio codec in and outputs
init_finish : out std_logic; --lights ledg[0] when init is finished (for debugging)
AUD_MCLK : out std_logic; --audio master clock
AUD_BCLK : in std_logic; -- Digital Audio bit clock
AUD_DACDAT : out std_logic; -- DAC data line
AUD_DACLRCK : in std_logic; -- DAC data left/right select
I2C_SDAT : out std_logic; -- serial interface data line
I2C_SCLK : out std_logic -- serial interface clock
);
END ENTITY synth;
ARCHITECTURE structure OF synth IS
component spi_read IS
PORT (
SCLK : IN std_logic;
CLK : IN std_logic;
RESET : IN std_logic;
SDATA : IN std_logic;
CS : IN std_logic;
dig0, dig1, dig2, dig3 : OUT std_logic_vector(6 DOWNTO 0); -- show key pressed on display dig2 en dig3 (resp high & low).
ADDR, DATA : OUT std_logic_vector(7 downto 0)
);
END component;
COMPONENT input_data_demux IS
PORT(
ADDR, DATA : in std_logic_vector(7 downto 0);
CLK : in std_logic;
RESET : in std_logic;
NOTE_ON, NOTE_OFF: out std_logic_vector(7 downto 0); --Note ON/OFF 0x80(off), 0xFF(on)
WAV_SELECT : out std_logic_vector(7 downto 0)
);
END COMPONENT;
component osc_handler IS
PORT(
CLK : in std_logic;
RESET : in std_logic;
NOTE_ON_OSC : in std_logic_vector(7 downto 0); --Note ON/OFF 0x80(off), 0xFF(on)
NOTE_OFF_OSC : in std_logic_vector(7 downto 0); --Note ON/OFF 0x80(off), 0xFF(on)
NOTE0, NOTE1 : out std_logic_vector(7 downto 0);
ENABLE0, ENABLE1 : out std_logic
);
END component;
COMPONENT DDS IS
GENERIC(lut_bit_width : integer := 8;
pa_bit_width : integer := 32
);
PORT (
clk : IN std_logic;
reset : IN std_logic;
ENABLE : in std_logic;
NOTE_ON_DDS: in std_logic_vector(7 downto 0); --Note ON/OFF 0x80(off), 0xFF(on);
SI_DATA, SQ_DATA, SA_DATA, TR_DATA : OUT std_logic_vector(15 downto 0);
a_clk : OUT std_logic
);
END COMPONENT;
COMPONENT mixer_entity IS
GENERIC(lut_bit_width : integer := 8;
DATA_width: integer := 16;
max_amplitude : integer := 32767;
min_amplitude : integer := -32767
);
PORT(
a_clk : in std_logic;
reset : in std_logic;
DATA_SI_1, DATA_SI_2 : in std_logic_vector(15 downto 0);
DATA_SQ_1, DATA_SQ_2 : in std_logic_vector(15 downto 0);
DATA_SA_1, DATA_SA_2 : in std_logic_vector(15 downto 0);
DATA_TR_1, DATA_TR_2 : in std_logic_vector(15 downto 0);
WAV_SELECT : in std_logic_vector(7 downto 0);
DATA_TO_AI : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT audio_interface IS
PORT (
LDATA, RDATA : IN std_logic_vector(15 downto 0); -- parallel external data inputs
clk, Reset : IN std_logic;
INIT_FINISH : OUT std_logic;
adc_full : OUT std_logic;
data_over : OUT std_logic; -- sample sync pulse
AUD_MCLK : OUT std_logic; -- Codec master clock OUTPUT
AUD_BCLK : IN std_logic; -- Digital Audio bit clock
AUD_ADCDAT : IN std_logic;
AUD_DACDAT : OUT std_logic; -- DAC data line
AUD_DACLRCK : IN std_logic; -- DAC data left/right select
AUD_ADCLRCK : IN std_logic; -- DAC data left/right select
I2C_SDAT : OUT std_logic; -- serial interface data line
I2C_SCLK : OUT std_logic; -- serial interface clock
ADCDATA : OUT std_logic_vector(31 downto 0)
);
END COMPONENT audio_interface;
SIGNAL AUDIO_DATA_OUT : std_logic_vector(15 downto 0);
signal ADDRO, DATAO : std_logic_vector(7 downto 0);
signal NOTE_ONO, NOTE_OFFO : std_logic_vector(7 downto 0); --Note ON/OFF 0x80(off), 0xFF(on)
SIGNAL NOTE0a, NOTE1a : std_logic_vector(7 downto 0);
signal as_clk0, as_clk1 : std_logic;
signal enabl0, enabl1 : std_logic;
SIGNAL WAV_SELECTA : std_logic_vector(7 downto 0);
SIGNAL SI_DATA1, SQ_DATA1, SA_DATA1, TR_DATA1 : std_logic_vector(15 downto 0);
SIGNAL SI_DATA2, SQ_DATA2, SA_DATA2, TR_DATA2 : std_logic_vector(15 downto 0);
BEGIN
spo : spi_read port map(SCLK=>SCLK, CLK=>CLK, RESET=>RESET, SDATA=>SDATA, CS=>CS, dig0=>dig0, dig1=>dig1, dig2=>dig2, dig3=>dig3, ADDR=>ADDRO, DATA=>DATAO);
wall : input_data_demux port map(ADDR=>ADDRO, DATA=>DATAO,CLK=>CLK, RESET=>RESET, NOTE_ON=>NOTE_ONO, NOTE_OFF=>NOTE_OFFO, WAV_SELECT=>WAV_SELECTA);
handl : osc_handler port map(CLK=>CLK, RESET=>RESET, NOTE_ON_OSC=>NOTE_ONO, NOTE_OFF_OSC=>NOTE_OFFO, NOTE0=>NOTE0a, NOTE1=>NOTE1a, ENABLE0=>enabl0, ENABLE1=>enabl1);
osc1: dds port map(clk=>clk, reset=>reset, NOTE_ON_DDS=>NOTE0a, ENABLE=>enabl0, a_clk=>as_clk0, SI_DATA=>SI_DATA1, SQ_DATA=>SQ_DATA1, SA_DATA=>SA_DATA1, TR_DATA=>TR_DATA1);
osc2: dds port map(clk=>clk, reset=>reset, NOTE_ON_DDS=>NOTE1a, ENABLE=>enabl1, a_clk=>as_clk1, SI_DATA=>SI_DATA2, SQ_DATA=>SQ_DATA2, SA_DATA=>SA_DATA2, TR_DATA=>TR_DATA2);
mix: mixer_entity port map(a_clk=>as_clk0, reset=>reset, DATA_SI_1=>SI_DATA1, DATA_SQ_1=>SQ_DATA1, DATA_SA_1=>SA_DATA1, DATA_TR_1=>TR_DATA1, DATA_SI_2=>SI_DATA2,DATA_SQ_2=>SQ_DATA2,DATA_SA_2=>SA_DATA2,DATA_TR_2=>TR_DATA2,WAV_SELECT=>WAV_SELECTA,DATA_TO_AI=>AUDIO_DATA_OUT);
s2a : audio_interface PORT MAP (AUDIO_DATA_OUT,AUDIO_DATA_OUT,clk,reset,INIT_FINISH,OPEN,OPEN,AUD_MCLK,AUD_BCLK,'0',AUD_DACDAT,AUD_DACLRCK,'0',I2C_SDAT,I2C_SCLK,OPEN);
END structure; | mit | 13284ab8c1e112e208b654b67a4bd4d6 | 0.658033 | 2.715779 | false | false | false | false |
esar/hdmilight-v2 | fpga/blockram.vhd | 1 | 1,803 |
-- A parameterized, inferable, true dual-port, dual-clock block RAM in VHDL.
-- Originally from http://danstrother.com/2010/09/11/inferring-rams-in-fpgas/
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity blockram is
generic (
DATA : integer := 72;
ADDR : integer := 10
);
port (
-- Port A
a_clk : in std_logic;
a_en : in std_logic;
a_wr : in std_logic;
a_rst : in std_logic;
a_addr : in std_logic_vector(ADDR-1 downto 0);
a_din : in std_logic_vector(DATA-1 downto 0);
a_dout : out std_logic_vector(DATA-1 downto 0);
-- Port B
b_clk : in std_logic;
b_en : in std_logic;
b_wr : in std_logic;
b_rst : in std_logic;
b_addr : in std_logic_vector(ADDR-1 downto 0);
b_din : in std_logic_vector(DATA-1 downto 0);
b_dout : out std_logic_vector(DATA-1 downto 0)
);
end blockram;
architecture Behavioral of blockram is
-- Shared memory
type mem_type is array ( (2**ADDR)-1 downto 0 ) of std_logic_vector(DATA-1 downto 0);
shared variable mem : mem_type;
begin
-- Port A
process(a_en, a_clk)
begin
if(a_en='1' and a_clk'event and a_clk='1') then
if(a_wr='1') then
mem(conv_integer(a_addr)) := a_din;
end if;
if(a_rst='1') then
a_dout <= (others => '0');
else
a_dout <= mem(conv_integer(a_addr));
end if;
end if;
end process;
-- Port B
process(b_en, b_clk)
begin
if(b_en='1' and b_clk'event and b_clk='1') then
if(b_wr='1') then
mem(conv_integer(b_addr)) := b_din;
end if;
if(b_rst='1') then
b_dout <= (others => '0');
else
b_dout <= mem(conv_integer(b_addr));
end if;
end if;
end process;
end Behavioral; | gpl-2.0 | b48cfb46321110ea4619130618c0a9fd | 0.57127 | 2.843849 | false | false | false | false |
freecores/gpib_controller | vhdl/src/gpib/if_func_PP.vhd | 1 | 4,923 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
-- Author: Andrzej Paluch
--
-- Create Date: 01:04:57 10/03/2011
-- Design Name:
-- Module Name: if_func_PP - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.utilPkg.all;
entity if_func_PP is
port(
-- device inputs
clk : in std_logic; -- clock
-- settings
lpeUsed : std_logic;
fixedPpLine : in std_logic_vector (2 downto 0);
-- local commands
pon : in std_logic; -- power on
lpe : in std_logic; -- local poll enable
ist : in std_logic; -- individual status
-- state inputs
ACDS : in std_logic; -- accept data state
LADS : in std_logic; -- listener address state (L or LE)
-- data input
dio_data : in std_logic_vector(3 downto 0); -- byte from data lines
-- remote command inputs
IDY : in std_logic; -- identify
PPE : in std_logic; -- parallel poll enable
PPD : in std_logic; -- parallel poll disable
PPC : in std_logic; -- parallel poll configure
PPU : in std_logic; -- parallel poll unconfigure
PCG : in std_logic; -- primary command group
-- remote command outputs
PPR : out std_logic; -- paralel poll response
-- PPR command data
ppBitValue : out std_logic; -- bit value
ppLineNumber : out std_logic_vector (2 downto 0);
-- reported states
PPAS : out std_logic -- parallel poll active state
);
end if_func_PP;
architecture Behavioral of if_func_PP is
-- states
type PP_STATE_1 is (
-- parallel poll idle state
ST_PPIS,
-- parallel poll standby state
ST_PPSS,
-- parallel poll active state
ST_PPAS
);
-- states
type PP_STATE_2 is (
-- parallel poll unaddressed to configure state
ST_PUCS,
-- parallel poll addressed to configure state
ST_PACS
);
-- current state
signal current_state_1 : PP_STATE_1;
signal current_state_2 : PP_STATE_2;
-- predicates
signal pred1, pred2, pred3, pred4, pred5 : boolean;
-- memorized PP metadata
signal S : std_logic;
signal lineAddr : std_logic_vector (2 downto 0);
begin
-- state machine process - PP_STATE_1
process(pon, clk) begin
if pon = '1' then
current_state_1 <= ST_PPIS;
elsif rising_edge(clk) then
case current_state_1 is
------------------
when ST_PPIS =>
if pred1 then
S <= dio_data(3);
lineAddr <= dio_data(2 downto 0);
current_state_1 <= ST_PPSS;
end if;
------------------
when ST_PPSS =>
if pred3 then
current_state_1 <= ST_PPAS;
elsif pred2 then
current_state_1 <= ST_PPIS;
end if;
------------------
when ST_PPAS =>
if not pred3 then
current_state_1 <= ST_PPSS;
end if;
------------------
when others =>
current_state_1 <= ST_PPIS;
end case;
end if;
end process;
-- state machine process - PP_STATE_2
process(pon, clk) begin
if pon = '1' then
current_state_2 <= ST_PUCS;
elsif rising_edge(clk) then
case current_state_2 is
------------------
when ST_PUCS =>
if pred4 then
current_state_2 <= ST_PACS;
end if;
------------------
when ST_PACS =>
if pred5 then
current_state_2 <= ST_PUCS;
end if;
------------------
when others =>
current_state_2 <= ST_PUCS;
end case;
end if;
end process;
ppBitValue <= (not S xor ist) when lpeUsed='0' else ist;
ppLineNumber <= lineAddr when lpeUsed='0' else fixedPpLine;
PPR <= to_stdl(current_state_1 = ST_PPAS);
PPAS <= to_stdl(current_state_1 = ST_PPAS);
-- predicates
with lpeUsed select
pred1 <=
is_1(lpe) when '1',
PPE='1' and current_state_2=ST_PACS and ACDS='1' when others;
with lpeUsed select
pred2 <=
is_1(not lpe) when '1',
((PPD='1' and current_state_2=ST_PACS) or PPU='1') and ACDS='1'
when others;
pred3 <= IDY='1';
pred4 <= PPC='1' and LADS='1' and ACDS='1';
pred5 <= PCG='1' and PPC='0' and ACDS='1';
end Behavioral;
| gpl-3.0 | d81a4ed5e6524666e5b859f044eff51d | 0.601869 | 3.308468 | false | false | false | false |
whitef0x0/EECE353-Lab4 | datapath.vhd | 1 | 2,969 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
LIBRARY WORK;
USE WORK.ALL;
ENTITY datapath IS
PORT (
clock : IN STD_LOGIC;
resetb : IN STD_LOGIC;
RESETX, RESETY, incr_y, incr_x, initl, drawl : IN STD_LOGIC;
x : OUT STD_LOGIC_VECTOR(7 downto 0); -- x0
y : OUT STD_LOGIC_VECTOR(6 downto 0);
xin : IN STD_LOGIC_VECTOR(7 downto 0); -- x1
yin : IN STD_LOGIC_VECTOR(6 downto 0);
xdone, ydone, ldone : OUT STD_LOGIC
);
END datapath;
ARCHITECTURE mixed OF datapath IS
BEGIN
PROCESS(clock, resetb)
VARIABLE x_tmp : unsigned(7 downto 0) := "00000000";
VARIABLE y_tmp : unsigned(6 downto 0) := "0000000";
VARIABLE dx : signed(8 downto 0);
VARIABLE dy : signed(7 downto 0);
VARIABLE x0 : unsigned(7 downto 0) := "01010000"; -- 80
VARIABLE y0 : unsigned(6 downto 0) := "0111100"; -- 60
VARIABLE x1 : unsigned(7 downto 0) := "01010000";
VARIABLE y1 : unsigned(6 downto 0) := "0111100";
VARIABLE sx : signed(1 downto 0);
VARIABLE sy : signed(1 downto 0);
VARIABLE error : signed(8 downto 0);
VARIABLE e2 : signed(9 downto 0);
BEGIN
IF (resetb = '0') THEN
y_tmp := "0000000";
x_tmp := "00000000";
x0 := "01010000"; -- 80
y0 := "0111100"; -- 60
x1 := "01010000"; -- 80
y1 := "0111100"; -- 60
ELSIF rising_edge(clock) THEN
--initialize line
IF (initl = '1') THEN
x0 := x1; -- 80
y0 := y1; -- 60
x1 := unsigned(xin); -- destination
y1 := unsigned(yin);
dx := to_signed(abs(to_integer(x1) - to_integer(x0)), 9);
dy := to_signed(abs(to_integer(y1) - to_integer(y0)), 8);
IF (x0 < x1) THEN
sx := to_signed(1, 2);
ELSE
sx := to_signed(-1, 2);
END IF;
IF (y0 < y1) THEN
sy := to_signed(1, 2);
ELSE
sy := to_signed(-1, 2);
END IF;
error := to_signed(to_integer(dx) - to_integer(dy), 9);
ldone <= '0';
--draw line loop
ELSIF (drawl = '1') THEN
x <= STD_LOGIC_VECTOR(x0);
y <= STD_LOGIC_VECTOR(y0);
-- Exit loop if we are at destination point
IF (x0 = x1) THEN
IF(y0 = y1) THEN
ldone <= '1';
END IF;
ELSE
e2 := signed(2*error)(9 downto 0);
IF (e2 > -dy) THEN
error := error - dy;
x0 := unsigned(signed(x0) + sx);
END IF;
IF (e2 < dx) THEN
error := error + dx;
y0 := unsigned(signed(y0) + sy);
END IF;
END IF;
--clear screen
ELSE
IF (RESETY = '1') THEN
y_tmp := "0000000";
ELSIF (INCR_Y = '1') THEN
y_tmp := y_tmp + 1;
IF (y_tmp = 119) THEN
YDONE <= '1';
ELSE
YDONE <= '0';
END IF;
END IF;
Y <= std_logic_vector(y_tmp);
IF (RESETX = '1') THEN
x_tmp := "00000000";
ELSIF (INCR_X = '1') THEN
x_tmp := x_tmp + 1;
IF (x_tmp = 159) THEN
XDONE <= '1';
ELSE
XDONE <= '0';
END IF;
END IF;
X <= std_logic_vector(x_tmp);
END IF;
END IF;
END PROCESS;
END mixed;
| mit | 5bb295af9008a9284d8c840786cd0af6 | 0.543617 | 2.741459 | false | false | false | false |
FelixWinterstein/Vivado-KMeans | filtering_algorithm_HLS/rtl/source/filtering_algorithm_wrapper.vhd | 1 | 9,161 | ----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- filtering_algorithm_wrapper - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity filtering_algorithm_wrapper is
port (
ap_clk : in std_logic;
ap_rst : in std_logic;
ap_start : in std_logic;
ap_done : out std_logic;
ap_idle : out std_logic;
node_data_dout : in std_logic_vector (319 downto 0);
node_data_empty_n : in std_logic;
node_data_read : out std_logic;
node_address_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
node_address_V_empty_n : IN STD_LOGIC;
node_address_V_read : OUT STD_LOGIC;
cntr_pos_init_value_V_dout : in std_logic_vector (47 downto 0);
cntr_pos_init_value_V_empty_n : in std_logic;
cntr_pos_init_value_V_read : out std_logic;
n_V : in std_logic_vector (15 downto 0);
k_V : in std_logic_vector (7 downto 0);
root_V_dout : in std_logic_vector (15 downto 0);
root_V_empty_n : in std_logic;
root_V_read : out std_logic;
distortion_out_V_din : out std_logic_vector (31 downto 0);
distortion_out_V_full_n : in std_logic;
distortion_out_V_write : out std_logic;
clusters_out_value_V_din : out std_logic_vector (47 downto 0);
clusters_out_value_V_full_n : in std_logic;
clusters_out_value_V_write : out std_logic
);
end filtering_algorithm_wrapper;
architecture Behavioral of filtering_algorithm_wrapper is
component filtering_algorithm_top is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
node_data_dout : IN STD_LOGIC_VECTOR (319 downto 0);
node_data_empty_n : IN STD_LOGIC;
node_data_read : OUT STD_LOGIC;
node_address_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
node_address_V_empty_n : IN STD_LOGIC;
node_address_V_read : OUT STD_LOGIC;
cntr_pos_init_value_V_dout : IN STD_LOGIC_VECTOR (47 downto 0);
cntr_pos_init_value_V_empty_n : IN STD_LOGIC;
cntr_pos_init_value_V_read : OUT STD_LOGIC;
n_V : IN STD_LOGIC_VECTOR (15 downto 0);
k_V : IN STD_LOGIC_VECTOR (7 downto 0);
root_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
root_V_empty_n : IN STD_LOGIC;
root_V_read : OUT STD_LOGIC;
distortion_out_V_din : OUT STD_LOGIC_VECTOR (31 downto 0);
distortion_out_V_full_n : IN STD_LOGIC;
distortion_out_V_write : OUT STD_LOGIC;
clusters_out_value_V_din : OUT STD_LOGIC_VECTOR (47 downto 0);
clusters_out_value_V_full_n : IN STD_LOGIC;
clusters_out_value_V_write : OUT STD_LOGIC
);
end component;
signal tmp_clk : std_logic;
signal ap_rst_reg : std_logic;
signal ap_start_reg : std_logic;
signal ap_done_tmp : std_logic;
signal ap_done_reg : std_logic;
signal ap_idle_tmp : std_logic;
signal ap_idle_reg : std_logic;
signal node_data_dout_reg : std_logic_vector (319 downto 0);
signal node_data_empty_n_reg : std_logic;
signal node_data_read_tmp : std_logic;
signal node_data_read_reg : std_logic;
signal node_address_V_dout_reg : std_logic_vector (15 downto 0);
signal node_address_V_empty_n_reg : std_logic;
signal node_address_V_read_tmp : std_logic;
signal node_address_V_read_reg : std_logic;
signal cntr_pos_init_value_V_dout_reg : std_logic_vector (47 downto 0);
signal cntr_pos_init_value_V_empty_n_reg : std_logic;
signal cntr_pos_init_value_V_read_tmp : std_logic;
signal cntr_pos_init_value_V_read_reg : std_logic;
signal n_V_reg : std_logic_vector (15 downto 0);
signal k_V_reg : std_logic_vector (7 downto 0);
signal root_V_reg : std_logic_vector (15 downto 0);
signal root_V_dout_reg : std_logic_vector (15 downto 0);
signal root_V_empty_n_reg : std_logic;
signal root_V_read_tmp : std_logic;
signal root_V_read_reg : std_logic;
signal distortion_out_V_din_tmp : std_logic_vector (31 downto 0);
signal distortion_out_V_din_reg : std_logic_vector (31 downto 0);
signal distortion_out_V_full_n_reg : std_logic;
signal distortion_out_V_write_tmp : std_logic;
signal distortion_out_V_write_reg : std_logic;
signal clusters_out_value_V_din_tmp : std_logic_vector (47 downto 0);
signal clusters_out_value_V_din_reg : std_logic_vector (47 downto 0);
signal clusters_out_value_V_full_n_reg : std_logic;
signal clusters_out_value_V_write_tmp : std_logic;
signal clusters_out_value_V_write_reg : std_logic;
begin
ClkBuffer: IBUFG
port map (
I => ap_clk,
O => tmp_clk
);
input_reg : process(tmp_clk)
begin
if rising_edge(tmp_clk) then
ap_rst_reg <= ap_rst;
ap_start_reg <= ap_start;
node_data_dout_reg <= node_data_dout;
node_data_empty_n_reg <= node_data_empty_n;
node_address_V_dout_reg <= node_address_V_dout;
node_address_V_empty_n_reg <= node_address_V_empty_n;
cntr_pos_init_value_V_dout_reg <= cntr_pos_init_value_V_dout;
cntr_pos_init_value_V_empty_n_reg <= cntr_pos_init_value_V_empty_n;
n_V_reg <= n_V;
k_V_reg <= k_V;
root_V_dout_reg <= root_V_dout;
root_V_empty_n_reg <= root_V_empty_n;
distortion_out_V_full_n_reg <= distortion_out_V_full_n;
clusters_out_value_V_full_n_reg <= clusters_out_value_V_full_n;
end if;
end process input_reg;
filtering_alogrithm_top_inst : filtering_algorithm_top
port map(
ap_clk => tmp_clk,
ap_rst => ap_rst_reg,
ap_start => ap_start_reg,
ap_done => ap_done_tmp,
ap_idle => ap_idle_tmp,
node_data_dout => node_data_dout_reg,
node_data_empty_n => node_data_empty_n_reg,
node_data_read => node_data_read_tmp,
node_address_V_dout => node_address_V_dout_reg,
node_address_V_empty_n => node_address_V_empty_n_reg,
node_address_V_read => node_address_V_read_tmp,
cntr_pos_init_value_V_dout => cntr_pos_init_value_V_dout_reg,
cntr_pos_init_value_V_empty_n => cntr_pos_init_value_V_empty_n_reg,
cntr_pos_init_value_V_read => cntr_pos_init_value_V_read_tmp,
n_V => n_V_reg,
k_V => k_V_reg,
root_V_dout => root_V_dout_reg,
root_V_empty_n => root_V_empty_n_reg,
root_V_read => root_V_read_tmp,
distortion_out_V_din => distortion_out_V_din_tmp,
distortion_out_V_full_n => distortion_out_V_full_n_reg,
distortion_out_V_write => distortion_out_V_write_tmp,
clusters_out_value_V_din => clusters_out_value_V_din_tmp,
clusters_out_value_V_full_n => clusters_out_value_V_full_n_reg,
clusters_out_value_V_write => clusters_out_value_V_write_tmp
);
output_reg : process(tmp_clk)
begin
if rising_edge(tmp_clk) then
ap_done_reg <= ap_done_tmp;
ap_idle_reg <= ap_idle_tmp;
node_data_read_reg <= node_data_read_tmp;
node_address_V_read_reg <= node_address_V_read_tmp;
root_V_read_reg <= root_V_read_tmp;
cntr_pos_init_value_V_read_reg <= cntr_pos_init_value_V_read_tmp;
distortion_out_V_din_reg <= distortion_out_V_din_tmp;
distortion_out_V_write_reg <= distortion_out_V_write_tmp;
clusters_out_value_V_din_reg <= clusters_out_value_V_din_tmp;
clusters_out_value_V_write_reg <= clusters_out_value_V_write_tmp;
end if;
end process output_reg;
ap_done <= ap_done_reg;
ap_idle <= ap_idle_reg;
node_data_read <= node_data_read_reg;
node_address_V_read <= node_address_V_read_reg;
cntr_pos_init_value_V_read <= cntr_pos_init_value_V_read_reg;
root_V_read <= root_V_read_reg;
distortion_out_V_din <= distortion_out_V_din_reg;
distortion_out_V_write <= distortion_out_V_write_reg;
clusters_out_value_V_din <= clusters_out_value_V_din_reg;
clusters_out_value_V_write <= clusters_out_value_V_write_reg;
end Behavioral;
| bsd-3-clause | b0c763ce1b94731fbae6f404a1bfe0f4 | 0.574282 | 3.28469 | false | false | false | false |
esar/hdmilight-v2 | fpga/colourTransformerConfigRam.vhd | 1 | 3,106 | ----------------------------------------------------------------------------------
--
-- Copyright (C) 2014 Stephen Robinson
--
-- This file is part of HDMI-Light
--
-- HDMI-Light is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- HDMI-Light is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file names COPING).
-- If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity colourTransformerConfigRam is
port (
-- Port A
a_clk : in std_logic;
a_wr : in std_logic;
a_addr : in std_logic_vector(11 downto 0);
a_din : in std_logic_vector(7 downto 0);
a_dout : out std_logic_vector(7 downto 0);
-- Port B
b_clk : in std_logic;
b_addr : in std_logic_vector(8 downto 0);
b_data : out std_logic_vector(63 downto 0)
);
end colourTransformerConfigRam;
architecture Behavioral of colourTransformerConfigRam is
type mem_t is array (0 to 2047) of std_logic_vector(7 downto 0);
shared variable memOdd1 : mem_t;
shared variable memEven1 : mem_t;
signal a_doutOdd1 : std_logic_vector(7 downto 0);
signal a_doutEven1 : std_logic_vector(7 downto 0);
begin
-- Port A
process(a_clk)
begin
if(rising_edge(a_clk)) then
if(a_addr(0) = '0') then
if(a_wr = '1') then
memOdd1(conv_integer(a_addr(11 downto 1))) := a_din;
end if;
end if;
a_doutOdd1 <= memOdd1(conv_integer(a_addr(11 downto 1)));
end if;
end process;
process(a_clk)
begin
if(rising_edge(a_clk)) then
if(a_addr(0) = '1') then
if(a_wr = '1') then
memEven1(conv_integer(a_addr(11 downto 1))) := a_din;
end if;
end if;
a_doutEven1 <= memEven1(conv_integer(a_addr(11 downto 1)));
end if;
end process;
a_dout <= a_doutOdd1 when a_addr(0) = '0' else a_doutEven1;
-- Port B
process(b_clk)
begin
if(rising_edge(b_clk)) then
b_data( 7 downto 0) <= memOdd1(conv_integer(b_addr(8 downto 0) & "00"));
b_data(23 downto 16) <= memOdd1(conv_integer(b_addr(8 downto 0) & "01"));
b_data(39 downto 32) <= memOdd1(conv_integer(b_addr(8 downto 0) & "10"));
b_data(55 downto 48) <= memOdd1(conv_integer(b_addr(8 downto 0) & "11"));
end if;
end process;
process(b_clk)
begin
if(rising_edge(b_clk)) then
b_data(15 downto 8) <= memEven1(conv_integer(b_addr(8 downto 0) & "00"));
b_data(31 downto 24) <= memEven1(conv_integer(b_addr(8 downto 0) & "01"));
b_data(47 downto 40) <= memEven1(conv_integer(b_addr(8 downto 0) & "10"));
b_data(63 downto 56) <= memEven1(conv_integer(b_addr(8 downto 0) & "11"));
end if;
end process;
end Behavioral;
| gpl-2.0 | 544c9a0749ebb8730e3812a256311c6f | 0.63812 | 2.952471 | false | false | false | false |
esar/hdmilight-v2 | fpga/avr/cpu_core.vhd | 1 | 10,158 | -------------------------------------------------------------------------------
--
-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
--
-- This code is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file named COPYING).
-- If not, see http://www.gnu.org/licenses/.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Module Name: cpu_core - Behavioral
-- Create Date: 13:51:24 11/07/2009
-- Description: the instruction set implementation of a CPU.
--
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cpu_core is
port ( I_CLK : in std_logic;
I_CE : in std_logic;
I_CLR : in std_logic;
I_INTVEC : in std_logic_vector( 5 downto 0);
I_DIN : in std_logic_vector(15 downto 0);
Q_OPC : out std_logic_vector(15 downto 0);
Q_PC : out std_logic_vector(15 downto 0);
Q_DOUT : out std_logic_vector(15 downto 0);
Q_ADR : out std_logic_vector(15 downto 0);
Q_RD_IO : out std_logic;
Q_WE_IO : out std_logic;
Q_WE_SRAM : out std_logic_vector(1 downto 0));
end cpu_core;
architecture Behavioral of cpu_core is
component opc_fetch
port( I_CLK : in std_logic;
I_CE : in std_logic;
I_CLR : in std_logic;
I_INTVEC : in std_logic_vector( 5 downto 0);
I_NEW_PC : in std_logic_vector(15 downto 0);
I_LOAD_PC : in std_logic;
I_PM_ADR : in std_logic_vector(15 downto 0);
I_SKIP : in std_logic;
Q_OPC : out std_logic_vector(31 downto 0);
Q_PC : out std_logic_vector(15 downto 0);
Q_PM_DOUT : out std_logic_vector( 7 downto 0);
Q_T0 : out std_logic);
end component;
signal F_PC : std_logic_vector(15 downto 0);
signal F_OPC : std_logic_vector(31 downto 0);
signal F_PM_DOUT : std_logic_vector( 7 downto 0);
signal F_T0 : std_logic;
component opc_deco is
port ( I_CLK : in std_logic;
I_CE : in std_logic;
I_OPC : in std_logic_vector(31 downto 0);
I_PC : in std_logic_vector(15 downto 0);
I_T0 : in std_logic;
Q_ALU_OP : out std_logic_vector( 4 downto 0);
Q_AMOD : out std_logic_vector( 5 downto 0);
Q_BIT : out std_logic_vector( 3 downto 0);
Q_DDDDD : out std_logic_vector( 4 downto 0);
Q_IMM : out std_logic_vector(15 downto 0);
Q_JADR : out std_logic_vector(15 downto 0);
Q_OPC : out std_logic_vector(15 downto 0);
Q_PC : out std_logic_vector(15 downto 0);
Q_PC_OP : out std_logic_vector( 2 downto 0);
Q_PMS : out std_logic; -- program memory select
Q_RD_M : out std_logic;
Q_RRRRR : out std_logic_vector( 4 downto 0);
Q_RSEL : out std_logic_vector( 1 downto 0);
Q_WE_01 : out std_logic;
Q_WE_D : out std_logic_vector( 1 downto 0);
Q_WE_F : out std_logic;
Q_WE_M : out std_logic_vector( 1 downto 0);
Q_WE_XYZS : out std_logic);
end component;
signal D_ALU_OP : std_logic_vector( 4 downto 0);
signal D_AMOD : std_logic_vector( 5 downto 0);
signal D_BIT : std_logic_vector( 3 downto 0);
signal D_DDDDD : std_logic_vector( 4 downto 0);
signal D_IMM : std_logic_vector(15 downto 0);
signal D_JADR : std_logic_vector(15 downto 0);
signal D_OPC : std_logic_vector(15 downto 0);
signal D_PC : std_logic_vector(15 downto 0);
signal D_PC_OP : std_logic_vector(2 downto 0);
signal D_PMS : std_logic;
signal D_RD_M : std_logic;
signal D_RRRRR : std_logic_vector( 4 downto 0);
signal D_RSEL : std_logic_vector( 1 downto 0);
signal D_WE_01 : std_logic;
signal D_WE_D : std_logic_vector( 1 downto 0);
signal D_WE_F : std_logic;
signal D_WE_M : std_logic_vector( 1 downto 0);
signal D_WE_XYZS : std_logic;
component data_path
port( I_CLK : in std_logic;
I_CE : in std_logic;
I_ALU_OP : in std_logic_vector( 4 downto 0);
I_AMOD : in std_logic_vector( 5 downto 0);
I_BIT : in std_logic_vector( 3 downto 0);
I_DDDDD : in std_logic_vector( 4 downto 0);
I_DIN : in std_logic_vector(15 downto 0);
I_IMM : in std_logic_vector(15 downto 0);
I_JADR : in std_logic_vector(15 downto 0);
I_PC_OP : in std_logic_vector( 2 downto 0);
I_OPC : in std_logic_vector(15 downto 0);
I_PC : in std_logic_vector(15 downto 0);
I_PMS : in std_logic; -- program memory select
I_RD_M : in std_logic;
I_RRRRR : in std_logic_vector( 4 downto 0);
I_RSEL : in std_logic_vector( 1 downto 0);
I_WE_01 : in std_logic;
I_WE_D : in std_logic_vector( 1 downto 0);
I_WE_F : in std_logic;
I_WE_M : in std_logic_vector( 1 downto 0);
I_WE_XYZS : in std_logic;
Q_ADR : out std_logic_vector(15 downto 0);
Q_DOUT : out std_logic_vector(15 downto 0);
Q_INT_ENA : out std_logic;
Q_LOAD_PC : out std_logic;
Q_NEW_PC : out std_logic_vector(15 downto 0);
Q_OPC : out std_logic_vector(15 downto 0);
Q_PC : out std_logic_vector(15 downto 0);
Q_RD_IO : out std_logic;
Q_SKIP : out std_logic;
Q_WE_IO : out std_logic;
Q_WE_SRAM : out std_logic_vector(1 downto 0));
end component;
signal R_INT_ENA : std_logic;
signal R_NEW_PC : std_logic_vector(15 downto 0);
signal R_LOAD_PC : std_logic;
signal R_SKIP : std_logic;
signal R_ADR : std_logic_vector(15 downto 0);
-- local signals
--
signal L_DIN : std_logic_vector(15 downto 0);
signal L_INTVEC_5 : std_logic;
begin
opcf : opc_fetch
port map( I_CLK => I_CLK,
I_CE => I_CE,
I_CLR => I_CLR,
I_INTVEC(5) => L_INTVEC_5,
I_INTVEC(4 downto 0) => I_INTVEC(4 downto 0),
I_LOAD_PC => R_LOAD_PC,
I_NEW_PC => R_NEW_PC,
I_PM_ADR => R_ADR,
I_SKIP => R_SKIP,
Q_PC => F_PC,
Q_OPC => F_OPC,
Q_T0 => F_T0,
Q_PM_DOUT => F_PM_DOUT);
odec : opc_deco
port map( I_CLK => I_CLK,
I_CE => I_CE,
I_OPC => F_OPC,
I_PC => F_PC,
I_T0 => F_T0,
Q_ALU_OP => D_ALU_OP,
Q_AMOD => D_AMOD,
Q_BIT => D_BIT,
Q_DDDDD => D_DDDDD,
Q_IMM => D_IMM,
Q_JADR => D_JADR,
Q_OPC => D_OPC,
Q_PC => D_PC,
Q_PC_OP => D_PC_OP,
Q_PMS => D_PMS,
Q_RD_M => D_RD_M,
Q_RRRRR => D_RRRRR,
Q_RSEL => D_RSEL,
Q_WE_01 => D_WE_01,
Q_WE_D => D_WE_D,
Q_WE_F => D_WE_F,
Q_WE_M => D_WE_M,
Q_WE_XYZS => D_WE_XYZS);
dpath : data_path
port map( I_CLK => I_CLK,
I_CE => I_CE,
I_ALU_OP => D_ALU_OP,
I_AMOD => D_AMOD,
I_BIT => D_BIT,
I_DDDDD => D_DDDDD,
I_DIN => L_DIN,
I_IMM => D_IMM,
I_JADR => D_JADR,
I_OPC => D_OPC,
I_PC => D_PC,
I_PC_OP => D_PC_OP,
I_PMS => D_PMS,
I_RD_M => D_RD_M,
I_RRRRR => D_RRRRR,
I_RSEL => D_RSEL,
I_WE_01 => D_WE_01,
I_WE_D => D_WE_D,
I_WE_F => D_WE_F,
I_WE_M => D_WE_M,
I_WE_XYZS => D_WE_XYZS,
Q_ADR => R_ADR,
Q_DOUT => Q_DOUT,
Q_INT_ENA => R_INT_ENA,
Q_NEW_PC => R_NEW_PC,
Q_OPC => Q_OPC,
Q_PC => Q_PC,
Q_LOAD_PC => R_LOAD_PC,
Q_RD_IO => Q_RD_IO,
Q_SKIP => R_SKIP,
Q_WE_IO => Q_WE_IO,
Q_WE_SRAM => Q_WE_SRAM);
L_DIN <= "00000000" & F_PM_DOUT when (D_PMS = '1') else I_DIN;
L_INTVEC_5 <= I_INTVEC(5) and R_INT_ENA;
Q_ADR <= R_ADR;
end Behavioral;
| gpl-2.0 | 7aeb4938a6eba0a72b1243830e3e9582 | 0.438472 | 3.409869 | false | false | false | false |
freecores/gpib_controller | vhdl/src/gpib_helper/Fifo8b.vhd | 1 | 6,169 | --------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: Fifo8b
-- Date:2011-11-28
-- Author: Andrzej Paluch
--
-- Description ${cursor}
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.utilPkg.all;
use work.helperComponents.all;
entity Fifo8b is
generic (
MAX_ADDR_BIT_NUM : integer := 10
);
port (
reset : in std_logic;
clk : in std_logic;
-------------- fifo --------------------
bytesAvailable : out std_logic;
availableBytesCount : out std_logic_vector(MAX_ADDR_BIT_NUM downto 0);
bufferFull : out std_logic;
resetFifo : in std_logic;
----------------------------------------
data_in : in std_logic_vector(7 downto 0);
ready_to_write :out std_logic;
strobe_write : in std_logic;
----------------------------------------
data_out : out std_logic_vector(7 downto 0);
ready_to_read : out std_logic;
strobe_read : in std_logic
);
end Fifo8b;
architecture arch of Fifo8b is
constant ADDR_BITS_COUNT : integer := MAX_ADDR_BIT_NUM + 1;
constant MEMORY_CELLS_COUNT : integer := 2**ADDR_BITS_COUNT;
constant MAX_DATA_LENGTH : integer := MEMORY_CELLS_COUNT - 1;
constant MAX_ADDR : integer := MAX_DATA_LENGTH;
-------------- memory ----------------
signal n_clk : std_logic;
signal p1_addr : std_logic_vector(MAX_ADDR_BIT_NUM downto 0);
signal p1_data_in : std_logic_vector(7 downto 0);
signal p1_strobe : std_logic;
signal p1_data_out : std_logic_vector(7 downto 0);
-------------------------------------------------
signal p2_addr : std_logic_vector(MAX_ADDR_BIT_NUM downto 0);
signal p2_data_in : std_logic_vector(7 downto 0);
signal p2_strobe : std_logic;
signal p2_data_out : std_logic_vector(7 downto 0);
------------- fifo --------------------
signal writeAddr : integer range 0 to MAX_ADDR;
signal readAddr : integer range 0 to MAX_ADDR;
signal readAddrValid : std_logic;
signal currentDataLen : integer range 0 to MAX_DATA_LENGTH;
-------- control ----------------------
signal ss_r, sr_r, ss_w, sr_w : std_logic;
begin
n_clk <= not clk;
p2_strobe <= '0';
ready_to_write <= to_stdl((ss_w = sr_w) and currentDataLen < MAX_DATA_LENGTH);
ready_to_read <= to_stdl((ss_r = sr_r) and currentDataLen > 0);
bytesAvailable <= to_stdl(currentDataLen > 0);
availableBytesCount <= conv_std_logic_vector(currentDataLen, ADDR_BITS_COUNT);
p1_data_in <= data_in;
data_out <= p2_data_out;
bufferFull <= to_stdl(currentDataLen = MAX_DATA_LENGTH);
p1_addr <= conv_std_logic_vector(writeAddr, ADDR_BITS_COUNT);
p2_addr <= conv_std_logic_vector(readAddr, ADDR_BITS_COUNT);
process (reset, clk) begin
if reset = '1' then
writeAddr <= 1;
readAddr <= 0;
readAddrValid <= '0';
sr_w <= '0';
sr_r <= '0';
p1_strobe <= '0';
elsif rising_edge(clk) then
if resetFifo = '1' then
writeAddr <= 1;
readAddr <= 0;
readAddrValid <= '0';
sr_w <= ss_w;
sr_r <= ss_r;
p1_strobe <= '0';
else
if sr_w /= ss_w and currentDataLen < MAX_DATA_LENGTH and
p1_strobe = '0' then
p1_strobe <= '1';
elsif sr_w /= ss_w and currentDataLen < MAX_DATA_LENGTH and
p1_strobe = '1' then
p1_strobe <= '0';
sr_w <= ss_w;
if writeAddr < MAX_ADDR then
writeAddr <= writeAddr + 1;
else
writeAddr <= 0;
end if;
if readAddrValid = '0' then
if readAddr < MAX_ADDR then
readAddr <= readAddr + 1;
else
readAddr <= 0;
end if;
readAddrValid <= '1';
end if;
end if;
if sr_r /= ss_r and currentDataLen > 0 and
readAddrValid = '1' then
sr_r <= ss_r;
if currentDataLen = 1 and
-- and last writing phase is not ongoing
not(sr_w /= ss_w and p1_strobe = '1') then
-- if writing is not ongoing
readAddrValid <= '0';
else
if readAddr < MAX_ADDR then
readAddr <= readAddr + 1;
else
readAddr <= 0;
end if;
end if;
end if;
end if;
end if;
end process;
-- calculate current length
process(writeAddr, readAddr, readAddrValid) begin
if readAddrValid = '0' then
currentDataLen <= 0;
elsif readAddr < writeAddr then
currentDataLen <= writeAddr - readAddr;
else -- readAddr > writeAddr, readAddr = writeAddr shoud never happen
currentDataLen <= (MEMORY_CELLS_COUNT - readAddr) + writeAddr;
end if;
end process;
-- subscribe write
process (reset, strobe_write) begin
if reset = '1' then
ss_w <= '0';
elsif rising_edge(strobe_write) then
if ss_w = sr_w then
ss_w <= not sr_w;
end if;
end if;
end process;
-- subscribe read
process (reset, strobe_read) begin
if reset = '1' then
ss_r <= '0';
elsif rising_edge(strobe_read) then
if ss_r = sr_r then
ss_r <= not sr_r;
end if;
end if;
end process;
-- target memory
mb: MemoryBlock port map (
reset => reset,
clk => n_clk,
-------------------------------------------------
p1_addr => p1_addr,
p1_data_in => p1_data_in,
p1_strobe => p1_strobe,
p1_data_out => p1_data_out,
-------------------------------------------------
p2_addr => p2_addr,
p2_data_in => p2_data_in,
p2_strobe => p2_strobe,
p2_data_out => p2_data_out
);
end arch;
| gpl-3.0 | 81a51046fbb3500d4bafd8bc57f25a3a | 0.580807 | 3.248552 | false | false | false | false |
mithro/HDMI2USB | ipcore_dir/rgbfifo/example_design/rgbfifo_exdes.vhd | 3 | 5,263 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rgbfifo_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity rgbfifo_exdes is
PORT (
CLK : IN std_logic;
VALID : OUT std_logic;
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(8-1 DOWNTO 0);
DOUT : OUT std_logic_vector(8-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end rgbfifo_exdes;
architecture xilinx of rgbfifo_exdes is
signal clk_i : std_logic;
component rgbfifo is
PORT (
CLK : IN std_logic;
VALID : OUT std_logic;
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(8-1 DOWNTO 0);
DOUT : OUT std_logic_vector(8-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
exdes_inst : rgbfifo
PORT MAP (
CLK => clk_i,
VALID => valid,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| bsd-2-clause | f0a3465a4dfdadf8c6c3e4c50e413a31 | 0.511115 | 5.070328 | false | false | false | false |
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