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PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_0/synth/blk_mem_gen_0.vhd | 1 | 13,998 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY blk_mem_gen_0 IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END blk_mem_gen_0;
ARCHITECTURE blk_mem_gen_0_arch OF blk_mem_gen_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF blk_mem_gen_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
sleep : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF blk_mem_gen_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2014.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF blk_mem_gen_0_arch : ARCHITECTURE IS "blk_mem_gen_0,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF blk_mem_gen_0_arch: ARCHITECTURE IS "blk_mem_gen_0,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=0,x_ipLanguage=VHDL,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=blk_mem_gen_0.mif,C_INIT_FILE=blk_mem_gen_0.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=64,C_READ_WIDTH_A=64,C_WRITE_DEPTH_A=512,C_READ_DEPTH_A=512,C_ADDRA_WIDTH=9,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=64,C_READ_WIDTH_B=64,C_WRITE_DEPTH_B=512,C_READ_DEPTH_B=512,C_ADDRB_WIDTH=9,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 6.966099 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "blk_mem_gen_0.mif",
C_INIT_FILE => "blk_mem_gen_0.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 64,
C_READ_WIDTH_A => 64,
C_WRITE_DEPTH_A => 512,
C_READ_DEPTH_A => 512,
C_ADDRA_WIDTH => 9,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 64,
C_READ_WIDTH_B => 64,
C_WRITE_DEPTH_B => 512,
C_READ_DEPTH_B => 512,
C_ADDRB_WIDTH => 9,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 6.966099 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => enb,
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END blk_mem_gen_0_arch;
| mit | 6fad7eade8fcb1ad903dd82c20816420 | 0.629876 | 3.018111 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sources_1/rtl/clocking/aeg_design_clk_wiz.vhd | 2 | 7,331 | -- file: tri_mode_ethernet_mac_0_clk_wiz.vhd
--
-- -----------------------------------------------------------------------------
-- (c) Copyright 2008-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1 125.000 0.000 50.0 91.364 85.928
-- CLK_OUT2 100.000 0.000 50.0 70.716 85.928
-- CLK_OUT2 200.000 0.000 50.0
--
------------------------------------------------------------------------------
-- Input Clock Input Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- primary 200.000 0.010
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity aeg_design_0_clk_wiz is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
CLK_OUT3 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end aeg_design_0_clk_wiz;
architecture xilinx of aeg_design_0_clk_wiz is
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfboutb_unused : std_logic;
signal clkout0 : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1 : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2 : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Clocking primitive
--------------------------------------
-- Instantiation of the MMCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 5.000,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE_F => 8.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 10,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 5,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN1_PERIOD => 5.000,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clkout0,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout,
CLKIN1 => CLK_IN1,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => LOCKED,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => RESET);
-- Output buffering
-------------------------------------
clkout1_buf : BUFGCE
port map
(O => CLK_OUT1,
CE => '1',
I => clkout0);
clkout2_buf : BUFGCE
port map
(O => CLK_OUT2,
CE => '1',
I => clkout1);
clkout3_buf : BUFGCE
port map
(O => CLK_OUT3,
CE => '1',
I => clkout2);
end xilinx;
| mit | b4cf39ccc8d1deb7df8af60f10136671 | 0.555313 | 4.257259 | false | false | false | false |
lennartbublies/ecdsa | src/e_gf2m_point_addition.test.vhd | 1 | 7,272 | ----------------------------------------------------------------------------------------------------
-- ENTITY - Elliptic Curve Point Addition
--
-- Ports:
-- clk_i - Clock
-- rst_i - Reset flag
-- enable_i - Enable computation
-- x1_i - X part of first point
-- y1_i - Y part of first point
-- x2_i - X part of seccond point
-- y2_i - Y part of thirs point
-- x3_io - X part of output point
-- y3_o - Y part of output point
-- ready_o - Ready flag
--
-- Math:
-- s = (py-qy)/(px-qx)
-- rx = s^2 - s - (px-qx)
-- ry = s * (px - rx) - rx - py
--
-- Based on:
-- http://arithmetic-circuits.org/finite-field/vhdl_Models/chapter10_codes/VHDL/K-163/K163_addition.vhd
--
-- Autor: Lennart Bublies (inf100434)
-- Date: 27.06.2017
----------------------------------------------------------------------------------------------------
------------------------------------------------------------
-- GF(2^M) elliptic curve point addition
------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.tld_ecdsa_package.all;
ENTITY e_gf2m_point_addition IS
GENERIC (
MODULO : std_logic_vector(M DOWNTO 0) := ONE
);
PORT(
-- Clock, reset, enable
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
-- Input signals
x1_i: IN std_logic_vector(M-1 DOWNTO 0);
y1_i: IN std_logic_vector(M-1 DOWNTO 0);
x2_i: IN std_logic_vector(M-1 DOWNTO 0);
y2_i: IN std_logic_vector(M-1 DOWNTO 0);
-- Output signals
x3_io: INOUT std_logic_vector(M-1 DOWNTO 0);
y3_o: OUT std_logic_vector(M-1 DOWNTO 0);
ready_o: OUT std_logic
);
END e_gf2m_point_addition;
ARCHITECTURE rtl of e_gf2m_point_addition IS
-- Import entity e_gf2m_divider
COMPONENT e_gf2m_divider IS
GENERIC (
MODULO : std_logic_vector(M DOWNTO 0)
);
PORT(
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
g_i: IN std_logic_vector(M-1 DOWNTO 0);
h_i: IN std_logic_vector(M-1 DOWNTO 0);
z_o: OUT std_logic_vector(M-1 DOWNTO 0);
ready_o: OUT std_logic
);
end COMPONENT;
-- Import entity e_gf2m_classic_squarer
COMPONENT e_gf2m_classic_squarer IS
GENERIC (
MODULO : std_logic_vector(M-1 DOWNTO 0)
);
PORT(
a_i: IN std_logic_vector(M-1 DOWNTO 0);
c_o: OUT std_logic_vector(M-1 DOWNTO 0)
);
end COMPONENT;
-- Import entity e_gf2m_interleaved_multiplier
COMPONENT e_gf2m_interleaved_multiplier IS
GENERIC (
MODULO : std_logic_vector(M-1 DOWNTO 0)
);
PORT(
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
a_i: IN std_logic_vector (M-1 DOWNTO 0);
b_i: IN std_logic_vector (M-1 DOWNTO 0);
z_o: OUT std_logic_vector (M-1 DOWNTO 0);
ready_o: OUT std_logic
);
end COMPONENT;
-- Temporary signals for divider and multiplier
SIGNAL div_in1, div_in2, lambda, lambda_square, mult_in2, mult_out: std_logic_vector(M-1 DOWNTO 0);
-- Signals to switch between multiplier and divider
SIGNAL start_div, div_done, start_mult, mult_done: std_logic;
-- Define all available states
subtype states IS natural RANGE 0 TO 6;
SIGNAL current_state: states;
BEGIN
-- Instantiate divider entity
-- Calculate s = (py-qy)/(px-qx)
divider: e_gf2m_divider GENERIC MAP (
MODULO => MODULO
) PORT MAP(
clk_i => clk_i,
rst_i => rst_i,
enable_i => start_div,
g_i => div_in1,
h_i => div_in2,
z_o => lambda,
ready_o => div_done
);
-- Instantiate squarer
-- Calculate s^2
lambda_square_computation: e_gf2m_classic_squarer GENERIC MAP (
MODULO => MODULO(M-1 DOWNTO 0)
) PORT MAP(
a_i => lambda,
c_o => lambda_square
);
-- Instantiate multiplier entity
-- Calculate s * (px - rx)
multiplier: e_gf2m_interleaved_multiplier GENERIC MAP (
MODULO => MODULO(M-1 DOWNTO 0)
) PORT MAP(
clk_i => clk_i,
rst_i => rst_i,
enable_i => start_mult,
a_i => lambda,
b_i => mult_in2,
z_o => mult_out,
ready_o => mult_done
);
-- Set divider input from entity input
-- Calculate (py-qy) and (px-qx)
divider_inputs: FOR i IN 0 TO M-1 GENERATE
div_in1(i) <= y1_i(i) xor y2_i(i);
div_in2(i) <= x1_i(i) xor x2_i(i);
END GENERATE;
-- Set multiplier input from entity input
-- Calculate (px - rx)
multiplier_inputs: FOR i IN 0 TO M-1 GENERATE
mult_in2(i) <= x1_i(i) xor x3_io(i);
END GENERATE;
-- Set output
-- Calculate rx = s^2 - s - (px-qx)
x_output: FOR i IN 0 TO M-1 GENERATE
x3_io(i) <= lambda_square(i) xor lambda(i) xor div_in2(i) xor a(i);
END GENERATE;
-- Set x3(0)
-- x3_io(0) <= not(lambda_square(0) xor lambda(0) xor div_in2(0));
-- Calculate ry = s * (px - rx) - rx - py
y_output: FOR i IN 0 TO M-1 GENERATE
y3_o(i) <= mult_out(i) xor x3_io(i) xor y1_i(i);
END GENERATE;
-- State machine
control_unit: PROCESS(clk_i, rst_i, current_state)
BEGIN
-- Handle current state
-- 0,1 : Default state
-- 2,3 : Calculate s = (py-qy)/(px-qx), s^2
-- 4,5,6 : Calculate rx/ry
CASE current_state IS
WHEN 0 TO 1 => start_div <= '0'; start_mult <= '0'; ready_o <= '1';
WHEN 2 => start_div <= '1'; start_mult <= '0'; ready_o <= '0';
WHEN 3 => start_div <= '0'; start_mult <= '0'; ready_o <= '0';
WHEN 4 => start_div <= '0'; start_mult <= '1'; ready_o <= '0';
WHEN 5 TO 6 => start_div <= '0'; start_mult <= '0'; ready_o <= '0';
END CASE;
IF rst_i = '1' THEN
-- Reset state if reset is high
current_state <= 0;
ELSIF clk_i'event and clk_i = '1' THEN
-- Set next state
CASE current_state IS
WHEN 0 =>
IF enable_i = '0' THEN
current_state <= 1;
END IF;
WHEN 1 =>
IF enable_i = '1' THEN
current_state <= 2;
END IF;
WHEN 2 =>
current_state <= 3;
WHEN 3 =>
IF div_done = '1' THEN
current_state <= 4;
END IF;
WHEN 4 =>
current_state <= 5;
WHEN 5 =>
IF mult_done = '1' THEN
current_state <= 6;
END IF;
WHEN 6 =>
current_state <= 0;
END CASE;
END IF;
END PROCESS;
END rtl; | gpl-3.0 | ec928aeccf26046dd8cf9427761395bd | 0.479923 | 3.496154 | false | false | false | false |
Caian/Minesweeper | Projeto/ps2_mouse.vhd | 1 | 3,004 | ---------------------------------------------------------
-- MC613 - UNICAMP
--
---------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
entity ps2_mouse is
port
(
------------------------ Clock Input ------------------------
CLOCK_24 : in STD_LOGIC_VECTOR (1 downto 0); -- 24 MHz
------------------------ Push Button ------------------------
KEY : in STD_LOGIC_VECTOR (3 downto 0); -- Pushbutton[3:0]
------------------------ PS2 --------------------------------
PS2_DAT : inout STD_LOGIC; -- PS2 Data
PS2_CLK : inout STD_LOGIC; -- PS2 Clock
Botoes : out STD_LOGIC_VECTOR (2 DOWNTO 0);
x_out, y_out : out std_logic_vector(9 downto 0)
);
end;
architecture struct of ps2_mouse is
component mouse_ctrl
generic(
clkfreq : integer
);
port(
ps2_data : inout std_logic;
ps2_clk : inout std_logic;
clk : in std_logic;
en : in std_logic;
resetn : in std_logic;
newdata : out std_logic;
bt_on : out std_logic_vector(2 downto 0);
ox, oy : out std_logic;
dx, dy : out std_logic_vector(8 downto 0);
wheel : out std_logic_vector(3 downto 0)
);
end component;
signal signewdata, resetn : std_logic;
signal dx, dy : std_logic_vector(8 downto 0);
signal x, y : std_logic_vector(10 downto 0);
signal x2, y2 : std_logic_vector(10 downto 0);
signal vazio : std_logic_vector(5 downto 0);
constant SENSIBILITY : integer := 2; -- Rise to decrease sensibility
begin
-- KEY(0) Reset
resetn <= KEY(0);
mousectrl : mouse_ctrl generic map (24000) port map(
PS2_DAT, PS2_CLK, CLOCK_24(0), '1', KEY(0),
signewdata, Botoes, vazio(5), vazio(4), dx, dy, vazio(3 downto 0)
);
-- Read new mouse data
process(signewdata, resetn)
variable xacc, yacc : integer range -10000 to 10000;
begin
if(rising_edge(signewdata)) then
x <= std_logic_vector(to_signed(to_integer(signed(x)) + ((xacc + to_integer(signed(dx))) / SENSIBILITY), 11));
y <= std_logic_vector(to_signed(to_integer(signed(y)) + ((yacc + to_integer(signed(dy))) / SENSIBILITY), 11));
xacc := ((xacc + to_integer(signed(dx))) rem SENSIBILITY);
yacc := ((yacc + to_integer(signed(dy))) rem SENSIBILITY);
if ((to_signed(to_integer(signed(x)), 11)) < 0) then
x <= "00000000000";
elsif ((to_signed(to_integer(signed(x)), 11)) > 640) then
x <= "01010000000";
else
x2 <= x;
end if;
if ((to_signed(to_integer(signed(y)), 11)) < 0) then
y <= "00000000000";
elsif ((to_signed(to_integer(signed(y)), 11)) > 480) then
y <= "00111100000";
else
y2 <= y;
end if;
end if;
if resetn = '0' then
xacc := 0;
yacc := 0;
x <= "00101000000";
y <= "00011110000";
x2 <= "00101000000";
y2 <= "00011110000";
end if;
end process;
x_out <= x2(9 downto 0);
y_out <= y2(9 downto 0);
end struct;
| gpl-2.0 | c1e1efa32879d37eea3d13890fe0d64c | 0.536618 | 2.860952 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/temac_testbench_source/sources_1/imports/example_design/fifo/tri_mode_ethernet_mac_0_tx_client_fifo.vhd | 1 | 67,389 | --------------------------------------------------------------------------------
-- Title : Transmitter FIFO with AxiStream interfaces
-- Version : 1.3
-- Project : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_tx_client_fifo.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This is a transmitter side FIFO for the design example
-- of the Tri-Mode Ethernet MAC core. AxiStream interfaces are used.
--
-- The FIFO is built around an Inferred Dual Port RAM,
-- giving a total memory capacity of 4096 bytes.
--
-- Valid frame data received from the user interface is written
-- into the Block RAM on the tx_fifo_aclkk. The FIFO will store
-- frames up to 4kbytes in length. If larger frames are written
-- to the FIFO, the AxiStream interface will accept the rest of the
-- frame, but that frame will be dropped by the FIFO and the
-- overflow signal will be asserted.
--
-- The FIFO is designed to work with a minimum frame length of 14
-- bytes.
--
-- When there is at least one complete frame in the FIFO, the MAC
-- transmitter AxiStream interface will be driven to request frame
-- transmission by placing the first byte of the frame onto
-- tx_axis_mac_tdata and by asserting tx_axis_mac_tvalid. The MAC will later
-- respond by asserting tx_axis_mac_tready. At this point the remaining
-- frame data is read out of the FIFO subject to tx_axis_mac_tready.
-- Data is read out of the FIFO on the tx_mac_aclk.
--
-- If the generic FULL_DUPLEX_ONLY is set to false, the FIFO will
-- requeue and retransmit frames as requested by the MAC. Once a
-- frame has been transmitted by the FIFO it is stored until the
-- possible retransmit window for that frame has expired.
--
-- The FIFO has been designed to operate with different clocks
-- on the write and read sides. The minimum write clock
-- frequency is the read clock frequency divided by 2.
--
-- The FIFO memory size can be increased by expanding the rd_addr
-- and wr_addr signal widths, to address further BRAMs.
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
-- Entity declaration for the Transmitter FIFO
--------------------------------------------------------------------------------
entity tri_mode_ethernet_mac_0_tx_client_fifo is
generic (
FULL_DUPLEX_ONLY : boolean := false);
port (
-- User-side (write-side) AxiStream interface
tx_fifo_aclk : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tlast : in std_logic;
tx_axis_fifo_tready : out std_logic;
-- MAC-side (read-side) AxiStream interface
tx_mac_aclk : in std_logic;
tx_mac_resetn : in std_logic;
tx_axis_mac_tdata : out std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : out std_logic;
tx_axis_mac_tlast : out std_logic;
tx_axis_mac_tready : in std_logic;
tx_axis_mac_tuser : out std_logic;
-- FIFO status and overflow indication,
-- synchronous to write-side (tx_user_aclk) interface
fifo_overflow : out std_logic;
fifo_status : out std_logic_vector(3 downto 0);
-- FIFO collision and retransmission requests from MAC
tx_collision : in std_logic;
tx_retransmit : in std_logic
);
end tri_mode_ethernet_mac_0_tx_client_fifo;
architecture RTL of tri_mode_ethernet_mac_0_tx_client_fifo is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
------------------------------------------------------------------------------
-- Component declaration for the synchronisation flip-flop pair
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_sync_block
port (
clk : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the block RAM
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_bram_tdp
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 12
);
port (
-- Port A
a_clk : in std_logic;
a_rst : in std_logic;
a_wr : in std_logic;
a_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
a_din : in std_logic_vector(DATA_WIDTH-1 downto 0);
-- Port B
b_clk : in std_logic;
b_en : in std_logic;
b_rst : in std_logic;
b_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
b_dout : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end component;
------------------------------------------------------------------------------
-- Define internal signals
------------------------------------------------------------------------------
-- Encoded read state machine states.
type rd_state_typ is (IDLE_s,
QUEUE1_s,
QUEUE2_s,
QUEUE3_s,
START_DATA1_s,
DATA_PRELOAD1_s,
DATA_PRELOAD2_s,
WAIT_HANDSHAKE_s,
FRAME_s,
HANDSHAKE_s,
FINISH_s,
DROP_ERR_s,
DROP_s,
RETRANSMIT_ERR_s,
RETRANSMIT_s);
signal rd_state : rd_state_typ;
signal rd_nxt_state : rd_state_typ;
-- Encoded write state machine states,
type wr_state_typ is (WAIT_s,
DATA_s,
EOF_s,
OVFLOW_s);
signal wr_state : wr_state_typ;
signal wr_nxt_state : wr_state_typ;
type data_pipe is array (0 to 1) of std_logic_vector(7 downto 0);
type cntl_pipe is array (0 to 1) of std_logic;
signal wr_eof_data_bram : std_logic_vector(8 downto 0);
signal wr_data_bram : std_logic_vector(7 downto 0);
signal wr_data_pipe : data_pipe;
signal wr_sof_pipe : cntl_pipe;
signal wr_eof_pipe : cntl_pipe;
signal wr_accept_pipe : cntl_pipe;
signal wr_accept_bram : std_logic;
signal wr_sof_int : std_logic;
signal wr_eof_bram : std_logic_vector(0 downto 0);
signal wr_eof_reg : std_logic;
signal wr_addr : unsigned(11 downto 0) := (others => '0');
signal wr_addr_inc : std_logic;
signal wr_start_addr_load : std_logic;
signal wr_addr_reload : std_logic;
signal wr_start_addr : unsigned(11 downto 0) := (others => '0');
signal wr_fifo_full : std_logic;
signal wr_en : std_logic;
signal wr_ovflow_dst_rdy : std_logic;
signal tx_axis_fifo_tready_int_n : std_logic;
signal data_count : unsigned(3 downto 0) := (others => '0');
signal frame_in_fifo : std_logic;
signal frames_in_fifo : std_logic;
signal frame_in_fifo_valid : std_logic;
signal frame_in_fifo_valid_tog : std_logic := '0';
signal frame_in_fifo_valid_sync : std_logic;
signal frame_in_fifo_valid_delay : std_logic;
signal rd_eof : std_logic;
signal rd_eof_pipe : std_logic;
signal rd_eof_reg : std_logic;
signal rd_addr : unsigned(11 downto 0) := (others => '0');
signal rd_addr_inc : std_logic;
signal rd_addr_reload : std_logic;
signal rd_eof_data_bram : std_logic_vector(8 downto 0);
signal rd_data_bram : std_logic_vector(7 downto 0);
signal rd_data_pipe : std_logic_vector(7 downto 0) := (others => '0');
signal rd_data_delay : std_logic_vector(7 downto 0) := (others => '0');
signal rd_eof_bram : std_logic_vector(0 downto 0);
signal rd_en : std_logic;
signal rd_tran_frame_tog : std_logic := '0';
signal wr_tran_frame_sync : std_logic;
signal wr_tran_frame_delay : std_logic := '0';
signal rd_retran_frame_tog : std_logic := '0';
signal wr_retran_frame_sync : std_logic;
signal wr_retran_frame_delay : std_logic := '0';
signal wr_store_frame : std_logic;
signal wr_eof_state : std_logic;
signal wr_eof_state_reg : std_logic;
signal wr_transmit_frame : std_logic;
signal wr_transmit_frame_delay : std_logic;
signal wr_retransmit_frame : std_logic;
signal wr_frames : unsigned(8 downto 0) := (others => '0');
signal wr_frame_in_fifo : std_logic;
signal wr_frames_in_fifo : std_logic;
signal rd_16_count : unsigned(3 downto 0) := (others => '0');
signal rd_txfer_en : std_logic;
signal rd_addr_txfer : unsigned(11 downto 0) := (others => '0');
signal rd_txfer_tog : std_logic := '0';
signal wr_txfer_tog_sync : std_logic;
signal wr_txfer_tog_delay : std_logic := '0';
signal wr_txfer_en : std_logic;
signal wr_rd_addr : unsigned(11 downto 0) := (others => '0');
signal wr_addr_diff : unsigned(11 downto 0) := (others => '0');
signal wr_fifo_status : unsigned(3 downto 0) := (others => '0');
signal rd_drop_frame : std_logic;
signal rd_retransmit : std_logic;
signal rd_start_addr : unsigned(11 downto 0) := (others => '0');
signal rd_start_addr_load : std_logic;
signal rd_start_addr_reload : std_logic;
signal rd_dec_addr : unsigned(11 downto 0) := (others => '0');
signal rd_transmit_frame : std_logic;
signal rd_retransmit_frame : std_logic;
signal rd_col_window_expire : std_logic;
signal rd_col_window_pipe : cntl_pipe;
signal wr_col_window_pipe : cntl_pipe;
signal wr_fifo_overflow : std_logic;
signal rd_slot_timer : unsigned(9 downto 0) := (others => '0');
signal wr_col_window_expire : std_logic;
signal rd_idle_state : std_logic;
signal tx_axis_mac_tdata_int_frame : std_logic_vector(7 downto 0);
signal tx_axis_mac_tdata_int_handshake : std_logic_vector(7 downto 0);
signal tx_axis_mac_tdata_int : std_logic_vector(7 downto 0) := (others => '0');
signal tx_axis_mac_tvalid_int_finish : std_logic;
signal tx_axis_mac_tvalid_int_droperr : std_logic;
signal tx_axis_mac_tvalid_int_retransmiterr : std_logic;
signal tx_axis_mac_tlast_int_frame_handshake : std_logic;
signal tx_axis_mac_tlast_int_finish : std_logic;
signal tx_axis_mac_tlast_int_droperr : std_logic;
signal tx_axis_mac_tlast_int_retransmiterr : std_logic;
signal tx_axis_mac_tuser_int_droperr : std_logic;
signal tx_axis_mac_tuser_int_retransmit : std_logic;
signal tx_fifo_reset : std_logic;
signal tx_mac_reset : std_logic;
-- Small delay for simulation purposes.
constant dly : time := 1 ps;
------------------------------------------------------------------------------
-- Attributes for FIFO simulation and synthesis
------------------------------------------------------------------------------
-- ASYNC_REG attributes added to simulate actual behaviour under
-- asynchronous operating conditions.
attribute ASYNC_REG : string;
attribute ASYNC_REG of wr_rd_addr : signal is "TRUE";
attribute ASYNC_REG of wr_col_window_pipe : signal is "TRUE";
------------------------------------------------------------------------------
-- Begin FIFO architecture
------------------------------------------------------------------------------
begin
-- invert reset sense as architecture is optimised for active high resets
tx_fifo_reset <= not tx_fifo_resetn;
tx_mac_reset <= not tx_mac_resetn;
------------------------------------------------------------------------------
-- Write state machine and control
------------------------------------------------------------------------------
-- Write state machine.
-- States are WAIT, DATA, EOF, OVFLOW.
-- Clock state to next state.
clock_wrs_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
if tx_fifo_reset = '1' then
wr_state <= WAIT_s after dly;
else
wr_state <= wr_nxt_state after dly;
end if;
end if;
end process clock_wrs_p;
-- Decode next state, combinitorial.
next_wrs_p : process(wr_state, wr_sof_pipe(1), wr_eof_pipe(0), wr_eof_pipe(1),
wr_eof_bram(0), wr_fifo_overflow, data_count)
begin
case wr_state is
when WAIT_s =>
if wr_sof_pipe(1) = '1' and wr_eof_pipe(1) = '0' then
wr_nxt_state <= DATA_s;
else
wr_nxt_state <= WAIT_s;
end if;
when DATA_s =>
-- Wait for the end of frame to be detected.
if wr_fifo_overflow = '1' and wr_eof_pipe(0) = '0'
and wr_eof_pipe(1) = '0' then
wr_nxt_state <= OVFLOW_s;
elsif wr_eof_pipe(1) = '1' then
if data_count(3 downto 2) /= "11" then
wr_nxt_state <= OVFLOW_s;
else
wr_nxt_state <= EOF_s;
end if;
else
wr_nxt_state <= DATA_s;
end if;
when EOF_s =>
-- If the start of frame is already in the pipe, a back-to-back frame
-- transmission has occured. Move straight back to frame state.
if wr_sof_pipe(1) = '1' and wr_eof_pipe(1) = '0' then
wr_nxt_state <= DATA_s;
elsif wr_eof_bram(0) = '1' then
wr_nxt_state <= WAIT_s;
else
wr_nxt_state <= EOF_s;
end if;
when OVFLOW_s =>
-- Wait until the end of frame is reached before clearing the overflow.
if wr_eof_bram(0) = '1' then
wr_nxt_state <= WAIT_s;
else
wr_nxt_state <= OVFLOW_s;
end if;
when others =>
wr_nxt_state <= WAIT_s;
end case;
end process;
-- small frame count - frames smaller than 10 bytes are problematic as the frame_in_fifo cannot
-- react quickly enough - empty detect could be used in the read domain but this doesn't fully cover all cases
-- the cleanest fix is to simply ignore frames smaller than 10 bytes
-- generate a counter which is cleaered on an sof and counts in data
data_count_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
if tx_fifo_reset = '1' then
data_count <= (others => '0') after dly;
else
if wr_sof_pipe(1) = '1' then
data_count <= (others => '0');
else
if data_count(3 downto 2) /= "11" then
data_count <= data_count + "0001";
end if;
end if;
end if;
end if;
end process data_count_p;
-- Decode output signals, combinatorial.
-- wr_en is used to enable the BRAM write and the address to increment.
wr_en <= '0' when wr_state = OVFLOW_s else wr_accept_bram;
wr_addr_inc <= wr_en;
wr_addr_reload <= '1' when wr_state = OVFLOW_s else '0';
wr_start_addr_load <= '1' when wr_state = EOF_s and wr_nxt_state = WAIT_s
else
'1' when wr_state = EOF_s and wr_nxt_state = DATA_s
else '0';
-- Pause the AxiStream handshake when the FIFO is full.
tx_axis_fifo_tready_int_n <= wr_ovflow_dst_rdy when wr_state = OVFLOW_s
else wr_fifo_full;
tx_axis_fifo_tready <= not tx_axis_fifo_tready_int_n;
-- Generate user overflow indicator.
fifo_overflow <= '1' when wr_state = OVFLOW_s else '0';
-- When in overflow and have captured ovflow EOF, set tx_axis_fifo_tready again.
p_ovflow_dst_rdy : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_ovflow_dst_rdy <= '0' after dly;
else
if wr_fifo_overflow = '1' and wr_state = DATA_s then
wr_ovflow_dst_rdy <= '0' after dly;
elsif tx_axis_fifo_tvalid = '1' and tx_axis_fifo_tlast = '1' then
wr_ovflow_dst_rdy <= '1' after dly;
end if;
end if;
end if;
end process;
-- EOF signals for use in overflow logic.
wr_eof_state <= '1' when wr_state = EOF_s else '0';
p_reg_eof_st : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_eof_state_reg <= '0' after dly;
else
wr_eof_state_reg <= wr_eof_state after dly;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- Read state machine and control
------------------------------------------------------------------------------
-- Read state machine.
-- States are IDLE, QUEUE1, QUEUE2, QUEUE3, QUEUE_ACK, WAIT_ACK, FRAME,
-- HANDSHAKE, FINISH, DROP_ERR, DROP, RETRANSMIT_ERR, RETRANSMIT.
-- Clock state to next state.
clock_rds_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_state <= IDLE_s after dly;
else
rd_state <= rd_nxt_state after dly;
end if;
end if;
end process clock_rds_p;
------------------------------------------------------------------------------
-- Full duplex-only state machine.
gen_fd_sm : if (FULL_DUPLEX_ONLY = TRUE) generate
-- Decode next state, combinatorial.
next_rds_p : process(rd_state, frame_in_fifo, frames_in_fifo, frame_in_fifo_valid, rd_eof, rd_eof_reg, tx_axis_mac_tready)
begin
case rd_state is
when IDLE_s =>
-- If there is a frame in the FIFO, start to queue the new frame
-- to the output.
if (frame_in_fifo = '1' and frame_in_fifo_valid = '1') or frames_in_fifo = '1' then
rd_nxt_state <= QUEUE1_s;
else
rd_nxt_state <= IDLE_s;
end if;
-- Load the output pipeline, which takes three clock cycles.
when QUEUE1_s =>
rd_nxt_state <= QUEUE2_s;
when QUEUE2_s =>
rd_nxt_state <= QUEUE3_s;
when QUEUE3_s =>
rd_nxt_state <= START_DATA1_s;
when START_DATA1_s =>
-- The pipeline is full and the frame output starts now.
rd_nxt_state <= DATA_PRELOAD1_s;
when DATA_PRELOAD1_s =>
-- Await the tx_axis_mac_tready acknowledge before moving on.
if tx_axis_mac_tready = '1' then
rd_nxt_state <= FRAME_s;
else
rd_nxt_state <= DATA_PRELOAD1_s;
end if;
when FRAME_s =>
-- Read the frame out of the FIFO. If the MAC deasserts
-- tx_axis_mac_tready, stall in the handshake state. If the EOF
-- flag is encountered, move to the finish state.
if tx_axis_mac_tready = '0' then
rd_nxt_state <= HANDSHAKE_s;
elsif rd_eof = '1' then
rd_nxt_state <= FINISH_s;
else
rd_nxt_state <= FRAME_s;
end if;
when HANDSHAKE_s =>
-- Await tx_axis_mac_tready before continuing frame transmission.
-- If the EOF flag is encountered, move to the finish state.
if tx_axis_mac_tready = '1' and rd_eof_reg = '1' then
rd_nxt_state <= FINISH_s;
elsif tx_axis_mac_tready = '1' and rd_eof_reg = '0' then
rd_nxt_state <= FRAME_s;
else
rd_nxt_state <= HANDSHAKE_s;
end if;
when FINISH_s =>
-- Frame has finished. Assure that the MAC has accepted the final
-- byte by transitioning to idle only when tx_axis_mac_tready is high.
if tx_axis_mac_tready = '1' then
rd_nxt_state <= IDLE_s;
else
rd_nxt_state <= FINISH_s;
end if;
when others =>
rd_nxt_state <= IDLE_s;
end case;
end process next_rds_p;
end generate gen_fd_sm;
------------------------------------------------------------------------------
-- Full and half duplex state machine.
gen_hd_sm : if (FULL_DUPLEX_ONLY = FALSE) generate
-- Decode the next state, combinatorial.
next_rds_p : process(rd_state, frame_in_fifo, frames_in_fifo, frame_in_fifo_valid, rd_eof_reg, tx_axis_mac_tready,
rd_drop_frame, rd_retransmit)
begin
case rd_state is
when IDLE_s =>
-- If a retransmit request is detected then prepare to retransmit.
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
-- If there is a frame in the FIFO, then queue the new frame to
-- the output.
elsif (frame_in_fifo = '1' and frame_in_fifo_valid = '1') or frames_in_fifo = '1' then
rd_nxt_state <= QUEUE1_s;
else
rd_nxt_state <= IDLE_s;
end if;
-- Load the output pipeline, which takes three clock cycles.
when QUEUE1_s =>
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
else
rd_nxt_state <= QUEUE2_s;
end if;
when QUEUE2_s =>
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
else
rd_nxt_state <= QUEUE3_s;
end if;
when QUEUE3_s =>
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
else
rd_nxt_state <= START_DATA1_s;
end if;
when START_DATA1_s =>
-- The pipeline is full and the frame output starts now.
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
else
rd_nxt_state <= DATA_PRELOAD1_s;
end if;
when DATA_PRELOAD1_s =>
-- Await the tx_axis_mac_tready acknowledge before moving on.
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
elsif tx_axis_mac_tready = '1' then
rd_nxt_state <= DATA_PRELOAD2_s;
else
rd_nxt_state <= DATA_PRELOAD1_s;
end if;
when DATA_PRELOAD2_s =>
-- If a collision-only request, then must drop the rest of the
-- current frame. If collision and retransmit, then prepare
-- to retransmit the frame.
if rd_drop_frame = '1' then
rd_nxt_state <= DROP_ERR_s;
elsif rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
-- Read the frame out of the FIFO. If the MAC deasserts
-- tx_axis_mac_tready, stall in the handshake state. If the EOF
-- flag is encountered, move to the finish state.
elsif tx_axis_mac_tready = '0' then
rd_nxt_state <= WAIT_HANDSHAKE_s;
elsif rd_eof_reg = '1' then
rd_nxt_state <= FINISH_s;
else
rd_nxt_state <= DATA_PRELOAD2_s;
end if;
when WAIT_HANDSHAKE_s =>
-- Await tx_axis_mac_tready before continuing frame transmission.
-- If the EOF flag is encountered, move to the finish state.
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
elsif tx_axis_mac_tready = '1' and rd_eof_reg = '1' then
rd_nxt_state <= FINISH_s;
elsif tx_axis_mac_tready = '1' and rd_eof_reg = '0' then
rd_nxt_state <= FRAME_s;
else
rd_nxt_state <= WAIT_HANDSHAKE_s;
end if;
when FRAME_s =>
-- If a collision-only request, then must drop the rest of the
-- current frame. If a collision and retransmit, then prepare
-- to retransmit the frame.
if rd_drop_frame = '1' then
rd_nxt_state <= DROP_ERR_s;
elsif rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
-- Read the frame out of the FIFO. If the MAC deasserts
-- tx_axis_mac_tready, stall in the handshake state. If the EOF
-- flag is encountered, move to the finish state.
elsif tx_axis_mac_tready = '0' then
rd_nxt_state <= HANDSHAKE_s;
elsif rd_eof_reg = '1' then
rd_nxt_state <= FINISH_s;
else
rd_nxt_state <= FRAME_s;
end if;
when HANDSHAKE_s =>
-- Await tx_axis_mac_tready before continuing frame transmission.
-- If the EOF flag is encountered, move to the finish state.
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
elsif tx_axis_mac_tready = '1' and rd_eof_reg = '1' then
rd_nxt_state <= FINISH_s;
elsif tx_axis_mac_tready = '1' and rd_eof_reg = '0' then
rd_nxt_state <= FRAME_s;
else
rd_nxt_state <= HANDSHAKE_s;
end if;
when FINISH_s =>
-- Frame has finished. Assure that the MAC has accepted the final
-- byte by transitioning to idle only when tx_axis_mac_tready is high.
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
elsif tx_axis_mac_tready = '1' then
rd_nxt_state <= IDLE_s;
else
rd_nxt_state <= FINISH_s;
end if;
when DROP_ERR_s =>
-- FIFO is ready to drop the frame. Assure that the MAC has
-- accepted the final byte and err signal before dropping.
if tx_axis_mac_tready = '1' then
rd_nxt_state <= DROP_s;
else
rd_nxt_state <= DROP_ERR_s;
end if;
when DROP_s =>
-- Wait until rest of frame has been cleared.
if rd_eof_reg = '1' then
rd_nxt_state <= IDLE_s;
else
rd_nxt_state <= DROP_s;
end if;
when RETRANSMIT_ERR_s =>
-- FIFO is ready to retransmit the frame. Assure that the MAC has
-- accepted the final byte and err signal before retransmitting.
if tx_axis_mac_tready = '1' then
rd_nxt_state <= RETRANSMIT_s;
else
rd_nxt_state <= RETRANSMIT_ERR_s;
end if;
when RETRANSMIT_s =>
-- Reload the data pipeline from the start of the frame.
rd_nxt_state <= QUEUE1_s;
when others =>
rd_nxt_state <= IDLE_s;
end case;
end process next_rds_p;
end generate gen_hd_sm;
-- Combinatorially select tdata candidates.
tx_axis_mac_tdata_int_frame <= tx_axis_mac_tdata_int when rd_nxt_state = HANDSHAKE_s or rd_nxt_state = WAIT_HANDSHAKE_s
else rd_data_pipe;
tx_axis_mac_tdata_int_handshake <= rd_data_pipe when rd_nxt_state = FINISH_s
else tx_axis_mac_tdata_int;
tx_axis_mac_tdata <= tx_axis_mac_tdata_int;
-- Decode output tdata based on current and next read state.
rd_data_decode_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if rd_nxt_state = FRAME_s or rd_nxt_state = DATA_PRELOAD2_s then
tx_axis_mac_tdata_int <= rd_data_pipe after dly;
elsif (rd_nxt_state = RETRANSMIT_ERR_s or rd_nxt_state = DROP_ERR_s)
then tx_axis_mac_tdata_int <= tx_axis_mac_tdata_int after dly;
else
case rd_state is
when START_DATA1_s =>
tx_axis_mac_tdata_int <= rd_data_pipe after dly;
when FRAME_s | DATA_PRELOAD2_s =>
tx_axis_mac_tdata_int <= tx_axis_mac_tdata_int_frame after dly;
when HANDSHAKE_s | WAIT_HANDSHAKE_s =>
tx_axis_mac_tdata_int <= tx_axis_mac_tdata_int_handshake after dly;
when others =>
tx_axis_mac_tdata_int <= tx_axis_mac_tdata_int after dly;
end case;
end if;
end if;
end process rd_data_decode_p;
-- Combinatorially select tvalid candidates.
tx_axis_mac_tvalid_int_finish <= '0' when rd_nxt_state = IDLE_s
else '1';
tx_axis_mac_tvalid_int_droperr <= '0' when rd_nxt_state = DROP_s
else '1';
tx_axis_mac_tvalid_int_retransmiterr <= '0' when rd_nxt_state = RETRANSMIT_s
else '1';
-- Decode output tvalid based on current and next read state.
rd_dv_decode_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if rd_nxt_state = FRAME_s or rd_nxt_state = DATA_PRELOAD2_s then
tx_axis_mac_tvalid <= '1' after dly;
elsif (rd_nxt_state = RETRANSMIT_ERR_s or rd_nxt_state = DROP_ERR_s)
then tx_axis_mac_tvalid <= '1' after dly;
else
case rd_state is
when START_DATA1_s =>
tx_axis_mac_tvalid <= '1' after dly;
when DATA_PRELOAD1_s =>
tx_axis_mac_tvalid <= '1' after dly;
when FRAME_s | DATA_PRELOAD2_s =>
tx_axis_mac_tvalid <= '1' after dly;
when HANDSHAKE_s | WAIT_HANDSHAKE_s =>
tx_axis_mac_tvalid <= '1' after dly;
when FINISH_s =>
tx_axis_mac_tvalid <= tx_axis_mac_tvalid_int_finish after dly;
when DROP_ERR_s =>
tx_axis_mac_tvalid <= tx_axis_mac_tvalid_int_droperr after dly;
when RETRANSMIT_ERR_s =>
tx_axis_mac_tvalid <= tx_axis_mac_tvalid_int_retransmiterr after dly;
when others =>
tx_axis_mac_tvalid <= '0' after dly;
end case;
end if;
end if;
end process rd_dv_decode_p;
-- Combinatorially select tlast candidates.
tx_axis_mac_tlast_int_frame_handshake <= rd_eof_reg when rd_nxt_state = FINISH_s
else '0';
tx_axis_mac_tlast_int_finish <= '0' when rd_nxt_state = IDLE_s
else rd_eof_reg;
tx_axis_mac_tlast_int_droperr <= '0' when rd_nxt_state = DROP_s
else '1';
tx_axis_mac_tlast_int_retransmiterr <= '0' when rd_nxt_state = RETRANSMIT_s
else '1';
-- Decode output tlast based on current and next read state.
rd_last_decode_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if rd_nxt_state = FRAME_s or rd_nxt_state = DATA_PRELOAD2_s then
tx_axis_mac_tlast <= rd_eof after dly;
elsif (rd_nxt_state = RETRANSMIT_ERR_s or rd_nxt_state = DROP_ERR_s)
then tx_axis_mac_tlast <= '1' after dly;
else
case rd_state is
when DATA_PRELOAD1_s =>
tx_axis_mac_tlast <= rd_eof after dly;
when FRAME_s | DATA_PRELOAD2_s =>
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_frame_handshake after dly;
when HANDSHAKE_s | WAIT_HANDSHAKE_s =>
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_frame_handshake after dly;
when FINISH_s =>
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_finish after dly;
when DROP_ERR_s =>
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_droperr after dly;
when RETRANSMIT_ERR_s =>
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_retransmiterr after dly;
when others =>
tx_axis_mac_tlast <= '0' after dly;
end case;
end if;
end if;
end process rd_last_decode_p;
-- Combinatorially select tuser candidates.
tx_axis_mac_tuser_int_droperr <= '0' when rd_nxt_state = DROP_s
else '1';
tx_axis_mac_tuser_int_retransmit <= '0' when rd_nxt_state = RETRANSMIT_s
else '1';
-- Decode output tuser based on current and next read state.
rd_user_decode_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if (rd_nxt_state = RETRANSMIT_ERR_s or rd_nxt_state = DROP_ERR_s)
then tx_axis_mac_tuser <= '1' after dly;
else
case rd_state is
when DROP_ERR_s =>
tx_axis_mac_tuser <= tx_axis_mac_tuser_int_droperr after dly;
when RETRANSMIT_ERR_s =>
tx_axis_mac_tuser <= tx_axis_mac_tuser_int_retransmit after dly;
when others =>
tx_axis_mac_tuser <= '0' after dly;
end case;
end if;
end if;
end process rd_user_decode_p;
------------------------------------------------------------------------------
-- Decode full duplex-only control signals.
gen_fd_decode : if (FULL_DUPLEX_ONLY = TRUE) generate
-- rd_en is used to enable the BRAM read and load the output pipeline.
rd_en <= '0' when rd_state = IDLE_s else
'1' when rd_nxt_state = FRAME_s else
'0' when (rd_state = FRAME_s and rd_nxt_state = HANDSHAKE_s) else
'0' when rd_nxt_state = HANDSHAKE_s else
'0' when rd_state = FINISH_s else
'0' when rd_state = DATA_PRELOAD1_s else '1';
-- When the BRAM is being read, enable the read address to be incremented.
rd_addr_inc <= rd_en;
rd_addr_reload <= '1' when rd_state /= FINISH_s and rd_nxt_state = FINISH_s
else '0';
-- Transmit frame pulse must never be more frequent than once per 64 clocks to
-- allow toggle to cross clock domain.
rd_transmit_frame <= '1' when rd_state = DATA_PRELOAD1_s and rd_nxt_state = FRAME_s
else '0';
-- Unused for full duplex only.
rd_start_addr_reload <= '0';
rd_start_addr_load <= '0';
rd_retransmit_frame <= '0';
end generate gen_fd_decode;
------------------------------------------------------------------------------
-- Decode full and half duplex control signals.
gen_hd_decode : if (FULL_DUPLEX_ONLY = FALSE) generate
-- rd_en is used to enable the BRAM read and load the output pipeline.
rd_en <= '0' when rd_state = IDLE_s else
'0' when rd_nxt_state = DROP_ERR_s else
'0' when (rd_nxt_state = DROP_s and rd_eof = '1') else
'1' when rd_nxt_state = FRAME_s or rd_nxt_state = DATA_PRELOAD2_s else
'0' when (rd_state = DATA_PRELOAD2_s and rd_nxt_state = WAIT_HANDSHAKE_s) else
'0' when (rd_state = FRAME_s and rd_nxt_state = HANDSHAKE_s) else
'0' when (rd_nxt_state = HANDSHAKE_s or rd_nxt_state = WAIT_HANDSHAKE_s) else
'0' when rd_state = FINISH_s else
'0' when rd_state = RETRANSMIT_ERR_s else
'0' when rd_state = RETRANSMIT_s else
'0' when rd_state = DATA_PRELOAD1_s else '1';
-- When the BRAM is being read, enable the read address to be incremented.
rd_addr_inc <= rd_en;
rd_addr_reload <= '1' when rd_state /= FINISH_s and rd_nxt_state = FINISH_s
else
'1' when rd_state = DROP_s and rd_nxt_state = IDLE_s
else '0';
-- Assertion indicates that the starting address must be reloaded to enable
-- the current frame to be retransmitted.
rd_start_addr_reload <= '1' when rd_state = RETRANSMIT_s else '0';
rd_start_addr_load <= '1' when rd_state= WAIT_HANDSHAKE_s and rd_nxt_state = FRAME_s
else
'1' when rd_col_window_expire = '1' else '0';
-- Transmit frame pulse must never be more frequent than once per 64 clocks to
-- allow toggle to cross clock domain.
rd_transmit_frame <= '1' when rd_state = WAIT_HANDSHAKE_s and rd_nxt_state = FRAME_s
else '0';
-- Retransmit frame pulse must never be more frequent than once per 16 clocks
-- to allow toggle to cross clock domain.
rd_retransmit_frame <= '1' when rd_state = RETRANSMIT_s else '0';
end generate gen_hd_decode; -- half duplex control signals
------------------------------------------------------------------------------
-- Frame count
-- We need to maintain a count of frames in the FIFO, so that we know when a
-- frame is available for transmission. The counter must be held on the write
-- clock domain as this is the faster clock if they differ.
------------------------------------------------------------------------------
-- A frame has been written to the FIFO.
wr_store_frame <= '1' when wr_state = EOF_s and wr_nxt_state /= EOF_s
else '0';
-- Generate a toggle to indicate when a frame has been transmitted by the FIFO.
p_rd_trans_tog : process (tx_mac_aclk)
begin
if tx_mac_aclk'event and tx_mac_aclk = '1' then
if rd_transmit_frame = '1' then
rd_tran_frame_tog <= not rd_tran_frame_tog after dly;
end if;
end if;
end process;
-- Synchronize the read transmit frame signal into the write clock domain.
resync_rd_tran_frame_tog : tri_mode_ethernet_mac_0_sync_block
port map (
clk => tx_fifo_aclk,
data_in => rd_tran_frame_tog,
data_out => wr_tran_frame_sync
);
-- Edge-detect of the resynchronized transmit frame signal.
p_delay_wr_trans : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
wr_tran_frame_delay <= wr_tran_frame_sync after dly;
end if;
end process p_delay_wr_trans;
p_sync_wr_trans : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_transmit_frame <= '0' after dly;
else
-- Edge detector
if (wr_tran_frame_delay xor wr_tran_frame_sync) = '1' then
wr_transmit_frame <= '1' after dly;
else
wr_transmit_frame <= '0' after dly;
end if;
end if;
end if;
end process p_sync_wr_trans;
------------------------------------------------------------------------------
-- Full duplex-only frame count.
gen_fd_count : if (FULL_DUPLEX_ONLY = TRUE) generate
-- Count the number of frames in the FIFO. The counter is incremented when a
-- frame is stored and decremented when a frame is transmitted. Need to keep
-- the counter on the write clock as this is the fastest clock if they differ.
p_wr_frames : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_frames <= (others => '0') after dly;
else
if (wr_store_frame and not wr_transmit_frame) = '1' then
wr_frames <= wr_frames + 1 after dly;
elsif (not wr_store_frame and wr_transmit_frame) = '1' then
wr_frames <= wr_frames - 1 after dly;
end if;
end if;
end if;
end process p_wr_frames;
end generate gen_fd_count;
------------------------------------------------------------------------------
-- Full and half duplex frame count.
gen_hd_count : if (FULL_DUPLEX_ONLY = FALSE) generate
-- Generate a toggle to indicate when a frame has been retransmitted from
-- the FIFO.
p_rd_retran_tog : process (tx_mac_aclk)
begin
if tx_mac_aclk'event and tx_mac_aclk = '1' then
if rd_retransmit_frame = '1' then
rd_retran_frame_tog <= not rd_retran_frame_tog after dly;
end if;
end if;
end process;
-- Synchronize the read retransmit frame signal into the write clock domain.
resync_rd_tran_frame_tog : tri_mode_ethernet_mac_0_sync_block
port map (
clk => tx_fifo_aclk,
data_in => rd_retran_frame_tog,
data_out => wr_retran_frame_sync
);
-- Edge detect of the resynchronized read transmit frame signal.
p_delay_wr_trans : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
wr_retran_frame_delay <= wr_retran_frame_sync after dly;
end if;
end process p_delay_wr_trans;
p_sync_wr_trans : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_retransmit_frame <= '0' after dly;
else
-- Edge detector
if (wr_retran_frame_delay xor wr_retran_frame_sync) = '1' then
wr_retransmit_frame <= '1' after dly;
else
wr_retransmit_frame <= '0' after dly;
end if;
end if;
end if;
end process p_sync_wr_trans;
-- Count the number of frames in the FIFO. The counter is incremented when a
-- frame is stored or retransmitted and decremented when a frame is
-- transmitted. Need to keep the counter on the write clock as this is the
-- fastest clock if they differ. Logic assumes transmit and retransmit cannot
-- happen at same time.
p_wr_frames : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_frames <= (others => '0') after dly;
else
if (wr_store_frame and wr_retransmit_frame) = '1' then
wr_frames <= wr_frames + 2 after dly;
elsif ((wr_store_frame or wr_retransmit_frame)
and not wr_transmit_frame) = '1' then
wr_frames <= wr_frames + 1 after dly;
elsif (wr_transmit_frame and not wr_store_frame) = '1' then
wr_frames <= wr_frames - 1 after dly;
end if;
end if;
end if;
end process p_wr_frames;
end generate gen_hd_count;
-- send wr_transmit_frame back to read domain to ensure it waits until the frame_in_fifo logic has been updated
p_delay_wr_transmit : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_transmit_frame_delay <= '0' after dly;
else
wr_transmit_frame_delay <= wr_transmit_frame after dly;
end if;
end if;
end process p_delay_wr_transmit;
p_wr_tx : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if wr_transmit_frame_delay = '1' then
frame_in_fifo_valid_tog <= not frame_in_fifo_valid_tog after dly;
end if;
end if;
end process p_wr_tx;
-- Generate a frame in FIFO signal for use in control logic.
p_wr_avail : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_frame_in_fifo <= '0' after dly;
else
if wr_frames /= (wr_frames'range => '0') then
wr_frame_in_fifo <= '1' after dly;
else
wr_frame_in_fifo <= '0' after dly;
end if;
end if;
end if;
end process p_wr_avail;
-- Generate a multiple frames in FIFO signal for use in control logic.
p_mult_wr_avail : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_frames_in_fifo <= '0' after dly;
else
if wr_frames >= "0000000010" then
wr_frames_in_fifo <= '1' after dly;
else
wr_frames_in_fifo <= '0' after dly;
end if;
end if;
end if;
end process p_mult_wr_avail;
-- Synchronize it back onto read domain for use in the read logic.
resync_wr_frame_in_fifo : tri_mode_ethernet_mac_0_sync_block
port map (
clk => tx_mac_aclk,
data_in => wr_frame_in_fifo,
data_out => frame_in_fifo
);
-- Synchronize it back onto read domain for use in the read logic.
resync_wr_frames_in_fifo : tri_mode_ethernet_mac_0_sync_block
port map (
clk => tx_mac_aclk,
data_in => wr_frames_in_fifo,
data_out => frames_in_fifo
);
-- in he case where only one frame is in the fifo we have to be careful about the faling edge of
-- the frame in fifo signal as for short frames this could occur after the state machine completes
resync_fif_valid_tog : tri_mode_ethernet_mac_0_sync_block
port map (
clk => tx_mac_aclk,
data_in => frame_in_fifo_valid_tog,
data_out => frame_in_fifo_valid_sync
);
-- Edge detect of the re-resynchronized read transmit frame signal.
p_delay_fif_valid : process (tx_mac_aclk)
begin
if tx_mac_aclk'event and tx_mac_aclk = '1' then
frame_in_fifo_valid_delay <= frame_in_fifo_valid_sync after dly;
end if;
end process p_delay_fif_valid;
p_sync_fif_valid : process (tx_mac_aclk)
begin
if tx_mac_aclk'event and tx_mac_aclk = '1' then
if tx_mac_reset = '1' then
frame_in_fifo_valid <= '1' after dly;
else
-- Edge detector
if (frame_in_fifo_valid_delay xor frame_in_fifo_valid_sync) = '1' then
frame_in_fifo_valid <= '1' after dly;
elsif rd_transmit_frame = '1' then
frame_in_fifo_valid <= '0' after dly;
end if;
end if;
end if;
end process p_sync_fif_valid;
------------------------------------------------------------------------------
-- Address counters
------------------------------------------------------------------------------
-- Write address is incremented when write enable signal has been asserted
wr_addr_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
if tx_fifo_reset = '1' then
wr_addr <= (others => '0') after dly;
elsif wr_addr_reload = '1' then
wr_addr <= wr_start_addr after dly;
elsif wr_addr_inc = '1' then
wr_addr <= wr_addr + 1 after dly;
end if;
end if;
end process wr_addr_p;
-- Store the start address in case the address must be reset.
wr_staddr_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
if tx_fifo_reset = '1' then
wr_start_addr <= (others => '0') after dly;
elsif wr_start_addr_load = '1' then
wr_start_addr <= wr_addr + 1 after dly;
end if;
end if;
end process wr_staddr_p;
------------------------------------------------------------------------------
-- Half duplex-only read address counters.
gen_fd_addr : if (FULL_DUPLEX_ONLY = TRUE) generate
-- Read address is incremented when read enable signal has been asserted.
rd_addr_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_addr <= (others => '0') after dly;
else
if rd_addr_reload = '1' then
rd_addr <= rd_dec_addr after dly;
elsif rd_addr_inc = '1' then
rd_addr <= rd_addr + 1 after dly;
end if;
end if;
end if;
end process rd_addr_p;
-- Do not need to keep a start address, but the address is needed to
-- calculate FIFO occupancy.
rd_start_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_start_addr <= (others => '0') after dly;
else
rd_start_addr <= rd_addr after dly;
end if;
end if;
end process rd_start_p;
end generate gen_fd_addr;
------------------------------------------------------------------------------
-- Full and half duplex read address counters
gen_hd_addr : if (FULL_DUPLEX_ONLY = FALSE) generate
-- Read address is incremented when read enable signal has been asserted.
rd_addr_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_addr <= (others => '0') after dly;
else
if rd_addr_reload = '1' then
rd_addr <= rd_dec_addr after dly;
elsif rd_start_addr_reload = '1' then
rd_addr <= rd_start_addr after dly;
elsif rd_addr_inc = '1' then
rd_addr <= rd_addr + 1 after dly;
end if;
end if;
end if;
end process rd_addr_p;
rd_staddr_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_start_addr <= (others => '0') after dly;
else
if rd_start_addr_load = '1' then
rd_start_addr <= rd_addr - 6 after dly;
end if;
end if;
end if;
end process rd_staddr_p;
-- Collision window expires after MAC has been transmitting for required slot
-- time. This is 512 clock cycles at 1Gbps. Also if the end of frame has fully
-- been transmitted by the MAC then a collision cannot occur. This collision
-- expiration signal goes high at 768 cycles from the start of the frame.
-- This is inefficient for short frames, however it should be enough to
-- prevent the FIFO from locking up.
rd_col_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_col_window_expire <= '0' after dly;
else
if rd_transmit_frame = '1' then
rd_col_window_expire <= '0' after dly;
elsif rd_slot_timer(9 downto 7) = "110" then
rd_col_window_expire <= '1' after dly;
end if;
end if;
end if;
end process;
rd_idle_state <= '1' when rd_state = IDLE_s else '0';
rd_colreg_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
rd_col_window_pipe(0) <= rd_col_window_expire
and rd_idle_state after dly;
if rd_txfer_en = '1' then
rd_col_window_pipe(1) <= rd_col_window_pipe(0) after dly;
end if;
end if;
end process;
rd_slot_time_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
-- Will not count until after the first frame is sent.
if tx_mac_reset = '1' then
rd_slot_timer <= "1111111111" after dly;
else
-- Reset counter.
if rd_transmit_frame = '1' then
rd_slot_timer <= (others => '0') after dly;
-- Do not allow counter to roll over, and
-- only count when frame is being transmitted.
elsif rd_slot_timer /= "1111111111" then
rd_slot_timer <= rd_slot_timer + 1 after dly;
end if;
end if;
end if;
end process;
end generate gen_hd_addr;
-- Read address generation
rd_decaddr_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_dec_addr <= (others => '0') after dly;
else
if rd_addr_inc = '1' then
rd_dec_addr <= rd_addr - 1 after dly;
end if;
end if;
end if;
end process rd_decaddr_p;
------------------------------------------------------------------------------
-- Data pipelines
------------------------------------------------------------------------------
-- Register data inputs to BRAM.
-- No resets to allow for SRL16 target.
reg_din_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
wr_data_pipe(0) <= tx_axis_fifo_tdata after dly;
if wr_accept_pipe(0) = '1' then
wr_data_pipe(1) <= wr_data_pipe(0) after dly;
end if;
if wr_accept_pipe(1) = '1' then
wr_data_bram <= wr_data_pipe(1) after dly;
end if;
end if;
end process reg_din_p;
-- Start of frame set when tvalid is asserted and previous frame has ended.
wr_sof_int <= tx_axis_fifo_tvalid and wr_eof_reg;
-- Set end of frame flag when tlast and tvalid are asserted together.
-- Reset to logic 1 to enable first frame's start of frame flag.
reg_eofreg_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
if tx_fifo_reset = '1' then
wr_eof_reg <= '1';
else
if tx_axis_fifo_tvalid = '1' and tx_axis_fifo_tready_int_n = '0' then
wr_eof_reg <= tx_axis_fifo_tlast;
end if;
end if;
end if;
end process reg_eofreg_p;
-- Pipeline the start of frame flag when the pipe is enabled.
reg_sof_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
wr_sof_pipe(0) <= wr_sof_int and not tx_axis_fifo_tlast after dly;
if wr_accept_pipe(0) = '1' then
wr_sof_pipe(1) <= wr_sof_pipe(0) after dly;
end if;
end if;
end process reg_sof_p;
-- Pipeline the pipeline enable signal, which is derived from simultaneous
-- assertion of tvalid and tready.
reg_acc_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
if (tx_fifo_reset = '1') then
wr_accept_pipe(0) <= '0' after dly;
wr_accept_pipe(1) <= '0' after dly;
wr_accept_bram <= '0' after dly;
else
wr_accept_pipe(0) <= tx_axis_fifo_tvalid and (not tx_axis_fifo_tready_int_n) and
not (tx_axis_fifo_tlast and wr_sof_int) after dly;
wr_accept_pipe(1) <= wr_accept_pipe(0) after dly;
wr_accept_bram <= wr_accept_pipe(1) after dly;
end if;
end if;
end process reg_acc_p;
-- Pipeline the end of frame flag when the pipe is enabled.
reg_eof_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
wr_eof_pipe(0) <= tx_axis_fifo_tvalid and tx_axis_fifo_tlast and not wr_sof_int after dly;
if wr_accept_pipe(0) = '1' then
wr_eof_pipe(1) <= wr_eof_pipe(0) after dly;
end if;
if wr_accept_pipe(1) = '1' then
wr_eof_bram(0) <= wr_eof_pipe(1) after dly;
end if;
end if;
end process reg_eof_p;
-- Register data outputs from BRAM.
-- No resets to allow SRL16 target.
reg_dout_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if rd_en = '1' then
rd_data_delay <= rd_data_bram after dly;
rd_data_pipe <= rd_data_delay after dly;
end if;
end if;
end process reg_dout_p;
reg_eofout_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if rd_en = '1' then
rd_eof_pipe <= rd_eof_bram(0) after dly;
rd_eof <= rd_eof_pipe after dly;
rd_eof_reg <= rd_eof or rd_eof_pipe after dly;
end if;
end if;
end process reg_eofout_p;
------------------------------------------------------------------------------
-- Half duplex-only drop and retransmission controls.
gen_hd_input : if (FULL_DUPLEX_ONLY = FALSE) generate
-- Register the collision without retransmit signal, which is a pulse that
-- causes the FIFO to drop the frame.
reg_col_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
rd_drop_frame <= tx_collision and (not tx_retransmit) after dly;
end if;
end process reg_col_p;
-- Register the collision with retransmit signal, which is a pulse that
-- causes the FIFO to retransmit the frame.
reg_retr_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
rd_retransmit <= tx_collision and tx_retransmit after dly;
end if;
end process reg_retr_p;
end generate gen_hd_input;
------------------------------------------------------------------------------
-- FIFO full functionality
------------------------------------------------------------------------------
-- Full functionality is the difference between read and write addresses.
-- We cannot use gray code this time as the read address and read start
-- addresses jump by more than 1.
-- We generate an enable pulse for the read side every 16 read clocks. This
-- provides for the worst-case situation where the write clock is 20MHz and
-- read clock is 125MHz.
p_rd_16_pulse : process (tx_mac_aclk)
begin
if tx_mac_aclk'event and tx_mac_aclk = '1' then
if tx_mac_reset = '1' then
rd_16_count <= (others => '0') after dly;
else
rd_16_count <= rd_16_count + 1 after dly;
end if;
end if;
end process;
rd_txfer_en <= '1' when rd_16_count = "1111" else '0';
-- Register the start address on the enable pulse.
p_rd_addr_txfer : process (tx_mac_aclk)
begin
if tx_mac_aclk'event and tx_mac_aclk = '1' then
if tx_mac_reset = '1' then
rd_addr_txfer <= (others => '0') after dly;
else
if rd_txfer_en = '1' then
rd_addr_txfer <= rd_start_addr after dly;
end if;
end if;
end if;
end process;
-- Generate a toggle to indicate that the address has been loaded.
p_rd_tog_txfer : process (tx_mac_aclk)
begin
if tx_mac_aclk'event and tx_mac_aclk = '1' then
if rd_txfer_en = '1' then
rd_txfer_tog <= not rd_txfer_tog after dly;
end if;
end if;
end process;
-- Synchronize the toggle to the write side.
resync_rd_txfer_tog : tri_mode_ethernet_mac_0_sync_block
port map (
clk => tx_fifo_aclk,
data_in => rd_txfer_tog,
data_out => wr_txfer_tog_sync
);
-- Delay the synchronized toggle by one cycle.
p_wr_tog_txfer : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
wr_txfer_tog_delay <= wr_txfer_tog_sync after dly;
end if;
end process;
-- Generate an enable pulse from the toggle. The address should have been
-- steady on the wr clock input for at least one clock.
wr_txfer_en <= wr_txfer_tog_delay xor wr_txfer_tog_sync;
-- Capture the address on the write clock when the enable pulse is high.
p_wr_addr_txfer : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_rd_addr <= (others => '0') after dly;
elsif wr_txfer_en = '1' then
wr_rd_addr <= rd_addr_txfer after dly;
end if;
end if;
end process;
-- Obtain the difference between write and read pointers
p_wr_addr_diff : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_addr_diff <= (others => '0') after dly;
else
wr_addr_diff <= wr_rd_addr - wr_addr after dly;
end if;
end if;
end process;
-- Detect when the FIFO is full.
-- The FIFO is considered to be full if the write address pointer is
-- within 0 to 3 of the read address pointer.
p_wr_full : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_fifo_full <= '0' after dly;
else
if wr_addr_diff(11 downto 4) = 0
and wr_addr_diff(3 downto 2) /= "00" then
wr_fifo_full <= '1' after dly;
else
wr_fifo_full <= '0' after dly;
end if;
end if;
end if;
end process p_wr_full;
-- Memory overflow occurs when the FIFO is full and there are no frames
-- available in the FIFO for transmission. If the collision window has
-- expired and there are no frames in the FIFO and the FIFO is full, then the
-- FIFO is in an overflow state. We must accept the rest of the incoming
-- frame in overflow condition.
gen_fd_ovflow : if (FULL_DUPLEX_ONLY = TRUE) generate
-- In full duplex mode, the FIFO memory can only overflow if the FIFO goes
-- full but there is no frame available to be retranmsitted. Therefore,
-- prevent signal from being asserted when store_frame signal is high, as
-- frame count is being updated.
wr_fifo_overflow <= '1' when wr_fifo_full = '1' and wr_frame_in_fifo = '0'
and wr_eof_state = '0' and wr_eof_state_reg = '0'
else '0';
-- Tie off unused half-duplex signals
wr_col_window_pipe(0) <= '0';
wr_col_window_pipe(1) <= '0';
end generate gen_fd_ovflow;
gen_hd_ovflow : if (FULL_DUPLEX_ONLY = FALSE) generate
-- In half duplex mode, register write collision window to give address
-- counter sufficient time to update. This will prevent the signal from
-- being asserted when the store_frame signal is high, as the frame count
-- is being updated.
wr_fifo_overflow <= '1' when wr_fifo_full = '1' and wr_frame_in_fifo = '0'
and wr_eof_state = '0' and wr_eof_state_reg = '0'
and wr_col_window_expire = '1'
else '0';
-- Register rd_col_window signal.
-- This signal is long, and will remain high until overflow functionality
-- has finished, so save just to register the once.
p_wr_col_expire : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_col_window_pipe(0) <= '0' after dly;
wr_col_window_pipe(1) <= '0' after dly;
wr_col_window_expire <= '0' after dly;
else
if wr_txfer_en = '1' then
wr_col_window_pipe(0) <= rd_col_window_pipe(1) after dly;
end if;
wr_col_window_pipe(1) <= wr_col_window_pipe(0) after dly;
wr_col_window_expire <= wr_col_window_pipe(1) after dly;
end if;
end if;
end process;
end generate gen_hd_ovflow;
------------------------------------------------------------------------------
-- FIFO status signals
------------------------------------------------------------------------------
-- The FIFO status is four bits which represents the occupancy of the FIFO
-- in sixteenths. To generate this signal we therefore only need to compare
-- the 4 most significant bits of the write address pointer with the 4 most
-- significant bits of the read address pointer.
p_fifo_status : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_fifo_status <= "0000" after dly;
else
if wr_addr_diff = (wr_addr_diff'range => '0') then
wr_fifo_status <= "0000" after dly;
else
wr_fifo_status(3) <= not wr_addr_diff(11) after dly;
wr_fifo_status(2) <= not wr_addr_diff(10) after dly;
wr_fifo_status(1) <= not wr_addr_diff(9) after dly;
wr_fifo_status(0) <= not wr_addr_diff(8) after dly;
end if;
end if;
end if;
end process p_fifo_status;
fifo_status <= std_logic_vector(wr_fifo_status);
------------------------------------------------------------------------------
-- Instantiate FIFO block memory
------------------------------------------------------------------------------
wr_eof_data_bram(8) <= wr_eof_bram(0);
wr_eof_data_bram(7 downto 0) <= wr_data_bram;
rd_eof_bram(0) <= rd_eof_data_bram(8);
rd_data_bram <= rd_eof_data_bram(7 downto 0);
tx_ramgen_i : tri_mode_ethernet_mac_0_bram_tdp
generic map (
DATA_WIDTH => 9,
ADDR_WIDTH => 12
)
port map (
b_dout => rd_eof_data_bram,
a_addr => std_logic_vector(wr_addr(11 downto 0)),
b_addr => std_logic_vector(rd_addr(11 downto 0)),
a_clk => tx_fifo_aclk,
b_clk => tx_mac_aclk,
a_din => wr_eof_data_bram,
b_en => rd_en,
a_rst => tx_fifo_reset,
b_rst => tx_mac_reset,
a_wr => wr_en
);
end RTL;
| mit | 781cbf2f6b733209ac5e7dcda84fac02 | 0.548057 | 3.754053 | false | false | false | false |
Caian/Minesweeper | Projeto/ram.vhd | 1 | 11,186 | -- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ram.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY ram IS
PORT
(
address_a : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
clock_a : IN STD_LOGIC := '1';
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END ram;
ARCHITECTURE SYN OF ram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
wren_b : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(7 DOWNTO 0);
q_b <= sub_wire1(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
init_file => "./ram.mif",
intended_device_family => "Cyclone II",
lpm_type => "altsyncram",
numwords_a => 2048,
numwords_b => 2048,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
widthad_a => 11,
widthad_b => 11,
width_a => 8,
width_b => 8,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
wren_a => wren_a,
clock0 => clock_a,
wren_b => wren_b,
clock1 => clock_b,
address_a => address_a,
address_b => address_b,
data_a => data_a,
data_b => data_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "5"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: ECC NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "../Ram/ram.mif"
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "4"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "4"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: INIT_FILE STRING "../Ram/ram.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: USED_PORT: address_a 0 0 11 0 INPUT NODEFVAL address_a[10..0]
-- Retrieval info: USED_PORT: address_b 0 0 11 0 INPUT NODEFVAL address_b[10..0]
-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC clock_a
-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b
-- Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL data_a[7..0]
-- Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL data_b[7..0]
-- Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL q_a[7..0]
-- Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL q_b[7..0]
-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND wren_a
-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND wren_b
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
-- Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
-- Retrieval info: CONNECT: @address_a 0 0 11 0 address_a 0 0 11 0
-- Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
-- Retrieval info: CONNECT: @address_b 0 0 11 0 address_b 0 0 11 0
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-2.0 | c011123f2569bcb5b28bee2c14a8417d | 0.659753 | 3.229215 | false | false | false | false |
lennartbublies/ecdsa | tests/tb_gf2m_divider.vhd | 1 | 6,152 | ----------------------------------------------------------------------------------------------------
-- Testbench - GF(2^M) Inversion
--
-- Autor: Lennart Bublies (inf100434)
-- Date: 22.06.2017
----------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
use ieee.math_real.all; -- for UNIFORM, TRUNC
USE std.textio.ALL;
USE work.tld_ecdsa_package.all;
ENTITY tb_gf2m_divider IS
END tb_gf2m_divider;
ARCHITECTURE behavior OF tb_gf2m_divider IS
-- Import entity e_classic_gf2m_multiplier
COMPONENT e_gf2m_classic_multiplier IS
GENERIC (
MODULO : std_logic_vector(M-1 DOWNTO 0)
);
PORT (
a_i: IN std_logic_vector(M-1 DOWNTO 0);
b_i: IN std_logic_vector(M-1 DOWNTO 0);
c_o: OUT std_logic_vector(M-1 DOWNTO 0)
);
END COMPONENT;
-- Import entity e_gf2m_divider
COMPONENT e_gf2m_divider IS
GENERIC (
MODULO : std_logic_vector(M DOWNTO 0)
);
PORT(
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
g_i: IN std_logic_vector(M-1 DOWNTO 0);
h_i: IN std_logic_vector(M-1 DOWNTO 0);
z_o: OUT std_logic_vector(M-1 DOWNTO 0);
ready_o: OUT std_logic
);
end COMPONENT;
-- Internal signals
SIGNAL x, y, z, z_by_y : std_logic_vector(M-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL clk, reset, start, done: std_logic;
CONSTANT ZERO: std_logic_vector(M-1 DOWNTO 0) := (OTHERS=>'0');
CONSTANT DELAY : time := 100 ns;
CONSTANT PERIOD : time := 200 ns;
CONSTANT DUTY_CYCLE : real := 0.5;
CONSTANT OFFSET : time := 0 ns;
CONSTANT NUMBER_TESTS: natural := 20;
BEGIN
-- Instantiate divider entity to compute z=x/y
uut1: e_gf2m_divider GENERIC MAP (
MODULO => P
) PORT MAP(
clk_i => clk,
rst_i => reset,
enable_i => start,
g_i => x,
h_i => y,
z_o => z,
ready_o => done
);
-- Instantiate multiplier entity to compute z*y=x
uut2: e_gf2m_classic_multiplier GENERIC MAP (
MODULO => P(M-1 DOWNTO 0)
) PORT MAP(
a_i => z,
b_i => y,
c_o => z_by_y
);
-- Clock process for clk
PROCESS
BEGIN
WAIT for OFFSET;
CLOCK_LOOP : LOOP
clk <= '0';
WAIT FOR (PERIOD *(1.0 - DUTY_CYCLE));
clk <= '1';
WAIT FOR (PERIOD * DUTY_CYCLE);
END LOOP CLOCK_LOOP;
END PROCESS;
-- Start test cases
tb : PROCESS
PROCEDURE gen_random(X : OUT std_logic_vector (M-1 DOWNTO 0); w: natural; s1, s2: inout Natural) IS
VARIABLE i_x, aux: integer;
VARIABLE rand: real;
BEGIN
aux := W/16;
FOR i IN 1 TO aux LOOP
UNIFORM(s1, s2, rand);
i_x := INTEGER(TRUNC(rand * real(65536)));-- real(2**16)));
x(i*16-1 DOWNTO (i-1)*16) := CONV_STD_LOGIC_VECTOR (i_x, 16);
END LOOP;
UNIFORM(s1, s2, rand);
i_x := INTEGER(TRUNC(rand * real(2**(w-aux*16))));
x(w-1 DOWNTO aux*16) := CONV_STD_LOGIC_VECTOR (i_x, (w-aux*16));
END PROCEDURE;
VARIABLE TX_LOC : LINE;
VARIABLE TX_STR : String(1 to 4096);
VARIABLE seed1, seed2: positive;
VARIABLE i_x, i_y, i_p, i_z, i_yz_modp: integer;
VARIABLE cycles, max_cycles, min_cycles, total_cycles: integer := 0;
VARIABLE avg_cycles: real;
VARIABLE initial_time, final_time: time;
VARIABLE xx: std_logic_vector (M-1 DownTo 0) ;
BEGIN
min_cycles:= 2**20;
start <= '0'; reset <= '1';
WAIT FOR PERIOD;
reset <= '0';
WAIT FOR PERIOD;
for I in 1 to NUMBER_TESTS LOOP
-- Generate random number for x and y
gen_random(xx, M, seed1, seed2);
x <= xx;
gen_random(xx, M, seed1, seed2);
while (xx = ZERO) LOOP
gen_random(xx, M, seed1, seed2);
END LOOP;
y <= xx;
-- Count runtime
start <= '1'; initial_time := now;
WAIT FOR PERIOD;
start <= '0';
wait until done = '1';
final_time := now;
cycles := (final_time - initial_time)/PERIOD;
total_cycles := total_cycles+cycles;
--ASSERT (FALSE) REPORT "Number of Cycles: " & integer'image(cycles) & " TotalCycles: " & integer'image(total_cycles) SEVERITY WARNING;
IF cycles > max_cycles THEN
max_cycles:= cycles;
END IF;
IF cycles < min_cycles THEN
min_cycles:= cycles;
END IF;
WAIT FOR 2*PERIOD;
-- Check if c=a/b and c*b=a
IF ( x /= z_by_y ) THEN
write(TX_LOC,string'("ERROR!!! z_by_y=")); write(TX_LOC, z_by_y);
write(TX_LOC,string'("/= x=")); write(TX_LOC, x);
write(TX_LOC,string'("( z=")); write(TX_LOC, z);
write(TX_LOC,string'(") using: ( A =")); write(TX_LOC, x);
write(TX_LOC, string'(", B =")); write(TX_LOC, y);
write(TX_LOC, string'(" )"));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
END IF;
END LOOP;
WAIT FOR DELAY;
-- Report results
avg_cycles := real(total_cycles)/real(NUMBER_TESTS);
ASSERT (FALSE) REPORT
"Simulation successful!. MinCycles: " & integer'image(min_cycles) &
" MaxCycles: " & integer'image(max_cycles) & " TotalCycles: " & integer'image(total_cycles) &
" AvgCycles: " & real'image(avg_cycles)
SEVERITY FAILURE;
END PROCESS;
END;
| gpl-3.0 | 7ed1b8f4b766809e12332c77ba707670 | 0.496912 | 3.666269 | false | false | false | false |
Caian/Minesweeper | Projeto/gfx.vhd | 1 | 6,370 | -- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: gfx.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY gfx IS
PORT
(
address : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END gfx;
ARCHITECTURE SYN OF gfx IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(3 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "./gfx.mif",
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 16384,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
widthad_a => 14,
width_a => 4,
width_byteena_a => 1
)
PORT MAP (
clock0 => clock,
address_a => address,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "../Gfx/gfx.hex"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "16384"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "14"
-- Retrieval info: PRIVATE: WidthData NUMERIC "4"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "../Gfx/gfx.hex"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 14 0 INPUT NODEFVAL address[13..0]
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock
-- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL q[3..0]
-- Retrieval info: CONNECT: @address_a 0 0 14 0 address 0 0 14 0
-- Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL gfx.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gfx.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gfx.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gfx.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gfx_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gfx_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gfx_wave*.jpg FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gfx_syn.v TRUE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-2.0 | c53b12be015e51ade2bd9889c5b79ced | 0.651805 | 3.521282 | false | false | false | false |
CEIT-Laboratories/Arch-Lab | AUT-MIPS/memory.vhd | 1 | 1,435 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 30-03-2016
-- Module Name: memory.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity memory is
port (address : in std_logic_vector (15 downto 0);
data_in : in std_logic_vector (15 downto 0);
data_out : out std_logic_vector (15 downto 0);
clk, read, write : in std_logic);
end entity;
architecture behavioral of memory is
type mem is array (natural range <>) of std_logic_vector (15 downto 0);
begin
process (clk)
constant memsize : integer := 2 ** 16;
variable memory : mem (0 to memsize - 1) := (
"0011000000000010",
"0011001001000010",
"1111000001010111",
"1111000001011110",
"1111000001100101",
"1111000001101100",
"1111000001110011",
"1111000001111010",
"0111000001000011",
"1000000001001100",
"1001000000111111",
"1010000000011010",
"0000000000000000",
"0000000000000010",
others => "0000000000000000"
);
begin
if clk'event and clk = '1' then
if read = '1' then -- Reading :)
data_out <= memory(to_integer(unsigned(address)));
elsif write = '1' then -- Writing :)
memory(to_integer(unsigned(address))) := data_in;
end if;
end if;
end process;
end architecture behavioral;
| gpl-3.0 | 7f3e53cbe5e9182dc23cb9a349207cdd | 0.595122 | 3.688946 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/temac_testbench_source/sources_1/imports/example_design/common/tri_mode_ethernet_mac_0_sync_block.vhd | 5 | 5,676 | --------------------------------------------------------------------------------
-- Title : CDC Sync Block
-- Project : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_sync_block.vhd
-- Author : Xilinx Inc.
--------------------------------------------------------------------------------
-- Description: Used on signals crossing from one clock domain to another, this
-- is a multiple flip-flop pipeline, with all flops placed together
-- into the same slice. Thus the routing delay between the two is
-- minimum to safe-guard against metastability issues.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity tri_mode_ethernet_mac_0_sync_block is
generic (
INITIALISE : bit := '0';
DEPTH : integer := 5
);
port (
clk : in std_logic; -- clock to be sync'ed to
data_in : in std_logic; -- Data to be 'synced'
data_out : out std_logic -- synced data
);
attribute dont_touch : string;
attribute dont_touch of tri_mode_ethernet_mac_0_sync_block : entity is "yes";
end tri_mode_ethernet_mac_0_sync_block;
architecture structural of tri_mode_ethernet_mac_0_sync_block is
-- Internal Signals
signal data_sync0 : std_logic;
signal data_sync1 : std_logic;
signal data_sync2 : std_logic;
signal data_sync3 : std_logic;
signal data_sync4 : std_logic;
-- These attributes will stop timing errors being reported in back annotated
-- SDF simulation.
attribute async_reg : string;
attribute async_reg of data_sync_reg0 : label is "true";
attribute async_reg of data_sync_reg1 : label is "true";
attribute async_reg of data_sync_reg2 : label is "true";
attribute async_reg of data_sync_reg3 : label is "true";
attribute async_reg of data_sync_reg4 : label is "true";
attribute shreg_extract : string;
attribute shreg_extract of data_sync_reg0 : label is "no";
attribute shreg_extract of data_sync_reg1 : label is "no";
attribute shreg_extract of data_sync_reg2 : label is "no";
attribute shreg_extract of data_sync_reg3 : label is "no";
attribute shreg_extract of data_sync_reg4 : label is "no";
begin
data_sync_reg0 : FDRE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
D => data_in,
Q => data_sync0,
CE => '1',
R => '0'
);
data_sync_reg1 : FDRE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
D => data_sync0,
Q => data_sync1,
CE => '1',
R => '0'
);
data_sync_reg2 : FDRE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
D => data_sync1,
Q => data_sync2,
CE => '1',
R => '0'
);
data_sync_reg3 : FDRE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
D => data_sync2,
Q => data_sync3,
CE => '1',
R => '0'
);
data_sync_reg4 : FDRE
generic map (
INIT => INITIALISE
)
port map (
C => clk,
D => data_sync3,
Q => data_sync4,
CE => '1',
R => '0'
);
data_out <= data_sync4;
end structural;
| mit | 8fdfa1dd650b62b427acd2ac58c47660 | 0.61487 | 4.039858 | false | false | false | false |
lfmunoz/4dsp_sip_interface | stellar_cmd.vhd | 1 | 12,485 | --------------------------------------------------------------------------------
-- file name : glb_stellar_cmd.vhd
--
-- author : e. barhorst
--
-- company : 4dsp
--
-- item : number
--
-- units : entity
-- arch_itecture
--
-- language : vhdl
--
--------------------------------------------------------------------------------
-- description
-- ===========
--
--
-- notes:
--------------------------------------------------------------------------------
--
-- disclaimer: limited warranty and disclaimer. these designs are
-- provided to you as is. 4dsp specifically disclaims any
-- implied warranties of merchantability, non-infringement, or
-- fitness for a particular purpose. 4dsp does not warrant that
-- the functions contained in these designs will meet your
-- requirements, or that the operation of these designs will be
-- uninterrupted or error free, or that defects in the designs
-- will be corrected. furthermore, 4dsp does not warrant or
-- make any representations regarding use or the results of the
-- use of the designs in terms of correctness, accuracy,
-- reliability, or otherwise.
--
-- limitation of liability. in no event will 4dsp or its
-- licensors be liable for any loss of data, lost profits, cost
-- or procurement of substitute goods or services, or for any
-- special, incidental, consequential, or indirect damages
-- arising from the use or operation of the designs or
-- accompanying documentation, however caused and on any theory
-- of liability. this limitation will apply even if 4dsp
-- has been advised of the possibility of such damage. this
-- limitation shall apply not-withstanding the failure of the
-- essential purpose of any limited remedies herein.
--
-- from
-- ver pcb mod date changes
-- === ======= ======== =======
--
-- 0.0 0 19-01-2009 new version
-- 31-08-2009 added the mailbox input port
----------------------------------------------
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Specify libraries
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
--------------------------------------------------------------------------------
-- Entity declaration
--------------------------------------------------------------------------------
entity stellar_cmd is
generic (
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"0000010"
);
port (
reset : in std_logic;
-- Command interface
clk_cmd : in std_logic; --cmd_in and cmd_out are synchronous to this clock;
out_cmd : out std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
in_cmd : in std_logic_vector(63 downto 0);
in_cmd_val : in std_logic;
cmd_always_ack : in std_logic;
-- Register interface
clk_reg : in std_logic; --register interface is synchronous to this clock
out_reg : out std_logic_vector(31 downto 0);--caries the out register data
out_reg_val : out std_logic; --the out_reg has valid data (pulse)
out_reg_val_ack : out std_logic; --the out_reg has valid data and expects and acknowledge back (pulse)
out_reg_addr : out std_logic_vector(27 downto 0);--out register address
in_reg : in std_logic_vector(31 downto 0);--requested register data is placed on this bus
in_reg_val : in std_logic; --pulse to indicate requested register is valid
in_reg_req : out std_logic; --pulse to request data
in_reg_addr : out std_logic_vector(27 downto 0);--requested address
--write acknowledge interface
wr_ack : in std_logic := '0'; --pulse to indicate write is done
-- Mailbox interface
mbx_in_reg : in std_logic_vector(31 downto 0);--value of the mailbox to send
mbx_in_val : in std_logic --pulse to indicate mailbox is valid
);
end entity stellar_cmd;
--------------------------------------------------------------------------------
-- Architecture declaration
--------------------------------------------------------------------------------
architecture arch_stellar_cmd of stellar_cmd is
-----------------------------------------------------------------------------------
-- Constant declarations
-----------------------------------------------------------------------------------
constant CMD_WR : std_logic_vector(3 downto 0) := x"1";
constant CMD_RD : std_logic_vector(3 downto 0) := x"2";
constant CMD_RD_ACK : std_logic_vector(3 downto 0) := x"4";
constant CMD_WR_ACK : std_logic_vector(3 downto 0) := x"5";
constant CMD_WR_EXPECTS_ACK : std_logic_vector(3 downto 0) := x"6";
-----------------------------------------------------------------------------------
-- Dignal declarations
-----------------------------------------------------------------------------------
signal register_wr : std_logic;
signal register_wr_ack : std_logic;
signal register_rd : std_logic;
signal out_cmd_val_sig : std_logic;
signal in_reg_addr_sig : std_logic_vector(27 downto 0);
signal out_reg_addr_sig : std_logic_vector(27 downto 0);
signal mbx_in_val_sig : std_logic;
signal mbx_received : std_logic;
signal wr_ack_sig : std_logic;
-----------------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------------
component pulse2pulse
port (
in_clk : in std_logic;
out_clk : in std_logic;
rst : in std_logic;
pulsein : in std_logic;
inbusy : out std_logic;
pulseout : out std_logic
);
end component;
-----------------------------------------------------------------------------------
-- Begin
-----------------------------------------------------------------------------------
begin
-----------------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------------
p2p0: pulse2pulse
port map (
in_clk => clk_cmd,
out_clk => clk_reg,
rst => reset,
pulsein => register_wr,
inbusy => open,
pulseout => out_reg_val
);
p2p1: pulse2pulse
port map (
in_clk => clk_cmd,
out_clk => clk_reg,
rst => reset,
pulsein => register_rd,
inbusy => open,
pulseout => in_reg_req
);
p2p2: pulse2pulse
port map (
in_clk => clk_reg,
out_clk => clk_cmd,
rst => reset,
pulsein => in_reg_val,
inbusy => open,
pulseout => out_cmd_val_sig
);
p2p3: pulse2pulse
port map (
in_clk => clk_reg,
out_clk => clk_cmd ,
rst => reset,
pulsein => mbx_in_val,
inbusy => open,
pulseout => mbx_in_val_sig
);
p2p4: pulse2pulse
port map (
in_clk => clk_reg,
out_clk => clk_cmd ,
rst => reset,
pulsein => wr_ack,
inbusy => open,
pulseout => wr_ack_sig
);
p2p5: pulse2pulse
port map (
in_clk => clk_cmd,
out_clk => clk_reg,
rst => reset,
pulsein => register_wr_ack,
inbusy => open,
pulseout => out_reg_val_ack
);
-----------------------------------------------------------------------------------
-- Synchronous processes
-----------------------------------------------------------------------------------
in_reg_proc: process (reset, clk_cmd)
begin
if (reset = '1') then
in_reg_addr_sig <= (others => '0');
register_rd <= '0';
mbx_received <= '0';
out_cmd <= (others => '0');
out_cmd_val <= '0';
elsif (clk_cmd'event and clk_cmd = '1') then
--register the requested address when the address is in the modules range
if (in_cmd_val = '1' and in_cmd(63 downto 60) = CMD_RD and in_cmd(59 downto 32) >= start_addr and in_cmd(59 downto 32) <= stop_addr) then
in_reg_addr_sig <= in_cmd(59 downto 32)-start_addr;
end if;
--generate the read req pulse when the address is in the modules range
if ((in_cmd_val = '1' and in_cmd(63 downto 60) = CMD_RD and in_cmd(59 downto 32) >= start_addr and in_cmd(59 downto 32) <= stop_addr) or cmd_always_ack = '1') then
register_rd <= '1';
else
register_rd <= '0';
end if;
--mailbox has less priority then command acknowledge
--create the output packet
if (out_cmd_val_sig = '1' and mbx_in_val_sig = '1') then
mbx_received <= '1';
elsif( mbx_received = '1' and out_cmd_val_sig = '0') then
mbx_received <= '0';
end if;
if (out_cmd_val_sig = '1') then
out_cmd(31 downto 0) <= in_reg;
out_cmd(59 downto 32) <= in_reg_addr_sig+start_addr;
out_cmd(63 downto 60) <= CMD_RD_ACK;
elsif (mbx_in_val_sig = '1' or mbx_received = '1') then
out_cmd(31 downto 0) <= mbx_in_reg;
out_cmd(59 downto 32) <= start_addr;
out_cmd(63 downto 60) <= (others=>'0');
elsif (wr_ack_sig = '1' ) then
out_cmd(31 downto 0) <= mbx_in_reg;
out_cmd(59 downto 32) <= out_reg_addr_sig+start_addr;
out_cmd(63 downto 60) <= CMD_WR_ACK;
else
out_cmd(63 downto 0) <= (others=>'0');
end if;
if (out_cmd_val_sig = '1') then
out_cmd_val <= '1';
elsif (mbx_in_val_sig = '1' or mbx_received = '1') then
out_cmd_val <= '1';
elsif (wr_ack_sig = '1') then
out_cmd_val <= '1';
else
out_cmd_val <= '0';
end if;
end if;
end process;
out_reg_proc: process(reset, clk_cmd)
begin
if (reset = '1') then
out_reg_addr_sig <= (others => '0');
out_reg <= (others => '0');
register_wr <= '0';
register_wr_ack <= '0';
elsif(clk_cmd'event and clk_cmd = '1') then
--register the requested address when the address is in the modules range
if (in_cmd_val = '1' and (in_cmd(63 downto 60) = CMD_WR or in_cmd(63 downto 60) = CMD_WR_EXPECTS_ACK)
and in_cmd(59 downto 32) >= start_addr and in_cmd(59 downto 32) <= stop_addr) then
out_reg_addr_sig <= in_cmd(59 downto 32) - start_addr;
out_reg <= in_cmd(31 downto 0);
end if;
--generate the write req pulse when the address is in the modules range
if (in_cmd_val = '1' and (in_cmd(63 downto 60) = CMD_WR or in_cmd(63 downto 60) = CMD_WR_EXPECTS_ACK)
and in_cmd(59 downto 32) >= start_addr and in_cmd(59 downto 32) <= stop_addr) then
register_wr <= '1';
else
register_wr <= '0';
end if;
--generate the write requests ack pulse when the address is in the modules range and command is write that expects an ack
if (in_cmd_val = '1' and in_cmd(63 downto 60) = CMD_WR_EXPECTS_ACK and in_cmd(59 downto 32) >= start_addr and in_cmd(59 downto 32) <= stop_addr) then
register_wr_ack <= '1';
else
register_wr_ack <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------------
-- Asynchronous mapping
-----------------------------------------------------------------------------------
in_reg_addr <= in_reg_addr_sig;
out_reg_addr <= out_reg_addr_sig;
-----------------------------------------------------------------------------------
-- End
-----------------------------------------------------------------------------------
end architecture arch_stellar_cmd;
| mit | 0fcd9542c3bd7ee6c5f5906e431d33c1 | 0.463116 | 4.017053 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_1/fifo_generator_1_funcsim.vhdl | 1 | 208,595 | -- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (win64) Build 881834 Fri Apr 4 14:15:54 MDT 2014
-- Date : Thu Jul 24 13:39:23 2014
-- Host : CE-2013-124 running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim
-- D:/SHS/Research/AutoEnetGway/Mine/xc702/aes_xc702/aes_xc702.srcs/sources_1/ip/fifo_generator_1/fifo_generator_1_funcsim.vhdl
-- Design : fifo_generator_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_1blk_mem_gen_prim_wrapper is
port (
DOUTB : out STD_LOGIC_VECTOR ( 35 downto 0 );
clk : in STD_LOGIC;
ENB : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRB : in STD_LOGIC_VECTOR ( 5 downto 0 );
ADDRA : in STD_LOGIC_VECTOR ( 5 downto 0 );
din : in STD_LOGIC_VECTOR ( 35 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_1blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end fifo_generator_1blk_mem_gen_prim_wrapper;
architecture STRUCTURE of fifo_generator_1blk_mem_gen_prim_wrapper is
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "SDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 0,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(13) => '0',
ADDRARDADDR(12) => '0',
ADDRARDADDR(11) => '0',
ADDRARDADDR(10 downto 5) => ADDRB(5 downto 0),
ADDRARDADDR(4) => '0',
ADDRARDADDR(3) => '0',
ADDRARDADDR(2) => '0',
ADDRARDADDR(1) => '0',
ADDRARDADDR(0) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10 downto 5) => ADDRA(5 downto 0),
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CLKARDCLK => clk,
CLKBWRCLK => clk,
DIADI(15 downto 8) => din(16 downto 9),
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(15 downto 8) => din(34 downto 27),
DIBDI(7 downto 0) => din(25 downto 18),
DIPADIP(1) => din(17),
DIPADIP(0) => din(8),
DIPBDIP(1) => din(35),
DIPBDIP(0) => din(26),
DOADO(15 downto 8) => DOUTB(16 downto 9),
DOADO(7 downto 0) => DOUTB(7 downto 0),
DOBDO(15 downto 8) => DOUTB(34 downto 27),
DOBDO(7 downto 0) => DOUTB(25 downto 18),
DOPADOP(1) => DOUTB(17),
DOPADOP(0) => DOUTB(8),
DOPBDOP(1) => DOUTB(35),
DOPBDOP(0) => DOUTB(26),
ENARDEN => ENB,
ENBWREN => E(0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => Q(0),
RSTRAMB => Q(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(3) => E(0),
WEBWE(2) => E(0),
WEBWE(1) => E(0),
WEBWE(0) => E(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_1blk_mem_gen_prim_wrapper__parameterized0\ is
port (
DOUTB : out STD_LOGIC_VECTOR ( 57 downto 0 );
ENB : in STD_LOGIC;
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRB : in STD_LOGIC_VECTOR ( 5 downto 0 );
ADDRA : in STD_LOGIC_VECTOR ( 5 downto 0 );
din : in STD_LOGIC_VECTOR ( 57 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_1blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper";
end \fifo_generator_1blk_mem_gen_prim_wrapper__parameterized0\;
architecture STRUCTURE of \fifo_generator_1blk_mem_gen_prim_wrapper__parameterized0\ is
signal \n_12_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\ : STD_LOGIC;
signal \n_20_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\ : STD_LOGIC;
signal \n_36_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\ : STD_LOGIC;
signal \n_44_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\ : STD_LOGIC;
signal \n_4_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\ : STD_LOGIC;
signal \n_52_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\ : STD_LOGIC;
signal \n_68_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\ : STD_LOGIC;
signal \n_69_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\ : STD_LOGIC;
signal \n_70_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\ : STD_LOGIC;
signal \n_71_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\ : STD_LOGIC;
signal \n_72_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\ : STD_LOGIC;
signal \n_73_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\ : STD_LOGIC;
signal \n_74_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\ : STD_LOGIC;
signal \n_75_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "SDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 72,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 0,
WRITE_WIDTH_B => 72
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14) => '0',
ADDRARDADDR(13) => '0',
ADDRARDADDR(12) => '0',
ADDRARDADDR(11 downto 6) => ADDRB(5 downto 0),
ADDRARDADDR(5) => '1',
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11 downto 6) => ADDRA(5 downto 0),
ADDRBWRADDR(5) => '1',
ADDRBWRADDR(4) => '1',
ADDRBWRADDR(3) => '1',
ADDRBWRADDR(2) => '1',
ADDRBWRADDR(1) => '1',
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30 downto 24) => din(28 downto 22),
DIADI(23) => '0',
DIADI(22 downto 16) => din(21 downto 15),
DIADI(15) => '0',
DIADI(14 downto 0) => din(14 downto 0),
DIBDI(31) => '0',
DIBDI(30 downto 24) => din(57 downto 51),
DIBDI(23) => '0',
DIBDI(22 downto 16) => din(50 downto 44),
DIBDI(15) => '0',
DIBDI(14 downto 0) => din(43 downto 29),
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31) => \n_4_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\,
DOADO(30 downto 24) => DOUTB(28 downto 22),
DOADO(23) => \n_12_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\,
DOADO(22 downto 16) => DOUTB(21 downto 15),
DOADO(15) => \n_20_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\,
DOADO(14 downto 0) => DOUTB(14 downto 0),
DOBDO(31) => \n_36_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\,
DOBDO(30 downto 24) => DOUTB(57 downto 51),
DOBDO(23) => \n_44_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\,
DOBDO(22 downto 16) => DOUTB(50 downto 44),
DOBDO(15) => \n_52_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\,
DOBDO(14 downto 0) => DOUTB(43 downto 29),
DOPADOP(3) => \n_68_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\,
DOPADOP(2) => \n_69_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\,
DOPADOP(1) => \n_70_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\,
DOPADOP(0) => \n_71_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\,
DOPBDOP(3) => \n_72_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\,
DOPBDOP(2) => \n_73_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\,
DOPBDOP(1) => \n_74_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\,
DOPBDOP(0) => \n_75_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENB,
ENBWREN => E(0),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => Q(0),
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => E(0),
WEBWE(6) => E(0),
WEBWE(5) => E(0),
WEBWE(4) => E(0),
WEBWE(3) => E(0),
WEBWE(2) => E(0),
WEBWE(1) => E(0),
WEBWE(0) => E(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_1rd_bin_cntr is
port (
O1 : out STD_LOGIC;
O2 : out STD_LOGIC;
O3 : out STD_LOGIC_VECTOR ( 5 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 5 downto 0 );
I2 : in STD_LOGIC;
p_18_out : in STD_LOGIC;
I3 : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_1rd_bin_cntr : entity is "rd_bin_cntr";
end fifo_generator_1rd_bin_cntr;
architecture STRUCTURE of fifo_generator_1rd_bin_cntr is
signal \^o2\ : STD_LOGIC;
signal \^o3\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal n_0_ram_empty_fb_i_i_2 : STD_LOGIC;
signal n_0_ram_empty_fb_i_i_3 : STD_LOGIC;
signal n_0_ram_full_i_i_6 : STD_LOGIC;
signal n_0_ram_full_i_i_7 : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 5 downto 0 );
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair3";
attribute counter : integer;
attribute counter of \gc0.count_reg[0]\ : label is 2;
attribute counter of \gc0.count_reg[1]\ : label is 2;
attribute counter of \gc0.count_reg[2]\ : label is 2;
attribute counter of \gc0.count_reg[3]\ : label is 2;
attribute counter of \gc0.count_reg[4]\ : label is 2;
attribute counter of \gc0.count_reg[5]\ : label is 2;
begin
O2 <= \^o2\;
O3(5 downto 0) <= \^o3\(5 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rd_pntr_plus1(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rd_pntr_plus1(0),
I1 => rd_pntr_plus1(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => rd_pntr_plus1(2),
I1 => rd_pntr_plus1(0),
I2 => rd_pntr_plus1(1),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => rd_pntr_plus1(1),
I1 => rd_pntr_plus1(0),
I2 => rd_pntr_plus1(2),
I3 => rd_pntr_plus1(3),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => rd_pntr_plus1(4),
I1 => rd_pntr_plus1(1),
I2 => rd_pntr_plus1(0),
I3 => rd_pntr_plus1(2),
I4 => rd_pntr_plus1(3),
O => plusOp(4)
);
\gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => rd_pntr_plus1(5),
I1 => rd_pntr_plus1(3),
I2 => rd_pntr_plus1(2),
I3 => rd_pntr_plus1(0),
I4 => rd_pntr_plus1(1),
I5 => rd_pntr_plus1(4),
O => plusOp(5)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(0),
Q => \^o3\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(1),
Q => \^o3\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(2),
Q => \^o3\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(3),
Q => \^o3\(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(4),
Q => \^o3\(4)
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(5),
Q => \^o3\(5)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => plusOp(0),
PRE => Q(0),
Q => rd_pntr_plus1(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => plusOp(1),
Q => rd_pntr_plus1(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => plusOp(2),
Q => rd_pntr_plus1(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => plusOp(3),
Q => rd_pntr_plus1(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => plusOp(4),
Q => rd_pntr_plus1(4)
);
\gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => Q(0),
D => plusOp(5),
Q => rd_pntr_plus1(5)
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FF000000FFFF0808"
)
port map (
I0 => n_0_ram_empty_fb_i_i_2,
I1 => n_0_ram_empty_fb_i_i_3,
I2 => I2,
I3 => \^o2\,
I4 => p_18_out,
I5 => I3(0),
O => O1
);
ram_empty_fb_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => rd_pntr_plus1(3),
I1 => I1(3),
I2 => rd_pntr_plus1(5),
I3 => I1(5),
I4 => I1(4),
I5 => rd_pntr_plus1(4),
O => n_0_ram_empty_fb_i_i_2
);
ram_empty_fb_i_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => rd_pntr_plus1(2),
I1 => I1(2),
I2 => rd_pntr_plus1(1),
I3 => I1(1),
I4 => I1(0),
I5 => rd_pntr_plus1(0),
O => n_0_ram_empty_fb_i_i_3
);
ram_full_i_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"BEFFFFBEFFFFFFFF"
)
port map (
I0 => n_0_ram_full_i_i_6,
I1 => \^o3\(2),
I2 => I1(2),
I3 => \^o3\(3),
I4 => I1(3),
I5 => n_0_ram_full_i_i_7,
O => \^o2\
);
ram_full_i_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => \^o3\(0),
I1 => I1(0),
I2 => \^o3\(1),
I3 => I1(1),
O => n_0_ram_full_i_i_6
);
ram_full_i_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^o3\(5),
I1 => I1(5),
I2 => \^o3\(4),
I3 => I1(4),
O => n_0_ram_full_i_i_7
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_1rd_fwft is
port (
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
O1 : out STD_LOGIC_VECTOR ( 0 to 0 );
ENB : out STD_LOGIC;
O2 : out STD_LOGIC;
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
p_18_out : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_1rd_fwft : entity is "rd_fwft";
end fifo_generator_1rd_fwft;
architecture STRUCTURE of fifo_generator_1rd_fwft is
signal curr_fwft_state : STD_LOGIC_VECTOR ( 0 to 0 );
signal empty_fwft_fb : STD_LOGIC;
signal empty_fwft_i0 : STD_LOGIC;
signal \n_0_gpregsm1.curr_fwft_state[1]_i_1\ : STD_LOGIC;
signal \n_0_gpregsm1.curr_fwft_state_reg[1]\ : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 0 to 0 );
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of empty_fwft_fb_reg : label is "no";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of empty_fwft_i_i_1 : label is "soft_lutpair1";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute SOFT_HLUTNM of \gc0.count_d1[5]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \goreg_bm.dout_i[93]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gpregsm1.curr_fwft_state[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gpregsm1.curr_fwft_state[1]_i_1\ : label is "soft_lutpair0";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute SOFT_HLUTNM of ram_empty_fb_i_i_4 : label is "soft_lutpair2";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAFFBF"
)
port map (
I0 => Q(0),
I1 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
I2 => curr_fwft_state(0),
I3 => rd_en,
I4 => p_18_out,
O => ENB
);
empty_fwft_fb_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_i0,
PRE => Q(1),
Q => empty_fwft_fb
);
empty_fwft_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"CF08"
)
port map (
I0 => rd_en,
I1 => curr_fwft_state(0),
I2 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
I3 => empty_fwft_fb,
O => empty_fwft_i0
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => empty_fwft_i0,
PRE => Q(1),
Q => empty
);
\gc0.count_d1[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4555"
)
port map (
I0 => p_18_out,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
O => E(0)
);
\goreg_bm.dout_i[93]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"A2"
)
port map (
I0 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
I1 => curr_fwft_state(0),
I2 => rd_en,
O => O1(0)
);
\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
I1 => curr_fwft_state(0),
I2 => rd_en,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"40FF"
)
port map (
I0 => rd_en,
I1 => curr_fwft_state(0),
I2 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
I3 => p_18_out,
O => \n_0_gpregsm1.curr_fwft_state[1]_i_1\
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => Q(1),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => Q(1),
D => \n_0_gpregsm1.curr_fwft_state[1]_i_1\,
Q => \n_0_gpregsm1.curr_fwft_state_reg[1]\
);
ram_empty_fb_i_i_4: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
I1 => curr_fwft_state(0),
I2 => rd_en,
O => O2
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_1rd_status_flags_ss is
port (
p_18_out : out STD_LOGIC;
I1 : in STD_LOGIC;
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_1rd_status_flags_ss : entity is "rd_status_flags_ss";
end fifo_generator_1rd_status_flags_ss;
architecture STRUCTURE of fifo_generator_1rd_status_flags_ss is
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
begin
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => I1,
PRE => Q(0),
Q => p_18_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_1reset_blk_ramfifo is
port (
AR : out STD_LOGIC_VECTOR ( 0 to 0 );
rst_d2 : out STD_LOGIC;
O1 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
clk : in STD_LOGIC;
rst : in STD_LOGIC;
p_1_out : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_1reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end fifo_generator_1reset_blk_ramfifo;
architecture STRUCTURE of fifo_generator_1reset_blk_ramfifo is
signal \n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\ : STD_LOGIC;
signal \n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\ : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_asreg_d1 : STD_LOGIC;
signal rd_rst_asreg_d2 : STD_LOGIC;
signal rst_d1 : STD_LOGIC;
signal \^rst_d2\ : STD_LOGIC;
signal rst_d3 : STD_LOGIC;
signal rst_full_gen_i : STD_LOGIC;
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_asreg_d1 : STD_LOGIC;
signal wr_rst_asreg_d2 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg\ : label is "true";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg\ : label is "true";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : label is "true";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg\ : label is "true";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg\ : label is "true";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : label is "true";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
begin
rst_d2 <= \^rst_d2\;
\grstd1.grst_full.grst_f.RST_FULL_GEN_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => rst,
D => rst_d3,
Q => rst_full_gen_i
);
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => rst_d1,
PRE => rst,
Q => \^rst_d2\
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \^rst_d2\,
PRE => rst,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rd_rst_asreg,
Q => rd_rst_asreg_d1,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rd_rst_asreg_d1,
Q => rd_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
port map (
C => clk,
CE => rd_rst_asreg_d1,
D => '0',
PRE => rst,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_rst_asreg,
I1 => rd_rst_asreg_d2,
O => \n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\,
Q => Q(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\,
Q => Q(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => wr_rst_asreg,
Q => wr_rst_asreg_d1,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => wr_rst_asreg_d1,
Q => wr_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
port map (
C => clk,
CE => wr_rst_asreg_d1,
D => '0',
PRE => rst,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_rst_asreg,
I1 => wr_rst_asreg_d2,
O => \n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\,
Q => AR(0)
);
ram_full_i_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => rst_full_gen_i,
I1 => p_1_out,
O => O1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_1wr_bin_cntr is
port (
ram_full_comb : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
ADDRB : in STD_LOGIC_VECTOR ( 5 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
I1 : in STD_LOGIC_VECTOR ( 0 to 0 );
I2 : in STD_LOGIC;
I3 : in STD_LOGIC;
clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_1wr_bin_cntr : entity is "wr_bin_cntr";
end fifo_generator_1wr_bin_cntr;
architecture STRUCTURE of fifo_generator_1wr_bin_cntr is
signal n_0_ram_full_i_i_2 : STD_LOGIC;
signal n_0_ram_full_i_i_3 : STD_LOGIC;
signal p_8_out : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gcc0.gc0.count[1]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gcc0.gc0.count[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gcc0.gc0.count[3]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gcc0.gc0.count[4]_i_1\ : label is "soft_lutpair5";
attribute counter : integer;
attribute counter of \gcc0.gc0.count_reg[0]\ : label is 3;
attribute counter of \gcc0.gc0.count_reg[1]\ : label is 3;
attribute counter of \gcc0.gc0.count_reg[2]\ : label is 3;
attribute counter of \gcc0.gc0.count_reg[3]\ : label is 3;
attribute counter of \gcc0.gc0.count_reg[4]\ : label is 3;
attribute counter of \gcc0.gc0.count_reg[5]\ : label is 3;
begin
\gcc0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_8_out(0),
O => \plusOp__0\(0)
);
\gcc0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_8_out(0),
I1 => p_8_out(1),
O => \plusOp__0\(1)
);
\gcc0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => p_8_out(2),
I1 => p_8_out(0),
I2 => p_8_out(1),
O => \plusOp__0\(2)
);
\gcc0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => p_8_out(1),
I1 => p_8_out(0),
I2 => p_8_out(2),
I3 => p_8_out(3),
O => \plusOp__0\(3)
);
\gcc0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => p_8_out(4),
I1 => p_8_out(1),
I2 => p_8_out(0),
I3 => p_8_out(2),
I4 => p_8_out(3),
O => \plusOp__0\(4)
);
\gcc0.gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => p_8_out(5),
I1 => p_8_out(3),
I2 => p_8_out(2),
I3 => p_8_out(0),
I4 => p_8_out(1),
I5 => p_8_out(4),
O => \plusOp__0\(5)
);
\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_8_out(0),
Q => Q(0)
);
\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_8_out(1),
Q => Q(1)
);
\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_8_out(2),
Q => Q(2)
);
\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_8_out(3),
Q => Q(3)
);
\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_8_out(4),
Q => Q(4)
);
\gcc0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => p_8_out(5),
Q => Q(5)
);
\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(0),
PRE => AR(0),
Q => p_8_out(0)
);
\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(1),
Q => p_8_out(1)
);
\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(2),
Q => p_8_out(2)
);
\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(3),
Q => p_8_out(3)
);
\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(4),
Q => p_8_out(4)
);
\gcc0.gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(5),
Q => p_8_out(5)
);
ram_full_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0080FFFF008000FF"
)
port map (
I0 => n_0_ram_full_i_i_2,
I1 => n_0_ram_full_i_i_3,
I2 => E(0),
I3 => I1(0),
I4 => I2,
I5 => I3,
O => ram_full_comb
);
ram_full_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_8_out(3),
I1 => ADDRB(3),
I2 => p_8_out(0),
I3 => ADDRB(0),
I4 => ADDRB(1),
I5 => p_8_out(1),
O => n_0_ram_full_i_i_2
);
ram_full_i_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_8_out(2),
I1 => ADDRB(2),
I2 => p_8_out(4),
I3 => ADDRB(4),
I4 => ADDRB(5),
I5 => p_8_out(5),
O => n_0_ram_full_i_i_3
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_1wr_status_flags_ss is
port (
p_1_out : out STD_LOGIC;
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_comb : in STD_LOGIC;
clk : in STD_LOGIC;
rst_d2 : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_1wr_status_flags_ss : entity is "wr_status_flags_ss";
end fifo_generator_1wr_status_flags_ss;
architecture STRUCTURE of fifo_generator_1wr_status_flags_ss is
signal \^p_1_out\ : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
p_1_out <= \^p_1_out\;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => \^p_1_out\,
O => E(0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => rst_d2,
Q => \^p_1_out\
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => rst_d2,
Q => full
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_1blk_mem_gen_prim_width is
port (
DOUTB : out STD_LOGIC_VECTOR ( 35 downto 0 );
clk : in STD_LOGIC;
ENB : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRB : in STD_LOGIC_VECTOR ( 5 downto 0 );
ADDRA : in STD_LOGIC_VECTOR ( 5 downto 0 );
din : in STD_LOGIC_VECTOR ( 35 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_1blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end fifo_generator_1blk_mem_gen_prim_width;
architecture STRUCTURE of fifo_generator_1blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.fifo_generator_1blk_mem_gen_prim_wrapper
port map (
ADDRA(5 downto 0) => ADDRA(5 downto 0),
ADDRB(5 downto 0) => ADDRB(5 downto 0),
DOUTB(35 downto 0) => DOUTB(35 downto 0),
E(0) => E(0),
ENB => ENB,
Q(0) => Q(0),
clk => clk,
din(35 downto 0) => din(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_1blk_mem_gen_prim_width__parameterized0\ is
port (
DOUTB : out STD_LOGIC_VECTOR ( 57 downto 0 );
ENB : in STD_LOGIC;
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRB : in STD_LOGIC_VECTOR ( 5 downto 0 );
ADDRA : in STD_LOGIC_VECTOR ( 5 downto 0 );
din : in STD_LOGIC_VECTOR ( 57 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_1blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \fifo_generator_1blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \fifo_generator_1blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_noinit.ram\: entity work.\fifo_generator_1blk_mem_gen_prim_wrapper__parameterized0\
port map (
ADDRA(5 downto 0) => ADDRA(5 downto 0),
ADDRB(5 downto 0) => ADDRB(5 downto 0),
DOUTB(57 downto 0) => DOUTB(57 downto 0),
E(0) => E(0),
ENB => ENB,
Q(0) => Q(0),
clk => clk,
din(57 downto 0) => din(57 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_1rd_logic is
port (
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
O1 : out STD_LOGIC_VECTOR ( 0 to 0 );
O2 : out STD_LOGIC;
ENB : out STD_LOGIC;
O3 : out STD_LOGIC_VECTOR ( 5 downto 0 );
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
I1 : in STD_LOGIC_VECTOR ( 5 downto 0 );
I2 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_1rd_logic : entity is "rd_logic";
end fifo_generator_1rd_logic;
architecture STRUCTURE of fifo_generator_1rd_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal n_0_rpntr : STD_LOGIC;
signal \n_4_gr1.rfwft\ : STD_LOGIC;
signal p_18_out : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gr1.rfwft\: entity work.fifo_generator_1rd_fwft
port map (
E(0) => \^e\(0),
ENB => ENB,
O1(0) => O1(0),
O2 => \n_4_gr1.rfwft\,
Q(1 downto 0) => Q(1 downto 0),
clk => clk,
empty => empty,
p_18_out => p_18_out,
rd_en => rd_en
);
\grss.rsts\: entity work.fifo_generator_1rd_status_flags_ss
port map (
I1 => n_0_rpntr,
Q(0) => Q(1),
clk => clk,
p_18_out => p_18_out
);
rpntr: entity work.fifo_generator_1rd_bin_cntr
port map (
E(0) => \^e\(0),
I1(5 downto 0) => I1(5 downto 0),
I2 => \n_4_gr1.rfwft\,
I3(0) => I2(0),
O1 => n_0_rpntr,
O2 => O2,
O3(5 downto 0) => O3(5 downto 0),
Q(0) => Q(1),
clk => clk,
p_18_out => p_18_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_1wr_logic is
port (
p_1_out : out STD_LOGIC;
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
clk : in STD_LOGIC;
rst_d2 : in STD_LOGIC;
ADDRB : in STD_LOGIC_VECTOR ( 5 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 0 to 0 );
I2 : in STD_LOGIC;
I3 : in STD_LOGIC;
wr_en : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_1wr_logic : entity is "wr_logic";
end fifo_generator_1wr_logic;
architecture STRUCTURE of fifo_generator_1wr_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal ram_full_comb : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gwss.wsts\: entity work.fifo_generator_1wr_status_flags_ss
port map (
E(0) => \^e\(0),
clk => clk,
full => full,
p_1_out => p_1_out,
ram_full_comb => ram_full_comb,
rst_d2 => rst_d2,
wr_en => wr_en
);
wpntr: entity work.fifo_generator_1wr_bin_cntr
port map (
ADDRB(5 downto 0) => ADDRB(5 downto 0),
AR(0) => AR(0),
E(0) => \^e\(0),
I1(0) => I1(0),
I2 => I2,
I3 => I3,
Q(5 downto 0) => Q(5 downto 0),
clk => clk,
ram_full_comb => ram_full_comb
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_1blk_mem_gen_generic_cstr is
port (
DOUTB : out STD_LOGIC_VECTOR ( 93 downto 0 );
clk : in STD_LOGIC;
ENB : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRB : in STD_LOGIC_VECTOR ( 5 downto 0 );
ADDRA : in STD_LOGIC_VECTOR ( 5 downto 0 );
din : in STD_LOGIC_VECTOR ( 93 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_1blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end fifo_generator_1blk_mem_gen_generic_cstr;
architecture STRUCTURE of fifo_generator_1blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.fifo_generator_1blk_mem_gen_prim_width
port map (
ADDRA(5 downto 0) => ADDRA(5 downto 0),
ADDRB(5 downto 0) => ADDRB(5 downto 0),
DOUTB(35 downto 0) => DOUTB(35 downto 0),
E(0) => E(0),
ENB => ENB,
Q(0) => Q(0),
clk => clk,
din(35 downto 0) => din(35 downto 0)
);
\ramloop[1].ram.r\: entity work.\fifo_generator_1blk_mem_gen_prim_width__parameterized0\
port map (
ADDRA(5 downto 0) => ADDRA(5 downto 0),
ADDRB(5 downto 0) => ADDRB(5 downto 0),
DOUTB(57 downto 0) => DOUTB(93 downto 36),
E(0) => E(0),
ENB => ENB,
Q(0) => Q(0),
clk => clk,
din(57 downto 0) => din(93 downto 36)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_1blk_mem_gen_top is
port (
DOUTB : out STD_LOGIC_VECTOR ( 93 downto 0 );
clk : in STD_LOGIC;
ENB : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRB : in STD_LOGIC_VECTOR ( 5 downto 0 );
ADDRA : in STD_LOGIC_VECTOR ( 5 downto 0 );
din : in STD_LOGIC_VECTOR ( 93 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_1blk_mem_gen_top : entity is "blk_mem_gen_top";
end fifo_generator_1blk_mem_gen_top;
architecture STRUCTURE of fifo_generator_1blk_mem_gen_top is
begin
\valid.cstr\: entity work.fifo_generator_1blk_mem_gen_generic_cstr
port map (
ADDRA(5 downto 0) => ADDRA(5 downto 0),
ADDRB(5 downto 0) => ADDRB(5 downto 0),
DOUTB(93 downto 0) => DOUTB(93 downto 0),
E(0) => E(0),
ENB => ENB,
Q(0) => Q(0),
clk => clk,
din(93 downto 0) => din(93 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_1blk_mem_gen_v8_2_synth is
port (
DOUTB : out STD_LOGIC_VECTOR ( 93 downto 0 );
clk : in STD_LOGIC;
ENB : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRB : in STD_LOGIC_VECTOR ( 5 downto 0 );
ADDRA : in STD_LOGIC_VECTOR ( 5 downto 0 );
din : in STD_LOGIC_VECTOR ( 93 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_1blk_mem_gen_v8_2_synth : entity is "blk_mem_gen_v8_2_synth";
end fifo_generator_1blk_mem_gen_v8_2_synth;
architecture STRUCTURE of fifo_generator_1blk_mem_gen_v8_2_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.fifo_generator_1blk_mem_gen_top
port map (
ADDRA(5 downto 0) => ADDRA(5 downto 0),
ADDRB(5 downto 0) => ADDRB(5 downto 0),
DOUTB(93 downto 0) => DOUTB(93 downto 0),
E(0) => E(0),
ENB => ENB,
Q(0) => Q(0),
clk => clk,
din(93 downto 0) => din(93 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_1blk_mem_gen_v8_2__parameterized0\ is
port (
DOUTB : out STD_LOGIC_VECTOR ( 93 downto 0 );
clk : in STD_LOGIC;
ENB : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRB : in STD_LOGIC_VECTOR ( 5 downto 0 );
ADDRA : in STD_LOGIC_VECTOR ( 5 downto 0 );
din : in STD_LOGIC_VECTOR ( 93 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_1blk_mem_gen_v8_2__parameterized0\ : entity is "blk_mem_gen_v8_2";
end \fifo_generator_1blk_mem_gen_v8_2__parameterized0\;
architecture STRUCTURE of \fifo_generator_1blk_mem_gen_v8_2__parameterized0\ is
begin
inst_blk_mem_gen: entity work.fifo_generator_1blk_mem_gen_v8_2_synth
port map (
ADDRA(5 downto 0) => ADDRA(5 downto 0),
ADDRB(5 downto 0) => ADDRB(5 downto 0),
DOUTB(93 downto 0) => DOUTB(93 downto 0),
E(0) => E(0),
ENB => ENB,
Q(0) => Q(0),
clk => clk,
din(93 downto 0) => din(93 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_1memory is
port (
dout : out STD_LOGIC_VECTOR ( 93 downto 0 );
clk : in STD_LOGIC;
ENB : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRB : in STD_LOGIC_VECTOR ( 5 downto 0 );
ADDRA : in STD_LOGIC_VECTOR ( 5 downto 0 );
din : in STD_LOGIC_VECTOR ( 93 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_1memory : entity is "memory";
end fifo_generator_1memory;
architecture STRUCTURE of fifo_generator_1memory is
signal doutb : STD_LOGIC_VECTOR ( 93 downto 0 );
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.\fifo_generator_1blk_mem_gen_v8_2__parameterized0\
port map (
ADDRA(5 downto 0) => ADDRA(5 downto 0),
ADDRB(5 downto 0) => ADDRB(5 downto 0),
DOUTB(93 downto 0) => doutb(93 downto 0),
E(0) => E(0),
ENB => ENB,
Q(0) => Q(0),
clk => clk,
din(93 downto 0) => din(93 downto 0)
);
\goreg_bm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(0),
Q => dout(0),
R => Q(0)
);
\goreg_bm.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(10),
Q => dout(10),
R => Q(0)
);
\goreg_bm.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(11),
Q => dout(11),
R => Q(0)
);
\goreg_bm.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(12),
Q => dout(12),
R => Q(0)
);
\goreg_bm.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(13),
Q => dout(13),
R => Q(0)
);
\goreg_bm.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(14),
Q => dout(14),
R => Q(0)
);
\goreg_bm.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(15),
Q => dout(15),
R => Q(0)
);
\goreg_bm.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(16),
Q => dout(16),
R => Q(0)
);
\goreg_bm.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(17),
Q => dout(17),
R => Q(0)
);
\goreg_bm.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(18),
Q => dout(18),
R => Q(0)
);
\goreg_bm.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(19),
Q => dout(19),
R => Q(0)
);
\goreg_bm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(1),
Q => dout(1),
R => Q(0)
);
\goreg_bm.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(20),
Q => dout(20),
R => Q(0)
);
\goreg_bm.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(21),
Q => dout(21),
R => Q(0)
);
\goreg_bm.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(22),
Q => dout(22),
R => Q(0)
);
\goreg_bm.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(23),
Q => dout(23),
R => Q(0)
);
\goreg_bm.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(24),
Q => dout(24),
R => Q(0)
);
\goreg_bm.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(25),
Q => dout(25),
R => Q(0)
);
\goreg_bm.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(26),
Q => dout(26),
R => Q(0)
);
\goreg_bm.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(27),
Q => dout(27),
R => Q(0)
);
\goreg_bm.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(28),
Q => dout(28),
R => Q(0)
);
\goreg_bm.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(29),
Q => dout(29),
R => Q(0)
);
\goreg_bm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(2),
Q => dout(2),
R => Q(0)
);
\goreg_bm.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(30),
Q => dout(30),
R => Q(0)
);
\goreg_bm.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(31),
Q => dout(31),
R => Q(0)
);
\goreg_bm.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(32),
Q => dout(32),
R => Q(0)
);
\goreg_bm.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(33),
Q => dout(33),
R => Q(0)
);
\goreg_bm.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(34),
Q => dout(34),
R => Q(0)
);
\goreg_bm.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(35),
Q => dout(35),
R => Q(0)
);
\goreg_bm.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(36),
Q => dout(36),
R => Q(0)
);
\goreg_bm.dout_i_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(37),
Q => dout(37),
R => Q(0)
);
\goreg_bm.dout_i_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(38),
Q => dout(38),
R => Q(0)
);
\goreg_bm.dout_i_reg[39]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(39),
Q => dout(39),
R => Q(0)
);
\goreg_bm.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(3),
Q => dout(3),
R => Q(0)
);
\goreg_bm.dout_i_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(40),
Q => dout(40),
R => Q(0)
);
\goreg_bm.dout_i_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(41),
Q => dout(41),
R => Q(0)
);
\goreg_bm.dout_i_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(42),
Q => dout(42),
R => Q(0)
);
\goreg_bm.dout_i_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(43),
Q => dout(43),
R => Q(0)
);
\goreg_bm.dout_i_reg[44]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(44),
Q => dout(44),
R => Q(0)
);
\goreg_bm.dout_i_reg[45]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(45),
Q => dout(45),
R => Q(0)
);
\goreg_bm.dout_i_reg[46]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(46),
Q => dout(46),
R => Q(0)
);
\goreg_bm.dout_i_reg[47]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(47),
Q => dout(47),
R => Q(0)
);
\goreg_bm.dout_i_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(48),
Q => dout(48),
R => Q(0)
);
\goreg_bm.dout_i_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(49),
Q => dout(49),
R => Q(0)
);
\goreg_bm.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(4),
Q => dout(4),
R => Q(0)
);
\goreg_bm.dout_i_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(50),
Q => dout(50),
R => Q(0)
);
\goreg_bm.dout_i_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(51),
Q => dout(51),
R => Q(0)
);
\goreg_bm.dout_i_reg[52]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(52),
Q => dout(52),
R => Q(0)
);
\goreg_bm.dout_i_reg[53]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(53),
Q => dout(53),
R => Q(0)
);
\goreg_bm.dout_i_reg[54]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(54),
Q => dout(54),
R => Q(0)
);
\goreg_bm.dout_i_reg[55]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(55),
Q => dout(55),
R => Q(0)
);
\goreg_bm.dout_i_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(56),
Q => dout(56),
R => Q(0)
);
\goreg_bm.dout_i_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(57),
Q => dout(57),
R => Q(0)
);
\goreg_bm.dout_i_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(58),
Q => dout(58),
R => Q(0)
);
\goreg_bm.dout_i_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(59),
Q => dout(59),
R => Q(0)
);
\goreg_bm.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(5),
Q => dout(5),
R => Q(0)
);
\goreg_bm.dout_i_reg[60]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(60),
Q => dout(60),
R => Q(0)
);
\goreg_bm.dout_i_reg[61]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(61),
Q => dout(61),
R => Q(0)
);
\goreg_bm.dout_i_reg[62]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(62),
Q => dout(62),
R => Q(0)
);
\goreg_bm.dout_i_reg[63]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(63),
Q => dout(63),
R => Q(0)
);
\goreg_bm.dout_i_reg[64]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(64),
Q => dout(64),
R => Q(0)
);
\goreg_bm.dout_i_reg[65]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(65),
Q => dout(65),
R => Q(0)
);
\goreg_bm.dout_i_reg[66]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(66),
Q => dout(66),
R => Q(0)
);
\goreg_bm.dout_i_reg[67]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(67),
Q => dout(67),
R => Q(0)
);
\goreg_bm.dout_i_reg[68]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(68),
Q => dout(68),
R => Q(0)
);
\goreg_bm.dout_i_reg[69]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(69),
Q => dout(69),
R => Q(0)
);
\goreg_bm.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(6),
Q => dout(6),
R => Q(0)
);
\goreg_bm.dout_i_reg[70]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(70),
Q => dout(70),
R => Q(0)
);
\goreg_bm.dout_i_reg[71]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(71),
Q => dout(71),
R => Q(0)
);
\goreg_bm.dout_i_reg[72]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(72),
Q => dout(72),
R => Q(0)
);
\goreg_bm.dout_i_reg[73]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(73),
Q => dout(73),
R => Q(0)
);
\goreg_bm.dout_i_reg[74]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(74),
Q => dout(74),
R => Q(0)
);
\goreg_bm.dout_i_reg[75]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(75),
Q => dout(75),
R => Q(0)
);
\goreg_bm.dout_i_reg[76]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(76),
Q => dout(76),
R => Q(0)
);
\goreg_bm.dout_i_reg[77]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(77),
Q => dout(77),
R => Q(0)
);
\goreg_bm.dout_i_reg[78]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(78),
Q => dout(78),
R => Q(0)
);
\goreg_bm.dout_i_reg[79]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(79),
Q => dout(79),
R => Q(0)
);
\goreg_bm.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(7),
Q => dout(7),
R => Q(0)
);
\goreg_bm.dout_i_reg[80]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(80),
Q => dout(80),
R => Q(0)
);
\goreg_bm.dout_i_reg[81]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(81),
Q => dout(81),
R => Q(0)
);
\goreg_bm.dout_i_reg[82]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(82),
Q => dout(82),
R => Q(0)
);
\goreg_bm.dout_i_reg[83]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(83),
Q => dout(83),
R => Q(0)
);
\goreg_bm.dout_i_reg[84]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(84),
Q => dout(84),
R => Q(0)
);
\goreg_bm.dout_i_reg[85]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(85),
Q => dout(85),
R => Q(0)
);
\goreg_bm.dout_i_reg[86]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(86),
Q => dout(86),
R => Q(0)
);
\goreg_bm.dout_i_reg[87]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(87),
Q => dout(87),
R => Q(0)
);
\goreg_bm.dout_i_reg[88]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(88),
Q => dout(88),
R => Q(0)
);
\goreg_bm.dout_i_reg[89]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(89),
Q => dout(89),
R => Q(0)
);
\goreg_bm.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(8),
Q => dout(8),
R => Q(0)
);
\goreg_bm.dout_i_reg[90]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(90),
Q => dout(90),
R => Q(0)
);
\goreg_bm.dout_i_reg[91]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(91),
Q => dout(91),
R => Q(0)
);
\goreg_bm.dout_i_reg[92]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(92),
Q => dout(92),
R => Q(0)
);
\goreg_bm.dout_i_reg[93]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(93),
Q => dout(93),
R => Q(0)
);
\goreg_bm.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => I1(0),
D => doutb(9),
Q => dout(9),
R => Q(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_1fifo_generator_ramfifo is
port (
dout : out STD_LOGIC_VECTOR ( 93 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 93 downto 0 );
rst : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_1fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end fifo_generator_1fifo_generator_ramfifo;
architecture STRUCTURE of fifo_generator_1fifo_generator_ramfifo is
signal RD_RST : STD_LOGIC;
signal \^rst\ : STD_LOGIC;
signal \n_1_gntv_or_sync_fifo.gl0.rd\ : STD_LOGIC;
signal n_2_rstblk : STD_LOGIC;
signal \n_3_gntv_or_sync_fifo.gl0.rd\ : STD_LOGIC;
signal n_4_rstblk : STD_LOGIC;
signal p_15_out : STD_LOGIC;
signal p_1_out : STD_LOGIC;
signal p_20_out : STD_LOGIC_VECTOR ( 5 downto 0 );
signal p_3_out : STD_LOGIC;
signal p_9_out : STD_LOGIC_VECTOR ( 5 downto 0 );
signal rst_d2 : STD_LOGIC;
signal tmp_ram_rd_en : STD_LOGIC;
begin
\gntv_or_sync_fifo.gl0.rd\: entity work.fifo_generator_1rd_logic
port map (
E(0) => \n_1_gntv_or_sync_fifo.gl0.rd\,
ENB => tmp_ram_rd_en,
I1(5 downto 0) => p_9_out(5 downto 0),
I2(0) => p_3_out,
O1(0) => p_15_out,
O2 => \n_3_gntv_or_sync_fifo.gl0.rd\,
O3(5 downto 0) => p_20_out(5 downto 0),
Q(1) => RD_RST,
Q(0) => n_4_rstblk,
clk => clk,
empty => empty,
rd_en => rd_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.fifo_generator_1wr_logic
port map (
ADDRB(5 downto 0) => p_20_out(5 downto 0),
AR(0) => \^rst\,
E(0) => p_3_out,
I1(0) => \n_1_gntv_or_sync_fifo.gl0.rd\,
I2 => n_2_rstblk,
I3 => \n_3_gntv_or_sync_fifo.gl0.rd\,
Q(5 downto 0) => p_9_out(5 downto 0),
clk => clk,
full => full,
p_1_out => p_1_out,
rst_d2 => rst_d2,
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.fifo_generator_1memory
port map (
ADDRA(5 downto 0) => p_9_out(5 downto 0),
ADDRB(5 downto 0) => p_20_out(5 downto 0),
E(0) => p_3_out,
ENB => tmp_ram_rd_en,
I1(0) => p_15_out,
Q(0) => n_4_rstblk,
clk => clk,
din(93 downto 0) => din(93 downto 0),
dout(93 downto 0) => dout(93 downto 0)
);
rstblk: entity work.fifo_generator_1reset_blk_ramfifo
port map (
AR(0) => \^rst\,
O1 => n_2_rstblk,
Q(1) => RD_RST,
Q(0) => n_4_rstblk,
clk => clk,
p_1_out => p_1_out,
rst => rst,
rst_d2 => rst_d2
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_1fifo_generator_top is
port (
dout : out STD_LOGIC_VECTOR ( 93 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 93 downto 0 );
rst : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_1fifo_generator_top : entity is "fifo_generator_top";
end fifo_generator_1fifo_generator_top;
architecture STRUCTURE of fifo_generator_1fifo_generator_top is
begin
\grf.rf\: entity work.fifo_generator_1fifo_generator_ramfifo
port map (
clk => clk,
din(93 downto 0) => din(93 downto 0),
dout(93 downto 0) => dout(93 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_1fifo_generator_v12_0_synth is
port (
dout : out STD_LOGIC_VECTOR ( 93 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 93 downto 0 );
rst : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_1fifo_generator_v12_0_synth : entity is "fifo_generator_v12_0_synth";
end fifo_generator_1fifo_generator_v12_0_synth;
architecture STRUCTURE of fifo_generator_1fifo_generator_v12_0_synth is
begin
\gconvfifo.rf\: entity work.fifo_generator_1fifo_generator_top
port map (
clk => clk,
din(93 downto 0) => din(93 downto 0),
dout(93 downto 0) => dout(93 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_1fifo_generator_v12_0__parameterized0\ is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 93 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 5 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 5 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 5 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 5 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 5 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 5 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 93 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 6 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 6 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 6 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is "fifo_generator_v12_0";
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 7;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 94;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 94;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
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attribute C_HAS_RD_RST of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is "BlankString";
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
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attribute C_PRELOAD_LATENCY of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is "512x72";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 63;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 62;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 7;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 64;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 6;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 7;
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attribute C_WR_DEPTH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 64;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 6;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 2;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 32;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 64;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 8;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is "1kx18";
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 2;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 16;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1024;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 10;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of \fifo_generator_1fifo_generator_v12_0__parameterized0\ : entity is 0;
end \fifo_generator_1fifo_generator_v12_0__parameterized0\;
architecture STRUCTURE of \fifo_generator_1fifo_generator_v12_0__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(6) <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(6) <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.fifo_generator_1fifo_generator_v12_0_synth
port map (
clk => clk,
din(93 downto 0) => din(93 downto 0),
dout(93 downto 0) => dout(93 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_1 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 93 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 93 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of fifo_generator_1 : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of fifo_generator_1 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of fifo_generator_1 : entity is "fifo_generator_v12_0,Vivado 2014.1";
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of fifo_generator_1 : entity is "fifo_generator_1,fifo_generator_v12_0,{}";
attribute core_generation_info : string;
attribute core_generation_info of fifo_generator_1 : entity is "fifo_generator_1,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=0,x_ipLanguage=VHDL,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=7,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=94,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=94,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=63,C_PROG_FULL_THRESH_NEGATE_VAL=62,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=7,C_RD_DEPTH=64,C_RD_FREQ=1,C_RD_PNTR_WIDTH=6,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=1,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=7,C_WR_DEPTH=64,C_WR_FREQ=1,C_WR_PNTR_WIDTH=6,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
end fifo_generator_1;
architecture STRUCTURE of fifo_generator_1 is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 6 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 6 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 6 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 7;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 94;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 94;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "512x72";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 63;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 62;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 7;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 64;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 6;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 1;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 7;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 64;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 6;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.\fifo_generator_1fifo_generator_v12_0__parameterized0\
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3) => '0',
axi_ar_prog_empty_thresh(2) => '0',
axi_ar_prog_empty_thresh(1) => '0',
axi_ar_prog_empty_thresh(0) => '0',
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3) => '0',
axi_ar_prog_full_thresh(2) => '0',
axi_ar_prog_full_thresh(1) => '0',
axi_ar_prog_full_thresh(0) => '0',
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3) => '0',
axi_aw_prog_empty_thresh(2) => '0',
axi_aw_prog_empty_thresh(1) => '0',
axi_aw_prog_empty_thresh(0) => '0',
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3) => '0',
axi_aw_prog_full_thresh(2) => '0',
axi_aw_prog_full_thresh(1) => '0',
axi_aw_prog_full_thresh(0) => '0',
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3) => '0',
axi_b_prog_empty_thresh(2) => '0',
axi_b_prog_empty_thresh(1) => '0',
axi_b_prog_empty_thresh(0) => '0',
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3) => '0',
axi_b_prog_full_thresh(2) => '0',
axi_b_prog_full_thresh(1) => '0',
axi_b_prog_full_thresh(0) => '0',
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9) => '0',
axi_r_prog_empty_thresh(8) => '0',
axi_r_prog_empty_thresh(7) => '0',
axi_r_prog_empty_thresh(6) => '0',
axi_r_prog_empty_thresh(5) => '0',
axi_r_prog_empty_thresh(4) => '0',
axi_r_prog_empty_thresh(3) => '0',
axi_r_prog_empty_thresh(2) => '0',
axi_r_prog_empty_thresh(1) => '0',
axi_r_prog_empty_thresh(0) => '0',
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9) => '0',
axi_r_prog_full_thresh(8) => '0',
axi_r_prog_full_thresh(7) => '0',
axi_r_prog_full_thresh(6) => '0',
axi_r_prog_full_thresh(5) => '0',
axi_r_prog_full_thresh(4) => '0',
axi_r_prog_full_thresh(3) => '0',
axi_r_prog_full_thresh(2) => '0',
axi_r_prog_full_thresh(1) => '0',
axi_r_prog_full_thresh(0) => '0',
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9) => '0',
axi_w_prog_empty_thresh(8) => '0',
axi_w_prog_empty_thresh(7) => '0',
axi_w_prog_empty_thresh(6) => '0',
axi_w_prog_empty_thresh(5) => '0',
axi_w_prog_empty_thresh(4) => '0',
axi_w_prog_empty_thresh(3) => '0',
axi_w_prog_empty_thresh(2) => '0',
axi_w_prog_empty_thresh(1) => '0',
axi_w_prog_empty_thresh(0) => '0',
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9) => '0',
axi_w_prog_full_thresh(8) => '0',
axi_w_prog_full_thresh(7) => '0',
axi_w_prog_full_thresh(6) => '0',
axi_w_prog_full_thresh(5) => '0',
axi_w_prog_full_thresh(4) => '0',
axi_w_prog_full_thresh(3) => '0',
axi_w_prog_full_thresh(2) => '0',
axi_w_prog_full_thresh(1) => '0',
axi_w_prog_full_thresh(0) => '0',
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9) => '0',
axis_prog_empty_thresh(8) => '0',
axis_prog_empty_thresh(7) => '0',
axis_prog_empty_thresh(6) => '0',
axis_prog_empty_thresh(5) => '0',
axis_prog_empty_thresh(4) => '0',
axis_prog_empty_thresh(3) => '0',
axis_prog_empty_thresh(2) => '0',
axis_prog_empty_thresh(1) => '0',
axis_prog_empty_thresh(0) => '0',
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9) => '0',
axis_prog_full_thresh(8) => '0',
axis_prog_full_thresh(7) => '0',
axis_prog_full_thresh(6) => '0',
axis_prog_full_thresh(5) => '0',
axis_prog_full_thresh(4) => '0',
axis_prog_full_thresh(3) => '0',
axis_prog_full_thresh(2) => '0',
axis_prog_full_thresh(1) => '0',
axis_prog_full_thresh(0) => '0',
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => clk,
data_count(6 downto 0) => NLW_U0_data_count_UNCONNECTED(6 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(93 downto 0) => din(93 downto 0),
dout(93 downto 0) => dout(93 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1) => '0',
m_axi_bresp(0) => '0',
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63) => '0',
m_axi_rdata(62) => '0',
m_axi_rdata(61) => '0',
m_axi_rdata(60) => '0',
m_axi_rdata(59) => '0',
m_axi_rdata(58) => '0',
m_axi_rdata(57) => '0',
m_axi_rdata(56) => '0',
m_axi_rdata(55) => '0',
m_axi_rdata(54) => '0',
m_axi_rdata(53) => '0',
m_axi_rdata(52) => '0',
m_axi_rdata(51) => '0',
m_axi_rdata(50) => '0',
m_axi_rdata(49) => '0',
m_axi_rdata(48) => '0',
m_axi_rdata(47) => '0',
m_axi_rdata(46) => '0',
m_axi_rdata(45) => '0',
m_axi_rdata(44) => '0',
m_axi_rdata(43) => '0',
m_axi_rdata(42) => '0',
m_axi_rdata(41) => '0',
m_axi_rdata(40) => '0',
m_axi_rdata(39) => '0',
m_axi_rdata(38) => '0',
m_axi_rdata(37) => '0',
m_axi_rdata(36) => '0',
m_axi_rdata(35) => '0',
m_axi_rdata(34) => '0',
m_axi_rdata(33) => '0',
m_axi_rdata(32) => '0',
m_axi_rdata(31) => '0',
m_axi_rdata(30) => '0',
m_axi_rdata(29) => '0',
m_axi_rdata(28) => '0',
m_axi_rdata(27) => '0',
m_axi_rdata(26) => '0',
m_axi_rdata(25) => '0',
m_axi_rdata(24) => '0',
m_axi_rdata(23) => '0',
m_axi_rdata(22) => '0',
m_axi_rdata(21) => '0',
m_axi_rdata(20) => '0',
m_axi_rdata(19) => '0',
m_axi_rdata(18) => '0',
m_axi_rdata(17) => '0',
m_axi_rdata(16) => '0',
m_axi_rdata(15) => '0',
m_axi_rdata(14) => '0',
m_axi_rdata(13) => '0',
m_axi_rdata(12) => '0',
m_axi_rdata(11) => '0',
m_axi_rdata(10) => '0',
m_axi_rdata(9) => '0',
m_axi_rdata(8) => '0',
m_axi_rdata(7) => '0',
m_axi_rdata(6) => '0',
m_axi_rdata(5) => '0',
m_axi_rdata(4) => '0',
m_axi_rdata(3) => '0',
m_axi_rdata(2) => '0',
m_axi_rdata(1) => '0',
m_axi_rdata(0) => '0',
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1) => '0',
m_axi_rresp(0) => '0',
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(5) => '0',
prog_empty_thresh(4) => '0',
prog_empty_thresh(3) => '0',
prog_empty_thresh(2) => '0',
prog_empty_thresh(1) => '0',
prog_empty_thresh(0) => '0',
prog_empty_thresh_assert(5) => '0',
prog_empty_thresh_assert(4) => '0',
prog_empty_thresh_assert(3) => '0',
prog_empty_thresh_assert(2) => '0',
prog_empty_thresh_assert(1) => '0',
prog_empty_thresh_assert(0) => '0',
prog_empty_thresh_negate(5) => '0',
prog_empty_thresh_negate(4) => '0',
prog_empty_thresh_negate(3) => '0',
prog_empty_thresh_negate(2) => '0',
prog_empty_thresh_negate(1) => '0',
prog_empty_thresh_negate(0) => '0',
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(5) => '0',
prog_full_thresh(4) => '0',
prog_full_thresh(3) => '0',
prog_full_thresh(2) => '0',
prog_full_thresh(1) => '0',
prog_full_thresh(0) => '0',
prog_full_thresh_assert(5) => '0',
prog_full_thresh_assert(4) => '0',
prog_full_thresh_assert(3) => '0',
prog_full_thresh_assert(2) => '0',
prog_full_thresh_assert(1) => '0',
prog_full_thresh_assert(0) => '0',
prog_full_thresh_negate(5) => '0',
prog_full_thresh_negate(4) => '0',
prog_full_thresh_negate(3) => '0',
prog_full_thresh_negate(2) => '0',
prog_full_thresh_negate(1) => '0',
prog_full_thresh_negate(0) => '0',
rd_clk => '0',
rd_data_count(6 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(6 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31) => '0',
s_axi_araddr(30) => '0',
s_axi_araddr(29) => '0',
s_axi_araddr(28) => '0',
s_axi_araddr(27) => '0',
s_axi_araddr(26) => '0',
s_axi_araddr(25) => '0',
s_axi_araddr(24) => '0',
s_axi_araddr(23) => '0',
s_axi_araddr(22) => '0',
s_axi_araddr(21) => '0',
s_axi_araddr(20) => '0',
s_axi_araddr(19) => '0',
s_axi_araddr(18) => '0',
s_axi_araddr(17) => '0',
s_axi_araddr(16) => '0',
s_axi_araddr(15) => '0',
s_axi_araddr(14) => '0',
s_axi_araddr(13) => '0',
s_axi_araddr(12) => '0',
s_axi_araddr(11) => '0',
s_axi_araddr(10) => '0',
s_axi_araddr(9) => '0',
s_axi_araddr(8) => '0',
s_axi_araddr(7) => '0',
s_axi_araddr(6) => '0',
s_axi_araddr(5) => '0',
s_axi_araddr(4) => '0',
s_axi_araddr(3) => '0',
s_axi_araddr(2) => '0',
s_axi_araddr(1) => '0',
s_axi_araddr(0) => '0',
s_axi_arburst(1) => '0',
s_axi_arburst(0) => '0',
s_axi_arcache(3) => '0',
s_axi_arcache(2) => '0',
s_axi_arcache(1) => '0',
s_axi_arcache(0) => '0',
s_axi_arid(0) => '0',
s_axi_arlen(7) => '0',
s_axi_arlen(6) => '0',
s_axi_arlen(5) => '0',
s_axi_arlen(4) => '0',
s_axi_arlen(3) => '0',
s_axi_arlen(2) => '0',
s_axi_arlen(1) => '0',
s_axi_arlen(0) => '0',
s_axi_arlock(0) => '0',
s_axi_arprot(2) => '0',
s_axi_arprot(1) => '0',
s_axi_arprot(0) => '0',
s_axi_arqos(3) => '0',
s_axi_arqos(2) => '0',
s_axi_arqos(1) => '0',
s_axi_arqos(0) => '0',
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3) => '0',
s_axi_arregion(2) => '0',
s_axi_arregion(1) => '0',
s_axi_arregion(0) => '0',
s_axi_arsize(2) => '0',
s_axi_arsize(1) => '0',
s_axi_arsize(0) => '0',
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31) => '0',
s_axi_awaddr(30) => '0',
s_axi_awaddr(29) => '0',
s_axi_awaddr(28) => '0',
s_axi_awaddr(27) => '0',
s_axi_awaddr(26) => '0',
s_axi_awaddr(25) => '0',
s_axi_awaddr(24) => '0',
s_axi_awaddr(23) => '0',
s_axi_awaddr(22) => '0',
s_axi_awaddr(21) => '0',
s_axi_awaddr(20) => '0',
s_axi_awaddr(19) => '0',
s_axi_awaddr(18) => '0',
s_axi_awaddr(17) => '0',
s_axi_awaddr(16) => '0',
s_axi_awaddr(15) => '0',
s_axi_awaddr(14) => '0',
s_axi_awaddr(13) => '0',
s_axi_awaddr(12) => '0',
s_axi_awaddr(11) => '0',
s_axi_awaddr(10) => '0',
s_axi_awaddr(9) => '0',
s_axi_awaddr(8) => '0',
s_axi_awaddr(7) => '0',
s_axi_awaddr(6) => '0',
s_axi_awaddr(5) => '0',
s_axi_awaddr(4) => '0',
s_axi_awaddr(3) => '0',
s_axi_awaddr(2) => '0',
s_axi_awaddr(1) => '0',
s_axi_awaddr(0) => '0',
s_axi_awburst(1) => '0',
s_axi_awburst(0) => '0',
s_axi_awcache(3) => '0',
s_axi_awcache(2) => '0',
s_axi_awcache(1) => '0',
s_axi_awcache(0) => '0',
s_axi_awid(0) => '0',
s_axi_awlen(7) => '0',
s_axi_awlen(6) => '0',
s_axi_awlen(5) => '0',
s_axi_awlen(4) => '0',
s_axi_awlen(3) => '0',
s_axi_awlen(2) => '0',
s_axi_awlen(1) => '0',
s_axi_awlen(0) => '0',
s_axi_awlock(0) => '0',
s_axi_awprot(2) => '0',
s_axi_awprot(1) => '0',
s_axi_awprot(0) => '0',
s_axi_awqos(3) => '0',
s_axi_awqos(2) => '0',
s_axi_awqos(1) => '0',
s_axi_awqos(0) => '0',
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3) => '0',
s_axi_awregion(2) => '0',
s_axi_awregion(1) => '0',
s_axi_awregion(0) => '0',
s_axi_awsize(2) => '0',
s_axi_awsize(1) => '0',
s_axi_awsize(0) => '0',
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63) => '0',
s_axi_wdata(62) => '0',
s_axi_wdata(61) => '0',
s_axi_wdata(60) => '0',
s_axi_wdata(59) => '0',
s_axi_wdata(58) => '0',
s_axi_wdata(57) => '0',
s_axi_wdata(56) => '0',
s_axi_wdata(55) => '0',
s_axi_wdata(54) => '0',
s_axi_wdata(53) => '0',
s_axi_wdata(52) => '0',
s_axi_wdata(51) => '0',
s_axi_wdata(50) => '0',
s_axi_wdata(49) => '0',
s_axi_wdata(48) => '0',
s_axi_wdata(47) => '0',
s_axi_wdata(46) => '0',
s_axi_wdata(45) => '0',
s_axi_wdata(44) => '0',
s_axi_wdata(43) => '0',
s_axi_wdata(42) => '0',
s_axi_wdata(41) => '0',
s_axi_wdata(40) => '0',
s_axi_wdata(39) => '0',
s_axi_wdata(38) => '0',
s_axi_wdata(37) => '0',
s_axi_wdata(36) => '0',
s_axi_wdata(35) => '0',
s_axi_wdata(34) => '0',
s_axi_wdata(33) => '0',
s_axi_wdata(32) => '0',
s_axi_wdata(31) => '0',
s_axi_wdata(30) => '0',
s_axi_wdata(29) => '0',
s_axi_wdata(28) => '0',
s_axi_wdata(27) => '0',
s_axi_wdata(26) => '0',
s_axi_wdata(25) => '0',
s_axi_wdata(24) => '0',
s_axi_wdata(23) => '0',
s_axi_wdata(22) => '0',
s_axi_wdata(21) => '0',
s_axi_wdata(20) => '0',
s_axi_wdata(19) => '0',
s_axi_wdata(18) => '0',
s_axi_wdata(17) => '0',
s_axi_wdata(16) => '0',
s_axi_wdata(15) => '0',
s_axi_wdata(14) => '0',
s_axi_wdata(13) => '0',
s_axi_wdata(12) => '0',
s_axi_wdata(11) => '0',
s_axi_wdata(10) => '0',
s_axi_wdata(9) => '0',
s_axi_wdata(8) => '0',
s_axi_wdata(7) => '0',
s_axi_wdata(6) => '0',
s_axi_wdata(5) => '0',
s_axi_wdata(4) => '0',
s_axi_wdata(3) => '0',
s_axi_wdata(2) => '0',
s_axi_wdata(1) => '0',
s_axi_wdata(0) => '0',
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7) => '0',
s_axi_wstrb(6) => '0',
s_axi_wstrb(5) => '0',
s_axi_wstrb(4) => '0',
s_axi_wstrb(3) => '0',
s_axi_wstrb(2) => '0',
s_axi_wstrb(1) => '0',
s_axi_wstrb(0) => '0',
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7) => '0',
s_axis_tdata(6) => '0',
s_axis_tdata(5) => '0',
s_axis_tdata(4) => '0',
s_axis_tdata(3) => '0',
s_axis_tdata(2) => '0',
s_axis_tdata(1) => '0',
s_axis_tdata(0) => '0',
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3) => '0',
s_axis_tuser(2) => '0',
s_axis_tuser(1) => '0',
s_axis_tuser(0) => '0',
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => '0',
wr_data_count(6 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(6 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
| mit | 2fa0a5a7de6636c55da10ba1701ff580 | 0.625394 | 3.027767 | false | false | false | false |
lennartbublies/ecdsa | tests/tb_ecdsa_key_generation.vhd | 1 | 2,809 | ----------------------------------------------------------------------------------------------------
-- Testbench - ECDSA Key Generation
--
-- Autor: Lennart Bublies (inf100434)
-- Date: 18.08.2017
----------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
use ieee.math_real.all; -- FOR UNIFORM, TRUNC
USE std.textio.ALL;
use work.tld_ecdsa_package.all;
ENTITY tb_ecdsa_key_generation IS
END tb_ecdsa_key_generation;
ARCHITECTURE rtl OF tb_ecdsa_key_generation IS
-- Import entity e_ecdsa_key_generation
COMPONENT e_ecdsa_key_generation IS
PORT(
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
k_i: IN std_logic_vector(M-1 DOWNTO 0);
xQ_o: INOUT std_logic_vector(M-1 DOWNTO 0);
yQ_o: INOUT std_logic_vector(M-1 DOWNTO 0);
ready_o: OUT std_logic
);
END COMPONENT;
-- Internal signals
SIGNAL k, xQ, yQ: std_logic_vector(M-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL clk, rst, enable, done: std_logic := '0';
CONSTANT ZERO: std_logic_vector(M-1 DOWNTO 0) := (OTHERS=>'0');
CONSTANT ONE: std_logic_vector(M-1 DOWNTO 0) := (0 => '1', OTHERS=>'0');
CONSTANT DELAY : time := 100 ns;
CONSTANT PERIOD : time := 200 ns;
CONSTANT DUTY_CYCLE : real := 0.5;
CONSTANT OFFSET : time := 0 ns;
BEGIN
-- Instantiate point addition entity
uut3: e_ecdsa_key_generation PORT MAP (
clk_i => clk,
rst_i => rst,
k_i => k,
xQ_o => xQ,
yQ_o => yQ,
enable_i => enable,
ready_o => done
);
-- Clock process FOR clk
PROCESS
BEGIN
WAIT FOR OFFSET;
CLOCK_LOOP : LOOP
clk <= '0';
WAIT FOR (PERIOD *(1.0 - DUTY_CYCLE));
clk <= '1';
WAIT FOR (PERIOD * DUTY_CYCLE);
END LOOP CLOCK_LOOP;
END PROCESS;
-- Start test cases
tb : PROCESS
-- Internal signals
VARIABLE TX_LOC : LINE;
VARIABLE TX_STR : String(1 TO 4096);
BEGIN
-- Disable computation and reset all entities
enable <= '0';
rst <= '1';
WAIT FOR PERIOD;
rst <= '0';
WAIT FOR PERIOD;
-- Test #1:
-- Set point P and Q for computation
k <= "000" & x"CD06203260EEE9549351BD29733E7D1E2ED49D88";
enable <= '1';
WAIT FOR PERIOD;
enable <= '0';
WAIT UNTIL (done = '1');
-- Report results
ASSERT (FALSE) REPORT
"Simulation successful!"
SEVERITY FAILURE;
END PROCESS;
END; | gpl-3.0 | 315617bd45d1b5047f5e3592f59f7158 | 0.518334 | 3.832196 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sources_1/rtl/switch_port/rx/input_queue_control.vhd | 2 | 16,225 | ----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 26.11.2013 17:14:16
-- Design Name:
-- Module Name: input_queue_control - rtl
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013.3
--
-- Description:
-- 3 Finite State Machines handle the reception of data frames and the control signals
-- config_input_state machine: receive valid ports informations from lookup module
-- data_input_state_machine: forward incoming frames to memory, count frame_length and store memory address
-- config_output_state machine: check if there are errors in the frame or if frame is to be skipped
-- if not: store output ports, frame length and memory pointer in frame queue fifo
-- the priority signal indicates which fifo to store the data in
--
-- more detailed information can found in file switch_port_rxpath_input_queue_control.svg
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
entity input_queue_control is
Generic (
RECEIVER_DATA_WIDTH : integer;
NR_PORTS : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer;
IQ_MEM_ADDR_WIDTH : integer;
IQ_MEM_DATA_WIDTH_RATIO : integer;
IQ_FIFO_DATA_WIDTH : integer;
FRAME_LENGTH_WIDTH : integer;
IQ_FIFO_PRIO_START : integer;
IQ_FIFO_FRAME_LEN_START : integer;
IQ_FIFO_TIMESTAMP_START : integer;
IQ_FIFO_PORTS_START : integer;
IQ_FIFO_MEM_PTR_START : integer;
-- register width constants
CONTROL_REG_ADDR_WIDTH : integer := 1; -- two entries
DATA_REG_ADDR_WIDTH : integer := 1 -- two entries
);
Port (
clk : in std_logic;
reset : in std_logic;
-- input interface mac
iqctrl_in_mac_data : in std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
iqctrl_in_mac_valid : in std_logic;
iqctrl_in_mac_last : in std_logic;
iqctrl_in_mac_error : in std_logic;
-- input interface lookup
iqctrl_in_lu_ports : in std_logic_vector(NR_PORTS-1 downto 0);
iqctrl_in_lu_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
iqctrl_in_lu_skip : in std_logic;
iqctrl_in_lu_timestamp : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
iqctrl_in_lu_valid : in std_logic;
-- output interface memory
iqctrl_out_mem_wenable : out std_logic;
iqctrl_out_mem_addr : out std_logic_vector(IQ_MEM_ADDR_WIDTH-1 downto 0);
iqctrl_out_mem_data : out std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
-- output interface fifo
iqctrl_out_fifo_wenable : out std_logic;
iqctrl_out_fifo_data : out std_logic_vector(IQ_FIFO_DATA_WIDTH-1 downto 0)
);
end input_queue_control;
architecture rtl of input_queue_control is
-- register address constants
constant CONTROL_REG_PORTS_START : integer := 0;
constant CONTROL_REG_PRIO_START : integer := CONTROL_REG_PORTS_START + NR_PORTS;
constant CONTROL_REG_TIMESTAMP_START : integer := CONTROL_REG_PRIO_START + VLAN_PRIO_WIDTH;
constant CONTROL_REG_SKIP_START : integer := CONTROL_REG_TIMESTAMP_START + TIMESTAMP_WIDTH;
constant DATA_REG_FRAME_LEN_START : integer := 0;
constant DATA_REG_MEM_PTR_START : integer := DATA_REG_FRAME_LEN_START + FRAME_LENGTH_WIDTH;
constant DATA_REG_ERROR_START : integer := DATA_REG_MEM_PTR_START + IQ_MEM_ADDR_WIDTH;
-- config_input_state machine
type config_input_state is (
IDLE,
HANDSHAKE
);
-- data_input_state machine
type data_input_state is (
IDLE,
WRITE_MEM
);
-- config_output_state machine
type config_output_state is (
IDLE,
WRITE_FIFO
);
-- state signals
signal cur_ci_state : config_input_state;
signal nxt_ci_state : config_input_state;
signal cur_di_state : data_input_state;
signal nxt_di_state : data_input_state;
signal cur_co_state : config_output_state;
signal nxt_co_state : config_output_state;
-- control path regsiters
constant CONTROL_REG_DEPTH : integer := 2 ** CONTROL_REG_ADDR_WIDTH;
constant CONTROL_REG_WIDTH : integer := NR_PORTS + VLAN_PRIO_WIDTH + TIMESTAMP_WIDTH + 1;
type control_reg_type is array(CONTROL_REG_DEPTH-1 downto 0) of std_logic_vector(CONTROL_REG_WIDTH-1 downto 0);
signal control_reg : control_reg_type := (others => (others => '0'));
signal control_rd_addr : std_logic_vector(CONTROL_REG_ADDR_WIDTH-1 downto 0);
signal control_nr_entries : std_logic_vector(CONTROL_REG_ADDR_WIDTH downto 0);
-- data path regsiters
constant DATA_REG_DEPTH : integer := 2 ** DATA_REG_ADDR_WIDTH;
constant DATA_REG_WIDTH : integer := IQ_MEM_ADDR_WIDTH + FRAME_LENGTH_WIDTH + 1;
type data_reg_type is array(DATA_REG_DEPTH-1 downto 0) of std_logic_vector(DATA_REG_WIDTH-1 downto 0);
signal data_reg : data_reg_type := (others => (others => '0'));
signal data_rd_addr : std_logic_vector(DATA_REG_ADDR_WIDTH-1 downto 0);
signal data_nr_entries : std_logic_vector(DATA_REG_ADDR_WIDTH downto 0);
-- config_input_state machine signals
signal control_reg_wr_sig : std_logic := '0';
-- data_input_state machine signals
signal update_frame_length_cnt : std_logic := '0';
signal update_mem_start_ptr : std_logic := '0';
signal data_reg_wr_sig : std_logic := '0';
-- config_output_state machine signals
signal control_reg_rd_sig : std_logic := '0';
signal data_reg_rd_sig : std_logic := '0';
signal write_fifo_sig : std_logic := '0';
-- process registers
signal frame_length_cnt : std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
signal mem_start_ptr_reg : std_logic_vector(IQ_MEM_ADDR_WIDTH-1 downto 0);
begin
-- next state logic
next_state_logic_p : process(clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
cur_ci_state <= IDLE;
cur_di_state <= IDLE;
cur_co_state <= IDLE;
else
cur_ci_state <= nxt_ci_state;
cur_di_state <= nxt_di_state;
cur_co_state <= nxt_co_state;
end if;
end if;
end process next_state_logic_p;
-- Decode next config_input_state, combinitorial logic
ci_output_logic_p : process(cur_ci_state, iqctrl_in_lu_valid)
begin
-- default signal assignments
nxt_ci_state <= IDLE;
control_reg_wr_sig <= '0';
case cur_ci_state is
when IDLE =>
if iqctrl_in_lu_valid = '1' then
nxt_ci_state <= HANDSHAKE;
control_reg_wr_sig <= '1'; -- control_reg_p
end if;
when HANDSHAKE =>
nxt_ci_state <= IDLE;
end case;
end process ci_output_logic_p;
-- control register read and write accesses
control_reg_p : process(clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
control_rd_addr <= (others => '0');
control_nr_entries <= (others => '0');
iqctrl_out_fifo_data(IQ_FIFO_PORTS_START+NR_PORTS-1 downto IQ_FIFO_PORTS_START)
<= (others => '0');
else
control_rd_addr <= control_rd_addr;
control_nr_entries <= control_nr_entries;
iqctrl_out_fifo_data(IQ_FIFO_PRIO_START+VLAN_PRIO_WIDTH-1 downto IQ_FIFO_PRIO_START)
<= control_reg(conv_integer(control_rd_addr))(CONTROL_REG_PRIO_START+VLAN_PRIO_WIDTH-1 downto CONTROL_REG_PRIO_START);
iqctrl_out_fifo_data(IQ_FIFO_TIMESTAMP_START+TIMESTAMP_WIDTH-1 downto IQ_FIFO_TIMESTAMP_START)
<= control_reg(conv_integer(control_rd_addr))(CONTROL_REG_TIMESTAMP_START+TIMESTAMP_WIDTH-1 downto CONTROL_REG_TIMESTAMP_START);
iqctrl_out_fifo_data(IQ_FIFO_PORTS_START+NR_PORTS-1 downto IQ_FIFO_PORTS_START)
<= control_reg(conv_integer(control_rd_addr))(CONTROL_REG_PORTS_START+NR_PORTS-1 downto CONTROL_REG_PORTS_START);
if control_reg_wr_sig = '1' and control_reg_rd_sig = '1' then
control_reg(conv_integer(control_rd_addr)+conv_integer(control_nr_entries))
<= iqctrl_in_lu_skip & iqctrl_in_lu_timestamp & iqctrl_in_lu_prio & iqctrl_in_lu_ports;
control_rd_addr <= control_rd_addr + 1;
elsif control_reg_wr_sig = '1' then
control_reg(conv_integer(control_rd_addr)+conv_integer(control_nr_entries))
<= iqctrl_in_lu_skip & iqctrl_in_lu_timestamp & iqctrl_in_lu_prio & iqctrl_in_lu_ports;
control_nr_entries <= control_nr_entries + 1;
elsif control_reg_rd_sig = '1' then
control_nr_entries <= control_nr_entries - 1;
control_rd_addr <= control_rd_addr + 1;
end if;
end if;
end if;
end process;
-- Decode next data_input_state, combinitorial logic
di_output_logic_p : process(cur_di_state, iqctrl_in_mac_valid, iqctrl_in_mac_last, mem_start_ptr_reg, frame_length_cnt,
iqctrl_in_mac_data, iqctrl_in_mac_error)
begin
-- default signal assignments
nxt_di_state <= IDLE;
iqctrl_out_mem_wenable <= iqctrl_in_mac_valid;
iqctrl_out_mem_data <= iqctrl_in_mac_data;
iqctrl_out_mem_addr <= mem_start_ptr_reg + frame_length_cnt;
update_frame_length_cnt <= '0';
update_mem_start_ptr <= '0';
data_reg_wr_sig <= '0';
case cur_di_state is
when IDLE =>
if iqctrl_in_mac_valid = '1' then
update_frame_length_cnt <= '1'; -- frame_length_cnt_p
nxt_di_state <= WRITE_MEM;
end if;
when WRITE_MEM =>
if iqctrl_in_mac_last = '1' and iqctrl_in_mac_valid = '1' then
nxt_di_state <= IDLE;
data_reg_wr_sig <= '1'; -- data_reg_p
if iqctrl_in_mac_error = '0' then
update_mem_start_ptr <= '1'; -- update_mem_ptr_p
end if;
elsif iqctrl_in_mac_valid = '1' then
nxt_di_state <= WRITE_MEM;
update_frame_length_cnt <= '1'; -- frame_length_cnt_p
else
nxt_di_state <= WRITE_MEM;
end if;
end case;
end process di_output_logic_p;
-- count bytes of the current frame
frame_length_cnt_p : process(clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
frame_length_cnt <= (others => '0');
else
frame_length_cnt <= frame_length_cnt + update_frame_length_cnt;
if nxt_di_state = IDLE then
frame_length_cnt <= (others => '0');
end if;
end if;
end if;
end process;
-- updates the start position of the next frame
update_mem_ptr_p : process(clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mem_start_ptr_reg <= (others => '0');
else
mem_start_ptr_reg <= mem_start_ptr_reg;
if update_mem_start_ptr = '1' then -- move start pointer to new 32-bit line
mem_start_ptr_reg <= mem_start_ptr_reg + frame_length_cnt + 1 +
(conv_integer(mem_start_ptr_reg + frame_length_cnt + 1) mod IQ_MEM_DATA_WIDTH_RATIO);
end if;
end if;
end if;
end process;
-- data register read and write accesses
data_reg_p : process(clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
data_rd_addr <= (others => '0');
data_nr_entries <= (others => '0');
iqctrl_out_fifo_data(IQ_FIFO_FRAME_LEN_START+FRAME_LENGTH_WIDTH-1 downto IQ_FIFO_FRAME_LEN_START)
<= (others => '0');
iqctrl_out_fifo_data(IQ_FIFO_MEM_PTR_START+IQ_MEM_ADDR_WIDTH-1 downto IQ_FIFO_MEM_PTR_START)
<= (others => '0');
else
data_rd_addr <= data_rd_addr;
data_nr_entries <= data_nr_entries;
iqctrl_out_fifo_data(IQ_FIFO_FRAME_LEN_START+FRAME_LENGTH_WIDTH-1 downto IQ_FIFO_FRAME_LEN_START)
<= data_reg(conv_integer(data_rd_addr))(DATA_REG_FRAME_LEN_START+FRAME_LENGTH_WIDTH-1 downto DATA_REG_FRAME_LEN_START);
iqctrl_out_fifo_data(IQ_FIFO_MEM_PTR_START+IQ_MEM_ADDR_WIDTH-1 downto IQ_FIFO_MEM_PTR_START)
<= data_reg(conv_integer(data_rd_addr))(DATA_REG_MEM_PTR_START+IQ_MEM_ADDR_WIDTH-1 downto DATA_REG_MEM_PTR_START);
if data_reg_wr_sig = '1' and data_reg_rd_sig = '1' then
data_reg(conv_integer(data_rd_addr)+conv_integer(data_nr_entries))
<= iqctrl_in_mac_error & mem_start_ptr_reg & frame_length_cnt + 1;
data_rd_addr <= data_rd_addr + 1;
elsif data_reg_wr_sig = '1' then
data_reg(conv_integer(data_rd_addr)+conv_integer(data_nr_entries))
<= iqctrl_in_mac_error & mem_start_ptr_reg & frame_length_cnt + 1;
data_nr_entries <= data_nr_entries + 1;
elsif data_reg_rd_sig = '1' then
data_rd_addr <= data_rd_addr + 1;
data_nr_entries <= data_nr_entries - 1;
end if;
end if;
end if;
end process;
-- Decode next config_output_state, combinitorial logic
co_output_logic_p : process(cur_co_state,control_nr_entries, data_nr_entries)
begin
-- default signal assignments
nxt_co_state <= IDLE;
control_reg_rd_sig <= '0';
data_reg_rd_sig <= '0';
write_fifo_sig <= '0';
case cur_co_state is
when IDLE =>
if control_nr_entries > 0 and data_nr_entries > 0 then
control_reg_rd_sig <= '1'; -- control_reg_p
data_reg_rd_sig <= '1'; -- data_reg_p
write_fifo_sig <= '1'; -- write_fifo_p
nxt_co_state <= WRITE_FIFO;
end if;
when WRITE_FIFO =>
nxt_co_state <= IDLE;
end case;
end process co_output_logic_p;
-- write data to fifo by setting the enable signal
write_fifo_p : process(clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
iqctrl_out_fifo_wenable <= '0';
else
iqctrl_out_fifo_wenable <= '0';
if write_fifo_sig = '1' then
if control_reg(conv_integer(control_rd_addr))(CONTROL_REG_SKIP_START) = '0'
and data_reg(conv_integer(data_rd_addr))(DATA_REG_ERROR_START) = '0'
and control_reg(conv_integer(control_rd_addr))(CONTROL_REG_PORTS_START+NR_PORTS-1 downto CONTROL_REG_PORTS_START) /= 0 then
iqctrl_out_fifo_wenable <= '1';
end if;
end if;
end if;
end if;
end process;
end rtl;
| mit | ae7a7edc3ee7c8949fec9addc80803bf | 0.545701 | 3.761883 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sim_1/imports/simulation/aeg_4ports_tb.vhd | 1 | 74,893 | ----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 23.12.2013 11:23:15
-- Design Name:
-- Module Name: aeg_4ports_tb - tb
-- Project Name: automotive ethernet gateway
--
-- Description:
-- testbench for ethernet switch with 4 ports
-- user can select which ports are to be active receiving frames on the rx (input) side (PORT_ENABLED)
-- every port monitors all of its frames on the tx (output) side independetly of active input side
-- the frames are inserted to the rx side by the p_stimulus processes
-- the frames are checked at the tx side by the p_monitor processes for correct syntax
-- every port sends two different kinds of frames back-to-back and periodically
-- the user can select the destination addresses, frame lengths and iterations of the frames
-- the user has the choice to select an input queue priority fifo (NR_IQ_FIFOS = 2)
-- the user has the choice to select an output queue priority fifo (NR_OQ_FIFOS = 2)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
use IEEE.std_logic_unsigned.all;
entity aeg_4ports_tb is
end aeg_4ports_tb;
architecture tb of aeg_4ports_tb is
-- aeg user constants
constant NR_PORTS : integer := 4; -- only four in this testbench
constant FABRIC_DATA_WIDTH : integer := 32; -- for other values, the memories and the constants of the address width have to be adjusted
-- input queue + output queue --> mem address width
-- input queue + output queue mem --> change ip data width
-- input queue control --> (de-)comment process at bottom accordingly
constant ARBITRATION : integer := 2; -- 1: Round Robin, 2: Priority based, 3: Latency based,
-- 4: Weighted prio/latency based, to do: 5: Fair Queuing
constant NR_IQ_FIFOS : integer := 2; -- [ 1, 2]
constant NR_OQ_FIFOS : integer := 2; -- [ 1, 2]
constant TIMESTAMP_WIDTH : integer := 64;
-- aeg fixed constants
constant GMII_DATA_WIDTH : integer := 8;
type frame_type is record
dest : std_logic_vector(7 downto 0); -- last byte of destination address
vlan_enable : boolean; -- indicates a vlan frame
vlan_prio : std_logic_vector(2 downto 0); -- vlan priority
frame_length : integer; -- length of the whole frame (including header)
iterations : integer; -- number of back to back transmissions of this frame
interframe_gap : integer; -- number of clock cycles between subsequent frames
end record;
type port_stimulus_type is record -- periodic stimulus of frames frame1 and frame2
frame1 : frame_type;
frame2 : frame_type;
iterations : integer;
end record;
-- aeg_tb stimuli 0123
constant PORT_ENABLED : std_logic_vector := "1111"; -- determines active ports receiving data
constant frame1_0 : frame_type := (
dest => x"21",
vlan_enable => false,
vlan_prio => "000",
frame_length => 64,
iterations => 1,
interframe_gap => 0);
constant frame2_0 : frame_type := (
dest => x"22", -- port 3 Non RT Traffic
vlan_enable => false,
vlan_prio => "000",
frame_length => 1024,
iterations => 1,
interframe_gap => 19115);
constant stim0 : port_stimulus_type := (frame1_0, frame2_0, 100);
constant frame1_1 : frame_type := (
dest => x"28",
vlan_enable => false,
vlan_prio => "000",
frame_length => 128,
iterations => 1,
interframe_gap => 0);
constant frame2_1 : frame_type := (
dest => x"02",
vlan_enable => false,
vlan_prio => "000",
frame_length => 970,
iterations => 1,
interframe_gap => 19115); -- RT Traffic
constant stim1 : port_stimulus_type := (frame1_1, frame2_1, 100);
constant frame1_2 : frame_type := (
dest => x"34",
vlan_enable => false,
vlan_prio => "000",
frame_length => 1518,
iterations => 1,
interframe_gap => 3076);
constant frame2_2 : frame_type := (
dest => x"38",
vlan_enable => false,
vlan_prio => "000",
frame_length => 64,
iterations => 0,
interframe_gap => 0);
constant stim2 : port_stimulus_type := (frame1_2, frame2_2, 0);
constant frame1_3 : frame_type := (
dest => x"44",
vlan_enable => true,
vlan_prio => "001",
frame_length => 200,
iterations => 1,
interframe_gap => 440);
constant frame2_3 : frame_type := (
dest => x"48",
vlan_enable => false,
vlan_prio => "000",
frame_length => 750,
iterations => 1,
interframe_gap => 1540);
constant stim3 : port_stimulus_type := (frame1_3, frame2_3, 0);
constant DA : std_logic_vector := x"DA";
constant SA : std_logic_vector := x"5A";
constant MAX_FRAME_LENGTH : integer := 1522;
-- testbench evaluation datatyps
type statistics_type is record
received_messages : integer; -- counter of received messages of this destination address
latency_100 : integer; -- number of messages up to 100 clock cycles
latency101_150 : integer;
latency151_200 : integer;
latency201_250 : integer;
latency251_300 : integer;
latency301_350 : integer;
latency351_400 : integer;
latency401_450 : integer;
latency451_500 : integer;
latency501_600 : integer;
latency601_700 : integer;
latency701_800 : integer;
latency801_900 : integer;
latency901_1000 : integer;
latency1001_1200 : integer;
latency1201_1400 : integer;
latency1401_1600 : integer;
latency1601_1800 : integer;
latency1801_2000 : integer;
latency2001_2200 : integer;
latency2201_2400 : integer;
latency2401_2600 : integer;
latency2601_2800 : integer;
latency2801_3000 : integer;
latency3001_3500 : integer;
latency3501_4000 : integer;
latency4001_4500 : integer;
latency4501_5000 : integer;
latency5001_5500 : integer;
latency5501_6000 : integer;
latency6001_6500 : integer;
latency6501_7000 : integer;
latency7001_7500 : integer;
latency7501_8000 : integer;
latency8001_8500 : integer;
latency8501_9000 : integer;
latency9001_9500 : integer;
latency9501_10000 : integer;
latency10001_12000 : integer;
latency12001_14000 : integer;
latency14001_16000 : integer;
latency16001_18000 : integer;
latency180001_20000 : integer;
latency20001_22500 : integer;
latency22501_25000 : integer;
latency25001_27500 : integer;
latency27501_30000 : integer;
latency30001_32500 : integer;
latency32501_35000 : integer;
latency35000x : integer;
end record;
type statistics_vector_type is array (0 to 255) of statistics_type;
type port_stats_type is record
received_frames : integer;
stat_vec : statistics_vector_type;
end record;
signal port_stats0 : port_stats_type := (received_frames => 0, stat_vec => (others => (others => 0)));
signal port_stats1 : port_stats_type := (received_frames => 0, stat_vec => (others => (others => 0)));
signal port_stats2 : port_stats_type := (received_frames => 0, stat_vec => (others => (others => 0)));
signal port_stats3 : port_stats_type := (received_frames => 0, stat_vec => (others => (others => 0)));
component automotive_ethernet_gateway is
Generic (
RECEIVER_DATA_WIDTH : integer := 8;
TRANSMITTER_DATA_WIDTH : integer := 8;
FABRIC_DATA_WIDTH : integer := 32;
NR_PORTS : integer := 4;
ARBITRATION : integer := 1;
FRAME_LENGTH_WIDTH : integer := 11;
NR_IQ_FIFOS : integer := 2;
NR_OQ_FIFOS : integer := 2;
TIMESTAMP_WIDTH : integer := 64;
GMII_DATA_WIDTH : integer := 8;
TX_IFG_DELAY_WIDTH : integer := 8;
PAUSE_VAL_WIDTH : integer := 16
);
port (
-- asynchronous reset
glbl_rst : in std_logic;
-- 200MHz clock input from board
clk_in_p : in std_logic;
clk_in_n : in std_logic;
phy_resetn : out std_logic_vector(NR_PORTS-1 downto 0);
intn : in std_logic_vector(NR_PORTS-1 downto 0);
latency : out std_logic_vector(NR_PORTS*TIMESTAMP_WIDTH-1 downto 0);
-- GMII Interface
-----------------
gmii_txd : out std_logic_vector(NR_PORTS*GMII_DATA_WIDTH-1 downto 0);
gmii_tx_en : out std_logic_vector(NR_PORTS-1 downto 0);
gmii_tx_er : out std_logic_vector(NR_PORTS-1 downto 0);
gmii_tx_clk : out std_logic_vector(NR_PORTS-1 downto 0);
gmii_rxd : in std_logic_vector(NR_PORTS*GMII_DATA_WIDTH-1 downto 0);
gmii_rx_dv : in std_logic_vector(NR_PORTS-1 downto 0);
gmii_rx_er : in std_logic_vector(NR_PORTS-1 downto 0);
gmii_rx_clk : in std_logic_vector(NR_PORTS-1 downto 0);
mii_tx_clk : in std_logic_vector(NR_PORTS-1 downto 0);
-- MDIO Interface
-----------------
mdio : inout std_logic_vector(NR_PORTS-1 downto 0);
mdc : out std_logic_vector(NR_PORTS-1 downto 0)
);
end component;
------------------------------------------------------------------------------
-- types to support frame data
------------------------------------------------------------------------------
type data_typ is record
data : std_logic_vector(7 downto 0); -- data
valid : std_logic; -- data_valid
error : std_logic; -- data_error
end record;
type frame_of_data_typ is array (natural range <>) of data_typ;
type frame_typ is record
columns : frame_of_data_typ(0 to MAX_FRAME_LENGTH); -- data field
interframe_gap : integer;
end record;
------------------------------------------------------------------------------
-- Stimulus - Frame data
------------------------------------------------------------------------------
shared variable frame_data0 : frame_typ;
shared variable frame_data1 : frame_typ;
shared variable frame_data2 : frame_typ;
shared variable frame_data3 : frame_typ;
------------------------------------------------------------------------------
-- CRC engine
------------------------------------------------------------------------------
function calc_crc (data : in std_logic_vector;
fcs : in std_logic_vector)
return std_logic_vector is
variable crc : std_logic_vector(31 downto 0);
variable crc_feedback : std_logic;
begin
crc := not fcs;
for I in 0 to 7 loop
crc_feedback := crc(0) xor data(I);
crc(4 downto 0) := crc(5 downto 1);
crc(5) := crc(6) xor crc_feedback;
crc(7 downto 6) := crc(8 downto 7);
crc(8) := crc(9) xor crc_feedback;
crc(9) := crc(10) xor crc_feedback;
crc(14 downto 10) := crc(15 downto 11);
crc(15) := crc(16) xor crc_feedback;
crc(18 downto 16) := crc(19 downto 17);
crc(19) := crc(20) xor crc_feedback;
crc(20) := crc(21) xor crc_feedback;
crc(21) := crc(22) xor crc_feedback;
crc(22) := crc(23);
crc(23) := crc(24) xor crc_feedback;
crc(24) := crc(25) xor crc_feedback;
crc(25) := crc(26);
crc(26) := crc(27) xor crc_feedback;
crc(27) := crc(28) xor crc_feedback;
crc(28) := crc(29);
crc(29) := crc(30) xor crc_feedback;
crc(30) := crc(31) xor crc_feedback;
crc(31) := crc_feedback;
end loop;
-- return the CRC result
return not crc;
end calc_crc;
function init_frame(
dest6 : in std_logic_vector(7 downto 0);
source6 : in std_logic_vector(7 downto 0);
vlan_enable : in boolean;
vlan_priority : in std_logic_vector(2 downto 0);
length : in integer;
interframe_gap : in integer
)
return frame_typ is
variable frame_data : frame_typ;
variable length_type : std_logic_vector(15 downto 0);
variable data_byte : std_logic_vector(15 downto 0);
variable i : integer;
variable vlan_bytes : integer := 0;
begin
if dest6 = x"FF" then
frame_data.columns(0) := ( DATA => dest6, VALID => '1', ERROR => '0'); -- Destination Address,
frame_data.columns(1) := ( DATA => dest6, VALID => '1', ERROR => '0');
frame_data.columns(2) := ( DATA => dest6, VALID => '1', ERROR => '0');
frame_data.columns(3) := ( DATA => dest6, VALID => '1', ERROR => '0');
frame_data.columns(4) := ( DATA => dest6, VALID => '1', ERROR => '0');
else
frame_data.columns(0) := ( DATA => DA, VALID => '1', ERROR => '0'); -- Destination Address,
frame_data.columns(1) := ( DATA => DA, VALID => '1', ERROR => '0');
frame_data.columns(2) := ( DATA => DA, VALID => '1', ERROR => '0');
frame_data.columns(3) := ( DATA => DA, VALID => '1', ERROR => '0');
frame_data.columns(4) := ( DATA => DA, VALID => '1', ERROR => '0');
end if;
frame_data.columns(5) := ( DATA => dest6, VALID => '1', ERROR => '0');
frame_data.columns(6) := ( DATA => SA, VALID => '1', ERROR => '0'); -- Source Address
frame_data.columns(7) := ( DATA => SA, VALID => '1', ERROR => '0');
frame_data.columns(8) := ( DATA => SA, VALID => '1', ERROR => '0');
frame_data.columns(9) := ( DATA => SA, VALID => '1', ERROR => '0');
frame_data.columns(10) := ( DATA => SA, VALID => '1', ERROR => '0');
frame_data.columns(11) := ( DATA => source6, VALID => '1', ERROR => '0');
-- VLAN
if vlan_enable then
vlan_bytes := 4;
frame_data.columns(12) := ( DATA => x"81", VALID => '1', ERROR => '0'); -- VLAN Identifier
frame_data.columns(13) := ( DATA => x"00", VALID => '1', ERROR => '0');
data_byte := x"00" & vlan_priority & "00000"; -- VLAN Priority
frame_data.columns(14) := ( DATA => data_byte(7 downto 0), VALID => '1', ERROR => '0');
frame_data.columns(15) := ( DATA => x"00", VALID => '1', ERROR => '0');
end if;
-- Length/Type
length_type := std_logic_vector(to_unsigned(length-18-vlan_bytes,length_type'length));
frame_data.columns(12+vlan_bytes) := ( DATA => length_type(15 downto 8), VALID => '1', ERROR => '0');
frame_data.columns(13+vlan_bytes) := ( DATA => length_type(7 downto 0), VALID => '1', ERROR => '0');
-- Payload
i := 14+vlan_bytes;
while i < length - 4 loop
data_byte := std_logic_vector(to_unsigned(i-13-vlan_bytes ,data_byte'length));
frame_data.columns(i) := ( DATA => data_byte(7 downto 0), VALID => '1', ERROR => '0');
i := i+1;
end loop;
-- Padding
while i < 60+vlan_bytes loop
frame_data.columns(i) := ( DATA => X"00", VALID => '1', ERROR => '0');
i := i+1;
end loop;
-- Stop writing
frame_data.columns(i) := ( DATA => X"00", VALID => '0', ERROR => '0');
-- interframe_gap
frame_data.interframe_gap := interframe_gap;
return frame_data;
end init_frame;
function update_stats(
port_stats_in : in port_stats_type;
data : in std_logic_vector(7 downto 0);
latency : in std_logic_vector(63 downto 0)
)
return port_stats_type is
variable port_stats : port_stats_type;
variable data_int : integer;
variable latency_int : integer;
begin
data_int := to_integer(unsigned(data));
latency_int := to_integer(unsigned(latency));
port_stats := port_stats_in;
port_stats.received_frames := port_stats.received_frames + 1;
port_stats.stat_vec(data_int).received_messages := port_stats.stat_vec(data_int).received_messages + 1;
if latency_int <= 100 then
port_stats.stat_vec(data_int).latency_100 := port_stats.stat_vec(data_int).latency_100 + 1;
elsif latency_int <= 150 then
port_stats.stat_vec(data_int).latency101_150 := port_stats.stat_vec(data_int).latency101_150 + 1;
elsif latency_int <= 200 then
port_stats.stat_vec(data_int).latency151_200 := port_stats.stat_vec(data_int).latency151_200 + 1;
elsif latency_int <= 250 then
port_stats.stat_vec(data_int).latency201_250 := port_stats.stat_vec(data_int).latency201_250 + 1;
elsif latency_int <= 300 then
port_stats.stat_vec(data_int).latency251_300 := port_stats.stat_vec(data_int).latency251_300 + 1;
elsif latency_int <= 350 then
port_stats.stat_vec(data_int).latency301_350 := port_stats.stat_vec(data_int).latency301_350 + 1;
elsif latency_int <= 400 then
port_stats.stat_vec(data_int).latency351_400 := port_stats.stat_vec(data_int).latency351_400 + 1;
elsif latency_int <= 450 then
port_stats.stat_vec(data_int).latency401_450 := port_stats.stat_vec(data_int).latency401_450 + 1;
elsif latency_int <= 500 then
port_stats.stat_vec(data_int).latency451_500 := port_stats.stat_vec(data_int).latency451_500 + 1;
elsif latency_int <= 600 then
port_stats.stat_vec(data_int).latency501_600 := port_stats.stat_vec(data_int).latency501_600 + 1;
elsif latency_int <= 700 then
port_stats.stat_vec(data_int).latency601_700 := port_stats.stat_vec(data_int).latency601_700 + 1;
elsif latency_int <= 800 then
port_stats.stat_vec(data_int).latency701_800 := port_stats.stat_vec(data_int).latency701_800 + 1;
elsif latency_int <= 900 then
port_stats.stat_vec(data_int).latency801_900 := port_stats.stat_vec(data_int).latency801_900 + 1;
elsif latency_int <= 1000 then
port_stats.stat_vec(data_int).latency901_1000 := port_stats.stat_vec(data_int).latency901_1000 + 1;
elsif latency_int <= 1200 then
port_stats.stat_vec(data_int).latency1001_1200 := port_stats.stat_vec(data_int).latency1001_1200 + 1;
elsif latency_int <= 1400 then
port_stats.stat_vec(data_int).latency1201_1400 := port_stats.stat_vec(data_int).latency1201_1400 + 1;
elsif latency_int <= 1600 then
port_stats.stat_vec(data_int).latency1401_1600 := port_stats.stat_vec(data_int).latency1401_1600 + 1;
elsif latency_int <= 1800 then
port_stats.stat_vec(data_int).latency1601_1800 := port_stats.stat_vec(data_int).latency1601_1800 + 1;
elsif latency_int <= 2000 then
port_stats.stat_vec(data_int).latency1801_2000 := port_stats.stat_vec(data_int).latency1801_2000 + 1;
elsif latency_int <= 2200 then
port_stats.stat_vec(data_int).latency2001_2200 := port_stats.stat_vec(data_int).latency2001_2200 + 1;
elsif latency_int <= 2400 then
port_stats.stat_vec(data_int).latency2201_2400 := port_stats.stat_vec(data_int).latency2201_2400 + 1;
elsif latency_int <= 2600 then
port_stats.stat_vec(data_int).latency2401_2600 := port_stats.stat_vec(data_int).latency2401_2600 + 1;
elsif latency_int <= 2800 then
port_stats.stat_vec(data_int).latency2601_2800 := port_stats.stat_vec(data_int).latency2601_2800 + 1;
elsif latency_int <= 3000 then
port_stats.stat_vec(data_int).latency2801_3000 := port_stats.stat_vec(data_int).latency2801_3000 + 1;
elsif latency_int <= 3500 then
port_stats.stat_vec(data_int).latency3001_3500 := port_stats.stat_vec(data_int).latency3001_3500 + 1;
elsif latency_int <= 4000 then
port_stats.stat_vec(data_int).latency3501_4000 := port_stats.stat_vec(data_int).latency3501_4000 + 1;
elsif latency_int <= 4500 then
port_stats.stat_vec(data_int).latency4001_4500 := port_stats.stat_vec(data_int).latency4001_4500 + 1;
elsif latency_int <= 5000 then
port_stats.stat_vec(data_int).latency4501_5000 := port_stats.stat_vec(data_int).latency4501_5000 + 1;
elsif latency_int <= 5500 then
port_stats.stat_vec(data_int).latency5001_5500 := port_stats.stat_vec(data_int).latency5001_5500 + 1;
elsif latency_int <= 6000 then
port_stats.stat_vec(data_int).latency5501_6000 := port_stats.stat_vec(data_int).latency5501_6000 + 1;
elsif latency_int <= 6500 then
port_stats.stat_vec(data_int).latency6001_6500 := port_stats.stat_vec(data_int).latency6001_6500 + 1;
elsif latency_int <= 7000 then
port_stats.stat_vec(data_int).latency6501_7000 := port_stats.stat_vec(data_int).latency6501_7000 + 1;
elsif latency_int <= 7500 then
port_stats.stat_vec(data_int).latency7001_7500 := port_stats.stat_vec(data_int).latency7001_7500 + 1;
elsif latency_int <= 8000 then
port_stats.stat_vec(data_int).latency7501_8000 := port_stats.stat_vec(data_int).latency7501_8000 + 1;
elsif latency_int <= 8500 then
port_stats.stat_vec(data_int).latency8001_8500 := port_stats.stat_vec(data_int).latency8001_8500 + 1;
elsif latency_int <= 9000 then
port_stats.stat_vec(data_int).latency8501_9000 := port_stats.stat_vec(data_int).latency8501_9000 + 1;
elsif latency_int <= 9500 then
port_stats.stat_vec(data_int).latency9001_9500 := port_stats.stat_vec(data_int).latency9001_9500 + 1;
elsif latency_int <= 10000 then
port_stats.stat_vec(data_int).latency9501_10000 := port_stats.stat_vec(data_int).latency9501_10000 + 1;
elsif latency_int <= 12000 then
port_stats.stat_vec(data_int).latency10001_12000 := port_stats.stat_vec(data_int).latency10001_12000 + 1;
elsif latency_int <= 14000 then
port_stats.stat_vec(data_int).latency12001_14000 := port_stats.stat_vec(data_int).latency12001_14000 + 1;
elsif latency_int <= 16000 then
port_stats.stat_vec(data_int).latency14001_16000 := port_stats.stat_vec(data_int).latency14001_16000 + 1;
elsif latency_int <= 18000 then
port_stats.stat_vec(data_int).latency16001_18000 := port_stats.stat_vec(data_int).latency16001_18000 + 1;
elsif latency_int <= 20000 then
port_stats.stat_vec(data_int).latency180001_20000 := port_stats.stat_vec(data_int).latency180001_20000 + 1;
elsif latency_int <= 22500 then
port_stats.stat_vec(data_int).latency20001_22500 := port_stats.stat_vec(data_int).latency20001_22500 + 1;
elsif latency_int <= 25000 then
port_stats.stat_vec(data_int).latency22501_25000 := port_stats.stat_vec(data_int).latency22501_25000 + 1;
elsif latency_int <= 27500 then
port_stats.stat_vec(data_int).latency25001_27500 := port_stats.stat_vec(data_int).latency25001_27500 + 1;
elsif latency_int <= 30000 then
port_stats.stat_vec(data_int).latency27501_30000 := port_stats.stat_vec(data_int).latency27501_30000 + 1;
elsif latency_int <= 32500 then
port_stats.stat_vec(data_int).latency30001_32500 := port_stats.stat_vec(data_int).latency30001_32500 + 1;
elsif latency_int <= 35000 then
port_stats.stat_vec(data_int).latency32501_35000 := port_stats.stat_vec(data_int).latency32501_35000 + 1;
else
port_stats.stat_vec(data_int).latency35000x := port_stats.stat_vec(data_int).latency35000x + 1;
end if;
return port_stats;
end update_stats;
-- testbench signals
constant gtx_period : time := 2.5 ns;
signal gtx_clk : std_logic;
signal gtx_clkn : std_logic;
signal reset : std_logic := '0';
signal demo_mode_error : std_logic_vector(3 downto 0) := (others => '0');
-- signal mdc : std_logic_vector(NR_PORTS-1 downto 0);
-- signal mdio : std_logic_vector(NR_PORTS-1 downto 0);
signal gmii_tx_clk : std_logic_vector(NR_PORTS-1 downto 0);
signal gmii_tx_en : std_logic_vector(NR_PORTS-1 downto 0);
signal gmii_tx_er : std_logic_vector(NR_PORTS-1 downto 0);
signal gmii_txd : std_logic_vector(NR_PORTS*GMII_DATA_WIDTH-1 downto 0) := (others => '0');
signal gmii_rx_clk : std_logic_vector(NR_PORTS-1 downto 0);
signal gmii_rx_dv : std_logic_vector(NR_PORTS-1 downto 0) := (others => '0');
signal gmii_rx_er : std_logic_vector(NR_PORTS-1 downto 0) := (others => '0');
signal gmii_rxd : std_logic_vector(NR_PORTS*GMII_DATA_WIDTH-1 downto 0) := (others => '0');
signal mii_tx_clk : std_logic_vector(NR_PORTS-1 downto 0) := (others => '0');
signal mdc : std_logic_vector(NR_PORTS-1 downto 0) := (others => '0');
signal mdio : std_logic_vector(NR_PORTS-1 downto 0) := (others => '0');
signal latency : std_logic_vector(NR_PORTS*TIMESTAMP_WIDTH-1 downto 0);
signal latency0 : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
signal latency1 : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
signal latency2 : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
signal latency3 : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
-- testbench control signals
signal reset_finished : boolean := false;
signal port0_finished : boolean := false;
signal port1_finished : boolean := false;
signal port2_finished : boolean := false;
signal port3_finished : boolean := false;
begin
latency0 <= latency(63 downto 0);
latency1 <= latency(127 downto 64);
latency2 <= latency(191 downto 128);
latency3 <= latency(255 downto 192);
------------------------------------------------------------------------------
-- Wire up Device Under Test
------------------------------------------------------------------------------
dut: automotive_ethernet_gateway
generic map(
NR_PORTS => NR_PORTS,
FABRIC_DATA_WIDTH => FABRIC_DATA_WIDTH,
ARBITRATION => ARBITRATION,
NR_IQ_FIFOS => NR_IQ_FIFOS,
NR_OQ_FIFOS => NR_OQ_FIFOS,
TIMESTAMP_WIDTH => TIMESTAMP_WIDTH
)
port map (
-- asynchronous reset
--------------------------------
glbl_rst => reset,
-- 200MHz clock input from board
clk_in_p => gtx_clk,
clk_in_n => gtx_clkn,
phy_resetn => open,
intn => "0000",
latency => latency,
-- GMII Interface
--------------------------------
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_tx_clk => gmii_tx_clk,
gmii_rxd => gmii_rxd,
gmii_rx_dv => gmii_rx_dv,
gmii_rx_er => gmii_rx_er,
gmii_rx_clk => gmii_rx_clk,
mii_tx_clk => mii_tx_clk,
-- MDIO Interface
mdc => mdc,
mdio => mdio
);
------------------------------------------------------------------------------
-- If the simulation is still going after delay below
-- then something has gone wrong: terminate with an error
------------------------------------------------------------------------------
p_timebomb : process
begin
wait for 2000 us;
assert false
report "ERROR - Simulation running forever!"
severity failure;
end process p_timebomb;
------------------------------------------------------------------------------
-- Clock drivers
------------------------------------------------------------------------------
-- drives input to an MMCM at 200MHz which creates gtx_clk at 125 MHz
p_gtx_clk : process
begin
gtx_clk <= '0';
gtx_clkn <= '1';
wait for 80 ns;
loop
wait for gtx_period;
gtx_clk <= '1';
gtx_clkn <= '0';
wait for gtx_period;
gtx_clk <= '0';
gtx_clkn <= '1';
end loop;
end process p_gtx_clk;
gmii_rx_clk <= gmii_tx_clk;
-----------------------------------------------------------------------------
-- init process.
-----------------------------------------------------------------------------
p_init : process
procedure mac_reset is
begin
assert false
report "Resetting core..." & cr
severity note;
reset <= '1';
wait for 200 ns;
reset <= '0';
assert false
report "Timing checks are valid" & cr
severity note;
end procedure mac_reset;
begin
assert false
report "Timing checks are not valid" & cr
severity note;
wait for 800 ns;
mac_reset;
reset_finished <= true;
wait;
end process p_init;
p_stop : process
begin
wait until port3_finished and port2_finished and port1_finished and port0_finished;
if demo_mode_error /= 0 then
assert false
report "Errors occured"
severity error;
end if;
wait for 100 us;
assert false
report "Simulation Completed without errors"
severity failure;
end process p_stop;
------------------------------------------------------------------------------
-- Stimulus process on port 0 (traffic generator)
------------------------------------------------------------------------------
p_stimulus0 : process
------------------------------
-- Procedure to inject a frame
------------------------------
procedure send_frame is
variable current_col : natural := 0; -- Column counter within frame
variable fcs : std_logic_vector(31 downto 0);
begin
wait until gmii_rx_clk(0)'event and gmii_rx_clk(0) = '1';
-- Reset the FCS calculation
fcs := (others => '0');
-- Adding the preamble field
for j in 0 to 7 loop
gmii_rxd(7 downto 0) <= "01010101";
gmii_rx_dv(0) <= '1';
gmii_rx_er(0) <= '0';
wait until gmii_rx_clk(0)'event and gmii_rx_clk(0) = '1';
end loop;
-- Adding the Start of Frame Delimiter (SFD)
gmii_rxd(7 downto 0) <= "11010101";
gmii_rx_dv(0) <= '1';
wait until gmii_rx_clk(0)'event and gmii_rx_clk(0) = '1';
current_col := 0;
gmii_rxd(7 downto 0) <= frame_data0.columns(current_col).data;
gmii_rx_dv(0) <= frame_data0.columns(current_col).valid;
gmii_rx_er(0) <= frame_data0.columns(current_col).error;
fcs := calc_crc(frame_data0.columns(current_col).data, fcs);
wait until gmii_rx_clk(0)'event and gmii_rx_clk(0) = '1';
current_col := current_col + 1;
-- loop over columns in frame.
while frame_data0.columns(current_col).valid /= '0' loop
-- send one column of data
gmii_rxd(7 downto 0) <= frame_data0.columns(current_col).data;
gmii_rx_dv(0) <= frame_data0.columns(current_col).valid;
gmii_rx_er(0) <= frame_data0.columns(current_col).error;
fcs := calc_crc(frame_data0.columns(current_col).data, fcs);
current_col := current_col + 1;
wait until gmii_rx_clk(0)'event and gmii_rx_clk(0) = '1';
end loop;
-- Send the CRC.
for j in 0 to 3 loop
gmii_rxd(7 downto 0) <= fcs(((8*j)+7) downto (8*j));
gmii_rx_dv(0) <= '1';
gmii_rx_er(0) <= '0';
wait until gmii_rx_clk(0)'event and gmii_rx_clk(0) = '1';
end loop;
-- Clear the data lines.
gmii_rxd(7 downto 0) <= (others => '0');
gmii_rx_dv(0) <= '0';
-- Adding the minimum Interframe gap for a receiver (12 idles)
for j in 0 to 9 loop
wait until gmii_rx_clk(0)'event and gmii_rx_clk(0) = '1';
end loop;
-- Adding further interframe gap as secified by the user
for j in 0 to frame_data0.interframe_gap loop
wait until gmii_rx_clk(0)'event and gmii_rx_clk(0) = '1';
end loop;
end send_frame;
variable frame_sa : std_logic_vector(7 downto 0);
variable frame_da : std_logic_vector(7 downto 0);
begin
-- Wait for the Management MDIO transaction to finish.
wait until reset_finished;
-- Wait for the internal resets to settle
wait for 800 ns;
frame_sa := X"00";
if PORT_ENABLED(0) = '0' then
port0_finished <= true;
else
for i in 0 to stim0.iterations-1 loop
for j in 0 to stim0.frame1.iterations-1 loop
frame_data0 := init_frame(stim0.frame1.dest, frame_sa, stim0.frame1.vlan_enable,
stim0.frame1.vlan_prio, stim0.frame1.frame_length, stim0.frame1.interframe_gap);
send_frame;
end loop;
for j in 0 to stim0.frame2.iterations-1 loop
frame_data0 := init_frame(stim0.frame2.dest, frame_sa, stim0.frame2.vlan_enable,
stim0.frame2.vlan_prio, stim0.frame2.frame_length, stim0.frame2.interframe_gap);
send_frame;
end loop;
end loop;
port0_finished <= true;
end if;
end process p_stimulus0;
------------------------------------------------------------------------------
-- Stimulus process on port 1
------------------------------------------------------------------------------
p_stimulus1 : process
------------------------------
-- Procedure to inject a frame
------------------------------
procedure send_frame is
variable current_col : natural := 0; -- Column counter within frame
variable fcs : std_logic_vector(31 downto 0);
begin
wait until gmii_rx_clk(1)'event and gmii_rx_clk(1) = '1';
-- Reset the FCS calculation
fcs := (others => '0');
-- Adding the preamble field
for j in 0 to 7 loop
gmii_rxd(15 downto 8) <= "01010101";
gmii_rx_dv(1) <= '1';
gmii_rx_er(1) <= '0';
wait until gmii_rx_clk(1)'event and gmii_rx_clk(1) = '1';
end loop;
-- Adding the Start of Frame Delimiter (SFD)
gmii_rxd(15 downto 8) <= "11010101";
gmii_rx_dv(1) <= '1';
wait until gmii_rx_clk(1)'event and gmii_rx_clk(1) = '1';
current_col := 0;
gmii_rxd(15 downto 8) <= frame_data1.columns(current_col).data;
gmii_rx_dv(1) <= frame_data1.columns(current_col).valid;
gmii_rx_er(1) <= frame_data1.columns(current_col).error;
fcs := calc_crc(frame_data1.columns(current_col).data, fcs);
wait until gmii_rx_clk(1)'event and gmii_rx_clk(1) = '1';
current_col := current_col + 1;
-- loop over columns in frame.
while frame_data1.columns(current_col).valid /= '0' loop
-- send one column of data
gmii_rxd(15 downto 8) <= frame_data1.columns(current_col).data;
gmii_rx_dv(1) <= frame_data1.columns(current_col).valid;
gmii_rx_er(1) <= frame_data1.columns(current_col).error;
fcs := calc_crc(frame_data1.columns(current_col).data, fcs);
current_col := current_col + 1;
wait until gmii_rx_clk(1)'event and gmii_rx_clk(1) = '1';
end loop;
-- Send the CRC.
for j in 0 to 3 loop
gmii_rxd(15 downto 8) <= fcs(((8*j)+7) downto (8*j));
gmii_rx_dv(1) <= '1';
gmii_rx_er(1) <= '0';
wait until gmii_rx_clk(1)'event and gmii_rx_clk(1) = '1';
end loop;
-- Clear the data lines.
gmii_rxd(15 downto 8) <= (others => '0');
gmii_rx_dv(1) <= '0';
-- Adding the minimum Interframe gap for a receiver (12 idles)
for j in 0 to 9 loop
wait until gmii_rx_clk(1)'event and gmii_rx_clk(1) = '1';
end loop;
-- Adding further interframe gap as secified by the user
for j in 0 to frame_data1.interframe_gap loop
wait until gmii_rx_clk(1)'event and gmii_rx_clk(1) = '1';
end loop;
end send_frame;
variable frame_sa : std_logic_vector(7 downto 0);
variable frame_da : std_logic_vector(7 downto 0);
begin
-- Wait for the Management MDIO transaction to finish.
wait until reset_finished;
-- Wait for the internal resets to settle
wait for 800 ns;
-- inject frames back to back
frame_sa := X"01";
if PORT_ENABLED(1) = '0' then
port1_finished <= true;
else
for i in 0 to stim1.iterations-1 loop
for j in 0 to stim1.frame1.iterations-1 loop
frame_data1 := init_frame(stim1.frame1.dest, frame_sa, stim1.frame1.vlan_enable,
stim1.frame1.vlan_prio, stim1.frame1.frame_length, stim1.frame1.interframe_gap);
send_frame;
end loop;
for j in 0 to stim1.frame2.iterations-1 loop
frame_data1 := init_frame(stim1.frame2.dest, frame_sa, stim1.frame2.vlan_enable,
stim1.frame2.vlan_prio, stim1.frame2.frame_length, stim1.frame2.interframe_gap);
send_frame;
end loop;
end loop;
port1_finished <= true;
end if;
end process p_stimulus1;
------------------------------------------------------------------------------
-- Stimulus process on port 2
------------------------------------------------------------------------------
p_stimulus2 : process
------------------------------
-- Procedure to inject a frame
------------------------------
procedure send_frame is
variable current_col : natural := 0; -- Column counter within frame
variable fcs : std_logic_vector(31 downto 0);
begin
wait until gmii_rx_clk(2)'event and gmii_rx_clk(2) = '1';
-- Reset the FCS calculation
fcs := (others => '0');
-- Adding the preamble field
for j in 0 to 7 loop
gmii_rxd(23 downto 16) <= "01010101";
gmii_rx_dv(2) <= '1';
gmii_rx_er(2) <= '0';
wait until gmii_rx_clk(2)'event and gmii_rx_clk(2) = '1';
end loop;
-- Adding the Start of Frame Delimiter (SFD)
gmii_rxd(23 downto 16) <= "11010101";
gmii_rx_dv(2) <= '1';
wait until gmii_rx_clk(2)'event and gmii_rx_clk(2) = '1';
current_col := 0;
gmii_rxd(23 downto 16) <= frame_data2.columns(current_col).data;
gmii_rx_dv(2) <= frame_data2.columns(current_col).valid;
gmii_rx_er(2) <= frame_data2.columns(current_col).error;
fcs := calc_crc(frame_data2.columns(current_col).data, fcs);
wait until gmii_rx_clk(2)'event and gmii_rx_clk(2) = '1';
current_col := current_col + 1;
-- loop over columns in frame.
while frame_data2.columns(current_col).valid /= '0' loop
-- send one column of data
gmii_rxd(23 downto 16) <= frame_data2.columns(current_col).data;
gmii_rx_dv(2) <= frame_data2.columns(current_col).valid;
gmii_rx_er(2) <= frame_data2.columns(current_col).error;
fcs := calc_crc(frame_data2.columns(current_col).data, fcs);
current_col := current_col + 1;
wait until gmii_rx_clk(2)'event and gmii_rx_clk(2) = '1';
end loop;
-- Send the CRC.
for j in 0 to 3 loop
gmii_rxd(23 downto 16) <= fcs(((8*j)+7) downto (8*j));
gmii_rx_dv(2) <= '1';
gmii_rx_er(2) <= '0';
wait until gmii_rx_clk(2)'event and gmii_rx_clk(2) = '1';
end loop;
-- Clear the data lines.
gmii_rxd(23 downto 16) <= (others => '0');
gmii_rx_dv(2) <= '0';
-- Adding the minimum Interframe gap for a receiver (12 idles)
for j in 0 to 9 loop
wait until gmii_rx_clk(2)'event and gmii_rx_clk(2) = '1';
end loop;
-- Adding further interframe gap as secified by the user
for j in 0 to frame_data2.interframe_gap loop
wait until gmii_rx_clk(2)'event and gmii_rx_clk(2) = '1';
end loop;
end send_frame;
variable frame_sa : std_logic_vector(7 downto 0);
variable frame_da : std_logic_vector(7 downto 0);
begin
-- Wait for the Management MDIO transaction to finish.
wait until reset_finished;
-- Wait for the internal resets to settle
wait for 800 ns;
-- inject frames back to back
frame_sa := X"02";
if PORT_ENABLED(2) = '0' then
port2_finished <= true;
else
for i in 0 to stim2.iterations-1 loop
for j in 0 to stim2.frame1.iterations-1 loop
frame_data2 := init_frame(stim2.frame1.dest, frame_sa, stim2.frame1.vlan_enable,
stim2.frame1.vlan_prio, stim2.frame1.frame_length, stim2.frame1.interframe_gap);
send_frame;
end loop;
for j in 0 to stim2.frame2.iterations-1 loop
frame_data2 := init_frame(stim2.frame2.dest, frame_sa, stim2.frame2.vlan_enable,
stim2.frame2.vlan_prio, stim2.frame2.frame_length, stim2.frame2.interframe_gap);
send_frame;
end loop;
end loop;
port2_finished <= true;
end if;
end process p_stimulus2;
------------------------------------------------------------------------------
-- Stimulus process on port 3
------------------------------------------------------------------------------
p_stimulus3 : process
------------------------------
-- Procedure to inject a frame
------------------------------
procedure send_frame is
variable current_col : natural := 0; -- Column counter within frame
variable fcs : std_logic_vector(31 downto 0);
begin
wait until gmii_rx_clk(3)'event and gmii_rx_clk(3) = '1';
-- Reset the FCS calculation
fcs := (others => '0');
-- Adding the preamble field
for j in 0 to 7 loop
gmii_rxd(31 downto 24) <= "01010101";
gmii_rx_dv(3) <= '1';
gmii_rx_er(3) <= '0';
wait until gmii_rx_clk(3)'event and gmii_rx_clk(3) = '1';
end loop;
-- Adding the Start of Frame Delimiter (SFD)
gmii_rxd(31 downto 24) <= "11010101";
gmii_rx_dv(3) <= '1';
wait until gmii_rx_clk(3)'event and gmii_rx_clk(3) = '1';
current_col := 0;
gmii_rxd(31 downto 24) <= frame_data3.columns(current_col).data;
gmii_rx_dv(3) <= frame_data3.columns(current_col).valid;
gmii_rx_er(3) <= frame_data3.columns(current_col).error;
fcs := calc_crc(frame_data3.columns(current_col).data, fcs);
wait until gmii_rx_clk(3)'event and gmii_rx_clk(3) = '1';
current_col := current_col + 1;
-- loop over columns in frame.
while frame_data3.columns(current_col).valid /= '0' loop
-- send one column of data
gmii_rxd(31 downto 24) <= frame_data3.columns(current_col).data;
gmii_rx_dv(3) <= frame_data3.columns(current_col).valid;
gmii_rx_er(3) <= frame_data3.columns(current_col).error;
fcs := calc_crc(frame_data3.columns(current_col).data, fcs);
current_col := current_col + 1;
wait until gmii_rx_clk(3)'event and gmii_rx_clk(3) = '1';
end loop;
-- Send the CRC.
for j in 0 to 3 loop
gmii_rxd(31 downto 24) <= fcs(((8*j)+7) downto (8*j));
gmii_rx_dv(3) <= '1';
gmii_rx_er(3) <= '0';
wait until gmii_rx_clk(3)'event and gmii_rx_clk(3) = '1';
end loop;
-- Clear the data lines.
gmii_rxd(31 downto 24) <= (others => '0');
gmii_rx_dv(3) <= '0';
-- Adding the minimum Interframe gap for a receiver (12 idles)
for j in 0 to 9 loop
wait until gmii_rx_clk(3)'event and gmii_rx_clk(3) = '1';
end loop;
-- Adding further interframe gap as secified by the user
for j in 0 to frame_data3.interframe_gap loop
wait until gmii_rx_clk(3)'event and gmii_rx_clk(3) = '1';
end loop;
end send_frame;
variable frame_sa : std_logic_vector(7 downto 0);
variable frame_da : std_logic_vector(7 downto 0);
begin
-- Wait for the Management MDIO transaction to finish.
wait until reset_finished;
-- Wait for the internal resets to settle
wait for 800 ns;
-- inject frames back to back
frame_sa := X"03";
if PORT_ENABLED(3) = '0' then
port3_finished <= true;
else
for i in 0 to stim3.iterations-1 loop
for j in 0 to stim3.frame1.iterations-1 loop
frame_data3 := init_frame(stim3.frame1.dest, frame_sa, stim3.frame1.vlan_enable,
stim3.frame1.vlan_prio, stim3.frame1.frame_length, stim3.frame1.interframe_gap);
send_frame;
end loop;
for j in 0 to stim3.frame2.iterations-1 loop
frame_data3 := init_frame(stim3.frame2.dest, frame_sa, stim3.frame2.vlan_enable,
stim3.frame2.vlan_prio, stim3.frame2.frame_length, stim3.frame2.interframe_gap);
send_frame;
end loop;
end loop;
port3_finished <= true;
end if;
end process p_stimulus3;
------------------------------------------------------------------------------
-- Monitor process. This process checks the data coming out of the
-- transmitter to make sure that it matches that inserted into the
-- receiver.
------------------------------------------------------------------------------
p_monitor0 : process
procedure check_frame is
variable current_col : natural := 0;
variable byte_cnt : natural := 0;
variable fcs : std_logic_vector(31 downto 0);
variable length : std_logic_vector(15 downto 0);
variable vlan_bytes : natural := 0;
begin
-- Reset the FCS calculation
fcs := (others => '0');
-- Parse over the preamble field
while gmii_tx_en(0) /= '1' or gmii_txd(7 downto 0) = "01010101" loop
wait until gmii_tx_clk(0)'event and gmii_tx_clk(0) = '1';
end loop;
-- Parse over the Start of Frame Delimiter (SFD)
if (gmii_txd(7 downto 0) /= "11010101") then
assert false
report "SFD not present @ Port 0" & cr
severity error;
end if;
wait until gmii_tx_clk(0)'event and gmii_tx_clk(0) = '1';
-- frame has started, loop over columns of frame
while current_col < 60+vlan_bytes or byte_cnt < length loop
-- check destination address
if current_col < 5 and gmii_txd(7 downto 0) /= x"FF" then
if gmii_txd(7 downto 0) /= DA then
demo_mode_error(0) <= '1';
assert false
report "gmii_txd incorrect during Destination Address field @ Port 0" & cr
severity error;
end if;
end if;
if current_col = 5 then
port_stats0 <= update_stats(port_stats0, gmii_txd(7 downto 0), latency0);
end if;
-- check source address
if current_col >= 6 and current_col < 11 then
if gmii_txd(7 downto 0) /= SA then
demo_mode_error(0) <= '1';
assert false
report "gmii_txd incorrect during Source Address field @ Port 0" & cr
severity error;
end if;
end if;
-- read length / vlan
if current_col = 12 then
if gmii_txd(7 downto 0) = x"81" then
vlan_bytes := 4;
else
vlan_bytes := 0;
length(15 downto 8) := gmii_txd(7 downto 0);
end if;
end if;
if current_col = 13 then
if vlan_bytes = 4 then
if gmii_txd(7 downto 0) /= x"00" then
demo_mode_error(0) <= '1';
assert false
report "vlan incorrect @ Port 0" & cr
severity error;
end if;
else
length(7 downto 0) := gmii_txd(7 downto 0);
end if;
end if;
if current_col = 16 and vlan_bytes = 4 then
length(15 downto 8) := gmii_txd(7 downto 0);
end if;
if current_col = 17 and vlan_bytes = 4 then
length(7 downto 0) := gmii_txd(7 downto 0);
end if;
-- data
if current_col > 13 + vlan_bytes and byte_cnt < length then
byte_cnt := byte_cnt + 1;
if gmii_txd(7 downto 0) /= (byte_cnt mod 256) then
demo_mode_error(0) <= '1';
assert false
report "gmii_txd incorrect @ Port 0" & cr
severity error;
end if;
-- padding
elsif current_col < 60 + vlan_bytes and byte_cnt = length then
if gmii_txd(7 downto 0) /= x"00" then
demo_mode_error(0) <= '1';
assert false
report "Padding incorrect @ Port 0" & cr
severity error;
end if;
end if;
-- calculate expected crc for the frame
fcs := calc_crc(gmii_txd(7 downto 0), fcs);
current_col := current_col + 1;
wait until gmii_tx_clk(0)'event and gmii_tx_clk(0) = '1';
end loop; -- while data valid
-- Check the FCS matches that expected from calculation
-- Having checked all data columns, txd must contain FCS.
for j in 0 to 3 loop
if gmii_tx_en(0) = '0' then
demo_mode_error(0) <= '1';
assert false
report "gmii_tx_en incorrect during FCS field @ Port 0" & cr
severity error;
end if;
if gmii_txd(7 downto 0) /= fcs(((8*j)+7) downto (8*j)) then
demo_mode_error(0) <= '1';
assert false
report "gmii_txd incorrect during FCS field @ Port 0" & cr
severity error;
end if;
wait until gmii_tx_clk(0)'event and gmii_tx_clk(0) = '1';
end loop; -- j
end check_frame;
variable frames_received : natural;
begin -- process p_monitor0
frames_received := 0;
-- wait for reset to complete before starting monitor to ignore false startup errors
wait until reset_finished;
while true loop
check_frame;
frames_received := frames_received + 1;
end loop;
end process p_monitor0;
p_monitor1 : process
procedure check_frame is
variable current_col : natural := 0;
variable byte_cnt : natural := 0;
variable fcs : std_logic_vector(31 downto 0);
variable length : std_logic_vector(15 downto 0);
variable data : std_logic_vector(7 downto 0);
variable vlan_bytes : natural := 0;
begin
-- Reset the FCS calculation
fcs := (others => '0');
-- Parse over the preamble field
while gmii_tx_en(1) /= '1' or gmii_txd(15 downto 8) = "01010101" loop
wait until gmii_tx_clk(1)'event and gmii_tx_clk(1) = '1';
end loop;
-- Parse over the Start of Frame Delimiter (SFD)
if (gmii_txd(15 downto 8) /= "11010101") then
assert false
report "SFD not present @ Port 1" & cr
severity error;
end if;
wait until gmii_tx_clk(1)'event and gmii_tx_clk(1) = '1';
-- frame has started, loop over columns of frame
while current_col < 60+vlan_bytes or byte_cnt < length loop
-- check destination address
if current_col < 5 and gmii_txd(15 downto 8) /= x"FF" then
if gmii_txd(15 downto 8) /= DA then
demo_mode_error(1) <= '1';
assert false
report "gmii_txd incorrect during Destination Address field @ Port 1" & cr
severity error;
end if;
end if;
if current_col = 5 then
port_stats1 <= update_stats(port_stats1, gmii_txd(15 downto 8), latency1);
end if;
-- check source address
if current_col >= 6 and current_col < 11 then
if gmii_txd(15 downto 8) /= SA then
demo_mode_error(1) <= '1';
assert false
report "gmii_txd incorrect during Source Address field @ Port 1" & cr
severity error;
end if;
end if;
-- read length / vlan
if current_col = 12 then
if gmii_txd(15 downto 8) = x"81" then
vlan_bytes := 4;
else
vlan_bytes := 0;
length(15 downto 8) := gmii_txd(15 downto 8);
end if;
end if;
if current_col = 13 then
if vlan_bytes = 4 then
if gmii_txd(15 downto 8) /= x"00" then
demo_mode_error(1) <= '1';
assert false
report "vlan incorrect @ Port 1" & cr
severity error;
end if;
else
length(7 downto 0) := gmii_txd(15 downto 8);
end if;
end if;
if current_col = 16 and vlan_bytes = 4 then
length(15 downto 8) := gmii_txd(15 downto 8);
end if;
if current_col = 17 and vlan_bytes = 4 then
length(7 downto 0) := gmii_txd(15 downto 8);
end if;
-- data
if current_col > 13 + vlan_bytes and byte_cnt < length then
byte_cnt := byte_cnt + 1;
if gmii_txd(15 downto 8) /= (byte_cnt mod 256) then
demo_mode_error(1) <= '1';
assert false
report "gmii_txd incorrect @ Port 1" & cr
severity error;
end if;
-- padding
elsif current_col < 60 + vlan_bytes and byte_cnt = length then
if gmii_txd(15 downto 8) /= x"00" then
demo_mode_error(1) <= '1';
assert false
report "Padding incorrect @ Port 1" & cr
severity error;
end if;
end if;
-- calculate expected crc for the frame
data := gmii_txd(15 downto 8);
fcs := calc_crc(data, fcs);
current_col := current_col + 1;
wait until gmii_tx_clk(1)'event and gmii_tx_clk(1) = '1';
end loop; -- while data valid
-- Check the FCS matches that expected from calculation
-- Having checked all data columns, txd must contain FCS.
for j in 0 to 3 loop
if gmii_tx_en(1) = '0' then
demo_mode_error(1) <= '1';
assert false
report "gmii_tx_en incorrect during FCS field @ Port 1" & cr
severity error;
end if;
if gmii_txd(15 downto 8) /= fcs(((8*j)+7) downto (8*j)) then
demo_mode_error(1) <= '1';
assert false
report "gmii_txd incorrect during FCS field @ Port 1" & cr
severity error;
end if;
wait until gmii_tx_clk(1)'event and gmii_tx_clk(1) = '1';
end loop; -- j
end check_frame;
variable frames_received : natural;
begin -- process p_monitor0
frames_received := 0;
-- wait for reset to complete before starting monitor to ignore false startup errors
wait until reset_finished;
while true loop
check_frame;
frames_received := frames_received + 1;
end loop;
end process p_monitor1;
p_monitor2 : process
procedure check_frame is
variable current_col : natural := 0;
variable byte_cnt : natural := 0;
variable fcs : std_logic_vector(31 downto 0);
variable length : std_logic_vector(15 downto 0);
variable data : std_logic_vector(7 downto 0);
variable vlan_bytes : natural := 0;
begin
-- Reset the FCS calculation
fcs := (others => '0');
-- Parse over the preamble field
while gmii_tx_en(2) /= '1' or gmii_txd(23 downto 16) = "01010101" loop
wait until gmii_tx_clk(2)'event and gmii_tx_clk(2) = '1';
end loop;
-- Parse over the Start of Frame Delimiter (SFD)
if (gmii_txd(23 downto 16) /= "11010101") then
assert false
report "SFD not present @ Port 2" & cr
severity error;
end if;
wait until gmii_tx_clk(2)'event and gmii_tx_clk(2) = '1';
-- frame has started, loop over columns of frame
while current_col < 60+vlan_bytes or byte_cnt < length loop
-- check destination address
if current_col < 5 and gmii_txd(23 downto 16) /= x"FF" then
if gmii_txd(23 downto 16) /= DA then
demo_mode_error(2) <= '1';
assert false
report "gmii_txd incorrect during Destination Address field @ Port 2" & cr
severity error;
end if;
end if;
if current_col = 5 then
port_stats2 <= update_stats(port_stats2, gmii_txd(23 downto 16), latency2);
end if;
-- check source address
if current_col >= 6 and current_col < 11 then
if gmii_txd(23 downto 16) /= SA then
demo_mode_error(2) <= '1';
assert false
report "gmii_txd incorrect during Source Address field @ Port 2" & cr
severity error;
end if;
end if;
-- read length / vlan
if current_col = 12 then
if gmii_txd(23 downto 16) = x"81" then
vlan_bytes := 4;
else
vlan_bytes := 0;
length(15 downto 8) := gmii_txd(23 downto 16);
end if;
end if;
if current_col = 13 then
if vlan_bytes = 4 then
if gmii_txd(23 downto 16) /= x"00" then
demo_mode_error(2) <= '1';
assert false
report "vlan incorrect @ Port 2" & cr
severity error;
end if;
else
length(7 downto 0) := gmii_txd(23 downto 16);
end if;
end if;
if current_col = 16 and vlan_bytes = 4 then
length(15 downto 8) := gmii_txd(23 downto 16);
end if;
if current_col = 17 and vlan_bytes = 4 then
length(7 downto 0) := gmii_txd(23 downto 16);
end if;
-- data
if current_col > 13 + vlan_bytes and byte_cnt < length then
byte_cnt := byte_cnt + 1;
if gmii_txd(23 downto 16) /= (byte_cnt mod 256) then
demo_mode_error(2) <= '1';
assert false
report "gmii_txd incorrect @ Port 2" & cr
severity error;
end if;
-- padding
elsif current_col < 60 + vlan_bytes and byte_cnt = length then
if gmii_txd(23 downto 16) /= x"00" then
demo_mode_error(2) <= '1';
assert false
report "Padding incorrect @ Port 2" & cr
severity error;
end if;
end if;
-- calculate expected crc for the frame
data := gmii_txd(23 downto 16);
fcs := calc_crc(data, fcs);
current_col := current_col + 1;
wait until gmii_tx_clk(2)'event and gmii_tx_clk(2) = '1';
end loop;
-- Check the FCS matches that expected from calculation
-- Having checked all data columns, txd must contain FCS.
for j in 0 to 3 loop
if gmii_tx_en(2) = '0' then
demo_mode_error(2) <= '1';
assert false
report "gmii_tx_en incorrect during FCS field @ Port 2" & cr
severity error;
end if;
if gmii_txd(23 downto 16) /= fcs(((8*j)+7) downto (8*j)) then
demo_mode_error(2) <= '1';
assert false
report "gmii_txd incorrect during FCS field @ Port 2" & cr
severity error;
end if;
wait until gmii_tx_clk(2)'event and gmii_tx_clk(2) = '1';
end loop; -- j
end check_frame;
variable frames_received : natural;
begin -- process p_monitor0
frames_received := 0;
-- wait for reset to complete before starting monitor to ignore false startup errors
wait until reset_finished;
while true loop
check_frame;
frames_received := frames_received + 1;
end loop;
end process p_monitor2;
p_monitor3 : process
procedure check_frame is
variable current_col : natural := 0;
variable byte_cnt : natural := 0;
variable fcs : std_logic_vector(31 downto 0);
variable length : std_logic_vector(15 downto 0);
variable data : std_logic_vector(7 downto 0);
variable vlan_bytes : natural := 0;
begin
-- Reset the FCS calculation
fcs := (others => '0');
-- Parse over the preamble field
while gmii_tx_en(3) /= '1' or gmii_txd(31 downto 24) = "01010101" loop
wait until gmii_tx_clk(3)'event and gmii_tx_clk(3) = '1';
end loop;
-- Parse over the Start of Frame Delimiter (SFD)
if (gmii_txd(31 downto 24) /= "11010101") then
assert false
report "SFD not present @ Port 3" & cr
severity error;
end if;
wait until gmii_tx_clk(3)'event and gmii_tx_clk(3) = '1';
-- frame has started, loop over columns of frame
while current_col < 60+vlan_bytes or byte_cnt < length loop
-- check destination address
if current_col < 5 and gmii_txd(31 downto 24) /= x"FF" then
if gmii_txd(31 downto 24) /= DA then
demo_mode_error(3) <= '1';
assert false
report "gmii_txd incorrect during Destination Address field @ Port 3" & cr
severity error;
end if;
end if;
if current_col = 5 then
port_stats3 <= update_stats(port_stats3, gmii_txd(31 downto 24), latency3);
end if;
-- check source address
if current_col >= 6 and current_col < 11 then
if gmii_txd(31 downto 24) /= SA then
demo_mode_error(3) <= '1';
assert false
report "gmii_txd incorrect during Source Address field @ Port 3" & cr
severity error;
end if;
end if;
-- read length / vlan
if current_col = 12 then
if gmii_txd(31 downto 24) = x"81" then
vlan_bytes := 4;
else
vlan_bytes := 0;
length(15 downto 8) := gmii_txd(31 downto 24);
end if;
end if;
if current_col = 13 then
if vlan_bytes = 4 then
if gmii_txd(31 downto 24) /= x"00" then
demo_mode_error(3) <= '1';
assert false
report "vlan incorrect @ Port 3" & cr
severity error;
end if;
else
length(7 downto 0) := gmii_txd(31 downto 24);
end if;
end if;
if current_col = 16 and vlan_bytes = 4 then
length(15 downto 8) := gmii_txd(31 downto 24);
end if;
if current_col = 17 and vlan_bytes = 4 then
length(7 downto 0) := gmii_txd(31 downto 24);
end if;
-- data
if current_col > 13 + vlan_bytes and byte_cnt < length then
byte_cnt := byte_cnt + 1;
if gmii_txd(31 downto 24) /= (byte_cnt mod 256) then
demo_mode_error(3) <= '1';
assert false
report "gmii_txd incorrect @ Port 3" & cr
severity error;
end if;
-- padding
elsif current_col < 60 + vlan_bytes and byte_cnt = length then
if gmii_txd(31 downto 24) /= x"00" then
demo_mode_error(3) <= '1';
assert false
report "Padding incorrect @ Port 3" & cr
severity error;
end if;
end if;
-- calculate expected crc for the frame
data := gmii_txd(31 downto 24);
fcs := calc_crc(data, fcs);
current_col := current_col + 1;
wait until gmii_tx_clk(3)'event and gmii_tx_clk(3) = '1';
end loop; -- while data valid
-- Check the FCS matches that expected from calculation
-- Having checked all data columns, txd must contain FCS.
for j in 0 to 3 loop
if gmii_tx_en(3) = '0' then
demo_mode_error(3) <= '1';
assert false
report "gmii_tx_en incorrect during FCS field @ Port 3" & cr
severity error;
end if;
if gmii_txd(31 downto 24) /= fcs(((8*j)+7) downto (8*j)) then
demo_mode_error(3) <= '1';
assert false
report "gmii_txd incorrect during FCS field @ Port 3" & cr
severity error;
end if;
wait until gmii_tx_clk(3)'event and gmii_tx_clk(3) = '1';
end loop; -- j
end check_frame;
variable frames_received : natural;
begin -- process p_monitor0
frames_received := 0;
-- wait for reset to complete before starting monitor to ignore false startup errors
wait until reset_finished;
while true loop
check_frame;
frames_received := frames_received + 1;
end loop;
end process p_monitor3;
end tb;
| mit | 4e9d923bdcd64d7a4d31fb4550e4123d | 0.477588 | 4.299007 | false | false | false | false |
glennchid/font5-firmware | ipcore_dir/DAQ_MEM/example_design/DAQ_MEM_prod.vhd | 1 | 10,255 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
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-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: DAQ_MEM_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : virtex5
-- C_XDEVICEFAMILY : virtex5
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 1
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 14
-- C_READ_WIDTH_A : 14
-- C_WRITE_DEPTH_A : 1024
-- C_READ_DEPTH_A : 1024
-- C_ADDRA_WIDTH : 10
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 7
-- C_READ_WIDTH_B : 7
-- C_WRITE_DEPTH_B : 2048
-- C_READ_DEPTH_B : 2048
-- C_ADDRB_WIDTH : 11
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY DAQ_MEM_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END DAQ_MEM_prod;
ARCHITECTURE xilinx OF DAQ_MEM_prod IS
COMPONENT DAQ_MEM_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ADDRB : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : DAQ_MEM_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
CLKA => CLKA,
--Port B
ADDRB => ADDRB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
| gpl-3.0 | 96dc9ce8772fe23d56fd666dec0528d7 | 0.491273 | 3.827921 | false | false | false | false |
rkujawa/cr2amiga | eppmodule.vhd | 1 | 1,709 | -- Module implementing communication through USB with Digilent EPP interface.
-- This needs to be reimplemented as clocked state machine... Now it works more
-- by coincidence than by design.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity eppmodule is
Port( -- uC-CPLD interface
astb : in STD_LOGIC;
dstb : in STD_LOGIC;
wr : in STD_LOGIC;
wt : out STD_LOGIC;
databus : inout STD_LOGIC_VECTOR (7 downto 0);
-- internal registers used to exchange the data
ssegReg : out STD_LOGIC_VECTOR (7 downto 0);
ledReg : out STD_LOGIC_VECTOR (3 downto 0);
btnReg : in STD_LOGIC_VECTOR (7 downto 0);
commDataOutReg : out STD_LOGIC_VECTOR (7 downto 0);
commDataInReg: in STD_LOGIC_VECTOR(7 downto 0));
end EppModule;
architecture Behavioral of eppmodule is
signal address : STD_LOGIC_VECTOR (7 downto 0);
begin
-- don't wait if address strobe or data strobe active
wt <= '1' when astb = '0' or dstb = '0' else '0';
databus <= commDataInReg when (wr = '1') and address = "00000001" else
btnReg when (wr = '1') and address = "00000010" else
-- somereg when (Wr = '1') AND address = "xxxxxxxx" else
"ZZZZZZZZ";
process (astb)
begin
if rising_edge(astb) then
address <= databus; -- read the address from data bus
end if;
end process;
process (dstb)
begin
if rising_edge(dstb) then
if wr = '0' then -- EPP data write cycle
if address = "00000000" then
ssegReg <= databus;
elsif address = "00000001" then
commDataOutReg <= databus;
elsif address = "00000010" then
ledReg <= databus(0) & databus(1) & databus(2) & databus(3);
end if;
end if;
end if;
end process;
end Behavioral;
| mit | 8a99a9e801e886c16a84c323541221d6 | 0.658865 | 3.312016 | false | false | false | false |
lennartbublies/ecdsa | src/e_gf2m_doubleadd_point_multiplication.vhd | 1 | 11,077 | ----------------------------------------------------------------------------------------------------
-- ENTITY - Elliptic Curve Point Multiplication
-- Implementation with Double-And-Add algorithm
--
-- Ports:
-- clk_i - Clock
-- rst_i - Reset flag
-- enable_i - Enable computation
-- xp_i - X part of input point
-- yp_i - Y part of input point
-- k - Multiplier k
-- xq_io - X part of output point
-- yq_io - Y part of output point
-- ready_o - Ready flag
--
-- Algorithm:
-- ro = INFINITY
-- for (i=0; i>k-1; i++) {
-- ro = point_double(ro)
-- if k(i) == 1 {
-- ro = point_add(ro, p)
-- }
-- }
--
-- Autor: Lennart Bublies (inf100434)
-- Date: 29.06.2017
----------------------------------------------------------------------------------------------------
------------------------------------------------------------
-- GF(2^M) point multiplication
------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.tld_ecdsa_package.all;
ENTITY e_gf2m_doubleadd_point_multiplication IS
GENERIC (
MODULO : std_logic_vector(M DOWNTO 0) := ONE
);
PORT (
-- Clock, reset, enable
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
xp_i: IN std_logic_vector(M-1 DOWNTO 0);
yp_i: IN std_logic_vector(M-1 DOWNTO 0);
k: IN std_logic_vector(M-1 DOWNTO 0);
xq_io: INOUT std_logic_vector(M-1 DOWNTO 0);
yq_io: INOUT std_logic_vector(M-1 DOWNTO 0);
ready_o: OUT std_logic
);
END e_gf2m_doubleadd_point_multiplication;
ARCHITECTURE rtl of e_gf2m_doubleadd_point_multiplication IS
-- Import entity e_k163_point_doubling
COMPONENT e_gf2m_point_doubling IS
GENERIC (
MODULO : std_logic_vector(M DOWNTO 0)
);
PORT(
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
x1_i: IN std_logic_vector(M-1 DOWNTO 0);
y1_i: IN std_logic_vector(M-1 DOWNTO 0);
x2_io: INOUT std_logic_vector(M-1 DOWNTO 0);
y2_o: OUT std_logic_vector(M-1 DOWNTO 0);
ready_o: OUT std_logic
);
END COMPONENT;
-- Import entity e_gf2m_point_addition
COMPONENT e_gf2m_point_addition IS
GENERIC (
MODULO : std_logic_vector(M DOWNTO 0)
);
PORT(
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
x1_i: IN std_logic_vector(M-1 DOWNTO 0);
y1_i: IN std_logic_vector(M-1 DOWNTO 0);
x2_i: IN std_logic_vector(M-1 DOWNTO 0);
y2_i: IN std_logic_vector(M-1 DOWNTO 0);
x3_io: INOUT std_logic_vector(M-1 DOWNTO 0);
y3_o: OUT std_logic_vector(M-1 DOWNTO 0);
ready_o: OUT std_logic
);
END COMPONENT;
-- Internal signals
SIGNAL start_doubling, doubling_done, start_addition, addition_done: std_logic;
SIGNAL sel, ch_q, ch_a, ch_aa, q_infinity, a_equal_0, a_equal_1, load, k_ready: std_logic;
SIGNAL next_xq, next_yq: std_logic_vector(M-1 DOWNTO 0);
SIGNAL x_double, y_double, x_doubleadd, y_doubleadd: std_logic_vector(M-1 DOWNTO 0);
SIGNAL a, aa, next_a, next_aa: std_logic_vector(M DOWNTO 0);
SIGNAL kk: std_logic_vector(0 TO M-1);
-- Define all available states
subtype states IS natural RANGE 0 TO 13;
SIGNAL current_state: states;
BEGIN
reverse_k: FOR i IN 0 TO M-1 GENERATE
kk(i) <= k(i);
END GENERATE;
-- Instantiate point doubling entity
doubling: e_gf2m_point_doubling GENERIC MAP (
MODULO => MODULO
) PORT MAP(
clk_i => clk_i,
rst_i => rst_i,
enable_i => start_doubling,
x1_i => xq_io,
y1_i => yq_io,
x2_io => x_double, --> Result if k(i)=0
y2_o => y_double, --> Result if k(i)=0
ready_o => doubling_done
);
-- Instantiate point addition entity
addition: e_gf2m_point_addition GENERIC MAP (
MODULO => MODULO
) PORT MAP(
clk_i => clk_i,
rst_i => rst_i,
enable_i => start_addition,
x1_i => x_double,
y1_i => y_double,
x2_i => xp_i,
y2_i => yp_i,
x3_io => x_doubleadd, --> Result if k(i)=1
y3_o => y_doubleadd, --> Result if k(i)=1
ready_o => addition_done
);
-- Select entity output from point addition or point doubling entity in dependence of k
WITH sel SELECT next_yq <= y_double WHEN '0', y_doubleadd WHEN OTHERS;
WITH sel SELECT next_xq <= x_double WHEN '0', x_doubleadd WHEN OTHERS;
-- Output register
register_q: PROCESS(clk_i)
BEGIN
IF clk_i' event and clk_i = '1' THEN
IF load = '1' THEN
xq_io <= (OTHERS=>'1');
yq_io <= (OTHERS=>'1');
q_infinity <= '1';
ELSIF ch_q = '1' THEN
xq_io <= next_xq;
yq_io <= next_yq;
q_infinity <= '0';
END IF;
END IF;
END PROCESS;
-- Register for k
register_a: PROCESS(clk_i)
BEGIN
IF clk_i' event and clk_i = '1' THEN
IF load = '1' THEN
a <= ('0'&kk);
aa <= ('0'&ONES);
k_ready <= '0';
ELSIF ch_aa = '1' THEN
a <= next_a;
aa <= next_aa;
ELSIF ch_a = '1' THEN
a <= next_a;
aa <= next_aa;
k_ready <= '1';
END IF;
END IF;
END PROCESS;
-- Shift k
shift_a: FOR i IN 0 TO m-1 GENERATE
next_a(i) <= a(i+1);
next_aa(i) <= aa(i+1);
END GENERATE;
next_a(m) <= a(m);
next_aa(m) <= aa(m);
-- If '1' enable point addition, otherwise only doubling
a_equal_0 <= '1' WHEN a = 0 ELSE '0';
a_equal_1 <= '1' WHEN a = 1 ELSE '0';
-- State machine
control_unit: PROCESS(clk_i, rst_i, current_state, a_equal_0, a_equal_1, a(0), q_infinity)
BEGIN
-- Handle current state
-- 0,1 : Default state
-- 2,3 : Intialize registers
-- 4,5 :
CASE current_state IS
WHEN 0 TO 1 => load <= '0'; sel <= '0'; ch_q <= '0'; ch_a <= '0'; ch_aa <= '0'; start_doubling <= '0'; start_addition <='0'; ready_o <= '1';
WHEN 2 => load <= '1'; sel <= '0'; ch_q <= '0'; ch_a <= '0'; ch_aa <= '0'; start_doubling <= '0'; start_addition <='0'; ready_o <= '0';
WHEN 3 => load <= '0'; sel <= '0'; ch_q <= '0'; ch_a <= '0'; ch_aa <= '0'; start_doubling <= '0'; start_addition <='0'; ready_o <= '0';
WHEN 4 => load <= '0'; sel <= '0'; ch_q <= '0'; ch_a <= '0'; ch_aa <= '0'; start_doubling <= '1'; start_addition <='0'; ready_o <= '0';
WHEN 5 => load <= '0'; sel <= '0'; ch_q <= '0'; ch_a <= '0'; ch_aa <= '0'; start_doubling <= '0'; start_addition <='0'; ready_o <= '0';
WHEN 6 => load <= '0'; sel <= '0'; ch_q <= '1'; ch_a <= '1'; ch_aa <= '0'; start_doubling <= '0'; start_addition <='0'; ready_o <= '0';
WHEN 7 => load <= '0'; sel <= '0'; ch_q <= '0'; ch_a <= '0'; ch_aa <= '0'; start_doubling <= '1'; start_addition <='0'; ready_o <= '0';
WHEN 8 => load <= '0'; sel <= '0'; ch_q <= '0'; ch_a <= '0'; ch_aa <= '0'; start_doubling <= '0'; start_addition <='0'; ready_o <= '0';
WHEN 9 => load <= '0'; sel <= '0'; ch_q <= '0'; ch_a <= '0'; ch_aa <= '0'; start_doubling <= '0'; start_addition <='1'; ready_o <= '0';
WHEN 10 => load <= '0'; sel <= '1'; ch_q <= '0'; ch_a <= '0'; ch_aa <= '0'; start_doubling <= '0'; start_addition <='0'; ready_o <= '0';
WHEN 11 => load <= '0'; sel <= '1'; ch_q <= '1'; ch_a <= '1'; ch_aa <= '0'; start_doubling <= '0'; start_addition <='0'; ready_o <= '0';
WHEN 12 => load <= '0'; sel <= '0'; ch_q <= '0'; ch_a <= '0'; ch_aa <= '1'; start_doubling <= '0'; start_addition <='0'; ready_o <= '0';
WHEN 13 => load <= '0'; sel <= '0'; ch_q <= '0'; ch_a <= '1'; ch_aa <= '0'; start_doubling <= '0'; start_addition <='0'; ready_o <= '0';
END CASE;
IF rst_i = '1' THEN
-- Reset state if reset is high
current_state <= 0;
ELSIF clk_i'event and clk_i = '1' THEN
-- Set next state
CASE current_state IS
WHEN 0 =>
IF enable_i = '0' THEN
current_state <= 1;
END IF;
WHEN 1 =>
IF enable_i = '1' THEN
current_state <= 2;
END IF;
WHEN 2 =>
current_state <= 3;
WHEN 3 =>
-- Shift beginning zero bits (result of inversion of k)
IF (a(0) = '0') and (k_ready = '0') THEN
current_state <= 12;
ELSIF (a(0) = '1') and (k_ready = '0') THEN
current_state <= 13;
-- k is completely processed --> finish
ELSIF (a_equal_0 = '1') and (a = aa) THEN
current_state <= 0;
ELSIF a_equal_0 = '1' THEN
current_state <= 4;
ELSIF (a_equal_1 = '1') and (q_infinity = '1') THEN
current_state <= 0;
-- Double but skip addition
ELSIF a(0) = '0' THEN
current_state <= 4;
-- Double and add
ELSE
current_state <= 7;
END IF;
-- Case: Only doubling
WHEN 4 =>
current_state <= 5; --> Double
WHEN 5 =>
IF doubling_done = '1' THEN
current_state <= 6;
END IF;
WHEN 6 =>
current_state <= 3;
-- Case: Double and add
WHEN 7 =>
current_state <= 8; --> Double
WHEN 8 =>
IF doubling_done = '1' THEN
current_state <= 9;
END IF;
WHEN 9 =>
current_state <= 10; --> Add
WHEN 10 =>
IF addition_done = '1' THEN
current_state <= 11;
END IF;
WHEN 11 =>
current_state <= 3;
WHEN 12 =>
current_state <= 3;
WHEN 13 =>
current_state <= 3;
END CASE;
END IF;
END PROCESS;
END rtl; | gpl-3.0 | 24fa8559af7f53faece8fa68e35bf116 | 0.438837 | 3.548046 | false | false | false | false |
glennchid/font5-firmware | ipcore_dir/lookuptable1/simulation/lookuptable1_synth.vhd | 1 | 10,389 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: lookuptable1_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY lookuptable1_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
CLKB_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE lookuptable1_synth_ARCH OF lookuptable1_synth IS
COMPONENT lookuptable1_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(27 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(27 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(27 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(27 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(27 DOWNTO 0);
SIGNAL CLKB: STD_LOGIC := '0';
SIGNAL RSTB: STD_LOGIC := '0';
SIGNAL WEB: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEB_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB: STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB_R: STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB: STD_LOGIC_VECTOR( 6 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB_R: STD_LOGIC_VECTOR( 6 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTB: STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL CHECK_DATA_TDP : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECKER_ENB_R : STD_LOGIC := '0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL clkb_in_i: STD_LOGIC;
SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
-- clkb_buf: bufg
-- PORT map(
-- i => CLKB_IN,
-- o => clkb_in_i
-- );
clkb_in_i <= CLKB_IN;
CLKB <= clkb_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
RSTB <= RESETB_SYNC_R3 AFTER 50 ns;
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
RESETB_SYNC_R1 <= RESET_IN;
RESETB_SYNC_R2 <= RESETB_SYNC_R1;
RESETB_SYNC_R3 <= RESETB_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST_A: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 28,
READ_WIDTH => 28 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECK_DATA_TDP(0) AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_DATA_CHECKER_INST_B: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 7,
READ_WIDTH => 7 )
PORT MAP (
CLK => CLKB,
RST => RSTB,
EN => CHECKER_ENB_R,
DATA_IN => DOUTB,
STATUS => ISSUE_FLAG(1)
);
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(RSTB='1') THEN
CHECKER_ENB_R <= '0';
ELSE
CHECKER_ENB_R <= CHECK_DATA_TDP(1) AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLKA => CLKA,
CLKB => CLKB,
TB_RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
CHECK_DATA => CHECK_DATA_TDP
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
WEB_R <= (OTHERS=>'0') AFTER 50 ns;
DINB_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
WEB_R <= WEB AFTER 50 ns;
DINB_R <= DINB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ADDRB_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
ADDRB_R <= ADDRB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: lookuptable1_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA,
--Port B
WEB => WEB_R,
ADDRB => ADDRB_R,
DINB => DINB_R,
DOUTB => DOUTB,
CLKB => CLKB
);
END ARCHITECTURE;
| gpl-3.0 | cfc937bdafbf2f27c09dccf6c17356b5 | 0.556839 | 3.613565 | false | false | false | false |
glennchid/font5-firmware | ipcore_dir/lookuptable1/simulation/bmg_stim_gen.vhd | 1 | 15,711 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For TDP
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For TDP
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_TDP IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_TDP;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_TDP IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLKA : IN STD_LOGIC;
CLKB : IN STD_LOGIC;
TB_RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(27 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
WEB : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
ADDRB : OUT STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
DINB : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC_VECTOR(1 DOWNTO 0):=(OTHERS => '0')
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT ADDR_ZERO : STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A : INTEGER:= DIVROUNDUP(28,28);
CONSTANT DATA_PART_CNT_B : INTEGER:= DIVROUNDUP(7,7);
SIGNAL WRITE_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT_A : STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT_A : STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT_B : STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT_B : STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(27 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB_INT : STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL MAX_COUNT : STD_LOGIC_VECTOR(10 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(32768,11);
SIGNAL DO_WRITE_A : STD_LOGIC := '0';
SIGNAL DO_READ_A : STD_LOGIC := '0';
SIGNAL DO_WRITE_B : STD_LOGIC := '0';
SIGNAL DO_READ_B : STD_LOGIC := '0';
SIGNAL COUNT_NO : STD_LOGIC_VECTOR (10 DOWNTO 0):=(OTHERS => '0');
SIGNAL DO_READ_RA : STD_LOGIC := '0';
SIGNAL DO_READ_RB : STD_LOGIC := '0';
SIGNAL DO_READ_REG_A: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL DO_READ_REG_B: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL COUNT : integer := 0;
SIGNAL COUNT_B : integer := 0;
CONSTANT WRITE_CNT_A : integer := 6;
CONSTANT READ_CNT_A : integer := 6;
CONSTANT WRITE_CNT_B : integer := 4;
CONSTANT READ_CNT_B : integer := 4;
signal porta_wr_rd : std_logic:='0';
signal portb_wr_rd : std_logic:='0';
signal porta_wr_rd_complete: std_logic:='0';
signal portb_wr_rd_complete: std_logic:='0';
signal incr_cnt : std_logic :='0';
signal incr_cnt_b : std_logic :='0';
SIGNAL PORTB_WR_RD_HAPPENED: STD_LOGIC :='0';
SIGNAL LATCH_PORTA_WR_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_L1 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_L2 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_R1 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_R2 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_HAPPENED: STD_LOGIC :='0';
SIGNAL LATCH_PORTB_WR_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_L1 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_L2 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_R1 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_R2 :STD_LOGIC :='0';
BEGIN
WRITE_ADDR_INT_A(12 DOWNTO 0) <= WRITE_ADDR_A(12 DOWNTO 0);
READ_ADDR_INT_A(12 DOWNTO 0) <= READ_ADDR_A(12 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE_A='1',WRITE_ADDR_INT_A,READ_ADDR_INT_A) ;
WRITE_ADDR_INT_B(14 DOWNTO 0) <= WRITE_ADDR_B(14 DOWNTO 0);
--To avoid collision during idle period, negating the read_addr of port A
READ_ADDR_INT_B(14 DOWNTO 0) <= IF_THEN_ELSE( (DO_WRITE_B='0' AND DO_READ_B='0'),ADDR_ZERO,READ_ADDR_B(14 DOWNTO 0));
ADDRB <= IF_THEN_ELSE(DO_WRITE_B='1',WRITE_ADDR_INT_B,READ_ADDR_INT_B) ;
DINA <= DINA_INT ;
DINB <= DINB_INT ;
CHECK_DATA(0) <= DO_READ_REG_A(0);
CHECK_DATA(1) <= DO_READ_REG_B(0);
RD_ADDR_GEN_INST_A:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 8192,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_READ_A,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR_A
);
WR_ADDR_GEN_INST_A:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>8192 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE_A,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR_A
);
RD_ADDR_GEN_INST_B:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 32768 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_READ_B,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR_B
);
WR_ADDR_GEN_INST_B:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 32768 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_WRITE_B,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR_B
);
WR_DATA_GEN_INST_A:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>28,
DOUT_WIDTH => 28,
DATA_PART_CNT => 1,
SEED => 2)
PORT MAP (
CLK =>CLKA,
RST => TB_RST,
EN => DO_WRITE_A,
DATA_OUT => DINA_INT
);
WR_DATA_GEN_INST_B:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>7,
DOUT_WIDTH =>7 ,
DATA_PART_CNT =>1,
SEED => 2)
PORT MAP (
CLK =>CLKB,
RST => TB_RST,
EN => DO_WRITE_B,
DATA_OUT => DINB_INT
);
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
LATCH_PORTB_WR_RD_COMPLETE<='0';
ELSIF(PORTB_WR_RD_COMPLETE='1') THEN
LATCH_PORTB_WR_RD_COMPLETE <='1';
ELSIF(PORTA_WR_RD_HAPPENED='1') THEN
LATCH_PORTB_WR_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD_L1 <='0';
PORTB_WR_RD_L2 <='0';
ELSE
PORTB_WR_RD_L1 <= LATCH_PORTB_WR_RD_COMPLETE;
PORTB_WR_RD_L2 <= PORTB_WR_RD_L1;
END IF;
END IF;
END PROCESS;
PORTA_WR_RD_EN: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD <='1';
ELSE
PORTA_WR_RD <= PORTB_WR_RD_L2;
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD_R1 <='0';
PORTA_WR_RD_R2 <='0';
ELSE
PORTA_WR_RD_R1 <=PORTA_WR_RD;
PORTA_WR_RD_R2 <=PORTA_WR_RD_R1;
END IF;
END IF;
END PROCESS;
PORTA_WR_RD_HAPPENED <= PORTA_WR_RD_R2;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
LATCH_PORTA_WR_RD_COMPLETE<='0';
ELSIF(PORTA_WR_RD_COMPLETE='1') THEN
LATCH_PORTA_WR_RD_COMPLETE <='1';
ELSIF(PORTB_WR_RD_HAPPENED='1') THEN
LATCH_PORTA_WR_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD_L1 <='0';
PORTA_WR_RD_L2 <='0';
ELSE
PORTA_WR_RD_L1 <= LATCH_PORTA_WR_RD_COMPLETE;
PORTA_WR_RD_L2 <= PORTA_WR_RD_L1;
END IF;
END IF;
END PROCESS;
PORTB_EN: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD <='0';
ELSE
PORTB_WR_RD <= PORTA_WR_RD_L2;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD_R1 <='0';
PORTB_WR_RD_R2 <='0';
ELSE
PORTB_WR_RD_R1 <=PORTB_WR_RD;
PORTB_WR_RD_R2 <=PORTB_WR_RD_R1;
END IF;
END IF;
END PROCESS;
---double registered of porta complete on portb clk
PORTB_WR_RD_HAPPENED <= PORTB_WR_RD_R2;
PORTA_WR_RD_COMPLETE <= '1' when count=(WRITE_CNT_A+READ_CNT_A) else '0';
start_counter: process(clka)
begin
if(rising_edge(clka)) then
if(TB_RST='1') then
incr_cnt <= '0';
elsif(porta_wr_rd ='1') then
incr_cnt <='1';
elsif(porta_wr_rd_complete='1') then
incr_cnt <='0';
end if;
end if;
end process;
COUNTER: process(clka)
begin
if(rising_edge(clka)) then
if(TB_RST='1') then
count <= 0;
elsif(incr_cnt='1') then
count<=count+1;
end if;
if(count=(WRITE_CNT_A+READ_CNT_A)) then
count<=0;
end if;
end if;
end process;
DO_WRITE_A<='1' when (count <WRITE_CNT_A and incr_cnt='1') else '0';
DO_READ_A <='1' when (count >WRITE_CNT_A and incr_cnt='1') else '0';
PORTB_WR_RD_COMPLETE <= '1' when count_b=(WRITE_CNT_B+READ_CNT_B) else '0';
startb_counter: process(clkb)
begin
if(rising_edge(clkb)) then
if(TB_RST='1') then
incr_cnt_b <= '0';
elsif(portb_wr_rd ='1') then
incr_cnt_b <='1';
elsif(portb_wr_rd_complete='1') then
incr_cnt_b <='0';
end if;
end if;
end process;
COUNTER_B: process(clkb)
begin
if(rising_edge(clkb)) then
if(TB_RST='1') then
count_b <= 0;
elsif(incr_cnt_b='1') then
count_b<=count_b+1;
end if;
if(count_b=WRITE_CNT_B+READ_CNT_B) then
count_b<=0;
end if;
end if;
end process;
DO_WRITE_B<='1' when (count_b <WRITE_CNT_B and incr_cnt_b='1') else '0';
DO_READ_B <='1' when (count_b >WRITE_CNT_B and incr_cnt_b='1') else '0';
BEGIN_SHIFT_REG_A: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_A(0),
CLK =>CLKA,
RST=>TB_RST,
D =>DO_READ_A
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_A(I),
CLK =>CLKA,
RST=>TB_RST,
D =>DO_READ_REG_A(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG_A;
BEGIN_SHIFT_REG_B: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_B(0),
CLK =>CLKB,
RST=>TB_RST,
D =>DO_READ_B
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_B(I),
CLK =>CLKB,
RST=>TB_RST,
D =>DO_READ_REG_B(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG_B;
REGCEA_PROCESS: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
DO_READ_RA <= '0';
ELSE
DO_READ_RA <= DO_READ_A;
END IF;
END IF;
END PROCESS;
REGCEB_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
DO_READ_RB <= '0';
ELSE
DO_READ_RB <= DO_READ_B;
END IF;
END IF;
END PROCESS;
---REGCEB SHOULD BE SET AT THE CORE OUTPUT REGISTER/EMBEEDED OUTPUT REGISTER
--- WHEN CORE OUTPUT REGISTER IS SET REGCE SHOUD BE SET TO '1' WHEN THE READ DATA IS AVAILABLE AT THE CORE OUTPUT REGISTER
--WHEN CORE OUTPUT REGISTER IS '0' AND OUTPUT_PRIMITIVE_REG ='1', REGCE SHOULD BE SET WHEN THE DATA IS AVAILABLE AT THE PRIMITIVE OUTPUT REGISTER.
-- HERE, TO GENERAILIZE REGCE IS ASSERTED
WEA(0) <= IF_THEN_ELSE(DO_WRITE_A='1','1','0') ;
WEB(0) <= IF_THEN_ELSE(DO_WRITE_B='1','1','0') ;
END ARCHITECTURE;
| gpl-3.0 | 03dcaf92a16dc6f87819ebf65be98a7b | 0.575266 | 3.210914 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/temac_testbench_source/sources_1/imports/example_design/tri_mode_ethernet_mac_0_fifo_block.vhd | 1 | 23,185 | --------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_fifo_block.v
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This is the FIFO Block level vhdl wrapper for the Tri-Mode
-- Ethernet MAC core. This wrapper enhances the standard MAC core
-- with an example FIFO. The interface to this FIFO is
-- designed to the AXI-S specification.
-- Please refer to core documentation for
-- additional FIFO and AXI-S information.
--
-- _________________________________________________________
-- | |
-- | FIFO BLOCK LEVEL WRAPPER |
-- | |
-- | _____________________ ______________________ |
-- | | _________________ | | | |
-- | | | | | | | |
-- -------->| | TX AXI FIFO | |---->| Tx Tx |--------->
-- | | | | | | AXI-S PHY | |
-- | | |_________________| | | I/F I/F | |
-- | | | | | |
-- AXI | | 10/100/1G | | TRI-MODE ETHERNET | |
-- Stream | | ETHERNET FIFO | | MAC | | PHY I/F
-- | | | | SUPPORT LEVEL | |
-- | | _________________ | | | |
-- | | | | | | | |
-- <--------| | RX AXI FIFO | |<----| Rx Rx |<---------
-- | | | | | | AXI-S PHY | |
-- | | |_________________| | | I/F I/F | |
-- | |_____________________| |______________________| |
-- | |
-- |_________________________________________________________|
--
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
-- The module declaration for the fifo block level wrapper.
--------------------------------------------------------------------------------
entity tri_mode_ethernet_mac_0_fifo_block is
port(
gtx_clk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Reference clock for IDELAYCTRL's
refclk : in std_logic;
-- Receiver Statistics Interface
-----------------------------------------
rx_mac_aclk : out std_logic;
rx_reset : out std_logic;
rx_statistics_vector : out std_logic_vector(27 downto 0);
rx_statistics_valid : out std_logic;
-- Receiver (AXI-S) Interface
------------------------------------------
rx_fifo_clock : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tready : in std_logic;
rx_axis_fifo_tlast : out std_logic;
-- Transmitter Statistics Interface
--------------------------------------------
tx_mac_aclk : out std_logic;
tx_reset : out std_logic;
tx_ifg_delay : in std_logic_vector(7 downto 0);
tx_statistics_vector : out std_logic_vector(31 downto 0);
tx_statistics_valid : out std_logic;
-- Transmitter (AXI-S) Interface
---------------------------------------------
tx_fifo_clock : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tready : out std_logic;
tx_axis_fifo_tlast : in std_logic;
-- MAC Control Interface
--------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(15 downto 0);
-- GMII Interface
-------------------
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
mii_tx_clk : in std_logic;
-- MDIO Interface
-------------------
mdio : inout std_logic;
mdc : out std_logic;
-- AXI-Lite Interface
-----------------
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
s_axi_awaddr : in std_logic_vector(11 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(11 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic
);
end tri_mode_ethernet_mac_0_fifo_block;
architecture wrapper of tri_mode_ethernet_mac_0_fifo_block is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of wrapper : architecture is "yes";
------------------------------------------------------------------------------
-- Component declaration for the Tri-Mode Ethernet MAC Support Level wrapper
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_support
port(
gtx_clk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Receiver Interface
----------------------------
rx_enable : out std_logic;
rx_statistics_vector : out std_logic_vector(27 downto 0);
rx_statistics_valid : out std_logic;
rx_mac_aclk : out std_logic;
rx_reset : out std_logic;
rx_axis_mac_tdata : out std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : out std_logic;
rx_axis_mac_tlast : out std_logic;
rx_axis_mac_tuser : out std_logic;
rx_axis_filter_tuser : out std_logic_vector(4 downto 0);
-- Transmitter Interface
-------------------------------
tx_enable : out std_logic;
tx_ifg_delay : in std_logic_vector(7 downto 0);
tx_statistics_vector : out std_logic_vector(31 downto 0);
tx_statistics_valid : out std_logic;
tx_mac_aclk : out std_logic;
tx_reset : out std_logic;
tx_axis_mac_tdata : in std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : in std_logic;
tx_axis_mac_tlast : in std_logic;
tx_axis_mac_tuser : in std_logic_vector(0 downto 0);
tx_axis_mac_tready : out std_logic;
-- MAC Control Interface
------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(15 downto 0);
-- Reference clock for IDELAYCTRL's
refclk : in std_logic;
speedis100 : out std_logic;
speedis10100 : out std_logic;
-- GMII Interface
-----------------
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
mii_tx_clk : in std_logic;
-- MDIO Interface
-----------------
mdio : inout std_logic;
mdc : out std_logic;
-- AXI-Lite Interface
-----------------
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
s_axi_awaddr : in std_logic_vector(11 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(11 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
mac_irq : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the fifo
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo
generic (
FULL_DUPLEX_ONLY : boolean := true); -- If fifo is to be used only in full
-- duplex set to true for optimised implementation
port (
tx_fifo_aclk : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tlast : in std_logic;
tx_axis_fifo_tready : out std_logic;
tx_mac_aclk : in std_logic;
tx_mac_resetn : in std_logic;
tx_axis_mac_tdata : out std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : out std_logic;
tx_axis_mac_tlast : out std_logic;
tx_axis_mac_tready : in std_logic;
tx_axis_mac_tuser : out std_logic;
tx_fifo_overflow : out std_logic;
tx_fifo_status : out std_logic_vector(3 downto 0);
tx_collision : in std_logic;
tx_retransmit : in std_logic;
rx_fifo_aclk : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tlast : out std_logic;
rx_axis_fifo_tready : in std_logic;
rx_mac_aclk : in std_logic;
rx_mac_resetn : in std_logic;
rx_axis_mac_tdata : in std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : in std_logic;
rx_axis_mac_tlast : in std_logic;
rx_axis_mac_tuser : in std_logic;
rx_fifo_status : out std_logic_vector(3 downto 0);
rx_fifo_overflow : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the reset synchroniser
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_reset_sync
port (
reset_in : in std_logic; -- Active high asynchronous reset
enable : in std_logic;
clk : in std_logic; -- clock to be sync'ed to
reset_out : out std_logic -- "Synchronised" reset signal
);
end component;
------------------------------------------------------------------------------
-- Internal signals used in this fifo block level wrapper.
------------------------------------------------------------------------------
signal rx_mac_aclk_int : std_logic; -- MAC Rx clock
signal tx_mac_aclk_int : std_logic; -- MAC Tx clock
signal rx_reset_int : std_logic; -- MAC Rx reset
signal tx_reset_int : std_logic; -- MAC Tx reset
signal tx_mac_resetn : std_logic;
signal rx_mac_resetn : std_logic;
signal tx_mac_reset : std_logic;
signal rx_mac_reset : std_logic;
-- MAC receiver client I/F
signal rx_axis_mac_tdata : std_logic_vector(7 downto 0);
signal rx_axis_mac_tvalid : std_logic;
signal rx_axis_mac_tlast : std_logic;
signal rx_axis_mac_tuser : std_logic;
-- MAC transmitter client I/F
signal tx_axis_mac_tdata : std_logic_vector(7 downto 0);
signal tx_axis_mac_tvalid : std_logic;
signal tx_axis_mac_tready : std_logic;
signal tx_axis_mac_tlast : std_logic;
signal tx_axis_mac_tuser : std_logic_vector(0 downto 0);
begin
------------------------------------------------------------------------------
-- Connect the output clock signals
------------------------------------------------------------------------------
rx_mac_aclk <= rx_mac_aclk_int;
tx_mac_aclk <= tx_mac_aclk_int;
rx_reset <= rx_reset_int;
tx_reset <= tx_reset_int;
------------------------------------------------------------------------------
-- Instantiate the Tri-Mode Ethernet MAC Support Level wrapper
------------------------------------------------------------------------------
trimac_sup_block : tri_mode_ethernet_mac_0_support
port map(
gtx_clk => gtx_clk,
-- asynchronous reset
glbl_rstn => glbl_rstn,
rx_axi_rstn => rx_axi_rstn,
tx_axi_rstn => tx_axi_rstn,
-- Client Receiver Interface
rx_enable => open,
rx_statistics_vector => rx_statistics_vector,
rx_statistics_valid => rx_statistics_valid,
rx_mac_aclk => rx_mac_aclk_int,
rx_reset => rx_reset_int,
rx_axis_mac_tdata => rx_axis_mac_tdata,
rx_axis_mac_tvalid => rx_axis_mac_tvalid,
rx_axis_mac_tlast => rx_axis_mac_tlast,
rx_axis_mac_tuser => rx_axis_mac_tuser,
rx_axis_filter_tuser => open,
-- Client Transmitter Interface
tx_enable => open,
tx_ifg_delay => tx_ifg_delay,
tx_statistics_vector => tx_statistics_vector,
tx_statistics_valid => tx_statistics_valid,
tx_mac_aclk => tx_mac_aclk_int,
tx_reset => tx_reset_int,
tx_axis_mac_tdata => tx_axis_mac_tdata ,
tx_axis_mac_tvalid => tx_axis_mac_tvalid,
tx_axis_mac_tlast => tx_axis_mac_tlast,
tx_axis_mac_tuser => tx_axis_mac_tuser,
tx_axis_mac_tready => tx_axis_mac_tready,
-- Flow Control
pause_req => pause_req,
pause_val => pause_val,
-- Reference clock for IDELAYCTRL's
refclk => refclk,
-- speed control
speedis100 => open,
speedis10100 => open,
-- GMII Interface
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_tx_clk => gmii_tx_clk,
gmii_rxd => gmii_rxd,
gmii_rx_dv => gmii_rx_dv,
gmii_rx_er => gmii_rx_er,
gmii_rx_clk => gmii_rx_clk,
mii_tx_clk => mii_tx_clk,
-- MDIO Interface
mdio => mdio,
mdc => mdc,
-- AXI lite interface
s_axi_aclk => s_axi_aclk,
s_axi_resetn => s_axi_resetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
mac_irq => open
);
------------------------------------------------------------------------------
-- Instantiate the user side FIFO
------------------------------------------------------------------------------
-- locally reset sync the mac generated resets - the resets are already fully sync
-- so adding a reset sync shouldn't change that
rx_mac_reset_gen : tri_mode_ethernet_mac_0_reset_sync
port map (
clk => rx_mac_aclk_int,
enable => '1',
reset_in => rx_reset_int,
reset_out => rx_mac_reset
);
tx_mac_reset_gen : tri_mode_ethernet_mac_0_reset_sync
port map (
clk => tx_mac_aclk_int,
enable => '1',
reset_in => tx_reset_int,
reset_out => tx_mac_reset
);
-- create inverted mac resets as the FIFO expects AXI compliant resets
tx_mac_resetn <= not tx_mac_reset;
rx_mac_resetn <= not rx_mac_reset;
user_side_FIFO : tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo
generic map(
FULL_DUPLEX_ONLY => true
)
port map(
-- Transmit FIFO MAC TX Interface
tx_fifo_aclk => tx_fifo_clock,
tx_fifo_resetn => tx_fifo_resetn,
tx_axis_fifo_tdata => tx_axis_fifo_tdata,
tx_axis_fifo_tvalid => tx_axis_fifo_tvalid,
tx_axis_fifo_tlast => tx_axis_fifo_tlast,
tx_axis_fifo_tready => tx_axis_fifo_tready,
tx_mac_aclk => tx_mac_aclk_int,
tx_mac_resetn => tx_mac_resetn,
tx_axis_mac_tdata => tx_axis_mac_tdata,
tx_axis_mac_tvalid => tx_axis_mac_tvalid,
tx_axis_mac_tlast => tx_axis_mac_tlast,
tx_axis_mac_tready => tx_axis_mac_tready,
tx_axis_mac_tuser => tx_axis_mac_tuser(0),
tx_fifo_overflow => open,
tx_fifo_status => open,
tx_collision => '0',
tx_retransmit => '0',
rx_fifo_aclk => rx_fifo_clock,
rx_fifo_resetn => rx_fifo_resetn,
rx_axis_fifo_tdata => rx_axis_fifo_tdata,
rx_axis_fifo_tvalid => rx_axis_fifo_tvalid,
rx_axis_fifo_tlast => rx_axis_fifo_tlast,
rx_axis_fifo_tready => rx_axis_fifo_tready,
rx_mac_aclk => rx_mac_aclk_int,
rx_mac_resetn => rx_mac_resetn,
rx_axis_mac_tdata => rx_axis_mac_tdata,
rx_axis_mac_tvalid => rx_axis_mac_tvalid,
rx_axis_mac_tlast => rx_axis_mac_tlast,
rx_axis_mac_tuser => rx_axis_mac_tuser,
rx_fifo_status => open,
rx_fifo_overflow => open
);
end wrapper;
| mit | 4a95945e20b0172ad54912c028410ce8 | 0.45633 | 4.121045 | false | false | false | false |
diecaptain/kalman_mppt | kn_kalman_Vactcapdashofkplusone.vhd | 1 | 1,233 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity kn_kalman_Vactcapdashofkplusone is
port
( clock : in std_logic;
Vactcapofk : in std_logic_vector(31 downto 0);
M : in std_logic_vector(31 downto 0);
Uofk : in std_logic_vector(31 downto 0);
Vactcapdashofkplusone : out std_logic_vector(31 downto 0)
);
end kn_kalman_Vactcapdashofkplusone;
architecture struct of kn_kalman_Vactcapdashofkplusone is
component kn_kalman_add IS
PORT
( clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component kn_kalman_mult IS
PORT
( clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal Z : std_logic_vector(31 downto 0);
begin
M1 : kn_kalman_mult port map (clock => clock, dataa => M, datab => Uofk, result => Z);
M2 : kn_kalman_add port map (clock => clock, dataa => Vactcapofk, datab => Z, result => Vactcapdashofkplusone);
end struct;
| gpl-2.0 | 41121e1dff8da222b78bbcf23cdc47d1 | 0.647202 | 3.502841 | false | false | false | false |
lfmunoz/4dsp_sip_interface | fmc116_ltc2175_ctrl.vhd | 1 | 17,845 | ----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity fmc116_ltc2175_ctrl is
generic (
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"0000005";
PRESEL : std_logic_vector(7 downto 0) := x"00"
);
port (
rst : in std_logic;
clk : in std_logic;
serial_clk : in std_logic;
sclk_ext : in std_logic;
-- Sequence interface
init_ena : in std_logic;
init_done : out std_logic;
-- Command Interface
clk_cmd : in std_logic;
in_cmd_val : in std_logic;
in_cmd : in std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
out_cmd : out std_logic_vector(63 downto 0);
in_cmd_busy : out std_logic;
-- SPI control
spi_n_oe : out std_logic;
spi_n_cs : out std_logic;
spi_sclk : out std_logic;
spi_sdo : out std_logic;
spi_sdi : in std_logic
);
end fmc116_ltc2175_ctrl;
architecture fmc116_ltc2175_ctrl_syn of fmc116_ltc2175_ctrl is
component fmc11x_stellar_cmd is
generic
(
start_addr :std_logic_vector(27 downto 0):=x"0000000";
stop_addr :std_logic_vector(27 downto 0):=x"0000010"
);
port (
reset : in std_logic;
-- Command interface
clk_cmd : in std_logic; --cmd_in and cmd_out are synchronous to this clock;
out_cmd : out std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
in_cmd : in std_logic_vector(63 downto 0);
in_cmd_val : in std_logic;
-- Register interface
clk_reg : in std_logic; --register interface is synchronous to this clock
out_reg : out std_logic_vector(31 downto 0);--caries the out register data
out_reg_val : out std_logic; --the out_reg has valid data (pulse)
out_reg_val_ack : out std_logic; --the out_reg has valid data and expects and acknowledge back (pulse)
out_reg_addr : out std_logic_vector(27 downto 0);--out register address
in_reg : in std_logic_vector(31 downto 0);--requested register data is placed on this bus
in_reg_val : in std_logic; --pulse to indicate requested register is valid
in_reg_req : out std_logic; --pulse to request data
in_reg_addr : out std_logic_vector(27 downto 0);--requested address
--write acknowledge interface
wr_ack : in std_logic; --pulse to indicate write is done
-- Mailbox interface
mbx_in_reg : in std_logic_vector(31 downto 0);--value of the mailbox to send
mbx_in_val : in std_logic --pulse to indicate mailbox is valid
);
end component;
component pulse2pulse
port (
rst : in std_logic;
in_clk : in std_logic;
out_clk : in std_logic;
pulsein : in std_logic;
pulseout : out std_logic;
inbusy : out std_logic
);
end component;
component ltc2175_init_mem is
port (
clka : in std_logic;
addra : in std_logic_vector(2 downto 0);
douta : out std_logic_vector(15 downto 0)
);
end component;
constant ADDR_GLOBAL : std_logic_vector(27 downto 0) := x"0000005";
constant ADDR_MAX_WR : std_logic_vector(27 downto 0) := x"0000004";
constant ADDR_MAX_RD : std_logic_vector(27 downto 0) := x"0000004";
type sh_states is (idle, instruct, data_io, data_valid);
signal sh_state : sh_states;
--signal sclk_prebuf : std_logic;
--signal serial_clk : std_logic;
--signal sclk_ext : std_logic;
signal out_reg_val : std_logic;
signal out_reg_addr : std_logic_vector(27 downto 0);
signal out_reg : std_logic_vector(31 downto 0);
signal in_reg_req : std_logic;
signal in_reg_addr : std_logic_vector(27 downto 0);
signal in_reg_val : std_logic;
signal in_reg : std_logic_vector(31 downto 0);
signal out_reg_val_ack : std_logic;
signal wr_ack : std_logic;
signal serial_val_ack : std_logic;
signal serial_val_ack_sclk : std_logic;
signal busy_del1 : std_logic;
signal busy_del2 : std_logic;
signal init_done_sclk_del : std_logic;
signal wr_cmd_ack : std_logic;
signal wr_ack_requested : std_logic;
signal done_sclk : std_logic;
signal init_done_sclk : std_logic;
signal init_done_tmp : std_logic;
signal init_done_prev : std_logic;
signal init : std_logic;
signal init_tmp : std_logic;
signal init_reg : std_logic;
signal inst_val : std_logic;
signal inst_reg_val : std_logic;
signal inst_rw : std_logic;
signal inst_reg : std_logic_vector(2 downto 0);
signal data_reg : std_logic_vector(7 downto 0);
signal sh_counter : integer;
signal shifting : std_logic;
signal read_n_write : std_logic;
signal ncs_int : std_logic;
signal busy : std_logic;
signal sdi : std_logic;
signal shift_reg : std_logic_vector(15+PRESEL'length downto 0);
signal init_address : std_logic_vector(2 downto 0);
signal init_data : std_logic_vector(15 downto 0);
signal read_byte_val : std_logic;
signal data_read_val : std_logic;
signal data_read : std_logic_vector(7 downto 0);
begin
----------------------------------------------------------------------------------------------------
-- Generate serial clock (max 6.66MHz, due to Tddata of 75ns)
----------------------------------------------------------------------------------------------------
-- process (clk)
-- -- Divide by 2^5 = 32, CLKmax = 32 x 6.66MHz
-- variable clk_div : std_logic_vector(4 downto 0) := (others => '0');
-- begin
-- if (rising_edge(clk)) then
-- clk_div := clk_div + '1';
-- -- The slave samples the data on the rising edge of SCLK.
-- -- therefore we make sure the external clock is slightly
-- -- after the internal clock.
-- sclk_ext <= clk_div(clk_div'length-1);
-- sclk_prebuf <= sclk_ext;
-- end if;
-- end process;
--
-- bufg_sclk : bufg
-- port map (
-- i => sclk_prebuf,
-- o => serial_clk
-- );
----------------------------------------------------------------------------------------------------
-- Stellar Command Interface
----------------------------------------------------------------------------------------------------
fmc11x_stellar_cmd_inst : fmc11x_stellar_cmd
generic map
(
start_addr =>start_addr,
stop_addr =>stop_addr
)
port map
(
reset =>rst,
--command if
clk_cmd =>clk_cmd,
out_cmd =>out_cmd,
out_cmd_val =>out_cmd_val,
in_cmd =>in_cmd,
in_cmd_val =>in_cmd_val,
--register interface
clk_reg =>clk_cmd,
out_reg =>out_reg,
out_reg_val =>out_reg_val,
out_reg_val_ack =>out_reg_val_ack,
out_reg_addr =>out_reg_addr,
in_reg =>in_reg,
in_reg_val =>in_reg_val,
in_reg_req =>in_reg_req,
in_reg_addr =>in_reg_addr,
wr_ack => wr_ack,
mbx_in_reg =>(others=>'0'),
mbx_in_val =>'0'
);
----------------------------------------------------------------------------------------------------
-- Shoot commands to the state machine
----------------------------------------------------------------------------------------------------
process (rst, clk)
begin
if (rst = '1') then
init_done <= '0';
init_done_tmp <= '0';
init_done_prev <= '0';
init <= '0';
in_reg_val <= '0';
in_reg <= (others => '0');
inst_val <= '0';
inst_rw <= '0';
inst_reg <= (others=> '0');
data_reg <= (others=> '0');
wr_ack <= '0';
wr_cmd_ack <= '0';
wr_ack_requested <= '0';
elsif (rising_edge(clk)) then
init_done <= init_done_sclk;
init_done_tmp <= done_sclk;
init_done_prev <= init_done_tmp;
-- Release the init flag on rising edge init done
if (init_done_tmp = '1' and init_done_prev = '0') then
init <= '0';
-- Enable the init flag when enable flag is high, but done flag is low
elsif (init_ena = '1' and init_done_tmp = '0') then
init <= '1';
-- There is one additional status and control register available
elsif ((out_reg_val = '1' or out_reg_val_ack = '1') and out_reg_addr = ADDR_GLOBAL) then
init <= out_reg(0);
end if;
--Write
if ((out_reg_val = '1' or out_reg_val_ack = '1') and out_reg_addr = ADDR_GLOBAL) then
wr_cmd_ack <= '1';
else
wr_cmd_ack <= '0';
end if;
-- only send a write Ack on request:
if (out_reg_val_ack = '1') then
wr_ack_requested <= '1';
elsif(wr_ack = '1') then
wr_ack_requested <= '0';
end if;
if (wr_cmd_ack = '1' and wr_ack_requested = '1') then
wr_ack <= '1';
elsif(serial_val_ack = '1' and inst_rw = '0' and wr_ack_requested = '1') then
wr_ack <= '1';
else
wr_ack <= '0';
end if;
-- There is one additional status and control register available
if (in_reg_req = '1' and in_reg_addr = ADDR_GLOBAL) then
in_reg_val <= '1';
in_reg <= conv_std_logic_vector(0, 27) & '0' & busy & '0' & '0' & init_done_prev;
-- read from serial if when address is within device range
elsif (in_reg_addr <= ADDR_MAX_RD) then
in_reg_val <= data_read_val;
in_reg <= conv_std_logic_vector(0, 24) & data_read;
else
in_reg_val <= '0';
in_reg <= in_reg;
end if;
-- Write instruction, only when address is within device range
if ((out_reg_val = '1' or out_reg_val_ack = '1') and out_reg_addr <= ADDR_MAX_WR) then
inst_val <= '1';
inst_rw <= '0'; -- write
inst_reg <= out_reg_addr(2 downto 0);
data_reg <= out_reg(7 downto 0);
-- Read instruction, only when address is within device range
elsif (in_reg_req = '1' and in_reg_addr <= ADDR_MAX_RD) then
inst_val <= '1';
inst_rw <= '1'; -- read
inst_reg <= in_reg_addr(2 downto 0);
data_reg <= data_reg;
-- No instruction
else
inst_val <= '0';
inst_rw <= inst_rw;
inst_reg <= inst_reg;
data_reg <= data_reg;
end if;
end if;
end process;
-- Intruction pulse
pulse2pulse_inst0 : pulse2pulse
port map
(
rst => rst,
in_clk => clk,
out_clk => serial_clk,
pulsein => inst_val,
pulseout => inst_reg_val,
inbusy => open
);
----------------------------------------------------------------------------------------------------
-- Serial interface state-machine
----------------------------------------------------------------------------------------------------
process (rst, serial_clk)
begin
if (rst = '1') then
init_tmp <= '0';
init_reg <= '0';
sh_state <= idle;
sh_counter <= 0;
shifting <= '0';
read_n_write <= '0';
ncs_int <= '1';
elsif (rising_edge(serial_clk)) then
-- Double synchonise flag from other clock domain
init_tmp <= init;
init_reg <= init_tmp;
-- Main state machine
case sh_state is
when idle =>
sh_counter <= shift_reg'length-data_reg'length-1; --total length minus data bytes;
-- Accept every instruction
if (inst_reg_val = '1' or init_reg = '1') then
shifting <= '1';
read_n_write <= inst_rw and not init_reg; -- force write during init
ncs_int <= '0';
sh_state <= instruct;
else
shifting <= '0';
ncs_int <= '1';
end if;
when instruct =>
if (sh_counter = 0) then
sh_counter <= data_reg'length-1;
sh_state <= data_io;
else
sh_counter <= sh_counter - 1;
end if;
when data_io =>
if (sh_counter = 0) then
sh_counter <= shift_reg'length-data_reg'length-1; --total length minus data bytes;
shifting <= '0';
ncs_int <= '1';
if (read_n_write = '1') then
sh_state <= data_valid;
else
sh_state <= idle;
end if;
else
sh_counter <= sh_counter - 1;
end if;
when data_valid =>
sh_state <= idle;
when others =>
sh_state <= idle;
end case;
end if;
end process;
busy <= '0' when (sh_state = idle and init_reg = '0') else '1';
-- Detect the end of a serial write, don't send an Ack after completing the initialisation.
process (serial_clk)
begin
if (rising_edge(serial_clk)) then
busy_del1 <= busy;
busy_del2 <= busy_del1;
init_done_sclk_del <= init_done_sclk;
if(busy_del2 = '1' and busy_del1 = '0' and init_done_sclk_del = '1' and init_done_sclk = '1') then
serial_val_ack_sclk <= '1';
elsif(busy_del2 = '1' and busy_del1 = '0' and init_done_sclk_del = '0' and init_done_sclk = '0') then
serial_val_ack_sclk <= '1';
else
serial_val_ack_sclk <= '0';
end if;
end if;
end process;
-- Transfer end write pulse to other clock domain
pulse2pulse_inst2 : pulse2pulse
port map
(
rst => rst,
in_clk => serial_clk,
out_clk => clk,
pulsein => serial_val_ack_sclk,
pulseout => serial_val_ack,
inbusy => open
);
----------------------------------------------------------------------------------------------------
-- Instruction & data shift register
----------------------------------------------------------------------------------------------------
process (rst, serial_clk)
begin
if (rst = '1') then
shift_reg <= (others => '0');
init_address <= (others => '0');
done_sclk <= '0';
init_done_sclk <= '0';
read_byte_val <= '0';
data_read <= (others => '0');
elsif (rising_edge(serial_clk)) then
if (init_reg = '1' and shifting = '0') then
shift_reg <= PRESEL & '0' & "0000" & init_data(10 downto 0);
-- Stop when update instruction is reveived (= last instruction)
if (init_data(10 downto 8) = ADDR_MAX_WR) then
init_address <= (others => '0');
done_sclk <= '1';
else
init_address <= init_address + 1;
done_sclk <= '0';
end if;
elsif (inst_reg_val = '1' and init_reg = '0') then
shift_reg <= PRESEL & inst_rw & "0000" & inst_reg & data_reg;
elsif (shifting = '1') then
shift_reg <= shift_reg(shift_reg'length-2 downto 0) & sdi;
end if;
if (done_sclk = '0') then
init_done_sclk <= '0';
elsif (sh_state = idle) then
init_done_sclk <= '1';
end if;
-- Data read from device
if (sh_state = data_valid) then
read_byte_val <= '1';
data_read <= shift_reg(7 downto 0);
else
read_byte_val <= '0';
data_read <= data_read;
end if;
end if;
end process;
-- Transfer data valid pulse to other clock domain
pulse2pulse_inst1 : pulse2pulse
port map
(
rst => rst,
in_clk => serial_clk,
out_clk => clk,
pulsein => read_byte_val,
pulseout => data_read_val,
inbusy => open
);
----------------------------------------------------------------------------------------------------
-- Initialization memory
----------------------------------------------------------------------------------------------------
ltc2175_init_mem_inst : ltc2175_init_mem
port map (
clka => serial_clk,
addra => init_address,
douta => init_data
);
----------------------------------------------------------------------------------------------------
-- Capture data in on rising edge SCLK
-- therefore freeze the signal on the falling edge of serial clock.
----------------------------------------------------------------------------------------------------
process (serial_clk)
begin
if (falling_edge(serial_clk)) then
sdi <= spi_sdi;
end if;
end process;
----------------------------------------------------------------------------------------------------
-- Connect entity
----------------------------------------------------------------------------------------------------
in_cmd_busy <= busy; -- serial interface busy
spi_n_oe <= '1' when (sh_state = data_io and read_n_write = '1') else ncs_int;
spi_n_cs <= ncs_int;
spi_sclk <= not sclk_ext when ncs_int = '0' else '0';
spi_sdo <= 'Z' when (sh_state = data_io and read_n_write = '1') else shift_reg(shift_reg'length - 1);
----------------------------------------------------------------------------------------------------
-- End
----------------------------------------------------------------------------------------------------
end fmc116_ltc2175_ctrl_syn;
| mit | b1e45cebf2c56d6579dcccc22dca54aa | 0.476044 | 3.619675 | false | false | false | false |
Naegolus/qam | src/tbd_qam.vhd | 1 | 2,748 | -----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- This file is part of the DE0 Nano Linux project --
-- http://www.de0nanolinux.com --
-- --
-- Author(s): --
-- - Helmut, [email protected] --
-- --
-----------------------------------------------------------------------------
-- --
-- Copyright (C) 2015 Authors and www.de0nanolinux.com --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.fixed_pkg.all;
entity qam_mapper is
generic
(
n : natural := 1
);
port
(
data : in std_ulogic_vector(4**n - 1 downto 0);
in_phase : out sfixed(1 downto -(4**(n - 1) - 2));
quadrature : out sfixed(1 downto -(4**(n - 1) - 2))
);
end entity qam_mapper;
architecture rtl of qam_mapper is
begin
qam_m: entity work.qam_mapper(rtl)
generic map
(
n => n
)
port map
(
data => data,
in_phase => in_phase,
quadrature => quadrature
);
end architecture rtl;
| gpl-3.0 | ad66fb3a517cbe700e3f9b22cb6fcd9b | 0.351892 | 5.346304 | false | false | false | false |
CEIT-Laboratories/Arch-Lab | AUT-MIPS/regfile.vhd | 1 | 925 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity regfile is
generic (N : integer := 3;
M : integer := 16);
port (readaddr1, readaddr2 : in std_logic_vector (N - 1 downto 0);
writeaddr : in std_logic_vector (N - 1 downto 0);
data : in std_logic_vector (M - 1 downto 0);
write, clk : in std_logic;
O1, O2 : out std_logic_vector (M - 1 downto 0));
end entity;
architecture rtl of regfile is
type mem is array (natural range <>) of std_logic_vector (M - 1 downto 0);
constant memsize : integer := 2 ** N;
signal memory : mem (0 to memsize - 1) := (others => (others => '0'));
begin
process (clk)
begin
if clk'event and clk = '1' then
if write = '1' then
memory(to_integer(unsigned(writeaddr))) <= data;
else
O1 <= memory(to_integer(unsigned(readaddr1)));
O2 <= memory(to_integer(unsigned(readaddr2)));
end if;
end if;
end process;
end architecture rtl;
| gpl-3.0 | aa58408340fdc8f9d0e0250adb9423f1 | 0.648649 | 2.955272 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sources_1/rtl/switch_port/config/config_mac_phy_sm.vhd | 2 | 33,013 | --------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_axi_lite_sm.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Description: This module is reponsible for bringing up both the MAC and the
-- attached PHY (if any) to enable basic packet transfer in both directions.
-- It is intended to be directly usable on a xilinx demo platform to demonstrate
-- simple bring up and data transfer. The mac speed is set via inputs (which
-- can be connected to dip switches) and the PHY is configured to ONLY advertise
-- the specified speed. To maximise compatibility on boards only IEEE registers
-- are used and the PHY address can be set via a parameter.
--
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity config_mac_phy_sm is
port (
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
phy_interrupt_n : in std_logic;
mac_interrupt : in std_logic;
mac_speed : in std_logic_vector(1 downto 0);
update_speed : in std_logic;
serial_command : in std_logic;
serial_response : out std_logic;
debug0_sig : out std_logic;
debug1_sig : out std_logic;
debug2_sig : out std_logic;
debug3_sig : out std_logic;
s_axi_awaddr : out std_logic_vector(11 downto 0) := (others => '0');
s_axi_awvalid : out std_logic := '0';
s_axi_awready : in std_logic := '0';
s_axi_wdata : out std_logic_vector(31 downto 0) := (others => '0');
s_axi_wvalid : out std_logic := '0';
s_axi_wready : in std_logic := '0';
s_axi_bresp : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_bvalid : in std_logic := '0';
s_axi_bready : out std_logic := '0';
s_axi_araddr : out std_logic_vector(11 downto 0) := (others => '0');
s_axi_arvalid : out std_logic := '0';
s_axi_arready : in std_logic := '0';
s_axi_rdata : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_rresp : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_rvalid : in std_logic := '0';
s_axi_rready : out std_logic := '0'
);
end config_mac_phy_sm;
architecture rtl of config_mac_phy_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
component aeg_design_0_sync_block
port (
clk : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end component;
-- main state machine
-- Encoded main state machine states.
type state_typ is (STARTUP,
-- CHANGE_SPEED, -- not necessary, check phy first
-- MDIO_SET_INTERRUPT,
-- MDIO_READ_INTERRUPT,
MDIO_RESTART, -- restart and autoneg
MDIO_STATS, -- polling for autoneg
MDIO_STATS_POLL_CHECK, -- polling for autoneg, replace with interrupt
MDIO_READ_INTERRUPT2,
MDIO_READ_SPEED,
MDIO_READ_SPEED_POLL,
MAC_UPDATE_SPEED100,
MAC_UPDATE_SPEED1000,
CHECK_SPEED); -- waiting for a speed update
-- MDIO State machine
type mdio_state_typ is (IDLE,
SET_DATA,
INIT,
POLL);
-- AXI State Machine
type axi_state_typ is (IDLE_A,
READ,
WRITE,
DONE);
-- Management configuration register address (0x500)
constant CONFIG_MANAGEMENT_ADD : std_logic_vector(16 downto 0) := "00000" & X"500";
-- Receiver configuration register address (0x4040)
constant RECEIVER_ADD : std_logic_vector(16 downto 0) := "00000" & X"404";
-- Transmitter configuration register address (0x4080)
constant TRANSMITTER_ADD : std_logic_vector(16 downto 0) :="00000" & X"408";
-- Speed configuration register address (0x410)
constant SPEED_CONFIG_ADD : std_logic_vector(16 downto 0) :="00000" & X"410";
-- MDIO registers
constant MDIO_CONTROL : std_logic_vector(16 downto 0) := "00000" & X"504";
constant MDIO_TX_DATA : std_logic_vector(16 downto 0) := "00000" & X"508";
constant MDIO_RX_DATA : std_logic_vector(16 downto 0) := "00000" & X"50C";
constant MDIO_OP_RD : std_logic_vector(1 downto 0) := "10";
constant MDIO_OP_WR : std_logic_vector(1 downto 0) := "01";
-- PHY Registers
-- phy address is actually a 6 bit field but other bits are reserved so simpler to specify as 8 bit
--constant PHY_ADDR : std_logic_vector(7 downto 0) := X"07";
constant PHY_ADDR : std_logic_vector(7 downto 0) := X"00";
constant PHY_CONTROL_REG : std_logic_vector(7 downto 0) := X"00";
constant PHY_STATUS_REG : std_logic_vector(7 downto 0) := X"01";
constant PHY_ABILITY_REG : std_logic_vector(7 downto 0) := X"04";
constant PHY_1000BASET_CONTROL_REG : std_logic_vector(7 downto 0) := X"09";
constant PHY_1000BASET_STATUS_REG : std_logic_vector(7 downto 0) := X"0A";
constant PHY_INTERRUPT_REG : std_logic_vector(7 downto 0) := X"12";
constant PHY_CLEAR_INTERRUPT_REG : std_logic_vector(7 downto 0) := X"13";
---------------------------------------------------
-- Signal declarations
signal axi_status : std_logic_vector(4 downto 0); -- used to keep track of axi transactions
signal mdio_ready : std_logic := '0'; -- captured to acknowledge the end of mdio transactions
signal axi_rd_data : std_logic_vector(31 downto 0) := (others => '0');
signal axi_wr_data : std_logic_vector(31 downto 0);
signal mdio_wr_data : std_logic_vector(31 downto 0) := (others => '0');
signal axi_state : state_typ; -- main state machine to configure example design
signal mdio_access_sm : mdio_state_typ; -- mdio state machine to handle mdio register config
signal axi_access_sm : axi_state_typ; -- axi state machine - handles the 5 channels
signal start_access : std_logic; -- used to kick the axi acees state machine
signal start_mdio : std_logic; -- used to kick the mdio state machine
signal drive_mdio : std_logic; -- selects between mdio fields and direct sm control
signal mdio_op : std_logic_vector(1 downto 0);
signal mdio_reg_addr : std_logic_vector(7 downto 0);
signal writenread : std_logic;
signal addr : std_logic_vector(16 downto 0);
signal speed : std_logic_vector(1 downto 0);
signal update_speed_sync : std_logic;
signal update_speed_reg : std_logic;
signal count_shift : std_logic_vector(20 downto 0) := (others => '1');
-- to avoid logic being stripped a serial input is included which enables an address/data and
-- control to be setup for a user config access..
signal serial_command_shift : std_logic_vector(36 downto 0);
signal load_data : std_logic;
signal capture_data : std_logic;
signal write_access : std_logic;
signal read_access : std_logic;
signal s_axi_reset : std_logic;
signal s_axi_awvalid_int : std_logic;
signal s_axi_wvalid_int : std_logic;
signal s_axi_bready_int : std_logic;
signal s_axi_arvalid_int : std_logic;
signal s_axi_rready_int : std_logic;
--attribute mark_debug : string;
--attribute mark_debug of axi_status : signal is "true";
--attribute mark_debug of mdio_ready : signal is "true";
--attribute mark_debug of axi_rd_data : signal is "true";
--attribute mark_debug of axi_wr_data : signal is "true";
--attribute mark_debug of mdio_wr_data : signal is "true";
--attribute mark_debug of axi_state : signal is "true";
--attribute mark_debug of mdio_access_sm : signal is "true";
--attribute mark_debug of axi_access_sm : signal is "true";
--attribute mark_debug of start_access : signal is "true";
--attribute mark_debug of start_mdio : signal is "true";
--attribute mark_debug of drive_mdio : signal is "true";
--attribute mark_debug of mdio_op : signal is "true";
--attribute mark_debug of mdio_reg_addr : signal is "true";
--attribute mark_debug of writenread : signal is "true";
--attribute mark_debug of addr : signal is "true";
--attribute mark_debug of speed : signal is "true";
--attribute mark_debug of update_speed_sync : signal is "true";
--attribute mark_debug of update_speed_reg : signal is "true";
--attribute mark_debug of count_shift : signal is "true";
--attribute mark_debug of s_axi_aclk : signal is "true";
--attribute mark_debug of s_axi_resetn : signal is "true";
--attribute mark_debug of phy_interrupt_n : signal is "true";
--attribute mark_debug of mac_interrupt : signal is "true";
--attribute mark_debug of s_axi_awaddr : signal is "true";
--attribute mark_debug of s_axi_awvalid : signal is "true";
--attribute mark_debug of s_axi_awready : signal is "true";
--attribute mark_debug of s_axi_wdata : signal is "true";
--attribute mark_debug of s_axi_wvalid : signal is "true";
--attribute mark_debug of s_axi_wready : signal is "true";
--attribute mark_debug of s_axi_bresp : signal is "true";
--attribute mark_debug of s_axi_bvalid : signal is "true";
--attribute mark_debug of s_axi_bready : signal is "true";
--attribute mark_debug of s_axi_araddr : signal is "true";
--attribute mark_debug of s_axi_arvalid : signal is "true";
--attribute mark_debug of s_axi_arready : signal is "true";
--attribute mark_debug of s_axi_rdata : signal is "true";
--attribute mark_debug of s_axi_rresp : signal is "true";
--attribute mark_debug of s_axi_rvalid : signal is "true";
--attribute mark_debug of s_axi_rready : signal is "true";
begin
s_axi_awvalid <= s_axi_awvalid_int;
s_axi_wvalid <= s_axi_wvalid_int;
s_axi_bready <= s_axi_bready_int;
s_axi_arvalid <= s_axi_arvalid_int;
s_axi_rready <= s_axi_rready_int;
s_axi_reset <= not s_axi_resetn;
update_speed_sync <= update_speed;
update_reg : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if s_axi_reset = '1' then
update_speed_reg <= '0';
else
update_speed_reg <= update_speed_sync;
end if;
end if;
end process update_reg;
-----------------------------------------------------------------------------
-- Management process. This process sets up the configuration by
-- turning off flow control, then checks gathered statistics at the
-- end of transmission
-----------------------------------------------------------------------------
gen_state : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if s_axi_reset = '1' then
axi_state <= STARTUP;
start_access <= '0';
start_mdio <= '0';
drive_mdio <= '0';
mdio_op <= (others => '0');
mdio_reg_addr <= (others => '0');
writenread <= '0';
addr <= (others => '0');
axi_wr_data <= (others => '0');
speed <= mac_speed;
debug0_sig <= '0';
debug1_sig <= '0';
debug2_sig <= '0';
debug3_sig <= '0';
-- main state machine is kicking off multi cycle accesses in each state so has to
-- stall while they take place
elsif axi_access_sm = IDLE_A and mdio_access_sm = IDLE and start_access = '0' and start_mdio = '0' then
case axi_state is
when STARTUP =>
-- this state will be ran after reset to wait for count_shift
if (count_shift(20) = '0') then
-- set up MDC frequency. Write to Management configuration
-- register. This will enable MDIO and set MDC to 2.5MHz
speed <= mac_speed;
assert false
report "Setting MDC Frequency to 2.5MHz...." & cr
severity note;
start_mdio <= '0';
drive_mdio <= '0';
start_access <= '1';
writenread <= '1';
addr <= CONFIG_MANAGEMENT_ADD;
--axi_wr_data <= X"00000053"; -- this is 2.5 MHz
axi_wr_data <= X"00000068";
axi_state <= MDIO_RESTART;
end if;
-- when SET_PHY_SPEEDS => -- not needed, MAC and PHY support both 10M - 1G defaultly
-- when MDIO_SET_INTERRUPT =>
-- debug0_sig <= '1';
-- -- set auto-negotiation interrupt
-- assert false
-- report "Setting Auto-Negotiation-Completed interrupt" & cr
-- severity note;
-- drive_mdio <= '1';
-- start_mdio <= '1';
-- start_access <= '0';
-- writenread <= '0';
-- mdio_reg_addr <= PHY_INTERRUPT_REG;
-- mdio_op <= MDIO_OP_WR;
-- axi_wr_data <= X"00000800"; -- bit 11 for auto-negotiation completed, bit 14 for speed changed
-- axi_state <= MDIO_READ_INTERRUPT;
-- when MDIO_READ_INTERRUPT =>
-- drive_mdio <= '1';
-- start_mdio <= '1';
-- start_access <= '0';
-- writenread <= '0';
-- assert false
-- report "Read interrupt" & cr
-- severity note;
-- mdio_reg_addr <= PHY_INTERRUPT_REG;
-- mdio_op <= MDIO_OP_RD;
-- axi_state <= MDIO_RESTART;
when MDIO_RESTART =>
if axi_rd_data = X"00010800" then
debug1_sig <= '1';
end if;
-- set autoneg and reset
-- if loopback is selected then do not set autonegotiate and program the required speed directly
-- otherwise set autonegotiate
assert false
report "Applying PHY software reset" & cr
severity note;
drive_mdio <= '1';
start_mdio <= '1';
start_access <= '0';
writenread <= '0';
mdio_reg_addr <= PHY_CONTROL_REG;
mdio_op <= MDIO_OP_WR;
--axi_wr_data <= X"0000" & X"9" & X"000";
axi_wr_data <= X"00009000";
axi_state <= MDIO_STATS;
when MDIO_STATS =>
drive_mdio <= '1';
start_mdio <= '1';
start_access <= '0';
writenread <= '0';
assert false
report "Wait for Autonegotiation to complete" & cr
severity note;
mdio_reg_addr <= PHY_STATUS_REG;
mdio_op <= MDIO_OP_RD;
axi_state <= MDIO_STATS_POLL_CHECK;
when MDIO_STATS_POLL_CHECK =>
-- bit 5 is autoneg complete - assume required speed is selected
if axi_rd_data(5) = '1' then
axi_state <= MDIO_READ_INTERRUPT2;
-- axi_state <= CHECK_SPEED;
else
axi_state <= MDIO_STATS;
end if;
when MDIO_READ_INTERRUPT2 =>
drive_mdio <= '1';
start_mdio <= '1';
start_access <= '0';
writenread <= '0';
assert false
report "Read interrupt" & cr
severity note;
mdio_reg_addr <= PHY_INTERRUPT_REG;
mdio_op <= MDIO_OP_RD;
axi_state <= MDIO_READ_SPEED;
when MDIO_READ_SPEED =>
drive_mdio <= '1';
start_mdio <= '1';
start_access <= '0';
writenread <= '0';
assert false
report "Read negotiated speed" & cr
severity note;
mdio_reg_addr <= PHY_1000BASET_STATUS_REG;
mdio_op <= MDIO_OP_RD;
axi_state <= MDIO_READ_SPEED_POLL;
when MDIO_READ_SPEED_POLL =>
if axi_rd_data(11) = '1' then -- link partner 1G capable
axi_state <= MAC_UPDATE_SPEED1000;
debug2_sig <= '1';
else
axi_state <= MAC_UPDATE_SPEED100;
debug2_sig <= '0';
end if;
when MAC_UPDATE_SPEED100 =>
assert false
report "Programming MAC speed 100" & cr
severity note;
drive_mdio <= '0';
start_mdio <= '0';
start_access <= '1';
writenread <= '1';
addr <= SPEED_CONFIG_ADD;
-- bits 31:30 are used
axi_wr_data <= "01" & X"0000000" & "00";
axi_state <= CHECK_SPEED;
when MAC_UPDATE_SPEED1000 =>
assert false
report "Programming MAC speed 1000" & cr
severity note;
drive_mdio <= '0';
start_mdio <= '0';
start_access <= '1';
writenread <= '1';
addr <= SPEED_CONFIG_ADD;
-- bits 31:30 are used
axi_wr_data <= "10" & X"0000000" & "00";
axi_state <= CHECK_SPEED;
when CHECK_SPEED =>
debug3_sig <= '1';
if update_speed_reg = '1' then
--axi_state <= CHANGE_SPEED;
axi_state <= STARTUP;
else
if capture_data = '1' then
axi_wr_data <= serial_command_shift(33 downto 2);
end if;
if write_access = '1' or read_access = '1' then
addr <= "00000" & serial_command_shift (13 downto 2);
start_access <= '1';
writenread <= write_access;
end if;
end if;
when others =>
axi_state <= STARTUP;
end case;
else
start_access <= '0';
start_mdio <= '0';
end if;
end if;
end process gen_state;
--------------------------------------------------
-- MDIO setup - split from main state machine to make more manageable
gen_mdio_state : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if s_axi_reset = '1' then
mdio_access_sm <= IDLE;
elsif axi_access_sm = IDLE_A or axi_access_sm = DONE then
case mdio_access_sm is
when IDLE =>
if start_mdio = '1' then
if mdio_op = MDIO_OP_WR then
mdio_access_sm <= SET_DATA;
mdio_wr_data <= axi_wr_data;
else
mdio_access_sm <= INIT;
mdio_wr_data <= PHY_ADDR & mdio_reg_addr & mdio_op & "001" & "00000000000";
end if;
end if;
when SET_DATA =>
mdio_access_sm <= INIT;
mdio_wr_data <= PHY_ADDR & mdio_reg_addr & mdio_op & "001" & "00000000000";
when INIT =>
mdio_access_sm <= POLL;
when POLL =>
if mdio_ready = '1' then
mdio_access_sm <= IDLE;
end if;
end case;
elsif mdio_access_sm = POLL and mdio_ready = '1' then
mdio_access_sm <= IDLE;
end if;
end if;
end process gen_mdio_state;
---------------------------------------------------------------------------------------------
-- processes to generate the axi transactions - only simple reads and write can be generated
gen_axi_state : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if s_axi_reset = '1' then
axi_access_sm <= IDLE_A;
else
case axi_access_sm is
when IDLE_A =>
if start_access = '1' or start_mdio = '1' or mdio_access_sm /= IDLE then
if mdio_access_sm = POLL then
axi_access_sm <= READ;
elsif (start_access = '1' and writenread = '1') or
(start_mdio = '1' or mdio_access_sm = SET_DATA or mdio_access_sm = INIT) then
axi_access_sm <= WRITE;
else
axi_access_sm <= READ;
end if;
end if;
when WRITE =>
-- wait in this state until axi_status signals the write is complete
if axi_status(4 downto 2) = "111" then
axi_access_sm <= DONE;
end if;
when READ =>
-- wait in this state until axi_status signals the read is complete
if axi_status(1 downto 0) = "11" then
axi_access_sm <= DONE;
end if;
when DONE =>
axi_access_sm <= IDLE_A;
end case;
end if;
end if;
end process gen_axi_state;
-- need a process per axi interface (i.e 5)
-- in each case the interface is driven accordingly and once acknowledged a sticky
-- status bit is set and the process waits until the access_sm moves on
-- READ ADDR
read_addr_p : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if axi_access_sm = READ then
if axi_status(0) = '0' then
if drive_mdio = '1' then
s_axi_araddr <= MDIO_RX_DATA(11 downto 0);
else
s_axi_araddr <= addr(11 downto 0);
end if;
s_axi_arvalid_int <= '1';
if s_axi_arready = '1' and s_axi_arvalid_int = '1' then
axi_status(0) <= '1';
s_axi_araddr <= (others => '0');
s_axi_arvalid_int <= '0';
end if;
end if;
else
axi_status(0) <= '0';
s_axi_araddr <= (others => '0');
s_axi_arvalid_int <= '0';
end if;
end if;
end process read_addr_p;
-- READ DATA/RESP
read_data_p : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if axi_access_sm = READ then
if axi_status(1) = '0' then
s_axi_rready_int <= '1';
if s_axi_rvalid = '1' and s_axi_rready_int = '1' then
axi_status(1) <= '1';
s_axi_rready_int <= '0';
axi_rd_data <= s_axi_rdata;
if drive_mdio = '1' and s_axi_rdata(16) = '1' then
mdio_ready <= '1';
end if;
end if;
end if;
else
s_axi_rready_int <= '0';
axi_status(1) <= '0';
if axi_access_sm = IDLE_A and (start_access = '1' or start_mdio = '1') then
mdio_ready <= '0';
axi_rd_data <= (others => '0');
end if;
end if;
end if;
end process read_data_p;
-- WRITE ADDR
write_addr_p : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if axi_access_sm = WRITE then
if axi_status(2) = '0' then
if drive_mdio = '1' then
if mdio_access_sm = SET_DATA then
s_axi_awaddr <= MDIO_TX_DATA(11 downto 0);
else
s_axi_awaddr <= MDIO_CONTROL(11 downto 0);
end if;
else
s_axi_awaddr <= addr(11 downto 0);
end if;
s_axi_awvalid_int <= '1';
if s_axi_awready = '1' and s_axi_awvalid_int = '1' then
axi_status(2) <= '1';
s_axi_awaddr <= (others => '0');
s_axi_awvalid_int <= '0';
end if;
end if;
else
s_axi_awaddr <= (others => '0');
s_axi_awvalid_int <= '0';
axi_status(2) <= '0';
end if;
end if;
end process write_addr_p;
-- WRITE DATA
write_data_p : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if axi_access_sm = WRITE then
if axi_status(3) = '0' then
if drive_mdio = '1' then
s_axi_wdata <= mdio_wr_data;
else
s_axi_wdata <= axi_wr_data;
end if;
s_axi_wvalid_int <= '1';
if s_axi_wready = '1' and s_axi_wvalid_int = '1' then
axi_status(3) <= '1';
s_axi_wdata <= (others => '0');
s_axi_wvalid_int <= '0';
end if;
end if;
else
s_axi_wdata <= (others => '0');
s_axi_wvalid_int <= '0';
axi_status(3) <= '0';
end if;
end if;
end process write_data_p;
-- WRITE RESP
write_resp_p : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if axi_access_sm = WRITE then
if axi_status(4) = '0' then
s_axi_bready_int <= '1';
if s_axi_bvalid = '1' and s_axi_bready_int = '1' then
axi_status(4) <= '1';
s_axi_bready_int <= '0';
end if;
end if;
else
s_axi_bready_int <= '0';
axi_status(4) <= '0';
end if;
end if;
end process write_resp_p;
shift_command : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if load_data = '1' then
serial_command_shift <= serial_command_shift(35 downto 33) & axi_rd_data & serial_command_shift(0) & serial_command;
else
serial_command_shift <= serial_command_shift(35 downto 0) & serial_command;
end if;
end if;
end process shift_command;
serial_response <= serial_command_shift(34) when axi_state = CHECK_SPEED else '1';
-- the serial command is expected to have a start and stop bit - to avoid a counter -
-- and a two bit code field in the uppper two bits.
-- these decode as follows:
-- 00 - read address
-- 01 - write address
-- 10 - write data
-- 11 - read data - slightly more involved - when detected the read data is registered into the shift and passed out
-- 11 is used for read data as if the input is tied high the output will simply reflect whatever was
-- captured but will not result in any activity
-- it is expected that the write data is setup BEFORE the write address
shift_decode : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
load_data <= '0';
capture_data <= '0';
write_access <= '0';
read_access <= '0';
if serial_command_shift(36) = '0' and serial_command_shift(35) = '1' and serial_command_shift(0) = '1' then
if serial_command_shift(34) = '1' and serial_command_shift(33) = '1' then
load_data <= '1';
elsif serial_command_shift(34) = '1' and serial_command_shift(33) = '0' then
capture_data <= '1';
elsif serial_command_shift(34) = '0' and serial_command_shift(33) = '1' then
write_access <= '1';
else
read_access <= '1';
end if;
end if;
end if;
end process shift_decode;
-- don't reset this - it will always be updated before it is used..
-- it does need an init value (all ones)
-- Create fully synchronous reset in the s_axi clock domain.
gen_count : process (s_axi_aclk)
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
count_shift <= count_shift(19 downto 0) & s_axi_reset;
end if;
end process gen_count;
end rtl;
| mit | 4906b3fb5156b6b223dd08e66b17e5e4 | 0.489353 | 4.160428 | false | false | false | false |
CEIT-Laboratories/Arch-Lab | priority-updater/src/memory.vhd | 1 | 1,149 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 30-03-2016
-- Module Name: memory.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity memory is
port (address : in std_logic_vector;
data_in : in std_logic_vector;
data_out : out std_logic_vector;
clk, rwbar : in std_logic);
end entity memory;
architecture behavioral of memory is
type mem is array (natural range <>, natural range <>) of std_logic;
begin
process (clk)
constant memsize : integer := 2 ** address'length;
variable memory : mem (0 to memsize - 1, data_in'range);
begin
if clk'event and clk = '1' then
if rwbar = '1' then -- Readiing :)
for i in data_out'range loop
data_out(i) <= memory (to_integer(unsigned(address)), i);
end loop;
else -- Writing :)
for i in data_in'range loop
memory (to_integer(unsigned(address)), i) := data_in (i);
end loop;
end if;
end if;
end process;
end architecture behavioral;
| gpl-3.0 | d01d852f8dd5f411275c2cc4a8db7171 | 0.569191 | 3.557276 | false | false | false | false |
Caian/Minesweeper | Projeto/vga_game_dec.vhd | 1 | 1,884 | ---------------------------------------------------------
-- MC613 - UNICAMP
--
-- Minesweeper
--
-- Caian Benedicto
-- Brunno Rodrigues Arangues
---------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
use work.all;
entity vga_game_dec is
port(
-- Estado do jogo
game_state : in std_logic_vector (1 downto 0);
-- Tipo do elemento e indice na ROM
element : in std_logic_vector (7 downto 0);
elemidx : out std_logic_vector (5 downto 0)
);
end entity;
architecture vga_game_dec_logic of vga_game_dec is
signal w, e, f, c, m : std_logic;
begin
-- Vitoria
w <= game_state(0);
-- Fim do jogo
e <= game_state(1);
-- Elemento mina
m <= '1' when element(3 downto 0) = "1111" else '0';
f <= element(4);
c <= element(5);
process (w, e, f, c, m)
begin
if ((not c and not e and not f and not w) or
(not c and not f and not m and not w)) = '1' then
-- Bloco fechado
elemidx <= "001001";
elsif ((c and e and not f and not m) or
(c and not f and not m and not w)) = '1' then
-- Bloco de numero
elemidx <= "00" & element(3 downto 0);
elsif (c and not f and m and not w) = '1' then
-- Explosao
elemidx <= "001101";
elsif ((not c and e and f and m) or
(not c and e and m and w) or
(not c and not e and f and not w)) = '1' then
-- Bandeira
elemidx <= "001010";
elsif (not c and e and not f and m and not w) = '1' then
-- Mina
elemidx <= "001011";
elsif (not c and e and f and not m and not w) = '1' then
-- Bandeira errada
elemidx <= "001100";
else
-- Situacao de erro
elemidx <= "001110";
end if;
end process;
end architecture;
| gpl-2.0 | f5512382ad3196c28f8854afdbcf2aa0 | 0.517516 | 3.155779 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_1/blk_mem_gen_1_funcsim.vhdl | 1 | 55,434 | -- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (win64) Build 881834 Fri Apr 4 14:15:54 MDT 2014
-- Date : Thu Jul 24 13:45:40 2014
-- Host : CE-2013-124 running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim
-- D:/SHS/Research/AutoEnetGway/Mine/xc702/aes_xc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_1/blk_mem_gen_1_funcsim.vhdl
-- Design : blk_mem_gen_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_1blk_mem_gen_prim_wrapper is
port (
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_1blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end blk_mem_gen_1blk_mem_gen_prim_wrapper;
architecture STRUCTURE of blk_mem_gen_1blk_mem_gen_prim_wrapper is
signal \n_72_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_73_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_74_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_75_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 5) => addrb(9 downto 0),
ADDRBWRADDR(4) => '1',
ADDRBWRADDR(3) => '1',
ADDRBWRADDR(2) => '1',
ADDRBWRADDR(1) => '1',
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => doutb(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3) => \n_72_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\,
DOPBDOP(2) => \n_73_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\,
DOPBDOP(1) => \n_74_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\,
DOPBDOP(0) => \n_75_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_1blk_mem_gen_prim_width is
port (
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_1blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end blk_mem_gen_1blk_mem_gen_prim_width;
architecture STRUCTURE of blk_mem_gen_1blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.blk_mem_gen_1blk_mem_gen_prim_wrapper
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(9 downto 0) => addrb(9 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_1blk_mem_gen_generic_cstr is
port (
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_1blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end blk_mem_gen_1blk_mem_gen_generic_cstr;
architecture STRUCTURE of blk_mem_gen_1blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.blk_mem_gen_1blk_mem_gen_prim_width
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(9 downto 0) => addrb(9 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_1blk_mem_gen_top is
port (
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_1blk_mem_gen_top : entity is "blk_mem_gen_top";
end blk_mem_gen_1blk_mem_gen_top;
architecture STRUCTURE of blk_mem_gen_1blk_mem_gen_top is
begin
\valid.cstr\: entity work.blk_mem_gen_1blk_mem_gen_generic_cstr
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(9 downto 0) => addrb(9 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_1blk_mem_gen_v8_2_synth is
port (
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
enb : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_1blk_mem_gen_v8_2_synth : entity is "blk_mem_gen_v8_2_synth";
end blk_mem_gen_1blk_mem_gen_v8_2_synth;
architecture STRUCTURE of blk_mem_gen_1blk_mem_gen_v8_2_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.blk_mem_gen_1blk_mem_gen_top
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(9 downto 0) => addrb(9 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 9 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 );
sleep : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is "blk_mem_gen_v8_2";
attribute C_FAMILY : string;
attribute C_FAMILY of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is "zynq";
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is "zynq";
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is "./";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is "NONE";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 4;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 9;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is "no_coe_file_loaded";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is "blk_mem_gen_1.mem";
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is "CE";
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is "READ_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 8;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 8;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 4096;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 4096;
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 12;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is "CE";
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is "READ_FIRST";
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 32;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 32;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 1024;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 1024;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 10;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is "ALL";
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is "1";
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is "Estimated Power for IP : 5.528025 mW";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ : entity is "yes";
end \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\;
architecture STRUCTURE of \blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
douta(7) <= \<const0>\;
douta(6) <= \<const0>\;
douta(5) <= \<const0>\;
douta(4) <= \<const0>\;
douta(3) <= \<const0>\;
douta(2) <= \<const0>\;
douta(1) <= \<const0>\;
douta(0) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.blk_mem_gen_1blk_mem_gen_v8_2_synth
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(9 downto 0) => addrb(9 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
enb => enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_1 is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
clkb : in STD_LOGIC;
enb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 9 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of blk_mem_gen_1 : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of blk_mem_gen_1 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of blk_mem_gen_1 : entity is "blk_mem_gen_v8_2,Vivado 2014.1";
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of blk_mem_gen_1 : entity is "blk_mem_gen_1,blk_mem_gen_v8_2,{}";
attribute core_generation_info : string;
attribute core_generation_info of blk_mem_gen_1 : entity is "blk_mem_gen_1,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=0,x_ipLanguage=VHDL,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=blk_mem_gen_1.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=READ_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=4096,C_READ_DEPTH_A=4096,C_ADDRA_WIDTH=12,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=READ_FIRST,C_WRITE_WIDTH_B=32,C_READ_WIDTH_B=32,C_WRITE_DEPTH_B=1024,C_READ_DEPTH_B=1024,C_ADDRB_WIDTH=10,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=1,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 5.528025 mW}";
end blk_mem_gen_1;
architecture STRUCTURE of blk_mem_gen_1 is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 12;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 10;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 1;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 5.528025 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 1;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "blk_mem_gen_1.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 1;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 4096;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 1024;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 8;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 32;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 4096;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 1024;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "READ_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "READ_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 8;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 32;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of U0 : label is std.standard.true;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.\blk_mem_gen_1blk_mem_gen_v8_2__parameterized0\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(9 downto 0) => addrb(9 downto 0),
clka => clka,
clkb => clkb,
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
dina(7 downto 0) => dina(7 downto 0),
dinb(31) => '0',
dinb(30) => '0',
dinb(29) => '0',
dinb(28) => '0',
dinb(27) => '0',
dinb(26) => '0',
dinb(25) => '0',
dinb(24) => '0',
dinb(23) => '0',
dinb(22) => '0',
dinb(21) => '0',
dinb(20) => '0',
dinb(19) => '0',
dinb(18) => '0',
dinb(17) => '0',
dinb(16) => '0',
dinb(15) => '0',
dinb(14) => '0',
dinb(13) => '0',
dinb(12) => '0',
dinb(11) => '0',
dinb(10) => '0',
dinb(9) => '0',
dinb(8) => '0',
dinb(7) => '0',
dinb(6) => '0',
dinb(5) => '0',
dinb(4) => '0',
dinb(3) => '0',
dinb(2) => '0',
dinb(1) => '0',
dinb(0) => '0',
douta(7 downto 0) => NLW_U0_douta_UNCONNECTED(7 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
eccpipece => '0',
ena => '0',
enb => enb,
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(9 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(9 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rstb => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31) => '0',
s_axi_araddr(30) => '0',
s_axi_araddr(29) => '0',
s_axi_araddr(28) => '0',
s_axi_araddr(27) => '0',
s_axi_araddr(26) => '0',
s_axi_araddr(25) => '0',
s_axi_araddr(24) => '0',
s_axi_araddr(23) => '0',
s_axi_araddr(22) => '0',
s_axi_araddr(21) => '0',
s_axi_araddr(20) => '0',
s_axi_araddr(19) => '0',
s_axi_araddr(18) => '0',
s_axi_araddr(17) => '0',
s_axi_araddr(16) => '0',
s_axi_araddr(15) => '0',
s_axi_araddr(14) => '0',
s_axi_araddr(13) => '0',
s_axi_araddr(12) => '0',
s_axi_araddr(11) => '0',
s_axi_araddr(10) => '0',
s_axi_araddr(9) => '0',
s_axi_araddr(8) => '0',
s_axi_araddr(7) => '0',
s_axi_araddr(6) => '0',
s_axi_araddr(5) => '0',
s_axi_araddr(4) => '0',
s_axi_araddr(3) => '0',
s_axi_araddr(2) => '0',
s_axi_araddr(1) => '0',
s_axi_araddr(0) => '0',
s_axi_arburst(1) => '0',
s_axi_arburst(0) => '0',
s_axi_arid(3) => '0',
s_axi_arid(2) => '0',
s_axi_arid(1) => '0',
s_axi_arid(0) => '0',
s_axi_arlen(7) => '0',
s_axi_arlen(6) => '0',
s_axi_arlen(5) => '0',
s_axi_arlen(4) => '0',
s_axi_arlen(3) => '0',
s_axi_arlen(2) => '0',
s_axi_arlen(1) => '0',
s_axi_arlen(0) => '0',
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2) => '0',
s_axi_arsize(1) => '0',
s_axi_arsize(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31) => '0',
s_axi_awaddr(30) => '0',
s_axi_awaddr(29) => '0',
s_axi_awaddr(28) => '0',
s_axi_awaddr(27) => '0',
s_axi_awaddr(26) => '0',
s_axi_awaddr(25) => '0',
s_axi_awaddr(24) => '0',
s_axi_awaddr(23) => '0',
s_axi_awaddr(22) => '0',
s_axi_awaddr(21) => '0',
s_axi_awaddr(20) => '0',
s_axi_awaddr(19) => '0',
s_axi_awaddr(18) => '0',
s_axi_awaddr(17) => '0',
s_axi_awaddr(16) => '0',
s_axi_awaddr(15) => '0',
s_axi_awaddr(14) => '0',
s_axi_awaddr(13) => '0',
s_axi_awaddr(12) => '0',
s_axi_awaddr(11) => '0',
s_axi_awaddr(10) => '0',
s_axi_awaddr(9) => '0',
s_axi_awaddr(8) => '0',
s_axi_awaddr(7) => '0',
s_axi_awaddr(6) => '0',
s_axi_awaddr(5) => '0',
s_axi_awaddr(4) => '0',
s_axi_awaddr(3) => '0',
s_axi_awaddr(2) => '0',
s_axi_awaddr(1) => '0',
s_axi_awaddr(0) => '0',
s_axi_awburst(1) => '0',
s_axi_awburst(0) => '0',
s_axi_awid(3) => '0',
s_axi_awid(2) => '0',
s_axi_awid(1) => '0',
s_axi_awid(0) => '0',
s_axi_awlen(7) => '0',
s_axi_awlen(6) => '0',
s_axi_awlen(5) => '0',
s_axi_awlen(4) => '0',
s_axi_awlen(3) => '0',
s_axi_awlen(2) => '0',
s_axi_awlen(1) => '0',
s_axi_awlen(0) => '0',
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2) => '0',
s_axi_awsize(1) => '0',
s_axi_awsize(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(9 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(9 downto 0),
s_axi_rdata(31 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(31 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(7) => '0',
s_axi_wdata(6) => '0',
s_axi_wdata(5) => '0',
s_axi_wdata(4) => '0',
s_axi_wdata(3) => '0',
s_axi_wdata(2) => '0',
s_axi_wdata(1) => '0',
s_axi_wdata(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
| mit | c4671e774d8b3d64d4fef705675cdd66 | 0.66912 | 3.353742 | false | false | false | false |
bargei/NoC264 | NoC264_2x2/deblocking_filter_node.vhd | 1 | 14,465 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
entity deblocking_filter_node is
generic (
data_width : integer := 64;
addr_width : integer := 1;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
-- recv interface to network
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
-- send interface to network
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic;
--debugging
has_rxd : out std_logic;
is_idle : out std_logic;
is_filtering : out std_logic;
is_tx_ing : out std_logic;
is_cleanup_ing : out std_logic;
rx_non_zero : out std_logic;
tx_non_zero : out std_logic
);
end entity deblocking_filter_node;
architecture fsmd of deblocking_filter_node is
component h264_deblock_filter_core is
port(
clk : in std_logic;
rst : in std_logic;
is_chroma : in std_logic;
boundary_strength : in signed(8 downto 0);
p0 : in signed(8 downto 0);
p1 : in signed(8 downto 0);
p2 : in signed(8 downto 0);
p3 : in signed(8 downto 0);
q0 : in signed(8 downto 0);
q1 : in signed(8 downto 0);
q2 : in signed(8 downto 0);
q3 : in signed(8 downto 0);
alpha : in signed(8 downto 0);
beta : in signed(8 downto 0);
tc0 : in signed(8 downto 0);
p0_out : out signed(8 downto 0);
p1_out : out signed(8 downto 0);
p2_out : out signed(8 downto 0);
q0_out : out signed(8 downto 0);
q1_out : out signed(8 downto 0);
q2_out : out signed(8 downto 0)
);
end component h264_deblock_filter_core;
component priority_encoder is
generic(
encoded_word_size : integer := 2
);
Port(
input : in std_logic_vector(2**encoded_word_size-1 downto 0);
output : out std_logic_vector(encoded_word_size-1 downto 0)
);
end component priority_encoder;
--signals
signal is_chroma : std_logic;
signal boundary_strength : std_logic_vector(8 downto 0);
signal p0 : std_logic_vector(8 downto 0);
signal p1 : std_logic_vector(8 downto 0);
signal p2 : std_logic_vector(8 downto 0);
signal p3 : std_logic_vector(8 downto 0);
signal q0 : std_logic_vector(8 downto 0);
signal q1 : std_logic_vector(8 downto 0);
signal q2 : std_logic_vector(8 downto 0);
signal q3 : std_logic_vector(8 downto 0);
signal alpha : std_logic_vector(8 downto 0);
signal beta : std_logic_vector(8 downto 0);
signal tc0 : std_logic_vector(8 downto 0);
signal bS : std_logic_vector(8 downto 0);
signal p0_out : signed(8 downto 0);
signal p1_out : signed(8 downto 0);
signal p2_out : signed(8 downto 0);
signal q0_out : signed(8 downto 0);
signal q1_out : signed(8 downto 0);
signal q2_out : signed(8 downto 0);
signal p0_out_vector : std_logic_vector(8 downto 0);
signal p1_out_vector : std_logic_vector(8 downto 0);
signal p2_out_vector : std_logic_vector(8 downto 0);
signal q0_out_vector : std_logic_vector(8 downto 0);
signal q1_out_vector : std_logic_vector(8 downto 0);
signal q2_out_vector : std_logic_vector(8 downto 0);
signal identifier : std_logic_vector(7 downto 0);
signal selected_vc_enc : std_logic_vector(vc_sel_width-1 downto 0);
signal selected_vc_q : std_logic_vector(vc_sel_width-1 downto 0);
signal selected_vc_d : std_logic_vector(vc_sel_width-1 downto 0);
signal selected_vc_one_hot : std_logic_vector(num_vc-1 downto 0);
signal has_rxd_q, has_rxd_d : std_logic;
signal recv_packet_q : std_logic_vector(127 downto 0);
signal recv_packet_d : std_logic_vector(127 downto 0);
signal send_data_0 : std_logic_vector(63 downto 0);
signal send_data_1 : std_logic_vector(63 downto 0);
--constants
constant p_index : integer := 96;
constant q_index : integer := 64;
constant param_index : integer := 32;
constant sys_param_index : integer := 0;
--states
type db_filter_states is (idle, select_vc, rx_0, rx_1, wait_rx_0, tx_0, tx_1, dequeue_0, dequeue_1, wait_tx_0, wait_tx_1);
signal next_state, current_state : db_filter_states;
begin
---------------------------------------------------------------------------
-- DATAPATH
---------------------------------------------------------------------------
process(clk, rst)
begin
if rst = '1' then
recv_packet_q <= (others => '0');
selected_vc_q <= (others => '0');
elsif rising_edge(clk) then
recv_packet_q <= recv_packet_d;
selected_vc_q <= selected_vc_d;
end if;
end process;
recv_packet_d(63 downto 0) <= recv_data when current_state = rx_0 else recv_packet_q(63 downto 0);
recv_packet_d(127 downto 64) <= recv_data when current_state = rx_1 else recv_packet_q(127 downto 64);
selected_vc_d <= selected_vc_enc when current_state = select_vc else selected_vc_q;
selected_vc_one_hot <= "01" when selected_vc_q = "0" else "10";
--parse input
p3( 7 downto 0 ) <= (recv_packet_q( p_index + 31 downto p_index + 24));
p2( 7 downto 0 ) <= (recv_packet_q( p_index + 23 downto p_index + 16));
p1( 7 downto 0 ) <= (recv_packet_q( p_index + 15 downto p_index + 8));
p0( 7 downto 0 ) <= (recv_packet_q( p_index + 7 downto p_index + 0));
q3( 7 downto 0 ) <= (recv_packet_q( q_index + 31 downto q_index + 24));
q2( 7 downto 0 ) <= (recv_packet_q( q_index + 23 downto q_index + 16));
q1( 7 downto 0 ) <= (recv_packet_q( q_index + 15 downto q_index + 8));
q0( 7 downto 0 ) <= (recv_packet_q( q_index + 7 downto q_index + 0));
alpha( 7 downto 0 ) <= (recv_packet_q( param_index + 31 downto param_index + 24));
beta( 7 downto 0 ) <= (recv_packet_q( param_index + 23 downto param_index + 16));
bS( 7 downto 0 ) <= (recv_packet_q( param_index + 15 downto param_index + 8 ));
tc0( 7 downto 0 ) <= (recv_packet_q( param_index + 7 downto param_index + 0 ));
p3( 8 ) <= '0';
p2( 8 ) <= '0';
p1( 8 ) <= '0';
p0( 8 ) <= '0';
q3( 8 ) <= '0';
q2( 8 ) <= '0';
q1( 8 ) <= '0';
q0( 8 ) <= '0';
alpha( 8 ) <= '0';
beta( 8 ) <= '0';
bS( 8 ) <= '0';
tc0( 8 ) <= '0';
is_chroma <= recv_packet_q( sys_param_index + 16 );
identifier <= recv_packet_q( sys_param_index + 15 downto sys_param_index + 8 );
--form response
p0_out_vector <= std_logic_vector(p0_out);
p1_out_vector <= std_logic_vector(p1_out);
p2_out_vector <= std_logic_vector(p2_out);
q0_out_vector <= std_logic_vector(q0_out);
q1_out_vector <= std_logic_vector(q1_out);
q2_out_vector <= std_logic_vector(q2_out);
send_data_1 <= p3(7 downto 0) &
p2_out_vector(7 downto 0) &
p1_out_vector(7 downto 0) &
p0_out_vector(7 downto 0) &
q3(7 downto 0) &
q2_out_vector(7 downto 0) &
q1_out_vector(7 downto 0) &
q0_out_vector(7 downto 0);
send_data_0 <= X"00000000" &
x"000000" &
identifier;
send_data <= send_data_0 when current_state = wait_tx_0 or current_state = dequeue_1 or current_state = tx_0 else
send_data_1;
--network controls
dest_addr <= std_logic_vector(to_unsigned(7, addr_width));
select_vc_read <= selected_vc_q;
set_tail_flit <= '1' when current_state = wait_tx_1 or current_state = tx_1 else '0';
send_flit <= '1' when current_state = tx_0 or current_state = tx_1 else '0';
dequeue <= selected_vc_one_hot when current_state = dequeue_0 or current_state = dequeue_1 else "00";
-- filter core
u0: component h264_deblock_filter_core port map(
clk => '0',
rst => '0',
is_chroma => is_chroma,
boundary_strength => signed( bs ),
p0 => signed( p0 ),
p1 => signed( p1 ),
p2 => signed( p2 ),
p3 => signed( p3 ),
q0 => signed( q0 ),
q1 => signed( q1 ),
q2 => signed( q2 ),
q3 => signed( q3 ),
alpha => signed( alpha ),
beta => signed( beta ),
tc0 => signed( tc0 ),
p0_out => p0_out,
p1_out => p1_out,
p2_out => p2_out,
q0_out => q0_out,
q1_out => q1_out,
q2_out => q2_out
);
-- select which bufer to read from
u1: priority_encoder generic map(vc_sel_width)
port map(data_in_buffer, selected_vc_enc);
---------------------------------------------------------------------------
-- STATE MACHINE
---------------------------------------------------------------------------
--state register
process(clk, rst) begin
if rst = '1' then
current_state <= idle;
elsif rising_edge(clk) then
current_state <= next_state;
end if;
end process;
--update logic
process(current_state, data_in_buffer, ready_to_send) begin
--default
next_state <= current_state;
if current_state = idle and or_reduce(data_in_buffer) = '1' then
next_state <= select_vc;
end if;
if current_state = select_vc then
next_state <= rx_0;
end if;
if current_state = rx_0 then
next_state <= dequeue_0;
end if;
if current_state = dequeue_0 then
next_state <= wait_rx_0;
end if;
if current_state = wait_rx_0 and or_reduce(data_in_buffer and selected_vc_one_hot) = '1' then
next_state <= rx_1;
end if;
if current_state = rx_1 then
next_state <= dequeue_1;
end if;
if current_state = dequeue_1 then
next_state <= wait_tx_0;
end if;
if current_state = wait_tx_0 and ready_to_send = '1' then
next_state <= tx_0;
end if;
if current_state = tx_0 then
next_state <= wait_tx_1;
end if;
if current_state = wait_tx_1 and ready_to_send = '1' then
next_state <= tx_1;
end if;
if current_state = tx_1 then
next_state <= idle;
end if;
end process;
---------------------------------------------------------------------------
-- rx tester
---------------------------------------------------------------------------
--process(clk, rst) begin
-- if rst = '1' then
-- has_rxd_q <= '0';
-- elsif rising_edge(clk) then
-- has_rxd_q <= has_rxd_d;
-- end if;
--end process;
--has_rxd_d <= has_rxd_q or or_reduce(data_in_buffer);
----has_rxd <= or_reduce(data_in_buffer);--has_rxd_d;
----
----is_idle <= '1' when current_state = idle else '0';
----is_filtering <= '1' when current_state = filter else '0';
----is_tx_ing <= '1' when current_state = transmit else '0';
----is_cleanup_ing <= '1' when current_state = cleanup else '0';
----
----rx_non_zero <= or_reduce(recv_data);
----tx_non_zero <= or_reduce(
---- p3(7 downto 0) &
---- p2_out_vector(7 downto 0) &
---- p1_out_vector(7 downto 0) &
---- p0_out_vector(7 downto 0) &
---- q3(7 downto 0) &
---- q2_out_vector(7 downto 0) &
---- q1_out_vector(7 downto 0) &
---- q0_out_vector(7 downto 0) &
---- X"00000000" &
---- x"000000" &
---- identifier );
----
end architecture fsmd;
| mit | 35515127972ac9a10c6618f0f1c96c17 | 0.451642 | 3.68629 | false | false | false | false |
boztalay/OldProjects | FPGA/Current Projects/Components/Clock_Gen.vhd | 1 | 1,431 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 01:50:30 10/15/2009
-- Design Name:
-- Module Name: Clock_Gen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: A clock generator, built for dividing the 50 MHz board clock
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Clock_Gen is
Port ( Board_Clock : in STD_LOGIC;
Sys_Clock : out STD_LOGIC);
end Clock_Gen;
architecture Behavioral of Clock_Gen is
begin
main: process(Board_Clock) is
constant hertz : integer := 100000;
constant cycles : integer := (25_000_000/hertz);
variable count : integer := 0;
variable output : STD_LOGIC := '0';
begin
if rising_edge(Board_Clock) then
count := count + 1;
if count > cycles then
count := 0;
output := not output;
end if;
end if;
Sys_Clock <= output;
end process main;
end Behavioral;
| mit | f398bf5817bd7fb71cda150e0c3c9913 | 0.566737 | 3.678663 | false | false | false | false |
bargei/NoC264 | NoC264_3x3/NoC_264.vhd | 1 | 98,520 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
ENTITY NoC_264 IS
port (
SLIDE_SW : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
BUTTON, M1_DDR2_oct_rdn, M1_DDR2_oct_rup : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
OSC_50_BANK3 : IN STD_LOGIC;
LED : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M1_DDR2_addr : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
M1_DDR2_ba : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
M1_DDR2_cas_n, M1_DDR2_ras_n, M1_DDR2_we_n : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
M1_DDR2_clk, M1_DDR2_clk_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M1_DDR2_cke, M1_DDR2_cs_n, M1_DDR2_odt : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M1_DDR2_dm : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
M1_DDR2_dq : INOUT STD_LOGIC_VECTOR (63 DOWNTO 0);
M1_DDR2_dqs, M1_DDR2_dqsn : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
M2_DDR2_addr : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
M2_DDR2_ba : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
M2_DDR2_cas_n, M2_DDR2_ras_n, M2_DDR2_we_n : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
M2_DDR2_clk, M2_DDR2_clk_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M2_DDR2_cke, M2_DDR2_cs_n, M2_DDR2_odt : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M2_DDR2_dm : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
M2_DDR2_dq : INOUT STD_LOGIC_VECTOR (63 DOWNTO 0);
M2_DDR2_dqs, M2_DDR2_dqsn : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
M2_DDR2_oct_rdn, M2_DDR2_oct_rup : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
sd_card_b_SD_cmd : inout std_logic := '0'; -- sd_card.b_SD_cmd
sd_card_b_SD_dat : inout std_logic := '0'; -- .b_SD_dat
sd_card_b_SD_dat3 : inout std_logic := '0'; -- .b_SD_dat3
sd_card_o_SD_clock : out std_logic;
gpio : out std_logic_vector(35 downto 0)
);
END NoC_264;
ARCHITECTURE MAIN OF NoC_264 IS
-- constants
constant data_width : integer := 64;
constant addr_width : integer := 4;
constant vc_sel_width : integer := 1;
constant num_vc : integer := 2;
constant flit_buff_depth : integer := 8;
COMPONENT nios_system
port (
clk_clk : in std_logic := '0'; -- clk.clk
cpu_0_noc_ctrl_export : out std_logic_vector(31 downto 0); -- cpu_0_noc_ctrl.export
cpu_0_noc_sts_export : in std_logic_vector(31 downto 0) := (others => '0'); -- cpu_0_noc_sts.export
cpu_0_rx_0_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- cpu_0_rx_0_external_connection.export
cpu_0_rx_1_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- cpu_0_rx_1_external_connection.export
cpu_0_rx_2_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- cpu_0_rx_2_external_connection.export
cpu_0_rx_3_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- cpu_0_rx_3_external_connection.export
cpu_0_rx_4_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- cpu_0_rx_4_external_connection.export
cpu_0_rx_5_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- cpu_0_rx_5_external_connection.export
cpu_0_rx_6_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- cpu_0_rx_6_external_connection.export
cpu_0_rx_7_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- cpu_0_rx_7_external_connection.export
cpu_0_tx_0_external_connection_export : out std_logic_vector(31 downto 0); -- cpu_0_tx_0_external_connection.export
cpu_0_tx_1_external_connection_export : out std_logic_vector(31 downto 0); -- cpu_0_tx_1_external_connection.export
cpu_0_tx_2_external_connection_export : out std_logic_vector(31 downto 0); -- cpu_0_tx_2_external_connection.export
cpu_0_tx_3_external_connection_export : out std_logic_vector(31 downto 0); -- cpu_0_tx_3_external_connection.export
cpu_0_tx_4_external_connection_export : out std_logic_vector(31 downto 0); -- cpu_0_tx_4_external_connection.export
cpu_0_tx_5_external_connection_export : out std_logic_vector(31 downto 0); -- cpu_0_tx_5_external_connection.export
cpu_0_tx_6_external_connection_export : out std_logic_vector(31 downto 0); -- cpu_0_tx_6_external_connection.export
cpu_0_tx_7_external_connection_export : out std_logic_vector(31 downto 0); -- cpu_0_tx_7_external_connection.export
cpu_1_noc_ctrl_export : out std_logic_vector(31 downto 0); -- cpu_1_noc_ctrl.export
cpu_1_noc_sts_export : in std_logic_vector(31 downto 0) := (others => '0'); -- cpu_1_noc_sts.export
cpu_1_rx_0_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- cpu_1_rx_0_external_connection.export
cpu_1_rx_1_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- cpu_1_rx_1_external_connection.export
cpu_1_rx_2_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- cpu_1_rx_2_external_connection.export
cpu_1_rx_3_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- cpu_1_rx_3_external_connection.export
cpu_1_rx_4_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- cpu_1_rx_4_external_connection.export
cpu_1_rx_5_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- cpu_1_rx_5_external_connection.export
cpu_1_rx_6_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- cpu_1_rx_6_external_connection.export
cpu_1_rx_7_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- cpu_1_rx_7_external_connection.export
cpu_1_tx_0_external_connection_export : out std_logic_vector(31 downto 0); -- cpu_1_tx_0_external_connection.export
cpu_1_tx_1_external_connection_export : out std_logic_vector(31 downto 0); -- cpu_1_tx_1_external_connection.export
cpu_1_tx_2_external_connection_export : out std_logic_vector(31 downto 0); -- cpu_1_tx_2_external_connection.export
cpu_1_tx_3_external_connection_export : out std_logic_vector(31 downto 0); -- cpu_1_tx_3_external_connection.export
cpu_1_tx_4_external_connection_export : out std_logic_vector(31 downto 0); -- cpu_1_tx_4_external_connection.export
cpu_1_tx_5_external_connection_export : out std_logic_vector(31 downto 0); -- cpu_1_tx_5_external_connection.export
cpu_1_tx_6_external_connection_export : out std_logic_vector(31 downto 0); -- cpu_1_tx_6_external_connection.export
cpu_1_tx_7_external_connection_export : out std_logic_vector(31 downto 0); -- cpu_1_tx_7_external_connection.export
leds_export : out std_logic_vector(7 downto 0); -- leds.export
memory_mem_a : out std_logic_vector(13 downto 0); -- memory.mem_a
memory_mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba
memory_mem_ck : out std_logic_vector(1 downto 0); -- .mem_ck
memory_mem_ck_n : out std_logic_vector(1 downto 0); -- .mem_ck_n
memory_mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
memory_mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
memory_mem_dm : out std_logic_vector(7 downto 0); -- .mem_dm
memory_mem_ras_n : out std_logic_vector(0 downto 0); -- .mem_ras_n
memory_mem_cas_n : out std_logic_vector(0 downto 0); -- .mem_cas_n
memory_mem_we_n : out std_logic_vector(0 downto 0); -- .mem_we_n
memory_mem_dq : inout std_logic_vector(63 downto 0) := (others => '0'); -- .mem_dq
memory_mem_dqs : inout std_logic_vector(7 downto 0) := (others => '0'); -- .mem_dqs
memory_mem_dqs_n : inout std_logic_vector(7 downto 0) := (others => '0'); -- .mem_dqs_n
memory_mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
memory_0_mem_a : out std_logic_vector(13 downto 0); -- memory_0.mem_a
memory_0_mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba
memory_0_mem_ck : out std_logic_vector(1 downto 0); -- .mem_ck
memory_0_mem_ck_n : out std_logic_vector(1 downto 0); -- .mem_ck_n
memory_0_mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
memory_0_mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
memory_0_mem_dm : out std_logic_vector(7 downto 0); -- .mem_dm
memory_0_mem_ras_n : out std_logic_vector(0 downto 0); -- .mem_ras_n
memory_0_mem_cas_n : out std_logic_vector(0 downto 0); -- .mem_cas_n
memory_0_mem_we_n : out std_logic_vector(0 downto 0); -- .mem_we_n
memory_0_mem_dq : inout std_logic_vector(63 downto 0) := (others => '0'); -- .mem_dq
memory_0_mem_dqs : inout std_logic_vector(7 downto 0) := (others => '0'); -- .mem_dqs
memory_0_mem_dqs_n : inout std_logic_vector(7 downto 0) := (others => '0'); -- .mem_dqs_n
memory_0_mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
oct_rdn : in std_logic := '0'; -- oct.rdn
oct_rup : in std_logic := '0'; -- .rup
oct_0_rdn : in std_logic := '0'; -- oct_0.rdn
oct_0_rup : in std_logic := '0'; -- .rup
pll_clock_clk : out std_logic; -- pll_clock.clk
sd_card_b_SD_cmd : inout std_logic := '0'; -- sd_card.b_SD_cmd
sd_card_b_SD_dat : inout std_logic := '0'; -- .b_SD_dat
sd_card_b_SD_dat3 : inout std_logic := '0'; -- .b_SD_dat3
sd_card_o_SD_clock : out std_logic; -- .o_SD_clock
switches_export : in std_logic_vector(7 downto 0) := (others => '0'); -- switches.export
vga_clock_clk : out std_logic -- vga_clock.clk
);
end component;
component intra_prediction_node is
generic (
data_width : integer := 128;
addr_width : integer := 1;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
-- recv interface to network
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
-- send interface to network
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic;
--debugging
s_intra_idle : out std_logic;
s_intra_data_rxd : out std_logic;
s_intra_write_sample : out std_logic;
s_intra_start_pred : out std_logic;
s_intra_start_tx_loop : out std_logic;
s_intra_start_tx_loop_hold : out std_logic;
s_intra_tx : out std_logic;
s_intra_tx_hold : out std_logic;
s_intra_tx_gen_next : out std_logic;
s_intra_dequeue_rx : out std_logic
);
end component intra_prediction_node;
component noc_interface is
generic(
data_width : integer := 64;
addr_width : integer := 1;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8;
use_vc : integer := 0
);
port(
--clk, reset
clk : in std_logic;
rst : in std_logic;
--user sending interface
send_data : in std_logic_vector(data_width-1 downto 0);
dest_addr : in std_logic_vector(addr_width-1 downto 0);
set_tail_flit : in std_logic;
send_flit : in std_logic;
ready_to_send : out std_logic;
--user receiving interface
recv_data : out std_logic_vector(data_width-1 downto 0);
src_addr : out std_logic_vector(addr_width-1 downto 0);
is_tail_flit : out std_logic;
data_in_buffer : out std_logic_vector(num_vc-1 downto 0);
dequeue : in std_logic_vector(num_vc-1 downto 0);
select_vc_read : in std_logic_vector(vc_sel_width-1 downto 0);
--interface to network
send_putFlit_flit_in : out std_logic_vector(data_width+addr_width+vc_sel_width+1 downto 0);
EN_send_putFlit : out std_logic;
EN_send_getNonFullVCs : out std_logic;
send_getNonFullVCs : in std_logic_vector(num_vc-1 downto 0);
EN_recv_getFlit : out std_logic;
recv_getFlit : in std_logic_vector(data_width+addr_width+vc_sel_width+1 downto 0);
recv_putNonFullVCs_nonFullVCs : out std_logic_vector(num_vc-1 downto 0);
EN_recv_putNonFullVCs : out std_logic;
recv_info_getRecvPortID : in std_logic_vector(addr_width-1 downto 0)
);
end component noc_interface;
component mkNetworkSimple is
port(
CLK : in std_logic;
RST_N : in std_logic;
send_ports_0_putFlit_flit_in : in std_logic_vector(70 downto 0);
EN_send_ports_0_putFlit : in std_logic;
EN_send_ports_0_getNonFullVCs : in std_logic;
send_ports_0_getNonFullVCs : out std_logic_vector(1 downto 0);
send_ports_1_putFlit_flit_in : in std_logic_vector(70 downto 0);
EN_send_ports_1_putFlit : in std_logic;
EN_send_ports_1_getNonFullVCs : in std_logic;
send_ports_1_getNonFullVCs : out std_logic_vector(1 downto 0);
send_ports_2_putFlit_flit_in : in std_logic_vector(70 downto 0);
EN_send_ports_2_putFlit : in std_logic;
EN_send_ports_2_getNonFullVCs : in std_logic;
send_ports_2_getNonFullVCs : out std_logic_vector(1 downto 0);
send_ports_3_putFlit_flit_in : in std_logic_vector(70 downto 0);
EN_send_ports_3_putFlit : in std_logic;
EN_send_ports_3_getNonFullVCs : in std_logic;
send_ports_3_getNonFullVCs : out std_logic_vector(1 downto 0);
send_ports_4_putFlit_flit_in : in std_logic_vector(70 downto 0);
EN_send_ports_4_putFlit : in std_logic;
EN_send_ports_4_getNonFullVCs : in std_logic;
send_ports_4_getNonFullVCs : out std_logic_vector(1 downto 0);
send_ports_5_putFlit_flit_in : in std_logic_vector(70 downto 0);
EN_send_ports_5_putFlit : in std_logic;
EN_send_ports_5_getNonFullVCs : in std_logic;
send_ports_5_getNonFullVCs : out std_logic_vector(1 downto 0);
send_ports_6_putFlit_flit_in : in std_logic_vector(70 downto 0);
EN_send_ports_6_putFlit : in std_logic;
EN_send_ports_6_getNonFullVCs : in std_logic;
send_ports_6_getNonFullVCs : out std_logic_vector(1 downto 0);
send_ports_7_putFlit_flit_in : in std_logic_vector(70 downto 0);
EN_send_ports_7_putFlit : in std_logic;
EN_send_ports_7_getNonFullVCs : in std_logic;
send_ports_7_getNonFullVCs : out std_logic_vector(1 downto 0);
send_ports_8_putFlit_flit_in : in std_logic_vector(70 downto 0);
EN_send_ports_8_putFlit : in std_logic;
EN_send_ports_8_getNonFullVCs : in std_logic;
send_ports_8_getNonFullVCs : out std_logic_vector(1 downto 0);
EN_recv_ports_0_getFlit : in std_logic;
recv_ports_0_getFlit : out std_logic_vector(70 downto 0);
recv_ports_0_putNonFullVCs_nonFullVCs : in std_logic_vector(1 downto 0);
EN_recv_ports_0_putNonFullVCs : in std_logic;
EN_recv_ports_1_getFlit : in std_logic;
recv_ports_1_getFlit : out std_logic_vector(70 downto 0);
recv_ports_1_putNonFullVCs_nonFullVCs : in std_logic_vector(1 downto 0);
EN_recv_ports_1_putNonFullVCs : in std_logic;
EN_recv_ports_2_getFlit : in std_logic;
recv_ports_2_getFlit : out std_logic_vector(70 downto 0);
recv_ports_2_putNonFullVCs_nonFullVCs : in std_logic_vector(1 downto 0);
EN_recv_ports_2_putNonFullVCs : in std_logic;
EN_recv_ports_3_getFlit : in std_logic;
recv_ports_3_getFlit : out std_logic_vector(70 downto 0);
recv_ports_3_putNonFullVCs_nonFullVCs : in std_logic_vector(1 downto 0);
EN_recv_ports_3_putNonFullVCs : in std_logic;
EN_recv_ports_4_getFlit : in std_logic;
recv_ports_4_getFlit : out std_logic_vector(70 downto 0);
recv_ports_4_putNonFullVCs_nonFullVCs : in std_logic_vector(1 downto 0);
EN_recv_ports_4_putNonFullVCs : in std_logic;
EN_recv_ports_5_getFlit : in std_logic;
recv_ports_5_getFlit : out std_logic_vector(70 downto 0);
recv_ports_5_putNonFullVCs_nonFullVCs : in std_logic_vector(1 downto 0);
EN_recv_ports_5_putNonFullVCs : in std_logic;
EN_recv_ports_6_getFlit : in std_logic;
recv_ports_6_getFlit : out std_logic_vector(70 downto 0);
recv_ports_6_putNonFullVCs_nonFullVCs : in std_logic_vector(1 downto 0);
EN_recv_ports_6_putNonFullVCs : in std_logic;
EN_recv_ports_7_getFlit : in std_logic;
recv_ports_7_getFlit : out std_logic_vector(70 downto 0);
recv_ports_7_putNonFullVCs_nonFullVCs : in std_logic_vector(1 downto 0);
EN_recv_ports_7_putNonFullVCs : in std_logic;
EN_recv_ports_8_getFlit : in std_logic;
recv_ports_8_getFlit : out std_logic_vector(70 downto 0);
recv_ports_8_putNonFullVCs_nonFullVCs : in std_logic_vector(1 downto 0);
EN_recv_ports_8_putNonFullVCs : in std_logic;
recv_ports_info_0_getRecvPortID : out std_logic_vector(3 downto 0);
recv_ports_info_1_getRecvPortID : out std_logic_vector(3 downto 0);
recv_ports_info_2_getRecvPortID : out std_logic_vector(3 downto 0);
recv_ports_info_3_getRecvPortID : out std_logic_vector(3 downto 0);
recv_ports_info_4_getRecvPortID : out std_logic_vector(3 downto 0);
recv_ports_info_5_getRecvPortID : out std_logic_vector(3 downto 0);
recv_ports_info_6_getRecvPortID : out std_logic_vector(3 downto 0);
recv_ports_info_7_getRecvPortID : out std_logic_vector(3 downto 0);
recv_ports_info_8_getRecvPortID : out std_logic_vector(3 downto 0)
);
end component mkNetworkSimple;
component deblocking_filter_node is
generic (
data_width : integer := 64;
addr_width : integer := 1;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
-- recv interface to network
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
-- send interface to network
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic;
has_rxd : out std_logic;
is_idle : out std_logic;
is_filtering : out std_logic;
is_tx_ing : out std_logic;
is_cleanup_ing : out std_logic;
rx_non_zero : out std_logic;
tx_non_zero : out std_logic
);
end component deblocking_filter_node;
component noc_control_plus is
generic(
data_width : integer := 128;
addr_width : integer := 2;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
-- recv interface to network
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
-- send interface to network
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic;
--send interface to CPU
set_tail_cpu : in std_logic;
addr_cpu : in std_logic_vector(addr_width-1 downto 0);
tx_0 : in std_logic_vector(31 downto 0);
tx_1 : in std_logic_vector(31 downto 0);
tx_2 : in std_logic_vector(31 downto 0);
tx_3 : in std_logic_vector(31 downto 0);
tx_4 : in std_logic_vector(31 downto 0);
tx_5 : in std_logic_vector(31 downto 0);
tx_6 : in std_logic_vector(31 downto 0);
tx_7 : in std_logic_vector(31 downto 0);
format_select : in std_logic_vector(7 downto 0);
send_cmd_cpu : in std_logic;
send_ack : out std_logic;
--receive interface to cpu
rx_0 : out std_logic_vector(31 downto 0);
rx_1 : out std_logic_vector(31 downto 0);
rx_2 : out std_logic_vector(31 downto 0);
rx_3 : out std_logic_vector(31 downto 0);
rx_4 : out std_logic_vector(31 downto 0);
rx_5 : out std_logic_vector(31 downto 0);
rx_6 : out std_logic_vector(31 downto 0);
rx_7 : out std_logic_vector(31 downto 0);
parse_select : in std_logic_vector(7 downto 0);
cpu_rx_ctrl : in std_logic;
rx_state_out : out std_logic_vector(7 downto 0)
);
end component noc_control_plus;
component inter_node is
generic(
size_x : integer := 12; --20 ; --12; --20 --20
size_y : integer := 12; --20 ; --12; --20 --20
interp_x : integer := 8; --4 ; --8; --2 --4
interp_y : integer := 2; --4 ; --1; --2 --4
sample_size : integer := 8; --8 ; --8;
samples_per_wr : integer := 16; --16 ; --8; --4 --16
data_width : integer := 128;--128 ; --64; --32 --128
addr_width : integer := 1; --1 ; --1;
vc_sel_width : integer := 1; --1 ; --1;
num_vc : integer := 2; --2 ; --2;
flit_buff_depth : integer := 8 --8 --8
);
port(
clk : in std_logic;
rst : in std_logic;
-- recv interface to network
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
-- send interface to network
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic
);
end component inter_node;
component chroma_motion is
generic(
data_width : integer := 64;
addr_width : integer := 4;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
-- recv interface to network
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
-- send interface to network
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic
);
end component chroma_motion;
component iqit_node is
generic(
sample_width : integer := 8;
qp_width : integer := 8;
wo_dc_width : integer := 8;
data_width : integer := 64;
addr_width : integer := 1;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
-- recv interface to network
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
-- send interface to network
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic
);
end component iqit_node;
component vga_node is
generic(
data_width : integer := 64;
addr_width : integer := 4;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
-- recv interface to network
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
-- send interface to network
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic;
-- vga connections
clk27 : in std_logic;
rst27 : in std_logic;
vga_red : out std_logic_vector(5 downto 0);
vga_blue : out std_logic_vector(5 downto 0);
vga_green : out std_logic_vector(5 downto 0);
vga_v_sync : out std_logic;
vga_h_sync : out std_logic
);
end component vga_node;
signal cpu_0_noc_ctrl_export : std_logic_vector(31 downto 0);
signal cpu_0_noc_sts_export : std_logic_vector(31 downto 0);
signal cpu_0_rx_high_export : std_logic_vector(31 downto 0);
signal cpu_0_rx_low_export : std_logic_vector(31 downto 0);
signal cpu_0_tx_high_export : std_logic_vector(31 downto 0);
signal cpu_0_tx_low_export : std_logic_vector(31 downto 0);
signal cpu_1_noc_ctrl_export : std_logic_vector(31 downto 0);
signal cpu_1_noc_sts_export : std_logic_vector(31 downto 0);
signal cpu_1_rx_high_export : std_logic_vector(31 downto 0);
signal cpu_1_rx_low_export : std_logic_vector(31 downto 0);
signal cpu_1_tx_high_export : std_logic_vector(31 downto 0);
signal cpu_1_tx_low_export : std_logic_vector(31 downto 0);
signal vga_clock_clk : std_logic;
signal cpu_0_rx_0_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_0_rx_1_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_0_rx_2_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_0_rx_3_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_0_rx_4_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_0_rx_5_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_0_rx_6_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_0_rx_7_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_0_tx_0_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_0_tx_1_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_0_tx_2_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_0_tx_3_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_0_tx_4_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_0_tx_5_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_0_tx_6_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_0_tx_7_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_1_rx_0_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_1_rx_1_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_1_rx_2_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_1_rx_3_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_1_rx_4_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_1_rx_5_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_1_rx_6_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_1_rx_7_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_1_tx_0_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_1_tx_1_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_1_tx_2_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_1_tx_3_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_1_tx_4_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_1_tx_5_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_1_tx_6_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_1_tx_7_external_connection_export : std_logic_vector(31 downto 0);
signal clock_50 : std_logic;
signal vga_clock : std_logic;
signal hps_h2f_rst : std_logic;
signal send_ports_0_putFlit_flit_in : std_logic_vector(70 downto 0);
signal EN_send_ports_0_putFlit : std_logic;
signal EN_send_ports_0_getNonFullVCs : std_logic;
signal send_ports_0_getNonFullVCs : std_logic_vector(1 downto 0);
signal send_ports_1_putFlit_flit_in : std_logic_vector(70 downto 0);
signal EN_send_ports_1_putFlit : std_logic;
signal EN_send_ports_1_getNonFullVCs : std_logic;
signal send_ports_1_getNonFullVCs : std_logic_vector(1 downto 0);
signal send_ports_2_putFlit_flit_in : std_logic_vector(70 downto 0);
signal EN_send_ports_2_putFlit : std_logic;
signal EN_send_ports_2_getNonFullVCs : std_logic;
signal send_ports_2_getNonFullVCs : std_logic_vector(1 downto 0);
signal send_ports_3_putFlit_flit_in : std_logic_vector(70 downto 0);
signal EN_send_ports_3_putFlit : std_logic;
signal EN_send_ports_3_getNonFullVCs : std_logic;
signal send_ports_3_getNonFullVCs : std_logic_vector(1 downto 0);
signal send_ports_4_putFlit_flit_in : std_logic_vector(70 downto 0);
signal EN_send_ports_4_putFlit : std_logic;
signal EN_send_ports_4_getNonFullVCs : std_logic;
signal send_ports_4_getNonFullVCs : std_logic_vector(1 downto 0);
signal send_ports_5_putFlit_flit_in : std_logic_vector(70 downto 0);
signal EN_send_ports_5_putFlit : std_logic;
signal EN_send_ports_5_getNonFullVCs : std_logic;
signal send_ports_5_getNonFullVCs : std_logic_vector(1 downto 0);
signal send_ports_6_putFlit_flit_in : std_logic_vector(70 downto 0);
signal EN_send_ports_6_putFlit : std_logic;
signal EN_send_ports_6_getNonFullVCs : std_logic;
signal send_ports_6_getNonFullVCs : std_logic_vector(1 downto 0);
signal send_ports_7_putFlit_flit_in : std_logic_vector(70 downto 0);
signal EN_send_ports_7_putFlit : std_logic;
signal EN_send_ports_7_getNonFullVCs : std_logic;
signal send_ports_7_getNonFullVCs : std_logic_vector(1 downto 0);
signal send_ports_8_putFlit_flit_in : std_logic_vector(70 downto 0);
signal EN_send_ports_8_putFlit : std_logic;
signal EN_send_ports_8_getNonFullVCs : std_logic;
signal send_ports_8_getNonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_0_getFlit : std_logic;
signal recv_ports_0_getFlit : std_logic_vector(70 downto 0);
signal recv_ports_0_putNonFullVCs_nonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_0_putNonFullVCs : std_logic;
signal EN_recv_ports_1_getFlit : std_logic;
signal recv_ports_1_getFlit : std_logic_vector(70 downto 0);
signal recv_ports_1_putNonFullVCs_nonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_1_putNonFullVCs : std_logic;
signal EN_recv_ports_2_getFlit : std_logic;
signal recv_ports_2_getFlit : std_logic_vector(70 downto 0);
signal recv_ports_2_putNonFullVCs_nonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_2_putNonFullVCs : std_logic;
signal EN_recv_ports_3_getFlit : std_logic;
signal recv_ports_3_getFlit : std_logic_vector(70 downto 0);
signal recv_ports_3_putNonFullVCs_nonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_3_putNonFullVCs : std_logic;
signal EN_recv_ports_4_getFlit : std_logic;
signal recv_ports_4_getFlit : std_logic_vector(70 downto 0);
signal recv_ports_4_putNonFullVCs_nonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_4_putNonFullVCs : std_logic;
signal EN_recv_ports_5_getFlit : std_logic;
signal recv_ports_5_getFlit : std_logic_vector(70 downto 0);
signal recv_ports_5_putNonFullVCs_nonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_5_putNonFullVCs : std_logic;
signal EN_recv_ports_6_getFlit : std_logic;
signal recv_ports_6_getFlit : std_logic_vector(70 downto 0);
signal recv_ports_6_putNonFullVCs_nonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_6_putNonFullVCs : std_logic;
signal EN_recv_ports_7_getFlit : std_logic;
signal recv_ports_7_getFlit : std_logic_vector(70 downto 0);
signal recv_ports_7_putNonFullVCs_nonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_7_putNonFullVCs : std_logic;
signal EN_recv_ports_8_getFlit : std_logic;
signal recv_ports_8_getFlit : std_logic_vector(70 downto 0);
signal recv_ports_8_putNonFullVCs_nonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_8_putNonFullVCs : std_logic;
signal recv_ports_info_0_getRecvPortID : std_logic_vector(3 downto 0);
signal recv_ports_info_1_getRecvPortID : std_logic_vector(3 downto 0);
signal recv_ports_info_2_getRecvPortID : std_logic_vector(3 downto 0);
signal recv_ports_info_3_getRecvPortID : std_logic_vector(3 downto 0);
signal recv_ports_info_4_getRecvPortID : std_logic_vector(3 downto 0);
signal recv_ports_info_5_getRecvPortID : std_logic_vector(3 downto 0);
signal recv_ports_info_6_getRecvPortID : std_logic_vector(3 downto 0);
signal recv_ports_info_7_getRecvPortID : std_logic_vector(3 downto 0);
signal recv_ports_info_8_getRecvPortID : std_logic_vector(3 downto 0);
signal send_ports_9_putFlit_flit_in : std_logic_vector(70 downto 0);
signal EN_send_ports_9_putFlit : std_logic;
signal EN_send_ports_9_getNonFullVCs : std_logic;
signal send_ports_9_getNonFullVCs : std_logic_vector(1 downto 0);
signal send_ports_10_putFlit_flit_in : std_logic_vector(70 downto 0);
signal EN_send_ports_10_putFlit : std_logic;
signal EN_send_ports_10_getNonFullVCs : std_logic;
signal send_ports_10_getNonFullVCs : std_logic_vector(1 downto 0);
signal send_ports_11_putFlit_flit_in : std_logic_vector(70 downto 0);
signal EN_send_ports_11_putFlit : std_logic;
signal EN_send_ports_11_getNonFullVCs : std_logic;
signal send_ports_11_getNonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_9_getFlit : std_logic;
signal recv_ports_9_getFlit : std_logic_vector(70 downto 0);
signal recv_ports_9_putNonFullVCs_nonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_9_putNonFullVCs : std_logic;
signal EN_recv_ports_10_getFlit : std_logic;
signal recv_ports_10_getFlit : std_logic_vector(70 downto 0);
signal recv_ports_10_putNonFullVCs_nonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_10_putNonFullVCs : std_logic;
signal EN_recv_ports_11_getFlit : std_logic;
signal recv_ports_11_getFlit : std_logic_vector(70 downto 0);
signal recv_ports_11_putNonFullVCs_nonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_11_putNonFullVCs : std_logic;
signal recv_ports_info_9_getRecvPortID : std_logic_vector(3 downto 0);
signal recv_ports_info_10_getRecvPortID : std_logic_vector(3 downto 0);
signal recv_ports_info_11_getRecvPortID : std_logic_vector(3 downto 0);
signal send_data_pe0 : std_logic_vector(data_width-1 downto 0);
signal dest_addr_pe0 : std_logic_vector(addr_width-1 downto 0);
signal set_tail_flit_pe0 : std_logic;
signal send_flit_pe0 : std_logic;
signal ready_to_send_pe0 : std_logic;
signal recv_data_pe0 : std_logic_vector(data_width-1 downto 0);
signal src_addr_pe0 : std_logic_vector(addr_width-1 downto 0);
signal is_tail_flit_pe0 : std_logic;
signal data_in_buffer_pe0 : std_logic_vector(num_vc-1 downto 0);
signal dequeue_pe0 : std_logic_vector(num_vc-1 downto 0);
signal select_vc_read_pe0 : std_logic_vector(vc_sel_width-1 downto 0);
signal send_data_pe1 : std_logic_vector(data_width-1 downto 0);
signal dest_addr_pe1 : std_logic_vector(addr_width-1 downto 0);
signal set_tail_flit_pe1 : std_logic;
signal send_flit_pe1 : std_logic;
signal ready_to_send_pe1 : std_logic;
signal recv_data_pe1 : std_logic_vector(data_width-1 downto 0);
signal src_addr_pe1 : std_logic_vector(addr_width-1 downto 0);
signal is_tail_flit_pe1 : std_logic;
signal data_in_buffer_pe1 : std_logic_vector(num_vc-1 downto 0);
signal dequeue_pe1 : std_logic_vector(num_vc-1 downto 0);
signal select_vc_read_pe1 : std_logic_vector(vc_sel_width-1 downto 0);
signal send_data_pe2 : std_logic_vector(data_width-1 downto 0);
signal dest_addr_pe2 : std_logic_vector(addr_width-1 downto 0);
signal set_tail_flit_pe2 : std_logic;
signal send_flit_pe2 : std_logic;
signal ready_to_send_pe2 : std_logic;
signal recv_data_pe2 : std_logic_vector(data_width-1 downto 0);
signal src_addr_pe2 : std_logic_vector(addr_width-1 downto 0);
signal is_tail_flit_pe2 : std_logic;
signal data_in_buffer_pe2 : std_logic_vector(num_vc-1 downto 0);
signal dequeue_pe2 : std_logic_vector(num_vc-1 downto 0);
signal select_vc_read_pe2 : std_logic_vector(vc_sel_width-1 downto 0);
signal send_data_pe3 : std_logic_vector(data_width-1 downto 0);
signal dest_addr_pe3 : std_logic_vector(addr_width-1 downto 0);
signal set_tail_flit_pe3 : std_logic;
signal send_flit_pe3 : std_logic;
signal ready_to_send_pe3 : std_logic;
signal recv_data_pe3 : std_logic_vector(data_width-1 downto 0);
signal src_addr_pe3 : std_logic_vector(addr_width-1 downto 0);
signal is_tail_flit_pe3 : std_logic;
signal data_in_buffer_pe3 : std_logic_vector(num_vc-1 downto 0);
signal dequeue_pe3 : std_logic_vector(num_vc-1 downto 0);
signal select_vc_read_pe3 : std_logic_vector(vc_sel_width-1 downto 0);
signal send_data_pe4 : std_logic_vector(data_width-1 downto 0);
signal dest_addr_pe4 : std_logic_vector(addr_width-1 downto 0);
signal set_tail_flit_pe4 : std_logic;
signal send_flit_pe4 : std_logic;
signal ready_to_send_pe4 : std_logic;
signal recv_data_pe4 : std_logic_vector(data_width-1 downto 0);
signal src_addr_pe4 : std_logic_vector(addr_width-1 downto 0);
signal is_tail_flit_pe4 : std_logic;
signal data_in_buffer_pe4 : std_logic_vector(num_vc-1 downto 0);
signal dequeue_pe4 : std_logic_vector(num_vc-1 downto 0);
signal select_vc_read_pe4 : std_logic_vector(vc_sel_width-1 downto 0);
signal send_data_pe5 : std_logic_vector(data_width-1 downto 0);
signal dest_addr_pe5 : std_logic_vector(addr_width-1 downto 0);
signal set_tail_flit_pe5 : std_logic;
signal send_flit_pe5 : std_logic;
signal ready_to_send_pe5 : std_logic;
signal recv_data_pe5 : std_logic_vector(data_width-1 downto 0);
signal src_addr_pe5 : std_logic_vector(addr_width-1 downto 0);
signal is_tail_flit_pe5 : std_logic;
signal data_in_buffer_pe5 : std_logic_vector(num_vc-1 downto 0);
signal dequeue_pe5 : std_logic_vector(num_vc-1 downto 0);
signal select_vc_read_pe5 : std_logic_vector(vc_sel_width-1 downto 0);
signal send_data_pe6 : std_logic_vector(data_width-1 downto 0);
signal dest_addr_pe6 : std_logic_vector(addr_width-1 downto 0);
signal set_tail_flit_pe6 : std_logic;
signal send_flit_pe6 : std_logic;
signal ready_to_send_pe6 : std_logic;
signal recv_data_pe6 : std_logic_vector(data_width-1 downto 0);
signal src_addr_pe6 : std_logic_vector(addr_width-1 downto 0);
signal is_tail_flit_pe6 : std_logic;
signal data_in_buffer_pe6 : std_logic_vector(num_vc-1 downto 0);
signal dequeue_pe6 : std_logic_vector(num_vc-1 downto 0);
signal select_vc_read_pe6 : std_logic_vector(vc_sel_width-1 downto 0);
signal send_data_pe7 : std_logic_vector(data_width-1 downto 0);
signal dest_addr_pe7 : std_logic_vector(addr_width-1 downto 0);
signal set_tail_flit_pe7 : std_logic;
signal send_flit_pe7 : std_logic;
signal ready_to_send_pe7 : std_logic;
signal recv_data_pe7 : std_logic_vector(data_width-1 downto 0);
signal src_addr_pe7 : std_logic_vector(addr_width-1 downto 0);
signal is_tail_flit_pe7 : std_logic;
signal data_in_buffer_pe7 : std_logic_vector(num_vc-1 downto 0);
signal dequeue_pe7 : std_logic_vector(num_vc-1 downto 0);
signal select_vc_read_pe7 : std_logic_vector(vc_sel_width-1 downto 0);
signal send_data_pe8 : std_logic_vector(data_width-1 downto 0);
signal dest_addr_pe8 : std_logic_vector(addr_width-1 downto 0);
signal set_tail_flit_pe8 : std_logic;
signal send_flit_pe8 : std_logic;
signal ready_to_send_pe8 : std_logic;
signal recv_data_pe8 : std_logic_vector(data_width-1 downto 0);
signal src_addr_pe8 : std_logic_vector(addr_width-1 downto 0);
signal is_tail_flit_pe8 : std_logic;
signal data_in_buffer_pe8 : std_logic_vector(num_vc-1 downto 0);
signal dequeue_pe8 : std_logic_vector(num_vc-1 downto 0);
signal select_vc_read_pe8 : std_logic_vector(vc_sel_width-1 downto 0);
signal send_data_pe9 : std_logic_vector(data_width-1 downto 0);
signal dest_addr_pe9 : std_logic_vector(addr_width-1 downto 0);
signal set_tail_flit_pe9 : std_logic;
signal send_flit_pe9 : std_logic;
signal ready_to_send_pe9 : std_logic;
signal recv_data_pe9 : std_logic_vector(data_width-1 downto 0);
signal src_addr_pe9 : std_logic_vector(addr_width-1 downto 0);
signal is_tail_flit_pe9 : std_logic;
signal data_in_buffer_pe9 : std_logic_vector(num_vc-1 downto 0);
signal dequeue_pe9 : std_logic_vector(num_vc-1 downto 0);
signal select_vc_read_pe9 : std_logic_vector(vc_sel_width-1 downto 0);
signal noc_rst : std_logic;
signal noc_ctrl_export : std_logic_vector(31 downto 0);
signal noc_status_export : std_logic_vector(31 downto 0);
signal LEDR_NOPE : std_logic_vector(9 downto 0);
signal is_idle : std_logic_vector(2 downto 0);
signal is_filtering : std_logic_vector(2 downto 0);
signal is_tx_ing : std_logic_vector(2 downto 0);
signal is_cleanup_ing : std_logic_vector(2 downto 0);
signal ledr : std_logic_vector(9 downto 0);
signal clk27 : std_logic;
signal rst27 : std_logic;
signal vga_red : std_logic_vector(5 downto 0);
signal vga_blue : std_logic_vector(5 downto 0);
signal vga_green : std_logic_vector(5 downto 0);
signal vga_v_sync : std_logic;
signal vga_h_sync : std_logic;
signal data_in_cpu_0 : std_logic_vector(63 downto 0);
signal data_out_cpu_0 : std_logic_vector(63 downto 0);
signal noc_ctrl_cpu_0 : std_logic_vector(31 downto 0);
signal noc_sts_cpu_0 : std_logic_vector(31 downto 0);
signal data_in_cpu_1 : std_logic_vector(63 downto 0);
signal data_out_cpu_1 : std_logic_vector(63 downto 0);
signal noc_ctrl_cpu_1 : std_logic_vector(31 downto 0);
signal noc_sts_cpu_1 : std_logic_vector(31 downto 0);
signal rx : std_logic_vector(63 downto 0);
signal pll_clock_clk : std_logic;
BEGIN
NiosII: nios_system
port MAP (
clk_clk => OSC_50_BANK3,
--reset_reset_n => BUTTON(0),
switches_export => SLIDE_SW,
leds_export => LED,
memory_mem_a => M1_DDR2_addr,
memory_mem_ba => M1_DDR2_ba,
memory_mem_ck => M1_DDR2_clk,
memory_mem_ck_n => M1_DDR2_clk_n,
memory_mem_cke => M1_DDR2_cke,
memory_mem_cs_n => M1_DDR2_cs_n,
memory_mem_dm => M1_DDR2_dm,
memory_mem_ras_n => M1_DDR2_ras_n,
memory_mem_cas_n => M1_DDR2_cas_n,
memory_mem_we_n => M1_DDR2_we_n,
memory_mem_dq => M1_DDR2_dq,
memory_mem_dqs => M1_DDR2_dqs,
memory_mem_dqs_n => M1_DDR2_dqsn,
memory_mem_odt => M1_DDR2_odt,
oct_rdn => M1_DDR2_oct_rdn(0),
oct_rup => M1_DDR2_oct_rup(0),
sd_card_b_SD_cmd => sd_card_b_SD_cmd,
sd_card_b_SD_dat => sd_card_b_SD_dat,
sd_card_b_SD_dat3 => sd_card_b_SD_dat3,
sd_card_o_SD_clock => sd_card_o_SD_clock,
memory_0_mem_a => M2_DDR2_addr,
memory_0_mem_ba => M2_DDR2_ba,
memory_0_mem_ck => M2_DDR2_clk,
memory_0_mem_ck_n => M2_DDR2_clk_n,
memory_0_mem_cke => M2_DDR2_cke,
memory_0_mem_cs_n => M2_DDR2_cs_n,
memory_0_mem_dm => M2_DDR2_dm,
memory_0_mem_ras_n => M2_DDR2_ras_n,
memory_0_mem_cas_n => M2_DDR2_cas_n,
memory_0_mem_we_n => M2_DDR2_we_n,
memory_0_mem_dq => M2_DDR2_dq,
memory_0_mem_dqs => M2_DDR2_dqs,
memory_0_mem_dqs_n => M2_DDR2_dqsn,
memory_0_mem_odt => M2_DDR2_odt,
oct_0_rdn => M2_DDR2_oct_rdn(0),
oct_0_rup => M2_DDR2_oct_rup(0),
pll_clock_clk => pll_clock_clk,
cpu_0_noc_ctrl_export => cpu_0_noc_ctrl_export,
cpu_0_noc_sts_export => cpu_0_noc_sts_export,
cpu_1_noc_ctrl_export => cpu_1_noc_ctrl_export,
cpu_1_noc_sts_export => cpu_1_noc_sts_export,
cpu_0_rx_0_external_connection_export => cpu_0_rx_0_external_connection_export,
cpu_0_rx_1_external_connection_export => cpu_0_rx_1_external_connection_export,
cpu_0_rx_2_external_connection_export => cpu_0_rx_2_external_connection_export,
cpu_0_rx_3_external_connection_export => cpu_0_rx_3_external_connection_export,
cpu_0_rx_4_external_connection_export => cpu_0_rx_4_external_connection_export,
cpu_0_rx_5_external_connection_export => cpu_0_rx_5_external_connection_export,
cpu_0_rx_6_external_connection_export => cpu_0_rx_6_external_connection_export,
cpu_0_rx_7_external_connection_export => cpu_0_rx_7_external_connection_export,
cpu_0_tx_0_external_connection_export => cpu_0_tx_0_external_connection_export,
cpu_0_tx_1_external_connection_export => cpu_0_tx_1_external_connection_export,
cpu_0_tx_2_external_connection_export => cpu_0_tx_2_external_connection_export,
cpu_0_tx_3_external_connection_export => cpu_0_tx_3_external_connection_export,
cpu_0_tx_4_external_connection_export => cpu_0_tx_4_external_connection_export,
cpu_0_tx_5_external_connection_export => cpu_0_tx_5_external_connection_export,
cpu_0_tx_6_external_connection_export => cpu_0_tx_6_external_connection_export,
cpu_0_tx_7_external_connection_export => cpu_0_tx_7_external_connection_export,
cpu_1_rx_0_external_connection_export => cpu_1_rx_0_external_connection_export,
cpu_1_rx_1_external_connection_export => cpu_1_rx_1_external_connection_export,
cpu_1_rx_2_external_connection_export => cpu_1_rx_2_external_connection_export,
cpu_1_rx_3_external_connection_export => cpu_1_rx_3_external_connection_export,
cpu_1_rx_4_external_connection_export => cpu_1_rx_4_external_connection_export,
cpu_1_rx_5_external_connection_export => cpu_1_rx_5_external_connection_export,
cpu_1_rx_6_external_connection_export => cpu_1_rx_6_external_connection_export,
cpu_1_rx_7_external_connection_export => cpu_1_rx_7_external_connection_export,
cpu_1_tx_0_external_connection_export => cpu_1_tx_0_external_connection_export,
cpu_1_tx_1_external_connection_export => cpu_1_tx_1_external_connection_export,
cpu_1_tx_2_external_connection_export => cpu_1_tx_2_external_connection_export,
cpu_1_tx_3_external_connection_export => cpu_1_tx_3_external_connection_export,
cpu_1_tx_4_external_connection_export => cpu_1_tx_4_external_connection_export,
cpu_1_tx_5_external_connection_export => cpu_1_tx_5_external_connection_export,
cpu_1_tx_6_external_connection_export => cpu_1_tx_6_external_connection_export,
cpu_1_tx_7_external_connection_export => cpu_1_tx_7_external_connection_export,
vga_clock_clk => vga_clock_clk
);
clock_50 <= OSC_50_BANK3;
vga_clock <= vga_clock_clk;
data_in_cpu_0 <= cpu_0_tx_0_external_connection_export & cpu_0_tx_1_external_connection_export;
noc_ctrl_cpu_0 <= cpu_0_noc_ctrl_export;
cpu_0_noc_sts_export <= noc_sts_cpu_0;
data_in_cpu_1 <= cpu_1_tx_0_external_connection_export & cpu_1_tx_1_external_connection_export;
noc_ctrl_cpu_1 <= cpu_1_noc_ctrl_export;
cpu_1_noc_sts_export <= noc_sts_cpu_1;
u1 : component mkNetworkSimple
port map(
CLK => CLOCK_50 ,
RST_N => not noc_rst ,
send_ports_0_putFlit_flit_in => send_ports_0_putFlit_flit_in ,
EN_send_ports_0_putFlit => EN_send_ports_0_putFlit ,
EN_send_ports_0_getNonFullVCs => EN_send_ports_0_getNonFullVCs ,
send_ports_0_getNonFullVCs => send_ports_0_getNonFullVCs ,
send_ports_1_putFlit_flit_in => send_ports_1_putFlit_flit_in ,
EN_send_ports_1_putFlit => EN_send_ports_1_putFlit ,
EN_send_ports_1_getNonFullVCs => EN_send_ports_1_getNonFullVCs ,
send_ports_1_getNonFullVCs => send_ports_1_getNonFullVCs ,
send_ports_2_putFlit_flit_in => send_ports_2_putFlit_flit_in ,
EN_send_ports_2_putFlit => EN_send_ports_2_putFlit ,
EN_send_ports_2_getNonFullVCs => EN_send_ports_2_getNonFullVCs ,
send_ports_2_getNonFullVCs => send_ports_2_getNonFullVCs ,
send_ports_3_putFlit_flit_in => send_ports_3_putFlit_flit_in ,
EN_send_ports_3_putFlit => EN_send_ports_3_putFlit ,
EN_send_ports_3_getNonFullVCs => EN_send_ports_3_getNonFullVCs ,
send_ports_3_getNonFullVCs => send_ports_3_getNonFullVCs ,
send_ports_4_putFlit_flit_in => send_ports_4_putFlit_flit_in ,
EN_send_ports_4_putFlit => EN_send_ports_4_putFlit ,
EN_send_ports_4_getNonFullVCs => EN_send_ports_4_getNonFullVCs ,
send_ports_4_getNonFullVCs => send_ports_4_getNonFullVCs ,
send_ports_5_putFlit_flit_in => send_ports_5_putFlit_flit_in ,
EN_send_ports_5_putFlit => EN_send_ports_5_putFlit ,
EN_send_ports_5_getNonFullVCs => EN_send_ports_5_getNonFullVCs ,
send_ports_5_getNonFullVCs => send_ports_5_getNonFullVCs ,
send_ports_6_putFlit_flit_in => send_ports_6_putFlit_flit_in ,
EN_send_ports_6_putFlit => EN_send_ports_6_putFlit ,
EN_send_ports_6_getNonFullVCs => EN_send_ports_6_getNonFullVCs ,
send_ports_6_getNonFullVCs => send_ports_6_getNonFullVCs ,
send_ports_7_putFlit_flit_in => send_ports_7_putFlit_flit_in ,
EN_send_ports_7_putFlit => EN_send_ports_7_putFlit ,
EN_send_ports_7_getNonFullVCs => EN_send_ports_7_getNonFullVCs ,
send_ports_7_getNonFullVCs => send_ports_7_getNonFullVCs ,
send_ports_8_putFlit_flit_in => send_ports_8_putFlit_flit_in ,
EN_send_ports_8_putFlit => EN_send_ports_8_putFlit ,
EN_send_ports_8_getNonFullVCs => EN_send_ports_8_getNonFullVCs ,
send_ports_8_getNonFullVCs => send_ports_8_getNonFullVCs ,
EN_recv_ports_0_getFlit => EN_recv_ports_0_getFlit ,
recv_ports_0_getFlit => recv_ports_0_getFlit ,
recv_ports_0_putNonFullVCs_nonFullVCs => recv_ports_0_putNonFullVCs_nonFullVCs ,
EN_recv_ports_0_putNonFullVCs => EN_recv_ports_0_putNonFullVCs ,
EN_recv_ports_1_getFlit => EN_recv_ports_1_getFlit ,
recv_ports_1_getFlit => recv_ports_1_getFlit ,
recv_ports_1_putNonFullVCs_nonFullVCs => recv_ports_1_putNonFullVCs_nonFullVCs ,
EN_recv_ports_1_putNonFullVCs => EN_recv_ports_1_putNonFullVCs ,
EN_recv_ports_2_getFlit => EN_recv_ports_2_getFlit ,
recv_ports_2_getFlit => recv_ports_2_getFlit ,
recv_ports_2_putNonFullVCs_nonFullVCs => recv_ports_2_putNonFullVCs_nonFullVCs ,
EN_recv_ports_2_putNonFullVCs => EN_recv_ports_2_putNonFullVCs ,
EN_recv_ports_3_getFlit => EN_recv_ports_3_getFlit ,
recv_ports_3_getFlit => recv_ports_3_getFlit ,
recv_ports_3_putNonFullVCs_nonFullVCs => recv_ports_3_putNonFullVCs_nonFullVCs ,
EN_recv_ports_3_putNonFullVCs => EN_recv_ports_3_putNonFullVCs ,
EN_recv_ports_4_getFlit => EN_recv_ports_4_getFlit ,
recv_ports_4_getFlit => recv_ports_4_getFlit ,
recv_ports_4_putNonFullVCs_nonFullVCs => recv_ports_4_putNonFullVCs_nonFullVCs ,
EN_recv_ports_4_putNonFullVCs => EN_recv_ports_4_putNonFullVCs ,
EN_recv_ports_5_getFlit => EN_recv_ports_5_getFlit ,
recv_ports_5_getFlit => recv_ports_5_getFlit ,
recv_ports_5_putNonFullVCs_nonFullVCs => recv_ports_5_putNonFullVCs_nonFullVCs ,
EN_recv_ports_5_putNonFullVCs => EN_recv_ports_5_putNonFullVCs ,
EN_recv_ports_6_getFlit => EN_recv_ports_6_getFlit ,
recv_ports_6_getFlit => recv_ports_6_getFlit ,
recv_ports_6_putNonFullVCs_nonFullVCs => recv_ports_6_putNonFullVCs_nonFullVCs ,
EN_recv_ports_6_putNonFullVCs => EN_recv_ports_6_putNonFullVCs ,
EN_recv_ports_7_getFlit => EN_recv_ports_7_getFlit ,
recv_ports_7_getFlit => recv_ports_7_getFlit ,
recv_ports_7_putNonFullVCs_nonFullVCs => recv_ports_7_putNonFullVCs_nonFullVCs ,
EN_recv_ports_7_putNonFullVCs => EN_recv_ports_7_putNonFullVCs ,
EN_recv_ports_8_getFlit => EN_recv_ports_8_getFlit ,
recv_ports_8_getFlit => recv_ports_8_getFlit ,
recv_ports_8_putNonFullVCs_nonFullVCs => recv_ports_8_putNonFullVCs_nonFullVCs ,
EN_recv_ports_8_putNonFullVCs => EN_recv_ports_8_putNonFullVCs ,
recv_ports_info_0_getRecvPortID => recv_ports_info_0_getRecvPortID ,
recv_ports_info_1_getRecvPortID => recv_ports_info_1_getRecvPortID ,
recv_ports_info_2_getRecvPortID => recv_ports_info_2_getRecvPortID ,
recv_ports_info_3_getRecvPortID => recv_ports_info_3_getRecvPortID ,
recv_ports_info_4_getRecvPortID => recv_ports_info_4_getRecvPortID ,
recv_ports_info_5_getRecvPortID => recv_ports_info_5_getRecvPortID ,
recv_ports_info_6_getRecvPortID => recv_ports_info_6_getRecvPortID ,
recv_ports_info_7_getRecvPortID => recv_ports_info_7_getRecvPortID ,
recv_ports_info_8_getRecvPortID => recv_ports_info_8_getRecvPortID
);
i0: noc_interface
generic map(
data_width => data_width,
addr_width => addr_width,
vc_sel_width => vc_sel_width,
num_vc => num_vc,
flit_buff_depth => flit_buff_depth,
use_vc => 1)
port map(
clk => clock_50,
rst => noc_rst,
send_data => send_data_pe0,
dest_addr => dest_addr_pe0,
set_tail_flit => set_tail_flit_pe0,
send_flit => send_flit_pe0,
ready_to_send => ready_to_send_pe0,
recv_data => recv_data_pe0,
src_addr => src_addr_pe0,
is_tail_flit => is_tail_flit_pe0,
data_in_buffer => data_in_buffer_pe0,
dequeue => dequeue_pe0,
select_vc_read => select_vc_read_pe0,
send_putFlit_flit_in => send_ports_0_putFlit_flit_in,
EN_send_putFlit => EN_send_ports_0_putFlit,
EN_send_getNonFullVCs => EN_send_ports_0_getNonFullVCs,
send_getNonFullVCs => send_ports_0_getNonFullVCs,
EN_recv_getFlit => EN_recv_ports_0_getFlit,
recv_getFlit => recv_ports_0_getFlit,
recv_putNonFullVCs_nonFullVCs => recv_ports_0_putNonFullVCs_nonFullVCs,
EN_recv_putNonFullVCs => EN_recv_ports_0_putNonFullVCs,
recv_info_getRecvPortID => recv_ports_info_0_getRecvPortID);
i1: noc_interface
generic map(
data_width => data_width,
addr_width => addr_width,
vc_sel_width => vc_sel_width,
num_vc => num_vc,
flit_buff_depth => flit_buff_depth)
port map(
clk => clock_50,
rst => noc_rst,
send_data => send_data_pe1,
dest_addr => dest_addr_pe1,
set_tail_flit => set_tail_flit_pe1,
send_flit => send_flit_pe1,
ready_to_send => ready_to_send_pe1,
recv_data => recv_data_pe1,
src_addr => src_addr_pe1,
is_tail_flit => is_tail_flit_pe1,
data_in_buffer => data_in_buffer_pe1,
dequeue => dequeue_pe1,
select_vc_read => select_vc_read_pe1,
send_putFlit_flit_in => send_ports_1_putFlit_flit_in,
EN_send_putFlit => EN_send_ports_1_putFlit,
EN_send_getNonFullVCs => EN_send_ports_1_getNonFullVCs,
send_getNonFullVCs => send_ports_1_getNonFullVCs,
EN_recv_getFlit => EN_recv_ports_1_getFlit,
recv_getFlit => recv_ports_1_getFlit,
recv_putNonFullVCs_nonFullVCs => recv_ports_1_putNonFullVCs_nonFullVCs,
EN_recv_putNonFullVCs => EN_recv_ports_1_putNonFullVCs,
recv_info_getRecvPortID => recv_ports_info_1_getRecvPortID);
i2: noc_interface
generic map(
data_width => data_width,
addr_width => addr_width,
vc_sel_width => vc_sel_width,
num_vc => num_vc,
flit_buff_depth => flit_buff_depth)
port map(
clk => clock_50,
rst => noc_rst,
send_data => send_data_pe2,
dest_addr => dest_addr_pe2,
set_tail_flit => set_tail_flit_pe2,
send_flit => send_flit_pe2,
ready_to_send => ready_to_send_pe2,
recv_data => recv_data_pe2,
src_addr => src_addr_pe2,
is_tail_flit => is_tail_flit_pe2,
data_in_buffer => data_in_buffer_pe2,
dequeue => dequeue_pe2,
select_vc_read => select_vc_read_pe2,
send_putFlit_flit_in => send_ports_2_putFlit_flit_in,
EN_send_putFlit => EN_send_ports_2_putFlit,
EN_send_getNonFullVCs => EN_send_ports_2_getNonFullVCs,
send_getNonFullVCs => send_ports_2_getNonFullVCs,
EN_recv_getFlit => EN_recv_ports_2_getFlit,
recv_getFlit => recv_ports_2_getFlit,
recv_putNonFullVCs_nonFullVCs => recv_ports_2_putNonFullVCs_nonFullVCs,
EN_recv_putNonFullVCs => EN_recv_ports_2_putNonFullVCs,
recv_info_getRecvPortID => recv_ports_info_2_getRecvPortID);
i3: noc_interface
generic map(
data_width => data_width,
addr_width => addr_width,
vc_sel_width => vc_sel_width,
num_vc => num_vc,
flit_buff_depth => flit_buff_depth)
port map(
clk => clock_50,
rst => noc_rst,
send_data => send_data_pe3,
dest_addr => dest_addr_pe3,
set_tail_flit => set_tail_flit_pe3,
send_flit => send_flit_pe3,
ready_to_send => ready_to_send_pe3,
recv_data => recv_data_pe3,
src_addr => src_addr_pe3,
is_tail_flit => is_tail_flit_pe3,
data_in_buffer => data_in_buffer_pe3,
dequeue => dequeue_pe3,
select_vc_read => select_vc_read_pe3,
send_putFlit_flit_in => send_ports_3_putFlit_flit_in,
EN_send_putFlit => EN_send_ports_3_putFlit,
EN_send_getNonFullVCs => EN_send_ports_3_getNonFullVCs,
send_getNonFullVCs => send_ports_3_getNonFullVCs,
EN_recv_getFlit => EN_recv_ports_3_getFlit,
recv_getFlit => recv_ports_3_getFlit,
recv_putNonFullVCs_nonFullVCs => recv_ports_3_putNonFullVCs_nonFullVCs,
EN_recv_putNonFullVCs => EN_recv_ports_3_putNonFullVCs,
recv_info_getRecvPortID => recv_ports_info_3_getRecvPortID);
i4: noc_interface
generic map(
data_width => data_width,
addr_width => addr_width,
vc_sel_width => vc_sel_width,
num_vc => num_vc,
flit_buff_depth => flit_buff_depth)
port map(
clk => clock_50,
rst => noc_rst,
send_data => send_data_pe4,
dest_addr => dest_addr_pe4,
set_tail_flit => set_tail_flit_pe4,
send_flit => send_flit_pe4,
ready_to_send => ready_to_send_pe4,
recv_data => recv_data_pe4,
src_addr => src_addr_pe4,
is_tail_flit => is_tail_flit_pe4,
data_in_buffer => data_in_buffer_pe4,
dequeue => dequeue_pe4,
select_vc_read => select_vc_read_pe4,
send_putFlit_flit_in => send_ports_4_putFlit_flit_in,
EN_send_putFlit => EN_send_ports_4_putFlit,
EN_send_getNonFullVCs => EN_send_ports_4_getNonFullVCs,
send_getNonFullVCs => send_ports_4_getNonFullVCs,
EN_recv_getFlit => EN_recv_ports_4_getFlit,
recv_getFlit => recv_ports_4_getFlit,
recv_putNonFullVCs_nonFullVCs => recv_ports_4_putNonFullVCs_nonFullVCs,
EN_recv_putNonFullVCs => EN_recv_ports_4_putNonFullVCs,
recv_info_getRecvPortID => recv_ports_info_4_getRecvPortID);
i5: noc_interface
generic map(
data_width => data_width,
addr_width => addr_width,
vc_sel_width => vc_sel_width,
num_vc => num_vc,
flit_buff_depth => flit_buff_depth)
port map(
clk => clock_50,
rst => noc_rst,
send_data => send_data_pe5,
dest_addr => dest_addr_pe5,
set_tail_flit => set_tail_flit_pe5,
send_flit => send_flit_pe5,
ready_to_send => ready_to_send_pe5,
recv_data => recv_data_pe5,
src_addr => src_addr_pe5,
is_tail_flit => is_tail_flit_pe5,
data_in_buffer => data_in_buffer_pe5,
dequeue => dequeue_pe5,
select_vc_read => select_vc_read_pe5,
send_putFlit_flit_in => send_ports_5_putFlit_flit_in,
EN_send_putFlit => EN_send_ports_5_putFlit,
EN_send_getNonFullVCs => EN_send_ports_5_getNonFullVCs,
send_getNonFullVCs => send_ports_5_getNonFullVCs,
EN_recv_getFlit => EN_recv_ports_5_getFlit,
recv_getFlit => recv_ports_5_getFlit,
recv_putNonFullVCs_nonFullVCs => recv_ports_5_putNonFullVCs_nonFullVCs,
EN_recv_putNonFullVCs => EN_recv_ports_5_putNonFullVCs,
recv_info_getRecvPortID => recv_ports_info_5_getRecvPortID);
i6: noc_interface
generic map(
data_width => data_width,
addr_width => addr_width,
vc_sel_width => vc_sel_width,
num_vc => num_vc,
flit_buff_depth => flit_buff_depth)
port map(
clk => clock_50,
rst => noc_rst,
send_data => send_data_pe6,
dest_addr => dest_addr_pe6,
set_tail_flit => set_tail_flit_pe6,
send_flit => send_flit_pe6,
ready_to_send => ready_to_send_pe6,
recv_data => recv_data_pe6,
src_addr => src_addr_pe6,
is_tail_flit => is_tail_flit_pe6,
data_in_buffer => data_in_buffer_pe6,
dequeue => dequeue_pe6,
select_vc_read => select_vc_read_pe6,
send_putFlit_flit_in => send_ports_6_putFlit_flit_in,
EN_send_putFlit => EN_send_ports_6_putFlit,
EN_send_getNonFullVCs => EN_send_ports_6_getNonFullVCs,
send_getNonFullVCs => send_ports_6_getNonFullVCs,
EN_recv_getFlit => EN_recv_ports_6_getFlit,
recv_getFlit => recv_ports_6_getFlit,
recv_putNonFullVCs_nonFullVCs => recv_ports_6_putNonFullVCs_nonFullVCs,
EN_recv_putNonFullVCs => EN_recv_ports_6_putNonFullVCs,
recv_info_getRecvPortID => recv_ports_info_6_getRecvPortID);
i7: noc_interface
generic map(
data_width => data_width,
addr_width => addr_width,
vc_sel_width => vc_sel_width,
num_vc => num_vc,
flit_buff_depth => flit_buff_depth,
use_vc => 0)
port map(
clk => clock_50,
rst => noc_rst,
send_data => send_data_pe7,
dest_addr => dest_addr_pe7,
set_tail_flit => set_tail_flit_pe7,
send_flit => send_flit_pe7,
ready_to_send => ready_to_send_pe7,
recv_data => recv_data_pe7,
src_addr => src_addr_pe7,
is_tail_flit => is_tail_flit_pe7,
data_in_buffer => data_in_buffer_pe7,
dequeue => dequeue_pe7,
select_vc_read => select_vc_read_pe7,
send_putFlit_flit_in => send_ports_7_putFlit_flit_in,
EN_send_putFlit => EN_send_ports_7_putFlit,
EN_send_getNonFullVCs => EN_send_ports_7_getNonFullVCs,
send_getNonFullVCs => send_ports_7_getNonFullVCs,
EN_recv_getFlit => EN_recv_ports_7_getFlit,
recv_getFlit => recv_ports_7_getFlit,
recv_putNonFullVCs_nonFullVCs => recv_ports_7_putNonFullVCs_nonFullVCs,
EN_recv_putNonFullVCs => EN_recv_ports_7_putNonFullVCs,
recv_info_getRecvPortID => recv_ports_info_7_getRecvPortID);
i8: noc_interface
generic map(
data_width => data_width,
addr_width => addr_width,
vc_sel_width => vc_sel_width,
num_vc => num_vc,
flit_buff_depth => flit_buff_depth)
port map(
clk => clock_50,
rst => noc_rst,
send_data => send_data_pe8,
dest_addr => dest_addr_pe8,
set_tail_flit => set_tail_flit_pe8,
send_flit => send_flit_pe8,
ready_to_send => ready_to_send_pe8,
recv_data => recv_data_pe8,
src_addr => src_addr_pe8,
is_tail_flit => is_tail_flit_pe8,
data_in_buffer => data_in_buffer_pe8,
dequeue => dequeue_pe8,
select_vc_read => select_vc_read_pe8,
send_putFlit_flit_in => send_ports_8_putFlit_flit_in,
EN_send_putFlit => EN_send_ports_8_putFlit,
EN_send_getNonFullVCs => EN_send_ports_8_getNonFullVCs,
send_getNonFullVCs => send_ports_8_getNonFullVCs,
EN_recv_getFlit => EN_recv_ports_8_getFlit,
recv_getFlit => recv_ports_8_getFlit,
recv_putNonFullVCs_nonFullVCs => recv_ports_8_putNonFullVCs_nonFullVCs,
EN_recv_putNonFullVCs => EN_recv_ports_8_putNonFullVCs,
recv_info_getRecvPortID => recv_ports_info_8_getRecvPortID);
n0: component deblocking_filter_node
generic map(
data_width => data_width ,
addr_width => addr_width ,
vc_sel_width => vc_sel_width ,
num_vc => num_vc ,
flit_buff_depth => flit_buff_depth
)
port map(
clk => clock_50,
rst => noc_rst,
recv_data => recv_data_pe2,
src_addr => src_addr_pe2,
is_tail_flit => is_tail_flit_pe2,
data_in_buffer => data_in_buffer_pe2,
dequeue => dequeue_pe2,
select_vc_read => select_vc_read_pe2,
send_data => send_data_pe2,
dest_addr => dest_addr_pe2,
set_tail_flit => set_tail_flit_pe2,
send_flit => send_flit_pe2,
ready_to_send => ready_to_send_pe2
);
n1: component inter_node
generic map(
size_x => 16,
size_y => 9,
interp_x => 4 ,
interp_y => 2 ,
sample_size => 8 ,
samples_per_wr => 8 ,
data_width => data_width ,
addr_width => addr_width ,
vc_sel_width => vc_sel_width ,
num_vc => num_vc ,
flit_buff_depth => flit_buff_depth
)
port map(
clk => clock_50,
rst => noc_rst,
recv_data => recv_data_pe5,
src_addr => src_addr_pe5,
is_tail_flit => is_tail_flit_pe5,
data_in_buffer => data_in_buffer_pe5,
dequeue => dequeue_pe5,
select_vc_read => select_vc_read_pe5,
send_data => send_data_pe5,
dest_addr => dest_addr_pe5,
set_tail_flit => set_tail_flit_pe5,
send_flit => send_flit_pe5,
ready_to_send => ready_to_send_pe5
);
n2: component intra_prediction_node
generic map(
data_width => data_width ,
addr_width => addr_width ,
vc_sel_width => vc_sel_width ,
num_vc => num_vc ,
flit_buff_depth => flit_buff_depth
)
port map(
clk => clock_50,
rst => noc_rst,
recv_data => recv_data_pe3,
src_addr => src_addr_pe3,
is_tail_flit => is_tail_flit_pe3,
data_in_buffer => data_in_buffer_pe3,
dequeue => dequeue_pe3,
select_vc_read => select_vc_read_pe3,
send_data => send_data_pe3,
dest_addr => dest_addr_pe3,
set_tail_flit => set_tail_flit_pe3,
send_flit => send_flit_pe3,
ready_to_send => ready_to_send_pe3,
s_intra_idle => ledr(0),
s_intra_data_rxd => ledr(1),
s_intra_write_sample => ledr(2),
s_intra_start_pred => ledr(3),
s_intra_start_tx_loop => ledr(4),
s_intra_start_tx_loop_hold => ledr(5),
s_intra_tx => ledr(6),
s_intra_tx_hold => ledr(7),
s_intra_tx_gen_next => ledr(8),
s_intra_dequeue_rx => ledr(9)
);
n3: component noc_control_plus
generic map(
data_width => data_width ,
addr_width => addr_width ,
vc_sel_width => vc_sel_width ,
num_vc => num_vc ,
flit_buff_depth => flit_buff_depth
)
port map(
clk => clock_50,
rst => noc_rst,
recv_data => recv_data_pe0,
src_addr => src_addr_pe0,
is_tail_flit => is_tail_flit_pe0,
data_in_buffer => data_in_buffer_pe0,
dequeue => dequeue_pe0,
select_vc_read => select_vc_read_pe0,
send_data => send_data_pe0,
dest_addr => dest_addr_pe0,
set_tail_flit => set_tail_flit_pe0,
send_flit => send_flit_pe0,
ready_to_send => ready_to_send_pe0,
set_tail_cpu => noc_ctrl_cpu_0(31),
addr_cpu => std_logic_vector(resize(unsigned(noc_ctrl_cpu_0(23 downto 16)),addr_width)),
format_select => noc_ctrl_cpu_0(7 downto 0),
send_cmd_cpu => noc_ctrl_cpu_0(30),
send_ack => noc_sts_cpu_0(31),
parse_select => noc_ctrl_cpu_0(15 downto 8),
cpu_rx_ctrl => noc_ctrl_cpu_0(29),
rx_state_out => noc_sts_cpu_0(7 downto 0),
rx_0 => cpu_0_rx_0_external_connection_export,
rx_1 => cpu_0_rx_1_external_connection_export,
rx_2 => cpu_0_rx_2_external_connection_export,
rx_3 => cpu_0_rx_3_external_connection_export,
rx_4 => cpu_0_rx_4_external_connection_export,
rx_5 => cpu_0_rx_5_external_connection_export,
rx_6 => cpu_0_rx_6_external_connection_export,
rx_7 => cpu_0_rx_7_external_connection_export,
tx_0 => cpu_0_tx_0_external_connection_export,
tx_1 => cpu_0_tx_1_external_connection_export,
tx_2 => cpu_0_tx_2_external_connection_export,
tx_3 => cpu_0_tx_3_external_connection_export,
tx_4 => cpu_0_tx_4_external_connection_export,
tx_5 => cpu_0_tx_5_external_connection_export,
tx_6 => cpu_0_tx_6_external_connection_export,
tx_7 => cpu_0_tx_7_external_connection_export
);
n4: component chroma_motion
generic map(
data_width => data_width ,
addr_width => addr_width ,
vc_sel_width => vc_sel_width ,
num_vc => num_vc ,
flit_buff_depth => flit_buff_depth
)
port map(
clk => clock_50,
rst => noc_rst,
recv_data => recv_data_pe4,
src_addr => src_addr_pe4,
is_tail_flit => is_tail_flit_pe4,
data_in_buffer => data_in_buffer_pe4,
dequeue => dequeue_pe4,
select_vc_read => select_vc_read_pe4,
send_data => send_data_pe4,
dest_addr => dest_addr_pe4,
set_tail_flit => set_tail_flit_pe4,
send_flit => send_flit_pe4,
ready_to_send => ready_to_send_pe4
);
n6: component iqit_node
generic map(
sample_width => 8,
qp_width => 8,
wo_dc_width => 8,
data_width => data_width ,
addr_width => addr_width ,
vc_sel_width => vc_sel_width ,
num_vc => num_vc ,
flit_buff_depth => flit_buff_depth
)
port map(
clk => clock_50,
rst => noc_rst,
recv_data => recv_data_pe1,
src_addr => src_addr_pe1,
is_tail_flit => is_tail_flit_pe1,
data_in_buffer => data_in_buffer_pe1,
dequeue => dequeue_pe1,
select_vc_read => select_vc_read_pe1,
send_data => send_data_pe1,
dest_addr => dest_addr_pe1,
set_tail_flit => set_tail_flit_pe1,
send_flit => send_flit_pe1,
ready_to_send => ready_to_send_pe1
);
n7: component noc_control_plus
generic map(
data_width => data_width ,
addr_width => addr_width ,
vc_sel_width => vc_sel_width ,
num_vc => num_vc ,
flit_buff_depth => flit_buff_depth
)
port map(
clk => clock_50,
rst => noc_rst,
recv_data => recv_data_pe7,
src_addr => src_addr_pe7,
is_tail_flit => is_tail_flit_pe7,
data_in_buffer => data_in_buffer_pe7,
dequeue => dequeue_pe7,
select_vc_read => select_vc_read_pe7,
send_data => send_data_pe7,
dest_addr => dest_addr_pe7,
set_tail_flit => set_tail_flit_pe7,
send_flit => send_flit_pe7,
ready_to_send => ready_to_send_pe7,
set_tail_cpu => noc_ctrl_cpu_1(31),
addr_cpu => std_logic_vector(resize(unsigned(noc_ctrl_cpu_1(23 downto 16)),addr_width)),
format_select => noc_ctrl_cpu_1(7 downto 0),
send_cmd_cpu => noc_ctrl_cpu_1(30),
send_ack => noc_sts_cpu_1(31),
parse_select => noc_ctrl_cpu_1(15 downto 8),
cpu_rx_ctrl => noc_ctrl_cpu_1(29),
rx_state_out => noc_sts_cpu_1(7 downto 0),
rx_0 => cpu_1_rx_0_external_connection_export,
rx_1 => cpu_1_rx_1_external_connection_export,
rx_2 => cpu_1_rx_2_external_connection_export,
rx_3 => cpu_1_rx_3_external_connection_export,
rx_4 => cpu_1_rx_4_external_connection_export,
rx_5 => cpu_1_rx_5_external_connection_export,
rx_6 => cpu_1_rx_6_external_connection_export,
rx_7 => cpu_1_rx_7_external_connection_export,
tx_0 => cpu_1_tx_0_external_connection_export,
tx_1 => cpu_1_tx_1_external_connection_export,
tx_2 => cpu_1_tx_2_external_connection_export,
tx_3 => cpu_1_tx_3_external_connection_export,
tx_4 => cpu_1_tx_4_external_connection_export,
tx_5 => cpu_1_tx_5_external_connection_export,
tx_6 => cpu_1_tx_6_external_connection_export,
tx_7 => cpu_1_tx_7_external_connection_export
);
n8: component vga_node
generic map(
data_width => data_width ,
addr_width => addr_width ,
vc_sel_width => vc_sel_width ,
num_vc => num_vc ,
flit_buff_depth => flit_buff_depth
)
port map(
clk => clock_50,
rst => noc_rst,
recv_data => recv_data_pe8,
src_addr => src_addr_pe8,
is_tail_flit => is_tail_flit_pe8,
data_in_buffer => data_in_buffer_pe8,
dequeue => dequeue_pe8,
select_vc_read => select_vc_read_pe8,
send_data => send_data_pe8,
dest_addr => dest_addr_pe8,
set_tail_flit => set_tail_flit_pe8,
send_flit => send_flit_pe8,
ready_to_send => ready_to_send_pe8,
clk27 => vga_clock,
rst27 => noc_rst,
vga_red => vga_red,
vga_blue => vga_blue,
vga_green => vga_green,
vga_v_sync => vga_v_sync,
vga_h_sync => vga_h_sync
);
--UNCOMMENT TO EXPERIMENT WITH 2 LMC NODES
--n9: component inter_node
--generic map(
-- size_x => 16,
-- size_y => 9,
-- interp_x => 4 ,
-- interp_y => 2 ,
-- sample_size => 8 ,
-- samples_per_wr => 8 ,
-- data_width => data_width ,
-- addr_width => addr_width ,
-- vc_sel_width => vc_sel_width ,
-- num_vc => num_vc ,
-- flit_buff_depth => flit_buff_depth
--)
--port map(
-- clk => clock_50,
-- rst => noc_rst,
-- recv_data => recv_data_pe6,
-- src_addr => src_addr_pe6,
-- is_tail_flit => is_tail_flit_pe6,
-- data_in_buffer => data_in_buffer_pe6,
-- dequeue => dequeue_pe6,
-- select_vc_read => select_vc_read_pe6,
-- send_data => send_data_pe6,
-- dest_addr => dest_addr_pe6,
-- set_tail_flit => set_tail_flit_pe6,
-- send_flit => send_flit_pe6,
-- ready_to_send => ready_to_send_pe6
--);
noc_rst <= noc_ctrl_cpu_0(28) or noc_ctrl_cpu_1(28);
--gpio header for vga
gpio(0 ) <= '0';
gpio(1 ) <= '0';
gpio(2 ) <= vga_v_sync;
gpio(3 ) <= '0';
gpio(4 ) <= vga_h_sync;
gpio(5 ) <= '0';
gpio(6 ) <= vga_blue(0);
gpio(7 ) <= vga_green(4);
gpio(8 ) <= '0';
gpio(9 ) <= vga_green(5);
gpio(10) <= vga_red(1);
gpio(11) <= vga_red(2);
gpio(12) <= '0';
gpio(13) <= '0';
gpio(14) <= '0';
gpio(15) <= '0';
gpio(16) <= vga_green(0);
gpio(17) <= '0';
gpio(18) <= vga_blue(5);
gpio(19) <= '0';
gpio(20) <= vga_green(1);
gpio(21) <= vga_blue(4);
gpio(22) <= '0';
gpio(23) <= vga_blue(3);
gpio(24) <= vga_blue(1);
gpio(25) <= '0';
gpio(26) <= vga_blue(2);
gpio(27) <= vga_green(2);
gpio(28) <= vga_green(3);
gpio(29) <= '0';
gpio(30) <= vga_red(3);
gpio(31) <= vga_red(0);
gpio(32) <= '0';
gpio(33) <= vga_red(4);
gpio(34) <= '0';
gpio(35) <= vga_red(5);
END MAIN; | mit | aaf1be26714030c55a7075108c28fd33 | 0.496691 | 3.685608 | false | false | false | false |
AfterRace/SoC_Project | vivado/project/project.srcs/sources_1/ipshared/tsotnep/filter_iir_v1_0/263d46e2/src/Filter_Top_Level.vhd | 2 | 7,208 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
entity Filter_Top_Level is
port(
AUDIO_OUT_L : out std_logic_vector(23 downto 0);
AUDIO_OUT_R : out std_logic_vector(23 downto 0);
FILTER_DONE : out std_logic;
CLK_100mhz : in std_logic;
SAMPLE_TRIG : in std_logic;
AUDIO_IN_L : in std_logic_vector(23 downto 0);
AUDIO_IN_R : in std_logic_vector(23 downto 0);
RST : in std_logic;
sample_trigger_en : in std_logic;
HP_SW : in std_logic;
BP_SW : in std_logic;
LP_SW : in std_logic;
slv_reg0 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg1 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg2 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg3 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg4 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg5 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg6 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg7 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg8 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg9 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg10 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg11 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg12 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg13 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg14 : in STD_LOGIC_VECTOR(31 downto 0)
);
end Filter_Top_Level;
architecture RTL of Filter_Top_Level is
component IIR_Biquad_II_v3 is
port(
Coef_b0 : std_logic_vector(31 downto 0);
Coef_b1 : std_logic_vector(31 downto 0);
Coef_b2 : std_logic_vector(31 downto 0);
Coef_a1 : std_logic_vector(31 downto 0);
Coef_a2 : std_logic_vector(31 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
sample_trig : in STD_LOGIC;
X_in : in STD_LOGIC_VECTOR(23 downto 0);
filter_done : out STD_LOGIC;
Y_out : out STD_LOGIC_VECTOR(23 downto 0)
);
end component;
signal IIR_LP_Done_R, IIR_LP_Done_L, IIR_BP_Done_R, IIR_BP_Done_L, IIR_HP_Done_R, IIR_HP_Done_L : std_logic;
signal AUDIO_OUT_TRUNC_L, AUDIO_OUT_TRUNC_R, IIR_LP_Y_Out_R, IIR_LP_Y_Out_L, IIR_BP_Y_Out_R, IIR_BP_Y_Out_L, IIR_HP_Y_Out_R, IIR_HP_Y_Out_L : std_logic_vector(23 downto 0);
signal sample_trigger_safe : STD_LOGIC := '0';
signal val : std_logic_vector(2 downto 0);
begin
sample_trigger_safe <= SAMPLE_TRIG or (not sample_trigger_en);
val <= HP_SW & BP_SW & LP_SW;
--USER logic implementation added here
---- connect all the "filter done" with an AND gate to the user_logic top level entity.
FILTER_DONE <= IIR_LP_Done_R and IIR_LP_Done_L and IIR_BP_Done_R and IIR_BP_Done_L and IIR_HP_Done_R and IIR_HP_Done_L;
AUDIO_OUT_L <= AUDIO_OUT_TRUNC_L; -- & X"00";
AUDIO_OUT_R <= AUDIO_OUT_TRUNC_R; -- & X"00";
---this process controls each individual filter and the final output of the filter.
process(IIR_BP_Y_Out_L, IIR_BP_Y_Out_R, IIR_HP_Y_Out_L, IIR_HP_Y_Out_R, IIR_LP_Y_Out_L, IIR_LP_Y_Out_R, val)
begin
case val is
when "111" =>
AUDIO_OUT_TRUNC_L <= (others => '0');
AUDIO_OUT_TRUNC_R <= (others => '0');
when "110" =>
AUDIO_OUT_TRUNC_L <= IIR_LP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_LP_Y_Out_R;
when "101" =>
AUDIO_OUT_TRUNC_L <= IIR_BP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_BP_Y_Out_R;
when "100" =>
AUDIO_OUT_TRUNC_L <= std_logic_vector(unsigned(IIR_LP_Y_Out_L) + unsigned(IIR_BP_Y_Out_L));
AUDIO_OUT_TRUNC_R <= std_logic_vector(unsigned(IIR_LP_Y_Out_R) + unsigned(IIR_BP_Y_Out_R));
when "011" =>
AUDIO_OUT_TRUNC_L <= IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_HP_Y_Out_R;
when "010" =>
AUDIO_OUT_TRUNC_L <= std_logic_vector(unsigned(IIR_LP_Y_Out_L) + unsigned(IIR_HP_Y_Out_L));
AUDIO_OUT_TRUNC_R <= std_logic_vector(unsigned(IIR_LP_Y_Out_R) + unsigned(IIR_HP_Y_Out_R));
when "001" =>
AUDIO_OUT_TRUNC_L <= std_logic_vector(unsigned(IIR_HP_Y_Out_L) + unsigned(IIR_BP_Y_Out_L));
AUDIO_OUT_TRUNC_R <= std_logic_vector(unsigned(IIR_HP_Y_Out_R) + unsigned(IIR_BP_Y_Out_R));
when "000" =>
AUDIO_OUT_TRUNC_L <= std_logic_vector(unsigned(IIR_LP_Y_Out_L) + unsigned(IIR_BP_Y_Out_L) + unsigned(IIR_HP_Y_Out_L));
AUDIO_OUT_TRUNC_R <= std_logic_vector(unsigned(IIR_LP_Y_Out_R) + unsigned(IIR_BP_Y_Out_R) + unsigned(IIR_HP_Y_Out_R));
when others =>
AUDIO_OUT_TRUNC_L <= (others => '0');
AUDIO_OUT_TRUNC_R <= (others => '0');
end case;
end process;
IIR_LP_R : IIR_Biquad_II_v3
port map(
Coef_b0 => slv_reg0,
Coef_b1 => slv_reg1,
Coef_b2 => slv_reg2,
Coef_a1 => slv_reg3,
Coef_a2 => slv_reg4,
clk => CLK_100mhz,
rst => RST,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_R(23 downto 0),
filter_done => IIR_LP_Done_R,
Y_out => IIR_LP_Y_Out_R
);
IIR_LP_L : IIR_Biquad_II_v3
port map(
Coef_b0 => slv_reg0,
Coef_b1 => slv_reg1,
Coef_b2 => slv_reg2,
Coef_a1 => slv_reg3,
Coef_a2 => slv_reg4,
clk => CLK_100mhz,
rst => RST,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_L(23 downto 0), --X_in_truncated_L,
filter_done => IIR_LP_Done_L,
Y_out => IIR_LP_Y_Out_L
);
IIR_BP_R : IIR_Biquad_II_v3 --(20 - 20000)
port map(
Coef_b0 => slv_reg5,
Coef_b1 => slv_reg6,
Coef_b2 => slv_reg7,
Coef_a1 => slv_reg8,
Coef_a2 => slv_reg9,
clk => CLK_100mhz,
rst => RST,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_R(23 downto 0), --X_in_truncated_R,
filter_done => IIR_BP_Done_R,
Y_out => IIR_BP_Y_Out_R
);
IIR_BP_L : IIR_Biquad_II_v3 --(20 - 20000)
port map(
Coef_b0 => slv_reg5,
Coef_b1 => slv_reg6,
Coef_b2 => slv_reg7,
Coef_a1 => slv_reg8,
Coef_a2 => slv_reg9,
clk => CLK_100mhz,
rst => RST,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_L(23 downto 0), --X_in_truncated_L,
filter_done => IIR_BP_Done_L,
Y_out => IIR_BP_Y_Out_L
);
IIR_HP_R : IIR_Biquad_II_v3
port map(
Coef_b0 => slv_reg10,
Coef_b1 => slv_reg11,
Coef_b2 => slv_reg12,
Coef_a1 => slv_reg13,
Coef_a2 => slv_reg14,
clk => CLK_100mhz,
rst => RST,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_R(23 downto 0), --X_in_truncated_R,
filter_done => IIR_HP_Done_R,
Y_out => IIR_HP_Y_Out_R
);
IIR_HP_L : IIR_Biquad_II_v3
port map(
Coef_b0 => slv_reg10,
Coef_b1 => slv_reg11,
Coef_b2 => slv_reg12,
Coef_a1 => slv_reg13,
Coef_a2 => slv_reg14,
clk => CLK_100mhz,
rst => RST,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_L(23 downto 0), --X_in_truncated_L,
filter_done => IIR_HP_Done_L,
Y_out => IIR_HP_Y_Out_L
);
end RTL;
| lgpl-3.0 | bea950cb1100ed289faa7a597fd3dcf4 | 0.562292 | 2.511498 | false | false | false | false |
boztalay/OldProjects | FPGA/FlashProgrammer/GenCounter.vhd | 2 | 1,330 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:39:09 11/26/2009
-- Design Name:
-- Module Name: GenCounter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity GenCounter is
generic (size : integer);
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR((size - 1) downto 0));
end GenCounter;
architecture Behavioral of GenCounter is
begin
main: process(clock, reset) is
variable count : STD_LOGIC_VECTOR((size - 1) downto 0) := (others => '0');
begin
if rising_edge(clock) then
count := count + 1;
end if;
if reset = '1' then
count := (others => '0');
end if;
data_out <= count;
end process;
end Behavioral;
| mit | 07d8ba2984ba21dd4dd404db31f20875 | 0.542857 | 3.653846 | false | false | false | false |
peladex/RHD2132_FPGA | quartus/test_spi_de0/fifo_test_1_inst.vhd | 1 | 203 | fifo_test_1_inst : fifo_test_1 PORT MAP (
clock => clock_sig,
data => data_sig,
rdreq => rdreq_sig,
wrreq => wrreq_sig,
empty => empty_sig,
full => full_sig,
q => q_sig
);
| gpl-3.0 | cf78c839e662d87ae88636512f51b903 | 0.53202 | 2.47561 | false | true | false | false |
boztalay/OldProjects | FPGA/Tests/ipcore_dir/FIFO.vhd | 1 | 5,651 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file FIFO.vhd when simulating
-- the core, FIFO. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY FIFO IS
port (
din: IN std_logic_VECTOR(7 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
empty: OUT std_logic;
full: OUT std_logic);
END FIFO;
ARCHITECTURE FIFO_a OF FIFO IS
-- synthesis translate_off
component wrapped_FIFO
port (
din: IN std_logic_VECTOR(7 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
empty: OUT std_logic;
full: OUT std_logic);
end component;
-- Configuration specification
for all : wrapped_FIFO use entity XilinxCoreLib.fifo_generator_v5_1(behavioral)
generic map(
c_has_int_clk => 0,
c_rd_freq => 1,
c_wr_response_latency => 1,
c_has_srst => 0,
c_enable_rst_sync => 1,
c_has_rd_data_count => 0,
c_din_width => 8,
c_has_wr_data_count => 0,
c_full_flags_rst_val => 1,
c_implementation_type => 2,
c_family => "spartan3",
c_use_embedded_reg => 0,
c_has_wr_rst => 0,
c_wr_freq => 1,
c_use_dout_rst => 1,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 1,
c_dout_width => 8,
c_msgon_val => 1,
c_rd_depth => 16,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_error_injection_type => 0,
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 4,
c_has_wr_ack => 0,
c_use_ecc => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 4,
c_use_fwft_data_count => 0,
c_has_almost_empty => 0,
c_rd_data_count_width => 4,
c_enable_rlocs => 0,
c_wr_pntr_width => 4,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 4,
c_preload_regs => 0,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 12,
c_wr_depth => 16,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_thresh_assert_val => 2,
c_has_valid => 0,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 13,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "512x36",
c_count_type => 0,
c_prog_full_type => 0,
c_memory_type => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_FIFO
port map (
din => din,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
dout => dout,
empty => empty,
full => full);
-- synthesis translate_on
END FIFO_a;
| mit | 7af54ed003678a7ccdcf161ecb459525 | 0.541143 | 3.488272 | false | false | false | false |
DaveyPocket/btrace448 | core/vga/textDevice.vhd | 1 | 1,004 | -- Btrace 448
-- Text Device - Draws text
--
-- Bradley Boccuzzi
-- 2016
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity textDevice is
port(clk: in std_logic;
row: in std_logic_vector(4 downto 0);
col: in std_logic_vector(6 downto 0);
pixel_x, pixel_y: in std_logic_vector(9 downto 0);
dev_on: out std_logic;
rgb: out std_logic_vector(2 downto 0));
end textDevice;
architecture arch of textDevice is
constant char: std_logic_vector(6 downto 0) := "1000001"; -- 0x41, 'A'
signal dout: std_logic_vector(7 downto 0);
signal ison: std_logic;
signal addr: std_logic_vector(10 downto 0);
begin
-- This should make a stripe of letter As down the screen
addr <= char & pixel_y(3 downto 0);
fr: entity work.font_rom port map(clk, addr, dout);
ison <= '1' when dout(to_integer(unsigned(pixel_x(2 downto 0)))) = '1' and pixel_x(9 downto 3) = col else '0';
rgb <= "111" when ison = '1' else "000";
dev_on <= ison;
end arch;
| gpl-3.0 | 070e03074243388154df4ea16d29ade0 | 0.654382 | 2.828169 | false | false | false | false |
peladex/RHD2132_FPGA | quartus/test_spi_de0/test_spi_slaves.vhd | 1 | 5,242 | -----------------------------------------------------------------------------------------------------------------------
-- Author:
--
-- Create Date: 09/11/2016 -- dd/mm/yyyy
-- Module Name: test_spi_slaves
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Este bloque instancia dos bloques spi escalvos tal que la salida de datos de uno esta conectada a la entrada
-- de datos del otro. Lo mismo sucede con la salida que indica un dato valido y la entrada write enable. Por lo tanto,
-- si un bloque recibe un dato, en el proximo ciclo spi ese dato sera enviado por el otro bloque spi.
--
-----------------------------------------------------------------------------------------------------------------------
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
LIBRARY lpm;
USE lpm.lpm_components.ALL;
ENTITY test_spi_slaves IS
PORT(
m_clk : in std_logic; -- master clock
m_reset : in std_logic; -- master reset
---- serial interface 1 ----
slave1_ssel_i : in std_logic := 'X'; -- spi bus slave select line
slave1_sck_i : in std_logic := 'X'; -- spi bus sck
slave1_mosi_i : in std_logic := 'X'; -- spi bus mosi output
slave1_miso_o : out std_logic := 'X'; -- spi bus spi_miso_i input
---- serial interface 2 ----
slave2_ssel_i : in std_logic := 'X'; -- spi bus slave select line
slave2_sck_i : in std_logic := 'X'; -- spi bus sck
slave2_mosi_i : in std_logic := 'X'; -- spi bus mosi output
slave2_miso_o : out std_logic := 'X' -- spi bus spi_miso_i input
);
END test_spi_slaves;
ARCHITECTURE synth OF test_spi_slaves IS
---- COMPONENTS
COMPONENT spi_slave IS
Generic (
N : positive := 16; -- 32bit serial word length is default
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
CPHA : std_logic := '0'; -- CPOL = clock polarity, CPHA = clock phase.
PREFETCH : positive := 2); -- prefetch lookahead cycles
Port (
clk_i : in std_logic := 'X'; -- internal interface clock (clocks di/do registers)
spi_ssel_i : in std_logic := 'X'; -- spi bus slave select line
spi_sck_i : in std_logic := 'X'; -- spi bus sck clock (clocks the shift register core)
spi_mosi_i : in std_logic := 'X'; -- spi bus mosi input
spi_miso_o : out std_logic := 'X'; -- spi bus spi_miso_o output
di_req_o : out std_logic; -- preload lookahead data request line
di_i : in std_logic_vector (N-1 downto 0) := (others => 'X'); -- parallel load data in (clocked in on rising edge of clk_i)
wren_i : in std_logic := 'X'; -- user data write enable
wr_ack_o : out std_logic; -- write acknowledge
do_valid_o : out std_logic; -- do_o data valid strobe, valid during one clk_i rising edge.
do_o : out std_logic_vector (N-1 downto 0); -- parallel output (clocked out on falling clk_i)
--- debug ports: can be removed for the application circuit ---
do_transfer_o : out std_logic; -- debug: internal transfer driver
wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher
rx_bit_next_o : out std_logic; -- debug: internal rx bit
state_dbg_o : out std_logic_vector (3 downto 0); -- debug: internal state register
sh_reg_dbg_o : out std_logic_vector (N-1 downto 0) -- debug: internal shift register
);
END COMPONENT;
---- SIGNALS
SIGNAL sg_slave1_di, sg_slave2_di : std_logic_vector(15 downto 0);
SIGNAL sg_slave1_wren, sg_slave2_wren : std_logic;
BEGIN
---- INSTANCES
SLAVE_1: spi_slave PORT MAP (
clk_i => m_clk,
spi_ssel_i => slave1_ssel_i,
spi_sck_i => slave1_sck_i,
spi_mosi_i => slave1_mosi_i,
spi_miso_o => slave1_miso_o,
di_i => sg_slave1_di,
wren_i => sg_slave1_wren,
do_valid_o => sg_slave1_wren,
do_o => sg_slave1_di
);
SLAVE_2: spi_slave PORT MAP (
clk_i => m_clk,
spi_ssel_i => slave2_ssel_i,
spi_sck_i => slave2_sck_i,
spi_mosi_i => slave2_mosi_i,
spi_miso_o => slave2_miso_o,
di_i => sg_slave2_di,
wren_i => sg_slave2_wren,
do_valid_o => sg_slave2_wren,
do_o => sg_slave2_di
);
END synth; | gpl-3.0 | 3c24cfad541df0b61b80d94ebedf33d3 | 0.471385 | 3.977238 | false | false | false | false |
fkolacek/FIT-VUT | INP2/fpga/lcdctrl.vhd | 1 | 10,257 | -- lcdctrl.vhd : High-level LCD controller with BUSY
-- Copyright (C) 2011/2012 Brno University of Technology,
-- Faculty of Information Technology
-- Author(s): Zdenek Vasicek <xvasic11 AT stud.fit.vutbr.cz>
--
-- LICENSE TERMS
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. All advertising materials mentioning features or use of this software
-- or firmware must display the following acknowledgement:
--
-- This product includes software developed by the University of
-- Technology, Faculty of Information Technology, Brno and its
-- contributors.
--
-- 4. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software or firmware is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id$
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity lcd_controller is
generic (
CMDLEN : integer := 10*10000; -- doba trvani prikazu (1 ms @ 20MHz ~ 10000)
LCD2x16 : boolean := False -- radic pro 2x16 nebo 1x16 LCD displej
);
port (
RST : in std_logic;
CLK : in std_logic;
-- interni rozhrani
DATA_IN : in std_logic_vector (7 downto 0);
WRITE_EN : in std_logic;
BUSY : out std_logic;
--- rozhrani LCD displeje
DISPLAY_RS : out std_logic;
DISPLAY_DATA : inout std_logic_vector(7 downto 0);
DISPLAY_RW : out std_logic;
DISPLAY_EN : out std_logic := '1'
);
end lcd_controller;
architecture behavioral of lcd_controller is
type FSMState is (init, init0, init1, init2, init3, idle, w0, w1, w2, w3, wa0, wa1, wa2, wa3);
function lcdaddrbits(islcd2x16: boolean) return integer is
begin
-- pragma translate off
-- pro simulaci vzdy 1 radkovy displej
return 4;
-- pragma translate on
if (islcd2x16) then return 5; end if;
return 4;
end function;
function lcdhas2rows(islcd2x16: boolean) return boolean is
begin
-- pragma translate off
-- pro simulaci vzdy 1 radkovy displej
return false;
-- pragma translate on
return (islcd2x16);
end function;
signal pstate : FSMState := init; -- FSM present state
signal nstate : FSMState; -- FSM next state
signal addr_reg : std_logic_vector(lcdaddrbits(LCD2x16)-1 downto 0) := (others => '0');
signal addr_inc : std_logic;
signal data_reg : std_logic_vector(7 downto 0);
signal init_data : std_logic_vector(8 downto 0);
signal datareg_en : std_logic;
signal data_sel : std_logic_vector(1 downto 0);
signal t_cnt : integer range 0 to CMDLEN-1 := 0;
signal t_lst : std_logic := '0';
signal t_en : std_logic;
constant INIT_ITEMS : integer := 5 + 8*2;
signal init_cnt : integer range 0 to INIT_ITEMS-1;
signal init_inc : std_logic;
signal init_lst : std_logic;
signal addr_data : std_logic_vector(7 downto 0);
begin
DISPLAY_RS <= '1' when (data_sel="11") else -- write char
init_data(8);
init_data <= "000111000" when (init_cnt=0) else -- Set Function
"000000001" when (init_cnt=1) else -- Clear Display
"000000010" when (init_cnt=2) else -- Cursor Home
"000001100" when (init_cnt=3) else -- Display on/off Control
"000000110" when (init_cnt=4) else -- Entry Mode Set
"001010000" when (init_cnt=5) else -- Own character #0x02, #0x0A
"100000001" when (init_cnt=6) else
"001010001" when (init_cnt=7) else
"100000001" when (init_cnt=8) else
"001010010" when (init_cnt=9) else
"100000001" when (init_cnt=10) else
"001010011" when (init_cnt=11) else
"100000101" when (init_cnt=12) else
"001010100" when (init_cnt=13) else
"100001001" when (init_cnt=14) else
"001010101" when (init_cnt=15) else
"100011111" when (init_cnt=16) else
"001010110" when (init_cnt=17) else
"100001000" when (init_cnt=18) else
"001010111" when (init_cnt=19) else
"100000100" when (init_cnt=20) else
"000000000";
DISPLAY_DATA <= init_data(7 downto 0) when (data_sel="01") else
addr_data when (data_sel="10") else -- set addr
data_reg when (data_sel="11") else -- write char
(others => 'Z');
addr_data <= "1" & addr_reg(4) & "00" & addr_reg(3 downto 0) when lcdhas2rows(LCD2x16) else -- LCD 2x16 (FITkit 2.x)
"1" & addr_reg(3) & "000" & addr_reg(2 downto 0); -- LCD 1x16 (FITkit 1.x)
process (RST, CLK)
begin
if (RST = '1') then
t_cnt <= 0;
elsif (CLK'event) and (CLK = '1') then
if (t_en = '1') then
t_lst <= '0';
if (t_cnt /= (CMDLEN-1)) then
t_cnt <= t_cnt + 1;
else
t_cnt <= 0;
t_lst <= '1';
end if;
end if;
end if;
end process;
-- data register
process(CLK, RST)
begin
if (RST = '1') then
data_reg <= (others => '0');
addr_reg <= (others => '0');
init_cnt <= 0;
elsif (CLK='1') and (CLK'event) then
if (WRITE_EN='1') and (datareg_en='1') then
data_reg <= DATA_IN;
end if;
if (addr_inc = '1') then
addr_reg <= addr_reg + 1;
end if;
if (init_inc = '1') then
init_cnt <= init_cnt + 1;
end if;
end if;
end process;
init_lst <= '1' when init_cnt = (INIT_ITEMS - 1) else '0';
-- FSM present state
process(CLK, RST)
begin
if (RST = '1') then
pstate <= init;
elsif (CLK='1') and (CLK'event) then
pstate <= nstate;
end if;
end process;
-- FSM next state logic, output logic
process(pstate, WRITE_EN, t_lst, init_lst)
begin
nstate <= init;
DISPLAY_RW <= '0';
DISPLAY_EN <= '0';
data_sel <= "00";
datareg_en <= '0';
BUSY <= '1';
t_en <= '1';
addr_inc <= '0';
init_inc <= '0';
case pstate is
when init =>
nstate <= init0;
-- Display Init
when init0 =>
nstate <= init0;
if (t_lst = '1') then
nstate <= init1;
end if;
data_sel <= "01";
when init1 =>
nstate <= init1;
if (t_lst = '1') then
nstate <= init2;
end if;
data_sel <= "01";
DISPLAY_EN <= '1';
when init2 =>
nstate <= init2;
if (t_lst = '1') then
nstate <= init3;
end if;
data_sel <= "01";
when init3 =>
nstate <= init3;
if (t_lst = '1') then
init_inc <= '1';
if (init_lst = '1') then
nstate <= idle;
else
nstate <= init0;
end if;
end if;
data_sel <= "01";
-- Idle
when idle =>
BUSY <= '0';
t_en <= '0';
datareg_en <= '1';
nstate <= idle;
if (WRITE_EN = '1') then
nstate <= wa0;
end if;
-- Write address
when wa0 =>
nstate <= wa0;
if (t_lst = '1') then
nstate <= wa1;
end if;
data_sel <= "10";
when wa1 =>
nstate <= wa1;
if (t_lst = '1') then
nstate <= wa2;
end if;
data_sel <= "10";
DISPLAY_EN <= '1';
when wa2 =>
nstate <= wa2;
if (t_lst = '1') then
nstate <= wa3;
end if;
data_sel <= "10";
when wa3 =>
nstate <= wa3;
if (t_lst = '1') then
nstate <= w0;
addr_inc <= '1';
end if;
data_sel <= "10";
-- Write character
when w0 =>
nstate <= w0;
if (t_lst = '1') then
nstate <= w1;
end if;
data_sel <= "11";
when w1 =>
nstate <= w1;
if (t_lst = '1') then
nstate <= w2;
end if;
data_sel <= "11";
DISPLAY_EN <= '1';
when w2 =>
nstate <= w2;
if (t_lst = '1') then
nstate <= w3;
end if;
data_sel <= "11";
when w3 =>
nstate <= w3;
if (t_lst = '1') then
nstate <= idle;
end if;
data_sel <= "11";
end case;
end process;
end behavioral;
| apache-2.0 | 7ac7afea3bfad2547e8b6cf8d2e89086 | 0.518378 | 3.845894 | false | false | false | false |
DaveyPocket/btrace448 | btrace/controller.vhd | 1 | 2,655 | -- Btrace 448
-- Controller
--
-- Bradley Boccuzzi
-- 2016
library ieee;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.btrace_pack.all;
entity controller is
port(clk, rst: in std_logic;
-- Control outputs
init_x, init_y, inc_x, inc_y: out std_logic;
set_vector, set_org: out std_logic;
next_obj, start_search: out std_logic;
clr_z_reg, clr_hit: out std_logic;
store: out std_logic;
paint: out std_logic;
done: out std_logic;
-- Status inputs
last_x, last_y, last_obj, obj_valid, start: in std_logic);
end controller;
architecture arch of controller is
-- Controller states
type states_t is (s_idle, s_start, s_set, s_wait, s_next, s_done);
signal controller_state: states_t := s_idle;
begin
process(clk, rst)
begin
if rst = '1' then
controller_state <= s_idle;
elsif rising_edge(clk) then
case controller_state is
when s_idle =>
if start = '1' then
controller_state <= s_start;
end if;
when s_start =>
controller_state <= s_set;
when s_set =>
controller_state <= s_wait;
when s_wait =>
controller_state <= s_next;
when s_next =>
if last_obj = '0' then
controller_state <= s_wait;
else
if last_x = '0' then
controller_state <= s_start;
else
if last_y = '0' then
controller_state <= s_start;
else
controller_state <= s_done;
end if;
end if;
end if;
when others =>
if start = '1' then
controller_state <= s_done;
else
controller_state <= s_idle;
end if;
end case;
end if;
end process;
clr_hit <= '1' when controller_state = s_start else '0';
clr_z_reg <= '1' when controller_state = s_start else '0';
init_x <= '1' when (controller_state = s_idle) or ((controller_state = s_next) and ((last_obj and last_x) = '1') and (last_y = '0')) else '0';
inc_y <= '1' when ((controller_state = s_next) and ((last_obj and last_x) = '1') and (last_y = '0')) else '0';
inc_x <= '1' when ((controller_state = s_next) and (last_obj = '1') and (last_x = '0')) else '0';
init_y <= '1' when (controller_state = s_idle) else '0';
set_vector <= '1' when controller_state = s_set else '0';
set_org <= '1' when controller_state = s_set else '0';
store <= '1' when (controller_state = s_wait) and (obj_valid = '1') else '0';
paint <= '1' when (controller_state = s_next) and (last_obj = '1') else '0';
next_obj <= '1' when (controller_state = s_next) else '0';
start_search <= '1' when (controller_state = s_start) else '0';
done <= '1' when (controller_state = s_done) else '0';
end arch;
| gpl-3.0 | 726625838b676b8c1ad68f90ced05cc4 | 0.612053 | 2.765625 | false | false | false | false |
pyrohaz/SSD1306_VHDLImplementation | SPI.vhd | 1 | 2,088 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SPI is
generic(
BitWidth: natural := 8;
Prescaler: natural := 0;
Master: std_logic := '1';
CPHA: std_logic := '1'; --Rising edge = 1, Falling edge = 0
CPOL: std_logic := '0' --Idle high = 1, Idle low = 0
);
port(
ClkO, DO, CS, Bsy: out std_logic;
ClkI, DI, Rst, Trig: in std_logic;
PDI: in std_logic_vector(BitWidth-1 downto 0); --Parallel data in
PDO: out std_logic_vector(BitWidth-1 downto 0) --Parallel data out
);
end SPI;
architecture A of SPI is
constant CSTog: std_logic := '1';
type States is (CSLow, CSHigh, DShift);
signal State: States := CSHigh;
signal DataI, DataO: std_logic_vector(BitWidth-1 downto 0);
signal Presc: unsigned(7 downto 0);
signal ClkOv: std_logic;
signal DCnt: unsigned(4 downto 0) := to_unsigned(BitWidth, 5);
signal TA, TAA: std_logic := '0';
begin
process(ClkI, DI, Rst, ClkOv)
begin
if(Rst = '0') then
State <= CSHigh;
CS <= '1';
DO <= '0';
ClkO <= '0';
TA <= '0';
TAA <= '0';
elsif(rising_edge(ClkI)) then
TAA <= TA;
TA <= Trig;
--Rising edge
if(TAA = '0' and TA = '1') then
DataO <= PDI;
State <= CSLow;
end if;
if(Presc(Prescaler) = '1') then
Presc <= (others => '0');
if(Master = '1') then
case State is
when CSHigh =>
Bsy <= '0';
if(CSTog = '1') then CS <= '1'; end if;
DCnt <= to_unsigned(BitWidth, 5);
DO <= '0';
ClkOv <= '0';
when CSLow =>
Bsy <= '1';
State <= DShift;
CS <= '0';
DO <= DataO(7);
when DShift =>
if(DCnt = "000") then
State <= CSHigh;
PDO <= DataI;
end if;
if(ClkOv = CPHA) then
DO <= DataO(to_integer(DCnt-1));
else
DataI(7 downto 0) <= DataI(6 downto 0) & DI;
DCnt <= DCnt - 1;
end if;
ClkOv <= not ClkOv;
end case;
else --Slave not yet implemented!
end if;
else
Presc <= Presc + 1;
end if;
end if;
ClkO <= ClkOv xor CPOL;
end process;
end A; | mit | ed70672e1f08a4ca22ae723d239c370a | 0.54454 | 2.758256 | false | false | false | false |
rpereira-dev/ENSIIE | UE/S3/microarchi/bus_ia_save/plus12.vhd | 1 | 7,829 | -- ########################################################################
-- $Software: busiac
-- $section : hardware component
-- $Id: plus12.vhd 325 2015-06-03 12:47:32Z ia $
-- $HeadURL: svn://lunix120.ensiie.fr/ia/cours/archi/projet/busiac/vhdl/plus12.vhd $
-- $Author : Ivan Auge (Email: [email protected])
-- ########################################################################
--
-- This file is part of the BUSIAC software: Copyright (C) 2010 by I. Auge.
--
-- This program is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at your
-- option) any later version.
--
-- BUSIAC software is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY ; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
-- Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with the GNU C Library; see the file COPYING. If not, write to the Free
-- Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
-- ######################################################################*/
-------------------------------------------------------------------------------
-- Ce module additionne 2 nombres de 12 bits signés.
-- Ses E/S sont les bus busin et busout.
--
-- Input:
-- busin_ctl (43 DOWNTO 40) : not used
-- busin_asrc(39 DOWNTO 32) : adresse emetteur (E_ADR)
-- busin_ades(31 DOWNTO 24) : adresse destination (MYADR)
-- busin_data(23 DOWNTO 12) : operande B en complement a 2
-- busin_data(11 DOWNTO 0) : operande A en complement a 2
--
-- Output:
-- busout_ctl (43 DOWNTO 40) : "0000"
-- busout_asrc(39 DOWNTO 32) : MYADR
-- busout_ades(31 DOWNTO 24) : E_ADR
-- busout_data(23) : V (overflow)
-- busout_data(22) : C (retenue sortante)
-- busout_data(21) : N (résultat négatif)
-- busout_data(20) : Z (résultat nul)
-- busout_data(19 DOWNTO 12) : "00000000"
-- busout_data(11 DOWNTO 0) : résultat en complément a 2 (A+B)
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.all;
ENTITY plus12 IS
GENERIC(
MYADR : STD_LOGIC_VECTOR(7 downto 0) := x"C0" ); -- 192
PORT(
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
-- interface busin
busin : in STD_LOGIC_VECTOR(43 DOWNTO 0);
busin_valid : in STD_LOGIC;
busin_eated : out STD_LOGIC;
-- interface busout
busout : OUT STD_LOGIC_VECTOR(43 DOWNTO 0);
busout_valid : OUT STD_LOGIC;
busout_eated : IN STD_LOGIC;
-- debug
debug : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END plus12;
ARCHITECTURE Montage OF plus12 IS
TYPE T_CMD_LoadNoop IS (LOAD, NOOP);
-- partie operative
-- le registre de transfert de busin vers busout
SIGNAL CMD_tft : T_CMD_LoadNoop;
SIGNAL R_tft : STD_LOGIC_VECTOR(43 DOWNTO 0);
-- le registre resultat de A+B, ov
-- on etend R sur 13 bits pour avoir la retenue
SIGNAL CMD_res : T_CMD_LoadNoop;
SIGNAL R_res : STD_LOGIC_VECTOR(12 DOWNTO 0);
-- les operandes A et B (1 bit de plus pour la retenue)
SIGNAL A,B : STD_LOGIC_VECTOR (12 DOWNTO 0); -- V1
-- bits de retenue et de somme de A+B -- V1
SIGNAL r,s : STD_LOGIC_VECTOR (12 DOWNTO 0); -- V1
-- SIGNAL A,B : SIGNED (12 DOWNTO 0); -- V2
-- l' adresse destination
SIGNAL busin_ades : STD_LOGIC_VECTOR ( 7 DOWNTO 0);
-- message résulat
SIGNAL mess_resultat : STD_LOGIC_VECTOR (43 DOWNTO 0);
-- partie controle
TYPE STATE_TYPE IS (ST_READ, ST_WRITE_TFT, ST_COMPUTE, ST_WRITE_SUM);
SIGNAL state : STATE_TYPE;
BEGIN
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
busin_ades <= busin(31 DOWNTO 24) ;
a <= "0" & R_tft(23 DOWNTO 12) ; -- V1
b <= "0" & R_tft(11 DOWNTO 0) ; -- V1
-- a <= SIGNED (R_tft(23 DOWNTO 12)) ; -- V2
-- b <= SIGNED (R_tft(11 DOWNTO 0)) ; -- V2
mess_resultat(43 DOWNTO 40) <= "0000";
mess_resultat(39 DOWNTO 32) <= MYADR;
mess_resultat(31 DOWNTO 24) <= R_tft(39 DOWNTO 32);
mess_resultat(23) <= -- overflow
'1' WHEN a(11)='1' AND b(11)='1' AND R_res(11)='0' ELSE -- N+N=P
'1' WHEN a(11)='0' AND b(11)='0' AND R_res(11)='1' ELSE -- P+P=N
'0' ;
mess_resultat(22) <= R_res(12); -- cout
mess_resultat(21) <= R_res(11); -- signe
mess_resultat(20) <= -- null
'1' WHEN R_res(11 downto 0) = x"000" ELSE '0';
mess_resultat(19 DOWNTO 12) <= "00000000" ;
mess_resultat(11 DOWNTO 0) <= R_res(11 DOWNTO 0);
-- s,r <-- a + b; -- V1
s <= a XOR b XOR r; -- V1
r(0) <= '0'; -- V1
r(12 DOWNTO 1) <= -- V1
( a(11 DOWNTO 0) AND b(11 DOWNTO 0) ) OR -- V1
( a(11 DOWNTO 0) AND r(11 DOWNTO 0) ) OR -- V1
( r(11 DOWNTO 0) AND b(11 DOWNTO 0) ); -- V1
PROCESS (clk)
BEGIN IF clk'EVENT AND clk = '1' THEN
-- R_tft
if ( CMD_tft = LOAD ) then
R_tft <= busin;
end if;
-- R_res
if ( CMD_res = LOAD ) then
R_res(12 DOWNTO 0) <= s ; -- V1
-- R_res(12 DOWNTO 0) <= STD_LOGIC_VECTOR(a + b) ; -- V2
end if;
END IF; END PROCESS;
-------------------------------------------------------------------------------
-- Partie Controle
-------------------------------------------------------------------------------
-- Inputs: busin_valid busout_eated
-- Outputs: busin_eated busout_valid, CMD_res, CMD_tft, busout
-------------------------------------------------------------------------------
-- fonction de transitition
PROCESS (reset,clk)
BEGIN
IF reset = '1' THEN
state <= ST_READ;
ELSIF clk'EVENT AND clk = '1' THEN
CASE state IS
WHEN ST_READ =>
IF busin_valid = '1' and busin_ades = MYADR THEN
state <= ST_COMPUTE;
ELSIF busin_valid = '1' and busin_ades /= MYADR THEN
state <= ST_WRITE_TFT;
END IF;
WHEN ST_COMPUTE =>
state <= ST_WRITE_SUM;
WHEN ST_WRITE_SUM =>
IF busout_eated = '1' THEN
state <= ST_READ;
END IF;
WHEN ST_WRITE_TFT =>
IF busout_eated = '1' THEN
state <= ST_READ;
END IF;
END CASE;
END IF;
END PROCESS;
-- fonction de sortie
WITH state SELECT busin_eated <=
'1' WHEN ST_READ,
'0' WHEN OTHERS;
WITH state SELECT busout_valid <=
'1' WHEN ST_WRITE_TFT,
'1' WHEN ST_WRITE_SUM,
'0' WHEN OTHERS;
WITH state SELECT CMD_res <=
LOAD WHEN ST_Compute,
NOOP WHEN OTHERS;
WITH state SELECT CMD_tft <=
LOAD WHEN ST_READ,
NOOP WHEN OTHERS;
WITH state SELECT busout <=
mess_resultat WHEN ST_WRITE_SUM,
R_tft WHEN OTHERS;
END Montage;
| gpl-3.0 | 940d5732f739ec8c1e9a0db99657920f | 0.479478 | 3.776437 | false | false | false | false |
DaveyPocket/btrace448 | core/reg.vhd | 1 | 661 | -- Btrace 448
-- Register
--
-- Bradley Boccuzzi
-- 2016
library ieee;
use ieee.std_logic_1164.all;
entity reg is
generic(N: integer := 8);
port(clk, rst: in std_logic;
en, clr: in std_logic;
D: in std_logic_vector(N-1 downto 0);
Q: out std_logic_vector(N-1 downto 0) := (others => '0');
init: in std_logic_vector(N-1 downto 0));
end reg;
architecture arch of reg is
constant zeros: std_logic_vector(N-1 downto 0) := (others => '0');
begin
process(clk, rst)
begin
if rst = '1' then
Q <= zeros;
elsif rising_edge(clk) then
if clr = '1' then
Q <= init;
elsif en = '1' then
Q <= D;
end if;
end if;
end process;
end arch;
| gpl-3.0 | 1a6ea88fc5fc75011473072a8d3e8456 | 0.618759 | 2.623016 | false | false | false | false |
boztalay/OldProjects | FPGA/Sys_SecondTimer/Comp_DecadeCnt4bit.vhd | 1 | 1,802 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 16:37:34 07/30/2009
-- Design Name:
-- Module Name: Comp_DecadeCnt4bit - Behavioral
-- Project Name: Decade Counter
-- Target Devices:
-- Tool versions:
-- Description: A decade counter with synchronous reset.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.10 - First draft written
-- Revision 0.15 - Syntax errors fixed
-- Revision 0.30 - UCF File written
-- Revision 1.00 - Generated programming file with successful hardware test
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Comp_DecadeCnt4bit is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
outputs : out STD_LOGIC_VECTOR (3 downto 0));
end Comp_DecadeCnt4bit;
architecture Behavioral of Comp_DecadeCnt4bit is
begin
main : process(clock, reset) is
variable output_var : STD_LOGIC_VECTOR (3 downto 0) := b"0001";
begin
if falling_edge(clock) then
case output_var is
when b"0001" =>
output_var := b"0010";
when b"0010" =>
output_var := b"0100";
when b"0100" =>
output_var := b"1000";
when b"1000" =>
output_var := b"0001";
when others =>
output_var := b"0001";
end case;
if reset = '1' then
output_var := b"0001";
end if;
end if;
outputs <= output_var;
end process main;
end Behavioral;
| mit | 161149a93f1e9c668a3c284d0e98c792 | 0.5899 | 3.604 | false | false | false | false |
AfterRace/SoC_Project | vivado/project/project.srcs/sources_1/ipshared/tsotnep/volume_pregain_v1_0/75ddc6aa/hdl/Volume_Pregain_v1_0.vhd | 2 | 5,227 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Volume_Pregain_v1_0 is
generic (
-- Users to add parameters here
INTBIT_WIDTH : integer := 24;
-- FRACBIT_WIDTH : integer := 8; now, its calculated below, in port mapping
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_DATA_WIDTH : integer := 32;
C_S00_AXI_ADDR_WIDTH : integer := 4
);
port (
-- Users to add ports here
OUT_VOLCTRL_L : out signed((24 - 1) downto 0) := (others => '0'); -- 24 bit signed output
OUT_VOLCTRL_R : out signed((24 - 1) downto 0) := (others => '0'); -- 24 bit signed output
OUT_RDY : out STD_LOGIC;
IN_SIG_L : in signed((24 - 1) downto 0); --amplifier input signal 24-bit
IN_SIG_R : in signed((24 - 1) downto 0); --amplifier input signal 24-bit
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S00_AXI
s00_axi_aclk : in std_logic;
s00_axi_aresetn : in std_logic;
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_awprot : in std_logic_vector(2 downto 0);
s00_axi_awvalid : in std_logic;
s00_axi_awready : out std_logic;
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
s00_axi_wvalid : in std_logic;
s00_axi_wready : out std_logic;
s00_axi_bresp : out std_logic_vector(1 downto 0);
s00_axi_bvalid : out std_logic;
s00_axi_bready : in std_logic;
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_arprot : in std_logic_vector(2 downto 0);
s00_axi_arvalid : in std_logic;
s00_axi_arready : out std_logic;
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_rresp : out std_logic_vector(1 downto 0);
s00_axi_rvalid : out std_logic;
s00_axi_rready : in std_logic
);
end Volume_Pregain_v1_0;
architecture arch_imp of Volume_Pregain_v1_0 is
-- component declaration
component Volume_Pregain_v1_0_S00_AXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 4;
INTBIT_WIDTH : integer;
FRACBIT_WIDTH : integer
);
port (
OUT_VOLCTRL_L : out signed((24 - 1) downto 0) := (others => '0'); -- 24 bit signed output
OUT_VOLCTRL_R : out signed((24 - 1) downto 0) := (others => '0'); -- 24 bit signed output
OUT_RDY : out STD_LOGIC;
IN_SIG_L : in signed((24 - 1) downto 0); --amplifier input signal 24-bit
IN_SIG_R : in signed((24 - 1) downto 0); --amplifier input signal 24-bit
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component Volume_Pregain_v1_0_S00_AXI;
begin
-- Instantiation of Axi Bus Interface S00_AXI
Volume_Pregain_v1_0_S00_AXI_inst : Volume_Pregain_v1_0_S00_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH,
INTBIT_WIDTH => INTBIT_WIDTH,
FRACBIT_WIDTH => C_S00_AXI_DATA_WIDTH - INTBIT_WIDTH
)
port map (
OUT_VOLCTRL_L => OUT_VOLCTRL_L,
OUT_VOLCTRL_R => OUT_VOLCTRL_R,
OUT_RDY => OUT_RDY,
IN_SIG_L => IN_SIG_L,
IN_SIG_R => IN_SIG_R,
S_AXI_ACLK => s00_axi_aclk,
S_AXI_ARESETN => s00_axi_aresetn,
S_AXI_AWADDR => s00_axi_awaddr,
S_AXI_AWPROT => s00_axi_awprot,
S_AXI_AWVALID => s00_axi_awvalid,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WDATA => s00_axi_wdata,
S_AXI_WSTRB => s00_axi_wstrb,
S_AXI_WVALID => s00_axi_wvalid,
S_AXI_WREADY => s00_axi_wready,
S_AXI_BRESP => s00_axi_bresp,
S_AXI_BVALID => s00_axi_bvalid,
S_AXI_BREADY => s00_axi_bready,
S_AXI_ARADDR => s00_axi_araddr,
S_AXI_ARPROT => s00_axi_arprot,
S_AXI_ARVALID => s00_axi_arvalid,
S_AXI_ARREADY => s00_axi_arready,
S_AXI_RDATA => s00_axi_rdata,
S_AXI_RRESP => s00_axi_rresp,
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready
);
-- Add user logic here
-- User logic ends
end arch_imp;
| lgpl-3.0 | 729a54e822b7fbd932c98465f5cb78ff | 0.614693 | 2.676395 | false | false | false | false |
bargei/NoC264 | NoC264_3x3/intra_prediction_node.vhd | 1 | 19,937 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
entity intra_prediction_node is
generic (
data_width : integer := 64;
addr_width : integer := 1;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
-- recv interface to network
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
-- send interface to network
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic;
--debugging
s_intra_idle : out std_logic;
s_intra_data_rxd : out std_logic;
s_intra_write_sample : out std_logic;
s_intra_start_pred : out std_logic;
s_intra_start_tx_loop : out std_logic;
s_intra_start_tx_loop_hold : out std_logic;
s_intra_tx : out std_logic;
s_intra_tx_hold : out std_logic;
s_intra_tx_gen_next : out std_logic;
s_intra_dequeue_rx : out std_logic
);
end entity intra_prediction_node;
architecture fsmd of intra_prediction_node is
---------------------------------------------------------------------------
--- Constants -------------------------------------------------------------
---------------------------------------------------------------------------
constant size_of_byte : integer := 8;
--- for parsing cmd byte --------------------------------------------------
constant cmd_start : integer := 0;
constant cmd_bytes : integer := 1;
constant cmd_end : integer := cmd_start + cmd_bytes * size_of_byte - 1;
--- for parsing set samples command ---------------------------------------
constant wr_addr_start : integer := cmd_end + 1;
constant wr_addr_bytes : integer := 1;
constant wr_addr_end : integer := wr_addr_start + wr_addr_bytes * size_of_byte - 1;
constant samples_start : integer := wr_addr_end + 1;
constant samples_bytes : integer := 4;
constant samples_end : integer := samples_start + samples_bytes * size_of_byte - 1;
--- for parsing perform prediction command --------------------------------
constant block_size_start : integer := cmd_end + 1;
constant block_size_bytes : integer := 1;
constant block_size_end : integer := block_size_start + block_size_bytes * size_of_byte - 1;
constant mode_start : integer := block_size_end + 1;
constant mode_bytes : integer := 1;
constant mode_end : integer := mode_start + mode_bytes * size_of_byte - 1;
constant availible_mask_start : integer := mode_end + 1;
constant availible_mask_bytes : integer := 4;
constant availible_mask_end : integer := availible_mask_start + availible_mask_bytes * size_of_byte - 1;
constant identifier_start : integer := availible_mask_end + 1;
constant identifier_bytes : integer := 1;
constant identifier_end : integer := identifier_start + identifier_bytes * size_of_byte - 1;
--- commands
constant cmd_write_sample : std_logic_vector(7 downto 0) := "00000001";
constant cmd_predict : std_logic_vector(7 downto 0) := "00000010";
--- tx constants ----------------------------------------------------------
constant flit_size : integer := data_width;
constant tx_len_16x16 : integer := 32; --todo --(16*16)/(flit_size/size_of_byte);
constant tx_len_8x8 : integer := 16; --todo --(8*8)/(flit_size/size_of_byte);
constant tx_len_4x4 : integer := 8; --todo --todo
constant tx_loop_max_16x16 : integer := tx_len_16x16;--integer( real(tx_len_16x16) / real(flit_size/size_of_byte) + 0.5 );
constant tx_loop_max_8x8 : integer := tx_len_8x8 ;--integer( real(tx_len_8x8 ) / real(flit_size/size_of_byte) + 0.5 );
constant tx_loop_max_4x4 : integer := tx_len_4x4 ;--integer( real(tx_len_4x4 ) / real(flit_size/size_of_byte) + 0.5 );
constant header_pad_size : integer := 0;
constant header_pad : std_logic_vector := std_logic_vector(to_unsigned(0, header_pad_size));
---------------------------------------------------------------------------
--- Components ------------------------------------------------------------
---------------------------------------------------------------------------
component intra_prediction_core is
port(
clk : in std_logic;
rst : in std_logic;
--interface to enable "set samples" command
sample_data : in std_logic_vector(31 downto 0);
sample_write_addr : in unsigned(7 downto 0);
sample_write_enable : in std_logic;
--interface to enable "perform prediction" command
block_size : in unsigned(7 downto 0);
mode : in unsigned(7 downto 0);
row_addr : in unsigned(7 downto 0);
availible_mask : in std_logic_vector(31 downto 0);
row_data : out unsigned(127 downto 0)
);
end component intra_prediction_core;
component priority_encoder is
generic(
encoded_word_size : integer := 3
);
Port(
input : in std_logic_vector(2**encoded_word_size-1 downto 0);
output : out std_logic_vector(encoded_word_size-1 downto 0)
);
end component priority_encoder;
---------------------------------------------------------------------------
-- Types ------------------------------------------------------------------
---------------------------------------------------------------------------
type intra_node_ctrl_states is ( intra_idle,
intra_data_rxd,
intra_write_sample,
intra_start_pred,
intra_start_tx_loop,
intra_start_tx_loop_hold,
intra_tx,
intra_tx_hold,
intra_tx_gen_next,
intra_tx_gen_next_hold,
intra_dequeue_rx );
---------------------------------------------------------------------------
--- Signals ---------------------------------------------------------------
---------------------------------------------------------------------------
signal sample_data : std_logic_vector(31 downto 0);
signal sample_write_addr : unsigned(7 downto 0);
signal sample_write_enable : std_logic;
signal block_size : unsigned(7 downto 0);
signal mode : unsigned(7 downto 0);
signal row_addr : unsigned(7 downto 0);
signal availible_mask : std_logic_vector(31 downto 0);
signal row_data : unsigned(127 downto 0);
signal wr_sample_data : std_logic;
signal wr_sample_write_addr : std_logic;
signal wr_sample_write_enable : std_logic;
signal wr_block_size : std_logic;
signal wr_mode : std_logic;
signal wr_row_addr : std_logic;
signal wr_availible_mask : std_logic;
signal wr_row_data : std_logic;
signal parsed_cmd : std_logic_vector(7 downto 0);
signal parsed_wr_addr : std_logic_vector(7 downto 0);
signal parsed_samples : std_logic_vector(31 downto 0);
signal parsed_block_size : std_logic_vector(7 downto 0);
signal parsed_mode : std_logic_vector(7 downto 0);
signal parsed_availible_mask : std_logic_vector(31 downto 0);
signal parsed_identifier : std_logic_vector(7 downto 0);
signal tx_loop_count_q : unsigned(7 downto 0);
signal tx_loop_count_d : unsigned(7 downto 0);
signal tx_loop_done : std_logic;
signal last_loop : std_logic;
signal send_data_internal : std_logic_vector(flit_size-1 downto 0);
signal intra_state : intra_node_ctrl_states;
signal next_intra_state : intra_node_ctrl_states;
signal selected_vc_encoder : std_logic_vector(vc_sel_width-1 downto 0);
signal row_seg_full : std_logic_vector(127 downto 0);
signal row_seg : std_logic_vector(flit_size-1 downto 0);
signal selected_vc_q : std_logic_vector(vc_sel_width-1 downto 0);
signal selected_vc_d : std_logic_vector(vc_sel_width-1 downto 0);
signal padded_id : std_logic_vector(31 downto 0);
signal padded_block_size : std_logic_vector(31 downto 0);
begin
---------------------------------------------------------------------------
--- Datapath --------------------------------------------------------------
---------------------------------------------------------------------------
--- instantiate the intra prediction core --------------------------------
core0: component intra_prediction_core port map(
clk => clk ,
rst => rst ,
sample_data => sample_data ,
sample_write_addr => sample_write_addr ,
sample_write_enable => sample_write_enable ,
block_size => block_size ,
mode => mode ,
row_addr => row_addr ,
availible_mask => availible_mask ,
row_data => row_data
);
-- instantiate priority_encoder for vc selection
encoded0: component priority_encoder generic map (
encoded_word_size => vc_sel_width
) Port map(
input => data_in_buffer,
output => selected_vc_encoder
);
--- implement data parser -------------------------------------------------
parsed_cmd <= recv_data(cmd_end downto cmd_start );
parsed_wr_addr <= recv_data(wr_addr_end downto wr_addr_start );
parsed_samples <= recv_data(samples_end downto samples_start );
parsed_block_size <= recv_data(block_size_end downto block_size_start );
parsed_mode <= recv_data(mode_end downto mode_start );
parsed_availible_mask <= recv_data(availible_mask_end downto availible_mask_start);
parsed_identifier <= recv_data(identifier_end downto identifier_start);
--- hook up parsed data to intra prediction core --------------------------
sample_data <= parsed_samples;
sample_write_addr <= unsigned(parsed_wr_addr);
block_size <= unsigned(parsed_block_size);
mode <= unsigned(parsed_mode);
availible_mask <= parsed_availible_mask;
--- data path registers ---------------------------------------------------
dp_regs: process(clk, rst) begin
if rst = '1' then
tx_loop_count_q <= (others => '0');
selected_vc_q <= (others => '0');
elsif rising_edge(clk) then
tx_loop_count_q <= tx_loop_count_d;
selected_vc_q <= selected_vc_d;
end if;
end process;
--- tx loop check ---------------------------------------------------------
tx_loop_done <= '0' when tx_loop_count_q < tx_loop_max_16x16 and block_size = to_unsigned(16, 8) else
'0' when tx_loop_count_q < tx_loop_max_8x8 and block_size = to_unsigned(8, 8) else
'0' when tx_loop_count_q < tx_loop_max_4x4 and block_size = to_unsigned(4, 8) else
'1';
last_loop <= '0' when tx_loop_count_q < (tx_loop_max_16x16 - 1) and block_size = to_unsigned(16, 8) else
'0' when tx_loop_count_q < (tx_loop_max_8x8 - 1) and block_size = to_unsigned(8, 8) else
'0' when tx_loop_count_q < (tx_loop_max_4x4 - 1) and block_size = to_unsigned(4, 8) else
'1';
--- row read address generator --------------------------------------------
-- supports 128, 64, and 32 bit flit data feilds
assert flit_size = 128 or flit_size = 64 or flit_size = 32 report "intra_prediction_node: unsupported flit size" severity failure;
row_addr <= tx_loop_count_q when flit_size = 128 else -- tx's full row per flit
shift_right(tx_loop_count_q, 1) when flit_size = 64 else -- tx's half row per flit
shift_right(tx_loop_count_q, 2) when flit_size = 32 else -- tx's quarter row per flit
(others => '0');
--- row segment selection -------------------------------------------------
row_seg_full <= std_logic_vector(row_data) when flit_size = 128 else
std_logic_vector(to_unsigned(0, 64)) & std_logic_vector(row_data(127 downto 64)) when flit_size = 64 and tx_loop_count_q(0) = '0' else
std_logic_vector(to_unsigned(0, 64)) & std_logic_vector(row_data(63 downto 0)) when flit_size = 64 and tx_loop_count_q(0) = '1' else
std_logic_vector(to_unsigned(0, 96)) & std_logic_vector(row_data(127 downto 96)) when flit_size = 32 and tx_loop_count_q(1 downto 0) = "00" else
std_logic_vector(to_unsigned(0, 96)) & std_logic_vector(row_data(95 downto 64)) when flit_size = 32 and tx_loop_count_q(1 downto 0) = "01" else
std_logic_vector(to_unsigned(0, 96)) & std_logic_vector(row_data(63 downto 32)) when flit_size = 32 and tx_loop_count_q(1 downto 0) = "10" else
std_logic_vector(to_unsigned(0, 96)) & std_logic_vector(row_data(31 downto 0) ) when flit_size = 32 and tx_loop_count_q(1 downto 0) = "11" else
(others => '0');
row_seg <= row_seg_full(flit_size-1 downto 0);
--- misc assignments ------------------------------------------------------
select_vc_read <= selected_vc_q;
padded_id <= std_logic_vector(to_unsigned(0, 24)) & parsed_identifier;
padded_block_size <= std_logic_vector(to_unsigned(0, 24)) & parsed_block_size;
---------------------------------------------------------------------------
--- State Machine ---------------------------------------------------------
---------------------------------------------------------------------------
--- FSM State Register ----------------------------------------------------
state_reg: process(clk, rst) begin
if rst = '1' then
intra_state <= intra_idle;
elsif rising_edge(clk) then
intra_state <= next_intra_state;
end if;
end process;
--- FSM Update Logic ------------------------------------------------------
state_update: process(parsed_cmd, intra_state, tx_loop_done) begin
-- default
next_intra_state <= intra_state;
-- wait for new data to arrive
if intra_state = intra_idle and or_reduce(data_in_buffer) = '1' then
next_intra_state <= intra_data_rxd;
end if;
-- write samples to intra_core
if intra_state = intra_data_rxd and parsed_cmd = cmd_write_sample then
next_intra_state <= intra_write_sample;
end if;
if intra_state = intra_write_sample then
next_intra_state <= intra_dequeue_rx;
end if;
-- perform prediction
if intra_state = intra_data_rxd and parsed_cmd = cmd_predict then
next_intra_state <= intra_start_pred;
end if;
if intra_state = intra_start_pred and ready_to_send = '1' then
next_intra_state <= intra_start_tx_loop;
end if;
--transmit result
if intra_state = intra_start_tx_loop then
next_intra_state <= intra_start_tx_loop_hold;
end if;
if intra_state = intra_start_tx_loop_hold and ready_to_send = '1' then
next_intra_state <= intra_tx;
end if;
if intra_state = intra_tx then
next_intra_state <= intra_tx_hold;
end if;
if intra_state = intra_tx_hold and tx_loop_done = '0' then
next_intra_state <= intra_tx_gen_next;
end if;
if intra_state = intra_tx_hold and tx_loop_done = '1' then
next_intra_state <= intra_dequeue_rx;
end if;
if intra_state = intra_tx_gen_next then
next_intra_state <= intra_tx_gen_next_hold;
end if;
if intra_state = intra_tx_gen_next_hold and ready_to_send = '1' then
next_intra_state <= intra_tx;
end if;
if intra_state = intra_dequeue_rx then
next_intra_state <= intra_idle;
end if;
end process;
--- FSM output logic ------------------------------------------------------
sample_write_enable <= '1' when intra_state = intra_write_sample else '0';
tx_loop_count_d <= (others => '0') when intra_state = intra_start_pred else
tx_loop_count_q + to_unsigned(1, 8) when intra_state = intra_tx else
tx_loop_count_q;
send_data <= header_pad & padded_block_size & padded_id when intra_state = intra_start_tx_loop or intra_state = intra_start_tx_loop_hold else
row_seg;
selected_vc_d <= selected_vc_encoder when intra_state = intra_data_rxd else selected_vc_q;
dequeue <= "01" when selected_vc_q = "0" and intra_state = intra_dequeue_rx else
"10" when selected_vc_q = "1" and intra_state = intra_dequeue_rx else
"00";
dest_addr <= std_logic_vector(to_unsigned(7, addr_width));
set_tail_flit <= '1' when last_loop = '1' else '0';
send_flit <= '1' when intra_state = intra_start_tx_loop else
'1' when intra_state = intra_tx else
'0';
--- debug outputs ---------------------------------------------------------
s_intra_idle <= '1' when intra_state = intra_idle else '0';
s_intra_data_rxd <= '1' when intra_state = intra_data_rxd else '0';
s_intra_write_sample <= '1' when intra_state = intra_write_sample else '0';
s_intra_start_pred <= '1' when intra_state = intra_start_pred else '0';
s_intra_start_tx_loop <= '1' when intra_state = intra_start_tx_loop else '0';
s_intra_start_tx_loop_hold <= '1' when intra_state = intra_start_tx_loop_hold else '0';
s_intra_tx <= '1' when intra_state = intra_tx else '0';
s_intra_tx_hold <= '1' when intra_state = intra_tx_hold else '0';
s_intra_tx_gen_next <= '1' when intra_state = intra_tx_gen_next else '0';
s_intra_dequeue_rx <= '1' when intra_state = intra_dequeue_rx else '0';
end architecture fsmd; | mit | 03305dcd37d42a7a86b6f7ae0b34f37a | 0.490746 | 4.037465 | false | false | false | false |
bargei/NoC264 | NoC264_2x2/intra_prediction_core.vhd | 1 | 35,531 | library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.math_real.all;
entity intra_prediction_core is
port(
clk : in std_logic;
rst : in std_logic;
--interface to enable "set samples" command
sample_data : in std_logic_vector(31 downto 0);
sample_write_addr : in unsigned(7 downto 0);
sample_write_enable : in std_logic;
--interface to enable "perform prediction" command
block_size : in unsigned(7 downto 0);
mode : in unsigned(7 downto 0);
row_addr : in unsigned(7 downto 0);
availible_mask : in std_logic_vector(31 downto 0);
row_data : out unsigned(127 downto 0)
);
end entity intra_prediction_core;
architecture rtl of intra_prediction_core is
constant dc_default : unsigned := "0000000010000000";
type row is array(15 downto 0) of unsigned(7 downto 0);
type macroblock_type is array (15 downto 0) of row;
signal macroblock : macroblock_type;
type sample_reg is array(8 downto 0) of std_logic_vector(31 downto 0);
signal samples_d, samples_q : sample_reg;
type samples_type is array(32 downto 0) of std_logic_vector(7 downto 0);
signal the_samples : samples_type;
type sample_array_row is array(16 downto 0) of unsigned(9 downto 0);
type sample_array_type is array(16 downto 0) of sample_array_row;
signal sample_array : sample_array_type;
signal dc_4_value : unsigned(15 downto 0);
signal dc_8_value : unsigned(15 downto 0);
signal dc_16_value : unsigned(15 downto 0);
signal dc_value : unsigned(9 downto 0);
type plane_value_row_type is array(16 downto 0) of signed(33 downto 0);
type plane_value_array_type is array(16 downto 0) of plane_value_row_type;
type plane_hv_type is array(7 downto 0) of signed(17 downto 0);
signal h,v : plane_hv_type;
signal a,b,c : signed(25 downto 0);
begin
--register file for holding sample data
reg_file: process(clk, rst) begin
if rst = '1' then
samples_q <= (others => (others => '0'));
elsif rising_edge(clk) then
samples_q <= samples_d;
end if;
end process;
reg_file_update: for i in 8 downto 0 generate
samples_d(i) <= sample_data when sample_write_enable = '1' and i = to_integer(unsigned(sample_write_addr))
else samples_q(i);
end generate;
--place neighbor samples into sample array
-- y\x-->
-- | \ |<--0--->| |<--1--->| |<--2--->| |<--3--->| |<-4->|
-- | \ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
-- | \___________________________________________________
--___ V 0 |0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
-- 1 |17 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
-- 5 2 |18 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
-- 3 |19 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
--___ 4 |20 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
-- 5 |21 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
-- 6 6 |22 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
-- 7 |23 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
--___ 8 |24 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
-- 9 |25 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
-- 7 10 |26 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
-- 11 |27 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
--___ 12 |28 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
-- 13 |29 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
-- 8 14 |30 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
-- 15 |31 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
--___ 16 |32 mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb mb
the_samples(0) <= samples_q(0)(31 downto 24);
the_samples(1) <= samples_q(0)(23 downto 16);
the_samples(2) <= samples_q(0)(15 downto 8 );
the_samples(3) <= samples_q(0)(7 downto 0 );
the_samples(4) <= samples_q(1)(31 downto 24);
the_samples(5) <= samples_q(1)(23 downto 16);
the_samples(6) <= samples_q(1)(15 downto 8 );
the_samples(7) <= samples_q(1)(7 downto 0 );
the_samples(8) <= samples_q(2)(31 downto 24);
the_samples(9) <= samples_q(2)(23 downto 16);
the_samples(10) <= samples_q(2)(15 downto 8 );
the_samples(11) <= samples_q(2)(7 downto 0 );
the_samples(12) <= samples_q(3)(31 downto 24);
the_samples(13) <= samples_q(3)(23 downto 16);
the_samples(14) <= samples_q(3)(15 downto 8 );
the_samples(15) <= samples_q(3)(7 downto 0 );
the_samples(16) <= samples_q(4)(7 downto 0 );
the_samples(17) <= samples_q(5)(31 downto 24);
the_samples(18) <= samples_q(5)(23 downto 16);
the_samples(19) <= samples_q(5)(15 downto 8 );
the_samples(20) <= samples_q(5)(7 downto 0 );
the_samples(21) <= samples_q(6)(31 downto 24);
the_samples(22) <= samples_q(6)(23 downto 16);
the_samples(23) <= samples_q(6)(15 downto 8 );
the_samples(24) <= samples_q(6)(7 downto 0 );
the_samples(25) <= samples_q(7)(31 downto 24);
the_samples(26) <= samples_q(7)(23 downto 16);
the_samples(27) <= samples_q(7)(15 downto 8 );
the_samples(28) <= samples_q(7)(7 downto 0 );
the_samples(29) <= samples_q(8)(31 downto 24);
the_samples(30) <= samples_q(8)(23 downto 16);
the_samples(31) <= samples_q(8)(15 downto 8 );
the_samples(32) <= samples_q(8)(7 downto 0 );
sample_array( 0 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 0 )));
sample_array( 0 )( 1 ) <= unsigned(std_logic_vector'("00"&the_samples( 1 )));
sample_array( 0 )( 2 ) <= unsigned(std_logic_vector'("00"&the_samples( 2 )));
sample_array( 0 )( 3 ) <= unsigned(std_logic_vector'("00"&the_samples( 3 )));
sample_array( 0 )( 4 ) <= unsigned(std_logic_vector'("00"&the_samples( 4 )));
sample_array( 0 )( 5 ) <= unsigned(std_logic_vector'("00"&the_samples( 5 )));
sample_array( 0 )( 6 ) <= unsigned(std_logic_vector'("00"&the_samples( 6 )));
sample_array( 0 )( 7 ) <= unsigned(std_logic_vector'("00"&the_samples( 7 )));
sample_array( 0 )( 8 ) <= unsigned(std_logic_vector'("00"&the_samples( 8 )));
sample_array( 0 )( 9 ) <= unsigned(std_logic_vector'("00"&the_samples( 9 )));
sample_array( 0 )( 10 ) <= unsigned(std_logic_vector'("00"&the_samples( 10 )));
sample_array( 0 )( 11 ) <= unsigned(std_logic_vector'("00"&the_samples( 11 )));
sample_array( 0 )( 12 ) <= unsigned(std_logic_vector'("00"&the_samples( 12 )));
sample_array( 0 )( 13 ) <= unsigned(std_logic_vector'("00"&the_samples( 13 )));
sample_array( 0 )( 14 ) <= unsigned(std_logic_vector'("00"&the_samples( 14 )));
sample_array( 0 )( 15 ) <= unsigned(std_logic_vector'("00"&the_samples( 15 )));
sample_array( 0 )( 16 ) <= unsigned(std_logic_vector'("00"&the_samples( 16 )));
sample_array( 1 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 17 )));
sample_array( 2 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 18 )));
sample_array( 3 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 19 )));
sample_array( 4 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 20 )));
sample_array( 5 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 21 )));
sample_array( 6 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 22 )));
sample_array( 7 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 23 )));
sample_array( 8 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 24 )));
sample_array( 9 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 25 )));
sample_array( 10 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 26 )));
sample_array( 11 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 27 )));
sample_array( 12 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 28 )));
sample_array( 13 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 29 )));
sample_array( 14 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 30 )));
sample_array( 15 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 31 )));
sample_array( 16 )( 0 ) <= unsigned(std_logic_vector'("00"&the_samples( 32 )));
--calculate dc values
dc_4_value <= shift_right(("000000"&sample_array(1)(0)) +
("000000"&sample_array(2)(0)) +
("000000"&sample_array(3)(0)) +
("000000"&sample_array(4)(0)) +
("000000"&sample_array(0)(1)) +
("000000"&sample_array(0)(2)) +
("000000"&sample_array(0)(3)) +
("000000"&sample_array(0)(4)) +
to_unsigned(4, 16), 3) when (and_reduce(availible_mask(31 downto 28)) and
and_reduce(availible_mask(15 downto 12))) = '1' else
shift_right(("000000"&sample_array(1)(0)) +
("000000"&sample_array(2)(0)) +
("000000"&sample_array(3)(0)) +
("000000"&sample_array(4)(0)) +
to_unsigned(2, 16), 2) when and_reduce(availible_mask(31 downto 28)) = '1' else
shift_right(("000000"&sample_array(0)(1)) +
("000000"&sample_array(0)(2)) +
("000000"&sample_array(0)(3)) +
("000000"&sample_array(0)(4)) +
to_unsigned(2, 16), 2) when and_reduce(availible_mask(15 downto 12)) = '1' else
dc_default;
--dc_8_value <= shift_right(("000000"&sample_array(1)(0)) +
-- ("000000"&sample_array(2)(0)) +
-- ("000000"&sample_array(3)(0)) +
-- ("000000"&sample_array(4)(0)) +
-- ("000000"&sample_array(5)(0)) +
-- ("000000"&sample_array(6)(0)) +
-- ("000000"&sample_array(7)(0)) +
-- ("000000"&sample_array(8)(0)) +
-- ("000000"&sample_array(0)(1)) +
-- ("000000"&sample_array(0)(2)) +
-- ("000000"&sample_array(0)(3)) +
-- ("000000"&sample_array(0)(4)) +
-- ("000000"&sample_array(0)(5)) +
-- ("000000"&sample_array(0)(6)) +
-- ("000000"&sample_array(0)(7)) +
-- ("000000"&sample_array(0)(8)) +
-- to_unsigned(8, 16), 4) when (and_reduce(availible_mask(31 downto 24)) and
-- and_reduce(availible_mask(15 downto 8))) = '1' else
-- shift_right(("000000"&sample_array(1)(0)) +
-- ("000000"&sample_array(2)(0)) +
-- ("000000"&sample_array(3)(0)) +
-- ("000000"&sample_array(4)(0)) +
-- ("000000"&sample_array(4)(0)) +
-- ("000000"&sample_array(5)(0)) +
-- ("000000"&sample_array(6)(0)) +
-- ("000000"&sample_array(7)(0)) +
-- ("000000"&sample_array(8)(0)) +
-- to_unsigned(4, 16), 3) when and_reduce(availible_mask(31 downto 24)) = '1' else
-- shift_right(("000000"&sample_array(0)(1)) +
-- ("000000"&sample_array(0)(2)) +
-- ("000000"&sample_array(0)(3)) +
-- ("000000"&sample_array(0)(4)) +
-- ("000000"&sample_array(0)(4)) +
-- ("000000"&sample_array(0)(5)) +
-- ("000000"&sample_array(0)(6)) +
-- ("000000"&sample_array(0)(7)) +
-- ("000000"&sample_array(0)(8)) +
-- to_unsigned(4, 16), 3) when and_reduce(availible_mask(15 downto 8)) = '1' else
-- dc_default;
dc_16_value <= shift_right(("000000"&sample_array(1 )(0)) +
("000000"&sample_array(2 )(0)) +
("000000"&sample_array(3 )(0)) +
("000000"&sample_array(4 )(0)) +
("000000"&sample_array(5 )(0)) +
("000000"&sample_array(6 )(0)) +
("000000"&sample_array(7 )(0)) +
("000000"&sample_array(8 )(0)) +
("000000"&sample_array(9 )(0)) +
("000000"&sample_array(10)(0)) +
("000000"&sample_array(11)(0)) +
("000000"&sample_array(12)(0)) +
("000000"&sample_array(13)(0)) +
("000000"&sample_array(14)(0)) +
("000000"&sample_array(15)(0)) +
("000000"&sample_array(16)(0)) +
("000000"&sample_array(0)(1 )) +
("000000"&sample_array(0)(2 )) +
("000000"&sample_array(0)(3 )) +
("000000"&sample_array(0)(4 )) +
("000000"&sample_array(0)(5 )) +
("000000"&sample_array(0)(6 )) +
("000000"&sample_array(0)(7 )) +
("000000"&sample_array(0)(8 )) +
("000000"&sample_array(0)(9 )) +
("000000"&sample_array(0)(10)) +
("000000"&sample_array(0)(11)) +
("000000"&sample_array(0)(12)) +
("000000"&sample_array(0)(13)) +
("000000"&sample_array(0)(14)) +
("000000"&sample_array(0)(15)) +
("000000"&sample_array(0)(16)) +
to_unsigned(16, 16), 5) when and_reduce(availible_mask(31 downto 0)) = '1' else
shift_right(("000000"&sample_array(1 )(0)) +
("000000"&sample_array(2 )(0)) +
("000000"&sample_array(3 )(0)) +
("000000"&sample_array(4 )(0)) +
("000000"&sample_array(5 )(0)) +
("000000"&sample_array(6 )(0)) +
("000000"&sample_array(7 )(0)) +
("000000"&sample_array(8 )(0)) +
("000000"&sample_array(9 )(0)) +
("000000"&sample_array(10)(0)) +
("000000"&sample_array(11)(0)) +
("000000"&sample_array(12)(0)) +
("000000"&sample_array(13)(0)) +
("000000"&sample_array(14)(0)) +
("000000"&sample_array(15)(0)) +
("000000"&sample_array(16)(0)) +
to_unsigned(8, 16), 4) when and_reduce(availible_mask(31 downto 16)) = '1' else
shift_right(("000000"&sample_array(0)(1 )) +
("000000"&sample_array(0)(2 )) +
("000000"&sample_array(0)(3 )) +
("000000"&sample_array(0)(4 )) +
("000000"&sample_array(0)(5 )) +
("000000"&sample_array(0)(6 )) +
("000000"&sample_array(0)(7 )) +
("000000"&sample_array(0)(8 )) +
("000000"&sample_array(0)(9 )) +
("000000"&sample_array(0)(10)) +
("000000"&sample_array(0)(11)) +
("000000"&sample_array(0)(12)) +
("000000"&sample_array(0)(13)) +
("000000"&sample_array(0)(14)) +
("000000"&sample_array(0)(15)) +
("000000"&sample_array(0)(16)) +
to_unsigned(8, 16), 4) when and_reduce(availible_mask(15 downto 0)) = '1' else
dc_default;
dc_value <= dc_4_value(9 downto 0) when block_size = to_unsigned(4, 8) else
--dc_8_value(9 downto 0) when block_size = to_unsigned(8, 8) else
dc_16_value(9 downto 0) when block_size = to_unsigned(16, 8) else
"1010101010"; --make errors obvious
-- some values needed for plane mode
a <= signed(shift_left( ("0000000000000000"&sample_array(0)(16)) + ("000000000000000"&sample_array(16)(0)), 4)) when block_size = 16 else
signed(shift_left( ("0000000000000000"&sample_array(0)(8 )) + ("000000000000000"&sample_array(8 )(0)), 4));
b <= shift_right( to_signed(5, 8) * h(7) + to_signed(32, 26) , 6) when block_size = 16 else
shift_right( to_signed(34, 8) * h(7) + to_signed(32, 26) , 6);
c <= shift_right( to_signed(5, 8) * v(7) + to_signed(32, 26) , 6) when block_size = 16 else
shift_right( to_signed(34, 8) * v(7) + to_signed(32, 26) , 6);
v(0) <= to_signed(1, 8) * (signed(sample_array(9)(0)) - signed(sample_array(7)(0))) when block_size = 16 else
to_signed(1, 8) * (signed(sample_array(5)(0)) - signed(sample_array(3)(0)));
h(0) <= to_signed(1, 8) * (signed(sample_array(0)(9)) - signed(sample_array(0)(7))) when block_size = 16 else
to_signed(1, 8) * (signed(sample_array(0)(5)) - signed(sample_array(0)(3)));
calc_h_v_plane: for xy in 7 downto 1 generate
v(xy) <= v(xy-1) + to_signed(xy+1,8) * (signed(sample_array(9+xy)(0)) - signed(sample_array(7-xy)(0))) when block_size = 16 else
v(xy-1) + to_signed(xy+1,8) * (signed(sample_array(5+xy)(0)) - signed(sample_array(3-xy)(0))) when block_size = 8 and xy <= 3 else
v(xy-1);
h(xy) <= h(xy-1) + to_signed(xy+1,8) * (signed(sample_array(0)(9+xy)) - signed(sample_array(0)(7-xy))) when block_size = 16 else
h(xy-1) + to_signed(xy+1,8) * (signed(sample_array(0)(5+xy)) - signed(sample_array(0)(3-xy))) when block_size = 8 and xy <= 3 else
h(xy-1);
end generate;
--calculate predicted samples
calculate_samples_row: for i in 16 downto 1 generate
calculate_samples_col: for j in 16 downto 1 generate
constant x : integer := j-1;
constant y : integer := i-1;
constant zVR : integer := 2 * x - y;
constant zVR_mod_2 : integer := zVR mod 2;
constant zVR_sign : integer := integer(sign(real(zVR)));
constant zHD : integer := 2 * y - x;
constant zHD_mod_2 : integer := zHD mod 2;
constant zHD_sign : integer := integer(sign(real(zHD)));
constant y_mod_2 : integer := y mod 2;
constant zHU : integer := x + 2 * y;
constant zHU_mod_2 : integer := zHU mod 2;
constant zHU_13_comp : integer := integer(sign(real(zHU-13)));
signal plane_pre_clip : plane_value_array_type;
signal plane_value : sample_array_type;
begin
plane_pre_clip(i)(j) <= shift_right(("00000000"&a) + b * to_signed(x-7, 8) + c * to_signed(y-7, 8) + to_signed(16, 34) , 5) when block_size = 16 else
shift_right(("00000000"&a) + b * to_signed(x-3, 8) + c * to_signed(y-3, 8) + to_signed(16, 34) , 5);
plane_value(i)(j) <= to_unsigned(0, 10) when plane_pre_clip(i)(j) < to_signed(0, 34) else
to_unsigned(255, 10) when plane_pre_clip(i)(j) > to_signed(255, 34) else
unsigned(plane_pre_clip(i)(j)(9 downto 0));
sample_array(i)(j) <=
--vertical
sample_array(i-1)(j) when mode = 0 else
--horizontal
sample_array(i)(j-1) when mode = 1 else
--dc prediction
dc_value when mode = 2 else
--diag down left
shift_right(sample_array(0)(7) + to_unsigned(3,2) * sample_array(0)(8)(7 downto 0) + to_unsigned(2,10) , 2) when mode = 3 and block_size = 4 and x = 3 and y = 3 else
shift_right(sample_array(0)((y+x+1) mod 17) + to_unsigned(2,2) * sample_array(0)((y+x+2) mod 17)(7 downto 0) + sample_array(0)((y+x+3) mod 17) + to_unsigned(2,10) , 2) when mode = 3 and block_size = 4 and (not(x = 3 and y = 3)) and ((y+x+3) <= 16) else
--shift_right(sample_array(0)(15) + to_unsigned(3,2) * sample_array(0)(16)(7 downto 0) + to_unsigned(2,10) , 2) when mode = 3 and block_size = 8 and x = 7 and y = 7 else
--shift_right(sample_array(0)((y+x+1) mod 17) + to_unsigned(2,2) * sample_array(0)((y+x+2) mod 17)(7 downto 0) + sample_array(0)((y+x+3) mod 17) + to_unsigned(2,10) , 2) when mode = 3 and block_size = 8 and (not(x = 7 and y = 7)) and ((y+x+3) <= 16) else
--diag down right
shift_right(sample_array(abs(y-x-1))(0) + to_unsigned(2,2) * sample_array(abs(y-x))(0)(7 downto 0) + sample_array(abs(y-x+1))(0) + to_unsigned(2,10) , 2) when mode = 4 and (block_size = 4) and (y > x) and ((y-x-1) >= 0)else
shift_right(sample_array(0)(abs(x-y-1)) + to_unsigned(2,2) * sample_array(0)(abs(x-y))(7 downto 0) + sample_array(0)(abs(x-y+1)) + to_unsigned(2,10) , 2) when mode = 4 and (block_size = 4) and (y < x) and ((x-y-1) >= 0)else
shift_right(sample_array(1)(0) + to_unsigned(2,2) * sample_array(0)(0)(7 downto 0) + sample_array(0)(1) + to_unsigned(2,10) , 2) when mode = 4 and (block_size = 4) and (y = x) else
--vertical right
shift_right(sample_array(0)(abs(x - y/2 ) mod 17) + sample_array(0)(abs(x - y/2 + 1) mod 17)(7 downto 0) + to_unsigned(1,10) , 1) when mode = 5 and (block_size = 4) and (zVR_mod_2 = 0) and ((x - y/2 ) >= 0) else
shift_right(sample_array(0)(abs(x - y/2 -1) mod 17) + to_unsigned(2,2) * sample_array(0)(abs(x - y/2 ) mod 17)(7 downto 0) + sample_array(0)(abs(x - y/2+1) mod 17) + to_unsigned(2,10) , 2) when mode = 5 and (block_size = 4) and (zVR_mod_2 = 1) and ((x - y/2 -1) >= 0) else
shift_right(sample_array(1)(0) + to_unsigned(2,2) * sample_array(0)(0)(7 downto 0) + sample_array(0)(1) + to_unsigned(2,10) , 2) when mode = 5 and (block_size = 4) and (zVR = -1) else
shift_right(sample_array(y)(0) + to_unsigned(2,2) * sample_array(y-1)(0)(7 downto 0) + sample_array(y-2)(0) + to_unsigned(2,10) , 2) when mode = 5 and (block_size = 4) and (zVR < -1) and ((y-2) >= 0) else
--horizontal down
shift_right(sample_array(abs(y - x/2) mod 17)(0) + sample_array(abs(y - x/2 + 1) mod 17)(0)(7 downto 0) + to_unsigned(1,10) , 1) when mode = 6 and (block_size = 4) and (zHD_mod_2 = 0) and (zHD >= 0) and ((y - x/2) >= 0)else
shift_right(sample_array(abs(y - x/2-1) mod 17)(0) + to_unsigned(2,2) * sample_array(abs(y - x/2 ) mod 17)(0)(7 downto 0) + sample_array(abs(y - x/2 + 1) mod 17)(0) + to_unsigned(2,10) , 2) when mode = 6 and (block_size = 4) and (zHD_mod_2 = 1) and (zHD >= 0) and ((y - x/2 - 1) >= 0) else
shift_right(sample_array(0)(1) + to_unsigned(2,2) * sample_array(0)(0)(7 downto 0) + sample_array(1)(0) + to_unsigned(2,10) , 2) when mode = 6 and (block_size = 4) and (zHD = -1) else
shift_right(sample_array(0)(x) + to_unsigned(2,2) * sample_array(0)(x-1)(7 downto 0) + sample_array(0)(x-2) + to_unsigned(2,10) , 2) when mode = 6 and (block_size = 4) and (zHD < -1) and ((x-2) >= 0) else
--vertical left
shift_right(sample_array(0)((x + y /2 + 1) mod 17) + sample_array(0)((x+y/2+2) mod 17)(7 downto 0) + to_unsigned(1,10) , 1) when mode = 7 and (block_size = 4) and y_mod_2 = 0 and ((x + y/2+2) <= 16) else
shift_right(sample_array(0)((x + y /2 + 1) mod 17) + to_unsigned(2,2) * sample_array(0)((x+y/2+2) mod 17)(7 downto 0) + sample_array(0)((x+y/2+3) mod 17) + to_unsigned(2,10) , 2) when mode = 7 and (block_size = 4) and y_mod_2 /= 0 and ((x + y/2+3) <= 16) else
--horizontal up
shift_right(sample_array((y + x/2 + 1) mod 17)(0) + sample_array((y+x/2+2) mod 17)(0)(7 downto 0) + to_unsigned(1,10) , 1) when mode = 8 and ((block_size = 4 and zHU < 5) ) and (zHU >= 0) and zHU_mod_2 = 0 else
shift_right(sample_array((y + x/2 + 1) mod 17)(0) + to_unsigned(2,2) * sample_array((y+x/2+2) mod 17)(0)(7 downto 0) + sample_array((y+x/2+3) mod 17)(0) + to_unsigned(2,10) , 2) when mode = 8 and ((block_size = 4 and zHU < 5) ) and (zHU >= 0) and zHU_mod_2 = 1 else
--shift_right(sample_array(7)(0) + to_unsigned(3,2) * sample_array(8)(0)(7 downto 0) + to_unsigned(2,10) , 2) when mode = 8 and block_size = 8 and zHU = 13 else
shift_right(sample_array(3)(0) + to_unsigned(3,2) * sample_array(4)(0)(7 downto 0) + to_unsigned(2,10) , 2) when mode = 8 and block_size = 4 and zHU = 5 else
--sample_array(8)(0) when mode = 8 and block_size = 8 and zHU > 13 else
sample_array(4)(0) when mode = 8 and block_size = 4 and zHU > 5 else
--plane
plane_value(i)(j) when mode = 3 and (block_size = 16 or block_size = 8) else
"0000000001";
end generate;
end generate;
--assign calculated samples to output macro block
assign_smpls_2_mb_row: for i in 15 downto 0 generate
assign_smpls_2_mb_col: for j in 15 downto 0 generate
macroblock(i)(j) <= sample_array(i+1)(j+1)(7 downto 0);
end generate;
end generate;
--output selected macroblock row
row_data <= macroblock(0 )(0)¯oblock(0 )(1)¯oblock(0 )(2)¯oblock(0 )(3)¯oblock(0 )(4)¯oblock(0 )(5)¯oblock(0 )(6)¯oblock(0 )(7)¯oblock(0 )(8)¯oblock(0 )(9)¯oblock(0 )(10)¯oblock(0 )(11)¯oblock(0 )(12)¯oblock(0 )(13)¯oblock(0 )(14)¯oblock(0 )(15) when row_addr = to_unsigned(0 , 8) else
macroblock(1 )(0)¯oblock(1 )(1)¯oblock(1 )(2)¯oblock(1 )(3)¯oblock(1 )(4)¯oblock(1 )(5)¯oblock(1 )(6)¯oblock(1 )(7)¯oblock(1 )(8)¯oblock(1 )(9)¯oblock(1 )(10)¯oblock(1 )(11)¯oblock(1 )(12)¯oblock(1 )(13)¯oblock(1 )(14)¯oblock(1 )(15) when row_addr = to_unsigned(1 , 8) else
macroblock(2 )(0)¯oblock(2 )(1)¯oblock(2 )(2)¯oblock(2 )(3)¯oblock(2 )(4)¯oblock(2 )(5)¯oblock(2 )(6)¯oblock(2 )(7)¯oblock(2 )(8)¯oblock(2 )(9)¯oblock(2 )(10)¯oblock(2 )(11)¯oblock(2 )(12)¯oblock(2 )(13)¯oblock(2 )(14)¯oblock(2 )(15) when row_addr = to_unsigned(2 , 8) else
macroblock(3 )(0)¯oblock(3 )(1)¯oblock(3 )(2)¯oblock(3 )(3)¯oblock(3 )(4)¯oblock(3 )(5)¯oblock(3 )(6)¯oblock(3 )(7)¯oblock(3 )(8)¯oblock(3 )(9)¯oblock(3 )(10)¯oblock(3 )(11)¯oblock(3 )(12)¯oblock(3 )(13)¯oblock(3 )(14)¯oblock(3 )(15) when row_addr = to_unsigned(3 , 8) else
macroblock(4 )(0)¯oblock(4 )(1)¯oblock(4 )(2)¯oblock(4 )(3)¯oblock(4 )(4)¯oblock(4 )(5)¯oblock(4 )(6)¯oblock(4 )(7)¯oblock(4 )(8)¯oblock(4 )(9)¯oblock(4 )(10)¯oblock(4 )(11)¯oblock(4 )(12)¯oblock(4 )(13)¯oblock(4 )(14)¯oblock(4 )(15) when row_addr = to_unsigned(4 , 8) else
macroblock(5 )(0)¯oblock(5 )(1)¯oblock(5 )(2)¯oblock(5 )(3)¯oblock(5 )(4)¯oblock(5 )(5)¯oblock(5 )(6)¯oblock(5 )(7)¯oblock(5 )(8)¯oblock(5 )(9)¯oblock(5 )(10)¯oblock(5 )(11)¯oblock(5 )(12)¯oblock(5 )(13)¯oblock(5 )(14)¯oblock(5 )(15) when row_addr = to_unsigned(5 , 8) else
macroblock(6 )(0)¯oblock(6 )(1)¯oblock(6 )(2)¯oblock(6 )(3)¯oblock(6 )(4)¯oblock(6 )(5)¯oblock(6 )(6)¯oblock(6 )(7)¯oblock(6 )(8)¯oblock(6 )(9)¯oblock(6 )(10)¯oblock(6 )(11)¯oblock(6 )(12)¯oblock(6 )(13)¯oblock(6 )(14)¯oblock(6 )(15) when row_addr = to_unsigned(6 , 8) else
macroblock(7 )(0)¯oblock(7 )(1)¯oblock(7 )(2)¯oblock(7 )(3)¯oblock(7 )(4)¯oblock(7 )(5)¯oblock(7 )(6)¯oblock(7 )(7)¯oblock(7 )(8)¯oblock(7 )(9)¯oblock(7 )(10)¯oblock(7 )(11)¯oblock(7 )(12)¯oblock(7 )(13)¯oblock(7 )(14)¯oblock(7 )(15) when row_addr = to_unsigned(7 , 8) else
macroblock(8 )(0)¯oblock(8 )(1)¯oblock(8 )(2)¯oblock(8 )(3)¯oblock(8 )(4)¯oblock(8 )(5)¯oblock(8 )(6)¯oblock(8 )(7)¯oblock(8 )(8)¯oblock(8 )(9)¯oblock(8 )(10)¯oblock(8 )(11)¯oblock(8 )(12)¯oblock(8 )(13)¯oblock(8 )(14)¯oblock(8 )(15) when row_addr = to_unsigned(8 , 8) else
macroblock(9 )(0)¯oblock(9 )(1)¯oblock(9 )(2)¯oblock(9 )(3)¯oblock(9 )(4)¯oblock(9 )(5)¯oblock(9 )(6)¯oblock(9 )(7)¯oblock(9 )(8)¯oblock(9 )(9)¯oblock(9 )(10)¯oblock(9 )(11)¯oblock(9 )(12)¯oblock(9 )(13)¯oblock(9 )(14)¯oblock(9 )(15) when row_addr = to_unsigned(9 , 8) else
macroblock(10)(0)¯oblock(10)(1)¯oblock(10)(2)¯oblock(10)(3)¯oblock(10)(4)¯oblock(10)(5)¯oblock(10)(6)¯oblock(10)(7)¯oblock(10)(8)¯oblock(10)(9)¯oblock(10)(10)¯oblock(10)(11)¯oblock(10)(12)¯oblock(10)(13)¯oblock(10)(14)¯oblock(10)(15) when row_addr = to_unsigned(10, 8) else
macroblock(11)(0)¯oblock(11)(1)¯oblock(11)(2)¯oblock(11)(3)¯oblock(11)(4)¯oblock(11)(5)¯oblock(11)(6)¯oblock(11)(7)¯oblock(11)(8)¯oblock(11)(9)¯oblock(11)(10)¯oblock(11)(11)¯oblock(11)(12)¯oblock(11)(13)¯oblock(11)(14)¯oblock(11)(15) when row_addr = to_unsigned(11, 8) else
macroblock(12)(0)¯oblock(12)(1)¯oblock(12)(2)¯oblock(12)(3)¯oblock(12)(4)¯oblock(12)(5)¯oblock(12)(6)¯oblock(12)(7)¯oblock(12)(8)¯oblock(12)(9)¯oblock(12)(10)¯oblock(12)(11)¯oblock(12)(12)¯oblock(12)(13)¯oblock(12)(14)¯oblock(12)(15) when row_addr = to_unsigned(12, 8) else
macroblock(13)(0)¯oblock(13)(1)¯oblock(13)(2)¯oblock(13)(3)¯oblock(13)(4)¯oblock(13)(5)¯oblock(13)(6)¯oblock(13)(7)¯oblock(13)(8)¯oblock(13)(9)¯oblock(13)(10)¯oblock(13)(11)¯oblock(13)(12)¯oblock(13)(13)¯oblock(13)(14)¯oblock(13)(15) when row_addr = to_unsigned(13, 8) else
macroblock(14)(0)¯oblock(14)(1)¯oblock(14)(2)¯oblock(14)(3)¯oblock(14)(4)¯oblock(14)(5)¯oblock(14)(6)¯oblock(14)(7)¯oblock(14)(8)¯oblock(14)(9)¯oblock(14)(10)¯oblock(14)(11)¯oblock(14)(12)¯oblock(14)(13)¯oblock(14)(14)¯oblock(14)(15) when row_addr = to_unsigned(14, 8) else
macroblock(15)(0)¯oblock(15)(1)¯oblock(15)(2)¯oblock(15)(3)¯oblock(15)(4)¯oblock(15)(5)¯oblock(15)(6)¯oblock(15)(7)¯oblock(15)(8)¯oblock(15)(9)¯oblock(15)(10)¯oblock(15)(11)¯oblock(15)(12)¯oblock(15)(13)¯oblock(15)(14)¯oblock(15)(15) when row_addr = to_unsigned(15, 8) else
to_unsigned(0, 128);
--row_data <= (others => '1');
end architecture rtl; | mit | 4cfa3ac3f3b731fdfc541cfb6a2296a1 | 0.473108 | 3.567728 | false | false | false | false |
rpereira-dev/ENSIIE | UE/S3/microarchi/bus_ia/moduler.vhd | 1 | 3,919 | -------------------------------------------------------------------------------
-- Entrée
-- clk, reset : la clock et le reset
-- T : un tick ('1' ou '0')
-- E : un entier entre 0 et 7, controllant la vitesse du tick 'S'
--
-- Sortie
-- S : un tick plus ou moins lent en fonction de 'E',
-- généré à partir de 'T'
--
-- Pour E="000", un tick 'S' est généré tous les 2 ticks 'T'
-- Pour E="001", un tick 'S' est généré tous les 5 ticks 'T'
-- Pour E="010", un tick 'S' est généré tous les 7 ticks 'T'
-- Pour E="011", un tick 'S' est généré tous les 10 ticks 'T'
-- Pour E="100", un tick 'S' est généré tous les 12 ticks 'T'
-- Pour E="101", un tick 'S' est généré tous les 15 ticks 'T'
-- Pour E="110", un tick 'S' est généré tous les 17 ticks 'T'
-- Pour E="111", un tick 'S' est généré tous les 20 ticks 'T'
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
-- moduler
entity moduler is
port(
-- clock et reset
clk : in STD_LOGIC;
reset : in STD_LOGIC;
-- tick d'entrée
T : in STD_LOGIC;
-- config d'entrée
E2 : in STD_LOGIC;
E1 : in STD_LOGIC;
E0 : in STD_LOGIC;
-- tick de sortie
S : out STD_LOGIC
);
end moduler;
architecture montage of moduler is
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
-- registre de stockage des 3 bits en un vecteur
signal E : STD_LOGIC_VECTOR(2 downto 0);
-- la commande courante
type T_CMD is (INIT, COUNT);
signal CMD : T_CMD;
-- registre stockant la valeur du registre à charger
signal V_E : unsigned(7 downto 0);
-- registre de comptagne V_E => V_E - 1 => ... 0 => V_E => ...
signal C : unsigned(7 downto 0);
-- boolean vaux 1 si C est à 0, 0 sinon
signal C_IS_ZERO: STD_LOGIC;
-------------------------------------------------------------------------------
-- Partie Contrôle
-------------------------------------------------------------------------------
type STATE_TYPE is (
ST_INIT, ST_COUNT
);
signal state : STATE_TYPE;
begin
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
process (reset, clk, V_E)
begin
IF reset = '1' THEN
C <= V_E;
ELSIF clk'event and clk = '1' then
IF CMD = INIT THEN
C <= V_E;
ELSIF CMD = COUNT AND T = '1' THEN
C <= C - 1;
END IF;
end if;
end process;
C_IS_ZERO <= '1' WHEN C = 0 ELSE '0' ;
E(0) <= E0;
E(1) <= E1;
E(2) <= E2;
-------------------------------------------------------------------------------
-- Partie Contrôle
-------------------------------------------------------------------------------
-- Inputs: T
-- Outputs: S, CMD
-------------------------------------------------------------------------------
-- fonction de transitition
process (reset, clk)
begin
if reset = '1' then
state <= ST_INIT;
elsif clk'event and clk = '1' then
case state is
when ST_INIT =>
state <= ST_COUNT ;
when ST_COUNT =>
IF C_IS_ZERO = '1' THEN
state <= ST_INIT ;
END IF ;
end case;
end if;
end process;
-- fonction de sortie
with state select CMD <=
INIT when ST_INIT,
COUNT when ST_COUNT
;
with E select V_E <=
to_unsigned( 2, 8) when "000",
to_unsigned( 5, 8) when "001",
to_unsigned( 7, 8) when "010",
to_unsigned(10, 8) when "011",
to_unsigned(12, 8) when "100",
to_unsigned(15, 8) when "101",
to_unsigned(17, 8) when "110",
to_unsigned(20, 8) when "111"
;
-- on génère un tick si on a atteint 0 dans le compteur
S <= C_IS_ZERO;
end montage;
| gpl-3.0 | 0a19488f6a6d87573c8aaf983ebd4406 | 0.449742 | 3.464286 | false | false | false | false |
boztalay/OldProjects | FPGA/Sync_Mem/Sync_Mem_TB.vhd | 1 | 3,658 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:31:37 07/02/2010
-- Design Name:
-- Module Name: C:/Users/georgecuris/Desktop/Folders/FPGA/Projects/Current Projects/Systems/Sync_Mem/Sync_Mem_TB.vhd
-- Project Name: Sync_Mem
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Sync_Mem
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY Sync_Mem_TB IS
END Sync_Mem_TB;
ARCHITECTURE behavior OF Sync_Mem_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Sync_Mem
PORT(
clock : IN std_logic;
reset : IN std_logic;
RAM_wait : IN std_logic;
memory_data_bus : INOUT std_logic_vector(15 downto 0);
memory_address_bus : OUT std_logic_vector(22 downto 0);
RAM_ce : OUT std_logic;
RAM_lb : OUT std_logic;
RAM_ub : OUT std_logic;
RAM_adv : OUT std_logic;
RAM_cre : OUT std_logic;
RAM_clk : OUT std_logic;
RAM_oe : OUT std_logic;
RAM_we : OUT std_logic;
flash_ce : OUT std_logic
);
END COMPONENT;
--Inputs
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal RAM_wait : std_logic := '0';
--BiDirs
signal memory_data_bus : std_logic_vector(15 downto 0);
--Outputs
signal memory_address_bus : std_logic_vector(22 downto 0);
signal RAM_ce : std_logic;
signal RAM_lb : std_logic;
signal RAM_ub : std_logic;
signal RAM_adv : std_logic;
signal RAM_cre : std_logic;
signal RAM_clk : std_logic;
signal RAM_oe : std_logic;
signal RAM_we : std_logic;
signal flash_ce : std_logic;
-- Clock period definitions
constant clock_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Sync_Mem PORT MAP (
clock => clock,
reset => reset,
RAM_wait => RAM_wait,
memory_data_bus => memory_data_bus,
memory_address_bus => memory_address_bus,
RAM_ce => RAM_ce,
RAM_lb => RAM_lb,
RAM_ub => RAM_ub,
RAM_adv => RAM_adv,
RAM_cre => RAM_cre,
RAM_clk => RAM_clk,
RAM_oe => RAM_oe,
RAM_we => RAM_we,
flash_ce => flash_ce
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <= '1';
memory_data_bus <= "ZZZZZZZZZZZZZZZZ";
wait for 100 ns;
reset <= '0';
RAM_wait <= '0';
wait for 60 ns;
RAM_wait <= '1';
wait for 60 ns;
RAM_wait <= '0';
wait for 80 ns;
RAM_wait <= '1';
memory_data_bus <= x"5555";
wait for 100 ns;
RAM_wait <= '0';
wait;
end process;
END;
| mit | d2cf1e20a9920f9528f511b5c9a7ec8d | 0.549481 | 3.541142 | false | false | false | false |
freecores/usb_fpga_2_16 | examples/usb-fpga-1.2/lightshow/fpga/lightshow.vhd | 36 | 2,235 | library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity lightshow is
port(
led : out std_logic_vector(11 downto 0);
CLK : in std_logic -- 32 MHz
);
end lightshow;
--signal declaration
architecture RTL of lightshow is
type tPattern is array(11 downto 0) of integer range 0 to 15;
signal pattern1 : tPattern := (0, 1, 2, 3, 4, 5, 6, 5, 4, 3, 2, 1);
signal pattern2 : tPattern := (6, 5, 4, 3, 2, 1, 0, 1, 2, 3, 4, 5);
signal pattern3 : tPattern := (0, 1, 4, 9, 4, 1, 0, 0, 0, 0, 0, 0);
type tXlatTable1 is array(0 to 12) of integer range 0 to 1023;
constant xt1 : tXlatTable1 := (0, 0, 1, 4, 13, 31, 64, 118, 202, 324, 493, 722, 1023);
type tXlatTable2 is array(0 to 9) of integer range 0 to 255;
--constant xt2 : tXlatTable2 := (0, 1, 11, 38, 90, 175, 303, 481, 718, 1023);
constant xt2 : tXlatTable2 := (0, 0, 3, 9, 22, 44, 76, 120, 179, 255);
signal cp1 : std_logic_vector(22 downto 0);
signal cp2 : std_logic_vector(22 downto 0);
signal cp3 : std_logic_vector(22 downto 0);
signal d : std_logic_vector(16 downto 0);
begin
dpCLK: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( cp1 = conv_std_logic_vector(3000000,23) )
then
pattern1(10 downto 0) <= pattern1(11 downto 1);
pattern1(11) <= pattern1(0);
cp1 <= (others => '0');
else
cp1 <= cp1 + 1;
end if;
if ( cp2 = conv_std_logic_vector(2200000,23) )
then
pattern2(10 downto 0) <= pattern2(11 downto 1);
pattern2(11) <= pattern2(0);
cp2 <= (others => '0');
else
cp2 <= cp2 + 1;
end if;
if ( cp3 = conv_std_logic_vector(1500000,23) )
then
pattern3(11 downto 1) <= pattern3(10 downto 0);
pattern3(0) <= pattern3(11);
cp3 <= (others => '0');
else
cp3 <= cp3 + 1;
end if;
if ( d = conv_std_logic_vector(1278*64-1,17) )
then
d <= (others => '0');
else
d <= d + 1;
end if;
for i in 0 to 11 loop
if ( d(16 downto 6) < conv_std_logic_vector( xt1(pattern1(i) + pattern2(i)) + xt2(pattern3(i)) ,11) )
then
led(i) <= '1';
else
led(i) <= '0';
end if;
end loop;
end if;
end process dpCLK;
end RTL;
| gpl-3.0 | b29b91e94ca79055c4d9cc9143a64e27 | 0.579418 | 2.689531 | false | false | false | false |
bargei/NoC264 | NoC264_2x2/vga_node.vhd | 1 | 16,652 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.math_real.all;
entity vga_node is
generic(
data_width : integer := 64;
addr_width : integer := 4;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
-- recv interface to network
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
-- send interface to network
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic;
-- vga connections
clk27 : in std_logic;
rst27 : in std_logic;
vga_red : out std_logic_vector(5 downto 0);
vga_blue : out std_logic_vector(5 downto 0);
vga_green : out std_logic_vector(5 downto 0);
vga_v_sync : out std_logic;
vga_h_sync : out std_logic
);
end entity vga_node;
architecture fsmd of vga_node is
--- Components ------------------------------------------------------------
component priority_encoder is
generic(
encoded_word_size : integer := 3
);
Port(
input : in std_logic_vector(2**encoded_word_size-1 downto 0);
output : out std_logic_vector(encoded_word_size-1 downto 0)
);
end component priority_encoder;
--component display_buffer is
--generic(
-- rgb_size : integer := 8;
-- horizontal : integer := 320;
-- vertical : integer := 144;
-- addr_size : integer := 16
--);
--port(
-- clk : in std_logic;
-- rst : in std_logic;
--
-- red_in : in std_logic_vector(rgb_size-1 downto 0);
-- green_in : in std_logic_vector(rgb_size-1 downto 0);
-- blue_in : in std_logic_vector(rgb_size-1 downto 0);
-- wr_addr : in std_logic_vector(addr_size-1 downto 0);
-- wr_enable : in std_logic;
--
-- red_out : out std_logic_vector(rgb_size-1 downto 0);
-- green_out : out std_logic_vector(rgb_size-1 downto 0);
-- blue_out : out std_logic_vector(rgb_size-1 downto 0);
-- rd_addr : in std_logic_vector(addr_size-1 downto 0)
--
--);
--end component display_buffer;
component vga_controller is
generic(
h_pulse : integer := 208; --horiztonal sync pulse width in pixels
h_bp : integer := 336; --horiztonal back porch width in pixels
h_pixels : integer := 1920; --horiztonal display width in pixels
h_fp : integer := 128; --horiztonal front porch width in pixels
h_pol : std_logic := '0'; --horizontal sync pulse polarity (1 = positive, 0 = negative)
v_pulse : integer := 3; --vertical sync pulse width in rows
v_bp : integer := 38; --vertical back porch width in rows
v_pixels : integer := 1200; --vertical display width in rows
v_fp : integer := 1; --vertical front porch width in rows
v_pol : std_logic := '1'); --vertical sync pulse polarity (1 = positive, 0 = negative)
port(
pixel_clk : in std_logic; --pixel clock at frequency of vga mode being used
reset_n : in std_logic; --active low asycnchronous reset
h_sync : out std_logic; --horiztonal sync pulse
v_sync : out std_logic; --vertical sync pulse
disp_ena : out std_logic; --display enable ('1' = display time, '0' = blanking time)
column : out integer; --horizontal pixel coordinate
row : out integer; --vertical pixel coordinate
n_blank : out std_logic; --direct blacking output to dac
n_sync : out std_logic); --sync-on-green output to dac
end component vga_controller;
component ram_dual is
generic
(
ram_width : integer := 24;
ram_depth : integer := 65536
);
port
(
clock1 : in std_logic;
clock2 : in std_logic;
data : in std_logic_vector(ram_width-1 downto 0);
write_address : in integer;
read_address : in integer;
we : in std_logic;
q : out std_logic_vector(ram_width-1 downto 0)
);
end component ram_dual;
component ycbcr_to_rgb is
port(
clk : in std_logic;
y : in std_logic_vector(7 downto 0);
cb : in std_logic_vector(7 downto 0);
cr : in std_logic_vector(7 downto 0);
red : out std_logic_vector(7 downto 0);
green : out std_logic_vector(7 downto 0);
blue : out std_logic_vector(7 downto 0)
);
end component ycbcr_to_rgb;
--component vga_driver is
--port(
-- r : in std_logic_vector(9 downto 0);
-- g : in std_logic_vector(9 downto 0);
-- b : in std_logic_vector(9 downto 0);
-- current_x : out std_logic_vector(9 downto 0);
-- current_y : out std_logic_vector(9 downto 0);
-- request : out std_logic;
-- vga_r : out std_logic_vector(9 downto 0);
-- vga_g : out std_logic_vector(9 downto 0);
-- vga_b : out std_logic_vector(9 downto 0);
-- vga_hs : out std_logic;
-- vga_vs : out std_logic;
-- vga_blank : out std_logic;
-- vga_clock : out std_logic;
-- clk27 : in std_logic;
-- rst27 : in std_logic
--);
--end component vga_driver;
--- Constants -------------------------------------------------------------
constant rgb_size : integer := 6;
constant horizontal : integer := 320;
constant vertical : integer := 200;
constant addr_size : integer := 19;
--- Types -----------------------------------------------------------------
type vga_node_states is (idle,
sel_vc,
rx,
convert_0,
wr_rgb_0,
convert_1,
wr_rgb_1,
dequeue_flit
);
--- signals and registers -------------------------------------------------
signal state : vga_node_states;
signal next_state : vga_node_states;
signal convert_counter_d : unsigned(7 downto 0);
signal convert_counter_q : unsigned(7 downto 0);
signal red_in : std_logic_vector(rgb_size-1 downto 0);
signal green_in : std_logic_vector(rgb_size-1 downto 0);
signal blue_in : std_logic_vector(rgb_size-1 downto 0);
signal wr_addr : integer;
signal wr_enable : std_logic;
signal red_out : std_logic_vector(rgb_size-1 downto 0);
signal green_out : std_logic_vector(rgb_size-1 downto 0);
signal blue_out : std_logic_vector(rgb_size-1 downto 0);
signal rd_addr : integer;
signal y : std_logic_vector(7 downto 0);
signal cb : std_logic_vector(7 downto 0);
signal cr : std_logic_vector(7 downto 0);
signal red : std_logic_vector(7 downto 0);
signal green : std_logic_vector(7 downto 0);
signal blue : std_logic_vector(7 downto 0);
signal r : std_logic_vector(9 downto 0);
signal g : std_logic_vector(9 downto 0);
signal b : std_logic_vector(9 downto 0);
signal current_x : integer;
signal current_y : integer;
signal request : std_logic;
signal vga_r : std_logic_vector(9 downto 0);
signal vga_g : std_logic_vector(9 downto 0);
signal vga_b : std_logic_vector(9 downto 0);
signal vga_hs : std_logic;
signal vga_vs : std_logic;
signal vga_blank : std_logic;
signal vga_clock : std_logic;
signal rd_addr_32 : std_logic_vector(31 downto 0);
signal sel_vc_d : std_logic_vector(vc_sel_width-1 downto 0);
signal sel_vc_q : std_logic_vector(vc_sel_width-1 downto 0);
signal sel_vc_enc : std_logic_vector(vc_sel_width-1 downto 0);
signal sel_vc_one_hot : std_logic_vector(num_vc-1 downto 0);
signal rgb_read : std_logic_vector(3*rgb_size-1 downto 0);
signal disp_ena : std_logic;
begin
---------------------------------------------------------------------------
--- DATAPATH --------------------------------------------------------------
---------------------------------------------------------------------------
--components
u0: component priority_encoder
generic map(
encoded_word_size => vc_sel_width
)
Port map(
input => data_in_buffer,
output => sel_vc_enc
);
--u1: component display_buffer
--generic map (
-- rgb_size => rgb_size ,
-- horizontal => horizontal,
-- vertical => vertical ,
-- addr_size => addr_size
--)
--port map(
-- clk => clk ,
-- rst => rst ,
-- red_in => red_in ,
-- green_in => green_in ,
-- blue_in => blue_in ,
-- wr_addr => wr_addr ,
-- wr_enable => wr_enable,
-- red_out => red_out ,
-- green_out => green_out,
-- blue_out => blue_out ,
-- rd_addr => rd_addr
--
--);
red_ram: component ram_dual
generic map
(
ram_width => 6,
ram_depth => horizontal*vertical
)
port map
(
clock1 => clk,
clock2 => clk27,
data => red_in,
write_address => wr_addr,
read_address => rd_addr,
we => wr_enable,
q => red_out
);
blue_ram: component ram_dual
generic map
(
ram_width => 6,
ram_depth => horizontal*vertical
)
port map
(
clock1 => clk,
clock2 => clk27,
data => blue_in,
write_address => wr_addr,
read_address => rd_addr,
we => wr_enable,
q => blue_out
);
green_ram: component ram_dual
generic map
(
ram_width => 6,
ram_depth => horizontal*vertical
)
port map
(
clock1 => clk,
clock2 => clk27,
data => green_in,
write_address => wr_addr,
read_address => rd_addr,
we => wr_enable,
q => green_out
);
u2: component ycbcr_to_rgb
port map(
clk => clk ,
y => y ,
cb => cb ,
cr => cr ,
red => red ,
green => green,
blue => blue
);
--u3: component vga_driver
--port map(
-- r => r ,
-- g => g ,
-- b => b ,
-- current_x => current_x,
-- current_y => current_y,
-- request => request ,
-- vga_r => vga_r ,
-- vga_g => vga_g ,
-- vga_b => vga_b ,
-- vga_hs => vga_hs ,
-- vga_vs => vga_vs ,
-- vga_blank => vga_blank,
-- vga_clock => vga_clock,
-- clk27 => clk27 ,
-- rst27 => rst27
--);
u3: component vga_controller
generic map(
h_pulse => 96,
h_bp => 48,
h_pixels => 640,
h_fp => 16,
h_pol => '0',
v_pulse => 2,
v_bp => 35,
v_pixels => 400,
v_fp => 12,
v_pol => '1'
)
port map(
pixel_clk => clk27,
reset_n => not rst27,
h_sync => vga_hs,
v_sync => vga_vs,
column => current_x,
row => current_y,
disp_ena => disp_ena
);
-- wire components together
-- r <= red_out & std_logic_vector(to_unsigned(0, 10-rgb_size));
-- g <= green_out & std_logic_vector(to_unsigned(0, 10-rgb_size));
-- b <= blue_out & std_logic_vector(to_unsigned(0, 10-rgb_size));
--rd_addr_32 <= std_logic_vector((to_unsigned(1, 22) * unsigned(current_x)) +
-- (unsigned(current_y) * to_unsigned(horizontal, 22)));
--
--rd_addr <= to_integer(unsigned(rd_addr_32));
rd_addr <= (current_x mod horizontal) +
(current_y mod vertical ) * horizontal;
vga_red <= red_out when disp_ena = '1' else "000000"; --red_out;
vga_blue <= blue_out when disp_ena = '1' else "000000"; --green_out;
vga_green <= green_out when disp_ena = '1' else "000000"; --blue_out;
vga_v_sync <= vga_vs;
vga_h_sync <= vga_hs;
y <= recv_data(63 downto 56) when state = convert_0 else recv_data(39 downto 32);
cb <= recv_data(55 downto 48) when state = convert_0 else recv_data(31 downto 24);
cr <= recv_data(47 downto 40) when state = convert_0 else recv_data(23 downto 16);
red_in <= red(7 downto 2);
green_in <= green(7 downto 2);
blue_in <= blue(7 downto 2);
wr_addr <= to_integer(unsigned(recv_data(15 downto 0))) when state = wr_rgb_0 or state = convert_0 else
to_integer(unsigned(recv_data(15 downto 0))) + 1;
wr_enable <= '1' when state = wr_rgb_0 else
'1' when state = wr_rgb_1 else
'0';
--counter for coversion wait states
convert_counter_d <= convert_counter_q + to_unsigned(1, 8) when state = convert_0 else
convert_counter_q + to_unsigned(1, 8) when state = convert_1 else
to_unsigned(0, 8);
process(clk, rst)
begin
if rst = '1' then
sel_vc_q <= (others => '0');
convert_counter_q <= (others => '0');
elsif rising_edge(clk) then
convert_counter_q <= convert_counter_d;
sel_vc_q <= sel_vc_d;
end if;
end process;
--packet generation
send_data <= (others => '0');
dest_addr <= (others => '0');
set_tail_flit <= '0';
send_flit <= '0';
--rx controls
sel_vc_d <= sel_vc_enc when state = sel_vc else sel_vc_q;
dequeue <= sel_vc_one_hot when state = dequeue_flit else "00";
select_vc_read <= sel_vc_q;
sel_vc_one_hot <= "01" when sel_vc_q = "0" else "10";
---------------------------------------------------------------------------
--- STATE MACHINE ---------------------------------------------------------
---------------------------------------------------------------------------
process(clk, rst)
begin
if rst = '1' then
state <= idle;
elsif rising_edge(clk) then
state <= next_state;
end if;
end process;
process(state, data_in_buffer, is_tail_flit, sel_vc_one_hot, ready_to_send, convert_counter_q)
begin
next_state <= state;
if state = idle and or_reduce(data_in_buffer) = '1' then
next_state <= sel_vc;
end if;
if state = sel_vc then
next_state <= rx;
end if;
if state = rx then
next_state <= convert_0;
end if;
if state = convert_0 and convert_counter_q > to_unsigned(2, 8) then
next_state <= wr_rgb_0;
end if;
if state = wr_rgb_0 then
next_state <= convert_1;
end if;
if state = convert_1 and convert_counter_q > to_unsigned(2, 8) then
next_state <= wr_rgb_1;
end if;
if state = wr_rgb_1 then
next_state <= dequeue_flit;
end if;
if state = dequeue_flit then
next_state <= idle;
end if;
end process;
end architecture;
| mit | 37ff8b104b205fd6a27905dbd993648b | 0.478261 | 3.545242 | false | false | false | false |
AfterRace/SoC_Project | vivado/project/project.srcs/sources_1/ipshared/tsotnep/volume_pregain_v1_0/75ddc6aa/src/MultiplierFP.vhd | 2 | 3,867 | library IEEE;
--use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MultiplierFP is
generic(INTBIT_WIDTH : integer; --Size of the integer part of the input/output vectors
FRACBIT_WIDTH : integer; --Bit width of the Fixed Point fraction of the input/output vectors
COUNT_WIDTH : positive := 6); --Size of the counter signal
--COUNT_WIDTH needs to be the exact size required to fit Output signal
-- for example if BIT_WIDTH is 16, COUNT_WIDTH needs to be 5.
-- The size of the output vector is 2 times the size of the input vector.
port(CLK : in std_logic; --clock
RESET : in std_logic; --RESET signal (pulse)
IN_SIG : in signed((INTBIT_WIDTH - 1) downto 0); --multiplicand
IN_COEF : in signed(((INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0); --mutiplier
OUT_MULT : out signed(((INTBIT_WIDTH + FRACBIT_WIDTH) * 2 - 1) downto 0) := (others => '0'); --result
READY : out std_logic := '0'); --Calculation ready signal (pulse)
end MultiplierFP;
architecture Behavioral of MultiplierFP is
type reg_type is record
counter : unsigned((COUNT_WIDTH - 1) downto 0);
EN : std_logic;
tmp1 : signed(((INTBIT_WIDTH + FRACBIT_WIDTH) * 2 - 1) downto 0); -- B / COEF
tmp2 : signed(((INTBIT_WIDTH + FRACBIT_WIDTH) * 2 - 1) downto 0);
tmpA : signed(((INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0); -- A / SIG
end record;
signal r, rin : reg_type := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
signal IN_SIG_TEMP : signed(((INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0);
begin
IN_SIG_TEMP((INTBIT_WIDTH + FRACBIT_WIDTH - 1) downto FRACBIT_WIDTH) <= IN_SIG;
--Control logic of the multiplication algorithm
combinational : process(IN_SIG_TEMP, IN_COEF, r, RESET)
variable v : reg_type := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
begin
if (RESET = '1') then
v := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
OUT_MULT <= (others => '0');
READY <= '0';
else
v := r;
v.counter := v.counter - 1; --At first cycle the counter ovwerflows and sets all bits to '1'-s giving the value of BIT_WIDTH - 1
--Initialisation. Copy inputs to variables for manipulation and protection
--against the changing of the inputs while calculating. We also reset the counter.
OUT_MULT <= v.tmp1;
if (v.counter = 2 * (INTBIT_WIDTH + FRACBIT_WIDTH) - 1) then
READY <= '1' and v.EN; --Output the READY signal only when we have a real answer
v.EN := '1';
v.tmpA := IN_SIG_TEMP;
v.tmp1 := RESIZE(IN_COEF, OUT_MULT'LENGTH);
v.tmp2 := (others => '0');
else
READY <= '0';
end if;
--check if we have to add
if (v.tmp1(0) = '1') then
v.tmp2 := v.tmp2 + v.tmpA;
end if;
--Next we are going to arithmetically shift tmp2 to the right so, that
--the bit that gets shifted out of it will shift into tmp1 from right
v.tmp1 := shift_right(v.tmp1, 1);
v.tmp1(2 * (INTBIT_WIDTH + FRACBIT_WIDTH) - 1) := v.tmp2(0);
v.tmp2 := shift_right(v.tmp2, 1);
end if;
rin <= v;
end process combinational;
sequential : process(CLK)
begin
if rising_edge(CLK) then
r <= rin;
end if;
end process sequential;
end Behavioral;
| lgpl-3.0 | 4c865dcf3ea94be42a54671af5bd1e66 | 0.599172 | 3.342264 | false | false | false | false |
peladex/RHD2132_FPGA | quartus/test_spi_de0/test_spi_de0.vhd | 1 | 11,233 | -----------------------------------------------------------------------------------------------------------------------
-- Author:
--
-- Create Date: 11/11/2016 -- dd/mm/yyyy
-- Module Name: test_spi_de0
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- ...
-----------------------------------------------------------------------------------------------------------------------
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
LIBRARY lpm;
USE lpm.lpm_components.ALL;
ENTITY test_spi_de0 IS
PORT(
m_clk : in std_logic; -- master clock
m_reset : in std_logic; -- master reset
boton2_set : in std_logic;
boton1_reset : in std_logic;
FULL_LED9 : out std_logic;
EMPTY_LED8 : out std_logic;
SW : in std_logic_vector(7 downto 0);
display0 : out std_logic_vector(0 to 6);
display1 : out std_logic_vector(0 to 6);
display2 : out std_logic_vector(0 to 6);
display3 : out std_logic_vector(0 to 6);
---- master interface 1 ----
spi1_ssel_o : out std_logic; -- spi bus slave select line
spi1_sck_o : out std_logic; -- spi bus sck
spi1_mosi_o : out std_logic; -- spi bus mosi output
spi1_miso_i : in std_logic := 'X'; -- spi bus spi_miso_i input
---- master interface 2 ----
spi2_ssel_o : out std_logic; -- spi bus slave select line
spi2_sck_o : out std_logic; -- spi bus sck
spi2_mosi_o : out std_logic; -- spi bus mosi output
spi2_miso_i : in std_logic := 'X'; -- spi bus spi_miso_i input
---- slave interface 1 ----
slave1_ssel_i : in std_logic := 'X'; -- spi bus slave select line
slave1_sck_i : in std_logic := 'X'; -- spi bus sck
slave1_mosi_i : in std_logic := 'X'; -- spi bus mosi output
slave1_miso_o : out std_logic := 'X'; -- spi bus spi_miso_i input
---- slave interface 2 ----
slave2_ssel_i : in std_logic := 'X'; -- spi bus slave select line
slave2_sck_i : in std_logic := 'X'; -- spi bus sck
slave2_mosi_i : in std_logic := 'X'; -- spi bus mosi output
slave2_miso_o : out std_logic := 'X'; -- spi bus spi_miso_i input
---- dbg ---
dbg_read_fifo_1 : out std_logic
---- fifo 1 interface ----
--f1_do_o : out std_logic_vector(15 downto 0);
--f1_wren_o : out std_logic;
---- fifo 2 interface ----
--f2_do_o : out std_logic_vector(15 downto 0);
--f2_wren_o : out std_logic
);
END test_spi_de0;
ARCHITECTURE synth OF test_spi_de0 IS
---- COMPONENTS
COMPONENT test_spi_side IS
PORT(
m_clk : in std_logic; -- master clock
m_reset : in std_logic; -- master reset
---- master_control interface ----
di_1_i : in std_logic_vector(15 downto 0);
do_1_o : out std_logic_vector(15 downto 0);
wren_1_i : in std_logic;
drdy_1_o : out std_logic;
rdreq_1_i : in std_logic;
di_2_i : in std_logic_vector(15 downto 0);
do_2_o : out std_logic_vector(15 downto 0);
wren_2_i : in std_logic;
drdy_2_o : out std_logic;
rdreq_2_i : in std_logic;
---- fifo 1 interface ----
f1_do_o : out std_logic_vector(15 downto 0);
f1_wren_o : out std_logic;
---- fifo 2 interface ----
f2_do_o : out std_logic_vector(15 downto 0);
f2_wren_o : out std_logic;
---- serial interface 1 ----
spi1_ssel_o : out std_logic; -- spi bus slave select line
spi1_sck_o : out std_logic; -- spi bus sck
spi1_mosi_o : out std_logic; -- spi bus mosi output
spi1_miso_i : in std_logic := 'X'; -- spi bus spi_miso_i input
---- serial interface 2 ----
spi2_ssel_o : out std_logic; -- spi bus slave select line
spi2_sck_o : out std_logic; -- spi bus sck
spi2_mosi_o : out std_logic; -- spi bus mosi output
spi2_miso_i : in std_logic := 'X' -- spi bus spi_miso_i input
);
END COMPONENT;
COMPONENT Maquina_de_Control IS
PORT(
CLK : IN STD_LOGIC; --Reset activo por ALTO!
RESET : IN STD_LOGIC; -- @ff:No me gusta agrupar aca! jaja
--senales de trigger de funciones
reg_func_in : IN STD_LOGIC_VECTOR(7 downto 0);
reg_func_out : OUT STD_LOGIC_VECTOR(7 downto 0);
---- load_param
reg_load_param_1 : IN STD_LOGIC_VECTOR(15 downto 0); -- @ff: Salida del banco de registros con configuracion del chip 1
selec_load_param_1 : OUT STD_LOGIC_VECTOR(7 downto 0); -- @ff: Selector del banco de registros (18 registros) del chip 1
--send_command
reg_send_com_in : IN STD_LOGIC_VECTOR(15 downto 0);
--Senales de comunicacion con bloque convertidor a SPI
reg_envio_out : OUT STD_LOGIC_VECTOR(15 downto 0); -- Registro donde mando el comando pronto para enviar.
ack_in : IN STD_LOGIC; -- ACK de que llego el dato al convertidor SPI. LO CONSIDERO UN PULSO DE UN CLK
WE_out : OUT STD_LOGIC -- Senal de control que indica que esta pronto para enviar el dato
);
END COMPONENT;
COMPONENT test_spi_slaves IS
PORT(
m_clk : in std_logic; -- master clock
m_reset : in std_logic; -- master reset
---- serial interface 1 ----
slave1_ssel_i : in std_logic := 'X'; -- spi bus slave select line
slave1_sck_i : in std_logic := 'X'; -- spi bus sck
slave1_mosi_i : in std_logic := 'X'; -- spi bus mosi output
slave1_miso_o : out std_logic := 'X'; -- spi bus spi_miso_i input
---- serial interface 2 ----
slave2_ssel_i : in std_logic := 'X'; -- spi bus slave select line
slave2_sck_i : in std_logic := 'X'; -- spi bus sck
slave2_mosi_i : in std_logic := 'X'; -- spi bus mosi output
slave2_miso_o : out std_logic := 'X' -- spi bus spi_miso_i input
);
END COMPONENT;
component GEN_PULSO is
port(
clk : in std_logic; -- clk
reset : in std_logic; -- reset
input : in std_logic; -- input
edge_detected : out std_logic -- edge_detected: pulso a 1 cuando
-- se detecta flanco en input
);
end component;
component fifo_test_1
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
end component;
COMPONENT hex27seg IS
PORT(
hex_in : IN STD_LOGIC_VECTOR(3 downto 0);
seg_out : OUT STD_LOGIC_VECTOR(6 downto 0)
);
END COMPONENT;
COMPONENT rebot_elim is
PORT(
Sn, Rn : in std_logic;
Q : out std_logic
);
END COMPONENT;
---- SIGNALS
signal sg_mc_do_1_o : std_logic_vector(15 downto 0);
signal sg_mc_wren_1_o : std_logic;
signal sg_drdy_1_o : std_logic;
signal sg_mc_rdreq_1_o : std_logic;
signal sg_mc_do_2_o : std_logic_vector(15 downto 0);
signal sg_mc_wren_2_o : std_logic;
signal sg_mc_rdreq_2_o : std_logic;
signal sg_spi1_ssel_o : std_logic;
signal sg_spi1_sck_o : std_logic;
signal sg_spi1_mosi_o : std_logic;
signal sg_spi1_miso_i : std_logic;
signal sg_spi2_ssel_o : std_logic;
signal sg_spi2_sck_o : std_logic;
signal sg_spi2_mosi_o : std_logic;
signal sg_spi2_miso_i : std_logic;
signal sg_f1_do_o : std_logic_vector(15 downto 0);
signal sg_f1_wren_o : std_logic;
signal sg_read_fifo_1 : std_logic;
signal q_sig : std_logic_vector(15 downto 0);
signal sg_flanco : std_logic;
BEGIN
---- INSTANCES
T_spi: test_spi_side port map (
m_clk => m_clk,
m_reset => m_reset,
---- master_control interface ----
di_1_i => sg_mc_do_1_o,
wren_1_i => sg_mc_wren_1_o,
drdy_1_o => sg_drdy_1_o,
rdreq_1_i => '0',
di_2_i => sg_mc_do_2_o,
wren_2_i => sg_mc_wren_2_o,
rdreq_2_i => '0',
---- fifo 1 interface ----
f1_do_o => sg_f1_do_o,
f1_wren_o => sg_f1_wren_o,
---- fifo 2 interface ----
--f2_do_o => f2_do_o,
--f2_wren_o => f2_wren_o,
---- serial interface 1 ----
spi1_ssel_o => spi1_ssel_o,
spi1_sck_o => spi1_sck_o,
spi1_mosi_o => spi1_mosi_o,
spi1_miso_i => spi1_miso_i,
---- serial interface 2 ----
spi2_ssel_o => spi2_ssel_o,
spi2_sck_o => spi2_sck_o,
spi2_mosi_o => spi2_mosi_o,
spi2_miso_i => spi2_miso_i
);
MC: Maquina_de_Control port map (
CLK => m_clk,
RESET => m_reset,
--senales de trigger de funciones
reg_func_in => SW,
---- load_param
reg_load_param_1 => X"BEEF",
--send_command
reg_send_com_in => X"AAAA",
--Senales de comunicacion con bloque convertidor a SPI
reg_envio_out => sg_mc_do_1_o,
ack_in => sg_drdy_1_o,
WE_out => sg_mc_wren_1_o
);
T_slaves: test_spi_slaves port map (
m_clk => m_clk,
m_reset => m_reset,
---- serial interface 1 ----
slave1_ssel_i => slave1_ssel_i,
slave1_sck_i => slave1_sck_i,
slave1_mosi_i => slave1_mosi_i,
slave1_miso_o => slave1_miso_o,
---- serial interface 2 ----
slave2_ssel_i => slave2_ssel_i,
slave2_sck_i => slave2_sck_i,
slave2_mosi_i => slave2_mosi_i,
slave2_miso_o => slave2_miso_o
);
gen_pul : GEN_PULSO port map (
clk => m_clk,
reset => m_reset,
input => sg_flanco,
edge_detected => sg_read_fifo_1
);
fifo_test_1_inst : fifo_test_1 PORT MAP (
clock => m_clk,
data => sg_f1_do_o,
rdreq => sg_read_fifo_1,
wrreq => sg_f1_wren_o,
empty => EMPTY_LED8,
full => FULL_LED9,
q => q_sig
);
hex0 : hex27seg port map (
hex_in => q_sig(3 downto 0),
seg_out => display0
);
hex1 : hex27seg port map (
hex_in => q_sig(7 downto 4),
seg_out => display1
);
hex2 : hex27seg port map (
hex_in => q_sig(11 downto 8),
seg_out => display2
);
hex3 : hex27seg port map (
hex_in => q_sig(15 downto 12),
seg_out => display3
);
RE: rebot_elim PORT map (
Sn => boton2_set,
Rn => boton1_reset,
Q => sg_flanco
);
dbg_read_fifo_1 <= sg_read_fifo_1;
END synth;
| gpl-3.0 | 8034b3ad66d4785ab5695d172e9e9164 | 0.505119 | 3.175855 | false | false | false | false |
bargei/NoC264 | NoC264_3x3/noc_controller.vhd | 1 | 9,011 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
entity noc_controller is
generic(
data_width : integer := 128;
addr_width : integer := 2;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
-- interface with hps
data_in : in std_logic_vector(data_width-1 downto 0);
data_out : out std_logic_vector(data_width-1 downto 0);
noc_ctrl : in std_logic_vector(31 downto 0);
noc_sts : out std_logic_vector(31 downto 0);
--network sending interface
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic;
--network receiving interface
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
--debugging
has_rxd : out std_logic;
tx_non_zero : out std_logic
);
end entity noc_controller;
architecture fsmd of noc_controller is
constant identifier_msb : integer := 7;
constant identifier_lsb : integer := 0;
constant num_data_regs : integer := 1;
component priority_encoder is
generic(
encoded_word_size : integer := 3
);
Port(
input : in std_logic_vector(2**encoded_word_size-1 downto 0);
output : out std_logic_vector(encoded_word_size-1 downto 0)
);
end component priority_encoder;
type regs is array(num_data_regs-1 downto 0) of std_logic_vector(data_width-1 downto 0);
signal data_register_d, data_register_q : regs;
signal data_in_buffer_q, data_in_buffer_delay : std_logic_vector(num_vc-1 downto 0);
signal write_enable : std_logic;
signal selected_vc_q, selected_vc_d, selected_vc_encoder : std_logic_vector(vc_sel_width-1 downto 0);
signal identifier : std_logic_vector(7 downto 0);
signal id_select : std_logic_vector(7 downto 0);
signal has_rxd_d, has_rxd_q : std_logic;
signal send_flit_once_edge, send_flit_once_d, send_flit_once_q, send_flit_once_q2 : std_logic;
type send_states is (idle, send, waiting);
signal send_state, next_send_state : send_states;
type rx_states is (rx_idle, rx_addr_rst, rx_start_read, rx_sel_vc, rx_rxd, rx_wait_cpu, rx_dequeue, rx_wait_flits);
signal rx_state, next_rx_state : rx_states;
signal selected_vc_one_hot : std_logic_vector(1 downto 0);
signal state : std_logic_vector(3 downto 0);
signal cpu_read_ctrl : std_logic;
begin
---------------------------------------------------------------------------
-- Sending Controls -------------------------------------------------------
---------------------------------------------------------------------------
-- output logic
send_data <= data_in;
dest_addr <= noc_ctrl(addr_width-1 downto 0);
set_tail_flit <= noc_ctrl(8);
send_flit <= '1' when send_state = send else '0';
-- state register
process(clk, rst) begin
if rst = '1' then
send_state <= idle;
elsif rising_edge(clk) then
send_state <= next_send_state;
end if;
end process;
-- state transition logic
process(send_state, noc_ctrl(9)) begin
next_send_state <= send_state;
if send_state = idle and noc_ctrl(9) = '1' then
next_send_state <= send;
end if;
if send_state = send then
next_send_state <= waiting;
end if;
if send_state = waiting and noc_ctrl(9) = '0' then
next_send_state <= idle;
end if;
end process;
---------------------------------------------------------------------------
-- receive inteface controls ----------------------------------------------
---------------------------------------------------------------------------
--rx_idle, rx_sel_vc, rx_rxd, rx_wait_cpu, rx_dequeue, rx_wait_flits, rx_addr_rst, rx_start_read
--- output logic ---
dequeue <= "01" when selected_vc_q = "0" and rx_state = rx_dequeue else
"10" when selected_vc_q = "1" and rx_state = rx_dequeue else
"00";
selected_vc_one_hot <= "01" when selected_vc_q = "0" else
"10";
select_vc_read <= selected_vc_q;
state <= std_logic_vector(to_unsigned(0, 4)) when rx_state = rx_idle else
std_logic_vector(to_unsigned(1, 4)) when rx_state = rx_sel_vc else
std_logic_vector(to_unsigned(2, 4)) when rx_state = rx_addr_rst else
std_logic_vector(to_unsigned(3, 4)) when rx_state = rx_start_read else
std_logic_vector(to_unsigned(4, 4)) when rx_state = rx_rxd else
std_logic_vector(to_unsigned(5, 4)) when rx_state = rx_wait_cpu else
std_logic_vector(to_unsigned(6, 4)) when rx_state = rx_dequeue else
std_logic_vector(to_unsigned(7, 4)) when rx_state = rx_wait_flits else
std_logic_vector(to_unsigned(15, 4));
--- data path ---
-- data path registers
process(clk, rst) begin
if rst = '1' then
selected_vc_q <=(others => '0');
elsif rising_edge(clk) then
selected_vc_q <= selected_vc_d;
end if;
end process;
--data path components
u0: priority_encoder generic map(vc_sel_width)
port map(data_in_buffer, selected_vc_encoder);
-- data path logic
selected_vc_d <= selected_vc_encoder when rx_state = rx_sel_vc else selected_vc_q;
cpu_read_ctrl <= noc_ctrl(14);
--- FSM ---
-- state register
process(clk, rst) begin
if rst = '1' then
rx_state <= rx_idle;
elsif rising_edge(clk) then
rx_state <= next_rx_state;
end if;
end process;
--- state transition logic
--rx_idle, rx_sel_vc, rx_rxd, rx_wait_cpu, rx_dequeue, rx_wait_flits
process(rx_state, data_in_buffer, selected_vc_q) begin
next_rx_state <= rx_state;
if rx_state = rx_idle and or_reduce(data_in_buffer) = '1' then
next_rx_state <= rx_sel_vc;
end if;
if rx_state = rx_sel_vc then
next_rx_state <= rx_addr_rst;
end if;
if rx_state = rx_addr_rst and cpu_read_ctrl = '1' then
next_rx_state <= rx_start_read;
end if;
if rx_state = rx_start_read and cpu_read_ctrl = '0' then
next_rx_state <= rx_rxd;
end if;
if rx_state = rx_rxd and cpu_read_ctrl = '1' then
next_rx_state <= rx_wait_cpu;
end if;
if rx_state = rx_wait_cpu and cpu_read_ctrl = '0' then
next_rx_state <= rx_dequeue;
end if;
if rx_state = rx_dequeue and is_tail_flit = '1' then
next_rx_state <= rx_idle;
end if;
if rx_state = rx_dequeue and is_tail_flit = '0' then
next_rx_state <= rx_wait_flits;
end if;
if rx_state = rx_wait_flits and or_reduce(data_in_buffer and selected_vc_one_hot) = '1' then
next_rx_state <= rx_rxd;
end if;
end process;
---------------------------------------------------------------------------
-- User Rx Interface -----------------------------------------------------
---------------------------------------------------------------------------
id_select <= noc_ctrl(31 downto 24);
--data_out <= data_register_q(to_integer(unsigned(id_select)));
data_out <= recv_data;
noc_sts(24 + addr_width - 1 downto 24) <= src_addr;
noc_sts(23 downto 20) <= state;
noc_sts(0) <= not ready_to_send;
noc_sts(17 downto 1) <= noc_ctrl(16 downto 0);
noc_sts(19 downto 18) <= "00" when send_state = idle else
"01" when send_state = send else
"10" when send_state = waiting else
"11";
---------------------------------------------------------------------------
-- debug ------------------------------------------------------------------
---------------------------------------------------------------------------
has_rxd <= or_reduce(data_in_buffer); --has_rxd_q;
tx_non_zero <= or_reduce(recv_data);
end architecture fsmd;
| mit | df51d2492437ed3b0b1c952d4885f7fc | 0.505049 | 3.729719 | false | false | false | false |
boztalay/OldProjects | FPGA/Systems/Sys_KeyboardTest/KeyboardTest/Sys_KeyboardTest.vhd | 1 | 5,382 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 23:07:45 06/06/2009
-- Design Name:
-- Module Name: Sys_KeyboardTest - Behavioral
-- Project Name: Keyboard Test
-- Target Devices:
-- Tool versions:
-- Description: A first-time attempt to interface a keyboard with the FPGA board.
-- The board will display the scan code in hexadecimal on two of the
-- 7-segment displays.
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - Tested PS/2 port's data and clock lines while the keyboard is idle
-- - Result: Both are stable at high
-- Revision 0.10 - Was able to fill an 11-bit register with pieces of data from the keyboard
-- and display the contents to LEDs on the board
-- - Note: Was only able to get proper scan codes after several keystrokes
-- Revision 0.50 - Selected and reversed the 8-bit scan code in the 11-bit piece of data
-- (the scan code is sent LSB first)
-- - Displayed the scan code on the standard 8 LEDs on the board
-- - Added vailidity checking by checking the first and last bits to be both
-- 0 and 1, respectively
-- - Added parity checking
-- - Note: I am still getting incorrect scan codes about every other keystroke.
-- How often a correct scan code is displayed changes with the key.
-- Oddly enough, these incorrect codes are being received despite the
-- filtering of the data received, as described above
-- Revision 0.90 - After revising the parity calculations several times, I...
-- -Simply took out the parity checking
-- -And lowered bit_count's limit to 10; I had forgotten that it starts at 0!
-- -Then changed back to displaying the scan code in MSB order on the 8 LEDs
-- -I had changed it several times during experimentation
-- Revision 1.00 - Added capability to display the scan codes in hex on the 7-segment displays
-- -To do so, added a frequency divider to produce 500Hz and a 7-segment decoder
-- Revision 1.10 - Added capability to show scan code in binary on the LEDs again,as well as
-- in hex on the displays
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity Sys_KeyboardTest is
Port ( KeyCLK : in STD_LOGIC;
KeyData : in STD_LOGIC;
MainCLK : in STD_LOGIC;
Anodes : out STD_LOGIC_VECTOR(3 downto 0);
Segments : out STD_LOGIC_VECTOR(6 downto 0);
Lights : out STD_LOGIC_VECTOR(7 downto 0));
end Sys_KeyboardTest;
architecture Behavioral of Sys_KeyboardTest is
--\Signals/--
signal Buf_KeyCLK : STD_LOGIC;
signal Buf_KeyData : STD_LOGIC;
signal Buf_MainCLK : STD_LOGIC;
signal CLK500Hz : STD_LOGIC;
signal Buf_CLK500Hz : STD_LOGIC;
signal Dummy : STD_LOGIC;
signal DecoderNum : STD_LOGIC_VECTOR(3 downto 0);
signal ScanCode : STD_LOGIC_VECTOR(7 downto 0);
--/Signals\--
--\Components/--
component Comp_FrequencyDivider is
Port ( SysCLK : in STD_LOGIC;
out1 : out STD_LOGIC;
out2 : out STD_LOGIC);
end component;
component Comp_7segDecoder is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
seg : out STD_LOGIC_VECTOR (6 downto 0));
end component;
--/Components\--
begin
--\BUFG Instantiations/--
BUFG_BufKeyCLK : BUFG
port map (
O => Buf_KeyCLK,
I => KeyCLK
);
BUFG_BufKeyData : BUFG
port map (
O => Buf_KeyData,
I => KeyData
);
BUFG_BufCLK500Hz : BUFG
port map (
O => Buf_CLK500Hz,
I => CLK500Hz
);
BUFG_BufMainCLK : BUFG
port map (
O => Buf_MainCLK,
I => MainCLK
);
--/BUFG Instantiations\--
DispCLK: Comp_FrequencyDivider port map (Buf_MainCLK, Dummy, CLK500Hz);
Decoder: Comp_7segDecoder port map (DecoderNum, Segments);
main : process(Buf_KeyCLK, Buf_KeyData, ScanCode)
variable bit_count : integer := 0;
variable data_stor : STD_LOGIC_VECTOR(10 downto 0);
variable started : boolean := false;
variable parity_chk : STD_LOGIC := '0';
begin
if (Buf_KeyCLK'event and Buf_KeyCLK = '0') then --if the lines are idle and the clock drops
if (started = false) then
started := true;
end if;
if (started = true) then
data_stor(bit_count) := Buf_KeyData; --grab the bit
bit_count := (bit_count + 1); --increment the index
if (bit_count > 10) then --if 11 bits have been sent, reset the counter
bit_count := 0;
if ((data_stor(0) = '0') and (data_stor(10) = '1')) then --check the first and last bits
ScanCode <= data_stor(8 downto 1); --send the scan code for displaying
end if;
started := false; --mark the lines as idle
end if;
end if;
end if;
end process;
disp : process(Buf_CLK500Hz, ScanCode)
variable digit : STD_LOGIC := '0';
begin
if (Buf_CLK500Hz'event and Buf_CLK500Hz = '1') then
if (digit = '0') then
Anodes <= "1110";
DecoderNum <= ScanCode(3 downto 0);
end if;
if (digit = '1') then
Anodes <= "1101";
DecoderNum <= ScanCode(7 downto 4);
end if;
digit := not digit;
end if;
Lights <= ScanCode;
end process;
end Behavioral; | mit | 8b72f98c32002b0f06745188dc8da9a9 | 0.637867 | 3.508475 | false | false | false | false |
boztalay/OldProjects | FPGA/Sys_SecondTimer/Comp_Counter4bit.vhd | 1 | 1,500 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 23:08:49 07/29/2009
-- Design Name:
-- Module Name: Comp_Counter - Behavioral
-- Project Name: Binary Counter
-- Target Devices:
-- Tool versions:
-- Description: A binary counter with synchronous reset.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.10 - First draft written
-- Revision 0.15 - Syntax errors fixed
-- Revision 1.00 - Generated programming file with a successful test on hardware
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Comp_Counter4bit is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
output : out STD_LOGIC_VECTOR (3 downto 0));
end Comp_Counter4bit;
architecture Behavioral of Comp_Counter4bit is
begin
main : process(reset, clock) is
variable value : STD_LOGIC_VECTOR(3 downto 0) := "0000";
begin
if falling_edge(clock) then
if reset = '1' or value = x"F" then
value := x"0";
else
value := value + x"1";
end if;
end if;
output <= value;
end process main;
end Behavioral;
| mit | 029bc90335225e6f091989db60a1d211 | 0.598667 | 3.75 | false | false | false | false |
rpereira-dev/ENSIIE | UE/S3/microarchi/bus_ia/dispatcher.vhd | 1 | 4,278 | -------------------------------------------------------------------------------
--
-- Ce bloc interprete des messages correspond aux commandes processeurs
--
-- Il prends un message en paramètre au format
-- (3 bits ; 21 bits)
-- ( cmd ; msg )
--
-- - 'cmd' la commande a executé
-- - 'msg' le message de la commande
--
-- TODO comment
--
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY dispatcher IS
PORT(
-- la master clock et le reset
clk : in STD_LOGIC;
reset : in STD_LOGIC;
-- message en entrée
busmsg : in STD_LOGIC_VECTOR(23 downto 0);
-- les 32 valeurs du 7 segments configurées (7 * 32 = 224) + N sur 6 bits
busSS : out STD_LOGIC_VECTOR(229 downto 0);
-- N_clock : nombre de clock à attendre pour générer un tick
busNClock : out STD_LOGIC_VECTOR(20 downto 0);
-- est à '1' si l'on doit envoyer un message au PC tous les 1000 ticks
busTICK1000 : out STD_LOGIC
);
END dispatcher;
ARCHITECTURE montage OF dispatcher IS
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
-- Commande pour 'busmsg'
-- SEND => envoit du message
-- NOOP => envoit d'un buffer 0
TYPE T_CMD IS (READ_MSG, DISPATCH);
signal cmd : T_CMD;
-- le registre de stockage des données du dernier message reçu
signal R_Msg : STD_LOGIC_VECTOR(23 downto 0);
-- check (ON ou OFF) pour que le processeur envoit un message au PC
-- tous les 1000 tickets de H100
signal R_TICK1000 : STD_LOGIC;
-- registre stockant les 32 valeurs du 7 segments configurées (7 * 32 = 224)
signal R_SS : STD_LOGIC_VECTOR(229 downto 0);
-- registre stockant V (nombre de master clock à attendre avant de générer un tick)
signal R_N_CLOCK : STD_LOGIC_VECTOR(20 downto 0);
-------------------------------------------------------------------------------
-- Partie Contrôle
-------------------------------------------------------------------------------
type STATE_TYPE is (
ST_READ, ST_DISPATCH
);
signal state : STATE_TYPE;
BEGIN
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
PROCESS (reset, clk)
BEGIN
-- si on reset
IF reset = '1' THEN
-- 100 ticks par seconde
R_N_CLOCK <= STD_LOGIC_VECTOR(to_unsigned(5000, 21));
-- configure le serpentin pour qu'il soit vide
R_SS <= (5 => '1', others => '0');
-- desactive le check TICK1000
R_TICK1000 <= '0';
ELSIF clk'event AND clk = '1' THEN
-- stocke le message
IF cmd = READ_MSG THEN
R_Msg <= busmsg;
-- dispatch le message
ELSIF cmd = DISPATCH THEN
-- switch l'id du message
CASE R_Msg(23 downto 21) IS
-- si 0 == NOOP
WHEN "000" =>
-- ne rien faire
-- hinit(n_clock)
WHEN "001" =>
R_N_CLOCK <= R_Msg(20 downto 0);
-- h-check-on()
WHEN "010" =>
R_TICK1000 <= '1';
-- h-check-off()
WHEN "011" =>
R_TICK1000 <= '0';
-- clr(s)
WHEN "100" =>
R_SS <= (5 => '1', others => '0');
-- si commande set-N(n)
WHEN "101" =>
R_SS(5 downto 0) <= R_Msg(5 downto 0);
-- si commande set-val(i, v)
WHEN "110" =>
-- TODO
-- R_SS((i + 1) * 7 - 1, i * 7) <= R_Msg(6 downto 0);
WHEN others =>
-- message invalide
END CASE;
END IF;
END IF;
END PROCESS;
busSS <= R_SS;
busNClock <= R_N_CLOCK;
busTICK1000 <= R_TICK1000;
-------------------------------------------------------------------------------
-- Partie Contrôle
-------------------------------------------------------------------------------
-- fonction de transitition
PROCESS (reset,clk)
BEGIN
IF clk'event AND clk = '1' THEN
IF state = ST_READ THEN
state <= ST_DISPATCH;
ELSIF state = ST_DISPATCH THEN
state <= ST_READ;
END IF;
END IF;
END PROCESS;
-- fonction de sortie
WITH state SELECT cmd <=
READ_MSG WHEN ST_READ,
DISPATCH WHEN ST_DISPATCH
;
end montage;
| gpl-3.0 | 4bf3c9b4f2c30dc7f128159170d6cafd | 0.487559 | 3.573826 | false | false | false | false |
bargei/NoC264 | NoC264_2x2/half_pixel_interpolator_fir.vhd | 1 | 4,099 | -- Inter-Prediction Interpolator Filter
-- see ITU Std. 8.4.2.2.1 and 8.4.2.2.2
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.math_real.all;
entity half_pixel_interpolator_fir is
port(
x0 : in std_logic_vector(7 downto 0);
x1 : in std_logic_vector(7 downto 0);
x2 : in std_logic_vector(7 downto 0);
x3 : in std_logic_vector(7 downto 0);
x4 : in std_logic_vector(7 downto 0);
x5 : in std_logic_vector(7 downto 0);
y : out std_logic_vector(7 downto 0)
);
end entity half_pixel_interpolator_fir;
--architecture rtl of half_pixel_interpolator_fir is
--
-- --interpolation equation
-- --y_1 = x0 -5*x1 + 20*x2 + 20*x3 - 5*x4 + x5
-- --y = clip1((y_1 + 16)>>5)
-- signal x0_times_1 : unsigned(15 downto 0);
-- signal x1_times_4 : unsigned(9 downto 0);
-- signal x1_times_5 : unsigned(15 downto 0);
-- signal x2_times_4 : unsigned(9 downto 0);
-- signal x2_times_16 : unsigned(11 downto 0);
-- signal x2_times_20 : unsigned(15 downto 0);
-- signal x3_times_4 : unsigned(9 downto 0);
-- signal x3_times_16 : unsigned(11 downto 0);
-- signal x3_times_20 : unsigned(15 downto 0);
-- signal x4_times_4 : unsigned(9 downto 0);
-- signal x4_times_5 : unsigned(15 downto 0);
-- signal x5_times_1 : unsigned(15 downto 0);
--
-- signal y_1 : unsigned(15 downto 0);
-- signal y_1_sr_5 : unsigned(15 downto 0);
-- signal y_candidate : std_logic_vector(15 downto 0);
--begin
--
-- x0_times_1 <= unsigned("00000000" & x0);
--
-- x1_times_4 <= shift_left(unsigned("00" & x1),2);
-- x1_times_5 <= unsigned("00000000" & x1) + x1_times_4;
--
-- x2_times_4 <= shift_left(unsigned("00" & x2), 2);
-- x2_times_16 <= shift_left(unsigned("0000" & x2), 4);
-- x2_times_20 <= unsigned("0000" & std_logic_vector(x2_times_16)) + x2_times_4;
--
-- x3_times_4 <= shift_left(unsigned("00" & x3 ), 2);
-- x3_times_16 <= shift_left(unsigned("0000" & x3), 4);
-- x3_times_20 <= unsigned("0000" & std_logic_vector(x3_times_16)) + x3_times_4;
--
-- x4_times_4 <= shift_left(unsigned("00" & x4), 2);
-- x4_times_5 <= unsigned("00000000" & x4) + x4_times_4;
--
-- x5_times_1 <= unsigned("00000000" & x5);
--
-- y_1 <= x0_times_1 - x1_times_5 + x2_times_20 + x3_times_20 - x4_times_5 + x5_times_1;
-- y_1_sr_5 <= shift_right(y_1, 5);
-- y_candidate <= std_logic_vector(y_1_sr_5);
-- y <= y_candidate(7 downto 0) when y_1_sr_5 >= to_unsigned(0, 16) and y_1_sr_5 <= to_unsigned(255, 16) else
-- std_logic_vector(to_unsigned(0, 8)) when y_1_sr_5 < to_unsigned(0, 16) else
-- std_logic_vector(to_unsigned(255, 8));
--
--end architecture rtl;
architecture dsp of half_pixel_interpolator_fir is
--interpolation equation
--y_1 = x0 -5*x1 + 20*x2 + 20*x3 - 5*x4 + x5
--y = clip1((y_1 + 16)>>5)
signal x0_u : unsigned(31 downto 0);
signal x1_u : unsigned(15 downto 0);
signal x2_u : unsigned(15 downto 0);
signal x3_u : unsigned(15 downto 0);
signal x4_u : unsigned(15 downto 0);
signal x5_u : unsigned(31 downto 0);
signal y_a : unsigned(31 downto 0);
signal y_b : unsigned(31 downto 0);
signal y_c : std_logic_vector(31 downto 0);
begin
x0_u <= unsigned(X"000000" & x0);
x1_u <= unsigned(X"00" & x1);
x2_u <= unsigned(X"00" & x2);
x3_u <= unsigned(X"00" & x3);
x4_u <= unsigned(X"00" & x4);
x5_u <= unsigned(X"000000" & x5);
y_a <= x0_u -
to_unsigned(5, 16) * x1_u +
to_unsigned(20, 16) * x2_u +
to_unsigned(20, 16) * x3_u -
to_unsigned(5, 16) * x4_u +
x5_u;
y_b <= shift_right(y_a, 5);
y_c <= std_logic_vector(y_b);
y <= y_c(7 downto 0) when y_b >= to_unsigned(0, 16) and y_b <= to_unsigned(255, 16) else
std_logic_vector(to_unsigned(0, 8)) when y_b < to_unsigned(0, 16) else
std_logic_vector(to_unsigned(255, 8));
end architecture dsp;
| mit | e511d0cfff0c3fd8014ab7c6d639ef1f | 0.569651 | 2.534941 | false | false | false | false |
fkolacek/FIT-VUT | INP2/fpga/kbctrl.vhd | 1 | 5,814 | -- kbctrl.vhd : High-level keyboard controller
-- Copyright (C) 2011 Brno University of Technology,
-- Faculty of Information Technology
-- Author(s): Zdenek Vasicek <xvasic11 AT stud.fit.vutbr.cz>
--
-- LICENSE TERMS
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. All advertising materials mentioning features or use of this software
-- or firmware must display the following acknowledgement:
--
-- This product includes software developed by the University of
-- Technology, Faculty of Information Technology, Brno and its
-- contributors.
--
-- 4. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software or firmware is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id$
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity kb_controller is
port (
RST : in std_logic;
CLK : in std_logic;
-- interni rozhrani
DATA : out std_logic_vector (7 downto 0);
DATA_REQ : in std_logic;
DATA_VLD : out std_logic;
REQ_ACK : out std_logic;
--- rozhrani LCD displeje
KB_IN : out std_logic_vector(3 downto 0);
KB_OUT : in std_logic_vector(3 downto 0)
);
end kb_controller;
architecture behavioral of kb_controller is
-- Keyboard 4x4
component keyboard_controller
port(
CLK : in std_logic;
RST : in std_logic;
DATA_OUT : out std_logic_vector(15 downto 0);
DATA_VLD : out std_logic;
KB_KIN : out std_logic_vector(3 downto 0);
KB_KOUT : in std_logic_vector(3 downto 0)
);
end component;
type t_k2a is array(0 to 15) of std_logic_vector(7 downto 0);
signal key2ascii : t_k2a := (X"31",X"34",X"37",X"0A",X"32",X"35",X"38",X"30",X"33",X"36",X"39",X"0A",X"41",X"42",X"43",X"44");
-- 1,4,7,CR,2,5,8,0,3,6,9,CR,A,B,C,D
signal key_data : std_logic_vector(15 downto 0);
signal key_reg : std_logic_vector(15 downto 0) := (others => '0');
signal key_vld : std_logic;
signal key_chg : std_logic := '0';
signal key_dwn : std_logic;
signal in_data : std_logic_vector(7 downto 0) := (others => '0');
signal in_vld : std_logic := '0';
signal in_st : integer range 0 to 8 := 0;
begin
DATA <= in_data;
DATA_VLD <= in_vld;
-- Radic klavesnice, vstupy
keybrd: entity work.keyboard_controller
port map(
CLK => CLK,
RST => RST, -- reset
DATA_OUT => key_data,
DATA_VLD => key_vld,
-- Keyboart
KB_KIN => KB_IN,
KB_KOUT => KB_OUT
);
process (CLK)
begin
if (CLK'event) and (CLK = '1') then
key_chg <= '0';
if (key_vld = '1') then
if (key_data /= key_reg) then
key_chg <= '1';
key_reg <= key_data;
end if;
end if;
end if;
end process;
key_dwn <= '0' when (key_reg = "0000000000000000") else '1';
process (CLK)
begin
if (CLK'event) and (CLK = '1') then
in_vld <= '0';
in_st <= 0;
REQ_ACK <= '0';
case in_st is
when 0 =>
in_st <= 0;
if (DATA_REQ = '1') then
in_st <= 1;
end if;
when 1 =>
in_st <= 1;
REQ_ACK <= '1'; -- pokud procesor ocekava vstup z klavesnice, rozsvitime D4
if (key_chg = '1') and (key_dwn = '1') then
in_data <= X"00";
in_st <= 0;
for i in 0 to 15 loop
if (conv_integer(key_reg) = 2**i) then
in_data <= key2ascii(i);
in_st <= 2;
end if;
end loop;
end if;
when 2 =>
in_st <= 2;
if (key_chg = '1') and (key_dwn = '0') then
in_st <= 3;
end if;
when 3 =>
in_vld <= '1';
in_st <= 3;
if (DATA_REQ = '0') then
in_st <= 0;
end if;
when others => null;
end case;
end if;
end process;
end behavioral;
| apache-2.0 | ec20bea72cde082fbfe58047123c8fd5 | 0.541796 | 3.876 | false | false | false | false |
peladex/RHD2132_FPGA | quartus/test_spi_comm/test_spi_comm.vhd | 1 | 7,478 | -----------------------------------------------------------------------------------------------------------------------
-- Author:
--
-- Create Date: 11/11/2016 -- dd/mm/yyyy
-- Module Name: test_spi_comm
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Prueba de comunicacion spi entre dos maestros y dos esclavos (1 a 1).
-- Si se da un flanco de subida en send_word_spi1_i(send_word_spi2_i) el bloque spi maestro 1(2) envia una dato a su
-- correspondiente esclavo.
-- El dato a enviar incremente en uno con cada envio.
-- El dato recibido por el escalvo es transferido al otro esclavo (a traves de la interfaz de datos paralelos).
-- Por lo tanto, si se da un flanco de subida en uno de los send_word y luego(*) se da un flanco en el otro, el dato
-- enviado por el primero es recibido por el segundo.
-- No se puede enviar datos por los dos spi maestro a la vez (restriccion del simulador de control maestro)
--
-- (*) Se debe esperar que termine el ciclo spi!
-----------------------------------------------------------------------------------------------------------------------
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
LIBRARY lpm;
USE lpm.lpm_components.ALL;
ENTITY test_spi_comm IS
PORT(
m_clk : in std_logic; -- master clock
m_reset : in std_logic; -- master reset
---- fifo 1 interface ----
f1_do_o : out std_logic_vector(15 downto 0);
f1_wren_o : out std_logic;
---- fifo 2 interface ----
f2_do_o : out std_logic_vector(15 downto 0);
f2_wren_o : out std_logic;
---- user interface ----
send_word_spi1_i : in std_logic;
send_word_spi2_i : in std_logic
);
END test_spi_comm;
ARCHITECTURE synth OF test_spi_comm IS
---- COMPONENTS
COMPONENT test_spi_side IS
PORT(
m_clk : in std_logic; -- master clock
m_reset : in std_logic; -- master reset
---- master_control interface ----
di_1_i : in std_logic_vector(15 downto 0);
do_1_o : out std_logic_vector(15 downto 0);
wren_1_i : in std_logic;
drdy_1_o : out std_logic;
rdreq_1_i : in std_logic;
di_2_i : in std_logic_vector(15 downto 0);
do_2_o : out std_logic_vector(15 downto 0);
wren_2_i : in std_logic;
drdy_2_o : out std_logic;
rdreq_2_i : in std_logic;
---- fifo 1 interface ----
f1_do_o : out std_logic_vector(15 downto 0);
f1_wren_o : out std_logic;
---- fifo 2 interface ----
f2_do_o : out std_logic_vector(15 downto 0);
f2_wren_o : out std_logic;
---- serial interface 1 ----
spi1_ssel_o : out std_logic; -- spi bus slave select line
spi1_sck_o : out std_logic; -- spi bus sck
spi1_mosi_o : out std_logic; -- spi bus mosi output
spi1_miso_i : in std_logic := 'X'; -- spi bus spi_miso_i input
---- serial interface 2 ----
spi2_ssel_o : out std_logic; -- spi bus slave select line
spi2_sck_o : out std_logic; -- spi bus sck
spi2_mosi_o : out std_logic; -- spi bus mosi output
spi2_miso_i : in std_logic := 'X' -- spi bus spi_miso_i input
);
END COMPONENT;
COMPONENT m_control_sim IS
PORT(
m_clk : in std_logic; -- master clock
m_reset : in std_logic; -- master reset
---- master_control interface ----
mc_di_1_i : in std_logic_vector(15 downto 0);
mc_do_1_o : out std_logic_vector(15 downto 0);
mc_wren_1_o : out std_logic;
mc_drdy_1_i : in std_logic;
mc_rdreq_1_o : out std_logic;
mc_di_2_i : in std_logic_vector(15 downto 0);
mc_do_2_o : out std_logic_vector(15 downto 0);
mc_wren_2_o : out std_logic;
mc_drdy_2_i : in std_logic;
mc_rdreq_2_o : out std_logic;
---- user interface ----
send_1_i : in std_logic;
send_2_i : in std_logic
);
END COMPONENT;
COMPONENT test_spi_slaves IS
PORT(
m_clk : in std_logic; -- master clock
m_reset : in std_logic; -- master reset
---- serial interface 1 ----
slave1_ssel_i : in std_logic := 'X'; -- spi bus slave select line
slave1_sck_i : in std_logic := 'X'; -- spi bus sck
slave1_mosi_i : in std_logic := 'X'; -- spi bus mosi output
slave1_miso_o : out std_logic := 'X'; -- spi bus spi_miso_i input
---- serial interface 2 ----
slave2_ssel_i : in std_logic := 'X'; -- spi bus slave select line
slave2_sck_i : in std_logic := 'X'; -- spi bus sck
slave2_mosi_i : in std_logic := 'X'; -- spi bus mosi output
slave2_miso_o : out std_logic := 'X' -- spi bus spi_miso_i input
);
END COMPONENT;
---- SIGNALS
signal sg_mc_do_1_o : std_logic_vector(15 downto 0);
signal sg_mc_wren_1_o : std_logic;
signal sg_mc_rdreq_1_o : std_logic;
signal sg_mc_do_2_o : std_logic_vector(15 downto 0);
signal sg_mc_wren_2_o : std_logic;
signal sg_mc_rdreq_2_o : std_logic;
signal sg_spi1_ssel_o : std_logic;
signal sg_spi1_sck_o : std_logic;
signal sg_spi1_mosi_o : std_logic;
signal sg_spi1_miso_i : std_logic;
signal sg_spi2_ssel_o : std_logic;
signal sg_spi2_sck_o : std_logic;
signal sg_spi2_mosi_o : std_logic;
signal sg_spi2_miso_i : std_logic;
BEGIN
---- INSTANCES
T_spi: test_spi_side port map (
m_clk => m_clk,
m_reset => m_reset,
---- master_control interface ----
di_1_i => sg_mc_do_1_o,
wren_1_i => sg_mc_wren_1_o,
rdreq_1_i => sg_mc_rdreq_1_o,
di_2_i => sg_mc_do_2_o,
wren_2_i => sg_mc_wren_2_o,
rdreq_2_i => sg_mc_rdreq_2_o,
---- fifo 1 interface ----
f1_do_o => f1_do_o,
f1_wren_o => f1_wren_o,
---- fifo 2 interface ----
f2_do_o => f2_do_o,
f2_wren_o => f2_wren_o,
---- serial interface 1 ----
spi1_ssel_o => sg_spi1_ssel_o,
spi1_sck_o => sg_spi1_sck_o,
spi1_mosi_o => sg_spi1_mosi_o,
spi1_miso_i => sg_spi1_miso_i,
---- serial interface 2 ----
spi2_ssel_o => sg_spi2_ssel_o,
spi2_sck_o => sg_spi2_sck_o,
spi2_mosi_o => sg_spi2_mosi_o,
spi2_miso_i => sg_spi2_miso_i
);
MC: m_control_sim port map (
m_clk => m_clk,
m_reset => m_reset,
---- master_control interface ----
mc_di_1_i => X"0000",
mc_do_1_o => sg_mc_do_1_o,
mc_wren_1_o => sg_mc_wren_1_o,
mc_drdy_1_i => '0',
mc_rdreq_1_o => sg_mc_rdreq_1_o,
mc_di_2_i => X"0000",
mc_do_2_o => sg_mc_do_2_o,
mc_wren_2_o => sg_mc_wren_2_o,
mc_drdy_2_i => '0',
mc_rdreq_2_o => sg_mc_rdreq_2_o,
---- user interface ----
send_1_i => send_word_spi1_i,
send_2_i => send_word_spi2_i
);
T_slaves: test_spi_slaves port map (
m_clk => m_clk,
m_reset => m_reset,
---- serial interface 1 ----
slave1_ssel_i => sg_spi1_ssel_o,
slave1_sck_i => sg_spi1_sck_o,
slave1_mosi_i => sg_spi1_mosi_o,
slave1_miso_o => sg_spi1_miso_i,
---- serial interface 2 ----
slave2_ssel_i => sg_spi2_ssel_o,
slave2_sck_i => sg_spi2_sck_o,
slave2_mosi_i => sg_spi2_mosi_o,
slave2_miso_o => sg_spi2_miso_i
);
END synth; | gpl-3.0 | 7970826ae749e51b4e53ad8298d0341f | 0.533298 | 2.819759 | false | false | false | false |
bargei/NoC264 | NoC264_2x2/priority_encoder.vhd | 1 | 2,661 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity priority_encoder is
generic(
encoded_word_size : integer := 2
);
Port(
input : in std_logic_vector(2**encoded_word_size-1 downto 0);
output : out std_logic_vector(encoded_word_size-1 downto 0)
);
end entity priority_encoder;
architecture rtl of priority_encoder is
signal any_previous : std_logic_vector(2**encoded_word_size-1 downto 0);
signal highest_bit_only : std_logic_vector(2**encoded_word_size-1 downto 0);
type encoded_sig_type is array(2**encoded_word_size-1 downto 0) of std_logic_vector(encoded_word_size-1 downto 0);
signal encoded_sig : encoded_sig_type;
begin
--- -- Convert to a one hot encoding
--- highest_bit_only(2**encoded_word_size-1) <= input(2**encoded_word_size-1);
--- any_previous(2**encoded_word_size-1) <= input(2**encoded_word_size-1);
--- one_hot_gen: for i in 2**encoded_word_size-2 downto 0 generate
--- begin
--- any_previous(i) <= input(i) or any_previous(i+1);
--- highest_bit_only(i) <= input(i) and not any_previous(i+1);
--- end generate;
---
--- -- create lookup table to convert from one hot to bin
--- -- will be sparse, but I'll trust the compiler for now
--- one_hot_to_bin <= (others => (others => '0'));
--- encode_lut: for i in encoded_word_size-1 downto 0 generate
--- constant output_value : std_logic_vector := std_logic_vector(to_unsigned(i,encoded_word_size));
--- constant lut_index : integer := 2**i;
--- begin
--- one_hot_to_bin(lut_index) <= output_value;
--- end generate;
---
--- -- output
--- output <= one_hot_to_bin(to_integer(unsigned(highest_bit_only)));
--process(input)
-- variable keep_looking : std_logic := '1';
--begin
-- for i in 2**encoded_word_size-1 downto 0 loop
-- if input(i) = '1' and keep_looking = '1' then
-- output <= std_logic_vector(to_unsigned(i, encoded_word_size));
-- keep_looking := '0';
-- end if;
-- end loop;
--end process;
any_previous(2**encoded_word_size-1) <= input(2**encoded_word_size-1);
encoded_sig(2**encoded_word_size-1) <= std_logic_vector(to_unsigned(2**encoded_word_size-1, encoded_word_size));
encode: for i in 2**encoded_word_size-2 downto 0 generate
begin
any_previous(i) <= input(i) or any_previous(i+1);
encoded_sig(i) <= std_logic_vector(to_unsigned(i, encoded_word_size)) when any_previous(i+1) = '0' else encoded_sig(i+1);
end generate;
output <= encoded_sig(0);
end architecture rtl; | mit | a46cc38124eac8fce47f7afc7745d677 | 0.61631 | 3.186826 | false | false | false | false |
bargei/NoC264 | NoC264_3x3/noc_interface.vhd | 1 | 6,989 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
entity noc_interface is
generic(
data_width : integer := 64;
addr_width : integer := 1;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8;
use_vc : integer := 0
);
port(
--clk, reset
clk : in std_logic;
rst : in std_logic;
--user sending interface
send_data : in std_logic_vector(data_width-1 downto 0);
dest_addr : in std_logic_vector(addr_width-1 downto 0);
set_tail_flit : in std_logic;
send_flit : in std_logic;
ready_to_send : out std_logic;
--user receiving interface
recv_data : out std_logic_vector(data_width-1 downto 0);
src_addr : out std_logic_vector(addr_width-1 downto 0);
is_tail_flit : out std_logic;
data_in_buffer : out std_logic_vector(num_vc-1 downto 0);
dequeue : in std_logic_vector(num_vc-1 downto 0);
select_vc_read : in std_logic_vector(vc_sel_width-1 downto 0);
--interface to network
send_putFlit_flit_in : out std_logic_vector(data_width+addr_width+vc_sel_width+1 downto 0);
EN_send_putFlit : out std_logic;
EN_send_getNonFullVCs : out std_logic;
send_getNonFullVCs : in std_logic_vector(num_vc-1 downto 0);
EN_recv_getFlit : out std_logic;
recv_getFlit : in std_logic_vector(data_width+addr_width+vc_sel_width+1 downto 0);
recv_putNonFullVCs_nonFullVCs : out std_logic_vector(num_vc-1 downto 0);
EN_recv_putNonFullVCs : out std_logic;
recv_info_getRecvPortID : in std_logic_vector(addr_width-1 downto 0)
);
end entity noc_interface;
architecture structural of noc_interface is
--fifo buffer for reciving
component fifo_buffer is
generic(
word_len : integer := 64;
buff_len : integer := 8
);
port(
write_data : in std_logic_vector(word_len-1 downto 0);
read_data : out std_logic_vector(word_len-1 downto 0);
buffer_full : out std_logic;
buffer_empty : out std_logic;
enqueue : in std_logic;
dequeue : in std_logic;
clk : in std_logic;
rst : in std_logic
);
end component fifo_buffer;
type fifo_io is array(num_vc-1 downto 0) of std_logic_vector(vc_sel_width+data_width+addr_width+1 downto 0);
signal write_vc, read_vc: fifo_io;
signal buffer_full_vc, buffer_empty_vc, enqueue_vc, dequeue_vc: std_logic_vector(num_vc-1 downto 0);
signal receive_vc: std_logic_vector(vc_sel_width-1 downto 0);
-- priority encoder
component priority_encoder is
generic(
encoded_word_size : integer := 3
);
Port(
input : in std_logic_vector(2**encoded_word_size-1 downto 0);
output : out std_logic_vector(encoded_word_size-1 downto 0)
);
end component priority_encoder;
signal selected_vc : std_logic_vector(vc_sel_width-1 downto 0);
--constants to parse flits
constant data_msb : integer := data_width-1;
constant data_lsb : integer := 0;
constant vc_msb : integer := vc_sel_width+data_width-1;
constant vc_lsb : integer := data_width;
constant addr_msb : integer := vc_sel_width+data_width+addr_width-1;
constant addr_lsb : integer := vc_sel_width+data_width;
constant is_tail_index : integer := vc_sel_width+data_width+addr_width;
constant is_valid_index : integer := vc_sel_width+data_width+addr_width+1;
constant flit_size : integer := vc_sel_width+data_width+addr_width+2;
begin
---------------------------------------------------------------------------
--RECEIVE SIDE ------------------------------------------------------------
---------------------------------------------------------------------------
-- create and map 1 buffer for each VC
receive_buffer: for i in num_vc-1 downto 0 generate
signal vc_select : integer;
signal flit_valid : std_logic;
begin
ur_i: fifo_buffer generic map(data_width+addr_width+vc_sel_width+2, flit_buff_depth)
port map(write_vc(i), read_vc(i), buffer_full_vc(i), buffer_empty_vc(i),
enqueue_vc(i), dequeue_vc(i), clk, rst);
vc_select <= to_integer(unsigned(recv_getFlit(vc_msb downto vc_lsb)));
flit_valid <= recv_getFlit(is_valid_index);
write_vc(i) <= recv_getFlit when i = vc_select else std_logic_vector(to_unsigned(0,flit_size));
enqueue_vc(i) <= flit_valid when i = vc_select else '0';
end generate;
-- IO for receive side of controller
EN_recv_getFlit <= '1'; -- always read to receive flits as long as buffers aren't full
recv_putNonFullVCs_nonFullVCs <= not buffer_full_vc;
data_in_buffer <= not buffer_empty_vc;
recv_data <= read_vc(to_integer(unsigned(select_vc_read)))(data_msb downto data_lsb);
dequeue_vc <= dequeue;
is_tail_flit <= read_vc(to_integer(unsigned(select_vc_read)))(is_tail_index);
src_addr <= read_vc(to_integer(unsigned(select_vc_read)))(addr_msb downto addr_lsb);
EN_recv_putNonFullVCs <= '1'; -- readme is not clear about what this does, assuming it is not need for peek flow control
---------------------------------------------------------------------------
--SEND SIDE ---------------------------------------------------------------
---------------------------------------------------------------------------
-------- priority encoder to determine which vc to use
------us_0: priority_encoder generic map(vc_sel_width)
------ port map(send_getNonFullVCs, selected_vc);
------
------
-------- IO for sending side of controller
------send_putFlit_flit_in <= send_flit & set_tail_flit & dest_addr & selected_vc & send_data;
--------ready_to_send <= '0' when to_integer(unsigned(send_getNonFullVCs)) = 0 else '1';
--------ready_to_send <= or_reduce(send_getNonFullVCs);
------EN_send_putFlit <= send_flit;
------EN_send_getNonFullVCs <= '1'; --always read to recieve credits
------
------
-- temp version which only sends on a selected vc
-- priority encoder to determine which vc to use
selected_vc <= std_logic_vector(to_unsigned(use_vc, vc_sel_width));
-- IO for sending side of controller
send_putFlit_flit_in <= send_flit & set_tail_flit & dest_addr & selected_vc & send_data;
ready_to_send <= send_getNonFullVCs(use_vc);
EN_send_putFlit <= send_flit;
EN_send_getNonFullVCs <= '1'; --always read to recieve credits
end architecture structural;
| mit | 540843f94e3cec2100a4003037873c91 | 0.560166 | 3.779881 | false | false | false | false |
bargei/NoC264 | NoC264_3x3/inter_core.vhd | 1 | 32,023 | -- Inter-Prediction Interpolator Filter
-- see ITU Std. 8.4.2.2.1 and 8.4.2.2.2
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.math_real.all;
entity inter_core is
generic(
x_len : integer := 4;
y_len : integer := 4;
sample_size : integer := 8
);
port(
samples : in std_logic_vector((x_len+5)*(y_len+5)*sample_size-1 downto 0);
sel : in std_logic_vector(7 downto 0);
result : out std_logic_vector(x_len*y_len*sample_size-1 downto 0)
);
end entity inter_core;
architecture rtl of inter_core is
---------------------------------------------------------------------------
--- Components ------------------------------------------------------------
---------------------------------------------------------------------------
component half_pixel_interpolator_fir is
port(
x0 : in std_logic_vector(7 downto 0);
x1 : in std_logic_vector(7 downto 0);
x2 : in std_logic_vector(7 downto 0);
x3 : in std_logic_vector(7 downto 0);
x4 : in std_logic_vector(7 downto 0);
x5 : in std_logic_vector(7 downto 0);
y : out std_logic_vector(7 downto 0)
);
end component half_pixel_interpolator_fir;
component avg2 is
port(
x0 : in std_logic_vector(7 downto 0);
x1 : in std_logic_vector(7 downto 0);
y : out std_logic_vector(7 downto 0)
);
end component avg2;
---------------------------------------------------------------------------
--- TYPES -----------------------------------------------------------------
---------------------------------------------------------------------------
type sample_row is array(x_len - 1 downto 0) of std_logic_vector(sample_size-1 downto 0);
type sample_array is array(y_len - 1 downto 0) of sample_row;
---------------------------------------------------------------------------
--- SIGNALS ---------------------------------------------------------------
---------------------------------------------------------------------------
--input samples
signal A_in : sample_array;
signal B_in : sample_array;
signal C_in : sample_array;
signal D_in : sample_array;
signal E_in : sample_array;
signal F_in : sample_array;
signal G_in : sample_array;
signal H_in : sample_array;
signal I_in : sample_array;
signal J_in : sample_array;
signal K_in : sample_array;
signal L_in : sample_array;
signal M_in : sample_array;
signal N_in : sample_array;
signal P_in : sample_array;
signal Q_in : sample_array;
signal R_in : sample_array;
signal S_in : sample_array;
signal T_in : sample_array;
signal U_in : sample_array;
-- intermediate interpolation results
signal aa : sample_array;
signal bb : sample_array;
signal cc : sample_array;
signal dd : sample_array;
signal ee : sample_array;
signal ff : sample_array;
signal gg : sample_array;
signal hh : sample_array;
-- final interpolation results
signal a : sample_array;
signal b : sample_array;
signal c : sample_array;
signal d : sample_array;
signal e : sample_array;
signal f : sample_array;
signal g : sample_array;
signal h : sample_array;
signal i : sample_array;
signal j : sample_array;
signal k : sample_array;
signal m : sample_array; --apparently ITU hates the letter l...
signal n : sample_array;
signal p : sample_array;
signal q : sample_array;
signal r : sample_array;
signal s : sample_array;
-- selected interpolation result
signal y : sample_array;
begin
interpx: for nx in x_len-1 downto 0 generate
begin
interpy: for ny in y_len-1 downto 0 generate
-- constants for parsing samples out of "samples"
constant row_0_start : integer := ny * (x_len+5) + nx;
constant row_1_start : integer := (ny+1) * (x_len+5) + nx;
constant row_2_start : integer := (ny+2) * (x_len+5) + nx;
constant row_3_start : integer := (ny+3) * (x_len+5) + nx;
constant row_4_start : integer := (ny+4) * (x_len+5) + nx;
constant row_5_start : integer := (ny+5) * (x_len+5) + nx;
constant g_in_row_pos : integer := 2;
constant g_in_row : integer := row_2_start;
constant g_in_sample_num : integer := g_in_row + g_in_row_pos;
constant g_in_low : integer := g_in_sample_num * sample_size;
constant g_in_high : integer := g_in_low + sample_size - 1;
constant h_in_row_pos : integer := 3;
constant h_in_row : integer := row_2_start;
constant h_in_sample_num : integer := h_in_row + h_in_row_pos;
constant h_in_low : integer := h_in_sample_num * sample_size;
constant h_in_high : integer := h_in_low + sample_size - 1;
constant m_in_row_pos : integer := 2;
constant m_in_row : integer := row_3_start;
constant m_in_sample_num : integer := m_in_row + m_in_row_pos;
constant m_in_low : integer := m_in_sample_num * sample_size;
constant m_in_high : integer := m_in_low + sample_size - 1;
constant sample_0_0_in_row_pos : integer := 0;
constant sample_0_0_in_row : integer := row_0_start;
constant sample_0_0_in_sample_num : integer := sample_0_0_in_row + sample_0_0_in_row_pos;
constant sample_0_0_in_low : integer := sample_0_0_in_sample_num * sample_size;
constant sample_0_0_in_high : integer := sample_0_0_in_low + sample_size - 1;
constant sample_0_1_in_row_pos : integer := 1;
constant sample_0_1_in_row : integer := row_0_start;
constant sample_0_1_in_sample_num : integer := sample_0_1_in_row + sample_0_1_in_row_pos;
constant sample_0_1_in_low : integer := sample_0_1_in_sample_num * sample_size;
constant sample_0_1_in_high : integer := sample_0_1_in_low + sample_size - 1;
constant sample_0_2_in_row_pos : integer := 2;
constant sample_0_2_in_row : integer := row_0_start;
constant sample_0_2_in_sample_num : integer := sample_0_2_in_row + sample_0_2_in_row_pos;
constant sample_0_2_in_low : integer := sample_0_2_in_sample_num * sample_size;
constant sample_0_2_in_high : integer := sample_0_2_in_low + sample_size - 1;
constant sample_0_3_in_row_pos : integer := 3;
constant sample_0_3_in_row : integer := row_0_start;
constant sample_0_3_in_sample_num : integer := sample_0_3_in_row + sample_0_3_in_row_pos;
constant sample_0_3_in_low : integer := sample_0_3_in_sample_num * sample_size;
constant sample_0_3_in_high : integer := sample_0_3_in_low + sample_size - 1;
constant sample_0_4_in_row_pos : integer := 4;
constant sample_0_4_in_row : integer := row_0_start;
constant sample_0_4_in_sample_num : integer := sample_0_4_in_row + sample_0_4_in_row_pos;
constant sample_0_4_in_low : integer := sample_0_4_in_sample_num * sample_size;
constant sample_0_4_in_high : integer := sample_0_4_in_low + sample_size - 1;
constant sample_0_5_in_row_pos : integer := 5;
constant sample_0_5_in_row : integer := row_0_start;
constant sample_0_5_in_sample_num : integer := sample_0_5_in_row + sample_0_5_in_row_pos;
constant sample_0_5_in_low : integer := sample_0_5_in_sample_num * sample_size;
constant sample_0_5_in_high : integer := sample_0_5_in_low + sample_size - 1;
constant sample_1_0_in_row_pos : integer := 0;
constant sample_1_0_in_row : integer := row_1_start;
constant sample_1_0_in_sample_num : integer := sample_1_0_in_row + sample_1_0_in_row_pos;
constant sample_1_0_in_low : integer := sample_1_0_in_sample_num * sample_size;
constant sample_1_0_in_high : integer := sample_1_0_in_low + sample_size - 1;
constant sample_1_1_in_row_pos : integer := 1;
constant sample_1_1_in_row : integer := row_1_start;
constant sample_1_1_in_sample_num : integer := sample_1_1_in_row + sample_1_1_in_row_pos;
constant sample_1_1_in_low : integer := sample_1_1_in_sample_num * sample_size;
constant sample_1_1_in_high : integer := sample_1_1_in_low + sample_size - 1;
constant sample_1_2_in_row_pos : integer := 2;
constant sample_1_2_in_row : integer := row_1_start;
constant sample_1_2_in_sample_num : integer := sample_1_2_in_row + sample_1_2_in_row_pos;
constant sample_1_2_in_low : integer := sample_1_2_in_sample_num * sample_size;
constant sample_1_2_in_high : integer := sample_1_2_in_low + sample_size - 1;
constant sample_1_3_in_row_pos : integer := 3;
constant sample_1_3_in_row : integer := row_1_start;
constant sample_1_3_in_sample_num : integer := sample_1_3_in_row + sample_1_3_in_row_pos;
constant sample_1_3_in_low : integer := sample_1_3_in_sample_num * sample_size;
constant sample_1_3_in_high : integer := sample_1_3_in_low + sample_size - 1;
constant sample_1_4_in_row_pos : integer := 4;
constant sample_1_4_in_row : integer := row_1_start;
constant sample_1_4_in_sample_num : integer := sample_1_4_in_row + sample_1_4_in_row_pos;
constant sample_1_4_in_low : integer := sample_1_4_in_sample_num * sample_size;
constant sample_1_4_in_high : integer := sample_1_4_in_low + sample_size - 1;
constant sample_1_5_in_row_pos : integer := 5;
constant sample_1_5_in_row : integer := row_1_start;
constant sample_1_5_in_sample_num : integer := sample_1_5_in_row + sample_1_5_in_row_pos;
constant sample_1_5_in_low : integer := sample_1_5_in_sample_num * sample_size;
constant sample_1_5_in_high : integer := sample_1_5_in_low + sample_size - 1;
constant sample_2_0_in_row_pos : integer := 0;
constant sample_2_0_in_row : integer := row_2_start;
constant sample_2_0_in_sample_num : integer := sample_2_0_in_row + sample_2_0_in_row_pos;
constant sample_2_0_in_low : integer := sample_2_0_in_sample_num * sample_size;
constant sample_2_0_in_high : integer := sample_2_0_in_low + sample_size - 1;
constant sample_2_1_in_row_pos : integer := 1;
constant sample_2_1_in_row : integer := row_2_start;
constant sample_2_1_in_sample_num : integer := sample_2_1_in_row + sample_2_1_in_row_pos;
constant sample_2_1_in_low : integer := sample_2_1_in_sample_num * sample_size;
constant sample_2_1_in_high : integer := sample_2_1_in_low + sample_size - 1;
constant sample_2_2_in_row_pos : integer := 2;
constant sample_2_2_in_row : integer := row_2_start;
constant sample_2_2_in_sample_num : integer := sample_2_2_in_row + sample_2_2_in_row_pos;
constant sample_2_2_in_low : integer := sample_2_2_in_sample_num * sample_size;
constant sample_2_2_in_high : integer := sample_2_2_in_low + sample_size - 1;
constant sample_2_3_in_row_pos : integer := 3;
constant sample_2_3_in_row : integer := row_2_start;
constant sample_2_3_in_sample_num : integer := sample_2_3_in_row + sample_2_3_in_row_pos;
constant sample_2_3_in_low : integer := sample_2_3_in_sample_num * sample_size;
constant sample_2_3_in_high : integer := sample_2_3_in_low + sample_size - 1;
constant sample_2_4_in_row_pos : integer := 4;
constant sample_2_4_in_row : integer := row_2_start;
constant sample_2_4_in_sample_num : integer := sample_2_4_in_row + sample_2_4_in_row_pos;
constant sample_2_4_in_low : integer := sample_2_4_in_sample_num * sample_size;
constant sample_2_4_in_high : integer := sample_2_4_in_low + sample_size - 1;
constant sample_2_5_in_row_pos : integer := 5;
constant sample_2_5_in_row : integer := row_2_start;
constant sample_2_5_in_sample_num : integer := sample_2_5_in_row + sample_2_5_in_row_pos;
constant sample_2_5_in_low : integer := sample_2_5_in_sample_num * sample_size;
constant sample_2_5_in_high : integer := sample_2_5_in_low + sample_size - 1;
constant sample_3_0_in_row_pos : integer := 0;
constant sample_3_0_in_row : integer := row_3_start;
constant sample_3_0_in_sample_num : integer := sample_3_0_in_row + sample_3_0_in_row_pos;
constant sample_3_0_in_low : integer := sample_3_0_in_sample_num * sample_size;
constant sample_3_0_in_high : integer := sample_3_0_in_low + sample_size - 1;
constant sample_3_1_in_row_pos : integer := 1;
constant sample_3_1_in_row : integer := row_3_start;
constant sample_3_1_in_sample_num : integer := sample_3_1_in_row + sample_3_1_in_row_pos;
constant sample_3_1_in_low : integer := sample_3_1_in_sample_num * sample_size;
constant sample_3_1_in_high : integer := sample_3_1_in_low + sample_size - 1;
constant sample_3_2_in_row_pos : integer := 2;
constant sample_3_2_in_row : integer := row_3_start;
constant sample_3_2_in_sample_num : integer := sample_3_2_in_row + sample_3_2_in_row_pos;
constant sample_3_2_in_low : integer := sample_3_2_in_sample_num * sample_size;
constant sample_3_2_in_high : integer := sample_3_2_in_low + sample_size - 1;
constant sample_3_3_in_row_pos : integer := 3;
constant sample_3_3_in_row : integer := row_3_start;
constant sample_3_3_in_sample_num : integer := sample_3_3_in_row + sample_3_3_in_row_pos;
constant sample_3_3_in_low : integer := sample_3_3_in_sample_num * sample_size;
constant sample_3_3_in_high : integer := sample_3_3_in_low + sample_size - 1;
constant sample_3_4_in_row_pos : integer := 4;
constant sample_3_4_in_row : integer := row_3_start;
constant sample_3_4_in_sample_num : integer := sample_3_4_in_row + sample_3_4_in_row_pos;
constant sample_3_4_in_low : integer := sample_3_4_in_sample_num * sample_size;
constant sample_3_4_in_high : integer := sample_3_4_in_low + sample_size - 1;
constant sample_3_5_in_row_pos : integer := 5;
constant sample_3_5_in_row : integer := row_3_start;
constant sample_3_5_in_sample_num : integer := sample_3_5_in_row + sample_3_5_in_row_pos;
constant sample_3_5_in_low : integer := sample_3_5_in_sample_num * sample_size;
constant sample_3_5_in_high : integer := sample_3_5_in_low + sample_size - 1;
constant sample_4_0_in_row_pos : integer := 0;
constant sample_4_0_in_row : integer := row_4_start;
constant sample_4_0_in_sample_num : integer := sample_4_0_in_row + sample_4_0_in_row_pos;
constant sample_4_0_in_low : integer := sample_4_0_in_sample_num * sample_size;
constant sample_4_0_in_high : integer := sample_4_0_in_low + sample_size - 1;
constant sample_4_1_in_row_pos : integer := 1;
constant sample_4_1_in_row : integer := row_4_start;
constant sample_4_1_in_sample_num : integer := sample_4_1_in_row + sample_4_1_in_row_pos;
constant sample_4_1_in_low : integer := sample_4_1_in_sample_num * sample_size;
constant sample_4_1_in_high : integer := sample_4_1_in_low + sample_size - 1;
constant sample_4_2_in_row_pos : integer := 2;
constant sample_4_2_in_row : integer := row_4_start;
constant sample_4_2_in_sample_num : integer := sample_4_2_in_row + sample_4_2_in_row_pos;
constant sample_4_2_in_low : integer := sample_4_2_in_sample_num * sample_size;
constant sample_4_2_in_high : integer := sample_4_2_in_low + sample_size - 1;
constant sample_4_3_in_row_pos : integer := 3;
constant sample_4_3_in_row : integer := row_4_start;
constant sample_4_3_in_sample_num : integer := sample_4_3_in_row + sample_4_3_in_row_pos;
constant sample_4_3_in_low : integer := sample_4_3_in_sample_num * sample_size;
constant sample_4_3_in_high : integer := sample_4_3_in_low + sample_size - 1;
constant sample_4_4_in_row_pos : integer := 4;
constant sample_4_4_in_row : integer := row_4_start;
constant sample_4_4_in_sample_num : integer := sample_4_4_in_row + sample_4_4_in_row_pos;
constant sample_4_4_in_low : integer := sample_4_4_in_sample_num * sample_size;
constant sample_4_4_in_high : integer := sample_4_4_in_low + sample_size - 1;
constant sample_4_5_in_row_pos : integer := 5;
constant sample_4_5_in_row : integer := row_4_start;
constant sample_4_5_in_sample_num : integer := sample_4_5_in_row + sample_4_5_in_row_pos;
constant sample_4_5_in_low : integer := sample_4_5_in_sample_num * sample_size;
constant sample_4_5_in_high : integer := sample_4_5_in_low + sample_size - 1;
constant sample_5_0_in_row_pos : integer := 0;
constant sample_5_0_in_row : integer := row_5_start;
constant sample_5_0_in_sample_num : integer := sample_5_0_in_row + sample_5_0_in_row_pos;
constant sample_5_0_in_low : integer := sample_5_0_in_sample_num * sample_size;
constant sample_5_0_in_high : integer := sample_5_0_in_low + sample_size - 1;
constant sample_5_1_in_row_pos : integer := 1;
constant sample_5_1_in_row : integer := row_5_start;
constant sample_5_1_in_sample_num : integer := sample_5_1_in_row + sample_5_1_in_row_pos;
constant sample_5_1_in_low : integer := sample_5_1_in_sample_num * sample_size;
constant sample_5_1_in_high : integer := sample_5_1_in_low + sample_size - 1;
constant sample_5_2_in_row_pos : integer := 2;
constant sample_5_2_in_row : integer := row_5_start;
constant sample_5_2_in_sample_num : integer := sample_5_2_in_row + sample_5_2_in_row_pos;
constant sample_5_2_in_low : integer := sample_5_2_in_sample_num * sample_size;
constant sample_5_2_in_high : integer := sample_5_2_in_low + sample_size - 1;
constant sample_5_3_in_row_pos : integer := 3;
constant sample_5_3_in_row : integer := row_5_start;
constant sample_5_3_in_sample_num : integer := sample_5_3_in_row + sample_5_3_in_row_pos;
constant sample_5_3_in_low : integer := sample_5_3_in_sample_num * sample_size;
constant sample_5_3_in_high : integer := sample_5_3_in_low + sample_size - 1;
constant sample_5_4_in_row_pos : integer := 4;
constant sample_5_4_in_row : integer := row_5_start;
constant sample_5_4_in_sample_num : integer := sample_5_4_in_row + sample_5_4_in_row_pos;
constant sample_5_4_in_low : integer := sample_5_4_in_sample_num * sample_size;
constant sample_5_4_in_high : integer := sample_5_4_in_low + sample_size - 1;
constant sample_5_5_in_row_pos : integer := 5;
constant sample_5_5_in_row : integer := row_5_start;
constant sample_5_5_in_sample_num : integer := sample_5_5_in_row + sample_5_5_in_row_pos;
constant sample_5_5_in_low : integer := sample_5_5_in_sample_num * sample_size;
constant sample_5_5_in_high : integer := sample_5_5_in_low + sample_size - 1;
begin
--parse input samples out of the input vector samples
G_in(ny)(nx) <= samples(g_in_high downto g_in_low);
H_in(ny)(nx) <= samples(h_in_high downto h_in_low);
M_in(ny)(nx) <= samples(m_in_high downto m_in_low);
-- half pixel interpolation between whole pixel values
fir_aa: component half_pixel_interpolator_fir port map(
x0 => samples(sample_0_0_in_high downto sample_0_0_in_low),
x1 => samples(sample_0_1_in_high downto sample_0_1_in_low),
x2 => samples(sample_0_2_in_high downto sample_0_2_in_low),
x3 => samples(sample_0_3_in_high downto sample_0_3_in_low),
x4 => samples(sample_0_4_in_high downto sample_0_4_in_low),
x5 => samples(sample_0_5_in_high downto sample_0_5_in_low),
y => aa(ny)(nx)
);
fir_bb: component half_pixel_interpolator_fir port map(
x0 => samples(sample_1_0_in_high downto sample_1_0_in_low),
x1 => samples(sample_1_1_in_high downto sample_1_1_in_low),
x2 => samples(sample_1_2_in_high downto sample_1_2_in_low),
x3 => samples(sample_1_3_in_high downto sample_1_3_in_low),
x4 => samples(sample_1_4_in_high downto sample_1_4_in_low),
x5 => samples(sample_1_5_in_high downto sample_1_5_in_low),
y => bb(ny)(nx)
);
fir_b: component half_pixel_interpolator_fir port map(
x0 => samples(sample_2_0_in_high downto sample_2_0_in_low),
x1 => samples(sample_2_1_in_high downto sample_2_1_in_low),
x2 => samples(sample_2_2_in_high downto sample_2_2_in_low),
x3 => samples(sample_2_3_in_high downto sample_2_3_in_low),
x4 => samples(sample_2_4_in_high downto sample_2_4_in_low),
x5 => samples(sample_2_5_in_high downto sample_2_5_in_low),
y => b(ny)(nx)
);
fir_s: component half_pixel_interpolator_fir port map(
x0 => samples(sample_3_0_in_high downto sample_3_0_in_low),
x1 => samples(sample_3_1_in_high downto sample_3_1_in_low),
x2 => samples(sample_3_2_in_high downto sample_3_2_in_low),
x3 => samples(sample_3_3_in_high downto sample_3_3_in_low),
x4 => samples(sample_3_4_in_high downto sample_3_4_in_low),
x5 => samples(sample_3_5_in_high downto sample_3_5_in_low),
y => s(ny)(nx)
);
fir_gg: component half_pixel_interpolator_fir port map(
x0 => samples(sample_4_0_in_high downto sample_4_0_in_low),
x1 => samples(sample_4_1_in_high downto sample_4_1_in_low),
x2 => samples(sample_4_2_in_high downto sample_4_2_in_low),
x3 => samples(sample_4_3_in_high downto sample_4_3_in_low),
x4 => samples(sample_4_4_in_high downto sample_4_4_in_low),
x5 => samples(sample_4_5_in_high downto sample_4_5_in_low),
y => gg(ny)(nx)
);
fir_hh: component half_pixel_interpolator_fir port map(
x0 => samples(sample_5_0_in_high downto sample_5_0_in_low),
x1 => samples(sample_5_1_in_high downto sample_5_1_in_low),
x2 => samples(sample_5_2_in_high downto sample_5_2_in_low),
x3 => samples(sample_5_3_in_high downto sample_5_3_in_low),
x4 => samples(sample_5_4_in_high downto sample_5_4_in_low),
x5 => samples(sample_5_5_in_high downto sample_5_5_in_low),
y => hh(ny)(nx)
);
fir_cc: component half_pixel_interpolator_fir port map(
x0 => samples(sample_0_0_in_high downto sample_0_0_in_low),
x1 => samples(sample_1_0_in_high downto sample_1_0_in_low),
x2 => samples(sample_2_0_in_high downto sample_2_0_in_low),
x3 => samples(sample_3_0_in_high downto sample_3_0_in_low),
x4 => samples(sample_4_0_in_high downto sample_4_0_in_low),
x5 => samples(sample_5_0_in_high downto sample_5_0_in_low),
y => cc(ny)(nx)
);
fir_dd: component half_pixel_interpolator_fir port map(
x0 => samples(sample_0_1_in_high downto sample_0_1_in_low),
x1 => samples(sample_1_1_in_high downto sample_1_1_in_low),
x2 => samples(sample_2_1_in_high downto sample_2_1_in_low),
x3 => samples(sample_3_1_in_high downto sample_3_1_in_low),
x4 => samples(sample_4_1_in_high downto sample_4_1_in_low),
x5 => samples(sample_5_1_in_high downto sample_5_1_in_low),
y => dd(ny)(nx)
);
fir_h: component half_pixel_interpolator_fir port map(
x0 => samples(sample_0_2_in_high downto sample_0_2_in_low),
x1 => samples(sample_1_2_in_high downto sample_1_2_in_low),
x2 => samples(sample_2_2_in_high downto sample_2_2_in_low),
x3 => samples(sample_3_2_in_high downto sample_3_2_in_low),
x4 => samples(sample_4_2_in_high downto sample_4_2_in_low),
x5 => samples(sample_5_2_in_high downto sample_5_2_in_low),
y => h(ny)(nx)
);
fir_m: component half_pixel_interpolator_fir port map(
x0 => samples(sample_0_3_in_high downto sample_0_3_in_low),
x1 => samples(sample_1_3_in_high downto sample_1_3_in_low),
x2 => samples(sample_2_3_in_high downto sample_2_3_in_low),
x3 => samples(sample_3_3_in_high downto sample_3_3_in_low),
x4 => samples(sample_4_3_in_high downto sample_4_3_in_low),
x5 => samples(sample_5_3_in_high downto sample_5_3_in_low),
y => m(ny)(nx)
);
fir_ee: component half_pixel_interpolator_fir port map(
x0 => samples(sample_0_4_in_high downto sample_0_4_in_low),
x1 => samples(sample_1_4_in_high downto sample_1_4_in_low),
x2 => samples(sample_2_4_in_high downto sample_2_4_in_low),
x3 => samples(sample_3_4_in_high downto sample_3_4_in_low),
x4 => samples(sample_4_4_in_high downto sample_4_4_in_low),
x5 => samples(sample_5_4_in_high downto sample_5_4_in_low),
y => ee(ny)(nx)
);
fir_ff: component half_pixel_interpolator_fir port map(
x0 => samples(sample_0_5_in_high downto sample_0_5_in_low),
x1 => samples(sample_1_5_in_high downto sample_1_5_in_low),
x2 => samples(sample_2_5_in_high downto sample_2_5_in_low),
x3 => samples(sample_3_5_in_high downto sample_3_5_in_low),
x4 => samples(sample_4_5_in_high downto sample_4_5_in_low),
x5 => samples(sample_5_5_in_high downto sample_5_5_in_low),
y => ff(ny)(nx)
);
-- half pixel interpolation from neighboring half pixel values
fir_j: component half_pixel_interpolator_fir port map(
x0 => aa(ny)(nx),
x1 => bb(ny)(nx),
x2 => b(ny)(nx),
x3 => s(ny)(nx),
x4 => gg(ny)(nx),
x5 => hh(ny)(nx),
y => j(ny)(nx)
);
-- quarter pixel interpolation
avg_a: component avg2 port map(x0 => G_in(ny)(nx), x1 => b(ny)(nx), y => a(ny)(nx));
avg_c: component avg2 port map(x0 => H_in(ny)(nx), x1 => b(ny)(nx), y => c(ny)(nx));
avg_d: component avg2 port map(x0 => G_in(ny)(nx), x1 => h(ny)(nx), y => d(ny)(nx));
avg_e: component avg2 port map(x0 => b(ny)(nx) , x1 => h(ny)(nx), y => e(ny)(nx));
avg_f: component avg2 port map(x0 => b(ny)(nx) , x1 => j(ny)(nx), y => f(ny)(nx));
avg_g: component avg2 port map(x0 => b(ny)(nx) , x1 => m(ny)(nx), y => g(ny)(nx));
avg_i: component avg2 port map(x0 => h(ny)(nx) , x1 => j(ny)(nx), y => i(ny)(nx));
avg_k: component avg2 port map(x0 => j(ny)(nx) , x1 => m(ny)(nx), y => k(ny)(nx));
avg_n: component avg2 port map(x0 => M_in(ny)(nx), x1 => h(ny)(nx), y => n(ny)(nx));
avg_p: component avg2 port map(x0 => h(ny)(nx) , x1 => s(ny)(nx), y => p(ny)(nx));
avg_q: component avg2 port map(x0 => j(ny)(nx) , x1 => s(ny)(nx), y => q(ny)(nx));
avg_r: component avg2 port map(x0 => m(ny)(nx) , x1 => s(ny)(nx), y => r(ny)(nx));
--assign output
y(ny)(nx) <= a(ny)(nx) when sel = x"01" else
b(ny)(nx) when sel = x"02" else
c(ny)(nx) when sel = x"03" else
d(ny)(nx) when sel = x"04" else
e(ny)(nx) when sel = x"05" else
f(ny)(nx) when sel = x"06" else
g(ny)(nx) when sel = x"07" else
h(ny)(nx) when sel = x"08" else
i(ny)(nx) when sel = x"09" else
j(ny)(nx) when sel = x"0A" else
k(ny)(nx) when sel = x"0B" else
n(ny)(nx) when sel = x"0C" else
p(ny)(nx) when sel = x"0D" else
q(ny)(nx) when sel = x"0E" else
r(ny)(nx) when sel = x"0F" else
G_in(ny)(nx) when sel = x"00" else
X"00";
end generate;
end generate;
--TODO: considering this is part of a generic component
-- this should be able to function with any valid generic values...
-- not just 2x4
result <= y(0)(0) & y(0)(1) & y(0)(2) & y(0)(3) & y(1)(0) & y(1)(1) & y(1)(2) & y(1)(3);
end architecture rtl;
| mit | 661f0e9d2e6681ecd1cdf81ace79a3d5 | 0.51538 | 3.239227 | false | false | false | false |
freecores/usb_fpga_2_16 | examples/usb-fpga-2.16/2.16b/intraffic/fpga/intraffic.vhd | 4 | 4,447 | library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity intraffic is
port(
RESET : in std_logic;
CONT : in std_logic;
IFCLK_IN : in std_logic;
FD : out std_logic_vector(15 downto 0);
SLOE : out std_logic;
SLRD : out std_logic;
SLWR : out std_logic;
FIFOADR0 : out std_logic;
FIFOADR1 : out std_logic;
PKTEND : out std_logic;
FLAGB : in std_logic
);
end intraffic;
architecture RTL of intraffic is
----------------------------
-- test pattern generator --
----------------------------
-- 30 bit counter
signal GEN_CNT : std_logic_vector(29 downto 0);
signal INT_CNT : std_logic_vector(6 downto 0);
signal FIFO_WORD : std_logic;
signal ifclk,ifclk_fbin,ifclk_fbout,ifclk_out : std_logic;
begin
SLOE <= '1';
SLRD <= '1';
FIFOADR0 <= '0';
FIFOADR1 <= '0';
PKTEND <= '1'; -- no data alignment
-- ifclk filter + deskew
ifclk_fb_buf : BUFG
port map (
I => ifclk_fbout,
O => ifclk_fbin
);
ifclk_out_buf : BUFG
port map (
I => ifclk_out,
O => ifclk
);
ifclk_mmcm : MMCME2_BASE
generic map (
BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
CLKFBOUT_MULT_F => 20.0, -- Multiply value for all CLKOUT, (2-64)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
CLKIN1_PERIOD => 0.0, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
CLKOUT0_DIVIDE_F => 20.0,
CLKOUT1_DIVIDE => 1,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 0.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
CLKOUT4_CASCADE => FALSE, -- Cascade CLKOUT4 counter with CLKOUT6 (FALSE, TRUE)
DIVCLK_DIVIDE => 1, -- Master division value, (1-56)
REF_JITTER1 => 0.0, -- Reference input jitter in UI, (0.000-0.999).
STARTUP_WAIT => FALSE -- Delay DONE until MMCM Locks, (TRUE / FALSE)
)
port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKOUT0 => ifclk_out, -- 1-bit output: CLKOUT0
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => ifclk_fbout, -- 1-bit output: Feedback clock
CLKIN1 => ifclk_in, -- 1-bit input: Input clock
-- Control Ports: 1-bit (each) input: PLL control ports
PWRDWN => '0', -- 1-bit input: Power-down
RST => RESET, -- 1-bit input: Reset
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
CLKFBIN => ifclk_fbin -- 1-bit input: Feedback clock
);
dpIFCLK: process (IFCLK, RESET)
begin
-- reset
if RESET = '1'
then
GEN_CNT <= ( others => '0' );
INT_CNT <= ( others => '0' );
FIFO_WORD <= '0';
SLWR <= '1';
-- IFCLK
elsif IFCLK'event and IFCLK = '1'
then
if CONT = '1' or FLAGB = '1'
then
if FIFO_WORD = '0'
then
FD(14 downto 0) <= GEN_CNT(14 downto 0);
else
FD(14 downto 0) <= GEN_CNT(29 downto 15);
end if;
FD(15) <= FIFO_WORD;
if FIFO_WORD = '1'
then
GEN_CNT <= GEN_CNT + '1';
if INT_CNT = conv_std_logic_vector(99,7)
then
INT_CNT <= ( others => '0' );
else
INT_CNT <= INT_CNT + '1';
end if;
end if;
FIFO_WORD <= not FIFO_WORD;
end if;
if ( INT_CNT >= conv_std_logic_vector(90,7) ) and ( CONT = '0' )
then
SLWR <= '1';
else
SLWR <= '0';
end if;
end if;
end process dpIFCLK;
end RTL;
| gpl-3.0 | f00a11e672966dd88e0f5324e33040cc | 0.534293 | 3.392067 | false | false | false | false |
peladex/RHD2132_FPGA | quartus/test_spi_side/test_spi_side.vhd | 1 | 8,552 | -----------------------------------------------------------------------------------------------------------------------
-- Author:
--
-- Create Date: 09/11/2016 -- dd/mm/yyyy
-- Module Name: test_spi_side
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Prueba de comunicacion entre el bloque interconnect y los dos bloques spi maestros.
--
--
-----------------------------------------------------------------------------------------------------------------------
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
LIBRARY lpm;
USE lpm.lpm_components.ALL;
ENTITY test_spi_side IS
PORT(
m_clk : in std_logic; -- master clock
m_reset : in std_logic; -- master reset
---- master_control interface ----
di_1_i : in std_logic_vector(15 downto 0);
do_1_o : out std_logic_vector(15 downto 0);
wren_1_i : in std_logic;
drdy_1_o : out std_logic;
rdreq_1_i : in std_logic;
di_2_i : in std_logic_vector(15 downto 0);
do_2_o : out std_logic_vector(15 downto 0);
wren_2_i : in std_logic;
drdy_2_o : out std_logic;
rdreq_2_i : in std_logic;
---- fifo 1 interface ----
f1_do_o : out std_logic_vector(15 downto 0);
f1_wren_o : out std_logic;
---- fifo 2 interface ----
f2_do_o : out std_logic_vector(15 downto 0);
f2_wren_o : out std_logic;
---- serial interface 1 ----
spi1_ssel_o : out std_logic; -- spi bus slave select line
spi1_sck_o : out std_logic; -- spi bus sck
spi1_mosi_o : out std_logic; -- spi bus mosi output
spi1_miso_i : in std_logic := 'X'; -- spi bus spi_miso_i input
---- serial interface 2 ----
spi2_ssel_o : out std_logic; -- spi bus slave select line
spi2_sck_o : out std_logic; -- spi bus sck
spi2_mosi_o : out std_logic; -- spi bus mosi output
spi2_miso_i : in std_logic := 'X' -- spi bus spi_miso_i input
);
END test_spi_side;
ARCHITECTURE synth OF test_spi_side IS
---- COMPONENTS
COMPONENT interconnect IS
PORT (
---- master_control interface ----
di_1_i : in std_logic_vector(15 downto 0);
do_1_o : out std_logic_vector(15 downto 0);
wren_1_i : in std_logic; --triggers spi cycle
drdy_1_o : out std_logic;
rdreq_1_i : in std_logic;
di_2_i : in std_logic_vector(15 downto 0);
do_2_o : out std_logic_vector(15 downto 0);
wren_2_i : in std_logic; --triggers spi cycle
drdy_2_o : out std_logic;
rdreq_2_i : in std_logic;
---- spi 1 interface ----
s1_do_o : out std_logic_vector(15 downto 0);
s1_di_i : in std_logic_vector(15 downto 0);
s1_wren_o : out std_logic;
s1_drdy_i : in std_logic;
---- spi 2 interface ----
s2_do_o : out std_logic_vector(15 downto 0);
s2_di_i : in std_logic_vector(15 downto 0);
s2_wren_o : out std_logic;
s2_drdy_i : in std_logic;
---- fifo 1 interface ----
f1_do_o : out std_logic_vector(15 downto 0);
f1_wren_o : out std_logic;
---- fifo 2 interface ----
f2_do_o : out std_logic_vector(15 downto 0);
f2_wren_o : out std_logic
);
END COMPONENT;
COMPONENT spi_master IS
Generic (
N : positive := 16; -- 32bit serial word length is default
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
CPHA : std_logic := '0'; -- CPOL = clock polarity, CPHA = clock phase.
PREFETCH : positive := 2; -- prefetch lookahead cycles
SPI_2X_CLK_DIV : positive := 2); -- for a 100MHz sclk_i, yields a 25MHz SCK
Port (
sclk_i : in std_logic := 'X'; -- high-speed serial interface system clock
pclk_i : in std_logic := 'X'; -- high-speed parallel interface system clock
rst_i : in std_logic := 'X'; -- reset core
---- serial interface ----
spi_ssel_o : out std_logic; -- spi bus slave select line
spi_sck_o : out std_logic; -- spi bus sck
spi_mosi_o : out std_logic; -- spi bus mosi output
spi_miso_i : in std_logic := 'X'; -- spi bus spi_miso_i input
---- parallel interface ----
di_req_o : out std_logic; -- preload lookahead data request line
di_i : in std_logic_vector (N-1 downto 0) := (others => 'X'); -- parallel data in (clocked on rising spi_clk after last bit)
wren_i : in std_logic := 'X'; -- user data write enable, starts transmission when interface is idle
wr_ack_o : out std_logic; -- write acknowledge
do_valid_o : out std_logic; -- do_o data valid signal, valid during one spi_clk rising edge.
do_o : out std_logic_vector (N-1 downto 0); -- parallel output (clocked on rising spi_clk after last bit)
--- debug ports: can be removed or left unconnected for the application circuit ---
sck_ena_o : out std_logic; -- debug: internal sck enable signal
sck_ena_ce_o : out std_logic; -- debug: internal sck clock enable signal
do_transfer_o : out std_logic; -- debug: internal transfer driver
wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher
rx_bit_reg_o : out std_logic; -- debug: internal rx bit
state_dbg_o : out std_logic_vector (3 downto 0); -- debug: internal state register
core_clk_o : out std_logic;
core_n_clk_o : out std_logic;
core_ce_o : out std_logic;
core_n_ce_o : out std_logic;
sh_reg_dbg_o : out std_logic_vector (N-1 downto 0) -- debug: internal shift register
);
END COMPONENT;
---- SIGNALS
SIGNAL sg_pll_out_clk : std_logic;
SIGNAL sg_do_1, sg_di_1 : std_logic_vector(15 downto 0);
SIGNAL sg_wren_1, sg_drdy_1 : std_logic;
SIGNAL sg_do_2, sg_di_2 : std_logic_vector(15 downto 0);
SIGNAL sg_wren_2, sg_drdy_2 : std_logic;
BEGIN
---- INSTANCES
U0: interconnect PORT MAP (
---- master_control interface ----
di_1_i => di_1_i,
do_1_o => do_1_o,
wren_1_i => wren_1_i,
drdy_1_o => drdy_1_o,
rdreq_1_i => rdreq_1_i,
di_2_i => di_2_i,
do_2_o => do_2_o,
wren_2_i => wren_2_i,
drdy_2_o => drdy_2_o,
rdreq_2_i => rdreq_2_i,
---- spi 1 interface ----
s1_do_o => sg_do_1,
s1_di_i => sg_di_1,
s1_wren_o => sg_wren_1,
s1_drdy_i => sg_drdy_1,
---- spi 2 interface ----
s2_do_o => sg_do_2,
s2_di_i => sg_di_2,
s2_wren_o => sg_wren_2,
s2_drdy_i => sg_drdy_2,
---- fifo 1 interface ----
f1_do_o => f1_do_o,
f1_wren_o => f1_wren_o,
---- fifo 2 interface ----
f2_do_o => f2_do_o,
f2_wren_o => f2_wren_o
);
SPI_1: spi_master PORT MAP (
sclk_i => sg_pll_out_clk,
pclk_i => sg_pll_out_clk,
rst_i => m_reset,
---- serial interface ----
spi_ssel_o => spi1_ssel_o,
spi_sck_o => spi1_sck_o,
spi_mosi_o => spi1_mosi_o,
spi_miso_i => spi1_miso_i,
---- parallel interface ----
di_i => sg_do_1,
wren_i => sg_wren_1,
do_valid_o => sg_drdy_1,
do_o => sg_di_1
);
SPI_2: spi_master PORT MAP (
sclk_i => sg_pll_out_clk,
pclk_i => sg_pll_out_clk,
rst_i => m_reset,
---- serial interface ----
spi_ssel_o => spi2_ssel_o,
spi_sck_o => spi2_sck_o,
spi_mosi_o => spi2_mosi_o,
spi_miso_i => spi2_miso_i,
---- parallel interface ----
di_i => sg_do_2,
wren_i => sg_wren_2,
do_valid_o => sg_drdy_2,
do_o => sg_di_2
);
sg_pll_out_clk <= m_clk;
END synth; | gpl-3.0 | 6915d348ee179c83db2664fdf4602384 | 0.485851 | 3.316014 | false | false | false | false |
DaveyPocket/btrace448 | core/debounceCounter.vhd | 1 | 592 | -- Btrace 448
-- Debounce Counter
--
-- Bradley Boccuzzi
-- 2016
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity debounceCounter is
generic(k: integer);
port(en, rst, clk: in std_logic;
Q: out std_logic_vector(k-1 downto 0));
end debounceCounter;
architecture yeayea of debounceCounter is
signal Qbuf: std_logic_vector(k-1 downto 0);
begin
Q <= Qbuf;
process(clk, rst)
begin
if (rst = '1') then
Qbuf <= (others => '0');
elsif rising_edge(clk) then
if (en = '1') then
Qbuf <= Qbuf + 1;
end if;
end if;
end process;
end yeayea;
| gpl-3.0 | 51c1e919a05667f761a833ef03be8a34 | 0.66723 | 2.728111 | false | false | false | false |
fkolacek/FIT-VUT | INP2/fpga/ram.vhd | 1 | 1,794 | -- ram.vhd : RAM memory
-- Copyright (C) 2011 Brno University of Technology,
-- Faculty of Information Technology
-- Author(s): Zdenek Vasicek <vasicek AT fit.vutbr.cz>
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity ram is
port (
CLK : in std_logic; -- hodiny
ADDR : in std_logic_vector(9 downto 0); -- adresa bunky
WDATA : in std_logic_vector(7 downto 0); -- data pro zapis
RDATA : out std_logic_vector(7 downto 0); -- nactena data (v dalsim taktu, pokud EN=1)
RDWR : in std_logic; -- 0 - cteni, 1 - zapis
EN : in std_logic -- 1 - povoleni prace s pameti
);
end ram;
-- ----------------------------------------------------------------------------
-- Architecture declaration
-- ----------------------------------------------------------------------------
architecture behavioral of ram is
type t_ram is array (0 to 2**10-1) of std_logic_vector (7 downto 0);
signal ram: t_ram := (others => X"00");
signal rd : std_logic_vector (7 downto 0) := (others => '0');
begin
RDATA <= rd;
-- RAM rd / wr
sram_mem: process (CLK)
begin
if (CLK'event) and (CLK = '1') then
if (EN = '1') then
if (RDWR = '1') then
ram(conv_integer(ADDR)) <= WDATA;
rd <= WDATA;
else
rd <= ram(conv_integer(ADDR));
end if;
end if;
end if;
end process;
end behavioral;
| apache-2.0 | 816525530f9b5dd203d69203b19afef2 | 0.429766 | 4.251185 | false | false | false | false |
boztalay/OldProjects | FPGA/Systems/Sys_LCDTest/netgen/synthesis/Sys_LCDTest_synthesis.vhd | 1 | 230,789 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: K.31
-- \ \ Application: netgen
-- / / Filename: Sys_LCDTest_synthesis.vhd
-- /___/ /\ Timestamp: Wed Apr 15 22:11:26 2009
-- \ \ / \
-- \___\/\___\
--
-- Command : -intstyle ise -ar Structure -tm Sys_LCDTest -w -dir netgen/synthesis -ofmt vhdl -sim Sys_LCDTest.ngc Sys_LCDTest_synthesis.vhd
-- Device : xc3s500e-4-fg320
-- Input file : Sys_LCDTest.ngc
-- Output file : C:\Users\Ben\Desktop\FPGAprojects\Systems\Sys_LCDTest\netgen\synthesis\Sys_LCDTest_synthesis.vhd
-- # of Entities : 1
-- Design Name : Sys_LCDTest
-- Xilinx : C:\Xilinx\10.1\ISE
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Development System Reference Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity Sys_LCDTest is
port (
E : out STD_LOGIC;
RS : out STD_LOGIC;
RW : out STD_LOGIC;
SysCLK : in STD_LOGIC := 'X';
databus : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end Sys_LCDTest;
architecture Structure of Sys_LCDTest is
signal Buf_CLK1MHz : STD_LOGIC;
signal Buf_SysCLK : STD_LOGIC;
signal E_OBUF_3 : STD_LOGIC;
signal G1_CLK1MHz_4 : STD_LOGIC;
signal G1_CLK1MHz_cmp_eq0000_5 : STD_LOGIC;
signal G1_Madd_cnt_add0000_cy_10_rt_22 : STD_LOGIC;
signal G1_Madd_cnt_add0000_cy_11_rt_24 : STD_LOGIC;
signal G1_Madd_cnt_add0000_cy_12_rt_26 : STD_LOGIC;
signal G1_Madd_cnt_add0000_cy_13_rt_28 : STD_LOGIC;
signal G1_Madd_cnt_add0000_cy_14_rt_30 : STD_LOGIC;
signal G1_Madd_cnt_add0000_cy_15_rt_32 : STD_LOGIC;
signal G1_Madd_cnt_add0000_cy_16_rt_34 : STD_LOGIC;
signal G1_Madd_cnt_add0000_cy_17_rt_36 : STD_LOGIC;
signal G1_Madd_cnt_add0000_cy_18_rt_38 : STD_LOGIC;
signal G1_Madd_cnt_add0000_cy_19_rt_40 : STD_LOGIC;
signal G1_Madd_cnt_add0000_cy_1_rt_42 : STD_LOGIC;
signal G1_Madd_cnt_add0000_cy_20_rt_44 : STD_LOGIC;
signal G1_Madd_cnt_add0000_cy_21_rt_46 : STD_LOGIC;
signal G1_Madd_cnt_add0000_cy_22_rt_48 : STD_LOGIC;
signal G1_Madd_cnt_add0000_cy_23_rt_50 : STD_LOGIC;
signal G1_Madd_cnt_add0000_cy_24_rt_52 : STD_LOGIC;
signal G1_Madd_cnt_add0000_cy_25_rt_54 : STD_LOGIC;
signal G1_Madd_cnt_add0000_cy_26_rt_56 : STD_LOGIC;
signal G1_Madd_cnt_add0000_cy_27_rt_58 : STD_LOGIC;
signal G1_Madd_cnt_add0000_cy_28_rt_60 : STD_LOGIC;
signal G1_Madd_cnt_add0000_cy_29_rt_62 : STD_LOGIC;
signal G1_Madd_cnt_add0000_cy_2_rt_64 : STD_LOGIC;
signal G1_Madd_cnt_add0000_cy_30_rt_66 : STD_LOGIC;
signal G1_Madd_cnt_add0000_cy_3_rt_68 : STD_LOGIC;
signal G1_Madd_cnt_add0000_cy_4_rt_70 : STD_LOGIC;
signal G1_Madd_cnt_add0000_cy_5_rt_72 : STD_LOGIC;
signal G1_Madd_cnt_add0000_cy_6_rt_74 : STD_LOGIC;
signal G1_Madd_cnt_add0000_cy_7_rt_76 : STD_LOGIC;
signal G1_Madd_cnt_add0000_cy_8_rt_78 : STD_LOGIC;
signal G1_Madd_cnt_add0000_cy_9_rt_80 : STD_LOGIC;
signal G1_Madd_cnt_add0000_xor_31_rt_82 : STD_LOGIC;
signal G1_Mcount_cnt_cy_10_rt_85 : STD_LOGIC;
signal G1_Mcount_cnt_cy_11_rt_87 : STD_LOGIC;
signal G1_Mcount_cnt_cy_12_rt_89 : STD_LOGIC;
signal G1_Mcount_cnt_cy_13_rt_91 : STD_LOGIC;
signal G1_Mcount_cnt_cy_14_rt_93 : STD_LOGIC;
signal G1_Mcount_cnt_cy_15_rt_95 : STD_LOGIC;
signal G1_Mcount_cnt_cy_16_rt_97 : STD_LOGIC;
signal G1_Mcount_cnt_cy_17_rt_99 : STD_LOGIC;
signal G1_Mcount_cnt_cy_18_rt_101 : STD_LOGIC;
signal G1_Mcount_cnt_cy_19_rt_103 : STD_LOGIC;
signal G1_Mcount_cnt_cy_1_rt_105 : STD_LOGIC;
signal G1_Mcount_cnt_cy_20_rt_107 : STD_LOGIC;
signal G1_Mcount_cnt_cy_21_rt_109 : STD_LOGIC;
signal G1_Mcount_cnt_cy_22_rt_111 : STD_LOGIC;
signal G1_Mcount_cnt_cy_23_rt_113 : STD_LOGIC;
signal G1_Mcount_cnt_cy_24_rt_115 : STD_LOGIC;
signal G1_Mcount_cnt_cy_25_rt_117 : STD_LOGIC;
signal G1_Mcount_cnt_cy_26_rt_119 : STD_LOGIC;
signal G1_Mcount_cnt_cy_27_rt_121 : STD_LOGIC;
signal G1_Mcount_cnt_cy_28_rt_123 : STD_LOGIC;
signal G1_Mcount_cnt_cy_29_rt_125 : STD_LOGIC;
signal G1_Mcount_cnt_cy_2_rt_127 : STD_LOGIC;
signal G1_Mcount_cnt_cy_30_rt_129 : STD_LOGIC;
signal G1_Mcount_cnt_cy_3_rt_131 : STD_LOGIC;
signal G1_Mcount_cnt_cy_4_rt_133 : STD_LOGIC;
signal G1_Mcount_cnt_cy_5_rt_135 : STD_LOGIC;
signal G1_Mcount_cnt_cy_6_rt_137 : STD_LOGIC;
signal G1_Mcount_cnt_cy_7_rt_139 : STD_LOGIC;
signal G1_Mcount_cnt_cy_8_rt_141 : STD_LOGIC;
signal G1_Mcount_cnt_cy_9_rt_143 : STD_LOGIC;
signal G1_Mcount_cnt_xor_31_rt_145 : STD_LOGIC;
signal G1_cnt_cmp_eq0000_209 : STD_LOGIC;
signal Madd_databus_add0000_cy_11_rt_212 : STD_LOGIC;
signal Madd_databus_add0000_cy_13_rt_215 : STD_LOGIC;
signal Madd_databus_add0000_cy_15_rt_218 : STD_LOGIC;
signal Madd_databus_add0000_cy_16_rt_220 : STD_LOGIC;
signal Madd_databus_add0000_cy_17_rt_222 : STD_LOGIC;
signal Madd_databus_add0000_cy_18_rt_224 : STD_LOGIC;
signal Madd_databus_add0000_cy_19_rt_226 : STD_LOGIC;
signal Madd_databus_add0000_cy_20_rt_228 : STD_LOGIC;
signal Madd_databus_add0000_cy_21_rt_230 : STD_LOGIC;
signal Madd_databus_add0000_cy_22_rt_232 : STD_LOGIC;
signal Madd_databus_add0000_cy_23_rt_234 : STD_LOGIC;
signal Madd_databus_add0000_cy_24_rt_236 : STD_LOGIC;
signal Madd_databus_add0000_cy_25_rt_238 : STD_LOGIC;
signal Madd_databus_add0000_cy_26_rt_240 : STD_LOGIC;
signal Madd_databus_add0000_cy_27_rt_242 : STD_LOGIC;
signal Madd_databus_add0000_cy_28_rt_244 : STD_LOGIC;
signal Madd_databus_add0000_cy_29_rt_246 : STD_LOGIC;
signal Madd_databus_add0000_cy_30_rt_248 : STD_LOGIC;
signal Madd_databus_add0000_cy_9_rt_255 : STD_LOGIC;
signal Madd_databus_add0000_lut_10_Q : STD_LOGIC;
signal Madd_databus_add0000_lut_12_Q : STD_LOGIC;
signal Madd_databus_add0000_lut_14_Q : STD_LOGIC;
signal Madd_databus_add0000_lut_4_Q : STD_LOGIC;
signal Madd_databus_add0000_lut_5_Q : STD_LOGIC;
signal Madd_databus_add0000_lut_6_Q : STD_LOGIC;
signal Madd_databus_add0000_lut_7_Q : STD_LOGIC;
signal Madd_databus_add0000_lut_8_Q : STD_LOGIC;
signal Madd_databus_add0000_xor_31_rt_264 : STD_LOGIC;
signal Madd_index_addsub0000_cy_10_rt_267 : STD_LOGIC;
signal Madd_index_addsub0000_cy_11_rt_269 : STD_LOGIC;
signal Madd_index_addsub0000_cy_12_rt_271 : STD_LOGIC;
signal Madd_index_addsub0000_cy_13_rt_273 : STD_LOGIC;
signal Madd_index_addsub0000_cy_14_rt_275 : STD_LOGIC;
signal Madd_index_addsub0000_cy_15_rt_277 : STD_LOGIC;
signal Madd_index_addsub0000_cy_16_rt_279 : STD_LOGIC;
signal Madd_index_addsub0000_cy_17_rt_281 : STD_LOGIC;
signal Madd_index_addsub0000_cy_18_rt_283 : STD_LOGIC;
signal Madd_index_addsub0000_cy_19_rt_285 : STD_LOGIC;
signal Madd_index_addsub0000_cy_1_rt_287 : STD_LOGIC;
signal Madd_index_addsub0000_cy_20_rt_289 : STD_LOGIC;
signal Madd_index_addsub0000_cy_21_rt_291 : STD_LOGIC;
signal Madd_index_addsub0000_cy_22_rt_293 : STD_LOGIC;
signal Madd_index_addsub0000_cy_23_rt_295 : STD_LOGIC;
signal Madd_index_addsub0000_cy_24_rt_297 : STD_LOGIC;
signal Madd_index_addsub0000_cy_25_rt_299 : STD_LOGIC;
signal Madd_index_addsub0000_cy_26_rt_301 : STD_LOGIC;
signal Madd_index_addsub0000_cy_27_rt_303 : STD_LOGIC;
signal Madd_index_addsub0000_cy_28_rt_305 : STD_LOGIC;
signal Madd_index_addsub0000_cy_29_rt_307 : STD_LOGIC;
signal Madd_index_addsub0000_cy_2_rt_309 : STD_LOGIC;
signal Madd_index_addsub0000_cy_30_rt_311 : STD_LOGIC;
signal Madd_index_addsub0000_cy_3_rt_313 : STD_LOGIC;
signal Madd_index_addsub0000_cy_4_rt_315 : STD_LOGIC;
signal Madd_index_addsub0000_cy_5_rt_317 : STD_LOGIC;
signal Madd_index_addsub0000_cy_6_rt_319 : STD_LOGIC;
signal Madd_index_addsub0000_cy_7_rt_321 : STD_LOGIC;
signal Madd_index_addsub0000_cy_8_rt_323 : STD_LOGIC;
signal Madd_index_addsub0000_cy_9_rt_325 : STD_LOGIC;
signal Madd_index_addsub0000_xor_31_rt_327 : STD_LOGIC;
signal Madd_wait_time_share0000_cy_10_rt_329 : STD_LOGIC;
signal Madd_wait_time_share0000_cy_11_rt_331 : STD_LOGIC;
signal Madd_wait_time_share0000_cy_12_rt_333 : STD_LOGIC;
signal Madd_wait_time_share0000_cy_13_rt_335 : STD_LOGIC;
signal Madd_wait_time_share0000_cy_14_rt_337 : STD_LOGIC;
signal Madd_wait_time_share0000_cy_15_rt_339 : STD_LOGIC;
signal Madd_wait_time_share0000_cy_16_rt_341 : STD_LOGIC;
signal Madd_wait_time_share0000_cy_17_rt_343 : STD_LOGIC;
signal Madd_wait_time_share0000_cy_18_rt_345 : STD_LOGIC;
signal Madd_wait_time_share0000_cy_19_rt_347 : STD_LOGIC;
signal Madd_wait_time_share0000_cy_20_rt_350 : STD_LOGIC;
signal Madd_wait_time_share0000_cy_21_rt_352 : STD_LOGIC;
signal Madd_wait_time_share0000_cy_22_rt_354 : STD_LOGIC;
signal Madd_wait_time_share0000_cy_23_rt_356 : STD_LOGIC;
signal Madd_wait_time_share0000_cy_24_rt_358 : STD_LOGIC;
signal Madd_wait_time_share0000_cy_25_rt_360 : STD_LOGIC;
signal Madd_wait_time_share0000_cy_26_rt_362 : STD_LOGIC;
signal Madd_wait_time_share0000_cy_27_rt_364 : STD_LOGIC;
signal Madd_wait_time_share0000_cy_28_rt_366 : STD_LOGIC;
signal Madd_wait_time_share0000_cy_29_rt_368 : STD_LOGIC;
signal Madd_wait_time_share0000_cy_2_rt_370 : STD_LOGIC;
signal Madd_wait_time_share0000_cy_30_rt_372 : STD_LOGIC;
signal Madd_wait_time_share0000_cy_3_rt_374 : STD_LOGIC;
signal Madd_wait_time_share0000_cy_6_rt_378 : STD_LOGIC;
signal Madd_wait_time_share0000_cy_7_rt_380 : STD_LOGIC;
signal Madd_wait_time_share0000_cy_8_rt_382 : STD_LOGIC;
signal Madd_wait_time_share0000_cy_9_rt_384 : STD_LOGIC;
signal Madd_wait_time_share0000_lut_1_Q : STD_LOGIC;
signal Madd_wait_time_share0000_lut_4_Q : STD_LOGIC;
signal Madd_wait_time_share0000_lut_5_Q : STD_LOGIC;
signal Madd_wait_time_share0000_xor_31_rt_388 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_0_1_422 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_0_2_423 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_0_3 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_0_0_rt_425 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_0_1_rt_426 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_0_2_rt_427 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_10_1_429 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_10_2 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_1_1_433 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_1_2_434 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_1_3 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_1_rt_436 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_2_1_438 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_2_2_439 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_2_3 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_2_1_rt_441 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_3_1_443 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_3_2_444 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_3_3 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_3_rt_446 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_4_1_448 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_4_2_449 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_4_3 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_4_2_rt_451 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_5_1_453 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_5_2_454 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_5_3 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_5_rt_456 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_6_1_458 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_6_2_459 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_6_3 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_6_0_rt_461 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_6_1_rt_462 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_7_1_464 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_7_2_465 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_7_3 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_7_rt_467 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_8_1_469 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_8_2_470 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_8_3 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_9_1_473 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_cy_9_2_474 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_lut_10_1_477 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_lut_10_2_478 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_lut_11_1 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_lut_11_2 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_lut_1_1_484 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_lut_1_2_485 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_lut_2_1_487 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_lut_2_2_488 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_lut_3_1 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_lut_3_2_491 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_lut_4_1_493 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_lut_4_2_494 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_lut_5_1_496 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_lut_5_2_497 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_lut_6_1_499 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_lut_7_1_501 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_lut_7_2_502 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_lut_8_1_504 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_lut_8_2_505 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_lut_8_3_506 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_lut_9_1_508 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_lut_9_2_509 : STD_LOGIC;
signal Mcompar_wait_time_cmp_ge0000_lut_9_3 : STD_LOGIC;
signal Mcount_count_us_cy_10_rt_594 : STD_LOGIC;
signal Mcount_count_us_cy_11_rt_596 : STD_LOGIC;
signal Mcount_count_us_cy_12_rt_598 : STD_LOGIC;
signal Mcount_count_us_cy_13_rt_600 : STD_LOGIC;
signal Mcount_count_us_cy_14_rt_602 : STD_LOGIC;
signal Mcount_count_us_cy_15_rt_604 : STD_LOGIC;
signal Mcount_count_us_cy_16_rt_606 : STD_LOGIC;
signal Mcount_count_us_cy_17_rt_608 : STD_LOGIC;
signal Mcount_count_us_cy_18_rt_610 : STD_LOGIC;
signal Mcount_count_us_cy_19_rt_612 : STD_LOGIC;
signal Mcount_count_us_cy_1_rt_614 : STD_LOGIC;
signal Mcount_count_us_cy_20_rt_616 : STD_LOGIC;
signal Mcount_count_us_cy_21_rt_618 : STD_LOGIC;
signal Mcount_count_us_cy_22_rt_620 : STD_LOGIC;
signal Mcount_count_us_cy_23_rt_622 : STD_LOGIC;
signal Mcount_count_us_cy_24_rt_624 : STD_LOGIC;
signal Mcount_count_us_cy_25_rt_626 : STD_LOGIC;
signal Mcount_count_us_cy_26_rt_628 : STD_LOGIC;
signal Mcount_count_us_cy_27_rt_630 : STD_LOGIC;
signal Mcount_count_us_cy_28_rt_632 : STD_LOGIC;
signal Mcount_count_us_cy_29_rt_634 : STD_LOGIC;
signal Mcount_count_us_cy_2_rt_636 : STD_LOGIC;
signal Mcount_count_us_cy_30_rt_638 : STD_LOGIC;
signal Mcount_count_us_cy_3_rt_640 : STD_LOGIC;
signal Mcount_count_us_cy_4_rt_642 : STD_LOGIC;
signal Mcount_count_us_cy_5_rt_644 : STD_LOGIC;
signal Mcount_count_us_cy_6_rt_646 : STD_LOGIC;
signal Mcount_count_us_cy_7_rt_648 : STD_LOGIC;
signal Mcount_count_us_cy_8_rt_650 : STD_LOGIC;
signal Mcount_count_us_cy_9_rt_652 : STD_LOGIC;
signal Mcount_count_us_xor_31_rt_654 : STD_LOGIC;
signal Mrom_databus_mux0005 : STD_LOGIC;
signal Mrom_databus_mux000512 : STD_LOGIC;
signal N11 : STD_LOGIC;
signal N13 : STD_LOGIC;
signal N20 : STD_LOGIC;
signal N22 : STD_LOGIC;
signal N23 : STD_LOGIC;
signal N25 : STD_LOGIC;
signal N26 : STD_LOGIC;
signal N28 : STD_LOGIC;
signal N29 : STD_LOGIC;
signal N30 : STD_LOGIC;
signal N31 : STD_LOGIC;
signal N32 : STD_LOGIC;
signal N33 : STD_LOGIC;
signal N4 : STD_LOGIC;
signal N41 : STD_LOGIC;
signal N81 : STD_LOGIC;
signal N9 : STD_LOGIC;
signal RS_OBUF_675 : STD_LOGIC;
signal RS_mux0005 : STD_LOGIC;
signal Result_10_1 : STD_LOGIC;
signal Result_11_1 : STD_LOGIC;
signal Result_12_1 : STD_LOGIC;
signal Result_13_1 : STD_LOGIC;
signal Result_14_1 : STD_LOGIC;
signal Result_15_1 : STD_LOGIC;
signal Result_16_1 : STD_LOGIC;
signal Result_17_1 : STD_LOGIC;
signal Result_18_1 : STD_LOGIC;
signal Result_19_1 : STD_LOGIC;
signal Result_1_1 : STD_LOGIC;
signal Result_20_1 : STD_LOGIC;
signal Result_21_1 : STD_LOGIC;
signal Result_22_1 : STD_LOGIC;
signal Result_23_1 : STD_LOGIC;
signal Result_24_1 : STD_LOGIC;
signal Result_25_1 : STD_LOGIC;
signal Result_26_1 : STD_LOGIC;
signal Result_27_1 : STD_LOGIC;
signal Result_28_1 : STD_LOGIC;
signal Result_29_1 : STD_LOGIC;
signal Result_2_1 : STD_LOGIC;
signal Result_30_1 : STD_LOGIC;
signal Result_31_1 : STD_LOGIC;
signal Result_3_1 : STD_LOGIC;
signal Result_4_1 : STD_LOGIC;
signal Result_5_1 : STD_LOGIC;
signal Result_6_1 : STD_LOGIC;
signal Result_7_1 : STD_LOGIC;
signal Result_8_1 : STD_LOGIC;
signal Result_9_1 : STD_LOGIC;
signal SysCLK_IBUFG_741 : STD_LOGIC;
signal Unbuf_E_742 : STD_LOGIC;
signal Unbuf_E_mux0009 : STD_LOGIC;
signal Unbuf_E_mux0009115_744 : STD_LOGIC;
signal Unbuf_E_mux000919_745 : STD_LOGIC;
signal Unbuf_E_mux000936_759 : STD_LOGIC;
signal Unbuf_E_mux000968_760 : STD_LOGIC;
signal Unbuf_E_mux000971_761 : STD_LOGIC;
signal databus_0_802 : STD_LOGIC;
signal databus_1_803 : STD_LOGIC;
signal databus_2_804 : STD_LOGIC;
signal databus_3_805 : STD_LOGIC;
signal databus_4_806 : STD_LOGIC;
signal databus_5_807 : STD_LOGIC;
signal databus_6_808 : STD_LOGIC;
signal databus_7_809 : STD_LOGIC;
signal databus_cmp_ge0000 : STD_LOGIC;
signal databus_cmp_ge0001 : STD_LOGIC;
signal databus_cmp_ge0002 : STD_LOGIC;
signal databus_mux0006_0_84 : STD_LOGIC;
signal databus_mux0006_0_841_842 : STD_LOGIC;
signal databus_mux0006_1_27_844 : STD_LOGIC;
signal databus_mux0006_2_50_846 : STD_LOGIC;
signal databus_mux0006_3_39_848 : STD_LOGIC;
signal databus_not0001 : STD_LOGIC;
signal wait_time_cmp_ge0000 : STD_LOGIC;
signal wait_time_cmp_ge00001 : STD_LOGIC;
signal wait_time_cmp_ge0001 : STD_LOGIC;
signal wait_time_cmp_lt0000 : STD_LOGIC;
signal G1_CLK1MHz_cmp_eq00001_wg_cy : STD_LOGIC_VECTOR ( 6 downto 0 );
signal G1_CLK1MHz_cmp_eq00001_wg_lut : STD_LOGIC_VECTOR ( 6 downto 0 );
signal G1_Madd_cnt_add0000_cy : STD_LOGIC_VECTOR ( 30 downto 0 );
signal G1_Madd_cnt_add0000_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
signal G1_Mcount_cnt_cy : STD_LOGIC_VECTOR ( 30 downto 0 );
signal G1_Mcount_cnt_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
signal G1_cnt : STD_LOGIC_VECTOR ( 31 downto 0 );
signal G1_cnt_add0000 : STD_LOGIC_VECTOR ( 31 downto 1 );
signal Madd_databus_add0000_cy : STD_LOGIC_VECTOR ( 30 downto 4 );
signal Madd_index_addsub0000_cy : STD_LOGIC_VECTOR ( 30 downto 0 );
signal Madd_index_addsub0000_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
signal Madd_wait_time_share0000_cy : STD_LOGIC_VECTOR ( 30 downto 1 );
signal Mcompar_wait_time_cmp_eq0000_cy : STD_LOGIC_VECTOR ( 15 downto 0 );
signal Mcompar_wait_time_cmp_eq0000_lut : STD_LOGIC_VECTOR ( 15 downto 0 );
signal Mcompar_wait_time_cmp_ge0000_cy : STD_LOGIC_VECTOR ( 11 downto 0 );
signal Mcompar_wait_time_cmp_ge0000_lut : STD_LOGIC_VECTOR ( 12 downto 0 );
signal Mcompar_wait_time_cmp_ge0001_cy : STD_LOGIC_VECTOR ( 30 downto 0 );
signal Mcompar_wait_time_cmp_ge0001_lut : STD_LOGIC_VECTOR ( 31 downto 0 );
signal Mcompar_wait_time_cmp_lt0000_cy : STD_LOGIC_VECTOR ( 8 downto 0 );
signal Mcompar_wait_time_cmp_lt0000_lut : STD_LOGIC_VECTOR ( 8 downto 0 );
signal Mcount_count_us_cy : STD_LOGIC_VECTOR ( 30 downto 0 );
signal Mcount_count_us_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
signal Result : STD_LOGIC_VECTOR ( 31 downto 1 );
signal Unbuf_E_mux00092_wg_cy : STD_LOGIC_VECTOR ( 5 downto 0 );
signal Unbuf_E_mux00092_wg_lut : STD_LOGIC_VECTOR ( 6 downto 0 );
signal count_us : STD_LOGIC_VECTOR ( 31 downto 0 );
signal databus_add0000 : STD_LOGIC_VECTOR ( 31 downto 5 );
signal databus_mux0006 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal index : STD_LOGIC_VECTOR ( 31 downto 0 );
signal index_addsub0000 : STD_LOGIC_VECTOR ( 31 downto 1 );
signal index_mux0003 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal wait_time : STD_LOGIC_VECTOR ( 31 downto 1 );
signal wait_time_mux0003 : STD_LOGIC_VECTOR ( 31 downto 1 );
signal wait_time_share0000 : STD_LOGIC_VECTOR ( 31 downto 2 );
begin
XST_GND : GND
port map (
G => Mrom_databus_mux000512
);
XST_VCC : VCC
port map (
P => Mrom_databus_mux0005
);
RS_3 : LD
generic map(
INIT => '0'
)
port map (
D => RS_mux0005,
G => databus_not0001,
Q => RS_OBUF_675
);
Unbuf_E : LD
port map (
D => Unbuf_E_mux0009,
G => databus_not0001,
Q => Unbuf_E_742
);
databus_0 : LD
port map (
D => databus_mux0006(0),
G => databus_not0001,
Q => databus_0_802
);
databus_1 : LD
port map (
D => databus_mux0006(1),
G => databus_not0001,
Q => databus_1_803
);
databus_2 : LD
port map (
D => databus_mux0006(2),
G => databus_not0001,
Q => databus_2_804
);
databus_3 : LD
port map (
D => databus_mux0006(3),
G => databus_not0001,
Q => databus_3_805
);
databus_4 : LD
port map (
D => databus_mux0006(4),
G => databus_not0001,
Q => databus_4_806
);
databus_5 : LD
port map (
D => databus_mux0006(5),
G => databus_not0001,
Q => databus_5_807
);
databus_6 : LD
port map (
D => databus_mux0006(6),
G => databus_not0001,
Q => databus_6_808
);
databus_7 : LD
port map (
D => databus_mux0006(7),
G => databus_not0001,
Q => databus_7_809
);
G1_CLK1MHz : FDRE
port map (
C => Buf_SysCLK,
CE => G1_CLK1MHz_cmp_eq0000_5,
D => Mrom_databus_mux0005,
R => G1_cnt_cmp_eq0000_209,
Q => G1_CLK1MHz_4
);
count_us_0 : FD
generic map(
INIT => '0'
)
port map (
C => Buf_CLK1MHz,
D => Mcount_count_us_lut(0),
Q => count_us(0)
);
count_us_1 : FD
generic map(
INIT => '0'
)
port map (
C => Buf_CLK1MHz,
D => Result(1),
Q => count_us(1)
);
count_us_2 : FD
generic map(
INIT => '0'
)
port map (
C => Buf_CLK1MHz,
D => Result(2),
Q => count_us(2)
);
count_us_3 : FD
generic map(
INIT => '0'
)
port map (
C => Buf_CLK1MHz,
D => Result(3),
Q => count_us(3)
);
count_us_4 : FD
generic map(
INIT => '0'
)
port map (
C => Buf_CLK1MHz,
D => Result(4),
Q => count_us(4)
);
count_us_5 : FD
generic map(
INIT => '0'
)
port map (
C => Buf_CLK1MHz,
D => Result(5),
Q => count_us(5)
);
count_us_6 : FD
generic map(
INIT => '0'
)
port map (
C => Buf_CLK1MHz,
D => Result(6),
Q => count_us(6)
);
count_us_7 : FD
generic map(
INIT => '0'
)
port map (
C => Buf_CLK1MHz,
D => Result(7),
Q => count_us(7)
);
count_us_8 : FD
generic map(
INIT => '0'
)
port map (
C => Buf_CLK1MHz,
D => Result(8),
Q => count_us(8)
);
count_us_9 : FD
generic map(
INIT => '0'
)
port map (
C => Buf_CLK1MHz,
D => Result(9),
Q => count_us(9)
);
count_us_10 : FD
generic map(
INIT => '0'
)
port map (
C => Buf_CLK1MHz,
D => Result(10),
Q => count_us(10)
);
count_us_11 : FD
generic map(
INIT => '0'
)
port map (
C => Buf_CLK1MHz,
D => Result(11),
Q => count_us(11)
);
count_us_12 : FD
generic map(
INIT => '0'
)
port map (
C => Buf_CLK1MHz,
D => Result(12),
Q => count_us(12)
);
count_us_13 : FD
generic map(
INIT => '0'
)
port map (
C => Buf_CLK1MHz,
D => Result(13),
Q => count_us(13)
);
count_us_14 : FD
generic map(
INIT => '0'
)
port map (
C => Buf_CLK1MHz,
D => Result(14),
Q => count_us(14)
);
count_us_15 : FD
generic map(
INIT => '0'
)
port map (
C => Buf_CLK1MHz,
D => Result(15),
Q => count_us(15)
);
count_us_16 : FD
generic map(
INIT => '0'
)
port map (
C => Buf_CLK1MHz,
D => Result(16),
Q => count_us(16)
);
count_us_17 : FD
generic map(
INIT => '0'
)
port map (
C => Buf_CLK1MHz,
D => Result(17),
Q => count_us(17)
);
count_us_18 : FD
generic map(
INIT => '0'
)
port map (
C => Buf_CLK1MHz,
D => Result(18),
Q => count_us(18)
);
count_us_19 : FD
generic map(
INIT => '0'
)
port map (
C => Buf_CLK1MHz,
D => Result(19),
Q => count_us(19)
);
count_us_20 : FD
generic map(
INIT => '0'
)
port map (
C => Buf_CLK1MHz,
D => Result(20),
Q => count_us(20)
);
count_us_21 : FD
generic map(
INIT => '0'
)
port map (
C => Buf_CLK1MHz,
D => Result(21),
Q => count_us(21)
);
count_us_22 : FD
generic map(
INIT => '0'
)
port map (
C => Buf_CLK1MHz,
D => Result(22),
Q => count_us(22)
);
count_us_23 : FD
generic map(
INIT => '0'
)
port map (
C => Buf_CLK1MHz,
D => Result(23),
Q => count_us(23)
);
count_us_24 : FD
generic map(
INIT => '0'
)
port map (
C => Buf_CLK1MHz,
D => Result(24),
Q => count_us(24)
);
count_us_25 : FD
generic map(
INIT => '0'
)
port map (
C => Buf_CLK1MHz,
D => Result(25),
Q => count_us(25)
);
count_us_26 : FD
generic map(
INIT => '0'
)
port map (
C => Buf_CLK1MHz,
D => Result(26),
Q => count_us(26)
);
count_us_27 : FD
generic map(
INIT => '0'
)
port map (
C => Buf_CLK1MHz,
D => Result(27),
Q => count_us(27)
);
count_us_28 : FD
generic map(
INIT => '0'
)
port map (
C => Buf_CLK1MHz,
D => Result(28),
Q => count_us(28)
);
count_us_29 : FD
generic map(
INIT => '0'
)
port map (
C => Buf_CLK1MHz,
D => Result(29),
Q => count_us(29)
);
count_us_30 : FD
generic map(
INIT => '0'
)
port map (
C => Buf_CLK1MHz,
D => Result(30),
Q => count_us(30)
);
count_us_31 : FD
generic map(
INIT => '0'
)
port map (
C => Buf_CLK1MHz,
D => Result(31),
Q => count_us(31)
);
G1_cnt_0 : FDR
generic map(
INIT => '0'
)
port map (
C => Buf_SysCLK,
D => G1_Mcount_cnt_lut(0),
R => G1_cnt_cmp_eq0000_209,
Q => G1_cnt(0)
);
G1_cnt_1 : FDR
generic map(
INIT => '0'
)
port map (
C => Buf_SysCLK,
D => Result_1_1,
R => G1_cnt_cmp_eq0000_209,
Q => G1_cnt(1)
);
G1_cnt_2 : FDR
generic map(
INIT => '0'
)
port map (
C => Buf_SysCLK,
D => Result_2_1,
R => G1_cnt_cmp_eq0000_209,
Q => G1_cnt(2)
);
G1_cnt_3 : FDR
generic map(
INIT => '0'
)
port map (
C => Buf_SysCLK,
D => Result_3_1,
R => G1_cnt_cmp_eq0000_209,
Q => G1_cnt(3)
);
G1_cnt_4 : FDR
generic map(
INIT => '0'
)
port map (
C => Buf_SysCLK,
D => Result_4_1,
R => G1_cnt_cmp_eq0000_209,
Q => G1_cnt(4)
);
G1_cnt_5 : FDR
generic map(
INIT => '0'
)
port map (
C => Buf_SysCLK,
D => Result_5_1,
R => G1_cnt_cmp_eq0000_209,
Q => G1_cnt(5)
);
G1_cnt_6 : FDR
generic map(
INIT => '0'
)
port map (
C => Buf_SysCLK,
D => Result_6_1,
R => G1_cnt_cmp_eq0000_209,
Q => G1_cnt(6)
);
G1_cnt_7 : FDR
generic map(
INIT => '0'
)
port map (
C => Buf_SysCLK,
D => Result_7_1,
R => G1_cnt_cmp_eq0000_209,
Q => G1_cnt(7)
);
G1_cnt_8 : FDR
generic map(
INIT => '0'
)
port map (
C => Buf_SysCLK,
D => Result_8_1,
R => G1_cnt_cmp_eq0000_209,
Q => G1_cnt(8)
);
G1_cnt_9 : FDR
generic map(
INIT => '0'
)
port map (
C => Buf_SysCLK,
D => Result_9_1,
R => G1_cnt_cmp_eq0000_209,
Q => G1_cnt(9)
);
G1_cnt_10 : FDR
generic map(
INIT => '0'
)
port map (
C => Buf_SysCLK,
D => Result_10_1,
R => G1_cnt_cmp_eq0000_209,
Q => G1_cnt(10)
);
G1_cnt_11 : FDR
generic map(
INIT => '0'
)
port map (
C => Buf_SysCLK,
D => Result_11_1,
R => G1_cnt_cmp_eq0000_209,
Q => G1_cnt(11)
);
G1_cnt_12 : FDR
generic map(
INIT => '0'
)
port map (
C => Buf_SysCLK,
D => Result_12_1,
R => G1_cnt_cmp_eq0000_209,
Q => G1_cnt(12)
);
G1_cnt_13 : FDR
generic map(
INIT => '0'
)
port map (
C => Buf_SysCLK,
D => Result_13_1,
R => G1_cnt_cmp_eq0000_209,
Q => G1_cnt(13)
);
G1_cnt_14 : FDR
generic map(
INIT => '0'
)
port map (
C => Buf_SysCLK,
D => Result_14_1,
R => G1_cnt_cmp_eq0000_209,
Q => G1_cnt(14)
);
G1_cnt_15 : FDR
generic map(
INIT => '0'
)
port map (
C => Buf_SysCLK,
D => Result_15_1,
R => G1_cnt_cmp_eq0000_209,
Q => G1_cnt(15)
);
G1_cnt_16 : FDR
generic map(
INIT => '0'
)
port map (
C => Buf_SysCLK,
D => Result_16_1,
R => G1_cnt_cmp_eq0000_209,
Q => G1_cnt(16)
);
G1_cnt_17 : FDR
generic map(
INIT => '0'
)
port map (
C => Buf_SysCLK,
D => Result_17_1,
R => G1_cnt_cmp_eq0000_209,
Q => G1_cnt(17)
);
G1_cnt_18 : FDR
generic map(
INIT => '0'
)
port map (
C => Buf_SysCLK,
D => Result_18_1,
R => G1_cnt_cmp_eq0000_209,
Q => G1_cnt(18)
);
G1_cnt_19 : FDR
generic map(
INIT => '0'
)
port map (
C => Buf_SysCLK,
D => Result_19_1,
R => G1_cnt_cmp_eq0000_209,
Q => G1_cnt(19)
);
G1_cnt_20 : FDR
generic map(
INIT => '0'
)
port map (
C => Buf_SysCLK,
D => Result_20_1,
R => G1_cnt_cmp_eq0000_209,
Q => G1_cnt(20)
);
G1_cnt_21 : FDR
generic map(
INIT => '0'
)
port map (
C => Buf_SysCLK,
D => Result_21_1,
R => G1_cnt_cmp_eq0000_209,
Q => G1_cnt(21)
);
G1_cnt_22 : FDR
generic map(
INIT => '0'
)
port map (
C => Buf_SysCLK,
D => Result_22_1,
R => G1_cnt_cmp_eq0000_209,
Q => G1_cnt(22)
);
G1_cnt_23 : FDR
generic map(
INIT => '0'
)
port map (
C => Buf_SysCLK,
D => Result_23_1,
R => G1_cnt_cmp_eq0000_209,
Q => G1_cnt(23)
);
G1_cnt_24 : FDR
generic map(
INIT => '0'
)
port map (
C => Buf_SysCLK,
D => Result_24_1,
R => G1_cnt_cmp_eq0000_209,
Q => G1_cnt(24)
);
G1_cnt_25 : FDR
generic map(
INIT => '0'
)
port map (
C => Buf_SysCLK,
D => Result_25_1,
R => G1_cnt_cmp_eq0000_209,
Q => G1_cnt(25)
);
G1_cnt_26 : FDR
generic map(
INIT => '0'
)
port map (
C => Buf_SysCLK,
D => Result_26_1,
R => G1_cnt_cmp_eq0000_209,
Q => G1_cnt(26)
);
G1_cnt_27 : FDR
generic map(
INIT => '0'
)
port map (
C => Buf_SysCLK,
D => Result_27_1,
R => G1_cnt_cmp_eq0000_209,
Q => G1_cnt(27)
);
G1_cnt_28 : FDR
generic map(
INIT => '0'
)
port map (
C => Buf_SysCLK,
D => Result_28_1,
R => G1_cnt_cmp_eq0000_209,
Q => G1_cnt(28)
);
G1_cnt_29 : FDR
generic map(
INIT => '0'
)
port map (
C => Buf_SysCLK,
D => Result_29_1,
R => G1_cnt_cmp_eq0000_209,
Q => G1_cnt(29)
);
G1_cnt_30 : FDR
generic map(
INIT => '0'
)
port map (
C => Buf_SysCLK,
D => Result_30_1,
R => G1_cnt_cmp_eq0000_209,
Q => G1_cnt(30)
);
G1_cnt_31 : FDR
generic map(
INIT => '0'
)
port map (
C => Buf_SysCLK,
D => Result_31_1,
R => G1_cnt_cmp_eq0000_209,
Q => G1_cnt(31)
);
Madd_wait_time_share0000_cy_1_Q : MUXCY
port map (
CI => Mrom_databus_mux000512,
DI => Mrom_databus_mux0005,
S => Madd_wait_time_share0000_lut_1_Q,
O => Madd_wait_time_share0000_cy(1)
);
Madd_wait_time_share0000_cy_2_Q : MUXCY
port map (
CI => Madd_wait_time_share0000_cy(1),
DI => Mrom_databus_mux000512,
S => Madd_wait_time_share0000_cy_2_rt_370,
O => Madd_wait_time_share0000_cy(2)
);
Madd_wait_time_share0000_xor_2_Q : XORCY
port map (
CI => Madd_wait_time_share0000_cy(1),
LI => Madd_wait_time_share0000_cy_2_rt_370,
O => wait_time_share0000(2)
);
Madd_wait_time_share0000_cy_3_Q : MUXCY
port map (
CI => Madd_wait_time_share0000_cy(2),
DI => Mrom_databus_mux000512,
S => Madd_wait_time_share0000_cy_3_rt_374,
O => Madd_wait_time_share0000_cy(3)
);
Madd_wait_time_share0000_xor_3_Q : XORCY
port map (
CI => Madd_wait_time_share0000_cy(2),
LI => Madd_wait_time_share0000_cy_3_rt_374,
O => wait_time_share0000(3)
);
Madd_wait_time_share0000_cy_4_Q : MUXCY
port map (
CI => Madd_wait_time_share0000_cy(3),
DI => Mrom_databus_mux0005,
S => Madd_wait_time_share0000_lut_4_Q,
O => Madd_wait_time_share0000_cy(4)
);
Madd_wait_time_share0000_xor_4_Q : XORCY
port map (
CI => Madd_wait_time_share0000_cy(3),
LI => Madd_wait_time_share0000_lut_4_Q,
O => wait_time_share0000(4)
);
Madd_wait_time_share0000_cy_5_Q : MUXCY
port map (
CI => Madd_wait_time_share0000_cy(4),
DI => Mrom_databus_mux0005,
S => Madd_wait_time_share0000_lut_5_Q,
O => Madd_wait_time_share0000_cy(5)
);
Madd_wait_time_share0000_xor_5_Q : XORCY
port map (
CI => Madd_wait_time_share0000_cy(4),
LI => Madd_wait_time_share0000_lut_5_Q,
O => wait_time_share0000(5)
);
Madd_wait_time_share0000_cy_6_Q : MUXCY
port map (
CI => Madd_wait_time_share0000_cy(5),
DI => Mrom_databus_mux000512,
S => Madd_wait_time_share0000_cy_6_rt_378,
O => Madd_wait_time_share0000_cy(6)
);
Madd_wait_time_share0000_xor_6_Q : XORCY
port map (
CI => Madd_wait_time_share0000_cy(5),
LI => Madd_wait_time_share0000_cy_6_rt_378,
O => wait_time_share0000(6)
);
Madd_wait_time_share0000_cy_7_Q : MUXCY
port map (
CI => Madd_wait_time_share0000_cy(6),
DI => Mrom_databus_mux000512,
S => Madd_wait_time_share0000_cy_7_rt_380,
O => Madd_wait_time_share0000_cy(7)
);
Madd_wait_time_share0000_xor_7_Q : XORCY
port map (
CI => Madd_wait_time_share0000_cy(6),
LI => Madd_wait_time_share0000_cy_7_rt_380,
O => wait_time_share0000(7)
);
Madd_wait_time_share0000_cy_8_Q : MUXCY
port map (
CI => Madd_wait_time_share0000_cy(7),
DI => Mrom_databus_mux000512,
S => Madd_wait_time_share0000_cy_8_rt_382,
O => Madd_wait_time_share0000_cy(8)
);
Madd_wait_time_share0000_xor_8_Q : XORCY
port map (
CI => Madd_wait_time_share0000_cy(7),
LI => Madd_wait_time_share0000_cy_8_rt_382,
O => wait_time_share0000(8)
);
Madd_wait_time_share0000_cy_9_Q : MUXCY
port map (
CI => Madd_wait_time_share0000_cy(8),
DI => Mrom_databus_mux000512,
S => Madd_wait_time_share0000_cy_9_rt_384,
O => Madd_wait_time_share0000_cy(9)
);
Madd_wait_time_share0000_xor_9_Q : XORCY
port map (
CI => Madd_wait_time_share0000_cy(8),
LI => Madd_wait_time_share0000_cy_9_rt_384,
O => wait_time_share0000(9)
);
Madd_wait_time_share0000_cy_10_Q : MUXCY
port map (
CI => Madd_wait_time_share0000_cy(9),
DI => Mrom_databus_mux000512,
S => Madd_wait_time_share0000_cy_10_rt_329,
O => Madd_wait_time_share0000_cy(10)
);
Madd_wait_time_share0000_xor_10_Q : XORCY
port map (
CI => Madd_wait_time_share0000_cy(9),
LI => Madd_wait_time_share0000_cy_10_rt_329,
O => wait_time_share0000(10)
);
Madd_wait_time_share0000_cy_11_Q : MUXCY
port map (
CI => Madd_wait_time_share0000_cy(10),
DI => Mrom_databus_mux000512,
S => Madd_wait_time_share0000_cy_11_rt_331,
O => Madd_wait_time_share0000_cy(11)
);
Madd_wait_time_share0000_xor_11_Q : XORCY
port map (
CI => Madd_wait_time_share0000_cy(10),
LI => Madd_wait_time_share0000_cy_11_rt_331,
O => wait_time_share0000(11)
);
Madd_wait_time_share0000_cy_12_Q : MUXCY
port map (
CI => Madd_wait_time_share0000_cy(11),
DI => Mrom_databus_mux000512,
S => Madd_wait_time_share0000_cy_12_rt_333,
O => Madd_wait_time_share0000_cy(12)
);
Madd_wait_time_share0000_xor_12_Q : XORCY
port map (
CI => Madd_wait_time_share0000_cy(11),
LI => Madd_wait_time_share0000_cy_12_rt_333,
O => wait_time_share0000(12)
);
Madd_wait_time_share0000_cy_13_Q : MUXCY
port map (
CI => Madd_wait_time_share0000_cy(12),
DI => Mrom_databus_mux000512,
S => Madd_wait_time_share0000_cy_13_rt_335,
O => Madd_wait_time_share0000_cy(13)
);
Madd_wait_time_share0000_xor_13_Q : XORCY
port map (
CI => Madd_wait_time_share0000_cy(12),
LI => Madd_wait_time_share0000_cy_13_rt_335,
O => wait_time_share0000(13)
);
Madd_wait_time_share0000_cy_14_Q : MUXCY
port map (
CI => Madd_wait_time_share0000_cy(13),
DI => Mrom_databus_mux000512,
S => Madd_wait_time_share0000_cy_14_rt_337,
O => Madd_wait_time_share0000_cy(14)
);
Madd_wait_time_share0000_xor_14_Q : XORCY
port map (
CI => Madd_wait_time_share0000_cy(13),
LI => Madd_wait_time_share0000_cy_14_rt_337,
O => wait_time_share0000(14)
);
Madd_wait_time_share0000_cy_15_Q : MUXCY
port map (
CI => Madd_wait_time_share0000_cy(14),
DI => Mrom_databus_mux000512,
S => Madd_wait_time_share0000_cy_15_rt_339,
O => Madd_wait_time_share0000_cy(15)
);
Madd_wait_time_share0000_xor_15_Q : XORCY
port map (
CI => Madd_wait_time_share0000_cy(14),
LI => Madd_wait_time_share0000_cy_15_rt_339,
O => wait_time_share0000(15)
);
Madd_wait_time_share0000_cy_16_Q : MUXCY
port map (
CI => Madd_wait_time_share0000_cy(15),
DI => Mrom_databus_mux000512,
S => Madd_wait_time_share0000_cy_16_rt_341,
O => Madd_wait_time_share0000_cy(16)
);
Madd_wait_time_share0000_xor_16_Q : XORCY
port map (
CI => Madd_wait_time_share0000_cy(15),
LI => Madd_wait_time_share0000_cy_16_rt_341,
O => wait_time_share0000(16)
);
Madd_wait_time_share0000_cy_17_Q : MUXCY
port map (
CI => Madd_wait_time_share0000_cy(16),
DI => Mrom_databus_mux000512,
S => Madd_wait_time_share0000_cy_17_rt_343,
O => Madd_wait_time_share0000_cy(17)
);
Madd_wait_time_share0000_xor_17_Q : XORCY
port map (
CI => Madd_wait_time_share0000_cy(16),
LI => Madd_wait_time_share0000_cy_17_rt_343,
O => wait_time_share0000(17)
);
Madd_wait_time_share0000_cy_18_Q : MUXCY
port map (
CI => Madd_wait_time_share0000_cy(17),
DI => Mrom_databus_mux000512,
S => Madd_wait_time_share0000_cy_18_rt_345,
O => Madd_wait_time_share0000_cy(18)
);
Madd_wait_time_share0000_xor_18_Q : XORCY
port map (
CI => Madd_wait_time_share0000_cy(17),
LI => Madd_wait_time_share0000_cy_18_rt_345,
O => wait_time_share0000(18)
);
Madd_wait_time_share0000_cy_19_Q : MUXCY
port map (
CI => Madd_wait_time_share0000_cy(18),
DI => Mrom_databus_mux000512,
S => Madd_wait_time_share0000_cy_19_rt_347,
O => Madd_wait_time_share0000_cy(19)
);
Madd_wait_time_share0000_xor_19_Q : XORCY
port map (
CI => Madd_wait_time_share0000_cy(18),
LI => Madd_wait_time_share0000_cy_19_rt_347,
O => wait_time_share0000(19)
);
Madd_wait_time_share0000_cy_20_Q : MUXCY
port map (
CI => Madd_wait_time_share0000_cy(19),
DI => Mrom_databus_mux000512,
S => Madd_wait_time_share0000_cy_20_rt_350,
O => Madd_wait_time_share0000_cy(20)
);
Madd_wait_time_share0000_xor_20_Q : XORCY
port map (
CI => Madd_wait_time_share0000_cy(19),
LI => Madd_wait_time_share0000_cy_20_rt_350,
O => wait_time_share0000(20)
);
Madd_wait_time_share0000_cy_21_Q : MUXCY
port map (
CI => Madd_wait_time_share0000_cy(20),
DI => Mrom_databus_mux000512,
S => Madd_wait_time_share0000_cy_21_rt_352,
O => Madd_wait_time_share0000_cy(21)
);
Madd_wait_time_share0000_xor_21_Q : XORCY
port map (
CI => Madd_wait_time_share0000_cy(20),
LI => Madd_wait_time_share0000_cy_21_rt_352,
O => wait_time_share0000(21)
);
Madd_wait_time_share0000_cy_22_Q : MUXCY
port map (
CI => Madd_wait_time_share0000_cy(21),
DI => Mrom_databus_mux000512,
S => Madd_wait_time_share0000_cy_22_rt_354,
O => Madd_wait_time_share0000_cy(22)
);
Madd_wait_time_share0000_xor_22_Q : XORCY
port map (
CI => Madd_wait_time_share0000_cy(21),
LI => Madd_wait_time_share0000_cy_22_rt_354,
O => wait_time_share0000(22)
);
Madd_wait_time_share0000_cy_23_Q : MUXCY
port map (
CI => Madd_wait_time_share0000_cy(22),
DI => Mrom_databus_mux000512,
S => Madd_wait_time_share0000_cy_23_rt_356,
O => Madd_wait_time_share0000_cy(23)
);
Madd_wait_time_share0000_xor_23_Q : XORCY
port map (
CI => Madd_wait_time_share0000_cy(22),
LI => Madd_wait_time_share0000_cy_23_rt_356,
O => wait_time_share0000(23)
);
Madd_wait_time_share0000_cy_24_Q : MUXCY
port map (
CI => Madd_wait_time_share0000_cy(23),
DI => Mrom_databus_mux000512,
S => Madd_wait_time_share0000_cy_24_rt_358,
O => Madd_wait_time_share0000_cy(24)
);
Madd_wait_time_share0000_xor_24_Q : XORCY
port map (
CI => Madd_wait_time_share0000_cy(23),
LI => Madd_wait_time_share0000_cy_24_rt_358,
O => wait_time_share0000(24)
);
Madd_wait_time_share0000_cy_25_Q : MUXCY
port map (
CI => Madd_wait_time_share0000_cy(24),
DI => Mrom_databus_mux000512,
S => Madd_wait_time_share0000_cy_25_rt_360,
O => Madd_wait_time_share0000_cy(25)
);
Madd_wait_time_share0000_xor_25_Q : XORCY
port map (
CI => Madd_wait_time_share0000_cy(24),
LI => Madd_wait_time_share0000_cy_25_rt_360,
O => wait_time_share0000(25)
);
Madd_wait_time_share0000_cy_26_Q : MUXCY
port map (
CI => Madd_wait_time_share0000_cy(25),
DI => Mrom_databus_mux000512,
S => Madd_wait_time_share0000_cy_26_rt_362,
O => Madd_wait_time_share0000_cy(26)
);
Madd_wait_time_share0000_xor_26_Q : XORCY
port map (
CI => Madd_wait_time_share0000_cy(25),
LI => Madd_wait_time_share0000_cy_26_rt_362,
O => wait_time_share0000(26)
);
Madd_wait_time_share0000_cy_27_Q : MUXCY
port map (
CI => Madd_wait_time_share0000_cy(26),
DI => Mrom_databus_mux000512,
S => Madd_wait_time_share0000_cy_27_rt_364,
O => Madd_wait_time_share0000_cy(27)
);
Madd_wait_time_share0000_xor_27_Q : XORCY
port map (
CI => Madd_wait_time_share0000_cy(26),
LI => Madd_wait_time_share0000_cy_27_rt_364,
O => wait_time_share0000(27)
);
Madd_wait_time_share0000_cy_28_Q : MUXCY
port map (
CI => Madd_wait_time_share0000_cy(27),
DI => Mrom_databus_mux000512,
S => Madd_wait_time_share0000_cy_28_rt_366,
O => Madd_wait_time_share0000_cy(28)
);
Madd_wait_time_share0000_xor_28_Q : XORCY
port map (
CI => Madd_wait_time_share0000_cy(27),
LI => Madd_wait_time_share0000_cy_28_rt_366,
O => wait_time_share0000(28)
);
Madd_wait_time_share0000_cy_29_Q : MUXCY
port map (
CI => Madd_wait_time_share0000_cy(28),
DI => Mrom_databus_mux000512,
S => Madd_wait_time_share0000_cy_29_rt_368,
O => Madd_wait_time_share0000_cy(29)
);
Madd_wait_time_share0000_xor_29_Q : XORCY
port map (
CI => Madd_wait_time_share0000_cy(28),
LI => Madd_wait_time_share0000_cy_29_rt_368,
O => wait_time_share0000(29)
);
Madd_wait_time_share0000_cy_30_Q : MUXCY
port map (
CI => Madd_wait_time_share0000_cy(29),
DI => Mrom_databus_mux000512,
S => Madd_wait_time_share0000_cy_30_rt_372,
O => Madd_wait_time_share0000_cy(30)
);
Madd_wait_time_share0000_xor_30_Q : XORCY
port map (
CI => Madd_wait_time_share0000_cy(29),
LI => Madd_wait_time_share0000_cy_30_rt_372,
O => wait_time_share0000(30)
);
Madd_wait_time_share0000_xor_31_Q : XORCY
port map (
CI => Madd_wait_time_share0000_cy(30),
LI => Madd_wait_time_share0000_xor_31_rt_388,
O => wait_time_share0000(31)
);
Madd_databus_add0000_cy_4_Q : MUXCY
port map (
CI => Mrom_databus_mux000512,
DI => Mrom_databus_mux0005,
S => Madd_databus_add0000_lut_4_Q,
O => Madd_databus_add0000_cy(4)
);
Madd_databus_add0000_cy_5_Q : MUXCY
port map (
CI => Madd_databus_add0000_cy(4),
DI => Mrom_databus_mux0005,
S => Madd_databus_add0000_lut_5_Q,
O => Madd_databus_add0000_cy(5)
);
Madd_databus_add0000_xor_5_Q : XORCY
port map (
CI => Madd_databus_add0000_cy(4),
LI => Madd_databus_add0000_lut_5_Q,
O => databus_add0000(5)
);
Madd_databus_add0000_cy_6_Q : MUXCY
port map (
CI => Madd_databus_add0000_cy(5),
DI => Mrom_databus_mux0005,
S => Madd_databus_add0000_lut_6_Q,
O => Madd_databus_add0000_cy(6)
);
Madd_databus_add0000_xor_6_Q : XORCY
port map (
CI => Madd_databus_add0000_cy(5),
LI => Madd_databus_add0000_lut_6_Q,
O => databus_add0000(6)
);
Madd_databus_add0000_cy_7_Q : MUXCY
port map (
CI => Madd_databus_add0000_cy(6),
DI => Mrom_databus_mux0005,
S => Madd_databus_add0000_lut_7_Q,
O => Madd_databus_add0000_cy(7)
);
Madd_databus_add0000_xor_7_Q : XORCY
port map (
CI => Madd_databus_add0000_cy(6),
LI => Madd_databus_add0000_lut_7_Q,
O => databus_add0000(7)
);
Madd_databus_add0000_cy_8_Q : MUXCY
port map (
CI => Madd_databus_add0000_cy(7),
DI => Mrom_databus_mux0005,
S => Madd_databus_add0000_lut_8_Q,
O => Madd_databus_add0000_cy(8)
);
Madd_databus_add0000_xor_8_Q : XORCY
port map (
CI => Madd_databus_add0000_cy(7),
LI => Madd_databus_add0000_lut_8_Q,
O => databus_add0000(8)
);
Madd_databus_add0000_cy_9_Q : MUXCY
port map (
CI => Madd_databus_add0000_cy(8),
DI => Mrom_databus_mux000512,
S => Madd_databus_add0000_cy_9_rt_255,
O => Madd_databus_add0000_cy(9)
);
Madd_databus_add0000_xor_9_Q : XORCY
port map (
CI => Madd_databus_add0000_cy(8),
LI => Madd_databus_add0000_cy_9_rt_255,
O => databus_add0000(9)
);
Madd_databus_add0000_cy_10_Q : MUXCY
port map (
CI => Madd_databus_add0000_cy(9),
DI => Mrom_databus_mux0005,
S => Madd_databus_add0000_lut_10_Q,
O => Madd_databus_add0000_cy(10)
);
Madd_databus_add0000_xor_10_Q : XORCY
port map (
CI => Madd_databus_add0000_cy(9),
LI => Madd_databus_add0000_lut_10_Q,
O => databus_add0000(10)
);
Madd_databus_add0000_cy_11_Q : MUXCY
port map (
CI => Madd_databus_add0000_cy(10),
DI => Mrom_databus_mux000512,
S => Madd_databus_add0000_cy_11_rt_212,
O => Madd_databus_add0000_cy(11)
);
Madd_databus_add0000_xor_11_Q : XORCY
port map (
CI => Madd_databus_add0000_cy(10),
LI => Madd_databus_add0000_cy_11_rt_212,
O => databus_add0000(11)
);
Madd_databus_add0000_cy_12_Q : MUXCY
port map (
CI => Madd_databus_add0000_cy(11),
DI => Mrom_databus_mux0005,
S => Madd_databus_add0000_lut_12_Q,
O => Madd_databus_add0000_cy(12)
);
Madd_databus_add0000_xor_12_Q : XORCY
port map (
CI => Madd_databus_add0000_cy(11),
LI => Madd_databus_add0000_lut_12_Q,
O => databus_add0000(12)
);
Madd_databus_add0000_cy_13_Q : MUXCY
port map (
CI => Madd_databus_add0000_cy(12),
DI => Mrom_databus_mux000512,
S => Madd_databus_add0000_cy_13_rt_215,
O => Madd_databus_add0000_cy(13)
);
Madd_databus_add0000_xor_13_Q : XORCY
port map (
CI => Madd_databus_add0000_cy(12),
LI => Madd_databus_add0000_cy_13_rt_215,
O => databus_add0000(13)
);
Madd_databus_add0000_cy_14_Q : MUXCY
port map (
CI => Madd_databus_add0000_cy(13),
DI => Mrom_databus_mux0005,
S => Madd_databus_add0000_lut_14_Q,
O => Madd_databus_add0000_cy(14)
);
Madd_databus_add0000_xor_14_Q : XORCY
port map (
CI => Madd_databus_add0000_cy(13),
LI => Madd_databus_add0000_lut_14_Q,
O => databus_add0000(14)
);
Madd_databus_add0000_cy_15_Q : MUXCY
port map (
CI => Madd_databus_add0000_cy(14),
DI => Mrom_databus_mux000512,
S => Madd_databus_add0000_cy_15_rt_218,
O => Madd_databus_add0000_cy(15)
);
Madd_databus_add0000_xor_15_Q : XORCY
port map (
CI => Madd_databus_add0000_cy(14),
LI => Madd_databus_add0000_cy_15_rt_218,
O => databus_add0000(15)
);
Madd_databus_add0000_cy_16_Q : MUXCY
port map (
CI => Madd_databus_add0000_cy(15),
DI => Mrom_databus_mux000512,
S => Madd_databus_add0000_cy_16_rt_220,
O => Madd_databus_add0000_cy(16)
);
Madd_databus_add0000_xor_16_Q : XORCY
port map (
CI => Madd_databus_add0000_cy(15),
LI => Madd_databus_add0000_cy_16_rt_220,
O => databus_add0000(16)
);
Madd_databus_add0000_cy_17_Q : MUXCY
port map (
CI => Madd_databus_add0000_cy(16),
DI => Mrom_databus_mux000512,
S => Madd_databus_add0000_cy_17_rt_222,
O => Madd_databus_add0000_cy(17)
);
Madd_databus_add0000_xor_17_Q : XORCY
port map (
CI => Madd_databus_add0000_cy(16),
LI => Madd_databus_add0000_cy_17_rt_222,
O => databus_add0000(17)
);
Madd_databus_add0000_cy_18_Q : MUXCY
port map (
CI => Madd_databus_add0000_cy(17),
DI => Mrom_databus_mux000512,
S => Madd_databus_add0000_cy_18_rt_224,
O => Madd_databus_add0000_cy(18)
);
Madd_databus_add0000_xor_18_Q : XORCY
port map (
CI => Madd_databus_add0000_cy(17),
LI => Madd_databus_add0000_cy_18_rt_224,
O => databus_add0000(18)
);
Madd_databus_add0000_cy_19_Q : MUXCY
port map (
CI => Madd_databus_add0000_cy(18),
DI => Mrom_databus_mux000512,
S => Madd_databus_add0000_cy_19_rt_226,
O => Madd_databus_add0000_cy(19)
);
Madd_databus_add0000_xor_19_Q : XORCY
port map (
CI => Madd_databus_add0000_cy(18),
LI => Madd_databus_add0000_cy_19_rt_226,
O => databus_add0000(19)
);
Madd_databus_add0000_cy_20_Q : MUXCY
port map (
CI => Madd_databus_add0000_cy(19),
DI => Mrom_databus_mux000512,
S => Madd_databus_add0000_cy_20_rt_228,
O => Madd_databus_add0000_cy(20)
);
Madd_databus_add0000_xor_20_Q : XORCY
port map (
CI => Madd_databus_add0000_cy(19),
LI => Madd_databus_add0000_cy_20_rt_228,
O => databus_add0000(20)
);
Madd_databus_add0000_cy_21_Q : MUXCY
port map (
CI => Madd_databus_add0000_cy(20),
DI => Mrom_databus_mux000512,
S => Madd_databus_add0000_cy_21_rt_230,
O => Madd_databus_add0000_cy(21)
);
Madd_databus_add0000_xor_21_Q : XORCY
port map (
CI => Madd_databus_add0000_cy(20),
LI => Madd_databus_add0000_cy_21_rt_230,
O => databus_add0000(21)
);
Madd_databus_add0000_cy_22_Q : MUXCY
port map (
CI => Madd_databus_add0000_cy(21),
DI => Mrom_databus_mux000512,
S => Madd_databus_add0000_cy_22_rt_232,
O => Madd_databus_add0000_cy(22)
);
Madd_databus_add0000_xor_22_Q : XORCY
port map (
CI => Madd_databus_add0000_cy(21),
LI => Madd_databus_add0000_cy_22_rt_232,
O => databus_add0000(22)
);
Madd_databus_add0000_cy_23_Q : MUXCY
port map (
CI => Madd_databus_add0000_cy(22),
DI => Mrom_databus_mux000512,
S => Madd_databus_add0000_cy_23_rt_234,
O => Madd_databus_add0000_cy(23)
);
Madd_databus_add0000_xor_23_Q : XORCY
port map (
CI => Madd_databus_add0000_cy(22),
LI => Madd_databus_add0000_cy_23_rt_234,
O => databus_add0000(23)
);
Madd_databus_add0000_cy_24_Q : MUXCY
port map (
CI => Madd_databus_add0000_cy(23),
DI => Mrom_databus_mux000512,
S => Madd_databus_add0000_cy_24_rt_236,
O => Madd_databus_add0000_cy(24)
);
Madd_databus_add0000_xor_24_Q : XORCY
port map (
CI => Madd_databus_add0000_cy(23),
LI => Madd_databus_add0000_cy_24_rt_236,
O => databus_add0000(24)
);
Madd_databus_add0000_cy_25_Q : MUXCY
port map (
CI => Madd_databus_add0000_cy(24),
DI => Mrom_databus_mux000512,
S => Madd_databus_add0000_cy_25_rt_238,
O => Madd_databus_add0000_cy(25)
);
Madd_databus_add0000_xor_25_Q : XORCY
port map (
CI => Madd_databus_add0000_cy(24),
LI => Madd_databus_add0000_cy_25_rt_238,
O => databus_add0000(25)
);
Madd_databus_add0000_cy_26_Q : MUXCY
port map (
CI => Madd_databus_add0000_cy(25),
DI => Mrom_databus_mux000512,
S => Madd_databus_add0000_cy_26_rt_240,
O => Madd_databus_add0000_cy(26)
);
Madd_databus_add0000_xor_26_Q : XORCY
port map (
CI => Madd_databus_add0000_cy(25),
LI => Madd_databus_add0000_cy_26_rt_240,
O => databus_add0000(26)
);
Madd_databus_add0000_cy_27_Q : MUXCY
port map (
CI => Madd_databus_add0000_cy(26),
DI => Mrom_databus_mux000512,
S => Madd_databus_add0000_cy_27_rt_242,
O => Madd_databus_add0000_cy(27)
);
Madd_databus_add0000_xor_27_Q : XORCY
port map (
CI => Madd_databus_add0000_cy(26),
LI => Madd_databus_add0000_cy_27_rt_242,
O => databus_add0000(27)
);
Madd_databus_add0000_cy_28_Q : MUXCY
port map (
CI => Madd_databus_add0000_cy(27),
DI => Mrom_databus_mux000512,
S => Madd_databus_add0000_cy_28_rt_244,
O => Madd_databus_add0000_cy(28)
);
Madd_databus_add0000_xor_28_Q : XORCY
port map (
CI => Madd_databus_add0000_cy(27),
LI => Madd_databus_add0000_cy_28_rt_244,
O => databus_add0000(28)
);
Madd_databus_add0000_cy_29_Q : MUXCY
port map (
CI => Madd_databus_add0000_cy(28),
DI => Mrom_databus_mux000512,
S => Madd_databus_add0000_cy_29_rt_246,
O => Madd_databus_add0000_cy(29)
);
Madd_databus_add0000_xor_29_Q : XORCY
port map (
CI => Madd_databus_add0000_cy(28),
LI => Madd_databus_add0000_cy_29_rt_246,
O => databus_add0000(29)
);
Madd_databus_add0000_cy_30_Q : MUXCY
port map (
CI => Madd_databus_add0000_cy(29),
DI => Mrom_databus_mux000512,
S => Madd_databus_add0000_cy_30_rt_248,
O => Madd_databus_add0000_cy(30)
);
Madd_databus_add0000_xor_30_Q : XORCY
port map (
CI => Madd_databus_add0000_cy(29),
LI => Madd_databus_add0000_cy_30_rt_248,
O => databus_add0000(30)
);
Madd_databus_add0000_xor_31_Q : XORCY
port map (
CI => Madd_databus_add0000_cy(30),
LI => Madd_databus_add0000_xor_31_rt_264,
O => databus_add0000(31)
);
Madd_index_addsub0000_cy_0_Q : MUXCY
port map (
CI => Mrom_databus_mux000512,
DI => Mrom_databus_mux0005,
S => Madd_index_addsub0000_lut(0),
O => Madd_index_addsub0000_cy(0)
);
Madd_index_addsub0000_cy_1_Q : MUXCY
port map (
CI => Madd_index_addsub0000_cy(0),
DI => Mrom_databus_mux000512,
S => Madd_index_addsub0000_cy_1_rt_287,
O => Madd_index_addsub0000_cy(1)
);
Madd_index_addsub0000_xor_1_Q : XORCY
port map (
CI => Madd_index_addsub0000_cy(0),
LI => Madd_index_addsub0000_cy_1_rt_287,
O => index_addsub0000(1)
);
Madd_index_addsub0000_cy_2_Q : MUXCY
port map (
CI => Madd_index_addsub0000_cy(1),
DI => Mrom_databus_mux000512,
S => Madd_index_addsub0000_cy_2_rt_309,
O => Madd_index_addsub0000_cy(2)
);
Madd_index_addsub0000_xor_2_Q : XORCY
port map (
CI => Madd_index_addsub0000_cy(1),
LI => Madd_index_addsub0000_cy_2_rt_309,
O => index_addsub0000(2)
);
Madd_index_addsub0000_cy_3_Q : MUXCY
port map (
CI => Madd_index_addsub0000_cy(2),
DI => Mrom_databus_mux000512,
S => Madd_index_addsub0000_cy_3_rt_313,
O => Madd_index_addsub0000_cy(3)
);
Madd_index_addsub0000_xor_3_Q : XORCY
port map (
CI => Madd_index_addsub0000_cy(2),
LI => Madd_index_addsub0000_cy_3_rt_313,
O => index_addsub0000(3)
);
Madd_index_addsub0000_cy_4_Q : MUXCY
port map (
CI => Madd_index_addsub0000_cy(3),
DI => Mrom_databus_mux000512,
S => Madd_index_addsub0000_cy_4_rt_315,
O => Madd_index_addsub0000_cy(4)
);
Madd_index_addsub0000_xor_4_Q : XORCY
port map (
CI => Madd_index_addsub0000_cy(3),
LI => Madd_index_addsub0000_cy_4_rt_315,
O => index_addsub0000(4)
);
Madd_index_addsub0000_cy_5_Q : MUXCY
port map (
CI => Madd_index_addsub0000_cy(4),
DI => Mrom_databus_mux000512,
S => Madd_index_addsub0000_cy_5_rt_317,
O => Madd_index_addsub0000_cy(5)
);
Madd_index_addsub0000_xor_5_Q : XORCY
port map (
CI => Madd_index_addsub0000_cy(4),
LI => Madd_index_addsub0000_cy_5_rt_317,
O => index_addsub0000(5)
);
Madd_index_addsub0000_cy_6_Q : MUXCY
port map (
CI => Madd_index_addsub0000_cy(5),
DI => Mrom_databus_mux000512,
S => Madd_index_addsub0000_cy_6_rt_319,
O => Madd_index_addsub0000_cy(6)
);
Madd_index_addsub0000_xor_6_Q : XORCY
port map (
CI => Madd_index_addsub0000_cy(5),
LI => Madd_index_addsub0000_cy_6_rt_319,
O => index_addsub0000(6)
);
Madd_index_addsub0000_cy_7_Q : MUXCY
port map (
CI => Madd_index_addsub0000_cy(6),
DI => Mrom_databus_mux000512,
S => Madd_index_addsub0000_cy_7_rt_321,
O => Madd_index_addsub0000_cy(7)
);
Madd_index_addsub0000_xor_7_Q : XORCY
port map (
CI => Madd_index_addsub0000_cy(6),
LI => Madd_index_addsub0000_cy_7_rt_321,
O => index_addsub0000(7)
);
Madd_index_addsub0000_cy_8_Q : MUXCY
port map (
CI => Madd_index_addsub0000_cy(7),
DI => Mrom_databus_mux000512,
S => Madd_index_addsub0000_cy_8_rt_323,
O => Madd_index_addsub0000_cy(8)
);
Madd_index_addsub0000_xor_8_Q : XORCY
port map (
CI => Madd_index_addsub0000_cy(7),
LI => Madd_index_addsub0000_cy_8_rt_323,
O => index_addsub0000(8)
);
Madd_index_addsub0000_cy_9_Q : MUXCY
port map (
CI => Madd_index_addsub0000_cy(8),
DI => Mrom_databus_mux000512,
S => Madd_index_addsub0000_cy_9_rt_325,
O => Madd_index_addsub0000_cy(9)
);
Madd_index_addsub0000_xor_9_Q : XORCY
port map (
CI => Madd_index_addsub0000_cy(8),
LI => Madd_index_addsub0000_cy_9_rt_325,
O => index_addsub0000(9)
);
Madd_index_addsub0000_cy_10_Q : MUXCY
port map (
CI => Madd_index_addsub0000_cy(9),
DI => Mrom_databus_mux000512,
S => Madd_index_addsub0000_cy_10_rt_267,
O => Madd_index_addsub0000_cy(10)
);
Madd_index_addsub0000_xor_10_Q : XORCY
port map (
CI => Madd_index_addsub0000_cy(9),
LI => Madd_index_addsub0000_cy_10_rt_267,
O => index_addsub0000(10)
);
Madd_index_addsub0000_cy_11_Q : MUXCY
port map (
CI => Madd_index_addsub0000_cy(10),
DI => Mrom_databus_mux000512,
S => Madd_index_addsub0000_cy_11_rt_269,
O => Madd_index_addsub0000_cy(11)
);
Madd_index_addsub0000_xor_11_Q : XORCY
port map (
CI => Madd_index_addsub0000_cy(10),
LI => Madd_index_addsub0000_cy_11_rt_269,
O => index_addsub0000(11)
);
Madd_index_addsub0000_cy_12_Q : MUXCY
port map (
CI => Madd_index_addsub0000_cy(11),
DI => Mrom_databus_mux000512,
S => Madd_index_addsub0000_cy_12_rt_271,
O => Madd_index_addsub0000_cy(12)
);
Madd_index_addsub0000_xor_12_Q : XORCY
port map (
CI => Madd_index_addsub0000_cy(11),
LI => Madd_index_addsub0000_cy_12_rt_271,
O => index_addsub0000(12)
);
Madd_index_addsub0000_cy_13_Q : MUXCY
port map (
CI => Madd_index_addsub0000_cy(12),
DI => Mrom_databus_mux000512,
S => Madd_index_addsub0000_cy_13_rt_273,
O => Madd_index_addsub0000_cy(13)
);
Madd_index_addsub0000_xor_13_Q : XORCY
port map (
CI => Madd_index_addsub0000_cy(12),
LI => Madd_index_addsub0000_cy_13_rt_273,
O => index_addsub0000(13)
);
Madd_index_addsub0000_cy_14_Q : MUXCY
port map (
CI => Madd_index_addsub0000_cy(13),
DI => Mrom_databus_mux000512,
S => Madd_index_addsub0000_cy_14_rt_275,
O => Madd_index_addsub0000_cy(14)
);
Madd_index_addsub0000_xor_14_Q : XORCY
port map (
CI => Madd_index_addsub0000_cy(13),
LI => Madd_index_addsub0000_cy_14_rt_275,
O => index_addsub0000(14)
);
Madd_index_addsub0000_cy_15_Q : MUXCY
port map (
CI => Madd_index_addsub0000_cy(14),
DI => Mrom_databus_mux000512,
S => Madd_index_addsub0000_cy_15_rt_277,
O => Madd_index_addsub0000_cy(15)
);
Madd_index_addsub0000_xor_15_Q : XORCY
port map (
CI => Madd_index_addsub0000_cy(14),
LI => Madd_index_addsub0000_cy_15_rt_277,
O => index_addsub0000(15)
);
Madd_index_addsub0000_cy_16_Q : MUXCY
port map (
CI => Madd_index_addsub0000_cy(15),
DI => Mrom_databus_mux000512,
S => Madd_index_addsub0000_cy_16_rt_279,
O => Madd_index_addsub0000_cy(16)
);
Madd_index_addsub0000_xor_16_Q : XORCY
port map (
CI => Madd_index_addsub0000_cy(15),
LI => Madd_index_addsub0000_cy_16_rt_279,
O => index_addsub0000(16)
);
Madd_index_addsub0000_cy_17_Q : MUXCY
port map (
CI => Madd_index_addsub0000_cy(16),
DI => Mrom_databus_mux000512,
S => Madd_index_addsub0000_cy_17_rt_281,
O => Madd_index_addsub0000_cy(17)
);
Madd_index_addsub0000_xor_17_Q : XORCY
port map (
CI => Madd_index_addsub0000_cy(16),
LI => Madd_index_addsub0000_cy_17_rt_281,
O => index_addsub0000(17)
);
Madd_index_addsub0000_cy_18_Q : MUXCY
port map (
CI => Madd_index_addsub0000_cy(17),
DI => Mrom_databus_mux000512,
S => Madd_index_addsub0000_cy_18_rt_283,
O => Madd_index_addsub0000_cy(18)
);
Madd_index_addsub0000_xor_18_Q : XORCY
port map (
CI => Madd_index_addsub0000_cy(17),
LI => Madd_index_addsub0000_cy_18_rt_283,
O => index_addsub0000(18)
);
Madd_index_addsub0000_cy_19_Q : MUXCY
port map (
CI => Madd_index_addsub0000_cy(18),
DI => Mrom_databus_mux000512,
S => Madd_index_addsub0000_cy_19_rt_285,
O => Madd_index_addsub0000_cy(19)
);
Madd_index_addsub0000_xor_19_Q : XORCY
port map (
CI => Madd_index_addsub0000_cy(18),
LI => Madd_index_addsub0000_cy_19_rt_285,
O => index_addsub0000(19)
);
Madd_index_addsub0000_cy_20_Q : MUXCY
port map (
CI => Madd_index_addsub0000_cy(19),
DI => Mrom_databus_mux000512,
S => Madd_index_addsub0000_cy_20_rt_289,
O => Madd_index_addsub0000_cy(20)
);
Madd_index_addsub0000_xor_20_Q : XORCY
port map (
CI => Madd_index_addsub0000_cy(19),
LI => Madd_index_addsub0000_cy_20_rt_289,
O => index_addsub0000(20)
);
Madd_index_addsub0000_cy_21_Q : MUXCY
port map (
CI => Madd_index_addsub0000_cy(20),
DI => Mrom_databus_mux000512,
S => Madd_index_addsub0000_cy_21_rt_291,
O => Madd_index_addsub0000_cy(21)
);
Madd_index_addsub0000_xor_21_Q : XORCY
port map (
CI => Madd_index_addsub0000_cy(20),
LI => Madd_index_addsub0000_cy_21_rt_291,
O => index_addsub0000(21)
);
Madd_index_addsub0000_cy_22_Q : MUXCY
port map (
CI => Madd_index_addsub0000_cy(21),
DI => Mrom_databus_mux000512,
S => Madd_index_addsub0000_cy_22_rt_293,
O => Madd_index_addsub0000_cy(22)
);
Madd_index_addsub0000_xor_22_Q : XORCY
port map (
CI => Madd_index_addsub0000_cy(21),
LI => Madd_index_addsub0000_cy_22_rt_293,
O => index_addsub0000(22)
);
Madd_index_addsub0000_cy_23_Q : MUXCY
port map (
CI => Madd_index_addsub0000_cy(22),
DI => Mrom_databus_mux000512,
S => Madd_index_addsub0000_cy_23_rt_295,
O => Madd_index_addsub0000_cy(23)
);
Madd_index_addsub0000_xor_23_Q : XORCY
port map (
CI => Madd_index_addsub0000_cy(22),
LI => Madd_index_addsub0000_cy_23_rt_295,
O => index_addsub0000(23)
);
Madd_index_addsub0000_cy_24_Q : MUXCY
port map (
CI => Madd_index_addsub0000_cy(23),
DI => Mrom_databus_mux000512,
S => Madd_index_addsub0000_cy_24_rt_297,
O => Madd_index_addsub0000_cy(24)
);
Madd_index_addsub0000_xor_24_Q : XORCY
port map (
CI => Madd_index_addsub0000_cy(23),
LI => Madd_index_addsub0000_cy_24_rt_297,
O => index_addsub0000(24)
);
Madd_index_addsub0000_cy_25_Q : MUXCY
port map (
CI => Madd_index_addsub0000_cy(24),
DI => Mrom_databus_mux000512,
S => Madd_index_addsub0000_cy_25_rt_299,
O => Madd_index_addsub0000_cy(25)
);
Madd_index_addsub0000_xor_25_Q : XORCY
port map (
CI => Madd_index_addsub0000_cy(24),
LI => Madd_index_addsub0000_cy_25_rt_299,
O => index_addsub0000(25)
);
Madd_index_addsub0000_cy_26_Q : MUXCY
port map (
CI => Madd_index_addsub0000_cy(25),
DI => Mrom_databus_mux000512,
S => Madd_index_addsub0000_cy_26_rt_301,
O => Madd_index_addsub0000_cy(26)
);
Madd_index_addsub0000_xor_26_Q : XORCY
port map (
CI => Madd_index_addsub0000_cy(25),
LI => Madd_index_addsub0000_cy_26_rt_301,
O => index_addsub0000(26)
);
Madd_index_addsub0000_cy_27_Q : MUXCY
port map (
CI => Madd_index_addsub0000_cy(26),
DI => Mrom_databus_mux000512,
S => Madd_index_addsub0000_cy_27_rt_303,
O => Madd_index_addsub0000_cy(27)
);
Madd_index_addsub0000_xor_27_Q : XORCY
port map (
CI => Madd_index_addsub0000_cy(26),
LI => Madd_index_addsub0000_cy_27_rt_303,
O => index_addsub0000(27)
);
Madd_index_addsub0000_cy_28_Q : MUXCY
port map (
CI => Madd_index_addsub0000_cy(27),
DI => Mrom_databus_mux000512,
S => Madd_index_addsub0000_cy_28_rt_305,
O => Madd_index_addsub0000_cy(28)
);
Madd_index_addsub0000_xor_28_Q : XORCY
port map (
CI => Madd_index_addsub0000_cy(27),
LI => Madd_index_addsub0000_cy_28_rt_305,
O => index_addsub0000(28)
);
Madd_index_addsub0000_cy_29_Q : MUXCY
port map (
CI => Madd_index_addsub0000_cy(28),
DI => Mrom_databus_mux000512,
S => Madd_index_addsub0000_cy_29_rt_307,
O => Madd_index_addsub0000_cy(29)
);
Madd_index_addsub0000_xor_29_Q : XORCY
port map (
CI => Madd_index_addsub0000_cy(28),
LI => Madd_index_addsub0000_cy_29_rt_307,
O => index_addsub0000(29)
);
Madd_index_addsub0000_cy_30_Q : MUXCY
port map (
CI => Madd_index_addsub0000_cy(29),
DI => Mrom_databus_mux000512,
S => Madd_index_addsub0000_cy_30_rt_311,
O => Madd_index_addsub0000_cy(30)
);
Madd_index_addsub0000_xor_30_Q : XORCY
port map (
CI => Madd_index_addsub0000_cy(29),
LI => Madd_index_addsub0000_cy_30_rt_311,
O => index_addsub0000(30)
);
Madd_index_addsub0000_xor_31_Q : XORCY
port map (
CI => Madd_index_addsub0000_cy(30),
LI => Madd_index_addsub0000_xor_31_rt_327,
O => index_addsub0000(31)
);
Mcompar_wait_time_cmp_ge0000_lut_0_Q : LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => count_us(4),
I1 => count_us(5),
I2 => count_us(6),
I3 => count_us(7),
O => Mcompar_wait_time_cmp_ge0000_lut(0)
);
Mcompar_wait_time_cmp_ge0000_cy_0_Q : MUXCY
port map (
CI => Mrom_databus_mux0005,
DI => Mrom_databus_mux000512,
S => Mcompar_wait_time_cmp_ge0000_lut(0),
O => Mcompar_wait_time_cmp_ge0000_cy(0)
);
Mcompar_wait_time_cmp_ge0000_cy_1_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy(0),
DI => Mrom_databus_mux000512,
S => Mcompar_wait_time_cmp_ge0000_cy_1_rt_436,
O => Mcompar_wait_time_cmp_ge0000_cy(1)
);
Mcompar_wait_time_cmp_ge0000_cy_2_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy(1),
DI => Mrom_databus_mux0005,
S => Mcompar_wait_time_cmp_ge0000_lut(2),
O => Mcompar_wait_time_cmp_ge0000_cy(2)
);
Mcompar_wait_time_cmp_ge0000_cy_3_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy(2),
DI => Mrom_databus_mux000512,
S => Mcompar_wait_time_cmp_ge0000_cy_3_rt_446,
O => Mcompar_wait_time_cmp_ge0000_cy(3)
);
Mcompar_wait_time_cmp_ge0000_cy_4_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy(3),
DI => Mrom_databus_mux0005,
S => Mcompar_wait_time_cmp_ge0000_lut(4),
O => Mcompar_wait_time_cmp_ge0000_cy(4)
);
Mcompar_wait_time_cmp_ge0000_cy_5_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy(4),
DI => Mrom_databus_mux000512,
S => Mcompar_wait_time_cmp_ge0000_cy_5_rt_456,
O => Mcompar_wait_time_cmp_ge0000_cy(5)
);
Mcompar_wait_time_cmp_ge0000_cy_6_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy(5),
DI => Mrom_databus_mux0005,
S => Mcompar_wait_time_cmp_ge0000_lut(6),
O => Mcompar_wait_time_cmp_ge0000_cy(6)
);
Mcompar_wait_time_cmp_ge0000_cy_7_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy(6),
DI => Mrom_databus_mux000512,
S => Mcompar_wait_time_cmp_ge0000_cy_7_rt_467,
O => Mcompar_wait_time_cmp_ge0000_cy(7)
);
Mcompar_wait_time_cmp_ge0000_lut_8_Q : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => count_us(15),
I1 => count_us(16),
I2 => count_us(17),
I3 => count_us(18),
O => Mcompar_wait_time_cmp_ge0000_lut(8)
);
Mcompar_wait_time_cmp_ge0000_cy_8_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy(7),
DI => Mrom_databus_mux0005,
S => Mcompar_wait_time_cmp_ge0000_lut(8),
O => Mcompar_wait_time_cmp_ge0000_cy(8)
);
Mcompar_wait_time_cmp_ge0000_lut_9_Q : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => count_us(19),
I1 => count_us(20),
I2 => count_us(21),
I3 => count_us(22),
O => Mcompar_wait_time_cmp_ge0000_lut(9)
);
Mcompar_wait_time_cmp_ge0000_cy_9_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy(8),
DI => Mrom_databus_mux0005,
S => Mcompar_wait_time_cmp_ge0000_lut(9),
O => Mcompar_wait_time_cmp_ge0000_cy(9)
);
Mcompar_wait_time_cmp_ge0000_lut_10_Q : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => count_us(23),
I1 => count_us(24),
I2 => count_us(25),
I3 => count_us(26),
O => Mcompar_wait_time_cmp_ge0000_lut(10)
);
Mcompar_wait_time_cmp_ge0000_cy_10_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy(9),
DI => Mrom_databus_mux0005,
S => Mcompar_wait_time_cmp_ge0000_lut(10),
O => Mcompar_wait_time_cmp_ge0000_cy(10)
);
Mcompar_wait_time_cmp_ge0000_lut_11_Q : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => count_us(27),
I1 => count_us(28),
I2 => count_us(29),
I3 => count_us(30),
O => Mcompar_wait_time_cmp_ge0000_lut(11)
);
Mcompar_wait_time_cmp_ge0000_cy_11_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy(10),
DI => Mrom_databus_mux0005,
S => Mcompar_wait_time_cmp_ge0000_lut(11),
O => Mcompar_wait_time_cmp_ge0000_cy(11)
);
Mcompar_wait_time_cmp_ge0000_cy_12_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy(11),
DI => Mrom_databus_mux000512,
S => Mcompar_wait_time_cmp_ge0000_lut(12),
O => wait_time_cmp_ge00001
);
Mcompar_wait_time_cmp_ge0000_cy_0_0 : MUXCY
port map (
CI => Mrom_databus_mux0005,
DI => Mrom_databus_mux000512,
S => Mcompar_wait_time_cmp_ge0000_cy_0_0_rt_425,
O => Mcompar_wait_time_cmp_ge0000_cy_0_1_422
);
Mcompar_wait_time_cmp_ge0000_cy_1_0 : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy_0_1_422,
DI => Mrom_databus_mux0005,
S => Mcompar_wait_time_cmp_ge0000_lut(1),
O => Mcompar_wait_time_cmp_ge0000_cy_1_1_433
);
Mcompar_wait_time_cmp_ge0000_lut_2_1 : LUT3
generic map(
INIT => X"80"
)
port map (
I0 => count_us(5),
I1 => count_us(6),
I2 => count_us(7),
O => Mcompar_wait_time_cmp_ge0000_lut_2_1_487
);
Mcompar_wait_time_cmp_ge0000_cy_2_0 : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy_1_1_433,
DI => Mrom_databus_mux000512,
S => Mcompar_wait_time_cmp_ge0000_lut_2_1_487,
O => Mcompar_wait_time_cmp_ge0000_cy_2_1_438
);
Mcompar_wait_time_cmp_ge0000_cy_3_0 : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy_2_1_438,
DI => Mrom_databus_mux0005,
S => Mcompar_wait_time_cmp_ge0000_lut(3),
O => Mcompar_wait_time_cmp_ge0000_cy_3_1_443
);
Mcompar_wait_time_cmp_ge0000_lut_4_1 : LUT3
generic map(
INIT => X"80"
)
port map (
I0 => count_us(9),
I1 => count_us(10),
I2 => count_us(11),
O => Mcompar_wait_time_cmp_ge0000_lut_4_1_493
);
Mcompar_wait_time_cmp_ge0000_cy_4_0 : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy_3_1_443,
DI => Mrom_databus_mux000512,
S => Mcompar_wait_time_cmp_ge0000_lut_4_1_493,
O => Mcompar_wait_time_cmp_ge0000_cy_4_1_448
);
Mcompar_wait_time_cmp_ge0000_lut_5_Q : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => count_us(12),
I1 => count_us(13),
O => Mcompar_wait_time_cmp_ge0000_lut(5)
);
Mcompar_wait_time_cmp_ge0000_cy_5_0 : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy_4_1_448,
DI => Mrom_databus_mux0005,
S => Mcompar_wait_time_cmp_ge0000_lut(5),
O => Mcompar_wait_time_cmp_ge0000_cy_5_1_453
);
Mcompar_wait_time_cmp_ge0000_cy_6_0 : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy_5_1_453,
DI => Mrom_databus_mux000512,
S => Mcompar_wait_time_cmp_ge0000_cy_6_0_rt_461,
O => Mcompar_wait_time_cmp_ge0000_cy_6_1_458
);
Mcompar_wait_time_cmp_ge0000_lut_7_Q : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => count_us(15),
I1 => count_us(16),
I2 => count_us(17),
I3 => count_us(18),
O => Mcompar_wait_time_cmp_ge0000_lut(7)
);
Mcompar_wait_time_cmp_ge0000_cy_7_0 : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy_6_1_458,
DI => Mrom_databus_mux0005,
S => Mcompar_wait_time_cmp_ge0000_lut(7),
O => Mcompar_wait_time_cmp_ge0000_cy_7_1_464
);
Mcompar_wait_time_cmp_ge0000_lut_8_1 : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => count_us(19),
I1 => count_us(20),
I2 => count_us(21),
I3 => count_us(22),
O => Mcompar_wait_time_cmp_ge0000_lut_8_1_504
);
Mcompar_wait_time_cmp_ge0000_cy_8_0 : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy_7_1_464,
DI => Mrom_databus_mux0005,
S => Mcompar_wait_time_cmp_ge0000_lut_8_1_504,
O => Mcompar_wait_time_cmp_ge0000_cy_8_1_469
);
Mcompar_wait_time_cmp_ge0000_lut_9_1 : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => count_us(23),
I1 => count_us(24),
I2 => count_us(25),
I3 => count_us(26),
O => Mcompar_wait_time_cmp_ge0000_lut_9_1_508
);
Mcompar_wait_time_cmp_ge0000_cy_9_0 : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy_8_1_469,
DI => Mrom_databus_mux0005,
S => Mcompar_wait_time_cmp_ge0000_lut_9_1_508,
O => Mcompar_wait_time_cmp_ge0000_cy_9_1_473
);
Mcompar_wait_time_cmp_ge0000_lut_10_1 : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => count_us(27),
I1 => count_us(28),
I2 => count_us(29),
I3 => count_us(30),
O => Mcompar_wait_time_cmp_ge0000_lut_10_1_477
);
Mcompar_wait_time_cmp_ge0000_cy_10_0 : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy_9_1_473,
DI => Mrom_databus_mux0005,
S => Mcompar_wait_time_cmp_ge0000_lut_10_1_477,
O => Mcompar_wait_time_cmp_ge0000_cy_10_1_429
);
Mcompar_wait_time_cmp_ge0000_cy_11_0 : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy_10_1_429,
DI => Mrom_databus_mux000512,
S => Mcompar_wait_time_cmp_ge0000_lut_11_1,
O => databus_cmp_ge0000
);
Mcompar_wait_time_cmp_ge0000_cy_0_1 : MUXCY
port map (
CI => Mrom_databus_mux0005,
DI => Mrom_databus_mux000512,
S => Mcompar_wait_time_cmp_ge0000_cy_0_1_rt_426,
O => Mcompar_wait_time_cmp_ge0000_cy_0_2_423
);
Mcompar_wait_time_cmp_ge0000_lut_1_1 : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => count_us(3),
I1 => count_us(4),
I2 => count_us(5),
I3 => count_us(6),
O => Mcompar_wait_time_cmp_ge0000_lut_1_1_484
);
Mcompar_wait_time_cmp_ge0000_cy_1_1 : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy_0_2_423,
DI => Mrom_databus_mux0005,
S => Mcompar_wait_time_cmp_ge0000_lut_1_1_484,
O => Mcompar_wait_time_cmp_ge0000_cy_1_2_434
);
Mcompar_wait_time_cmp_ge0000_cy_2_1 : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy_1_2_434,
DI => Mrom_databus_mux000512,
S => Mcompar_wait_time_cmp_ge0000_cy_2_1_rt_441,
O => Mcompar_wait_time_cmp_ge0000_cy_2_2_439
);
Mcompar_wait_time_cmp_ge0000_cy_3_1 : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy_2_2_439,
DI => Mrom_databus_mux0005,
S => Mcompar_wait_time_cmp_ge0000_lut_3_1,
O => Mcompar_wait_time_cmp_ge0000_cy_3_2_444
);
Mcompar_wait_time_cmp_ge0000_lut_4_2 : LUT3
generic map(
INIT => X"80"
)
port map (
I0 => count_us(9),
I1 => count_us(10),
I2 => count_us(11),
O => Mcompar_wait_time_cmp_ge0000_lut_4_2_494
);
Mcompar_wait_time_cmp_ge0000_cy_4_1 : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy_3_2_444,
DI => Mrom_databus_mux000512,
S => Mcompar_wait_time_cmp_ge0000_lut_4_2_494,
O => Mcompar_wait_time_cmp_ge0000_cy_4_2_449
);
Mcompar_wait_time_cmp_ge0000_lut_5_1 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => count_us(12),
I1 => count_us(13),
O => Mcompar_wait_time_cmp_ge0000_lut_5_1_496
);
Mcompar_wait_time_cmp_ge0000_cy_5_1 : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy_4_2_449,
DI => Mrom_databus_mux0005,
S => Mcompar_wait_time_cmp_ge0000_lut_5_1_496,
O => Mcompar_wait_time_cmp_ge0000_cy_5_2_454
);
Mcompar_wait_time_cmp_ge0000_cy_6_1 : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy_5_2_454,
DI => Mrom_databus_mux000512,
S => Mcompar_wait_time_cmp_ge0000_cy_6_1_rt_462,
O => Mcompar_wait_time_cmp_ge0000_cy_6_2_459
);
Mcompar_wait_time_cmp_ge0000_lut_7_1 : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => count_us(15),
I1 => count_us(16),
I2 => count_us(17),
I3 => count_us(18),
O => Mcompar_wait_time_cmp_ge0000_lut_7_1_501
);
Mcompar_wait_time_cmp_ge0000_cy_7_1 : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy_6_2_459,
DI => Mrom_databus_mux0005,
S => Mcompar_wait_time_cmp_ge0000_lut_7_1_501,
O => Mcompar_wait_time_cmp_ge0000_cy_7_2_465
);
Mcompar_wait_time_cmp_ge0000_lut_8_2 : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => count_us(19),
I1 => count_us(20),
I2 => count_us(21),
I3 => count_us(22),
O => Mcompar_wait_time_cmp_ge0000_lut_8_2_505
);
Mcompar_wait_time_cmp_ge0000_cy_8_1 : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy_7_2_465,
DI => Mrom_databus_mux0005,
S => Mcompar_wait_time_cmp_ge0000_lut_8_2_505,
O => Mcompar_wait_time_cmp_ge0000_cy_8_2_470
);
Mcompar_wait_time_cmp_ge0000_lut_9_2 : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => count_us(23),
I1 => count_us(24),
I2 => count_us(25),
I3 => count_us(26),
O => Mcompar_wait_time_cmp_ge0000_lut_9_2_509
);
Mcompar_wait_time_cmp_ge0000_cy_9_1 : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy_8_2_470,
DI => Mrom_databus_mux0005,
S => Mcompar_wait_time_cmp_ge0000_lut_9_2_509,
O => Mcompar_wait_time_cmp_ge0000_cy_9_2_474
);
Mcompar_wait_time_cmp_ge0000_lut_10_2 : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => count_us(27),
I1 => count_us(28),
I2 => count_us(29),
I3 => count_us(30),
O => Mcompar_wait_time_cmp_ge0000_lut_10_2_478
);
Mcompar_wait_time_cmp_ge0000_cy_10_1 : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy_9_2_474,
DI => Mrom_databus_mux0005,
S => Mcompar_wait_time_cmp_ge0000_lut_10_2_478,
O => Mcompar_wait_time_cmp_ge0000_cy_10_2
);
Mcompar_wait_time_cmp_ge0000_cy_11_1 : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy_10_2,
DI => Mrom_databus_mux000512,
S => Mcompar_wait_time_cmp_ge0000_lut_11_2,
O => databus_cmp_ge0001
);
Mcompar_wait_time_cmp_ge0000_cy_0_2 : MUXCY
port map (
CI => Mrom_databus_mux0005,
DI => Mrom_databus_mux000512,
S => Mcompar_wait_time_cmp_ge0000_cy_0_2_rt_427,
O => Mcompar_wait_time_cmp_ge0000_cy_0_3
);
Mcompar_wait_time_cmp_ge0000_lut_1_2 : LUT3
generic map(
INIT => X"01"
)
port map (
I0 => count_us(6),
I1 => count_us(7),
I2 => count_us(8),
O => Mcompar_wait_time_cmp_ge0000_lut_1_2_485
);
Mcompar_wait_time_cmp_ge0000_cy_1_2 : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy_0_3,
DI => Mrom_databus_mux0005,
S => Mcompar_wait_time_cmp_ge0000_lut_1_2_485,
O => Mcompar_wait_time_cmp_ge0000_cy_1_3
);
Mcompar_wait_time_cmp_ge0000_lut_2_2 : LUT3
generic map(
INIT => X"80"
)
port map (
I0 => count_us(9),
I1 => count_us(10),
I2 => count_us(11),
O => Mcompar_wait_time_cmp_ge0000_lut_2_2_488
);
Mcompar_wait_time_cmp_ge0000_cy_2_2 : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy_1_3,
DI => Mrom_databus_mux000512,
S => Mcompar_wait_time_cmp_ge0000_lut_2_2_488,
O => Mcompar_wait_time_cmp_ge0000_cy_2_3
);
Mcompar_wait_time_cmp_ge0000_lut_3_2 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => count_us(12),
I1 => count_us(13),
O => Mcompar_wait_time_cmp_ge0000_lut_3_2_491
);
Mcompar_wait_time_cmp_ge0000_cy_3_2 : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy_2_3,
DI => Mrom_databus_mux0005,
S => Mcompar_wait_time_cmp_ge0000_lut_3_2_491,
O => Mcompar_wait_time_cmp_ge0000_cy_3_3
);
Mcompar_wait_time_cmp_ge0000_cy_4_2 : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy_3_3,
DI => Mrom_databus_mux000512,
S => Mcompar_wait_time_cmp_ge0000_cy_4_2_rt_451,
O => Mcompar_wait_time_cmp_ge0000_cy_4_3
);
Mcompar_wait_time_cmp_ge0000_lut_5_2 : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => count_us(15),
I1 => count_us(16),
I2 => count_us(17),
I3 => count_us(18),
O => Mcompar_wait_time_cmp_ge0000_lut_5_2_497
);
Mcompar_wait_time_cmp_ge0000_cy_5_2 : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy_4_3,
DI => Mrom_databus_mux0005,
S => Mcompar_wait_time_cmp_ge0000_lut_5_2_497,
O => Mcompar_wait_time_cmp_ge0000_cy_5_3
);
Mcompar_wait_time_cmp_ge0000_lut_6_1 : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => count_us(19),
I1 => count_us(20),
I2 => count_us(21),
I3 => count_us(22),
O => Mcompar_wait_time_cmp_ge0000_lut_6_1_499
);
Mcompar_wait_time_cmp_ge0000_cy_6_2 : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy_5_3,
DI => Mrom_databus_mux0005,
S => Mcompar_wait_time_cmp_ge0000_lut_6_1_499,
O => Mcompar_wait_time_cmp_ge0000_cy_6_3
);
Mcompar_wait_time_cmp_ge0000_lut_7_2 : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => count_us(23),
I1 => count_us(24),
I2 => count_us(25),
I3 => count_us(26),
O => Mcompar_wait_time_cmp_ge0000_lut_7_2_502
);
Mcompar_wait_time_cmp_ge0000_cy_7_2 : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy_6_3,
DI => Mrom_databus_mux0005,
S => Mcompar_wait_time_cmp_ge0000_lut_7_2_502,
O => Mcompar_wait_time_cmp_ge0000_cy_7_3
);
Mcompar_wait_time_cmp_ge0000_lut_8_3 : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => count_us(27),
I1 => count_us(28),
I2 => count_us(29),
I3 => count_us(30),
O => Mcompar_wait_time_cmp_ge0000_lut_8_3_506
);
Mcompar_wait_time_cmp_ge0000_cy_8_2 : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy_7_3,
DI => Mrom_databus_mux0005,
S => Mcompar_wait_time_cmp_ge0000_lut_8_3_506,
O => Mcompar_wait_time_cmp_ge0000_cy_8_3
);
Mcompar_wait_time_cmp_ge0000_cy_9_2 : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0000_cy_8_3,
DI => Mrom_databus_mux000512,
S => Mcompar_wait_time_cmp_ge0000_lut_9_3,
O => databus_cmp_ge0002
);
G1_Madd_cnt_add0000_cy_0_Q : MUXCY
port map (
CI => Mrom_databus_mux000512,
DI => Mrom_databus_mux0005,
S => G1_Madd_cnt_add0000_lut(0),
O => G1_Madd_cnt_add0000_cy(0)
);
G1_Madd_cnt_add0000_cy_1_Q : MUXCY
port map (
CI => G1_Madd_cnt_add0000_cy(0),
DI => Mrom_databus_mux000512,
S => G1_Madd_cnt_add0000_cy_1_rt_42,
O => G1_Madd_cnt_add0000_cy(1)
);
G1_Madd_cnt_add0000_xor_1_Q : XORCY
port map (
CI => G1_Madd_cnt_add0000_cy(0),
LI => G1_Madd_cnt_add0000_cy_1_rt_42,
O => G1_cnt_add0000(1)
);
G1_Madd_cnt_add0000_cy_2_Q : MUXCY
port map (
CI => G1_Madd_cnt_add0000_cy(1),
DI => Mrom_databus_mux000512,
S => G1_Madd_cnt_add0000_cy_2_rt_64,
O => G1_Madd_cnt_add0000_cy(2)
);
G1_Madd_cnt_add0000_xor_2_Q : XORCY
port map (
CI => G1_Madd_cnt_add0000_cy(1),
LI => G1_Madd_cnt_add0000_cy_2_rt_64,
O => G1_cnt_add0000(2)
);
G1_Madd_cnt_add0000_cy_3_Q : MUXCY
port map (
CI => G1_Madd_cnt_add0000_cy(2),
DI => Mrom_databus_mux000512,
S => G1_Madd_cnt_add0000_cy_3_rt_68,
O => G1_Madd_cnt_add0000_cy(3)
);
G1_Madd_cnt_add0000_xor_3_Q : XORCY
port map (
CI => G1_Madd_cnt_add0000_cy(2),
LI => G1_Madd_cnt_add0000_cy_3_rt_68,
O => G1_cnt_add0000(3)
);
G1_Madd_cnt_add0000_cy_4_Q : MUXCY
port map (
CI => G1_Madd_cnt_add0000_cy(3),
DI => Mrom_databus_mux000512,
S => G1_Madd_cnt_add0000_cy_4_rt_70,
O => G1_Madd_cnt_add0000_cy(4)
);
G1_Madd_cnt_add0000_xor_4_Q : XORCY
port map (
CI => G1_Madd_cnt_add0000_cy(3),
LI => G1_Madd_cnt_add0000_cy_4_rt_70,
O => G1_cnt_add0000(4)
);
G1_Madd_cnt_add0000_cy_5_Q : MUXCY
port map (
CI => G1_Madd_cnt_add0000_cy(4),
DI => Mrom_databus_mux000512,
S => G1_Madd_cnt_add0000_cy_5_rt_72,
O => G1_Madd_cnt_add0000_cy(5)
);
G1_Madd_cnt_add0000_xor_5_Q : XORCY
port map (
CI => G1_Madd_cnt_add0000_cy(4),
LI => G1_Madd_cnt_add0000_cy_5_rt_72,
O => G1_cnt_add0000(5)
);
G1_Madd_cnt_add0000_cy_6_Q : MUXCY
port map (
CI => G1_Madd_cnt_add0000_cy(5),
DI => Mrom_databus_mux000512,
S => G1_Madd_cnt_add0000_cy_6_rt_74,
O => G1_Madd_cnt_add0000_cy(6)
);
G1_Madd_cnt_add0000_xor_6_Q : XORCY
port map (
CI => G1_Madd_cnt_add0000_cy(5),
LI => G1_Madd_cnt_add0000_cy_6_rt_74,
O => G1_cnt_add0000(6)
);
G1_Madd_cnt_add0000_cy_7_Q : MUXCY
port map (
CI => G1_Madd_cnt_add0000_cy(6),
DI => Mrom_databus_mux000512,
S => G1_Madd_cnt_add0000_cy_7_rt_76,
O => G1_Madd_cnt_add0000_cy(7)
);
G1_Madd_cnt_add0000_xor_7_Q : XORCY
port map (
CI => G1_Madd_cnt_add0000_cy(6),
LI => G1_Madd_cnt_add0000_cy_7_rt_76,
O => G1_cnt_add0000(7)
);
G1_Madd_cnt_add0000_cy_8_Q : MUXCY
port map (
CI => G1_Madd_cnt_add0000_cy(7),
DI => Mrom_databus_mux000512,
S => G1_Madd_cnt_add0000_cy_8_rt_78,
O => G1_Madd_cnt_add0000_cy(8)
);
G1_Madd_cnt_add0000_xor_8_Q : XORCY
port map (
CI => G1_Madd_cnt_add0000_cy(7),
LI => G1_Madd_cnt_add0000_cy_8_rt_78,
O => G1_cnt_add0000(8)
);
G1_Madd_cnt_add0000_cy_9_Q : MUXCY
port map (
CI => G1_Madd_cnt_add0000_cy(8),
DI => Mrom_databus_mux000512,
S => G1_Madd_cnt_add0000_cy_9_rt_80,
O => G1_Madd_cnt_add0000_cy(9)
);
G1_Madd_cnt_add0000_xor_9_Q : XORCY
port map (
CI => G1_Madd_cnt_add0000_cy(8),
LI => G1_Madd_cnt_add0000_cy_9_rt_80,
O => G1_cnt_add0000(9)
);
G1_Madd_cnt_add0000_cy_10_Q : MUXCY
port map (
CI => G1_Madd_cnt_add0000_cy(9),
DI => Mrom_databus_mux000512,
S => G1_Madd_cnt_add0000_cy_10_rt_22,
O => G1_Madd_cnt_add0000_cy(10)
);
G1_Madd_cnt_add0000_xor_10_Q : XORCY
port map (
CI => G1_Madd_cnt_add0000_cy(9),
LI => G1_Madd_cnt_add0000_cy_10_rt_22,
O => G1_cnt_add0000(10)
);
G1_Madd_cnt_add0000_cy_11_Q : MUXCY
port map (
CI => G1_Madd_cnt_add0000_cy(10),
DI => Mrom_databus_mux000512,
S => G1_Madd_cnt_add0000_cy_11_rt_24,
O => G1_Madd_cnt_add0000_cy(11)
);
G1_Madd_cnt_add0000_xor_11_Q : XORCY
port map (
CI => G1_Madd_cnt_add0000_cy(10),
LI => G1_Madd_cnt_add0000_cy_11_rt_24,
O => G1_cnt_add0000(11)
);
G1_Madd_cnt_add0000_cy_12_Q : MUXCY
port map (
CI => G1_Madd_cnt_add0000_cy(11),
DI => Mrom_databus_mux000512,
S => G1_Madd_cnt_add0000_cy_12_rt_26,
O => G1_Madd_cnt_add0000_cy(12)
);
G1_Madd_cnt_add0000_xor_12_Q : XORCY
port map (
CI => G1_Madd_cnt_add0000_cy(11),
LI => G1_Madd_cnt_add0000_cy_12_rt_26,
O => G1_cnt_add0000(12)
);
G1_Madd_cnt_add0000_cy_13_Q : MUXCY
port map (
CI => G1_Madd_cnt_add0000_cy(12),
DI => Mrom_databus_mux000512,
S => G1_Madd_cnt_add0000_cy_13_rt_28,
O => G1_Madd_cnt_add0000_cy(13)
);
G1_Madd_cnt_add0000_xor_13_Q : XORCY
port map (
CI => G1_Madd_cnt_add0000_cy(12),
LI => G1_Madd_cnt_add0000_cy_13_rt_28,
O => G1_cnt_add0000(13)
);
G1_Madd_cnt_add0000_cy_14_Q : MUXCY
port map (
CI => G1_Madd_cnt_add0000_cy(13),
DI => Mrom_databus_mux000512,
S => G1_Madd_cnt_add0000_cy_14_rt_30,
O => G1_Madd_cnt_add0000_cy(14)
);
G1_Madd_cnt_add0000_xor_14_Q : XORCY
port map (
CI => G1_Madd_cnt_add0000_cy(13),
LI => G1_Madd_cnt_add0000_cy_14_rt_30,
O => G1_cnt_add0000(14)
);
G1_Madd_cnt_add0000_cy_15_Q : MUXCY
port map (
CI => G1_Madd_cnt_add0000_cy(14),
DI => Mrom_databus_mux000512,
S => G1_Madd_cnt_add0000_cy_15_rt_32,
O => G1_Madd_cnt_add0000_cy(15)
);
G1_Madd_cnt_add0000_xor_15_Q : XORCY
port map (
CI => G1_Madd_cnt_add0000_cy(14),
LI => G1_Madd_cnt_add0000_cy_15_rt_32,
O => G1_cnt_add0000(15)
);
G1_Madd_cnt_add0000_cy_16_Q : MUXCY
port map (
CI => G1_Madd_cnt_add0000_cy(15),
DI => Mrom_databus_mux000512,
S => G1_Madd_cnt_add0000_cy_16_rt_34,
O => G1_Madd_cnt_add0000_cy(16)
);
G1_Madd_cnt_add0000_xor_16_Q : XORCY
port map (
CI => G1_Madd_cnt_add0000_cy(15),
LI => G1_Madd_cnt_add0000_cy_16_rt_34,
O => G1_cnt_add0000(16)
);
G1_Madd_cnt_add0000_cy_17_Q : MUXCY
port map (
CI => G1_Madd_cnt_add0000_cy(16),
DI => Mrom_databus_mux000512,
S => G1_Madd_cnt_add0000_cy_17_rt_36,
O => G1_Madd_cnt_add0000_cy(17)
);
G1_Madd_cnt_add0000_xor_17_Q : XORCY
port map (
CI => G1_Madd_cnt_add0000_cy(16),
LI => G1_Madd_cnt_add0000_cy_17_rt_36,
O => G1_cnt_add0000(17)
);
G1_Madd_cnt_add0000_cy_18_Q : MUXCY
port map (
CI => G1_Madd_cnt_add0000_cy(17),
DI => Mrom_databus_mux000512,
S => G1_Madd_cnt_add0000_cy_18_rt_38,
O => G1_Madd_cnt_add0000_cy(18)
);
G1_Madd_cnt_add0000_xor_18_Q : XORCY
port map (
CI => G1_Madd_cnt_add0000_cy(17),
LI => G1_Madd_cnt_add0000_cy_18_rt_38,
O => G1_cnt_add0000(18)
);
G1_Madd_cnt_add0000_cy_19_Q : MUXCY
port map (
CI => G1_Madd_cnt_add0000_cy(18),
DI => Mrom_databus_mux000512,
S => G1_Madd_cnt_add0000_cy_19_rt_40,
O => G1_Madd_cnt_add0000_cy(19)
);
G1_Madd_cnt_add0000_xor_19_Q : XORCY
port map (
CI => G1_Madd_cnt_add0000_cy(18),
LI => G1_Madd_cnt_add0000_cy_19_rt_40,
O => G1_cnt_add0000(19)
);
G1_Madd_cnt_add0000_cy_20_Q : MUXCY
port map (
CI => G1_Madd_cnt_add0000_cy(19),
DI => Mrom_databus_mux000512,
S => G1_Madd_cnt_add0000_cy_20_rt_44,
O => G1_Madd_cnt_add0000_cy(20)
);
G1_Madd_cnt_add0000_xor_20_Q : XORCY
port map (
CI => G1_Madd_cnt_add0000_cy(19),
LI => G1_Madd_cnt_add0000_cy_20_rt_44,
O => G1_cnt_add0000(20)
);
G1_Madd_cnt_add0000_cy_21_Q : MUXCY
port map (
CI => G1_Madd_cnt_add0000_cy(20),
DI => Mrom_databus_mux000512,
S => G1_Madd_cnt_add0000_cy_21_rt_46,
O => G1_Madd_cnt_add0000_cy(21)
);
G1_Madd_cnt_add0000_xor_21_Q : XORCY
port map (
CI => G1_Madd_cnt_add0000_cy(20),
LI => G1_Madd_cnt_add0000_cy_21_rt_46,
O => G1_cnt_add0000(21)
);
G1_Madd_cnt_add0000_cy_22_Q : MUXCY
port map (
CI => G1_Madd_cnt_add0000_cy(21),
DI => Mrom_databus_mux000512,
S => G1_Madd_cnt_add0000_cy_22_rt_48,
O => G1_Madd_cnt_add0000_cy(22)
);
G1_Madd_cnt_add0000_xor_22_Q : XORCY
port map (
CI => G1_Madd_cnt_add0000_cy(21),
LI => G1_Madd_cnt_add0000_cy_22_rt_48,
O => G1_cnt_add0000(22)
);
G1_Madd_cnt_add0000_cy_23_Q : MUXCY
port map (
CI => G1_Madd_cnt_add0000_cy(22),
DI => Mrom_databus_mux000512,
S => G1_Madd_cnt_add0000_cy_23_rt_50,
O => G1_Madd_cnt_add0000_cy(23)
);
G1_Madd_cnt_add0000_xor_23_Q : XORCY
port map (
CI => G1_Madd_cnt_add0000_cy(22),
LI => G1_Madd_cnt_add0000_cy_23_rt_50,
O => G1_cnt_add0000(23)
);
G1_Madd_cnt_add0000_cy_24_Q : MUXCY
port map (
CI => G1_Madd_cnt_add0000_cy(23),
DI => Mrom_databus_mux000512,
S => G1_Madd_cnt_add0000_cy_24_rt_52,
O => G1_Madd_cnt_add0000_cy(24)
);
G1_Madd_cnt_add0000_xor_24_Q : XORCY
port map (
CI => G1_Madd_cnt_add0000_cy(23),
LI => G1_Madd_cnt_add0000_cy_24_rt_52,
O => G1_cnt_add0000(24)
);
G1_Madd_cnt_add0000_cy_25_Q : MUXCY
port map (
CI => G1_Madd_cnt_add0000_cy(24),
DI => Mrom_databus_mux000512,
S => G1_Madd_cnt_add0000_cy_25_rt_54,
O => G1_Madd_cnt_add0000_cy(25)
);
G1_Madd_cnt_add0000_xor_25_Q : XORCY
port map (
CI => G1_Madd_cnt_add0000_cy(24),
LI => G1_Madd_cnt_add0000_cy_25_rt_54,
O => G1_cnt_add0000(25)
);
G1_Madd_cnt_add0000_cy_26_Q : MUXCY
port map (
CI => G1_Madd_cnt_add0000_cy(25),
DI => Mrom_databus_mux000512,
S => G1_Madd_cnt_add0000_cy_26_rt_56,
O => G1_Madd_cnt_add0000_cy(26)
);
G1_Madd_cnt_add0000_xor_26_Q : XORCY
port map (
CI => G1_Madd_cnt_add0000_cy(25),
LI => G1_Madd_cnt_add0000_cy_26_rt_56,
O => G1_cnt_add0000(26)
);
G1_Madd_cnt_add0000_cy_27_Q : MUXCY
port map (
CI => G1_Madd_cnt_add0000_cy(26),
DI => Mrom_databus_mux000512,
S => G1_Madd_cnt_add0000_cy_27_rt_58,
O => G1_Madd_cnt_add0000_cy(27)
);
G1_Madd_cnt_add0000_xor_27_Q : XORCY
port map (
CI => G1_Madd_cnt_add0000_cy(26),
LI => G1_Madd_cnt_add0000_cy_27_rt_58,
O => G1_cnt_add0000(27)
);
G1_Madd_cnt_add0000_cy_28_Q : MUXCY
port map (
CI => G1_Madd_cnt_add0000_cy(27),
DI => Mrom_databus_mux000512,
S => G1_Madd_cnt_add0000_cy_28_rt_60,
O => G1_Madd_cnt_add0000_cy(28)
);
G1_Madd_cnt_add0000_xor_28_Q : XORCY
port map (
CI => G1_Madd_cnt_add0000_cy(27),
LI => G1_Madd_cnt_add0000_cy_28_rt_60,
O => G1_cnt_add0000(28)
);
G1_Madd_cnt_add0000_cy_29_Q : MUXCY
port map (
CI => G1_Madd_cnt_add0000_cy(28),
DI => Mrom_databus_mux000512,
S => G1_Madd_cnt_add0000_cy_29_rt_62,
O => G1_Madd_cnt_add0000_cy(29)
);
G1_Madd_cnt_add0000_xor_29_Q : XORCY
port map (
CI => G1_Madd_cnt_add0000_cy(28),
LI => G1_Madd_cnt_add0000_cy_29_rt_62,
O => G1_cnt_add0000(29)
);
G1_Madd_cnt_add0000_cy_30_Q : MUXCY
port map (
CI => G1_Madd_cnt_add0000_cy(29),
DI => Mrom_databus_mux000512,
S => G1_Madd_cnt_add0000_cy_30_rt_66,
O => G1_Madd_cnt_add0000_cy(30)
);
G1_Madd_cnt_add0000_xor_30_Q : XORCY
port map (
CI => G1_Madd_cnt_add0000_cy(29),
LI => G1_Madd_cnt_add0000_cy_30_rt_66,
O => G1_cnt_add0000(30)
);
G1_Madd_cnt_add0000_xor_31_Q : XORCY
port map (
CI => G1_Madd_cnt_add0000_cy(30),
LI => G1_Madd_cnt_add0000_xor_31_rt_82,
O => G1_cnt_add0000(31)
);
G1_Mcount_cnt_cy_0_Q : MUXCY
port map (
CI => Mrom_databus_mux000512,
DI => Mrom_databus_mux0005,
S => G1_Mcount_cnt_lut(0),
O => G1_Mcount_cnt_cy(0)
);
G1_Mcount_cnt_cy_1_Q : MUXCY
port map (
CI => G1_Mcount_cnt_cy(0),
DI => Mrom_databus_mux000512,
S => G1_Mcount_cnt_cy_1_rt_105,
O => G1_Mcount_cnt_cy(1)
);
G1_Mcount_cnt_xor_1_Q : XORCY
port map (
CI => G1_Mcount_cnt_cy(0),
LI => G1_Mcount_cnt_cy_1_rt_105,
O => Result_1_1
);
G1_Mcount_cnt_cy_2_Q : MUXCY
port map (
CI => G1_Mcount_cnt_cy(1),
DI => Mrom_databus_mux000512,
S => G1_Mcount_cnt_cy_2_rt_127,
O => G1_Mcount_cnt_cy(2)
);
G1_Mcount_cnt_xor_2_Q : XORCY
port map (
CI => G1_Mcount_cnt_cy(1),
LI => G1_Mcount_cnt_cy_2_rt_127,
O => Result_2_1
);
G1_Mcount_cnt_cy_3_Q : MUXCY
port map (
CI => G1_Mcount_cnt_cy(2),
DI => Mrom_databus_mux000512,
S => G1_Mcount_cnt_cy_3_rt_131,
O => G1_Mcount_cnt_cy(3)
);
G1_Mcount_cnt_xor_3_Q : XORCY
port map (
CI => G1_Mcount_cnt_cy(2),
LI => G1_Mcount_cnt_cy_3_rt_131,
O => Result_3_1
);
G1_Mcount_cnt_cy_4_Q : MUXCY
port map (
CI => G1_Mcount_cnt_cy(3),
DI => Mrom_databus_mux000512,
S => G1_Mcount_cnt_cy_4_rt_133,
O => G1_Mcount_cnt_cy(4)
);
G1_Mcount_cnt_xor_4_Q : XORCY
port map (
CI => G1_Mcount_cnt_cy(3),
LI => G1_Mcount_cnt_cy_4_rt_133,
O => Result_4_1
);
G1_Mcount_cnt_cy_5_Q : MUXCY
port map (
CI => G1_Mcount_cnt_cy(4),
DI => Mrom_databus_mux000512,
S => G1_Mcount_cnt_cy_5_rt_135,
O => G1_Mcount_cnt_cy(5)
);
G1_Mcount_cnt_xor_5_Q : XORCY
port map (
CI => G1_Mcount_cnt_cy(4),
LI => G1_Mcount_cnt_cy_5_rt_135,
O => Result_5_1
);
G1_Mcount_cnt_cy_6_Q : MUXCY
port map (
CI => G1_Mcount_cnt_cy(5),
DI => Mrom_databus_mux000512,
S => G1_Mcount_cnt_cy_6_rt_137,
O => G1_Mcount_cnt_cy(6)
);
G1_Mcount_cnt_xor_6_Q : XORCY
port map (
CI => G1_Mcount_cnt_cy(5),
LI => G1_Mcount_cnt_cy_6_rt_137,
O => Result_6_1
);
G1_Mcount_cnt_cy_7_Q : MUXCY
port map (
CI => G1_Mcount_cnt_cy(6),
DI => Mrom_databus_mux000512,
S => G1_Mcount_cnt_cy_7_rt_139,
O => G1_Mcount_cnt_cy(7)
);
G1_Mcount_cnt_xor_7_Q : XORCY
port map (
CI => G1_Mcount_cnt_cy(6),
LI => G1_Mcount_cnt_cy_7_rt_139,
O => Result_7_1
);
G1_Mcount_cnt_cy_8_Q : MUXCY
port map (
CI => G1_Mcount_cnt_cy(7),
DI => Mrom_databus_mux000512,
S => G1_Mcount_cnt_cy_8_rt_141,
O => G1_Mcount_cnt_cy(8)
);
G1_Mcount_cnt_xor_8_Q : XORCY
port map (
CI => G1_Mcount_cnt_cy(7),
LI => G1_Mcount_cnt_cy_8_rt_141,
O => Result_8_1
);
G1_Mcount_cnt_cy_9_Q : MUXCY
port map (
CI => G1_Mcount_cnt_cy(8),
DI => Mrom_databus_mux000512,
S => G1_Mcount_cnt_cy_9_rt_143,
O => G1_Mcount_cnt_cy(9)
);
G1_Mcount_cnt_xor_9_Q : XORCY
port map (
CI => G1_Mcount_cnt_cy(8),
LI => G1_Mcount_cnt_cy_9_rt_143,
O => Result_9_1
);
G1_Mcount_cnt_cy_10_Q : MUXCY
port map (
CI => G1_Mcount_cnt_cy(9),
DI => Mrom_databus_mux000512,
S => G1_Mcount_cnt_cy_10_rt_85,
O => G1_Mcount_cnt_cy(10)
);
G1_Mcount_cnt_xor_10_Q : XORCY
port map (
CI => G1_Mcount_cnt_cy(9),
LI => G1_Mcount_cnt_cy_10_rt_85,
O => Result_10_1
);
G1_Mcount_cnt_cy_11_Q : MUXCY
port map (
CI => G1_Mcount_cnt_cy(10),
DI => Mrom_databus_mux000512,
S => G1_Mcount_cnt_cy_11_rt_87,
O => G1_Mcount_cnt_cy(11)
);
G1_Mcount_cnt_xor_11_Q : XORCY
port map (
CI => G1_Mcount_cnt_cy(10),
LI => G1_Mcount_cnt_cy_11_rt_87,
O => Result_11_1
);
G1_Mcount_cnt_cy_12_Q : MUXCY
port map (
CI => G1_Mcount_cnt_cy(11),
DI => Mrom_databus_mux000512,
S => G1_Mcount_cnt_cy_12_rt_89,
O => G1_Mcount_cnt_cy(12)
);
G1_Mcount_cnt_xor_12_Q : XORCY
port map (
CI => G1_Mcount_cnt_cy(11),
LI => G1_Mcount_cnt_cy_12_rt_89,
O => Result_12_1
);
G1_Mcount_cnt_cy_13_Q : MUXCY
port map (
CI => G1_Mcount_cnt_cy(12),
DI => Mrom_databus_mux000512,
S => G1_Mcount_cnt_cy_13_rt_91,
O => G1_Mcount_cnt_cy(13)
);
G1_Mcount_cnt_xor_13_Q : XORCY
port map (
CI => G1_Mcount_cnt_cy(12),
LI => G1_Mcount_cnt_cy_13_rt_91,
O => Result_13_1
);
G1_Mcount_cnt_cy_14_Q : MUXCY
port map (
CI => G1_Mcount_cnt_cy(13),
DI => Mrom_databus_mux000512,
S => G1_Mcount_cnt_cy_14_rt_93,
O => G1_Mcount_cnt_cy(14)
);
G1_Mcount_cnt_xor_14_Q : XORCY
port map (
CI => G1_Mcount_cnt_cy(13),
LI => G1_Mcount_cnt_cy_14_rt_93,
O => Result_14_1
);
G1_Mcount_cnt_cy_15_Q : MUXCY
port map (
CI => G1_Mcount_cnt_cy(14),
DI => Mrom_databus_mux000512,
S => G1_Mcount_cnt_cy_15_rt_95,
O => G1_Mcount_cnt_cy(15)
);
G1_Mcount_cnt_xor_15_Q : XORCY
port map (
CI => G1_Mcount_cnt_cy(14),
LI => G1_Mcount_cnt_cy_15_rt_95,
O => Result_15_1
);
G1_Mcount_cnt_cy_16_Q : MUXCY
port map (
CI => G1_Mcount_cnt_cy(15),
DI => Mrom_databus_mux000512,
S => G1_Mcount_cnt_cy_16_rt_97,
O => G1_Mcount_cnt_cy(16)
);
G1_Mcount_cnt_xor_16_Q : XORCY
port map (
CI => G1_Mcount_cnt_cy(15),
LI => G1_Mcount_cnt_cy_16_rt_97,
O => Result_16_1
);
G1_Mcount_cnt_cy_17_Q : MUXCY
port map (
CI => G1_Mcount_cnt_cy(16),
DI => Mrom_databus_mux000512,
S => G1_Mcount_cnt_cy_17_rt_99,
O => G1_Mcount_cnt_cy(17)
);
G1_Mcount_cnt_xor_17_Q : XORCY
port map (
CI => G1_Mcount_cnt_cy(16),
LI => G1_Mcount_cnt_cy_17_rt_99,
O => Result_17_1
);
G1_Mcount_cnt_cy_18_Q : MUXCY
port map (
CI => G1_Mcount_cnt_cy(17),
DI => Mrom_databus_mux000512,
S => G1_Mcount_cnt_cy_18_rt_101,
O => G1_Mcount_cnt_cy(18)
);
G1_Mcount_cnt_xor_18_Q : XORCY
port map (
CI => G1_Mcount_cnt_cy(17),
LI => G1_Mcount_cnt_cy_18_rt_101,
O => Result_18_1
);
G1_Mcount_cnt_cy_19_Q : MUXCY
port map (
CI => G1_Mcount_cnt_cy(18),
DI => Mrom_databus_mux000512,
S => G1_Mcount_cnt_cy_19_rt_103,
O => G1_Mcount_cnt_cy(19)
);
G1_Mcount_cnt_xor_19_Q : XORCY
port map (
CI => G1_Mcount_cnt_cy(18),
LI => G1_Mcount_cnt_cy_19_rt_103,
O => Result_19_1
);
G1_Mcount_cnt_cy_20_Q : MUXCY
port map (
CI => G1_Mcount_cnt_cy(19),
DI => Mrom_databus_mux000512,
S => G1_Mcount_cnt_cy_20_rt_107,
O => G1_Mcount_cnt_cy(20)
);
G1_Mcount_cnt_xor_20_Q : XORCY
port map (
CI => G1_Mcount_cnt_cy(19),
LI => G1_Mcount_cnt_cy_20_rt_107,
O => Result_20_1
);
G1_Mcount_cnt_cy_21_Q : MUXCY
port map (
CI => G1_Mcount_cnt_cy(20),
DI => Mrom_databus_mux000512,
S => G1_Mcount_cnt_cy_21_rt_109,
O => G1_Mcount_cnt_cy(21)
);
G1_Mcount_cnt_xor_21_Q : XORCY
port map (
CI => G1_Mcount_cnt_cy(20),
LI => G1_Mcount_cnt_cy_21_rt_109,
O => Result_21_1
);
G1_Mcount_cnt_cy_22_Q : MUXCY
port map (
CI => G1_Mcount_cnt_cy(21),
DI => Mrom_databus_mux000512,
S => G1_Mcount_cnt_cy_22_rt_111,
O => G1_Mcount_cnt_cy(22)
);
G1_Mcount_cnt_xor_22_Q : XORCY
port map (
CI => G1_Mcount_cnt_cy(21),
LI => G1_Mcount_cnt_cy_22_rt_111,
O => Result_22_1
);
G1_Mcount_cnt_cy_23_Q : MUXCY
port map (
CI => G1_Mcount_cnt_cy(22),
DI => Mrom_databus_mux000512,
S => G1_Mcount_cnt_cy_23_rt_113,
O => G1_Mcount_cnt_cy(23)
);
G1_Mcount_cnt_xor_23_Q : XORCY
port map (
CI => G1_Mcount_cnt_cy(22),
LI => G1_Mcount_cnt_cy_23_rt_113,
O => Result_23_1
);
G1_Mcount_cnt_cy_24_Q : MUXCY
port map (
CI => G1_Mcount_cnt_cy(23),
DI => Mrom_databus_mux000512,
S => G1_Mcount_cnt_cy_24_rt_115,
O => G1_Mcount_cnt_cy(24)
);
G1_Mcount_cnt_xor_24_Q : XORCY
port map (
CI => G1_Mcount_cnt_cy(23),
LI => G1_Mcount_cnt_cy_24_rt_115,
O => Result_24_1
);
G1_Mcount_cnt_cy_25_Q : MUXCY
port map (
CI => G1_Mcount_cnt_cy(24),
DI => Mrom_databus_mux000512,
S => G1_Mcount_cnt_cy_25_rt_117,
O => G1_Mcount_cnt_cy(25)
);
G1_Mcount_cnt_xor_25_Q : XORCY
port map (
CI => G1_Mcount_cnt_cy(24),
LI => G1_Mcount_cnt_cy_25_rt_117,
O => Result_25_1
);
G1_Mcount_cnt_cy_26_Q : MUXCY
port map (
CI => G1_Mcount_cnt_cy(25),
DI => Mrom_databus_mux000512,
S => G1_Mcount_cnt_cy_26_rt_119,
O => G1_Mcount_cnt_cy(26)
);
G1_Mcount_cnt_xor_26_Q : XORCY
port map (
CI => G1_Mcount_cnt_cy(25),
LI => G1_Mcount_cnt_cy_26_rt_119,
O => Result_26_1
);
G1_Mcount_cnt_cy_27_Q : MUXCY
port map (
CI => G1_Mcount_cnt_cy(26),
DI => Mrom_databus_mux000512,
S => G1_Mcount_cnt_cy_27_rt_121,
O => G1_Mcount_cnt_cy(27)
);
G1_Mcount_cnt_xor_27_Q : XORCY
port map (
CI => G1_Mcount_cnt_cy(26),
LI => G1_Mcount_cnt_cy_27_rt_121,
O => Result_27_1
);
G1_Mcount_cnt_cy_28_Q : MUXCY
port map (
CI => G1_Mcount_cnt_cy(27),
DI => Mrom_databus_mux000512,
S => G1_Mcount_cnt_cy_28_rt_123,
O => G1_Mcount_cnt_cy(28)
);
G1_Mcount_cnt_xor_28_Q : XORCY
port map (
CI => G1_Mcount_cnt_cy(27),
LI => G1_Mcount_cnt_cy_28_rt_123,
O => Result_28_1
);
G1_Mcount_cnt_cy_29_Q : MUXCY
port map (
CI => G1_Mcount_cnt_cy(28),
DI => Mrom_databus_mux000512,
S => G1_Mcount_cnt_cy_29_rt_125,
O => G1_Mcount_cnt_cy(29)
);
G1_Mcount_cnt_xor_29_Q : XORCY
port map (
CI => G1_Mcount_cnt_cy(28),
LI => G1_Mcount_cnt_cy_29_rt_125,
O => Result_29_1
);
G1_Mcount_cnt_cy_30_Q : MUXCY
port map (
CI => G1_Mcount_cnt_cy(29),
DI => Mrom_databus_mux000512,
S => G1_Mcount_cnt_cy_30_rt_129,
O => G1_Mcount_cnt_cy(30)
);
G1_Mcount_cnt_xor_30_Q : XORCY
port map (
CI => G1_Mcount_cnt_cy(29),
LI => G1_Mcount_cnt_cy_30_rt_129,
O => Result_30_1
);
G1_Mcount_cnt_xor_31_Q : XORCY
port map (
CI => G1_Mcount_cnt_cy(30),
LI => G1_Mcount_cnt_xor_31_rt_145,
O => Result_31_1
);
Mcount_count_us_cy_0_Q : MUXCY
port map (
CI => Mrom_databus_mux000512,
DI => Mrom_databus_mux0005,
S => Mcount_count_us_lut(0),
O => Mcount_count_us_cy(0)
);
Mcount_count_us_cy_1_Q : MUXCY
port map (
CI => Mcount_count_us_cy(0),
DI => Mrom_databus_mux000512,
S => Mcount_count_us_cy_1_rt_614,
O => Mcount_count_us_cy(1)
);
Mcount_count_us_xor_1_Q : XORCY
port map (
CI => Mcount_count_us_cy(0),
LI => Mcount_count_us_cy_1_rt_614,
O => Result(1)
);
Mcount_count_us_cy_2_Q : MUXCY
port map (
CI => Mcount_count_us_cy(1),
DI => Mrom_databus_mux000512,
S => Mcount_count_us_cy_2_rt_636,
O => Mcount_count_us_cy(2)
);
Mcount_count_us_xor_2_Q : XORCY
port map (
CI => Mcount_count_us_cy(1),
LI => Mcount_count_us_cy_2_rt_636,
O => Result(2)
);
Mcount_count_us_cy_3_Q : MUXCY
port map (
CI => Mcount_count_us_cy(2),
DI => Mrom_databus_mux000512,
S => Mcount_count_us_cy_3_rt_640,
O => Mcount_count_us_cy(3)
);
Mcount_count_us_xor_3_Q : XORCY
port map (
CI => Mcount_count_us_cy(2),
LI => Mcount_count_us_cy_3_rt_640,
O => Result(3)
);
Mcount_count_us_cy_4_Q : MUXCY
port map (
CI => Mcount_count_us_cy(3),
DI => Mrom_databus_mux000512,
S => Mcount_count_us_cy_4_rt_642,
O => Mcount_count_us_cy(4)
);
Mcount_count_us_xor_4_Q : XORCY
port map (
CI => Mcount_count_us_cy(3),
LI => Mcount_count_us_cy_4_rt_642,
O => Result(4)
);
Mcount_count_us_cy_5_Q : MUXCY
port map (
CI => Mcount_count_us_cy(4),
DI => Mrom_databus_mux000512,
S => Mcount_count_us_cy_5_rt_644,
O => Mcount_count_us_cy(5)
);
Mcount_count_us_xor_5_Q : XORCY
port map (
CI => Mcount_count_us_cy(4),
LI => Mcount_count_us_cy_5_rt_644,
O => Result(5)
);
Mcount_count_us_cy_6_Q : MUXCY
port map (
CI => Mcount_count_us_cy(5),
DI => Mrom_databus_mux000512,
S => Mcount_count_us_cy_6_rt_646,
O => Mcount_count_us_cy(6)
);
Mcount_count_us_xor_6_Q : XORCY
port map (
CI => Mcount_count_us_cy(5),
LI => Mcount_count_us_cy_6_rt_646,
O => Result(6)
);
Mcount_count_us_cy_7_Q : MUXCY
port map (
CI => Mcount_count_us_cy(6),
DI => Mrom_databus_mux000512,
S => Mcount_count_us_cy_7_rt_648,
O => Mcount_count_us_cy(7)
);
Mcount_count_us_xor_7_Q : XORCY
port map (
CI => Mcount_count_us_cy(6),
LI => Mcount_count_us_cy_7_rt_648,
O => Result(7)
);
Mcount_count_us_cy_8_Q : MUXCY
port map (
CI => Mcount_count_us_cy(7),
DI => Mrom_databus_mux000512,
S => Mcount_count_us_cy_8_rt_650,
O => Mcount_count_us_cy(8)
);
Mcount_count_us_xor_8_Q : XORCY
port map (
CI => Mcount_count_us_cy(7),
LI => Mcount_count_us_cy_8_rt_650,
O => Result(8)
);
Mcount_count_us_cy_9_Q : MUXCY
port map (
CI => Mcount_count_us_cy(8),
DI => Mrom_databus_mux000512,
S => Mcount_count_us_cy_9_rt_652,
O => Mcount_count_us_cy(9)
);
Mcount_count_us_xor_9_Q : XORCY
port map (
CI => Mcount_count_us_cy(8),
LI => Mcount_count_us_cy_9_rt_652,
O => Result(9)
);
Mcount_count_us_cy_10_Q : MUXCY
port map (
CI => Mcount_count_us_cy(9),
DI => Mrom_databus_mux000512,
S => Mcount_count_us_cy_10_rt_594,
O => Mcount_count_us_cy(10)
);
Mcount_count_us_xor_10_Q : XORCY
port map (
CI => Mcount_count_us_cy(9),
LI => Mcount_count_us_cy_10_rt_594,
O => Result(10)
);
Mcount_count_us_cy_11_Q : MUXCY
port map (
CI => Mcount_count_us_cy(10),
DI => Mrom_databus_mux000512,
S => Mcount_count_us_cy_11_rt_596,
O => Mcount_count_us_cy(11)
);
Mcount_count_us_xor_11_Q : XORCY
port map (
CI => Mcount_count_us_cy(10),
LI => Mcount_count_us_cy_11_rt_596,
O => Result(11)
);
Mcount_count_us_cy_12_Q : MUXCY
port map (
CI => Mcount_count_us_cy(11),
DI => Mrom_databus_mux000512,
S => Mcount_count_us_cy_12_rt_598,
O => Mcount_count_us_cy(12)
);
Mcount_count_us_xor_12_Q : XORCY
port map (
CI => Mcount_count_us_cy(11),
LI => Mcount_count_us_cy_12_rt_598,
O => Result(12)
);
Mcount_count_us_cy_13_Q : MUXCY
port map (
CI => Mcount_count_us_cy(12),
DI => Mrom_databus_mux000512,
S => Mcount_count_us_cy_13_rt_600,
O => Mcount_count_us_cy(13)
);
Mcount_count_us_xor_13_Q : XORCY
port map (
CI => Mcount_count_us_cy(12),
LI => Mcount_count_us_cy_13_rt_600,
O => Result(13)
);
Mcount_count_us_cy_14_Q : MUXCY
port map (
CI => Mcount_count_us_cy(13),
DI => Mrom_databus_mux000512,
S => Mcount_count_us_cy_14_rt_602,
O => Mcount_count_us_cy(14)
);
Mcount_count_us_xor_14_Q : XORCY
port map (
CI => Mcount_count_us_cy(13),
LI => Mcount_count_us_cy_14_rt_602,
O => Result(14)
);
Mcount_count_us_cy_15_Q : MUXCY
port map (
CI => Mcount_count_us_cy(14),
DI => Mrom_databus_mux000512,
S => Mcount_count_us_cy_15_rt_604,
O => Mcount_count_us_cy(15)
);
Mcount_count_us_xor_15_Q : XORCY
port map (
CI => Mcount_count_us_cy(14),
LI => Mcount_count_us_cy_15_rt_604,
O => Result(15)
);
Mcount_count_us_cy_16_Q : MUXCY
port map (
CI => Mcount_count_us_cy(15),
DI => Mrom_databus_mux000512,
S => Mcount_count_us_cy_16_rt_606,
O => Mcount_count_us_cy(16)
);
Mcount_count_us_xor_16_Q : XORCY
port map (
CI => Mcount_count_us_cy(15),
LI => Mcount_count_us_cy_16_rt_606,
O => Result(16)
);
Mcount_count_us_cy_17_Q : MUXCY
port map (
CI => Mcount_count_us_cy(16),
DI => Mrom_databus_mux000512,
S => Mcount_count_us_cy_17_rt_608,
O => Mcount_count_us_cy(17)
);
Mcount_count_us_xor_17_Q : XORCY
port map (
CI => Mcount_count_us_cy(16),
LI => Mcount_count_us_cy_17_rt_608,
O => Result(17)
);
Mcount_count_us_cy_18_Q : MUXCY
port map (
CI => Mcount_count_us_cy(17),
DI => Mrom_databus_mux000512,
S => Mcount_count_us_cy_18_rt_610,
O => Mcount_count_us_cy(18)
);
Mcount_count_us_xor_18_Q : XORCY
port map (
CI => Mcount_count_us_cy(17),
LI => Mcount_count_us_cy_18_rt_610,
O => Result(18)
);
Mcount_count_us_cy_19_Q : MUXCY
port map (
CI => Mcount_count_us_cy(18),
DI => Mrom_databus_mux000512,
S => Mcount_count_us_cy_19_rt_612,
O => Mcount_count_us_cy(19)
);
Mcount_count_us_xor_19_Q : XORCY
port map (
CI => Mcount_count_us_cy(18),
LI => Mcount_count_us_cy_19_rt_612,
O => Result(19)
);
Mcount_count_us_cy_20_Q : MUXCY
port map (
CI => Mcount_count_us_cy(19),
DI => Mrom_databus_mux000512,
S => Mcount_count_us_cy_20_rt_616,
O => Mcount_count_us_cy(20)
);
Mcount_count_us_xor_20_Q : XORCY
port map (
CI => Mcount_count_us_cy(19),
LI => Mcount_count_us_cy_20_rt_616,
O => Result(20)
);
Mcount_count_us_cy_21_Q : MUXCY
port map (
CI => Mcount_count_us_cy(20),
DI => Mrom_databus_mux000512,
S => Mcount_count_us_cy_21_rt_618,
O => Mcount_count_us_cy(21)
);
Mcount_count_us_xor_21_Q : XORCY
port map (
CI => Mcount_count_us_cy(20),
LI => Mcount_count_us_cy_21_rt_618,
O => Result(21)
);
Mcount_count_us_cy_22_Q : MUXCY
port map (
CI => Mcount_count_us_cy(21),
DI => Mrom_databus_mux000512,
S => Mcount_count_us_cy_22_rt_620,
O => Mcount_count_us_cy(22)
);
Mcount_count_us_xor_22_Q : XORCY
port map (
CI => Mcount_count_us_cy(21),
LI => Mcount_count_us_cy_22_rt_620,
O => Result(22)
);
Mcount_count_us_cy_23_Q : MUXCY
port map (
CI => Mcount_count_us_cy(22),
DI => Mrom_databus_mux000512,
S => Mcount_count_us_cy_23_rt_622,
O => Mcount_count_us_cy(23)
);
Mcount_count_us_xor_23_Q : XORCY
port map (
CI => Mcount_count_us_cy(22),
LI => Mcount_count_us_cy_23_rt_622,
O => Result(23)
);
Mcount_count_us_cy_24_Q : MUXCY
port map (
CI => Mcount_count_us_cy(23),
DI => Mrom_databus_mux000512,
S => Mcount_count_us_cy_24_rt_624,
O => Mcount_count_us_cy(24)
);
Mcount_count_us_xor_24_Q : XORCY
port map (
CI => Mcount_count_us_cy(23),
LI => Mcount_count_us_cy_24_rt_624,
O => Result(24)
);
Mcount_count_us_cy_25_Q : MUXCY
port map (
CI => Mcount_count_us_cy(24),
DI => Mrom_databus_mux000512,
S => Mcount_count_us_cy_25_rt_626,
O => Mcount_count_us_cy(25)
);
Mcount_count_us_xor_25_Q : XORCY
port map (
CI => Mcount_count_us_cy(24),
LI => Mcount_count_us_cy_25_rt_626,
O => Result(25)
);
Mcount_count_us_cy_26_Q : MUXCY
port map (
CI => Mcount_count_us_cy(25),
DI => Mrom_databus_mux000512,
S => Mcount_count_us_cy_26_rt_628,
O => Mcount_count_us_cy(26)
);
Mcount_count_us_xor_26_Q : XORCY
port map (
CI => Mcount_count_us_cy(25),
LI => Mcount_count_us_cy_26_rt_628,
O => Result(26)
);
Mcount_count_us_cy_27_Q : MUXCY
port map (
CI => Mcount_count_us_cy(26),
DI => Mrom_databus_mux000512,
S => Mcount_count_us_cy_27_rt_630,
O => Mcount_count_us_cy(27)
);
Mcount_count_us_xor_27_Q : XORCY
port map (
CI => Mcount_count_us_cy(26),
LI => Mcount_count_us_cy_27_rt_630,
O => Result(27)
);
Mcount_count_us_cy_28_Q : MUXCY
port map (
CI => Mcount_count_us_cy(27),
DI => Mrom_databus_mux000512,
S => Mcount_count_us_cy_28_rt_632,
O => Mcount_count_us_cy(28)
);
Mcount_count_us_xor_28_Q : XORCY
port map (
CI => Mcount_count_us_cy(27),
LI => Mcount_count_us_cy_28_rt_632,
O => Result(28)
);
Mcount_count_us_cy_29_Q : MUXCY
port map (
CI => Mcount_count_us_cy(28),
DI => Mrom_databus_mux000512,
S => Mcount_count_us_cy_29_rt_634,
O => Mcount_count_us_cy(29)
);
Mcount_count_us_xor_29_Q : XORCY
port map (
CI => Mcount_count_us_cy(28),
LI => Mcount_count_us_cy_29_rt_634,
O => Result(29)
);
Mcount_count_us_cy_30_Q : MUXCY
port map (
CI => Mcount_count_us_cy(29),
DI => Mrom_databus_mux000512,
S => Mcount_count_us_cy_30_rt_638,
O => Mcount_count_us_cy(30)
);
Mcount_count_us_xor_30_Q : XORCY
port map (
CI => Mcount_count_us_cy(29),
LI => Mcount_count_us_cy_30_rt_638,
O => Result(30)
);
Mcount_count_us_xor_31_Q : XORCY
port map (
CI => Mcount_count_us_cy(30),
LI => Mcount_count_us_xor_31_rt_654,
O => Result(31)
);
Mcompar_wait_time_cmp_ge0001_cy_0_Q : MUXCY
port map (
CI => Mrom_databus_mux0005,
DI => count_us(0),
S => Mcompar_wait_time_cmp_ge0001_lut(0),
O => Mcompar_wait_time_cmp_ge0001_cy(0)
);
Mcompar_wait_time_cmp_ge0001_lut_1_Q : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => count_us(1),
I1 => wait_time(1),
O => Mcompar_wait_time_cmp_ge0001_lut(1)
);
Mcompar_wait_time_cmp_ge0001_cy_1_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0001_cy(0),
DI => count_us(1),
S => Mcompar_wait_time_cmp_ge0001_lut(1),
O => Mcompar_wait_time_cmp_ge0001_cy(1)
);
Mcompar_wait_time_cmp_ge0001_lut_2_Q : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => count_us(2),
I1 => wait_time(2),
O => Mcompar_wait_time_cmp_ge0001_lut(2)
);
Mcompar_wait_time_cmp_ge0001_cy_2_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0001_cy(1),
DI => count_us(2),
S => Mcompar_wait_time_cmp_ge0001_lut(2),
O => Mcompar_wait_time_cmp_ge0001_cy(2)
);
Mcompar_wait_time_cmp_ge0001_lut_3_Q : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => count_us(3),
I1 => wait_time(3),
O => Mcompar_wait_time_cmp_ge0001_lut(3)
);
Mcompar_wait_time_cmp_ge0001_cy_3_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0001_cy(2),
DI => count_us(3),
S => Mcompar_wait_time_cmp_ge0001_lut(3),
O => Mcompar_wait_time_cmp_ge0001_cy(3)
);
Mcompar_wait_time_cmp_ge0001_cy_4_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0001_cy(3),
DI => count_us(4),
S => Mcompar_wait_time_cmp_ge0001_lut(4),
O => Mcompar_wait_time_cmp_ge0001_cy(4)
);
Mcompar_wait_time_cmp_ge0001_lut_5_Q : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => count_us(5),
I1 => databus_add0000(5),
O => Mcompar_wait_time_cmp_ge0001_lut(5)
);
Mcompar_wait_time_cmp_ge0001_cy_5_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0001_cy(4),
DI => count_us(5),
S => Mcompar_wait_time_cmp_ge0001_lut(5),
O => Mcompar_wait_time_cmp_ge0001_cy(5)
);
Mcompar_wait_time_cmp_ge0001_lut_6_Q : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => count_us(6),
I1 => databus_add0000(6),
O => Mcompar_wait_time_cmp_ge0001_lut(6)
);
Mcompar_wait_time_cmp_ge0001_cy_6_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0001_cy(5),
DI => count_us(6),
S => Mcompar_wait_time_cmp_ge0001_lut(6),
O => Mcompar_wait_time_cmp_ge0001_cy(6)
);
Mcompar_wait_time_cmp_ge0001_lut_7_Q : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => count_us(7),
I1 => databus_add0000(7),
O => Mcompar_wait_time_cmp_ge0001_lut(7)
);
Mcompar_wait_time_cmp_ge0001_cy_7_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0001_cy(6),
DI => count_us(7),
S => Mcompar_wait_time_cmp_ge0001_lut(7),
O => Mcompar_wait_time_cmp_ge0001_cy(7)
);
Mcompar_wait_time_cmp_ge0001_lut_8_Q : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => count_us(8),
I1 => databus_add0000(8),
O => Mcompar_wait_time_cmp_ge0001_lut(8)
);
Mcompar_wait_time_cmp_ge0001_cy_8_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0001_cy(7),
DI => count_us(8),
S => Mcompar_wait_time_cmp_ge0001_lut(8),
O => Mcompar_wait_time_cmp_ge0001_cy(8)
);
Mcompar_wait_time_cmp_ge0001_lut_9_Q : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => count_us(9),
I1 => databus_add0000(9),
O => Mcompar_wait_time_cmp_ge0001_lut(9)
);
Mcompar_wait_time_cmp_ge0001_cy_9_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0001_cy(8),
DI => count_us(9),
S => Mcompar_wait_time_cmp_ge0001_lut(9),
O => Mcompar_wait_time_cmp_ge0001_cy(9)
);
Mcompar_wait_time_cmp_ge0001_lut_10_Q : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => count_us(10),
I1 => databus_add0000(10),
O => Mcompar_wait_time_cmp_ge0001_lut(10)
);
Mcompar_wait_time_cmp_ge0001_cy_10_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0001_cy(9),
DI => count_us(10),
S => Mcompar_wait_time_cmp_ge0001_lut(10),
O => Mcompar_wait_time_cmp_ge0001_cy(10)
);
Mcompar_wait_time_cmp_ge0001_lut_11_Q : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => count_us(11),
I1 => databus_add0000(11),
O => Mcompar_wait_time_cmp_ge0001_lut(11)
);
Mcompar_wait_time_cmp_ge0001_cy_11_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0001_cy(10),
DI => count_us(11),
S => Mcompar_wait_time_cmp_ge0001_lut(11),
O => Mcompar_wait_time_cmp_ge0001_cy(11)
);
Mcompar_wait_time_cmp_ge0001_lut_12_Q : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => count_us(12),
I1 => databus_add0000(12),
O => Mcompar_wait_time_cmp_ge0001_lut(12)
);
Mcompar_wait_time_cmp_ge0001_cy_12_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0001_cy(11),
DI => count_us(12),
S => Mcompar_wait_time_cmp_ge0001_lut(12),
O => Mcompar_wait_time_cmp_ge0001_cy(12)
);
Mcompar_wait_time_cmp_ge0001_lut_13_Q : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => count_us(13),
I1 => databus_add0000(13),
O => Mcompar_wait_time_cmp_ge0001_lut(13)
);
Mcompar_wait_time_cmp_ge0001_cy_13_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0001_cy(12),
DI => count_us(13),
S => Mcompar_wait_time_cmp_ge0001_lut(13),
O => Mcompar_wait_time_cmp_ge0001_cy(13)
);
Mcompar_wait_time_cmp_ge0001_lut_14_Q : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => count_us(14),
I1 => databus_add0000(14),
O => Mcompar_wait_time_cmp_ge0001_lut(14)
);
Mcompar_wait_time_cmp_ge0001_cy_14_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0001_cy(13),
DI => count_us(14),
S => Mcompar_wait_time_cmp_ge0001_lut(14),
O => Mcompar_wait_time_cmp_ge0001_cy(14)
);
Mcompar_wait_time_cmp_ge0001_lut_15_Q : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => count_us(15),
I1 => databus_add0000(15),
O => Mcompar_wait_time_cmp_ge0001_lut(15)
);
Mcompar_wait_time_cmp_ge0001_cy_15_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0001_cy(14),
DI => count_us(15),
S => Mcompar_wait_time_cmp_ge0001_lut(15),
O => Mcompar_wait_time_cmp_ge0001_cy(15)
);
Mcompar_wait_time_cmp_ge0001_lut_16_Q : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => count_us(16),
I1 => databus_add0000(16),
O => Mcompar_wait_time_cmp_ge0001_lut(16)
);
Mcompar_wait_time_cmp_ge0001_cy_16_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0001_cy(15),
DI => count_us(16),
S => Mcompar_wait_time_cmp_ge0001_lut(16),
O => Mcompar_wait_time_cmp_ge0001_cy(16)
);
Mcompar_wait_time_cmp_ge0001_lut_17_Q : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => count_us(17),
I1 => databus_add0000(17),
O => Mcompar_wait_time_cmp_ge0001_lut(17)
);
Mcompar_wait_time_cmp_ge0001_cy_17_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0001_cy(16),
DI => count_us(17),
S => Mcompar_wait_time_cmp_ge0001_lut(17),
O => Mcompar_wait_time_cmp_ge0001_cy(17)
);
Mcompar_wait_time_cmp_ge0001_lut_18_Q : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => count_us(18),
I1 => databus_add0000(18),
O => Mcompar_wait_time_cmp_ge0001_lut(18)
);
Mcompar_wait_time_cmp_ge0001_cy_18_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0001_cy(17),
DI => count_us(18),
S => Mcompar_wait_time_cmp_ge0001_lut(18),
O => Mcompar_wait_time_cmp_ge0001_cy(18)
);
Mcompar_wait_time_cmp_ge0001_lut_19_Q : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => count_us(19),
I1 => databus_add0000(19),
O => Mcompar_wait_time_cmp_ge0001_lut(19)
);
Mcompar_wait_time_cmp_ge0001_cy_19_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0001_cy(18),
DI => count_us(19),
S => Mcompar_wait_time_cmp_ge0001_lut(19),
O => Mcompar_wait_time_cmp_ge0001_cy(19)
);
Mcompar_wait_time_cmp_ge0001_lut_20_Q : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => count_us(20),
I1 => databus_add0000(20),
O => Mcompar_wait_time_cmp_ge0001_lut(20)
);
Mcompar_wait_time_cmp_ge0001_cy_20_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0001_cy(19),
DI => count_us(20),
S => Mcompar_wait_time_cmp_ge0001_lut(20),
O => Mcompar_wait_time_cmp_ge0001_cy(20)
);
Mcompar_wait_time_cmp_ge0001_lut_21_Q : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => count_us(21),
I1 => databus_add0000(21),
O => Mcompar_wait_time_cmp_ge0001_lut(21)
);
Mcompar_wait_time_cmp_ge0001_cy_21_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0001_cy(20),
DI => count_us(21),
S => Mcompar_wait_time_cmp_ge0001_lut(21),
O => Mcompar_wait_time_cmp_ge0001_cy(21)
);
Mcompar_wait_time_cmp_ge0001_lut_22_Q : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => count_us(22),
I1 => databus_add0000(22),
O => Mcompar_wait_time_cmp_ge0001_lut(22)
);
Mcompar_wait_time_cmp_ge0001_cy_22_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0001_cy(21),
DI => count_us(22),
S => Mcompar_wait_time_cmp_ge0001_lut(22),
O => Mcompar_wait_time_cmp_ge0001_cy(22)
);
Mcompar_wait_time_cmp_ge0001_lut_23_Q : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => count_us(23),
I1 => databus_add0000(23),
O => Mcompar_wait_time_cmp_ge0001_lut(23)
);
Mcompar_wait_time_cmp_ge0001_cy_23_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0001_cy(22),
DI => count_us(23),
S => Mcompar_wait_time_cmp_ge0001_lut(23),
O => Mcompar_wait_time_cmp_ge0001_cy(23)
);
Mcompar_wait_time_cmp_ge0001_lut_24_Q : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => count_us(24),
I1 => databus_add0000(24),
O => Mcompar_wait_time_cmp_ge0001_lut(24)
);
Mcompar_wait_time_cmp_ge0001_cy_24_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0001_cy(23),
DI => count_us(24),
S => Mcompar_wait_time_cmp_ge0001_lut(24),
O => Mcompar_wait_time_cmp_ge0001_cy(24)
);
Mcompar_wait_time_cmp_ge0001_lut_25_Q : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => count_us(25),
I1 => databus_add0000(25),
O => Mcompar_wait_time_cmp_ge0001_lut(25)
);
Mcompar_wait_time_cmp_ge0001_cy_25_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0001_cy(24),
DI => count_us(25),
S => Mcompar_wait_time_cmp_ge0001_lut(25),
O => Mcompar_wait_time_cmp_ge0001_cy(25)
);
Mcompar_wait_time_cmp_ge0001_lut_26_Q : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => count_us(26),
I1 => databus_add0000(26),
O => Mcompar_wait_time_cmp_ge0001_lut(26)
);
Mcompar_wait_time_cmp_ge0001_cy_26_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0001_cy(25),
DI => count_us(26),
S => Mcompar_wait_time_cmp_ge0001_lut(26),
O => Mcompar_wait_time_cmp_ge0001_cy(26)
);
Mcompar_wait_time_cmp_ge0001_lut_27_Q : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => count_us(27),
I1 => databus_add0000(27),
O => Mcompar_wait_time_cmp_ge0001_lut(27)
);
Mcompar_wait_time_cmp_ge0001_cy_27_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0001_cy(26),
DI => count_us(27),
S => Mcompar_wait_time_cmp_ge0001_lut(27),
O => Mcompar_wait_time_cmp_ge0001_cy(27)
);
Mcompar_wait_time_cmp_ge0001_lut_28_Q : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => count_us(28),
I1 => databus_add0000(28),
O => Mcompar_wait_time_cmp_ge0001_lut(28)
);
Mcompar_wait_time_cmp_ge0001_cy_28_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0001_cy(27),
DI => count_us(28),
S => Mcompar_wait_time_cmp_ge0001_lut(28),
O => Mcompar_wait_time_cmp_ge0001_cy(28)
);
Mcompar_wait_time_cmp_ge0001_lut_29_Q : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => count_us(29),
I1 => databus_add0000(29),
O => Mcompar_wait_time_cmp_ge0001_lut(29)
);
Mcompar_wait_time_cmp_ge0001_cy_29_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0001_cy(28),
DI => count_us(29),
S => Mcompar_wait_time_cmp_ge0001_lut(29),
O => Mcompar_wait_time_cmp_ge0001_cy(29)
);
Mcompar_wait_time_cmp_ge0001_lut_30_Q : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => count_us(30),
I1 => databus_add0000(30),
O => Mcompar_wait_time_cmp_ge0001_lut(30)
);
Mcompar_wait_time_cmp_ge0001_cy_30_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0001_cy(29),
DI => count_us(30),
S => Mcompar_wait_time_cmp_ge0001_lut(30),
O => Mcompar_wait_time_cmp_ge0001_cy(30)
);
Mcompar_wait_time_cmp_ge0001_lut_31_Q : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => count_us(31),
I1 => databus_add0000(31),
O => Mcompar_wait_time_cmp_ge0001_lut(31)
);
Mcompar_wait_time_cmp_ge0001_cy_31_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_ge0001_cy(30),
DI => databus_add0000(31),
S => Mcompar_wait_time_cmp_ge0001_lut(31),
O => wait_time_cmp_ge0001
);
Mcompar_wait_time_cmp_eq0000_lut_0_Q : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => count_us(0),
I1 => Mrom_databus_mux000512,
I2 => count_us(1),
I3 => wait_time(1),
O => Mcompar_wait_time_cmp_eq0000_lut(0)
);
Mcompar_wait_time_cmp_eq0000_cy_0_Q : MUXCY
port map (
CI => Mrom_databus_mux0005,
DI => Mrom_databus_mux000512,
S => Mcompar_wait_time_cmp_eq0000_lut(0),
O => Mcompar_wait_time_cmp_eq0000_cy(0)
);
Mcompar_wait_time_cmp_eq0000_lut_1_Q : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => count_us(2),
I1 => wait_time(2),
I2 => count_us(3),
I3 => wait_time(3),
O => Mcompar_wait_time_cmp_eq0000_lut(1)
);
Mcompar_wait_time_cmp_eq0000_cy_1_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_eq0000_cy(0),
DI => Mrom_databus_mux000512,
S => Mcompar_wait_time_cmp_eq0000_lut(1),
O => Mcompar_wait_time_cmp_eq0000_cy(1)
);
Mcompar_wait_time_cmp_eq0000_cy_2_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_eq0000_cy(1),
DI => Mrom_databus_mux000512,
S => Mcompar_wait_time_cmp_eq0000_lut(2),
O => Mcompar_wait_time_cmp_eq0000_cy(2)
);
Mcompar_wait_time_cmp_eq0000_lut_3_Q : LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => count_us(7),
I1 => count_us(6),
I2 => databus_add0000(6),
I3 => databus_add0000(7),
O => Mcompar_wait_time_cmp_eq0000_lut(3)
);
Mcompar_wait_time_cmp_eq0000_cy_3_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_eq0000_cy(2),
DI => Mrom_databus_mux000512,
S => Mcompar_wait_time_cmp_eq0000_lut(3),
O => Mcompar_wait_time_cmp_eq0000_cy(3)
);
Mcompar_wait_time_cmp_eq0000_lut_4_Q : LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => count_us(9),
I1 => count_us(8),
I2 => databus_add0000(8),
I3 => databus_add0000(9),
O => Mcompar_wait_time_cmp_eq0000_lut(4)
);
Mcompar_wait_time_cmp_eq0000_cy_4_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_eq0000_cy(3),
DI => Mrom_databus_mux000512,
S => Mcompar_wait_time_cmp_eq0000_lut(4),
O => Mcompar_wait_time_cmp_eq0000_cy(4)
);
Mcompar_wait_time_cmp_eq0000_lut_5_Q : LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => count_us(11),
I1 => count_us(10),
I2 => databus_add0000(10),
I3 => databus_add0000(11),
O => Mcompar_wait_time_cmp_eq0000_lut(5)
);
Mcompar_wait_time_cmp_eq0000_cy_5_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_eq0000_cy(4),
DI => Mrom_databus_mux000512,
S => Mcompar_wait_time_cmp_eq0000_lut(5),
O => Mcompar_wait_time_cmp_eq0000_cy(5)
);
Mcompar_wait_time_cmp_eq0000_lut_6_Q : LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => count_us(13),
I1 => count_us(12),
I2 => databus_add0000(12),
I3 => databus_add0000(13),
O => Mcompar_wait_time_cmp_eq0000_lut(6)
);
Mcompar_wait_time_cmp_eq0000_cy_6_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_eq0000_cy(5),
DI => Mrom_databus_mux000512,
S => Mcompar_wait_time_cmp_eq0000_lut(6),
O => Mcompar_wait_time_cmp_eq0000_cy(6)
);
Mcompar_wait_time_cmp_eq0000_lut_7_Q : LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => count_us(15),
I1 => count_us(14),
I2 => databus_add0000(14),
I3 => databus_add0000(15),
O => Mcompar_wait_time_cmp_eq0000_lut(7)
);
Mcompar_wait_time_cmp_eq0000_cy_7_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_eq0000_cy(6),
DI => Mrom_databus_mux000512,
S => Mcompar_wait_time_cmp_eq0000_lut(7),
O => Mcompar_wait_time_cmp_eq0000_cy(7)
);
Mcompar_wait_time_cmp_eq0000_lut_8_Q : LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => count_us(17),
I1 => count_us(16),
I2 => databus_add0000(16),
I3 => databus_add0000(17),
O => Mcompar_wait_time_cmp_eq0000_lut(8)
);
Mcompar_wait_time_cmp_eq0000_cy_8_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_eq0000_cy(7),
DI => Mrom_databus_mux000512,
S => Mcompar_wait_time_cmp_eq0000_lut(8),
O => Mcompar_wait_time_cmp_eq0000_cy(8)
);
Mcompar_wait_time_cmp_eq0000_lut_9_Q : LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => count_us(19),
I1 => count_us(18),
I2 => databus_add0000(18),
I3 => databus_add0000(19),
O => Mcompar_wait_time_cmp_eq0000_lut(9)
);
Mcompar_wait_time_cmp_eq0000_cy_9_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_eq0000_cy(8),
DI => Mrom_databus_mux000512,
S => Mcompar_wait_time_cmp_eq0000_lut(9),
O => Mcompar_wait_time_cmp_eq0000_cy(9)
);
Mcompar_wait_time_cmp_eq0000_lut_10_Q : LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => count_us(21),
I1 => count_us(20),
I2 => databus_add0000(20),
I3 => databus_add0000(21),
O => Mcompar_wait_time_cmp_eq0000_lut(10)
);
Mcompar_wait_time_cmp_eq0000_cy_10_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_eq0000_cy(9),
DI => Mrom_databus_mux000512,
S => Mcompar_wait_time_cmp_eq0000_lut(10),
O => Mcompar_wait_time_cmp_eq0000_cy(10)
);
Mcompar_wait_time_cmp_eq0000_lut_11_Q : LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => count_us(23),
I1 => count_us(22),
I2 => databus_add0000(22),
I3 => databus_add0000(23),
O => Mcompar_wait_time_cmp_eq0000_lut(11)
);
Mcompar_wait_time_cmp_eq0000_cy_11_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_eq0000_cy(10),
DI => Mrom_databus_mux000512,
S => Mcompar_wait_time_cmp_eq0000_lut(11),
O => Mcompar_wait_time_cmp_eq0000_cy(11)
);
Mcompar_wait_time_cmp_eq0000_lut_12_Q : LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => count_us(25),
I1 => count_us(24),
I2 => databus_add0000(24),
I3 => databus_add0000(25),
O => Mcompar_wait_time_cmp_eq0000_lut(12)
);
Mcompar_wait_time_cmp_eq0000_cy_12_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_eq0000_cy(11),
DI => Mrom_databus_mux000512,
S => Mcompar_wait_time_cmp_eq0000_lut(12),
O => Mcompar_wait_time_cmp_eq0000_cy(12)
);
Mcompar_wait_time_cmp_eq0000_lut_13_Q : LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => count_us(27),
I1 => count_us(26),
I2 => databus_add0000(26),
I3 => databus_add0000(27),
O => Mcompar_wait_time_cmp_eq0000_lut(13)
);
Mcompar_wait_time_cmp_eq0000_cy_13_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_eq0000_cy(12),
DI => Mrom_databus_mux000512,
S => Mcompar_wait_time_cmp_eq0000_lut(13),
O => Mcompar_wait_time_cmp_eq0000_cy(13)
);
Mcompar_wait_time_cmp_eq0000_lut_14_Q : LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => count_us(29),
I1 => count_us(28),
I2 => databus_add0000(28),
I3 => databus_add0000(29),
O => Mcompar_wait_time_cmp_eq0000_lut(14)
);
Mcompar_wait_time_cmp_eq0000_cy_14_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_eq0000_cy(13),
DI => Mrom_databus_mux000512,
S => Mcompar_wait_time_cmp_eq0000_lut(14),
O => Mcompar_wait_time_cmp_eq0000_cy(14)
);
Mcompar_wait_time_cmp_eq0000_lut_15_Q : LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => count_us(31),
I1 => count_us(30),
I2 => databus_add0000(30),
I3 => databus_add0000(31),
O => Mcompar_wait_time_cmp_eq0000_lut(15)
);
Mcompar_wait_time_cmp_eq0000_cy_15_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_eq0000_cy(14),
DI => Mrom_databus_mux000512,
S => Mcompar_wait_time_cmp_eq0000_lut(15),
O => Mcompar_wait_time_cmp_eq0000_cy(15)
);
Mcompar_wait_time_cmp_lt0000_lut_0_Q : LUT2
generic map(
INIT => X"8"
)
port map (
I0 => index(2),
I1 => index(3),
O => Mcompar_wait_time_cmp_lt0000_lut(0)
);
Mcompar_wait_time_cmp_lt0000_cy_0_Q : MUXCY
port map (
CI => Mrom_databus_mux0005,
DI => Mrom_databus_mux000512,
S => Mcompar_wait_time_cmp_lt0000_lut(0),
O => Mcompar_wait_time_cmp_lt0000_cy(0)
);
Mcompar_wait_time_cmp_lt0000_lut_1_Q : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => index(4),
I1 => index(5),
I2 => index(6),
I3 => index(7),
O => Mcompar_wait_time_cmp_lt0000_lut(1)
);
Mcompar_wait_time_cmp_lt0000_cy_1_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_lt0000_cy(0),
DI => Mrom_databus_mux0005,
S => Mcompar_wait_time_cmp_lt0000_lut(1),
O => Mcompar_wait_time_cmp_lt0000_cy(1)
);
Mcompar_wait_time_cmp_lt0000_lut_2_Q : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => index(8),
I1 => index(9),
I2 => index(10),
I3 => index(11),
O => Mcompar_wait_time_cmp_lt0000_lut(2)
);
Mcompar_wait_time_cmp_lt0000_cy_2_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_lt0000_cy(1),
DI => Mrom_databus_mux0005,
S => Mcompar_wait_time_cmp_lt0000_lut(2),
O => Mcompar_wait_time_cmp_lt0000_cy(2)
);
Mcompar_wait_time_cmp_lt0000_lut_3_Q : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => index(12),
I1 => index(13),
I2 => index(14),
I3 => index(15),
O => Mcompar_wait_time_cmp_lt0000_lut(3)
);
Mcompar_wait_time_cmp_lt0000_cy_3_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_lt0000_cy(2),
DI => Mrom_databus_mux0005,
S => Mcompar_wait_time_cmp_lt0000_lut(3),
O => Mcompar_wait_time_cmp_lt0000_cy(3)
);
Mcompar_wait_time_cmp_lt0000_lut_4_Q : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => index(16),
I1 => index(17),
I2 => index(18),
I3 => index(19),
O => Mcompar_wait_time_cmp_lt0000_lut(4)
);
Mcompar_wait_time_cmp_lt0000_cy_4_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_lt0000_cy(3),
DI => Mrom_databus_mux0005,
S => Mcompar_wait_time_cmp_lt0000_lut(4),
O => Mcompar_wait_time_cmp_lt0000_cy(4)
);
Mcompar_wait_time_cmp_lt0000_lut_5_Q : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => index(20),
I1 => index(21),
I2 => index(22),
I3 => index(23),
O => Mcompar_wait_time_cmp_lt0000_lut(5)
);
Mcompar_wait_time_cmp_lt0000_cy_5_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_lt0000_cy(4),
DI => Mrom_databus_mux0005,
S => Mcompar_wait_time_cmp_lt0000_lut(5),
O => Mcompar_wait_time_cmp_lt0000_cy(5)
);
Mcompar_wait_time_cmp_lt0000_lut_6_Q : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => index(24),
I1 => index(25),
I2 => index(26),
I3 => index(27),
O => Mcompar_wait_time_cmp_lt0000_lut(6)
);
Mcompar_wait_time_cmp_lt0000_cy_6_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_lt0000_cy(5),
DI => Mrom_databus_mux0005,
S => Mcompar_wait_time_cmp_lt0000_lut(6),
O => Mcompar_wait_time_cmp_lt0000_cy(6)
);
Mcompar_wait_time_cmp_lt0000_lut_7_Q : LUT3
generic map(
INIT => X"01"
)
port map (
I0 => index(28),
I1 => index(29),
I2 => index(30),
O => Mcompar_wait_time_cmp_lt0000_lut(7)
);
Mcompar_wait_time_cmp_lt0000_cy_7_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_lt0000_cy(6),
DI => Mrom_databus_mux0005,
S => Mcompar_wait_time_cmp_lt0000_lut(7),
O => Mcompar_wait_time_cmp_lt0000_cy(7)
);
Mcompar_wait_time_cmp_lt0000_cy_8_Q : MUXCY
port map (
CI => Mcompar_wait_time_cmp_lt0000_cy(7),
DI => Mrom_databus_mux000512,
S => Mcompar_wait_time_cmp_lt0000_lut(8),
O => Mcompar_wait_time_cmp_lt0000_cy(8)
);
BUFG_BufSysCLK : BUFG
port map (
I => SysCLK_IBUFG_741,
O => Buf_SysCLK
);
BUFG_BufCLK1MHz : BUFG
port map (
I => G1_CLK1MHz_4,
O => Buf_CLK1MHz
);
BUFG_BufE : BUFG
port map (
I => Unbuf_E_742,
O => E_OBUF_3
);
index_0 : LDE
generic map(
INIT => '1'
)
port map (
D => index_mux0003(0),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => index(0)
);
index_1 : LDE
generic map(
INIT => '0'
)
port map (
D => index_mux0003(1),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => index(1)
);
index_2 : LDE
generic map(
INIT => '0'
)
port map (
D => index_mux0003(2),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => index(2)
);
index_3 : LDE
generic map(
INIT => '0'
)
port map (
D => index_mux0003(3),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => index(3)
);
index_4 : LDE
generic map(
INIT => '0'
)
port map (
D => index_mux0003(4),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => index(4)
);
index_5 : LDE
generic map(
INIT => '0'
)
port map (
D => index_mux0003(5),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => index(5)
);
index_6 : LDE
generic map(
INIT => '0'
)
port map (
D => index_mux0003(6),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => index(6)
);
index_7 : LDE
generic map(
INIT => '0'
)
port map (
D => index_mux0003(7),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => index(7)
);
index_8 : LDE
generic map(
INIT => '0'
)
port map (
D => index_mux0003(8),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => index(8)
);
index_9 : LDE
generic map(
INIT => '0'
)
port map (
D => index_mux0003(9),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => index(9)
);
index_10 : LDE
generic map(
INIT => '0'
)
port map (
D => index_mux0003(10),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => index(10)
);
index_11 : LDE
generic map(
INIT => '0'
)
port map (
D => index_mux0003(11),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => index(11)
);
index_12 : LDE
generic map(
INIT => '0'
)
port map (
D => index_mux0003(12),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => index(12)
);
index_13 : LDE
generic map(
INIT => '0'
)
port map (
D => index_mux0003(13),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => index(13)
);
index_14 : LDE
generic map(
INIT => '0'
)
port map (
D => index_mux0003(14),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => index(14)
);
index_15 : LDE
generic map(
INIT => '0'
)
port map (
D => index_mux0003(15),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => index(15)
);
index_16 : LDE
generic map(
INIT => '0'
)
port map (
D => index_mux0003(16),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => index(16)
);
index_17 : LDE
generic map(
INIT => '0'
)
port map (
D => index_mux0003(17),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => index(17)
);
index_18 : LDE
generic map(
INIT => '0'
)
port map (
D => index_mux0003(18),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => index(18)
);
index_19 : LDE
generic map(
INIT => '0'
)
port map (
D => index_mux0003(19),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => index(19)
);
index_20 : LDE
generic map(
INIT => '0'
)
port map (
D => index_mux0003(20),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => index(20)
);
index_21 : LDE
generic map(
INIT => '0'
)
port map (
D => index_mux0003(21),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => index(21)
);
index_22 : LDE
generic map(
INIT => '0'
)
port map (
D => index_mux0003(22),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => index(22)
);
index_23 : LDE
generic map(
INIT => '0'
)
port map (
D => index_mux0003(23),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => index(23)
);
index_24 : LDE
generic map(
INIT => '0'
)
port map (
D => index_mux0003(24),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => index(24)
);
index_25 : LDE
generic map(
INIT => '0'
)
port map (
D => index_mux0003(25),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => index(25)
);
index_26 : LDE
generic map(
INIT => '0'
)
port map (
D => index_mux0003(26),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => index(26)
);
index_27 : LDE
generic map(
INIT => '0'
)
port map (
D => index_mux0003(27),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => index(27)
);
index_28 : LDE
generic map(
INIT => '0'
)
port map (
D => index_mux0003(28),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => index(28)
);
index_29 : LDE
generic map(
INIT => '0'
)
port map (
D => index_mux0003(29),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => index(29)
);
index_30 : LDE
generic map(
INIT => '0'
)
port map (
D => index_mux0003(30),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => index(30)
);
index_31 : LDE
generic map(
INIT => '0'
)
port map (
D => index_mux0003(31),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => index(31)
);
wait_time_1 : LDE
generic map(
INIT => '1'
)
port map (
D => wait_time_mux0003(1),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => wait_time(1)
);
wait_time_2 : LDE
generic map(
INIT => '0'
)
port map (
D => wait_time_mux0003(2),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => wait_time(2)
);
wait_time_3 : LDE
generic map(
INIT => '0'
)
port map (
D => wait_time_mux0003(3),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => wait_time(3)
);
wait_time_4 : LDE
generic map(
INIT => '1'
)
port map (
D => wait_time_mux0003(4),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => wait_time(4)
);
wait_time_5 : LDE
generic map(
INIT => '1'
)
port map (
D => wait_time_mux0003(5),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => wait_time(5)
);
wait_time_6 : LDE
generic map(
INIT => '0'
)
port map (
D => wait_time_mux0003(6),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => wait_time(6)
);
wait_time_7 : LDE
generic map(
INIT => '0'
)
port map (
D => wait_time_mux0003(7),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => wait_time(7)
);
wait_time_8 : LDE
generic map(
INIT => '0'
)
port map (
D => wait_time_mux0003(8),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => wait_time(8)
);
wait_time_9 : LDE
generic map(
INIT => '0'
)
port map (
D => wait_time_mux0003(9),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => wait_time(9)
);
wait_time_10 : LDE
generic map(
INIT => '0'
)
port map (
D => wait_time_mux0003(10),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => wait_time(10)
);
wait_time_11 : LDE
generic map(
INIT => '0'
)
port map (
D => wait_time_mux0003(11),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => wait_time(11)
);
wait_time_12 : LDE
generic map(
INIT => '0'
)
port map (
D => wait_time_mux0003(12),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => wait_time(12)
);
wait_time_13 : LDE
generic map(
INIT => '0'
)
port map (
D => wait_time_mux0003(13),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => wait_time(13)
);
wait_time_14 : LDE
generic map(
INIT => '0'
)
port map (
D => wait_time_mux0003(14),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => wait_time(14)
);
wait_time_15 : LDE
generic map(
INIT => '0'
)
port map (
D => wait_time_mux0003(15),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => wait_time(15)
);
wait_time_16 : LDE
generic map(
INIT => '0'
)
port map (
D => wait_time_mux0003(16),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => wait_time(16)
);
wait_time_17 : LDE
generic map(
INIT => '0'
)
port map (
D => wait_time_mux0003(17),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => wait_time(17)
);
wait_time_18 : LDE
generic map(
INIT => '0'
)
port map (
D => wait_time_mux0003(18),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => wait_time(18)
);
wait_time_19 : LDE
generic map(
INIT => '0'
)
port map (
D => wait_time_mux0003(19),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => wait_time(19)
);
wait_time_20 : LDE
generic map(
INIT => '0'
)
port map (
D => wait_time_mux0003(20),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => wait_time(20)
);
wait_time_21 : LDE
generic map(
INIT => '0'
)
port map (
D => wait_time_mux0003(21),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => wait_time(21)
);
wait_time_22 : LDE
generic map(
INIT => '0'
)
port map (
D => wait_time_mux0003(22),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => wait_time(22)
);
wait_time_23 : LDE
generic map(
INIT => '0'
)
port map (
D => wait_time_mux0003(23),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => wait_time(23)
);
wait_time_24 : LDE
generic map(
INIT => '0'
)
port map (
D => wait_time_mux0003(24),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => wait_time(24)
);
wait_time_25 : LDE
generic map(
INIT => '0'
)
port map (
D => wait_time_mux0003(25),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => wait_time(25)
);
wait_time_26 : LDE
generic map(
INIT => '0'
)
port map (
D => wait_time_mux0003(26),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => wait_time(26)
);
wait_time_27 : LDE
generic map(
INIT => '0'
)
port map (
D => wait_time_mux0003(27),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => wait_time(27)
);
wait_time_28 : LDE
generic map(
INIT => '0'
)
port map (
D => wait_time_mux0003(28),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => wait_time(28)
);
wait_time_29 : LDE
generic map(
INIT => '0'
)
port map (
D => wait_time_mux0003(29),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => wait_time(29)
);
wait_time_30 : LDE
generic map(
INIT => '0'
)
port map (
D => wait_time_mux0003(30),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => wait_time(30)
);
wait_time_31 : LDE
generic map(
INIT => '0'
)
port map (
D => wait_time_mux0003(31),
G => wait_time_cmp_ge0000,
GE => wait_time_cmp_lt0000,
Q => wait_time(31)
);
Unbuf_E_mux00092_wg_lut_0_Q : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => count_us(19),
I1 => count_us(23),
O => Unbuf_E_mux00092_wg_lut(0)
);
Unbuf_E_mux00092_wg_cy_0_Q : MUXCY
port map (
CI => Mrom_databus_mux000512,
DI => Mrom_databus_mux0005,
S => Unbuf_E_mux00092_wg_lut(0),
O => Unbuf_E_mux00092_wg_cy(0)
);
Unbuf_E_mux00092_wg_lut_1_Q : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => count_us(21),
I1 => count_us(22),
I2 => count_us(18),
I3 => count_us(26),
O => Unbuf_E_mux00092_wg_lut(1)
);
Unbuf_E_mux00092_wg_cy_1_Q : MUXCY
port map (
CI => Unbuf_E_mux00092_wg_cy(0),
DI => Mrom_databus_mux0005,
S => Unbuf_E_mux00092_wg_lut(1),
O => Unbuf_E_mux00092_wg_cy(1)
);
Unbuf_E_mux00092_wg_lut_2_Q : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => count_us(24),
I1 => count_us(25),
I2 => count_us(20),
I3 => count_us(27),
O => Unbuf_E_mux00092_wg_lut(2)
);
Unbuf_E_mux00092_wg_cy_2_Q : MUXCY
port map (
CI => Unbuf_E_mux00092_wg_cy(1),
DI => Mrom_databus_mux0005,
S => Unbuf_E_mux00092_wg_lut(2),
O => Unbuf_E_mux00092_wg_cy(2)
);
Unbuf_E_mux00092_wg_lut_3_Q : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => count_us(28),
I1 => count_us(29),
I2 => count_us(17),
I3 => count_us(30),
O => Unbuf_E_mux00092_wg_lut(3)
);
Unbuf_E_mux00092_wg_cy_3_Q : MUXCY
port map (
CI => Unbuf_E_mux00092_wg_cy(2),
DI => Mrom_databus_mux0005,
S => Unbuf_E_mux00092_wg_lut(3),
O => Unbuf_E_mux00092_wg_cy(3)
);
Unbuf_E_mux00092_wg_lut_4_Q : LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => count_us(11),
I1 => count_us(31),
I2 => count_us(16),
I3 => count_us(10),
O => Unbuf_E_mux00092_wg_lut(4)
);
Unbuf_E_mux00092_wg_cy_4_Q : MUXCY
port map (
CI => Unbuf_E_mux00092_wg_cy(3),
DI => Mrom_databus_mux0005,
S => Unbuf_E_mux00092_wg_lut(4),
O => Unbuf_E_mux00092_wg_cy(4)
);
Unbuf_E_mux00092_wg_lut_5_Q : LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => count_us(4),
I1 => count_us(14),
I2 => count_us(15),
I3 => count_us(1),
O => Unbuf_E_mux00092_wg_lut(5)
);
Unbuf_E_mux00092_wg_cy_5_Q : MUXCY
port map (
CI => Unbuf_E_mux00092_wg_cy(4),
DI => Mrom_databus_mux0005,
S => Unbuf_E_mux00092_wg_lut(5),
O => Unbuf_E_mux00092_wg_cy(5)
);
Unbuf_E_mux00092_wg_lut_6_Q : LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => count_us(12),
I1 => count_us(9),
I2 => count_us(13),
I3 => count_us(0),
O => Unbuf_E_mux00092_wg_lut(6)
);
Unbuf_E_mux00092_wg_cy_6_Q : MUXCY
port map (
CI => Unbuf_E_mux00092_wg_cy(5),
DI => Mrom_databus_mux0005,
S => Unbuf_E_mux00092_wg_lut(6),
O => N41
);
G1_CLK1MHz_cmp_eq00001_wg_lut_0_Q : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => G1_cnt_add0000(22),
I1 => G1_cnt_add0000(23),
I2 => G1_cnt_add0000(24),
I3 => G1_cnt_add0000(25),
O => G1_CLK1MHz_cmp_eq00001_wg_lut(0)
);
G1_CLK1MHz_cmp_eq00001_wg_cy_0_Q : MUXCY
port map (
CI => Mrom_databus_mux0005,
DI => Mrom_databus_mux000512,
S => G1_CLK1MHz_cmp_eq00001_wg_lut(0),
O => G1_CLK1MHz_cmp_eq00001_wg_cy(0)
);
G1_CLK1MHz_cmp_eq00001_wg_lut_1_Q : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => G1_cnt_add0000(19),
I1 => G1_cnt_add0000(20),
I2 => G1_cnt_add0000(21),
I3 => G1_cnt_add0000(26),
O => G1_CLK1MHz_cmp_eq00001_wg_lut(1)
);
G1_CLK1MHz_cmp_eq00001_wg_cy_1_Q : MUXCY
port map (
CI => G1_CLK1MHz_cmp_eq00001_wg_cy(0),
DI => Mrom_databus_mux000512,
S => G1_CLK1MHz_cmp_eq00001_wg_lut(1),
O => G1_CLK1MHz_cmp_eq00001_wg_cy(1)
);
G1_CLK1MHz_cmp_eq00001_wg_lut_2_Q : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => G1_cnt_add0000(16),
I1 => G1_cnt_add0000(17),
I2 => G1_cnt_add0000(18),
I3 => G1_cnt_add0000(27),
O => G1_CLK1MHz_cmp_eq00001_wg_lut(2)
);
G1_CLK1MHz_cmp_eq00001_wg_cy_2_Q : MUXCY
port map (
CI => G1_CLK1MHz_cmp_eq00001_wg_cy(1),
DI => Mrom_databus_mux000512,
S => G1_CLK1MHz_cmp_eq00001_wg_lut(2),
O => G1_CLK1MHz_cmp_eq00001_wg_cy(2)
);
G1_CLK1MHz_cmp_eq00001_wg_lut_3_Q : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => G1_cnt_add0000(13),
I1 => G1_cnt_add0000(14),
I2 => G1_cnt_add0000(15),
I3 => G1_cnt_add0000(28),
O => G1_CLK1MHz_cmp_eq00001_wg_lut(3)
);
G1_CLK1MHz_cmp_eq00001_wg_cy_3_Q : MUXCY
port map (
CI => G1_CLK1MHz_cmp_eq00001_wg_cy(2),
DI => Mrom_databus_mux000512,
S => G1_CLK1MHz_cmp_eq00001_wg_lut(3),
O => G1_CLK1MHz_cmp_eq00001_wg_cy(3)
);
G1_CLK1MHz_cmp_eq00001_wg_lut_4_Q : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => G1_cnt_add0000(10),
I1 => G1_cnt_add0000(11),
I2 => G1_cnt_add0000(12),
I3 => G1_cnt_add0000(29),
O => G1_CLK1MHz_cmp_eq00001_wg_lut(4)
);
G1_CLK1MHz_cmp_eq00001_wg_cy_4_Q : MUXCY
port map (
CI => G1_CLK1MHz_cmp_eq00001_wg_cy(3),
DI => Mrom_databus_mux000512,
S => G1_CLK1MHz_cmp_eq00001_wg_lut(4),
O => G1_CLK1MHz_cmp_eq00001_wg_cy(4)
);
G1_CLK1MHz_cmp_eq00001_wg_lut_5_Q : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => G1_cnt_add0000(7),
I1 => G1_cnt_add0000(8),
I2 => G1_cnt_add0000(9),
I3 => G1_cnt_add0000(30),
O => G1_CLK1MHz_cmp_eq00001_wg_lut(5)
);
G1_CLK1MHz_cmp_eq00001_wg_cy_5_Q : MUXCY
port map (
CI => G1_CLK1MHz_cmp_eq00001_wg_cy(4),
DI => Mrom_databus_mux000512,
S => G1_CLK1MHz_cmp_eq00001_wg_lut(5),
O => G1_CLK1MHz_cmp_eq00001_wg_cy(5)
);
G1_CLK1MHz_cmp_eq00001_wg_lut_6_Q : LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => G1_cnt_add0000(2),
I1 => G1_cnt_add0000(4),
I2 => G1_cnt_add0000(6),
I3 => G1_cnt_add0000(31),
O => G1_CLK1MHz_cmp_eq00001_wg_lut(6)
);
G1_CLK1MHz_cmp_eq00001_wg_cy_6_Q : MUXCY
port map (
CI => G1_CLK1MHz_cmp_eq00001_wg_cy(5),
DI => Mrom_databus_mux000512,
S => G1_CLK1MHz_cmp_eq00001_wg_lut(6),
O => G1_CLK1MHz_cmp_eq00001_wg_cy(6)
);
databus_mux0006_3_11 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => wait_time_cmp_ge00001,
I1 => databus_cmp_ge0000,
O => N25
);
Unbuf_E_mux0009321 : LUT2
generic map(
INIT => X"E"
)
port map (
I0 => databus_cmp_ge0001,
I1 => databus_cmp_ge0002,
O => N81
);
databus_not00011 : LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => databus_cmp_ge0000,
I1 => wait_time_cmp_ge00001,
I2 => databus_cmp_ge0002,
I3 => databus_cmp_ge0001,
O => databus_not0001
);
databus_mux0006_5_SW0 : LUT3
generic map(
INIT => X"F6"
)
port map (
I0 => index(1),
I1 => index(2),
I2 => index(3),
O => N4
);
databus_mux0006_5_Q : LUT4
generic map(
INIT => X"FF8A"
)
port map (
I0 => RS_mux0005,
I1 => N4,
I2 => index(0),
I3 => N23,
O => databus_mux0006(5)
);
databus_mux0006_3_39 : LUT4
generic map(
INIT => X"141E"
)
port map (
I0 => index(2),
I1 => index(0),
I2 => index(3),
I3 => index(1),
O => databus_mux0006_3_39_848
);
databus_mux0006_3_55 : LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => N25,
I1 => N81,
I2 => RS_mux0005,
I3 => databus_mux0006_3_39_848,
O => databus_mux0006(3)
);
databus_mux0006_1_27 : LUT4
generic map(
INIT => X"BA91"
)
port map (
I0 => index(2),
I1 => index(1),
I2 => index(3),
I3 => index(0),
O => databus_mux0006_1_27_844
);
databus_mux0006_1_40 : LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => databus_cmp_ge0001,
I1 => N25,
I2 => RS_mux0005,
I3 => databus_mux0006_1_27_844,
O => databus_mux0006(1)
);
databus_mux0006_2_50 : LUT4
generic map(
INIT => X"0DBA"
)
port map (
I0 => index(1),
I1 => index(0),
I2 => index(3),
I3 => index(2),
O => databus_mux0006_2_50_846
);
databus_mux0006_2_68 : LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => databus_cmp_ge0001,
I1 => N25,
I2 => RS_mux0005,
I3 => databus_mux0006_2_50_846,
O => databus_mux0006(2)
);
Unbuf_E_mux000919 : LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => count_us(7),
I1 => count_us(5),
I2 => count_us(2),
O => Unbuf_E_mux000919_745
);
Unbuf_E_mux000968 : LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => databus_cmp_ge0000,
I1 => databus_cmp_ge0002,
I2 => databus_cmp_ge0001,
O => Unbuf_E_mux000968_760
);
Unbuf_E_mux000971 : LUT4
generic map(
INIT => X"CCC8"
)
port map (
I0 => count_us(7),
I1 => Unbuf_E_mux000968_760,
I2 => count_us(5),
I3 => count_us(2),
O => Unbuf_E_mux000971_761
);
G1_CLK1MHz_cmp_eq0000 : LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => G1_cnt_add0000(3),
I1 => G1_cnt_add0000(5),
I2 => N9,
I3 => G1_CLK1MHz_cmp_eq00001_wg_cy(6),
O => G1_CLK1MHz_cmp_eq0000_5
);
G1_cnt_cmp_eq0000 : LUT4
generic map(
INIT => X"0400"
)
port map (
I0 => G1_cnt_add0000(3),
I1 => G1_cnt_add0000(5),
I2 => N11,
I3 => G1_CLK1MHz_cmp_eq00001_wg_cy(6),
O => G1_cnt_cmp_eq0000_209
);
SysCLK_IBUFG : IBUFG
port map (
I => SysCLK,
O => SysCLK_IBUFG_741
);
E_OBUF : OBUF
port map (
I => E_OBUF_3,
O => E
);
RS_OBUF : OBUF
port map (
I => RS_OBUF_675,
O => RS
);
RW_OBUF : OBUF
port map (
I => Mrom_databus_mux000512,
O => RW
);
databus_7_OBUF : OBUF
port map (
I => databus_7_809,
O => databus(7)
);
databus_6_OBUF : OBUF
port map (
I => databus_6_808,
O => databus(6)
);
databus_5_OBUF : OBUF
port map (
I => databus_5_807,
O => databus(5)
);
databus_4_OBUF : OBUF
port map (
I => databus_4_806,
O => databus(4)
);
databus_3_OBUF : OBUF
port map (
I => databus_3_805,
O => databus(3)
);
databus_2_OBUF : OBUF
port map (
I => databus_2_804,
O => databus(2)
);
databus_1_OBUF : OBUF
port map (
I => databus_1_803,
O => databus(1)
);
databus_0_OBUF : OBUF
port map (
I => databus_0_802,
O => databus(0)
);
Madd_wait_time_share0000_cy_2_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(2),
O => Madd_wait_time_share0000_cy_2_rt_370
);
Madd_wait_time_share0000_cy_3_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(3),
O => Madd_wait_time_share0000_cy_3_rt_374
);
Madd_wait_time_share0000_cy_6_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(6),
O => Madd_wait_time_share0000_cy_6_rt_378
);
Madd_wait_time_share0000_cy_7_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(7),
O => Madd_wait_time_share0000_cy_7_rt_380
);
Madd_wait_time_share0000_cy_8_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(8),
O => Madd_wait_time_share0000_cy_8_rt_382
);
Madd_wait_time_share0000_cy_9_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(9),
O => Madd_wait_time_share0000_cy_9_rt_384
);
Madd_wait_time_share0000_cy_10_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(10),
O => Madd_wait_time_share0000_cy_10_rt_329
);
Madd_wait_time_share0000_cy_11_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(11),
O => Madd_wait_time_share0000_cy_11_rt_331
);
Madd_wait_time_share0000_cy_12_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(12),
O => Madd_wait_time_share0000_cy_12_rt_333
);
Madd_wait_time_share0000_cy_13_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(13),
O => Madd_wait_time_share0000_cy_13_rt_335
);
Madd_wait_time_share0000_cy_14_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(14),
O => Madd_wait_time_share0000_cy_14_rt_337
);
Madd_wait_time_share0000_cy_15_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(15),
O => Madd_wait_time_share0000_cy_15_rt_339
);
Madd_wait_time_share0000_cy_16_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(16),
O => Madd_wait_time_share0000_cy_16_rt_341
);
Madd_wait_time_share0000_cy_17_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(17),
O => Madd_wait_time_share0000_cy_17_rt_343
);
Madd_wait_time_share0000_cy_18_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(18),
O => Madd_wait_time_share0000_cy_18_rt_345
);
Madd_wait_time_share0000_cy_19_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(19),
O => Madd_wait_time_share0000_cy_19_rt_347
);
Madd_wait_time_share0000_cy_20_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(20),
O => Madd_wait_time_share0000_cy_20_rt_350
);
Madd_wait_time_share0000_cy_21_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(21),
O => Madd_wait_time_share0000_cy_21_rt_352
);
Madd_wait_time_share0000_cy_22_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(22),
O => Madd_wait_time_share0000_cy_22_rt_354
);
Madd_wait_time_share0000_cy_23_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(23),
O => Madd_wait_time_share0000_cy_23_rt_356
);
Madd_wait_time_share0000_cy_24_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(24),
O => Madd_wait_time_share0000_cy_24_rt_358
);
Madd_wait_time_share0000_cy_25_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(25),
O => Madd_wait_time_share0000_cy_25_rt_360
);
Madd_wait_time_share0000_cy_26_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(26),
O => Madd_wait_time_share0000_cy_26_rt_362
);
Madd_wait_time_share0000_cy_27_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(27),
O => Madd_wait_time_share0000_cy_27_rt_364
);
Madd_wait_time_share0000_cy_28_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(28),
O => Madd_wait_time_share0000_cy_28_rt_366
);
Madd_wait_time_share0000_cy_29_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(29),
O => Madd_wait_time_share0000_cy_29_rt_368
);
Madd_wait_time_share0000_cy_30_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(30),
O => Madd_wait_time_share0000_cy_30_rt_372
);
Madd_databus_add0000_cy_9_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(9),
O => Madd_databus_add0000_cy_9_rt_255
);
Madd_databus_add0000_cy_11_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(11),
O => Madd_databus_add0000_cy_11_rt_212
);
Madd_databus_add0000_cy_13_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(13),
O => Madd_databus_add0000_cy_13_rt_215
);
Madd_databus_add0000_cy_15_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(15),
O => Madd_databus_add0000_cy_15_rt_218
);
Madd_databus_add0000_cy_16_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(16),
O => Madd_databus_add0000_cy_16_rt_220
);
Madd_databus_add0000_cy_17_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(17),
O => Madd_databus_add0000_cy_17_rt_222
);
Madd_databus_add0000_cy_18_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(18),
O => Madd_databus_add0000_cy_18_rt_224
);
Madd_databus_add0000_cy_19_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(19),
O => Madd_databus_add0000_cy_19_rt_226
);
Madd_databus_add0000_cy_20_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(20),
O => Madd_databus_add0000_cy_20_rt_228
);
Madd_databus_add0000_cy_21_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(21),
O => Madd_databus_add0000_cy_21_rt_230
);
Madd_databus_add0000_cy_22_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(22),
O => Madd_databus_add0000_cy_22_rt_232
);
Madd_databus_add0000_cy_23_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(23),
O => Madd_databus_add0000_cy_23_rt_234
);
Madd_databus_add0000_cy_24_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(24),
O => Madd_databus_add0000_cy_24_rt_236
);
Madd_databus_add0000_cy_25_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(25),
O => Madd_databus_add0000_cy_25_rt_238
);
Madd_databus_add0000_cy_26_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(26),
O => Madd_databus_add0000_cy_26_rt_240
);
Madd_databus_add0000_cy_27_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(27),
O => Madd_databus_add0000_cy_27_rt_242
);
Madd_databus_add0000_cy_28_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(28),
O => Madd_databus_add0000_cy_28_rt_244
);
Madd_databus_add0000_cy_29_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(29),
O => Madd_databus_add0000_cy_29_rt_246
);
Madd_databus_add0000_cy_30_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(30),
O => Madd_databus_add0000_cy_30_rt_248
);
Madd_index_addsub0000_cy_1_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => index(1),
O => Madd_index_addsub0000_cy_1_rt_287
);
Madd_index_addsub0000_cy_2_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => index(2),
O => Madd_index_addsub0000_cy_2_rt_309
);
Madd_index_addsub0000_cy_3_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => index(3),
O => Madd_index_addsub0000_cy_3_rt_313
);
Madd_index_addsub0000_cy_4_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => index(4),
O => Madd_index_addsub0000_cy_4_rt_315
);
Madd_index_addsub0000_cy_5_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => index(5),
O => Madd_index_addsub0000_cy_5_rt_317
);
Madd_index_addsub0000_cy_6_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => index(6),
O => Madd_index_addsub0000_cy_6_rt_319
);
Madd_index_addsub0000_cy_7_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => index(7),
O => Madd_index_addsub0000_cy_7_rt_321
);
Madd_index_addsub0000_cy_8_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => index(8),
O => Madd_index_addsub0000_cy_8_rt_323
);
Madd_index_addsub0000_cy_9_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => index(9),
O => Madd_index_addsub0000_cy_9_rt_325
);
Madd_index_addsub0000_cy_10_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => index(10),
O => Madd_index_addsub0000_cy_10_rt_267
);
Madd_index_addsub0000_cy_11_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => index(11),
O => Madd_index_addsub0000_cy_11_rt_269
);
Madd_index_addsub0000_cy_12_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => index(12),
O => Madd_index_addsub0000_cy_12_rt_271
);
Madd_index_addsub0000_cy_13_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => index(13),
O => Madd_index_addsub0000_cy_13_rt_273
);
Madd_index_addsub0000_cy_14_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => index(14),
O => Madd_index_addsub0000_cy_14_rt_275
);
Madd_index_addsub0000_cy_15_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => index(15),
O => Madd_index_addsub0000_cy_15_rt_277
);
Madd_index_addsub0000_cy_16_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => index(16),
O => Madd_index_addsub0000_cy_16_rt_279
);
Madd_index_addsub0000_cy_17_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => index(17),
O => Madd_index_addsub0000_cy_17_rt_281
);
Madd_index_addsub0000_cy_18_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => index(18),
O => Madd_index_addsub0000_cy_18_rt_283
);
Madd_index_addsub0000_cy_19_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => index(19),
O => Madd_index_addsub0000_cy_19_rt_285
);
Madd_index_addsub0000_cy_20_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => index(20),
O => Madd_index_addsub0000_cy_20_rt_289
);
Madd_index_addsub0000_cy_21_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => index(21),
O => Madd_index_addsub0000_cy_21_rt_291
);
Madd_index_addsub0000_cy_22_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => index(22),
O => Madd_index_addsub0000_cy_22_rt_293
);
Madd_index_addsub0000_cy_23_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => index(23),
O => Madd_index_addsub0000_cy_23_rt_295
);
Madd_index_addsub0000_cy_24_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => index(24),
O => Madd_index_addsub0000_cy_24_rt_297
);
Madd_index_addsub0000_cy_25_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => index(25),
O => Madd_index_addsub0000_cy_25_rt_299
);
Madd_index_addsub0000_cy_26_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => index(26),
O => Madd_index_addsub0000_cy_26_rt_301
);
Madd_index_addsub0000_cy_27_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => index(27),
O => Madd_index_addsub0000_cy_27_rt_303
);
Madd_index_addsub0000_cy_28_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => index(28),
O => Madd_index_addsub0000_cy_28_rt_305
);
Madd_index_addsub0000_cy_29_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => index(29),
O => Madd_index_addsub0000_cy_29_rt_307
);
Madd_index_addsub0000_cy_30_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => index(30),
O => Madd_index_addsub0000_cy_30_rt_311
);
Mcompar_wait_time_cmp_ge0000_cy_1_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(8),
O => Mcompar_wait_time_cmp_ge0000_cy_1_rt_436
);
Mcompar_wait_time_cmp_ge0000_cy_3_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(10),
O => Mcompar_wait_time_cmp_ge0000_cy_3_rt_446
);
Mcompar_wait_time_cmp_ge0000_cy_5_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(12),
O => Mcompar_wait_time_cmp_ge0000_cy_5_rt_456
);
Mcompar_wait_time_cmp_ge0000_cy_7_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(14),
O => Mcompar_wait_time_cmp_ge0000_cy_7_rt_467
);
Mcompar_wait_time_cmp_ge0000_cy_0_0_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(3),
O => Mcompar_wait_time_cmp_ge0000_cy_0_0_rt_425
);
Mcompar_wait_time_cmp_ge0000_cy_6_0_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(14),
O => Mcompar_wait_time_cmp_ge0000_cy_6_0_rt_461
);
Mcompar_wait_time_cmp_ge0000_cy_0_1_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(2),
O => Mcompar_wait_time_cmp_ge0000_cy_0_1_rt_426
);
Mcompar_wait_time_cmp_ge0000_cy_2_1_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(7),
O => Mcompar_wait_time_cmp_ge0000_cy_2_1_rt_441
);
Mcompar_wait_time_cmp_ge0000_cy_6_1_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(14),
O => Mcompar_wait_time_cmp_ge0000_cy_6_1_rt_462
);
Mcompar_wait_time_cmp_ge0000_cy_0_2_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(5),
O => Mcompar_wait_time_cmp_ge0000_cy_0_2_rt_427
);
Mcompar_wait_time_cmp_ge0000_cy_4_2_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(14),
O => Mcompar_wait_time_cmp_ge0000_cy_4_2_rt_451
);
G1_Madd_cnt_add0000_cy_1_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(1),
O => G1_Madd_cnt_add0000_cy_1_rt_42
);
G1_Madd_cnt_add0000_cy_2_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(2),
O => G1_Madd_cnt_add0000_cy_2_rt_64
);
G1_Madd_cnt_add0000_cy_3_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(3),
O => G1_Madd_cnt_add0000_cy_3_rt_68
);
G1_Madd_cnt_add0000_cy_4_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(4),
O => G1_Madd_cnt_add0000_cy_4_rt_70
);
G1_Madd_cnt_add0000_cy_5_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(5),
O => G1_Madd_cnt_add0000_cy_5_rt_72
);
G1_Madd_cnt_add0000_cy_6_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(6),
O => G1_Madd_cnt_add0000_cy_6_rt_74
);
G1_Madd_cnt_add0000_cy_7_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(7),
O => G1_Madd_cnt_add0000_cy_7_rt_76
);
G1_Madd_cnt_add0000_cy_8_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(8),
O => G1_Madd_cnt_add0000_cy_8_rt_78
);
G1_Madd_cnt_add0000_cy_9_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(9),
O => G1_Madd_cnt_add0000_cy_9_rt_80
);
G1_Madd_cnt_add0000_cy_10_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(10),
O => G1_Madd_cnt_add0000_cy_10_rt_22
);
G1_Madd_cnt_add0000_cy_11_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(11),
O => G1_Madd_cnt_add0000_cy_11_rt_24
);
G1_Madd_cnt_add0000_cy_12_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(12),
O => G1_Madd_cnt_add0000_cy_12_rt_26
);
G1_Madd_cnt_add0000_cy_13_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(13),
O => G1_Madd_cnt_add0000_cy_13_rt_28
);
G1_Madd_cnt_add0000_cy_14_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(14),
O => G1_Madd_cnt_add0000_cy_14_rt_30
);
G1_Madd_cnt_add0000_cy_15_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(15),
O => G1_Madd_cnt_add0000_cy_15_rt_32
);
G1_Madd_cnt_add0000_cy_16_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(16),
O => G1_Madd_cnt_add0000_cy_16_rt_34
);
G1_Madd_cnt_add0000_cy_17_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(17),
O => G1_Madd_cnt_add0000_cy_17_rt_36
);
G1_Madd_cnt_add0000_cy_18_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(18),
O => G1_Madd_cnt_add0000_cy_18_rt_38
);
G1_Madd_cnt_add0000_cy_19_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(19),
O => G1_Madd_cnt_add0000_cy_19_rt_40
);
G1_Madd_cnt_add0000_cy_20_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(20),
O => G1_Madd_cnt_add0000_cy_20_rt_44
);
G1_Madd_cnt_add0000_cy_21_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(21),
O => G1_Madd_cnt_add0000_cy_21_rt_46
);
G1_Madd_cnt_add0000_cy_22_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(22),
O => G1_Madd_cnt_add0000_cy_22_rt_48
);
G1_Madd_cnt_add0000_cy_23_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(23),
O => G1_Madd_cnt_add0000_cy_23_rt_50
);
G1_Madd_cnt_add0000_cy_24_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(24),
O => G1_Madd_cnt_add0000_cy_24_rt_52
);
G1_Madd_cnt_add0000_cy_25_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(25),
O => G1_Madd_cnt_add0000_cy_25_rt_54
);
G1_Madd_cnt_add0000_cy_26_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(26),
O => G1_Madd_cnt_add0000_cy_26_rt_56
);
G1_Madd_cnt_add0000_cy_27_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(27),
O => G1_Madd_cnt_add0000_cy_27_rt_58
);
G1_Madd_cnt_add0000_cy_28_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(28),
O => G1_Madd_cnt_add0000_cy_28_rt_60
);
G1_Madd_cnt_add0000_cy_29_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(29),
O => G1_Madd_cnt_add0000_cy_29_rt_62
);
G1_Madd_cnt_add0000_cy_30_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(30),
O => G1_Madd_cnt_add0000_cy_30_rt_66
);
G1_Mcount_cnt_cy_1_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(1),
O => G1_Mcount_cnt_cy_1_rt_105
);
G1_Mcount_cnt_cy_2_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(2),
O => G1_Mcount_cnt_cy_2_rt_127
);
G1_Mcount_cnt_cy_3_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(3),
O => G1_Mcount_cnt_cy_3_rt_131
);
G1_Mcount_cnt_cy_4_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(4),
O => G1_Mcount_cnt_cy_4_rt_133
);
G1_Mcount_cnt_cy_5_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(5),
O => G1_Mcount_cnt_cy_5_rt_135
);
G1_Mcount_cnt_cy_6_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(6),
O => G1_Mcount_cnt_cy_6_rt_137
);
G1_Mcount_cnt_cy_7_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(7),
O => G1_Mcount_cnt_cy_7_rt_139
);
G1_Mcount_cnt_cy_8_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(8),
O => G1_Mcount_cnt_cy_8_rt_141
);
G1_Mcount_cnt_cy_9_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(9),
O => G1_Mcount_cnt_cy_9_rt_143
);
G1_Mcount_cnt_cy_10_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(10),
O => G1_Mcount_cnt_cy_10_rt_85
);
G1_Mcount_cnt_cy_11_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(11),
O => G1_Mcount_cnt_cy_11_rt_87
);
G1_Mcount_cnt_cy_12_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(12),
O => G1_Mcount_cnt_cy_12_rt_89
);
G1_Mcount_cnt_cy_13_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(13),
O => G1_Mcount_cnt_cy_13_rt_91
);
G1_Mcount_cnt_cy_14_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(14),
O => G1_Mcount_cnt_cy_14_rt_93
);
G1_Mcount_cnt_cy_15_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(15),
O => G1_Mcount_cnt_cy_15_rt_95
);
G1_Mcount_cnt_cy_16_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(16),
O => G1_Mcount_cnt_cy_16_rt_97
);
G1_Mcount_cnt_cy_17_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(17),
O => G1_Mcount_cnt_cy_17_rt_99
);
G1_Mcount_cnt_cy_18_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(18),
O => G1_Mcount_cnt_cy_18_rt_101
);
G1_Mcount_cnt_cy_19_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(19),
O => G1_Mcount_cnt_cy_19_rt_103
);
G1_Mcount_cnt_cy_20_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(20),
O => G1_Mcount_cnt_cy_20_rt_107
);
G1_Mcount_cnt_cy_21_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(21),
O => G1_Mcount_cnt_cy_21_rt_109
);
G1_Mcount_cnt_cy_22_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(22),
O => G1_Mcount_cnt_cy_22_rt_111
);
G1_Mcount_cnt_cy_23_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(23),
O => G1_Mcount_cnt_cy_23_rt_113
);
G1_Mcount_cnt_cy_24_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(24),
O => G1_Mcount_cnt_cy_24_rt_115
);
G1_Mcount_cnt_cy_25_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(25),
O => G1_Mcount_cnt_cy_25_rt_117
);
G1_Mcount_cnt_cy_26_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(26),
O => G1_Mcount_cnt_cy_26_rt_119
);
G1_Mcount_cnt_cy_27_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(27),
O => G1_Mcount_cnt_cy_27_rt_121
);
G1_Mcount_cnt_cy_28_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(28),
O => G1_Mcount_cnt_cy_28_rt_123
);
G1_Mcount_cnt_cy_29_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(29),
O => G1_Mcount_cnt_cy_29_rt_125
);
G1_Mcount_cnt_cy_30_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(30),
O => G1_Mcount_cnt_cy_30_rt_129
);
Mcount_count_us_cy_1_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(1),
O => Mcount_count_us_cy_1_rt_614
);
Mcount_count_us_cy_2_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(2),
O => Mcount_count_us_cy_2_rt_636
);
Mcount_count_us_cy_3_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(3),
O => Mcount_count_us_cy_3_rt_640
);
Mcount_count_us_cy_4_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(4),
O => Mcount_count_us_cy_4_rt_642
);
Mcount_count_us_cy_5_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(5),
O => Mcount_count_us_cy_5_rt_644
);
Mcount_count_us_cy_6_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(6),
O => Mcount_count_us_cy_6_rt_646
);
Mcount_count_us_cy_7_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(7),
O => Mcount_count_us_cy_7_rt_648
);
Mcount_count_us_cy_8_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(8),
O => Mcount_count_us_cy_8_rt_650
);
Mcount_count_us_cy_9_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(9),
O => Mcount_count_us_cy_9_rt_652
);
Mcount_count_us_cy_10_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(10),
O => Mcount_count_us_cy_10_rt_594
);
Mcount_count_us_cy_11_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(11),
O => Mcount_count_us_cy_11_rt_596
);
Mcount_count_us_cy_12_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(12),
O => Mcount_count_us_cy_12_rt_598
);
Mcount_count_us_cy_13_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(13),
O => Mcount_count_us_cy_13_rt_600
);
Mcount_count_us_cy_14_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(14),
O => Mcount_count_us_cy_14_rt_602
);
Mcount_count_us_cy_15_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(15),
O => Mcount_count_us_cy_15_rt_604
);
Mcount_count_us_cy_16_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(16),
O => Mcount_count_us_cy_16_rt_606
);
Mcount_count_us_cy_17_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(17),
O => Mcount_count_us_cy_17_rt_608
);
Mcount_count_us_cy_18_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(18),
O => Mcount_count_us_cy_18_rt_610
);
Mcount_count_us_cy_19_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(19),
O => Mcount_count_us_cy_19_rt_612
);
Mcount_count_us_cy_20_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(20),
O => Mcount_count_us_cy_20_rt_616
);
Mcount_count_us_cy_21_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(21),
O => Mcount_count_us_cy_21_rt_618
);
Mcount_count_us_cy_22_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(22),
O => Mcount_count_us_cy_22_rt_620
);
Mcount_count_us_cy_23_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(23),
O => Mcount_count_us_cy_23_rt_622
);
Mcount_count_us_cy_24_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(24),
O => Mcount_count_us_cy_24_rt_624
);
Mcount_count_us_cy_25_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(25),
O => Mcount_count_us_cy_25_rt_626
);
Mcount_count_us_cy_26_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(26),
O => Mcount_count_us_cy_26_rt_628
);
Mcount_count_us_cy_27_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(27),
O => Mcount_count_us_cy_27_rt_630
);
Mcount_count_us_cy_28_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(28),
O => Mcount_count_us_cy_28_rt_632
);
Mcount_count_us_cy_29_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(29),
O => Mcount_count_us_cy_29_rt_634
);
Mcount_count_us_cy_30_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(30),
O => Mcount_count_us_cy_30_rt_638
);
Madd_wait_time_share0000_xor_31_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(31),
O => Madd_wait_time_share0000_xor_31_rt_388
);
Madd_databus_add0000_xor_31_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => wait_time(31),
O => Madd_databus_add0000_xor_31_rt_264
);
Madd_index_addsub0000_xor_31_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => index(31),
O => Madd_index_addsub0000_xor_31_rt_327
);
G1_Madd_cnt_add0000_xor_31_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(31),
O => G1_Madd_cnt_add0000_xor_31_rt_82
);
G1_Mcount_cnt_xor_31_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => G1_cnt(31),
O => G1_Mcount_cnt_xor_31_rt_145
);
Mcount_count_us_xor_31_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_us(31),
O => Mcount_count_us_xor_31_rt_654
);
Mmux_index_mux0003251 : LUT4
generic map(
INIT => X"ACAA"
)
port map (
I0 => index(31),
I1 => index_addsub0000(31),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => index_mux0003(31)
);
Mmux_index_mux0003241 : LUT4
generic map(
INIT => X"ACAA"
)
port map (
I0 => index(30),
I1 => index_addsub0000(30),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => index_mux0003(30)
);
Mmux_index_mux0003221 : LUT4
generic map(
INIT => X"ACAA"
)
port map (
I0 => index(29),
I1 => index_addsub0000(29),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => index_mux0003(29)
);
Mmux_index_mux0003211 : LUT4
generic map(
INIT => X"ACAA"
)
port map (
I0 => index(28),
I1 => index_addsub0000(28),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => index_mux0003(28)
);
Mmux_index_mux0003201 : LUT4
generic map(
INIT => X"ACAA"
)
port map (
I0 => index(27),
I1 => index_addsub0000(27),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => index_mux0003(27)
);
Mmux_index_mux0003191 : LUT4
generic map(
INIT => X"ACAA"
)
port map (
I0 => index(26),
I1 => index_addsub0000(26),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => index_mux0003(26)
);
Mmux_index_mux0003181 : LUT4
generic map(
INIT => X"ACAA"
)
port map (
I0 => index(25),
I1 => index_addsub0000(25),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => index_mux0003(25)
);
Mmux_index_mux0003171 : LUT4
generic map(
INIT => X"ACAA"
)
port map (
I0 => index(24),
I1 => index_addsub0000(24),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => index_mux0003(24)
);
Mmux_index_mux0003161 : LUT4
generic map(
INIT => X"ACAA"
)
port map (
I0 => index(23),
I1 => index_addsub0000(23),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => index_mux0003(23)
);
Mmux_index_mux0003151 : LUT4
generic map(
INIT => X"ACAA"
)
port map (
I0 => index(22),
I1 => index_addsub0000(22),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => index_mux0003(22)
);
Mmux_index_mux0003141 : LUT4
generic map(
INIT => X"ACAA"
)
port map (
I0 => index(21),
I1 => index_addsub0000(21),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => index_mux0003(21)
);
Mmux_index_mux0003131 : LUT4
generic map(
INIT => X"ACAA"
)
port map (
I0 => index(20),
I1 => index_addsub0000(20),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => index_mux0003(20)
);
Mmux_index_mux0003111 : LUT4
generic map(
INIT => X"ACAA"
)
port map (
I0 => index(19),
I1 => index_addsub0000(19),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => index_mux0003(19)
);
Mmux_index_mux0003101 : LUT4
generic map(
INIT => X"ACAA"
)
port map (
I0 => index(18),
I1 => index_addsub0000(18),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => index_mux0003(18)
);
Mmux_index_mux000391 : LUT4
generic map(
INIT => X"ACAA"
)
port map (
I0 => index(17),
I1 => index_addsub0000(17),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => index_mux0003(17)
);
Mmux_index_mux000381 : LUT4
generic map(
INIT => X"ACAA"
)
port map (
I0 => index(16),
I1 => index_addsub0000(16),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => index_mux0003(16)
);
Mmux_index_mux000371 : LUT4
generic map(
INIT => X"ACAA"
)
port map (
I0 => index(15),
I1 => index_addsub0000(15),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => index_mux0003(15)
);
Mmux_index_mux000361 : LUT4
generic map(
INIT => X"ACAA"
)
port map (
I0 => index(14),
I1 => index_addsub0000(14),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => index_mux0003(14)
);
Mmux_index_mux000351 : LUT4
generic map(
INIT => X"ACAA"
)
port map (
I0 => index(13),
I1 => index_addsub0000(13),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => index_mux0003(13)
);
Mmux_index_mux000341 : LUT4
generic map(
INIT => X"ACAA"
)
port map (
I0 => index(12),
I1 => index_addsub0000(12),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => index_mux0003(12)
);
Mmux_index_mux000331 : LUT4
generic map(
INIT => X"ACAA"
)
port map (
I0 => index(11),
I1 => index_addsub0000(11),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => index_mux0003(11)
);
Mmux_index_mux000321 : LUT4
generic map(
INIT => X"ACAA"
)
port map (
I0 => index(10),
I1 => index_addsub0000(10),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => index_mux0003(10)
);
Mmux_index_mux0003321 : LUT4
generic map(
INIT => X"ACAA"
)
port map (
I0 => index(9),
I1 => index_addsub0000(9),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => index_mux0003(9)
);
Mmux_index_mux0003311 : LUT4
generic map(
INIT => X"ACAA"
)
port map (
I0 => index(8),
I1 => index_addsub0000(8),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => index_mux0003(8)
);
Mmux_index_mux0003301 : LUT4
generic map(
INIT => X"ACAA"
)
port map (
I0 => index(7),
I1 => index_addsub0000(7),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => index_mux0003(7)
);
Mmux_index_mux0003291 : LUT4
generic map(
INIT => X"ACAA"
)
port map (
I0 => index(6),
I1 => index_addsub0000(6),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => index_mux0003(6)
);
Mmux_index_mux0003281 : LUT4
generic map(
INIT => X"ACAA"
)
port map (
I0 => index(5),
I1 => index_addsub0000(5),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => index_mux0003(5)
);
Mmux_index_mux0003271 : LUT4
generic map(
INIT => X"ACAA"
)
port map (
I0 => index(4),
I1 => index_addsub0000(4),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => index_mux0003(4)
);
Mmux_index_mux0003261 : LUT4
generic map(
INIT => X"ACAA"
)
port map (
I0 => index(3),
I1 => index_addsub0000(3),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => index_mux0003(3)
);
Mmux_index_mux0003231 : LUT4
generic map(
INIT => X"ACAA"
)
port map (
I0 => index(2),
I1 => index_addsub0000(2),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => index_mux0003(2)
);
Mmux_wait_time_mux0003251 : LUT4
generic map(
INIT => X"CCCA"
)
port map (
I0 => wait_time(31),
I1 => wait_time_share0000(31),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => wait_time_mux0003(31)
);
Mmux_wait_time_mux0003241 : LUT4
generic map(
INIT => X"CCCA"
)
port map (
I0 => wait_time(30),
I1 => wait_time_share0000(30),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => wait_time_mux0003(30)
);
Mmux_index_mux0003121 : LUT4
generic map(
INIT => X"ACAA"
)
port map (
I0 => index(1),
I1 => index_addsub0000(1),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => index_mux0003(1)
);
Mmux_wait_time_mux0003221 : LUT4
generic map(
INIT => X"CCCA"
)
port map (
I0 => wait_time(29),
I1 => wait_time_share0000(29),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => wait_time_mux0003(29)
);
Mmux_wait_time_mux0003211 : LUT4
generic map(
INIT => X"CCCA"
)
port map (
I0 => wait_time(28),
I1 => wait_time_share0000(28),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => wait_time_mux0003(28)
);
Mmux_wait_time_mux0003201 : LUT4
generic map(
INIT => X"CCCA"
)
port map (
I0 => wait_time(27),
I1 => wait_time_share0000(27),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => wait_time_mux0003(27)
);
Mmux_wait_time_mux0003191 : LUT4
generic map(
INIT => X"CCCA"
)
port map (
I0 => wait_time(26),
I1 => wait_time_share0000(26),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => wait_time_mux0003(26)
);
Mmux_wait_time_mux0003181 : LUT4
generic map(
INIT => X"CCCA"
)
port map (
I0 => wait_time(25),
I1 => wait_time_share0000(25),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => wait_time_mux0003(25)
);
Mmux_wait_time_mux0003171 : LUT4
generic map(
INIT => X"CCCA"
)
port map (
I0 => wait_time(24),
I1 => wait_time_share0000(24),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => wait_time_mux0003(24)
);
Mmux_wait_time_mux0003161 : LUT4
generic map(
INIT => X"CCCA"
)
port map (
I0 => wait_time(23),
I1 => wait_time_share0000(23),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => wait_time_mux0003(23)
);
Mmux_wait_time_mux0003151 : LUT4
generic map(
INIT => X"CCCA"
)
port map (
I0 => wait_time(22),
I1 => wait_time_share0000(22),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => wait_time_mux0003(22)
);
Mmux_wait_time_mux0003141 : LUT4
generic map(
INIT => X"CCCA"
)
port map (
I0 => wait_time(21),
I1 => wait_time_share0000(21),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => wait_time_mux0003(21)
);
Mmux_wait_time_mux0003131 : LUT4
generic map(
INIT => X"CCCA"
)
port map (
I0 => wait_time(20),
I1 => wait_time_share0000(20),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => wait_time_mux0003(20)
);
Mmux_wait_time_mux0003111 : LUT4
generic map(
INIT => X"CCCA"
)
port map (
I0 => wait_time(19),
I1 => wait_time_share0000(19),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => wait_time_mux0003(19)
);
Mmux_wait_time_mux0003101 : LUT4
generic map(
INIT => X"CCCA"
)
port map (
I0 => wait_time(18),
I1 => wait_time_share0000(18),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => wait_time_mux0003(18)
);
Mmux_wait_time_mux000391 : LUT4
generic map(
INIT => X"CCCA"
)
port map (
I0 => wait_time(17),
I1 => wait_time_share0000(17),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => wait_time_mux0003(17)
);
Mmux_wait_time_mux000381 : LUT4
generic map(
INIT => X"CCCA"
)
port map (
I0 => wait_time(16),
I1 => wait_time_share0000(16),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => wait_time_mux0003(16)
);
Mmux_wait_time_mux000371 : LUT4
generic map(
INIT => X"CCCA"
)
port map (
I0 => wait_time(15),
I1 => wait_time_share0000(15),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => wait_time_mux0003(15)
);
Mmux_wait_time_mux000361 : LUT4
generic map(
INIT => X"CCCA"
)
port map (
I0 => wait_time(14),
I1 => wait_time_share0000(14),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => wait_time_mux0003(14)
);
Mmux_wait_time_mux000351 : LUT4
generic map(
INIT => X"CCCA"
)
port map (
I0 => wait_time(13),
I1 => wait_time_share0000(13),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => wait_time_mux0003(13)
);
Mmux_wait_time_mux000341 : LUT4
generic map(
INIT => X"CCCA"
)
port map (
I0 => wait_time(12),
I1 => wait_time_share0000(12),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => wait_time_mux0003(12)
);
Mmux_wait_time_mux000331 : LUT4
generic map(
INIT => X"CCCA"
)
port map (
I0 => wait_time(11),
I1 => wait_time_share0000(11),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => wait_time_mux0003(11)
);
Mmux_wait_time_mux000321 : LUT4
generic map(
INIT => X"CCCA"
)
port map (
I0 => wait_time(10),
I1 => wait_time_share0000(10),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => wait_time_mux0003(10)
);
Mmux_wait_time_mux0003321 : LUT4
generic map(
INIT => X"CCCA"
)
port map (
I0 => wait_time(9),
I1 => wait_time_share0000(9),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => wait_time_mux0003(9)
);
Mmux_wait_time_mux0003311 : LUT4
generic map(
INIT => X"CCCA"
)
port map (
I0 => wait_time(8),
I1 => wait_time_share0000(8),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => wait_time_mux0003(8)
);
Mmux_wait_time_mux0003301 : LUT4
generic map(
INIT => X"CCCA"
)
port map (
I0 => wait_time(7),
I1 => wait_time_share0000(7),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => wait_time_mux0003(7)
);
Mmux_wait_time_mux0003291 : LUT4
generic map(
INIT => X"CCCA"
)
port map (
I0 => wait_time(6),
I1 => wait_time_share0000(6),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => wait_time_mux0003(6)
);
Mmux_wait_time_mux0003281 : LUT4
generic map(
INIT => X"CCCA"
)
port map (
I0 => wait_time(5),
I1 => wait_time_share0000(5),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => wait_time_mux0003(5)
);
Mmux_wait_time_mux0003271 : LUT4
generic map(
INIT => X"CCCA"
)
port map (
I0 => wait_time(4),
I1 => wait_time_share0000(4),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => wait_time_mux0003(4)
);
Mmux_wait_time_mux0003261 : LUT4
generic map(
INIT => X"CCCA"
)
port map (
I0 => wait_time(3),
I1 => wait_time_share0000(3),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => wait_time_mux0003(3)
);
Mmux_wait_time_mux0003231 : LUT4
generic map(
INIT => X"CCCA"
)
port map (
I0 => wait_time(2),
I1 => wait_time_share0000(2),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => wait_time_mux0003(2)
);
Mmux_index_mux000311 : LUT4
generic map(
INIT => X"ACAA"
)
port map (
I0 => index(0),
I1 => Madd_index_addsub0000_lut(0),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => index_mux0003(0)
);
Mmux_wait_time_mux0003121 : LUT4
generic map(
INIT => X"CCCA"
)
port map (
I0 => wait_time(1),
I1 => Madd_wait_time_share0000_lut_1_Q,
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
I3 => wait_time_cmp_ge0001,
O => wait_time_mux0003(1)
);
Mcompar_wait_time_cmp_eq0000_lut_2_Q : LUT4
generic map(
INIT => X"6006"
)
port map (
I0 => count_us(4),
I1 => wait_time(4),
I2 => count_us(5),
I3 => databus_add0000(5),
O => Mcompar_wait_time_cmp_eq0000_lut(2)
);
databus_mux0006_4_SW2 : LUT4
generic map(
INIT => X"C881"
)
port map (
I0 => index(0),
I1 => index(2),
I2 => index(1),
I3 => index(3),
O => N13
);
databus_mux0006_4_Q : LUT3
generic map(
INIT => X"EA"
)
port map (
I0 => N23,
I1 => RS_mux0005,
I2 => N13,
O => databus_mux0006(4)
);
Mcompar_wait_time_cmp_ge0001_lut_4_Q : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => count_us(4),
I1 => wait_time(4),
O => Mcompar_wait_time_cmp_ge0001_lut(4)
);
databus_mux0006_4_21 : LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => wait_time_cmp_ge00001,
I1 => databus_cmp_ge0002,
I2 => databus_cmp_ge0000,
I3 => databus_cmp_ge0001,
O => N23
);
databus_mux0006_4_11 : LUT3
generic map(
INIT => X"08"
)
port map (
I0 => Mcompar_wait_time_cmp_eq0000_cy(15),
I1 => wait_time_cmp_ge00001,
I2 => Mcompar_wait_time_cmp_lt0000_cy(8),
O => RS_mux0005
);
databus_mux0006_6_SW1 : LUT4
generic map(
INIT => X"FF9F"
)
port map (
I0 => index(3),
I1 => index(1),
I2 => index(2),
I3 => index(0),
O => N20
);
databus_mux0006_6_Q : LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => wait_time_cmp_ge00001,
I1 => Mcompar_wait_time_cmp_eq0000_cy(15),
I2 => Mcompar_wait_time_cmp_lt0000_cy(8),
I3 => N20,
O => databus_mux0006(6)
);
databus_mux0006_7_SW1 : LUT4
generic map(
INIT => X"8881"
)
port map (
I0 => index(3),
I1 => index(2),
I2 => index(0),
I3 => index(1),
O => N22
);
databus_mux0006_7_Q : LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => wait_time_cmp_ge00001,
I1 => Mcompar_wait_time_cmp_eq0000_cy(15),
I2 => Mcompar_wait_time_cmp_lt0000_cy(8),
I3 => N22,
O => databus_mux0006(7)
);
databus_mux0006_0_84_SW0_SW1 : LUT4
generic map(
INIT => X"A9AD"
)
port map (
I0 => index(2),
I1 => index(3),
I2 => index(0),
I3 => index(1),
O => N26
);
Unbuf_E_mux0009166 : MUXF5
port map (
I0 => N28,
I1 => N29,
S => wait_time_cmp_ge00001,
O => Unbuf_E_mux0009
);
Unbuf_E_mux0009166_F : LUT4
generic map(
INIT => X"EFEE"
)
port map (
I0 => Unbuf_E_mux000971_761,
I1 => Unbuf_E_mux0009115_744,
I2 => databus_cmp_ge0000,
I3 => Unbuf_E_mux000936_759,
O => N28
);
Unbuf_E_mux0009166_G : LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => wait_time_cmp_lt0000,
I1 => Mcompar_wait_time_cmp_eq0000_cy(15),
I2 => wait_time_cmp_ge0001,
O => N29
);
Unbuf_E_mux000936 : MUXF5
port map (
I0 => N30,
I1 => N31,
S => databus_cmp_ge0001,
O => Unbuf_E_mux000936_759
);
Unbuf_E_mux000936_F : LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => databus_cmp_ge0002,
I1 => count_us(3),
I2 => count_us(6),
I3 => count_us(8),
O => N30
);
Unbuf_E_mux000936_G : LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => count_us(3),
I1 => Unbuf_E_mux000919_745,
I2 => count_us(8),
O => N31
);
Unbuf_E_mux0009115 : MUXF5
port map (
I0 => N32,
I1 => N33,
S => databus_cmp_ge0000,
O => Unbuf_E_mux0009115_744
);
Unbuf_E_mux0009115_F : LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => N41,
I1 => N81,
I2 => databus_cmp_ge0001,
I3 => count_us(6),
O => N32
);
Unbuf_E_mux0009115_G : LUT4
generic map(
INIT => X"FFBF"
)
port map (
I0 => count_us(6),
I1 => count_us(3),
I2 => count_us(8),
I3 => N41,
O => N33
);
wait_time_cmp_ge0000_BUFG : BUFG
port map (
I => wait_time_cmp_ge00001,
O => wait_time_cmp_ge0000
);
Madd_wait_time_share0000_lut_1_INV_0 : INV
port map (
I => wait_time(1),
O => Madd_wait_time_share0000_lut_1_Q
);
Madd_wait_time_share0000_lut_4_INV_0 : INV
port map (
I => wait_time(4),
O => Madd_wait_time_share0000_lut_4_Q
);
Madd_wait_time_share0000_lut_5_INV_0 : INV
port map (
I => wait_time(5),
O => Madd_wait_time_share0000_lut_5_Q
);
Madd_databus_add0000_lut_4_INV_0 : INV
port map (
I => wait_time(4),
O => Madd_databus_add0000_lut_4_Q
);
Madd_databus_add0000_lut_5_INV_0 : INV
port map (
I => wait_time(5),
O => Madd_databus_add0000_lut_5_Q
);
Madd_databus_add0000_lut_6_INV_0 : INV
port map (
I => wait_time(6),
O => Madd_databus_add0000_lut_6_Q
);
Madd_databus_add0000_lut_7_INV_0 : INV
port map (
I => wait_time(7),
O => Madd_databus_add0000_lut_7_Q
);
Madd_databus_add0000_lut_8_INV_0 : INV
port map (
I => wait_time(8),
O => Madd_databus_add0000_lut_8_Q
);
Madd_databus_add0000_lut_10_INV_0 : INV
port map (
I => wait_time(10),
O => Madd_databus_add0000_lut_10_Q
);
Madd_databus_add0000_lut_12_INV_0 : INV
port map (
I => wait_time(12),
O => Madd_databus_add0000_lut_12_Q
);
Madd_databus_add0000_lut_14_INV_0 : INV
port map (
I => wait_time(14),
O => Madd_databus_add0000_lut_14_Q
);
Madd_index_addsub0000_lut_0_INV_0 : INV
port map (
I => index(0),
O => Madd_index_addsub0000_lut(0)
);
Mcompar_wait_time_cmp_ge0000_lut_2_INV_0 : INV
port map (
I => count_us(9),
O => Mcompar_wait_time_cmp_ge0000_lut(2)
);
Mcompar_wait_time_cmp_ge0000_lut_4_INV_0 : INV
port map (
I => count_us(11),
O => Mcompar_wait_time_cmp_ge0000_lut(4)
);
Mcompar_wait_time_cmp_ge0000_lut_6_INV_0 : INV
port map (
I => count_us(13),
O => Mcompar_wait_time_cmp_ge0000_lut(6)
);
Mcompar_wait_time_cmp_ge0000_lut_1_INV_0 : INV
port map (
I => count_us(4),
O => Mcompar_wait_time_cmp_ge0000_lut(1)
);
Mcompar_wait_time_cmp_ge0000_lut_3_INV_0 : INV
port map (
I => count_us(8),
O => Mcompar_wait_time_cmp_ge0000_lut(3)
);
Mcompar_wait_time_cmp_ge0000_lut_3_1_INV_0 : INV
port map (
I => count_us(8),
O => Mcompar_wait_time_cmp_ge0000_lut_3_1
);
G1_Madd_cnt_add0000_lut_0_INV_0 : INV
port map (
I => G1_cnt(0),
O => G1_Madd_cnt_add0000_lut(0)
);
G1_Mcount_cnt_lut_0_INV_0 : INV
port map (
I => G1_cnt(0),
O => G1_Mcount_cnt_lut(0)
);
Mcount_count_us_lut_0_INV_0 : INV
port map (
I => count_us(0),
O => Mcount_count_us_lut(0)
);
Mcompar_wait_time_cmp_lt0000_cy_8_inv_INV_0 : INV
port map (
I => Mcompar_wait_time_cmp_lt0000_cy(8),
O => wait_time_cmp_lt0000
);
Mcompar_wait_time_cmp_ge0000_lut_11_11_INV_0 : INV
port map (
I => count_us(31),
O => Mcompar_wait_time_cmp_ge0000_lut_11_1
);
Mcompar_wait_time_cmp_ge0000_lut_11_21_INV_0 : INV
port map (
I => count_us(31),
O => Mcompar_wait_time_cmp_ge0000_lut_11_2
);
Mcompar_wait_time_cmp_ge0000_lut_12_1_INV_0 : INV
port map (
I => count_us(31),
O => Mcompar_wait_time_cmp_ge0000_lut(12)
);
Mcompar_wait_time_cmp_ge0000_lut_9_31_INV_0 : INV
port map (
I => count_us(31),
O => Mcompar_wait_time_cmp_ge0000_lut_9_3
);
Mcompar_wait_time_cmp_ge0001_lut_0_1_INV_0 : INV
port map (
I => count_us(0),
O => Mcompar_wait_time_cmp_ge0001_lut(0)
);
Mcompar_wait_time_cmp_lt0000_lut_8_1_INV_0 : INV
port map (
I => index(31),
O => Mcompar_wait_time_cmp_lt0000_lut(8)
);
databus_mux0006_0_841 : LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => N26,
I1 => Mcompar_wait_time_cmp_lt0000_cy(8),
I2 => Mcompar_wait_time_cmp_eq0000_cy(15),
O => databus_mux0006_0_84
);
databus_mux0006_0_842 : LUT2
generic map(
INIT => X"E"
)
port map (
I0 => databus_cmp_ge0001,
I1 => databus_cmp_ge0000,
O => databus_mux0006_0_841_842
);
databus_mux0006_0_84_f5 : MUXF5
port map (
I0 => databus_mux0006_0_841_842,
I1 => databus_mux0006_0_84,
S => wait_time_cmp_ge00001,
O => databus_mux0006(0)
);
G1_CLK1MHz_cmp_eq0000_SW0 : LUT2_L
generic map(
INIT => X"E"
)
port map (
I0 => G1_cnt(0),
I1 => G1_cnt_add0000(1),
LO => N9
);
G1_cnt_cmp_eq0000_SW0 : LUT2_L
generic map(
INIT => X"7"
)
port map (
I0 => G1_cnt_add0000(1),
I1 => G1_cnt(0),
LO => N11
);
end Structure;
| mit | 262470bcc33868a1a292d1d783db3369 | 0.547907 | 2.733851 | false | false | false | false |
freecores/usb_fpga_2_16 | examples/usb-fpga-1.11/1.11c/memtest/fpga/memtest.vhd | 16 | 23,751 | library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity memtest is
port(
FXCLK : in std_logic;
RESET_IN : in std_logic;
IFCLK : in std_logic;
-- FX2 FIFO
FD : out std_logic_vector(15 downto 0);
SLOE : out std_logic;
SLRD : out std_logic;
SLWR : out std_logic;
FIFOADR0 : out std_logic;
FIFOADR1 : out std_logic;
PKTEND : out std_logic;
FLAGB : in std_logic;
PA3 : in std_logic;
-- errors ...
PC : out std_logic_vector(7 downto 0);
-- DDR-SDRAM
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(1 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic
);
end memtest;
architecture RTL of memtest is
component dcm0
port (
-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic;
CLK_VALID : out std_logic
);
end component;
component mem0
generic (
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 5000;
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
C3_RST_ACT_LOW : integer := 0;
C3_CALIB_SOFT_IP : string := "FALSE";
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
C3_NUM_DQ_PINS : integer := 16;
C3_MEM_ADDR_WIDTH : integer := 13;
C3_MEM_BANKADDR_WIDTH : integer := 2
);
port (
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_n : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic;
c3_p1_cmd_clk : in std_logic;
c3_p1_cmd_en : in std_logic;
c3_p1_cmd_instr : in std_logic_vector(2 downto 0);
c3_p1_cmd_bl : in std_logic_vector(5 downto 0);
c3_p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p1_cmd_empty : out std_logic;
c3_p1_cmd_full : out std_logic;
c3_p1_wr_clk : in std_logic;
c3_p1_wr_en : in std_logic;
c3_p1_wr_mask : in std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0);
c3_p1_wr_data : in std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_wr_full : out std_logic;
c3_p1_wr_empty : out std_logic;
c3_p1_wr_count : out std_logic_vector(6 downto 0);
c3_p1_wr_underrun : out std_logic;
c3_p1_wr_error : out std_logic;
c3_p1_rd_clk : in std_logic;
c3_p1_rd_en : in std_logic;
c3_p1_rd_data : out std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_rd_full : out std_logic;
c3_p1_rd_empty : out std_logic;
c3_p1_rd_count : out std_logic_vector(6 downto 0);
c3_p1_rd_overflow : out std_logic;
c3_p1_rd_error : out std_logic;
c3_p2_cmd_clk : in std_logic;
c3_p2_cmd_en : in std_logic;
c3_p2_cmd_instr : in std_logic_vector(2 downto 0);
c3_p2_cmd_bl : in std_logic_vector(5 downto 0);
c3_p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p2_cmd_empty : out std_logic;
c3_p2_cmd_full : out std_logic;
c3_p2_wr_clk : in std_logic;
c3_p2_wr_en : in std_logic;
c3_p2_wr_mask : in std_logic_vector(3 downto 0);
c3_p2_wr_data : in std_logic_vector(31 downto 0);
c3_p2_wr_full : out std_logic;
c3_p2_wr_empty : out std_logic;
c3_p2_wr_count : out std_logic_vector(6 downto 0);
c3_p2_wr_underrun : out std_logic;
c3_p2_wr_error : out std_logic;
c3_p3_cmd_clk : in std_logic;
c3_p3_cmd_en : in std_logic;
c3_p3_cmd_instr : in std_logic_vector(2 downto 0);
c3_p3_cmd_bl : in std_logic_vector(5 downto 0);
c3_p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p3_cmd_empty : out std_logic;
c3_p3_cmd_full : out std_logic;
c3_p3_rd_clk : in std_logic;
c3_p3_rd_en : in std_logic;
c3_p3_rd_data : out std_logic_vector(31 downto 0);
c3_p3_rd_full : out std_logic;
c3_p3_rd_empty : out std_logic;
c3_p3_rd_count : out std_logic_vector(6 downto 0);
c3_p3_rd_overflow : out std_logic;
c3_p3_rd_error : out std_logic;
c3_p4_cmd_clk : in std_logic;
c3_p4_cmd_en : in std_logic;
c3_p4_cmd_instr : in std_logic_vector(2 downto 0);
c3_p4_cmd_bl : in std_logic_vector(5 downto 0);
c3_p4_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p4_cmd_empty : out std_logic;
c3_p4_cmd_full : out std_logic;
c3_p4_wr_clk : in std_logic;
c3_p4_wr_en : in std_logic;
c3_p4_wr_mask : in std_logic_vector(3 downto 0);
c3_p4_wr_data : in std_logic_vector(31 downto 0);
c3_p4_wr_full : out std_logic;
c3_p4_wr_empty : out std_logic;
c3_p4_wr_count : out std_logic_vector(6 downto 0);
c3_p4_wr_underrun : out std_logic;
c3_p4_wr_error : out std_logic;
c3_p5_cmd_clk : in std_logic;
c3_p5_cmd_en : in std_logic;
c3_p5_cmd_instr : in std_logic_vector(2 downto 0);
c3_p5_cmd_bl : in std_logic_vector(5 downto 0);
c3_p5_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p5_cmd_empty : out std_logic;
c3_p5_cmd_full : out std_logic;
c3_p5_rd_clk : in std_logic;
c3_p5_rd_en : in std_logic;
c3_p5_rd_data : out std_logic_vector(31 downto 0);
c3_p5_rd_full : out std_logic;
c3_p5_rd_empty : out std_logic;
c3_p5_rd_count : out std_logic_vector(6 downto 0);
c3_p5_rd_overflow : out std_logic;
c3_p5_rd_error : out std_logic
);
end component;
signal CLK : std_logic;
signal RESET0 : std_logic; -- released after dcm0 is ready
signal RESET : std_logic; -- released after MCB is ready
signal DCM0_LOCKED : std_logic;
signal DCM0_CLK_VALID : std_logic;
----------------------------
-- test pattern generator --
----------------------------
signal GEN_CNT : std_logic_vector(29 downto 0);
signal GEN_PATTERN : std_logic_vector(29 downto 0);
signal FIFO_WORD : std_logic;
-----------------------
-- memory controller --
-----------------------
signal MEM_CLK : std_logic;
signal C3_CALIB_DONE : std_logic;
signal C3_RST0 : std_logic;
---------------
-- DRAM FIFO --
---------------
signal WR_CLK : std_logic;
signal WR_CMD_EN : std_logic_vector(2 downto 0);
type WR_CMD_ADDR_ARRAY is array(2 downto 0) of std_logic_vector(29 downto 0);
signal WR_CMD_ADDR : WR_CMD_ADDR_ARRAY;
signal WR_ADDR : std_logic_vector(17 downto 0); -- in 256 bytes burst blocks
signal WR_EN : std_logic_vector(2 downto 0);
signal WR_EN_TMP : std_logic_vector(2 downto 0);
signal WR_DATA : std_logic_vector(31 downto 0);
signal WR_EMPTY : std_logic_vector(2 downto 0);
signal WR_UNDERRUN : std_logic_vector(2 downto 0);
signal WR_ERROR : std_logic_vector(2 downto 0);
type WR_COUNT_ARRAY is array(2 downto 0) of std_logic_vector(6 downto 0);
signal WR_COUNT : WR_COUNT_ARRAY;
signal WR_PORT : std_logic_vector(1 downto 0);
signal RD_CLK : std_logic;
signal RD_CMD_EN : std_logic_vector(2 downto 0);
type RD_CMD_ADDR_ARRAY is array(2 downto 0) of std_logic_vector(29 downto 0);
signal RD_CMD_ADDR : WR_CMD_ADDR_ARRAY;
signal RD_ADDR : std_logic_vector(17 downto 0); -- in 256 bytes burst blocks
signal RD_EN : std_logic_vector(2 downto 0);
type RD_DATA_ARRAY is array(2 downto 0) of std_logic_vector(31 downto 0);
signal RD_DATA : RD_DATA_ARRAY;
signal RD_EMPTY : std_logic_vector(2 downto 0);
signal RD_OVERFLOW : std_logic_vector(2 downto 0);
signal RD_ERROR : std_logic_vector(2 downto 0);
signal RD_PORT : std_logic_vector(1 downto 0);
type RD_COUNT_ARRAY is array(2 downto 0) of std_logic_vector(6 downto 0);
signal RD_COUNT : RD_COUNT_ARRAY;
signal FD_TMP : std_logic_vector(15 downto 0);
signal RD_ADDR2 : std_logic_vector(17 downto 0); -- 256 bytes burst block currently beeing read
signal RD_ADDR2_BAK1 : std_logic_vector(17 downto 0); -- backup for synchronization
signal RD_ADDR2_BAK2 : std_logic_vector(17 downto 0); -- backup for synchronization
signal WR_ADDR2 : std_logic_vector(17 downto 0); -- 256 bytes burst block currently beeing written
signal WR_ADDR2_BAK1 : std_logic_vector(17 downto 0); -- backup for synchronization
signal WR_ADDR2_BAK2 : std_logic_vector(17 downto 0); -- backup for synchronization
signal RD_STOP : std_logic;
begin
inst_dcm0 : dcm0 port map(
-- Clock in ports
CLK_IN1 => FXCLK,
-- Clock out ports
CLK_OUT1 => MEM_CLK,
CLK_OUT2 => CLK,
-- Status and control signals
RESET => RESET_IN,
LOCKED => DCM0_LOCKED,
CLK_VALID => DCM0_CLK_VALID
);
inst_mem0 : mem0 port map (
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
mcb3_dram_dm => mcb3_dram_dm,
mcb3_rzq => mcb3_rzq,
c3_sys_clk => MEM_CLK,
c3_sys_rst_n => RESET0,
c3_clk0 => open,
c3_rst0 => C3_RST0,
c3_calib_done => C3_CALIB_DONE,
c3_p0_cmd_clk => WR_CLK,
c3_p0_cmd_en => WR_CMD_EN(0),
c3_p0_cmd_instr => "000",
c3_p0_cmd_bl => ( others => '1' ),
c3_p0_cmd_byte_addr => WR_CMD_ADDR(0),
c3_p0_cmd_empty => open,
c3_p0_cmd_full => open,
c3_p0_wr_clk => WR_CLK,
c3_p0_wr_en => WR_EN(0),
c3_p0_wr_mask => ( others => '0' ),
c3_p0_wr_data => WR_DATA,
c3_p0_wr_full => open,
c3_p0_wr_empty => WR_EMPTY(0),
c3_p0_wr_count => open,
c3_p0_wr_underrun => WR_UNDERRUN(0),
c3_p0_wr_error => WR_ERROR(0),
c3_p0_rd_clk => WR_CLK,
c3_p0_rd_en => '0',
c3_p0_rd_data => open,
c3_p0_rd_full => open,
c3_p0_rd_empty => open,
c3_p0_rd_count => open,
c3_p0_rd_overflow => open,
c3_p0_rd_error => open,
c3_p2_cmd_clk => WR_CLK,
c3_p2_cmd_en => WR_CMD_EN(1),
c3_p2_cmd_instr => "000",
c3_p2_cmd_bl => ( others => '1' ),
c3_p2_cmd_byte_addr => WR_CMD_ADDR(1),
c3_p2_cmd_empty => open,
c3_p2_cmd_full => open,
c3_p2_wr_clk => WR_CLK,
c3_p2_wr_en => WR_EN(1),
c3_p2_wr_mask => ( others => '0' ),
c3_p2_wr_data => WR_DATA,
c3_p2_wr_full => open,
c3_p2_wr_empty => WR_EMPTY(1),
c3_p2_wr_count => open,
c3_p2_wr_underrun => WR_UNDERRUN(1),
c3_p2_wr_error => WR_ERROR(1),
c3_p4_cmd_clk => WR_CLK,
c3_p4_cmd_en => WR_CMD_EN(2),
c3_p4_cmd_instr => "000",
c3_p4_cmd_bl => ( others => '1' ),
c3_p4_cmd_byte_addr => WR_CMD_ADDR(2),
c3_p4_cmd_empty => open,
c3_p4_cmd_full => open,
c3_p4_wr_clk => WR_CLK,
c3_p4_wr_en => WR_EN(2),
c3_p4_wr_mask => ( others => '0' ),
c3_p4_wr_data => WR_DATA,
c3_p4_wr_full => open,
c3_p4_wr_empty => WR_EMPTY(2),
c3_p4_wr_count => open,
c3_p4_wr_underrun => WR_UNDERRUN(2),
c3_p4_wr_error => WR_ERROR(2),
c3_p1_cmd_clk => RD_CLK,
c3_p1_cmd_en => RD_CMD_EN(0),
c3_p1_cmd_instr => "001",
c3_p1_cmd_bl => ( others => '1' ),
c3_p1_cmd_byte_addr => RD_CMD_ADDR(0),
c3_p1_cmd_empty => open,
c3_p1_cmd_full => open,
c3_p1_wr_clk => RD_CLK,
c3_p1_wr_en => '0',
c3_p1_wr_mask => ( others => '0' ),
c3_p1_wr_data => ( others => '0' ),
c3_p1_wr_full => open,
c3_p1_wr_empty => open,
c3_p1_wr_count => open,
c3_p1_wr_underrun => open,
c3_p1_wr_error => open,
c3_p1_rd_clk => RD_CLK,
c3_p1_rd_en => RD_EN(0),
c3_p1_rd_data => RD_DATA(0),
c3_p1_rd_full => open,
c3_p1_rd_empty => RD_EMPTY(0),
c3_p1_rd_count => open,
c3_p1_rd_overflow => RD_OVERFLOW(0),
c3_p1_rd_error => RD_ERROR(0),
c3_p3_cmd_clk => RD_CLK,
c3_p3_cmd_en => RD_CMD_EN(1),
c3_p3_cmd_instr => "001",
c3_p3_cmd_bl => ( others => '1' ),
c3_p3_cmd_byte_addr => RD_CMD_ADDR(1),
c3_p3_cmd_empty => open,
c3_p3_cmd_full => open,
c3_p3_rd_clk => RD_CLK,
c3_p3_rd_en => RD_EN(1),
c3_p3_rd_data => RD_DATA(1),
c3_p3_rd_full => open,
c3_p3_rd_empty => RD_EMPTY(1),
c3_p3_rd_count => open,
c3_p3_rd_overflow => RD_OVERFLOW(1),
c3_p3_rd_error => RD_ERROR(1),
c3_p5_cmd_clk => RD_CLK,
c3_p5_cmd_en => RD_CMD_EN(2),
c3_p5_cmd_instr => "001",
c3_p5_cmd_bl => ( others => '1' ),
c3_p5_cmd_byte_addr => RD_CMD_ADDR(2),
c3_p5_cmd_empty => open,
c3_p5_cmd_full => open,
c3_p5_rd_clk => RD_CLK,
c3_p5_rd_en => RD_EN(2),
c3_p5_rd_data => RD_DATA(2),
c3_p5_rd_full => open,
c3_p5_rd_empty => RD_EMPTY(2),
c3_p5_rd_count => open,
c3_p5_rd_overflow => RD_OVERFLOW(2),
c3_p5_rd_error => RD_ERROR(2)
);
SLOE <= '1';
SLRD <= '1';
FIFOADR0 <= '0';
FIFOADR1 <= '0';
PKTEND <= '1';
WR_CLK <= CLK;
RD_CLK <= IFCLK;
RESET0 <= RESET_IN or (not DCM0_LOCKED) or (not DCM0_CLK_VALID);
RESET <= RESET0 or (not C3_CALIB_DONE) or C3_RST0;
PC(0) <= WR_UNDERRUN(0) or WR_UNDERRUN(1) or WR_UNDERRUN(2);
PC(1) <= WR_ERROR(0) or WR_ERROR(1) or WR_ERROR(2);
PC(2) <= RD_OVERFLOW(0) or RD_OVERFLOW(1) or RD_OVERFLOW(2);
PC(3) <= RD_ERROR(0) or RD_ERROR(1) or RD_ERROR(2);
PC(4) <= C3_CALIB_DONE;
PC(5) <= C3_RST0;
PC(6) <= RESET0;
PC(7) <= RESET;
dpCLK: process (CLK, RESET)
begin
-- reset
if RESET = '1'
then
GEN_CNT <= ( others => '0' );
GEN_PATTERN <= "100101010101010101010101010101";
WR_CMD_EN <= ( others => '0' );
WR_CMD_ADDR(0) <= ( others => '0' );
WR_CMD_ADDR(1) <= ( others => '0' );
WR_CMD_ADDR(2) <= ( others => '0' );
WR_ADDR <= conv_std_logic_vector(3,18);
WR_EN <= ( others => '0' );
WR_COUNT(0) <= ( others => '0' );
WR_COUNT(1) <= ( others => '0' );
WR_COUNT(2) <= ( others => '0' );
WR_PORT <= ( others => '0' );
WR_ADDR2 <= ( others => '0' );
RD_ADDR2_BAK1 <= ( others => '0' );
RD_ADDR2_BAK2 <= ( others => '0' );
-- CLK
elsif CLK'event and CLK = '1'
then
WR_CMD_EN <= ( others => '0' );
WR_EN <= ( others => '0' );
WR_CMD_ADDR(conv_integer(WR_PORT))(25 downto 8) <= WR_ADDR;
if ( WR_COUNT(conv_integer(WR_PORT)) = conv_std_logic_vector(64,7) )
then
-- FF flag = 1
if ( RD_ADDR2_BAK1 = RD_ADDR2_BAK2 ) and ( RD_ADDR2_BAK2 /= WR_ADDR )
then
WR_CMD_EN(conv_integer(WR_PORT)) <= '1';
WR_COUNT(conv_integer(WR_PORT)) <= ( others => '0' );
if WR_PORT = "10"
then
WR_PORT <= "00";
else
WR_PORT <= WR_PORT + 1;
end if;
WR_ADDR <= WR_ADDR + 1;
WR_ADDR2 <= WR_ADDR2 + 1;
end if;
elsif ( WR_COUNT(conv_integer(WR_PORT)) = conv_std_logic_vector(0,7)) and (WR_EMPTY(conv_integer(WR_PORT)) = '0' ) -- write port fifo not empty
then
-- FF flag = 1
else
WR_EN(conv_integer(WR_PORT)) <= '1';
WR_DATA(31) <= '1';
WR_DATA(15) <= '0';
if PA3 = '1'
then
WR_DATA(30 downto 16) <= GEN_PATTERN(29 downto 15);
WR_DATA(14 downto 0) <= GEN_PATTERN(14 downto 0);
else
WR_DATA(30 downto 16) <= GEN_CNT(29 downto 15);
WR_DATA(14 downto 0) <= GEN_CNT(14 downto 0);
end if;
GEN_CNT <= GEN_CNT + 1;
GEN_PATTERN(29) <= GEN_PATTERN(0);
GEN_PATTERN(28 downto 0) <= GEN_PATTERN(29 downto 1);
-- if ( WR_COUNT(conv_integer(WR_PORT)) = conv_std_logic_vector(63,7) ) and ( RD_ADDR2_BAK1 = RD_ADDR2_BAK2 ) and ( RD_ADDR2_BAK2 /= WR_ADDR )
-- Add code from above here. This saves one clock cylcle and is required for uninterrupred input.
-- then
-- else
WR_COUNT(conv_integer(WR_PORT)) <= WR_COUNT(conv_integer(WR_PORT)) + 1;
-- end if;
end if;
RD_ADDR2_BAK1 <= RD_ADDR2;
RD_ADDR2_BAK2 <= RD_ADDR2_BAK1;
end if;
end process dpCLK;
dpIFCLK: process (IFCLK, RESET)
begin
-- reset
if RESET = '1'
then
FIFO_WORD <= '0';
SLWR <= '1';
RD_CMD_EN <= ( others => '0' );
RD_CMD_ADDR(0) <= ( others => '0' );
RD_CMD_ADDR(1) <= ( others => '0' );
RD_CMD_ADDR(2) <= ( others => '0' );
RD_ADDR <= conv_std_logic_vector(3,18);
RD_EN <= ( others => '0' );
RD_COUNT(0) <= conv_std_logic_vector(64,7);
RD_COUNT(1) <= conv_std_logic_vector(64,7);
RD_COUNT(2) <= conv_std_logic_vector(64,7);
RD_PORT <= ( others => '0' );
RD_ADDR2 <= ( others => '0' );
WR_ADDR2_BAK1 <= ( others => '0' );
WR_ADDR2_BAK2 <= ( others => '0' );
RD_STOP <= '1';
-- IFCLK
elsif IFCLK'event and IFCLK = '1'
then
RD_CMD_EN <= ( others => '0' );
RD_CMD_ADDR(conv_integer(RD_PORT))(25 downto 8) <= RD_ADDR;
RD_EN(conv_integer(RD_PORT)) <= '0';
if FLAGB = '1'
then
if ( RD_EMPTY(conv_integer(RD_PORT)) = '1' ) or ( RD_COUNT(conv_integer(RD_PORT)) = conv_std_logic_vector(64,7) )
then
SLWR <= '1';
if ( RD_COUNT(conv_integer(RD_PORT)) = conv_std_logic_vector(64,7) ) and ( RD_EMPTY(conv_integer(RD_PORT)) = '1' ) and ( WR_ADDR2_BAK2 = WR_ADDR2_BAK1 ) and ( WR_ADDR2_BAK2 /= RD_ADDR ) and ( RD_STOP = '0' )
then
RD_CMD_EN(conv_integer(RD_PORT)) <= '1';
RD_COUNT(conv_integer(RD_PORT)) <= ( others => '0' );
if RD_PORT = "10"
then
RD_PORT <= "00";
else
RD_PORT <= RD_PORT + 1;
end if;
RD_ADDR <= RD_ADDR + 1;
RD_ADDR2 <= RD_ADDR2 + 1;
end if;
else
SLWR <= '0';
if FIFO_WORD = '0'
then
FD(15 downto 0) <= RD_DATA(conv_integer(RD_PORT))(15 downto 0);
FD_TMP <= RD_DATA(conv_integer(RD_PORT))(31 downto 16);
RD_EN(conv_integer(RD_PORT)) <= '1';
else
FD(15 downto 0) <= FD_TMP;
RD_COUNT(conv_integer(RD_PORT)) <= RD_COUNT(conv_integer(RD_PORT)) + 1;
end if;
FIFO_WORD <= not FIFO_WORD;
end if;
end if;
WR_ADDR2_BAK1 <= WR_ADDR2;
WR_ADDR2_BAK2 <= WR_ADDR2_BAK1;
if ( WR_ADDR2_BAK1 = WR_ADDR2_BAK2 ) and ( WR_ADDR2_BAK2(3) = '1')
then
RD_STOP <= '0';
end if;
end if;
end process dpIFCLK;
end RTL;
| gpl-3.0 | 2a0f4a672f2ee091148a76bf83918add | 0.494674 | 2.769796 | false | false | false | false |
rpereira-dev/ENSIIE | UE/S3/microarchi/bus_ia_save/terminateurSplit.vhd | 2 | 5,791 | -- ########################################################################
-- $Software: busiac
-- $section : hardware component
-- $Id: terminateurSplit.vhd 322 2015-05-29 06:43:59Z ia $
-- $HeadURL: svn://lunix120.ensiie.fr/ia/cours/archi/projet/busiac/vhdl/terminateurSplit.vhd $
-- $Author : Ivan Auge (Email: [email protected])
-- ########################################################################
--
-- This file is part of the BUSIAC software: Copyright (C) 2010 by I. Auge.
--
-- This program is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at your
-- option) any later version.
--
-- BUSIAC software is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY ; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
-- Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with the GNU C Library; see the file COPYING. If not, write to the Free
-- Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
-- ######################################################################*/
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
-------------------------------------------------------------------------------
-- Ce module récupère un message (????,addrsrc,addrdest,data) sur busin et le
-- découpe en 6 octets B5, B4, B3,B2,B1,B0 puis les envoie 1 par 1 sur RS232out.
-- B0 est le premier octet envoyé, B5 est le dernier octet envoyé.
-- busin[43:40] = control = B5 (0000CCCC)
-- busin[39:32] = adddest = B4
-- busin[31:24] = addrsrc = B3
-- busin[23: 0] = data = B2<<16 | B1<<8 | B0
--
-- Du coté busin, il suit le protocole "poignee de main" (signaux: busin,
-- busin_valid, busin_eated).
-- Du coté RS232out, il suit le protocole du module RS232out (signaux:
-- Data, Ndata, Busy).
-------------------------------------------------------------------------------
ENTITY terminateurSplit IS
PORT(
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
-- interface busin
busin : in STD_LOGIC_VECTOR(43 DOWNTO 0);
busin_valid : in STD_LOGIC;
busin_eated : out STD_LOGIC;
-- interface vers rs232in
Data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
Ndata : OUT STD_LOGIC;
Busy : IN STD_LOGIC);
END terminateurSplit;
ARCHITECTURE Montage OF terminateurSplit IS
-- compteur donnant le nombre d'octets de R deja envoye sur Data
TYPE T_CMD_i IS (NOOP, COUNT, INIT);
SIGNAL CMD_i : T_CMD_i ;
SIGNAL R_i : INTEGER RANGE 0 TO 6;
SIGNAL VT_endLoop: STD_LOGIC;
-- accumule les octets venant de Data.
TYPE T_CMD IS (NOOP, LOAD, SHIFT);
SIGNAL CMD : T_CMD ;
SIGNAL R : STD_LOGIC_VECTOR (47 DOWNTO 0);
-- FSM
TYPE STATE_TYPE IS (
ST_READ_BUSIN, ST_WAIT_NOBUSY, ST_WRITE, ST_LOOP);
SIGNAL state : STATE_TYPE;
BEGIN
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
PROCESS (clk)
BEGIN IF clk'EVENT AND clk = '1' THEN
-- R_i
if ( CMD_i = INIT ) then
R_i <= 6 ;
elsif ( CMD_i = COUNT ) then
R_i <= R_i - 1;
else
R_i <= R_i;
end if;
-- R
if ( CMD = LOAD ) then
R(43 DOWNTO 0) <= busin ;
R(47 DOWNTO 44) <= "0000" ;
elsif ( CMD = SHIFT ) then
R(39 DOWNTO 32) <= R(47 DOWNTO 40);
R(31 DOWNTO 24) <= R(39 DOWNTO 32);
R(23 DOWNTO 16) <= R(31 DOWNTO 24);
R(15 DOWNTO 8) <= R(23 DOWNTO 16);
R( 7 DOWNTO 0) <= R(15 DOWNTO 8);
else
R <= R ;
end if;
END IF; END PROCESS;
VT_endLoop <= '1' when R_i=0 else '0' ;
data <= R(7 DOWNTO 0);
-------------------------------------------------------------------------------
-- Partie Contrôle
-------------------------------------------------------------------------------
-- Inputs: busin_valid Busy
-- Outputs: busin_eated Ndata CMD_i CMD
-------------------------------------------------------------------------------
-- fonction de transitition
PROCESS (reset,clk)
BEGIN
IF reset = '1' THEN
state <= ST_READ_BUSIN;
ELSIF clk'EVENT AND clk = '1' THEN
CASE state IS
WHEN ST_READ_BUSIN =>
IF busin_valid = '1' THEN state <= ST_WAIT_NOBUSY; END IF;
WHEN ST_WAIT_NOBUSY =>
IF Busy /= '1' THEN state <= ST_WRITE; END IF;
WHEN ST_WRITE =>
state <= ST_LOOP;
WHEN ST_LOOP =>
IF VT_endLoop = '1' THEN
state <= ST_READ_BUSIN;
ELSE
state <= ST_WAIT_NOBUSY;
END IF;
END CASE;
END IF;
END PROCESS;
-- fonction de sortie
WITH state SELECT busin_eated <=
'1' WHEN ST_READ_BUSIN,
'0' WHEN OTHERS;
WITH state SELECT Ndata <=
'1' WHEN ST_WRITE,
'0' WHEN OTHERS;
WITH state SELECT CMD_i <=
INIT WHEN ST_READ_BUSIN,
COUNT WHEN ST_WRITE,
NOOP WHEN OTHERS;
WITH state SELECT CMD <=
LOAD WHEN ST_READ_BUSIN,
SHIFT WHEN ST_WRITE,
NOOP WHEN OTHERS;
END Montage;
| gpl-3.0 | 5e1aad9aec89e8100bfb350303a1bca6 | 0.477516 | 4.009709 | false | false | false | false |
DaveyPocket/btrace448 | btrace/datapath.vhd | 1 | 5,725 | -- Btrace 448
-- Datapath
--
-- Bradley Boccuzzi
-- 2016
library ieee;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.btrace_pack.all;
entity datapath is
port(clk, rst: in std_logic;
-- Control inputs
init_x, init_y, inc_x, inc_y: in std_logic;
set_vector, set_org: in std_logic;
next_obj, start_search: in std_logic;
clr_z_reg, clr_hit: in std_logic;
store: in std_logic;
paint: in std_logic;
-- External inputs
e_set_camera: in std_logic;
e_camera_point: in point;
e_set_obj: in std_logic;
e_obj_addr: in std_logic_vector(3 downto 0);
e_obj_data: in object;
e_set_max: in std_logic;
e_max_objects: in std_logic_vector(3 downto 0);
-- Status outputs
last_x, last_y, last_obj, obj_valid: out std_logic;
-- External outputs
hsync, vsync: out std_logic;
rgb: out std_logic_vector(11 downto 0);
-- For debugging only, do not include in top level
d_rgb: out std_logic_vector(11 downto 0);
d_px, d_py: out std_logic_vector(8 downto 0));
end datapath;
architecture arch of datapath is
constant int, frac: integer := 16;
constant w_px: integer := 9;
constant w_py: integer := 8;
constant w_obj_count: integer := 4;
constant w_t: integer := 32;
constant screen_z: sfixed := to_sfixed(0, 15, -16);
constant screen_width: std_logic_vector(8 downto 0) := '1' & x"40";
constant screen_height: std_logic_vector(7 downto 0) := x"F0";
constant max_distance: std_logic_vector(w_t-1 downto 0) := std_logic_vector(to_unsigned(500000, w_t));
constant pre_cat_x: std_logic_vector(15 - w_px downto 0) := (others => '0');
constant post_cat: std_logic_vector(15 downto 0) := (others => '0');
constant pre_cat_y: std_logic_vector(15 - w_py downto 0) := (others => '0');
signal px, x: std_logic_vector(w_px-1 downto 0);
signal pixel_x, pixel_y: std_logic_vector(9 downto 0);
signal py, y: std_logic_vector(w_py-1 downto 0);
signal camera_point, pre_point, origin: point;
signal subx, suby, subz: sfixed(int downto -frac); -- No int-1 due to carry bit
signal pre_vector, direction_vector: vector;
signal i: std_logic_vector(w_obj_count-1 downto 0);
signal obj_close, obj_hit, and_out: std_logic;
signal z_temp, t_std: std_logic_vector(31 downto 0);
signal obj_temp, object_records: object;
--signal t: sfixed(15 downto -16);
signal hit_something, video_on, p_tick, overlay_on: std_logic;
signal color_mux, buf_out, overlay_out, rgb_overlay: std_logic_vector(11 downto 0);
signal cat_x, cat_y: std_logic_vector(31 downto 0);
signal max_objects: std_logic_vector(w_obj_count-1 downto 0);
begin
-- Ray generator--
-- x_counter
x_counter: entity work.counter generic map(w_px) port map(clk, rst, init_x, inc_x, '0', "000000000", px);
-- y_counter
y_counter: entity work.counter generic map(w_py) port map(clk, rst, init_y, inc_y, '0', x"00", py);
-- comp_x
last_x <= '1' when (px = std_logic_vector(unsigned(screen_width) - 1)) else '0';
-- comp_y
last_y <= '1' when (py = std_logic_vector(unsigned(screen_height) - 1)) else '0';
-- x
x <= std_logic_vector(unsigned(px) - unsigned(('0' & screen_width(8 downto 1))));
-- y
y <= std_logic_vector(unsigned(py) - unsigned(('0' & screen_height(7 downto 1))));
-- camera_reg
camera_reg: entity work.point_reg port map(clk, rst, e_set_camera, e_camera_point, camera_point);
-- subx
cat_x <= pre_cat_x & x & post_cat;
subx <= to_sfixed(cat_x, 15, -16) - camera_point.x;
-- suby
cat_y <= pre_cat_y & y & post_cat;
suby <= to_sfixed(cat_y, 15, -16) - camera_point.y;
-- subz
subz <= screen_z - camera_point.z;
-- pre_vector
pre_vector.m_x <= subx(15 downto -16);
pre_vector.m_y <= suby(15 downto -16);
pre_vector.m_z <= subz(15 downto -16);
-- vector_reg
vect_reg: entity work.vector_reg port map(clk, rst, set_vector, pre_vector, direction_vector);
-- pre_point
pre_point.x <= to_sfixed(cat_x, 15, -16);
pre_point.y <= to_sfixed(cat_y, 15, -16);
pre_point.z <= screen_z;
-- origin_reg
origin_reg: entity work.point_reg port map(clk, rst, set_org, pre_point, origin);
-- i_reg
i_counter: entity work.counter generic map (w_obj_count) port map(clk, rst, start_search, next_obj, '0', x"0", i);
-- comp_i
last_obj <= '1' when (i = max_objects) else '0';
-- z_temp_reg
z_temp_reg: entity work.reg generic map(32) port map(clk, rst, store, clr_z_reg, t_std, z_temp, max_distance);
-- comp_t
obj_close <= '1' when (signed(t_std) < signed(z_temp)) else '0';
-- store
and_out <= obj_hit and obj_close;
obj_valid <= and_out;
-- hit_reg
hit_reg: entity work.dff port map(hit_something, clk, and_out, rst, clr_hit, hit_something);
-- obj_temp_reg
obj_temp_reg: entity work.object_reg port map(clk, rst, store, object_records, obj_temp);
-- Sphere generator
sphere_generator: entity work.sphere_gen generic map(16, 16) port map(clk, direction_vector, origin, object_records, t_std, obj_hit);
-- Object record table
object_record_tab: entity work.object_table port map(clk, e_set_obj, i, e_obj_addr, e_obj_data, object_records);
-- screen
screen: entity work.frame_buf port map (clk, paint, color_mux, buf_out, px, py, pixel_x(9 downto 1), pixel_y(8 downto 1));
-- vga_sync
vga_device: entity work.vga_sync port map(clk, rst, hsync, vsync, video_on, p_tick, pixel_x, pixel_y);
-- Multiplexers
color_mux <= obj_temp.color when hit_something = '1' else x"00F";
overlay_out <= buf_out when overlay_on = '0' else rgb_overlay;
rgb <= overlay_out when video_on = '1' else x"000";
-- Max object register
max_obj: entity work.reg generic map(4) port map(clk, rst, e_set_max, '0', e_max_objects, max_objects, x"0");
-- Temporary
overlay_on <= '0';
d_rgb <= color_mux;
d_px <= px;
d_py <= '0' & py;
end arch;
| gpl-3.0 | 12edabd19996ab13c47b2505fd8f0a54 | 0.667424 | 2.632184 | false | false | false | false |
boztalay/OldProjects | FPGA/Subsystems/Subsys_Adder/netgen/synthesis/Subsys_Adder_synthesis.vhd | 1 | 10,730 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: K.31
-- \ \ Application: netgen
-- / / Filename: Subsys_Adder_synthesis.vhd
-- /___/ /\ Timestamp: Sun Apr 12 03:25:34 2009
-- \ \ / \
-- \___\/\___\
--
-- Command : -intstyle ise -ar Structure -tm Subsys_Adder -w -dir netgen/synthesis -ofmt vhdl -sim Subsys_Adder.ngc Subsys_Adder_synthesis.vhd
-- Device : xc3s500e-4-fg320
-- Input file : Subsys_Adder.ngc
-- Output file : C:\Users\Ben\Desktop\FPGAprojects\Subsystems\Subsys_Adder\netgen\synthesis\Subsys_Adder_synthesis.vhd
-- # of Entities : 1
-- Design Name : Subsys_Adder
-- Xilinx : C:\Xilinx\10.1\ISE
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Development System Reference Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity Subsys_Adder is
port (
CLK1 : in STD_LOGIC := 'X';
CLK2 : in STD_LOGIC := 'X';
ano : out STD_LOGIC_VECTOR ( 3 downto 0 );
seg : out STD_LOGIC_VECTOR ( 6 downto 0 );
N1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
N2 : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end Subsys_Adder;
architecture Structure of Subsys_Adder is
signal CLK1_IBUF_1 : STD_LOGIC;
signal CLK2_IBUF_3 : STD_LOGIC;
signal G1_G1_S3 : STD_LOGIC;
signal G1_G2_S3 : STD_LOGIC;
signal G1_G3_S3 : STD_LOGIC;
signal G2_G1_S3 : STD_LOGIC;
signal G2_G2_S3 : STD_LOGIC;
signal G2_G3_S3 : STD_LOGIC;
signal G6_G1_S3 : STD_LOGIC;
signal G6_G2_G4_Q : STD_LOGIC;
signal G6_G2_S3 : STD_LOGIC;
signal G6_G3_G4_Q : STD_LOGIC;
signal G6_G3_G4_Q1_14 : STD_LOGIC;
signal G6_G3_S3 : STD_LOGIC;
signal G6_G4_G4_Q : STD_LOGIC;
signal G6_G4_G4_Q1_17 : STD_LOGIC;
signal G6_G4_S3 : STD_LOGIC;
signal G7_Mrom_seg : STD_LOGIC;
signal G7_Mrom_seg1 : STD_LOGIC;
signal G7_Mrom_seg2 : STD_LOGIC;
signal G7_Mrom_seg3 : STD_LOGIC;
signal G7_Mrom_seg4 : STD_LOGIC;
signal G7_Mrom_seg5 : STD_LOGIC;
signal G7_Mrom_seg6 : STD_LOGIC;
signal N0 : STD_LOGIC;
signal N11 : STD_LOGIC;
signal N1_0_IBUF_31 : STD_LOGIC;
signal N1_1_IBUF_32 : STD_LOGIC;
signal N1_2_IBUF_33 : STD_LOGIC;
signal N2_0_IBUF_37 : STD_LOGIC;
signal N2_1_IBUF_38 : STD_LOGIC;
signal N2_2_IBUF_39 : STD_LOGIC;
signal S1 : STD_LOGIC;
signal S14 : STD_LOGIC;
signal S15 : STD_LOGIC;
signal S16 : STD_LOGIC;
signal S17 : STD_LOGIC;
signal S2 : STD_LOGIC;
signal S3 : STD_LOGIC;
signal S4 : STD_LOGIC;
signal S5 : STD_LOGIC;
signal S6 : STD_LOGIC;
signal S8 : STD_LOGIC;
begin
XST_GND : GND
port map (
G => N0
);
XST_VCC : VCC
port map (
P => N11
);
G6_G4_G7_Q1 : LUT3
generic map(
INIT => X"4E"
)
port map (
I0 => CLK2_IBUF_3,
I1 => S17,
I2 => G6_G4_S3,
O => S17
);
G6_G3_G7_Q1 : LUT3
generic map(
INIT => X"4E"
)
port map (
I0 => CLK2_IBUF_3,
I1 => S16,
I2 => G6_G3_S3,
O => S16
);
G6_G2_G7_Q1 : LUT3
generic map(
INIT => X"4E"
)
port map (
I0 => CLK2_IBUF_3,
I1 => S15,
I2 => G6_G2_S3,
O => S15
);
G6_G1_G7_Q1 : LUT3
generic map(
INIT => X"4E"
)
port map (
I0 => CLK2_IBUF_3,
I1 => S14,
I2 => G6_G1_S3,
O => S14
);
G2_G3_G7_Q1 : LUT3
generic map(
INIT => X"4E"
)
port map (
I0 => CLK1_IBUF_1,
I1 => S6,
I2 => G2_G3_S3,
O => S6
);
G2_G3_G4_Q1 : LUT3
generic map(
INIT => X"B1"
)
port map (
I0 => CLK1_IBUF_1,
I1 => N2_2_IBUF_39,
I2 => G2_G3_S3,
O => G2_G3_S3
);
G2_G2_G7_Q1 : LUT3
generic map(
INIT => X"4E"
)
port map (
I0 => CLK1_IBUF_1,
I1 => S5,
I2 => G2_G2_S3,
O => S5
);
G2_G2_G4_Q1 : LUT3
generic map(
INIT => X"B1"
)
port map (
I0 => CLK1_IBUF_1,
I1 => N2_1_IBUF_38,
I2 => G2_G2_S3,
O => G2_G2_S3
);
G2_G1_G7_Q1 : LUT3
generic map(
INIT => X"4E"
)
port map (
I0 => CLK1_IBUF_1,
I1 => S4,
I2 => G2_G1_S3,
O => S4
);
G2_G1_G4_Q1 : LUT3
generic map(
INIT => X"B1"
)
port map (
I0 => CLK1_IBUF_1,
I1 => N2_0_IBUF_37,
I2 => G2_G1_S3,
O => G2_G1_S3
);
G1_G3_G7_Q1 : LUT3
generic map(
INIT => X"4E"
)
port map (
I0 => CLK1_IBUF_1,
I1 => S3,
I2 => G1_G3_S3,
O => S3
);
G1_G3_G4_Q1 : LUT3
generic map(
INIT => X"B1"
)
port map (
I0 => CLK1_IBUF_1,
I1 => N1_2_IBUF_33,
I2 => G1_G3_S3,
O => G1_G3_S3
);
G1_G2_G7_Q1 : LUT3
generic map(
INIT => X"4E"
)
port map (
I0 => CLK1_IBUF_1,
I1 => S2,
I2 => G1_G2_S3,
O => S2
);
G1_G2_G4_Q1 : LUT3
generic map(
INIT => X"B1"
)
port map (
I0 => CLK1_IBUF_1,
I1 => N1_1_IBUF_32,
I2 => G1_G2_S3,
O => G1_G2_S3
);
G1_G1_G7_Q1 : LUT3
generic map(
INIT => X"4E"
)
port map (
I0 => CLK1_IBUF_1,
I1 => S1,
I2 => G1_G1_S3,
O => S1
);
G1_G1_G4_Q1 : LUT3
generic map(
INIT => X"B1"
)
port map (
I0 => CLK1_IBUF_1,
I1 => N1_0_IBUF_31,
I2 => G1_G1_S3,
O => G1_G1_S3
);
G4_G5_Q1 : LUT4
generic map(
INIT => X"EA80"
)
port map (
I0 => S2,
I1 => S1,
I2 => S4,
I3 => S5,
O => S8
);
G7_Mrom_seg41 : LUT4
generic map(
INIT => X"454C"
)
port map (
I0 => S17,
I1 => S14,
I2 => S15,
I3 => S16,
O => G7_Mrom_seg4
);
G6_G1_G4_Q1 : LUT4
generic map(
INIT => X"EB41"
)
port map (
I0 => CLK2_IBUF_3,
I1 => S1,
I2 => S4,
I3 => G6_G1_S3,
O => G6_G1_S3
);
G7_Mrom_seg21 : LUT4
generic map(
INIT => X"80C2"
)
port map (
I0 => S15,
I1 => S17,
I2 => S16,
I3 => S14,
O => G7_Mrom_seg2
);
G7_Mrom_seg61 : LUT4
generic map(
INIT => X"0941"
)
port map (
I0 => S15,
I1 => S16,
I2 => S17,
I3 => S14,
O => G7_Mrom_seg6
);
G7_Mrom_seg51 : LUT4
generic map(
INIT => X"6032"
)
port map (
I0 => S15,
I1 => S17,
I2 => S14,
I3 => S16,
O => G7_Mrom_seg5
);
G7_Mrom_seg111 : LUT4
generic map(
INIT => X"B860"
)
port map (
I0 => S17,
I1 => S14,
I2 => S16,
I3 => S15,
O => G7_Mrom_seg1
);
G7_Mrom_seg31 : LUT4
generic map(
INIT => X"9086"
)
port map (
I0 => S14,
I1 => S16,
I2 => S15,
I3 => S17,
O => G7_Mrom_seg3
);
G7_Mrom_seg11 : LUT4
generic map(
INIT => X"2812"
)
port map (
I0 => S14,
I1 => S15,
I2 => S16,
I3 => S17,
O => G7_Mrom_seg
);
CLK1_IBUF : IBUF
port map (
I => CLK1,
O => CLK1_IBUF_1
);
CLK2_IBUF : IBUF
port map (
I => CLK2,
O => CLK2_IBUF_3
);
N1_2_IBUF : IBUF
port map (
I => N1(2),
O => N1_2_IBUF_33
);
N1_1_IBUF : IBUF
port map (
I => N1(1),
O => N1_1_IBUF_32
);
N1_0_IBUF : IBUF
port map (
I => N1(0),
O => N1_0_IBUF_31
);
N2_2_IBUF : IBUF
port map (
I => N2(2),
O => N2_2_IBUF_39
);
N2_1_IBUF : IBUF
port map (
I => N2(1),
O => N2_1_IBUF_38
);
N2_0_IBUF : IBUF
port map (
I => N2(0),
O => N2_0_IBUF_37
);
ano_3_OBUF : OBUF
port map (
I => N11,
O => ano(3)
);
ano_2_OBUF : OBUF
port map (
I => N11,
O => ano(2)
);
ano_1_OBUF : OBUF
port map (
I => N11,
O => ano(1)
);
ano_0_OBUF : OBUF
port map (
I => N0,
O => ano(0)
);
seg_6_OBUF : OBUF
port map (
I => G7_Mrom_seg6,
O => seg(6)
);
seg_5_OBUF : OBUF
port map (
I => G7_Mrom_seg5,
O => seg(5)
);
seg_4_OBUF : OBUF
port map (
I => G7_Mrom_seg4,
O => seg(4)
);
seg_3_OBUF : OBUF
port map (
I => G7_Mrom_seg3,
O => seg(3)
);
seg_2_OBUF : OBUF
port map (
I => G7_Mrom_seg2,
O => seg(2)
);
seg_1_OBUF : OBUF
port map (
I => G7_Mrom_seg1,
O => seg(1)
);
seg_0_OBUF : OBUF
port map (
I => G7_Mrom_seg,
O => seg(0)
);
G6_G4_G4_Q1 : LUT4
generic map(
INIT => X"888D"
)
port map (
I0 => CLK2_IBUF_3,
I1 => G6_G4_S3,
I2 => S6,
I3 => S3,
O => G6_G4_G4_Q
);
G6_G4_G4_Q2 : LUT4
generic map(
INIT => X"B1F5"
)
port map (
I0 => CLK2_IBUF_3,
I1 => S3,
I2 => G6_G4_S3,
I3 => S6,
O => G6_G4_G4_Q1_17
);
G6_G4_G4_Q_f5 : MUXF5
port map (
I0 => G6_G4_G4_Q1_17,
I1 => G6_G4_G4_Q,
S => S8,
O => G6_G4_S3
);
G6_G3_G4_Q1 : LUT4
generic map(
INIT => X"BE14"
)
port map (
I0 => CLK2_IBUF_3,
I1 => S6,
I2 => S3,
I3 => G6_G3_S3,
O => G6_G3_G4_Q
);
G6_G3_G4_Q2 : LUT4
generic map(
INIT => X"EB41"
)
port map (
I0 => CLK2_IBUF_3,
I1 => S6,
I2 => S3,
I3 => G6_G3_S3,
O => G6_G3_G4_Q1_14
);
G6_G3_G4_Q_f5 : MUXF5
port map (
I0 => G6_G3_G4_Q1_14,
I1 => G6_G3_G4_Q,
S => S8,
O => G6_G3_S3
);
G6_G2_G4_Q1 : LUT4
generic map(
INIT => X"69A5"
)
port map (
I0 => S2,
I1 => S4,
I2 => S5,
I3 => S1,
O => G6_G2_G4_Q
);
G6_G2_G4_Q_f5 : MUXF5
port map (
I0 => G6_G2_G4_Q,
I1 => G6_G2_S3,
S => CLK2_IBUF_3,
O => G6_G2_S3
);
end Structure;
| mit | ce2f2600ef95e88129043befc9252248 | 0.451445 | 2.554762 | false | false | false | false |
bargei/NoC264 | NoC264_3x3/priority_encoder.vhd | 1 | 1,235 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity priority_encoder is
generic(
encoded_word_size : integer := 2
);
Port(
input : in std_logic_vector(2**encoded_word_size-1 downto 0);
output : out std_logic_vector(encoded_word_size-1 downto 0)
);
end entity priority_encoder;
architecture rtl of priority_encoder is
signal any_previous : std_logic_vector(2**encoded_word_size-1 downto 0);
signal highest_bit_only : std_logic_vector(2**encoded_word_size-1 downto 0);
type encoded_sig_type is array(2**encoded_word_size-1 downto 0) of std_logic_vector(encoded_word_size-1 downto 0);
signal encoded_sig : encoded_sig_type;
begin
any_previous(2**encoded_word_size-1) <= input(2**encoded_word_size-1);
encoded_sig(2**encoded_word_size-1) <= std_logic_vector(to_unsigned(2**encoded_word_size-1, encoded_word_size));
encode: for i in 2**encoded_word_size-2 downto 0 generate
begin
any_previous(i) <= input(i) or any_previous(i+1);
encoded_sig(i) <= std_logic_vector(to_unsigned(i, encoded_word_size)) when any_previous(i+1) = '0' else encoded_sig(i+1);
end generate;
output <= encoded_sig(0);
end architecture rtl; | mit | 6b020de1c4718080599ec560ec38a016 | 0.680972 | 3.0875 | false | false | false | false |
freecores/line_codes | rtl/vhdl/ami_enc.vhd | 1 | 557 |
-- implementation of the AMI encoder.
entity ami_enc is
port (
clr_bar,
clk : in bit; -- clock input.
e : in bit; -- input.
s0, s1 : out bit -- output.
);
end ami_enc;
architecture behaviour of ami_enc is
signal q : bit; -- 1 flipflops for 2 states.
begin
process (clk, clr_bar) begin
if clr_bar = '0' then
q <= '0';
s1 <= '0';
s0 <= '0';
elsif clk'event and clk = '1' then
q <= q xor e;
s1 <= q and e;
s0 <= e and (not q);
end if;
end process;
end behaviour;
| gpl-2.0 | 475066c190794f2ac506325c8e08f63b | 0.518851 | 2.717073 | false | false | false | false |
bargei/NoC264 | NoC264_2x2/NoC_264_SoC.vhd | 1 | 107,639 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
ENTITY NoC_264_SoC IS
PORT(
---------fpga connections-------------
clock_50: in std_logic;
sw:in std_logic_vector(9 downto 0);
ledr: out std_logic_vector(9 downto 0);
---------hps connections---------------
hps_conv_usb_n:inout std_logic;
hps_ddr3_addr:out std_logic_vector(14 downto 0);
hps_ddr3_ba: out std_logic_vector(2 downto 0);
hps_ddr3_cas_n: out std_logic;
hps_ddr3_cke:out std_logic;
hps_ddr3_ck_n: out std_logic;
hps_ddr3_ck_p: out std_logic;
hps_ddr3_cs_n: out std_logic;
hps_ddr3_dm: out std_logic_vector(3 downto 0);
hps_ddr3_dq: inout std_logic_vector(31 downto 0);
hps_ddr3_dqs_n: inout std_logic_vector(3 downto 0);
hps_ddr3_dqs_p: inout std_logic_vector(3 downto 0);
hps_ddr3_odt: out std_logic;
hps_ddr3_ras_n: out std_logic;
hps_ddr3_reset_n: out std_logic;
hps_ddr3_rzq: in std_logic;
hps_ddr3_we_n: out std_logic;
hps_enet_gtx_clk: out std_logic;
hps_enet_int_n:inout std_logic;
hps_enet_mdc:out std_logic;
hps_enet_mdio:inout std_logic;
hps_enet_rx_clk: in std_logic;
hps_enet_rx_data: in std_logic_vector(3 downto 0);
hps_enet_rx_dv: in std_logic;
hps_enet_tx_data: out std_logic_vector(3 downto 0);
hps_enet_tx_en: out std_logic;
hps_key: inout std_logic;
hps_sd_clk: out std_logic;
hps_sd_cmd: inout std_logic;
hps_sd_data: inout std_logic_vector(3 downto 0);
hps_uart_rx: in std_logic;
hps_uart_tx: out std_logic;
hps_usb_clkout: in std_logic;
hps_usb_data:inout std_logic_vector(7 downto 0);
hps_usb_dir: in std_logic;
hps_usb_nxt: in std_logic;
hps_usb_stp: out std_logic;
VGA_CLK : out std_logic;
VGA_HS : out std_logic;
VGA_VS : out std_logic;
VGA_BLANK_N : out std_logic;
VGA_SYNC_N : out std_logic;
VGA_R : out std_logic_vector(7 downto 0);
VGA_G : out std_logic_vector(7 downto 0);
VGA_B : out std_logic_vector(7 downto 0)
);
END NoC_264_SoC;
architecture main of NoC_264_SoC is
-- constants
constant data_width : integer := 64;
constant addr_width : integer := 4;
constant vc_sel_width : integer := 1;
constant num_vc : integer := 2;
constant flit_buff_depth : integer := 8;
component hps_fpga is
port (
clk_clk : in std_logic := '0'; -- clk.clk
cpu_0_rx_0_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- cpu_0_rx_0_external_connection.export
cpu_0_rx_1_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- cpu_0_rx_1_external_connection.export
cpu_0_rx_2_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- cpu_0_rx_2_external_connection.export
cpu_0_rx_3_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- cpu_0_rx_3_external_connection.export
cpu_0_rx_4_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- cpu_0_rx_4_external_connection.export
cpu_0_rx_5_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- cpu_0_rx_5_external_connection.export
cpu_0_rx_6_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- cpu_0_rx_6_external_connection.export
cpu_0_rx_7_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- cpu_0_rx_7_external_connection.export
cpu_0_tx_0_external_connection_export : out std_logic_vector(31 downto 0); -- cpu_0_tx_0_external_connection.export
cpu_0_tx_1_external_connection_export : out std_logic_vector(31 downto 0); -- cpu_0_tx_1_external_connection.export
cpu_0_tx_2_external_connection_export : out std_logic_vector(31 downto 0); -- cpu_0_tx_2_external_connection.export
cpu_0_tx_3_external_connection_export : out std_logic_vector(31 downto 0); -- cpu_0_tx_3_external_connection.export
cpu_0_tx_4_external_connection_export : out std_logic_vector(31 downto 0); -- cpu_0_tx_4_external_connection.export
cpu_0_tx_5_external_connection_export : out std_logic_vector(31 downto 0); -- cpu_0_tx_5_external_connection.export
cpu_0_tx_6_external_connection_export : out std_logic_vector(31 downto 0); -- cpu_0_tx_6_external_connection.export
cpu_0_tx_7_external_connection_export : out std_logic_vector(31 downto 0); -- cpu_0_tx_7_external_connection.export
cpu_1_rx_0_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- cpu_1_rx_0_external_connection.export
cpu_1_rx_1_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- cpu_1_rx_1_external_connection.export
cpu_1_rx_2_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- cpu_1_rx_2_external_connection.export
cpu_1_rx_3_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- cpu_1_rx_3_external_connection.export
cpu_1_rx_4_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- cpu_1_rx_4_external_connection.export
cpu_1_rx_5_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- cpu_1_rx_5_external_connection.export
cpu_1_rx_6_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- cpu_1_rx_6_external_connection.export
cpu_1_rx_7_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- cpu_1_rx_7_external_connection.export
cpu_1_tx_0_external_connection_export : out std_logic_vector(31 downto 0); -- cpu_1_tx_0_external_connection.export
cpu_1_tx_1_external_connection_export : out std_logic_vector(31 downto 0); -- cpu_1_tx_1_external_connection.export
cpu_1_tx_2_external_connection_export : out std_logic_vector(31 downto 0); -- cpu_1_tx_2_external_connection.export
cpu_1_tx_3_external_connection_export : out std_logic_vector(31 downto 0); -- cpu_1_tx_3_external_connection.export
cpu_1_tx_4_external_connection_export : out std_logic_vector(31 downto 0); -- cpu_1_tx_4_external_connection.export
cpu_1_tx_5_external_connection_export : out std_logic_vector(31 downto 0); -- cpu_1_tx_5_external_connection.export
cpu_1_tx_6_external_connection_export : out std_logic_vector(31 downto 0); -- cpu_1_tx_6_external_connection.export
cpu_1_tx_7_external_connection_export : out std_logic_vector(31 downto 0); -- cpu_1_tx_7_external_connection.export
hps_0_h2f_reset_reset_n : out std_logic; -- hps_0_h2f_reset.reset_n
hps_io_hps_io_emac1_inst_TX_CLK : out std_logic; -- hps_io.hps_io_emac1_inst_TX_CLK
hps_io_hps_io_emac1_inst_TXD0 : out std_logic; -- .hps_io_emac1_inst_TXD0
hps_io_hps_io_emac1_inst_TXD1 : out std_logic; -- .hps_io_emac1_inst_TXD1
hps_io_hps_io_emac1_inst_TXD2 : out std_logic; -- .hps_io_emac1_inst_TXD2
hps_io_hps_io_emac1_inst_TXD3 : out std_logic; -- .hps_io_emac1_inst_TXD3
hps_io_hps_io_emac1_inst_RXD0 : in std_logic := '0'; -- .hps_io_emac1_inst_RXD0
hps_io_hps_io_emac1_inst_MDIO : inout std_logic := '0'; -- .hps_io_emac1_inst_MDIO
hps_io_hps_io_emac1_inst_MDC : out std_logic; -- .hps_io_emac1_inst_MDC
hps_io_hps_io_emac1_inst_RX_CTL : in std_logic := '0'; -- .hps_io_emac1_inst_RX_CTL
hps_io_hps_io_emac1_inst_TX_CTL : out std_logic; -- .hps_io_emac1_inst_TX_CTL
hps_io_hps_io_emac1_inst_RX_CLK : in std_logic := '0'; -- .hps_io_emac1_inst_RX_CLK
hps_io_hps_io_emac1_inst_RXD1 : in std_logic := '0'; -- .hps_io_emac1_inst_RXD1
hps_io_hps_io_emac1_inst_RXD2 : in std_logic := '0'; -- .hps_io_emac1_inst_RXD2
hps_io_hps_io_emac1_inst_RXD3 : in std_logic := '0'; -- .hps_io_emac1_inst_RXD3
hps_io_hps_io_sdio_inst_CMD : inout std_logic := '0'; -- .hps_io_sdio_inst_CMD
hps_io_hps_io_sdio_inst_D0 : inout std_logic := '0'; -- .hps_io_sdio_inst_D0
hps_io_hps_io_sdio_inst_D1 : inout std_logic := '0'; -- .hps_io_sdio_inst_D1
hps_io_hps_io_sdio_inst_CLK : out std_logic; -- .hps_io_sdio_inst_CLK
hps_io_hps_io_sdio_inst_D2 : inout std_logic := '0'; -- .hps_io_sdio_inst_D2
hps_io_hps_io_sdio_inst_D3 : inout std_logic := '0'; -- .hps_io_sdio_inst_D3
hps_io_hps_io_usb1_inst_D0 : inout std_logic := '0'; -- .hps_io_usb1_inst_D0
hps_io_hps_io_usb1_inst_D1 : inout std_logic := '0'; -- .hps_io_usb1_inst_D1
hps_io_hps_io_usb1_inst_D2 : inout std_logic := '0'; -- .hps_io_usb1_inst_D2
hps_io_hps_io_usb1_inst_D3 : inout std_logic := '0'; -- .hps_io_usb1_inst_D3
hps_io_hps_io_usb1_inst_D4 : inout std_logic := '0'; -- .hps_io_usb1_inst_D4
hps_io_hps_io_usb1_inst_D5 : inout std_logic := '0'; -- .hps_io_usb1_inst_D5
hps_io_hps_io_usb1_inst_D6 : inout std_logic := '0'; -- .hps_io_usb1_inst_D6
hps_io_hps_io_usb1_inst_D7 : inout std_logic := '0'; -- .hps_io_usb1_inst_D7
hps_io_hps_io_usb1_inst_CLK : in std_logic := '0'; -- .hps_io_usb1_inst_CLK
hps_io_hps_io_usb1_inst_STP : out std_logic; -- .hps_io_usb1_inst_STP
hps_io_hps_io_usb1_inst_DIR : in std_logic := '0'; -- .hps_io_usb1_inst_DIR
hps_io_hps_io_usb1_inst_NXT : in std_logic := '0'; -- .hps_io_usb1_inst_NXT
hps_io_hps_io_uart0_inst_RX : in std_logic := '0'; -- .hps_io_uart0_inst_RX
hps_io_hps_io_uart0_inst_TX : out std_logic; -- .hps_io_uart0_inst_TX
led_external_connection_export : out std_logic_vector(9 downto 0); -- led_external_connection.export
memory_mem_a : out std_logic_vector(14 downto 0); -- memory.mem_a
memory_mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba
memory_mem_ck : out std_logic; -- .mem_ck
memory_mem_ck_n : out std_logic; -- .mem_ck_n
memory_mem_cke : out std_logic; -- .mem_cke
memory_mem_cs_n : out std_logic; -- .mem_cs_n
memory_mem_ras_n : out std_logic; -- .mem_ras_n
memory_mem_cas_n : out std_logic; -- .mem_cas_n
memory_mem_we_n : out std_logic; -- .mem_we_n
memory_mem_reset_n : out std_logic; -- .mem_reset_n
memory_mem_dq : inout std_logic_vector(31 downto 0) := (others => '0'); -- .mem_dq
memory_mem_dqs : inout std_logic_vector(3 downto 0) := (others => '0'); -- .mem_dqs
memory_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => '0'); -- .mem_dqs_n
memory_mem_odt : out std_logic; -- .mem_odt
memory_mem_dm : out std_logic_vector(3 downto 0); -- .mem_dm
memory_oct_rzqin : in std_logic := '0'; -- .oct_rzqin
noc_ctrl_0_external_connection_export : out std_logic_vector(31 downto 0); -- noc_ctrl_0_external_connection.export
noc_ctrl_1_external_connection_export : out std_logic_vector(31 downto 0); -- noc_ctrl_1_external_connection.export
noc_status_0_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- noc_status_0_external_connection.export
noc_status_1_external_connection_export : in std_logic_vector(31 downto 0) := (others => '0'); -- noc_status_1_external_connection.export
reset_reset_n : in std_logic := '0'; -- reset.reset_n
sw_external_connection_export : in std_logic_vector(9 downto 0) := (others => '0'); -- sw_external_connection.export
pll_0_outclk0_clk : out std_logic;
noc_clock_clk : out std_logic --
);
end component hps_fpga;
component intra_prediction_node is
generic (
data_width : integer := 128;
addr_width : integer := 1;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
-- recv interface to network
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
-- send interface to network
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic;
--debugging
s_intra_idle : out std_logic;
s_intra_data_rxd : out std_logic;
s_intra_write_sample : out std_logic;
s_intra_start_pred : out std_logic;
s_intra_start_tx_loop : out std_logic;
s_intra_start_tx_loop_hold : out std_logic;
s_intra_tx : out std_logic;
s_intra_tx_hold : out std_logic;
s_intra_tx_gen_next : out std_logic;
s_intra_dequeue_rx : out std_logic
);
end component intra_prediction_node;
component network_interface is
generic(
data_width : integer := 64;
addr_width : integer := 1;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
--clk, reset
clk : in std_logic;
rst : in std_logic;
--user sending interface
send_data : in std_logic_vector(data_width-1 downto 0);
dest_addr : in std_logic_vector(addr_width-1 downto 0);
set_tail_flit : in std_logic;
send_flit : in std_logic;
ready_to_send : out std_logic;
--user receiving interface
recv_data : out std_logic_vector(data_width-1 downto 0);
src_addr : out std_logic_vector(addr_width-1 downto 0);
is_tail_flit : out std_logic;
data_in_buffer : out std_logic_vector(num_vc-1 downto 0);
dequeue : in std_logic_vector(num_vc-1 downto 0);
select_vc_read : in std_logic_vector(vc_sel_width-1 downto 0);
--interface to network
send_putFlit_flit_in : out std_logic_vector(data_width+addr_width+vc_sel_width+1 downto 0);
EN_send_putFlit : out std_logic;
EN_send_getNonFullVCs : out std_logic;
send_getNonFullVCs : in std_logic_vector(num_vc-1 downto 0);
EN_recv_getFlit : out std_logic;
recv_getFlit : in std_logic_vector(data_width+addr_width+vc_sel_width+1 downto 0);
recv_putNonFullVCs_nonFullVCs : out std_logic_vector(num_vc-1 downto 0);
EN_recv_putNonFullVCs : out std_logic;
recv_info_getRecvPortID : in std_logic_vector(addr_width-1 downto 0)
);
end component network_interface;
component mkNetworkSimple is
port(
CLK : in std_logic;
RST_N : in std_logic;
send_ports_0_putFlit_flit_in : in std_logic_vector(70 downto 0);
EN_send_ports_0_putFlit : in std_logic;
EN_send_ports_0_getNonFullVCs : in std_logic;
send_ports_0_getNonFullVCs : out std_logic_vector(1 downto 0);
send_ports_1_putFlit_flit_in : in std_logic_vector(70 downto 0);
EN_send_ports_1_putFlit : in std_logic;
EN_send_ports_1_getNonFullVCs : in std_logic;
send_ports_1_getNonFullVCs : out std_logic_vector(1 downto 0);
send_ports_2_putFlit_flit_in : in std_logic_vector(70 downto 0);
EN_send_ports_2_putFlit : in std_logic;
EN_send_ports_2_getNonFullVCs : in std_logic;
send_ports_2_getNonFullVCs : out std_logic_vector(1 downto 0);
send_ports_3_putFlit_flit_in : in std_logic_vector(70 downto 0);
EN_send_ports_3_putFlit : in std_logic;
EN_send_ports_3_getNonFullVCs : in std_logic;
send_ports_3_getNonFullVCs : out std_logic_vector(1 downto 0);
send_ports_4_putFlit_flit_in : in std_logic_vector(70 downto 0);
EN_send_ports_4_putFlit : in std_logic;
EN_send_ports_4_getNonFullVCs : in std_logic;
send_ports_4_getNonFullVCs : out std_logic_vector(1 downto 0);
send_ports_5_putFlit_flit_in : in std_logic_vector(70 downto 0);
EN_send_ports_5_putFlit : in std_logic;
EN_send_ports_5_getNonFullVCs : in std_logic;
send_ports_5_getNonFullVCs : out std_logic_vector(1 downto 0);
send_ports_6_putFlit_flit_in : in std_logic_vector(70 downto 0);
EN_send_ports_6_putFlit : in std_logic;
EN_send_ports_6_getNonFullVCs : in std_logic;
send_ports_6_getNonFullVCs : out std_logic_vector(1 downto 0);
send_ports_7_putFlit_flit_in : in std_logic_vector(70 downto 0);
EN_send_ports_7_putFlit : in std_logic;
EN_send_ports_7_getNonFullVCs : in std_logic;
send_ports_7_getNonFullVCs : out std_logic_vector(1 downto 0);
send_ports_8_putFlit_flit_in : in std_logic_vector(70 downto 0);
EN_send_ports_8_putFlit : in std_logic;
EN_send_ports_8_getNonFullVCs : in std_logic;
send_ports_8_getNonFullVCs : out std_logic_vector(1 downto 0);
send_ports_9_putFlit_flit_in : in std_logic_vector(70 downto 0);
EN_send_ports_9_putFlit : in std_logic;
EN_send_ports_9_getNonFullVCs : in std_logic;
send_ports_9_getNonFullVCs : out std_logic_vector(1 downto 0);
send_ports_10_putFlit_flit_in : in std_logic_vector(70 downto 0);
EN_send_ports_10_putFlit : in std_logic;
EN_send_ports_10_getNonFullVCs : in std_logic;
send_ports_10_getNonFullVCs : out std_logic_vector(1 downto 0);
send_ports_11_putFlit_flit_in : in std_logic_vector(70 downto 0);
EN_send_ports_11_putFlit : in std_logic;
EN_send_ports_11_getNonFullVCs : in std_logic;
send_ports_11_getNonFullVCs : out std_logic_vector(1 downto 0);
EN_recv_ports_0_getFlit : in std_logic;
recv_ports_0_getFlit : out std_logic_vector(70 downto 0);
recv_ports_0_putNonFullVCs_nonFullVCs : in std_logic_vector(1 downto 0);
EN_recv_ports_0_putNonFullVCs : in std_logic;
EN_recv_ports_1_getFlit : in std_logic;
recv_ports_1_getFlit : out std_logic_vector(70 downto 0);
recv_ports_1_putNonFullVCs_nonFullVCs : in std_logic_vector(1 downto 0);
EN_recv_ports_1_putNonFullVCs : in std_logic;
EN_recv_ports_2_getFlit : in std_logic;
recv_ports_2_getFlit : out std_logic_vector(70 downto 0);
recv_ports_2_putNonFullVCs_nonFullVCs : in std_logic_vector(1 downto 0);
EN_recv_ports_2_putNonFullVCs : in std_logic;
EN_recv_ports_3_getFlit : in std_logic;
recv_ports_3_getFlit : out std_logic_vector(70 downto 0);
recv_ports_3_putNonFullVCs_nonFullVCs : in std_logic_vector(1 downto 0);
EN_recv_ports_3_putNonFullVCs : in std_logic;
EN_recv_ports_4_getFlit : in std_logic;
recv_ports_4_getFlit : out std_logic_vector(70 downto 0);
recv_ports_4_putNonFullVCs_nonFullVCs : in std_logic_vector(1 downto 0);
EN_recv_ports_4_putNonFullVCs : in std_logic;
EN_recv_ports_5_getFlit : in std_logic;
recv_ports_5_getFlit : out std_logic_vector(70 downto 0);
recv_ports_5_putNonFullVCs_nonFullVCs : in std_logic_vector(1 downto 0);
EN_recv_ports_5_putNonFullVCs : in std_logic;
EN_recv_ports_6_getFlit : in std_logic;
recv_ports_6_getFlit : out std_logic_vector(70 downto 0);
recv_ports_6_putNonFullVCs_nonFullVCs : in std_logic_vector(1 downto 0);
EN_recv_ports_6_putNonFullVCs : in std_logic;
EN_recv_ports_7_getFlit : in std_logic;
recv_ports_7_getFlit : out std_logic_vector(70 downto 0);
recv_ports_7_putNonFullVCs_nonFullVCs : in std_logic_vector(1 downto 0);
EN_recv_ports_7_putNonFullVCs : in std_logic;
EN_recv_ports_8_getFlit : in std_logic;
recv_ports_8_getFlit : out std_logic_vector(70 downto 0);
recv_ports_8_putNonFullVCs_nonFullVCs : in std_logic_vector(1 downto 0);
EN_recv_ports_8_putNonFullVCs : in std_logic;
EN_recv_ports_9_getFlit : in std_logic;
recv_ports_9_getFlit : out std_logic_vector(70 downto 0);
recv_ports_9_putNonFullVCs_nonFullVCs : in std_logic_vector(1 downto 0);
EN_recv_ports_9_putNonFullVCs : in std_logic;
EN_recv_ports_10_getFlit : in std_logic;
recv_ports_10_getFlit : out std_logic_vector(70 downto 0);
recv_ports_10_putNonFullVCs_nonFullVCs : in std_logic_vector(1 downto 0);
EN_recv_ports_10_putNonFullVCs : in std_logic;
EN_recv_ports_11_getFlit : in std_logic;
recv_ports_11_getFlit : out std_logic_vector(70 downto 0);
recv_ports_11_putNonFullVCs_nonFullVCs : in std_logic_vector(1 downto 0);
EN_recv_ports_11_putNonFullVCs : in std_logic;
recv_ports_info_0_getRecvPortID : out std_logic_vector(3 downto 0);
recv_ports_info_1_getRecvPortID : out std_logic_vector(3 downto 0);
recv_ports_info_2_getRecvPortID : out std_logic_vector(3 downto 0);
recv_ports_info_3_getRecvPortID : out std_logic_vector(3 downto 0);
recv_ports_info_4_getRecvPortID : out std_logic_vector(3 downto 0);
recv_ports_info_5_getRecvPortID : out std_logic_vector(3 downto 0);
recv_ports_info_6_getRecvPortID : out std_logic_vector(3 downto 0);
recv_ports_info_7_getRecvPortID : out std_logic_vector(3 downto 0);
recv_ports_info_8_getRecvPortID : out std_logic_vector(3 downto 0);
recv_ports_info_9_getRecvPortID : out std_logic_vector(3 downto 0);
recv_ports_info_10_getRecvPortID : out std_logic_vector(3 downto 0);
recv_ports_info_11_getRecvPortID : out std_logic_vector(3 downto 0)
);
end component mkNetworkSimple;
component deblocking_filter_node is
generic (
data_width : integer := 64;
addr_width : integer := 1;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
-- recv interface to network
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
-- send interface to network
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic;
has_rxd : out std_logic;
is_idle : out std_logic;
is_filtering : out std_logic;
is_tx_ing : out std_logic;
is_cleanup_ing : out std_logic;
rx_non_zero : out std_logic;
tx_non_zero : out std_logic
);
end component deblocking_filter_node;
component noc_control_plus is
generic(
data_width : integer := 128;
addr_width : integer := 2;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
-- recv interface to network
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
-- send interface to network
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic;
--send interface to CPU
set_tail_cpu : in std_logic;
addr_cpu : in std_logic_vector(addr_width-1 downto 0);
tx_0 : in std_logic_vector(31 downto 0);
tx_1 : in std_logic_vector(31 downto 0);
tx_2 : in std_logic_vector(31 downto 0);
tx_3 : in std_logic_vector(31 downto 0);
tx_4 : in std_logic_vector(31 downto 0);
tx_5 : in std_logic_vector(31 downto 0);
tx_6 : in std_logic_vector(31 downto 0);
tx_7 : in std_logic_vector(31 downto 0);
format_select : in std_logic_vector(7 downto 0);
send_cmd_cpu : in std_logic;
send_ack : out std_logic;
--receive interface to cpu
rx_0 : out std_logic_vector(31 downto 0);
rx_1 : out std_logic_vector(31 downto 0);
rx_2 : out std_logic_vector(31 downto 0);
rx_3 : out std_logic_vector(31 downto 0);
rx_4 : out std_logic_vector(31 downto 0);
rx_5 : out std_logic_vector(31 downto 0);
rx_6 : out std_logic_vector(31 downto 0);
rx_7 : out std_logic_vector(31 downto 0);
parse_select : in std_logic_vector(7 downto 0);
cpu_rx_ctrl : in std_logic;
rx_state_out : out std_logic_vector(7 downto 0)
);
end component noc_control_plus;
component inter_node is
generic(
size_x : integer := 12; --20 ; --12; --20 --20
size_y : integer := 12; --20 ; --12; --20 --20
interp_x : integer := 8; --4 ; --8; --2 --4
interp_y : integer := 2; --4 ; --1; --2 --4
sample_size : integer := 8; --8 ; --8;
samples_per_wr : integer := 16; --16 ; --8; --4 --16
data_width : integer := 128;--128 ; --64; --32 --128
addr_width : integer := 1; --1 ; --1;
vc_sel_width : integer := 1; --1 ; --1;
num_vc : integer := 2; --2 ; --2;
flit_buff_depth : integer := 8 --8 --8
);
port(
clk : in std_logic;
rst : in std_logic;
-- recv interface to network
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
-- send interface to network
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic
);
end component inter_node;
component chroma_motion is
generic(
data_width : integer := 64;
addr_width : integer := 4;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
-- recv interface to network
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
-- send interface to network
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic
--debug
--state_out : out std_logic_vector(7 downto 0)
);
end component chroma_motion;
component iqit_node is
generic(
sample_width : integer := 8;
qp_width : integer := 8;
wo_dc_width : integer := 8;
data_width : integer := 64;
addr_width : integer := 1;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
-- recv interface to network
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
-- send interface to network
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic
);
end component iqit_node;
component noc_interface is
generic(
data_width : integer := 64;
addr_width : integer := 1;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8;
use_vc : integer := 0
);
port(
--clk, reset
clk : in std_logic;
rst : in std_logic;
--user sending interface
send_data : in std_logic_vector(data_width-1 downto 0);
dest_addr : in std_logic_vector(addr_width-1 downto 0);
set_tail_flit : in std_logic;
send_flit : in std_logic;
ready_to_send : out std_logic;
--user receiving interface
recv_data : out std_logic_vector(data_width-1 downto 0);
src_addr : out std_logic_vector(addr_width-1 downto 0);
is_tail_flit : out std_logic;
data_in_buffer : out std_logic_vector(num_vc-1 downto 0);
dequeue : in std_logic_vector(num_vc-1 downto 0);
select_vc_read : in std_logic_vector(vc_sel_width-1 downto 0);
--interface to network
send_putFlit_flit_in : out std_logic_vector(data_width+addr_width+vc_sel_width+1 downto 0);
EN_send_putFlit : out std_logic;
EN_send_getNonFullVCs : out std_logic;
send_getNonFullVCs : in std_logic_vector(num_vc-1 downto 0);
EN_recv_getFlit : out std_logic;
recv_getFlit : in std_logic_vector(data_width+addr_width+vc_sel_width+1 downto 0);
recv_putNonFullVCs_nonFullVCs : out std_logic_vector(num_vc-1 downto 0);
EN_recv_putNonFullVCs : out std_logic;
recv_info_getRecvPortID : in std_logic_vector(addr_width-1 downto 0)
);
end component noc_interface;
component vga_node is
generic(
data_width : integer := 64;
addr_width : integer := 4;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
-- recv interface to network
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
-- send interface to network
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic;
-- vga connections
clk27 : in std_logic;
rst27 : in std_logic;
vga_red : out std_logic_vector(5 downto 0);
vga_blue : out std_logic_vector(5 downto 0);
vga_green : out std_logic_vector(5 downto 0);
vga_v_sync : out std_logic;
vga_h_sync : out std_logic
);
end component vga_node;
signal hps_h2f_rst : std_logic;
signal flit_word_0_export : std_logic_vector(31 downto 0);
signal flit_rx_0_export : std_logic_vector(31 downto 0);
signal flit_word_2_export : std_logic_vector(31 downto 0);
signal flit_rx_2_export : std_logic_vector(31 downto 0);
signal flit_word_1_export : std_logic_vector(31 downto 0);
signal flit_rx_1_export : std_logic_vector(31 downto 0);
signal flit_word_3_export : std_logic_vector(31 downto 0);
signal flit_rx_3_export : std_logic_vector(31 downto 0);
signal send_ports_0_putFlit_flit_in : std_logic_vector(70 downto 0);
signal EN_send_ports_0_putFlit : std_logic;
signal EN_send_ports_0_getNonFullVCs : std_logic;
signal send_ports_0_getNonFullVCs : std_logic_vector(1 downto 0);
signal send_ports_1_putFlit_flit_in : std_logic_vector(70 downto 0);
signal EN_send_ports_1_putFlit : std_logic;
signal EN_send_ports_1_getNonFullVCs : std_logic;
signal send_ports_1_getNonFullVCs : std_logic_vector(1 downto 0);
signal send_ports_2_putFlit_flit_in : std_logic_vector(70 downto 0);
signal EN_send_ports_2_putFlit : std_logic;
signal EN_send_ports_2_getNonFullVCs : std_logic;
signal send_ports_2_getNonFullVCs : std_logic_vector(1 downto 0);
signal send_ports_3_putFlit_flit_in : std_logic_vector(70 downto 0);
signal EN_send_ports_3_putFlit : std_logic;
signal EN_send_ports_3_getNonFullVCs : std_logic;
signal send_ports_3_getNonFullVCs : std_logic_vector(1 downto 0);
signal send_ports_4_putFlit_flit_in : std_logic_vector(70 downto 0);
signal EN_send_ports_4_putFlit : std_logic;
signal EN_send_ports_4_getNonFullVCs : std_logic;
signal send_ports_4_getNonFullVCs : std_logic_vector(1 downto 0);
signal send_ports_5_putFlit_flit_in : std_logic_vector(70 downto 0);
signal EN_send_ports_5_putFlit : std_logic;
signal EN_send_ports_5_getNonFullVCs : std_logic;
signal send_ports_5_getNonFullVCs : std_logic_vector(1 downto 0);
signal send_ports_6_putFlit_flit_in : std_logic_vector(70 downto 0);
signal EN_send_ports_6_putFlit : std_logic;
signal EN_send_ports_6_getNonFullVCs : std_logic;
signal send_ports_6_getNonFullVCs : std_logic_vector(1 downto 0);
signal send_ports_7_putFlit_flit_in : std_logic_vector(70 downto 0);
signal EN_send_ports_7_putFlit : std_logic;
signal EN_send_ports_7_getNonFullVCs : std_logic;
signal send_ports_7_getNonFullVCs : std_logic_vector(1 downto 0);
signal send_ports_8_putFlit_flit_in : std_logic_vector(70 downto 0);
signal EN_send_ports_8_putFlit : std_logic;
signal EN_send_ports_8_getNonFullVCs : std_logic;
signal send_ports_8_getNonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_0_getFlit : std_logic;
signal recv_ports_0_getFlit : std_logic_vector(70 downto 0);
signal recv_ports_0_putNonFullVCs_nonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_0_putNonFullVCs : std_logic;
signal EN_recv_ports_1_getFlit : std_logic;
signal recv_ports_1_getFlit : std_logic_vector(70 downto 0);
signal recv_ports_1_putNonFullVCs_nonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_1_putNonFullVCs : std_logic;
signal EN_recv_ports_2_getFlit : std_logic;
signal recv_ports_2_getFlit : std_logic_vector(70 downto 0);
signal recv_ports_2_putNonFullVCs_nonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_2_putNonFullVCs : std_logic;
signal EN_recv_ports_3_getFlit : std_logic;
signal recv_ports_3_getFlit : std_logic_vector(70 downto 0);
signal recv_ports_3_putNonFullVCs_nonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_3_putNonFullVCs : std_logic;
signal EN_recv_ports_4_getFlit : std_logic;
signal recv_ports_4_getFlit : std_logic_vector(70 downto 0);
signal recv_ports_4_putNonFullVCs_nonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_4_putNonFullVCs : std_logic;
signal EN_recv_ports_5_getFlit : std_logic;
signal recv_ports_5_getFlit : std_logic_vector(70 downto 0);
signal recv_ports_5_putNonFullVCs_nonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_5_putNonFullVCs : std_logic;
signal EN_recv_ports_6_getFlit : std_logic;
signal recv_ports_6_getFlit : std_logic_vector(70 downto 0);
signal recv_ports_6_putNonFullVCs_nonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_6_putNonFullVCs : std_logic;
signal EN_recv_ports_7_getFlit : std_logic;
signal recv_ports_7_getFlit : std_logic_vector(70 downto 0);
signal recv_ports_7_putNonFullVCs_nonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_7_putNonFullVCs : std_logic;
signal EN_recv_ports_8_getFlit : std_logic;
signal recv_ports_8_getFlit : std_logic_vector(70 downto 0);
signal recv_ports_8_putNonFullVCs_nonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_8_putNonFullVCs : std_logic;
signal recv_ports_info_0_getRecvPortID : std_logic_vector(3 downto 0);
signal recv_ports_info_1_getRecvPortID : std_logic_vector(3 downto 0);
signal recv_ports_info_2_getRecvPortID : std_logic_vector(3 downto 0);
signal recv_ports_info_3_getRecvPortID : std_logic_vector(3 downto 0);
signal recv_ports_info_4_getRecvPortID : std_logic_vector(3 downto 0);
signal recv_ports_info_5_getRecvPortID : std_logic_vector(3 downto 0);
signal recv_ports_info_6_getRecvPortID : std_logic_vector(3 downto 0);
signal recv_ports_info_7_getRecvPortID : std_logic_vector(3 downto 0);
signal recv_ports_info_8_getRecvPortID : std_logic_vector(3 downto 0);
signal send_ports_9_putFlit_flit_in : std_logic_vector(70 downto 0);
signal EN_send_ports_9_putFlit : std_logic;
signal EN_send_ports_9_getNonFullVCs : std_logic;
signal send_ports_9_getNonFullVCs : std_logic_vector(1 downto 0);
signal send_ports_10_putFlit_flit_in : std_logic_vector(70 downto 0);
signal EN_send_ports_10_putFlit : std_logic;
signal EN_send_ports_10_getNonFullVCs : std_logic;
signal send_ports_10_getNonFullVCs : std_logic_vector(1 downto 0);
signal send_ports_11_putFlit_flit_in : std_logic_vector(70 downto 0);
signal EN_send_ports_11_putFlit : std_logic;
signal EN_send_ports_11_getNonFullVCs : std_logic;
signal send_ports_11_getNonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_9_getFlit : std_logic;
signal recv_ports_9_getFlit : std_logic_vector(70 downto 0);
signal recv_ports_9_putNonFullVCs_nonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_9_putNonFullVCs : std_logic;
signal EN_recv_ports_10_getFlit : std_logic;
signal recv_ports_10_getFlit : std_logic_vector(70 downto 0);
signal recv_ports_10_putNonFullVCs_nonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_10_putNonFullVCs : std_logic;
signal EN_recv_ports_11_getFlit : std_logic;
signal recv_ports_11_getFlit : std_logic_vector(70 downto 0);
signal recv_ports_11_putNonFullVCs_nonFullVCs : std_logic_vector(1 downto 0);
signal EN_recv_ports_11_putNonFullVCs : std_logic;
signal recv_ports_info_9_getRecvPortID : std_logic_vector(3 downto 0);
signal recv_ports_info_10_getRecvPortID : std_logic_vector(3 downto 0);
signal recv_ports_info_11_getRecvPortID : std_logic_vector(3 downto 0);
signal send_data_pe0 : std_logic_vector(data_width-1 downto 0);
signal dest_addr_pe0 : std_logic_vector(addr_width-1 downto 0);
signal set_tail_flit_pe0 : std_logic;
signal send_flit_pe0 : std_logic;
signal ready_to_send_pe0 : std_logic;
signal recv_data_pe0 : std_logic_vector(data_width-1 downto 0);
signal src_addr_pe0 : std_logic_vector(addr_width-1 downto 0);
signal is_tail_flit_pe0 : std_logic;
signal data_in_buffer_pe0 : std_logic_vector(num_vc-1 downto 0);
signal dequeue_pe0 : std_logic_vector(num_vc-1 downto 0);
signal select_vc_read_pe0 : std_logic_vector(vc_sel_width-1 downto 0);
signal send_data_pe1 : std_logic_vector(data_width-1 downto 0);
signal dest_addr_pe1 : std_logic_vector(addr_width-1 downto 0);
signal set_tail_flit_pe1 : std_logic;
signal send_flit_pe1 : std_logic;
signal ready_to_send_pe1 : std_logic;
signal recv_data_pe1 : std_logic_vector(data_width-1 downto 0);
signal src_addr_pe1 : std_logic_vector(addr_width-1 downto 0);
signal is_tail_flit_pe1 : std_logic;
signal data_in_buffer_pe1 : std_logic_vector(num_vc-1 downto 0);
signal dequeue_pe1 : std_logic_vector(num_vc-1 downto 0);
signal select_vc_read_pe1 : std_logic_vector(vc_sel_width-1 downto 0);
signal send_data_pe2 : std_logic_vector(data_width-1 downto 0);
signal dest_addr_pe2 : std_logic_vector(addr_width-1 downto 0);
signal set_tail_flit_pe2 : std_logic;
signal send_flit_pe2 : std_logic;
signal ready_to_send_pe2 : std_logic;
signal recv_data_pe2 : std_logic_vector(data_width-1 downto 0);
signal src_addr_pe2 : std_logic_vector(addr_width-1 downto 0);
signal is_tail_flit_pe2 : std_logic;
signal data_in_buffer_pe2 : std_logic_vector(num_vc-1 downto 0);
signal dequeue_pe2 : std_logic_vector(num_vc-1 downto 0);
signal select_vc_read_pe2 : std_logic_vector(vc_sel_width-1 downto 0);
signal send_data_pe3 : std_logic_vector(data_width-1 downto 0);
signal dest_addr_pe3 : std_logic_vector(addr_width-1 downto 0);
signal set_tail_flit_pe3 : std_logic;
signal send_flit_pe3 : std_logic;
signal ready_to_send_pe3 : std_logic;
signal recv_data_pe3 : std_logic_vector(data_width-1 downto 0);
signal src_addr_pe3 : std_logic_vector(addr_width-1 downto 0);
signal is_tail_flit_pe3 : std_logic;
signal data_in_buffer_pe3 : std_logic_vector(num_vc-1 downto 0);
signal dequeue_pe3 : std_logic_vector(num_vc-1 downto 0);
signal select_vc_read_pe3 : std_logic_vector(vc_sel_width-1 downto 0);
signal send_data_pe4 : std_logic_vector(data_width-1 downto 0);
signal dest_addr_pe4 : std_logic_vector(addr_width-1 downto 0);
signal set_tail_flit_pe4 : std_logic;
signal send_flit_pe4 : std_logic;
signal ready_to_send_pe4 : std_logic;
signal recv_data_pe4 : std_logic_vector(data_width-1 downto 0);
signal src_addr_pe4 : std_logic_vector(addr_width-1 downto 0);
signal is_tail_flit_pe4 : std_logic;
signal data_in_buffer_pe4 : std_logic_vector(num_vc-1 downto 0);
signal dequeue_pe4 : std_logic_vector(num_vc-1 downto 0);
signal select_vc_read_pe4 : std_logic_vector(vc_sel_width-1 downto 0);
signal send_data_pe5 : std_logic_vector(data_width-1 downto 0);
signal dest_addr_pe5 : std_logic_vector(addr_width-1 downto 0);
signal set_tail_flit_pe5 : std_logic;
signal send_flit_pe5 : std_logic;
signal ready_to_send_pe5 : std_logic;
signal recv_data_pe5 : std_logic_vector(data_width-1 downto 0);
signal src_addr_pe5 : std_logic_vector(addr_width-1 downto 0);
signal is_tail_flit_pe5 : std_logic;
signal data_in_buffer_pe5 : std_logic_vector(num_vc-1 downto 0);
signal dequeue_pe5 : std_logic_vector(num_vc-1 downto 0);
signal select_vc_read_pe5 : std_logic_vector(vc_sel_width-1 downto 0);
signal send_data_pe6 : std_logic_vector(data_width-1 downto 0);
signal dest_addr_pe6 : std_logic_vector(addr_width-1 downto 0);
signal set_tail_flit_pe6 : std_logic;
signal send_flit_pe6 : std_logic;
signal ready_to_send_pe6 : std_logic;
signal recv_data_pe6 : std_logic_vector(data_width-1 downto 0);
signal src_addr_pe6 : std_logic_vector(addr_width-1 downto 0);
signal is_tail_flit_pe6 : std_logic;
signal data_in_buffer_pe6 : std_logic_vector(num_vc-1 downto 0);
signal dequeue_pe6 : std_logic_vector(num_vc-1 downto 0);
signal select_vc_read_pe6 : std_logic_vector(vc_sel_width-1 downto 0);
signal send_data_pe7 : std_logic_vector(data_width-1 downto 0);
signal dest_addr_pe7 : std_logic_vector(addr_width-1 downto 0);
signal set_tail_flit_pe7 : std_logic;
signal send_flit_pe7 : std_logic;
signal ready_to_send_pe7 : std_logic;
signal recv_data_pe7 : std_logic_vector(data_width-1 downto 0);
signal src_addr_pe7 : std_logic_vector(addr_width-1 downto 0);
signal is_tail_flit_pe7 : std_logic;
signal data_in_buffer_pe7 : std_logic_vector(num_vc-1 downto 0);
signal dequeue_pe7 : std_logic_vector(num_vc-1 downto 0);
signal select_vc_read_pe7 : std_logic_vector(vc_sel_width-1 downto 0);
signal send_data_pe8 : std_logic_vector(data_width-1 downto 0);
signal dest_addr_pe8 : std_logic_vector(addr_width-1 downto 0);
signal set_tail_flit_pe8 : std_logic;
signal send_flit_pe8 : std_logic;
signal ready_to_send_pe8 : std_logic;
signal recv_data_pe8 : std_logic_vector(data_width-1 downto 0);
signal src_addr_pe8 : std_logic_vector(addr_width-1 downto 0);
signal is_tail_flit_pe8 : std_logic;
signal data_in_buffer_pe8 : std_logic_vector(num_vc-1 downto 0);
signal dequeue_pe8 : std_logic_vector(num_vc-1 downto 0);
signal select_vc_read_pe8 : std_logic_vector(vc_sel_width-1 downto 0);
signal send_data_pe9 : std_logic_vector(data_width-1 downto 0);
signal dest_addr_pe9 : std_logic_vector(addr_width-1 downto 0);
signal set_tail_flit_pe9 : std_logic;
signal send_flit_pe9 : std_logic;
signal ready_to_send_pe9 : std_logic;
signal recv_data_pe9 : std_logic_vector(data_width-1 downto 0);
signal src_addr_pe9 : std_logic_vector(addr_width-1 downto 0);
signal is_tail_flit_pe9 : std_logic;
signal data_in_buffer_pe9 : std_logic_vector(num_vc-1 downto 0);
signal dequeue_pe9 : std_logic_vector(num_vc-1 downto 0);
signal select_vc_read_pe9 : std_logic_vector(vc_sel_width-1 downto 0);
signal noc_rst : std_logic;
signal noc_ctrl_export : std_logic_vector(31 downto 0);
signal noc_status_export : std_logic_vector(31 downto 0);
signal data_out : std_logic_vector(data_width-1 downto 0);
signal LEDR_NOPE : std_logic_vector(9 downto 0);
signal is_idle : std_logic_vector(2 downto 0);
signal is_filtering : std_logic_vector(2 downto 0);
signal is_tx_ing : std_logic_vector(2 downto 0);
signal is_cleanup_ing : std_logic_vector(2 downto 0);
signal cpu_0_rx_0_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_0_rx_1_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_0_rx_2_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_0_rx_3_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_0_rx_4_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_0_rx_5_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_0_rx_6_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_0_rx_7_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_0_tx_0_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_0_tx_1_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_0_tx_2_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_0_tx_3_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_0_tx_4_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_0_tx_5_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_0_tx_6_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_0_tx_7_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_1_rx_0_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_1_rx_1_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_1_rx_2_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_1_rx_3_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_1_rx_4_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_1_rx_5_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_1_rx_6_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_1_rx_7_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_1_tx_0_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_1_tx_1_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_1_tx_2_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_1_tx_3_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_1_tx_4_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_1_tx_5_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_1_tx_6_external_connection_export : std_logic_vector(31 downto 0);
signal cpu_1_tx_7_external_connection_export : std_logic_vector(31 downto 0);
signal noc_ctrl_0_external_connection_export : std_logic_vector(31 downto 0);
signal noc_ctrl_1_external_connection_export : std_logic_vector(31 downto 0);
signal noc_status_0_external_connection_export : std_logic_vector(31 downto 0);
signal noc_status_1_external_connection_export : std_logic_vector(31 downto 0);
signal noc_ctrl_cpu_0 : std_logic_vector(31 downto 0);
signal noc_ctrl_cpu_1 : std_logic_vector(31 downto 0);
signal noc_sts_cpu_0 : std_logic_vector(31 downto 0);
signal noc_sts_cpu_1 : std_logic_vector(31 downto 0);
signal vga_clk_sig : std_logic;
signal noc_clock_clk : std_logic;
BEGIN
u0 : component hps_fpga
port map (
clk_clk => CLOCK_50, -- clk.clk
reset_reset_n => '1', -- reset.reset_n
memory_mem_a => HPS_DDR3_ADDR, -- memory.mem_a
memory_mem_ba => HPS_DDR3_BA, -- .mem_ba
memory_mem_ck => HPS_DDR3_CK_P, -- .mem_ck
memory_mem_ck_n => HPS_DDR3_CK_N, -- .mem_ck_n
memory_mem_cke => HPS_DDR3_CKE, -- .mem_cke
memory_mem_cs_n => HPS_DDR3_CS_N, -- .mem_cs_n
memory_mem_ras_n => HPS_DDR3_RAS_N, -- .mem_ras_n
memory_mem_cas_n => HPS_DDR3_CAS_N, -- .mem_cas_n
memory_mem_we_n => HPS_DDR3_WE_N, -- .mem_we_n
memory_mem_reset_n => HPS_DDR3_RESET_N, -- .mem_reset_n
memory_mem_dq => HPS_DDR3_DQ, -- .mem_dq
memory_mem_dqs => HPS_DDR3_DQS_P, -- .mem_dqs
memory_mem_dqs_n => HPS_DDR3_DQS_N, -- .mem_dqs_n
memory_mem_odt => HPS_DDR3_ODT, -- .mem_odt
memory_mem_dm => HPS_DDR3_DM, -- .mem_dm
memory_oct_rzqin => HPS_DDR3_RZQ, -- .oct_rzqin
hps_0_h2f_reset_reset_n => HPS_H2F_RST, -- hps_0_h2f_reset.reset_n
led_external_connection_export => LEDR_NOPE, -- led_external_connection.export
sw_external_connection_export => SW, -- sw_external_connection.export
hps_io_hps_io_emac1_inst_TX_CLK => HPS_ENET_GTX_CLK, -- hps_io.hps_io_emac1_inst_TX_CLK
hps_io_hps_io_emac1_inst_TXD0 => HPS_ENET_TX_DATA(0), -- .hps_io_emac1_inst_TXD0
hps_io_hps_io_emac1_inst_TXD1 => HPS_ENET_TX_DATA(1), -- .hps_io_emac1_inst_TXD1
hps_io_hps_io_emac1_inst_TXD2 => HPS_ENET_TX_DATA(2), -- .hps_io_emac1_inst_TXD2
hps_io_hps_io_emac1_inst_TXD3 => HPS_ENET_TX_DATA(3), -- .hps_io_emac1_inst_TXD3
hps_io_hps_io_emac1_inst_RXD0 => HPS_ENET_RX_DATA(0), -- .hps_io_emac1_inst_RXD0
hps_io_hps_io_emac1_inst_MDIO => HPS_ENET_MDIO, -- .hps_io_emac1_inst_MDIO
hps_io_hps_io_emac1_inst_MDC => HPS_ENET_MDC, -- .hps_io_emac1_inst_MDC
hps_io_hps_io_emac1_inst_RX_CTL => HPS_ENET_RX_DV, -- .hps_io_emac1_inst_RX_CTL
hps_io_hps_io_emac1_inst_TX_CTL => HPS_ENET_TX_EN, -- .hps_io_emac1_inst_TX_CTL
hps_io_hps_io_emac1_inst_RX_CLK => HPS_ENET_RX_CLK, -- .hps_io_emac1_inst_RX_CLK
hps_io_hps_io_emac1_inst_RXD1 => HPS_ENET_RX_DATA(1), -- .hps_io_emac1_inst_RXD1
hps_io_hps_io_emac1_inst_RXD2 => HPS_ENET_RX_DATA(2), -- .hps_io_emac1_inst_RXD2
hps_io_hps_io_emac1_inst_RXD3 => HPS_ENET_RX_DATA(3), -- .hps_io_emac1_inst_RXD3
hps_io_hps_io_sdio_inst_CMD => HPS_SD_CMD, -- .hps_io_sdio_inst_CMD
hps_io_hps_io_sdio_inst_D0 => HPS_SD_DATA(0), -- .hps_io_sdio_inst_D0
hps_io_hps_io_sdio_inst_D1 => HPS_SD_DATA(1), -- .hps_io_sdio_inst_D1
hps_io_hps_io_sdio_inst_CLK => HPS_SD_CLK, -- .hps_io_sdio_inst_CLK
hps_io_hps_io_sdio_inst_D2 => HPS_SD_DATA(2), -- .hps_io_sdio_inst_D2
hps_io_hps_io_sdio_inst_D3 => HPS_SD_DATA(3), -- .hps_io_sdio_inst_D3
hps_io_hps_io_usb1_inst_D0 => HPS_USB_DATA(0), -- .hps_io_usb1_inst_D0
hps_io_hps_io_usb1_inst_D1 => HPS_USB_DATA(1), -- .hps_io_usb1_inst_D1
hps_io_hps_io_usb1_inst_D2 => HPS_USB_DATA(2), -- .hps_io_usb1_inst_D2
hps_io_hps_io_usb1_inst_D3 => HPS_USB_DATA(3), -- .hps_io_usb1_inst_D3
hps_io_hps_io_usb1_inst_D4 => HPS_USB_DATA(4), -- .hps_io_usb1_inst_D4
hps_io_hps_io_usb1_inst_D5 => HPS_USB_DATA(5), -- .hps_io_usb1_inst_D5
hps_io_hps_io_usb1_inst_D6 => HPS_USB_DATA(6), -- .hps_io_usb1_inst_D6
hps_io_hps_io_usb1_inst_D7 => HPS_USB_DATA(7), -- .hps_io_usb1_inst_D7
hps_io_hps_io_usb1_inst_CLK => HPS_USB_CLKOUT, -- .hps_io_usb1_inst_CLK
hps_io_hps_io_usb1_inst_STP => HPS_USB_STP, -- .hps_io_usb1_inst_STP
hps_io_hps_io_usb1_inst_DIR => HPS_USB_DIR, -- .hps_io_usb1_inst_DIR
hps_io_hps_io_usb1_inst_NXT => HPS_USB_NXT, -- .hps_io_usb1_inst_NXT
hps_io_hps_io_uart0_inst_RX => HPS_UART_RX, -- .hps_io_uart0_inst_RX
hps_io_hps_io_uart0_inst_TX => HPS_UART_TX, -- .hps_io_uart0_inst_TX
cpu_0_rx_0_external_connection_export => cpu_0_rx_0_external_connection_export ,
cpu_0_rx_1_external_connection_export => cpu_0_rx_1_external_connection_export ,
cpu_0_rx_2_external_connection_export => cpu_0_rx_2_external_connection_export ,
cpu_0_rx_3_external_connection_export => cpu_0_rx_3_external_connection_export ,
cpu_0_rx_4_external_connection_export => cpu_0_rx_4_external_connection_export ,
cpu_0_rx_5_external_connection_export => cpu_0_rx_5_external_connection_export ,
cpu_0_rx_6_external_connection_export => cpu_0_rx_6_external_connection_export ,
cpu_0_rx_7_external_connection_export => cpu_0_rx_7_external_connection_export ,
cpu_0_tx_0_external_connection_export => cpu_0_tx_0_external_connection_export ,
cpu_0_tx_1_external_connection_export => cpu_0_tx_1_external_connection_export ,
cpu_0_tx_2_external_connection_export => cpu_0_tx_2_external_connection_export ,
cpu_0_tx_3_external_connection_export => cpu_0_tx_3_external_connection_export ,
cpu_0_tx_4_external_connection_export => cpu_0_tx_4_external_connection_export ,
cpu_0_tx_5_external_connection_export => cpu_0_tx_5_external_connection_export ,
cpu_0_tx_6_external_connection_export => cpu_0_tx_6_external_connection_export ,
cpu_0_tx_7_external_connection_export => cpu_0_tx_7_external_connection_export ,
cpu_1_rx_0_external_connection_export => cpu_1_rx_0_external_connection_export ,
cpu_1_rx_1_external_connection_export => cpu_1_rx_1_external_connection_export ,
cpu_1_rx_2_external_connection_export => cpu_1_rx_2_external_connection_export ,
cpu_1_rx_3_external_connection_export => cpu_1_rx_3_external_connection_export ,
cpu_1_rx_4_external_connection_export => cpu_1_rx_4_external_connection_export ,
cpu_1_rx_5_external_connection_export => cpu_1_rx_5_external_connection_export ,
cpu_1_rx_6_external_connection_export => cpu_1_rx_6_external_connection_export ,
cpu_1_rx_7_external_connection_export => cpu_1_rx_7_external_connection_export ,
cpu_1_tx_0_external_connection_export => cpu_1_tx_0_external_connection_export ,
cpu_1_tx_1_external_connection_export => cpu_1_tx_1_external_connection_export ,
cpu_1_tx_2_external_connection_export => cpu_1_tx_2_external_connection_export ,
cpu_1_tx_3_external_connection_export => cpu_1_tx_3_external_connection_export ,
cpu_1_tx_4_external_connection_export => cpu_1_tx_4_external_connection_export ,
cpu_1_tx_5_external_connection_export => cpu_1_tx_5_external_connection_export ,
cpu_1_tx_6_external_connection_export => cpu_1_tx_6_external_connection_export ,
cpu_1_tx_7_external_connection_export => cpu_1_tx_7_external_connection_export ,
noc_ctrl_0_external_connection_export => noc_ctrl_0_external_connection_export ,
noc_ctrl_1_external_connection_export => noc_ctrl_1_external_connection_export ,
noc_status_0_external_connection_export => noc_status_0_external_connection_export,
noc_status_1_external_connection_export => noc_status_1_external_connection_export,
pll_0_outclk0_clk => VGA_CLK_SIG,
noc_clock_clk => noc_clock_clk
);
u1 : component mkNetworkSimple
port map(
CLK => CLOCK_50 ,
RST_N => not noc_rst ,
send_ports_0_putFlit_flit_in => send_ports_0_putFlit_flit_in ,
EN_send_ports_0_putFlit => EN_send_ports_0_putFlit ,
EN_send_ports_0_getNonFullVCs => EN_send_ports_0_getNonFullVCs ,
send_ports_0_getNonFullVCs => send_ports_0_getNonFullVCs ,
send_ports_1_putFlit_flit_in => send_ports_1_putFlit_flit_in ,
EN_send_ports_1_putFlit => EN_send_ports_1_putFlit ,
EN_send_ports_1_getNonFullVCs => EN_send_ports_1_getNonFullVCs ,
send_ports_1_getNonFullVCs => send_ports_1_getNonFullVCs ,
send_ports_2_putFlit_flit_in => send_ports_2_putFlit_flit_in ,
EN_send_ports_2_putFlit => EN_send_ports_2_putFlit ,
EN_send_ports_2_getNonFullVCs => EN_send_ports_2_getNonFullVCs ,
send_ports_2_getNonFullVCs => send_ports_2_getNonFullVCs ,
send_ports_3_putFlit_flit_in => send_ports_3_putFlit_flit_in ,
EN_send_ports_3_putFlit => EN_send_ports_3_putFlit ,
EN_send_ports_3_getNonFullVCs => EN_send_ports_3_getNonFullVCs ,
send_ports_3_getNonFullVCs => send_ports_3_getNonFullVCs ,
send_ports_4_putFlit_flit_in => send_ports_4_putFlit_flit_in ,
EN_send_ports_4_putFlit => EN_send_ports_4_putFlit ,
EN_send_ports_4_getNonFullVCs => EN_send_ports_4_getNonFullVCs ,
send_ports_4_getNonFullVCs => send_ports_4_getNonFullVCs ,
send_ports_5_putFlit_flit_in => send_ports_5_putFlit_flit_in ,
EN_send_ports_5_putFlit => EN_send_ports_5_putFlit ,
EN_send_ports_5_getNonFullVCs => EN_send_ports_5_getNonFullVCs ,
send_ports_5_getNonFullVCs => send_ports_5_getNonFullVCs ,
send_ports_6_putFlit_flit_in => send_ports_6_putFlit_flit_in ,
EN_send_ports_6_putFlit => EN_send_ports_6_putFlit ,
EN_send_ports_6_getNonFullVCs => EN_send_ports_6_getNonFullVCs ,
send_ports_6_getNonFullVCs => send_ports_6_getNonFullVCs ,
send_ports_7_putFlit_flit_in => send_ports_7_putFlit_flit_in ,
EN_send_ports_7_putFlit => EN_send_ports_7_putFlit ,
EN_send_ports_7_getNonFullVCs => EN_send_ports_7_getNonFullVCs ,
send_ports_7_getNonFullVCs => send_ports_7_getNonFullVCs ,
send_ports_8_putFlit_flit_in => send_ports_8_putFlit_flit_in ,
EN_send_ports_8_putFlit => EN_send_ports_8_putFlit ,
EN_send_ports_8_getNonFullVCs => EN_send_ports_8_getNonFullVCs ,
send_ports_8_getNonFullVCs => send_ports_8_getNonFullVCs ,
EN_recv_ports_0_getFlit => EN_recv_ports_0_getFlit ,
recv_ports_0_getFlit => recv_ports_0_getFlit ,
recv_ports_0_putNonFullVCs_nonFullVCs => recv_ports_0_putNonFullVCs_nonFullVCs ,
EN_recv_ports_0_putNonFullVCs => EN_recv_ports_0_putNonFullVCs ,
EN_recv_ports_1_getFlit => EN_recv_ports_1_getFlit ,
recv_ports_1_getFlit => recv_ports_1_getFlit ,
recv_ports_1_putNonFullVCs_nonFullVCs => recv_ports_1_putNonFullVCs_nonFullVCs ,
EN_recv_ports_1_putNonFullVCs => EN_recv_ports_1_putNonFullVCs ,
EN_recv_ports_2_getFlit => EN_recv_ports_2_getFlit ,
recv_ports_2_getFlit => recv_ports_2_getFlit ,
recv_ports_2_putNonFullVCs_nonFullVCs => recv_ports_2_putNonFullVCs_nonFullVCs ,
EN_recv_ports_2_putNonFullVCs => EN_recv_ports_2_putNonFullVCs ,
EN_recv_ports_3_getFlit => EN_recv_ports_3_getFlit ,
recv_ports_3_getFlit => recv_ports_3_getFlit ,
recv_ports_3_putNonFullVCs_nonFullVCs => recv_ports_3_putNonFullVCs_nonFullVCs ,
EN_recv_ports_3_putNonFullVCs => EN_recv_ports_3_putNonFullVCs ,
EN_recv_ports_4_getFlit => EN_recv_ports_4_getFlit ,
recv_ports_4_getFlit => recv_ports_4_getFlit ,
recv_ports_4_putNonFullVCs_nonFullVCs => recv_ports_4_putNonFullVCs_nonFullVCs ,
EN_recv_ports_4_putNonFullVCs => EN_recv_ports_4_putNonFullVCs ,
EN_recv_ports_5_getFlit => EN_recv_ports_5_getFlit ,
recv_ports_5_getFlit => recv_ports_5_getFlit ,
recv_ports_5_putNonFullVCs_nonFullVCs => recv_ports_5_putNonFullVCs_nonFullVCs ,
EN_recv_ports_5_putNonFullVCs => EN_recv_ports_5_putNonFullVCs ,
EN_recv_ports_6_getFlit => EN_recv_ports_6_getFlit ,
recv_ports_6_getFlit => recv_ports_6_getFlit ,
recv_ports_6_putNonFullVCs_nonFullVCs => recv_ports_6_putNonFullVCs_nonFullVCs ,
EN_recv_ports_6_putNonFullVCs => EN_recv_ports_6_putNonFullVCs ,
EN_recv_ports_7_getFlit => EN_recv_ports_7_getFlit ,
recv_ports_7_getFlit => recv_ports_7_getFlit ,
recv_ports_7_putNonFullVCs_nonFullVCs => recv_ports_7_putNonFullVCs_nonFullVCs ,
EN_recv_ports_7_putNonFullVCs => EN_recv_ports_7_putNonFullVCs ,
EN_recv_ports_8_getFlit => EN_recv_ports_8_getFlit ,
recv_ports_8_getFlit => recv_ports_8_getFlit ,
recv_ports_8_putNonFullVCs_nonFullVCs => recv_ports_8_putNonFullVCs_nonFullVCs ,
EN_recv_ports_8_putNonFullVCs => EN_recv_ports_8_putNonFullVCs ,
recv_ports_info_0_getRecvPortID => recv_ports_info_0_getRecvPortID ,
recv_ports_info_1_getRecvPortID => recv_ports_info_1_getRecvPortID ,
recv_ports_info_2_getRecvPortID => recv_ports_info_2_getRecvPortID ,
recv_ports_info_3_getRecvPortID => recv_ports_info_3_getRecvPortID ,
recv_ports_info_4_getRecvPortID => recv_ports_info_4_getRecvPortID ,
recv_ports_info_5_getRecvPortID => recv_ports_info_5_getRecvPortID ,
recv_ports_info_6_getRecvPortID => recv_ports_info_6_getRecvPortID ,
recv_ports_info_7_getRecvPortID => recv_ports_info_7_getRecvPortID ,
recv_ports_info_8_getRecvPortID => recv_ports_info_8_getRecvPortID ,
send_ports_9_putFlit_flit_in => send_ports_9_putFlit_flit_in ,
EN_send_ports_9_putFlit => EN_send_ports_9_putFlit ,
EN_send_ports_9_getNonFullVCs => EN_send_ports_9_getNonFullVCs ,
send_ports_9_getNonFullVCs => send_ports_9_getNonFullVCs ,
send_ports_10_putFlit_flit_in => send_ports_10_putFlit_flit_in ,
EN_send_ports_10_putFlit => EN_send_ports_10_putFlit ,
EN_send_ports_10_getNonFullVCs => EN_send_ports_10_getNonFullVCs ,
send_ports_10_getNonFullVCs => send_ports_10_getNonFullVCs ,
send_ports_11_putFlit_flit_in => send_ports_11_putFlit_flit_in ,
EN_send_ports_11_putFlit => EN_send_ports_11_putFlit ,
EN_send_ports_11_getNonFullVCs => EN_send_ports_11_getNonFullVCs ,
send_ports_11_getNonFullVCs => send_ports_11_getNonFullVCs ,
EN_recv_ports_9_getFlit => EN_recv_ports_9_getFlit ,
recv_ports_9_getFlit => recv_ports_9_getFlit ,
recv_ports_9_putNonFullVCs_nonFullVCs => recv_ports_9_putNonFullVCs_nonFullVCs ,
EN_recv_ports_9_putNonFullVCs => EN_recv_ports_9_putNonFullVCs ,
EN_recv_ports_10_getFlit => EN_recv_ports_10_getFlit ,
recv_ports_10_getFlit => recv_ports_10_getFlit ,
recv_ports_10_putNonFullVCs_nonFullVCs => recv_ports_10_putNonFullVCs_nonFullVCs ,
EN_recv_ports_10_putNonFullVCs => EN_recv_ports_10_putNonFullVCs ,
EN_recv_ports_11_getFlit => EN_recv_ports_11_getFlit ,
recv_ports_11_getFlit => recv_ports_11_getFlit ,
recv_ports_11_putNonFullVCs_nonFullVCs => recv_ports_11_putNonFullVCs_nonFullVCs ,
EN_recv_ports_11_putNonFullVCs => EN_recv_ports_11_putNonFullVCs ,
recv_ports_info_9_getRecvPortID => recv_ports_info_9_getRecvPortID ,
recv_ports_info_10_getRecvPortID => recv_ports_info_10_getRecvPortID ,
recv_ports_info_11_getRecvPortID => recv_ports_info_11_getRecvPortID
);
i0: noc_interface
generic map(
data_width => data_width,
addr_width => addr_width,
vc_sel_width => vc_sel_width,
num_vc => num_vc,
flit_buff_depth => flit_buff_depth,
use_vc => 1)
port map(
clk => clock_50,
rst => noc_rst,
send_data => send_data_pe0,
dest_addr => dest_addr_pe0,
set_tail_flit => set_tail_flit_pe0,
send_flit => send_flit_pe0,
ready_to_send => ready_to_send_pe0,
recv_data => recv_data_pe0,
src_addr => src_addr_pe0,
is_tail_flit => is_tail_flit_pe0,
data_in_buffer => data_in_buffer_pe0,
dequeue => dequeue_pe0,
select_vc_read => select_vc_read_pe0,
send_putFlit_flit_in => send_ports_0_putFlit_flit_in,
EN_send_putFlit => EN_send_ports_0_putFlit,
EN_send_getNonFullVCs => EN_send_ports_0_getNonFullVCs,
send_getNonFullVCs => send_ports_0_getNonFullVCs,
EN_recv_getFlit => EN_recv_ports_0_getFlit,
recv_getFlit => recv_ports_0_getFlit,
recv_putNonFullVCs_nonFullVCs => recv_ports_0_putNonFullVCs_nonFullVCs,
EN_recv_putNonFullVCs => EN_recv_ports_0_putNonFullVCs,
recv_info_getRecvPortID => recv_ports_info_0_getRecvPortID);
i1: noc_interface
generic map(
data_width => data_width,
addr_width => addr_width,
vc_sel_width => vc_sel_width,
num_vc => num_vc,
flit_buff_depth => flit_buff_depth)
port map(
clk => clock_50,
rst => noc_rst,
send_data => send_data_pe1,
dest_addr => dest_addr_pe1,
set_tail_flit => set_tail_flit_pe1,
send_flit => send_flit_pe1,
ready_to_send => ready_to_send_pe1,
recv_data => recv_data_pe1,
src_addr => src_addr_pe1,
is_tail_flit => is_tail_flit_pe1,
data_in_buffer => data_in_buffer_pe1,
dequeue => dequeue_pe1,
select_vc_read => select_vc_read_pe1,
send_putFlit_flit_in => send_ports_1_putFlit_flit_in,
EN_send_putFlit => EN_send_ports_1_putFlit,
EN_send_getNonFullVCs => EN_send_ports_1_getNonFullVCs,
send_getNonFullVCs => send_ports_1_getNonFullVCs,
EN_recv_getFlit => EN_recv_ports_1_getFlit,
recv_getFlit => recv_ports_1_getFlit,
recv_putNonFullVCs_nonFullVCs => recv_ports_1_putNonFullVCs_nonFullVCs,
EN_recv_putNonFullVCs => EN_recv_ports_1_putNonFullVCs,
recv_info_getRecvPortID => recv_ports_info_1_getRecvPortID);
i2: noc_interface
generic map(
data_width => data_width,
addr_width => addr_width,
vc_sel_width => vc_sel_width,
num_vc => num_vc,
flit_buff_depth => flit_buff_depth)
port map(
clk => clock_50,
rst => noc_rst,
send_data => send_data_pe2,
dest_addr => dest_addr_pe2,
set_tail_flit => set_tail_flit_pe2,
send_flit => send_flit_pe2,
ready_to_send => ready_to_send_pe2,
recv_data => recv_data_pe2,
src_addr => src_addr_pe2,
is_tail_flit => is_tail_flit_pe2,
data_in_buffer => data_in_buffer_pe2,
dequeue => dequeue_pe2,
select_vc_read => select_vc_read_pe2,
send_putFlit_flit_in => send_ports_2_putFlit_flit_in,
EN_send_putFlit => EN_send_ports_2_putFlit,
EN_send_getNonFullVCs => EN_send_ports_2_getNonFullVCs,
send_getNonFullVCs => send_ports_2_getNonFullVCs,
EN_recv_getFlit => EN_recv_ports_2_getFlit,
recv_getFlit => recv_ports_2_getFlit,
recv_putNonFullVCs_nonFullVCs => recv_ports_2_putNonFullVCs_nonFullVCs,
EN_recv_putNonFullVCs => EN_recv_ports_2_putNonFullVCs,
recv_info_getRecvPortID => recv_ports_info_2_getRecvPortID);
i4: noc_interface
generic map(
data_width => data_width,
addr_width => addr_width,
vc_sel_width => vc_sel_width,
num_vc => num_vc,
flit_buff_depth => flit_buff_depth)
port map(
clk => clock_50,
rst => noc_rst,
send_data => send_data_pe4,
dest_addr => dest_addr_pe4,
set_tail_flit => set_tail_flit_pe4,
send_flit => send_flit_pe4,
ready_to_send => ready_to_send_pe4,
recv_data => recv_data_pe4,
src_addr => src_addr_pe4,
is_tail_flit => is_tail_flit_pe4,
data_in_buffer => data_in_buffer_pe4,
dequeue => dequeue_pe4,
select_vc_read => select_vc_read_pe4,
send_putFlit_flit_in => send_ports_4_putFlit_flit_in,
EN_send_putFlit => EN_send_ports_4_putFlit,
EN_send_getNonFullVCs => EN_send_ports_4_getNonFullVCs,
send_getNonFullVCs => send_ports_4_getNonFullVCs,
EN_recv_getFlit => EN_recv_ports_4_getFlit,
recv_getFlit => recv_ports_4_getFlit,
recv_putNonFullVCs_nonFullVCs => recv_ports_4_putNonFullVCs_nonFullVCs,
EN_recv_putNonFullVCs => EN_recv_ports_4_putNonFullVCs,
recv_info_getRecvPortID => recv_ports_info_4_getRecvPortID);
i5: noc_interface
generic map(
data_width => data_width,
addr_width => addr_width,
vc_sel_width => vc_sel_width,
num_vc => num_vc,
flit_buff_depth => flit_buff_depth)
port map(
clk => clock_50,
rst => noc_rst,
send_data => send_data_pe5,
dest_addr => dest_addr_pe5,
set_tail_flit => set_tail_flit_pe5,
send_flit => send_flit_pe5,
ready_to_send => ready_to_send_pe5,
recv_data => recv_data_pe5,
src_addr => src_addr_pe5,
is_tail_flit => is_tail_flit_pe5,
data_in_buffer => data_in_buffer_pe5,
dequeue => dequeue_pe5,
select_vc_read => select_vc_read_pe5,
send_putFlit_flit_in => send_ports_5_putFlit_flit_in,
EN_send_putFlit => EN_send_ports_5_putFlit,
EN_send_getNonFullVCs => EN_send_ports_5_getNonFullVCs,
send_getNonFullVCs => send_ports_5_getNonFullVCs,
EN_recv_getFlit => EN_recv_ports_5_getFlit,
recv_getFlit => recv_ports_5_getFlit,
recv_putNonFullVCs_nonFullVCs => recv_ports_5_putNonFullVCs_nonFullVCs,
EN_recv_putNonFullVCs => EN_recv_ports_5_putNonFullVCs,
recv_info_getRecvPortID => recv_ports_info_5_getRecvPortID);
i6: noc_interface
generic map(
data_width => data_width,
addr_width => addr_width,
vc_sel_width => vc_sel_width,
num_vc => num_vc,
flit_buff_depth => flit_buff_depth)
port map(
clk => clock_50,
rst => noc_rst,
send_data => send_data_pe6,
dest_addr => dest_addr_pe6,
set_tail_flit => set_tail_flit_pe6,
send_flit => send_flit_pe6,
ready_to_send => ready_to_send_pe6,
recv_data => recv_data_pe6,
src_addr => src_addr_pe6,
is_tail_flit => is_tail_flit_pe6,
data_in_buffer => data_in_buffer_pe6,
dequeue => dequeue_pe6,
select_vc_read => select_vc_read_pe6,
send_putFlit_flit_in => send_ports_6_putFlit_flit_in,
EN_send_putFlit => EN_send_ports_6_putFlit,
EN_send_getNonFullVCs => EN_send_ports_6_getNonFullVCs,
send_getNonFullVCs => send_ports_6_getNonFullVCs,
EN_recv_getFlit => EN_recv_ports_6_getFlit,
recv_getFlit => recv_ports_6_getFlit,
recv_putNonFullVCs_nonFullVCs => recv_ports_6_putNonFullVCs_nonFullVCs,
EN_recv_putNonFullVCs => EN_recv_ports_6_putNonFullVCs,
recv_info_getRecvPortID => recv_ports_info_6_getRecvPortID);
i7: noc_interface
generic map(
data_width => data_width,
addr_width => addr_width,
vc_sel_width => vc_sel_width,
num_vc => num_vc,
flit_buff_depth => flit_buff_depth,
use_vc => 0)
port map(
clk => clock_50,
rst => noc_rst,
send_data => send_data_pe7,
dest_addr => dest_addr_pe7,
set_tail_flit => set_tail_flit_pe7,
send_flit => send_flit_pe7,
ready_to_send => ready_to_send_pe7,
recv_data => recv_data_pe7,
src_addr => src_addr_pe7,
is_tail_flit => is_tail_flit_pe7,
data_in_buffer => data_in_buffer_pe7,
dequeue => dequeue_pe7,
select_vc_read => select_vc_read_pe7,
send_putFlit_flit_in => send_ports_7_putFlit_flit_in,
EN_send_putFlit => EN_send_ports_7_putFlit,
EN_send_getNonFullVCs => EN_send_ports_7_getNonFullVCs,
send_getNonFullVCs => send_ports_7_getNonFullVCs,
EN_recv_getFlit => EN_recv_ports_7_getFlit,
recv_getFlit => recv_ports_7_getFlit,
recv_putNonFullVCs_nonFullVCs => recv_ports_7_putNonFullVCs_nonFullVCs,
EN_recv_putNonFullVCs => EN_recv_ports_7_putNonFullVCs,
recv_info_getRecvPortID => recv_ports_info_7_getRecvPortID);
i8: noc_interface
generic map(
data_width => data_width,
addr_width => addr_width,
vc_sel_width => vc_sel_width,
num_vc => num_vc,
flit_buff_depth => flit_buff_depth,
use_vc => 0)
port map(
clk => clock_50,
rst => noc_rst,
send_data => send_data_pe8,
dest_addr => dest_addr_pe8,
set_tail_flit => set_tail_flit_pe8,
send_flit => send_flit_pe8,
ready_to_send => ready_to_send_pe8,
recv_data => recv_data_pe8,
src_addr => src_addr_pe8,
is_tail_flit => is_tail_flit_pe8,
data_in_buffer => data_in_buffer_pe8,
dequeue => dequeue_pe8,
select_vc_read => select_vc_read_pe8,
send_putFlit_flit_in => send_ports_8_putFlit_flit_in,
EN_send_putFlit => EN_send_ports_8_putFlit,
EN_send_getNonFullVCs => EN_send_ports_8_getNonFullVCs,
send_getNonFullVCs => send_ports_8_getNonFullVCs,
EN_recv_getFlit => EN_recv_ports_8_getFlit,
recv_getFlit => recv_ports_8_getFlit,
recv_putNonFullVCs_nonFullVCs => recv_ports_8_putNonFullVCs_nonFullVCs,
EN_recv_putNonFullVCs => EN_recv_ports_8_putNonFullVCs,
recv_info_getRecvPortID => recv_ports_info_8_getRecvPortID);
i9: noc_interface
generic map(
data_width => data_width,
addr_width => addr_width,
vc_sel_width => vc_sel_width,
num_vc => num_vc,
flit_buff_depth => flit_buff_depth,
use_vc => 0)
port map(
clk => clock_50,
rst => noc_rst,
send_data => send_data_pe9,
dest_addr => dest_addr_pe9,
set_tail_flit => set_tail_flit_pe9,
send_flit => send_flit_pe9,
ready_to_send => ready_to_send_pe9,
recv_data => recv_data_pe9,
src_addr => src_addr_pe9,
is_tail_flit => is_tail_flit_pe9,
data_in_buffer => data_in_buffer_pe9,
dequeue => dequeue_pe9,
select_vc_read => select_vc_read_pe9,
send_putFlit_flit_in => send_ports_9_putFlit_flit_in,
EN_send_putFlit => EN_send_ports_9_putFlit,
EN_send_getNonFullVCs => EN_send_ports_9_getNonFullVCs,
send_getNonFullVCs => send_ports_9_getNonFullVCs,
EN_recv_getFlit => EN_recv_ports_9_getFlit,
recv_getFlit => recv_ports_9_getFlit,
recv_putNonFullVCs_nonFullVCs => recv_ports_9_putNonFullVCs_nonFullVCs,
EN_recv_putNonFullVCs => EN_recv_ports_9_putNonFullVCs,
recv_info_getRecvPortID => recv_ports_info_9_getRecvPortID);
n0: component deblocking_filter_node
generic map(
data_width => data_width ,
addr_width => addr_width ,
vc_sel_width => vc_sel_width ,
num_vc => num_vc ,
flit_buff_depth => flit_buff_depth
)
port map(
clk => clock_50,
rst => noc_rst,
recv_data => recv_data_pe5,
src_addr => src_addr_pe5,
is_tail_flit => is_tail_flit_pe5,
data_in_buffer => data_in_buffer_pe5,
dequeue => dequeue_pe5,
select_vc_read => select_vc_read_pe5,
send_data => send_data_pe5,
dest_addr => dest_addr_pe5,
set_tail_flit => set_tail_flit_pe5,
send_flit => send_flit_pe5,
ready_to_send => ready_to_send_pe5
);
n1: component inter_node
generic map(
size_x => 16,
size_y => 9,
interp_x => 4 ,
interp_y => 2 ,
sample_size => 8 ,
samples_per_wr => 8 ,
data_width => data_width ,
addr_width => addr_width ,
vc_sel_width => vc_sel_width ,
num_vc => num_vc ,
flit_buff_depth => flit_buff_depth
)
port map(
clk => clock_50,
rst => noc_rst,
recv_data => recv_data_pe2,
src_addr => src_addr_pe2,
is_tail_flit => is_tail_flit_pe2,
data_in_buffer => data_in_buffer_pe2,
dequeue => dequeue_pe2,
select_vc_read => select_vc_read_pe2,
send_data => send_data_pe2,
dest_addr => dest_addr_pe2,
set_tail_flit => set_tail_flit_pe2,
send_flit => send_flit_pe2,
ready_to_send => ready_to_send_pe2
);
n3: component noc_control_plus
generic map(
data_width => data_width ,
addr_width => addr_width ,
vc_sel_width => vc_sel_width ,
num_vc => num_vc ,
flit_buff_depth => flit_buff_depth
)
port map(
clk => clock_50,
rst => noc_rst,
recv_data => recv_data_pe0,
src_addr => src_addr_pe0,
is_tail_flit => is_tail_flit_pe0,
data_in_buffer => data_in_buffer_pe0,
dequeue => dequeue_pe0,
select_vc_read => select_vc_read_pe0,
send_data => send_data_pe0,
dest_addr => dest_addr_pe0,
set_tail_flit => set_tail_flit_pe0,
send_flit => send_flit_pe0,
ready_to_send => ready_to_send_pe0,
set_tail_cpu => noc_ctrl_cpu_0(31),
addr_cpu => std_logic_vector(resize(unsigned(noc_ctrl_cpu_0(23 downto 16)),addr_width)),
format_select => noc_ctrl_cpu_0(7 downto 0),
send_cmd_cpu => noc_ctrl_cpu_0(30),
send_ack => noc_sts_cpu_0(31),
parse_select => noc_ctrl_cpu_0(15 downto 8),
cpu_rx_ctrl => noc_ctrl_cpu_0(29),
rx_state_out => noc_sts_cpu_0(7 downto 0),
rx_0 => cpu_0_rx_0_external_connection_export,
rx_1 => cpu_0_rx_1_external_connection_export,
rx_2 => cpu_0_rx_2_external_connection_export,
rx_3 => cpu_0_rx_3_external_connection_export,
rx_4 => cpu_0_rx_4_external_connection_export,
rx_5 => cpu_0_rx_5_external_connection_export,
rx_6 => cpu_0_rx_6_external_connection_export,
rx_7 => cpu_0_rx_7_external_connection_export,
tx_0 => cpu_0_tx_0_external_connection_export,
tx_1 => cpu_0_tx_1_external_connection_export,
tx_2 => cpu_0_tx_2_external_connection_export,
tx_3 => cpu_0_tx_3_external_connection_export,
tx_4 => cpu_0_tx_4_external_connection_export,
tx_5 => cpu_0_tx_5_external_connection_export,
tx_6 => cpu_0_tx_6_external_connection_export,
tx_7 => cpu_0_tx_7_external_connection_export
);
n4: component chroma_motion
generic map(
data_width => data_width ,
addr_width => addr_width ,
vc_sel_width => vc_sel_width ,
num_vc => num_vc ,
flit_buff_depth => flit_buff_depth
)
port map(
clk => clock_50,
rst => noc_rst,
recv_data => recv_data_pe4,
src_addr => src_addr_pe4,
is_tail_flit => is_tail_flit_pe4,
data_in_buffer => data_in_buffer_pe4,
dequeue => dequeue_pe4,
select_vc_read => select_vc_read_pe4,
send_data => send_data_pe4,
dest_addr => dest_addr_pe4,
set_tail_flit => set_tail_flit_pe4,
send_flit => send_flit_pe4,
ready_to_send => ready_to_send_pe4
);
n6: component iqit_node
generic map(
sample_width => 8,
qp_width => 8,
wo_dc_width => 8,
data_width => data_width ,
addr_width => addr_width ,
vc_sel_width => vc_sel_width ,
num_vc => num_vc ,
flit_buff_depth => flit_buff_depth
)
port map(
clk => clock_50,
rst => noc_rst,
recv_data => recv_data_pe6,
src_addr => src_addr_pe6,
is_tail_flit => is_tail_flit_pe6,
data_in_buffer => data_in_buffer_pe6,
dequeue => dequeue_pe6,
select_vc_read => select_vc_read_pe6,
send_data => send_data_pe6,
dest_addr => dest_addr_pe6,
set_tail_flit => set_tail_flit_pe6,
send_flit => send_flit_pe6,
ready_to_send => ready_to_send_pe6
);
n7: component noc_control_plus
generic map(
data_width => data_width ,
addr_width => addr_width ,
vc_sel_width => vc_sel_width ,
num_vc => num_vc ,
flit_buff_depth => flit_buff_depth
)
port map(
clk => clock_50,
rst => noc_rst,
recv_data => recv_data_pe7,
src_addr => src_addr_pe7,
is_tail_flit => is_tail_flit_pe7,
data_in_buffer => data_in_buffer_pe7,
dequeue => dequeue_pe7,
select_vc_read => select_vc_read_pe7,
send_data => send_data_pe7,
dest_addr => dest_addr_pe7,
set_tail_flit => set_tail_flit_pe7,
send_flit => send_flit_pe7,
ready_to_send => ready_to_send_pe7,
set_tail_cpu => noc_ctrl_cpu_1(31),
addr_cpu => std_logic_vector(resize(unsigned(noc_ctrl_cpu_1(23 downto 16)),addr_width)),
format_select => noc_ctrl_cpu_1(7 downto 0),
send_cmd_cpu => noc_ctrl_cpu_1(30),
send_ack => noc_sts_cpu_1(31),
parse_select => noc_ctrl_cpu_1(15 downto 8),
cpu_rx_ctrl => noc_ctrl_cpu_1(29),
rx_state_out => noc_sts_cpu_1(7 downto 0),
rx_0 => cpu_1_rx_0_external_connection_export,
rx_1 => cpu_1_rx_1_external_connection_export,
rx_2 => cpu_1_rx_2_external_connection_export,
rx_3 => cpu_1_rx_3_external_connection_export,
rx_4 => cpu_1_rx_4_external_connection_export,
rx_5 => cpu_1_rx_5_external_connection_export,
rx_6 => cpu_1_rx_6_external_connection_export,
rx_7 => cpu_1_rx_7_external_connection_export,
tx_0 => cpu_1_tx_0_external_connection_export,
tx_1 => cpu_1_tx_1_external_connection_export,
tx_2 => cpu_1_tx_2_external_connection_export,
tx_3 => cpu_1_tx_3_external_connection_export,
tx_4 => cpu_1_tx_4_external_connection_export,
tx_5 => cpu_1_tx_5_external_connection_export,
tx_6 => cpu_1_tx_6_external_connection_export,
tx_7 => cpu_1_tx_7_external_connection_export
);
n8: component vga_node
generic map(
data_width => data_width ,
addr_width => addr_width ,
vc_sel_width => vc_sel_width ,
num_vc => num_vc ,
flit_buff_depth => flit_buff_depth
)
port map(
clk => clock_50,
rst => noc_rst,
recv_data => recv_data_pe8,
src_addr => src_addr_pe8,
is_tail_flit => is_tail_flit_pe8,
data_in_buffer => data_in_buffer_pe8,
dequeue => dequeue_pe8,
select_vc_read => select_vc_read_pe8,
send_data => send_data_pe8,
dest_addr => dest_addr_pe8,
set_tail_flit => set_tail_flit_pe8,
send_flit => send_flit_pe8,
ready_to_send => ready_to_send_pe8,
clk27 => vga_clk_sig,
rst27 => noc_rst,
vga_red => vga_r(7 downto 2),
vga_blue => vga_b(7 downto 2),
vga_green => vga_g(7 downto 2),
vga_v_sync => vga_vs,
vga_h_sync => vga_hs
);
--n9: component inter_node
--generic map(
--size_x => 16,
--size_y => 9,
--interp_x => 4 ,
--interp_y => 2 ,
--sample_size => 8 ,
--samples_per_wr => 8 ,
--data_width => data_width ,
--addr_width => addr_width ,
--vc_sel_width => vc_sel_width ,
--num_vc => num_vc ,
--flit_buff_depth => flit_buff_depth
--)
--port map(
-- clk => clock_50,
-- rst => noc_rst,
-- recv_data => recv_data_pe9,
-- src_addr => src_addr_pe9,
-- is_tail_flit => is_tail_flit_pe9,
-- data_in_buffer => data_in_buffer_pe9,
-- dequeue => dequeue_pe9,
-- select_vc_read => select_vc_read_pe9,
-- send_data => send_data_pe9,
-- dest_addr => dest_addr_pe9,
-- set_tail_flit => set_tail_flit_pe9,
-- send_flit => send_flit_pe9,
-- ready_to_send => ready_to_send_pe9
--);
VGA_CLK <= vga_clk_sig;
VGA_BLANK_N <= '1';
VGA_SYNC_N <= '1';
VGA_R(1 downto 0) <= (others => '0');
VGA_G(1 downto 0) <= (others => '0');
VGA_B(1 downto 0) <= (others => '0');
--noc_status_export(31 downto 4) <= (others => '0');
noc_rst <= noc_ctrl_cpu_0(28) or noc_ctrl_cpu_1(28);
noc_ctrl_cpu_0 <= noc_ctrl_0_external_connection_export;
noc_ctrl_cpu_1 <= noc_ctrl_1_external_connection_export;
noc_status_0_external_connection_export <= noc_sts_cpu_0;
noc_status_1_external_connection_export <= noc_sts_cpu_1;
END MAIN; | mit | 93666544425cf09c74dd1c45614eefa5 | 0.501686 | 3.592397 | false | false | false | false |
peladex/RHD2132_FPGA | quartus/test_spi_de0/rebot_elim.vhd | 1 | 1,433 | ---------------------------------------------------------
-- REBOT_ELIM
-- creacion 09/04/05
-- Circuito eliminador de rebotes
--
-- Circuito utilizado para generar pulsos mediante dos pulsadores.
-- Si la entrada Sn=0 ==> Q=0
-- Si la entrada Rn=0 ==> Q=1
-- Si Sn=Rn=1 se mantiene el valor de Q
-- Sn = 0 tiene prioridad sobre Rn = O
--
---------------------------------------------------------
---------------------------------------------------------
----- package PK_REBOT_ELIM
---------------------------------------------------------
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
PACKAGE pk_rebot_elim IS
COMPONENT rebot_elim is
PORT(
Sn, Rn : in std_logic;
Q : out std_logic
);
END COMPONENT;
END PACKAGE;
-----------------------------------------------------------
----- ENTITY REBOT_ELIM
-----------------------------------------------------------
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
entity rebot_elim is
port(
Sn, Rn : in std_logic;
Q : out std_logic
);
end rebot_elim;
architecture BEHAV of rebot_elim is
begin
---------------------------------------
eliminador_de_rebotes: process (Sn, Rn)
---------------------------------------
begin
if (Sn = '0') then
Q <= '1';
elsif (Rn = '0') then
Q <= '0';
end if;
end process;
end BEHAV; | gpl-3.0 | f93f79ac0aa28fb0b47526055c5da14f | 0.388695 | 4.141618 | false | false | false | false |
peladex/RHD2132_FPGA | quartus/test_spi_de0/test_spi_side.vhd | 2 | 8,462 | -----------------------------------------------------------------------------------------------------------------------
-- Author:
--
-- Create Date: 09/11/2016 -- dd/mm/yyyy
-- Module Name: test_spi_side
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- ...
--
-----------------------------------------------------------------------------------------------------------------------
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
LIBRARY lpm;
USE lpm.lpm_components.ALL;
ENTITY test_spi_side IS
PORT(
m_clk : in std_logic; -- master clock
m_reset : in std_logic; -- master reset
---- master_control interface ----
di_1_i : in std_logic_vector(15 downto 0);
do_1_o : out std_logic_vector(15 downto 0);
wren_1_i : in std_logic;
drdy_1_o : out std_logic;
rdreq_1_i : in std_logic;
di_2_i : in std_logic_vector(15 downto 0);
do_2_o : out std_logic_vector(15 downto 0);
wren_2_i : in std_logic;
drdy_2_o : out std_logic;
rdreq_2_i : in std_logic;
---- fifo 1 interface ----
f1_do_o : out std_logic_vector(15 downto 0);
f1_wren_o : out std_logic;
---- fifo 2 interface ----
f2_do_o : out std_logic_vector(15 downto 0);
f2_wren_o : out std_logic;
---- serial interface 1 ----
spi1_ssel_o : out std_logic; -- spi bus slave select line
spi1_sck_o : out std_logic; -- spi bus sck
spi1_mosi_o : out std_logic; -- spi bus mosi output
spi1_miso_i : in std_logic := 'X'; -- spi bus spi_miso_i input
---- serial interface 2 ----
spi2_ssel_o : out std_logic; -- spi bus slave select line
spi2_sck_o : out std_logic; -- spi bus sck
spi2_mosi_o : out std_logic; -- spi bus mosi output
spi2_miso_i : in std_logic := 'X' -- spi bus spi_miso_i input
);
END test_spi_side;
ARCHITECTURE synth OF test_spi_side IS
---- COMPONENTS
COMPONENT interconnect IS
PORT (
---- master_control interface ----
di_1_i : in std_logic_vector(15 downto 0);
do_1_o : out std_logic_vector(15 downto 0);
wren_1_i : in std_logic; --triggers spi cycle
drdy_1_o : out std_logic;
rdreq_1_i : in std_logic;
di_2_i : in std_logic_vector(15 downto 0);
do_2_o : out std_logic_vector(15 downto 0);
wren_2_i : in std_logic; --triggers spi cycle
drdy_2_o : out std_logic;
rdreq_2_i : in std_logic;
---- spi 1 interface ----
s1_do_o : out std_logic_vector(15 downto 0);
s1_di_i : in std_logic_vector(15 downto 0);
s1_wren_o : out std_logic;
s1_drdy_i : in std_logic;
---- spi 2 interface ----
s2_do_o : out std_logic_vector(15 downto 0);
s2_di_i : in std_logic_vector(15 downto 0);
s2_wren_o : out std_logic;
s2_drdy_i : in std_logic;
---- fifo 1 interface ----
f1_do_o : out std_logic_vector(15 downto 0);
f1_wren_o : out std_logic;
---- fifo 2 interface ----
f2_do_o : out std_logic_vector(15 downto 0);
f2_wren_o : out std_logic
);
END COMPONENT;
COMPONENT spi_master IS
Generic (
N : positive := 16; -- 32bit serial word length is default
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
CPHA : std_logic := '0'; -- CPOL = clock polarity, CPHA = clock phase.
PREFETCH : positive := 2; -- prefetch lookahead cycles
SPI_2X_CLK_DIV : positive := 2); -- for a 100MHz sclk_i, yields a 25MHz SCK
Port (
sclk_i : in std_logic := 'X'; -- high-speed serial interface system clock
pclk_i : in std_logic := 'X'; -- high-speed parallel interface system clock
rst_i : in std_logic := 'X'; -- reset core
---- serial interface ----
spi_ssel_o : out std_logic; -- spi bus slave select line
spi_sck_o : out std_logic; -- spi bus sck
spi_mosi_o : out std_logic; -- spi bus mosi output
spi_miso_i : in std_logic := 'X'; -- spi bus spi_miso_i input
---- parallel interface ----
di_req_o : out std_logic; -- preload lookahead data request line
di_i : in std_logic_vector (N-1 downto 0) := (others => 'X'); -- parallel data in (clocked on rising spi_clk after last bit)
wren_i : in std_logic := 'X'; -- user data write enable, starts transmission when interface is idle
wr_ack_o : out std_logic; -- write acknowledge
do_valid_o : out std_logic; -- do_o data valid signal, valid during one spi_clk rising edge.
do_o : out std_logic_vector (N-1 downto 0); -- parallel output (clocked on rising spi_clk after last bit)
--- debug ports: can be removed or left unconnected for the application circuit ---
sck_ena_o : out std_logic; -- debug: internal sck enable signal
sck_ena_ce_o : out std_logic; -- debug: internal sck clock enable signal
do_transfer_o : out std_logic; -- debug: internal transfer driver
wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher
rx_bit_reg_o : out std_logic; -- debug: internal rx bit
state_dbg_o : out std_logic_vector (3 downto 0); -- debug: internal state register
core_clk_o : out std_logic;
core_n_clk_o : out std_logic;
core_ce_o : out std_logic;
core_n_ce_o : out std_logic;
sh_reg_dbg_o : out std_logic_vector (N-1 downto 0) -- debug: internal shift register
);
END COMPONENT;
---- SIGNALS
SIGNAL sg_pll_out_clk : std_logic;
SIGNAL sg_do_1, sg_di_1 : std_logic_vector(15 downto 0);
SIGNAL sg_wren_1, sg_drdy_1 : std_logic;
SIGNAL sg_do_2, sg_di_2 : std_logic_vector(15 downto 0);
SIGNAL sg_wren_2, sg_drdy_2 : std_logic;
BEGIN
---- INSTANCES
U0: interconnect PORT MAP (
---- master_control interface ----
di_1_i => di_1_i,
do_1_o => do_1_o,
wren_1_i => wren_1_i,
drdy_1_o => drdy_1_o,
rdreq_1_i => rdreq_1_i,
di_2_i => di_2_i,
do_2_o => do_2_o,
wren_2_i => wren_2_i,
drdy_2_o => drdy_2_o,
rdreq_2_i => rdreq_2_i,
---- spi 1 interface ----
s1_do_o => sg_do_1,
s1_di_i => sg_di_1,
s1_wren_o => sg_wren_1,
s1_drdy_i => sg_drdy_1,
---- spi 2 interface ----
s2_do_o => sg_do_2,
s2_di_i => sg_di_2,
s2_wren_o => sg_wren_2,
s2_drdy_i => sg_drdy_2,
---- fifo 1 interface ----
f1_do_o => f1_do_o,
f1_wren_o => f1_wren_o,
---- fifo 2 interface ----
f2_do_o => f2_do_o,
f2_wren_o => f2_wren_o
);
SPI_1: spi_master PORT MAP (
sclk_i => sg_pll_out_clk,
pclk_i => sg_pll_out_clk,
rst_i => m_reset,
---- serial interface ----
spi_ssel_o => spi1_ssel_o,
spi_sck_o => spi1_sck_o,
spi_mosi_o => spi1_mosi_o,
spi_miso_i => spi1_miso_i,
---- parallel interface ----
di_i => sg_do_1,
wren_i => sg_wren_1,
do_valid_o => sg_drdy_1,
do_o => sg_di_1
);
SPI_2: spi_master PORT MAP (
sclk_i => sg_pll_out_clk,
pclk_i => sg_pll_out_clk,
rst_i => m_reset,
---- serial interface ----
spi_ssel_o => spi2_ssel_o,
spi_sck_o => spi2_sck_o,
spi_mosi_o => spi2_mosi_o,
spi_miso_i => spi2_miso_i,
---- parallel interface ----
di_i => sg_do_2,
wren_i => sg_wren_2,
do_valid_o => sg_drdy_2,
do_o => sg_di_2
);
sg_pll_out_clk <= m_clk;
END synth; | gpl-3.0 | 1ca23d42a6eca8b100e51671a9238377 | 0.482746 | 3.305469 | false | false | false | false |
boztalay/OldProjects | FPGA/FlashProgrammer/FlashReadTest/FlashReadTest.vhd | 1 | 3,007 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02:28:59 11/25/2009
-- Design Name:
-- Module Name: FlashReadTest - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity FlashReadTest is
Port ( mclk : in STD_LOGIC;
DQ : in STD_LOGIC_VECTOR(15 downto 0);
A : out STD_LOGIC_VECTOR(22 downto 0);
an : out STD_LOGIC_VECTOR(3 downto 0);
a_to_g : out STD_LOGIC_VECTOR(6 downto 0);
clk_led : out STD_LOGIC;
FlashCE_L : out STD_LOGIC;
FlashRP_L : out STD_LOGIC;
WE_L : out STD_LOGIC;
OE_L : out STD_LOGIC;
CE_L : out STD_LOGIC);
end FlashReadTest;
architecture Behavioral of FlashReadTest is
signal clk_1hz : STD_LOGIC := '0';
signal to_decoder : STD_LOGIC_VECTOR(3 downto 0);
component Comp_7segDecoder is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
seg : out STD_LOGIC_VECTOR (6 downto 0));
end component;
begin
FlashCE_L <= '0';
CE_L <= '1';
WE_L <= '1';
FlashRP_L <= '1';
OE_L <= '0';
clocker: process (mclk) is
variable count : integer := 0;
begin
if rising_edge(mclk) then
count := count + 1;
end if;
if count = 50000000 then
count := 0;
clk_1hz <= '0';
end if;
if count = 25000000 then
clk_1hz <= '1';
end if;
end process;
counter: process (clk_1hz) is
variable addr_count : STD_LOGIC_VECTOR(22 downto 0) := b"00000000000000000000000";
begin
if rising_edge(clk_1hz) then
addr_count := addr_count + 1;
end if;
A <= addr_count;
end process;
disp_data: process(DQ, mclk) is
variable clk_count : integer := 0;
variable disp_count : integer := 0;
begin
if rising_edge(mclk) then
clk_count := clk_count + 1;
if clk_count = 250000 then
disp_count := disp_count + 1;
clk_count := 0;
if disp_count = 4 then
disp_count := 0;
end if;
end if;
end if;
if disp_count = 0 then
an <= "1110";
to_decoder <= DQ(3 downto 0);
elsif disp_count = 1 then
an <= "1101";
to_decoder <= DQ(7 downto 4);
elsif disp_count = 2 then
an <= "1011";
to_decoder <= DQ(11 downto 8);
elsif disp_count = 3 then
an <= "0111";
to_decoder <= DQ(15 downto 12);
end if;
end process;
decoder : Comp_7segDecoder port map (to_decoder,
a_to_g);
clk_led <= clk_1Hz;
end Behavioral;
| mit | 02abdbd59c6d2f4ba0eed8e69c0670ee | 0.551048 | 3.198936 | false | false | false | false |
boztalay/OldProjects | FPGA/LCD_Control/Clock_Gen.vhd | 1 | 1,351 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:50:30 10/15/2009
-- Design Name:
-- Module Name: Clock_Gen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Clock_Gen is
Port ( Board_Clock : in STD_LOGIC;
Sys_Clock : out STD_LOGIC);
end Clock_Gen;
architecture Behavioral of Clock_Gen is
begin
main: process(Board_Clock) is
constant hertz : integer := 100000;
constant cycles : integer := (25_000_000/hertz);
variable count : integer := 0;
variable output : STD_LOGIC := '0';
begin
if rising_edge(Board_Clock) then
count := count + 1;
if count > cycles then
count := 0;
output := not output;
end if;
end if;
Sys_Clock <= output;
end process main;
end Behavioral;
| mit | f595c108ad73b002023484e72c2d40b6 | 0.556625 | 3.621984 | false | false | false | false |
AfterRace/SoC_Project | vivado/project/project.srcs/sources_1/ipshared/user.org/audio_to_axi_v1_0/27de6532/hdl/audio_to_AXI_v1_0_S00_AXI.vhd | 2 | 16,287 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity audio_to_AXI_v1_0_S00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
-- Users to add ports here
audio_in_l : in std_logic_vector(23 downto 0);
audio_in_r : in std_logic_vector(23 downto 0);
audio_in_valid : in std_logic;
audio_out_valid_irq : out std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end audio_to_AXI_v1_0_S00_AXI;
architecture arch_imp of audio_to_AXI_v1_0_S00_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 1;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 4
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
-- Declaration of user logic
component audio_bridge
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
audio_in_l : in STD_LOGIC_VECTOR (23 downto 0);
audio_in_r : in STD_LOGIC_VECTOR (23 downto 0);
audio_in_valid : in STD_LOGIC;
audio_out_l : out STD_LOGIC_VECTOR (23 downto 0);
audio_out_r : out STD_LOGIC_VECTOR (23 downto 0);
audio_out_valid : out STD_LOGIC);
end component audio_bridge;
signal audio_out_l_axi : std_logic_vector(31 downto 0);
signal audio_out_r_axi : std_logic_vector(31 downto 0);
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"00" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"11" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (audio_out_l_axi, audio_out_r_axi, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"00" =>
reg_data_out <= audio_out_l_axi;
when b"01" =>
reg_data_out <= audio_out_r_axi;
when b"10" =>
reg_data_out <= (others => '0');
when b"11" =>
reg_data_out <= (others => '0');
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
audio_bridge_0 : audio_bridge
port map(
audio_out_valid => audio_out_valid_irq,
audio_out_l => audio_out_l_axi(23 downto 0),
audio_out_r => audio_out_r_axi(23 downto 0),
audio_in_valid => audio_in_valid,
audio_in_l => audio_in_l,
audio_in_r => audio_in_r,
rst => S_AXI_ARESETN,
clk => S_AXI_ACLK
);
-- User logic ends
end arch_imp;
| lgpl-3.0 | 65742b933034a1545a71576ea823d368 | 0.610303 | 3.444797 | false | false | false | false |
AfterRace/SoC_Project | vivado/project/project.srcs/sources_1/ipshared/tsotnep/filter_iir_v1_0/263d46e2/src/Multiplier.vhd | 2 | 9,257 | library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
entity multiplier is
generic(MultiplierIsShiftAdd : boolean := true;
BIT_WIDTH : positive := 16; --Size on input/output vectors
COUNT_WIDTH : positive := 5); --Size of the counter signal
--COUNT_WIDTH needs to be the exact size required to fit Output signal
-- for example if BIT_WIDHT is 16, COUNT_WIDHT needs to be 5.
-- The size of the output vector is 2 times the size of the input vector.
port(CLK : in std_logic; --clock
TRIGGER : in std_logic; --RESET signal (pulse)
A : in signed((BIT_WIDTH - 1) downto 0); --multiplicand
B : in signed((BIT_WIDTH - 1) downto 0); --mutiplier
RES : out signed((BIT_WIDTH * 2 - 1) downto 0) := (others => '0'); --result
READY : out std_logic := '0'); --Calculation ready signal (pulse)
end multiplier;
architecture Behavioral of multiplier is
type reg_type is record
counter : unsigned((COUNT_WIDTH - 1) downto 0);
EN : std_logic;
tmp1 : signed((BIT_WIDTH * 2 - 1) downto 0); -- B
tmp2 : signed((BIT_WIDTH * 2 - 1) downto 0);
tmpA : signed((BIT_WIDTH - 1) downto 0); -- A
end record;
signal r, rin : reg_type := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
signal s_RES, r_late : signed((BIT_WIDTH * 2 - 1) downto 0) := (others => '0');
signal s_READY, sr_READY, sr_recalc : std_logic;
constant c_trigger : std_logic := '0';
begin
--Control logic of the multiplication algorithm
ShiftAdd : if MultiplierIsShiftAdd = true generate
READY <= sr_READY;
combinational : process(A, B, r, TRIGGER, sr_recalc, r_late)
variable v : reg_type := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
begin
s_RES <= r_late;
rin <= r;
s_READY <= '0';
if sr_recalc = '1' then
if (TRIGGER = c_trigger) then
v := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
s_RES <= (others => '0');
s_READY <= '0';
else
v := r;
v.counter := v.counter - 1; --At first cycle the counter ovwerflows and sets all bits to '1'-s giving the value of BIT_WIDTH - 1
--Initialisation. Copy inputs to variables for manipulation and protection
--against the changing of the inputs while calculating. We also reset the counter.
s_RES <= v.tmp1;
if (v.counter = 2 * BIT_WIDTH - 1) then
s_READY <= '1' and v.EN; --Output the READY signal only when we have a real answer
v.EN := '1';
v.tmpA := A;
v.tmp1 := RESIZE(B, RES'LENGTH);
v.tmp2 := (others => '0');
else
s_READY <= '0';
end if;
--check if we have to add
if (v.tmp1(0) = '1') then
v.tmp2 := v.tmp2 + v.tmpA;
end if;
--Next we are going to arithmetically shift tmp2 to the right so, that
--the bit that gets shifted out of it will shift into tmp1 from right
v.tmp1 := shift_right(v.tmp1, 1);
v.tmp1(2 * BIT_WIDTH - 1) := v.tmp2(0);
v.tmp2 := shift_right(v.tmp2, 1);
end if;
rin <= v;
end if;
end process combinational;
sequential : process(CLK)
begin
if rising_edge(CLK) then
r <= rin;
if s_READY = '1' then
r_late <= r.tmp1; --
end if;
end if;
end process sequential;
process(CLK, TRIGGER)
begin
if TRIGGER = c_trigger then
RES <= (others => '0');
sr_READY <= '0';
elsif rising_edge(CLK) then
if s_READY = '1' then
RES <= s_RES; --rin.tmp1;--
sr_READY <= '1'; -- registered Ready signal. the ready signal we remain high until the multplier is reset again
end if;
end if;
end process;
process(CLK, TRIGGER)
begin
if TRIGGER = c_trigger then
sr_recalc <= '1';
elsif rising_edge(CLK) then
if s_READY = '1' then
sr_recalc <= '0';
end if;
end if;
end process;
end generate;
DedicatedMultiplier : if MultiplierIsShiftAdd = false generate
P_Multiply : process(TRIGGER, A, B)
variable v_mul_res : signed((BIT_WIDTH * 2 - 1) downto 0);
variable v_A, v_B : signed((BIT_WIDTH - 1) downto 0);
variable v_en : std_logic := '0';
begin
if (TRIGGER = c_trigger) then
v_mul_res := (others => '0');
v_A := (others => '0');
v_B := (others => '0');
RES <= (others => '0');
READY <= '0';
v_en := '0';
else
v_A := A;
v_B := B;
v_mul_res := v_A * v_B;
v_en := '1';
end if;
RES <= v_mul_res;
READY <= '1' and v_en;
end process;
end generate;
end Behavioral;
--library IEEE;
--use IEEE.std_logic_1164.all;
--use ieee.numeric_std.all;
--
--entity multiplier is
-- generic ( MultiplierIsShiftAdd: boolean:=true;
-- BIT_WIDTH : positive := 16; --Size on input/output vectors
-- COUNT_WIDTH : positive := 5); --Size of the counter signal
-- --COUNT_WIDTH needs to be the exact size required to fit Output signal
-- -- for example if BIT_WIDHT is 16, COUNT_WIDHT needs to be 5.
-- -- The size of the output vector is 2 times the size of the input vector.
--
-- Port ( CLK : in std_logic; --clock
-- TRIGGER : in std_logic; --RESET signal (pulse)
-- A : in signed ((BIT_WIDTH - 1) downto 0); --multiplicand
-- B : in signed ((BIT_WIDTH - 1) downto 0); --mutiplier
-- RES : out signed ((BIT_WIDTH*2 - 1) downto 0) := (others => '0'); --result
-- READY : out std_logic := '0'); --Calculation ready signal (pulse)
--end multiplier;
--
--
--architecture Behavioral of multiplier is
-- type reg_type is record
-- counter : unsigned ( (COUNT_WIDTH-1) downto 0 );
-- EN : std_logic;
-- tmp1 : signed ((BIT_WIDTH*2 - 1) downto 0); -- B
-- tmp2 : signed ((BIT_WIDTH*2 - 1) downto 0);
-- tmpA : signed ((BIT_WIDTH - 1) downto 0); -- A
-- end record;
-- signal r, rin : reg_type := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
--begin
--
-- --Control logic of the multiplication algorithm
--ShiftAdd: if MultiplierIsShiftAdd = true generate
-- combinational : process(A, B, r, TRIGGER)
-- variable v : reg_type := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
--
-- begin
-- if (TRIGGER = '0') then
-- v := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
-- RES <= (others => '0');
-- READY <= '0';
-- else
-- v := r;
-- v.counter := v.counter -1; --At first cycle the counter ovwerflows and sets all bits to '1'-s giving the value of BIT_WIDTH - 1
-- --Initialisation. Copy inputs to variables for manipulation and protection
-- --against the changing of the inputs while calculating. We also TRIGGER the counter.
-- RES <= v.tmp1;
-- if (v.counter = 2*BIT_WIDTH-1) then
-- READY <= '1' and v.EN; --Output the READY signal only when we have a real answer
-- v.EN := '1';
-- v.tmpA := A;
-- v.tmp1 := RESIZE(B,RES'LENGTH);
-- v.tmp2 := (others => '0');
-- else
-- READY <= '0';
-- end if;
--
-- --check if we have to add
-- if (v.tmp1(0) = '1') then
-- v.tmp2 := v.tmp2 + v.tmpA;
-- end if;
--
-- --Next we are going to arithmetically shift tmp2 to the right so, that
-- --the bit that gets shifted out of it will shift into tmp1 from right
-- v.tmp1 := shift_right(v.tmp1, 1);
-- v.tmp1(2*BIT_WIDTH-1) := v.tmp2(0);
-- v.tmp2 := shift_right(v.tmp2, 1);
-- end if;
-- rin <= v;
-- end process combinational;
--
-- sequential : process (CLK)
-- begin
-- if rising_edge(CLK) then
-- r <= rin;
-- end if;
-- end process sequential;
--end generate;
--
-- DedicatedMultiplier: if MultiplierIsShiftAdd = false generate
-- P_Multiply: process(TRIGGER,A,B)
-- variable v_mul_res: signed ((BIT_WIDTH*2 - 1) downto 0);
-- variable v_A, v_B: signed ((BIT_WIDTH - 1) downto 0);
-- variable v_en: std_logic:='0';
-- begin
-- if (TRIGGER = '0') then
-- v_mul_res := (others => '0');
-- v_A := (others => '0');
-- v_B := (others => '0');
-- RES <= (others => '0');
-- READY <= '0';
-- v_en := '0';
-- else
-- v_A := A;
-- v_B := B;
-- v_mul_res := v_A * v_B;
-- v_en := '1';
-- end if;
-- RES <= v_mul_res;
-- READY <= '1' and v_en;
-- end process;
-- end generate;
--end Behavioral;
--
| lgpl-3.0 | c15822a1be92e539080a71b98e4ec224 | 0.507616 | 3.106376 | false | false | false | false |
bargei/NoC264 | NoC264_3x3/chroma_motion.vhd | 1 | 12,683 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.math_real.all;
-------------------------------------------------------------------------------
--- chroma_motion.vhd
--- Ian Barge, 2017
---
--- Implements an NoC node for performing motion compensation on chroma samples.
--- Designed for use with the NoC generated using CONNECT
--- http://users.ece.cmu.edu/~mpapamic/connect/
---
--- see https://www.itu.int/rec/T-REC-H.264-201610-I/en for more information on
--- this algorith (section 8.4.2.2.2) and h.264 as a whole
---
--- Input packet format:
--- flit 0: 63..40 RESERVED
--- 39..32 motion vector Cr channel, x component
--- 31..24 motion vector Cr channel, y component
--- 23..16 motion vector Cb channel, x component
--- 15..8 motion vector Cb channel, y component
--- 7..0 packet identifier
---
--- flit 1: Cr reference (0,0), (1,0), (2,0), (0,1), (1,1), (2,1), ... (1,2)*
--- flit 2: Cb reference (0,0), (1,0), (2,0), (0,1), (1,1), (2,1), ... (1,2)*
--- flit 3: 63..40: RESERVED
--- 39..32: Cr reference (2,2)
--- 31..8: RESERVED
--- 7..0: Cb reference (2,2)
--- * 8 bits each
entity chroma_motion is
generic(
data_width : integer := 64;
addr_width : integer := 4;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
-- recv interface to network
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
-- send interface to network
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic
);
end entity chroma_motion;
architecture fsmd of chroma_motion is
--- Components ------------------------------------------------------------
component priority_encoder is
generic(
encoded_word_size : integer := 3
);
Port(
input : in std_logic_vector(2**encoded_word_size-1 downto 0);
output : out std_logic_vector(encoded_word_size-1 downto 0)
);
end component priority_encoder;
--- Types -----------------------------------------------------------------
type chroma_motion_states is (idle,
sel_vc,
rx_header,
dequeue_header,
wait_rx_cr,
rx_cr,
dequeue_cr,
wait_rx_cb,
rx_cb,
dequeue_cb,
wait_rx_crcb,
rx_crcb,
dequeue_crcb,
wait_tx_header,
tx_header,
wait_tx_data,
tx_data);
type reference_array is array (8 downto 0) of integer;
type result_array is array (3 downto 0) of integer;
--- signals and registers -------------------------------------------------
signal cr_ref_d : reference_array;
signal cb_ref_d : reference_array;
signal cr_ref_q : reference_array;
signal cb_ref_q : reference_array;
signal cr_result : result_array;
signal cb_result : result_array;
signal cr_x_frac_d : integer;
signal cr_y_frac_d : integer;
signal cr_x_frac_q : integer;
signal cr_y_frac_q : integer;
signal cb_x_frac_d : integer;
signal cb_y_frac_d : integer;
signal cb_x_frac_q : integer;
signal cb_y_frac_q : integer;
signal ref_d : std_logic_vector(7 downto 0);
signal ref_q : std_logic_vector(7 downto 0);
signal result_vect : std_logic_vector(63 downto 0);
signal resp_header : std_logic_vector(63 downto 0);
signal state : chroma_motion_states;
signal next_state : chroma_motion_states;
signal sel_vc_d : std_logic_vector(vc_sel_width-1 downto 0);
signal sel_vc_q : std_logic_vector(vc_sel_width-1 downto 0);
signal sel_vc_enc : std_logic_vector(vc_sel_width-1 downto 0);
signal sel_vc_one_hot : std_logic_vector(num_vc-1 downto 0);
begin
---------------------------------------------------------------------------
--- DATAPATH --------------------------------------------------------------
---------------------------------------------------------------------------
--components
u2: component priority_encoder
generic map(
encoded_word_size => vc_sel_width
)
Port map(
input => data_in_buffer,
output => sel_vc_enc
);
--registers
regs: process(clk, rst) begin
if rst = '1' then
cr_ref_q <= (others => 0);
cb_ref_q <= (others => 0);
cr_x_frac_q <= 0;
cr_y_frac_q <= 0;
cb_x_frac_q <= 0;
cb_y_frac_q <= 0;
ref_q <= (others => '0');
sel_vc_q <= (others => '0');
state <= idle;
elsif rising_edge(clk) then
cr_ref_q <= cr_ref_d;
cb_ref_q <= cb_ref_d;
cr_x_frac_q <= cr_x_frac_d;
cr_y_frac_q <= cr_y_frac_d;
cb_x_frac_q <= cb_x_frac_d;
cb_y_frac_q <= cb_y_frac_d;
ref_q <= ref_d;
sel_vc_q <= sel_vc_d;
state <= next_state;
end if;
end process;
--register update
reg_update: for i in 7 downto 0 generate
constant recv_data_low_index : integer := i * 8;
constant recv_data_high_index : integer := recv_data_low_index + 7;
begin
cr_ref_d(i) <= to_integer(unsigned(recv_data(recv_data_high_index downto
recv_data_low_index))) when state = rx_cr
else cr_ref_q(i);
cb_ref_d(i) <= to_integer(unsigned(recv_data(recv_data_high_index downto
recv_data_low_index))) when state = rx_cb
else cb_ref_q(i);
end generate;
cr_ref_d(8) <= to_integer(unsigned(recv_data(39 downto 32))) when state = rx_crcb else cr_ref_q(8);
cb_ref_d(8) <= to_integer(unsigned(recv_data(7 downto 0 ))) when state = rx_crcb else cb_ref_q(8);
cr_x_frac_d <= to_integer(unsigned(recv_data(39 downto 32))) when state = rx_header else cr_x_frac_q;
cr_y_frac_d <= to_integer(unsigned(recv_data(31 downto 24))) when state = rx_header else cr_y_frac_q;
cb_x_frac_d <= to_integer(unsigned(recv_data(23 downto 16))) when state = rx_header else cb_x_frac_q;
cb_y_frac_d <= to_integer(unsigned(recv_data(15 downto 8 ))) when state = rx_header else cb_y_frac_q;
ref_d <= recv_data(7 downto 0) when state = rx_header else ref_q;
sel_vc_d <= sel_vc_enc when state = sel_vc else sel_vc_q;
--the algorithm
--2d linear interpolator for 2 2x2 blocks
chroma_motion_x: for x in 1 downto 0 generate
chroma_motion_y: for y in 1 downto 0 generate
constant ref_0_0_index : integer := x + y*3;
constant ref_0_1_index : integer := x + (y+1)*3;
constant ref_1_0_index : integer := (x+1) + y*3;
constant ref_1_1_index : integer := (x+1) + (y+1) * 3;
constant cr_cb_result_index : integer := x + y*2;
begin
cr_result(cr_cb_result_index) <=
((8-cr_x_frac_q)*(8-cr_y_frac_q)*cr_ref_q(ref_0_0_index) +
cr_x_frac_q*(8-cr_y_frac_q)*cr_ref_q(ref_1_0_index) +
(8-cr_x_frac_q)*cr_y_frac_q*cr_ref_q(ref_0_1_index) +
cr_x_frac_q*cr_y_frac_q*cr_ref_q(ref_1_1_index) +
32
)/64;
cb_result(cr_cb_result_index) <=
((8-cb_x_frac_q)*(8-cb_y_frac_q)*cb_ref_q(ref_0_0_index) +
cb_x_frac_q*(8-cb_y_frac_q)*cb_ref_q(ref_1_0_index) +
(8-cb_x_frac_q)*cb_y_frac_q*cb_ref_q(ref_0_1_index) +
cb_x_frac_q*cb_y_frac_q*cb_ref_q(ref_1_1_index) +
32
)/64;
end generate;
end generate;
--output formatting
result_vect <= std_logic_vector(to_unsigned(cr_result(0), 8)) &
std_logic_vector(to_unsigned(cr_result(1), 8)) &
std_logic_vector(to_unsigned(cr_result(2), 8)) &
std_logic_vector(to_unsigned(cr_result(3), 8)) &
std_logic_vector(to_unsigned(cb_result(0), 8)) &
std_logic_vector(to_unsigned(cb_result(1), 8)) &
std_logic_vector(to_unsigned(cb_result(2), 8)) &
std_logic_vector(to_unsigned(cb_result(3), 8));
resp_header <= x"00000000000000" & ref_q;
--packet generation
send_data <= resp_header when state = wait_tx_header or state = tx_header else result_vect;
dest_addr <= std_logic_vector(to_unsigned(7, addr_width));
set_tail_flit <= '1' when state = wait_tx_data or state = tx_data else '0';
send_flit <= '1' when state = tx_header or state = tx_data else '0';
--rx controls
dequeue <= sel_vc_one_hot when state = dequeue_cb or state = dequeue_cr or state = dequeue_crcb or state = dequeue_header else "00";
select_vc_read <= sel_vc_q;
sel_vc_one_hot <= "01" when sel_vc_q = "0" else "10";
---------------------------------------------------------------------------
--- STATE MACHINE ---------------------------------------------------------
---------------------------------------------------------------------------
process(state, data_in_buffer, is_tail_flit, sel_vc_one_hot, ready_to_send)
begin
next_state <= state;
if state = idle and or_reduce(data_in_buffer) = '1' then
next_state <= sel_vc;
end if;
if state = sel_vc then
next_state <= rx_header;
end if;
if state = rx_header then
next_state <= dequeue_header;
end if;
if state = dequeue_header then
next_state <= wait_rx_cr;
end if;
if state = wait_rx_cr and or_reduce(sel_vc_one_hot and data_in_buffer) = '1' then
next_state <= rx_cr;
end if;
if state = rx_cr then
next_state <= dequeue_cr;
end if;
if state = dequeue_cr then
next_state <= wait_rx_cb;
end if;
if state = wait_rx_cb and or_reduce(sel_vc_one_hot and data_in_buffer) = '1' then
next_state <= rx_cb;
end if;
if state = rx_cb then
next_state <= dequeue_cb;
end if;
if state = dequeue_cb then
next_state <= wait_rx_crcb;
end if;
if state = wait_rx_crcb and or_reduce(sel_vc_one_hot and data_in_buffer) = '1' then
next_state <= rx_crcb;
end if;
if state = rx_crcb then
next_state <= dequeue_crcb;
end if;
if state = dequeue_crcb then
next_state <= wait_tx_header;
end if;
if state = wait_tx_header and ready_to_send = '1' then
next_state <= tx_header;
end if;
if state = tx_header then
next_state <= wait_tx_data;
end if;
if state = wait_tx_data and ready_to_send = '1' then
next_state <= tx_data;
end if;
if state = tx_data then
next_state <= idle;
end if;
end process;
end architecture;
| mit | fa18f5ccab7d917cfc240eb3034da7ed | 0.47197 | 3.622679 | false | false | false | false |
boztalay/OldProjects | FPGA/LCD_Control/TestCPU1_SynthBench_TB.vhd | 1 | 2,555 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:02:32 10/20/2009
-- Design Name:
-- Module Name: E:/FPGA/Projects/Current Projects/Systems/TestCPU1/TestCPU1_SynthBench_TB.vhd
-- Project Name: TestCPU1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: TestCPU1_SynthBench
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY TestCPU1_SynthBench_TB IS
END TestCPU1_SynthBench_TB;
ARCHITECTURE behavior OF TestCPU1_SynthBench_TB IS
-- Component Declaration for the Unit Under Test (UUT)
component TestCPU1_SynthBench is
Port ( board_clk : in STD_LOGIC;
anodes : out STD_LOGIC_VECTOR(3 downto 0);
out_pins : out STD_LOGIC_VECTOR(31 downto 0);
LCD_DB : out STD_LOGIC_VECTOR(7 downto 0);
r2 : out STD_LOGIC_VECTOR(15 downto 0);
r5 : out STD_LOGIC_VECTOR(15 downto 0);
CPU_clk : out STD_LOGIC);
end component;
--Inputs
signal board_clk : std_logic := '0';
--Outputs
signal out_pins : std_logic_vector(31 downto 0);
signal LCD_DB : STD_LOGIC_VECTOR(7 downto 0);
signal r2 : STD_LOGIC_VECTOR(15 downto 0);
signal r5 : STD_LOGIC_VECTOR(15 downto 0);
signal CPU_clk : STD_LOGIC;
-- Clock period definitions
constant board_clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: TestCPU1_SynthBench PORT MAP (
board_clk => board_clk,
out_pins => out_pins,
LCD_DB => LCD_DB,
r2 => r2,
r5 => r5,
CPU_clk => CPU_clk
);
-- Clock process definitions
board_clk_process :process
begin
board_clk <= '0';
wait for board_clk_period/2;
board_clk <= '1';
wait for board_clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait;
end process;
END;
| mit | 91336b2988f836b4c797f231d4fbaf62 | 0.60274 | 3.629261 | false | true | false | false |
DaveyPocket/btrace448 | core/inputInterface.vhd | 1 | 986 | -- Btrace 448
-- Input Interface
--
-- Bradley Boccuzzi
-- 2016
library ieee;
use ieee.std_logic_1164.all;
entity inputInterface is
port(clk, rst: in std_logic;
BTNS, BTNU, BTND, BTNL, BTNR: in std_logic; -- Raw inputs from dev. board
BTNSd, BTNUd, BTNDd, BTNLd, BTNRd: out std_logic); -- Debounced/buffered buttons
end inputInterface;
architecture arch of inputInterface is
signal d: std_logic_vector(4 downto 0); -- Debouncer outputs
signal bi, bo: std_logic_vector(0 to 4); -- Vectors mapping to inputs and outputs, used in generation of rising edge detectors and debouncers.
begin
bi <= BTNS & BTNU & BTND & BTNL & BTNR;
BTNSd <= bo(0);
BTNUd <= bo(1);
BTNDd <= bo(2);
BTNLd <= bo(3);
BTNRd <= bo(4);
genInputInterface:
for i in 0 to 4 generate
debx: entity work.debouncer generic map(30, 11) port map (bi(i), clk, rst, d(i));
redx: entity work.red port map(d(i), rst, clk, bo(i));
end generate genInputInterface;
end arch;
| gpl-3.0 | 65f82f5d6306f5fd85c6bf106de37605 | 0.670385 | 3.015291 | false | false | false | false |
rpereira-dev/ENSIIE | UE/S3/microarchi/tp1/tp2.vhd | 1 | 753 | -- includes
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
-- prototypage
ENTITY tp2 IS
PORT (
e : IN STD_LOGIC_VECTOR (3 downto 0) ; -- 2^4 = 16, codes les entiers de 0 à 9
s : OUT STD_LOGIC_VECTOR (6 downto 0) -- 1 bit par segment (abcdefg)_2, bit de poids faible 'à droite'
);
END tp2;
-- architecture
ARCHITECTURE arch OF tp2 IS
BEGIN
WITH e SELECT s <=
"1111110" WHEN "0000", -- 0 => abcdef-
"0110000" WHEN "0001", -- 1 => -bc----
"1101101" WHEN "0010",
"1111001" WHEN "0011",
"0110011" WHEN "0100",
"1011011" WHEN "0101",
"1011111" WHEN "0110",
"1110010" WHEN "0111",
"1111111" WHEN "1000",
"1111011" WHEN "1001",
"1001111" WHEN "----" -- >= 10 => affiches 'E'
;
END arch ; | gpl-3.0 | 39c7a040c85164776bbebfb9e6ba7ced | 0.604527 | 2.812734 | false | false | false | false |
freecores/line_codes | rtl/vhdl/hdb1_dec.vhd | 1 | 565 |
-- implementation of the HDB1 decoder.
entity hdb1_dec is
port (
clr_bar,
clk, e0, e1 : in bit; -- inputs.
s : out bit -- output.
);
end hdb1_dec;
architecture behaviour of hdb1_dec is
signal q0, q1: bit; -- two flipflops.
begin
process (clk, clr_bar) begin
if clr_bar = '0' then
q0 <= '0';
q1 <= '0';
s <= '0';
elsif clk'event and clk = '1' then
s <= ( q0 and (not e0) ) or ( q1 and (not e1) );
q0 <= (not q0) and e0;
q1 <= (not q1) and e1;
end if;
end process;
end behaviour;
| gpl-2.0 | 5ab2b31b94237015b80909b29c74a1dc | 0.527434 | 2.556561 | false | false | false | false |
bargei/NoC264 | NoC264_3x3/vga_controller.vhd | 2 | 4,773 | --------------------------------------------------------------------------------
--
-- FileName: vga_controller.vhd
-- Dependencies: none
-- Design Software: Quartus II 64-bit Version 12.1 Build 177 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 05/10/2013 Scott Larson
-- Initial Public Release
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY vga_controller IS
GENERIC(
h_pulse : INTEGER := 208; --horiztonal sync pulse width in pixels
h_bp : INTEGER := 336; --horiztonal back porch width in pixels
h_pixels : INTEGER := 1920; --horiztonal display width in pixels
h_fp : INTEGER := 128; --horiztonal front porch width in pixels
h_pol : STD_LOGIC := '0'; --horizontal sync pulse polarity (1 = positive, 0 = negative)
v_pulse : INTEGER := 3; --vertical sync pulse width in rows
v_bp : INTEGER := 38; --vertical back porch width in rows
v_pixels : INTEGER := 1200; --vertical display width in rows
v_fp : INTEGER := 1; --vertical front porch width in rows
v_pol : STD_LOGIC := '1'); --vertical sync pulse polarity (1 = positive, 0 = negative)
PORT(
pixel_clk : IN STD_LOGIC; --pixel clock at frequency of VGA mode being used
reset_n : IN STD_LOGIC; --active low asycnchronous reset
h_sync : OUT STD_LOGIC; --horiztonal sync pulse
v_sync : OUT STD_LOGIC; --vertical sync pulse
disp_ena : OUT STD_LOGIC; --display enable ('1' = display time, '0' = blanking time)
column : OUT INTEGER; --horizontal pixel coordinate
row : OUT INTEGER; --vertical pixel coordinate
n_blank : OUT STD_LOGIC; --direct blacking output to DAC
n_sync : OUT STD_LOGIC); --sync-on-green output to DAC
END vga_controller;
ARCHITECTURE behavior OF vga_controller IS
CONSTANT h_period : INTEGER := h_pulse + h_bp + h_pixels + h_fp; --total number of pixel clocks in a row
CONSTANT v_period : INTEGER := v_pulse + v_bp + v_pixels + v_fp; --total number of rows in column
BEGIN
n_blank <= '1'; --no direct blanking
n_sync <= '0'; --no sync on green
PROCESS(pixel_clk, reset_n)
VARIABLE h_count : INTEGER RANGE 0 TO h_period - 1 := 0; --horizontal counter (counts the columns)
VARIABLE v_count : INTEGER RANGE 0 TO v_period - 1 := 0; --vertical counter (counts the rows)
BEGIN
IF(reset_n = '0') THEN --reset asserted
h_count := 0; --reset horizontal counter
v_count := 0; --reset vertical counter
h_sync <= NOT h_pol; --deassert horizontal sync
v_sync <= NOT v_pol; --deassert vertical sync
disp_ena <= '0'; --disable display
column <= 0; --reset column pixel coordinate
row <= 0; --reset row pixel coordinate
ELSIF(pixel_clk'EVENT AND pixel_clk = '1') THEN
--counters
IF(h_count < h_period - 1) THEN --horizontal counter (pixels)
h_count := h_count + 1;
ELSE
h_count := 0;
IF(v_count < v_period - 1) THEN --veritcal counter (rows)
v_count := v_count + 1;
ELSE
v_count := 0;
END IF;
END IF;
--horizontal sync signal
IF(h_count < h_pixels + h_fp OR h_count > h_pixels + h_fp + h_pulse) THEN
h_sync <= NOT h_pol; --deassert horiztonal sync pulse
ELSE
h_sync <= h_pol; --assert horiztonal sync pulse
END IF;
--vertical sync signal
IF(v_count < v_pixels + v_fp OR v_count > v_pixels + v_fp + v_pulse) THEN
v_sync <= NOT v_pol; --deassert vertical sync pulse
ELSE
v_sync <= v_pol; --assert vertical sync pulse
END IF;
--set pixel coordinates
IF(h_count < h_pixels) THEN --horiztonal display time
column <= h_count; --set horiztonal pixel coordinate
END IF;
IF(v_count < v_pixels) THEN --vertical display time
row <= v_count; --set vertical pixel coordinate
END IF;
--set display enable output
IF(h_count < h_pixels AND v_count < v_pixels) THEN --display time
disp_ena <= '1'; --enable display
ELSE --blanking time
disp_ena <= '0'; --disable display
END IF;
END IF;
END PROCESS;
END behavior; | mit | 898d960a665988f10d3db07317198b42 | 0.629583 | 3.249149 | false | false | false | false |
bargei/NoC264 | NoC264_2x2/chroma_motion.vhd | 1 | 12,604 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.math_real.all;
entity chroma_motion is
generic(
data_width : integer := 64;
addr_width : integer := 4;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
-- recv interface to network
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
-- send interface to network
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic
--debug
--state_out : out std_logic_vector(7 downto 0)
);
end entity chroma_motion;
architecture fsmd of chroma_motion is
--- Components ------------------------------------------------------------
component priority_encoder is
generic(
encoded_word_size : integer := 3
);
Port(
input : in std_logic_vector(2**encoded_word_size-1 downto 0);
output : out std_logic_vector(encoded_word_size-1 downto 0)
);
end component priority_encoder;
--- Types -----------------------------------------------------------------
type chroma_motion_states is (idle,
sel_vc,
rx_header,
dequeue_header,
wait_rx_cr,
rx_cr,
dequeue_cr,
wait_rx_cb,
rx_cb,
dequeue_cb,
wait_rx_crcb,
rx_crcb,
dequeue_crcb,
wait_tx_header,
tx_header,
wait_tx_data,
tx_data);
type reference_array is array (8 downto 0) of integer;
type result_array is array (3 downto 0) of integer;
--- signals and registers -------------------------------------------------
signal cr_ref_d : reference_array;
signal cb_ref_d : reference_array;
signal cr_ref_q : reference_array;
signal cb_ref_q : reference_array;
signal cr_result : result_array;
signal cb_result : result_array;
signal cr_x_frac_d : integer;
signal cr_y_frac_d : integer;
signal cr_x_frac_q : integer;
signal cr_y_frac_q : integer;
signal cb_x_frac_d : integer;
signal cb_y_frac_d : integer;
signal cb_x_frac_q : integer;
signal cb_y_frac_q : integer;
signal ref_d : std_logic_vector(7 downto 0);
signal ref_q : std_logic_vector(7 downto 0);
signal result_vect : std_logic_vector(63 downto 0);
signal resp_header : std_logic_vector(63 downto 0);
signal state : chroma_motion_states;
signal next_state : chroma_motion_states;
signal sel_vc_d : std_logic_vector(vc_sel_width-1 downto 0);
signal sel_vc_q : std_logic_vector(vc_sel_width-1 downto 0);
signal sel_vc_enc : std_logic_vector(vc_sel_width-1 downto 0);
signal sel_vc_one_hot : std_logic_vector(num_vc-1 downto 0);
begin
---------------------------------------------------------------------------
--- DATAPATH --------------------------------------------------------------
---------------------------------------------------------------------------
--components
u2: component priority_encoder
generic map(
encoded_word_size => vc_sel_width
)
Port map(
input => data_in_buffer,
output => sel_vc_enc
);
--registers
regs: process(clk, rst) begin
if rst = '1' then
cr_ref_q <= (others => 0);
cb_ref_q <= (others => 0);
cr_x_frac_q <= 0;
cr_y_frac_q <= 0;
cb_x_frac_q <= 0;
cb_y_frac_q <= 0;
ref_q <= (others => '0');
sel_vc_q <= (others => '0');
state <= idle;
elsif rising_edge(clk) then
cr_ref_q <= cr_ref_d;
cb_ref_q <= cb_ref_d;
cr_x_frac_q <= cr_x_frac_d;
cr_y_frac_q <= cr_y_frac_d;
cb_x_frac_q <= cb_x_frac_d;
cb_y_frac_q <= cb_y_frac_d;
ref_q <= ref_d;
sel_vc_q <= sel_vc_d;
state <= next_state;
end if;
end process;
--register update
reg_update: for i in 7 downto 0 generate
constant recv_data_low_index : integer := i * 8;
constant recv_data_high_index : integer := recv_data_low_index + 7;
begin
cr_ref_d(i) <= to_integer(unsigned(recv_data(recv_data_high_index downto
recv_data_low_index))) when state = rx_cr
else cr_ref_q(i);
cb_ref_d(i) <= to_integer(unsigned(recv_data(recv_data_high_index downto
recv_data_low_index))) when state = rx_cb
else cb_ref_q(i);
end generate;
cr_ref_d(8) <= to_integer(unsigned(recv_data(39 downto 32))) when state = rx_crcb else cr_ref_q(8);
cb_ref_d(8) <= to_integer(unsigned(recv_data(7 downto 0 ))) when state = rx_crcb else cb_ref_q(8);
cr_x_frac_d <= to_integer(unsigned(recv_data(39 downto 32))) when state = rx_header else cr_x_frac_q;
cr_y_frac_d <= to_integer(unsigned(recv_data(31 downto 24))) when state = rx_header else cr_y_frac_q;
cb_x_frac_d <= to_integer(unsigned(recv_data(23 downto 16))) when state = rx_header else cb_x_frac_q;
cb_y_frac_d <= to_integer(unsigned(recv_data(15 downto 8 ))) when state = rx_header else cb_y_frac_q;
ref_d <= recv_data(7 downto 0) when state = rx_header else ref_q;
sel_vc_d <= sel_vc_enc when state = sel_vc else sel_vc_q;
--the algorithm
chroma_motion_x: for x in 1 downto 0 generate
chroma_motion_y: for y in 1 downto 0 generate
constant ref_0_0_index : integer := x + y*3;
constant ref_0_1_index : integer := x + (y+1)*3;
constant ref_1_0_index : integer := (x+1) + y*3;
constant ref_1_1_index : integer := (x+1) + (y+1) * 3;
constant cr_cb_result_index : integer := x + y*2;
begin
cr_result(cr_cb_result_index) <=
((8-cr_x_frac_q)*(8-cr_y_frac_q)*cr_ref_q(ref_0_0_index) +
cr_x_frac_q*(8-cr_y_frac_q)*cr_ref_q(ref_1_0_index) +
(8-cr_x_frac_q)*cr_y_frac_q*cr_ref_q(ref_0_1_index) +
cr_x_frac_q*cr_y_frac_q*cr_ref_q(ref_1_1_index) +
32
)/64;
cb_result(cr_cb_result_index) <=
((8-cb_x_frac_q)*(8-cb_y_frac_q)*cb_ref_q(ref_0_0_index) +
cb_x_frac_q*(8-cb_y_frac_q)*cb_ref_q(ref_1_0_index) +
(8-cb_x_frac_q)*cb_y_frac_q*cb_ref_q(ref_0_1_index) +
cb_x_frac_q*cb_y_frac_q*cb_ref_q(ref_1_1_index) +
32
)/64;
end generate;
end generate;
--output formatting
result_vect <= std_logic_vector(to_unsigned(cr_result(0), 8)) &
std_logic_vector(to_unsigned(cr_result(1), 8)) &
std_logic_vector(to_unsigned(cr_result(2), 8)) &
std_logic_vector(to_unsigned(cr_result(3), 8)) &
std_logic_vector(to_unsigned(cb_result(0), 8)) &
std_logic_vector(to_unsigned(cb_result(1), 8)) &
std_logic_vector(to_unsigned(cb_result(2), 8)) &
std_logic_vector(to_unsigned(cb_result(3), 8));
resp_header <= x"00000000000000" & ref_q;
--packet generation
send_data <= resp_header when state = wait_tx_header or state = tx_header else result_vect;
dest_addr <= std_logic_vector(to_unsigned(7, addr_width));
set_tail_flit <= '1' when state = wait_tx_data or state = tx_data else '0';
send_flit <= '1' when state = tx_header or state = tx_data else '0';
--rx controls
dequeue <= sel_vc_one_hot when state = dequeue_cb or state = dequeue_cr or state = dequeue_crcb or state = dequeue_header else "00";
select_vc_read <= sel_vc_q;
sel_vc_one_hot <= "01" when sel_vc_q = "0" else "10";
---------------------------------------------------------------------------
--- STATE MACHINE ---------------------------------------------------------
---------------------------------------------------------------------------
process(state, data_in_buffer, is_tail_flit, sel_vc_one_hot, ready_to_send)
begin
next_state <= state;
if state = idle and or_reduce(data_in_buffer) = '1' then
next_state <= sel_vc;
end if;
if state = sel_vc then
next_state <= rx_header;
end if;
if state = rx_header then
next_state <= dequeue_header;
end if;
if state = dequeue_header then
next_state <= wait_rx_cr;
end if;
if state = wait_rx_cr and or_reduce(sel_vc_one_hot and data_in_buffer) = '1' then
next_state <= rx_cr;
end if;
if state = rx_cr then
next_state <= dequeue_cr;
end if;
if state = dequeue_cr then
next_state <= wait_rx_cb;
end if;
if state = wait_rx_cb and or_reduce(sel_vc_one_hot and data_in_buffer) = '1' then
next_state <= rx_cb;
end if;
if state = rx_cb then
next_state <= dequeue_cb;
end if;
if state = dequeue_cb then
next_state <= wait_rx_crcb;
end if;
if state = wait_rx_crcb and or_reduce(sel_vc_one_hot and data_in_buffer) = '1' then
next_state <= rx_crcb;
end if;
if state = rx_crcb then
next_state <= dequeue_crcb;
end if;
if state = dequeue_crcb then
next_state <= wait_tx_header;
end if;
if state = wait_tx_header and ready_to_send = '1' then
next_state <= tx_header;
end if;
if state = tx_header then
next_state <= wait_tx_data;
end if;
if state = wait_tx_data and ready_to_send = '1' then
next_state <= tx_data;
end if;
if state = tx_data then
next_state <= idle;
end if;
end process;
--state_out <= x"00" when state = idle else
-- x"01" when state = sel_vc else
-- x"02" when state = rx_header else
-- x"03" when state = dequeue_header else
-- x"04" when state = wait_rx_cr else
-- x"05" when state = rx_cr else
-- x"06" when state = dequeue_cr else
-- x"07" when state = wait_rx_cb else
-- x"08" when state = rx_cb else
-- x"09" when state = dequeue_cb else
-- x"0A" when state = wait_rx_crcb else
-- x"0B" when state = rx_crcb else
-- x"0C" when state = dequeue_crcb else
-- x"0D" when state = wait_tx_header else
-- x"0E" when state = tx_header else
-- x"0F" when state = wait_tx_data else
-- x"10" when state = tx_data else
-- x"FF";
end architecture;
| mit | c83e73bc06389d66b9eb3869ca0fd743 | 0.461996 | 3.665019 | false | false | false | false |
DaveyPocket/btrace448 | top.vhd | 1 | 2,457 | library ieee;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee.std_logic_1164.all;
use work.btrace_pack.all;
entity top is
port(clk, rst: in std_logic;
btns, btnr, btnu: in std_logic;
rgb: out std_logic_vector(11 downto 0);
hsync, vsync, led: out std_logic);
end top;
architecture arch of top is
constant my_z: sfixed(15 downto -16) := to_sfixed(-1000, 15, -16);
constant obj_z: sfixed(15 downto -16) := to_sfixed(100, 15, -16);
constant obj_size: sfixed(15 downto -16) := to_sfixed(80, 15, -16);
constant my_point: point := ((others => '0'), (others => '0'), my_z);
constant my_object_point: point := (obj_z, obj_z, obj_z);
constant my_object: object := (my_object_point, obj_size, x"FFF");
constant no_object: point := ((others => '0'), (others => '0'), my_z);
-- Control signals
signal init_x, init_y, inc_x, inc_y: std_logic;
signal set_vector, set_org: std_logic;
signal next_obj, start_search: std_logic;
signal clr_z_reg, clr_hit: std_logic;
signal store: std_logic;
signal paint: std_logic;
signal done: std_logic;
-- External inputs
signal e_set_camera: std_logic;
signal e_camera_point: point;
signal e_set_obj: std_logic;
signal e_obj_addr: std_logic_vector(3 downto 0);
signal e_obj_data: object;
signal e_set_max: std_logic;
signal e_max_objects: std_logic_vector(3 downto 0);
-- Status signals
signal last_x, last_y, last_obj, obj_valid, start: std_logic;
begin
dpath: entity work.datapath port map(clk, rst,
-- Control inputs
init_x, init_y, inc_x, inc_y,
set_vector, set_org,
next_obj, start_search,
clr_z_reg, clr_hit,
store,
paint,
-- External inputs
e_set_camera,
e_camera_point,
e_set_obj,
e_obj_addr, e_obj_data,
e_set_max, e_max_objects,
-- Status outputs
last_x, last_y, last_obj, obj_valid,
-- External outputs
hsync, vsync, rgb,
-- Debug
open, open, open);
controller_thing: entity work.controller port map(clk, rst,
-- Control
init_x, init_y, inc_x, inc_y,
set_vector, set_org,
next_obj, start_search,
clr_z_reg, clr_hit,
store,
paint,
done,
-- Status
last_x, last_y, last_obj, obj_valid, start);
e_max_objects <= x"0";
e_set_camera <= btns;
e_set_obj <= btnr;
e_set_max <= btnr;
e_obj_data <= my_object;
e_obj_addr <= (others => '0');
e_camera_point <= my_point;
led <= done;
start <= btnu;
end arch;
| gpl-3.0 | f48fb98d09375dcda03f67f19416e181 | 0.62963 | 2.688184 | false | false | false | false |
bargei/NoC264 | NoC264_2x2/noc_control_plus.vhd | 1 | 20,326 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
entity noc_control_plus is
generic (
data_width : integer := 64;
addr_width : integer := 4;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
-- recv interface to network
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
-- send interface to network
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic;
--send interface to CPU
set_tail_cpu : in std_logic;
addr_cpu : in std_logic_vector(addr_width-1 downto 0);
tx_0 : in std_logic_vector(31 downto 0);
tx_1 : in std_logic_vector(31 downto 0);
tx_2 : in std_logic_vector(31 downto 0);
tx_3 : in std_logic_vector(31 downto 0);
tx_4 : in std_logic_vector(31 downto 0);
tx_5 : in std_logic_vector(31 downto 0);
tx_6 : in std_logic_vector(31 downto 0);
tx_7 : in std_logic_vector(31 downto 0);
format_select : in std_logic_vector(7 downto 0);
send_cmd_cpu : in std_logic;
send_ack : out std_logic;
--receive interface to cpu
rx_0 : out std_logic_vector(31 downto 0);
rx_1 : out std_logic_vector(31 downto 0);
rx_2 : out std_logic_vector(31 downto 0);
rx_3 : out std_logic_vector(31 downto 0);
rx_4 : out std_logic_vector(31 downto 0);
rx_5 : out std_logic_vector(31 downto 0);
rx_6 : out std_logic_vector(31 downto 0);
rx_7 : out std_logic_vector(31 downto 0);
parse_select : in std_logic_vector(7 downto 0);
cpu_rx_ctrl : in std_logic;
rx_state_out : out std_logic_vector(7 downto 0)
);
end entity noc_control_plus;
architecture fsmd of noc_control_plus is
component priority_encoder is
generic(
encoded_word_size : integer := 3
);
Port(
input : in std_logic_vector(2**encoded_word_size-1 downto 0);
output : out std_logic_vector(encoded_word_size-1 downto 0)
);
end component priority_encoder;
----------------------------------------------------------------------------
--- SIGNALS and CONSTANTS For Formating Flits ------------------------------
----------------------------------------------------------------------------
--mode 0: fit as many of the lowest bits from each data word into the flit
--Example: for 64 bit flits put the lowest 8 bits from each data word
--This one covers inter and deblock
signal mode_0_flit : std_logic_vector(data_width-1 downto 0);
--mode 1: same as mode 0 but with data0-data3 only
signal mode_1_flit : std_logic_vector(data_width-1 downto 0);
--mode 2: same as modes 1,2 but with data0 and data1 only
signal mode_2_flit : std_logic_vector(data_width-1 downto 0);
--mode 3: data 0 only, zero fill
signal mode_3_flit : std_logic_vector(data_width-1 downto 0);
--mode 4: data 0 only, sign fill
signal mode_4_flit : std_logic_vector(data_width-1 downto 0);
--mode 5: Intra Set Command
signal mode_5_flit : std_logic_vector(data_width-1 downto 0);
--mode 6: Intra Start Prediction Command
signal mode_6_flit : std_logic_vector(data_width-1 downto 0);
--mode 7: Write to Display
signal mode_7_flit : std_logic_vector(data_width-1 downto 0);
--mode 8: IQIT Header
signal mode_8_flit : std_logic_vector(data_width-1 downto 0);
--mode 9: IQIT row
signal mode_9_flit : std_logic_vector(data_width-1 downto 0);
signal the_flit : std_logic_vector(data_width-1 downto 0);
--modes 0... 1
constant eight_flit : integer := data_width/8;
constant quarter_flit : integer := data_width/4;
--mode 3
constant zero_fill : integer := data_width-32;
----------------------------------------------------------------------------
--- TYPES and SIGNALS for Sending Side State Machine -----------------------
----------------------------------------------------------------------------
type send_state_type is (idle, send_requested, tx, ack);
signal send_state, next_send_state : send_state_type;
----------------------------------------------------------------------------
--- SIGNALS and CONSTANTS for Recieve Side ---------------------------------
----------------------------------------------------------------------------
type rx_states is (rx_idle, rx_addr_rst, rx_start_read, rx_sel_vc, rx_rxd, rx_wait_cpu, rx_dequeue, rx_wait_flits);
signal rx_state, next_rx_state : rx_states;
signal selected_vc_one_hot : std_logic_vector(1 downto 0);
signal state : std_logic_vector(3 downto 0);
signal cpu_read_ctrl : std_logic;
signal selected_vc_q, selected_vc_d, selected_vc_encoder : std_logic_vector(vc_sel_width-1 downto 0);
----------------------------------------------------------------------------
--- REGISTER for HW Timer --------------------------------------------------
----------------------------------------------------------------------------
signal timer_d, timer_q : unsigned(31 downto 0);
begin
--==========================================================================
--==========================================================================
--==SENDING SIDE============================================================
--==========================================================================
--==========================================================================
----------------------------------------------------------------------------
--- FLIT GENERATION --------------------------------------------------------
----------------------------------------------------------------------------
--format flit
mode_0_flit <= tx_0(eight_flit-1 downto 0) &
tx_1(eight_flit-1 downto 0) &
tx_2(eight_flit-1 downto 0) &
tx_3(eight_flit-1 downto 0) &
tx_4(eight_flit-1 downto 0) &
tx_5(eight_flit-1 downto 0) &
tx_6(eight_flit-1 downto 0) &
tx_7(eight_flit-1 downto 0);
mode_1_flit <= tx_0(quarter_flit-1 downto 0) &
tx_1(quarter_flit-1 downto 0) &
tx_2(quarter_flit-1 downto 0) &
tx_3(quarter_flit-1 downto 0);
mode_2_flit <= tx_0 & tx_1;
mode_3_flit <= std_logic_vector(to_unsigned(0,zero_fill)) & tx_0;
mode_4_flit <= std_logic_vector(resize(signed( tx_0 ), data_width));
mode_5_flit <= mode_0_flit;
mode_6_flit <= mode_0_flit;
mode_7_flit <= tx_0(eight_flit-1 downto 0) &
tx_1(eight_flit-1 downto 0) &
tx_2(eight_flit-1 downto 0) &
tx_3(eight_flit-1 downto 0) &
tx_4(eight_flit-1 downto 0) &
tx_5(eight_flit-1 downto 0) &
tx_6(quarter_flit-1 downto 0);
mode_8_flit <= tx_0(15 downto 0) & --dc upper byte
tx_1(7 downto 0) & --qp
tx_2(7 downto 0) & --wo dc
tx_3(1 downto 0) & --LCbCr
tx_4(10 downto 0) & --y coord
tx_5(10 downto 0) & --x ccord
tx_6(7 downto 0); --id
mode_9_flit <= mode_0_flit;
--select flit
the_flit <= mode_0_flit when format_select = std_logic_vector(to_unsigned(0, 8)) else
mode_1_flit when format_select = std_logic_vector(to_unsigned(1, 8)) else
mode_2_flit when format_select = std_logic_vector(to_unsigned(2, 8)) else
mode_3_flit when format_select = std_logic_vector(to_unsigned(3, 8)) else
mode_4_flit when format_select = std_logic_vector(to_unsigned(4, 8)) else
mode_5_flit when format_select = std_logic_vector(to_unsigned(5, 8)) else
mode_6_flit when format_select = std_logic_vector(to_unsigned(6, 8)) else
mode_7_flit when format_select = std_logic_vector(to_unsigned(7, 8)) else
mode_8_flit when format_select = std_logic_vector(to_unsigned(8, 8)) else
mode_9_flit when format_select = std_logic_vector(to_unsigned(9, 8)) else
std_logic_vector(to_unsigned(0, data_width));
----------------------------------------------------------------------------
--- SEND FSM ---------------------------------------------------------------
----------------------------------------------------------------------------
process(clk, rst)
begin
if rst = '1' then
send_state <= idle;
elsif rising_edge(clk) then
send_state <= next_send_state;
end if;
end process;
process(send_state, send_cmd_cpu, ready_to_send)
begin
--default
next_send_state <= send_state;
if send_state = idle and send_cmd_cpu = '1' then
next_send_state <= send_requested;
end if;
if send_state = send_requested and ready_to_send = '1' then
next_send_state <= tx;
end if;
if send_state = tx then
next_send_state <= ack;
end if;
if send_state = ack and send_cmd_cpu = '0' then
next_send_state <= idle;
end if;
end process;
----------------------------------------------------------------------------
--- SEND SIDE OUTPUTS ------------------------------------------------------
----------------------------------------------------------------------------
send_data <= the_flit;
dest_addr <= addr_cpu;
set_tail_flit <= set_tail_cpu when send_state = send_requested or send_state = tx else '0';
send_flit <= '1' when send_state = tx else '0';
send_ack <= '1' when send_state = ack else '0';
--==========================================================================
--==========================================================================
--==RECEIVING SIDE==========================================================
--==========================================================================
--==========================================================================
----------------------------------------------------------------------------
-- DATAPATH ----------------------------------------------------------------
----------------------------------------------------------------------------
process(clk, rst) begin
if rst = '1' then
selected_vc_q <=(others => '0');
elsif rising_edge(clk) then
selected_vc_q <= selected_vc_d;
end if;
end process;
u0: priority_encoder generic map(vc_sel_width)
port map(data_in_buffer, selected_vc_encoder);
selected_vc_d <= selected_vc_encoder when rx_state = rx_sel_vc else selected_vc_q;
cpu_read_ctrl <= cpu_rx_ctrl;
--Parser
rx_0 <= std_logic_vector(resize(unsigned(recv_data(63 downto 32)), 32)) when parse_select = std_logic_vector(to_unsigned(0, 8)) else --mode 0: 32 bit unsigned
std_logic_vector(resize(unsigned(recv_data(63 downto 48)), 32)) when parse_select = std_logic_vector(to_unsigned(1, 8)) else --mode 1: 16 bit unsigned
std_logic_vector(resize(unsigned(recv_data(63 downto 56)), 32)) when parse_select = std_logic_vector(to_unsigned(2, 8)) else --mode 2: 8 bit unsigned
std_logic_vector(resize(signed( recv_data(63 downto 32)), 32)) when parse_select = std_logic_vector(to_unsigned(3, 8)) else --mode 3: 32 bit signed
std_logic_vector(resize(signed( recv_data(63 downto 48)), 32)) when parse_select = std_logic_vector(to_unsigned(4, 8)) else --mode 4: 16 bit signed
std_logic_vector(resize(signed( recv_data(63 downto 56)), 32)) when parse_select = std_logic_vector(to_unsigned(5, 8)) else --mode 5: 8 bit signed
(others => '0');
rx_1 <= std_logic_vector(resize(unsigned(recv_data(31 downto 0 )), 32)) when parse_select = std_logic_vector(to_unsigned(0, 8)) else --mode 0: 32 bit unsigned
std_logic_vector(resize(unsigned(recv_data(47 downto 32)), 32)) when parse_select = std_logic_vector(to_unsigned(1, 8)) else --mode 1: 16 bit unsigned
std_logic_vector(resize(unsigned(recv_data(55 downto 48)), 32)) when parse_select = std_logic_vector(to_unsigned(2, 8)) else --mode 2: 8 bit unsigned
std_logic_vector(resize(signed( recv_data(31 downto 0 )), 32)) when parse_select = std_logic_vector(to_unsigned(3, 8)) else --mode 3: 32 bit signed
std_logic_vector(resize(signed( recv_data(47 downto 32)), 32)) when parse_select = std_logic_vector(to_unsigned(4, 8)) else --mode 4: 16 bit signed
std_logic_vector(resize(signed( recv_data(55 downto 48)), 32)) when parse_select = std_logic_vector(to_unsigned(5, 8)) else --mode 5: 8 bit signed
(others => '0');
rx_2 <= std_logic_vector(resize(unsigned(recv_data(31 downto 16)), 32)) when parse_select = std_logic_vector(to_unsigned(1, 8)) else --mode 1: 16 bit unsigned
std_logic_vector(resize(unsigned(recv_data(47 downto 40)), 32)) when parse_select = std_logic_vector(to_unsigned(2, 8)) else --mode 2: 8 bit unsigned
std_logic_vector(resize(signed( recv_data(31 downto 16)), 32)) when parse_select = std_logic_vector(to_unsigned(4, 8)) else --mode 4: 16 bit signed
std_logic_vector(resize(signed( recv_data(47 downto 40)), 32)) when parse_select = std_logic_vector(to_unsigned(5, 8)) else --mode 5: 8 bit signed
std_logic_vector(timer_q); --this input reused for timer
rx_3 <= std_logic_vector(resize(unsigned(recv_data(15 downto 0 )), 32)) when parse_select = std_logic_vector(to_unsigned(1, 8)) else --mode 1: 16 bit unsigned
std_logic_vector(resize(unsigned(recv_data(39 downto 32)), 32)) when parse_select = std_logic_vector(to_unsigned(2, 8)) else --mode 2: 8 bit unsigned
std_logic_vector(resize(signed( recv_data(15 downto 0 )), 32)) when parse_select = std_logic_vector(to_unsigned(4, 8)) else --mode 4: 16 bit signed
std_logic_vector(resize(signed( recv_data(39 downto 32)), 32)) when parse_select = std_logic_vector(to_unsigned(5, 8)) else --mode 5: 8 bit signed
(others => '0');
rx_4 <= std_logic_vector(resize(unsigned(recv_data(31 downto 24)), 32)) when parse_select = std_logic_vector(to_unsigned(2, 8)) else --mode 2: 8 bit unsigned
std_logic_vector(resize(signed( recv_data(31 downto 24)), 32)) when parse_select = std_logic_vector(to_unsigned(5, 8)) else --mode 5: 8 bit signed
(others => '0');
rx_5 <= std_logic_vector(resize(unsigned(recv_data(23 downto 16)), 32)) when parse_select = std_logic_vector(to_unsigned(2, 8)) else --mode 2: 8 bit unsigned
std_logic_vector(resize(signed( recv_data(23 downto 16)), 32)) when parse_select = std_logic_vector(to_unsigned(5, 8)) else --mode 5: 8 bit signed
(others => '0');
rx_6 <= std_logic_vector(resize(unsigned(recv_data(15 downto 8 )), 32)) when parse_select = std_logic_vector(to_unsigned(2, 8)) else --mode 2: 8 bit unsigned
std_logic_vector(resize(signed( recv_data(15 downto 8 )), 32)) when parse_select = std_logic_vector(to_unsigned(5, 8)) else --mode 5: 8 bit signed
(others => '0');
rx_7 <= std_logic_vector(resize(unsigned(recv_data(7 downto 0 )), 32)) when parse_select = std_logic_vector(to_unsigned(2, 8)) else --mode 2: 8 bit unsigned
std_logic_vector(resize(signed( recv_data(7 downto 0 )), 32)) when parse_select = std_logic_vector(to_unsigned(5, 8)) else --mode 5: 8 bit signed
(others => '0');
--NoC Controls
dequeue <= "01" when selected_vc_q = "0" and rx_state = rx_dequeue else
"10" when selected_vc_q = "1" and rx_state = rx_dequeue else
"00";
selected_vc_one_hot <= "01" when selected_vc_q = "0" else
"10";
select_vc_read <= selected_vc_q;
rx_state_out <= std_logic_vector(to_unsigned(0, 8)) when rx_state = rx_idle else
std_logic_vector(to_unsigned(1, 8)) when rx_state = rx_sel_vc else
std_logic_vector(to_unsigned(2, 8)) when rx_state = rx_addr_rst else
std_logic_vector(to_unsigned(3, 8)) when rx_state = rx_start_read else
std_logic_vector(to_unsigned(4, 8)) when rx_state = rx_rxd else
std_logic_vector(to_unsigned(5, 8)) when rx_state = rx_wait_cpu else
std_logic_vector(to_unsigned(6, 8)) when rx_state = rx_dequeue else
std_logic_vector(to_unsigned(7, 8)) when rx_state = rx_wait_flits else
std_logic_vector(to_unsigned(15, 8));
----------------------------------------------------------------------------
--- RX FSM -----------------------------------------------------------------
----------------------------------------------------------------------------
process(clk, rst) begin
if rst = '1' then
rx_state <= rx_idle;
elsif rising_edge(clk) then
rx_state <= next_rx_state;
end if;
end process;
process(rx_state, data_in_buffer, selected_vc_q, cpu_read_ctrl) begin
next_rx_state <= rx_state;
if rx_state = rx_idle and or_reduce(data_in_buffer) = '1' then
next_rx_state <= rx_sel_vc;
end if;
if rx_state = rx_sel_vc then
next_rx_state <= rx_addr_rst;
end if;
if rx_state = rx_addr_rst and cpu_read_ctrl = '1' then
next_rx_state <= rx_start_read;
end if;
if rx_state = rx_start_read and cpu_read_ctrl = '0' then
next_rx_state <= rx_rxd;
end if;
if rx_state = rx_rxd and cpu_read_ctrl = '1' then
next_rx_state <= rx_wait_cpu;
end if;
if rx_state = rx_wait_cpu and cpu_read_ctrl = '0' then
next_rx_state <= rx_dequeue;
end if;
if rx_state = rx_dequeue and is_tail_flit = '1' then
next_rx_state <= rx_idle;
end if;
if rx_state = rx_dequeue and is_tail_flit = '0' then
next_rx_state <= rx_wait_flits;
end if;
if rx_state = rx_wait_flits and or_reduce(data_in_buffer and selected_vc_one_hot) = '1' then
next_rx_state <= rx_rxd;
end if;
end process;
--==========================================================================
--==========================================================================
--==TIMER===================================================================
--==========================================================================
--==========================================================================
process(clk, rst) begin
if rst = '1' then
timer_q <= (others => '0');
elsif rising_edge(clk) then
timer_q <= timer_d;
end if;
end process;
timer_d <= timer_q + to_unsigned(1, 32);
end architecture fsmd;
| mit | 08f5858b0b19cf3df09b46a696c78ea3 | 0.488734 | 3.901344 | false | false | false | false |
freecores/line_codes | bench/vhdl/smlt_hdb1_dec.vhd | 1 | 982 | -- smlttion for HDB1 decoder.
entity smlt_hdb1_dec is
end smlt_hdb1_dec;
architecture behaviour of smlt_hdb1_dec is
--data type:
component hdb1_dec
port (
clr_bar,
clk, e0, e1 : in bit;
s : out bit);
end component;
--binding:
for a: hdb1_dec use entity work.hdb1_dec;
--declaring the signals present in this architecture:
signal CLK, S, E0, E1, clrb: bit;
signal input0, input1: bit_vector(0 to 24);
begin --architecture.
a: hdb1_dec port map
( clr_bar => clrb, clk=> CLK, e0 => E0, e1 => E1,
s => S );
input0 <= "0100010110001011001001101";
input1 <= "0001001000100100100110010";
process begin
clrb <= '1';
for i in 0 to 24 loop
E0 <= input0(i);
E1 <= input1(i);
CLK <= '0';
wait for 9 ns;
CLK <= '1';
wait for 1 ns;
end loop;
wait;
end process;
end behaviour;
| gpl-2.0 | 56cfd0f0e88a7a948fe2c23d4842e123 | 0.531568 | 3.157556 | false | false | false | false |
bargei/NoC264 | NoC264_3x3/deblocking_filter_node.vhd | 1 | 13,242 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
entity deblocking_filter_node is
generic (
data_width : integer := 64;
addr_width : integer := 1;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
-- recv interface to network
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
-- send interface to network
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic;
--debugging
has_rxd : out std_logic;
is_idle : out std_logic;
is_filtering : out std_logic;
is_tx_ing : out std_logic;
is_cleanup_ing : out std_logic;
rx_non_zero : out std_logic;
tx_non_zero : out std_logic
);
end entity deblocking_filter_node;
architecture fsmd of deblocking_filter_node is
component h264_deblock_filter_core is
port(
clk : in std_logic;
rst : in std_logic;
is_chroma : in std_logic;
boundary_strength : in signed(8 downto 0);
p0 : in signed(8 downto 0);
p1 : in signed(8 downto 0);
p2 : in signed(8 downto 0);
p3 : in signed(8 downto 0);
q0 : in signed(8 downto 0);
q1 : in signed(8 downto 0);
q2 : in signed(8 downto 0);
q3 : in signed(8 downto 0);
alpha : in signed(8 downto 0);
beta : in signed(8 downto 0);
tc0 : in signed(8 downto 0);
p0_out : out signed(8 downto 0);
p1_out : out signed(8 downto 0);
p2_out : out signed(8 downto 0);
q0_out : out signed(8 downto 0);
q1_out : out signed(8 downto 0);
q2_out : out signed(8 downto 0)
);
end component h264_deblock_filter_core;
component priority_encoder is
generic(
encoded_word_size : integer := 2
);
Port(
input : in std_logic_vector(2**encoded_word_size-1 downto 0);
output : out std_logic_vector(encoded_word_size-1 downto 0)
);
end component priority_encoder;
--signals
signal is_chroma : std_logic;
signal boundary_strength : std_logic_vector(8 downto 0);
signal p0 : std_logic_vector(8 downto 0);
signal p1 : std_logic_vector(8 downto 0);
signal p2 : std_logic_vector(8 downto 0);
signal p3 : std_logic_vector(8 downto 0);
signal q0 : std_logic_vector(8 downto 0);
signal q1 : std_logic_vector(8 downto 0);
signal q2 : std_logic_vector(8 downto 0);
signal q3 : std_logic_vector(8 downto 0);
signal alpha : std_logic_vector(8 downto 0);
signal beta : std_logic_vector(8 downto 0);
signal tc0 : std_logic_vector(8 downto 0);
signal bS : std_logic_vector(8 downto 0);
signal p0_out : signed(8 downto 0);
signal p1_out : signed(8 downto 0);
signal p2_out : signed(8 downto 0);
signal q0_out : signed(8 downto 0);
signal q1_out : signed(8 downto 0);
signal q2_out : signed(8 downto 0);
signal p0_out_vector : std_logic_vector(8 downto 0);
signal p1_out_vector : std_logic_vector(8 downto 0);
signal p2_out_vector : std_logic_vector(8 downto 0);
signal q0_out_vector : std_logic_vector(8 downto 0);
signal q1_out_vector : std_logic_vector(8 downto 0);
signal q2_out_vector : std_logic_vector(8 downto 0);
signal identifier : std_logic_vector(7 downto 0);
signal selected_vc_enc : std_logic_vector(vc_sel_width-1 downto 0);
signal selected_vc_q : std_logic_vector(vc_sel_width-1 downto 0);
signal selected_vc_d : std_logic_vector(vc_sel_width-1 downto 0);
signal selected_vc_one_hot : std_logic_vector(num_vc-1 downto 0);
signal has_rxd_q, has_rxd_d : std_logic;
signal recv_packet_q : std_logic_vector(127 downto 0);
signal recv_packet_d : std_logic_vector(127 downto 0);
signal send_data_0 : std_logic_vector(63 downto 0);
signal send_data_1 : std_logic_vector(63 downto 0);
--constants
constant p_index : integer := 96;
constant q_index : integer := 64;
constant param_index : integer := 32;
constant sys_param_index : integer := 0;
--states
type db_filter_states is (idle, select_vc, rx_0, rx_1, wait_rx_0, tx_0, tx_1, dequeue_0, dequeue_1, wait_tx_0, wait_tx_1);
signal next_state, current_state : db_filter_states;
begin
---------------------------------------------------------------------------
-- DATAPATH
---------------------------------------------------------------------------
process(clk, rst)
begin
if rst = '1' then
recv_packet_q <= (others => '0');
selected_vc_q <= (others => '0');
elsif rising_edge(clk) then
recv_packet_q <= recv_packet_d;
selected_vc_q <= selected_vc_d;
end if;
end process;
recv_packet_d(63 downto 0) <= recv_data when current_state = rx_0 else recv_packet_q(63 downto 0);
recv_packet_d(127 downto 64) <= recv_data when current_state = rx_1 else recv_packet_q(127 downto 64);
selected_vc_d <= selected_vc_enc when current_state = select_vc else selected_vc_q;
selected_vc_one_hot <= "01" when selected_vc_q = "0" else "10";
--parse input
p3( 7 downto 0 ) <= (recv_packet_q( p_index + 31 downto p_index + 24));
p2( 7 downto 0 ) <= (recv_packet_q( p_index + 23 downto p_index + 16));
p1( 7 downto 0 ) <= (recv_packet_q( p_index + 15 downto p_index + 8));
p0( 7 downto 0 ) <= (recv_packet_q( p_index + 7 downto p_index + 0));
q3( 7 downto 0 ) <= (recv_packet_q( q_index + 31 downto q_index + 24));
q2( 7 downto 0 ) <= (recv_packet_q( q_index + 23 downto q_index + 16));
q1( 7 downto 0 ) <= (recv_packet_q( q_index + 15 downto q_index + 8));
q0( 7 downto 0 ) <= (recv_packet_q( q_index + 7 downto q_index + 0));
alpha( 7 downto 0 ) <= (recv_packet_q( param_index + 31 downto param_index + 24));
beta( 7 downto 0 ) <= (recv_packet_q( param_index + 23 downto param_index + 16));
bS( 7 downto 0 ) <= (recv_packet_q( param_index + 15 downto param_index + 8 ));
tc0( 7 downto 0 ) <= (recv_packet_q( param_index + 7 downto param_index + 0 ));
p3( 8 ) <= '0';
p2( 8 ) <= '0';
p1( 8 ) <= '0';
p0( 8 ) <= '0';
q3( 8 ) <= '0';
q2( 8 ) <= '0';
q1( 8 ) <= '0';
q0( 8 ) <= '0';
alpha( 8 ) <= '0';
beta( 8 ) <= '0';
bS( 8 ) <= '0';
tc0( 8 ) <= '0';
is_chroma <= recv_packet_q( sys_param_index + 16 );
identifier <= recv_packet_q( sys_param_index + 15 downto sys_param_index + 8 );
--form response
p0_out_vector <= std_logic_vector(p0_out);
p1_out_vector <= std_logic_vector(p1_out);
p2_out_vector <= std_logic_vector(p2_out);
q0_out_vector <= std_logic_vector(q0_out);
q1_out_vector <= std_logic_vector(q1_out);
q2_out_vector <= std_logic_vector(q2_out);
send_data_1 <= p3(7 downto 0) &
p2_out_vector(7 downto 0) &
p1_out_vector(7 downto 0) &
p0_out_vector(7 downto 0) &
q3(7 downto 0) &
q2_out_vector(7 downto 0) &
q1_out_vector(7 downto 0) &
q0_out_vector(7 downto 0);
send_data_0 <= X"00000000" &
x"000000" &
identifier;
send_data <= send_data_0 when current_state = wait_tx_0 or current_state = dequeue_1 or current_state = tx_0 else
send_data_1;
--network controls
dest_addr <= std_logic_vector(to_unsigned(7, addr_width));
select_vc_read <= selected_vc_q;
set_tail_flit <= '1' when current_state = wait_tx_1 or current_state = tx_1 else '0';
send_flit <= '1' when current_state = tx_0 or current_state = tx_1 else '0';
dequeue <= selected_vc_one_hot when current_state = dequeue_0 or current_state = dequeue_1 else "00";
-- filter core
u0: component h264_deblock_filter_core port map(
clk => '0',
rst => '0',
is_chroma => is_chroma,
boundary_strength => signed( bs ),
p0 => signed( p0 ),
p1 => signed( p1 ),
p2 => signed( p2 ),
p3 => signed( p3 ),
q0 => signed( q0 ),
q1 => signed( q1 ),
q2 => signed( q2 ),
q3 => signed( q3 ),
alpha => signed( alpha ),
beta => signed( beta ),
tc0 => signed( tc0 ),
p0_out => p0_out,
p1_out => p1_out,
p2_out => p2_out,
q0_out => q0_out,
q1_out => q1_out,
q2_out => q2_out
);
-- select which bufer to read from
u1: priority_encoder generic map(vc_sel_width)
port map(data_in_buffer, selected_vc_enc);
---------------------------------------------------------------------------
-- STATE MACHINE
---------------------------------------------------------------------------
--state register
process(clk, rst) begin
if rst = '1' then
current_state <= idle;
elsif rising_edge(clk) then
current_state <= next_state;
end if;
end process;
--update logic
process(current_state, data_in_buffer, ready_to_send) begin
--default
next_state <= current_state;
if current_state = idle and or_reduce(data_in_buffer) = '1' then
next_state <= select_vc;
end if;
if current_state = select_vc then
next_state <= rx_0;
end if;
if current_state = rx_0 then
next_state <= dequeue_0;
end if;
if current_state = dequeue_0 then
next_state <= wait_rx_0;
end if;
if current_state = wait_rx_0 and or_reduce(data_in_buffer and selected_vc_one_hot) = '1' then
next_state <= rx_1;
end if;
if current_state = rx_1 then
next_state <= dequeue_1;
end if;
if current_state = dequeue_1 then
next_state <= wait_tx_0;
end if;
if current_state = wait_tx_0 and ready_to_send = '1' then
next_state <= tx_0;
end if;
if current_state = tx_0 then
next_state <= wait_tx_1;
end if;
if current_state = wait_tx_1 and ready_to_send = '1' then
next_state <= tx_1;
end if;
if current_state = tx_1 then
next_state <= idle;
end if;
end process;
end architecture fsmd;
| mit | 028f541ac8ec1819aa1425ead3b3ae4a | 0.454463 | 3.760863 | false | false | false | false |
rpereira-dev/ENSIIE | UE/S3/microarchi/bus_ia/h100.vhd | 1 | 2,777 | -------------------------------------------------------------------------------
-- Entrée:
-- clk, reset la clock et le reset
-- Entier E coddé sur 24 bits
--
-- Sortie:
-- T , le tick : '0' ou '1'
-- T passe à '1' pendant un master clock, tous les 'E' master clock
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
entity h100 is
port(
-- clock et reset
clk : in STD_LOGIC;
reset : in STD_LOGIC;
-- entrée/sortie
E : in STD_LOGIC_VECTOR(23 downto 0);
T : out STD_LOGIC
);
end h100;
architecture montage of h100 is
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
type T_CMD is (LOAD, DECR, NOOP);
-- la commande courante
signal CMD : T_CMD;
-- le registre de stockage, compteur des clocks
signal R : unsigned (23 downto 0);
-- boolean vrai si R est à 0
signal R_IS_NULL: STD_LOGIC;
-------------------------------------------------------------------------------
-- Partie Contrôle
-------------------------------------------------------------------------------
type STATE_TYPE is (
ST_LOAD, ST_DECR, ST_TICK
);
signal state : STATE_TYPE;
begin
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
process (clk)
begin if clk'event and clk = '1' then
IF CMD = LOAD THEN
-- charges 'E' dans le compteur 'R', en multipliant par 2
R <= unsigned(E);
ELSIF CMD = DECR THEN
R <= R - 1;
END IF;
end if;
end process;
R_IS_NULL <= '1' WHEN R = 0 ELSE '0' ;
-------------------------------------------------------------------------------
-- Partie Contrôle
-------------------------------------------------------------------------------
-- Inputs: R_IS_NULL, state
-- Outputs: T, CMD, state
-------------------------------------------------------------------------------
-- fonction de transitition
process (reset, clk)
begin
if reset = '1' then
state <= ST_LOAD;
elsif clk'event and clk = '1' then
case state is
when ST_LOAD =>
state <= ST_DECR ;
when ST_DECR =>
IF R_IS_NULL = '1' THEN
state <= ST_TICK;
END IF ;
when ST_TICK =>
state <= ST_LOAD ;
end case;
end if;
end process;
-- fonction de sortie
with state select T <=
'1' when ST_TICK,
'0' when others
;
with state select CMD <=
LOAD when ST_LOAD,
DECR when ST_DECR,
NOOP when ST_TICK
;
end montage;
| gpl-3.0 | ee481ddbc72490d4a6b2c9e1e1c46d8d | 0.396315 | 4.082596 | false | false | false | false |
bargei/NoC264 | NoC264_2x2/inter_node.vhd | 1 | 15,257 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.math_real.all;
entity inter_node is
generic(
size_x : integer := 9;--12; --20 ; --12; --20 --20
size_y : integer := 9;--12; --20 ; --12; --20 --20
interp_x : integer := 4;--8; --4 ; --8; --2 --4
interp_y : integer := 4;--2; --4 ; --1; --2 --4
sample_size : integer := 8;--8; --8 ; --8;
samples_per_wr : integer := 8;--16; --16 ; --8; --4 --16
data_width : integer := 64;--128;--128 ; --64; --32 --128
addr_width : integer := 4;--1; --1 ; --1;
vc_sel_width : integer := 1;--1; --1 ; --1;
num_vc : integer := 2;--2; --2 ; --2;
flit_buff_depth : integer := 8--8 --8 --8
);
port(
clk : in std_logic;
rst : in std_logic;
-- recv interface to network
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
-- send interface to network
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic--;
----debug
--state_out : out std_logic_vector(7 downto 0);
--counter : out std_logic_vector(7 downto 0);
--rd_addr_x_out : out std_logic_vector(7 downto 0);
--rd_addr_y_out : out std_logic_vector(7 downto 0);
--height_out : out std_logic_vector(7 downto 0);
--wr_addr_x_out : out std_logic_vector(7 downto 0);
--wr_addr_y_out : out std_logic_vector(7 downto 0);
--interp_input : out std_logic_vector(9*7*8-1 downto 0)
);
end entity inter_node;
architecture fsmd of inter_node is
---------------------------------------------------------------------------
-- Constants --------------------------------------------------------------
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Components -------------------------------------------------------------
---------------------------------------------------------------------------
component inter_core is
generic(
x_len : integer := 4;
y_len : integer := 4;
sample_size : integer := 8
);
port(
samples : in std_logic_vector((x_len+5)*(y_len+5)*sample_size-1 downto 0);
sel : in std_logic_vector(7 downto 0);
result : out std_logic_vector(x_len*y_len*sample_size-1 downto 0)
);
end component inter_core;
component inter_core_reg_file is
generic(
size_x : integer := 20;
size_y : integer := 20;
interp_x : integer := 1;
interp_y : integer := 1;
sample_size : integer := 4;
samples_per_wr : integer := 1
);
port(
clk : in std_logic;
rst : in std_logic;
--read interface
rd_addr_x : in std_logic_vector(7 downto 0);
rd_addr_y : in std_logic_vector(7 downto 0);
rd_samples : out std_logic_vector((interp_x+5)*(interp_y+5)*sample_size-1 downto 0);
--write interface
wr_addr_x : in std_logic_vector(7 downto 0);
wr_addr_y : in std_logic_vector(7 downto 0);
wr_enable : in std_logic;
wr_samples : in std_logic_vector(samples_per_wr*sample_size-1 downto 0)
);
end component inter_core_reg_file;
component priority_encoder is
generic(
encoded_word_size : integer := 3
);
Port(
input : in std_logic_vector(2**encoded_word_size-1 downto 0);
output : out std_logic_vector(encoded_word_size-1 downto 0)
);
end component priority_encoder;
---------------------------------------------------------------------------
-- Types ------------------------------------------------------------------
---------------------------------------------------------------------------
type inter_states is (idle, sel_vc, init_rx, rx, rx_dequeue, wait_rx, init_tx, gen_resp, wait_tx, tx);
---------------------------------------------------------------------------
-- Signals ----------------------------------------------------------------
---------------------------------------------------------------------------
--component interfaces
signal rd_addr_x : std_logic_vector(7 downto 0);
signal rd_addr_y : std_logic_vector(7 downto 0);
signal rd_samples : std_logic_vector((interp_x+5)*(interp_y+5)*sample_size-1 downto 0);
signal wr_addr_x : std_logic_vector(7 downto 0);
signal wr_addr_y : std_logic_vector(7 downto 0);
signal wr_enable : std_logic;
signal wr_samples : std_logic_vector(samples_per_wr*sample_size-1 downto 0);
signal sel : std_logic_vector(7 downto 0);
signal result : std_logic_vector(interp_x*interp_y*sample_size-1 downto 0);
-- FSMD registers and signals
signal interp_mode_d : std_logic_vector(7 downto 0);
signal interp_mode_q : std_logic_vector(7 downto 0);
signal cmd_width_d : std_logic_vector(7 downto 0);
signal cmd_width_q : std_logic_vector(7 downto 0);
signal cmd_height_d : std_logic_vector(7 downto 0);
signal cmd_height_q : std_logic_vector(7 downto 0);
signal part_width_d : std_logic_vector(7 downto 0);
signal part_width_q : std_logic_vector(7 downto 0);
signal part_height_d : std_logic_vector(7 downto 0);
signal part_height_q : std_logic_vector(7 downto 0);
signal ref_num_d : std_logic_vector(31 downto 0);
signal ref_num_q : std_logic_vector(31 downto 0);
signal counter_d : unsigned(7 downto 0);
signal counter_q : unsigned(7 downto 0);
signal tx_max_count : unsigned(7 downto 0);
signal selected_vc_encoder : std_logic_vector(vc_sel_width-1 downto 0);
signal selected_vc_d : std_logic_vector(vc_sel_width-1 downto 0);
signal selected_vc_q : std_logic_vector(vc_sel_width-1 downto 0);
signal selected_vc_one_hot : std_logic_vector(num_vc-1 downto 0);
signal wr_addr_x_int : integer;
signal wr_addr_y_int : integer;
signal rd_addr_x_int : integer;
signal rd_addr_y_int : integer;
-- state machine signals
signal state : inter_states;
signal next_state : inter_states;
begin
---------------------------------------------------------------------------
-- Datapath ---------------------------------------------------------------
---------------------------------------------------------------------------
u0: component inter_core
generic map(
x_len => interp_x,
y_len => interp_y,
sample_size => sample_size
)
port map(
samples => rd_samples,
sel => sel,
result => result
);
u1: component inter_core_reg_file
generic map(
size_x => size_x,
size_y => size_y,
interp_x => interp_x,
interp_y => interp_y,
sample_size => sample_size,
samples_per_wr => samples_per_wr
)
port map(
clk => clk,
rst => rst,
rd_addr_x => rd_addr_x,
rd_addr_y => rd_addr_y,
rd_samples => rd_samples,
wr_addr_x => wr_addr_x,
wr_addr_y => wr_addr_y,
wr_enable => wr_enable,
wr_samples => wr_samples
);
u2: component priority_encoder
generic map(
encoded_word_size => vc_sel_width
)
Port map(
input => data_in_buffer,
output => selected_vc_encoder
);
--datapath registers
process(clk, rst)
begin
if rst = '1' then
interp_mode_q <= (others => '0');
cmd_width_q <= (others => '0');
cmd_height_q <= (others => '0');
part_width_q <= (others => '0');
part_height_q <= (others => '0');
ref_num_q <= (others => '0');
counter_q <= (others => '0');
selected_vc_q <= (others => '0');
elsif rising_edge(clk) then
interp_mode_q <= interp_mode_d;
cmd_width_q <= cmd_width_d;
cmd_height_q <= cmd_height_d;
part_width_q <= part_width_d;
part_height_q <= part_height_d;
ref_num_q <= ref_num_d;
counter_q <= counter_d;
selected_vc_q <= selected_vc_d;
end if;
end process;
--Parser logic
ref_num_d <= recv_data(31 downto 0 ) when state = rx and counter_q = x"00" else ref_num_q;
interp_mode_d <= recv_data(7 downto 0 ) when state = rx and counter_q = x"01" else interp_mode_q;
--cmd_width_d <= recv_data(15 downto 8 ) when state = rx and counter_q = x"01" else cmd_width_q;
--cmd_height_d <= recv_data(24 downto 16 ) when state = rx and counter_q = x"01" else cmd_height_q;
part_width_d <= recv_data(15 downto 8) when state = rx and counter_q = x"01" else part_width_q;
part_height_d <= recv_data(23 downto 16) when state = rx and counter_q = x"01" else part_height_q;
sel <= interp_mode_q;
wr_samples <= recv_data(sample_size*samples_per_wr-1 downto 0);
selected_vc_one_hot <= "10" when selected_vc_d = "1" else "01"; --todo make generic
--calculate buffer write addresses
-- for now assume all 20x20 samples are sent every time
-- TODO: this is an oppurtunity for speed improvement latter on
-- time permitting...
-- this will require the use of the width/heigth inputs
wr_addr_x_int <= to_integer(unsigned(counter_q - to_unsigned(2, 8))) mod (size_x/samples_per_wr);
wr_addr_y_int <= to_integer(unsigned(counter_q - to_unsigned(2, 8))) / (size_x/samples_per_wr);
wr_addr_x <= std_logic_vector(to_unsigned(wr_addr_x_int, 8));
wr_addr_y <= std_logic_vector(to_unsigned(wr_addr_y_int, 8));
--buffer controls
wr_enable <= '1' when state = rx and counter_q >= to_unsigned(2, 8) else '0';
--counter update
counter_d <= counter_q + to_unsigned(1, 8) when state = rx_dequeue or state = gen_resp else
to_unsigned(0, 8) when state = init_tx or state = sel_vc else
counter_q;
--select virtual channel
selected_vc_d <= selected_vc_encoder when state = sel_vc else selected_vc_q;
--packet generation logic
assert interp_x*interp_y*sample_size = data_width report "inter_prediction_node: interpolation-block/flit-size mismatch" severity error;
send_data <= X"00000000" & ref_num_q when counter_q = x"01" else result;
rd_addr_x_int <= 2; -- todo: this really shouldn't be a constant, some parameters will not work...
rd_addr_x <= std_logic_vector(to_unsigned(rd_addr_x_int, 8));
rd_addr_y_int <= (to_integer(unsigned(counter_q)) - 2)*2 + 2;
rd_addr_y <= std_logic_vector(to_unsigned(rd_addr_y_int, 8));
tx_max_count <= unsigned(part_height_q) + to_unsigned(1, 8);
--output logic (Noc control stuff)
dequeue <= selected_vc_one_hot when state = rx_dequeue else (others => '0');
select_vc_read <= selected_vc_q;
dest_addr <= std_logic_vector(to_unsigned(7, addr_width));
set_tail_flit <= '1' when (state = tx or state = wait_tx) and counter_q >= tx_max_count else '0';
send_flit <= '1' when state = tx else '0';
---------------------------------------------------------------------------
-- State Machine ----------------------------------------------------------
---------------------------------------------------------------------------
process(clk, rst)
begin
if rst = '1' then
state <= idle;
elsif rising_edge(clk) then
state <= next_state;
end if;
end process;
process(state, data_in_buffer, is_tail_flit, selected_vc_one_hot, ready_to_send, counter_q, tx_max_count)
begin
--default
next_state <= state;
if state = idle and or_reduce(data_in_buffer) = '1' then
next_state <= sel_vc;
end if;
if state = sel_vc then
next_state <= init_rx;
end if;
if state = init_rx then
next_state <= rx;
end if;
if state = rx then
next_state <= rx_dequeue;
end if;
if state = rx_dequeue and is_tail_flit = '0' then
next_state <= wait_rx;
end if;
if state = rx_dequeue and is_tail_flit = '1' then
next_state <= init_tx;
end if;
if state = wait_rx and or_reduce(selected_vc_one_hot and data_in_buffer) = '1' then
next_state <= rx;
end if;
if state = init_tx then
next_state <= gen_resp;
end if;
if state = gen_resp then
next_state <= wait_tx;
end if;
if state = wait_tx and ready_to_send = '1' then
next_state <= tx;
end if;
if state = tx and counter_q < tx_max_count then
next_state <= gen_resp;
end if;
if state = tx and counter_q >= tx_max_count then
next_state <= idle;
end if;
end process;
--debug
--state_out <= x"00" when state = idle else
-- x"01" when state = sel_vc else
-- x"02" when state = init_rx else
-- x"03" when state = rx else
-- x"04" when state = rx_dequeue else
-- x"05" when state = wait_rx else
-- x"06" when state = init_tx else
-- x"07" when state = gen_resp else
-- x"08" when state = wait_tx else
-- x"09" when state = tx else
-- x"FF";
--counter <= std_logic_vector(counter_q);
--rd_addr_x_out <= rd_addr_x;
--rd_addr_y_out <= rd_addr_y;
--height_out <= part_height_q;
--wr_addr_x_out <= wr_addr_x;
--wr_addr_y_out <= wr_addr_y;
--interp_input <= rd_samples;
end architecture fsmd; | mit | 59bd8e7eef32e648e67927f0f7997751 | 0.478141 | 3.694189 | false | false | false | false |
DaveyPocket/btrace448 | core/buf.vhd | 1 | 963 | -- Btrace 448
-- Dual-port BRAM
--
-- Bradley Boccuzzi
-- 2016
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity buf is
generic(N: integer := 4); -- Address bits
port(clk: in std_logic;
en: in std_logic;
Din: in std_logic_vector(11 downto 0);
Dout: out std_logic_vector(11 downto 0);
iAddr: in std_logic_vector(N-1 downto 0);
Addr: in std_logic_vector(N-1 downto 0));
end buf;
architecture arch of buf is
type ram_t is array(0 to (2**N)-1) of std_logic_vector(11 downto 0);
signal ram: ram_t; -- Uninitialized!
signal addrRegi, addrRego: std_logic_vector(N-1 downto 0);
begin
Dout <= ram(to_integer(unsigned(addrRego)));
process(clk)
begin
if rising_edge(clk) then
addrRegi <= iAddr;-- Inferring BRAM.........
addrRego <= Addr;-- Inferring BRAM.........
if (en = '1') then
ram(to_integer(unsigned(addrRegi))) <= Din;
end if;
end if;
end process;
end arch;
| gpl-3.0 | 69bab4cc3d8f89bf01e70815b2bd3ce7 | 0.635514 | 2.883234 | false | false | false | false |
boztalay/OldProjects | FPGA/LCD_Control/TestCPU1_RegFile.vhd | 1 | 2,205 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 00:57:43 10/03/2009
-- Design Name:
-- Module Name: TestCPU1_RegFile - Behavioral
-- Project Name: Test CPU 1
-- Target Devices:
-- Tool versions:
-- Description: The register file for Test CPU 1
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TestCPU1_RegFile is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
ld_val: in STD_LOGIC;
ALUB_out : in STD_LOGIC;
src1_addr : in STD_LOGIC_VECTOR(2 downto 0);
src2_addr : in STD_LOGIC_VECTOR(2 downto 0);
dest_addr : in STD_LOGIC_VECTOR(2 downto 0);
data_to_load : in STD_LOGIC_VECTOR(15 downto 0);
to_ALUA_out : out STD_LOGIC_VECTOR(15 downto 0);
to_ALUB_out : out STD_LOGIC_VECTOR(15 downto 0);
data_collection_1 : out STD_LOGIC_VECTOR(15 downto 0)); --
end TestCPU1_RegFile;
architecture Behavioral of TestCPU1_RegFile is
begin
RegFile: process (clock, reset, ALUB_out, src1_addr, src2_addr) is
type reg_array is array (7 downto 0) of
STD_LOGIC_VECTOR(15 downto 0);
variable reg_file: reg_array := (others => b"0000000000000000");
begin
if falling_edge(clock) then
if reset = '1' then
reg_file := (others => b"0000000000000000");
elsif ((ld_val = '1') and (dest_addr /= b"000")) then
reg_file(conv_integer(unsigned(dest_addr))) := data_to_load;
end if;
end if;
if ALUB_out = '0' then
to_ALUB_out <= x"0000";
else
to_ALUB_out <= reg_file(conv_integer(unsigned(src2_addr)));
end if;
to_ALUA_out <= reg_file(conv_integer(unsigned(src1_addr)));
data_collection_1 <= reg_file(1);
end process;
end Behavioral;
| mit | dd5fb1540fd385bae840b306b0cb5c4a | 0.589569 | 3.340909 | false | true | false | false |
AfterRace/SoC_Project | vivado/project/project.srcs/sources_1/ipshared/tsotnep/filter_iir_v1_0/263d46e2/hdl/FILTER_IIR_v1_0_S00_AXI.vhd | 2 | 27,253 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FILTER_IIR_v1_0_S00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 7
);
port (
-- Users to add ports here
AUDIO_OUT_L : out std_logic_vector(23 downto 0);
AUDIO_OUT_R : out std_logic_vector(23 downto 0);
FILTER_DONE : out std_logic;
SAMPLE_TRIG : in std_logic;
AUDIO_IN_L : in std_logic_vector(23 downto 0);
AUDIO_IN_R : in std_logic_vector(23 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end FILTER_IIR_v1_0_S00_AXI;
architecture arch_imp of FILTER_IIR_v1_0_S00_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 4;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 20
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg12 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg13 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg14 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg15 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg16 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg17 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg18 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg19 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
slv_reg8 <= (others => '0');
slv_reg9 <= (others => '0');
slv_reg10 <= (others => '0');
slv_reg11 <= (others => '0');
slv_reg12 <= (others => '0');
slv_reg13 <= (others => '0');
slv_reg14 <= (others => '0');
slv_reg15 <= (others => '0');
slv_reg16 <= (others => '0');
slv_reg17 <= (others => '0');
slv_reg18 <= (others => '0');
slv_reg19 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"00000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 8
slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 9
slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 10
slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 11
slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 12
slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 13
slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 14
slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 15
slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 16
slv_reg16(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 17
slv_reg17(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 18
slv_reg18(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 19
slv_reg19(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
slv_reg8 <= slv_reg8;
slv_reg9 <= slv_reg9;
slv_reg10 <= slv_reg10;
slv_reg11 <= slv_reg11;
slv_reg12 <= slv_reg12;
slv_reg13 <= slv_reg13;
slv_reg14 <= slv_reg14;
slv_reg15 <= slv_reg15;
slv_reg16 <= slv_reg16;
slv_reg17 <= slv_reg17;
slv_reg18 <= slv_reg18;
slv_reg19 <= slv_reg19;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, slv_reg18, slv_reg19, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"00000" =>
reg_data_out <= slv_reg0;
when b"00001" =>
reg_data_out <= slv_reg1;
when b"00010" =>
reg_data_out <= slv_reg2;
when b"00011" =>
reg_data_out <= slv_reg3;
when b"00100" =>
reg_data_out <= slv_reg4;
when b"00101" =>
reg_data_out <= slv_reg5;
when b"00110" =>
reg_data_out <= slv_reg6;
when b"00111" =>
reg_data_out <= slv_reg7;
when b"01000" =>
reg_data_out <= slv_reg8;
when b"01001" =>
reg_data_out <= slv_reg9;
when b"01010" =>
reg_data_out <= slv_reg10;
when b"01011" =>
reg_data_out <= slv_reg11;
when b"01100" =>
reg_data_out <= slv_reg12;
when b"01101" =>
reg_data_out <= slv_reg13;
when b"01110" =>
reg_data_out <= slv_reg14;
when b"01111" =>
reg_data_out <= slv_reg15;
when b"10000" =>
reg_data_out <= slv_reg16;
when b"10001" =>
reg_data_out <= slv_reg17;
when b"10010" =>
reg_data_out <= slv_reg18;
when b"10011" =>
reg_data_out <= slv_reg19;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
Filter_Top_Level_inst : entity work.Filter_Top_Level
port map(
AUDIO_OUT_L => AUDIO_OUT_L,
AUDIO_OUT_R => AUDIO_OUT_R,
FILTER_DONE => FILTER_DONE,
CLK_100mhz => S_AXI_ACLK,
SAMPLE_TRIG => SAMPLE_TRIG,
AUDIO_IN_L => AUDIO_IN_L,
AUDIO_IN_R => AUDIO_IN_R,
RST => slv_reg15(0),
sample_trigger_en => slv_reg16(0),
HP_SW => slv_reg17(0),
BP_SW => slv_reg18(0),
LP_SW => slv_reg19(0),
slv_reg0 => slv_reg0,
slv_reg1 => slv_reg1,
slv_reg2 => slv_reg2,
slv_reg3 => slv_reg3,
slv_reg4 => slv_reg4,
slv_reg5 => slv_reg5,
slv_reg6 => slv_reg6,
slv_reg7 => slv_reg7,
slv_reg8 => slv_reg8,
slv_reg9 => slv_reg9,
slv_reg10 => slv_reg10,
slv_reg11 => slv_reg11,
slv_reg12 => slv_reg12,
slv_reg13 => slv_reg13,
slv_reg14 => slv_reg14
);
-- User logic ends
end arch_imp;
| lgpl-3.0 | 2ad7be2b8c257a5ddee30bdf10f017b5 | 0.559792 | 3.468185 | false | false | false | false |
peladex/RHD2132_FPGA | src/spi_master_slave/spi_loopback_test.vhd | 2 | 14,081 | --------------------------------------------------------------------------------
-- Company:
-- Engineer: Jonny Doin
--
-- Create Date: 22:59:18 04/25/2011
-- Design Name: spi_master_slave
-- Module Name: spi_master_slave/spi_loopback_test.vhd
-- Project Name: SPI_interface
-- Target Device: Spartan-6
-- Tool versions: ISE 13.1
-- Description: Testbench to simulate the master and slave SPI interfaces. Each module can be tested
-- in a "real" environment, where the 'spi_master' exchanges data with the 'spi_slave'
-- module, simulating the internal working of each design.
-- In behavioral simulation, select a matching data width (N) and spi mode (CPOL, CPHA) for
-- both modules, and also a different clock domain for each parallel interface.
-- Different values for PREFETCH for each interface can be tested, to model the best value
-- for the pipelined memory / bus that is attached to the di/do ports.
-- To test the parallel interfaces, a simple ROM memory is simulated for each interface, with
-- 8 words of data to be sent, synchronous to each clock and flow control signals.
--
--
-- VHDL Test Bench Created by ISE for modules: 'spi_master' and 'spi_slave'
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.10 - Implemented FIFO simulation for each interface.
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
library work;
use work.all;
ENTITY spi_loopback_test IS
GENERIC (
N : positive := 32; -- 32bit serial word length is default
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
CPHA : std_logic := '1'; -- CPOL = clock polarity, CPHA = clock phase.
PREFETCH : positive := 2 -- prefetch lookahead cycles
);
END spi_loopback_test;
ARCHITECTURE behavior OF spi_loopback_test IS
--=========================================================
-- Component declaration for the Unit Under Test (UUT)
--=========================================================
COMPONENT spi_loopback
PORT(
m_clk_i : IN std_logic;
m_rst_i : IN std_logic;
m_spi_miso_i : IN std_logic;
m_di_i : IN std_logic_vector(31 downto 0);
m_wren_i : IN std_logic;
s_clk_i : IN std_logic;
s_spi_ssel_i : IN std_logic;
s_spi_sck_i : IN std_logic;
s_spi_mosi_i : IN std_logic;
s_di_i : IN std_logic_vector(31 downto 0);
s_wren_i : IN std_logic;
m_spi_ssel_o : OUT std_logic;
m_spi_sck_o : OUT std_logic;
m_spi_mosi_o : OUT std_logic;
m_di_req_o : OUT std_logic;
m_do_valid_o : OUT std_logic;
m_do_o : OUT std_logic_vector(31 downto 0);
m_do_transfer_o : OUT std_logic;
m_wren_o : OUT std_logic;
m_wren_ack_o : OUT std_logic;
m_rx_bit_reg_o : OUT std_logic;
m_state_dbg_o : OUT std_logic_vector(5 downto 0);
m_core_clk_o : OUT std_logic;
m_core_n_clk_o : OUT std_logic;
m_sh_reg_dbg_o : OUT std_logic_vector(31 downto 0);
s_spi_miso_o : OUT std_logic;
s_di_req_o : OUT std_logic;
s_do_valid_o : OUT std_logic;
s_do_o : OUT std_logic_vector(31 downto 0);
s_do_transfer_o : OUT std_logic;
s_wren_o : OUT std_logic;
s_wren_ack_o : OUT std_logic;
s_rx_bit_reg_o : OUT std_logic;
s_state_dbg_o : OUT std_logic_vector(5 downto 0)
);
END COMPONENT;
--=========================================================
-- constants
--=========================================================
constant fifo_memory_size : integer := 16;
--=========================================================
-- types
--=========================================================
type fifo_memory_type is array (0 to fifo_memory_size-1) of std_logic_vector (N-1 downto 0);
--=========================================================
-- signals to connect the instances
--=========================================================
-- internal clk and rst
signal m_clk : std_logic := '0'; -- clock domain for the master parallel interface. Must be faster than spi bus sck.
signal s_clk : std_logic := '0'; -- clock domain for the slave parallel interface. Must be faster than spi bus sck.
signal rst : std_logic := 'U';
-- spi bus wires
signal spi_sck : std_logic;
signal spi_ssel : std_logic;
signal spi_miso : std_logic;
signal spi_mosi : std_logic;
-- master parallel interface
signal di_m : std_logic_vector (N-1 downto 0) := (others => '0');
signal do_m : std_logic_vector (N-1 downto 0) := (others => 'U');
signal do_valid_m : std_logic;
signal do_transfer_m : std_logic;
signal di_req_m : std_logic;
signal wren_m : std_logic := '0';
signal wren_o_m : std_logic := 'U';
signal wren_ack_o_m : std_logic := 'U';
signal rx_bit_reg_m : std_logic;
signal state_m : std_logic_vector (5 downto 0);
signal core_clk_o_m : std_logic;
signal core_n_clk_o_m : std_logic;
signal sh_reg_m : std_logic_vector (N-1 downto 0) := (others => '0');
-- slave parallel interface
signal di_s : std_logic_vector (N-1 downto 0) := (others => '0');
signal do_s : std_logic_vector (N-1 downto 0);
signal do_valid_s : std_logic;
signal do_transfer_s : std_logic;
signal di_req_s : std_logic;
signal wren_s : std_logic := '0';
signal wren_o_s : std_logic := 'U';
signal wren_ack_o_s : std_logic := 'U';
signal rx_bit_reg_s : std_logic;
signal state_s : std_logic_vector (5 downto 0);
-- signal sh_reg_s : std_logic_vector (N-1 downto 0);
--=========================================================
-- Clock period definitions
--=========================================================
constant m_clk_period : time := 10 ns; -- 100MHz master parallel clock
constant s_clk_period : time := 10 ns; -- 100MHz slave parallel clock
BEGIN
--=========================================================
-- Component instantiation for the Unit Under Test (UUT)
--=========================================================
Inst_spi_loopback: spi_loopback
port map(
----------------MASTER-----------------------
m_clk_i => m_clk,
m_rst_i => rst,
m_spi_ssel_o => spi_ssel,
m_spi_sck_o => spi_sck,
m_spi_mosi_o => spi_mosi,
m_spi_miso_i => spi_miso,
m_di_req_o => di_req_m,
m_di_i => di_m,
m_wren_i => wren_m,
m_do_valid_o => do_valid_m,
m_do_o => do_m,
----- debug -----
m_do_transfer_o => do_transfer_m,
m_wren_o => wren_o_m,
m_wren_ack_o => wren_ack_o_m,
m_rx_bit_reg_o => rx_bit_reg_m,
m_state_dbg_o => state_m,
m_core_clk_o => core_clk_o_m,
m_core_n_clk_o => core_n_clk_o_m,
m_sh_reg_dbg_o => sh_reg_m,
----------------SLAVE-----------------------
s_clk_i => s_clk,
s_spi_ssel_i => spi_ssel,
s_spi_sck_i => spi_sck,
s_spi_mosi_i => spi_mosi,
s_spi_miso_o => spi_miso,
s_di_req_o => di_req_s,
s_di_i => di_s,
s_wren_i => wren_s,
s_do_valid_o => do_valid_s,
s_do_o => do_s,
----- debug -----
s_do_transfer_o => do_transfer_s,
s_wren_o => wren_o_s,
s_wren_ack_o => wren_ack_o_s,
s_rx_bit_reg_o => rx_bit_reg_s,
s_state_dbg_o => state_s
-- s_sh_reg_dbg_o => sh_reg_s
);
--=========================================================
-- Clock generator processes
--=========================================================
m_clk_process : process
begin
m_clk <= '0';
wait for m_clk_period/2;
m_clk <= '1';
wait for m_clk_period/2;
end process m_clk_process;
s_clk_process : process
begin
s_clk <= '0';
wait for s_clk_period/2;
s_clk <= '1';
wait for s_clk_period/2;
end process s_clk_process;
--=========================================================
-- rst_i process
--=========================================================
rst <= '0', '1' after 20 ns, '0' after 100 ns;
--=========================================================
-- Master interface process
--=========================================================
master_tx_fifo_proc: process is
variable fifo_memory : fifo_memory_type :=
(X"87654321",X"abcdef01",X"faceb007",X"10203049",X"85a5a5a5",X"7aaa5551",X"7adecabe",X"57564789",
X"12345678",X"beefbeef",X"fee1600d",X"f158ba17",X"5ee1a7e3",X"101096da",X"600ddeed",X"deaddead");
variable fifo_head : integer range 0 to fifo_memory_size-1;
begin
-- synchronous rst_i
wait until rst = '1';
wait until m_clk'event and m_clk = '1';
di_m <= (others => '0');
wren_m <= '0';
fifo_head := 0;
wait until rst = '0';
wait until di_req_m = '1'; -- wait shift register request for data
-- load next fifo contents into shift register
for cnt in 0 to (fifo_memory_size/2)-1 loop
fifo_head := cnt; -- pre-compute next pointer
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
di_m <= fifo_memory(fifo_head); -- place data into tx_data input bus
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
wren_m <= '1'; -- write data into spi master
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
wren_m <= '0'; -- remove write enable signal
wait until di_req_m = '1'; -- wait shift register request for data
end loop;
wait until spi_ssel = '1';
wait for 2000 ns;
for cnt in (fifo_memory_size/2) to fifo_memory_size-1 loop
fifo_head := cnt; -- pre-compute next pointer
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
di_m <= fifo_memory(fifo_head); -- place data into tx_data input bus
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
wren_m <= '1'; -- write data into spi master
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge
wren_m <= '0'; -- remove write enable signal
wait until di_req_m = '1'; -- wait shift register request for data
end loop;
wait;
end process master_tx_fifo_proc;
--=========================================================
-- Slave interface process
--=========================================================
slave_tx_fifo_proc: process is
variable fifo_memory : fifo_memory_type :=
(X"90201031",X"97640231",X"ef55aaf1",X"babaca51",X"b00b1ee5",X"51525354",X"81828384",X"91929394",
X"be575ec5",X"2fa57410",X"cafed0ce",X"afadab0a",X"bac7ed1a",X"f05fac75",X"2acbac7e",X"12345678");
variable fifo_head : integer range 0 to fifo_memory_size-1;
begin
-- synchronous rst_i
wait until rst = '1';
wait until s_clk'event and s_clk = '1';
di_s <= (others => '0');
wren_s <= '0';
fifo_head := 0;
wait until rst = '0';
wait until di_req_s = '1'; -- wait shift register request for data
-- load next fifo contents into shift register
for cnt in 0 to fifo_memory_size-1 loop
fifo_head := cnt; -- pre-compute next pointer
wait until s_clk'event and s_clk = '1'; -- sync fifo data load at next rising edge
di_s <= fifo_memory(fifo_head); -- place data into tx_data input bus
wait until s_clk'event and s_clk = '1'; -- sync fifo data load at next rising edge
wren_s <= '1'; -- write data into shift register
wait until s_clk'event and s_clk = '1'; -- sync fifo data load at next rising edge
wait until s_clk'event and s_clk = '1'; -- sync fifo data load at next rising edge
wren_s <= '0'; -- remove write enable signal
wait until di_req_s = '1'; -- wait shift register request for data
end loop;
wait;
end process slave_tx_fifo_proc;
END ARCHITECTURE behavior;
| gpl-3.0 | 74d918f7e61243581008e629522f5158 | 0.484483 | 3.811857 | false | false | false | false |
bargei/NoC264 | NoC264_3x3/network_interface_latched_vc.vhd | 1 | 7,360 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
entity network_interface is
generic(
data_width : integer := 64;
addr_width : integer := 1;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
--clk, reset
clk : in std_logic;
rst : in std_logic;
--user sending interface
send_data : in std_logic_vector(data_width-1 downto 0);
dest_addr : in std_logic_vector(addr_width-1 downto 0);
set_tail_flit : in std_logic;
send_flit : in std_logic;
ready_to_send : out std_logic;
--user receiving interface
recv_data : out std_logic_vector(data_width-1 downto 0);
src_addr : out std_logic_vector(addr_width-1 downto 0);
is_tail_flit : out std_logic;
data_in_buffer : out std_logic_vector(num_vc-1 downto 0);
dequeue : in std_logic_vector(num_vc-1 downto 0);
select_vc_read : in std_logic_vector(vc_sel_width-1 downto 0);
--interface to network
send_putFlit_flit_in : out std_logic_vector(data_width+addr_width+vc_sel_width+1 downto 0);
EN_send_putFlit : out std_logic;
EN_send_getNonFullVCs : out std_logic;
send_getNonFullVCs : in std_logic_vector(num_vc-1 downto 0);
EN_recv_getFlit : out std_logic;
recv_getFlit : in std_logic_vector(data_width+addr_width+vc_sel_width+1 downto 0);
recv_putNonFullVCs_nonFullVCs : out std_logic_vector(num_vc-1 downto 0);
EN_recv_putNonFullVCs : out std_logic;
recv_info_getRecvPortID : in std_logic_vector(addr_width-1 downto 0)
);
end entity network_interface;
architecture structural of network_interface is
--fifo buffer for reciving
component fifo_buffer is
generic(
word_len : integer := 64;
buff_len : integer := 8
);
port(
write_data : in std_logic_vector(word_len-1 downto 0);
read_data : out std_logic_vector(word_len-1 downto 0);
buffer_full : out std_logic;
buffer_empty : out std_logic;
enqueue : in std_logic;
dequeue : in std_logic;
clk : in std_logic;
rst : in std_logic
);
end component fifo_buffer;
type fifo_io is array(num_vc-1 downto 0) of std_logic_vector(vc_sel_width+data_width+addr_width+1 downto 0);
signal write_vc, read_vc: fifo_io;
signal buffer_full_vc, buffer_empty_vc, enqueue_vc, dequeue_vc: std_logic_vector(num_vc-1 downto 0);
signal receive_vc: std_logic_vector(vc_sel_width-1 downto 0);
-- priority encoder
component priority_encoder is
generic(
encoded_word_size : integer := 3
);
Port(
input : in std_logic_vector(2**encoded_word_size-1 downto 0);
output : out std_logic_vector(encoded_word_size-1 downto 0)
);
end component priority_encoder;
signal selected_vc_d : std_logic_vector(vc_sel_width-1 downto 0);
signal selected_vc_q : std_logic_vector(vc_sel_width-1 downto 0);
signal selected_vc_enc : std_logic_vector(vc_sel_width-1 downto 0);
type ni_states is (idle, sending);
signal state, next_state : ni_states;
--constants to parse flits
constant data_msb : integer := data_width-1;
constant data_lsb : integer := 0;
constant vc_msb : integer := vc_sel_width+data_width-1;
constant vc_lsb : integer := data_width;
constant addr_msb : integer := vc_sel_width+data_width+addr_width-1;
constant addr_lsb : integer := vc_sel_width+data_width;
constant is_tail_index : integer := vc_sel_width+data_width+addr_width;
constant is_valid_index : integer := vc_sel_width+data_width+addr_width+1;
constant flit_size : integer := vc_sel_width+data_width+addr_width+2;
begin
---------------------------------------------------------------------------
--RECEIVE SIDE ------------------------------------------------------------
---------------------------------------------------------------------------
-- create and map 1 buffer for each VC
receive_buffer: for i in num_vc-1 downto 0 generate
signal vc_select : integer;
signal flit_valid : std_logic;
begin
ur_i: fifo_buffer generic map(data_width+addr_width+vc_sel_width+2, flit_buff_depth)
port map(write_vc(i), read_vc(i), buffer_full_vc(i), buffer_empty_vc(i),
enqueue_vc(i), dequeue_vc(i), clk, rst);
vc_select <= to_integer(unsigned(recv_getFlit(vc_msb downto vc_lsb)));
flit_valid <= recv_getFlit(is_valid_index);
write_vc(i) <= recv_getFlit when i = vc_select else std_logic_vector(to_unsigned(0,flit_size));
enqueue_vc(i) <= flit_valid when i = vc_select else '0';
end generate;
-- IO for receive side of controller
EN_recv_getFlit <= '1'; -- always read to receive flits as long as buffers aren't full
recv_putNonFullVCs_nonFullVCs <= not buffer_full_vc;
data_in_buffer <= not buffer_empty_vc;
recv_data <= read_vc(to_integer(unsigned(select_vc_read)))(data_msb downto data_lsb);
dequeue_vc <= dequeue;
is_tail_flit <= read_vc(to_integer(unsigned(select_vc_read)))(is_tail_index);
src_addr <= read_vc(to_integer(unsigned(select_vc_read)))(addr_msb downto addr_lsb);
EN_recv_putNonFullVCs <= '1'; -- readme is not clear about what this does, assuming it is not need for peek flow control
---------------------------------------------------------------------------
--SEND SIDE ---------------------------------------------------------------
---------------------------------------------------------------------------
-- priority encoder to determine which vc to use
us_0: priority_encoder generic map(vc_sel_width)
port map(send_getNonFullVCs, selected_vc_enc);
process(clk, rst)
begin
if rst = '1' then
selected_vc_q <= (others => '0');
state <= idle;
elsif rising_edge(clk) then
selected_vc_q <= selected_vc_d;
state <= next_state;
end if;
end process;
selected_vc_d <= selected_vc_enc when state = idle else
selected_vc_q;
process(state, send_flit, set_tail_flit)
begin
next_state <= state;
if state = idle and send_flit = '1' then
next_state <= sending;
end if;
if state = sending and set_tail_flit = '1' then
next_state <= idle;
end if;
end process;
-- IO for sending side of controller
send_putFlit_flit_in <= send_flit & set_tail_flit & dest_addr & selected_vc_q & send_data;
ready_to_send <= or_reduce(send_getNonFullVCs) when state = idle else
send_getNonFullVCs(0) when state = sending and selected_vc_q = "01" else
send_getNonFullVCs(1) when state = sending and selected_vc_q = "10";
EN_send_putFlit <= send_flit;
EN_send_getNonFullVCs <= '1'; --always read to recieve credits
end architecture structural;
| mit | 8348303c95df7df573d60b3088669909 | 0.565353 | 3.702213 | false | false | false | false |
AfterRace/SoC_Project | vivado/project/project.srcs/sources_1/ipshared/user.org/zed_audio_v1_0/8de2dafc/hdl/adau1761_izedboard.vhd | 2 | 4,658 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:47:06 01/18/2014
-- Design Name:
-- Module Name: adau1761_izedboard - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library unisim;
use unisim.vcomponents.all;
entity adau1761_izedboard is
Port ( clk_48 : in STD_LOGIC;
AC_ADR0 : out STD_LOGIC;
AC_ADR1 : out STD_LOGIC;
AC_GPIO0 : out STD_LOGIC; -- I2S MISO
AC_GPIO1 : in STD_LOGIC; -- I2S MOSI
AC_GPIO2 : in STD_LOGIC; -- I2S_bclk
AC_GPIO3 : in STD_LOGIC; -- I2S_LR
AC_MCLK : out STD_LOGIC;
AC_SCK : out STD_LOGIC;
AC_SDA : inout STD_LOGIC;
hphone_l : in std_logic_vector(23 downto 0);
hphone_r : in std_logic_vector(23 downto 0);
line_in_l : out std_logic_vector(23 downto 0);
line_in_r : out std_logic_vector(23 downto 0);
new_sample: out std_logic;
sw : in std_logic_vector(1 downto 0);
active : out std_logic_vector(1 downto 0)
);
end adau1761_izedboard;
architecture Behavioral of adau1761_izedboard is
COMPONENT i2c
PORT(
clk : IN std_logic;
i2c_sda_i : IN std_logic;
i2c_sda_o : OUT std_logic;
i2c_sda_t : OUT std_logic;
i2c_scl : OUT std_logic;
sw : in std_logic_vector(1 downto 0);
active : out std_logic_vector(1 downto 0));
END COMPONENT;
COMPONENT ADAU1761_interface
PORT(
clk_48 : IN std_logic;
codec_master_clk : OUT std_logic
);
END COMPONENT;
COMPONENT i2s_bit_clock
PORT(
clk_48 : IN std_logic;
pulse_per_bit : OUT std_logic;
i2s_clk : OUT std_logic
);
END COMPONENT;
component clocking
port(
CLK_100 : in std_logic;
CLK_48 : out std_logic;
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
COMPONENT audio_signal
PORT(
clk : IN std_logic;
sample_taken : IN std_logic;
audio_l : OUT std_logic_vector(15 downto 0);
audio_r : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT i2s_data_interface
PORT(
clk : IN std_logic;
audio_l_in : IN std_logic_vector(23 downto 0);
audio_r_in : IN std_logic_vector(23 downto 0);
i2s_bclk : IN std_logic;
i2s_lr : IN std_logic;
audio_l_out : OUT std_logic_vector(23 downto 0);
audio_r_out : OUT std_logic_vector(23 downto 0);
new_sample : OUT std_logic;
i2s_d_out : OUT std_logic;
i2s_d_in : IN std_logic
);
END COMPONENT;
signal audio_l : std_logic_vector(15 downto 0);
signal audio_r : std_logic_vector(15 downto 0);
signal codec_master_clk : std_logic;
signal i2c_scl : std_logic;
signal i2c_sda_i : std_logic;
signal i2c_sda_o : std_logic;
signal i2c_sda_t : std_logic;
signal i2s_mosi : std_logic;
signal i2s_miso : std_logic;
signal i2s_bclk : std_logic;
signal i2s_lr : std_logic;
begin
AC_ADR0 <= '1';
AC_ADR1 <= '1';
AC_GPIO0 <= i2s_MISO;
i2s_MOSI <= AC_GPIO1;
i2s_bclk <= AC_GPIO2;
i2s_lr <= AC_GPIO3;
AC_MCLK <= codec_master_clk;
AC_SCK <= i2c_scl;
i_i2s_sda_obuf : IOBUF
port map (
IO => AC_SDA, -- Buffer inout port (connect directly to top-level port)
O => i2c_sda_i, -- Buffer output (to fabric)
I => i2c_sda_o, -- Buffer input (from fabric)
T => i2c_sda_t -- 3-state enable input, high=input, low=output
);
Inst_i2c: i2c PORT MAP(
clk => CLK_48,
i2c_sda_i => i2c_sda_i,
i2c_sda_o => i2c_sda_o,
i2c_sda_t => i2c_sda_t,
i2c_scl => i2c_scl,
sw => sw,
active => active
);
i_ADAU1761_interface: ADAU1761_interface PORT MAP(
clk_48 => clk_48 ,
codec_master_clk => codec_master_clk
);
Inst_i2s_data_interface: i2s_data_interface PORT MAP(
clk => clk_48,
audio_l_out => line_in_l,
audio_r_out => line_in_r,
audio_l_in => hphone_l,
audio_r_in => hphone_r,
new_sample => new_sample,
i2s_bclk => i2s_bclk,
i2s_d_out => i2s_MISO,
i2s_d_in => i2s_MOSI,
i2s_lr => i2s_lr
);
end Behavioral; | lgpl-3.0 | 08c0836c92ad8121466c49ab4ad39d5e | 0.539717 | 2.862938 | false | false | false | false |
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