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SKravitsky/ECEC412 | IFIDRegister.vhd | 1 | 593 | library ieee;
use ieee.std_logic_1164.all;
entity IFIDRegister is
port(
clk: in std_logic;
AddressIn, InstructionIn: in std_logic_vector(31 downto 0);
AddressOut, InstructionOut: out std_logic_vector(31 downto 0)
);
end IFIDRegister;
architecture Structural of IFIDRegister is
signal Address, Instruction: std_logic_vector(31 downto 0) := X"00000000";
begin
AddressOut <= Address;
InstructionOut <= Instruction;
process(clk)
begin
if rising_edge(clk) then
Address <= AddressIn;
Instruction <= InstructionIn;
end if;
end process;
end Structural;
| apache-2.0 | 9aa428c4a4c7881fa64c005f0c16b29a | 0.716695 | 3.825806 | false | false | false | false |
ashtonchase/logic_analyzer | test/UART_tb.vhd | 1 | 5,436 | -------------------------------------------------------------------------------
-- Title : UART testbench
-- Project : fpga_logic_analyzer
-------------------------------------------------------------------------------
-- File : UART_tb.vhd
-- Created : 2016-02-22
-- Last update: 2016-03-28
-- Standard : VHDL'08
-------------------------------------------------------------------------------
-- Description: This is the UART testbench
-------------------------------------------------------------------------------
-- Copyright (c) 2016 Ashton Johnson, Paul Henny, Ian Swepston, David Hurt
-------------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-03-16 1.0 ian Created
-------------------------------------------------------------------------------
use WORK.all;
library ieee;
use IEEE.std_logic_1164.all;
entity UART_tb is
end entity;
library ieee;
use IEEE.std_logic_1164.all;
architecture test of UART_tb is
signal clk : std_logic := '1'; -- clock
signal rst : std_logic; -- reset logic
signal rx_get_more_data : std_logic; -- stop bit found for stream in
signal rx_data_ready : std_logic; -- stream out ready
signal rx : std_logic; -- receive line
signal data_in : std_logic_vector(7 downto 0) := (others => '0'); -- data to be transmitted
signal tx_data_ready : std_logic; -- stream out stop bit sent
signal tx_data_sent : std_logic; -- ready for rx
signal tx : std_logic := '1'; -- transmit line
signal data_out : std_logic_vector(7 downto 0) := (others => '0');
signal receive_data : std_logic_vector(7 downto 0);
signal baud_clock : std_logic := '1';
signal baud_counter : integer := 0;
constant baud_rate : integer := 10_000;
constant clock_freq : integer := 10_000_000;
constant baud_total : integer := (clock_freq/baud_rate)/2;
begin
u1 : entity work.uart_comms
generic map (clock_freq => clock_freq, baud_rate => baud_rate)
port map (
clk => clk,
rst => rst,
rx_get_more_data => rx_get_more_data,
rx_data_ready => rx_data_ready,
rx => rx,
data_in => data_in,
tx_data_ready => tx_data_ready,
tx_data_sent => tx_data_sent,
tx => tx,
data_out => data_out);
process (clk)
begin
clk <= not clk after 50 ns; -- 10 MHz clock
end process;
baud_clocking : process (clk)
begin
if(clk = '1' and clk'event) then
if (baud_counter < baud_total-1) then
baud_counter <= baud_counter + 1;
else
baud_counter <= 0;
baud_clock <= not baud_clock;
end if;
end if;
end process baud_clocking;
process
begin
rx <= '1';
rst <= '0';
wait for 10 ns;
receive_data <= "10011100";
wait until rising_edge(baud_clock);
rx_get_more_data <= '0';
wait until rising_edge(baud_clock);
rx <= '1'; -- nothing
wait until rising_edge(baud_clock);
rx <= '0'; -- stb
wait until rising_edge(baud_clock);
rx <= receive_data(0);
wait until rising_edge(baud_clock);
rx <= receive_data(1);
wait until rising_edge(baud_clock);
rx <= receive_data(2);
wait until rising_edge(baud_clock);
rx <= receive_data(3);
wait until rising_edge(baud_clock);
rx <= receive_data(4);
wait until rising_edge(baud_clock);
rx <= receive_data(5);
wait until rising_edge(baud_clock);
rx <= receive_data(6);
wait until rising_edge(baud_clock);
rx <= receive_data(7);
wait until rising_edge(baud_clock);
rx <= '1'; -- end
assert data_out=receive_data report "data out does not match UART data in" severity failure;
wait for 100 us;
wait until rising_edge(baud_clock);
rx_get_more_data <= '1';
end process;
process
begin
tx_data_ready <= '0';
wait until rising_edge(baud_clock);
wait until rising_edge(baud_clock);
wait until rising_edge(baud_clock);
wait until rising_edge(baud_clock);
data_in <= "10100111";
tx_data_ready <= '1';
wait for 100 ms;
end process;
end test;
| gpl-2.0 | 695396ed91956a606b800c36b30beaa7 | 0.510854 | 4.074963 | false | false | false | false |
SKravitsky/ECEC412 | MulticycleCPU.vhd | 1 | 6,125 | library ieee;
use ieee.std_logic_1164.all;
entity MulticycleCPU is
port(
clk: in std_logic;
CarryOut, Overflow: out std_logic
);
end MulticycleCPU;
architecture Behavioral of MulticycleCPU is
component PCMulticycle is
port(
clk, d: in std_logic;
AddressIn: in std_logic_vector(31 downto 0);
AddressOut: out std_logic_vector(31 downto 0)
);
end component;
component Add
port(
x: in std_logic_vector(31 downto 0);
y: in std_logic_vector(31 downto 0);
z: out std_logic_vector(31 downto 0)
);
end component;
component SignExtend
port(
x: in std_logic_vector(15 downto 0);
y: out std_logic_vector(31 downto 0)
);
end component;
component ShiftLeft2
port(
x: in std_logic_vector(31 downto 0);
y: out std_logic_vector(31 downto 0)
);
end component;
component ShiftLeft2Jump
port(
x: in std_logic_vector(25 downto 0);
y: in std_logic_vector(3 downto 0);
z: out std_logic_vector(31 downto 0)
);
end component;
component Mux5
port(
x, y: in std_logic_vector (4 downto 0);
sel: in std_logic;
z :out std_logic_vector(4 downto 0)
);
end component;
component Mux32
port(
x, y: in std_logic_vector (31 downto 0);
sel: in std_logic;
z: out std_logic_vector(31 downto 0)
);
end component;
component And2
port(
a, b: in std_logic;
y: out std_logic
);
end component;
component Or2 is
port(
a, b: in std_logic;
y: out std_logic
);
end component;
component ALU
generic(
n: natural := 32
);
port(
a, b: in std_logic_vector(n-1 downto 0);
Oper: in std_logic_vector(3 downto 0);
Result: buffer std_logic_vector(n-1 downto 0);
Zero, CarryOut, Overflow: buffer std_logic
);
end component;
component IR is
port (
x: in std_logic_vector(31 downto 0);
clk, IRWrite: in std_logic;
y: out std_logic_vector(31 downto 0)
);
end component;
component RegistersMulticycle is
port(
RR1, RR2, WR: in std_logic_vector(4 downto 0);
WD: in std_logic_vector(31 downto 0);
RegWrite: in std_logic;
RD1, RD2: out std_logic_vector(31 downto 0)
);
end component;
component RegA is
port(
x: in std_logic_vector(31 downto 0);
clk: in std_logic;
y: out std_logic_vector(31 downto 0)
);
end component;
component RegB is
port(
x: in std_logic_vector(31 downto 0);
clk: in std_logic;
y: out std_logic_vector(31 downto 0)
);
end component;
component InstructionMemory
port (
Address: in std_logic_vector(31 downto 0);
ReadData: out std_logic_vector(31 downto 0)
);
end component;
component MDR is
port (
x: in std_logic_vector(31 downto 0);
clk: in std_logic;
y: out std_logic_vector(31 downto 0)
);
end component;
component DataMemoryMulticycle is
port(
WriteData: in std_logic_vector(31 downto 0);
Address: in std_logic_vector(31 downto 0);
MemRead, MemWrite: in std_logic;
ReadData: out std_logic_vector(31 downto 0)
);
end component;
component ALUControl
port(
ALUOp: in std_logic_vector(1 downto 0);
Funct: in std_logic_vector(5 downto 0);
Operation: out std_logic_vector(3 downto 0)
);
end component;
component MUX3Way is
port(
w, x, y: in std_logic_vector(31 downto 0);
sel: in std_logic_vector(1 downto 0);
z:out std_logic_vector(31 downto 0)
);
end component;
component MUX4Way is
port(
v, w, x, y: in std_logic_vector(31 downto 0);
sel: in std_logic_vector(1 downto 0);
z:out std_logic_vector(31 downto 0)
);
end component;
component MulticycleControl is
port(
Opcode: in std_logic_vector(5 downto 0);
clk: in std_logic;
RegDst, RegWrite, ALUSrcA, IRWrite, MemtoReg, MemWrite, MemRead, IorD, PCWrite, PCWriteCond: out std_logic;
ALUSrcB, ALUOp, PCSource: out std_logic_vector(1 downto 0)
);
end component;
signal D, PCWriteCond, PCWrite, IorD, MemRead, MemWrite, MemtoReg, IRWrite, ALUSrcA, RegWrite, RegDst, Zero, W: std_logic := '0';
signal ALUOp, ALUSrcB, PCSource: std_logic_vector(1 downto 0) := "00";
signal Operation: std_logic_vector(3 downto 0) := "0000";
signal K: std_logic_vector(4 downto 0) := "00000";
signal C, E, F, G, H, I, J, L, M, N, P, Q, R, S, T, U, V, Instruction: std_logic_vector(31 downto 0) := X"00000000";
begin
PC_instance: PCMulticycle port map(clk, D, C, E);
Mux32_instance_0: Mux32 port map(E, F, IorD, G);
DataMemory_instance: DataMemoryMulticycle port map(H, G, MemRead, MemWrite, I);
IR_instance: IR port map(I, clk, IRWrite, Instruction);
Mux5_instance: Mux5 port map(Instruction(20 downto 16), Instruction(15 downto 11), RegDst, K);
MDR_instance: MDR port map(I, clk, J);
Mux32_instance_1: Mux32 port map(F, J, MemtoReg, L);
Registers_instance: RegistersMulticycle port map(Instruction(25 downto 21), Instruction(20 downto 16), K, L, RegWrite, M, N);
RegA_instance: RegA port map(M, clk, P);
RegA_instance_2: RegA port map(N, clk, H);
SignExtend_instance: SignExtend port map(Instruction(15 downto 0), Q);
ShiftLeft2_instance: ShiftLeft2 port map(Q, R);
MUX4Way_instance: MUX4Way port map(H, X"00000004", Q, R, ALUSrcB, T);
Mux32_instance_2: Mux32 port map(E, P, ALUSrcA, S);
ShiftLeft2Jump_instance: ShiftLeft2Jump port map(Instruction(25 downto 0), E(31 downto 28), V);
MUX3Way_instance: MUX3Way port map(U, F, V, PCSource, C);
And2_instance: And2 port map(Zero, PCWriteCond, W);
Or2_instance: Or2 port map(W, PCWrite, D);
ALU_instance: ALU port map(S, T, Operation, U, Zero, Carryout, Overflow);
ALUControl_instance: ALUControl port map(ALUOp, Instruction(5 downto 0), Operation);
ALUOut: RegB port map(U, clk, F);
Control_instance: MulticycleControl port map(Instruction(31 downto 26), clk, RegDst, RegWrite, ALUSrcA, IRWrite, MemtoReg, MemWrite, MemRead, IorD, PCWrite, PCWriteCond, ALUSrcB, ALUOp, PCSource);
end Behavioral;
| apache-2.0 | 8b3dcf809a2a054432fa4d239c3ad39b | 0.64849 | 3.365385 | false | false | false | false |
siavooshpayandehazad/NoC_Router | RTL/Chip_Designs/IMMORTAL_Chip_2017/network_files/Allocator_with_checkers_with_FI/allocator_credit_counter_logic_pseudo_checkers.vhd | 3 | 14,958 | --Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator_credit_counter_logic_pseudo_checkers is
port (
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
credit_counter_N_out, credit_counter_E_out, credit_counter_W_out, credit_counter_S_out, credit_counter_L_out : in std_logic_vector(1 downto 0);
valid_N, valid_E, valid_W, valid_S, valid_L: in std_logic; -- ?? Not sure yet ! grant or valid !
credit_counter_N_in, credit_counter_E_in, credit_counter_W_in, credit_counter_S_in, credit_counter_L_in : in std_logic_vector(1 downto 0);
-- Checker outputs
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_N_credit_counter_N_out_increment,
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change,
err_grant_N_credit_counter_N_out_decrement,
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change,
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_E_credit_counter_E_out_increment,
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change,
err_grant_E_credit_counter_E_out_decrement,
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change,
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_W_credit_counter_W_out_increment,
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change,
err_grant_W_credit_counter_W_out_decrement,
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change,
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_S_credit_counter_S_out_increment,
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change,
err_grant_S_credit_counter_S_out_decrement,
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change,
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal,
err_credit_in_L_credit_counter_L_out_increment,
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change,
err_grant_L_credit_counter_L_out_decrement,
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change,
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal : out std_logic
);
end allocator_credit_counter_logic_pseudo_checkers;
architecture behavior of allocator_credit_counter_logic_pseudo_checkers is
begin
-- The combionational part
----------------------------------------------------------------
-- Checkers for the process handling the credit counters
-- North credit counter
process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out)
begin
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '0';
if (credit_in_N = '1' and valid_N = '1' and credit_counter_N_in /= credit_counter_N_out) then
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '1';
end if;
end process;
process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out)
begin
err_credit_in_N_credit_counter_N_out_increment <= '0';
if (credit_in_N = '1' and valid_N = '0' and credit_counter_N_out < 3 and credit_counter_N_in /= credit_counter_N_out + 1) then
err_credit_in_N_credit_counter_N_out_increment <= '1';
end if;
end process;
process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out)
begin
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change <= '0';
if (credit_in_N = '1' and valid_N = '0' and credit_counter_N_out = 3 and credit_counter_N_in /= credit_counter_N_out) then
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change <= '1';
end if;
end process;
process (valid_N, credit_in_N, credit_counter_N_in, credit_counter_N_out)
begin
err_grant_N_credit_counter_N_out_decrement <= '0';
if (valid_N = '1' and credit_in_N = '0' and credit_counter_N_out > 0 and credit_counter_N_in /= credit_counter_N_out - 1) then
err_grant_N_credit_counter_N_out_decrement <= '1';
end if;
end process;
process (valid_N, credit_in_N, credit_counter_N_in, credit_counter_N_out)
begin
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change <= '0';
if (valid_N = '1' and credit_in_N = '0' and credit_counter_N_out = 0 and credit_counter_N_in /= credit_counter_N_out) then
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change <= '1';
end if;
end process;
process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out)
begin
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '0';
if (credit_in_N = '0' and valid_N = '0' and credit_counter_N_in /= credit_counter_N_out) then
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '1';
end if;
end process;
-- East credit counter
process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out)
begin
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '0';
if (credit_in_E = '1' and valid_E = '1' and credit_counter_E_in /= credit_counter_E_out) then
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '1';
end if;
end process;
process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out)
begin
err_credit_in_E_credit_counter_E_out_increment <= '0';
if (credit_in_E = '1' and valid_E = '0' and credit_counter_E_out < 3 and credit_counter_E_in /= credit_counter_E_out + 1) then
err_credit_in_E_credit_counter_E_out_increment <= '1';
end if;
end process;
process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out)
begin
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change <= '0';
if (credit_in_E = '1' and valid_E = '0' and credit_counter_E_out = 3 and credit_counter_E_in /= credit_counter_E_out) then
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change <= '1';
end if;
end process;
process (valid_E, credit_in_E, credit_counter_E_in, credit_counter_E_out)
begin
err_grant_E_credit_counter_E_out_decrement <= '0';
if (valid_E = '1' and credit_in_E = '0' and credit_counter_E_out > 0 and credit_counter_E_in /= credit_counter_E_out - 1) then
err_grant_E_credit_counter_E_out_decrement <= '1';
end if;
end process;
process (valid_E, credit_in_E, credit_counter_E_in, credit_counter_E_out)
begin
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change <= '0';
if (valid_E = '1' and credit_in_E = '0' and credit_counter_E_out = 0 and credit_counter_E_in /= credit_counter_E_out) then
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change <= '1';
end if;
end process;
process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out)
begin
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '0';
if (credit_in_E = '0' and valid_E = '0' and credit_counter_E_in /= credit_counter_E_out) then
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '1';
end if;
end process;
-- West credit counter
process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out)
begin
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '0';
if (credit_in_W = '1' and valid_W = '1' and credit_counter_W_in /= credit_counter_W_out) then
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '1';
end if;
end process;
process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out)
begin
err_credit_in_W_credit_counter_W_out_increment <= '0';
if (credit_in_W = '1' and valid_W = '0' and credit_counter_W_out < 3 and credit_counter_W_in /= credit_counter_W_out + 1) then
err_credit_in_W_credit_counter_W_out_increment <= '1';
end if;
end process;
process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out)
begin
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change <= '0';
if ( (credit_in_W = '1' and valid_W = '0' and credit_counter_W_out = 3) and credit_counter_W_in /= credit_counter_W_out) then
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change <= '1';
end if;
end process;
process (valid_W, credit_in_W, credit_counter_W_in, credit_counter_W_out)
begin
err_grant_W_credit_counter_W_out_decrement <= '0';
if (valid_W = '1' and credit_in_W = '0' and credit_counter_W_out > 0 and credit_counter_W_in /= credit_counter_W_out - 1) then
err_grant_W_credit_counter_W_out_decrement <= '1';
end if;
end process;
process (valid_W, credit_in_W, credit_counter_W_in, credit_counter_W_out)
begin
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change <= '0';
if ( valid_W = '1' and credit_in_W = '0' and credit_counter_W_out = 0 and credit_counter_W_in /= credit_counter_W_out) then
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change <= '1';
end if;
end process;
process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out)
begin
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '0';
if (credit_in_W = '0' and valid_W = '0' and credit_counter_W_in /= credit_counter_W_out) then
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '1';
end if;
end process;
-- South credit counter
process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out)
begin
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '0';
if (credit_in_S = '1' and valid_S = '1' and credit_counter_S_in /= credit_counter_S_out) then
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '1';
end if;
end process;
process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out)
begin
err_credit_in_S_credit_counter_S_out_increment <= '0';
if (credit_in_S = '1' and valid_S = '0' and credit_counter_S_out < 3 and credit_counter_S_in /= credit_counter_S_out + 1) then
err_credit_in_S_credit_counter_S_out_increment <= '1';
end if;
end process;
process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out)
begin
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change <= '0';
if ( credit_in_S = '1' and valid_S = '0' and credit_counter_S_out = 3 and credit_counter_S_in /= credit_counter_S_out) then
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change <= '1';
end if;
end process;
process (valid_S, credit_in_S, credit_counter_S_in, credit_counter_S_out)
begin
err_grant_S_credit_counter_S_out_decrement <= '0';
if (valid_S = '1' and credit_in_S = '0' and credit_counter_S_out > 0 and credit_counter_S_in /= credit_counter_S_out - 1) then
err_grant_S_credit_counter_S_out_decrement <= '1';
end if;
end process;
process (valid_S, credit_in_S, credit_counter_S_in, credit_counter_S_out)
begin
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change <= '0';
if (valid_S = '1' and credit_in_S = '0' and credit_counter_S_out = 0 and credit_counter_S_in /= credit_counter_S_out) then
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change <= '1';
end if;
end process;
process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out)
begin
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '0';
if (credit_in_S = '0' and valid_S = '0' and credit_counter_S_in /= credit_counter_S_out) then
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '1';
end if;
end process;
-- Local credit counter
process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out)
begin
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '0';
if (credit_in_L = '1' and valid_L = '1' and credit_counter_L_in /= credit_counter_L_out) then
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '1';
end if;
end process;
process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out)
begin
err_credit_in_L_credit_counter_L_out_increment <= '0';
if (credit_in_L = '1' and valid_L = '0' and credit_counter_L_out < 3 and credit_counter_L_in /= credit_counter_L_out + 1) then
err_credit_in_L_credit_counter_L_out_increment <= '1';
end if;
end process;
process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out)
begin
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change <= '0';
if (credit_in_L = '1' and valid_L = '0' and credit_counter_L_out = 3 and credit_counter_L_in /= credit_counter_L_out) then
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change <= '1';
end if;
end process;
process (valid_L, credit_in_L, credit_counter_L_in, credit_counter_L_out)
begin
err_grant_L_credit_counter_L_out_decrement <= '0';
if (valid_L = '1' and credit_in_L = '0' and credit_counter_L_out > 0 and credit_counter_L_in /= credit_counter_L_out - 1) then
err_grant_L_credit_counter_L_out_decrement <= '1';
end if;
end process;
process (valid_L, credit_in_L, credit_counter_L_in, credit_counter_L_out)
begin
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change <= '0';
if (valid_L = '1' and credit_in_L = '0' and credit_counter_L_out = 0 and credit_counter_L_in /= credit_counter_L_out) then
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change <= '1';
end if;
end process;
process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out)
begin
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '0';
if (credit_in_L = '0' and valid_L = '0' and credit_counter_L_in /= credit_counter_L_out) then
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '1';
end if;
end process;
END;
| gpl-3.0 | 9bfa0f775f7b71ea0f223e88388ba76f | 0.674288 | 2.665835 | false | false | false | false |
siavooshpayandehazad/NoC_Router | RTL/Processor_NI/reg_bank_xilinx.vhd | 3 | 9,852 | ---------------------------------------------------------------------
-- TITLE: Register Bank
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/2/01
-- FILENAME: reg_bank.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements a register bank with 32 registers that are 32-bits wide.
-- There are two read-ports and one write port.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
library UNISIM; --May need to uncomment for ModelSim
use UNISIM.vcomponents.all; --May need to uncomment for ModelSim
entity reg_bank is
port(clk : in std_logic;
reset_in : in std_logic;
pause : in std_logic;
interrupt_in : in std_logic; -- modified
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
rd_index : in std_logic_vector(5 downto 0);
reg_source_out : out std_logic_vector(31 downto 0);
reg_target_out : out std_logic_vector(31 downto 0);
reg_dest_new : in std_logic_vector(31 downto 0);
intr_enable : out std_logic);
end; --entity reg_bank
--------------------------------------------------------------------
-- The ram_block architecture attempts to use TWO dual-port memories.
-- Different FPGAs and ASICs need different implementations.
-- Choose one of the RAM implementations below.
-- I need feedback on this section!
--------------------------------------------------------------------
architecture ram_block of reg_bank is
signal intr_enable_reg : std_logic;
--controls access to dual-port memories
signal addr_read1, addr_read2 : std_logic_vector(4 downto 0);
signal addr_write : std_logic_vector(4 downto 0);
signal data_out1, data_out2 : std_logic_vector(31 downto 0);
signal write_enable : std_logic;
signal data_out1A, data_out1B : std_logic_vector(31 downto 0);
signal data_out2A, data_out2B : std_logic_vector(31 downto 0);
signal weA, weB : std_logic;
signal no_connect : std_logic_vector(127 downto 0);
begin
--------------------------------------
-- Implements register bank control --
--------------------------------------
reg_proc: process(clk, rs_index, rt_index, rd_index, reg_dest_new, intr_enable_reg,
data_out1, data_out2, reset_in, pause)
begin
--setup for first dual-port memory
if rs_index = "101110" then --reg_epc CP0 14
addr_read1 <= "00000";
else
addr_read1 <= rs_index(4 downto 0);
end if;
case rs_index is
when "000000" => reg_source_out <= ZERO;
when "101100" => reg_source_out <= ZERO(31 downto 1) & intr_enable_reg;
--interrupt vector address = 0x3c
when "111111" => reg_source_out <= ZERO(31 downto 8) & "00111100";
when others => reg_source_out <= data_out1;
end case;
--setup for second dual-port memory
addr_read2 <= rt_index(4 downto 0);
case rt_index is
when "000000" => reg_target_out <= ZERO;
when others => reg_target_out <= data_out2;
end case;
--setup write port for both dual-port memories
if rd_index /= "000000" and rd_index /= "101100" and pause = '0' then
write_enable <= '1';
else
write_enable <= '0';
end if;
if rd_index = "101110" then --reg_epc CP0 14
addr_write <= "00000";--"01110" --"11010"; -- Reg $26 to save PC when interrupt occurs, but is it safe ??
else
addr_write <= rd_index(4 downto 0);
end if;
if reset_in = '1' then
intr_enable_reg <= '0';
elsif rising_edge(clk) then
if rd_index = "101110" then --reg_epc CP0 14
intr_enable_reg <= '0'; --disable interrupts
elsif rd_index = "101100" then
intr_enable_reg <= reg_dest_new(0); -- Check the IEc (Interrupt Enable current) bit (bit 0 of the status register)
end if;
end if;
intr_enable <= intr_enable_reg;
end process;
-----------------------
-- Implements memory --
-----------------------
-- RAM16X1D: 16 x 1 positive edge write, asynchronous read dual-port
-- distributed RAM for all Xilinx FPGAs
-- From library UNISIM; use UNISIM.vcomponents.all;
reg_loop: for i in 0 to 31 generate
begin
--Read port 1 lower 16 registers
reg_bit1a : RAM16X1D
port map (
WCLK => clk, -- Port A write clock input
WE => weA, -- Port A write enable input
A0 => addr_write(0), -- Port A address[0] input bit
A1 => addr_write(1), -- Port A address[1] input bit
A2 => addr_write(2), -- Port A address[2] input bit
A3 => addr_write(3), -- Port A address[3] input bit
D => reg_dest_new(i), -- Port A 1-bit data input
DPRA0 => addr_read1(0), -- Port B address[0] input bit
DPRA1 => addr_read1(1), -- Port B address[1] input bit
DPRA2 => addr_read1(2), -- Port B address[2] input bit
DPRA3 => addr_read1(3), -- Port B address[3] input bit
DPO => data_out1A(i), -- Port B 1-bit data output
SPO => no_connect(i) -- Port A 1-bit data output
);
--Read port 1 upper 16 registers
reg_bit1b : RAM16X1D
port map (
WCLK => clk, -- Port A write clock input
WE => weB, -- Port A write enable input
A0 => addr_write(0), -- Port A address[0] input bit
A1 => addr_write(1), -- Port A address[1] input bit
A2 => addr_write(2), -- Port A address[2] input bit
A3 => addr_write(3), -- Port A address[3] input bit
D => reg_dest_new(i), -- Port A 1-bit data input
DPRA0 => addr_read1(0), -- Port B address[0] input bit
DPRA1 => addr_read1(1), -- Port B address[1] input bit
DPRA2 => addr_read1(2), -- Port B address[2] input bit
DPRA3 => addr_read1(3), -- Port B address[3] input bit
DPO => data_out1B(i), -- Port B 1-bit data output
SPO => no_connect(32+i) -- Port A 1-bit data output
);
--Read port 2 lower 16 registers
reg_bit2a : RAM16X1D
port map (
WCLK => clk, -- Port A write clock input
WE => weA, -- Port A write enable input
A0 => addr_write(0), -- Port A address[0] input bit
A1 => addr_write(1), -- Port A address[1] input bit
A2 => addr_write(2), -- Port A address[2] input bit
A3 => addr_write(3), -- Port A address[3] input bit
D => reg_dest_new(i), -- Port A 1-bit data input
DPRA0 => addr_read2(0), -- Port B address[0] input bit
DPRA1 => addr_read2(1), -- Port B address[1] input bit
DPRA2 => addr_read2(2), -- Port B address[2] input bit
DPRA3 => addr_read2(3), -- Port B address[3] input bit
DPO => data_out2A(i), -- Port B 1-bit data output
SPO => no_connect(64+i) -- Port A 1-bit data output
);
--Read port 2 upper 16 registers
reg_bit2b : RAM16X1D
port map (
WCLK => clk, -- Port A write clock input
WE => weB, -- Port A write enable input
A0 => addr_write(0), -- Port A address[0] input bit
A1 => addr_write(1), -- Port A address[1] input bit
A2 => addr_write(2), -- Port A address[2] input bit
A3 => addr_write(3), -- Port A address[3] input bit
D => reg_dest_new(i), -- Port A 1-bit data input
DPRA0 => addr_read2(0), -- Port B address[0] input bit
DPRA1 => addr_read2(1), -- Port B address[1] input bit
DPRA2 => addr_read2(2), -- Port B address[2] input bit
DPRA3 => addr_read2(3), -- Port B address[3] input bit
DPO => data_out2B(i), -- Port B 1-bit data output
SPO => no_connect(96+i) -- Port A 1-bit data output
);
end generate; --reg_loop
data_out1 <= data_out1A when addr_read1(4)='0' else data_out1B;
data_out2 <= data_out2A when addr_read2(4)='0' else data_out2B;
weA <= write_enable and not addr_write(4); --lower 16 registers
weB <= write_enable and addr_write(4); --upper 16 registers
end; --architecture ram_block
| gpl-3.0 | 08c176bda2de55b7170829545aaf8a49 | 0.478279 | 4.011401 | false | false | false | false |
siavooshpayandehazad/NoC_Router | RTL/Router/credit_based/RTL/New_SHMU_on_Node/With_checkers/arbiter_out_one_hot_with_checkers.vhd | 9 | 17,021 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
entity arbiter_out is
port (
reset: in std_logic;
clk: in std_logic;
X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y :in std_logic; -- From LBDR modules
credit: in std_logic_vector(1 downto 0);
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_req_X_N,
err_North_req_X_N,
err_North_credit_not_zero_req_X_N_grant_N,
err_North_credit_zero_or_not_req_X_N_not_grant_N,
err_East_req_X_E,
err_East_credit_not_zero_req_X_E_grant_E,
err_East_credit_zero_or_not_req_X_E_not_grant_E,
err_West_req_X_W,
err_West_credit_not_zero_req_X_W_grant_W,
err_West_credit_zero_or_not_req_X_W_not_grant_W,
err_South_req_X_S,
err_South_credit_not_zero_req_X_S_grant_S,
err_South_credit_zero_or_not_req_X_S_not_grant_S,
err_Local_req_X_L,
err_Local_credit_not_zero_req_X_L_grant_L,
err_Local_credit_zero_or_not_req_X_L_not_grant_L,
err_IDLE_req_X_E,
err_North_req_X_E,
err_East_req_X_W,
err_West_req_X_S,
err_South_req_X_L,
err_Local_req_X_N,
err_IDLE_req_X_W,
err_North_req_X_W,
err_East_req_X_S,
err_West_req_X_L,
err_South_req_X_N,
err_Local_req_X_E,
err_IDLE_req_X_S,
err_North_req_X_S,
err_East_req_X_L,
err_West_req_X_N,
err_South_req_X_E,
err_Local_req_X_W,
err_IDLE_req_X_L,
err_North_req_X_L,
err_East_req_X_N,
err_West_req_X_E,
err_South_req_X_W,
err_Local_req_X_S,
err_state_in_onehot,
err_no_request_grants,
err_request_IDLE_state,
err_request_IDLE_not_Grants,
err_state_North_Invalid_Grant,
err_state_East_Invalid_Grant,
err_state_West_Invalid_Grant,
err_state_South_Invalid_Grant,
err_state_Local_Invalid_Grant,
err_Grants_onehot_or_all_zero : out std_logic
);
end;
architecture behavior of arbiter_out is
component Arbiter_out_one_hot_pseudo_checkers is
port ( credit: in std_logic_vector(1 downto 0);
req_X_N, req_X_E, req_X_W, req_X_S, req_X_L :in std_logic; -- From LBDR modules
state: in std_logic_vector (5 downto 0); -- 6 states for Arbiter_out's FSM
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : in std_logic; -- Grants given to LBDR requests (encoded as one-hot)
state_in: in std_logic_vector (5 downto 0); -- 6 states for Arbiter's FSM
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_req_X_N,
err_North_req_X_N,
err_North_credit_not_zero_req_X_N_grant_N,
err_North_credit_zero_or_not_req_X_N_not_grant_N,
err_East_req_X_E,
err_East_credit_not_zero_req_X_E_grant_E,
err_East_credit_zero_or_not_req_X_E_not_grant_E,
err_West_req_X_W,
err_West_credit_not_zero_req_X_W_grant_W,
err_West_credit_zero_or_not_req_X_W_not_grant_W,
err_South_req_X_S,
err_South_credit_not_zero_req_X_S_grant_S,
err_South_credit_zero_or_not_req_X_S_not_grant_S,
err_Local_req_X_L,
err_Local_credit_not_zero_req_X_L_grant_L,
err_Local_credit_zero_or_not_req_X_L_not_grant_L,
err_IDLE_req_X_E,
err_North_req_X_E,
err_East_req_X_W,
err_West_req_X_S,
err_South_req_X_L,
err_Local_req_X_N,
err_IDLE_req_X_W,
err_North_req_X_W,
err_East_req_X_S,
err_West_req_X_L,
err_South_req_X_N,
err_Local_req_X_E,
err_IDLE_req_X_S,
err_North_req_X_S,
err_East_req_X_L,
err_West_req_X_N,
err_South_req_X_E,
err_Local_req_X_W,
err_IDLE_req_X_L,
err_North_req_X_L,
err_East_req_X_N,
err_West_req_X_E,
err_South_req_X_W,
err_Local_req_X_S,
err_state_in_onehot,
err_no_request_grants,
err_request_IDLE_state,
err_request_IDLE_not_Grants,
err_state_North_Invalid_Grant,
err_state_East_Invalid_Grant,
err_state_West_Invalid_Grant,
err_state_South_Invalid_Grant,
err_state_Local_Invalid_Grant,
err_Grants_onehot_or_all_zero : out std_logic
);
end component;
--TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
CONSTANT IDLE: std_logic_vector (5 downto 0) := "000001";
CONSTANT Local: std_logic_vector (5 downto 0) := "000010";
CONSTANT North: std_logic_vector (5 downto 0) := "000100";
CONSTANT East: std_logic_vector (5 downto 0) := "001000";
CONSTANT West: std_logic_vector (5 downto 0) := "010000";
CONSTANT South: std_logic_vector (5 downto 0) := "100000";
SIGNAL state, state_in : std_logic_vector (5 downto 0) := IDLE; -- : STATE_TYPE := IDLE;
SIGNAL grant_Y_N_sig, grant_Y_E_sig, grant_Y_W_sig, grant_Y_S_sig, grant_Y_L_sig : std_logic;
begin
-- We did this because of the checker outputs!
grant_Y_N <= grant_Y_N_sig;
grant_Y_E <= grant_Y_E_sig;
grant_Y_W <= grant_Y_W_sig;
grant_Y_S <= grant_Y_S_sig;
grant_Y_L <= grant_Y_L_sig;
-- Sequential part
process (clk, reset)begin
if reset = '0' then
state <= IDLE;
elsif clk'event and clk ='1' then
state <= state_in;
end if;
end process;
-- Arbiter_out checkers module instantiation
ARBITER_OUT_ONE_HOT_CHECKERS: Arbiter_out_one_hot_pseudo_checkers
port map (
credit => credit,
req_X_N => X_N_Y,
req_X_E => X_E_Y,
req_X_W => X_W_Y,
req_X_S => X_S_Y,
req_X_L => X_L_Y,
state => state,
grant_Y_N => grant_Y_N_sig,
grant_Y_E => grant_Y_E_sig,
grant_Y_W => grant_Y_W_sig,
grant_Y_S => grant_Y_S_sig,
grant_Y_L => grant_Y_L_sig,
state_in => state_in,
-- Checker outputs
err_Requests_state_in_state_not_equal => err_Requests_state_in_state_not_equal,
err_IDLE_req_X_N => err_IDLE_req_X_N,
err_North_req_X_N => err_North_req_X_N,
err_North_credit_not_zero_req_X_N_grant_N => err_North_credit_not_zero_req_X_N_grant_N,
err_North_credit_zero_or_not_req_X_N_not_grant_N => err_North_credit_zero_or_not_req_X_N_not_grant_N,
err_East_req_X_E => err_East_req_X_E,
err_East_credit_not_zero_req_X_E_grant_E => err_East_credit_not_zero_req_X_E_grant_E,
err_East_credit_zero_or_not_req_X_E_not_grant_E => err_East_credit_zero_or_not_req_X_E_not_grant_E,
err_West_req_X_W => err_West_req_X_W,
err_West_credit_not_zero_req_X_W_grant_W => err_West_credit_not_zero_req_X_W_grant_W,
err_West_credit_zero_or_not_req_X_W_not_grant_W => err_West_credit_zero_or_not_req_X_W_not_grant_W,
err_South_req_X_S => err_South_req_X_S,
err_South_credit_not_zero_req_X_S_grant_S => err_South_credit_not_zero_req_X_S_grant_S,
err_South_credit_zero_or_not_req_X_S_not_grant_S => err_South_credit_zero_or_not_req_X_S_not_grant_S,
err_Local_req_X_L => err_Local_req_X_L,
err_Local_credit_not_zero_req_X_L_grant_L => err_Local_credit_not_zero_req_X_L_grant_L,
err_Local_credit_zero_or_not_req_X_L_not_grant_L => err_Local_credit_zero_or_not_req_X_L_not_grant_L,
err_IDLE_req_X_E => err_IDLE_req_X_E,
err_North_req_X_E => err_North_req_X_E,
err_East_req_X_W => err_East_req_X_W,
err_West_req_X_S => err_West_req_X_S,
err_South_req_X_L => err_South_req_X_L,
err_Local_req_X_N => err_Local_req_X_N,
err_IDLE_req_X_W => err_IDLE_req_X_W,
err_North_req_X_W => err_North_req_X_W,
err_East_req_X_S => err_East_req_X_S,
err_West_req_X_L => err_West_req_X_L,
err_South_req_X_N => err_South_req_X_N,
err_Local_req_X_E => err_Local_req_X_E,
err_IDLE_req_X_S => err_IDLE_req_X_S,
err_North_req_X_S => err_North_req_X_S,
err_East_req_X_L => err_East_req_X_L,
err_West_req_X_N => err_West_req_X_N,
err_South_req_X_E => err_South_req_X_E,
err_Local_req_X_W => err_Local_req_X_W,
err_IDLE_req_X_L => err_IDLE_req_X_L,
err_North_req_X_L => err_North_req_X_L,
err_East_req_X_N => err_East_req_X_N,
err_West_req_X_E => err_West_req_X_E,
err_South_req_X_W => err_South_req_X_W,
err_Local_req_X_S => err_Local_req_X_S,
err_state_in_onehot => err_state_in_onehot,
err_no_request_grants => err_no_request_grants,
err_request_IDLE_state => err_request_IDLE_state,
err_request_IDLE_not_Grants => err_request_IDLE_not_Grants,
err_state_North_Invalid_Grant => err_state_North_Invalid_Grant,
err_state_East_Invalid_Grant => err_state_East_Invalid_Grant,
err_state_West_Invalid_Grant => err_state_West_Invalid_Grant,
err_state_South_Invalid_Grant => err_state_South_Invalid_Grant,
err_state_Local_Invalid_Grant => err_state_Local_Invalid_Grant,
err_Grants_onehot_or_all_zero => err_Grants_onehot_or_all_zero
);
-- anything below here is pure combinational
process(state, X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y, credit)
begin
grant_Y_N_sig <= '0';
grant_Y_E_sig <= '0';
grant_Y_W_sig <= '0';
grant_Y_S_sig <= '0';
grant_Y_L_sig <= '0';
case state is
when IDLE =>
if X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when North =>
if credit /= "00" and X_N_Y = '1' then
grant_Y_N_sig <= '1';
end if;
if X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when East =>
if credit /= "00" and X_E_Y = '1' then
grant_Y_E_sig <= '1';
end if;
if X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
else
state_in <= IDLE;
end if;
when West =>
if credit /= "00" and X_W_Y = '1' then
grant_Y_W_sig <= '1';
end if;
if X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
else
state_in <= IDLE;
end if;
when South =>
if credit /= "00" and X_S_Y = '1' then
grant_Y_S_sig <= '1';
end if;
if X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
else
state_in <= IDLE;
end if;
when others =>
if credit /= "00" and X_L_Y = '1' then
grant_Y_L_sig <= '1';
end if;
if X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
else
state_in <= IDLE;
end if;
end case;
end process;
end;
| gpl-3.0 | 2f387c6a28edac6f622b689524607c83 | 0.394454 | 3.729404 | false | false | false | false |
siavooshpayandehazad/NoC_Router | RTL/Chip_Designs/IMMORTAL_Chip_2017/network_files/FIFO_one_hot_credit_based_packet_drop_classifier_support_with_checkers_with_FI/FIFO_one_hot_credit_based_packet_drop_classifier_support_with_checkers_with_FI.vhd | 3 | 49,371 | --Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.component_pack.all;
entity FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
fault_info, health_info: out std_logic;
-- fault injector shift register with serial input signals
TCK: in std_logic;
SE: in std_logic; -- shift enable
UE: in std_logic; -- update enable
SI: in std_logic; -- serial Input
SO: out std_logic; -- serial output
-- Checker outputs
-- Functional checkers
err_empty_full, err_empty_read_en, err_full_write_en, err_state_in_onehot,
err_read_pointer_in_onehot, err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer, err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full,
err_read_pointer_increment, err_read_pointer_not_increment, err_write_en, err_not_write_en, err_not_write_en1,
err_not_write_en2, err_read_en_mismatch, err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit, err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in, err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info, err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit, err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit, err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in, err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal, err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in : out std_logic
);
end FIFO_credit_based;
architecture behavior of FIFO_credit_based is
----------------------------------------
-- Signals related to fault injection --
----------------------------------------
-- Total: 8 bits
signal FI_add_sta: std_logic_vector(7 downto 0); -- 6 bits for fault injection location address (ceil of log2(44) = 6)
-- 2 bits for type of fault (SA0 or SA1)
signal non_faulty_signals: std_logic_vector (43 downto 0); -- 44 bits for internal- and output-related signals (non-faulty)
signal faulty_signals: std_logic_vector(43 downto 0); -- 44 bits for internal- and output-related signals (with single stuck-at fault injected in one of them)
----------------------------------------
----------------------------------------
signal read_pointer, read_pointer_in, write_pointer, write_pointer_in: std_logic_vector(3 downto 0);
signal full, empty: std_logic;
signal read_en, write_en: std_logic;
signal FIFO_MEM_1, FIFO_MEM_1_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_2, FIFO_MEM_2_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_3, FIFO_MEM_3_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_4, FIFO_MEM_4_in : std_logic_vector(DATA_WIDTH-1 downto 0);
-- Packet Dropping FSM states encoded as one-hot (because of checkers for one-bit error detection)
CONSTANT Idle: std_logic_vector (4 downto 0) := "00001";
CONSTANT Header_flit: std_logic_vector (4 downto 0) := "00010";
CONSTANT Body_flit: std_logic_vector (4 downto 0) := "00100";
CONSTANT Tail_flit: std_logic_vector (4 downto 0) := "01000";
CONSTANT Packet_drop: std_logic_vector (4 downto 0) := "10000";
signal fault_info_in, fault_info_out: std_logic;
signal faulty_packet_in, faulty_packet_out: std_logic;
signal xor_all, fault_out: std_logic;
signal state_out, state_in : std_logic_vector(4 downto 0); -- : state_type;
signal fake_credit, credit_in, write_fake_flit: std_logic;
signal fake_credit_counter, fake_credit_counter_in: std_logic_vector(1 downto 0);
-- Signal(s) needed for FIFO control part checkers
signal fault_info_sig, health_info_sig : std_logic;
-- Signal(s) used for creating the chain of injected fault locations (Control Part of FIFO only)
-- Total: 44 bits ??!!
-- FIFO's control part internal-related signals
signal read_pointer_faulty, read_pointer_in_faulty : std_logic_vector(3 downto 0);
signal write_pointer_faulty, write_pointer_in_faulty : std_logic_vector(3 downto 0);
signal full_faulty, read_en_faulty, write_en_faulty : std_logic;
signal fake_credit_faulty : std_logic;
signal fake_credit_counter_faulty, fake_credit_counter_in_faulty : std_logic_vector(1 downto 0);
signal state_out_faulty, state_in_faulty : std_logic_vector (4 downto 0);
signal fault_info_out_faulty, fault_info_in_faulty : std_logic;
signal faulty_packet_out_faulty, faulty_packet_in_faulty : std_logic;
--signal flit_type_faulty : std_logic; -- ??!! (Actually, flit_type is an alias, showing RX from bits 31 downto 29, maybe we can define it as a signal for injection) (Not sure yet !)
signal fault_out_faulty, write_fake_flit_faulty : std_logic;
-- FIFO's control part output-related signals
signal credit_in_faulty : std_logic; -- ??!! (Actually, it is credit_in, which is the previous value of credit_out in FIFO)
signal empty_faulty : std_logic;
signal fault_info_sig_faulty : std_logic; -- ??!! (which goes to the fault_info output of FIFO)
signal health_info_sig_faulty : std_logic; -- ??!! (which goes to the health_info output of FIFO)
begin
--------------------------------------------------------------------------------------------
-- block diagram of the FIFO!
--------------------------------------------------------------------------------------------
-- circular buffer structure
-- <--- WriteP
-- ---------------------------------
-- | 3 | 2 | 1 | 0 |
-- ---------------------------------
-- <--- readP
--------------------------------------------------------------------------------------------
-- Packet drop state machine
-- +---+ No +---+ No
-- | | Flit | | Flit
-- | v | v
-- healthy +--------+ +--------+
-- +---header-->| | | |-------------------+
-- | +->| Header |---Healthy body-->| Body |------------+ |
-- | | +--------+ +--------+ | |
-- | | | ^ | Healthy | ^ Healthy |
-- | | | | | body | | Tail |
-- | | | | | +---+ | |
-- | | | | | v |
-- +--------+ | | | | +--------+ |
-- No +-->| | | | | +-----------------Healthy Tail------>| | |
-- Flit| | IDLE | | | | | Tail |--)--+
-- +---| | | | +-----------Healthy Header--------------| | | |
-- +--------+ | | +--------+ | |
-- ^ | ^ | Faulty No Faulty | |
-- | | | | Flit Flit Flit | |
-- | | | | +------------+ +---+ +---+ | |
-- | | | + --Healthy------+ | | | | | | |
-- | | | header | v | v | v | |
-- | | | +------------------+ | |
-- | | +----Healthy Tail-----| Packet | | |
-- | +-------Faulty Flit----->| Drop |<-----------------------+ |
-- | +------------------+ |
-- +-------------------------------------------------No Flit------------------+
--
------------------------------------------------------------------------------------------------
-------------------------------------
---- Related to fault injection -----
-------------------------------------
-- Total: 44 bits
-- Still not sure whether to include flit_type or not ??!!
-- credit_in is actually the previous value of credit_out in FIFO !!
-- for fault_info and health_info outputs, not sure whether to include them or the signals with _sig suffix in their names ??!!
non_faulty_signals <= read_pointer & read_pointer_in & write_pointer & write_pointer_in & full & read_en &
write_en & fake_credit & fake_credit_counter & fake_credit_counter_in & state_out &
state_in & fault_info_out & fault_info_in & faulty_packet_out & faulty_packet_in &
fault_out & write_fake_flit & credit_in & empty & fault_info_sig & health_info_sig;
-- Fault injector module instantiation
FI: fault_injector generic map(DATA_WIDTH => 44, ADDRESS_WIDTH => 6)
port map (data_in=> non_faulty_signals , address => FI_add_sta(7 downto 2), sta_0=> FI_add_sta(1), sta_1=> FI_add_sta(0), data_out=> faulty_signals
);
-- Extracting faulty values for internal- and output-related signals
-- Total: 44 bits
read_pointer_faulty <= faulty_signals (43 downto 40);
read_pointer_in_faulty <= faulty_signals (39 downto 36);
write_pointer_faulty <= faulty_signals (35 downto 32);
write_pointer_in_faulty <= faulty_signals (31 downto 28);
full_faulty <= faulty_signals (27);
read_en_faulty <= faulty_signals (26);
write_en_faulty <= faulty_signals (25);
fake_credit_faulty <= faulty_signals (24);
fake_credit_counter_faulty <= faulty_signals (23 downto 22);
fake_credit_counter_in_faulty <= faulty_signals (21 downto 20);
state_out_faulty <= faulty_signals (19 downto 15);
state_in_faulty <= faulty_signals (14 downto 10);
fault_info_out_faulty <= faulty_signals (9);
fault_info_in_faulty <= faulty_signals (8);
faulty_packet_out_faulty <= faulty_signals (7);
faulty_packet_in_faulty <= faulty_signals (6);
fault_out_faulty <= faulty_signals (5);
write_fake_flit_faulty <= faulty_signals (4);
credit_in_faulty <= faulty_signals (3);
empty_faulty <= faulty_signals (2);
fault_info_sig_faulty <= faulty_signals (1);
health_info_sig_faulty <= faulty_signals (0);
-- Total: 8 bits
-- We only use the shift register with serial in for :
-- (1) feeding the values of address width
-- (the address where the single stuck-at fault should be injected)
-- (2) feeding the values of the type of fault (stuck-at-1 (SA1) or stuck-at-0 (SA0) or no fault)
SR: shift_register_serial_in generic map(REG_WIDTH => 8)
port map ( TCK=> TCK, reset=>reset, SE=> SE, UE=> UE, SI=> SI, SO=> SO, data_out_parallel=> FI_add_sta
);
-------------------------------------
-------------------------------------
-- FIFO control part with packet drop and fault classifier support checkers instantiation
FIFO_control_part_checkers:
FIFO_credit_based_control_part_checkers
port map (
valid_in => valid_in,
read_en_N => read_en_N, read_en_E => read_en_E, read_en_W => read_en_W, read_en_S => read_en_S, read_en_L => read_en_L,
read_pointer => read_pointer_faulty, read_pointer_in => read_pointer_in_faulty,
write_pointer => write_pointer_faulty, write_pointer_in => write_pointer_in_faulty,
credit_out => credit_in_faulty, -- correct ?! (credit_in in FIFO is actually the previous value of credit_out, going to the input of a register)
empty_out => empty_faulty, full_out => full_faulty, read_en_out => read_en_faulty, write_en_out => write_en_faulty,
fake_credit => fake_credit_faulty, fake_credit_counter => fake_credit_counter_faulty,
fake_credit_counter_in => fake_credit_counter_in_faulty, state_out => state_out_faulty, state_in => state_in_faulty,
fault_info => fault_info_sig_faulty, -- connected to signal
fault_info_out => fault_info_out_faulty, fault_info_in => fault_info_in_faulty,
health_info => health_info_sig_faulty, -- connected to signal
faulty_packet_out => faulty_packet_out_faulty, faulty_packet_in => faulty_packet_in_faulty,
flit_type => RX(DATA_WIDTH-1 downto DATA_WIDTH-3), -- Behrad: Not sure about this yet ?!
fault_out => fault_out_faulty, write_fake_flit => write_fake_flit_faulty,
-- Functional checkers
err_empty_full => err_empty_full, err_empty_read_en => err_empty_read_en, err_full_write_en => err_full_write_en,
err_state_in_onehot => err_state_in_onehot, err_read_pointer_in_onehot => err_read_pointer_in_onehot,
err_write_pointer_in_onehot => err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer => err_write_en_write_pointer, err_not_write_en_write_pointer => err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => err_read_pointer_write_pointer_full,
err_read_pointer_increment => err_read_pointer_increment, err_read_pointer_not_increment => err_read_pointer_not_increment,
err_write_en => err_write_en, err_not_write_en => err_not_write_en, err_not_write_en1 => err_not_write_en1,
err_not_write_en2 => err_not_write_en2, err_read_en_mismatch => err_read_en_mismatch,
err_read_en_mismatch1 => err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment => err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change => err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change => err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out => err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit => err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in => err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit => err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop => err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in => err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in => err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info => err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit => err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in => err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in => err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit => err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit => err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info => err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in => err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in => err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info => err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info => err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit => err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit => err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit => err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle => err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in => err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit => err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit => err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal => err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in
);
-- Becuase of checkers we did this
fault_info <= fault_info_sig; -- Not sure yet ?!
health_info <= health_info_sig; -- Not sure yet ?!
-- Sequential part
process (clk, reset)begin
if reset = '0' then
read_pointer <= "0001";
write_pointer <= "0001";
FIFO_MEM_1 <= (others=>'0'); FIFO_MEM_2 <= (others=>'0'); FIFO_MEM_3 <= (others=>'0'); FIFO_MEM_4 <= (others=>'0');
fake_credit_counter <= (others=>'0');
faulty_packet_out <= '0';
credit_out <= '0';
state_out <= Idle;
fault_info_out <= '0';
elsif clk'event and clk = '1' then
write_pointer <= write_pointer_in;
read_pointer <= read_pointer_in;
state_out <= state_in;
faulty_packet_out <= faulty_packet_in;
credit_out <= credit_in;
fake_credit_counter <= fake_credit_counter_in;
if write_en = '1' then
--write into the memory
FIFO_MEM_1 <= FIFO_MEM_1_in; FIFO_MEM_2 <= FIFO_MEM_2_in; FIFO_MEM_3 <= FIFO_MEM_3_in; FIFO_MEM_4 <= FIFO_MEM_4_in;
end if;
fault_info_out <= fault_info_in;
end if;
end process;
-- Anything below here is pure combinational
-- combinatorial part
fault_info_sig <= fault_info_out;
process(fake_credit, read_en, fake_credit_counter) begin
fake_credit_counter_in <= fake_credit_counter;
credit_in <= '0';
if fake_credit = '1' and read_en = '1' then
fake_credit_counter_in <= fake_credit_counter + 1 ;
end if;
if fake_credit = '1' or read_en ='1' then
credit_in <= '1';
end if;
if fake_credit = '0' and read_en = '0' and fake_credit_counter > 0 then
fake_credit_counter_in <= fake_credit_counter - 1 ;
credit_in <= '1';
end if;
end process;
process(valid_in, RX) begin
xor_all <= '0';
if valid_in = '1' then
xor_all <= XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
end if;
end process;
process(valid_in, RX, xor_all)begin
fault_out <= '0';
if valid_in = '1' and xor_all /= RX(0) then
fault_out <= '1';
end if;
end process;
process(RX, faulty_packet_out, fault_out, write_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4, state_out, valid_in) begin
-- this is the default value of the memory!
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
end case ;
--some defaults
fault_info_in <= '0';
health_info_sig <= '0';
fake_credit <= '0';
state_in <= state_out;
faulty_packet_in <= faulty_packet_out;
write_fake_flit <= '0';
case(state_out) is
when Idle =>
if fault_out = '0' then
if valid_in = '1' then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
else
fake_credit <= '1';
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
when Header_flit =>
if valid_in = '1' then
if fault_out = '0' then
if RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010" then
state_in <= Body_flit;
elsif RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100" then
state_in <= Tail_flit;
else
-- we should not be here!
state_in <= state_out;
end if;
else -- fault_out = '1'
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail;
end case ;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= state_out;
end if;
when Body_flit =>
if valid_in = '1' then
if fault_out = '0' then
if RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010" then
state_in <= state_out;
elsif RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100" then
state_in <= Tail_flit;
health_info_sig <= '1';
else
-- we should not be here!
state_in <= state_out;
end if;
else -- fault_out = '1'
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail;
end case ;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= state_out;
end if;
when Tail_flit =>
if valid_in = '1' then
if fault_out = '0' then
if RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001" then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
else -- fault_out = '1'
fake_credit <= '1';
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= Idle;
end if;
when Packet_drop =>
state_in <= state_out;
if faulty_packet_out = '1' then
report "FIFO dropping packet at" & time'image(now) &"!" severity note;
if valid_in = '1' and RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001" and fault_out = '0' then
faulty_packet_in <= '0';
state_in <= Header_flit;
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
end case ;
elsif valid_in = '1' and RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100" and fault_out = '0' then
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
faulty_packet_in <= '0';
state_in <= Idle;
fake_credit <= '1';
else -- fault_out might have been '1'
if valid_in = '1' and RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001" then
fault_info_in <= '1';
end if;
if valid_in = '1' then
fake_credit <= '1';
end if;
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= state_out;
end if;
end if;
when others => state_in <= state_out;
end case;
end process;
process(read_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin
case( read_pointer ) is
when "0001" => Data_out <= FIFO_MEM_1;
when "0010" => Data_out <= FIFO_MEM_2;
when "0100" => Data_out <= FIFO_MEM_3;
when others => Data_out <= FIFO_MEM_4;
end case ;
end process;
read_en <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty;
empty_out <= empty;
process(write_en, write_pointer)begin
write_pointer_in <= write_pointer;
if write_en = '1' then
write_pointer_in <= write_pointer(2 downto 0)&write_pointer(3);
end if;
end process;
process(read_en, empty, read_pointer)begin
read_pointer_in <= read_pointer;
if (read_en = '1' and empty = '0') then
read_pointer_in <= read_pointer(2 downto 0)&read_pointer(3);
end if;
end process;
process(full, valid_in, write_fake_flit, faulty_packet_out, fault_out) begin
write_en <= '0';
if valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full ='0' then
write_en <= '1';
end if;
end process;
process(write_pointer, read_pointer) begin
empty <= '0';
full <= '0';
if read_pointer = write_pointer then
empty <= '1';
end if;
-- if write_pointer = read_pointer>>1 then
if write_pointer = read_pointer(0)&read_pointer(3 downto 1) then
full <= '1';
end if;
end process;
end;
| gpl-3.0 | d53e6205105a19857e91170b70ff7a74 | 0.578781 | 3.285705 | false | false | false | false |
AndyMcC0/UVVM_All | uvvm_util/src/string_methods_pkg.vhd | 1 | 43,951 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use work.types_pkg.all;
use work.adaptations_pkg.all;
package string_methods_pkg is
-- Need a low level "alert" in the form of a simple assertion (as string handling may also fail)
procedure bitvis_assert(
val : boolean;
severeness : severity_level;
msg : string;
scope : string
);
function justify(
val : string;
justified : side;
width : natural;
format_spaces : t_format_spaces;
truncate : t_truncate_string
) return string;
-- DEPRECATED.
-- Function will be removed in future versions of UVVM-Util
function justify(
val : string;
width : natural := 0;
justified : side := RIGHT;
format: t_format_string := AS_IS -- No defaults on 4 first param - to avoid ambiguity with std.textio
) return string;
function pos_of_leftmost(
target : character;
vector : string;
result_if_not_found : natural := 1
) return natural;
function pos_of_rightmost(
target : character;
vector : string;
result_if_not_found : natural := 1
) return natural;
function pos_of_leftmost_non_zero(
vector : string;
result_if_not_found : natural := 1
) return natural;
function pos_of_rightmost_non_whitespace(
vector : string;
result_if_not_found : natural := 1
) return natural;
function valid_length( -- of string excluding trailing NULs
vector : string
) return natural;
function get_string_between_delimiters(
val : string;
delim_left : character;
delim_right: character;
start_from : SIDE; -- search from left or right (Only RIGHT implemented so far)
occurrence : positive := 1 -- stop on N'th occurrence of delimeter pair. Default first occurrence
) return string;
function get_procedure_name_from_instance_name(
val : string
) return string;
function get_process_name_from_instance_name(
val : string
) return string;
function get_entity_name_from_instance_name(
val : string
) return string;
function return_string_if_true(
val : string;
return_val : boolean
) return string;
function return_string1_if_true_otherwise_string2(
val1 : string;
val2 : string;
return_val : boolean
) return string;
function to_upper(
val : string
) return string;
function fill_string(
val : character;
width : natural
) return string;
function pad_string(
val : string;
char : character;
width : natural;
side : side := LEFT
) return string;
function replace_backslash_n_with_lf(
source : string
) return string;
function remove_initial_chars(
source : string;
num : natural
) return string;
function wrap_lines(
constant text_string : string;
constant alignment_pos1 : natural; -- Line position of first aligned character in line 1
constant alignment_pos2 : natural; -- Line position of first aligned character in line 2, etc...
constant line_width : natural
) return string;
procedure wrap_lines(
variable text_lines : inout line;
constant alignment_pos1 : natural; -- Line position prior to first aligned character (incl. Prefix)
constant alignment_pos2 : natural;
constant line_width : natural
);
procedure prefix_lines(
variable text_lines : inout line;
constant prefix : string := C_LOG_PREFIX
);
function replace(
val : string;
target_char : character;
exchange_char : character
) return string;
procedure replace(
variable text_line : inout line;
target_char : character;
exchange_char : character
);
--========================================================
-- Handle missing overloads from 'standard_additions'
--========================================================
function to_string(
val : boolean;
width : natural;
justified : side;
format_spaces : t_format_spaces;
truncate : t_truncate_string := DISALLOW_TRUNCATE
) return string;
function to_string(
val : integer;
width : natural;
justified : side;
format_spaces : t_format_spaces;
truncate : t_truncate_string := DISALLOW_TRUNCATE
) return string;
-- This function has been deprecated and will be removed in the next major release
-- DEPRECATED
function to_string(
val : boolean;
width : natural;
justified : side := right;
format: t_format_string := AS_IS
) return string;
-- This function has been deprecated and will be removed in the next major release
-- DEPRECATED
function to_string(
val : integer;
width : natural;
justified : side := right;
format : t_format_string := AS_IS
) return string;
function to_string(
val : std_logic_vector;
radix : t_radix;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string;
function to_string(
val : unsigned;
radix : t_radix;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string;
function to_string(
val : signed;
radix : t_radix;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string;
function to_string(
val : t_byte_array;
radix : t_radix := HEX_BIN_IF_INVALID;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string;
--========================================================
-- Handle types defined at lower levels
--========================================================
function to_string(
val : t_alert_level;
width : natural;
justified : side := right
) return string;
function to_string(
val : t_msg_id;
width : natural;
justified : side := right
) return string;
function to_string(
val : t_attention;
width : natural;
justified : side := right
) return string;
procedure to_string(
val : t_alert_attention_counters;
order : t_order := FINAL
);
function ascii_to_char(
ascii_pos : integer range 0 to 255;
ascii_allow : t_ascii_allow := ALLOW_ALL
) return character;
function char_to_ascii(
char : character
) return integer;
-- return string with only valid ascii characters
function to_string(
val : string
) return string;
function add_msg_delimiter(
msg : string
) return string;
end package string_methods_pkg;
package body string_methods_pkg is
-- Need a low level "alert" in the form of a simple assertion (as string handling may also fail)
procedure bitvis_assert(
val : boolean;
severeness : severity_level;
msg : string;
scope : string
) is
begin
assert val
report LF & C_LOG_PREFIX & " *** " & to_string(severeness) & "*** caused by Bitvis Util > string handling > "
& scope & LF & C_LOG_PREFIX & " " & add_msg_delimiter(msg) & LF
severity severeness;
end;
function to_upper(
val : string
) return string is
variable v_result : string (val'range) := val;
variable char : character;
begin
for i in val'range loop
-- NOTE: Illegal characters are allowed and will pass through (check Mentor's std_developers_kit)
if ( v_result(i) >= 'a' and v_result(i) <= 'z') then
v_result(i) := character'val( character'pos(v_result(i)) - character'pos('a') + character'pos('A') );
end if;
end loop;
return v_result;
end to_upper;
function fill_string(
val : character;
width : natural
) return string is
variable v_result : string (1 to maximum(1, width));
begin
if (width = 0) then
return "";
else
for i in 1 to width loop
v_result(i) := val;
end loop;
end if;
return v_result;
end fill_string;
function pad_string(
val : string;
char : character;
width : natural;
side : side := LEFT
) return string is
variable v_result : string (1 to maximum(1, width));
begin
if (width = 0) then
return "";
elsif (width <= val'length) then
return val(1 to width);
else
v_result := (others => char);
if side = LEFT then
v_result(1 to val'length) := val;
else
v_result(v_result'length-val'length+1 to v_result'length) := val;
end if;
end if;
return v_result;
end pad_string;
-- This procedure has been deprecated, and will be removed in the near future.
function justify(
val : string;
width : natural := 0;
justified : side := RIGHT;
format : t_format_string := AS_IS -- No defaults on 4 first param - to avoid ambiguity with std.textio
) return string is
constant val_length : natural := val'length;
variable result : string(1 to width) := (others => ' ');
begin
-- return val if width is too small
if val_length >= width then
if (format = TRUNCATE) then
return val(1 to width);
else
return val;
end if;
end if;
if justified = left then
result(1 to val_length) := val;
elsif justified = right then
result(width - val_length + 1 to width) := val;
end if;
return result;
end function;
function justify(
val : string;
justified : side;
width : natural;
format_spaces : t_format_spaces;
truncate : t_truncate_string
) return string is
variable v_val_length : natural := val'length;
variable v_formatted_val : string (1 to val'length);
variable v_num_leading_space : natural := 1;
variable v_result : string(1 to width) := (others => ' ');
begin
-- Remove leading space if format_spaces is SKIP_LEADING_SPACE
if format_spaces = SKIP_LEADING_SPACE then
-- Find how many leading spaces there are
while( (val(v_num_leading_space) = ' ') and (v_num_leading_space < v_val_length)) loop
v_num_leading_space := v_num_leading_space + 1;
end loop;
-- Remove leading space if any
v_formatted_val := remove_initial_chars(val,v_num_leading_space);
v_val_length := v_formatted_val'length;
else
v_formatted_val := val;
end if;
-- Truncate and return if the string is wider that allowed
if v_val_length >= width then
if (truncate = ALLOW_TRUNCATE) then
return v_formatted_val(1 to width);
else
return v_formatted_val;
end if;
end if;
-- Justify if string is within the width specifications
if justified = left then
v_result(1 to v_val_length) := v_formatted_val;
elsif justified = right then
v_result(width - v_val_length + 1 to width) := v_formatted_val;
end if;
return v_result;
end function;
function pos_of_leftmost(
target : character;
vector : string;
result_if_not_found : natural := 1
) return natural is
alias a_vector : string(1 to vector'length) is vector;
begin
bitvis_assert(vector'length > 0, FAILURE, "String input is empty", "pos_of_leftmost()");
bitvis_assert(vector'ascending, FAILURE, "Only implemented for string(N to M)", "pos_of_leftmost()");
for i in a_vector'left to a_vector'right loop
if (a_vector(i) = target) then
return i;
end if;
end loop;
return result_if_not_found;
end;
function pos_of_rightmost(
target : character;
vector : string;
result_if_not_found : natural := 1
) return natural is
alias a_vector : string(1 to vector'length) is vector;
begin
bitvis_assert(vector'length > 0, FAILURE, "String input is empty", "pos_of_rightmost()");
bitvis_assert(vector'ascending, FAILURE, "Only implemented for string(N to M)", "pos_of_rightmost()");
for i in a_vector'right downto a_vector'left loop
if (a_vector(i) = target) then
return i;
end if;
end loop;
return result_if_not_found;
end;
function pos_of_leftmost_non_zero(
vector : string;
result_if_not_found : natural := 1
) return natural is
alias a_vector : string(1 to vector'length) is vector;
begin
bitvis_assert(vector'length > 0, FAILURE, "String input is empty", "pos_of_leftmost_non_zero()");
for i in a_vector'left to a_vector'right loop
if (a_vector(i) /= '0' and a_vector(i) /= ' ') then
return i;
end if;
end loop;
return result_if_not_found;
end;
function pos_of_rightmost_non_whitespace(
vector : string;
result_if_not_found : natural := 1
) return natural is
alias a_vector : string(1 to vector'length) is vector;
begin
bitvis_assert(vector'length > 0, FAILURE, "String input is empty", "pos_of_rightmost_non_whitespace()");
for i in a_vector'right downto a_vector'left loop
if a_vector(i) /= ' ' then
return i;
end if;
end loop;
return result_if_not_found;
end;
function valid_length( -- of string excluding trailing NULs
vector : string
) return natural is
begin
return pos_of_leftmost(NUL, vector, vector'length);
end;
function string_contains_char(
val : string;
char : character
) return boolean is
alias a_val : string(1 to val'length) is val;
begin
if (val'length = 0) then
return false;
else
for i in val'left to val'right loop
if (val(i) = char) then
return true;
end if;
end loop;
-- falls through only if not found
return false;
end if;
end;
-- get_*_name
-- Note: for sub-programs the following is given: library:package:procedure:object
-- Note: for design hierachy the following is given: complete hierarchy from sim-object down to process object
-- e.g. 'sbi_tb:i_test_harness:i2_sbi_vvc:p_constructor:v_msg'
-- Attribute instance_name also gives [procedure signature] or @entity-name(architecture name)
function get_string_between_delimiters(
val : string;
delim_left : character;
delim_right: character;
start_from : SIDE; -- search from left or right (Only RIGHT implemented so far)
occurrence : positive := 1 -- stop on N'th occurrence of delimeter pair. Default first occurrence
) return string is
variable v_left : natural := 0;
variable v_right : natural := 0;
variable v_start : natural := val'length;
variable v_occurrence : natural := 0;
alias a_val : string(1 to val'length) is val;
begin
bitvis_assert(a_val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_string_between_delimiters()");
bitvis_assert(start_from = RIGHT, FAILURE, "Only search from RIGHT is implemented so far", "get_string_between_delimiters()");
loop
-- RIGHT
v_left := 0; -- default
v_right := pos_of_rightmost(delim_right, a_val(1 to v_start), 0);
if v_right > 0 then -- i.e. found
L1: for i in v_right-1 downto 1 loop -- searching backwards for delimeter
if (a_val(i) = delim_left) then
v_left := i;
v_start := i; -- Previous end delimeter could also be a start delimeter for next section
v_occurrence := v_occurrence + 1;
exit L1;
end if;
end loop; -- searching backwards
end if;
if v_right = 0 or v_left = 0 then
return ""; -- No delimeter pair found, and none can be found in the rest (with chars in between)
end if;
if v_occurrence = occurrence then
-- Match
if (v_right - v_left) < 2 then
return ""; -- no chars in between delimeters
else
return a_val(v_left+1 to v_right-1);
end if;
end if;
if v_start < 3 then
return ""; -- No delimeter pair found, and none can be found in the rest (with chars in between)
end if;
end loop; -- Will continue until match or not found
end;
-- ':sbi_tb(func):i_test_harness@test_harness(struct):i2_sbi_vvc@sbi_vvc(struct):p_constructor:instance'
-- ':sbi_tb:i_test_harness:i1_sbi_vvc:p_constructor:instance'
-- - Process name: Search for 2nd last param in path name
-- - Entity name: Search for 3nd last param in path name
--':bitvis_vip_sbi:sbi_bfm_pkg:sbi_write[unsigned,std_logic_vector,string,std_logic,std_logic,unsigned,
-- std_logic,std_logic,std_logic,std_logic_vector,time,string,t_msg_id_panel,t_sbi_config]:msg'
-- - Procedure name: Search for 2nd last param in path name and remove all inside []
function get_procedure_name_from_instance_name(
val : string
) return string is
variable v_line : line;
variable v_msg_line : line;
begin
bitvis_assert(val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_procedure_name_from_instance_name()");
write(v_line, get_string_between_delimiters(val, ':', '[', RIGHT));
if (string_contains_char(val, '@')) then
write(v_msg_line, string'("Must be called with <sub-program object>'instance_name"));
else
write(v_msg_line, string'(" "));
end if;
bitvis_assert(v_line'length > 0, ERROR, "No procedure name found. " & v_msg_line.all, "get_procedure_name_from_instance_name()");
return v_line.all;
end;
function get_process_name_from_instance_name(
val : string
) return string is
variable v_line : line;
variable v_msg_line : line;
begin
bitvis_assert(val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_process_name_from_instance_name()");
write(v_line, get_string_between_delimiters(val, ':', ':', RIGHT));
if (string_contains_char(val, '[')) then
write(v_msg_line, string'("Must be called with <process-local object>'instance_name"));
else
write(v_msg_line, string'(" "));
end if;
bitvis_assert(v_line'length > 0, ERROR, "No process name found", "get_process_name_from_instance_name()");
return v_line.all;
end;
function get_entity_name_from_instance_name(
val : string
) return string is
variable v_line : line;
variable v_msg_line : line;
begin
bitvis_assert(val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_entity_name_from_instance_name()");
if string_contains_char(val, '@') then -- for path with instantiations
write(v_line, get_string_between_delimiters(val, '@', '(', RIGHT));
else -- for path with only a single entity
write(v_line, get_string_between_delimiters(val, ':', '(', RIGHT));
end if;
if (string_contains_char(val, '[')) then
write(v_msg_line, string'("Must be called with <Entity/arch-local object>'instance_name"));
else
write(v_msg_line, string'(" "));
end if;
bitvis_assert(v_line'length > 0, ERROR, "No entity name found", "get_entity_name_from_instance_name()");
return v_line.all;
end;
function adjust_leading_0(
val : string;
format : t_format_zeros := SKIP_LEADING_0
) return string is
alias a_val : string(1 to val'length) is val;
constant leftmost_non_zero : natural := pos_of_leftmost_non_zero(a_val, 1);
begin
if val'length <= 1 then
return val;
end if;
if format = SKIP_LEADING_0 then
return a_val(leftmost_non_zero to val'length);
else
return a_val;
end if;
end function;
function return_string_if_true(
val : string;
return_val : boolean
) return string is
begin
if return_val then
return val;
else
return "";
end if;
end function;
function return_string1_if_true_otherwise_string2(
val1 : string;
val2 : string;
return_val : boolean
) return string is
begin
if return_val then
return val1;
else
return val2;
end if;
end function;
function replace_backslash_n_with_lf(
source : string
) return string is
variable v_source_idx : natural := 0;
variable v_dest_idx : natural := 0;
variable v_dest : string(1 to source'length);
begin
if source'length = 0 then
return "";
else
if C_USE_BACKSLASH_N_AS_LF then
loop
v_source_idx := v_source_idx + 1;
v_dest_idx := v_dest_idx + 1;
if (v_source_idx < source'length) then
if (source(v_source_idx to v_source_idx +1) /= "\n") then
v_dest(v_dest_idx) := source(v_source_idx);
else
v_dest(v_dest_idx) := LF;
v_source_idx := v_source_idx + 1; -- Additional increment as two chars (\n) are consumed
if (v_source_idx = source'length) then
exit;
end if;
end if;
else
-- Final character in string
v_dest(v_dest_idx) := source(v_source_idx);
exit;
end if;
end loop;
else
v_dest := source;
v_dest_idx := source'length;
end if;
return v_dest(1 to v_dest_idx);
end if;
end;
function remove_initial_chars(
source : string;
num : natural
) return string is
begin
if source'length <= num then
return "";
else
return source(1 + num to source'right);
end if;
end;
function wrap_lines(
constant text_string : string;
constant alignment_pos1 : natural; -- Line position of first aligned character in line 1
constant alignment_pos2 : natural; -- Line position of first aligned character in line 2
constant line_width : natural
) return string is
variable v_text_lines : line;
variable v_result : string(1 to 2 * text_string'length + alignment_pos1 + 100); -- Margin for aligns and LF insertions
variable v_result_width : natural;
begin
write(v_text_lines, text_string);
wrap_lines(v_text_lines, alignment_pos1, alignment_pos2, line_width);
v_result_width := v_text_lines'length;
bitvis_assert(v_result_width <= v_result'length, FAILURE,
" String is too long after wrapping. Increase v_result string size.", "wrap_lines()");
v_result(1 to v_result_width) := v_text_lines.all;
deallocate(v_text_lines);
return v_result(1 to v_result_width);
end;
procedure wrap_lines(
variable text_lines : inout line;
constant alignment_pos1 : natural; -- Line position of first aligned character in line 1
constant alignment_pos2 : natural; -- Line position of first aligned character in line 2
constant line_width : natural
) is
variable v_string : string(1 to text_lines'length) := text_lines.all;
variable v_string_width : natural := text_lines'length;
variable v_line_no : natural := 0;
variable v_last_string_wrap : natural := 0;
variable v_min_string_wrap : natural;
variable v_max_string_wrap : natural;
begin
deallocate(text_lines); -- empty the line prior to filling it up again
l_line: loop -- For every tekstline found in text_lines
v_line_no := v_line_no + 1;
-- Find position to wrap in v_string
if (v_line_no = 1) then
v_min_string_wrap := 1; -- Minimum 1 character of input line
v_max_string_wrap := minimum(line_width - alignment_pos1 + 1, v_string_width);
write(text_lines, fill_string(' ', alignment_pos1 - 1));
else
v_min_string_wrap := v_last_string_wrap + 1; -- Minimum 1 character further into the inpit line
v_max_string_wrap := minimum(v_last_string_wrap + (line_width - alignment_pos2 + 1), v_string_width);
write(text_lines, fill_string(' ', alignment_pos2 - 1));
end if;
-- 1. First handle any potential explicit line feed in the current maximum text line
-- Search forward for potential LF
for i in (v_last_string_wrap + 1) to minimum(v_max_string_wrap + 1, v_string_width) loop
if (character(v_string(i)) = LF) then
write(text_lines, v_string((v_last_string_wrap + 1) to i)); -- LF now terminates this part
v_last_string_wrap := i;
next l_line; -- next line
end if;
end loop;
-- 2. Then check if remaining text fits into a single text line
if (v_string_width <= v_max_string_wrap) then
-- No (more) wrapping required
write(text_lines, v_string((v_last_string_wrap + 1) to v_string_width));
exit; -- No more lines
end if;
-- 3. Search for blanks from char after max msg width and downwards (in the left direction)
for i in v_max_string_wrap + 1 downto (v_last_string_wrap + 1) loop
if (character(v_string(i)) = ' ') then
write(text_lines, v_string((v_last_string_wrap + 1) to i-1)); -- Exchange last blank with LF
v_last_string_wrap := i;
if (i = v_string_width ) then
exit l_line;
end if;
-- Skip any potential extra blanks in the string
for j in (i+1) to v_string_width loop
if (v_string(j) = ' ') then
v_last_string_wrap := j;
if (j = v_string_width ) then
exit l_line;
end if;
else
write(text_lines, LF); -- Exchange last blanks with LF, provided not at the end of the string
exit;
end if;
end loop;
next l_line; -- next line
end if;
end loop;
-- 4. At this point no LF or blank is found in the searched section of the string.
-- Hence just break the string - and continue.
write(text_lines, v_string((v_last_string_wrap + 1) to v_max_string_wrap) & LF); -- Added LF termination
v_last_string_wrap := v_max_string_wrap;
end loop;
end;
procedure prefix_lines(
variable text_lines : inout line;
constant prefix : string := C_LOG_PREFIX
) is
variable v_string : string(1 to text_lines'length) := text_lines.all;
variable v_string_width : natural := text_lines'length;
constant prefix_width : natural := prefix'length;
variable v_last_string_wrap : natural := 0;
variable i : natural := 0; -- for indexing v_string
begin
deallocate(text_lines); -- empty the line prior to filling it up again
l_line : loop
-- 1. Write prefix
write(text_lines, prefix);
-- 2. Write rest of text line (or rest of input line if no LF)
l_char: loop
i := i + 1;
if (i < v_string_width) then
if (character(v_string(i)) = LF) then
write(text_lines, v_string((v_last_string_wrap + 1) to i));
v_last_string_wrap := i;
exit l_char;
end if;
else
-- 3. Reached end of string. Hence just write the rest.
write(text_lines, v_string((v_last_string_wrap + 1) to v_string_width));
-- But ensure new line with prefix if ending with LF
if (v_string(i) = LF) then
write(text_lines, prefix);
end if;
exit l_char;
end if;
end loop;
if (i = v_string_width) then
exit;
end if;
end loop;
end;
function replace(
val : string;
target_char : character;
exchange_char : character
) return string is
variable result : string(1 to val'length) := val;
begin
for i in val'range loop
if val(i) = target_char then
result(i) := exchange_char;
end if;
end loop;
return result;
end;
procedure replace(
variable text_line : inout line;
target_char : character;
exchange_char : character
) is
variable v_string : string(1 to text_line'length) := text_line.all;
variable v_string_width : natural := text_line'length;
variable i : natural := 0; -- for indexing v_string
begin
if v_string_width > 0 then
deallocate(text_line); -- empty the line prior to filling it up again
-- 1. Loop through string and replace characters
l_char: loop
i := i + 1;
if (i < v_string_width) then
if (character(v_string(i)) = target_char) then
v_string(i) := exchange_char;
end if;
else
-- 2. Reached end of string. Hence just write the new string.
write(text_line, v_string);
exit l_char;
end if;
end loop;
end if;
end;
--========================================================
-- Handle missing overloads from 'standard_additions' + advanced overloads
--========================================================
function to_string(
val : boolean;
width : natural;
justified : side;
format_spaces : t_format_spaces;
truncate : t_truncate_string := DISALLOW_TRUNCATE
) return string is
begin
return justify(to_string(val), justified, width, format_spaces, truncate);
end;
function to_string(
val : integer;
width : natural;
justified : side;
format_spaces : t_format_spaces;
truncate : t_truncate_string := DISALLOW_TRUNCATE
) return string is
begin
return justify(to_string(val), justified, width, format_spaces, truncate);
end;
-- This function has been deprecated and will be removed in the next major release
function to_string(
val : boolean;
width : natural;
justified : side := right;
format : t_format_string := AS_IS
) return string is
begin
return justify(to_string(val), width, justified, format);
end;
-- This function has been deprecated and will be removed in the next major release
function to_string(
val : integer;
width : natural;
justified : side := right;
format : t_format_string := AS_IS
) return string is
begin
return justify(to_string(val), width, justified, format);
end;
function to_string(
val : std_logic_vector;
radix : t_radix;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string is
variable v_line : line;
alias a_val : std_logic_vector(val'length - 1 downto 0) is val;
variable v_result : string(1 to 10 + 2 * val'length); --
variable v_width : natural;
variable v_use_end_char : boolean := false;
begin
if val'length = 0 then
-- Value length is zero,
-- return empty string.
return "";
end if;
if radix = BIN then
if prefix = INCL_RADIX then
write(v_line, string'("b"""));
v_use_end_char := true;
end if;
write(v_line, adjust_leading_0(to_string(val), format));
elsif radix = HEX then
if prefix = INCL_RADIX then
write(v_line, string'("x"""));
v_use_end_char := true;
end if;
write(v_line, adjust_leading_0(to_hstring(val), format));
elsif radix = DEC then
if prefix = INCL_RADIX then
write(v_line, string'("d"""));
v_use_end_char := true;
end if;
-- Assuming that val is not signed
if (val'length > 31) then
write(v_line, to_hstring(val) & " (too wide to be converted to integer)" );
else
write(v_line, adjust_leading_0(to_string(to_integer(unsigned(val))), format));
end if;
elsif radix = HEX_BIN_IF_INVALID then
if prefix = INCL_RADIX then
write(v_line, string'("x"""));
end if;
if is_x(val) then
write(v_line, adjust_leading_0(to_hstring(val), format));
if prefix = INCL_RADIX then
write(v_line, string'("""")); -- terminate hex value
end if;
write(v_line, string'(" (b"""));
write(v_line, adjust_leading_0(to_string(val), format));
write(v_line, string'(""""));
write(v_line, string'(")"));
else
write(v_line, adjust_leading_0(to_hstring(val), format));
if prefix = INCL_RADIX then
write(v_line, string'(""""));
end if;
end if;
end if;
if v_use_end_char then
write(v_line, string'(""""));
end if;
v_width := v_line'length;
v_result(1 to v_width) := v_line.all;
deallocate(v_line);
return v_result(1 to v_width);
end;
function to_string(
val : unsigned;
radix : t_radix;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string is
begin
return to_string(std_logic_vector(val), radix, format, prefix);
end;
function to_string(
val : signed;
radix : t_radix;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string is
variable v_line : line;
variable v_result : string(1 to 10 + 2 * val'length); --
variable v_width : natural;
variable v_use_end_char : boolean := false;
begin
-- Support negative numbers by _not_ using the slv overload when converting to decimal
if radix = DEC then
if val'length = 0 then
-- Value length is zero,
-- return empty string.
return "";
end if;
if prefix = INCL_RADIX then
write(v_line, string'("d"""));
v_use_end_char := true;
end if;
if (val'length > 32) then
write(v_line, to_string(std_logic_vector(val),radix, format, prefix) & " (too wide to be converted to integer)" );
else
write(v_line, adjust_leading_0(to_string(to_integer(signed(val))), format));
end if;
if v_use_end_char then
write(v_line, string'(""""));
end if;
v_width := v_line'length;
v_result(1 to v_width) := v_line.all;
deallocate(v_line);
return v_result(1 to v_width);
else -- No decimal convertion: May be treated as slv, so use the slv overload
return to_string(std_logic_vector(val), radix, format, prefix);
end if;
end;
function to_string(
val : t_byte_array;
radix : t_radix := HEX_BIN_IF_INVALID;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string is
variable v_line : line;
variable v_result : string(1 to 2 + -- parentheses
2*(val'length - 1) + -- commas
26 * val'length); -- 26 is max length of returned value from slv to_string()
variable v_width : natural;
begin
if val'length = 0 then
-- Value length is zero,
-- return empty string.
return "";
elsif val'length = 1 then
-- Value length is 1
-- Return the single value it contains
return to_string(val(val'low), radix, format, prefix);
else
-- Value length more than 1
-- Comma-separate all array members and return
write(v_line, string'("("));
for i in val'range loop
write(v_line, to_string(val(i), radix, format, prefix));
if i < val'right and val'ascending then
write(v_line, string'(", "));
elsif i > val'right and not val'ascending then
write(v_line, string'(", "));
end if;
end loop;
write(v_line, string'(")"));
v_width := v_line'length;
v_result(1 to v_width) := v_line.all;
deallocate(v_line);
return v_result(1 to v_width);
end if;
end;
--========================================================
-- Handle types defined at lower levels
--========================================================
function to_string(
val : t_alert_level;
width : natural;
justified : side := right
) return string is
constant inner_string : string := t_alert_level'image(val);
begin
return to_upper(justify(inner_string, justified, width));
end function;
function to_string(
val : t_msg_id;
width : natural;
justified : side := right
) return string is
constant inner_string : string := t_msg_id'image(val);
begin
return to_upper(justify(inner_string, justified, width));
end function;
function to_string(
val : t_attention;
width : natural;
justified : side := right
) return string is
begin
return to_upper(justify(t_attention'image(val), justified, width));
end;
-- function to_string(
-- dummy : t_void
-- ) return string is
-- begin
-- return "VOID";
-- end function;
procedure to_string(
val : t_alert_attention_counters;
order : t_order := FINAL
) is
variable v_line : line;
variable v_line_copy : line;
variable v_status_failed : boolean := true;
variable v_mismatch : boolean := false;
variable v_header : string(1 to 42);
constant prefix : string := C_LOG_PREFIX & " ";
begin
if order = INTERMEDIATE then
v_header := "*** INTERMEDIATE SUMMARY OF ALL ALERTS ***";
else -- order=FINAL
v_header := "*** FINAL SUMMARY OF ALL ALERTS *** ";
end if;
write(v_line,
LF &
fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
v_header & LF &
fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
" REGARDED EXPECTED IGNORED Comment?" & LF);
for i in NOTE to t_alert_level'right loop
write(v_line, " " & to_upper(to_string(i, 13, LEFT)) & ": "); -- Severity
for j in t_attention'left to t_attention'right loop
write(v_line, to_string(integer'(val(i)(j)), 6, RIGHT, KEEP_LEADING_SPACE) & " ");
end loop;
if (val(i)(REGARD) = val(i)(EXPECT)) then
write(v_line, " ok " & LF);
else
write(v_line, " *** " & to_string(i,0) & " *** " & LF);
if (i > MANUAL_CHECK) then
if (val(i)(REGARD) < val(i)(EXPECT)) then
v_mismatch := true;
else
v_status_failed := false;
end if;
end if;
end if;
end loop;
write(v_line, fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF);
-- Print a conclusion when called from the FINAL part of the test sequencer
-- but not when called from in the middle of the test sequence (order=INTERMEDIATE)
if order = FINAL then
if not v_status_failed then
write(v_line, ">> Simulation FAILED, with unexpected serious alert(s)" & LF);
elsif v_mismatch then
write(v_line, ">> Simulation FAILED: Mismatch between counted and expected serious alerts" & LF);
else
write(v_line, ">> Simulation SUCCESS: No mismatch between counted and expected serious alerts" & LF);
end if;
write(v_line, fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF & LF);
end if;
wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-prefix'length);
prefix_lines(v_line, prefix);
-- Write the info string to the target file
write (v_line_copy, v_line.all & lf); -- copy line
writeline(OUTPUT, v_line);
writeline(LOG_FILE, v_line_copy);
end;
-- Convert from ASCII to character
-- Inputs:
-- ascii_pos (integer) : ASCII number input
-- ascii_allow (t_ascii_allow) : Decide what to do with invisible control characters:
-- - If ascii_allow = ALLOW_ALL (default) : return the character for any ascii_pos
-- - If ascii_allow = ALLOW_PRINTABLE_ONLY : return the character only if it is printable
function ascii_to_char(
ascii_pos : integer range 0 to 255; -- Supporting Extended ASCII
ascii_allow : t_ascii_allow := ALLOW_ALL
) return character is
variable v_printable : boolean := true;
begin
if ascii_pos < 32 or -- NUL, SOH, STX etc
(ascii_pos >= 128 and ascii_pos < 160) then -- C128 to C159
v_printable := false;
end if;
if ascii_allow = ALLOW_ALL or
(ascii_allow = ALLOW_PRINTABLE_ONLY and v_printable) then
return character'val(ascii_pos);
else
return ' '; -- Must return something when invisible control signals
end if;
end;
-- Convert from character to ASCII integer
function char_to_ascii(
char : character
) return integer is
begin
return character'pos(char);
end;
-- return string with only valid ascii characters
function to_string(
val : string
) return string is
variable v_new_string : string(1 to val'length);
variable v_char_idx : natural := 0;
variable v_ascii_pos : natural;
begin
for i in val'range loop
v_ascii_pos := character'pos(val(i));
if (v_ascii_pos < 32 and v_ascii_pos /= 10) or -- NUL, SOH, STX etc, LF(10) is not removed.
(v_ascii_pos >= 128 and v_ascii_pos < 160) then -- C128 to C159
-- illegal char
null;
else
-- legal char
v_char_idx := v_char_idx + 1;
v_new_string(v_char_idx) := val(i);
end if;
end loop;
if v_char_idx = 0 then
return "";
else
return v_new_string(1 to v_char_idx);
end if;
end;
function add_msg_delimiter(
msg : string
) return string is
begin
if msg'length /= 0 then
if valid_length(msg) /= 1 then
if msg(1) = C_MSG_DELIMITER then
return msg;
else
return C_MSG_DELIMITER & msg & C_MSG_DELIMITER;
end if;
end if;
end if;
return "";
end;
end package body string_methods_pkg;
| mit | 70263117c09b5a023b99916e0eb4e5fc | 0.582672 | 3.812874 | false | false | false | false |
hacklabmikkeli/knobs-galore | lookup.vhdl | 2 | 3,498 | --
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
entity lookup is
generic (TABLE: ctl_lut_t
);
port (EN: in std_logic
;CLK_EVEN: in std_logic
;CLK_ODD: in std_logic
;X: in ctl_signal
;Y: in ctl_signal
;Z: out ctl_signal
);
end entity;
architecture lookup_impl of lookup is
attribute ram_style: string;
signal rom: ctl_lut_t := TABLE;
attribute ram_style of rom: signal is "block";
signal s1_left_ref: ctl_signal := (others => '0');
signal s1_right_ref: ctl_signal := (others => '0');
signal s1_y: ctl_signal := (others => '0');
signal s2_left_mult: unsigned(12 downto 0) := (others => '0');
signal s2_right_mult: unsigned(12 downto 0) := (others => '0');
signal s3_z_buf: ctl_signal := (others => '0');
begin
process(CLK_EVEN)
variable x_ix: integer range 0 to 255;
variable y_ix: integer range 0 to 15;
begin
if EN = '1' and rising_edge(CLK_EVEN) then
x_ix := to_integer(X);
y_ix := to_integer(Y(7 downto 4));
s1_left_ref <= rom(x_ix, y_ix);
end if;
end process;
process(CLK_EVEN)
variable y_plusone: unsigned(4 downto 0);
variable x_ix: integer range 0 to 255;
variable y_ix: integer range 1 to 16;
begin
if EN = '1' and rising_edge(CLK_EVEN) then
y_plusone := ("0" & Y(7 downto 4)) + 1;
x_ix := to_integer(X);
y_ix := to_integer(y_plusone);
s1_right_ref <= rom(x_ix, y_ix);
end if;
end process;
process(CLK_EVEN)
begin
if EN = '1' and rising_edge(CLK_EVEN) then
s1_y <= Y;
end if;
end process;
process(CLK_ODD)
variable s1_y_recip: unsigned(4 downto 0);
begin
if EN = '1' and rising_edge(CLK_ODD) then
s1_y_recip := "10000" - s1_y(3 downto 0);
s2_left_mult <= s1_y_recip * s1_left_ref;
end if;
end process;
process(CLK_ODD)
variable s1_y_fact: unsigned(4 downto 0);
begin
if EN = '1' and rising_edge(CLK_ODD) then
s1_y_fact := "0" & s1_y(3 downto 0);
s2_right_mult <= s1_y_fact * s1_right_ref;
end if;
end process;
process(CLK_EVEN)
variable s2_z_wide: unsigned(12 downto 0);
begin
if EN = '1' and rising_edge(CLK_EVEN) then
s2_z_wide := s2_left_mult + s2_right_mult;
s3_z_buf <= s2_z_wide(11 downto 4);
end if;
end process;
Z <= s3_z_buf;
end architecture;
| gpl-3.0 | ec4b3f1a5276d1b535469f81db4c1e3a | 0.563751 | 3.37971 | false | false | false | false |
nsauzede/cpu86 | papilio1/ipcore_dir/dcm32to40.vhd | 1 | 3,155 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application : xaw2vhdl
-- / / Filename : dcm32to40.vhd
-- /___/ /\ Timestamp : 02/17/2015 10:02:14
-- \ \ / \
-- \___\/\___\
--
--Command: xaw2vhdl-st C:\nico\perso\hack\hackerspace\fpga\x86\cpu86\papilio1\ipcore_dir\.\dcm32to40.xaw C:\nico\perso\hack\hackerspace\fpga\x86\cpu86\papilio1\ipcore_dir\.\dcm32to40
--Design Name: dcm32to40
--Device: xc3s500e-4vq100
--
-- Module dcm32to40
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
-- Period Jitter (unit interval) for block DCM_SP_INST = 0.04 UI
-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 0.92 ns
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity dcm32to40 is
port ( CLKIN_IN : in std_logic;
CLKFX_OUT : out std_logic;
CLKIN_IBUFG_OUT : out std_logic;
CLK0_OUT : out std_logic);
end dcm32to40;
architecture BEHAVIORAL of dcm32to40 is
signal CLKFB_IN : std_logic;
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal CLK0_BUF : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
CLK0_OUT <= CLKFB_IN;
CLKFX_BUFG_INST : BUFG
port map (I=>CLKFX_BUF,
O=>CLKFX_OUT);
CLKIN_IBUFG_INST : IBUFG
port map (I=>CLKIN_IN,
O=>CLKIN_IBUFG);
CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLKFB_IN);
DCM_SP_INST : DCM_SP
generic map( CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 4,
CLKFX_MULTIPLY => 5,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.250,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>CLKFB_IN,
CLKIN=>CLKIN_IBUFG,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>GND_BIT,
CLKDV=>open,
CLKFX=>CLKFX_BUF,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>open,
PSDONE=>open,
STATUS=>open);
end BEHAVIORAL;
| gpl-2.0 | cc543cd65b9d0d13f04ee59cc73968a6 | 0.470998 | 3.664344 | false | false | false | false |
nsauzede/cpu86 | drigmorn1/top_drigmorn1/drigmorn1_top.vhd | 1 | 9,809 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Toplevel : CPU86, 256Byte ROM, 16550 UART, 40K8 SRAM (all blockrams used)--
-------------------------------------------------------------------------------
-- Revision History: --
-- --
-- Date: Revision Author --
-- --
-- 30 Dec 2007 0.1 H. Tiggeler First version --
-- 17 May 2008 0.75 H. Tiggeler Updated for CPU86 ver0.75 --
-- 27 Jun 2008 0.79 H. Tiggeler Changed UART to Opencores 16750 --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY drigmorn1_top IS
PORT(
CLOCK_40MHZ : IN std_logic;
CTS : IN std_logic := '1';
PIN3 : IN std_logic;
RXD : IN std_logic;
LED1 : OUT std_logic;
LED2N : OUT std_logic;
LED3N : OUT std_logic;
PIN4 : OUT std_logic;
RTS : OUT std_logic;
TXD : OUT std_logic
);
END drigmorn1_top ;
ARCHITECTURE struct OF drigmorn1_top IS
-- Architecture declarations
signal csromn : std_logic;
-- Internal signal declarations
SIGNAL DCDn : std_logic := '1';
SIGNAL DSRn : std_logic := '1';
SIGNAL RIn : std_logic := '1';
SIGNAL abus : std_logic_vector(19 DOWNTO 0);
SIGNAL clk : std_logic;
SIGNAL cscom1 : std_logic;
SIGNAL dbus_com1 : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_in : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_in_cpu : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_out : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_rom : std_logic_vector(7 DOWNTO 0);
SIGNAL dout : std_logic;
SIGNAL dout1 : std_logic;
SIGNAL intr : std_logic;
SIGNAL iom : std_logic;
SIGNAL nmi : std_logic;
SIGNAL por : std_logic;
SIGNAL rdn : std_logic;
SIGNAL resoutn : std_logic;
SIGNAL sel_s : std_logic_vector(1 DOWNTO 0);
SIGNAL wea : std_logic_VECTOR(0 DOWNTO 0);
SIGNAL wran : std_logic;
SIGNAL wrcom : std_logic;
SIGNAL wrn : std_logic;
signal rxclk_s : std_logic;
-- Component Declarations
COMPONENT cpu86
PORT(
clk : IN std_logic;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
intr : IN std_logic;
nmi : IN std_logic;
por : IN std_logic;
abus : OUT std_logic_vector (19 DOWNTO 0);
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
cpuerror : OUT std_logic;
inta : OUT std_logic;
iom : OUT std_logic;
rdn : OUT std_logic;
resoutn : OUT std_logic;
wran : OUT std_logic;
wrn : OUT std_logic
);
END COMPONENT;
COMPONENT blk_mem_40K
PORT (
addra : IN std_logic_VECTOR (15 DOWNTO 0);
clka : IN std_logic;
dina : IN std_logic_VECTOR (7 DOWNTO 0);
wea : IN std_logic_VECTOR (0 DOWNTO 0);
douta : OUT std_logic_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
COMPONENT bootstrap
PORT (
abus : IN std_logic_vector (7 DOWNTO 0);
dbus : OUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
COMPONENT uart_top
PORT (
BR_clk : IN std_logic ;
CTSn : IN std_logic := '1';
DCDn : IN std_logic := '1';
DSRn : IN std_logic := '1';
RIn : IN std_logic := '1';
abus : IN std_logic_vector (2 DOWNTO 0);
clk : IN std_logic ;
csn : IN std_logic ;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
rdn : IN std_logic ;
resetn : IN std_logic ;
sRX : IN std_logic ;
wrn : IN std_logic ;
B_CLK : OUT std_logic ;
DTRn : OUT std_logic ;
IRQ : OUT std_logic ;
OUT1n : OUT std_logic ;
OUT2n : OUT std_logic ;
RTSn : OUT std_logic ;
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
stx : OUT std_logic
);
END COMPONENT;
BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 4 mux
-- dmux 1
process(sel_s,dbus_com1,dbus_in,dbus_rom)
begin
case sel_s is
when "01" => dbus_in_cpu <= dbus_com1; -- UART
when "10" => dbus_in_cpu <= dbus_rom; -- BootStrap Loader
when others=> dbus_in_cpu <= dbus_in; -- Embedded SRAM
end case;
end process;
-- HDL Embedded Text Block 7 clogic
clk <= CLOCK_40MHZ;
wrcom <= not wrn;
wea(0)<= not wrn;
PIN4 <= resoutn; -- For debug only
-- dbus_in_cpu multiplexer
sel_s <= cscom1 & csromn;
-- chip_select
-- Comport, uart_16550
-- COM1, 0x3F8-0x3FF
cscom1 <= '0' when (abus(15 downto 3)="0000001111111" AND iom='1') else '1';
-- Bootstrap ROM 256 bytes
-- FFFFF-FF=FFF00
csromn <= '0' when ((abus(19 downto 8)=X"FFF") AND iom='0') else '1';
nmi <= '0';
intr <= '0';
dout <= '0';
dout1 <= '0';
DCDn <= '0';
DSRn <= '0';
RIn <= '0';
por <= NOT(PIN3);
-- Instance port mappings.
U_1 : cpu86
PORT MAP (
clk => clk,
dbus_in => dbus_in_cpu,
intr => intr,
nmi => nmi,
por => por,
abus => abus,
cpuerror => LED1,
dbus_out => dbus_out,
inta => OPEN,
iom => iom,
rdn => rdn,
resoutn => resoutn,
wran => wran,
wrn => wrn
);
U_3 : blk_mem_40K
PORT MAP (
clka => clk,
dina => dbus_out,
addra => abus(15 DOWNTO 0),
wea => wea,
douta => dbus_in
);
U_2 : bootstrap
PORT MAP (
abus => abus(7 DOWNTO 0),
dbus => dbus_rom
);
U_0 : uart_top
PORT MAP (
BR_clk => rxclk_s,
CTSn => CTS,
DCDn => DCDn,
DSRn => DSRn,
RIn => RIn,
abus => abus(2 DOWNTO 0),
clk => clk,
csn => cscom1,
dbus_in => dbus_out,
rdn => rdn,
resetn => resoutn,
sRX => RXD,
wrn => wrn,
B_CLK => rxclk_s,
DTRn => OPEN,
IRQ => OPEN,
OUT1n => led2n,
OUT2n => led3n,
RTSn => RTS,
dbus_out => dbus_com1,
stx => TXD
);
END struct;
| gpl-2.0 | 627ae3610b20d161ec994879ee608596 | 0.41309 | 4.231665 | false | false | false | false |
nsauzede/cpu86 | papilio2_lcd/r_table.vhd | 3 | 36,630 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity r_table is
port ( addr : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(2 downto 0));
end r_table;
architecture rtl of r_table is
begin
process(addr)
begin
case addr is
when "1110101100000000" => dout <= "000";
when "1110100100000000" => dout <= "000";
when "1111111111100000" => dout <= "001";
when "1111111100100110" => dout <= "001";
when "1111111100100000" => dout <= "001";
when "1111111101100000" => dout <= "001";
when "1111111110100000" => dout <= "001";
when "1110101000000000" => dout <= "000";
when "1111111100101110" => dout <= "001";
when "1111111100101000" => dout <= "001";
when "1111111101101000" => dout <= "001";
when "1111111110101000" => dout <= "001";
when "1110100000000000" => dout <= "000";
when "1111111111010000" => dout <= "001";
when "1111111100010110" => dout <= "001";
when "1111111100010000" => dout <= "001";
when "1111111101010000" => dout <= "001";
when "1111111110010000" => dout <= "001";
when "1001101000000000" => dout <= "000";
when "1111111100011110" => dout <= "001";
when "1111111100011000" => dout <= "001";
when "1111111101011000" => dout <= "001";
when "1111111110011000" => dout <= "001";
when "1100001100000000" => dout <= "000";
when "1100001000000000" => dout <= "000";
when "1100101100000000" => dout <= "000";
when "1100101000000000" => dout <= "000";
when "0111010000000000" => dout <= "000";
when "0111110000000000" => dout <= "000";
when "0111111000000000" => dout <= "000";
when "0111001000000000" => dout <= "000";
when "0111011000000000" => dout <= "000";
when "0111101000000000" => dout <= "000";
when "0111000000000000" => dout <= "000";
when "0111100000000000" => dout <= "000";
when "0111010100000000" => dout <= "000";
when "0111110100000000" => dout <= "000";
when "0111111100000000" => dout <= "000";
when "0111001100000000" => dout <= "000";
when "0111011100000000" => dout <= "000";
when "0111101100000000" => dout <= "000";
when "0111000100000000" => dout <= "000";
when "0111100100000000" => dout <= "000";
when "1110001100000000" => dout <= "000";
when "1110001000000000" => dout <= "000";
when "1110000100000000" => dout <= "000";
when "1110000000000000" => dout <= "000";
when "1100110100000000" => dout <= "000";
when "1100110000000000" => dout <= "000";
when "1100111000000000" => dout <= "000";
when "1100111100000000" => dout <= "000";
when "1111100000000000" => dout <= "000";
when "1111010100000000" => dout <= "000";
when "1111100100000000" => dout <= "000";
when "1111110000000000" => dout <= "000";
when "1111110100000000" => dout <= "000";
when "1111101000000000" => dout <= "000";
when "1111101100000000" => dout <= "000";
when "1111010000000000" => dout <= "000";
when "1001101100000000" => dout <= "000";
when "1111000000000000" => dout <= "000";
when "1001000000000000" => dout <= "000";
when "0010011000000000" => dout <= "000";
when "0010111000000000" => dout <= "000";
when "0011011000000000" => dout <= "000";
when "0011111000000000" => dout <= "000";
when "1000100011000000" => dout <= "001";
when "1000100000000000" => dout <= "001";
when "1000100001000000" => dout <= "001";
when "1000100010000000" => dout <= "001";
when "1000100000000110" => dout <= "001";
when "1000100111000000" => dout <= "001";
when "1000100100000000" => dout <= "001";
when "1000100101000000" => dout <= "001";
when "1000100110000000" => dout <= "001";
when "1000100100000110" => dout <= "001";
when "1000101011000000" => dout <= "001";
when "1000101000000000" => dout <= "001";
when "1000101001000000" => dout <= "001";
when "1000101010000000" => dout <= "001";
when "1000101000000110" => dout <= "001";
when "1000101111000000" => dout <= "001";
when "1000101100000000" => dout <= "001";
when "1000101101000000" => dout <= "001";
when "1000101110000000" => dout <= "001";
when "1000101100000110" => dout <= "001";
when "1100011000000000" => dout <= "001";
when "1100011001000000" => dout <= "001";
when "1100011010000000" => dout <= "001";
when "1100011000000110" => dout <= "001";
when "1100011100000000" => dout <= "001";
when "1100011101000000" => dout <= "001";
when "1100011110000000" => dout <= "001";
when "1100011100000110" => dout <= "001";
when "1011000000000000" => dout <= "010";
when "1011000100000000" => dout <= "010";
when "1011001000000000" => dout <= "010";
when "1011001100000000" => dout <= "010";
when "1011010000000000" => dout <= "010";
when "1011010100000000" => dout <= "010";
when "1011011000000000" => dout <= "010";
when "1011011100000000" => dout <= "010";
when "1011100000000000" => dout <= "010";
when "1011100100000000" => dout <= "010";
when "1011101000000000" => dout <= "010";
when "1011101100000000" => dout <= "010";
when "1011110000000000" => dout <= "010";
when "1011110100000000" => dout <= "010";
when "1011111000000000" => dout <= "010";
when "1011111100000000" => dout <= "010";
when "1010000000000000" => dout <= "011";
when "1010000100000000" => dout <= "011";
when "1010001000000000" => dout <= "011";
when "1010001100000000" => dout <= "011";
when "1000111011000000" => dout <= "001";
when "1000111000000000" => dout <= "001";
when "1000111001000000" => dout <= "001";
when "1000111010000000" => dout <= "001";
when "1000111000000110" => dout <= "001";
when "1000110011000000" => dout <= "001";
when "1000110000000000" => dout <= "001";
when "1000110001000000" => dout <= "001";
when "1000110010000000" => dout <= "001";
when "1000110000000110" => dout <= "001";
when "1111111100110000" => dout <= "001";
when "1111111101110000" => dout <= "001";
when "1111111110110000" => dout <= "001";
when "1111111100110110" => dout <= "001";
when "0101000000000000" => dout <= "010";
when "0101000100000000" => dout <= "010";
when "0101001000000000" => dout <= "010";
when "0101001100000000" => dout <= "010";
when "0101010000000000" => dout <= "010";
when "0101010100000000" => dout <= "010";
when "0101011000000000" => dout <= "010";
when "0101011100000000" => dout <= "010";
when "0000011000000000" => dout <= "011";
when "0000111000000000" => dout <= "011";
when "0001011000000000" => dout <= "011";
when "0001111000000000" => dout <= "011";
when "1000111100000000" => dout <= "001";
when "1000111101000000" => dout <= "001";
when "1000111110000000" => dout <= "001";
when "1000111100000110" => dout <= "001";
when "1000111111000000" => dout <= "001";
when "0101100000000000" => dout <= "010";
when "0101100100000000" => dout <= "010";
when "0101101000000000" => dout <= "010";
when "0101101100000000" => dout <= "010";
when "0101110000000000" => dout <= "010";
when "0101110100000000" => dout <= "010";
when "0101111000000000" => dout <= "010";
when "0101111100000000" => dout <= "010";
when "0000011100000000" => dout <= "011";
when "0001011100000000" => dout <= "011";
when "0001111100000000" => dout <= "011";
when "1000011011000000" => dout <= "001";
when "1000011000000000" => dout <= "001";
when "1000011001000000" => dout <= "001";
when "1000011010000000" => dout <= "001";
when "1000011000000110" => dout <= "001";
when "1000011111000000" => dout <= "001";
when "1000011100000000" => dout <= "001";
when "1000011101000000" => dout <= "001";
when "1000011110000000" => dout <= "001";
when "1000011100000110" => dout <= "001";
when "1001000100000000" => dout <= "010";
when "1001001000000000" => dout <= "010";
when "1001001100000000" => dout <= "010";
when "1001010000000000" => dout <= "010";
when "1001010100000000" => dout <= "010";
when "1001011000000000" => dout <= "010";
when "1001011100000000" => dout <= "010";
when "1110010000000000" => dout <= "000";
when "1110010100000000" => dout <= "000";
when "1110110000000000" => dout <= "000";
when "1110110100000000" => dout <= "000";
when "1110011000000000" => dout <= "000";
when "1110011100000000" => dout <= "000";
when "1110111100000000" => dout <= "000";
when "1110111000000000" => dout <= "000";
when "1101011100000000" => dout <= "000";
when "1001111100000000" => dout <= "000";
when "1001111000000000" => dout <= "000";
when "1001110000000000" => dout <= "000";
when "1001110100000000" => dout <= "000";
when "1000110100000110" => dout <= "001";
when "1000110111000000" => dout <= "001";
when "1000110100000000" => dout <= "001";
when "1000110101000000" => dout <= "001";
when "1000110110000000" => dout <= "001";
when "1100010100000110" => dout <= "001";
when "1100010100000000" => dout <= "001";
when "1100010101000000" => dout <= "001";
when "1100010110000000" => dout <= "001";
when "1100010000000110" => dout <= "001";
when "1100010000000000" => dout <= "001";
when "1100010001000000" => dout <= "001";
when "1100010010000000" => dout <= "001";
when "0000000011000000" => dout <= "001";
when "0000000000000110" => dout <= "001";
when "0000000000000000" => dout <= "001";
when "0000000001000000" => dout <= "001";
when "0000000010000000" => dout <= "001";
when "0000000111000000" => dout <= "001";
when "0000000100000110" => dout <= "001";
when "0000000100000000" => dout <= "001";
when "0000000101000000" => dout <= "001";
when "0000000110000000" => dout <= "001";
when "0000001011000000" => dout <= "001";
when "0000001000000110" => dout <= "001";
when "0000001000000000" => dout <= "001";
when "0000001001000000" => dout <= "001";
when "0000001010000000" => dout <= "001";
when "0000001111000000" => dout <= "001";
when "0000001100000110" => dout <= "001";
when "0000001100000000" => dout <= "001";
when "0000001101000000" => dout <= "001";
when "0000001110000000" => dout <= "001";
when "1000000011000000" => dout <= "001";
when "1000000000000110" => dout <= "001";
when "1000000000000000" => dout <= "001";
when "1000000001000000" => dout <= "001";
when "1000000010000000" => dout <= "001";
when "1000000111000000" => dout <= "001";
when "1000000100000110" => dout <= "001";
when "1000000100000000" => dout <= "001";
when "1000000101000000" => dout <= "001";
when "1000000110000000" => dout <= "001";
when "1000001111000000" => dout <= "001";
when "1000001100000110" => dout <= "001";
when "1000001100000000" => dout <= "001";
when "1000001101000000" => dout <= "001";
when "1000001110000000" => dout <= "001";
when "0000010000000000" => dout <= "000";
when "0000010100000000" => dout <= "000";
when "0001000011000000" => dout <= "001";
when "0001000000000110" => dout <= "001";
when "0001000000000000" => dout <= "001";
when "0001000001000000" => dout <= "001";
when "0001000010000000" => dout <= "001";
when "0001000111000000" => dout <= "001";
when "0001000100000110" => dout <= "001";
when "0001000100000000" => dout <= "001";
when "0001000101000000" => dout <= "001";
when "0001000110000000" => dout <= "001";
when "0001001011000000" => dout <= "001";
when "0001001000000110" => dout <= "001";
when "0001001000000000" => dout <= "001";
when "0001001001000000" => dout <= "001";
when "0001001010000000" => dout <= "001";
when "0001001111000000" => dout <= "001";
when "0001001100000110" => dout <= "001";
when "0001001100000000" => dout <= "001";
when "0001001101000000" => dout <= "001";
when "0001001110000000" => dout <= "001";
when "1000000011010000" => dout <= "001";
when "1000000000010110" => dout <= "001";
when "1000000000010000" => dout <= "001";
when "1000000001010000" => dout <= "001";
when "1000000010010000" => dout <= "001";
when "1000000111010000" => dout <= "001";
when "1000000100010110" => dout <= "001";
when "1000000100010000" => dout <= "001";
when "1000000101010000" => dout <= "001";
when "1000000110010000" => dout <= "001";
when "1000001111010000" => dout <= "001";
when "1000001100010110" => dout <= "001";
when "1000001100010000" => dout <= "001";
when "1000001101010000" => dout <= "001";
when "1000001110010000" => dout <= "001";
when "0001010000000000" => dout <= "000";
when "0001010100000000" => dout <= "000";
when "0010100011000000" => dout <= "001";
when "0010100000000110" => dout <= "001";
when "0010100000000000" => dout <= "001";
when "0010100001000000" => dout <= "001";
when "0010100010000000" => dout <= "001";
when "0010100111000000" => dout <= "001";
when "0010100100000110" => dout <= "001";
when "0010100100000000" => dout <= "001";
when "0010100101000000" => dout <= "001";
when "0010100110000000" => dout <= "001";
when "0010101011000000" => dout <= "001";
when "0010101000000110" => dout <= "001";
when "0010101000000000" => dout <= "001";
when "0010101001000000" => dout <= "001";
when "0010101010000000" => dout <= "001";
when "0010101111000000" => dout <= "001";
when "0010101100000110" => dout <= "001";
when "0010101100000000" => dout <= "001";
when "0010101101000000" => dout <= "001";
when "0010101110000000" => dout <= "001";
when "1000000011101000" => dout <= "001";
when "1000000000101110" => dout <= "001";
when "1000000000101000" => dout <= "001";
when "1000000001101000" => dout <= "001";
when "1000000010101000" => dout <= "001";
when "1000000111101000" => dout <= "001";
when "1000000100101110" => dout <= "001";
when "1000000100101000" => dout <= "001";
when "1000000101101000" => dout <= "001";
when "1000000110101000" => dout <= "001";
when "1000001111101000" => dout <= "001";
when "1000001100101110" => dout <= "001";
when "1000001100101000" => dout <= "001";
when "1000001101101000" => dout <= "001";
when "1000001110101000" => dout <= "001";
when "0010110000000000" => dout <= "000";
when "0010110100000000" => dout <= "000";
when "0001100011000000" => dout <= "001";
when "0001100000000110" => dout <= "001";
when "0001100000000000" => dout <= "001";
when "0001100001000000" => dout <= "001";
when "0001100010000000" => dout <= "001";
when "0001100111000000" => dout <= "001";
when "0001100100000110" => dout <= "001";
when "0001100100000000" => dout <= "001";
when "0001100101000000" => dout <= "001";
when "0001100110000000" => dout <= "001";
when "0001101011000000" => dout <= "001";
when "0001101000000110" => dout <= "001";
when "0001101000000000" => dout <= "001";
when "0001101001000000" => dout <= "001";
when "0001101010000000" => dout <= "001";
when "0001101111000000" => dout <= "001";
when "0001101100000110" => dout <= "001";
when "0001101100000000" => dout <= "001";
when "0001101101000000" => dout <= "001";
when "0001101110000000" => dout <= "001";
when "1000000011011000" => dout <= "001";
when "1000000000011110" => dout <= "001";
when "1000000000011000" => dout <= "001";
when "1000000001011000" => dout <= "001";
when "1000000010011000" => dout <= "001";
when "1000000111011000" => dout <= "001";
when "1000000100011110" => dout <= "001";
when "1000000100011000" => dout <= "001";
when "1000000101011000" => dout <= "001";
when "1000000110011000" => dout <= "001";
when "1000001111011000" => dout <= "001";
when "1000001100011110" => dout <= "001";
when "1000001100011000" => dout <= "001";
when "1000001101011000" => dout <= "001";
when "1000001110011000" => dout <= "001";
when "0001110000000000" => dout <= "000";
when "0001110100000000" => dout <= "000";
when "1111111011000000" => dout <= "001";
when "1111111000000110" => dout <= "001";
when "1111111000000000" => dout <= "001";
when "1111111001000000" => dout <= "001";
when "1111111010000000" => dout <= "001";
when "1111111100000110" => dout <= "001";
when "1111111100000000" => dout <= "001";
when "1111111101000000" => dout <= "001";
when "1111111110000000" => dout <= "001";
when "0100000000000000" => dout <= "010";
when "0100000100000000" => dout <= "010";
when "0100001000000000" => dout <= "010";
when "0100001100000000" => dout <= "010";
when "0100010000000000" => dout <= "010";
when "0100010100000000" => dout <= "010";
when "0100011000000000" => dout <= "010";
when "0100011100000000" => dout <= "010";
when "1111111011001000" => dout <= "001";
when "1111111000001110" => dout <= "001";
when "1111111000001000" => dout <= "001";
when "1111111001001000" => dout <= "001";
when "1111111010001000" => dout <= "001";
when "1111111100001110" => dout <= "001";
when "1111111100001000" => dout <= "001";
when "1111111101001000" => dout <= "001";
when "1111111110001000" => dout <= "001";
when "0100100000000000" => dout <= "010";
when "0100100100000000" => dout <= "010";
when "0100101000000000" => dout <= "010";
when "0100101100000000" => dout <= "010";
when "0100110000000000" => dout <= "010";
when "0100110100000000" => dout <= "010";
when "0100111000000000" => dout <= "010";
when "0100111100000000" => dout <= "010";
when "0011101011000000" => dout <= "001";
when "0011101000000110" => dout <= "001";
when "0011101000000000" => dout <= "001";
when "0011101001000000" => dout <= "001";
when "0011101010000000" => dout <= "001";
when "0011101111000000" => dout <= "001";
when "0011101100000110" => dout <= "001";
when "0011101100000000" => dout <= "001";
when "0011101101000000" => dout <= "001";
when "0011101110000000" => dout <= "001";
when "0011100000000110" => dout <= "001";
when "0011100000000000" => dout <= "001";
when "0011100001000000" => dout <= "001";
when "0011100010000000" => dout <= "001";
when "0011100011000000" => dout <= "001";
when "0011100100000110" => dout <= "001";
when "0011100100000000" => dout <= "001";
when "0011100101000000" => dout <= "001";
when "0011100110000000" => dout <= "001";
when "0011100111000000" => dout <= "001";
when "1000000011111000" => dout <= "001";
when "1000000000111110" => dout <= "001";
when "1000000000111000" => dout <= "001";
when "1000000001111000" => dout <= "001";
when "1000000010111000" => dout <= "001";
when "1000000111111000" => dout <= "001";
when "1000000100111110" => dout <= "001";
when "1000000100111000" => dout <= "001";
when "1000000101111000" => dout <= "001";
when "1000000110111000" => dout <= "001";
when "1000001111111000" => dout <= "001";
when "1000001100111110" => dout <= "001";
when "1000001100111000" => dout <= "001";
when "1000001101111000" => dout <= "001";
when "1000001110111000" => dout <= "001";
when "0011110000000000" => dout <= "000";
when "0011110100000000" => dout <= "000";
when "1111011011011000" => dout <= "001";
when "1111011000011110" => dout <= "001";
when "1111011000011000" => dout <= "001";
when "1111011001011000" => dout <= "001";
when "1111011010011000" => dout <= "001";
when "1111011111011000" => dout <= "001";
when "1111011100011110" => dout <= "001";
when "1111011100011000" => dout <= "001";
when "1111011101011000" => dout <= "001";
when "1111011110011000" => dout <= "001";
when "0011011100000000" => dout <= "000";
when "0010011100000000" => dout <= "000";
when "0011111100000000" => dout <= "000";
when "0010111100000000" => dout <= "000";
when "1111011011100000" => dout <= "001";
when "1111011000100110" => dout <= "001";
when "1111011000100000" => dout <= "001";
when "1111011001100000" => dout <= "001";
when "1111011010100000" => dout <= "001";
when "1111011111100000" => dout <= "001";
when "1111011100100110" => dout <= "001";
when "1111011100100000" => dout <= "001";
when "1111011101100000" => dout <= "001";
when "1111011110100000" => dout <= "001";
when "1111011011101000" => dout <= "001";
when "1111011000101110" => dout <= "001";
when "1111011000101000" => dout <= "001";
when "1111011001101000" => dout <= "001";
when "1111011010101000" => dout <= "001";
when "1111011111101000" => dout <= "001";
when "1111011100101110" => dout <= "001";
when "1111011100101000" => dout <= "001";
when "1111011101101000" => dout <= "001";
when "1111011110101000" => dout <= "001";
when "1111011011110000" => dout <= "001";
when "1111011000110110" => dout <= "001";
when "1111011000110000" => dout <= "001";
when "1111011001110000" => dout <= "001";
when "1111011010110000" => dout <= "001";
when "1111011111110000" => dout <= "001";
when "1111011100110110" => dout <= "001";
when "1111011100110000" => dout <= "001";
when "1111011101110000" => dout <= "001";
when "1111011110110000" => dout <= "001";
when "1111011011111000" => dout <= "001";
when "1111011000111110" => dout <= "001";
when "1111011000111000" => dout <= "001";
when "1111011001111000" => dout <= "001";
when "1111011010111000" => dout <= "001";
when "1111011111111000" => dout <= "001";
when "1111011100111110" => dout <= "001";
when "1111011100111000" => dout <= "001";
when "1111011101111000" => dout <= "001";
when "1111011110111000" => dout <= "001";
when "1101010000000000" => dout <= "000";
when "1101010100000000" => dout <= "000";
when "1001100000000000" => dout <= "000";
when "1001100100000000" => dout <= "000";
when "1101000011000000" => dout <= "001";
when "1101000000000110" => dout <= "001";
when "1101000000000000" => dout <= "001";
when "1101000001000000" => dout <= "001";
when "1101000010000000" => dout <= "001";
when "1101000111000000" => dout <= "001";
when "1101000100000110" => dout <= "001";
when "1101000100000000" => dout <= "001";
when "1101000101000000" => dout <= "001";
when "1101000110000000" => dout <= "001";
when "1101001011000000" => dout <= "001";
when "1101001000000110" => dout <= "001";
when "1101001000000000" => dout <= "001";
when "1101001001000000" => dout <= "001";
when "1101001010000000" => dout <= "001";
when "1101001111000000" => dout <= "001";
when "1101001100000110" => dout <= "001";
when "1101001100000000" => dout <= "001";
when "1101001101000000" => dout <= "001";
when "1101001110000000" => dout <= "001";
when "0010000011000000" => dout <= "001";
when "0010000000000110" => dout <= "001";
when "0010000000000000" => dout <= "001";
when "0010000001000000" => dout <= "001";
when "0010000010000000" => dout <= "001";
when "0010000111000000" => dout <= "001";
when "0010000100000110" => dout <= "001";
when "0010000100000000" => dout <= "001";
when "0010000101000000" => dout <= "001";
when "0010000110000000" => dout <= "001";
when "0010001011000000" => dout <= "001";
when "0010001000000110" => dout <= "001";
when "0010001000000000" => dout <= "001";
when "0010001001000000" => dout <= "001";
when "0010001010000000" => dout <= "001";
when "0010001111000000" => dout <= "001";
when "0010001100000110" => dout <= "001";
when "0010001100000000" => dout <= "001";
when "0010001101000000" => dout <= "001";
when "0010001110000000" => dout <= "001";
when "1000000011100000" => dout <= "001";
when "1000000000100110" => dout <= "001";
when "1000000000100000" => dout <= "001";
when "1000000001100000" => dout <= "001";
when "1000000010100000" => dout <= "001";
when "1000000111100000" => dout <= "001";
when "1000000100100110" => dout <= "001";
when "1000000100100000" => dout <= "001";
when "1000000101100000" => dout <= "001";
when "1000000110100000" => dout <= "001";
when "1000001111100000" => dout <= "001";
when "1000001100100110" => dout <= "001";
when "1000001100100000" => dout <= "001";
when "1000001101100000" => dout <= "001";
when "1000001110100000" => dout <= "001";
when "0010010000000000" => dout <= "000";
when "0010010100000000" => dout <= "000";
when "0000100000000110" => dout <= "001";
when "0000100000000000" => dout <= "001";
when "0000100001000000" => dout <= "001";
when "0000100010000000" => dout <= "001";
when "0000100011000000" => dout <= "001";
when "0000100100000110" => dout <= "001";
when "0000100100000000" => dout <= "001";
when "0000100101000000" => dout <= "001";
when "0000100110000000" => dout <= "001";
when "0000100111000000" => dout <= "001";
when "0000101011000000" => dout <= "001";
when "0000101000000110" => dout <= "001";
when "0000101000000000" => dout <= "001";
when "0000101001000000" => dout <= "001";
when "0000101010000000" => dout <= "001";
when "0000101111000000" => dout <= "001";
when "0000101100000110" => dout <= "001";
when "0000101100000000" => dout <= "001";
when "0000101101000000" => dout <= "001";
when "0000101110000000" => dout <= "001";
when "1000000011001000" => dout <= "001";
when "1000000000001110" => dout <= "001";
when "1000000000001000" => dout <= "001";
when "1000000001001000" => dout <= "001";
when "1000000010001000" => dout <= "001";
when "1000000111001000" => dout <= "001";
when "1000000100001110" => dout <= "001";
when "1000000100001000" => dout <= "001";
when "1000000101001000" => dout <= "001";
when "1000000110001000" => dout <= "001";
when "1000001111001000" => dout <= "001";
when "1000001100001110" => dout <= "001";
when "1000001100001000" => dout <= "001";
when "1000001101001000" => dout <= "001";
when "1000001110001000" => dout <= "001";
when "0000110000000000" => dout <= "000";
when "0000110100000000" => dout <= "000";
when "1000010000000110" => dout <= "001";
when "1000010000000000" => dout <= "001";
when "1000010001000000" => dout <= "001";
when "1000010010000000" => dout <= "001";
when "1000010100000110" => dout <= "001";
when "1000010100000000" => dout <= "001";
when "1000010101000000" => dout <= "001";
when "1000010110000000" => dout <= "001";
when "1000010011000000" => dout <= "001";
when "1000010111000000" => dout <= "001";
when "1111011011000000" => dout <= "000";
when "1111011000000110" => dout <= "000";
when "1111011000000000" => dout <= "000";
when "1111011001000000" => dout <= "000";
when "1111011010000000" => dout <= "000";
when "1111011111000000" => dout <= "000";
when "1111011100000110" => dout <= "000";
when "1111011100000000" => dout <= "000";
when "1111011101000000" => dout <= "000";
when "1111011110000000" => dout <= "000";
when "1010100000000000" => dout <= "000";
when "1010100100000000" => dout <= "000";
when "0011000000000110" => dout <= "001";
when "0011000000000000" => dout <= "001";
when "0011000001000000" => dout <= "001";
when "0011000010000000" => dout <= "001";
when "0011000011000000" => dout <= "001";
when "0011000100000110" => dout <= "001";
when "0011000100000000" => dout <= "001";
when "0011000101000000" => dout <= "001";
when "0011000110000000" => dout <= "001";
when "0011000111000000" => dout <= "001";
when "0011001011000000" => dout <= "001";
when "0011001000000110" => dout <= "001";
when "0011001000000000" => dout <= "001";
when "0011001001000000" => dout <= "001";
when "0011001010000000" => dout <= "001";
when "0011001111000000" => dout <= "001";
when "0011001100000110" => dout <= "001";
when "0011001100000000" => dout <= "001";
when "0011001101000000" => dout <= "001";
when "0011001110000000" => dout <= "001";
when "1000000011110000" => dout <= "001";
when "1000000000110110" => dout <= "001";
when "1000000000110000" => dout <= "001";
when "1000000001110000" => dout <= "001";
when "1000000010110000" => dout <= "001";
when "1000000111110000" => dout <= "001";
when "1000000100110110" => dout <= "001";
when "1000000100110000" => dout <= "001";
when "1000000101110000" => dout <= "001";
when "1000000110110000" => dout <= "001";
when "1000001111110000" => dout <= "001";
when "1000001100110110" => dout <= "001";
when "1000001100110000" => dout <= "001";
when "1000001101110000" => dout <= "001";
when "1000001110110000" => dout <= "001";
when "0011010000000000" => dout <= "000";
when "0011010100000000" => dout <= "000";
when "1111011011010000" => dout <= "001";
when "1111011000010110" => dout <= "001";
when "1111011000010000" => dout <= "001";
when "1111011001010000" => dout <= "001";
when "1111011010010000" => dout <= "001";
when "1111011111010000" => dout <= "001";
when "1111011100010110" => dout <= "001";
when "1111011100010000" => dout <= "001";
when "1111011101010000" => dout <= "001";
when "1111011110010000" => dout <= "001";
when "1010010000000000" => dout <= "000";
when "1010010100000000" => dout <= "000";
when "1010011000000000" => dout <= "000";
when "1010011100000000" => dout <= "000";
when "1010111000000000" => dout <= "000";
when "1010111100000000" => dout <= "000";
when "1010110000000000" => dout <= "000";
when "1010110100000000" => dout <= "000";
when "1010101000000000" => dout <= "000";
when "1010101100000000" => dout <= "000";
when "1111001000000000" => dout <= "000";
when "1111001100000000" => dout <= "000";
when "0110000000000000" => dout <= "000";
when "0110000100000000" => dout <= "000";
when "1100100000000000" => dout <= "000";
when "1100100100000000" => dout <= "000";
when "0110001000000000" => dout <= "000";
when "0110110000000000" => dout <= "000";
when "0110110100000000" => dout <= "000";
when "0110111000000000" => dout <= "000";
when "0110111100000000" => dout <= "000";
when "0000111100000000" => dout <= "000";
when "0110001100000000" => dout <= "000";
when "0110010000000000" => dout <= "000";
when "0110010100000000" => dout <= "000";
when "0110011000000000" => dout <= "000";
when "0110011100000000" => dout <= "000";
when "1000001000000000" => dout <= "000";
when "1101011000000000" => dout <= "000";
when "1111000100000000" => dout <= "000";
when "1100000000000000" => dout <= "000";
when "1100000100000000" => dout <= "000";
when others => dout <= "---";
end case;
end process;
end rtl; | gpl-2.0 | 7562b3c902c81c9cae030fe73ffc291c | 0.52558 | 4.309919 | false | false | false | false |
nsauzede/cpu86 | papilio2_lcd/vga_sync.vhd | 2 | 2,106 | --
-- Copyright 2011, Kevin Lindsey
-- See LICENSE file for licensing information
--
-- Based on code from P. P. Chu, "FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version", 2008
-- Chapters 12-13
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
entity vga_sync is
port(
clock: in std_logic;
reset: in std_logic;
hsync, vsync: out std_logic;
video_on: out std_logic;
pixel_tick: out std_logic;
pixel_x, pixel_y: out std_logic_vector(9 downto 0)
);
end vga_sync;
architecture arch of vga_sync is
signal h_sync_reg, v_sync_reg, video_on_reg: std_logic := '0';
signal v_count_reg: std_logic_vector(9 downto 0);
signal h_count_reg: std_logic_vector(9 downto 0);
-- VGA 640x480
constant thp : integer := 6; -- hsync 156
constant htotal : integer := 850; -- screen size, with back porch 900
constant tvp : integer := 34; -- vsync 1
constant vtotal : integer := 560; -- screen size, with back porch 560
begin
-- registers
process(clock)
begin
if rising_edge(clock) then
video_on_reg <= '1';
if h_count_reg < (thp) then
h_sync_reg <= '0';
video_on_reg <= '0';
else
h_sync_reg <= '1';
end if;
if v_count_reg < tvp then
v_sync_reg <= '0';
video_on_reg <= '0';
else
v_sync_reg <= '1';
end if;
if h_count_reg = htotal then
h_count_reg <= (others => '0');
if v_count_reg = vtotal then
v_count_reg <= (others => '0');
else
v_count_reg <= v_count_reg + 1;
end if;
else
h_count_reg <= h_count_reg + 1;
end if;
end if;
end process;
-- video on/off
-- video_on <= h_sync_reg and v_sync_reg;
video_on <= video_on_reg;
-- output signals
hsync <= h_sync_reg;
vsync <= v_sync_reg;
pixel_x <= std_logic_vector(h_count_reg)-thp-104;
pixel_y <= std_logic_vector(v_count_reg)-tvp;
-- pixel_tick <= p_tick;
end arch;
| gpl-2.0 | 003a5014a77959970497fb5441deaffc | 0.563628 | 3.115385 | false | false | false | false |
nsauzede/cpu86 | papilio2_lcd/a_table.vhd | 3 | 36,628 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity a_table is
port ( addr : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(2 downto 0));
end a_table;
architecture rtl of a_table is
begin
process(addr)
begin
case addr is
when "1110101100000000" => dout <= "001";
when "1110100100000000" => dout <= "010";
when "1111111111100000" => dout <= "000";
when "1111111100100110" => dout <= "100";
when "1111111100100000" => dout <= "000";
when "1111111101100000" => dout <= "011";
when "1111111110100000" => dout <= "100";
when "1110101000000000" => dout <= "010";
when "1111111100101110" => dout <= "100";
when "1111111100101000" => dout <= "000";
when "1111111101101000" => dout <= "011";
when "1111111110101000" => dout <= "100";
when "1110100000000000" => dout <= "010";
when "1111111111010000" => dout <= "000";
when "1111111100010110" => dout <= "100";
when "1111111100010000" => dout <= "000";
when "1111111101010000" => dout <= "011";
when "1111111110010000" => dout <= "100";
when "1001101000000000" => dout <= "010";
when "1111111100011110" => dout <= "100";
when "1111111100011000" => dout <= "000";
when "1111111101011000" => dout <= "011";
when "1111111110011000" => dout <= "100";
when "1100001100000000" => dout <= "000";
when "1100001000000000" => dout <= "000";
when "1100101100000000" => dout <= "000";
when "1100101000000000" => dout <= "000";
when "0111010000000000" => dout <= "001";
when "0111110000000000" => dout <= "001";
when "0111111000000000" => dout <= "001";
when "0111001000000000" => dout <= "001";
when "0111011000000000" => dout <= "001";
when "0111101000000000" => dout <= "001";
when "0111000000000000" => dout <= "001";
when "0111100000000000" => dout <= "001";
when "0111010100000000" => dout <= "001";
when "0111110100000000" => dout <= "001";
when "0111111100000000" => dout <= "001";
when "0111001100000000" => dout <= "001";
when "0111011100000000" => dout <= "001";
when "0111101100000000" => dout <= "001";
when "0111000100000000" => dout <= "001";
when "0111100100000000" => dout <= "001";
when "1110001100000000" => dout <= "001";
when "1110001000000000" => dout <= "001";
when "1110000100000000" => dout <= "001";
when "1110000000000000" => dout <= "001";
when "1100110100000000" => dout <= "101";
when "1100110000000000" => dout <= "110";
when "1100111000000000" => dout <= "111";
when "1100111100000000" => dout <= "000";
when "1111100000000000" => dout <= "000";
when "1111010100000000" => dout <= "000";
when "1111100100000000" => dout <= "000";
when "1111110000000000" => dout <= "000";
when "1111110100000000" => dout <= "000";
when "1111101000000000" => dout <= "000";
when "1111101100000000" => dout <= "000";
when "1111010000000000" => dout <= "000";
when "1001101100000000" => dout <= "000";
when "1111000000000000" => dout <= "000";
when "1001000000000000" => dout <= "000";
when "0010011000000000" => dout <= "000";
when "0010111000000000" => dout <= "000";
when "0011011000000000" => dout <= "000";
when "0011111000000000" => dout <= "000";
when "1000100011000000" => dout <= "000";
when "1000100000000000" => dout <= "000";
when "1000100001000000" => dout <= "011";
when "1000100010000000" => dout <= "100";
when "1000100000000110" => dout <= "100";
when "1000100111000000" => dout <= "000";
when "1000100100000000" => dout <= "000";
when "1000100101000000" => dout <= "011";
when "1000100110000000" => dout <= "100";
when "1000100100000110" => dout <= "100";
when "1000101011000000" => dout <= "000";
when "1000101000000000" => dout <= "000";
when "1000101001000000" => dout <= "011";
when "1000101010000000" => dout <= "100";
when "1000101000000110" => dout <= "100";
when "1000101111000000" => dout <= "000";
when "1000101100000000" => dout <= "000";
when "1000101101000000" => dout <= "011";
when "1000101110000000" => dout <= "100";
when "1000101100000110" => dout <= "100";
when "1100011000000000" => dout <= "000";
when "1100011001000000" => dout <= "011";
when "1100011010000000" => dout <= "100";
when "1100011000000110" => dout <= "100";
when "1100011100000000" => dout <= "000";
when "1100011101000000" => dout <= "011";
when "1100011110000000" => dout <= "100";
when "1100011100000110" => dout <= "100";
when "1011000000000000" => dout <= "000";
when "1011000100000000" => dout <= "000";
when "1011001000000000" => dout <= "000";
when "1011001100000000" => dout <= "000";
when "1011010000000000" => dout <= "000";
when "1011010100000000" => dout <= "000";
when "1011011000000000" => dout <= "000";
when "1011011100000000" => dout <= "000";
when "1011100000000000" => dout <= "000";
when "1011100100000000" => dout <= "000";
when "1011101000000000" => dout <= "000";
when "1011101100000000" => dout <= "000";
when "1011110000000000" => dout <= "000";
when "1011110100000000" => dout <= "000";
when "1011111000000000" => dout <= "000";
when "1011111100000000" => dout <= "000";
when "1010000000000000" => dout <= "010";
when "1010000100000000" => dout <= "010";
when "1010001000000000" => dout <= "010";
when "1010001100000000" => dout <= "010";
when "1000111011000000" => dout <= "000";
when "1000111000000000" => dout <= "000";
when "1000111001000000" => dout <= "011";
when "1000111010000000" => dout <= "100";
when "1000111000000110" => dout <= "100";
when "1000110011000000" => dout <= "000";
when "1000110000000000" => dout <= "000";
when "1000110001000000" => dout <= "011";
when "1000110010000000" => dout <= "100";
when "1000110000000110" => dout <= "100";
when "1111111100110000" => dout <= "000";
when "1111111101110000" => dout <= "011";
when "1111111110110000" => dout <= "100";
when "1111111100110110" => dout <= "100";
when "0101000000000000" => dout <= "000";
when "0101000100000000" => dout <= "000";
when "0101001000000000" => dout <= "000";
when "0101001100000000" => dout <= "000";
when "0101010000000000" => dout <= "000";
when "0101010100000000" => dout <= "000";
when "0101011000000000" => dout <= "000";
when "0101011100000000" => dout <= "000";
when "0000011000000000" => dout <= "000";
when "0000111000000000" => dout <= "000";
when "0001011000000000" => dout <= "000";
when "0001111000000000" => dout <= "000";
when "1000111100000000" => dout <= "000";
when "1000111101000000" => dout <= "011";
when "1000111110000000" => dout <= "100";
when "1000111100000110" => dout <= "100";
when "1000111111000000" => dout <= "000";
when "0101100000000000" => dout <= "000";
when "0101100100000000" => dout <= "000";
when "0101101000000000" => dout <= "000";
when "0101101100000000" => dout <= "000";
when "0101110000000000" => dout <= "000";
when "0101110100000000" => dout <= "000";
when "0101111000000000" => dout <= "000";
when "0101111100000000" => dout <= "000";
when "0000011100000000" => dout <= "000";
when "0001011100000000" => dout <= "000";
when "0001111100000000" => dout <= "000";
when "1000011011000000" => dout <= "000";
when "1000011000000000" => dout <= "000";
when "1000011001000000" => dout <= "011";
when "1000011010000000" => dout <= "100";
when "1000011000000110" => dout <= "100";
when "1000011111000000" => dout <= "000";
when "1000011100000000" => dout <= "000";
when "1000011101000000" => dout <= "011";
when "1000011110000000" => dout <= "100";
when "1000011100000110" => dout <= "100";
when "1001000100000000" => dout <= "000";
when "1001001000000000" => dout <= "000";
when "1001001100000000" => dout <= "000";
when "1001010000000000" => dout <= "000";
when "1001010100000000" => dout <= "000";
when "1001011000000000" => dout <= "000";
when "1001011100000000" => dout <= "000";
when "1110010000000000" => dout <= "101";
when "1110010100000000" => dout <= "101";
when "1110110000000000" => dout <= "000";
when "1110110100000000" => dout <= "000";
when "1110011000000000" => dout <= "101";
when "1110011100000000" => dout <= "101";
when "1110111100000000" => dout <= "000";
when "1110111000000000" => dout <= "000";
when "1101011100000000" => dout <= "000";
when "1001111100000000" => dout <= "000";
when "1001111000000000" => dout <= "000";
when "1001110000000000" => dout <= "000";
when "1001110100000000" => dout <= "000";
when "1000110100000110" => dout <= "100";
when "1000110111000000" => dout <= "000";
when "1000110100000000" => dout <= "000";
when "1000110101000000" => dout <= "011";
when "1000110110000000" => dout <= "100";
when "1100010100000110" => dout <= "100";
when "1100010100000000" => dout <= "000";
when "1100010101000000" => dout <= "011";
when "1100010110000000" => dout <= "100";
when "1100010000000110" => dout <= "100";
when "1100010000000000" => dout <= "000";
when "1100010001000000" => dout <= "011";
when "1100010010000000" => dout <= "100";
when "0000000011000000" => dout <= "000";
when "0000000000000110" => dout <= "100";
when "0000000000000000" => dout <= "000";
when "0000000001000000" => dout <= "011";
when "0000000010000000" => dout <= "100";
when "0000000111000000" => dout <= "000";
when "0000000100000110" => dout <= "100";
when "0000000100000000" => dout <= "000";
when "0000000101000000" => dout <= "011";
when "0000000110000000" => dout <= "100";
when "0000001011000000" => dout <= "000";
when "0000001000000110" => dout <= "100";
when "0000001000000000" => dout <= "000";
when "0000001001000000" => dout <= "011";
when "0000001010000000" => dout <= "100";
when "0000001111000000" => dout <= "000";
when "0000001100000110" => dout <= "100";
when "0000001100000000" => dout <= "000";
when "0000001101000000" => dout <= "011";
when "0000001110000000" => dout <= "100";
when "1000000011000000" => dout <= "000";
when "1000000000000110" => dout <= "100";
when "1000000000000000" => dout <= "000";
when "1000000001000000" => dout <= "011";
when "1000000010000000" => dout <= "100";
when "1000000111000000" => dout <= "000";
when "1000000100000110" => dout <= "100";
when "1000000100000000" => dout <= "000";
when "1000000101000000" => dout <= "011";
when "1000000110000000" => dout <= "100";
when "1000001111000000" => dout <= "000";
when "1000001100000110" => dout <= "100";
when "1000001100000000" => dout <= "000";
when "1000001101000000" => dout <= "011";
when "1000001110000000" => dout <= "100";
when "0000010000000000" => dout <= "000";
when "0000010100000000" => dout <= "000";
when "0001000011000000" => dout <= "000";
when "0001000000000110" => dout <= "100";
when "0001000000000000" => dout <= "000";
when "0001000001000000" => dout <= "011";
when "0001000010000000" => dout <= "100";
when "0001000111000000" => dout <= "000";
when "0001000100000110" => dout <= "100";
when "0001000100000000" => dout <= "000";
when "0001000101000000" => dout <= "011";
when "0001000110000000" => dout <= "100";
when "0001001011000000" => dout <= "000";
when "0001001000000110" => dout <= "100";
when "0001001000000000" => dout <= "000";
when "0001001001000000" => dout <= "011";
when "0001001010000000" => dout <= "100";
when "0001001111000000" => dout <= "000";
when "0001001100000110" => dout <= "100";
when "0001001100000000" => dout <= "000";
when "0001001101000000" => dout <= "011";
when "0001001110000000" => dout <= "100";
when "1000000011010000" => dout <= "000";
when "1000000000010110" => dout <= "100";
when "1000000000010000" => dout <= "000";
when "1000000001010000" => dout <= "011";
when "1000000010010000" => dout <= "100";
when "1000000111010000" => dout <= "000";
when "1000000100010110" => dout <= "100";
when "1000000100010000" => dout <= "000";
when "1000000101010000" => dout <= "011";
when "1000000110010000" => dout <= "100";
when "1000001111010000" => dout <= "000";
when "1000001100010110" => dout <= "100";
when "1000001100010000" => dout <= "000";
when "1000001101010000" => dout <= "011";
when "1000001110010000" => dout <= "100";
when "0001010000000000" => dout <= "000";
when "0001010100000000" => dout <= "000";
when "0010100011000000" => dout <= "000";
when "0010100000000110" => dout <= "100";
when "0010100000000000" => dout <= "000";
when "0010100001000000" => dout <= "011";
when "0010100010000000" => dout <= "100";
when "0010100111000000" => dout <= "000";
when "0010100100000110" => dout <= "100";
when "0010100100000000" => dout <= "000";
when "0010100101000000" => dout <= "011";
when "0010100110000000" => dout <= "100";
when "0010101011000000" => dout <= "000";
when "0010101000000110" => dout <= "100";
when "0010101000000000" => dout <= "000";
when "0010101001000000" => dout <= "011";
when "0010101010000000" => dout <= "100";
when "0010101111000000" => dout <= "000";
when "0010101100000110" => dout <= "100";
when "0010101100000000" => dout <= "000";
when "0010101101000000" => dout <= "011";
when "0010101110000000" => dout <= "100";
when "1000000011101000" => dout <= "000";
when "1000000000101110" => dout <= "100";
when "1000000000101000" => dout <= "000";
when "1000000001101000" => dout <= "011";
when "1000000010101000" => dout <= "100";
when "1000000111101000" => dout <= "000";
when "1000000100101110" => dout <= "100";
when "1000000100101000" => dout <= "000";
when "1000000101101000" => dout <= "011";
when "1000000110101000" => dout <= "100";
when "1000001111101000" => dout <= "000";
when "1000001100101110" => dout <= "100";
when "1000001100101000" => dout <= "000";
when "1000001101101000" => dout <= "011";
when "1000001110101000" => dout <= "100";
when "0010110000000000" => dout <= "000";
when "0010110100000000" => dout <= "000";
when "0001100011000000" => dout <= "000";
when "0001100000000110" => dout <= "100";
when "0001100000000000" => dout <= "000";
when "0001100001000000" => dout <= "011";
when "0001100010000000" => dout <= "100";
when "0001100111000000" => dout <= "000";
when "0001100100000110" => dout <= "100";
when "0001100100000000" => dout <= "000";
when "0001100101000000" => dout <= "011";
when "0001100110000000" => dout <= "100";
when "0001101011000000" => dout <= "000";
when "0001101000000110" => dout <= "100";
when "0001101000000000" => dout <= "000";
when "0001101001000000" => dout <= "011";
when "0001101010000000" => dout <= "100";
when "0001101111000000" => dout <= "000";
when "0001101100000110" => dout <= "100";
when "0001101100000000" => dout <= "000";
when "0001101101000000" => dout <= "011";
when "0001101110000000" => dout <= "100";
when "1000000011011000" => dout <= "000";
when "1000000000011110" => dout <= "100";
when "1000000000011000" => dout <= "000";
when "1000000001011000" => dout <= "011";
when "1000000010011000" => dout <= "100";
when "1000000111011000" => dout <= "000";
when "1000000100011110" => dout <= "100";
when "1000000100011000" => dout <= "000";
when "1000000101011000" => dout <= "011";
when "1000000110011000" => dout <= "100";
when "1000001111011000" => dout <= "000";
when "1000001100011110" => dout <= "100";
when "1000001100011000" => dout <= "000";
when "1000001101011000" => dout <= "011";
when "1000001110011000" => dout <= "100";
when "0001110000000000" => dout <= "000";
when "0001110100000000" => dout <= "000";
when "1111111011000000" => dout <= "000";
when "1111111000000110" => dout <= "100";
when "1111111000000000" => dout <= "000";
when "1111111001000000" => dout <= "011";
when "1111111010000000" => dout <= "100";
when "1111111100000110" => dout <= "100";
when "1111111100000000" => dout <= "000";
when "1111111101000000" => dout <= "011";
when "1111111110000000" => dout <= "100";
when "0100000000000000" => dout <= "000";
when "0100000100000000" => dout <= "000";
when "0100001000000000" => dout <= "000";
when "0100001100000000" => dout <= "000";
when "0100010000000000" => dout <= "000";
when "0100010100000000" => dout <= "000";
when "0100011000000000" => dout <= "000";
when "0100011100000000" => dout <= "000";
when "1111111011001000" => dout <= "000";
when "1111111000001110" => dout <= "100";
when "1111111000001000" => dout <= "000";
when "1111111001001000" => dout <= "011";
when "1111111010001000" => dout <= "100";
when "1111111100001110" => dout <= "100";
when "1111111100001000" => dout <= "000";
when "1111111101001000" => dout <= "011";
when "1111111110001000" => dout <= "100";
when "0100100000000000" => dout <= "000";
when "0100100100000000" => dout <= "000";
when "0100101000000000" => dout <= "000";
when "0100101100000000" => dout <= "000";
when "0100110000000000" => dout <= "000";
when "0100110100000000" => dout <= "000";
when "0100111000000000" => dout <= "000";
when "0100111100000000" => dout <= "000";
when "0011101011000000" => dout <= "000";
when "0011101000000110" => dout <= "100";
when "0011101000000000" => dout <= "000";
when "0011101001000000" => dout <= "011";
when "0011101010000000" => dout <= "100";
when "0011101111000000" => dout <= "000";
when "0011101100000110" => dout <= "100";
when "0011101100000000" => dout <= "000";
when "0011101101000000" => dout <= "011";
when "0011101110000000" => dout <= "100";
when "0011100000000110" => dout <= "100";
when "0011100000000000" => dout <= "000";
when "0011100001000000" => dout <= "011";
when "0011100010000000" => dout <= "100";
when "0011100011000000" => dout <= "000";
when "0011100100000110" => dout <= "100";
when "0011100100000000" => dout <= "000";
when "0011100101000000" => dout <= "011";
when "0011100110000000" => dout <= "100";
when "0011100111000000" => dout <= "000";
when "1000000011111000" => dout <= "000";
when "1000000000111110" => dout <= "100";
when "1000000000111000" => dout <= "000";
when "1000000001111000" => dout <= "011";
when "1000000010111000" => dout <= "100";
when "1000000111111000" => dout <= "000";
when "1000000100111110" => dout <= "100";
when "1000000100111000" => dout <= "000";
when "1000000101111000" => dout <= "011";
when "1000000110111000" => dout <= "100";
when "1000001111111000" => dout <= "000";
when "1000001100111110" => dout <= "100";
when "1000001100111000" => dout <= "000";
when "1000001101111000" => dout <= "011";
when "1000001110111000" => dout <= "100";
when "0011110000000000" => dout <= "000";
when "0011110100000000" => dout <= "000";
when "1111011011011000" => dout <= "000";
when "1111011000011110" => dout <= "100";
when "1111011000011000" => dout <= "000";
when "1111011001011000" => dout <= "011";
when "1111011010011000" => dout <= "100";
when "1111011111011000" => dout <= "000";
when "1111011100011110" => dout <= "100";
when "1111011100011000" => dout <= "000";
when "1111011101011000" => dout <= "011";
when "1111011110011000" => dout <= "100";
when "0011011100000000" => dout <= "001";
when "0010011100000000" => dout <= "001";
when "0011111100000000" => dout <= "001";
when "0010111100000000" => dout <= "001";
when "1111011011100000" => dout <= "000";
when "1111011000100110" => dout <= "100";
when "1111011000100000" => dout <= "000";
when "1111011001100000" => dout <= "011";
when "1111011010100000" => dout <= "100";
when "1111011111100000" => dout <= "000";
when "1111011100100110" => dout <= "100";
when "1111011100100000" => dout <= "000";
when "1111011101100000" => dout <= "011";
when "1111011110100000" => dout <= "100";
when "1111011011101000" => dout <= "000";
when "1111011000101110" => dout <= "100";
when "1111011000101000" => dout <= "000";
when "1111011001101000" => dout <= "011";
when "1111011010101000" => dout <= "100";
when "1111011111101000" => dout <= "000";
when "1111011100101110" => dout <= "100";
when "1111011100101000" => dout <= "000";
when "1111011101101000" => dout <= "011";
when "1111011110101000" => dout <= "100";
when "1111011011110000" => dout <= "000";
when "1111011000110110" => dout <= "100";
when "1111011000110000" => dout <= "000";
when "1111011001110000" => dout <= "011";
when "1111011010110000" => dout <= "100";
when "1111011111110000" => dout <= "000";
when "1111011100110110" => dout <= "100";
when "1111011100110000" => dout <= "000";
when "1111011101110000" => dout <= "011";
when "1111011110110000" => dout <= "100";
when "1111011011111000" => dout <= "000";
when "1111011000111110" => dout <= "100";
when "1111011000111000" => dout <= "000";
when "1111011001111000" => dout <= "011";
when "1111011010111000" => dout <= "100";
when "1111011111111000" => dout <= "000";
when "1111011100111110" => dout <= "100";
when "1111011100111000" => dout <= "000";
when "1111011101111000" => dout <= "011";
when "1111011110111000" => dout <= "100";
when "1101010000000000" => dout <= "000";
when "1101010100000000" => dout <= "000";
when "1001100000000000" => dout <= "000";
when "1001100100000000" => dout <= "000";
when "1101000011000000" => dout <= "000";
when "1101000000000110" => dout <= "100";
when "1101000000000000" => dout <= "000";
when "1101000001000000" => dout <= "011";
when "1101000010000000" => dout <= "100";
when "1101000111000000" => dout <= "000";
when "1101000100000110" => dout <= "100";
when "1101000100000000" => dout <= "000";
when "1101000101000000" => dout <= "011";
when "1101000110000000" => dout <= "100";
when "1101001011000000" => dout <= "000";
when "1101001000000110" => dout <= "100";
when "1101001000000000" => dout <= "000";
when "1101001001000000" => dout <= "011";
when "1101001010000000" => dout <= "100";
when "1101001111000000" => dout <= "000";
when "1101001100000110" => dout <= "100";
when "1101001100000000" => dout <= "000";
when "1101001101000000" => dout <= "011";
when "1101001110000000" => dout <= "100";
when "0010000011000000" => dout <= "000";
when "0010000000000110" => dout <= "100";
when "0010000000000000" => dout <= "000";
when "0010000001000000" => dout <= "011";
when "0010000010000000" => dout <= "100";
when "0010000111000000" => dout <= "000";
when "0010000100000110" => dout <= "100";
when "0010000100000000" => dout <= "000";
when "0010000101000000" => dout <= "011";
when "0010000110000000" => dout <= "100";
when "0010001011000000" => dout <= "000";
when "0010001000000110" => dout <= "100";
when "0010001000000000" => dout <= "000";
when "0010001001000000" => dout <= "011";
when "0010001010000000" => dout <= "100";
when "0010001111000000" => dout <= "000";
when "0010001100000110" => dout <= "100";
when "0010001100000000" => dout <= "000";
when "0010001101000000" => dout <= "011";
when "0010001110000000" => dout <= "100";
when "1000000011100000" => dout <= "000";
when "1000000000100110" => dout <= "100";
when "1000000000100000" => dout <= "000";
when "1000000001100000" => dout <= "011";
when "1000000010100000" => dout <= "100";
when "1000000111100000" => dout <= "000";
when "1000000100100110" => dout <= "100";
when "1000000100100000" => dout <= "000";
when "1000000101100000" => dout <= "011";
when "1000000110100000" => dout <= "100";
when "1000001111100000" => dout <= "000";
when "1000001100100110" => dout <= "100";
when "1000001100100000" => dout <= "000";
when "1000001101100000" => dout <= "011";
when "1000001110100000" => dout <= "100";
when "0010010000000000" => dout <= "000";
when "0010010100000000" => dout <= "000";
when "0000100000000110" => dout <= "100";
when "0000100000000000" => dout <= "000";
when "0000100001000000" => dout <= "011";
when "0000100010000000" => dout <= "100";
when "0000100011000000" => dout <= "000";
when "0000100100000110" => dout <= "100";
when "0000100100000000" => dout <= "000";
when "0000100101000000" => dout <= "011";
when "0000100110000000" => dout <= "100";
when "0000100111000000" => dout <= "000";
when "0000101011000000" => dout <= "000";
when "0000101000000110" => dout <= "100";
when "0000101000000000" => dout <= "000";
when "0000101001000000" => dout <= "011";
when "0000101010000000" => dout <= "100";
when "0000101111000000" => dout <= "000";
when "0000101100000110" => dout <= "100";
when "0000101100000000" => dout <= "000";
when "0000101101000000" => dout <= "011";
when "0000101110000000" => dout <= "100";
when "1000000011001000" => dout <= "000";
when "1000000000001110" => dout <= "100";
when "1000000000001000" => dout <= "000";
when "1000000001001000" => dout <= "011";
when "1000000010001000" => dout <= "100";
when "1000000111001000" => dout <= "000";
when "1000000100001110" => dout <= "100";
when "1000000100001000" => dout <= "000";
when "1000000101001000" => dout <= "011";
when "1000000110001000" => dout <= "100";
when "1000001111001000" => dout <= "000";
when "1000001100001110" => dout <= "100";
when "1000001100001000" => dout <= "000";
when "1000001101001000" => dout <= "011";
when "1000001110001000" => dout <= "100";
when "0000110000000000" => dout <= "000";
when "0000110100000000" => dout <= "000";
when "1000010000000110" => dout <= "100";
when "1000010000000000" => dout <= "000";
when "1000010001000000" => dout <= "011";
when "1000010010000000" => dout <= "100";
when "1000010100000110" => dout <= "100";
when "1000010100000000" => dout <= "000";
when "1000010101000000" => dout <= "011";
when "1000010110000000" => dout <= "100";
when "1000010011000000" => dout <= "000";
when "1000010111000000" => dout <= "000";
when "1111011011000000" => dout <= "000";
when "1111011000000110" => dout <= "100";
when "1111011000000000" => dout <= "000";
when "1111011001000000" => dout <= "011";
when "1111011010000000" => dout <= "100";
when "1111011111000000" => dout <= "000";
when "1111011100000110" => dout <= "100";
when "1111011100000000" => dout <= "000";
when "1111011101000000" => dout <= "011";
when "1111011110000000" => dout <= "100";
when "1010100000000000" => dout <= "000";
when "1010100100000000" => dout <= "000";
when "0011000000000110" => dout <= "100";
when "0011000000000000" => dout <= "000";
when "0011000001000000" => dout <= "011";
when "0011000010000000" => dout <= "100";
when "0011000011000000" => dout <= "000";
when "0011000100000110" => dout <= "100";
when "0011000100000000" => dout <= "000";
when "0011000101000000" => dout <= "011";
when "0011000110000000" => dout <= "100";
when "0011000111000000" => dout <= "000";
when "0011001011000000" => dout <= "000";
when "0011001000000110" => dout <= "100";
when "0011001000000000" => dout <= "000";
when "0011001001000000" => dout <= "011";
when "0011001010000000" => dout <= "100";
when "0011001111000000" => dout <= "000";
when "0011001100000110" => dout <= "100";
when "0011001100000000" => dout <= "000";
when "0011001101000000" => dout <= "011";
when "0011001110000000" => dout <= "100";
when "1000000011110000" => dout <= "000";
when "1000000000110110" => dout <= "100";
when "1000000000110000" => dout <= "000";
when "1000000001110000" => dout <= "011";
when "1000000010110000" => dout <= "100";
when "1000000111110000" => dout <= "000";
when "1000000100110110" => dout <= "100";
when "1000000100110000" => dout <= "000";
when "1000000101110000" => dout <= "011";
when "1000000110110000" => dout <= "100";
when "1000001111110000" => dout <= "000";
when "1000001100110110" => dout <= "100";
when "1000001100110000" => dout <= "000";
when "1000001101110000" => dout <= "011";
when "1000001110110000" => dout <= "100";
when "0011010000000000" => dout <= "000";
when "0011010100000000" => dout <= "000";
when "1111011011010000" => dout <= "000";
when "1111011000010110" => dout <= "100";
when "1111011000010000" => dout <= "000";
when "1111011001010000" => dout <= "011";
when "1111011010010000" => dout <= "100";
when "1111011111010000" => dout <= "000";
when "1111011100010110" => dout <= "100";
when "1111011100010000" => dout <= "000";
when "1111011101010000" => dout <= "011";
when "1111011110010000" => dout <= "100";
when "1010010000000000" => dout <= "000";
when "1010010100000000" => dout <= "000";
when "1010011000000000" => dout <= "000";
when "1010011100000000" => dout <= "000";
when "1010111000000000" => dout <= "000";
when "1010111100000000" => dout <= "000";
when "1010110000000000" => dout <= "000";
when "1010110100000000" => dout <= "000";
when "1010101000000000" => dout <= "000";
when "1010101100000000" => dout <= "000";
when "1111001000000000" => dout <= "000";
when "1111001100000000" => dout <= "000";
when "0110000000000000" => dout <= "000";
when "0110000100000000" => dout <= "000";
when "1100100000000000" => dout <= "000";
when "1100100100000000" => dout <= "000";
when "0110001000000000" => dout <= "000";
when "0110110000000000" => dout <= "000";
when "0110110100000000" => dout <= "000";
when "0110111000000000" => dout <= "000";
when "0110111100000000" => dout <= "000";
when "0000111100000000" => dout <= "000";
when "0110001100000000" => dout <= "000";
when "0110010000000000" => dout <= "000";
when "0110010100000000" => dout <= "000";
when "0110011000000000" => dout <= "000";
when "0110011100000000" => dout <= "000";
when "1000001000000000" => dout <= "000";
when "1101011000000000" => dout <= "000";
when "1111000100000000" => dout <= "000";
when "1100000000000000" => dout <= "000";
when "1100000100000000" => dout <= "000";
when others => dout <= "---";
end case;
end process;
end rtl; | gpl-2.0 | 7a10bb4aadc75e616fb6c833781c92b6 | 0.525609 | 4.309683 | false | false | false | false |
VenturaSolutionsInc/VHDL | igmp/igmp_assembler_tb.vhd | 1 | 3,182 | -------------------------------------------------------------------------------
-- Title : Testbench for design "igmp_assembler"
-- Project :
-------------------------------------------------------------------------------
-- File : igmp_assembler_tb.vhd
-- Author : <Kelly@APOLLO>
-- Company :
-- Created : 2010-05-21
-- Last update: 2010-06-27
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2010
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-05-21 1.0 Kelly Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity igmp_assembler_tb is
end igmp_assembler_tb;
-------------------------------------------------------------------------------
architecture testbench of igmp_assembler_tb is
-- component generics
constant gen_dataWidth : integer := 8;
-- component ports
signal dataClk : std_logic;
signal reset : std_logic;
signal srcMAC : std_logic_vector(47 downto 0):=X"010040506660";
signal destMAC : std_logic_vector(47 downto 0):=X"01005E1C1901";
signal vlanEn : std_logic;
signal vlanId : std_logic_vector(11 downto 0):=X"06A";
signal srcIP : std_logic_vector(31 downto 0):=X"C0A80164";
signal destIP : std_logic_vector(31 downto 0):=X"EF9C1901";
signal join : std_logic;
signal respond : std_logic;
signal leave : std_logic;
signal tx_ready_n : std_logic;
signal tx_sof : std_logic;
signal tx_eof : std_logic;
signal tx_vld : std_logic;
signal tx_data : std_logic_vector(7 downto 0);
begin -- testbench
-- generate the clock
process
begin
dataClk <= '0';
wait for 4 ns;
dataClk <= '1';
wait for 4 ns;
end process;
-- component instantiation
igmp_assembler_entity: entity work.igmp_assembler
generic map (
gen_dataWidth => gen_dataWidth)
port map (
dataClk => dataClk,
reset => reset,
srcMAC => srcMAC,
destMAC => destMAC,
vlanEn => vlanEn,
vlanId => vlanId,
srcIP => srcIP,
destIP => destIP,
join => join,
messageSent => open,
leave => leave,
tx_ready_n => tx_ready_n,
tx_sof => tx_sof,
tx_eof => tx_eof,
tx_vld => tx_vld,
tx_data => tx_data
);
vlanEn <= '1';
process
begin
reset <= '1';
join <= '0';
respond <= '0';
leave <= '0';
tx_ready_n <= '0';
wait for 16 ns;
reset <= '0';
join <= '1';
wait for 16 ns;
join <= '0';
wait for 450 ns;
leave <= '1';
wait for 16 ns;
leave <= '0';
wait;
end process;
end testbench;
| gpl-2.0 | 47e65cfe419e1972a271d51c6802401e | 0.435889 | 4.248331 | false | false | false | false |
nsauzede/cpu86 | p2_vga_spi/drigmorn1_top.vhd | 1 | 13,331 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Toplevel : CPU86, 256Byte ROM, 16550 UART, 40K8 SRAM (all blockrams used)--
-------------------------------------------------------------------------------
-- Revision History: --
-- --
-- Date: Revision Author --
-- --
-- 30 Dec 2007 0.1 H. Tiggeler First version --
-- 17 May 2008 0.75 H. Tiggeler Updated for CPU86 ver0.75 --
-- 27 Jun 2008 0.79 H. Tiggeler Changed UART to Opencores 16750 --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY drigmorn1_top IS
PORT(
sram_addr : out std_logic_vector(20 downto 0);
sram_data : inout std_logic_vector(7 downto 0);
sram_ce : out std_logic;
sram_we : out std_logic;
sram_oe : out std_logic;
vramaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
vramdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
spi_cs : out std_logic;
spi_clk : out std_logic;
spi_mosi : out std_logic;
spi_miso : in std_logic;
buttons : in STD_LOGIC_VECTOR (3 downto 0);
leds : out STD_LOGIC_VECTOR (3 downto 0);
CLOCK_40MHZ : IN std_logic;
CTS : IN std_logic := '1';
PIN3 : IN std_logic;
RXD : IN std_logic;
LED1 : OUT std_logic;
LED2N : OUT std_logic;
LED3N : OUT std_logic;
PIN4 : OUT std_logic;
RTS : OUT std_logic;
TXD : OUT std_logic
);
END drigmorn1_top ;
ARCHITECTURE struct OF drigmorn1_top IS
-- Architecture declarations
signal csromn : std_logic;
signal csesramn : std_logic;
signal csisramn : std_logic;
signal csspin : std_logic;
signal csspi : std_logic;
signal csbutled : std_logic;
signal leds_b : STD_LOGIC_VECTOR (3 downto 0);
-- Internal signal declarations
SIGNAL DCDn : std_logic := '1';
SIGNAL DSRn : std_logic := '1';
SIGNAL RIn : std_logic := '1';
SIGNAL abus : std_logic_vector(19 DOWNTO 0);
SIGNAL clk : std_logic;
SIGNAL cscom1 : std_logic;
SIGNAL dbus_com1 : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_in : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_in_cpu : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_out : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_rom : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_esram : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_spi : std_logic_vector(7 DOWNTO 0);
SIGNAL dout : std_logic;
SIGNAL dout1 : std_logic;
SIGNAL intr : std_logic;
SIGNAL iom : std_logic;
SIGNAL nmi : std_logic;
SIGNAL por : std_logic;
SIGNAL rdn : std_logic;
SIGNAL resoutn : std_logic;
SIGNAL sel_s : std_logic_vector(5 DOWNTO 0);
SIGNAL wea : std_logic_VECTOR(0 DOWNTO 0);
SIGNAL wran : std_logic;
SIGNAL wrcom : std_logic;
SIGNAL wspi : std_logic;
SIGNAL wrn : std_logic;
signal rxclk_s : std_logic;
-- Component Declarations
COMPONENT cpu86
PORT(
clk : IN std_logic;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
intr : IN std_logic;
nmi : IN std_logic;
por : IN std_logic;
abus : OUT std_logic_vector (19 DOWNTO 0);
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
cpuerror : OUT std_logic;
inta : OUT std_logic;
iom : OUT std_logic;
rdn : OUT std_logic;
resoutn : OUT std_logic;
wran : OUT std_logic;
wrn : OUT std_logic
);
END COMPONENT;
-- COMPONENT blk_mem_40K
-- PORT (
-- addra : IN std_logic_VECTOR (15 DOWNTO 0);
-- clka : IN std_logic;
-- dina : IN std_logic_VECTOR (7 DOWNTO 0);
-- wea : IN std_logic_VECTOR (0 DOWNTO 0);
-- douta : OUT std_logic_VECTOR (7 DOWNTO 0)
-- );
-- END COMPONENT;
component blk_mem_40K
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END component;
COMPONENT bootstrap
PORT (
abus : IN std_logic_vector (7 DOWNTO 0);
dbus : OUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
COMPONENT uart_top
PORT (
BR_clk : IN std_logic ;
CTSn : IN std_logic := '1';
DCDn : IN std_logic := '1';
DSRn : IN std_logic := '1';
RIn : IN std_logic := '1';
abus : IN std_logic_vector (2 DOWNTO 0);
clk : IN std_logic ;
csn : IN std_logic ;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
rdn : IN std_logic ;
resetn : IN std_logic ;
sRX : IN std_logic ;
wrn : IN std_logic ;
B_CLK : OUT std_logic ;
DTRn : OUT std_logic ;
IRQ : OUT std_logic ;
OUT1n : OUT std_logic ;
OUT2n : OUT std_logic ;
RTSn : OUT std_logic ;
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
stx : OUT std_logic
);
END COMPONENT;
BEGIN
sram_addr <= '0' & abus;
---- sram_data <= dbus_.
-- dbus_esram <= sram_data;
-- sram_data <= (others => 'Z') when rdn='0' else sram_data;
-- sram_ce <= csesramn;
-- sram_we <= wrn;
-- sram_oe <= rdn;
process(csesramn,wrn,rdn,dbus_out,sram_data)
begin
sram_ce <= '1';
sram_we <= '1';
sram_oe <= '1';
sram_data <= (others => 'Z');
if csesramn='0' then
sram_ce <= '0';
if wrn='0' then
sram_data <= dbus_out;
sram_we <= '0';
else
if rdn='0' then
dbus_esram <= sram_data;
sram_oe <= '0';
end if;
end if;
end if;
end process;
leds <= leds_b;
leds_b <= dbus_out(3 downto 0) when (csbutled='0') and (wrn='0') else leds_b;
-- Architecture concurrent statements
-- HDL Embedded Text Block 4 mux
-- dmux 1
process(sel_s,dbus_com1,dbus_in,dbus_rom,dbus_esram,dbus_spi,buttons)
begin
case sel_s is
when "011111" => dbus_in_cpu <= dbus_com1; -- UART
when "101111" => dbus_in_cpu <= dbus_rom; -- BootStrap Loader
when "110111" => dbus_in_cpu <= dbus_in; -- Embedded SRAM
when "111011" => dbus_in_cpu <= dbus_spi; -- SPI
when "111101" => dbus_in_cpu <= sram_data; -- External SRAM
when "111110" => dbus_in_cpu <= x"0" & buttons; -- butled
when others => dbus_in_cpu <= dbus_in_cpu; -- default : latch
end case;
end process;
-- HDL Embedded Text Block 7 clogic
clk <= CLOCK_40MHZ;
wrcom <= not wrn;
wea(0)<= not wrn and not csisramn;
wspi<= not wrn;
PIN4 <= resoutn; -- For debug only
-- dbus_in_cpu multiplexer
sel_s <= cscom1 & csromn & csisramn & csspin & csesramn & csbutled;
-- chip_select
-- Comport, uart_16550
-- COM1, 0x3F8-0x3FF
cscom1 <= '0' when (abus(15 downto 4)=x"03f" AND iom='1') else '1';
-- SPI, 0x400-0x407
csspin <= '0' when (abus(15 downto 4)=x"040" AND iom='1') else '1';
csspi <= not csspin;
-- BUTLED, 0x500-0x507
csbutled <= '0' when ((abus(15 downto 4)=X"050") AND iom='1') else '1';
-- Bootstrap ROM 256 bytes
-- FFFFF-FF=FFF00
csromn <= '0' when ((abus(19 downto 8)=X"FFF") AND iom='0') else '1';
-- external SRAM
-- 0x5F8-0x5FF
-- csesramn <= '0' when (csromn='1' and csisramn='1' AND iom='0') else '1';
-- csesramn <= not (cscom1 and csromnn and csiramn);
csesramn <= '0' when ((abus(19 downto 16)=X"E") AND iom='0') else '1';
-- internal SRAM
-- below 0x4000
csisramn <= '0' when (abus(19 downto 16)=x"0" AND iom='0') else '1';
spim0: entity work.spi_master
port map ( clk => clk,
reset => por,
cpu_address => abus(2 downto 0),
cpu_wait => open,
data_in => dbus_out,
data_out => dbus_spi,
enable => csspi,
req_read => '0',
req_write => wspi,
slave_cs => spi_cs,
slave_clk => spi_clk,
slave_mosi => spi_mosi,
slave_miso => spi_miso
);
nmi <= '0';
intr <= '0';
dout <= '0';
dout1 <= '0';
DCDn <= '0';
DSRn <= '0';
RIn <= '0';
por <= NOT(PIN3);
-- Instance port mappings.
U_1 : cpu86
PORT MAP (
clk => clk,
dbus_in => dbus_in_cpu,
intr => intr,
nmi => nmi,
por => por,
abus => abus,
cpuerror => LED1,
dbus_out => dbus_out,
inta => OPEN,
iom => iom,
rdn => rdn,
resoutn => resoutn,
wran => wran,
wrn => wrn
);
-- U_3 : blk_mem_40K
-- PORT MAP (
-- clka => clk,
-- dina => dbus_out,
-- addra => abus(15 DOWNTO 0),
-- wea => wea,
-- douta => dbus_in
-- );
U_3 : blk_mem_40K
PORT MAP (
clka => clk,
dina => dbus_out,
addra => abus(15 DOWNTO 0),
wea => wea,
douta => dbus_in,
clkb => clk,
dinb => (others => '0'),
addrb => vramaddr,
web => (others => '0'),
doutb => vramdata
);
U_2 : bootstrap
PORT MAP (
abus => abus(7 DOWNTO 0),
dbus => dbus_rom
);
U_0 : uart_top
PORT MAP (
BR_clk => rxclk_s,
CTSn => CTS,
DCDn => DCDn,
DSRn => DSRn,
RIn => RIn,
abus => abus(2 DOWNTO 0),
clk => clk,
csn => cscom1,
dbus_in => dbus_out,
rdn => rdn,
resetn => resoutn,
sRX => RXD,
wrn => wrn,
B_CLK => rxclk_s,
DTRn => OPEN,
IRQ => OPEN,
OUT1n => led2n,
OUT2n => led3n,
RTSn => RTS,
dbus_out => dbus_com1,
stx => TXD
);
END struct;
| gpl-2.0 | ce5838ad39a35b7f7da10896c516f03e | 0.458855 | 3.754154 | false | false | false | false |
ismailalmahdi/HMAC-SHA384-VHDL | HMACSHA384_ISMAIL.vhd | 1 | 17,117 | --------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-------??? ??????? ???? ?????? ?????????????????? ??? ??????---------------
-------??? ???????? ???????????????????????????????? ???????????--------------
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-------??? ?????? ?????? ??? ?????????????????? ?????? ???--------------
--------------------------------------------------------------------------------
------------------------??????? ?????? ??? ???--------------------------------
------------------------??????????????????? ???--------------------------------
-------------------------???????????????????????--------------------------------
-------------------------???????????????????????--------------------------------
------------------------???????????????? ???--------------------------------
------------------------??????? ??????------???--------------------------------
--------------------------------------------------------------------------------
-----------???---???????---???????????????????????????---???--------------------
-----------???---????????--????????????????????????????--???--------------------
-----------???---?????????-??????---???---??????--??????-???--------------------
-----------???---????????????????---???---??????--??????????--------------------
-----------???????????? ?????????---???---??????????? ??????--------------------
------------??????? ??? ????????---???---??????????? ?????--------------------
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.All;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--------------------------------------------------------------------------------
--///////////////////// PACKAGE HEADER STARTS HERE ///////////////////////////--
--------------------------------------------------------------------------------
package HMACSHA384_ISMAIL is
-----------------------
-- Declare constants --
-----------------------
constant block_size : integer := 1024; --bits
constant word_size : integer := 64; --bits
constant rounds_number : integer := 80; --bits
constant hashed_size : integer := 384; --bits
constant length_bits : integer := 128; --bits
------------------------------
-- Declare functions needed --
------------------------------
-- MESSAGE PADDING FUNCTION
function message_padding (message: std_logic_vector)
return std_logic_vector;
-- GET MESSAGE BLOCK FUNCTION
function get_message_block (padded_message:std_logic_vector; block_number: integer)
return std_logic_vector;
-- GET MESSAGE BLOCKS COUNT
function get_message_blocks_count(padded_message:std_logic_vector)
return integer;
---- F FUNCTION
function F_FUNCTION (H : std_logic_vector (hashed_size - 1 downto 0);
message_block: std_logic_vector (block_size - 1 downto 0) )
return std_logic_vector;
-- F FUNCTION SUB FUNCTIONS
function T1 (f,c,d,e,w,k:std_logic_vector(word_size-1 downto 0))
return std_logic_vector;
function T2 (a,b,c:std_logic_vector(word_size-1 downto 0))
return std_logic_vector;
function Ch(c,d,e:std_logic_vector(word_size-1 downto 0))
return std_logic_vector;
function Maj(a,b,c:std_logic_vector(word_size-1 downto 0))
return std_logic_vector;
function SumA(a:std_logic_vector(word_size-1 downto 0))
return std_logic_vector;
function SumE(e:std_logic_vector(word_size-1 downto 0))
return std_logic_vector;
function Key(index: integer)
return std_logic_vector;
function ROTR(WORD:std_logic_vector(word_size-1 downto 0);ROUNDS:integer)
return std_logic_vector;
function SHR(WORD:std_logic_vector(word_size-1 downto 0);ROUNDS:integer)
return std_logic_vector;
--- W FUNCTIONS
function W_HASHING_1(word:std_logic_vector(word_size-1 downto 0))
return std_logic_vector;
function W_HASHING_2(word:std_logic_vector(word_size-1 downto 0))
return std_logic_vector;
function get_w_value (w_register: std_logic_vector (((rounds_number * word_size) - 1 )downto 0);
w_index: integer)
return std_logic_vector;
function generate_w_value(message_block:std_logic_vector(block_size-1 downto 0))
return std_logic_vector;
------ SHA384 HASHING FUNCTION
function SHA384_HASHING( message:std_logic_vector;
IV: std_logic_vector(hashed_size - 1 downto 0))
return std_logic_vector;
------ HMACSHA384 HASHING FUNCTION
function HMACSHA384( IV : std_logic_vector (hashed_size-1 downto 0);-- salt
KEY : std_logic_vector;
message :std_logic_vector) -- message size
return std_logic_vector;
------ HMACSHA384 SUB FUNCTIONS
function opad_generate (block_size: integer)
return std_logic_vector;
function ipad_generate (block_size: integer)
return std_logic_vector;
end HMACSHA384_ISMAIL;
--------------------------------------------------------------------------------
--///////////////////// PACKAGE HEADER ENDS HERE /////////////////////////////--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--///////////////////// PACKAGE BODY STARTS HERE /////////////////////////////--
--------------------------------------------------------------------------------
package body HMACSHA384_ISMAIL is --- START OF PACKAGE BODY
-------------------------
---- MESSAGE PADDING ----
-------------------------
function message_padding (message: std_logic_vector)
return std_logic_vector is
variable mod_val: integer := (message'length) mod block_size;
variable padding_length : integer := ((block_size-129)+(block_size - mod_val));
variable padded_length : integer := (
message'length
+ (1 + padding_length)
+ length_bits
);
variable message_length: std_logic_vector(
(length_bits - 1) downto 0
) := (others=>'0');
variable padded_message: std_logic_vector (
(padded_length - 1) downto 0
) := (others => '0');
variable padding: std_logic_vector (
(padding_length) downto 0
) := (others => '0');
begin
message_length := std_logic_vector(to_unsigned(message'length,length_bits));
padding := "1" & std_logic_vector(to_unsigned(0,padding_length));
padded_message := message & padding & message_length;
return padded_message;
end message_padding;
---------------------------------
---- GET MESSAGE BLOCK COUNT ----
---------------------------------
function get_message_blocks_count(padded_message:std_logic_vector)
return integer is
variable blocks_count : integer := (padded_message'length/block_size);
begin
return blocks_count;
end get_message_blocks_count;
---------------------------
---- GET MESSAGE BLOCK ----
---------------------------
function get_message_block (padded_message:std_logic_vector; block_number: integer)
return std_logic_vector is
variable blocks_count : integer := get_message_blocks_count(padded_message);
begin
return padded_message(((blocks_count - block_number) * block_size) - 1 downto
(((blocks_count - (block_number + 1)) * block_size ))) ;
end get_message_block;
--------------------
---- FUNCTION F ----
--------------------
function F_FUNCTION (H : std_logic_vector (hashed_size - 1 downto 0);
message_block: std_logic_vector (block_size - 1 downto 0) )
return std_logic_vector is
variable memory: std_logic_vector(5119 downto 0);
variable a,b,c,d,e,f,w,k : std_logic_vector (word_size-1 downto 0);
begin
a := H(383 downto 320);
b := H(319 downto 256);
c := H(255 downto 192);
d := H(191 downto 128);
e := H(127 downto 64);
f := H(63 downto 0);
memory := generate_w_value(message_block);
roundsloop : for i in 0 to (rounds_number-1) loop
-- init values
w := get_w_value(memory,i);
k := Key(i);
a := T1(f,c,d,e,w,k) + T2(a,b,c);
b := a;
c := b;
d := c;
e := d + T1(f,c,d,e,w,k);
f := e;
end loop ; -- roundsloop
return (a & b & c & d & e & f);
end F_FUNCTION;
---------------------------
---- GENERATE T1 VALUE ----
---------------------------
function T1 (f,c,d,e,w,k:std_logic_vector(word_size-1 downto 0))
return std_logic_vector is
begin
return (f + Ch(c,d,e) + SumE(e) + w + k);
end T1;
---------------------------
---- GENERATE T2 VALUE ----
---------------------------
function T2 (a,b,c:std_logic_vector(word_size-1 downto 0))
return std_logic_vector is
begin
return (SumA(a) + Maj(a,b,c));
end T2;
---------------------------
---- GENERATE Ch VALUE ----
---------------------------
function Ch(c,d,e:std_logic_vector(word_size-1 downto 0))
return std_logic_vector is
begin
return ((c and d) xor ((not c) and e));
end Ch;
----------------------------
---- GENERATE Maj VALUE ----
----------------------------
function Maj(a,b,c:std_logic_vector(word_size-1 downto 0))
return std_logic_vector is
begin
return ((a and b) xor (a and c) xor (b and c));
end Maj;
-----------------------------
---- GENERATE SumA VALUE ----
-----------------------------
function SumA(a:std_logic_vector(word_size-1 downto 0))
return std_logic_vector is
variable tmp: std_logic_vector (word_size-1 downto 0);
begin
identifier : for i in 0 to hashed_size loop
tmp:= ROTR(a,28) xor ROTR(a,34) xor ROTR(a,39);
end loop ; -- identifier
return tmp;
end SumA;
-----------------------------
---- GENERATE SumE VALUE ----
-----------------------------
function SumE(e:std_logic_vector(word_size-1 downto 0))
return std_logic_vector is
variable tmp: std_logic_vector (word_size-1 downto 0);
begin
identifier : for i in 1 to hashed_size loop
tmp:= ROTR(e,14) xor ROTR(e,18) xor ROTR(e,41);
end loop ; -- identifier
return tmp;
end SumE;
--------------------------
---- GENERATE k VALUE ----
--------------------------
function Key(index: integer)
return std_logic_vector is
begin
return std_logic_vector(to_unsigned(index,word_size));
end Key;
--------------------------
---- GENERATE W VALUE ----
--------------------------
function generate_w_value(message_block:std_logic_vector(block_size-1 downto 0))
return std_logic_vector is
variable generated_word : std_logic_vector(word_size-1 downto 0);
variable WI1,WI2,WI3,WI4 : integer;
variable w_leg : integer := (rounds_number * word_size) - 1;
variable w_reg : std_logic_vector ( w_leg downto 0);
begin
w_reg( w_leg downto 4096) := message_block;
wordGen : for t in 16 to (rounds_number - 1) loop
WI1 := t - 16 ; WI2 := t - 15 ;
WI3 := t - 7 ; WI4 := t - 2 ;
w_reg ( (64*(80-(t))) - 1 downto (64*(80-(t+1))) )
:= w_reg ( (64*(80-(WI1))) - 1 downto (64*(80-(WI1+1))) )
+
W_HASHING_1(
w_reg ( (64*(80-(WI2))) - 1 downto (64*(80-(WI2+1))) )
)
+
w_reg ( (64*(80-(WI3))) - 1 downto (64*(80-(WI3+1))) )
+
W_HASHING_2(
w_reg ( (64*(80-(WI4))) - 1 downto (64*(80-(WI4+1))) )
);
end loop ; -- wordGen
return w_reg;
end generate_w_value;
---------------------
---- GET W VALUE ----
---------------------
function get_w_value (w_register: std_logic_vector (((rounds_number * word_size) - 1 )downto 0);
w_index: integer)
return std_logic_vector is
begin
-- should not be more then 79
assert (w_index > (rounds_number - 1))
report "the value should not be more than 79"
severity warning;
return w_register(((word_size * (rounds_number-w_index)) - 1) downto
(word_size * (rounds_number-(w_index+1))));
end get_w_value;
------------------------------
---- W HASHING FUNCTIONS -----
------------------------------
-- FRIST W HASHING FUNCTION
function W_HASHING_1(word:std_logic_vector(word_size-1 downto 0))
return std_logic_vector is
variable hashedWord1 : std_logic_vector(word_size-1 downto 0);
begin
hash1looping : for i in 0 to hashed_size loop
hashedWord1 := ROTR(word,1) xor ROTR(word,8) xor SHR(word,7);
end loop ; -- hash1looping
return hashedWord1;
end W_HASHING_1;
-- SECOND W HASHING FUNCTION
function W_HASHING_2(word:std_logic_vector(word_size-1 downto 0))
return std_logic_vector is
variable hashedWord2 : std_logic_vector(word_size-1 downto 0);
begin
hash2looping : for i in 1 to hashed_size loop
hashedWord2 := ROTR(word,19) xor ROTR(word,61) xor SHR(word,6);
end loop ; -- hash2looping
return hashedWord2;
end W_HASHING_2;
-------------------------
---- ROTATE Function ----
-------------------------
function ROTR(WORD:std_logic_vector(word_size-1 downto 0);ROUNDS:integer)
return std_logic_vector is
variable ratatedWord: std_logic_vector(word_size-1 downto 0) := WORD;
begin
ROTATELOOP : for i in 1 to ROUNDS loop
ratatedWord := ratatedWord(0) & ratatedWord (word_size-1 downto 1);
end loop ; -- ROTATELOOP
return ratatedWord;
end ROTR;
-------------------------
---- SHR Function ----
-------------------------
function SHR(WORD:std_logic_vector(word_size-1 downto 0);ROUNDS:integer)
return std_logic_vector is
variable shiftedWord: std_logic_vector(word_size-1 downto 0) := WORD;
begin
SHIFTLOOP : for i in 1 to ROUNDS loop
shiftedWord := "0" & shiftedWord (word_size-1 downto 1);
end loop ; -- SHIFTLOOP
return shiftedWord;
end SHR;
---------------------------------
---- SHA384 HASHING Function ----
---------------------------------
function SHA384_HASHING( message:std_logic_vector;
IV: std_logic_vector(hashed_size - 1 downto 0))
return std_logic_vector is
variable block_count : integer :=
get_message_blocks_count(message_padding(message));
variable mblock : std_logic_vector(block_size-1 downto 0);
variable NHash : std_logic_vector(hashed_size-1 downto 0) := IV;
begin
identifier : for i in 0 to (block_count-1) loop
mblock := get_message_block(message_padding(message),i);
NHash := NHash + F_FUNCTION(NHash,mblock);
end loop ; -- identifier
return NHash;
end SHA384_HASHING;
------------------------
---- HMAC FUNCTION -----
------------------------
function HMACSHA384( IV : std_logic_vector (hashed_size-1 downto 0);-- salt
KEY : std_logic_vector;
message :std_logic_vector) -- message size
return std_logic_vector is
variable ipad : std_logic_vector (block_size - 1 downto 0) := ipad_generate(block_size);
variable opad : std_logic_vector (block_size - 1 downto 0) := opad_generate(block_size);
variable Si,So : std_logic_vector (block_size-1 downto 0);
variable kmessage1 : std_logic_vector((block_size + message'length)-1 downto 0);
variable kmessage2 : std_logic_vector ((hashed_size + block_size)-1 downto 0);
variable results1,results2: std_logic_vector((hashed_size -1 ) downto 0);
begin
Si := KEY xor ipad;
So := KEY xor opad;
kmessage1 := Si & message;
results1 := SHA384_HASHING(kmessage1,IV);
kmessage2 := So & results1;
results2 := SHA384_HASHING(kmessage2,IV);
return results2;
end HMACSHA384; -- end of function
-----------------------------
---- GENERATE ipad VALUE ----
-----------------------------
function ipad_generate (block_size: integer)
return std_logic_vector is
variable repeat_times : integer := (block_size/8);
variable final_ipad : std_logic_vector((8 * repeat_times)-1 downto 0);
variable init_ipad : std_logic_vector(7 downto 0) := "00110110";
begin
repeatloop : for i in 0 to (repeat_times-1) loop
final_ipad(((8 * (repeat_times-i))-1) downto ((8 * (repeat_times-(i+1)))))
:= init_ipad;
end loop ; -- repeatloop
return final_ipad;
end ipad_generate;
-----------------------------
---- GENERATE opad VALUE ----
-----------------------------
function opad_generate (block_size: integer)
return std_logic_vector is
variable repeat_times : integer := (block_size/8);
variable final_opad : std_logic_vector((8 * repeat_times)-1 downto 0);
variable init_opad : std_logic_vector(7 downto 0) := "01011100";
begin
repeatloop : for i in 0 to (repeat_times-1) loop
final_opad(((8 * (repeat_times-i))-1) downto ((8 * (repeat_times-(i+1)))))
:= init_opad;
end loop ; -- repeatloop
return final_opad;
end opad_generate;
end HMACSHA384_ISMAIL; --- END OF PACKAGE BODY
--------------------------------------------------------------------------------
--///////////////////// PACKAGE BODY ENDS HERE ///////////////////////////////--
--------------------------------------------------------------------------------
| mit | 0ca8a9c7d7cc2e271b84a0c7ddfd8ca9 | 0.496582 | 3.672388 | false | false | false | false |
kdgwill/VHDL_Verilog_Encryptions_And_Ciphers | VHDL_RC5/Encryption_Decryption/rc5_key.vhd | 1 | 5,346 | --RC5 Round Key Generation
--i=0;j=0;
--do 78 times
----A = S[i] = (S[i] + A + B) <<< 3;
----B = L[j] = (L[j] + A + B) <<< (A + B);
----i = (i + 1) mod 26;
----j = (j + 1) mod 4;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; -- we will use CONV_INTEGER
USE WORK.RC5_PKG.ALL;
entity rc5_key is
port( clr,clk : in std_logic; -- Asynchronous reset and Clock Signal
key : in std_logic_vector(127 downto 0);
key_vld : in std_logic;
skey : out rc5_rom_26;
key_rdy : out std_logic);
end rc5_key;
architecture key_exp of rc5_key is
signal i_cnt : std_logic_vector(04 downto 00); -- s_array counter
signal j_cnt : std_logic_vector(04 downto 00); -- l_array counter
signal r_cnt : std_logic_vector(06 downto 00); -- overall counterer; counts to 78
signal a : std_logic_vector(31 downto 00);
signal a_circ : std_logic_vector(31 downto 00);
signal a_reg : std_logic_vector(31 downto 00); -- register A
signal b : std_logic_vector(31 downto 00);
signal b_circ : std_logic_vector(31 downto 00);
signal b_reg : std_logic_vector(31 downto 00); -- register B
signal temp : std_logic_vector(31 downto 00);
--Key Expansion state machine has five states: idle, key in, expansion and ready
signal state : rc5_key_StateType;
signal l : rc5_rom_4;
signal s : rc5_rom_26;
begin
-- it is not a data-dependent rotation!
--A = S[i] = (S[i] + A + B) <<< 3;
a <= s(conv_integer(i_cnt)) + a_reg + b_reg; --S + A + B
a_circ <= a(28 downto 0) & a(31 downto 29); --rot by 3
-- this is a data-dependent rotation!
--B = L[j] = (L[j] + A + B) <<< (A + B);
b <= l(conv_integer(j_cnt)) + a_circ + b_reg; --L + A + B
-- rot by A + B
temp <= a_circ + b_reg;
ROT_A_LEFT: rotLeft
PORT MAP(din=>b,amnt=>temp(4 DOWNTO 0),dout=>b_circ);--b_circ <<< temp
state_block:
process(clr, clk)
begin
if (clr = '0') then
state <= st_idle;
elsif (rising_edge(clk)) then
case state is
when st_idle =>
if(key_vld = '1') then
state <= st_key_in;
end if;
when st_key_in =>
state <= st_key_exp;
when st_key_exp =>
if (r_cnt = "1001101") then
state <= st_ready;
end if;
when st_ready =>
IF( key_vld='1') THEN -- /= is not equals to
state <= st_key_in; --in event of new key start at key_in
--state otherwise would be a timing issue
--state<=ST_IDLE; --If Input Changes then restart
END IF;
end case;
end if;
end process;
a_reg_block:
process(clr, clk)
begin
if(clr = '0') then
a_reg <= (others => '0');
elsif (rising_edge(clk)) then
if (state = st_key_exp) then
a_reg <= a_circ;
end if;
end if;
end process;
b_reg_block:
process(clr, clk)
begin
if(clr = '0') then
b_reg <= (others => '0');
elsif (rising_edge(clk)) then
if (state = st_key_exp) then
b_reg <= b_circ;
end if;
end if;
end process;
s_array_counter_block:
process(clr, clk)
begin
if(clr='0') then i_cnt<=(others=>'0');
elsif(rising_edge(clk)) then
if(state=ST_KEY_EXP) then
if(i_cnt="11001") then i_cnt <= (others=>'0');
else i_cnt <= i_cnt + 1;
end if;
end if;
end if;
end process;
l_array_counter_block:
process(clr, clk)
begin
if(clr='0') then j_cnt<=(others=>'0');
elsif(rising_edge(clk)) then
if(j_cnt="00011") then j_cnt<=(others=>'0');
else j_cnt <= j_cnt + 1;
end if;
end if;
end process;
overall_counter_block:
process(clr, clk)
begin
if (clr = '0') then
r_cnt <= "0000000";
elsif (rising_edge(clk)) then
if (state = st_key_exp) then
r_cnt <= r_cnt + 1;
end if;
end if;
end process;
--S[0] = 0xB7E15163 (Pw)
--for i=1 to 25 do S[i] = S[i-1]+ 0x9E3779B9 (Qw)
--array s
process(clr, clk)
begin
if (clr = '0') then
s(0) <= X"b7e15163"; s(1) <= X"5618cb1c";s(2) <= X"f45044d5";
s(3) <= X"9287be8e";s(4) <= X"30bf3847";s(5) <= X"cef6b200";
s(6) <= X"6d2e2bb9";s(7) <= X"0b65a572";s(8) <= X"a99d1f2b";
s(9) <= X"47d498e4";s(10) <= X"e60c129d";s(11) <= X"84438c56";
s(12) <= X"227b060f";s(13) <= X"c0b27fc8";s(14) <= X"5ee9f981";
s(15) <= X"fd21733a";s(16) <= X"9b58ecf3";s(17) <= X"399066ac";
s(18) <= X"d7c7e065";s(19) <= X"75ff5a1e";s(20) <= X"1436d3d7";
s(21) <= X"b26e4d90";s(22) <= X"50a5c749";s(23) <= X"eedd4102";
s(24) <= X"8d14babb";s(25) <= X"2b4c3474";
elsif (rising_edge(clk)) then
if (state = st_key_exp) then
s(conv_integer(i_cnt)) <= a_circ;--i = (i + 1) mod 26;
end if;
end if;
end process;
--l array
process(clr, clk)
begin
if(clr = '0') then
l(0) <= (others=>'0');
l(1) <= (others=>'0');
l(2) <= (others=>'0');
l(3) <= (others=>'0');
elsif (rising_edge(clk)) then
if(state = st_key_in) then
l(0) <= key(31 downto 0);
l(1) <= key(63 downto 32);
l(2) <= key(95 downto 64);
l(3) <= key(127 downto 96);
elsif(state = st_key_exp) then
l(conv_integer(j_cnt)) <= b_circ; --j = (j + 1) mod 4;
end if;
end if;
end process;
skey <= s;
with state select
key_rdy <= '1' when st_ready,
'0' when others;
end key_exp; | lgpl-2.1 | 88722842ba2791deeda80dce62eef291 | 0.543584 | 2.469284 | false | false | false | false |
nsauzede/cpu86 | p2_vga_spi/spi_master.vhd | 2 | 7,000 | --+-----------------------------------+-------------------------------------+--
--| ___ ___ | (c) 2013-2014 William R Sowerbutts |--
--| ___ ___ ___ ___( _ ) / _ \ | [email protected] |--
--| / __|/ _ \ / __|_ / _ \| | | | | |--
--| \__ \ (_) | (__ / / (_) | |_| | | A Z80 FPGA computer, just for fun |--
--| |___/\___/ \___/___\___/ \___/ | |--
--| | http://sowerbutts.com/ |--
--+-----------------------------------+-------------------------------------+--
--| A rudimentary SPI master peripheral |--
--+-------------------------------------------------------------------------+--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity spi_master is
port ( clk : in std_logic;
reset : in std_logic;
cpu_address : in std_logic_vector(2 downto 0);
cpu_wait : out std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
enable : in std_logic;
req_read : in std_logic;
req_write : in std_logic;
slave_cs : out std_logic;
slave_clk : out std_logic;
slave_mosi : out std_logic;
slave_miso : in std_logic
);
end spi_master;
-- registers:
-- base+0 -- chip select control; bit 0 is slave_cs
-- base+1 -- status register; bit 0 indicates "transmitter busy"
-- base+2 -- transmitter: write a byte here, starts SPI bus transaction
-- base+3 -- receiver: last byte received (updated on each transation)
-- base+4 -- clock divider: clk counts from 0 to whatever is in this register before proceeding
--
-- Note that if an SPI transfer is underway already the CPU will be
-- forced to wait until it completes before any register can be
-- read or written. This is very convenient as it means you can
-- just read or write bytes without checking the status register.
architecture Behavioral of spi_master is
-- start up in idle state
signal slave_cs_register : std_logic := '1';
signal slave_clk_register : std_logic := '1'; --MODE3
-- signal slave_clk_register : std_logic := '0'; --MODE0
signal slave_mosi_register: std_logic := '0';
signal data_out_sr : std_logic_vector(7 downto 0) := (others => '0'); -- shifted left ie MSB <- LSB
-- signal data_out_sr : std_logic_vector(7 downto 0) := x"55"; -- shifted left ie MSB <- LSB
signal data_in_sr : std_logic_vector(7 downto 0) := (others => '0'); -- shifted left ie MSB <- LSB
signal busy_sr : std_logic_vector(7 downto 0) := (others => '0'); -- shifted left ie MSB <- LSB
signal clk_divide_target : unsigned(7 downto 0) := (others => '0');
-- signal clk_divide_target : unsigned(7 downto 0) := x"aa";
signal clk_divide_value : unsigned(7 downto 0) := (others => '0');
signal cpu_was_idle : std_logic := '1';
-- cpu visible registers
signal chip_select_out : std_logic_vector(7 downto 0);
signal status_data_out : std_logic_vector(7 downto 0);
begin
chip_select_out <= "0000000" & slave_cs_register;
status_data_out <= "0000000" & busy_sr(7);
cpu_wait <= busy_sr(7);
with cpu_address select
data_out <=
chip_select_out when "000",
status_data_out when "001",
data_out_sr when "010",
data_in_sr when "011",
std_logic_vector(clk_divide_target) when "100",
status_data_out when others;
-- data_out <= data_out_sr;
slave_cs <= slave_cs_register;
slave_clk <= slave_clk_register;
slave_mosi <= slave_mosi_register;
spimaster_proc: process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
slave_cs_register <= '1';
slave_clk_register <= '1'; --MODE3
-- slave_clk_register <= '0'; --MODE0
slave_mosi_register <= '0';
data_out_sr <= (others => '0');
-- data_out_sr <= x"aa";
data_in_sr <= (others => '0');
busy_sr <= (others => '0');
clk_divide_target <= (others => '0');
clk_divide_value <= (others => '0');
cpu_was_idle <= '1';
else
-- divide down input clk to get 2 * spi clk
clk_divide_value <= clk_divide_value + 1;
if clk_divide_value = clk_divide_target then
clk_divide_value <= to_unsigned(0, 8);
end if;
if busy_sr(7) = '1' then
if clk_divide_value = clk_divide_target then
-- we're in the midst of a transaction! whoo!
if slave_clk_register = '1' then
-- clk is high; next cycle will be falling edge of clk
slave_clk_register <= '0';
slave_mosi_register <= data_out_sr(7);
-- shift data out
data_out_sr <= data_out_sr(6 downto 0) & '0';
else
-- clk is low; next cycle will be rising edge of clk
slave_clk_register <= '1';
-- shift busy
busy_sr <= busy_sr(6 downto 0) & '0';
-- latch data in
data_in_sr <= data_in_sr(6 downto 0) & slave_miso;
end if;
end if;
end if;
if enable = '1' and req_write = '1' then
if busy_sr(7) = '0' and cpu_was_idle = '1' then
cpu_was_idle <= '0';
case cpu_address is
when "000" =>
slave_cs_register <= data_in(0);
when "010" =>
-- only allow writes when transmitter is idle
data_out_sr <= data_in;
busy_sr <= (others => '1');
when "100" =>
clk_divide_target <= unsigned(data_in);
when others => -- no change
end case;
else
cpu_was_idle <= cpu_was_idle;
end if;
else
cpu_was_idle <= '1';
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | 41971223d40d5db2388364d326ba6d20 | 0.432571 | 4.247573 | false | false | false | false |
VenturaSolutionsInc/VHDL | igmp/checksum.vhd | 1 | 7,667 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.util.all;
entity checksum is
port (
dataClk : in std_logic;
reset : in std_logic;
start_checksum : in std_logic;
multicast_ip : in std_logic_vector(31 downto 0);
source_ip : in std_logic_vector(31 downto 0);
checksum_done : out std_logic;
ipv4_layer_checksum_j : out std_logic_vector(15 downto 0);
ipv4_layer_checksum_l : out std_logic_vector(15 downto 0);
igmp_layer_checksum_j : out std_logic_vector(15 downto 0);
igmp_layer_checksum_l : out std_logic_vector(15 downto 0)
);
end checksum;
architecture rtl of checksum is
type checkSumStateMachine is (init_s, calc_s, done_s);
signal checksum_state : checkSumStateMachine := init_s;
signal igmp_l, igmp_j, igmp_r1, igmp_r2, ipv4_j, ipv4_l, ipv4_r1, ipv4_r2 : unsigned(16 downto 0) := (others => '0');
signal start_checksum_r : std_logic := '0';
signal multicast_ip_r, source_ip_r : std_logic_vector(31 downto 0) := (others => '0');
signal chksum_sub_state : std_logic_vector(2 downto 0) := (others => '0');
-- constant c_ipv4header : std_logic_vector(15 downto 0) := "1000011000011110";
-- constant c_igmpheader_j : std_logic_vector(15 downto 0) := "0001011000000000";
-- constant c_igmpheader_l : std_logic_vector(15 downto 0) := "0001011100000000";
constant c_leaveIP : std_logic_vector(31 downto 0) := X"E0000002";
--signal ipv4_r : std_logic_vector(16 downto 0);
begin -- rtl
register_incoming : process(dataClk, reset)
begin
if(rising_edge(dataClk))then
if(reset = '1')then
start_checksum_r <= '0';
multicast_ip_r <= (others => '0');
source_ip_r <= (others => '0');
else
start_checksum_r <= start_checksum;
multicast_ip_r <= multicast_ip;
source_ip_r <= source_ip;
end if;
end if;
end process;
checksum_state_machine : process(dataClk, reset)
begin
if(rising_edge(dataClk))then
if(reset = '1')then
igmp_l <= (others => '0');
igmp_j <= (others => '0');
igmp_r1 <= (others => '0');
igmp_r2 <= (others => '0');
ipv4_j <= (others => '0');
ipv4_l <= (others => '0');
ipv4_r1 <= (others => '0');
ipv4_r2 <= (others => '0');
ipv4_layer_checksum_j <= (others => '0');
ipv4_layer_checksum_l <= (others => '0');
igmp_layer_checksum_j <= (others => '0');
igmp_layer_checksum_l <= (others => '0');
checksum_done <= '0';
chksum_sub_state <= (others => '0');
checksum_done <= '0';
else
case checksum_state is
when init_s =>
if(start_checksum_r = '1')then
checksum_state <= calc_s;
checksum_done <= '0';
igmp_l <= ('0' & X"1700"); --(others => '0');
igmp_j <= ('0' & X"1600"); --(others => '0');
ipv4_j <= ('0' & X"861E"); --(others => '0');
ipv4_l <= ('0' & X"861E"); --(others => '0');
else
-- checksum_done <= '0';
checksum_state <= init_s;
end if;
when calc_s =>
case chksum_sub_state is
when "000" =>
igmp_r1 <= igmp_j + ('0' & unsigned(multicast_ip_r(31 downto 16)));
igmp_r2 <= igmp_l + ('0' & unsigned(multicast_ip_r(31 downto 16)));
ipv4_r1 <= ipv4_j + ('0' & unsigned(source_ip_r(31 downto 16)));
ipv4_r2 <= ipv4_l + ('0' & unsigned(source_ip_r(31 downto 16)));
chksum_sub_state <= "001";
when "001" =>
igmp_j <= ('0' & igmp_r1(15 downto 0)) + igmp_r1(16);
igmp_l <= ('0' & igmp_r2(15 downto 0)) + igmp_r2(16);
ipv4_j <= ('0' & ipv4_r1(15 downto 0)) + ipv4_r1(16);
ipv4_l <= ('0' & ipv4_r2(15 downto 0)) + ipv4_r2(16);
chksum_sub_state <= "010";
when "010" =>
-- Addition for the carry bit
igmp_r1 <= ('0' & igmp_j(15 downto 0)) + ('0' & unsigned(multicast_ip_r(15 downto 0)));
igmp_r2 <= ('0' & igmp_l(15 downto 0)) + ('0' & unsigned(multicast_ip_r(15 downto 0)));
ipv4_r1 <= ('0' & ipv4_j(15 downto 0)) + ('0' & unsigned(source_ip_r(15 downto 0)));
ipv4_r2 <= ('0' & ipv4_l(15 downto 0)) + ('0' & unsigned(source_ip_r(15 downto 0)));
chksum_sub_state <= "011";
when "011" =>
igmp_j <= ('0' & igmp_r1(15 downto 0))+ igmp_r1(16);
igmp_l <= ('0' & igmp_r2(15 downto 0))+ igmp_r2(16);
ipv4_j <= ('0' & ipv4_r1(15 downto 0)) + ipv4_r1(16);
ipv4_l <= ('0' & ipv4_r2(15 downto 0)) + ipv4_r2(16);
chksum_sub_state <= "100";
when "100" =>
ipv4_r1 <= ('0' & ipv4_j(15 downto 0)) + unsigned(multicast_ip_r(31 downto 16));
ipv4_r2 <= ('0' & ipv4_l(15 downto 0)) + unsigned(c_leaveIP(31 downto 16));
chksum_sub_state <= "101";
when "101" =>
ipv4_j <= ('0' & ipv4_r1(15 downto 0)) + ipv4_r1(16);
ipv4_l <= ('0' & ipv4_r2(15 downto 0)) + ipv4_r2(16);
chksum_sub_state <= "110";
when "110" =>
ipv4_r1 <= ('0' & ipv4_j(15 downto 0)) + unsigned(multicast_ip_r(15 downto 0));
ipv4_r2 <= ('0' & ipv4_l(15 downto 0)) + unsigned(c_leaveIP(15 downto 0));
chksum_sub_state <= "111";
when "111" =>
ipv4_j <= ('0' & ipv4_r1(15 downto 0)) + ipv4_r1(16);
ipv4_l <= ('0' & ipv4_r2(15 downto 0)) + ipv4_r2(16);
chksum_sub_state <= "000";
checksum_state <= done_s;
--when "111" =>
-- ipv4_layer_checksum_j <= std_logic_vector(ipv4);
-- ipv4_layer_checksum_l <= std_logic_vector(ipv4_t);
-- igmp_layer_checksum_j <= std_logic_vector(igmp_j);
-- igmp_layer_checksum_l <= std_logic_vector(igmp_l);
-- checksum_done <= '1';
when others =>
ipv4_layer_checksum_j <= (others => '0');
ipv4_layer_checksum_l <= (others => '0');
igmp_layer_checksum_j <= (others => '0');
igmp_layer_checksum_l <= (others => '0');
checksum_done <= '0';
end case;
when done_s =>
ipv4_layer_checksum_j <= vecInvert(std_logic_vector(ipv4_j(15 downto 0)));
ipv4_layer_checksum_l <= vecInvert(std_logic_vector(ipv4_l(15 downto 0)));
igmp_layer_checksum_j <= vecInvert(std_logic_vector(igmp_j(15 downto 0)));
igmp_layer_checksum_l <= vecInvert(std_logic_vector(igmp_l(15 downto 0)));
checksum_done <= '1';
checksum_state <= init_s;
end case;
end if;
end if;
end process;
end rtl;
| gpl-2.0 | 9b3785201a347f212720e674a2cc5607 | 0.456763 | 3.409071 | false | false | false | false |
kdgwill/VHDL_Verilog_Encryptions_And_Ciphers | VHDL_RC5/Basys2Encryption/rc5_impl/netgen/par/rc5_timesim.vhd | 1 | 543,741 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.20131013
-- \ \ Application: netgen
-- / / Filename: rc5_timesim.vhd
-- /___/ /\ Timestamp: Tue Apr 07 17:38:47 2015
-- \ \ / \
-- \___\/\___\
--
-- Command : -filter C:/SkyDrive/School/Polytechnic/EL6463_AdvancedHardwareDesign/Labs/Lab7/rc5_impl/iseconfig/filter.filter -intstyle ise -s 4 -pcf rc5.pcf -rpw 100 -tpw 0 -ar Structure -tm rc5 -insert_pp_buffers true -w -dir netgen/par -ofmt vhdl -sim rc5.ncd rc5_timesim.vhd
-- Device : 3s100ecp132-4 (PRODUCTION 1.27 2013-10-13)
-- Input file : rc5.ncd
-- Output file : C:\SkyDrive\School\Polytechnic\EL6463_AdvancedHardwareDesign\Labs\Lab7\rc5_impl\netgen\par\rc5_timesim.vhd
-- # of Entities : 1
-- Design Name : rc5
-- Xilinx : C:\Xilinx\14.7\ISE_DS\ISE\
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity rc5 is
port (
clr : in STD_LOGIC := 'X';
segment_e_i : out STD_LOGIC;
do_rdy : out STD_LOGIC;
segment_f_i : out STD_LOGIC;
segment_g_i : out STD_LOGIC;
clk_25 : in STD_LOGIC := 'X';
di_vld : in STD_LOGIC := 'X';
segment_a_i : out STD_LOGIC;
segment_b_i : out STD_LOGIC;
segment_c_i : out STD_LOGIC;
segment_d_i : out STD_LOGIC;
AN : out STD_LOGIC_VECTOR ( 3 downto 0 );
swtch_led : out STD_LOGIC_VECTOR ( 7 downto 0 );
din_lower : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end rc5;
architecture Structure of rc5 is
signal NlwRenamedSig_IO_clr : STD_LOGIC;
signal NlwRenamedSig_IO_di_vld : STD_LOGIC;
signal clk_25_BUFGP : STD_LOGIC;
signal clr_IBUF_3948 : STD_LOGIC;
signal Mcount_LED_flash_cnt_cy_1_Q : STD_LOGIC;
signal Mcount_LED_flash_cnt_cy_3_Q : STD_LOGIC;
signal Mcount_LED_flash_cnt_cy_5_Q : STD_LOGIC;
signal Sh64_0 : STD_LOGIC;
signal Mrom_a_rom0000_0 : STD_LOGIC;
signal Mrom_a_rom00001_0 : STD_LOGIC;
signal Sh33 : STD_LOGIC;
signal Sh49 : STD_LOGIC;
signal Madd_a_cy_1_Q : STD_LOGIC;
signal Mrom_a_rom00002_0 : STD_LOGIC;
signal Sh34 : STD_LOGIC;
signal Sh50 : STD_LOGIC;
signal N224_0 : STD_LOGIC;
signal Sh35 : STD_LOGIC;
signal Sh51 : STD_LOGIC;
signal Madd_a_cy_3_Q : STD_LOGIC;
signal Mrom_a_rom00004_0 : STD_LOGIC;
signal Sh36 : STD_LOGIC;
signal Sh52 : STD_LOGIC;
signal Mrom_a_rom00005_0 : STD_LOGIC;
signal Sh37 : STD_LOGIC;
signal Sh53 : STD_LOGIC;
signal Madd_a_cy_5_Q : STD_LOGIC;
signal Mrom_a_rom00006_0 : STD_LOGIC;
signal Sh38 : STD_LOGIC;
signal Sh54 : STD_LOGIC;
signal N286_0 : STD_LOGIC;
signal Sh55 : STD_LOGIC;
signal Sh39 : STD_LOGIC;
signal Madd_a_cy_7_Q : STD_LOGIC;
signal Mrom_a_rom00008_0 : STD_LOGIC;
signal Sh40 : STD_LOGIC;
signal Sh56 : STD_LOGIC;
signal Mrom_a_rom00009_0 : STD_LOGIC;
signal Sh41 : STD_LOGIC;
signal Sh57 : STD_LOGIC;
signal Madd_a_cy_9_Q : STD_LOGIC;
signal Mrom_a_rom000010_0 : STD_LOGIC;
signal Sh42 : STD_LOGIC;
signal Sh58 : STD_LOGIC;
signal Sh59 : STD_LOGIC;
signal Mrom_a_rom000011_0 : STD_LOGIC;
signal Sh43 : STD_LOGIC;
signal Madd_a_cy_11_Q : STD_LOGIC;
signal Sh60 : STD_LOGIC;
signal N222_0 : STD_LOGIC;
signal Sh44 : STD_LOGIC;
signal Mrom_a_rom000013_0 : STD_LOGIC;
signal Sh45 : STD_LOGIC;
signal Sh61 : STD_LOGIC;
signal Madd_a_cy_13_Q : STD_LOGIC;
signal N226_0 : STD_LOGIC;
signal Sh46 : STD_LOGIC;
signal Sh62 : STD_LOGIC;
signal Sh63 : STD_LOGIC;
signal Mrom_a_rom000015_0 : STD_LOGIC;
signal Sh47 : STD_LOGIC;
signal Madd_a_cy_15_Q : STD_LOGIC;
signal Sh32 : STD_LOGIC;
signal Mrom_a_rom000016_0 : STD_LOGIC;
signal Sh48 : STD_LOGIC;
signal Mrom_a_rom000017_0 : STD_LOGIC;
signal Madd_a_cy_17_Q : STD_LOGIC;
signal Mrom_a_rom000018_0 : STD_LOGIC;
signal Mrom_a_rom000019_0 : STD_LOGIC;
signal Madd_a_cy_19_Q : STD_LOGIC;
signal Sh84_0 : STD_LOGIC;
signal Mrom_a_rom000021_0 : STD_LOGIC;
signal Madd_a_cy_21_Q : STD_LOGIC;
signal N520_0 : STD_LOGIC;
signal Mrom_a_rom000023_0 : STD_LOGIC;
signal Madd_a_cy_23_Q : STD_LOGIC;
signal Mrom_a_rom000024_0 : STD_LOGIC;
signal Mrom_a_rom000025_0 : STD_LOGIC;
signal Madd_a_cy_25_Q : STD_LOGIC;
signal Mrom_a_rom000026_0 : STD_LOGIC;
signal Mrom_a_rom000027_0 : STD_LOGIC;
signal Madd_a_cy_27_Q : STD_LOGIC;
signal N518_0 : STD_LOGIC;
signal Mrom_a_rom000029_0 : STD_LOGIC;
signal Mrom_a_rom000030_0 : STD_LOGIC;
signal Mrom_a_rom000031_0 : STD_LOGIC;
signal Sh160 : STD_LOGIC;
signal Mrom_b_rom0000_0 : STD_LOGIC;
signal Sh145 : STD_LOGIC;
signal Mrom_b_rom00001_0 : STD_LOGIC;
signal Sh129 : STD_LOGIC;
signal b_1_Q : STD_LOGIC;
signal Madd_b_cy_1_Q : STD_LOGIC;
signal Sh162 : STD_LOGIC;
signal N14_0 : STD_LOGIC;
signal N17_0 : STD_LOGIC;
signal Sh163 : STD_LOGIC;
signal N33_0 : STD_LOGIC;
signal N12_0 : STD_LOGIC;
signal i_cnt_mux0001_0_22_4123 : STD_LOGIC;
signal b_2_Q : STD_LOGIC;
signal b_3_Q : STD_LOGIC;
signal Madd_b_cy_3_Q : STD_LOGIC;
signal Sh164 : STD_LOGIC;
signal N20_0 : STD_LOGIC;
signal Mrom_b_rom00005_0 : STD_LOGIC;
signal Sh133 : STD_LOGIC;
signal Sh149 : STD_LOGIC;
signal b_4_Q : STD_LOGIC;
signal b_5_Q : STD_LOGIC;
signal Madd_b_cy_5_Q : STD_LOGIC;
signal Sh150_0 : STD_LOGIC;
signal Mrom_b_rom00006_0 : STD_LOGIC;
signal Sh134 : STD_LOGIC;
signal Sh151 : STD_LOGIC;
signal Mrom_b_rom00007_0 : STD_LOGIC;
signal Sh135 : STD_LOGIC;
signal b_6_Q : STD_LOGIC;
signal b_7_Q : STD_LOGIC;
signal Madd_b_cy_7_Q : STD_LOGIC;
signal Mrom_b_rom00008_0 : STD_LOGIC;
signal Sh136 : STD_LOGIC;
signal Sh152 : STD_LOGIC;
signal Mrom_b_rom00009_0 : STD_LOGIC;
signal Sh137 : STD_LOGIC;
signal Sh153 : STD_LOGIC;
signal Madd_b_cy_9_Q : STD_LOGIC;
signal Sh154_0 : STD_LOGIC;
signal Mrom_b_rom000010_0 : STD_LOGIC;
signal Sh138 : STD_LOGIC;
signal Mrom_b_rom000011_0 : STD_LOGIC;
signal Sh139 : STD_LOGIC;
signal Sh155 : STD_LOGIC;
signal b_11_Q : STD_LOGIC;
signal Madd_b_cy_11_Q : STD_LOGIC;
signal Mrom_b_rom000012_0 : STD_LOGIC;
signal Sh140 : STD_LOGIC;
signal Sh156 : STD_LOGIC;
signal Mrom_b_rom000013_0 : STD_LOGIC;
signal Sh141 : STD_LOGIC;
signal Sh157 : STD_LOGIC;
signal b_12_Q : STD_LOGIC;
signal b_13_Q : STD_LOGIC;
signal Madd_b_cy_13_Q : STD_LOGIC;
signal Sh158 : STD_LOGIC;
signal Mrom_b_rom000014_0 : STD_LOGIC;
signal Sh142 : STD_LOGIC;
signal Sh175 : STD_LOGIC;
signal N522_0 : STD_LOGIC;
signal b_14_Q : STD_LOGIC;
signal b_15_Q : STD_LOGIC;
signal Madd_b_cy_15_Q : STD_LOGIC;
signal Mrom_b_rom000016_0 : STD_LOGIC;
signal Sh144_0 : STD_LOGIC;
signal Sh128 : STD_LOGIC;
signal Mrom_b_rom000017_0 : STD_LOGIC;
signal b_16_Q : STD_LOGIC;
signal b_17_Q : STD_LOGIC;
signal Madd_b_cy_17_Q : STD_LOGIC;
signal Sh178 : STD_LOGIC;
signal N27_0 : STD_LOGIC;
signal N77_0 : STD_LOGIC;
signal N34_0 : STD_LOGIC;
signal Mrom_b_rom000019_0 : STD_LOGIC;
signal Sh147_0 : STD_LOGIC;
signal Sh131 : STD_LOGIC;
signal b_18_Q : STD_LOGIC;
signal b_19_Q : STD_LOGIC;
signal Madd_b_cy_19_Q : STD_LOGIC;
signal Mrom_b_rom000020_0 : STD_LOGIC;
signal Sh148_0 : STD_LOGIC;
signal Sh132 : STD_LOGIC;
signal Mrom_b_rom000021_0 : STD_LOGIC;
signal b_20_Q : STD_LOGIC;
signal b_21_Q : STD_LOGIC;
signal Madd_b_cy_21_Q : STD_LOGIC;
signal Mrom_b_rom000022_0 : STD_LOGIC;
signal Mrom_b_rom000023_0 : STD_LOGIC;
signal b_22_Q : STD_LOGIC;
signal b_23_Q : STD_LOGIC;
signal Madd_b_cy_23_Q : STD_LOGIC;
signal Mrom_b_rom000024_0 : STD_LOGIC;
signal Sh185_0 : STD_LOGIC;
signal N111_0 : STD_LOGIC;
signal b_24_Q : STD_LOGIC;
signal b_25_Q : STD_LOGIC;
signal Madd_b_cy_25_Q : STD_LOGIC;
signal Mrom_b_rom000026_0 : STD_LOGIC;
signal Mrom_b_rom000027_0 : STD_LOGIC;
signal b_26_Q : STD_LOGIC;
signal b_27_Q : STD_LOGIC;
signal Madd_b_cy_27_Q : STD_LOGIC;
signal Mrom_b_rom000028_0 : STD_LOGIC;
signal Mrom_b_rom000029_0 : STD_LOGIC;
signal b_28_Q : STD_LOGIC;
signal b_29_Q : STD_LOGIC;
signal Mrom_b_rom000030_0 : STD_LOGIC;
signal Mrom_b_rom000031_0 : STD_LOGIC;
signal Sh159_0 : STD_LOGIC;
signal Sh143_0 : STD_LOGIC;
signal b_30_Q : STD_LOGIC;
signal b_31_Q : STD_LOGIC;
signal Madd_b_pre_cy_0_Q : STD_LOGIC;
signal swtch_led_1_OBUF_4254 : STD_LOGIC;
signal swtch_led_3_OBUF_4256 : STD_LOGIC;
signal swtch_led_4_OBUF_4257 : STD_LOGIC;
signal swtch_led_5_OBUF_4258 : STD_LOGIC;
signal swtch_led_6_OBUF_4259 : STD_LOGIC;
signal swtch_led_7_OBUF_4260 : STD_LOGIC;
signal AN_0_4261 : STD_LOGIC;
signal AN_1_4262 : STD_LOGIC;
signal AN_2_4263 : STD_LOGIC;
signal AN_3_4264 : STD_LOGIC;
signal di_vld_IBUF_4273 : STD_LOGIC;
signal Sh1212_0 : STD_LOGIC;
signal Sh1232_0 : STD_LOGIC;
signal Sh991_0 : STD_LOGIC;
signal Sh1011 : STD_LOGIC;
signal Sh13120 : STD_LOGIC;
signal Sh125 : STD_LOGIC;
signal Sh121 : STD_LOGIC;
signal Sh101 : STD_LOGIC;
signal Sh97 : STD_LOGIC;
signal Sh100 : STD_LOGIC;
signal Sh96 : STD_LOGIC;
signal Sh108 : STD_LOGIC;
signal Sh104 : STD_LOGIC;
signal Sh109 : STD_LOGIC;
signal Sh105 : STD_LOGIC;
signal Sh102_0 : STD_LOGIC;
signal Sh98_0 : STD_LOGIC;
signal Sh110_0 : STD_LOGIC;
signal Sh106_0 : STD_LOGIC;
signal Sh123 : STD_LOGIC;
signal Sh127 : STD_LOGIC;
signal Sh103_0 : STD_LOGIC;
signal Sh99_0 : STD_LOGIC;
signal Sh1022_0 : STD_LOGIC;
signal Sh1002_0 : STD_LOGIC;
signal Sh1102_0 : STD_LOGIC;
signal Sh1082_0 : STD_LOGIC;
signal Sh14612 : STD_LOGIC;
signal Sh124 : STD_LOGIC;
signal Sh1032_0 : STD_LOGIC;
signal Sh1012_0 : STD_LOGIC;
signal Sh1112_0 : STD_LOGIC;
signal Sh1092_0 : STD_LOGIC;
signal Sh14712 : STD_LOGIC;
signal Sh107 : STD_LOGIC;
signal state_FSM_FFd1_4311 : STD_LOGIC;
signal state_FSM_FFd2_4312 : STD_LOGIC;
signal b_reg_mux0000_10_10_0 : STD_LOGIC;
signal b_reg_0_3_4316 : STD_LOGIC;
signal ab_xor_7_0 : STD_LOGIC;
signal ab_xor_9_0 : STD_LOGIC;
signal Sh10 : STD_LOGIC;
signal b_reg_0_2_4323 : STD_LOGIC;
signal ab_xor_11_0 : STD_LOGIC;
signal ab_xor_12_0 : STD_LOGIC;
signal Sh13 : STD_LOGIC;
signal ab_xor_19_0 : STD_LOGIC;
signal ab_xor_20_0 : STD_LOGIC;
signal Sh21 : STD_LOGIC;
signal ab_xor_13_0 : STD_LOGIC;
signal Sh14 : STD_LOGIC;
signal ab_xor_21_0 : STD_LOGIC;
signal Sh22_4347 : STD_LOGIC;
signal ab_xor_27_0 : STD_LOGIC;
signal ab_xor_29_0 : STD_LOGIC;
signal Sh30 : STD_LOGIC;
signal ab_xor_15_0 : STD_LOGIC;
signal ab_xor_16_0 : STD_LOGIC;
signal Sh17 : STD_LOGIC;
signal ab_xor_23_0 : STD_LOGIC;
signal ab_xor_24_0 : STD_LOGIC;
signal Sh25 : STD_LOGIC;
signal ab_xor_17_0 : STD_LOGIC;
signal Sh18 : STD_LOGIC;
signal ab_xor_25_0 : STD_LOGIC;
signal Sh26 : STD_LOGIC;
signal ab_xor_28_0 : STD_LOGIC;
signal Sh29 : STD_LOGIC;
signal b_reg_2_1_4381 : STD_LOGIC;
signal b_reg_0_1_4382 : STD_LOGIC;
signal b_reg_4_1_4383 : STD_LOGIC;
signal ab_xor_3_0 : STD_LOGIC;
signal Sh4 : STD_LOGIC;
signal ab_xor_5_0 : STD_LOGIC;
signal Sh8 : STD_LOGIC;
signal Sh1262_0 : STD_LOGIC;
signal Sh962_0 : STD_LOGIC;
signal Sh1272_0 : STD_LOGIC;
signal N264_0 : STD_LOGIC;
signal N263_0 : STD_LOGIC;
signal N247_0 : STD_LOGIC;
signal N246_0 : STD_LOGIC;
signal Sh1182_0 : STD_LOGIC;
signal N182_0 : STD_LOGIC;
signal N181_0 : STD_LOGIC;
signal Sh120 : STD_LOGIC;
signal Sh1202_0 : STD_LOGIC;
signal N194_0 : STD_LOGIC;
signal N193_0 : STD_LOGIC;
signal Sh112 : STD_LOGIC;
signal Sh1122_0 : STD_LOGIC;
signal N261_0 : STD_LOGIC;
signal N260_0 : STD_LOGIC;
signal Sh1042_0 : STD_LOGIC;
signal Sh1192_0 : STD_LOGIC;
signal N179_0 : STD_LOGIC;
signal N178_0 : STD_LOGIC;
signal N191_0 : STD_LOGIC;
signal N190_0 : STD_LOGIC;
signal Sh113 : STD_LOGIC;
signal Sh1132_0 : STD_LOGIC;
signal N241_0 : STD_LOGIC;
signal N240_0 : STD_LOGIC;
signal Sh1052_0 : STD_LOGIC;
signal Sh1222_0 : STD_LOGIC;
signal N176_0 : STD_LOGIC;
signal N175_0 : STD_LOGIC;
signal Sh1242_0 : STD_LOGIC;
signal Sh1142_0 : STD_LOGIC;
signal N188_0 : STD_LOGIC;
signal N187_0 : STD_LOGIC;
signal Sh116 : STD_LOGIC;
signal Sh1162_0 : STD_LOGIC;
signal Sh1062_0 : STD_LOGIC;
signal N258_0 : STD_LOGIC;
signal N257_0 : STD_LOGIC;
signal N173_0 : STD_LOGIC;
signal N172_0 : STD_LOGIC;
signal Sh1252_0 : STD_LOGIC;
signal Sh1152_0 : STD_LOGIC;
signal N185_0 : STD_LOGIC;
signal N184_0 : STD_LOGIC;
signal Sh117 : STD_LOGIC;
signal Sh1172_0 : STD_LOGIC;
signal Sh1072_0 : STD_LOGIC;
signal N235_0 : STD_LOGIC;
signal N234_0 : STD_LOGIC;
signal Sh3 : STD_LOGIC;
signal ab_xor_4_0 : STD_LOGIC;
signal Sh7 : STD_LOGIC;
signal ab_xor_8_0 : STD_LOGIC;
signal Sh11 : STD_LOGIC;
signal Sh15 : STD_LOGIC;
signal Sh23_4457 : STD_LOGIC;
signal ab_xor_31_0 : STD_LOGIC;
signal Sh31 : STD_LOGIC;
signal Sh19 : STD_LOGIC;
signal Sh27 : STD_LOGIC;
signal Sh12 : STD_LOGIC;
signal Sh20 : STD_LOGIC;
signal Sh16 : STD_LOGIC;
signal Sh24 : STD_LOGIC;
signal Sh28 : STD_LOGIC;
signal N200 : STD_LOGIC;
signal N199_0 : STD_LOGIC;
signal N197 : STD_LOGIC;
signal N196_0 : STD_LOGIC;
signal Sh : STD_LOGIC;
signal b_reg_mux0000_2_5_0 : STD_LOGIC;
signal b_reg_mux0000_2_13_0 : STD_LOGIC;
signal N291 : STD_LOGIC;
signal N292 : STD_LOGIC;
signal Madd_b_pre_cy_2_Q : STD_LOGIC;
signal N281 : STD_LOGIC;
signal N282 : STD_LOGIC;
signal b_reg_mux0000_4_3_0 : STD_LOGIC;
signal b_reg_mux0000_4_12_0 : STD_LOGIC;
signal N278 : STD_LOGIC;
signal N279 : STD_LOGIC;
signal Sh1307 : STD_LOGIC;
signal Sh14416_4486 : STD_LOGIC;
signal Sh14412_0 : STD_LOGIC;
signal Sh14413_0 : STD_LOGIC;
signal Sh12813_0 : STD_LOGIC;
signal Sh1287_0 : STD_LOGIC;
signal Sh12816_0 : STD_LOGIC;
signal Sh1507 : STD_LOGIC;
signal Sh982_4493 : STD_LOGIC;
signal Sh13820 : STD_LOGIC;
signal Sh1517 : STD_LOGIC;
signal Sh14613_0 : STD_LOGIC;
signal Sh14616_0 : STD_LOGIC;
signal Sh13013_0 : STD_LOGIC;
signal Sh13016_0 : STD_LOGIC;
signal Sh14713_4500 : STD_LOGIC;
signal Sh14716_4501 : STD_LOGIC;
signal Sh1310_0 : STD_LOGIC;
signal Sh1313 : STD_LOGIC;
signal Sh1487_4504 : STD_LOGIC;
signal Sh14816_0 : STD_LOGIC;
signal Sh14813_0 : STD_LOGIC;
signal Sh13220_0 : STD_LOGIC;
signal Sh5 : STD_LOGIC;
signal Sh1 : STD_LOGIC;
signal Sh9 : STD_LOGIC;
signal Sh1547 : STD_LOGIC;
signal Sh13420 : STD_LOGIC;
signal Sh1557 : STD_LOGIC;
signal Sh6 : STD_LOGIC;
signal Sh2 : STD_LOGIC;
signal Sh1597 : STD_LOGIC;
signal Sh14313_0 : STD_LOGIC;
signal Sh14316_4518 : STD_LOGIC;
signal Sh1437_0 : STD_LOGIC;
signal Sh1587 : STD_LOGIC;
signal Madd_b_pre_cy_4_0 : STD_LOGIC;
signal N275 : STD_LOGIC;
signal N276 : STD_LOGIC;
signal b_reg_mux0000_6_3_0 : STD_LOGIC;
signal b_reg_mux0000_6_12_0 : STD_LOGIC;
signal N272 : STD_LOGIC;
signal N273 : STD_LOGIC;
signal Madd_b_pre_cy_6_Q : STD_LOGIC;
signal N269 : STD_LOGIC;
signal N270 : STD_LOGIC;
signal b_reg_mux0000_0_Q : STD_LOGIC;
signal N266 : STD_LOGIC;
signal N267 : STD_LOGIC;
signal i_cnt_mux0001_0_25_0 : STD_LOGIC;
signal N514_0 : STD_LOGIC;
signal Sh15013_0 : STD_LOGIC;
signal Sh15016_O : STD_LOGIC;
signal Sh15413_0 : STD_LOGIC;
signal Sh15416_O : STD_LOGIC;
signal Sh5720_0 : STD_LOGIC;
signal Sh5320_0 : STD_LOGIC;
signal Sh5820_0 : STD_LOGIC;
signal Sh5420_0 : STD_LOGIC;
signal Sh337_0 : STD_LOGIC;
signal Sh347_0 : STD_LOGIC;
signal N249_0 : STD_LOGIC;
signal Mxor_ba_xor_Result_5_1_SW1_O : STD_LOGIC;
signal N243_0 : STD_LOGIC;
signal Mxor_ba_xor_Result_13_1_SW1_O : STD_LOGIC;
signal N231_0 : STD_LOGIC;
signal Mxor_ba_xor_Result_7_1_SW1_O : STD_LOGIC;
signal N254_0 : STD_LOGIC;
signal Mxor_ba_xor_Result_15_1_SW1_O : STD_LOGIC;
signal N228_0 : STD_LOGIC;
signal Mxor_ba_xor_Result_9_1_SW1_O : STD_LOGIC;
signal N237_0 : STD_LOGIC;
signal Mxor_ba_xor_Result_17_1_SW1_O : STD_LOGIC;
signal N217_0 : STD_LOGIC;
signal Mxor_ba_xor_Result_25_1_SW1_O : STD_LOGIC;
signal N211_0 : STD_LOGIC;
signal Mxor_ba_xor_Result_11_1_SW1_O : STD_LOGIC;
signal N251_0 : STD_LOGIC;
signal Mxor_ba_xor_Result_19_1_SW1_O : STD_LOGIC;
signal N205_0 : STD_LOGIC;
signal Mxor_ba_xor_Result_21_1_SW1_O : STD_LOGIC;
signal N214_0 : STD_LOGIC;
signal Mxor_ba_xor_Result_29_1_SW1_O : STD_LOGIC;
signal N208_0 : STD_LOGIC;
signal Mxor_ba_xor_Result_23_1_SW1_O : STD_LOGIC;
signal N202_0 : STD_LOGIC;
signal Sh12913_0 : STD_LOGIC;
signal Sh1297_0 : STD_LOGIC;
signal Sh12916_0 : STD_LOGIC;
signal Sh15513_0 : STD_LOGIC;
signal Sh15516_0 : STD_LOGIC;
signal Sh1567_0 : STD_LOGIC;
signal Sh1497_0 : STD_LOGIC;
signal Sh1537_0 : STD_LOGIC;
signal Sh1577_0 : STD_LOGIC;
signal Sh15813_0 : STD_LOGIC;
signal Sh15816_0 : STD_LOGIC;
signal Sh15113_0 : STD_LOGIC;
signal Sh15116_0 : STD_LOGIC;
signal Sh1527_0 : STD_LOGIC;
signal b_reg_3_1_4597 : STD_LOGIC;
signal N289_0 : STD_LOGIC;
signal N288_0 : STD_LOGIC;
signal N516 : STD_LOGIC;
signal state_cmp_eq0000 : STD_LOGIC;
signal LED_flash_cnt_0_DXMUX_4658 : STD_LOGIC;
signal LED_flash_cnt_0_XORF_4656 : STD_LOGIC;
signal LED_flash_cnt_0_LOGIC_ONE_4655 : STD_LOGIC;
signal LED_flash_cnt_0_CYINIT_4654 : STD_LOGIC;
signal LED_flash_cnt_0_CYSELF_4645 : STD_LOGIC;
signal LED_flash_cnt_0_BXINV_4643 : STD_LOGIC;
signal LED_flash_cnt_0_DYMUX_4636 : STD_LOGIC;
signal LED_flash_cnt_0_XORG_4634 : STD_LOGIC;
signal LED_flash_cnt_0_CYMUXG_4633 : STD_LOGIC;
signal Mcount_LED_flash_cnt_cy_0_Q : STD_LOGIC;
signal LED_flash_cnt_0_LOGIC_ZERO_4631 : STD_LOGIC;
signal LED_flash_cnt_0_CYSELG_4622 : STD_LOGIC;
signal LED_flash_cnt_0_G : STD_LOGIC;
signal LED_flash_cnt_0_SRINV_4620 : STD_LOGIC;
signal LED_flash_cnt_0_CLKINV_4619 : STD_LOGIC;
signal LED_flash_cnt_2_DXMUX_4714 : STD_LOGIC;
signal LED_flash_cnt_2_XORF_4712 : STD_LOGIC;
signal LED_flash_cnt_2_CYINIT_4711 : STD_LOGIC;
signal LED_flash_cnt_2_F : STD_LOGIC;
signal LED_flash_cnt_2_DYMUX_4695 : STD_LOGIC;
signal LED_flash_cnt_2_XORG_4693 : STD_LOGIC;
signal Mcount_LED_flash_cnt_cy_2_Q : STD_LOGIC;
signal LED_flash_cnt_2_CYSELF_4691 : STD_LOGIC;
signal LED_flash_cnt_2_CYMUXFAST_4690 : STD_LOGIC;
signal LED_flash_cnt_2_CYAND_4689 : STD_LOGIC;
signal LED_flash_cnt_2_FASTCARRY_4688 : STD_LOGIC;
signal LED_flash_cnt_2_CYMUXG2_4687 : STD_LOGIC;
signal LED_flash_cnt_2_CYMUXF2_4686 : STD_LOGIC;
signal LED_flash_cnt_2_LOGIC_ZERO_4685 : STD_LOGIC;
signal LED_flash_cnt_2_CYSELG_4676 : STD_LOGIC;
signal LED_flash_cnt_2_G : STD_LOGIC;
signal LED_flash_cnt_2_SRINV_4674 : STD_LOGIC;
signal LED_flash_cnt_2_CLKINV_4673 : STD_LOGIC;
signal LED_flash_cnt_4_FFY_RST : STD_LOGIC;
signal LED_flash_cnt_4_DXMUX_4770 : STD_LOGIC;
signal LED_flash_cnt_4_XORF_4768 : STD_LOGIC;
signal LED_flash_cnt_4_CYINIT_4767 : STD_LOGIC;
signal LED_flash_cnt_4_F : STD_LOGIC;
signal LED_flash_cnt_4_DYMUX_4751 : STD_LOGIC;
signal LED_flash_cnt_4_XORG_4749 : STD_LOGIC;
signal Mcount_LED_flash_cnt_cy_4_Q : STD_LOGIC;
signal LED_flash_cnt_4_CYSELF_4747 : STD_LOGIC;
signal LED_flash_cnt_4_CYMUXFAST_4746 : STD_LOGIC;
signal LED_flash_cnt_4_CYAND_4745 : STD_LOGIC;
signal LED_flash_cnt_4_FASTCARRY_4744 : STD_LOGIC;
signal LED_flash_cnt_4_CYMUXG2_4743 : STD_LOGIC;
signal LED_flash_cnt_4_CYMUXF2_4742 : STD_LOGIC;
signal LED_flash_cnt_4_LOGIC_ZERO_4741 : STD_LOGIC;
signal LED_flash_cnt_4_CYSELG_4732 : STD_LOGIC;
signal LED_flash_cnt_4_G : STD_LOGIC;
signal LED_flash_cnt_4_SRINV_4730 : STD_LOGIC;
signal LED_flash_cnt_4_CLKINV_4729 : STD_LOGIC;
signal LED_flash_cnt_6_DXMUX_4826 : STD_LOGIC;
signal LED_flash_cnt_6_XORF_4824 : STD_LOGIC;
signal LED_flash_cnt_6_CYINIT_4823 : STD_LOGIC;
signal LED_flash_cnt_6_F : STD_LOGIC;
signal LED_flash_cnt_6_DYMUX_4807 : STD_LOGIC;
signal LED_flash_cnt_6_XORG_4805 : STD_LOGIC;
signal Mcount_LED_flash_cnt_cy_6_Q : STD_LOGIC;
signal LED_flash_cnt_6_CYSELF_4803 : STD_LOGIC;
signal LED_flash_cnt_6_CYMUXFAST_4802 : STD_LOGIC;
signal LED_flash_cnt_6_CYAND_4801 : STD_LOGIC;
signal LED_flash_cnt_6_FASTCARRY_4800 : STD_LOGIC;
signal LED_flash_cnt_6_CYMUXG2_4799 : STD_LOGIC;
signal LED_flash_cnt_6_CYMUXF2_4798 : STD_LOGIC;
signal LED_flash_cnt_6_LOGIC_ZERO_4797 : STD_LOGIC;
signal LED_flash_cnt_6_CYSELG_4788 : STD_LOGIC;
signal LED_flash_cnt_6_G : STD_LOGIC;
signal LED_flash_cnt_6_SRINV_4786 : STD_LOGIC;
signal LED_flash_cnt_6_CLKINV_4785 : STD_LOGIC;
signal LED_flash_cnt_8_DXMUX_4875 : STD_LOGIC;
signal LED_flash_cnt_8_XORF_4873 : STD_LOGIC;
signal LED_flash_cnt_8_LOGIC_ZERO_4872 : STD_LOGIC;
signal LED_flash_cnt_8_CYINIT_4871 : STD_LOGIC;
signal LED_flash_cnt_8_CYSELF_4862 : STD_LOGIC;
signal LED_flash_cnt_8_F : STD_LOGIC;
signal LED_flash_cnt_8_DYMUX_4854 : STD_LOGIC;
signal LED_flash_cnt_8_XORG_4852 : STD_LOGIC;
signal Mcount_LED_flash_cnt_cy_8_Q : STD_LOGIC;
signal LED_flash_cnt_9_rt_4849 : STD_LOGIC;
signal LED_flash_cnt_8_SRINV_4841 : STD_LOGIC;
signal LED_flash_cnt_8_CLKINV_4840 : STD_LOGIC;
signal a_0_XORF_4918 : STD_LOGIC;
signal a_0_CYINIT_4917 : STD_LOGIC;
signal a_0_CY0F_4916 : STD_LOGIC;
signal a_0_CYSELF_4908 : STD_LOGIC;
signal a_0_BXINV_4906 : STD_LOGIC;
signal a_0_XORG_4904 : STD_LOGIC;
signal a_0_CYMUXG_4903 : STD_LOGIC;
signal Madd_a_cy_0_Q : STD_LOGIC;
signal a_0_CY0G_4901 : STD_LOGIC;
signal a_0_CYSELG_4895 : STD_LOGIC;
signal a_2_XORF_4961 : STD_LOGIC;
signal a_2_CYINIT_4960 : STD_LOGIC;
signal a_2_CY0F_4959 : STD_LOGIC;
signal a_2_XORG_4950 : STD_LOGIC;
signal Madd_a_cy_2_Q : STD_LOGIC;
signal a_2_CYSELF_4948 : STD_LOGIC;
signal a_2_CYMUXFAST_4947 : STD_LOGIC;
signal a_2_CYAND_4946 : STD_LOGIC;
signal a_2_FASTCARRY_4945 : STD_LOGIC;
signal a_2_CYMUXG2_4944 : STD_LOGIC;
signal a_2_CYMUXF2_4943 : STD_LOGIC;
signal a_2_CY0G_4942 : STD_LOGIC;
signal a_2_CYSELG_4936 : STD_LOGIC;
signal a_4_XORF_5004 : STD_LOGIC;
signal a_4_CYINIT_5003 : STD_LOGIC;
signal a_4_CY0F_5002 : STD_LOGIC;
signal a_4_XORG_4993 : STD_LOGIC;
signal Madd_a_cy_4_Q : STD_LOGIC;
signal a_4_CYSELF_4991 : STD_LOGIC;
signal a_4_CYMUXFAST_4990 : STD_LOGIC;
signal a_4_CYAND_4989 : STD_LOGIC;
signal a_4_FASTCARRY_4988 : STD_LOGIC;
signal a_4_CYMUXG2_4987 : STD_LOGIC;
signal a_4_CYMUXF2_4986 : STD_LOGIC;
signal a_4_CY0G_4985 : STD_LOGIC;
signal a_4_CYSELG_4979 : STD_LOGIC;
signal a_6_XORF_5047 : STD_LOGIC;
signal a_6_CYINIT_5046 : STD_LOGIC;
signal a_6_CY0F_5045 : STD_LOGIC;
signal a_6_XORG_5036 : STD_LOGIC;
signal Madd_a_cy_6_Q : STD_LOGIC;
signal a_6_CYSELF_5034 : STD_LOGIC;
signal a_6_CYMUXFAST_5033 : STD_LOGIC;
signal a_6_CYAND_5032 : STD_LOGIC;
signal a_6_FASTCARRY_5031 : STD_LOGIC;
signal a_6_CYMUXG2_5030 : STD_LOGIC;
signal a_6_CYMUXF2_5029 : STD_LOGIC;
signal a_6_CY0G_5028 : STD_LOGIC;
signal a_6_CYSELG_5022 : STD_LOGIC;
signal a_8_XORF_5090 : STD_LOGIC;
signal a_8_CYINIT_5089 : STD_LOGIC;
signal a_8_CY0F_5088 : STD_LOGIC;
signal a_8_XORG_5079 : STD_LOGIC;
signal Madd_a_cy_8_Q : STD_LOGIC;
signal a_8_CYSELF_5077 : STD_LOGIC;
signal a_8_CYMUXFAST_5076 : STD_LOGIC;
signal a_8_CYAND_5075 : STD_LOGIC;
signal a_8_FASTCARRY_5074 : STD_LOGIC;
signal a_8_CYMUXG2_5073 : STD_LOGIC;
signal a_8_CYMUXF2_5072 : STD_LOGIC;
signal a_8_CY0G_5071 : STD_LOGIC;
signal a_8_CYSELG_5065 : STD_LOGIC;
signal a_10_XORF_5133 : STD_LOGIC;
signal a_10_CYINIT_5132 : STD_LOGIC;
signal a_10_CY0F_5131 : STD_LOGIC;
signal a_10_XORG_5122 : STD_LOGIC;
signal Madd_a_cy_10_Q : STD_LOGIC;
signal a_10_CYSELF_5120 : STD_LOGIC;
signal a_10_CYMUXFAST_5119 : STD_LOGIC;
signal a_10_CYAND_5118 : STD_LOGIC;
signal a_10_FASTCARRY_5117 : STD_LOGIC;
signal a_10_CYMUXG2_5116 : STD_LOGIC;
signal a_10_CYMUXF2_5115 : STD_LOGIC;
signal a_10_CY0G_5114 : STD_LOGIC;
signal a_10_CYSELG_5108 : STD_LOGIC;
signal a_12_XORF_5176 : STD_LOGIC;
signal a_12_CYINIT_5175 : STD_LOGIC;
signal a_12_CY0F_5174 : STD_LOGIC;
signal a_12_XORG_5165 : STD_LOGIC;
signal Madd_a_cy_12_Q : STD_LOGIC;
signal a_12_CYSELF_5163 : STD_LOGIC;
signal a_12_CYMUXFAST_5162 : STD_LOGIC;
signal a_12_CYAND_5161 : STD_LOGIC;
signal a_12_FASTCARRY_5160 : STD_LOGIC;
signal a_12_CYMUXG2_5159 : STD_LOGIC;
signal a_12_CYMUXF2_5158 : STD_LOGIC;
signal a_12_CY0G_5157 : STD_LOGIC;
signal a_12_CYSELG_5151 : STD_LOGIC;
signal a_14_XORF_5219 : STD_LOGIC;
signal a_14_CYINIT_5218 : STD_LOGIC;
signal a_14_CY0F_5217 : STD_LOGIC;
signal a_14_XORG_5208 : STD_LOGIC;
signal Madd_a_cy_14_Q : STD_LOGIC;
signal a_14_CYSELF_5206 : STD_LOGIC;
signal a_14_CYMUXFAST_5205 : STD_LOGIC;
signal a_14_CYAND_5204 : STD_LOGIC;
signal a_14_FASTCARRY_5203 : STD_LOGIC;
signal a_14_CYMUXG2_5202 : STD_LOGIC;
signal a_14_CYMUXF2_5201 : STD_LOGIC;
signal a_14_CY0G_5200 : STD_LOGIC;
signal a_14_CYSELG_5194 : STD_LOGIC;
signal a_16_XORF_5262 : STD_LOGIC;
signal a_16_CYINIT_5261 : STD_LOGIC;
signal a_16_CY0F_5260 : STD_LOGIC;
signal a_16_XORG_5251 : STD_LOGIC;
signal Madd_a_cy_16_Q : STD_LOGIC;
signal a_16_CYSELF_5249 : STD_LOGIC;
signal a_16_CYMUXFAST_5248 : STD_LOGIC;
signal a_16_CYAND_5247 : STD_LOGIC;
signal a_16_FASTCARRY_5246 : STD_LOGIC;
signal a_16_CYMUXG2_5245 : STD_LOGIC;
signal a_16_CYMUXF2_5244 : STD_LOGIC;
signal a_16_CY0G_5243 : STD_LOGIC;
signal a_16_CYSELG_5237 : STD_LOGIC;
signal a_18_XORF_5305 : STD_LOGIC;
signal a_18_CYINIT_5304 : STD_LOGIC;
signal a_18_CY0F_5303 : STD_LOGIC;
signal a_18_XORG_5294 : STD_LOGIC;
signal Madd_a_cy_18_Q : STD_LOGIC;
signal a_18_CYSELF_5292 : STD_LOGIC;
signal a_18_CYMUXFAST_5291 : STD_LOGIC;
signal a_18_CYAND_5290 : STD_LOGIC;
signal a_18_FASTCARRY_5289 : STD_LOGIC;
signal a_18_CYMUXG2_5288 : STD_LOGIC;
signal a_18_CYMUXF2_5287 : STD_LOGIC;
signal a_18_CY0G_5286 : STD_LOGIC;
signal a_18_CYSELG_5280 : STD_LOGIC;
signal a_20_XORF_5346 : STD_LOGIC;
signal a_20_CYINIT_5345 : STD_LOGIC;
signal a_20_CY0F_5344 : STD_LOGIC;
signal a_20_XORG_5336 : STD_LOGIC;
signal Madd_a_cy_20_Q : STD_LOGIC;
signal a_20_CYSELF_5334 : STD_LOGIC;
signal a_20_CYMUXFAST_5333 : STD_LOGIC;
signal a_20_CYAND_5332 : STD_LOGIC;
signal a_20_FASTCARRY_5331 : STD_LOGIC;
signal a_20_CYMUXG2_5330 : STD_LOGIC;
signal a_20_CYMUXF2_5329 : STD_LOGIC;
signal a_20_CY0G_5328 : STD_LOGIC;
signal a_20_CYSELG_5322 : STD_LOGIC;
signal a_22_XORF_5389 : STD_LOGIC;
signal a_22_CYINIT_5388 : STD_LOGIC;
signal a_22_CY0F_5387 : STD_LOGIC;
signal a_22_XORG_5378 : STD_LOGIC;
signal Madd_a_cy_22_Q : STD_LOGIC;
signal a_22_CYSELF_5376 : STD_LOGIC;
signal a_22_CYMUXFAST_5375 : STD_LOGIC;
signal a_22_CYAND_5374 : STD_LOGIC;
signal a_22_FASTCARRY_5373 : STD_LOGIC;
signal a_22_CYMUXG2_5372 : STD_LOGIC;
signal a_22_CYMUXF2_5371 : STD_LOGIC;
signal a_22_CY0G_5370 : STD_LOGIC;
signal a_22_CYSELG_5364 : STD_LOGIC;
signal a_24_XORF_5432 : STD_LOGIC;
signal a_24_CYINIT_5431 : STD_LOGIC;
signal a_24_CY0F_5430 : STD_LOGIC;
signal a_24_XORG_5421 : STD_LOGIC;
signal Madd_a_cy_24_Q : STD_LOGIC;
signal a_24_CYSELF_5419 : STD_LOGIC;
signal a_24_CYMUXFAST_5418 : STD_LOGIC;
signal a_24_CYAND_5417 : STD_LOGIC;
signal a_24_FASTCARRY_5416 : STD_LOGIC;
signal a_24_CYMUXG2_5415 : STD_LOGIC;
signal a_24_CYMUXF2_5414 : STD_LOGIC;
signal a_24_CY0G_5413 : STD_LOGIC;
signal a_24_CYSELG_5407 : STD_LOGIC;
signal a_26_XORF_5475 : STD_LOGIC;
signal a_26_CYINIT_5474 : STD_LOGIC;
signal a_26_CY0F_5473 : STD_LOGIC;
signal a_26_XORG_5464 : STD_LOGIC;
signal Madd_a_cy_26_Q : STD_LOGIC;
signal a_26_CYSELF_5462 : STD_LOGIC;
signal a_26_CYMUXFAST_5461 : STD_LOGIC;
signal a_26_CYAND_5460 : STD_LOGIC;
signal a_26_FASTCARRY_5459 : STD_LOGIC;
signal a_26_CYMUXG2_5458 : STD_LOGIC;
signal a_26_CYMUXF2_5457 : STD_LOGIC;
signal a_26_CY0G_5456 : STD_LOGIC;
signal a_26_CYSELG_5450 : STD_LOGIC;
signal a_28_XORF_5518 : STD_LOGIC;
signal a_28_CYINIT_5517 : STD_LOGIC;
signal a_28_CY0F_5516 : STD_LOGIC;
signal a_28_XORG_5507 : STD_LOGIC;
signal Madd_a_cy_28_Q : STD_LOGIC;
signal a_28_CYSELF_5505 : STD_LOGIC;
signal a_28_CYMUXFAST_5504 : STD_LOGIC;
signal a_28_CYAND_5503 : STD_LOGIC;
signal a_28_FASTCARRY_5502 : STD_LOGIC;
signal a_28_CYMUXG2_5501 : STD_LOGIC;
signal a_28_CYMUXF2_5500 : STD_LOGIC;
signal a_28_CY0G_5499 : STD_LOGIC;
signal a_28_CYSELG_5493 : STD_LOGIC;
signal a_30_XORF_5551 : STD_LOGIC;
signal a_30_CYINIT_5550 : STD_LOGIC;
signal a_30_CY0F_5549 : STD_LOGIC;
signal a_30_CYSELF_5543 : STD_LOGIC;
signal a_30_XORG_5539 : STD_LOGIC;
signal Madd_a_cy_30_Q : STD_LOGIC;
signal b_0_XORF_5589 : STD_LOGIC;
signal b_0_CYINIT_5588 : STD_LOGIC;
signal b_0_CY0F_5587 : STD_LOGIC;
signal b_0_CYSELF_5579 : STD_LOGIC;
signal b_0_BXINV_5577 : STD_LOGIC;
signal b_0_XORG_5575 : STD_LOGIC;
signal b_0_CYMUXG_5574 : STD_LOGIC;
signal Madd_b_cy_0_Q : STD_LOGIC;
signal b_0_CY0G_5572 : STD_LOGIC;
signal b_0_CYSELG_5566 : STD_LOGIC;
signal b_2_XORF_5628 : STD_LOGIC;
signal b_2_CYINIT_5627 : STD_LOGIC;
signal b_2_CY0F_5626 : STD_LOGIC;
signal b_2_XORG_5618 : STD_LOGIC;
signal Madd_b_cy_2_Q : STD_LOGIC;
signal b_2_CYSELF_5616 : STD_LOGIC;
signal b_2_CYMUXFAST_5615 : STD_LOGIC;
signal b_2_CYAND_5614 : STD_LOGIC;
signal b_2_FASTCARRY_5613 : STD_LOGIC;
signal b_2_CYMUXG2_5612 : STD_LOGIC;
signal b_2_CYMUXF2_5611 : STD_LOGIC;
signal b_2_CY0G_5610 : STD_LOGIC;
signal b_2_CYSELG_5604 : STD_LOGIC;
signal b_4_XORF_5669 : STD_LOGIC;
signal b_4_CYINIT_5668 : STD_LOGIC;
signal b_4_CY0F_5667 : STD_LOGIC;
signal b_4_XORG_5658 : STD_LOGIC;
signal Madd_b_cy_4_Q : STD_LOGIC;
signal b_4_CYSELF_5656 : STD_LOGIC;
signal b_4_CYMUXFAST_5655 : STD_LOGIC;
signal b_4_CYAND_5654 : STD_LOGIC;
signal b_4_FASTCARRY_5653 : STD_LOGIC;
signal b_4_CYMUXG2_5652 : STD_LOGIC;
signal b_4_CYMUXF2_5651 : STD_LOGIC;
signal b_4_CY0G_5650 : STD_LOGIC;
signal b_4_CYSELG_5644 : STD_LOGIC;
signal b_6_XORF_5712 : STD_LOGIC;
signal b_6_CYINIT_5711 : STD_LOGIC;
signal b_6_CY0F_5710 : STD_LOGIC;
signal b_6_XORG_5701 : STD_LOGIC;
signal Madd_b_cy_6_Q : STD_LOGIC;
signal b_6_CYSELF_5699 : STD_LOGIC;
signal b_6_CYMUXFAST_5698 : STD_LOGIC;
signal b_6_CYAND_5697 : STD_LOGIC;
signal b_6_FASTCARRY_5696 : STD_LOGIC;
signal b_6_CYMUXG2_5695 : STD_LOGIC;
signal b_6_CYMUXF2_5694 : STD_LOGIC;
signal b_6_CY0G_5693 : STD_LOGIC;
signal b_6_CYSELG_5687 : STD_LOGIC;
signal b_8_XORF_5755 : STD_LOGIC;
signal b_8_CYINIT_5754 : STD_LOGIC;
signal b_8_CY0F_5753 : STD_LOGIC;
signal b_8_XORG_5744 : STD_LOGIC;
signal Madd_b_cy_8_Q : STD_LOGIC;
signal b_8_CYSELF_5742 : STD_LOGIC;
signal b_8_CYMUXFAST_5741 : STD_LOGIC;
signal b_8_CYAND_5740 : STD_LOGIC;
signal b_8_FASTCARRY_5739 : STD_LOGIC;
signal b_8_CYMUXG2_5738 : STD_LOGIC;
signal b_8_CYMUXF2_5737 : STD_LOGIC;
signal b_8_CY0G_5736 : STD_LOGIC;
signal b_8_CYSELG_5730 : STD_LOGIC;
signal b_10_XORF_5798 : STD_LOGIC;
signal b_10_CYINIT_5797 : STD_LOGIC;
signal b_10_CY0F_5796 : STD_LOGIC;
signal b_10_XORG_5787 : STD_LOGIC;
signal Madd_b_cy_10_Q : STD_LOGIC;
signal b_10_CYSELF_5785 : STD_LOGIC;
signal b_10_CYMUXFAST_5784 : STD_LOGIC;
signal b_10_CYAND_5783 : STD_LOGIC;
signal b_10_FASTCARRY_5782 : STD_LOGIC;
signal b_10_CYMUXG2_5781 : STD_LOGIC;
signal b_10_CYMUXF2_5780 : STD_LOGIC;
signal b_10_CY0G_5779 : STD_LOGIC;
signal b_10_CYSELG_5773 : STD_LOGIC;
signal b_12_XORF_5841 : STD_LOGIC;
signal b_12_CYINIT_5840 : STD_LOGIC;
signal b_12_CY0F_5839 : STD_LOGIC;
signal b_12_XORG_5830 : STD_LOGIC;
signal Madd_b_cy_12_Q : STD_LOGIC;
signal b_12_CYSELF_5828 : STD_LOGIC;
signal b_12_CYMUXFAST_5827 : STD_LOGIC;
signal b_12_CYAND_5826 : STD_LOGIC;
signal b_12_FASTCARRY_5825 : STD_LOGIC;
signal b_12_CYMUXG2_5824 : STD_LOGIC;
signal b_12_CYMUXF2_5823 : STD_LOGIC;
signal b_12_CY0G_5822 : STD_LOGIC;
signal b_12_CYSELG_5816 : STD_LOGIC;
signal b_14_XORF_5882 : STD_LOGIC;
signal b_14_CYINIT_5881 : STD_LOGIC;
signal b_14_CY0F_5880 : STD_LOGIC;
signal b_14_XORG_5871 : STD_LOGIC;
signal Madd_b_cy_14_Q : STD_LOGIC;
signal b_14_CYSELF_5869 : STD_LOGIC;
signal b_14_CYMUXFAST_5868 : STD_LOGIC;
signal b_14_CYAND_5867 : STD_LOGIC;
signal b_14_FASTCARRY_5866 : STD_LOGIC;
signal b_14_CYMUXG2_5865 : STD_LOGIC;
signal b_14_CYMUXF2_5864 : STD_LOGIC;
signal b_14_CY0G_5863 : STD_LOGIC;
signal b_14_CYSELG_5857 : STD_LOGIC;
signal b_16_XORF_5925 : STD_LOGIC;
signal b_16_CYINIT_5924 : STD_LOGIC;
signal b_16_CY0F_5923 : STD_LOGIC;
signal b_16_XORG_5914 : STD_LOGIC;
signal Madd_b_cy_16_Q : STD_LOGIC;
signal b_16_CYSELF_5912 : STD_LOGIC;
signal b_16_CYMUXFAST_5911 : STD_LOGIC;
signal b_16_CYAND_5910 : STD_LOGIC;
signal b_16_FASTCARRY_5909 : STD_LOGIC;
signal b_16_CYMUXG2_5908 : STD_LOGIC;
signal b_16_CYMUXF2_5907 : STD_LOGIC;
signal b_16_CY0G_5906 : STD_LOGIC;
signal b_16_CYSELG_5900 : STD_LOGIC;
signal b_18_XORF_5966 : STD_LOGIC;
signal b_18_CYINIT_5965 : STD_LOGIC;
signal b_18_CY0F_5964 : STD_LOGIC;
signal b_18_XORG_5956 : STD_LOGIC;
signal Madd_b_cy_18_Q : STD_LOGIC;
signal b_18_CYSELF_5954 : STD_LOGIC;
signal b_18_CYMUXFAST_5953 : STD_LOGIC;
signal b_18_CYAND_5952 : STD_LOGIC;
signal b_18_FASTCARRY_5951 : STD_LOGIC;
signal b_18_CYMUXG2_5950 : STD_LOGIC;
signal b_18_CYMUXF2_5949 : STD_LOGIC;
signal b_18_CY0G_5948 : STD_LOGIC;
signal b_18_CYSELG_5942 : STD_LOGIC;
signal b_20_XORF_6009 : STD_LOGIC;
signal b_20_CYINIT_6008 : STD_LOGIC;
signal b_20_CY0F_6007 : STD_LOGIC;
signal b_20_XORG_5998 : STD_LOGIC;
signal Madd_b_cy_20_Q : STD_LOGIC;
signal b_20_CYSELF_5996 : STD_LOGIC;
signal b_20_CYMUXFAST_5995 : STD_LOGIC;
signal b_20_CYAND_5994 : STD_LOGIC;
signal b_20_FASTCARRY_5993 : STD_LOGIC;
signal b_20_CYMUXG2_5992 : STD_LOGIC;
signal b_20_CYMUXF2_5991 : STD_LOGIC;
signal b_20_CY0G_5990 : STD_LOGIC;
signal b_20_CYSELG_5984 : STD_LOGIC;
signal b_22_XORF_6052 : STD_LOGIC;
signal b_22_CYINIT_6051 : STD_LOGIC;
signal b_22_CY0F_6050 : STD_LOGIC;
signal b_22_XORG_6041 : STD_LOGIC;
signal Madd_b_cy_22_Q : STD_LOGIC;
signal b_22_CYSELF_6039 : STD_LOGIC;
signal b_22_CYMUXFAST_6038 : STD_LOGIC;
signal b_22_CYAND_6037 : STD_LOGIC;
signal b_22_FASTCARRY_6036 : STD_LOGIC;
signal b_22_CYMUXG2_6035 : STD_LOGIC;
signal b_22_CYMUXF2_6034 : STD_LOGIC;
signal b_22_CY0G_6033 : STD_LOGIC;
signal b_22_CYSELG_6027 : STD_LOGIC;
signal b_24_XORF_6093 : STD_LOGIC;
signal b_24_CYINIT_6092 : STD_LOGIC;
signal b_24_CY0F_6091 : STD_LOGIC;
signal b_24_XORG_6082 : STD_LOGIC;
signal Madd_b_cy_24_Q : STD_LOGIC;
signal b_24_CYSELF_6080 : STD_LOGIC;
signal b_24_CYMUXFAST_6079 : STD_LOGIC;
signal b_24_CYAND_6078 : STD_LOGIC;
signal b_24_FASTCARRY_6077 : STD_LOGIC;
signal b_24_CYMUXG2_6076 : STD_LOGIC;
signal b_24_CYMUXF2_6075 : STD_LOGIC;
signal b_24_CY0G_6074 : STD_LOGIC;
signal b_24_CYSELG_6068 : STD_LOGIC;
signal b_26_XORF_6136 : STD_LOGIC;
signal b_26_CYINIT_6135 : STD_LOGIC;
signal b_26_CY0F_6134 : STD_LOGIC;
signal b_26_XORG_6125 : STD_LOGIC;
signal Madd_b_cy_26_Q : STD_LOGIC;
signal b_26_CYSELF_6123 : STD_LOGIC;
signal b_26_CYMUXFAST_6122 : STD_LOGIC;
signal b_26_CYAND_6121 : STD_LOGIC;
signal b_26_FASTCARRY_6120 : STD_LOGIC;
signal b_26_CYMUXG2_6119 : STD_LOGIC;
signal b_26_CYMUXF2_6118 : STD_LOGIC;
signal b_26_CY0G_6117 : STD_LOGIC;
signal b_26_CYSELG_6111 : STD_LOGIC;
signal b_28_XORF_6179 : STD_LOGIC;
signal b_28_CYINIT_6178 : STD_LOGIC;
signal b_28_CY0F_6177 : STD_LOGIC;
signal b_28_XORG_6168 : STD_LOGIC;
signal Madd_b_cy_28_Q : STD_LOGIC;
signal b_28_CYSELF_6166 : STD_LOGIC;
signal b_28_CYMUXFAST_6165 : STD_LOGIC;
signal b_28_CYAND_6164 : STD_LOGIC;
signal b_28_FASTCARRY_6163 : STD_LOGIC;
signal b_28_CYMUXG2_6162 : STD_LOGIC;
signal b_28_CYMUXF2_6161 : STD_LOGIC;
signal b_28_CY0G_6160 : STD_LOGIC;
signal b_28_CYSELG_6154 : STD_LOGIC;
signal b_30_XORF_6212 : STD_LOGIC;
signal b_30_CYINIT_6211 : STD_LOGIC;
signal b_30_CY0F_6210 : STD_LOGIC;
signal b_30_CYSELF_6204 : STD_LOGIC;
signal b_30_XORG_6200 : STD_LOGIC;
signal Madd_b_cy_30_Q : STD_LOGIC;
signal din_lower_0_INBUF : STD_LOGIC;
signal din_lower_1_INBUF : STD_LOGIC;
signal din_lower_2_INBUF : STD_LOGIC;
signal din_lower_3_INBUF : STD_LOGIC;
signal din_lower_4_INBUF : STD_LOGIC;
signal din_lower_5_INBUF : STD_LOGIC;
signal din_lower_6_INBUF : STD_LOGIC;
signal din_lower_7_INBUF : STD_LOGIC;
signal clr_INBUF : STD_LOGIC;
signal AN_0_O : STD_LOGIC;
signal AN_1_O : STD_LOGIC;
signal AN_2_O : STD_LOGIC;
signal AN_3_O : STD_LOGIC;
signal segment_a_i_O : STD_LOGIC;
signal segment_b_i_O : STD_LOGIC;
signal segment_c_i_O : STD_LOGIC;
signal segment_d_i_O : STD_LOGIC;
signal segment_e_i_O : STD_LOGIC;
signal segment_f_i_O : STD_LOGIC;
signal segment_g_i_O : STD_LOGIC;
signal clk_25_INBUF : STD_LOGIC;
signal di_vld_INBUF : STD_LOGIC;
signal do_rdy_O : STD_LOGIC;
signal swtch_led_0_O : STD_LOGIC;
signal swtch_led_1_O : STD_LOGIC;
signal swtch_led_2_O : STD_LOGIC;
signal swtch_led_3_O : STD_LOGIC;
signal swtch_led_4_O : STD_LOGIC;
signal swtch_led_5_O : STD_LOGIC;
signal swtch_led_6_O : STD_LOGIC;
signal swtch_led_7_O : STD_LOGIC;
signal clk_25_BUFGP_BUFG_S_INVNOT : STD_LOGIC;
signal clk_25_BUFGP_BUFG_I0_INV : STD_LOGIC;
signal Sh13120_F5MUX_6468 : STD_LOGIC;
signal N403 : STD_LOGIC;
signal Sh13120_BXINV_6460 : STD_LOGIC;
signal N402 : STD_LOGIC;
signal Sh133_F5MUX_6493 : STD_LOGIC;
signal N527 : STD_LOGIC;
signal Sh133_BXINV_6485 : STD_LOGIC;
signal N526 : STD_LOGIC;
signal Sh140_F5MUX_6518 : STD_LOGIC;
signal N407 : STD_LOGIC;
signal Sh140_BXINV_6510 : STD_LOGIC;
signal N406 : STD_LOGIC;
signal Sh141_F5MUX_6543 : STD_LOGIC;
signal N409 : STD_LOGIC;
signal Sh141_BXINV_6535 : STD_LOGIC;
signal N408 : STD_LOGIC;
signal Sh142_F5MUX_6568 : STD_LOGIC;
signal N315 : STD_LOGIC;
signal Sh142_BXINV_6560 : STD_LOGIC;
signal N314 : STD_LOGIC;
signal Sh135_F5MUX_6593 : STD_LOGIC;
signal N303 : STD_LOGIC;
signal Sh135_BXINV_6585 : STD_LOGIC;
signal N302 : STD_LOGIC;
signal Sh14612_F5MUX_6618 : STD_LOGIC;
signal N415 : STD_LOGIC;
signal Sh14612_BXINV_6611 : STD_LOGIC;
signal N414 : STD_LOGIC;
signal Sh136_F5MUX_6643 : STD_LOGIC;
signal N305 : STD_LOGIC;
signal Sh136_BXINV_6635 : STD_LOGIC;
signal N304 : STD_LOGIC;
signal Sh14712_F5MUX_6668 : STD_LOGIC;
signal N413 : STD_LOGIC;
signal Sh14712_BXINV_6661 : STD_LOGIC;
signal N412 : STD_LOGIC;
signal Sh137_F5MUX_6693 : STD_LOGIC;
signal N307 : STD_LOGIC;
signal Sh137_BXINV_6685 : STD_LOGIC;
signal N306 : STD_LOGIC;
signal Sh139_F5MUX_6718 : STD_LOGIC;
signal N299 : STD_LOGIC;
signal Sh139_BXINV_6710 : STD_LOGIC;
signal N298 : STD_LOGIC;
signal b_reg_10_FFX_RST : STD_LOGIC;
signal b_reg_10_DXMUX_6749 : STD_LOGIC;
signal b_reg_10_F5MUX_6747 : STD_LOGIC;
signal N529 : STD_LOGIC;
signal b_reg_10_BXINV_6740 : STD_LOGIC;
signal N528 : STD_LOGIC;
signal b_reg_10_CLKINV_6731 : STD_LOGIC;
signal Sh10_F5MUX_6779 : STD_LOGIC;
signal N471 : STD_LOGIC;
signal Sh10_BXINV_6772 : STD_LOGIC;
signal N470 : STD_LOGIC;
signal Sh13_F5MUX_6804 : STD_LOGIC;
signal N495 : STD_LOGIC;
signal Sh13_BXINV_6797 : STD_LOGIC;
signal N494 : STD_LOGIC;
signal Sh21_F5MUX_6829 : STD_LOGIC;
signal N491 : STD_LOGIC;
signal Sh21_BXINV_6822 : STD_LOGIC;
signal N490 : STD_LOGIC;
signal Sh14_F5MUX_6854 : STD_LOGIC;
signal N487 : STD_LOGIC;
signal Sh14_BXINV_6847 : STD_LOGIC;
signal N486 : STD_LOGIC;
signal Sh22_F5MUX_6879 : STD_LOGIC;
signal N483 : STD_LOGIC;
signal Sh22_BXINV_6872 : STD_LOGIC;
signal N482 : STD_LOGIC;
signal Sh30_F5MUX_6904 : STD_LOGIC;
signal N473 : STD_LOGIC;
signal Sh30_BXINV_6897 : STD_LOGIC;
signal N472 : STD_LOGIC;
signal Sh17_F5MUX_6929 : STD_LOGIC;
signal N493 : STD_LOGIC;
signal Sh17_BXINV_6922 : STD_LOGIC;
signal N492 : STD_LOGIC;
signal Sh25_F5MUX_6954 : STD_LOGIC;
signal N489 : STD_LOGIC;
signal Sh25_BXINV_6947 : STD_LOGIC;
signal N488 : STD_LOGIC;
signal Sh18_F5MUX_6979 : STD_LOGIC;
signal N485 : STD_LOGIC;
signal Sh18_BXINV_6972 : STD_LOGIC;
signal N484 : STD_LOGIC;
signal Sh26_F5MUX_7004 : STD_LOGIC;
signal N481 : STD_LOGIC;
signal Sh26_BXINV_6997 : STD_LOGIC;
signal N480 : STD_LOGIC;
signal Sh29_F5MUX_7029 : STD_LOGIC;
signal N479 : STD_LOGIC;
signal Sh29_BXINV_7022 : STD_LOGIC;
signal N478 : STD_LOGIC;
signal Sh4_F5MUX_7054 : STD_LOGIC;
signal N301 : STD_LOGIC;
signal Sh4_BXINV_7047 : STD_LOGIC;
signal N300 : STD_LOGIC;
signal Sh8_F5MUX_7079 : STD_LOGIC;
signal N325 : STD_LOGIC;
signal Sh8_BXINV_7072 : STD_LOGIC;
signal N324 : STD_LOGIC;
signal Sh96_F5MUX_7106 : STD_LOGIC;
signal Sh1262_rt_7104 : STD_LOGIC;
signal Sh96_BXINV_7096 : STD_LOGIC;
signal Sh962 : STD_LOGIC;
signal Sh97_F5MUX_7131 : STD_LOGIC;
signal Sh1272_rt_7129 : STD_LOGIC;
signal Sh97_BXINV_7121 : STD_LOGIC;
signal Sh972_7119 : STD_LOGIC;
signal Sh100_F5MUX_7158 : STD_LOGIC;
signal Sh1001_7156 : STD_LOGIC;
signal Sh100_BXINV_7151 : STD_LOGIC;
signal Sh1002 : STD_LOGIC;
signal Sh101_F5MUX_7185 : STD_LOGIC;
signal Sh1011_rt_7183 : STD_LOGIC;
signal Sh101_BXINV_7175 : STD_LOGIC;
signal Sh1012 : STD_LOGIC;
signal Sh120_F5MUX_7212 : STD_LOGIC;
signal Sh1182_rt_7210 : STD_LOGIC;
signal Sh120_BXINV_7202 : STD_LOGIC;
signal Sh1202 : STD_LOGIC;
signal Sh112_F5MUX_7239 : STD_LOGIC;
signal Sh1102_rt_7237 : STD_LOGIC;
signal Sh112_BXINV_7229 : STD_LOGIC;
signal Sh1122 : STD_LOGIC;
signal Sh104_F5MUX_7266 : STD_LOGIC;
signal Sh1022_rt_7264 : STD_LOGIC;
signal Sh104_BXINV_7256 : STD_LOGIC;
signal Sh1042 : STD_LOGIC;
signal Sh121_F5MUX_7293 : STD_LOGIC;
signal Sh1192_rt_7291 : STD_LOGIC;
signal Sh121_BXINV_7283 : STD_LOGIC;
signal Sh1212 : STD_LOGIC;
signal Sh113_F5MUX_7320 : STD_LOGIC;
signal Sh1112_rt_7318 : STD_LOGIC;
signal Sh113_BXINV_7310 : STD_LOGIC;
signal Sh1132 : STD_LOGIC;
signal Sh105_F5MUX_7347 : STD_LOGIC;
signal Sh1032_rt_7345 : STD_LOGIC;
signal Sh105_BXINV_7337 : STD_LOGIC;
signal Sh1052 : STD_LOGIC;
signal Sh124_F5MUX_7374 : STD_LOGIC;
signal Sh1222_rt_7372 : STD_LOGIC;
signal Sh124_BXINV_7364 : STD_LOGIC;
signal Sh1242 : STD_LOGIC;
signal Sh116_F5MUX_7401 : STD_LOGIC;
signal Sh1142_rt_7399 : STD_LOGIC;
signal Sh116_BXINV_7391 : STD_LOGIC;
signal Sh1162 : STD_LOGIC;
signal Sh108_F5MUX_7428 : STD_LOGIC;
signal Sh1062_rt_7426 : STD_LOGIC;
signal Sh108_BXINV_7418 : STD_LOGIC;
signal Sh1082 : STD_LOGIC;
signal Sh125_F5MUX_7455 : STD_LOGIC;
signal Sh1232_rt_7453 : STD_LOGIC;
signal Sh125_BXINV_7445 : STD_LOGIC;
signal Sh1252 : STD_LOGIC;
signal Sh117_F5MUX_7482 : STD_LOGIC;
signal Sh1152_rt_7480 : STD_LOGIC;
signal Sh117_BXINV_7472 : STD_LOGIC;
signal Sh1172 : STD_LOGIC;
signal Sh109_F5MUX_7509 : STD_LOGIC;
signal Sh1072_rt_7507 : STD_LOGIC;
signal Sh109_BXINV_7499 : STD_LOGIC;
signal Sh1092 : STD_LOGIC;
signal Sh3_F5MUX_7534 : STD_LOGIC;
signal N309 : STD_LOGIC;
signal Sh3_BXINV_7526 : STD_LOGIC;
signal N308 : STD_LOGIC;
signal Sh7_F5MUX_7559 : STD_LOGIC;
signal N337 : STD_LOGIC;
signal Sh7_BXINV_7552 : STD_LOGIC;
signal N336 : STD_LOGIC;
signal Sh11_F5MUX_7584 : STD_LOGIC;
signal N349 : STD_LOGIC;
signal Sh11_BXINV_7577 : STD_LOGIC;
signal N348 : STD_LOGIC;
signal Sh15_F5MUX_7609 : STD_LOGIC;
signal N347 : STD_LOGIC;
signal Sh15_BXINV_7602 : STD_LOGIC;
signal N346 : STD_LOGIC;
signal Sh23_F5MUX_7634 : STD_LOGIC;
signal N343 : STD_LOGIC;
signal Sh23_BXINV_7627 : STD_LOGIC;
signal N342 : STD_LOGIC;
signal Sh31_F5MUX_7659 : STD_LOGIC;
signal N339 : STD_LOGIC;
signal Sh31_BXINV_7652 : STD_LOGIC;
signal N338 : STD_LOGIC;
signal Sh19_F5MUX_7684 : STD_LOGIC;
signal N345 : STD_LOGIC;
signal Sh19_BXINV_7677 : STD_LOGIC;
signal N344 : STD_LOGIC;
signal Sh27_F5MUX_7709 : STD_LOGIC;
signal N341 : STD_LOGIC;
signal Sh27_BXINV_7702 : STD_LOGIC;
signal N340 : STD_LOGIC;
signal Sh12_F5MUX_7734 : STD_LOGIC;
signal N335 : STD_LOGIC;
signal Sh12_BXINV_7727 : STD_LOGIC;
signal N334 : STD_LOGIC;
signal Sh20_F5MUX_7759 : STD_LOGIC;
signal N331 : STD_LOGIC;
signal Sh20_BXINV_7752 : STD_LOGIC;
signal N330 : STD_LOGIC;
signal Sh16_F5MUX_7784 : STD_LOGIC;
signal N333 : STD_LOGIC;
signal Sh16_BXINV_7777 : STD_LOGIC;
signal N332 : STD_LOGIC;
signal Sh24_F5MUX_7809 : STD_LOGIC;
signal N329 : STD_LOGIC;
signal Sh24_BXINV_7802 : STD_LOGIC;
signal N328 : STD_LOGIC;
signal Sh28_F5MUX_7834 : STD_LOGIC;
signal N327 : STD_LOGIC;
signal Sh28_BXINV_7827 : STD_LOGIC;
signal N326 : STD_LOGIC;
signal Sh123_F5MUX_7859 : STD_LOGIC;
signal N497 : STD_LOGIC;
signal Sh123_BXINV_7852 : STD_LOGIC;
signal N496 : STD_LOGIC;
signal Sh127_F5MUX_7884 : STD_LOGIC;
signal N461 : STD_LOGIC;
signal Sh127_BXINV_7877 : STD_LOGIC;
signal N460 : STD_LOGIC;
signal Sh145_F5MUX_7909 : STD_LOGIC;
signal Sh14531 : STD_LOGIC;
signal Sh145_BXINV_7901 : STD_LOGIC;
signal Sh145311_7899 : STD_LOGIC;
signal Sh_F5MUX_7934 : STD_LOGIC;
signal N411 : STD_LOGIC;
signal Sh_BXINV_7927 : STD_LOGIC;
signal N410 : STD_LOGIC;
signal N291_F5MUX_7959 : STD_LOGIC;
signal N465 : STD_LOGIC;
signal N291_BXINV_7950 : STD_LOGIC;
signal N464 : STD_LOGIC;
signal N292_F5MUX_7984 : STD_LOGIC;
signal N467 : STD_LOGIC;
signal N292_BXINV_7975 : STD_LOGIC;
signal N466 : STD_LOGIC;
signal N281_F5MUX_8009 : STD_LOGIC;
signal N457 : STD_LOGIC;
signal N281_BXINV_8000 : STD_LOGIC;
signal N456 : STD_LOGIC;
signal N282_F5MUX_8034 : STD_LOGIC;
signal N459 : STD_LOGIC;
signal N282_BXINV_8025 : STD_LOGIC;
signal N458 : STD_LOGIC;
signal N278_F5MUX_8059 : STD_LOGIC;
signal N453 : STD_LOGIC;
signal N278_BXINV_8050 : STD_LOGIC;
signal N452 : STD_LOGIC;
signal N279_F5MUX_8084 : STD_LOGIC;
signal N455 : STD_LOGIC;
signal N279_BXINV_8075 : STD_LOGIC;
signal N454 : STD_LOGIC;
signal Sh1307_F5MUX_8109 : STD_LOGIC;
signal N371 : STD_LOGIC;
signal Sh1307_BXINV_8101 : STD_LOGIC;
signal N370 : STD_LOGIC;
signal Sh160_F5MUX_8134 : STD_LOGIC;
signal N319 : STD_LOGIC;
signal Sh160_BXINV_8127 : STD_LOGIC;
signal N318 : STD_LOGIC;
signal Sh1507_F5MUX_8159 : STD_LOGIC;
signal N435 : STD_LOGIC;
signal Sh1507_BXINV_8151 : STD_LOGIC;
signal N434 : STD_LOGIC;
signal Sh13820_F5MUX_8184 : STD_LOGIC;
signal N417 : STD_LOGIC;
signal Sh13820_BXINV_8176 : STD_LOGIC;
signal N416 : STD_LOGIC;
signal Sh1517_F5MUX_8209 : STD_LOGIC;
signal N433 : STD_LOGIC;
signal Sh1517_BXINV_8201 : STD_LOGIC;
signal N432 : STD_LOGIC;
signal Sh162_F5MUX_8234 : STD_LOGIC;
signal N317 : STD_LOGIC;
signal Sh162_BXINV_8227 : STD_LOGIC;
signal N316 : STD_LOGIC;
signal Sh40_F5MUX_8259 : STD_LOGIC;
signal N369 : STD_LOGIC;
signal Sh40_BXINV_8251 : STD_LOGIC;
signal N368 : STD_LOGIC;
signal Sh32_F5MUX_8284 : STD_LOGIC;
signal N353 : STD_LOGIC;
signal Sh32_BXINV_8276 : STD_LOGIC;
signal N352 : STD_LOGIC;
signal Sh163_F5MUX_8309 : STD_LOGIC;
signal N311 : STD_LOGIC;
signal Sh163_BXINV_8302 : STD_LOGIC;
signal N310 : STD_LOGIC;
signal Sh164_F5MUX_8334 : STD_LOGIC;
signal N313 : STD_LOGIC;
signal Sh164_BXINV_8327 : STD_LOGIC;
signal N312 : STD_LOGIC;
signal Sh41_F5MUX_8359 : STD_LOGIC;
signal N425 : STD_LOGIC;
signal Sh41_BXINV_8351 : STD_LOGIC;
signal N424 : STD_LOGIC;
signal Sh1547_F5MUX_8384 : STD_LOGIC;
signal N421 : STD_LOGIC;
signal Sh1547_BXINV_8376 : STD_LOGIC;
signal N420 : STD_LOGIC;
signal Sh13420_F5MUX_8409 : STD_LOGIC;
signal N401 : STD_LOGIC;
signal Sh13420_BXINV_8401 : STD_LOGIC;
signal N400 : STD_LOGIC;
signal Sh33_F5MUX_8434 : STD_LOGIC;
signal N375 : STD_LOGIC;
signal Sh33_BXINV_8426 : STD_LOGIC;
signal N374 : STD_LOGIC;
signal Sh1557_F5MUX_8459 : STD_LOGIC;
signal N419 : STD_LOGIC;
signal Sh1557_BXINV_8451 : STD_LOGIC;
signal N418 : STD_LOGIC;
signal Sh42_F5MUX_8484 : STD_LOGIC;
signal N429 : STD_LOGIC;
signal Sh42_BXINV_8476 : STD_LOGIC;
signal N428 : STD_LOGIC;
signal Sh34_F5MUX_8509 : STD_LOGIC;
signal N379 : STD_LOGIC;
signal Sh34_BXINV_8501 : STD_LOGIC;
signal N378 : STD_LOGIC;
signal Sh50_F5MUX_8534 : STD_LOGIC;
signal N377 : STD_LOGIC;
signal Sh50_BXINV_8526 : STD_LOGIC;
signal N376 : STD_LOGIC;
signal Sh175_F5MUX_8559 : STD_LOGIC;
signal N321 : STD_LOGIC;
signal Sh175_BXINV_8552 : STD_LOGIC;
signal N320 : STD_LOGIC;
signal Sh1587_F5MUX_8584 : STD_LOGIC;
signal N427 : STD_LOGIC;
signal Sh1587_BXINV_8576 : STD_LOGIC;
signal N426 : STD_LOGIC;
signal Sh43_F5MUX_8609 : STD_LOGIC;
signal N383 : STD_LOGIC;
signal Sh43_BXINV_8601 : STD_LOGIC;
signal N382 : STD_LOGIC;
signal Sh35_F5MUX_8634 : STD_LOGIC;
signal N357 : STD_LOGIC;
signal Sh35_BXINV_8626 : STD_LOGIC;
signal N356 : STD_LOGIC;
signal Sh51_F5MUX_8659 : STD_LOGIC;
signal N355 : STD_LOGIC;
signal Sh51_BXINV_8651 : STD_LOGIC;
signal N354 : STD_LOGIC;
signal Sh1597_F5MUX_8684 : STD_LOGIC;
signal N469 : STD_LOGIC;
signal Sh1597_BXINV_8676 : STD_LOGIC;
signal N468 : STD_LOGIC;
signal Sh178_F5MUX_8709 : STD_LOGIC;
signal N323 : STD_LOGIC;
signal Sh178_BXINV_8702 : STD_LOGIC;
signal N322 : STD_LOGIC;
signal Sh44_F5MUX_8734 : STD_LOGIC;
signal N387 : STD_LOGIC;
signal Sh44_BXINV_8726 : STD_LOGIC;
signal N386 : STD_LOGIC;
signal Sh60_F5MUX_8759 : STD_LOGIC;
signal N385 : STD_LOGIC;
signal Sh60_BXINV_8751 : STD_LOGIC;
signal N384 : STD_LOGIC;
signal Sh36_F5MUX_8784 : STD_LOGIC;
signal N361 : STD_LOGIC;
signal Sh36_BXINV_8776 : STD_LOGIC;
signal N360 : STD_LOGIC;
signal Sh52_F5MUX_8809 : STD_LOGIC;
signal N359 : STD_LOGIC;
signal Sh52_BXINV_8801 : STD_LOGIC;
signal N358 : STD_LOGIC;
signal Sh45_F5MUX_8834 : STD_LOGIC;
signal N431 : STD_LOGIC;
signal Sh45_BXINV_8826 : STD_LOGIC;
signal N430 : STD_LOGIC;
signal Sh37_F5MUX_8859 : STD_LOGIC;
signal N391 : STD_LOGIC;
signal Sh37_BXINV_8851 : STD_LOGIC;
signal N390 : STD_LOGIC;
signal Sh53_F5MUX_8884 : STD_LOGIC;
signal N389 : STD_LOGIC;
signal Sh53_BXINV_8876 : STD_LOGIC;
signal N388 : STD_LOGIC;
signal Sh46_F5MUX_8909 : STD_LOGIC;
signal N423 : STD_LOGIC;
signal Sh46_BXINV_8901 : STD_LOGIC;
signal N422 : STD_LOGIC;
signal Sh38_F5MUX_8934 : STD_LOGIC;
signal N395 : STD_LOGIC;
signal Sh38_BXINV_8926 : STD_LOGIC;
signal N394 : STD_LOGIC;
signal Sh54_F5MUX_8959 : STD_LOGIC;
signal N393 : STD_LOGIC;
signal Sh54_BXINV_8951 : STD_LOGIC;
signal N392 : STD_LOGIC;
signal Sh47_F5MUX_8984 : STD_LOGIC;
signal N399 : STD_LOGIC;
signal Sh47_BXINV_8976 : STD_LOGIC;
signal N398 : STD_LOGIC;
signal Sh63_F5MUX_9009 : STD_LOGIC;
signal N397 : STD_LOGIC;
signal Sh63_BXINV_9001 : STD_LOGIC;
signal N396 : STD_LOGIC;
signal Sh39_F5MUX_9034 : STD_LOGIC;
signal N365 : STD_LOGIC;
signal Sh39_BXINV_9026 : STD_LOGIC;
signal N364 : STD_LOGIC;
signal Sh55_F5MUX_9059 : STD_LOGIC;
signal N363 : STD_LOGIC;
signal Sh55_BXINV_9051 : STD_LOGIC;
signal N362 : STD_LOGIC;
signal Sh56_F5MUX_9084 : STD_LOGIC;
signal N367 : STD_LOGIC;
signal Sh56_BXINV_9076 : STD_LOGIC;
signal N366 : STD_LOGIC;
signal Sh48_F5MUX_9109 : STD_LOGIC;
signal N351 : STD_LOGIC;
signal Sh48_BXINV_9101 : STD_LOGIC;
signal N350 : STD_LOGIC;
signal Sh49_F5MUX_9134 : STD_LOGIC;
signal N373 : STD_LOGIC;
signal Sh49_BXINV_9126 : STD_LOGIC;
signal N372 : STD_LOGIC;
signal Sh59_F5MUX_9159 : STD_LOGIC;
signal N381 : STD_LOGIC;
signal Sh59_BXINV_9151 : STD_LOGIC;
signal N380 : STD_LOGIC;
signal N275_F5MUX_9184 : STD_LOGIC;
signal N449 : STD_LOGIC;
signal N275_BXINV_9175 : STD_LOGIC;
signal N448 : STD_LOGIC;
signal N276_F5MUX_9209 : STD_LOGIC;
signal N451 : STD_LOGIC;
signal N276_BXINV_9200 : STD_LOGIC;
signal N450 : STD_LOGIC;
signal b_reg_8_DXMUX_9240 : STD_LOGIC;
signal b_reg_8_F5MUX_9238 : STD_LOGIC;
signal N533 : STD_LOGIC;
signal b_reg_8_BXINV_9231 : STD_LOGIC;
signal N532 : STD_LOGIC;
signal b_reg_8_CLKINV_9222 : STD_LOGIC;
signal b_reg_9_DXMUX_9276 : STD_LOGIC;
signal b_reg_9_F5MUX_9274 : STD_LOGIC;
signal N531 : STD_LOGIC;
signal b_reg_9_BXINV_9267 : STD_LOGIC;
signal N530 : STD_LOGIC;
signal b_reg_9_CLKINV_9258 : STD_LOGIC;
signal N272_F5MUX_9306 : STD_LOGIC;
signal N445 : STD_LOGIC;
signal N272_BXINV_9297 : STD_LOGIC;
signal N444 : STD_LOGIC;
signal N273_F5MUX_9331 : STD_LOGIC;
signal N447 : STD_LOGIC;
signal N273_BXINV_9322 : STD_LOGIC;
signal N446 : STD_LOGIC;
signal Sh1_F5MUX_9356 : STD_LOGIC;
signal N405 : STD_LOGIC;
signal Sh1_BXINV_9349 : STD_LOGIC;
signal N404 : STD_LOGIC;
signal Sh2_F5MUX_9381 : STD_LOGIC;
signal Sh210 : STD_LOGIC;
signal Sh2_BXINV_9374 : STD_LOGIC;
signal Sh211 : STD_LOGIC;
signal Sh5_F5MUX_9406 : STD_LOGIC;
signal N477 : STD_LOGIC;
signal Sh5_BXINV_9399 : STD_LOGIC;
signal N476 : STD_LOGIC;
signal N269_F5MUX_9431 : STD_LOGIC;
signal N441 : STD_LOGIC;
signal N269_BXINV_9422 : STD_LOGIC;
signal N440 : STD_LOGIC;
signal N270_F5MUX_9456 : STD_LOGIC;
signal N443 : STD_LOGIC;
signal N270_BXINV_9447 : STD_LOGIC;
signal N442 : STD_LOGIC;
signal Sh6_F5MUX_9481 : STD_LOGIC;
signal N463 : STD_LOGIC;
signal Sh6_BXINV_9474 : STD_LOGIC;
signal N462 : STD_LOGIC;
signal Sh9_F5MUX_9506 : STD_LOGIC;
signal N475 : STD_LOGIC;
signal Sh9_BXINV_9499 : STD_LOGIC;
signal N474 : STD_LOGIC;
signal b_reg_0_1_DXMUX_9538 : STD_LOGIC;
signal b_reg_0_1_FXMUX_9537 : STD_LOGIC;
signal b_reg_0_1_F5MUX_9536 : STD_LOGIC;
signal N525 : STD_LOGIC;
signal b_reg_0_1_BXINV_9529 : STD_LOGIC;
signal N524 : STD_LOGIC;
signal b_reg_0_1_CLKINV_9521 : STD_LOGIC;
signal hex_digit_i_0_DXMUX_9574 : STD_LOGIC;
signal hex_digit_i_0_F5MUX_9572 : STD_LOGIC;
signal Mmux_hex_digit_i_mux0001_3_9570 : STD_LOGIC;
signal hex_digit_i_0_BXINV_9564 : STD_LOGIC;
signal Mmux_hex_digit_i_mux0001_4_9562 : STD_LOGIC;
signal hex_digit_i_0_CLKINV_9555 : STD_LOGIC;
signal N266_F5MUX_9604 : STD_LOGIC;
signal N437 : STD_LOGIC;
signal N266_BXINV_9595 : STD_LOGIC;
signal N436 : STD_LOGIC;
signal N267_F5MUX_9629 : STD_LOGIC;
signal N439 : STD_LOGIC;
signal N267_BXINV_9620 : STD_LOGIC;
signal N438 : STD_LOGIC;
signal i_cnt_3_DXMUX_9660 : STD_LOGIC;
signal i_cnt_3_F5MUX_9658 : STD_LOGIC;
signal i_cnt_mux0001_0_56 : STD_LOGIC;
signal i_cnt_3_BXINV_9651 : STD_LOGIC;
signal i_cnt_mux0001_0_561_9649 : STD_LOGIC;
signal i_cnt_3_CLKINV_9642 : STD_LOGIC;
signal hex_digit_i_1_DXMUX_9696 : STD_LOGIC;
signal hex_digit_i_1_F5MUX_9694 : STD_LOGIC;
signal Mmux_hex_digit_i_mux0001_31_9692 : STD_LOGIC;
signal hex_digit_i_1_BXINV_9686 : STD_LOGIC;
signal Mmux_hex_digit_i_mux0001_41_9684 : STD_LOGIC;
signal hex_digit_i_1_CLKINV_9677 : STD_LOGIC;
signal hex_digit_i_2_DXMUX_9732 : STD_LOGIC;
signal hex_digit_i_2_F5MUX_9730 : STD_LOGIC;
signal Mmux_hex_digit_i_mux0001_32_9728 : STD_LOGIC;
signal hex_digit_i_2_BXINV_9722 : STD_LOGIC;
signal Mmux_hex_digit_i_mux0001_42_9720 : STD_LOGIC;
signal hex_digit_i_2_CLKINV_9713 : STD_LOGIC;
signal hex_digit_i_3_DXMUX_9768 : STD_LOGIC;
signal hex_digit_i_3_F5MUX_9766 : STD_LOGIC;
signal Mmux_hex_digit_i_mux0001_33_9764 : STD_LOGIC;
signal hex_digit_i_3_BXINV_9758 : STD_LOGIC;
signal Mmux_hex_digit_i_mux0001_43_9756 : STD_LOGIC;
signal hex_digit_i_3_CLKINV_9749 : STD_LOGIC;
signal Sh150 : STD_LOGIC;
signal Sh15016_O_pack_1 : STD_LOGIC;
signal Sh143 : STD_LOGIC;
signal Sh14316_pack_1 : STD_LOGIC;
signal Sh144 : STD_LOGIC;
signal Sh14416_pack_1 : STD_LOGIC;
signal Sh154 : STD_LOGIC;
signal Sh15416_O_pack_1 : STD_LOGIC;
signal Sh147 : STD_LOGIC;
signal Sh14713_pack_1 : STD_LOGIC;
signal Sh148 : STD_LOGIC;
signal Sh1487_pack_1 : STD_LOGIC;
signal Sh159 : STD_LOGIC;
signal Sh1313_pack_1 : STD_LOGIC;
signal Sh73 : STD_LOGIC;
signal Sh57_pack_1 : STD_LOGIC;
signal Sh74 : STD_LOGIC;
signal Sh58_pack_1 : STD_LOGIC;
signal Sh77 : STD_LOGIC;
signal Sh61_pack_1 : STD_LOGIC;
signal Sh78 : STD_LOGIC;
signal Sh62_pack_1 : STD_LOGIC;
signal N249 : STD_LOGIC;
signal Sh14716_pack_1 : STD_LOGIC;
signal Sh1022_10084 : STD_LOGIC;
signal Mxor_ba_xor_Result_5_1_SW1_O_pack_1 : STD_LOGIC;
signal Sh1102_10108 : STD_LOGIC;
signal Mxor_ba_xor_Result_13_1_SW1_O_pack_1 : STD_LOGIC;
signal Sh1032_10132 : STD_LOGIC;
signal Mxor_ba_xor_Result_7_1_SW1_O_pack_1 : STD_LOGIC;
signal Sh1112_10156 : STD_LOGIC;
signal Mxor_ba_xor_Result_15_1_SW1_O_pack_1 : STD_LOGIC;
signal Sh1062_10180 : STD_LOGIC;
signal Mxor_ba_xor_Result_9_1_SW1_O_pack_1 : STD_LOGIC;
signal Sh1142_10204 : STD_LOGIC;
signal Mxor_ba_xor_Result_17_1_SW1_O_pack_1 : STD_LOGIC;
signal Sh1222_10228 : STD_LOGIC;
signal Mxor_ba_xor_Result_25_1_SW1_O_pack_1 : STD_LOGIC;
signal Sh1072_10252 : STD_LOGIC;
signal Mxor_ba_xor_Result_11_1_SW1_O_pack_1 : STD_LOGIC;
signal Sh1152_10276 : STD_LOGIC;
signal Mxor_ba_xor_Result_19_1_SW1_O_pack_1 : STD_LOGIC;
signal Sh1232_10300 : STD_LOGIC;
signal N200_pack_1 : STD_LOGIC;
signal Sh1182_10324 : STD_LOGIC;
signal Mxor_ba_xor_Result_21_1_SW1_O_pack_1 : STD_LOGIC;
signal Sh1262_10348 : STD_LOGIC;
signal Mxor_ba_xor_Result_29_1_SW1_O_pack_1 : STD_LOGIC;
signal Sh13016 : STD_LOGIC;
signal Sh982_pack_1 : STD_LOGIC;
signal Sh1192_10396 : STD_LOGIC;
signal Mxor_ba_xor_Result_23_1_SW1_O_pack_1 : STD_LOGIC;
signal Sh1272_10420 : STD_LOGIC;
signal N197_pack_1 : STD_LOGIC;
signal Sh161 : STD_LOGIC;
signal Sh129_pack_1 : STD_LOGIC;
signal Sh170 : STD_LOGIC;
signal Sh138_pack_1 : STD_LOGIC;
signal Sh1437_10492 : STD_LOGIC;
signal Sh107_pack_1 : STD_LOGIC;
signal Sh171 : STD_LOGIC;
signal Sh155_pack_1 : STD_LOGIC;
signal Sh172 : STD_LOGIC;
signal Sh156_pack_1 : STD_LOGIC;
signal Sh180 : STD_LOGIC;
signal Sh132_pack_1 : STD_LOGIC;
signal Sh165 : STD_LOGIC;
signal Sh149_pack_1 : STD_LOGIC;
signal Sh173 : STD_LOGIC;
signal Sh157_pack_1 : STD_LOGIC;
signal Sh166 : STD_LOGIC;
signal Sh134_pack_1 : STD_LOGIC;
signal Sh174 : STD_LOGIC;
signal Sh158_pack_1 : STD_LOGIC;
signal Sh167 : STD_LOGIC;
signal Sh151_pack_1 : STD_LOGIC;
signal Sh168 : STD_LOGIC;
signal Sh152_pack_1 : STD_LOGIC;
signal Sh176 : STD_LOGIC;
signal Sh128_pack_1 : STD_LOGIC;
signal Sh169 : STD_LOGIC;
signal Sh153_pack_1 : STD_LOGIC;
signal Sh179 : STD_LOGIC;
signal Sh131_pack_1 : STD_LOGIC;
signal b_reg_2_1_DYMUX_10800 : STD_LOGIC;
signal b_reg_2_1_GYMUX_10799 : STD_LOGIC;
signal b_reg_mux0000_2_Q : STD_LOGIC;
signal b_reg_2_1_CLKINV_10790 : STD_LOGIC;
signal b_reg_3_1_DYMUX_10824 : STD_LOGIC;
signal b_reg_3_1_GYMUX_10823 : STD_LOGIC;
signal b_reg_mux0000_3_Q : STD_LOGIC;
signal b_reg_3_1_CLKINV_10814 : STD_LOGIC;
signal b_reg_4_1_DYMUX_10848 : STD_LOGIC;
signal b_reg_4_1_GYMUX_10847 : STD_LOGIC;
signal b_reg_mux0000_4_Q : STD_LOGIC;
signal b_reg_4_1_CLKINV_10838 : STD_LOGIC;
signal AN_1_DXMUX_10889 : STD_LOGIC;
signal Mrom_AN_mux00011 : STD_LOGIC;
signal AN_1_DYMUX_10874 : STD_LOGIC;
signal Mrom_AN_mux0001 : STD_LOGIC;
signal AN_1_SRINV_10864 : STD_LOGIC;
signal AN_1_CLKINV_10863 : STD_LOGIC;
signal AN_3_DXMUX_10929 : STD_LOGIC;
signal Mrom_AN_mux00013 : STD_LOGIC;
signal AN_3_DYMUX_10914 : STD_LOGIC;
signal Mrom_AN_mux00012 : STD_LOGIC;
signal AN_3_SRINV_10904 : STD_LOGIC;
signal AN_3_CLKINV_10903 : STD_LOGIC;
signal a_reg_1_DXMUX_10970 : STD_LOGIC;
signal a_reg_1_DYMUX_10956 : STD_LOGIC;
signal a_reg_1_SRINV_10948 : STD_LOGIC;
signal a_reg_1_CLKINV_10947 : STD_LOGIC;
signal a_reg_3_DXMUX_11012 : STD_LOGIC;
signal a_reg_3_DYMUX_10998 : STD_LOGIC;
signal a_reg_3_SRINV_10990 : STD_LOGIC;
signal a_reg_3_CLKINV_10989 : STD_LOGIC;
signal a_reg_5_DXMUX_11054 : STD_LOGIC;
signal a_reg_5_DYMUX_11040 : STD_LOGIC;
signal a_reg_5_SRINV_11032 : STD_LOGIC;
signal a_reg_5_CLKINV_11031 : STD_LOGIC;
signal a_reg_7_DXMUX_11096 : STD_LOGIC;
signal a_reg_7_DYMUX_11082 : STD_LOGIC;
signal a_reg_7_SRINV_11074 : STD_LOGIC;
signal a_reg_7_CLKINV_11073 : STD_LOGIC;
signal a_reg_9_DXMUX_11138 : STD_LOGIC;
signal a_reg_9_DYMUX_11124 : STD_LOGIC;
signal a_reg_9_SRINV_11116 : STD_LOGIC;
signal a_reg_9_CLKINV_11115 : STD_LOGIC;
signal b_reg_7_DXMUX_11180 : STD_LOGIC;
signal b_reg_mux0000_7_Q : STD_LOGIC;
signal b_reg_7_DYMUX_11165 : STD_LOGIC;
signal b_reg_mux0000_6_Q : STD_LOGIC;
signal b_reg_7_SRINV_11156 : STD_LOGIC;
signal b_reg_7_CLKINV_11155 : STD_LOGIC;
signal i_cnt_1_DXMUX_11221 : STD_LOGIC;
signal i_cnt_1_DYMUX_11208 : STD_LOGIC;
signal i_cnt_1_SRINV_11199 : STD_LOGIC;
signal i_cnt_1_CLKINV_11198 : STD_LOGIC;
signal a_reg_11_DXMUX_11263 : STD_LOGIC;
signal a_reg_11_DYMUX_11249 : STD_LOGIC;
signal a_reg_11_SRINV_11241 : STD_LOGIC;
signal a_reg_11_CLKINV_11240 : STD_LOGIC;
signal a_reg_21_FFY_RST : STD_LOGIC;
signal a_reg_21_FFX_RST : STD_LOGIC;
signal a_reg_21_DXMUX_11305 : STD_LOGIC;
signal a_reg_21_DYMUX_11291 : STD_LOGIC;
signal a_reg_21_SRINV_11283 : STD_LOGIC;
signal a_reg_21_CLKINV_11282 : STD_LOGIC;
signal a_reg_13_FFY_RST : STD_LOGIC;
signal a_reg_13_FFX_RST : STD_LOGIC;
signal a_reg_13_DXMUX_11347 : STD_LOGIC;
signal a_reg_13_DYMUX_11333 : STD_LOGIC;
signal a_reg_13_SRINV_11325 : STD_LOGIC;
signal a_reg_13_CLKINV_11324 : STD_LOGIC;
signal a_reg_31_FFY_RST : STD_LOGIC;
signal a_reg_31_FFX_RST : STD_LOGIC;
signal a_reg_31_DXMUX_11389 : STD_LOGIC;
signal a_reg_31_DYMUX_11375 : STD_LOGIC;
signal a_reg_31_SRINV_11367 : STD_LOGIC;
signal a_reg_31_CLKINV_11366 : STD_LOGIC;
signal a_reg_23_FFY_RST : STD_LOGIC;
signal a_reg_23_DXMUX_11431 : STD_LOGIC;
signal a_reg_23_DYMUX_11417 : STD_LOGIC;
signal a_reg_23_SRINV_11409 : STD_LOGIC;
signal a_reg_23_CLKINV_11408 : STD_LOGIC;
signal a_reg_15_DXMUX_11473 : STD_LOGIC;
signal a_reg_15_DYMUX_11459 : STD_LOGIC;
signal a_reg_15_SRINV_11451 : STD_LOGIC;
signal a_reg_15_CLKINV_11450 : STD_LOGIC;
signal a_reg_25_DXMUX_11515 : STD_LOGIC;
signal a_reg_25_DYMUX_11501 : STD_LOGIC;
signal a_reg_25_SRINV_11493 : STD_LOGIC;
signal a_reg_25_CLKINV_11492 : STD_LOGIC;
signal a_reg_17_DXMUX_11557 : STD_LOGIC;
signal a_reg_17_DYMUX_11543 : STD_LOGIC;
signal a_reg_17_SRINV_11535 : STD_LOGIC;
signal a_reg_17_CLKINV_11534 : STD_LOGIC;
signal a_reg_27_DXMUX_11599 : STD_LOGIC;
signal a_reg_27_DYMUX_11585 : STD_LOGIC;
signal a_reg_27_SRINV_11577 : STD_LOGIC;
signal a_reg_27_CLKINV_11576 : STD_LOGIC;
signal a_reg_19_DXMUX_11641 : STD_LOGIC;
signal a_reg_19_DYMUX_11627 : STD_LOGIC;
signal a_reg_19_SRINV_11619 : STD_LOGIC;
signal a_reg_19_CLKINV_11618 : STD_LOGIC;
signal a_reg_29_DXMUX_11683 : STD_LOGIC;
signal a_reg_29_DYMUX_11669 : STD_LOGIC;
signal a_reg_29_SRINV_11661 : STD_LOGIC;
signal a_reg_29_CLKINV_11660 : STD_LOGIC;
signal b_reg_11_DYMUX_11706 : STD_LOGIC;
signal b_reg_mux0000_11_Q : STD_LOGIC;
signal b_reg_11_CLKINV_11696 : STD_LOGIC;
signal b_reg_21_DXMUX_11748 : STD_LOGIC;
signal b_reg_mux0000_21_Q : STD_LOGIC;
signal b_reg_21_DYMUX_11734 : STD_LOGIC;
signal b_reg_mux0000_20_Q : STD_LOGIC;
signal b_reg_21_SRINV_11726 : STD_LOGIC;
signal b_reg_21_CLKINV_11725 : STD_LOGIC;
signal b_reg_13_DXMUX_11790 : STD_LOGIC;
signal b_reg_mux0000_13_Q : STD_LOGIC;
signal b_reg_13_DYMUX_11776 : STD_LOGIC;
signal b_reg_mux0000_12_Q : STD_LOGIC;
signal b_reg_13_SRINV_11768 : STD_LOGIC;
signal b_reg_13_CLKINV_11767 : STD_LOGIC;
signal b_reg_31_DXMUX_11832 : STD_LOGIC;
signal b_reg_mux0000_31_Q : STD_LOGIC;
signal b_reg_31_DYMUX_11818 : STD_LOGIC;
signal b_reg_mux0000_30_Q : STD_LOGIC;
signal b_reg_31_SRINV_11810 : STD_LOGIC;
signal b_reg_31_CLKINV_11809 : STD_LOGIC;
signal b_reg_23_DXMUX_11874 : STD_LOGIC;
signal b_reg_mux0000_23_Q : STD_LOGIC;
signal b_reg_23_DYMUX_11860 : STD_LOGIC;
signal b_reg_mux0000_22_Q : STD_LOGIC;
signal b_reg_23_SRINV_11852 : STD_LOGIC;
signal b_reg_23_CLKINV_11851 : STD_LOGIC;
signal b_reg_15_DXMUX_11916 : STD_LOGIC;
signal b_reg_mux0000_15_Q : STD_LOGIC;
signal b_reg_15_DYMUX_11902 : STD_LOGIC;
signal b_reg_mux0000_14_Q : STD_LOGIC;
signal b_reg_15_SRINV_11894 : STD_LOGIC;
signal b_reg_15_CLKINV_11893 : STD_LOGIC;
signal b_reg_25_DXMUX_11958 : STD_LOGIC;
signal b_reg_mux0000_25_Q : STD_LOGIC;
signal b_reg_25_DYMUX_11944 : STD_LOGIC;
signal b_reg_mux0000_24_Q : STD_LOGIC;
signal b_reg_25_SRINV_11936 : STD_LOGIC;
signal b_reg_25_CLKINV_11935 : STD_LOGIC;
signal b_reg_17_DXMUX_12000 : STD_LOGIC;
signal b_reg_mux0000_17_Q : STD_LOGIC;
signal b_reg_17_DYMUX_11986 : STD_LOGIC;
signal b_reg_mux0000_16_Q : STD_LOGIC;
signal b_reg_17_SRINV_11978 : STD_LOGIC;
signal b_reg_17_CLKINV_11977 : STD_LOGIC;
signal b_reg_27_DXMUX_12042 : STD_LOGIC;
signal b_reg_mux0000_27_Q : STD_LOGIC;
signal b_reg_27_DYMUX_12028 : STD_LOGIC;
signal b_reg_mux0000_26_Q : STD_LOGIC;
signal b_reg_27_SRINV_12020 : STD_LOGIC;
signal b_reg_27_CLKINV_12019 : STD_LOGIC;
signal b_reg_19_DXMUX_12084 : STD_LOGIC;
signal b_reg_mux0000_19_Q : STD_LOGIC;
signal b_reg_19_DYMUX_12070 : STD_LOGIC;
signal b_reg_mux0000_18_Q : STD_LOGIC;
signal b_reg_19_SRINV_12062 : STD_LOGIC;
signal b_reg_19_CLKINV_12061 : STD_LOGIC;
signal b_reg_29_DXMUX_12126 : STD_LOGIC;
signal b_reg_mux0000_29_Q : STD_LOGIC;
signal b_reg_29_DYMUX_12112 : STD_LOGIC;
signal b_reg_mux0000_28_Q : STD_LOGIC;
signal b_reg_29_SRINV_12104 : STD_LOGIC;
signal b_reg_29_CLKINV_12103 : STD_LOGIC;
signal Sh1287_12154 : STD_LOGIC;
signal Sh13220_12146 : STD_LOGIC;
signal Sh110 : STD_LOGIC;
signal Sh15013_12170 : STD_LOGIC;
signal Sh103 : STD_LOGIC;
signal Sh14313_12194 : STD_LOGIC;
signal Sh15816_12226 : STD_LOGIC;
signal Sh15113_12219 : STD_LOGIC;
signal Sh1310 : STD_LOGIC;
signal Sh15116_12243 : STD_LOGIC;
signal Sh14813_12274 : STD_LOGIC;
signal Sh14412_12265 : STD_LOGIC;
signal Sh12816 : STD_LOGIC;
signal Sh14413_12289 : STD_LOGIC;
signal Sh14616_12322 : STD_LOGIC;
signal Sh15413_12315 : STD_LOGIC;
signal Sh106 : STD_LOGIC;
signal Sh14613_12338 : STD_LOGIC;
signal Sh15516_12370 : STD_LOGIC;
signal Sh15513_12363 : STD_LOGIC;
signal Sh1527_12394 : STD_LOGIC;
signal Sh14816_12386 : STD_LOGIC;
signal Sh13013 : STD_LOGIC;
signal Sh15813_12411 : STD_LOGIC;
signal b_reg_0_2_DYMUX_12428 : STD_LOGIC;
signal b_reg_0_2_CLKINV_12425 : STD_LOGIC;
signal b_reg_0_3_DYMUX_12442 : STD_LOGIC;
signal b_reg_0_3_CLKINV_12439 : STD_LOGIC;
signal ab_xor_3_Q : STD_LOGIC;
signal ab_xor_4_Q : STD_LOGIC;
signal N247 : STD_LOGIC;
signal ab_xor_5_Q : STD_LOGIC;
signal N261 : STD_LOGIC;
signal ab_xor_7_Q : STD_LOGIC;
signal N260 : STD_LOGIC;
signal ab_xor_8_Q : STD_LOGIC;
signal N241 : STD_LOGIC;
signal ab_xor_9_Q : STD_LOGIC;
signal Sh102 : STD_LOGIC;
signal Sh98 : STD_LOGIC;
signal N520 : STD_LOGIC;
signal N286 : STD_LOGIC;
signal N522 : STD_LOGIC;
signal N224 : STD_LOGIC;
signal N518 : STD_LOGIC;
signal N226 : STD_LOGIC;
signal N258 : STD_LOGIC;
signal ab_xor_11_Q : STD_LOGIC;
signal N257 : STD_LOGIC;
signal ab_xor_12_Q : STD_LOGIC;
signal N188 : STD_LOGIC;
signal ab_xor_20_Q : STD_LOGIC;
signal N235 : STD_LOGIC;
signal ab_xor_13_Q : STD_LOGIC;
signal N214 : STD_LOGIC;
signal ab_xor_21_Q : STD_LOGIC;
signal N228 : STD_LOGIC;
signal ab_xor_15_Q : STD_LOGIC;
signal N202 : STD_LOGIC;
signal ab_xor_23_Q : STD_LOGIC;
signal N196 : STD_LOGIC;
signal ab_xor_31_Q : STD_LOGIC;
signal N194 : STD_LOGIC;
signal ab_xor_16_Q : STD_LOGIC;
signal N182 : STD_LOGIC;
signal ab_xor_24_Q : STD_LOGIC;
signal N217 : STD_LOGIC;
signal ab_xor_17_Q : STD_LOGIC;
signal N211 : STD_LOGIC;
signal ab_xor_25_Q : STD_LOGIC;
signal N205 : STD_LOGIC;
signal ab_xor_19_Q : STD_LOGIC;
signal N199 : STD_LOGIC;
signal ab_xor_27_Q : STD_LOGIC;
signal N176 : STD_LOGIC;
signal ab_xor_28_Q : STD_LOGIC;
signal N208 : STD_LOGIC;
signal ab_xor_29_Q : STD_LOGIC;
signal N191 : STD_LOGIC;
signal N193 : STD_LOGIC;
signal N179 : STD_LOGIC;
signal N181 : STD_LOGIC;
signal N289 : STD_LOGIC;
signal N190 : STD_LOGIC;
signal N288 : STD_LOGIC;
signal N178 : STD_LOGIC;
signal N185 : STD_LOGIC;
signal N187 : STD_LOGIC;
signal N173 : STD_LOGIC;
signal N175 : STD_LOGIC;
signal N264 : STD_LOGIC;
signal N184 : STD_LOGIC;
signal N263 : STD_LOGIC;
signal N172 : STD_LOGIC;
signal Sh86 : STD_LOGIC;
signal Sh70 : STD_LOGIC;
signal Sh87 : STD_LOGIC;
signal Sh71 : STD_LOGIC;
signal Sh80 : STD_LOGIC;
signal Sh64 : STD_LOGIC;
signal Sh88 : STD_LOGIC;
signal Sh72 : STD_LOGIC;
signal Sh5320 : STD_LOGIC;
signal Sh5720 : STD_LOGIC;
signal Sh81 : STD_LOGIC;
signal Sh65 : STD_LOGIC;
signal Sh5420 : STD_LOGIC;
signal Sh5820 : STD_LOGIC;
signal Sh82 : STD_LOGIC;
signal Sh66 : STD_LOGIC;
signal N246 : STD_LOGIC;
signal Sh90 : STD_LOGIC;
signal Sh83 : STD_LOGIC;
signal Sh67 : STD_LOGIC;
signal Sh91 : STD_LOGIC;
signal Sh75 : STD_LOGIC;
signal Sh84 : STD_LOGIC;
signal Sh68 : STD_LOGIC;
signal Sh92 : STD_LOGIC;
signal Sh76 : STD_LOGIC;
signal Sh85 : STD_LOGIC;
signal Sh69 : STD_LOGIC;
signal Sh79 : STD_LOGIC;
signal Sh93 : STD_LOGIC;
signal Sh89 : STD_LOGIC;
signal Sh94 : STD_LOGIC;
signal N254 : STD_LOGIC;
signal Sh991_13638 : STD_LOGIC;
signal Sh99 : STD_LOGIC;
signal Sh1011_pack_1 : STD_LOGIC;
signal b_reg_mux0000_2_13_13694 : STD_LOGIC;
signal b_reg_mux0000_2_5_13686 : STD_LOGIC;
signal b_reg_1_DXMUX_13736 : STD_LOGIC;
signal b_reg_1_F5MUX_13734 : STD_LOGIC;
signal N499 : STD_LOGIC;
signal b_reg_1_BXINV_13726 : STD_LOGIC;
signal b_reg_1_DYMUX_13719 : STD_LOGIC;
signal N498 : STD_LOGIC;
signal b_reg_1_SRINV_13711 : STD_LOGIC;
signal b_reg_1_CLKINV_13710 : STD_LOGIC;
signal b_reg_3_DXMUX_13760 : STD_LOGIC;
signal b_reg_3_DYMUX_13752 : STD_LOGIC;
signal b_reg_3_SRINV_13750 : STD_LOGIC;
signal b_reg_3_CLKINV_13749 : STD_LOGIC;
signal b_reg_4_DXMUX_13793 : STD_LOGIC;
signal b_reg_4_DYMUX_13785 : STD_LOGIC;
signal b_reg_mux0000_5_Q : STD_LOGIC;
signal b_reg_4_SRINV_13776 : STD_LOGIC;
signal b_reg_4_CLKINV_13775 : STD_LOGIC;
signal b_reg_mux0000_4_12_13821 : STD_LOGIC;
signal b_reg_mux0000_4_3_13813 : STD_LOGIC;
signal b_reg_mux0000_6_12_13845 : STD_LOGIC;
signal b_reg_mux0000_6_3_13837 : STD_LOGIC;
signal Mrom_b_rom000024_13869 : STD_LOGIC;
signal N27 : STD_LOGIC;
signal N111 : STD_LOGIC;
signal N12 : STD_LOGIC;
signal N20 : STD_LOGIC;
signal N17 : STD_LOGIC;
signal Mrom_b_rom00005_13941 : STD_LOGIC;
signal N222 : STD_LOGIC;
signal i_cnt_mux0001_0_25_13965 : STD_LOGIC;
signal i_cnt_mux0001_0_22_pack_1 : STD_LOGIC;
signal Sh1567_13989 : STD_LOGIC;
signal Sh12813 : STD_LOGIC;
signal Sh1577_14013 : STD_LOGIC;
signal Sh12913 : STD_LOGIC;
signal Sh1297_14037 : STD_LOGIC;
signal Sh12916 : STD_LOGIC;
signal Sh1497_14061 : STD_LOGIC;
signal Sh1537_14053 : STD_LOGIC;
signal Sh177 : STD_LOGIC;
signal Sh181 : STD_LOGIC;
signal Sh183 : STD_LOGIC;
signal Sh182 : STD_LOGIC;
signal Sh184 : STD_LOGIC;
signal Sh190 : STD_LOGIC;
signal Sh186 : STD_LOGIC;
signal Sh185 : STD_LOGIC;
signal Sh188 : STD_LOGIC;
signal Sh187 : STD_LOGIC;
signal Sh347 : STD_LOGIC;
signal Sh337 : STD_LOGIC;
signal Sh189 : STD_LOGIC;
signal Madd_b_pre_cy_4_Q : STD_LOGIC;
signal Madd_b_pre_cy_2_pack_1 : STD_LOGIC;
signal b_reg_mux0000_10_10 : STD_LOGIC;
signal Madd_b_pre_cy_6_pack_1 : STD_LOGIC;
signal segment_a_i_OBUF_14289 : STD_LOGIC;
signal segment_g_i_OBUF_14282 : STD_LOGIC;
signal segment_d_i_OBUF_14313 : STD_LOGIC;
signal segment_e_i_OBUF_14306 : STD_LOGIC;
signal segment_f_i_OBUF_14337 : STD_LOGIC;
signal segment_c_i_OBUF_14330 : STD_LOGIC;
signal segment_b_i_OBUF_14349 : STD_LOGIC;
signal N14 : STD_LOGIC;
signal N514 : STD_LOGIC;
signal i_cnt_2_DXMUX_14404 : STD_LOGIC;
signal N516_pack_3 : STD_LOGIC;
signal i_cnt_2_CLKINV_14388 : STD_LOGIC;
signal Mrom_b_rom000012_14432 : STD_LOGIC;
signal Mrom_a_rom000010 : STD_LOGIC;
signal Mrom_b_rom000020_14456 : STD_LOGIC;
signal Mrom_a_rom000011_14449 : STD_LOGIC;
signal Mrom_b_rom00008_14480 : STD_LOGIC;
signal Mrom_a_rom000021 : STD_LOGIC;
signal Mrom_b_rom000013_14504 : STD_LOGIC;
signal Mrom_a_rom000030 : STD_LOGIC;
signal Mrom_b_rom000031 : STD_LOGIC;
signal Mrom_a_rom000031 : STD_LOGIC;
signal Mrom_b_rom000023 : STD_LOGIC;
signal Mrom_a_rom000025 : STD_LOGIC;
signal Mrom_b_rom000017_14576 : STD_LOGIC;
signal Mrom_a_rom000026 : STD_LOGIC;
signal Mrom_b_rom00007 : STD_LOGIC;
signal Mrom_a_rom000019 : STD_LOGIC;
signal Mrom_b_rom000030 : STD_LOGIC;
signal Mrom_a_rom000027 : STD_LOGIC;
signal N237 : STD_LOGIC;
signal N251 : STD_LOGIC;
signal Mrom_b_rom000028 : STD_LOGIC;
signal Mrom_b_rom000011_14665 : STD_LOGIC;
signal N231 : STD_LOGIC;
signal N234 : STD_LOGIC;
signal Mrom_b_rom000026 : STD_LOGIC;
signal N77 : STD_LOGIC;
signal N33 : STD_LOGIC;
signal N34 : STD_LOGIC;
signal do_rdy_OBUF_14756 : STD_LOGIC;
signal Mrom_b_rom000022 : STD_LOGIC;
signal Mrom_a_rom00001 : STD_LOGIC;
signal Mrom_b_rom000016 : STD_LOGIC;
signal Mrom_a_rom0000 : STD_LOGIC;
signal Mrom_b_rom000010 : STD_LOGIC;
signal Mrom_a_rom000013_14821 : STD_LOGIC;
signal Mrom_b_rom00006 : STD_LOGIC;
signal Mrom_a_rom000023_14845 : STD_LOGIC;
signal Mrom_b_rom00009_14876 : STD_LOGIC;
signal Mrom_a_rom000015_14869 : STD_LOGIC;
signal Mrom_b_rom000021 : STD_LOGIC;
signal Mrom_a_rom000024_14893 : STD_LOGIC;
signal Mrom_b_rom000014_14924 : STD_LOGIC;
signal Mrom_a_rom000016_14917 : STD_LOGIC;
signal Mrom_b_rom00001 : STD_LOGIC;
signal Mrom_a_rom000017_14941 : STD_LOGIC;
signal Mrom_a_rom000029_14972 : STD_LOGIC;
signal Mrom_a_rom000018_14965 : STD_LOGIC;
signal Mrom_b_rom000029_14996 : STD_LOGIC;
signal Mrom_a_rom00006 : STD_LOGIC;
signal Mrom_a_rom00009_15020 : STD_LOGIC;
signal Mrom_a_rom00008 : STD_LOGIC;
signal Mrom_a_rom00005_15044 : STD_LOGIC;
signal Mrom_b_rom000019 : STD_LOGIC;
signal Mrom_a_rom00002_15068 : STD_LOGIC;
signal Mrom_b_rom000027 : STD_LOGIC;
signal state_FSM_FFd2_DXMUX_15109 : STD_LOGIC;
signal state_FSM_FFd2_In : STD_LOGIC;
signal state_FSM_FFd2_DYMUX_15095 : STD_LOGIC;
signal state_cmp_eq0000_pack_4 : STD_LOGIC;
signal state_FSM_FFd2_SRINV_15086 : STD_LOGIC;
signal state_FSM_FFd2_CLKINV_15085 : STD_LOGIC;
signal Mrom_b_rom0000 : STD_LOGIC;
signal Mrom_a_rom00004_15130 : STD_LOGIC;
signal N240 : STD_LOGIC;
signal N243 : STD_LOGIC;
signal hex_digit_i_3_FFX_RSTAND_9773 : STD_LOGIC;
signal b_reg_8_FFX_RSTAND_9245 : STD_LOGIC;
signal b_reg_9_FFX_RSTAND_9281 : STD_LOGIC;
signal b_reg_0_1_FFX_RSTAND_9543 : STD_LOGIC;
signal hex_digit_i_0_FFX_RSTAND_9579 : STD_LOGIC;
signal i_cnt_3_FFX_RSTAND_9665 : STD_LOGIC;
signal hex_digit_i_1_FFX_RSTAND_9701 : STD_LOGIC;
signal hex_digit_i_2_FFX_RSTAND_9737 : STD_LOGIC;
signal b_reg_2_1_FFY_RSTAND_10805 : STD_LOGIC;
signal b_reg_3_1_FFY_RSTAND_10829 : STD_LOGIC;
signal b_reg_4_1_FFY_RSTAND_10853 : STD_LOGIC;
signal b_reg_11_FFY_RSTAND_11711 : STD_LOGIC;
signal b_reg_0_2_FFY_RSTAND_12433 : STD_LOGIC;
signal b_reg_0_3_FFY_RSTAND_12447 : STD_LOGIC;
signal i_cnt_2_FFX_RSTAND_14409 : STD_LOGIC;
signal VCC : STD_LOGIC;
signal GND : STD_LOGIC;
signal LED_flash_cnt : STD_LOGIC_VECTOR ( 9 downto 0 );
signal b_reg : STD_LOGIC_VECTOR ( 31 downto 0 );
signal a : STD_LOGIC_VECTOR ( 31 downto 0 );
signal i_cnt : STD_LOGIC_VECTOR ( 3 downto 0 );
signal Madd_b_pre_lut : STD_LOGIC_VECTOR ( 2 downto 2 );
signal a_reg : STD_LOGIC_VECTOR ( 31 downto 0 );
signal hex_digit_i : STD_LOGIC_VECTOR ( 3 downto 0 );
signal Mcount_LED_flash_cnt_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
signal Madd_a_lut : STD_LOGIC_VECTOR ( 31 downto 0 );
signal Madd_b_lut : STD_LOGIC_VECTOR ( 31 downto 0 );
signal a_reg_mux0000 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal i_cnt_mux0001 : STD_LOGIC_VECTOR ( 3 downto 1 );
begin
NlwRenamedSig_IO_clr <= clr;
NlwRenamedSig_IO_di_vld <= di_vld;
LED_flash_cnt_0_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X31Y10"
)
port map (
O => LED_flash_cnt_0_LOGIC_ZERO_4631
);
LED_flash_cnt_0_LOGIC_ONE : X_ONE
generic map(
LOC => "SLICE_X31Y10"
)
port map (
O => LED_flash_cnt_0_LOGIC_ONE_4655
);
LED_flash_cnt_0_DXMUX : X_BUF
generic map(
LOC => "SLICE_X31Y10",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_0_XORF_4656,
O => LED_flash_cnt_0_DXMUX_4658
);
LED_flash_cnt_0_XORF : X_XOR2
generic map(
LOC => "SLICE_X31Y10"
)
port map (
I0 => LED_flash_cnt_0_CYINIT_4654,
I1 => Mcount_LED_flash_cnt_lut(0),
O => LED_flash_cnt_0_XORF_4656
);
LED_flash_cnt_0_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X31Y10"
)
port map (
IA => LED_flash_cnt_0_LOGIC_ONE_4655,
IB => LED_flash_cnt_0_CYINIT_4654,
SEL => LED_flash_cnt_0_CYSELF_4645,
O => Mcount_LED_flash_cnt_cy_0_Q
);
LED_flash_cnt_0_CYINIT : X_BUF
generic map(
LOC => "SLICE_X31Y10",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_0_BXINV_4643,
O => LED_flash_cnt_0_CYINIT_4654
);
LED_flash_cnt_0_CYSELF : X_BUF
generic map(
LOC => "SLICE_X31Y10",
PATHPULSE => 638 ps
)
port map (
I => Mcount_LED_flash_cnt_lut(0),
O => LED_flash_cnt_0_CYSELF_4645
);
LED_flash_cnt_0_BXINV : X_BUF
generic map(
LOC => "SLICE_X31Y10",
PATHPULSE => 638 ps
)
port map (
I => '0',
O => LED_flash_cnt_0_BXINV_4643
);
LED_flash_cnt_0_DYMUX : X_BUF
generic map(
LOC => "SLICE_X31Y10",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_0_XORG_4634,
O => LED_flash_cnt_0_DYMUX_4636
);
LED_flash_cnt_0_XORG : X_XOR2
generic map(
LOC => "SLICE_X31Y10"
)
port map (
I0 => Mcount_LED_flash_cnt_cy_0_Q,
I1 => LED_flash_cnt_0_G,
O => LED_flash_cnt_0_XORG_4634
);
LED_flash_cnt_0_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X31Y10",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_0_CYMUXG_4633,
O => Mcount_LED_flash_cnt_cy_1_Q
);
LED_flash_cnt_0_CYMUXG : X_MUX2
generic map(
LOC => "SLICE_X31Y10"
)
port map (
IA => LED_flash_cnt_0_LOGIC_ZERO_4631,
IB => Mcount_LED_flash_cnt_cy_0_Q,
SEL => LED_flash_cnt_0_CYSELG_4622,
O => LED_flash_cnt_0_CYMUXG_4633
);
LED_flash_cnt_0_CYSELG : X_BUF
generic map(
LOC => "SLICE_X31Y10",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_0_G,
O => LED_flash_cnt_0_CYSELG_4622
);
LED_flash_cnt_0_SRINV : X_BUF
generic map(
LOC => "SLICE_X31Y10",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => LED_flash_cnt_0_SRINV_4620
);
LED_flash_cnt_0_CLKINV : X_BUF
generic map(
LOC => "SLICE_X31Y10",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => LED_flash_cnt_0_CLKINV_4619
);
LED_flash_cnt_2_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X31Y11"
)
port map (
O => LED_flash_cnt_2_LOGIC_ZERO_4685
);
LED_flash_cnt_2_DXMUX : X_BUF
generic map(
LOC => "SLICE_X31Y11",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_2_XORF_4712,
O => LED_flash_cnt_2_DXMUX_4714
);
LED_flash_cnt_2_XORF : X_XOR2
generic map(
LOC => "SLICE_X31Y11"
)
port map (
I0 => LED_flash_cnt_2_CYINIT_4711,
I1 => LED_flash_cnt_2_F,
O => LED_flash_cnt_2_XORF_4712
);
LED_flash_cnt_2_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X31Y11"
)
port map (
IA => LED_flash_cnt_2_LOGIC_ZERO_4685,
IB => LED_flash_cnt_2_CYINIT_4711,
SEL => LED_flash_cnt_2_CYSELF_4691,
O => Mcount_LED_flash_cnt_cy_2_Q
);
LED_flash_cnt_2_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X31Y11"
)
port map (
IA => LED_flash_cnt_2_LOGIC_ZERO_4685,
IB => LED_flash_cnt_2_LOGIC_ZERO_4685,
SEL => LED_flash_cnt_2_CYSELF_4691,
O => LED_flash_cnt_2_CYMUXF2_4686
);
LED_flash_cnt_2_CYINIT : X_BUF
generic map(
LOC => "SLICE_X31Y11",
PATHPULSE => 638 ps
)
port map (
I => Mcount_LED_flash_cnt_cy_1_Q,
O => LED_flash_cnt_2_CYINIT_4711
);
LED_flash_cnt_2_CYSELF : X_BUF
generic map(
LOC => "SLICE_X31Y11",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_2_F,
O => LED_flash_cnt_2_CYSELF_4691
);
LED_flash_cnt_2_DYMUX : X_BUF
generic map(
LOC => "SLICE_X31Y11",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_2_XORG_4693,
O => LED_flash_cnt_2_DYMUX_4695
);
LED_flash_cnt_2_XORG : X_XOR2
generic map(
LOC => "SLICE_X31Y11"
)
port map (
I0 => Mcount_LED_flash_cnt_cy_2_Q,
I1 => LED_flash_cnt_2_G,
O => LED_flash_cnt_2_XORG_4693
);
LED_flash_cnt_2_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X31Y11",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_2_CYMUXFAST_4690,
O => Mcount_LED_flash_cnt_cy_3_Q
);
LED_flash_cnt_2_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X31Y11",
PATHPULSE => 638 ps
)
port map (
I => Mcount_LED_flash_cnt_cy_1_Q,
O => LED_flash_cnt_2_FASTCARRY_4688
);
LED_flash_cnt_2_CYAND : X_AND2
generic map(
LOC => "SLICE_X31Y11"
)
port map (
I0 => LED_flash_cnt_2_CYSELG_4676,
I1 => LED_flash_cnt_2_CYSELF_4691,
O => LED_flash_cnt_2_CYAND_4689
);
LED_flash_cnt_2_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X31Y11"
)
port map (
IA => LED_flash_cnt_2_CYMUXG2_4687,
IB => LED_flash_cnt_2_FASTCARRY_4688,
SEL => LED_flash_cnt_2_CYAND_4689,
O => LED_flash_cnt_2_CYMUXFAST_4690
);
LED_flash_cnt_2_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X31Y11"
)
port map (
IA => LED_flash_cnt_2_LOGIC_ZERO_4685,
IB => LED_flash_cnt_2_CYMUXF2_4686,
SEL => LED_flash_cnt_2_CYSELG_4676,
O => LED_flash_cnt_2_CYMUXG2_4687
);
LED_flash_cnt_2_CYSELG : X_BUF
generic map(
LOC => "SLICE_X31Y11",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_2_G,
O => LED_flash_cnt_2_CYSELG_4676
);
LED_flash_cnt_2_SRINV : X_BUF
generic map(
LOC => "SLICE_X31Y11",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => LED_flash_cnt_2_SRINV_4674
);
LED_flash_cnt_2_CLKINV : X_BUF
generic map(
LOC => "SLICE_X31Y11",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => LED_flash_cnt_2_CLKINV_4673
);
LED_flash_cnt_4_FFY_RSTOR : X_BUF
generic map(
LOC => "SLICE_X31Y12",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_4_SRINV_4730,
O => LED_flash_cnt_4_FFY_RST
);
LED_flash_cnt_5 : X_FF
generic map(
LOC => "SLICE_X31Y12",
INIT => '0'
)
port map (
I => LED_flash_cnt_4_DYMUX_4751,
CE => VCC,
CLK => LED_flash_cnt_4_CLKINV_4729,
SET => GND,
RST => LED_flash_cnt_4_FFY_RST,
O => LED_flash_cnt(5)
);
LED_flash_cnt_4_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X31Y12"
)
port map (
O => LED_flash_cnt_4_LOGIC_ZERO_4741
);
LED_flash_cnt_4_DXMUX : X_BUF
generic map(
LOC => "SLICE_X31Y12",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_4_XORF_4768,
O => LED_flash_cnt_4_DXMUX_4770
);
LED_flash_cnt_4_XORF : X_XOR2
generic map(
LOC => "SLICE_X31Y12"
)
port map (
I0 => LED_flash_cnt_4_CYINIT_4767,
I1 => LED_flash_cnt_4_F,
O => LED_flash_cnt_4_XORF_4768
);
LED_flash_cnt_4_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X31Y12"
)
port map (
IA => LED_flash_cnt_4_LOGIC_ZERO_4741,
IB => LED_flash_cnt_4_CYINIT_4767,
SEL => LED_flash_cnt_4_CYSELF_4747,
O => Mcount_LED_flash_cnt_cy_4_Q
);
LED_flash_cnt_4_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X31Y12"
)
port map (
IA => LED_flash_cnt_4_LOGIC_ZERO_4741,
IB => LED_flash_cnt_4_LOGIC_ZERO_4741,
SEL => LED_flash_cnt_4_CYSELF_4747,
O => LED_flash_cnt_4_CYMUXF2_4742
);
LED_flash_cnt_4_CYINIT : X_BUF
generic map(
LOC => "SLICE_X31Y12",
PATHPULSE => 638 ps
)
port map (
I => Mcount_LED_flash_cnt_cy_3_Q,
O => LED_flash_cnt_4_CYINIT_4767
);
LED_flash_cnt_4_CYSELF : X_BUF
generic map(
LOC => "SLICE_X31Y12",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_4_F,
O => LED_flash_cnt_4_CYSELF_4747
);
LED_flash_cnt_4_DYMUX : X_BUF
generic map(
LOC => "SLICE_X31Y12",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_4_XORG_4749,
O => LED_flash_cnt_4_DYMUX_4751
);
LED_flash_cnt_4_XORG : X_XOR2
generic map(
LOC => "SLICE_X31Y12"
)
port map (
I0 => Mcount_LED_flash_cnt_cy_4_Q,
I1 => LED_flash_cnt_4_G,
O => LED_flash_cnt_4_XORG_4749
);
LED_flash_cnt_4_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X31Y12",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_4_CYMUXFAST_4746,
O => Mcount_LED_flash_cnt_cy_5_Q
);
LED_flash_cnt_4_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X31Y12",
PATHPULSE => 638 ps
)
port map (
I => Mcount_LED_flash_cnt_cy_3_Q,
O => LED_flash_cnt_4_FASTCARRY_4744
);
LED_flash_cnt_4_CYAND : X_AND2
generic map(
LOC => "SLICE_X31Y12"
)
port map (
I0 => LED_flash_cnt_4_CYSELG_4732,
I1 => LED_flash_cnt_4_CYSELF_4747,
O => LED_flash_cnt_4_CYAND_4745
);
LED_flash_cnt_4_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X31Y12"
)
port map (
IA => LED_flash_cnt_4_CYMUXG2_4743,
IB => LED_flash_cnt_4_FASTCARRY_4744,
SEL => LED_flash_cnt_4_CYAND_4745,
O => LED_flash_cnt_4_CYMUXFAST_4746
);
LED_flash_cnt_4_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X31Y12"
)
port map (
IA => LED_flash_cnt_4_LOGIC_ZERO_4741,
IB => LED_flash_cnt_4_CYMUXF2_4742,
SEL => LED_flash_cnt_4_CYSELG_4732,
O => LED_flash_cnt_4_CYMUXG2_4743
);
LED_flash_cnt_4_CYSELG : X_BUF
generic map(
LOC => "SLICE_X31Y12",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_4_G,
O => LED_flash_cnt_4_CYSELG_4732
);
LED_flash_cnt_4_SRINV : X_BUF
generic map(
LOC => "SLICE_X31Y12",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => LED_flash_cnt_4_SRINV_4730
);
LED_flash_cnt_4_CLKINV : X_BUF
generic map(
LOC => "SLICE_X31Y12",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => LED_flash_cnt_4_CLKINV_4729
);
LED_flash_cnt_6_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X31Y13"
)
port map (
O => LED_flash_cnt_6_LOGIC_ZERO_4797
);
LED_flash_cnt_6_DXMUX : X_BUF
generic map(
LOC => "SLICE_X31Y13",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_6_XORF_4824,
O => LED_flash_cnt_6_DXMUX_4826
);
LED_flash_cnt_6_XORF : X_XOR2
generic map(
LOC => "SLICE_X31Y13"
)
port map (
I0 => LED_flash_cnt_6_CYINIT_4823,
I1 => LED_flash_cnt_6_F,
O => LED_flash_cnt_6_XORF_4824
);
LED_flash_cnt_6_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X31Y13"
)
port map (
IA => LED_flash_cnt_6_LOGIC_ZERO_4797,
IB => LED_flash_cnt_6_CYINIT_4823,
SEL => LED_flash_cnt_6_CYSELF_4803,
O => Mcount_LED_flash_cnt_cy_6_Q
);
LED_flash_cnt_6_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X31Y13"
)
port map (
IA => LED_flash_cnt_6_LOGIC_ZERO_4797,
IB => LED_flash_cnt_6_LOGIC_ZERO_4797,
SEL => LED_flash_cnt_6_CYSELF_4803,
O => LED_flash_cnt_6_CYMUXF2_4798
);
LED_flash_cnt_6_CYINIT : X_BUF
generic map(
LOC => "SLICE_X31Y13",
PATHPULSE => 638 ps
)
port map (
I => Mcount_LED_flash_cnt_cy_5_Q,
O => LED_flash_cnt_6_CYINIT_4823
);
LED_flash_cnt_6_CYSELF : X_BUF
generic map(
LOC => "SLICE_X31Y13",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_6_F,
O => LED_flash_cnt_6_CYSELF_4803
);
LED_flash_cnt_6_DYMUX : X_BUF
generic map(
LOC => "SLICE_X31Y13",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_6_XORG_4805,
O => LED_flash_cnt_6_DYMUX_4807
);
LED_flash_cnt_6_XORG : X_XOR2
generic map(
LOC => "SLICE_X31Y13"
)
port map (
I0 => Mcount_LED_flash_cnt_cy_6_Q,
I1 => LED_flash_cnt_6_G,
O => LED_flash_cnt_6_XORG_4805
);
LED_flash_cnt_6_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X31Y13",
PATHPULSE => 638 ps
)
port map (
I => Mcount_LED_flash_cnt_cy_5_Q,
O => LED_flash_cnt_6_FASTCARRY_4800
);
LED_flash_cnt_6_CYAND : X_AND2
generic map(
LOC => "SLICE_X31Y13"
)
port map (
I0 => LED_flash_cnt_6_CYSELG_4788,
I1 => LED_flash_cnt_6_CYSELF_4803,
O => LED_flash_cnt_6_CYAND_4801
);
LED_flash_cnt_6_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X31Y13"
)
port map (
IA => LED_flash_cnt_6_CYMUXG2_4799,
IB => LED_flash_cnt_6_FASTCARRY_4800,
SEL => LED_flash_cnt_6_CYAND_4801,
O => LED_flash_cnt_6_CYMUXFAST_4802
);
LED_flash_cnt_6_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X31Y13"
)
port map (
IA => LED_flash_cnt_6_LOGIC_ZERO_4797,
IB => LED_flash_cnt_6_CYMUXF2_4798,
SEL => LED_flash_cnt_6_CYSELG_4788,
O => LED_flash_cnt_6_CYMUXG2_4799
);
LED_flash_cnt_6_CYSELG : X_BUF
generic map(
LOC => "SLICE_X31Y13",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_6_G,
O => LED_flash_cnt_6_CYSELG_4788
);
LED_flash_cnt_6_SRINV : X_BUF
generic map(
LOC => "SLICE_X31Y13",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => LED_flash_cnt_6_SRINV_4786
);
LED_flash_cnt_6_CLKINV : X_BUF
generic map(
LOC => "SLICE_X31Y13",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => LED_flash_cnt_6_CLKINV_4785
);
LED_flash_cnt_8_LOGIC_ZERO : X_ZERO
generic map(
LOC => "SLICE_X31Y14"
)
port map (
O => LED_flash_cnt_8_LOGIC_ZERO_4872
);
LED_flash_cnt_8_DXMUX : X_BUF
generic map(
LOC => "SLICE_X31Y14",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_8_XORF_4873,
O => LED_flash_cnt_8_DXMUX_4875
);
LED_flash_cnt_8_XORF : X_XOR2
generic map(
LOC => "SLICE_X31Y14"
)
port map (
I0 => LED_flash_cnt_8_CYINIT_4871,
I1 => LED_flash_cnt_8_F,
O => LED_flash_cnt_8_XORF_4873
);
LED_flash_cnt_8_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X31Y14"
)
port map (
IA => LED_flash_cnt_8_LOGIC_ZERO_4872,
IB => LED_flash_cnt_8_CYINIT_4871,
SEL => LED_flash_cnt_8_CYSELF_4862,
O => Mcount_LED_flash_cnt_cy_8_Q
);
LED_flash_cnt_8_CYINIT : X_BUF
generic map(
LOC => "SLICE_X31Y14",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_6_CYMUXFAST_4802,
O => LED_flash_cnt_8_CYINIT_4871
);
LED_flash_cnt_8_CYSELF : X_BUF
generic map(
LOC => "SLICE_X31Y14",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_8_F,
O => LED_flash_cnt_8_CYSELF_4862
);
LED_flash_cnt_8_DYMUX : X_BUF
generic map(
LOC => "SLICE_X31Y14",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt_8_XORG_4852,
O => LED_flash_cnt_8_DYMUX_4854
);
LED_flash_cnt_8_XORG : X_XOR2
generic map(
LOC => "SLICE_X31Y14"
)
port map (
I0 => Mcount_LED_flash_cnt_cy_8_Q,
I1 => LED_flash_cnt_9_rt_4849,
O => LED_flash_cnt_8_XORG_4852
);
LED_flash_cnt_8_SRINV : X_BUF
generic map(
LOC => "SLICE_X31Y14",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => LED_flash_cnt_8_SRINV_4841
);
LED_flash_cnt_8_CLKINV : X_BUF
generic map(
LOC => "SLICE_X31Y14",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => LED_flash_cnt_8_CLKINV_4840
);
LED_flash_cnt_9_rt : X_LUT4
generic map(
INIT => X"AAAA",
LOC => "SLICE_X31Y14"
)
port map (
ADR0 => LED_flash_cnt(9),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => LED_flash_cnt_9_rt_4849
);
a_0_XUSED : X_BUF
generic map(
LOC => "SLICE_X17Y16",
PATHPULSE => 638 ps
)
port map (
I => a_0_XORF_4918,
O => a(0)
);
a_0_XORF : X_XOR2
generic map(
LOC => "SLICE_X17Y16"
)
port map (
I0 => a_0_CYINIT_4917,
I1 => Madd_a_lut(0),
O => a_0_XORF_4918
);
a_0_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X17Y16"
)
port map (
IA => a_0_CY0F_4916,
IB => a_0_CYINIT_4917,
SEL => a_0_CYSELF_4908,
O => Madd_a_cy_0_Q
);
a_0_CYINIT : X_BUF
generic map(
LOC => "SLICE_X17Y16",
PATHPULSE => 638 ps
)
port map (
I => a_0_BXINV_4906,
O => a_0_CYINIT_4917
);
a_0_CY0F : X_BUF
generic map(
LOC => "SLICE_X17Y16",
PATHPULSE => 638 ps
)
port map (
I => Sh64_0,
O => a_0_CY0F_4916
);
a_0_CYSELF : X_BUF
generic map(
LOC => "SLICE_X17Y16",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(0),
O => a_0_CYSELF_4908
);
a_0_BXINV : X_BUF
generic map(
LOC => "SLICE_X17Y16",
PATHPULSE => 638 ps
)
port map (
I => '0',
O => a_0_BXINV_4906
);
a_0_YUSED : X_BUF
generic map(
LOC => "SLICE_X17Y16",
PATHPULSE => 638 ps
)
port map (
I => a_0_XORG_4904,
O => a(1)
);
a_0_XORG : X_XOR2
generic map(
LOC => "SLICE_X17Y16"
)
port map (
I0 => Madd_a_cy_0_Q,
I1 => Madd_a_lut(1),
O => a_0_XORG_4904
);
a_0_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X17Y16",
PATHPULSE => 638 ps
)
port map (
I => a_0_CYMUXG_4903,
O => Madd_a_cy_1_Q
);
a_0_CYMUXG : X_MUX2
generic map(
LOC => "SLICE_X17Y16"
)
port map (
IA => a_0_CY0G_4901,
IB => Madd_a_cy_0_Q,
SEL => a_0_CYSELG_4895,
O => a_0_CYMUXG_4903
);
a_0_CY0G : X_BUF
generic map(
LOC => "SLICE_X17Y16",
PATHPULSE => 638 ps
)
port map (
I => Sh65,
O => a_0_CY0G_4901
);
a_0_CYSELG : X_BUF
generic map(
LOC => "SLICE_X17Y16",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(1),
O => a_0_CYSELG_4895
);
a_2_XUSED : X_BUF
generic map(
LOC => "SLICE_X17Y17",
PATHPULSE => 638 ps
)
port map (
I => a_2_XORF_4961,
O => a(2)
);
a_2_XORF : X_XOR2
generic map(
LOC => "SLICE_X17Y17"
)
port map (
I0 => a_2_CYINIT_4960,
I1 => Madd_a_lut(2),
O => a_2_XORF_4961
);
a_2_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X17Y17"
)
port map (
IA => a_2_CY0F_4959,
IB => a_2_CYINIT_4960,
SEL => a_2_CYSELF_4948,
O => Madd_a_cy_2_Q
);
a_2_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X17Y17"
)
port map (
IA => a_2_CY0F_4959,
IB => a_2_CY0F_4959,
SEL => a_2_CYSELF_4948,
O => a_2_CYMUXF2_4943
);
a_2_CYINIT : X_BUF
generic map(
LOC => "SLICE_X17Y17",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_1_Q,
O => a_2_CYINIT_4960
);
a_2_CY0F : X_BUF
generic map(
LOC => "SLICE_X17Y17",
PATHPULSE => 638 ps
)
port map (
I => Sh66,
O => a_2_CY0F_4959
);
a_2_CYSELF : X_BUF
generic map(
LOC => "SLICE_X17Y17",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(2),
O => a_2_CYSELF_4948
);
a_2_YUSED : X_BUF
generic map(
LOC => "SLICE_X17Y17",
PATHPULSE => 638 ps
)
port map (
I => a_2_XORG_4950,
O => a(3)
);
a_2_XORG : X_XOR2
generic map(
LOC => "SLICE_X17Y17"
)
port map (
I0 => Madd_a_cy_2_Q,
I1 => Madd_a_lut(3),
O => a_2_XORG_4950
);
a_2_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X17Y17",
PATHPULSE => 638 ps
)
port map (
I => a_2_CYMUXFAST_4947,
O => Madd_a_cy_3_Q
);
a_2_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X17Y17",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_1_Q,
O => a_2_FASTCARRY_4945
);
a_2_CYAND : X_AND2
generic map(
LOC => "SLICE_X17Y17"
)
port map (
I0 => a_2_CYSELG_4936,
I1 => a_2_CYSELF_4948,
O => a_2_CYAND_4946
);
a_2_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X17Y17"
)
port map (
IA => a_2_CYMUXG2_4944,
IB => a_2_FASTCARRY_4945,
SEL => a_2_CYAND_4946,
O => a_2_CYMUXFAST_4947
);
a_2_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X17Y17"
)
port map (
IA => a_2_CY0G_4942,
IB => a_2_CYMUXF2_4943,
SEL => a_2_CYSELG_4936,
O => a_2_CYMUXG2_4944
);
a_2_CY0G : X_BUF
generic map(
LOC => "SLICE_X17Y17",
PATHPULSE => 638 ps
)
port map (
I => Sh67,
O => a_2_CY0G_4942
);
a_2_CYSELG : X_BUF
generic map(
LOC => "SLICE_X17Y17",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(3),
O => a_2_CYSELG_4936
);
Madd_a_lut_5_Q : X_LUT4
generic map(
INIT => X"1ED2",
LOC => "SLICE_X17Y18"
)
port map (
ADR0 => Sh37,
ADR1 => b_reg(4),
ADR2 => Mrom_a_rom00005_0,
ADR3 => Sh53,
O => Madd_a_lut(5)
);
a_4_XUSED : X_BUF
generic map(
LOC => "SLICE_X17Y18",
PATHPULSE => 638 ps
)
port map (
I => a_4_XORF_5004,
O => a(4)
);
a_4_XORF : X_XOR2
generic map(
LOC => "SLICE_X17Y18"
)
port map (
I0 => a_4_CYINIT_5003,
I1 => Madd_a_lut(4),
O => a_4_XORF_5004
);
a_4_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X17Y18"
)
port map (
IA => a_4_CY0F_5002,
IB => a_4_CYINIT_5003,
SEL => a_4_CYSELF_4991,
O => Madd_a_cy_4_Q
);
a_4_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X17Y18"
)
port map (
IA => a_4_CY0F_5002,
IB => a_4_CY0F_5002,
SEL => a_4_CYSELF_4991,
O => a_4_CYMUXF2_4986
);
a_4_CYINIT : X_BUF
generic map(
LOC => "SLICE_X17Y18",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_3_Q,
O => a_4_CYINIT_5003
);
a_4_CY0F : X_BUF
generic map(
LOC => "SLICE_X17Y18",
PATHPULSE => 638 ps
)
port map (
I => Sh68,
O => a_4_CY0F_5002
);
a_4_CYSELF : X_BUF
generic map(
LOC => "SLICE_X17Y18",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(4),
O => a_4_CYSELF_4991
);
a_4_YUSED : X_BUF
generic map(
LOC => "SLICE_X17Y18",
PATHPULSE => 638 ps
)
port map (
I => a_4_XORG_4993,
O => a(5)
);
a_4_XORG : X_XOR2
generic map(
LOC => "SLICE_X17Y18"
)
port map (
I0 => Madd_a_cy_4_Q,
I1 => Madd_a_lut(5),
O => a_4_XORG_4993
);
a_4_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X17Y18",
PATHPULSE => 638 ps
)
port map (
I => a_4_CYMUXFAST_4990,
O => Madd_a_cy_5_Q
);
a_4_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X17Y18",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_3_Q,
O => a_4_FASTCARRY_4988
);
a_4_CYAND : X_AND2
generic map(
LOC => "SLICE_X17Y18"
)
port map (
I0 => a_4_CYSELG_4979,
I1 => a_4_CYSELF_4991,
O => a_4_CYAND_4989
);
a_4_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X17Y18"
)
port map (
IA => a_4_CYMUXG2_4987,
IB => a_4_FASTCARRY_4988,
SEL => a_4_CYAND_4989,
O => a_4_CYMUXFAST_4990
);
a_4_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X17Y18"
)
port map (
IA => a_4_CY0G_4985,
IB => a_4_CYMUXF2_4986,
SEL => a_4_CYSELG_4979,
O => a_4_CYMUXG2_4987
);
a_4_CY0G : X_BUF
generic map(
LOC => "SLICE_X17Y18",
PATHPULSE => 638 ps
)
port map (
I => Sh69,
O => a_4_CY0G_4985
);
a_4_CYSELG : X_BUF
generic map(
LOC => "SLICE_X17Y18",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(5),
O => a_4_CYSELG_4979
);
a_6_XUSED : X_BUF
generic map(
LOC => "SLICE_X17Y19",
PATHPULSE => 638 ps
)
port map (
I => a_6_XORF_5047,
O => a(6)
);
a_6_XORF : X_XOR2
generic map(
LOC => "SLICE_X17Y19"
)
port map (
I0 => a_6_CYINIT_5046,
I1 => Madd_a_lut(6),
O => a_6_XORF_5047
);
a_6_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X17Y19"
)
port map (
IA => a_6_CY0F_5045,
IB => a_6_CYINIT_5046,
SEL => a_6_CYSELF_5034,
O => Madd_a_cy_6_Q
);
a_6_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X17Y19"
)
port map (
IA => a_6_CY0F_5045,
IB => a_6_CY0F_5045,
SEL => a_6_CYSELF_5034,
O => a_6_CYMUXF2_5029
);
a_6_CYINIT : X_BUF
generic map(
LOC => "SLICE_X17Y19",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_5_Q,
O => a_6_CYINIT_5046
);
a_6_CY0F : X_BUF
generic map(
LOC => "SLICE_X17Y19",
PATHPULSE => 638 ps
)
port map (
I => Sh70,
O => a_6_CY0F_5045
);
a_6_CYSELF : X_BUF
generic map(
LOC => "SLICE_X17Y19",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(6),
O => a_6_CYSELF_5034
);
a_6_YUSED : X_BUF
generic map(
LOC => "SLICE_X17Y19",
PATHPULSE => 638 ps
)
port map (
I => a_6_XORG_5036,
O => a(7)
);
a_6_XORG : X_XOR2
generic map(
LOC => "SLICE_X17Y19"
)
port map (
I0 => Madd_a_cy_6_Q,
I1 => Madd_a_lut(7),
O => a_6_XORG_5036
);
a_6_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X17Y19",
PATHPULSE => 638 ps
)
port map (
I => a_6_CYMUXFAST_5033,
O => Madd_a_cy_7_Q
);
a_6_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X17Y19",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_5_Q,
O => a_6_FASTCARRY_5031
);
a_6_CYAND : X_AND2
generic map(
LOC => "SLICE_X17Y19"
)
port map (
I0 => a_6_CYSELG_5022,
I1 => a_6_CYSELF_5034,
O => a_6_CYAND_5032
);
a_6_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X17Y19"
)
port map (
IA => a_6_CYMUXG2_5030,
IB => a_6_FASTCARRY_5031,
SEL => a_6_CYAND_5032,
O => a_6_CYMUXFAST_5033
);
a_6_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X17Y19"
)
port map (
IA => a_6_CY0G_5028,
IB => a_6_CYMUXF2_5029,
SEL => a_6_CYSELG_5022,
O => a_6_CYMUXG2_5030
);
a_6_CY0G : X_BUF
generic map(
LOC => "SLICE_X17Y19",
PATHPULSE => 638 ps
)
port map (
I => Sh71,
O => a_6_CY0G_5028
);
a_6_CYSELG : X_BUF
generic map(
LOC => "SLICE_X17Y19",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(7),
O => a_6_CYSELG_5022
);
a_8_XUSED : X_BUF
generic map(
LOC => "SLICE_X17Y20",
PATHPULSE => 638 ps
)
port map (
I => a_8_XORF_5090,
O => a(8)
);
a_8_XORF : X_XOR2
generic map(
LOC => "SLICE_X17Y20"
)
port map (
I0 => a_8_CYINIT_5089,
I1 => Madd_a_lut(8),
O => a_8_XORF_5090
);
a_8_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X17Y20"
)
port map (
IA => a_8_CY0F_5088,
IB => a_8_CYINIT_5089,
SEL => a_8_CYSELF_5077,
O => Madd_a_cy_8_Q
);
a_8_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X17Y20"
)
port map (
IA => a_8_CY0F_5088,
IB => a_8_CY0F_5088,
SEL => a_8_CYSELF_5077,
O => a_8_CYMUXF2_5072
);
a_8_CYINIT : X_BUF
generic map(
LOC => "SLICE_X17Y20",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_7_Q,
O => a_8_CYINIT_5089
);
a_8_CY0F : X_BUF
generic map(
LOC => "SLICE_X17Y20",
PATHPULSE => 638 ps
)
port map (
I => Sh72,
O => a_8_CY0F_5088
);
a_8_CYSELF : X_BUF
generic map(
LOC => "SLICE_X17Y20",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(8),
O => a_8_CYSELF_5077
);
a_8_YUSED : X_BUF
generic map(
LOC => "SLICE_X17Y20",
PATHPULSE => 638 ps
)
port map (
I => a_8_XORG_5079,
O => a(9)
);
a_8_XORG : X_XOR2
generic map(
LOC => "SLICE_X17Y20"
)
port map (
I0 => Madd_a_cy_8_Q,
I1 => Madd_a_lut(9),
O => a_8_XORG_5079
);
a_8_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X17Y20",
PATHPULSE => 638 ps
)
port map (
I => a_8_CYMUXFAST_5076,
O => Madd_a_cy_9_Q
);
a_8_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X17Y20",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_7_Q,
O => a_8_FASTCARRY_5074
);
a_8_CYAND : X_AND2
generic map(
LOC => "SLICE_X17Y20"
)
port map (
I0 => a_8_CYSELG_5065,
I1 => a_8_CYSELF_5077,
O => a_8_CYAND_5075
);
a_8_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X17Y20"
)
port map (
IA => a_8_CYMUXG2_5073,
IB => a_8_FASTCARRY_5074,
SEL => a_8_CYAND_5075,
O => a_8_CYMUXFAST_5076
);
a_8_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X17Y20"
)
port map (
IA => a_8_CY0G_5071,
IB => a_8_CYMUXF2_5072,
SEL => a_8_CYSELG_5065,
O => a_8_CYMUXG2_5073
);
a_8_CY0G : X_BUF
generic map(
LOC => "SLICE_X17Y20",
PATHPULSE => 638 ps
)
port map (
I => Sh73,
O => a_8_CY0G_5071
);
a_8_CYSELG : X_BUF
generic map(
LOC => "SLICE_X17Y20",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(9),
O => a_8_CYSELG_5065
);
a_10_XUSED : X_BUF
generic map(
LOC => "SLICE_X17Y21",
PATHPULSE => 638 ps
)
port map (
I => a_10_XORF_5133,
O => a(10)
);
a_10_XORF : X_XOR2
generic map(
LOC => "SLICE_X17Y21"
)
port map (
I0 => a_10_CYINIT_5132,
I1 => Madd_a_lut(10),
O => a_10_XORF_5133
);
a_10_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X17Y21"
)
port map (
IA => a_10_CY0F_5131,
IB => a_10_CYINIT_5132,
SEL => a_10_CYSELF_5120,
O => Madd_a_cy_10_Q
);
a_10_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X17Y21"
)
port map (
IA => a_10_CY0F_5131,
IB => a_10_CY0F_5131,
SEL => a_10_CYSELF_5120,
O => a_10_CYMUXF2_5115
);
a_10_CYINIT : X_BUF
generic map(
LOC => "SLICE_X17Y21",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_9_Q,
O => a_10_CYINIT_5132
);
a_10_CY0F : X_BUF
generic map(
LOC => "SLICE_X17Y21",
PATHPULSE => 638 ps
)
port map (
I => Sh74,
O => a_10_CY0F_5131
);
a_10_CYSELF : X_BUF
generic map(
LOC => "SLICE_X17Y21",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(10),
O => a_10_CYSELF_5120
);
a_10_YUSED : X_BUF
generic map(
LOC => "SLICE_X17Y21",
PATHPULSE => 638 ps
)
port map (
I => a_10_XORG_5122,
O => a(11)
);
a_10_XORG : X_XOR2
generic map(
LOC => "SLICE_X17Y21"
)
port map (
I0 => Madd_a_cy_10_Q,
I1 => Madd_a_lut(11),
O => a_10_XORG_5122
);
a_10_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X17Y21",
PATHPULSE => 638 ps
)
port map (
I => a_10_CYMUXFAST_5119,
O => Madd_a_cy_11_Q
);
a_10_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X17Y21",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_9_Q,
O => a_10_FASTCARRY_5117
);
a_10_CYAND : X_AND2
generic map(
LOC => "SLICE_X17Y21"
)
port map (
I0 => a_10_CYSELG_5108,
I1 => a_10_CYSELF_5120,
O => a_10_CYAND_5118
);
a_10_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X17Y21"
)
port map (
IA => a_10_CYMUXG2_5116,
IB => a_10_FASTCARRY_5117,
SEL => a_10_CYAND_5118,
O => a_10_CYMUXFAST_5119
);
a_10_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X17Y21"
)
port map (
IA => a_10_CY0G_5114,
IB => a_10_CYMUXF2_5115,
SEL => a_10_CYSELG_5108,
O => a_10_CYMUXG2_5116
);
a_10_CY0G : X_BUF
generic map(
LOC => "SLICE_X17Y21",
PATHPULSE => 638 ps
)
port map (
I => Sh75,
O => a_10_CY0G_5114
);
a_10_CYSELG : X_BUF
generic map(
LOC => "SLICE_X17Y21",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(11),
O => a_10_CYSELG_5108
);
Madd_a_lut_13_Q : X_LUT4
generic map(
INIT => X"4B78",
LOC => "SLICE_X17Y22"
)
port map (
ADR0 => Sh61,
ADR1 => b_reg(4),
ADR2 => Mrom_a_rom000013_0,
ADR3 => Sh45,
O => Madd_a_lut(13)
);
a_12_XUSED : X_BUF
generic map(
LOC => "SLICE_X17Y22",
PATHPULSE => 638 ps
)
port map (
I => a_12_XORF_5176,
O => a(12)
);
a_12_XORF : X_XOR2
generic map(
LOC => "SLICE_X17Y22"
)
port map (
I0 => a_12_CYINIT_5175,
I1 => Madd_a_lut(12),
O => a_12_XORF_5176
);
a_12_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X17Y22"
)
port map (
IA => a_12_CY0F_5174,
IB => a_12_CYINIT_5175,
SEL => a_12_CYSELF_5163,
O => Madd_a_cy_12_Q
);
a_12_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X17Y22"
)
port map (
IA => a_12_CY0F_5174,
IB => a_12_CY0F_5174,
SEL => a_12_CYSELF_5163,
O => a_12_CYMUXF2_5158
);
a_12_CYINIT : X_BUF
generic map(
LOC => "SLICE_X17Y22",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_11_Q,
O => a_12_CYINIT_5175
);
a_12_CY0F : X_BUF
generic map(
LOC => "SLICE_X17Y22",
PATHPULSE => 638 ps
)
port map (
I => Sh76,
O => a_12_CY0F_5174
);
a_12_CYSELF : X_BUF
generic map(
LOC => "SLICE_X17Y22",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(12),
O => a_12_CYSELF_5163
);
a_12_YUSED : X_BUF
generic map(
LOC => "SLICE_X17Y22",
PATHPULSE => 638 ps
)
port map (
I => a_12_XORG_5165,
O => a(13)
);
a_12_XORG : X_XOR2
generic map(
LOC => "SLICE_X17Y22"
)
port map (
I0 => Madd_a_cy_12_Q,
I1 => Madd_a_lut(13),
O => a_12_XORG_5165
);
a_12_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X17Y22",
PATHPULSE => 638 ps
)
port map (
I => a_12_CYMUXFAST_5162,
O => Madd_a_cy_13_Q
);
a_12_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X17Y22",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_11_Q,
O => a_12_FASTCARRY_5160
);
a_12_CYAND : X_AND2
generic map(
LOC => "SLICE_X17Y22"
)
port map (
I0 => a_12_CYSELG_5151,
I1 => a_12_CYSELF_5163,
O => a_12_CYAND_5161
);
a_12_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X17Y22"
)
port map (
IA => a_12_CYMUXG2_5159,
IB => a_12_FASTCARRY_5160,
SEL => a_12_CYAND_5161,
O => a_12_CYMUXFAST_5162
);
a_12_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X17Y22"
)
port map (
IA => a_12_CY0G_5157,
IB => a_12_CYMUXF2_5158,
SEL => a_12_CYSELG_5151,
O => a_12_CYMUXG2_5159
);
a_12_CY0G : X_BUF
generic map(
LOC => "SLICE_X17Y22",
PATHPULSE => 638 ps
)
port map (
I => Sh77,
O => a_12_CY0G_5157
);
a_12_CYSELG : X_BUF
generic map(
LOC => "SLICE_X17Y22",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(13),
O => a_12_CYSELG_5151
);
a_14_XUSED : X_BUF
generic map(
LOC => "SLICE_X17Y23",
PATHPULSE => 638 ps
)
port map (
I => a_14_XORF_5219,
O => a(14)
);
a_14_XORF : X_XOR2
generic map(
LOC => "SLICE_X17Y23"
)
port map (
I0 => a_14_CYINIT_5218,
I1 => Madd_a_lut(14),
O => a_14_XORF_5219
);
a_14_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X17Y23"
)
port map (
IA => a_14_CY0F_5217,
IB => a_14_CYINIT_5218,
SEL => a_14_CYSELF_5206,
O => Madd_a_cy_14_Q
);
a_14_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X17Y23"
)
port map (
IA => a_14_CY0F_5217,
IB => a_14_CY0F_5217,
SEL => a_14_CYSELF_5206,
O => a_14_CYMUXF2_5201
);
a_14_CYINIT : X_BUF
generic map(
LOC => "SLICE_X17Y23",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_13_Q,
O => a_14_CYINIT_5218
);
a_14_CY0F : X_BUF
generic map(
LOC => "SLICE_X17Y23",
PATHPULSE => 638 ps
)
port map (
I => Sh78,
O => a_14_CY0F_5217
);
a_14_CYSELF : X_BUF
generic map(
LOC => "SLICE_X17Y23",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(14),
O => a_14_CYSELF_5206
);
a_14_YUSED : X_BUF
generic map(
LOC => "SLICE_X17Y23",
PATHPULSE => 638 ps
)
port map (
I => a_14_XORG_5208,
O => a(15)
);
a_14_XORG : X_XOR2
generic map(
LOC => "SLICE_X17Y23"
)
port map (
I0 => Madd_a_cy_14_Q,
I1 => Madd_a_lut(15),
O => a_14_XORG_5208
);
a_14_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X17Y23",
PATHPULSE => 638 ps
)
port map (
I => a_14_CYMUXFAST_5205,
O => Madd_a_cy_15_Q
);
a_14_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X17Y23",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_13_Q,
O => a_14_FASTCARRY_5203
);
a_14_CYAND : X_AND2
generic map(
LOC => "SLICE_X17Y23"
)
port map (
I0 => a_14_CYSELG_5194,
I1 => a_14_CYSELF_5206,
O => a_14_CYAND_5204
);
a_14_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X17Y23"
)
port map (
IA => a_14_CYMUXG2_5202,
IB => a_14_FASTCARRY_5203,
SEL => a_14_CYAND_5204,
O => a_14_CYMUXFAST_5205
);
a_14_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X17Y23"
)
port map (
IA => a_14_CY0G_5200,
IB => a_14_CYMUXF2_5201,
SEL => a_14_CYSELG_5194,
O => a_14_CYMUXG2_5202
);
a_14_CY0G : X_BUF
generic map(
LOC => "SLICE_X17Y23",
PATHPULSE => 638 ps
)
port map (
I => Sh79,
O => a_14_CY0G_5200
);
a_14_CYSELG : X_BUF
generic map(
LOC => "SLICE_X17Y23",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(15),
O => a_14_CYSELG_5194
);
a_16_XUSED : X_BUF
generic map(
LOC => "SLICE_X17Y24",
PATHPULSE => 638 ps
)
port map (
I => a_16_XORF_5262,
O => a(16)
);
a_16_XORF : X_XOR2
generic map(
LOC => "SLICE_X17Y24"
)
port map (
I0 => a_16_CYINIT_5261,
I1 => Madd_a_lut(16),
O => a_16_XORF_5262
);
a_16_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X17Y24"
)
port map (
IA => a_16_CY0F_5260,
IB => a_16_CYINIT_5261,
SEL => a_16_CYSELF_5249,
O => Madd_a_cy_16_Q
);
a_16_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X17Y24"
)
port map (
IA => a_16_CY0F_5260,
IB => a_16_CY0F_5260,
SEL => a_16_CYSELF_5249,
O => a_16_CYMUXF2_5244
);
a_16_CYINIT : X_BUF
generic map(
LOC => "SLICE_X17Y24",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_15_Q,
O => a_16_CYINIT_5261
);
a_16_CY0F : X_BUF
generic map(
LOC => "SLICE_X17Y24",
PATHPULSE => 638 ps
)
port map (
I => Sh80,
O => a_16_CY0F_5260
);
a_16_CYSELF : X_BUF
generic map(
LOC => "SLICE_X17Y24",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(16),
O => a_16_CYSELF_5249
);
a_16_YUSED : X_BUF
generic map(
LOC => "SLICE_X17Y24",
PATHPULSE => 638 ps
)
port map (
I => a_16_XORG_5251,
O => a(17)
);
a_16_XORG : X_XOR2
generic map(
LOC => "SLICE_X17Y24"
)
port map (
I0 => Madd_a_cy_16_Q,
I1 => Madd_a_lut(17),
O => a_16_XORG_5251
);
a_16_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X17Y24",
PATHPULSE => 638 ps
)
port map (
I => a_16_CYMUXFAST_5248,
O => Madd_a_cy_17_Q
);
a_16_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X17Y24",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_15_Q,
O => a_16_FASTCARRY_5246
);
a_16_CYAND : X_AND2
generic map(
LOC => "SLICE_X17Y24"
)
port map (
I0 => a_16_CYSELG_5237,
I1 => a_16_CYSELF_5249,
O => a_16_CYAND_5247
);
a_16_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X17Y24"
)
port map (
IA => a_16_CYMUXG2_5245,
IB => a_16_FASTCARRY_5246,
SEL => a_16_CYAND_5247,
O => a_16_CYMUXFAST_5248
);
a_16_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X17Y24"
)
port map (
IA => a_16_CY0G_5243,
IB => a_16_CYMUXF2_5244,
SEL => a_16_CYSELG_5237,
O => a_16_CYMUXG2_5245
);
a_16_CY0G : X_BUF
generic map(
LOC => "SLICE_X17Y24",
PATHPULSE => 638 ps
)
port map (
I => Sh81,
O => a_16_CY0G_5243
);
a_16_CYSELG : X_BUF
generic map(
LOC => "SLICE_X17Y24",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(17),
O => a_16_CYSELG_5237
);
Madd_a_lut_16_Q : X_LUT4
generic map(
INIT => X"569A",
LOC => "SLICE_X17Y24"
)
port map (
ADR0 => Mrom_a_rom000016_0,
ADR1 => b_reg(4),
ADR2 => Sh48,
ADR3 => Sh32,
O => Madd_a_lut(16)
);
a_18_XUSED : X_BUF
generic map(
LOC => "SLICE_X17Y25",
PATHPULSE => 638 ps
)
port map (
I => a_18_XORF_5305,
O => a(18)
);
a_18_XORF : X_XOR2
generic map(
LOC => "SLICE_X17Y25"
)
port map (
I0 => a_18_CYINIT_5304,
I1 => Madd_a_lut(18),
O => a_18_XORF_5305
);
a_18_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X17Y25"
)
port map (
IA => a_18_CY0F_5303,
IB => a_18_CYINIT_5304,
SEL => a_18_CYSELF_5292,
O => Madd_a_cy_18_Q
);
a_18_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X17Y25"
)
port map (
IA => a_18_CY0F_5303,
IB => a_18_CY0F_5303,
SEL => a_18_CYSELF_5292,
O => a_18_CYMUXF2_5287
);
a_18_CYINIT : X_BUF
generic map(
LOC => "SLICE_X17Y25",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_17_Q,
O => a_18_CYINIT_5304
);
a_18_CY0F : X_BUF
generic map(
LOC => "SLICE_X17Y25",
PATHPULSE => 638 ps
)
port map (
I => Sh82,
O => a_18_CY0F_5303
);
a_18_CYSELF : X_BUF
generic map(
LOC => "SLICE_X17Y25",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(18),
O => a_18_CYSELF_5292
);
a_18_YUSED : X_BUF
generic map(
LOC => "SLICE_X17Y25",
PATHPULSE => 638 ps
)
port map (
I => a_18_XORG_5294,
O => a(19)
);
a_18_XORG : X_XOR2
generic map(
LOC => "SLICE_X17Y25"
)
port map (
I0 => Madd_a_cy_18_Q,
I1 => Madd_a_lut(19),
O => a_18_XORG_5294
);
a_18_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X17Y25",
PATHPULSE => 638 ps
)
port map (
I => a_18_CYMUXFAST_5291,
O => Madd_a_cy_19_Q
);
a_18_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X17Y25",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_17_Q,
O => a_18_FASTCARRY_5289
);
a_18_CYAND : X_AND2
generic map(
LOC => "SLICE_X17Y25"
)
port map (
I0 => a_18_CYSELG_5280,
I1 => a_18_CYSELF_5292,
O => a_18_CYAND_5290
);
a_18_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X17Y25"
)
port map (
IA => a_18_CYMUXG2_5288,
IB => a_18_FASTCARRY_5289,
SEL => a_18_CYAND_5290,
O => a_18_CYMUXFAST_5291
);
a_18_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X17Y25"
)
port map (
IA => a_18_CY0G_5286,
IB => a_18_CYMUXF2_5287,
SEL => a_18_CYSELG_5280,
O => a_18_CYMUXG2_5288
);
a_18_CY0G : X_BUF
generic map(
LOC => "SLICE_X17Y25",
PATHPULSE => 638 ps
)
port map (
I => Sh83,
O => a_18_CY0G_5286
);
a_18_CYSELG : X_BUF
generic map(
LOC => "SLICE_X17Y25",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(19),
O => a_18_CYSELG_5280
);
a_20_XUSED : X_BUF
generic map(
LOC => "SLICE_X17Y26",
PATHPULSE => 638 ps
)
port map (
I => a_20_XORF_5346,
O => a(20)
);
a_20_XORF : X_XOR2
generic map(
LOC => "SLICE_X17Y26"
)
port map (
I0 => a_20_CYINIT_5345,
I1 => Madd_a_lut(20),
O => a_20_XORF_5346
);
a_20_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X17Y26"
)
port map (
IA => a_20_CY0F_5344,
IB => a_20_CYINIT_5345,
SEL => a_20_CYSELF_5334,
O => Madd_a_cy_20_Q
);
a_20_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X17Y26"
)
port map (
IA => a_20_CY0F_5344,
IB => a_20_CY0F_5344,
SEL => a_20_CYSELF_5334,
O => a_20_CYMUXF2_5329
);
a_20_CYINIT : X_BUF
generic map(
LOC => "SLICE_X17Y26",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_19_Q,
O => a_20_CYINIT_5345
);
a_20_CY0F : X_BUF
generic map(
LOC => "SLICE_X17Y26",
PATHPULSE => 638 ps
)
port map (
I => Sh84_0,
O => a_20_CY0F_5344
);
a_20_CYSELF : X_BUF
generic map(
LOC => "SLICE_X17Y26",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(20),
O => a_20_CYSELF_5334
);
a_20_YUSED : X_BUF
generic map(
LOC => "SLICE_X17Y26",
PATHPULSE => 638 ps
)
port map (
I => a_20_XORG_5336,
O => a(21)
);
a_20_XORG : X_XOR2
generic map(
LOC => "SLICE_X17Y26"
)
port map (
I0 => Madd_a_cy_20_Q,
I1 => Madd_a_lut(21),
O => a_20_XORG_5336
);
a_20_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X17Y26",
PATHPULSE => 638 ps
)
port map (
I => a_20_CYMUXFAST_5333,
O => Madd_a_cy_21_Q
);
a_20_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X17Y26",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_19_Q,
O => a_20_FASTCARRY_5331
);
a_20_CYAND : X_AND2
generic map(
LOC => "SLICE_X17Y26"
)
port map (
I0 => a_20_CYSELG_5322,
I1 => a_20_CYSELF_5334,
O => a_20_CYAND_5332
);
a_20_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X17Y26"
)
port map (
IA => a_20_CYMUXG2_5330,
IB => a_20_FASTCARRY_5331,
SEL => a_20_CYAND_5332,
O => a_20_CYMUXFAST_5333
);
a_20_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X17Y26"
)
port map (
IA => a_20_CY0G_5328,
IB => a_20_CYMUXF2_5329,
SEL => a_20_CYSELG_5322,
O => a_20_CYMUXG2_5330
);
a_20_CY0G : X_BUF
generic map(
LOC => "SLICE_X17Y26",
PATHPULSE => 638 ps
)
port map (
I => Sh85,
O => a_20_CY0G_5328
);
a_20_CYSELG : X_BUF
generic map(
LOC => "SLICE_X17Y26",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(21),
O => a_20_CYSELG_5322
);
Madd_a_lut_23_Q : X_LUT4
generic map(
INIT => X"1ED2",
LOC => "SLICE_X17Y27"
)
port map (
ADR0 => Sh55,
ADR1 => b_reg(4),
ADR2 => Mrom_a_rom000023_0,
ADR3 => Sh39,
O => Madd_a_lut(23)
);
a_22_XUSED : X_BUF
generic map(
LOC => "SLICE_X17Y27",
PATHPULSE => 638 ps
)
port map (
I => a_22_XORF_5389,
O => a(22)
);
a_22_XORF : X_XOR2
generic map(
LOC => "SLICE_X17Y27"
)
port map (
I0 => a_22_CYINIT_5388,
I1 => Madd_a_lut(22),
O => a_22_XORF_5389
);
a_22_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X17Y27"
)
port map (
IA => a_22_CY0F_5387,
IB => a_22_CYINIT_5388,
SEL => a_22_CYSELF_5376,
O => Madd_a_cy_22_Q
);
a_22_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X17Y27"
)
port map (
IA => a_22_CY0F_5387,
IB => a_22_CY0F_5387,
SEL => a_22_CYSELF_5376,
O => a_22_CYMUXF2_5371
);
a_22_CYINIT : X_BUF
generic map(
LOC => "SLICE_X17Y27",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_21_Q,
O => a_22_CYINIT_5388
);
a_22_CY0F : X_BUF
generic map(
LOC => "SLICE_X17Y27",
PATHPULSE => 638 ps
)
port map (
I => Sh86,
O => a_22_CY0F_5387
);
a_22_CYSELF : X_BUF
generic map(
LOC => "SLICE_X17Y27",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(22),
O => a_22_CYSELF_5376
);
a_22_YUSED : X_BUF
generic map(
LOC => "SLICE_X17Y27",
PATHPULSE => 638 ps
)
port map (
I => a_22_XORG_5378,
O => a(23)
);
a_22_XORG : X_XOR2
generic map(
LOC => "SLICE_X17Y27"
)
port map (
I0 => Madd_a_cy_22_Q,
I1 => Madd_a_lut(23),
O => a_22_XORG_5378
);
a_22_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X17Y27",
PATHPULSE => 638 ps
)
port map (
I => a_22_CYMUXFAST_5375,
O => Madd_a_cy_23_Q
);
a_22_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X17Y27",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_21_Q,
O => a_22_FASTCARRY_5373
);
a_22_CYAND : X_AND2
generic map(
LOC => "SLICE_X17Y27"
)
port map (
I0 => a_22_CYSELG_5364,
I1 => a_22_CYSELF_5376,
O => a_22_CYAND_5374
);
a_22_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X17Y27"
)
port map (
IA => a_22_CYMUXG2_5372,
IB => a_22_FASTCARRY_5373,
SEL => a_22_CYAND_5374,
O => a_22_CYMUXFAST_5375
);
a_22_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X17Y27"
)
port map (
IA => a_22_CY0G_5370,
IB => a_22_CYMUXF2_5371,
SEL => a_22_CYSELG_5364,
O => a_22_CYMUXG2_5372
);
a_22_CY0G : X_BUF
generic map(
LOC => "SLICE_X17Y27",
PATHPULSE => 638 ps
)
port map (
I => Sh87,
O => a_22_CY0G_5370
);
a_22_CYSELG : X_BUF
generic map(
LOC => "SLICE_X17Y27",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(23),
O => a_22_CYSELG_5364
);
a_24_XUSED : X_BUF
generic map(
LOC => "SLICE_X17Y28",
PATHPULSE => 638 ps
)
port map (
I => a_24_XORF_5432,
O => a(24)
);
a_24_XORF : X_XOR2
generic map(
LOC => "SLICE_X17Y28"
)
port map (
I0 => a_24_CYINIT_5431,
I1 => Madd_a_lut(24),
O => a_24_XORF_5432
);
a_24_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X17Y28"
)
port map (
IA => a_24_CY0F_5430,
IB => a_24_CYINIT_5431,
SEL => a_24_CYSELF_5419,
O => Madd_a_cy_24_Q
);
a_24_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X17Y28"
)
port map (
IA => a_24_CY0F_5430,
IB => a_24_CY0F_5430,
SEL => a_24_CYSELF_5419,
O => a_24_CYMUXF2_5414
);
a_24_CYINIT : X_BUF
generic map(
LOC => "SLICE_X17Y28",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_23_Q,
O => a_24_CYINIT_5431
);
a_24_CY0F : X_BUF
generic map(
LOC => "SLICE_X17Y28",
PATHPULSE => 638 ps
)
port map (
I => Sh88,
O => a_24_CY0F_5430
);
a_24_CYSELF : X_BUF
generic map(
LOC => "SLICE_X17Y28",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(24),
O => a_24_CYSELF_5419
);
a_24_YUSED : X_BUF
generic map(
LOC => "SLICE_X17Y28",
PATHPULSE => 638 ps
)
port map (
I => a_24_XORG_5421,
O => a(25)
);
a_24_XORG : X_XOR2
generic map(
LOC => "SLICE_X17Y28"
)
port map (
I0 => Madd_a_cy_24_Q,
I1 => Madd_a_lut(25),
O => a_24_XORG_5421
);
a_24_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X17Y28",
PATHPULSE => 638 ps
)
port map (
I => a_24_CYMUXFAST_5418,
O => Madd_a_cy_25_Q
);
a_24_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X17Y28",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_23_Q,
O => a_24_FASTCARRY_5416
);
a_24_CYAND : X_AND2
generic map(
LOC => "SLICE_X17Y28"
)
port map (
I0 => a_24_CYSELG_5407,
I1 => a_24_CYSELF_5419,
O => a_24_CYAND_5417
);
a_24_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X17Y28"
)
port map (
IA => a_24_CYMUXG2_5415,
IB => a_24_FASTCARRY_5416,
SEL => a_24_CYAND_5417,
O => a_24_CYMUXFAST_5418
);
a_24_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X17Y28"
)
port map (
IA => a_24_CY0G_5413,
IB => a_24_CYMUXF2_5414,
SEL => a_24_CYSELG_5407,
O => a_24_CYMUXG2_5415
);
a_24_CY0G : X_BUF
generic map(
LOC => "SLICE_X17Y28",
PATHPULSE => 638 ps
)
port map (
I => Sh89,
O => a_24_CY0G_5413
);
a_24_CYSELG : X_BUF
generic map(
LOC => "SLICE_X17Y28",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(25),
O => a_24_CYSELG_5407
);
a_26_XUSED : X_BUF
generic map(
LOC => "SLICE_X17Y29",
PATHPULSE => 638 ps
)
port map (
I => a_26_XORF_5475,
O => a(26)
);
a_26_XORF : X_XOR2
generic map(
LOC => "SLICE_X17Y29"
)
port map (
I0 => a_26_CYINIT_5474,
I1 => Madd_a_lut(26),
O => a_26_XORF_5475
);
a_26_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X17Y29"
)
port map (
IA => a_26_CY0F_5473,
IB => a_26_CYINIT_5474,
SEL => a_26_CYSELF_5462,
O => Madd_a_cy_26_Q
);
a_26_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X17Y29"
)
port map (
IA => a_26_CY0F_5473,
IB => a_26_CY0F_5473,
SEL => a_26_CYSELF_5462,
O => a_26_CYMUXF2_5457
);
a_26_CYINIT : X_BUF
generic map(
LOC => "SLICE_X17Y29",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_25_Q,
O => a_26_CYINIT_5474
);
a_26_CY0F : X_BUF
generic map(
LOC => "SLICE_X17Y29",
PATHPULSE => 638 ps
)
port map (
I => Sh90,
O => a_26_CY0F_5473
);
a_26_CYSELF : X_BUF
generic map(
LOC => "SLICE_X17Y29",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(26),
O => a_26_CYSELF_5462
);
a_26_YUSED : X_BUF
generic map(
LOC => "SLICE_X17Y29",
PATHPULSE => 638 ps
)
port map (
I => a_26_XORG_5464,
O => a(27)
);
a_26_XORG : X_XOR2
generic map(
LOC => "SLICE_X17Y29"
)
port map (
I0 => Madd_a_cy_26_Q,
I1 => Madd_a_lut(27),
O => a_26_XORG_5464
);
a_26_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X17Y29",
PATHPULSE => 638 ps
)
port map (
I => a_26_CYMUXFAST_5461,
O => Madd_a_cy_27_Q
);
a_26_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X17Y29",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_25_Q,
O => a_26_FASTCARRY_5459
);
a_26_CYAND : X_AND2
generic map(
LOC => "SLICE_X17Y29"
)
port map (
I0 => a_26_CYSELG_5450,
I1 => a_26_CYSELF_5462,
O => a_26_CYAND_5460
);
a_26_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X17Y29"
)
port map (
IA => a_26_CYMUXG2_5458,
IB => a_26_FASTCARRY_5459,
SEL => a_26_CYAND_5460,
O => a_26_CYMUXFAST_5461
);
a_26_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X17Y29"
)
port map (
IA => a_26_CY0G_5456,
IB => a_26_CYMUXF2_5457,
SEL => a_26_CYSELG_5450,
O => a_26_CYMUXG2_5458
);
a_26_CY0G : X_BUF
generic map(
LOC => "SLICE_X17Y29",
PATHPULSE => 638 ps
)
port map (
I => Sh91,
O => a_26_CY0G_5456
);
a_26_CYSELG : X_BUF
generic map(
LOC => "SLICE_X17Y29",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(27),
O => a_26_CYSELG_5450
);
Madd_a_lut_26_Q : X_LUT4
generic map(
INIT => X"5A66",
LOC => "SLICE_X17Y29"
)
port map (
ADR0 => Mrom_a_rom000026_0,
ADR1 => Sh58,
ADR2 => Sh42,
ADR3 => b_reg(4),
O => Madd_a_lut(26)
);
a_28_XUSED : X_BUF
generic map(
LOC => "SLICE_X17Y30",
PATHPULSE => 638 ps
)
port map (
I => a_28_XORF_5518,
O => a(28)
);
a_28_XORF : X_XOR2
generic map(
LOC => "SLICE_X17Y30"
)
port map (
I0 => a_28_CYINIT_5517,
I1 => Madd_a_lut(28),
O => a_28_XORF_5518
);
a_28_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X17Y30"
)
port map (
IA => a_28_CY0F_5516,
IB => a_28_CYINIT_5517,
SEL => a_28_CYSELF_5505,
O => Madd_a_cy_28_Q
);
a_28_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X17Y30"
)
port map (
IA => a_28_CY0F_5516,
IB => a_28_CY0F_5516,
SEL => a_28_CYSELF_5505,
O => a_28_CYMUXF2_5500
);
a_28_CYINIT : X_BUF
generic map(
LOC => "SLICE_X17Y30",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_27_Q,
O => a_28_CYINIT_5517
);
a_28_CY0F : X_BUF
generic map(
LOC => "SLICE_X17Y30",
PATHPULSE => 638 ps
)
port map (
I => Sh92,
O => a_28_CY0F_5516
);
a_28_CYSELF : X_BUF
generic map(
LOC => "SLICE_X17Y30",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(28),
O => a_28_CYSELF_5505
);
a_28_YUSED : X_BUF
generic map(
LOC => "SLICE_X17Y30",
PATHPULSE => 638 ps
)
port map (
I => a_28_XORG_5507,
O => a(29)
);
a_28_XORG : X_XOR2
generic map(
LOC => "SLICE_X17Y30"
)
port map (
I0 => Madd_a_cy_28_Q,
I1 => Madd_a_lut(29),
O => a_28_XORG_5507
);
a_28_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X17Y30",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_cy_27_Q,
O => a_28_FASTCARRY_5502
);
a_28_CYAND : X_AND2
generic map(
LOC => "SLICE_X17Y30"
)
port map (
I0 => a_28_CYSELG_5493,
I1 => a_28_CYSELF_5505,
O => a_28_CYAND_5503
);
a_28_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X17Y30"
)
port map (
IA => a_28_CYMUXG2_5501,
IB => a_28_FASTCARRY_5502,
SEL => a_28_CYAND_5503,
O => a_28_CYMUXFAST_5504
);
a_28_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X17Y30"
)
port map (
IA => a_28_CY0G_5499,
IB => a_28_CYMUXF2_5500,
SEL => a_28_CYSELG_5493,
O => a_28_CYMUXG2_5501
);
a_28_CY0G : X_BUF
generic map(
LOC => "SLICE_X17Y30",
PATHPULSE => 638 ps
)
port map (
I => Sh93,
O => a_28_CY0G_5499
);
a_28_CYSELG : X_BUF
generic map(
LOC => "SLICE_X17Y30",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(29),
O => a_28_CYSELG_5493
);
a_30_XUSED : X_BUF
generic map(
LOC => "SLICE_X17Y31",
PATHPULSE => 638 ps
)
port map (
I => a_30_XORF_5551,
O => a(30)
);
a_30_XORF : X_XOR2
generic map(
LOC => "SLICE_X17Y31"
)
port map (
I0 => a_30_CYINIT_5550,
I1 => Madd_a_lut(30),
O => a_30_XORF_5551
);
a_30_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X17Y31"
)
port map (
IA => a_30_CY0F_5549,
IB => a_30_CYINIT_5550,
SEL => a_30_CYSELF_5543,
O => Madd_a_cy_30_Q
);
a_30_CYINIT : X_BUF
generic map(
LOC => "SLICE_X17Y31",
PATHPULSE => 638 ps
)
port map (
I => a_28_CYMUXFAST_5504,
O => a_30_CYINIT_5550
);
a_30_CY0F : X_BUF
generic map(
LOC => "SLICE_X17Y31",
PATHPULSE => 638 ps
)
port map (
I => Sh94,
O => a_30_CY0F_5549
);
a_30_CYSELF : X_BUF
generic map(
LOC => "SLICE_X17Y31",
PATHPULSE => 638 ps
)
port map (
I => Madd_a_lut(30),
O => a_30_CYSELF_5543
);
a_30_YUSED : X_BUF
generic map(
LOC => "SLICE_X17Y31",
PATHPULSE => 638 ps
)
port map (
I => a_30_XORG_5539,
O => a(31)
);
a_30_XORG : X_XOR2
generic map(
LOC => "SLICE_X17Y31"
)
port map (
I0 => Madd_a_cy_30_Q,
I1 => Madd_a_lut(31),
O => a_30_XORG_5539
);
Madd_b_lut_0_Q : X_LUT4
generic map(
INIT => X"6666",
LOC => "SLICE_X21Y12"
)
port map (
ADR0 => Mrom_b_rom0000_0,
ADR1 => Sh160,
ADR2 => VCC,
ADR3 => VCC,
O => Madd_b_lut(0)
);
b_0_XORF : X_XOR2
generic map(
LOC => "SLICE_X21Y12"
)
port map (
I0 => b_0_CYINIT_5588,
I1 => Madd_b_lut(0),
O => b_0_XORF_5589
);
b_0_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X21Y12"
)
port map (
IA => b_0_CY0F_5587,
IB => b_0_CYINIT_5588,
SEL => b_0_CYSELF_5579,
O => Madd_b_cy_0_Q
);
b_0_CYINIT : X_BUF
generic map(
LOC => "SLICE_X21Y12",
PATHPULSE => 638 ps
)
port map (
I => b_0_BXINV_5577,
O => b_0_CYINIT_5588
);
b_0_CY0F : X_BUF
generic map(
LOC => "SLICE_X21Y12",
PATHPULSE => 638 ps
)
port map (
I => Sh160,
O => b_0_CY0F_5587
);
b_0_CYSELF : X_BUF
generic map(
LOC => "SLICE_X21Y12",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(0),
O => b_0_CYSELF_5579
);
b_0_BXINV : X_BUF
generic map(
LOC => "SLICE_X21Y12",
PATHPULSE => 638 ps
)
port map (
I => '0',
O => b_0_BXINV_5577
);
b_0_YUSED : X_BUF
generic map(
LOC => "SLICE_X21Y12",
PATHPULSE => 638 ps
)
port map (
I => b_0_XORG_5575,
O => b_1_Q
);
b_0_XORG : X_XOR2
generic map(
LOC => "SLICE_X21Y12"
)
port map (
I0 => Madd_b_cy_0_Q,
I1 => Madd_b_lut(1),
O => b_0_XORG_5575
);
b_0_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X21Y12",
PATHPULSE => 638 ps
)
port map (
I => b_0_CYMUXG_5574,
O => Madd_b_cy_1_Q
);
b_0_CYMUXG : X_MUX2
generic map(
LOC => "SLICE_X21Y12"
)
port map (
IA => b_0_CY0G_5572,
IB => Madd_b_cy_0_Q,
SEL => b_0_CYSELG_5566,
O => b_0_CYMUXG_5574
);
b_0_CY0G : X_BUF
generic map(
LOC => "SLICE_X21Y12",
PATHPULSE => 638 ps
)
port map (
I => Sh161,
O => b_0_CY0G_5572
);
b_0_CYSELG : X_BUF
generic map(
LOC => "SLICE_X21Y12",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(1),
O => b_0_CYSELG_5566
);
b_2_XUSED : X_BUF
generic map(
LOC => "SLICE_X21Y13",
PATHPULSE => 638 ps
)
port map (
I => b_2_XORF_5628,
O => b_2_Q
);
b_2_XORF : X_XOR2
generic map(
LOC => "SLICE_X21Y13"
)
port map (
I0 => b_2_CYINIT_5627,
I1 => Madd_b_lut(2),
O => b_2_XORF_5628
);
b_2_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X21Y13"
)
port map (
IA => b_2_CY0F_5626,
IB => b_2_CYINIT_5627,
SEL => b_2_CYSELF_5616,
O => Madd_b_cy_2_Q
);
b_2_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X21Y13"
)
port map (
IA => b_2_CY0F_5626,
IB => b_2_CY0F_5626,
SEL => b_2_CYSELF_5616,
O => b_2_CYMUXF2_5611
);
b_2_CYINIT : X_BUF
generic map(
LOC => "SLICE_X21Y13",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_1_Q,
O => b_2_CYINIT_5627
);
b_2_CY0F : X_BUF
generic map(
LOC => "SLICE_X21Y13",
PATHPULSE => 638 ps
)
port map (
I => Sh162,
O => b_2_CY0F_5626
);
b_2_CYSELF : X_BUF
generic map(
LOC => "SLICE_X21Y13",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(2),
O => b_2_CYSELF_5616
);
b_2_YUSED : X_BUF
generic map(
LOC => "SLICE_X21Y13",
PATHPULSE => 638 ps
)
port map (
I => b_2_XORG_5618,
O => b_3_Q
);
b_2_XORG : X_XOR2
generic map(
LOC => "SLICE_X21Y13"
)
port map (
I0 => Madd_b_cy_2_Q,
I1 => Madd_b_lut(3),
O => b_2_XORG_5618
);
b_2_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X21Y13",
PATHPULSE => 638 ps
)
port map (
I => b_2_CYMUXFAST_5615,
O => Madd_b_cy_3_Q
);
b_2_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X21Y13",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_1_Q,
O => b_2_FASTCARRY_5613
);
b_2_CYAND : X_AND2
generic map(
LOC => "SLICE_X21Y13"
)
port map (
I0 => b_2_CYSELG_5604,
I1 => b_2_CYSELF_5616,
O => b_2_CYAND_5614
);
b_2_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X21Y13"
)
port map (
IA => b_2_CYMUXG2_5612,
IB => b_2_FASTCARRY_5613,
SEL => b_2_CYAND_5614,
O => b_2_CYMUXFAST_5615
);
b_2_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X21Y13"
)
port map (
IA => b_2_CY0G_5610,
IB => b_2_CYMUXF2_5611,
SEL => b_2_CYSELG_5604,
O => b_2_CYMUXG2_5612
);
b_2_CY0G : X_BUF
generic map(
LOC => "SLICE_X21Y13",
PATHPULSE => 638 ps
)
port map (
I => Sh163,
O => b_2_CY0G_5610
);
b_2_CYSELG : X_BUF
generic map(
LOC => "SLICE_X21Y13",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(3),
O => b_2_CYSELG_5604
);
Madd_b_lut_5_Q : X_LUT4
generic map(
INIT => X"396C",
LOC => "SLICE_X21Y14"
)
port map (
ADR0 => a(4),
ADR1 => Mrom_b_rom00005_0,
ADR2 => Sh149,
ADR3 => Sh133,
O => Madd_b_lut(5)
);
b_4_XUSED : X_BUF
generic map(
LOC => "SLICE_X21Y14",
PATHPULSE => 638 ps
)
port map (
I => b_4_XORF_5669,
O => b_4_Q
);
b_4_XORF : X_XOR2
generic map(
LOC => "SLICE_X21Y14"
)
port map (
I0 => b_4_CYINIT_5668,
I1 => Madd_b_lut(4),
O => b_4_XORF_5669
);
b_4_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X21Y14"
)
port map (
IA => b_4_CY0F_5667,
IB => b_4_CYINIT_5668,
SEL => b_4_CYSELF_5656,
O => Madd_b_cy_4_Q
);
b_4_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X21Y14"
)
port map (
IA => b_4_CY0F_5667,
IB => b_4_CY0F_5667,
SEL => b_4_CYSELF_5656,
O => b_4_CYMUXF2_5651
);
b_4_CYINIT : X_BUF
generic map(
LOC => "SLICE_X21Y14",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_3_Q,
O => b_4_CYINIT_5668
);
b_4_CY0F : X_BUF
generic map(
LOC => "SLICE_X21Y14",
PATHPULSE => 638 ps
)
port map (
I => Sh164,
O => b_4_CY0F_5667
);
b_4_CYSELF : X_BUF
generic map(
LOC => "SLICE_X21Y14",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(4),
O => b_4_CYSELF_5656
);
b_4_YUSED : X_BUF
generic map(
LOC => "SLICE_X21Y14",
PATHPULSE => 638 ps
)
port map (
I => b_4_XORG_5658,
O => b_5_Q
);
b_4_XORG : X_XOR2
generic map(
LOC => "SLICE_X21Y14"
)
port map (
I0 => Madd_b_cy_4_Q,
I1 => Madd_b_lut(5),
O => b_4_XORG_5658
);
b_4_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X21Y14",
PATHPULSE => 638 ps
)
port map (
I => b_4_CYMUXFAST_5655,
O => Madd_b_cy_5_Q
);
b_4_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X21Y14",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_3_Q,
O => b_4_FASTCARRY_5653
);
b_4_CYAND : X_AND2
generic map(
LOC => "SLICE_X21Y14"
)
port map (
I0 => b_4_CYSELG_5644,
I1 => b_4_CYSELF_5656,
O => b_4_CYAND_5654
);
b_4_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X21Y14"
)
port map (
IA => b_4_CYMUXG2_5652,
IB => b_4_FASTCARRY_5653,
SEL => b_4_CYAND_5654,
O => b_4_CYMUXFAST_5655
);
b_4_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X21Y14"
)
port map (
IA => b_4_CY0G_5650,
IB => b_4_CYMUXF2_5651,
SEL => b_4_CYSELG_5644,
O => b_4_CYMUXG2_5652
);
b_4_CY0G : X_BUF
generic map(
LOC => "SLICE_X21Y14",
PATHPULSE => 638 ps
)
port map (
I => Sh165,
O => b_4_CY0G_5650
);
b_4_CYSELG : X_BUF
generic map(
LOC => "SLICE_X21Y14",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(5),
O => b_4_CYSELG_5644
);
b_6_XUSED : X_BUF
generic map(
LOC => "SLICE_X21Y15",
PATHPULSE => 638 ps
)
port map (
I => b_6_XORF_5712,
O => b_6_Q
);
b_6_XORF : X_XOR2
generic map(
LOC => "SLICE_X21Y15"
)
port map (
I0 => b_6_CYINIT_5711,
I1 => Madd_b_lut(6),
O => b_6_XORF_5712
);
b_6_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X21Y15"
)
port map (
IA => b_6_CY0F_5710,
IB => b_6_CYINIT_5711,
SEL => b_6_CYSELF_5699,
O => Madd_b_cy_6_Q
);
b_6_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X21Y15"
)
port map (
IA => b_6_CY0F_5710,
IB => b_6_CY0F_5710,
SEL => b_6_CYSELF_5699,
O => b_6_CYMUXF2_5694
);
b_6_CYINIT : X_BUF
generic map(
LOC => "SLICE_X21Y15",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_5_Q,
O => b_6_CYINIT_5711
);
b_6_CY0F : X_BUF
generic map(
LOC => "SLICE_X21Y15",
PATHPULSE => 638 ps
)
port map (
I => Sh166,
O => b_6_CY0F_5710
);
b_6_CYSELF : X_BUF
generic map(
LOC => "SLICE_X21Y15",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(6),
O => b_6_CYSELF_5699
);
b_6_YUSED : X_BUF
generic map(
LOC => "SLICE_X21Y15",
PATHPULSE => 638 ps
)
port map (
I => b_6_XORG_5701,
O => b_7_Q
);
b_6_XORG : X_XOR2
generic map(
LOC => "SLICE_X21Y15"
)
port map (
I0 => Madd_b_cy_6_Q,
I1 => Madd_b_lut(7),
O => b_6_XORG_5701
);
b_6_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X21Y15",
PATHPULSE => 638 ps
)
port map (
I => b_6_CYMUXFAST_5698,
O => Madd_b_cy_7_Q
);
b_6_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X21Y15",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_5_Q,
O => b_6_FASTCARRY_5696
);
b_6_CYAND : X_AND2
generic map(
LOC => "SLICE_X21Y15"
)
port map (
I0 => b_6_CYSELG_5687,
I1 => b_6_CYSELF_5699,
O => b_6_CYAND_5697
);
b_6_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X21Y15"
)
port map (
IA => b_6_CYMUXG2_5695,
IB => b_6_FASTCARRY_5696,
SEL => b_6_CYAND_5697,
O => b_6_CYMUXFAST_5698
);
b_6_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X21Y15"
)
port map (
IA => b_6_CY0G_5693,
IB => b_6_CYMUXF2_5694,
SEL => b_6_CYSELG_5687,
O => b_6_CYMUXG2_5695
);
b_6_CY0G : X_BUF
generic map(
LOC => "SLICE_X21Y15",
PATHPULSE => 638 ps
)
port map (
I => Sh167,
O => b_6_CY0G_5693
);
b_6_CYSELG : X_BUF
generic map(
LOC => "SLICE_X21Y15",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(7),
O => b_6_CYSELG_5687
);
b_8_XORF : X_XOR2
generic map(
LOC => "SLICE_X21Y16"
)
port map (
I0 => b_8_CYINIT_5754,
I1 => Madd_b_lut(8),
O => b_8_XORF_5755
);
b_8_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X21Y16"
)
port map (
IA => b_8_CY0F_5753,
IB => b_8_CYINIT_5754,
SEL => b_8_CYSELF_5742,
O => Madd_b_cy_8_Q
);
b_8_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X21Y16"
)
port map (
IA => b_8_CY0F_5753,
IB => b_8_CY0F_5753,
SEL => b_8_CYSELF_5742,
O => b_8_CYMUXF2_5737
);
b_8_CYINIT : X_BUF
generic map(
LOC => "SLICE_X21Y16",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_7_Q,
O => b_8_CYINIT_5754
);
b_8_CY0F : X_BUF
generic map(
LOC => "SLICE_X21Y16",
PATHPULSE => 638 ps
)
port map (
I => Sh168,
O => b_8_CY0F_5753
);
b_8_CYSELF : X_BUF
generic map(
LOC => "SLICE_X21Y16",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(8),
O => b_8_CYSELF_5742
);
b_8_XORG : X_XOR2
generic map(
LOC => "SLICE_X21Y16"
)
port map (
I0 => Madd_b_cy_8_Q,
I1 => Madd_b_lut(9),
O => b_8_XORG_5744
);
b_8_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X21Y16",
PATHPULSE => 638 ps
)
port map (
I => b_8_CYMUXFAST_5741,
O => Madd_b_cy_9_Q
);
b_8_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X21Y16",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_7_Q,
O => b_8_FASTCARRY_5739
);
b_8_CYAND : X_AND2
generic map(
LOC => "SLICE_X21Y16"
)
port map (
I0 => b_8_CYSELG_5730,
I1 => b_8_CYSELF_5742,
O => b_8_CYAND_5740
);
b_8_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X21Y16"
)
port map (
IA => b_8_CYMUXG2_5738,
IB => b_8_FASTCARRY_5739,
SEL => b_8_CYAND_5740,
O => b_8_CYMUXFAST_5741
);
b_8_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X21Y16"
)
port map (
IA => b_8_CY0G_5736,
IB => b_8_CYMUXF2_5737,
SEL => b_8_CYSELG_5730,
O => b_8_CYMUXG2_5738
);
b_8_CY0G : X_BUF
generic map(
LOC => "SLICE_X21Y16",
PATHPULSE => 638 ps
)
port map (
I => Sh169,
O => b_8_CY0G_5736
);
b_8_CYSELG : X_BUF
generic map(
LOC => "SLICE_X21Y16",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(9),
O => b_8_CYSELG_5730
);
b_10_XORF : X_XOR2
generic map(
LOC => "SLICE_X21Y17"
)
port map (
I0 => b_10_CYINIT_5797,
I1 => Madd_b_lut(10),
O => b_10_XORF_5798
);
b_10_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X21Y17"
)
port map (
IA => b_10_CY0F_5796,
IB => b_10_CYINIT_5797,
SEL => b_10_CYSELF_5785,
O => Madd_b_cy_10_Q
);
b_10_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X21Y17"
)
port map (
IA => b_10_CY0F_5796,
IB => b_10_CY0F_5796,
SEL => b_10_CYSELF_5785,
O => b_10_CYMUXF2_5780
);
b_10_CYINIT : X_BUF
generic map(
LOC => "SLICE_X21Y17",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_9_Q,
O => b_10_CYINIT_5797
);
b_10_CY0F : X_BUF
generic map(
LOC => "SLICE_X21Y17",
PATHPULSE => 638 ps
)
port map (
I => Sh170,
O => b_10_CY0F_5796
);
b_10_CYSELF : X_BUF
generic map(
LOC => "SLICE_X21Y17",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(10),
O => b_10_CYSELF_5785
);
b_10_YUSED : X_BUF
generic map(
LOC => "SLICE_X21Y17",
PATHPULSE => 638 ps
)
port map (
I => b_10_XORG_5787,
O => b_11_Q
);
b_10_XORG : X_XOR2
generic map(
LOC => "SLICE_X21Y17"
)
port map (
I0 => Madd_b_cy_10_Q,
I1 => Madd_b_lut(11),
O => b_10_XORG_5787
);
b_10_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X21Y17",
PATHPULSE => 638 ps
)
port map (
I => b_10_CYMUXFAST_5784,
O => Madd_b_cy_11_Q
);
b_10_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X21Y17",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_9_Q,
O => b_10_FASTCARRY_5782
);
b_10_CYAND : X_AND2
generic map(
LOC => "SLICE_X21Y17"
)
port map (
I0 => b_10_CYSELG_5773,
I1 => b_10_CYSELF_5785,
O => b_10_CYAND_5783
);
b_10_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X21Y17"
)
port map (
IA => b_10_CYMUXG2_5781,
IB => b_10_FASTCARRY_5782,
SEL => b_10_CYAND_5783,
O => b_10_CYMUXFAST_5784
);
b_10_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X21Y17"
)
port map (
IA => b_10_CY0G_5779,
IB => b_10_CYMUXF2_5780,
SEL => b_10_CYSELG_5773,
O => b_10_CYMUXG2_5781
);
b_10_CY0G : X_BUF
generic map(
LOC => "SLICE_X21Y17",
PATHPULSE => 638 ps
)
port map (
I => Sh171,
O => b_10_CY0G_5779
);
b_10_CYSELG : X_BUF
generic map(
LOC => "SLICE_X21Y17",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(11),
O => b_10_CYSELG_5773
);
b_12_XUSED : X_BUF
generic map(
LOC => "SLICE_X21Y18",
PATHPULSE => 638 ps
)
port map (
I => b_12_XORF_5841,
O => b_12_Q
);
b_12_XORF : X_XOR2
generic map(
LOC => "SLICE_X21Y18"
)
port map (
I0 => b_12_CYINIT_5840,
I1 => Madd_b_lut(12),
O => b_12_XORF_5841
);
b_12_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X21Y18"
)
port map (
IA => b_12_CY0F_5839,
IB => b_12_CYINIT_5840,
SEL => b_12_CYSELF_5828,
O => Madd_b_cy_12_Q
);
b_12_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X21Y18"
)
port map (
IA => b_12_CY0F_5839,
IB => b_12_CY0F_5839,
SEL => b_12_CYSELF_5828,
O => b_12_CYMUXF2_5823
);
b_12_CYINIT : X_BUF
generic map(
LOC => "SLICE_X21Y18",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_11_Q,
O => b_12_CYINIT_5840
);
b_12_CY0F : X_BUF
generic map(
LOC => "SLICE_X21Y18",
PATHPULSE => 638 ps
)
port map (
I => Sh172,
O => b_12_CY0F_5839
);
b_12_CYSELF : X_BUF
generic map(
LOC => "SLICE_X21Y18",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(12),
O => b_12_CYSELF_5828
);
b_12_YUSED : X_BUF
generic map(
LOC => "SLICE_X21Y18",
PATHPULSE => 638 ps
)
port map (
I => b_12_XORG_5830,
O => b_13_Q
);
b_12_XORG : X_XOR2
generic map(
LOC => "SLICE_X21Y18"
)
port map (
I0 => Madd_b_cy_12_Q,
I1 => Madd_b_lut(13),
O => b_12_XORG_5830
);
b_12_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X21Y18",
PATHPULSE => 638 ps
)
port map (
I => b_12_CYMUXFAST_5827,
O => Madd_b_cy_13_Q
);
b_12_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X21Y18",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_11_Q,
O => b_12_FASTCARRY_5825
);
b_12_CYAND : X_AND2
generic map(
LOC => "SLICE_X21Y18"
)
port map (
I0 => b_12_CYSELG_5816,
I1 => b_12_CYSELF_5828,
O => b_12_CYAND_5826
);
b_12_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X21Y18"
)
port map (
IA => b_12_CYMUXG2_5824,
IB => b_12_FASTCARRY_5825,
SEL => b_12_CYAND_5826,
O => b_12_CYMUXFAST_5827
);
b_12_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X21Y18"
)
port map (
IA => b_12_CY0G_5822,
IB => b_12_CYMUXF2_5823,
SEL => b_12_CYSELG_5816,
O => b_12_CYMUXG2_5824
);
b_12_CY0G : X_BUF
generic map(
LOC => "SLICE_X21Y18",
PATHPULSE => 638 ps
)
port map (
I => Sh173,
O => b_12_CY0G_5822
);
b_12_CYSELG : X_BUF
generic map(
LOC => "SLICE_X21Y18",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(13),
O => b_12_CYSELG_5816
);
b_14_XUSED : X_BUF
generic map(
LOC => "SLICE_X21Y19",
PATHPULSE => 638 ps
)
port map (
I => b_14_XORF_5882,
O => b_14_Q
);
b_14_XORF : X_XOR2
generic map(
LOC => "SLICE_X21Y19"
)
port map (
I0 => b_14_CYINIT_5881,
I1 => Madd_b_lut(14),
O => b_14_XORF_5882
);
b_14_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X21Y19"
)
port map (
IA => b_14_CY0F_5880,
IB => b_14_CYINIT_5881,
SEL => b_14_CYSELF_5869,
O => Madd_b_cy_14_Q
);
b_14_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X21Y19"
)
port map (
IA => b_14_CY0F_5880,
IB => b_14_CY0F_5880,
SEL => b_14_CYSELF_5869,
O => b_14_CYMUXF2_5864
);
b_14_CYINIT : X_BUF
generic map(
LOC => "SLICE_X21Y19",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_13_Q,
O => b_14_CYINIT_5881
);
b_14_CY0F : X_BUF
generic map(
LOC => "SLICE_X21Y19",
PATHPULSE => 638 ps
)
port map (
I => Sh174,
O => b_14_CY0F_5880
);
b_14_CYSELF : X_BUF
generic map(
LOC => "SLICE_X21Y19",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(14),
O => b_14_CYSELF_5869
);
b_14_YUSED : X_BUF
generic map(
LOC => "SLICE_X21Y19",
PATHPULSE => 638 ps
)
port map (
I => b_14_XORG_5871,
O => b_15_Q
);
b_14_XORG : X_XOR2
generic map(
LOC => "SLICE_X21Y19"
)
port map (
I0 => Madd_b_cy_14_Q,
I1 => Madd_b_lut(15),
O => b_14_XORG_5871
);
b_14_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X21Y19",
PATHPULSE => 638 ps
)
port map (
I => b_14_CYMUXFAST_5868,
O => Madd_b_cy_15_Q
);
b_14_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X21Y19",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_13_Q,
O => b_14_FASTCARRY_5866
);
b_14_CYAND : X_AND2
generic map(
LOC => "SLICE_X21Y19"
)
port map (
I0 => b_14_CYSELG_5857,
I1 => b_14_CYSELF_5869,
O => b_14_CYAND_5867
);
b_14_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X21Y19"
)
port map (
IA => b_14_CYMUXG2_5865,
IB => b_14_FASTCARRY_5866,
SEL => b_14_CYAND_5867,
O => b_14_CYMUXFAST_5868
);
b_14_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X21Y19"
)
port map (
IA => b_14_CY0G_5863,
IB => b_14_CYMUXF2_5864,
SEL => b_14_CYSELG_5857,
O => b_14_CYMUXG2_5865
);
b_14_CY0G : X_BUF
generic map(
LOC => "SLICE_X21Y19",
PATHPULSE => 638 ps
)
port map (
I => Sh175,
O => b_14_CY0G_5863
);
b_14_CYSELG : X_BUF
generic map(
LOC => "SLICE_X21Y19",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(15),
O => b_14_CYSELG_5857
);
b_16_XUSED : X_BUF
generic map(
LOC => "SLICE_X21Y20",
PATHPULSE => 638 ps
)
port map (
I => b_16_XORF_5925,
O => b_16_Q
);
b_16_XORF : X_XOR2
generic map(
LOC => "SLICE_X21Y20"
)
port map (
I0 => b_16_CYINIT_5924,
I1 => Madd_b_lut(16),
O => b_16_XORF_5925
);
b_16_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X21Y20"
)
port map (
IA => b_16_CY0F_5923,
IB => b_16_CYINIT_5924,
SEL => b_16_CYSELF_5912,
O => Madd_b_cy_16_Q
);
b_16_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X21Y20"
)
port map (
IA => b_16_CY0F_5923,
IB => b_16_CY0F_5923,
SEL => b_16_CYSELF_5912,
O => b_16_CYMUXF2_5907
);
b_16_CYINIT : X_BUF
generic map(
LOC => "SLICE_X21Y20",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_15_Q,
O => b_16_CYINIT_5924
);
b_16_CY0F : X_BUF
generic map(
LOC => "SLICE_X21Y20",
PATHPULSE => 638 ps
)
port map (
I => Sh176,
O => b_16_CY0F_5923
);
b_16_CYSELF : X_BUF
generic map(
LOC => "SLICE_X21Y20",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(16),
O => b_16_CYSELF_5912
);
b_16_YUSED : X_BUF
generic map(
LOC => "SLICE_X21Y20",
PATHPULSE => 638 ps
)
port map (
I => b_16_XORG_5914,
O => b_17_Q
);
b_16_XORG : X_XOR2
generic map(
LOC => "SLICE_X21Y20"
)
port map (
I0 => Madd_b_cy_16_Q,
I1 => Madd_b_lut(17),
O => b_16_XORG_5914
);
b_16_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X21Y20",
PATHPULSE => 638 ps
)
port map (
I => b_16_CYMUXFAST_5911,
O => Madd_b_cy_17_Q
);
b_16_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X21Y20",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_15_Q,
O => b_16_FASTCARRY_5909
);
b_16_CYAND : X_AND2
generic map(
LOC => "SLICE_X21Y20"
)
port map (
I0 => b_16_CYSELG_5900,
I1 => b_16_CYSELF_5912,
O => b_16_CYAND_5910
);
b_16_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X21Y20"
)
port map (
IA => b_16_CYMUXG2_5908,
IB => b_16_FASTCARRY_5909,
SEL => b_16_CYAND_5910,
O => b_16_CYMUXFAST_5911
);
b_16_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X21Y20"
)
port map (
IA => b_16_CY0G_5906,
IB => b_16_CYMUXF2_5907,
SEL => b_16_CYSELG_5900,
O => b_16_CYMUXG2_5908
);
b_16_CY0G : X_BUF
generic map(
LOC => "SLICE_X21Y20",
PATHPULSE => 638 ps
)
port map (
I => Sh177,
O => b_16_CY0G_5906
);
b_16_CYSELG : X_BUF
generic map(
LOC => "SLICE_X21Y20",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(17),
O => b_16_CYSELG_5900
);
b_18_XUSED : X_BUF
generic map(
LOC => "SLICE_X21Y21",
PATHPULSE => 638 ps
)
port map (
I => b_18_XORF_5966,
O => b_18_Q
);
b_18_XORF : X_XOR2
generic map(
LOC => "SLICE_X21Y21"
)
port map (
I0 => b_18_CYINIT_5965,
I1 => Madd_b_lut(18),
O => b_18_XORF_5966
);
b_18_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X21Y21"
)
port map (
IA => b_18_CY0F_5964,
IB => b_18_CYINIT_5965,
SEL => b_18_CYSELF_5954,
O => Madd_b_cy_18_Q
);
b_18_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X21Y21"
)
port map (
IA => b_18_CY0F_5964,
IB => b_18_CY0F_5964,
SEL => b_18_CYSELF_5954,
O => b_18_CYMUXF2_5949
);
b_18_CYINIT : X_BUF
generic map(
LOC => "SLICE_X21Y21",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_17_Q,
O => b_18_CYINIT_5965
);
b_18_CY0F : X_BUF
generic map(
LOC => "SLICE_X21Y21",
PATHPULSE => 638 ps
)
port map (
I => Sh178,
O => b_18_CY0F_5964
);
b_18_CYSELF : X_BUF
generic map(
LOC => "SLICE_X21Y21",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(18),
O => b_18_CYSELF_5954
);
b_18_YUSED : X_BUF
generic map(
LOC => "SLICE_X21Y21",
PATHPULSE => 638 ps
)
port map (
I => b_18_XORG_5956,
O => b_19_Q
);
b_18_XORG : X_XOR2
generic map(
LOC => "SLICE_X21Y21"
)
port map (
I0 => Madd_b_cy_18_Q,
I1 => Madd_b_lut(19),
O => b_18_XORG_5956
);
b_18_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X21Y21",
PATHPULSE => 638 ps
)
port map (
I => b_18_CYMUXFAST_5953,
O => Madd_b_cy_19_Q
);
b_18_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X21Y21",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_17_Q,
O => b_18_FASTCARRY_5951
);
b_18_CYAND : X_AND2
generic map(
LOC => "SLICE_X21Y21"
)
port map (
I0 => b_18_CYSELG_5942,
I1 => b_18_CYSELF_5954,
O => b_18_CYAND_5952
);
b_18_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X21Y21"
)
port map (
IA => b_18_CYMUXG2_5950,
IB => b_18_FASTCARRY_5951,
SEL => b_18_CYAND_5952,
O => b_18_CYMUXFAST_5953
);
b_18_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X21Y21"
)
port map (
IA => b_18_CY0G_5948,
IB => b_18_CYMUXF2_5949,
SEL => b_18_CYSELG_5942,
O => b_18_CYMUXG2_5950
);
b_18_CY0G : X_BUF
generic map(
LOC => "SLICE_X21Y21",
PATHPULSE => 638 ps
)
port map (
I => Sh179,
O => b_18_CY0G_5948
);
b_18_CYSELG : X_BUF
generic map(
LOC => "SLICE_X21Y21",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(19),
O => b_18_CYSELG_5942
);
b_20_XUSED : X_BUF
generic map(
LOC => "SLICE_X21Y22",
PATHPULSE => 638 ps
)
port map (
I => b_20_XORF_6009,
O => b_20_Q
);
b_20_XORF : X_XOR2
generic map(
LOC => "SLICE_X21Y22"
)
port map (
I0 => b_20_CYINIT_6008,
I1 => Madd_b_lut(20),
O => b_20_XORF_6009
);
b_20_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X21Y22"
)
port map (
IA => b_20_CY0F_6007,
IB => b_20_CYINIT_6008,
SEL => b_20_CYSELF_5996,
O => Madd_b_cy_20_Q
);
b_20_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X21Y22"
)
port map (
IA => b_20_CY0F_6007,
IB => b_20_CY0F_6007,
SEL => b_20_CYSELF_5996,
O => b_20_CYMUXF2_5991
);
b_20_CYINIT : X_BUF
generic map(
LOC => "SLICE_X21Y22",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_19_Q,
O => b_20_CYINIT_6008
);
b_20_CY0F : X_BUF
generic map(
LOC => "SLICE_X21Y22",
PATHPULSE => 638 ps
)
port map (
I => Sh180,
O => b_20_CY0F_6007
);
b_20_CYSELF : X_BUF
generic map(
LOC => "SLICE_X21Y22",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(20),
O => b_20_CYSELF_5996
);
b_20_YUSED : X_BUF
generic map(
LOC => "SLICE_X21Y22",
PATHPULSE => 638 ps
)
port map (
I => b_20_XORG_5998,
O => b_21_Q
);
b_20_XORG : X_XOR2
generic map(
LOC => "SLICE_X21Y22"
)
port map (
I0 => Madd_b_cy_20_Q,
I1 => Madd_b_lut(21),
O => b_20_XORG_5998
);
b_20_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X21Y22",
PATHPULSE => 638 ps
)
port map (
I => b_20_CYMUXFAST_5995,
O => Madd_b_cy_21_Q
);
b_20_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X21Y22",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_19_Q,
O => b_20_FASTCARRY_5993
);
b_20_CYAND : X_AND2
generic map(
LOC => "SLICE_X21Y22"
)
port map (
I0 => b_20_CYSELG_5984,
I1 => b_20_CYSELF_5996,
O => b_20_CYAND_5994
);
b_20_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X21Y22"
)
port map (
IA => b_20_CYMUXG2_5992,
IB => b_20_FASTCARRY_5993,
SEL => b_20_CYAND_5994,
O => b_20_CYMUXFAST_5995
);
b_20_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X21Y22"
)
port map (
IA => b_20_CY0G_5990,
IB => b_20_CYMUXF2_5991,
SEL => b_20_CYSELG_5984,
O => b_20_CYMUXG2_5992
);
b_20_CY0G : X_BUF
generic map(
LOC => "SLICE_X21Y22",
PATHPULSE => 638 ps
)
port map (
I => Sh181,
O => b_20_CY0G_5990
);
b_20_CYSELG : X_BUF
generic map(
LOC => "SLICE_X21Y22",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(21),
O => b_20_CYSELG_5984
);
b_22_XUSED : X_BUF
generic map(
LOC => "SLICE_X21Y23",
PATHPULSE => 638 ps
)
port map (
I => b_22_XORF_6052,
O => b_22_Q
);
b_22_XORF : X_XOR2
generic map(
LOC => "SLICE_X21Y23"
)
port map (
I0 => b_22_CYINIT_6051,
I1 => Madd_b_lut(22),
O => b_22_XORF_6052
);
b_22_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X21Y23"
)
port map (
IA => b_22_CY0F_6050,
IB => b_22_CYINIT_6051,
SEL => b_22_CYSELF_6039,
O => Madd_b_cy_22_Q
);
b_22_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X21Y23"
)
port map (
IA => b_22_CY0F_6050,
IB => b_22_CY0F_6050,
SEL => b_22_CYSELF_6039,
O => b_22_CYMUXF2_6034
);
b_22_CYINIT : X_BUF
generic map(
LOC => "SLICE_X21Y23",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_21_Q,
O => b_22_CYINIT_6051
);
b_22_CY0F : X_BUF
generic map(
LOC => "SLICE_X21Y23",
PATHPULSE => 638 ps
)
port map (
I => Sh182,
O => b_22_CY0F_6050
);
b_22_CYSELF : X_BUF
generic map(
LOC => "SLICE_X21Y23",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(22),
O => b_22_CYSELF_6039
);
b_22_YUSED : X_BUF
generic map(
LOC => "SLICE_X21Y23",
PATHPULSE => 638 ps
)
port map (
I => b_22_XORG_6041,
O => b_23_Q
);
b_22_XORG : X_XOR2
generic map(
LOC => "SLICE_X21Y23"
)
port map (
I0 => Madd_b_cy_22_Q,
I1 => Madd_b_lut(23),
O => b_22_XORG_6041
);
b_22_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X21Y23",
PATHPULSE => 638 ps
)
port map (
I => b_22_CYMUXFAST_6038,
O => Madd_b_cy_23_Q
);
b_22_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X21Y23",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_21_Q,
O => b_22_FASTCARRY_6036
);
b_22_CYAND : X_AND2
generic map(
LOC => "SLICE_X21Y23"
)
port map (
I0 => b_22_CYSELG_6027,
I1 => b_22_CYSELF_6039,
O => b_22_CYAND_6037
);
b_22_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X21Y23"
)
port map (
IA => b_22_CYMUXG2_6035,
IB => b_22_FASTCARRY_6036,
SEL => b_22_CYAND_6037,
O => b_22_CYMUXFAST_6038
);
b_22_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X21Y23"
)
port map (
IA => b_22_CY0G_6033,
IB => b_22_CYMUXF2_6034,
SEL => b_22_CYSELG_6027,
O => b_22_CYMUXG2_6035
);
b_22_CY0G : X_BUF
generic map(
LOC => "SLICE_X21Y23",
PATHPULSE => 638 ps
)
port map (
I => Sh183,
O => b_22_CY0G_6033
);
b_22_CYSELG : X_BUF
generic map(
LOC => "SLICE_X21Y23",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(23),
O => b_22_CYSELG_6027
);
b_24_XUSED : X_BUF
generic map(
LOC => "SLICE_X21Y24",
PATHPULSE => 638 ps
)
port map (
I => b_24_XORF_6093,
O => b_24_Q
);
b_24_XORF : X_XOR2
generic map(
LOC => "SLICE_X21Y24"
)
port map (
I0 => b_24_CYINIT_6092,
I1 => Madd_b_lut(24),
O => b_24_XORF_6093
);
b_24_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X21Y24"
)
port map (
IA => b_24_CY0F_6091,
IB => b_24_CYINIT_6092,
SEL => b_24_CYSELF_6080,
O => Madd_b_cy_24_Q
);
b_24_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X21Y24"
)
port map (
IA => b_24_CY0F_6091,
IB => b_24_CY0F_6091,
SEL => b_24_CYSELF_6080,
O => b_24_CYMUXF2_6075
);
b_24_CYINIT : X_BUF
generic map(
LOC => "SLICE_X21Y24",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_23_Q,
O => b_24_CYINIT_6092
);
b_24_CY0F : X_BUF
generic map(
LOC => "SLICE_X21Y24",
PATHPULSE => 638 ps
)
port map (
I => Sh184,
O => b_24_CY0F_6091
);
b_24_CYSELF : X_BUF
generic map(
LOC => "SLICE_X21Y24",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(24),
O => b_24_CYSELF_6080
);
b_24_YUSED : X_BUF
generic map(
LOC => "SLICE_X21Y24",
PATHPULSE => 638 ps
)
port map (
I => b_24_XORG_6082,
O => b_25_Q
);
b_24_XORG : X_XOR2
generic map(
LOC => "SLICE_X21Y24"
)
port map (
I0 => Madd_b_cy_24_Q,
I1 => Madd_b_lut(25),
O => b_24_XORG_6082
);
b_24_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X21Y24",
PATHPULSE => 638 ps
)
port map (
I => b_24_CYMUXFAST_6079,
O => Madd_b_cy_25_Q
);
b_24_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X21Y24",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_23_Q,
O => b_24_FASTCARRY_6077
);
b_24_CYAND : X_AND2
generic map(
LOC => "SLICE_X21Y24"
)
port map (
I0 => b_24_CYSELG_6068,
I1 => b_24_CYSELF_6080,
O => b_24_CYAND_6078
);
b_24_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X21Y24"
)
port map (
IA => b_24_CYMUXG2_6076,
IB => b_24_FASTCARRY_6077,
SEL => b_24_CYAND_6078,
O => b_24_CYMUXFAST_6079
);
b_24_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X21Y24"
)
port map (
IA => b_24_CY0G_6074,
IB => b_24_CYMUXF2_6075,
SEL => b_24_CYSELG_6068,
O => b_24_CYMUXG2_6076
);
b_24_CY0G : X_BUF
generic map(
LOC => "SLICE_X21Y24",
PATHPULSE => 638 ps
)
port map (
I => Sh185_0,
O => b_24_CY0G_6074
);
b_24_CYSELG : X_BUF
generic map(
LOC => "SLICE_X21Y24",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(25),
O => b_24_CYSELG_6068
);
b_26_XUSED : X_BUF
generic map(
LOC => "SLICE_X21Y25",
PATHPULSE => 638 ps
)
port map (
I => b_26_XORF_6136,
O => b_26_Q
);
b_26_XORF : X_XOR2
generic map(
LOC => "SLICE_X21Y25"
)
port map (
I0 => b_26_CYINIT_6135,
I1 => Madd_b_lut(26),
O => b_26_XORF_6136
);
b_26_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X21Y25"
)
port map (
IA => b_26_CY0F_6134,
IB => b_26_CYINIT_6135,
SEL => b_26_CYSELF_6123,
O => Madd_b_cy_26_Q
);
b_26_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X21Y25"
)
port map (
IA => b_26_CY0F_6134,
IB => b_26_CY0F_6134,
SEL => b_26_CYSELF_6123,
O => b_26_CYMUXF2_6118
);
b_26_CYINIT : X_BUF
generic map(
LOC => "SLICE_X21Y25",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_25_Q,
O => b_26_CYINIT_6135
);
b_26_CY0F : X_BUF
generic map(
LOC => "SLICE_X21Y25",
PATHPULSE => 638 ps
)
port map (
I => Sh186,
O => b_26_CY0F_6134
);
b_26_CYSELF : X_BUF
generic map(
LOC => "SLICE_X21Y25",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(26),
O => b_26_CYSELF_6123
);
b_26_YUSED : X_BUF
generic map(
LOC => "SLICE_X21Y25",
PATHPULSE => 638 ps
)
port map (
I => b_26_XORG_6125,
O => b_27_Q
);
b_26_XORG : X_XOR2
generic map(
LOC => "SLICE_X21Y25"
)
port map (
I0 => Madd_b_cy_26_Q,
I1 => Madd_b_lut(27),
O => b_26_XORG_6125
);
b_26_COUTUSED : X_BUF
generic map(
LOC => "SLICE_X21Y25",
PATHPULSE => 638 ps
)
port map (
I => b_26_CYMUXFAST_6122,
O => Madd_b_cy_27_Q
);
b_26_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X21Y25",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_25_Q,
O => b_26_FASTCARRY_6120
);
b_26_CYAND : X_AND2
generic map(
LOC => "SLICE_X21Y25"
)
port map (
I0 => b_26_CYSELG_6111,
I1 => b_26_CYSELF_6123,
O => b_26_CYAND_6121
);
b_26_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X21Y25"
)
port map (
IA => b_26_CYMUXG2_6119,
IB => b_26_FASTCARRY_6120,
SEL => b_26_CYAND_6121,
O => b_26_CYMUXFAST_6122
);
b_26_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X21Y25"
)
port map (
IA => b_26_CY0G_6117,
IB => b_26_CYMUXF2_6118,
SEL => b_26_CYSELG_6111,
O => b_26_CYMUXG2_6119
);
b_26_CY0G : X_BUF
generic map(
LOC => "SLICE_X21Y25",
PATHPULSE => 638 ps
)
port map (
I => Sh187,
O => b_26_CY0G_6117
);
b_26_CYSELG : X_BUF
generic map(
LOC => "SLICE_X21Y25",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(27),
O => b_26_CYSELG_6111
);
b_28_XUSED : X_BUF
generic map(
LOC => "SLICE_X21Y26",
PATHPULSE => 638 ps
)
port map (
I => b_28_XORF_6179,
O => b_28_Q
);
b_28_XORF : X_XOR2
generic map(
LOC => "SLICE_X21Y26"
)
port map (
I0 => b_28_CYINIT_6178,
I1 => Madd_b_lut(28),
O => b_28_XORF_6179
);
b_28_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X21Y26"
)
port map (
IA => b_28_CY0F_6177,
IB => b_28_CYINIT_6178,
SEL => b_28_CYSELF_6166,
O => Madd_b_cy_28_Q
);
b_28_CYMUXF2 : X_MUX2
generic map(
LOC => "SLICE_X21Y26"
)
port map (
IA => b_28_CY0F_6177,
IB => b_28_CY0F_6177,
SEL => b_28_CYSELF_6166,
O => b_28_CYMUXF2_6161
);
b_28_CYINIT : X_BUF
generic map(
LOC => "SLICE_X21Y26",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_27_Q,
O => b_28_CYINIT_6178
);
b_28_CY0F : X_BUF
generic map(
LOC => "SLICE_X21Y26",
PATHPULSE => 638 ps
)
port map (
I => Sh188,
O => b_28_CY0F_6177
);
b_28_CYSELF : X_BUF
generic map(
LOC => "SLICE_X21Y26",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(28),
O => b_28_CYSELF_6166
);
b_28_YUSED : X_BUF
generic map(
LOC => "SLICE_X21Y26",
PATHPULSE => 638 ps
)
port map (
I => b_28_XORG_6168,
O => b_29_Q
);
b_28_XORG : X_XOR2
generic map(
LOC => "SLICE_X21Y26"
)
port map (
I0 => Madd_b_cy_28_Q,
I1 => Madd_b_lut(29),
O => b_28_XORG_6168
);
b_28_FASTCARRY : X_BUF
generic map(
LOC => "SLICE_X21Y26",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_cy_27_Q,
O => b_28_FASTCARRY_6163
);
b_28_CYAND : X_AND2
generic map(
LOC => "SLICE_X21Y26"
)
port map (
I0 => b_28_CYSELG_6154,
I1 => b_28_CYSELF_6166,
O => b_28_CYAND_6164
);
b_28_CYMUXFAST : X_MUX2
generic map(
LOC => "SLICE_X21Y26"
)
port map (
IA => b_28_CYMUXG2_6162,
IB => b_28_FASTCARRY_6163,
SEL => b_28_CYAND_6164,
O => b_28_CYMUXFAST_6165
);
b_28_CYMUXG2 : X_MUX2
generic map(
LOC => "SLICE_X21Y26"
)
port map (
IA => b_28_CY0G_6160,
IB => b_28_CYMUXF2_6161,
SEL => b_28_CYSELG_6154,
O => b_28_CYMUXG2_6162
);
b_28_CY0G : X_BUF
generic map(
LOC => "SLICE_X21Y26",
PATHPULSE => 638 ps
)
port map (
I => Sh189,
O => b_28_CY0G_6160
);
b_28_CYSELG : X_BUF
generic map(
LOC => "SLICE_X21Y26",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(29),
O => b_28_CYSELG_6154
);
b_30_XUSED : X_BUF
generic map(
LOC => "SLICE_X21Y27",
PATHPULSE => 638 ps
)
port map (
I => b_30_XORF_6212,
O => b_30_Q
);
b_30_XORF : X_XOR2
generic map(
LOC => "SLICE_X21Y27"
)
port map (
I0 => b_30_CYINIT_6211,
I1 => Madd_b_lut(30),
O => b_30_XORF_6212
);
b_30_CYMUXF : X_MUX2
generic map(
LOC => "SLICE_X21Y27"
)
port map (
IA => b_30_CY0F_6210,
IB => b_30_CYINIT_6211,
SEL => b_30_CYSELF_6204,
O => Madd_b_cy_30_Q
);
b_30_CYINIT : X_BUF
generic map(
LOC => "SLICE_X21Y27",
PATHPULSE => 638 ps
)
port map (
I => b_28_CYMUXFAST_6165,
O => b_30_CYINIT_6211
);
b_30_CY0F : X_BUF
generic map(
LOC => "SLICE_X21Y27",
PATHPULSE => 638 ps
)
port map (
I => Sh190,
O => b_30_CY0F_6210
);
b_30_CYSELF : X_BUF
generic map(
LOC => "SLICE_X21Y27",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_lut(30),
O => b_30_CYSELF_6204
);
b_30_YUSED : X_BUF
generic map(
LOC => "SLICE_X21Y27",
PATHPULSE => 638 ps
)
port map (
I => b_30_XORG_6200,
O => b_31_Q
);
b_30_XORG : X_XOR2
generic map(
LOC => "SLICE_X21Y27"
)
port map (
I0 => Madd_b_cy_30_Q,
I1 => Madd_b_lut(31),
O => b_30_XORG_6200
);
din_lower_0_IBUF : X_BUF
generic map(
LOC => "IPAD60",
PATHPULSE => 638 ps
)
port map (
I => din_lower(0),
O => din_lower_0_INBUF
);
din_lower_1_IBUF : X_BUF
generic map(
LOC => "PAD83",
PATHPULSE => 638 ps
)
port map (
I => din_lower(1),
O => din_lower_1_INBUF
);
din_lower_2_IBUF : X_BUF
generic map(
LOC => "IPAD86",
PATHPULSE => 638 ps
)
port map (
I => din_lower(2),
O => din_lower_2_INBUF
);
din_lower_3_IBUF : X_BUF
generic map(
LOC => "IPAD3",
PATHPULSE => 638 ps
)
port map (
I => din_lower(3),
O => din_lower_3_INBUF
);
din_lower_4_IBUF : X_BUF
generic map(
LOC => "PAD94",
PATHPULSE => 638 ps
)
port map (
I => din_lower(4),
O => din_lower_4_INBUF
);
din_lower_5_IBUF : X_BUF
generic map(
LOC => "PAD99",
PATHPULSE => 638 ps
)
port map (
I => din_lower(5),
O => din_lower_5_INBUF
);
din_lower_6_IBUF : X_BUF
generic map(
LOC => "IPAD100",
PATHPULSE => 638 ps
)
port map (
I => din_lower(6),
O => din_lower_6_INBUF
);
din_lower_7_IBUF : X_BUF
generic map(
LOC => "IPAD73",
PATHPULSE => 638 ps
)
port map (
I => din_lower(7),
O => din_lower_7_INBUF
);
clr_PULLUP : X_PU
generic map(
LOC => "PAD11"
)
port map (
O => NlwRenamedSig_IO_clr
);
clr_IBUF : X_BUF
generic map(
LOC => "PAD11",
PATHPULSE => 638 ps
)
port map (
I => NlwRenamedSig_IO_clr,
O => clr_INBUF
);
AN_0_OBUF : X_OBUF
generic map(
LOC => "PAD33"
)
port map (
I => AN_0_O,
O => AN(0)
);
AN_1_OBUF : X_OBUF
generic map(
LOC => "PAD44"
)
port map (
I => AN_1_O,
O => AN(1)
);
AN_2_OBUF : X_OBUF
generic map(
LOC => "PAD51"
)
port map (
I => AN_2_O,
O => AN(2)
);
AN_3_OBUF : X_OBUF
generic map(
LOC => "PAD45"
)
port map (
I => AN_3_O,
O => AN(3)
);
segment_a_i_OBUF : X_OBUF
generic map(
LOC => "PAD48"
)
port map (
I => segment_a_i_O,
O => segment_a_i
);
segment_b_i_OBUF : X_OBUF
generic map(
LOC => "PAD39"
)
port map (
I => segment_b_i_O,
O => segment_b_i
);
segment_c_i_OBUF : X_OBUF
generic map(
LOC => "PAD53"
)
port map (
I => segment_c_i_O,
O => segment_c_i
);
segment_d_i_OBUF : X_OBUF
generic map(
LOC => "PAD59"
)
port map (
I => segment_d_i_O,
O => segment_d_i
);
segment_e_i_OBUF : X_OBUF
generic map(
LOC => "PAD56"
)
port map (
I => segment_e_i_O,
O => segment_e_i
);
segment_f_i_OBUF : X_OBUF
generic map(
LOC => "PAD49"
)
port map (
I => segment_f_i_O,
O => segment_f_i
);
segment_g_i_OBUF : X_OBUF
generic map(
LOC => "PAD52"
)
port map (
I => segment_g_i_O,
O => segment_g_i
);
clk_25_BUFGP_IBUFG : X_BUF
generic map(
LOC => "IPAD13",
PATHPULSE => 638 ps
)
port map (
I => clk_25,
O => clk_25_INBUF
);
di_vld_PULLUP : X_PU
generic map(
LOC => "PAD72"
)
port map (
O => NlwRenamedSig_IO_di_vld
);
di_vld_IBUF : X_BUF
generic map(
LOC => "PAD72",
PATHPULSE => 638 ps
)
port map (
I => NlwRenamedSig_IO_di_vld,
O => di_vld_INBUF
);
do_rdy_OBUF : X_OBUF
generic map(
LOC => "PAD79"
)
port map (
I => do_rdy_O,
O => do_rdy
);
swtch_led_0_OBUF : X_OBUF
generic map(
LOC => "PAD69"
)
port map (
I => swtch_led_0_O,
O => swtch_led(0)
);
swtch_led_1_OBUF : X_OBUF
generic map(
LOC => "PAD58"
)
port map (
I => swtch_led_1_O,
O => swtch_led(1)
);
swtch_led_2_OBUF : X_OBUF
generic map(
LOC => "PAD64"
)
port map (
I => swtch_led_2_O,
O => swtch_led(2)
);
swtch_led_3_OBUF : X_OBUF
generic map(
LOC => "PAD65"
)
port map (
I => swtch_led_3_O,
O => swtch_led(3)
);
swtch_led_4_OBUF : X_OBUF
generic map(
LOC => "PAD68"
)
port map (
I => swtch_led_4_O,
O => swtch_led(4)
);
swtch_led_5_OBUF : X_OBUF
generic map(
LOC => "PAD71"
)
port map (
I => swtch_led_5_O,
O => swtch_led(5)
);
swtch_led_6_OBUF : X_OBUF
generic map(
LOC => "PAD70"
)
port map (
I => swtch_led_6_O,
O => swtch_led(6)
);
swtch_led_7_OBUF : X_OBUF
generic map(
LOC => "PAD96"
)
port map (
I => swtch_led_7_O,
O => swtch_led(7)
);
clk_25_BUFGP_BUFG : X_BUFGMUX
generic map(
LOC => "BUFGMUX_X2Y11"
)
port map (
I0 => clk_25_BUFGP_BUFG_I0_INV,
I1 => GND,
S => clk_25_BUFGP_BUFG_S_INVNOT,
O => clk_25_BUFGP
);
clk_25_BUFGP_BUFG_SINV : X_INV
generic map(
LOC => "BUFGMUX_X2Y11",
PATHPULSE => 638 ps
)
port map (
I => '1',
O => clk_25_BUFGP_BUFG_S_INVNOT
);
clk_25_BUFGP_BUFG_I0_USED : X_BUF
generic map(
LOC => "BUFGMUX_X2Y11",
PATHPULSE => 638 ps
)
port map (
I => clk_25_INBUF,
O => clk_25_BUFGP_BUFG_I0_INV
);
Sh13120_XUSED : X_BUF
generic map(
LOC => "SLICE_X26Y18",
PATHPULSE => 638 ps
)
port map (
I => Sh13120_F5MUX_6468,
O => Sh13120
);
Sh13120_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X26Y18"
)
port map (
IA => N402,
IB => N403,
SEL => Sh13120_BXINV_6460,
O => Sh13120_F5MUX_6468
);
Sh13120_BXINV : X_BUF
generic map(
LOC => "SLICE_X26Y18",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh13120_BXINV_6460
);
Sh13332_G : X_LUT4
generic map(
INIT => X"AACC",
LOC => "SLICE_X26Y14"
)
port map (
ADR0 => Sh121,
ADR1 => Sh125,
ADR2 => VCC,
ADR3 => a(2),
O => N527
);
Sh133_XUSED : X_BUF
generic map(
LOC => "SLICE_X26Y14",
PATHPULSE => 638 ps
)
port map (
I => Sh133_F5MUX_6493,
O => Sh133
);
Sh133_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X26Y14"
)
port map (
IA => N526,
IB => N527,
SEL => Sh133_BXINV_6485,
O => Sh133_F5MUX_6493
);
Sh133_BXINV : X_BUF
generic map(
LOC => "SLICE_X26Y14",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh133_BXINV_6485
);
Sh13332_F : X_LUT4
generic map(
INIT => X"FC30",
LOC => "SLICE_X26Y14"
)
port map (
ADR0 => VCC,
ADR1 => a(2),
ADR2 => Sh101,
ADR3 => Sh97,
O => N526
);
Sh14029_G : X_LUT4
generic map(
INIT => X"AFA0",
LOC => "SLICE_X26Y16"
)
port map (
ADR0 => Sh96,
ADR1 => VCC,
ADR2 => a(2),
ADR3 => Sh100,
O => N407
);
Sh140_XUSED : X_BUF
generic map(
LOC => "SLICE_X26Y16",
PATHPULSE => 638 ps
)
port map (
I => Sh140_F5MUX_6518,
O => Sh140
);
Sh140_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X26Y16"
)
port map (
IA => N406,
IB => N407,
SEL => Sh140_BXINV_6510,
O => Sh140_F5MUX_6518
);
Sh140_BXINV : X_BUF
generic map(
LOC => "SLICE_X26Y16",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh140_BXINV_6510
);
Sh14029_F : X_LUT4
generic map(
INIT => X"AACC",
LOC => "SLICE_X26Y16"
)
port map (
ADR0 => Sh104,
ADR1 => Sh108,
ADR2 => VCC,
ADR3 => a(2),
O => N406
);
Sh14129_G : X_LUT4
generic map(
INIT => X"ACAC",
LOC => "SLICE_X25Y15"
)
port map (
ADR0 => Sh97,
ADR1 => Sh101,
ADR2 => a(2),
ADR3 => VCC,
O => N409
);
Sh141_XUSED : X_BUF
generic map(
LOC => "SLICE_X25Y15",
PATHPULSE => 638 ps
)
port map (
I => Sh141_F5MUX_6543,
O => Sh141
);
Sh141_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X25Y15"
)
port map (
IA => N408,
IB => N409,
SEL => Sh141_BXINV_6535,
O => Sh141_F5MUX_6543
);
Sh141_BXINV : X_BUF
generic map(
LOC => "SLICE_X25Y15",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh141_BXINV_6535
);
Sh14129_F : X_LUT4
generic map(
INIT => X"E4E4",
LOC => "SLICE_X25Y15"
)
port map (
ADR0 => a(2),
ADR1 => Sh109,
ADR2 => Sh105,
ADR3 => VCC,
O => N408
);
Sh14229_G : X_LUT4
generic map(
INIT => X"D8D8",
LOC => "SLICE_X27Y19"
)
port map (
ADR0 => a(2),
ADR1 => Sh98_0,
ADR2 => Sh102_0,
ADR3 => VCC,
O => N315
);
Sh142_XUSED : X_BUF
generic map(
LOC => "SLICE_X27Y19",
PATHPULSE => 638 ps
)
port map (
I => Sh142_F5MUX_6568,
O => Sh142
);
Sh142_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X27Y19"
)
port map (
IA => N314,
IB => N315,
SEL => Sh142_BXINV_6560,
O => Sh142_F5MUX_6568
);
Sh142_BXINV : X_BUF
generic map(
LOC => "SLICE_X27Y19",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh142_BXINV_6560
);
Sh14229_F : X_LUT4
generic map(
INIT => X"EE44",
LOC => "SLICE_X27Y19"
)
port map (
ADR0 => a(2),
ADR1 => Sh110_0,
ADR2 => VCC,
ADR3 => Sh106_0,
O => N314
);
Sh13528_G : X_LUT4
generic map(
INIT => X"CCF0",
LOC => "SLICE_X22Y26"
)
port map (
ADR0 => VCC,
ADR1 => Sh123,
ADR2 => Sh127,
ADR3 => a(2),
O => N303
);
Sh135_XUSED : X_BUF
generic map(
LOC => "SLICE_X22Y26",
PATHPULSE => 638 ps
)
port map (
I => Sh135_F5MUX_6593,
O => Sh135
);
Sh135_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X22Y26"
)
port map (
IA => N302,
IB => N303,
SEL => Sh135_BXINV_6585,
O => Sh135_F5MUX_6593
);
Sh135_BXINV : X_BUF
generic map(
LOC => "SLICE_X22Y26",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh135_BXINV_6585
);
Sh13528_F : X_LUT4
generic map(
INIT => X"FC30",
LOC => "SLICE_X22Y26"
)
port map (
ADR0 => VCC,
ADR1 => a(2),
ADR2 => Sh103_0,
ADR3 => Sh99_0,
O => N302
);
Sh14612_G : X_LUT4
generic map(
INIT => X"CA00",
LOC => "SLICE_X27Y20"
)
port map (
ADR0 => Sh1022_0,
ADR1 => Sh1002_0,
ADR2 => a(1),
ADR3 => a(2),
O => N415
);
Sh14612_XUSED : X_BUF
generic map(
LOC => "SLICE_X27Y20",
PATHPULSE => 638 ps
)
port map (
I => Sh14612_F5MUX_6618,
O => Sh14612
);
Sh14612_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X27Y20"
)
port map (
IA => N414,
IB => N415,
SEL => Sh14612_BXINV_6611,
O => Sh14612_F5MUX_6618
);
Sh14612_BXINV : X_BUF
generic map(
LOC => "SLICE_X27Y20",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh14612_BXINV_6611
);
Sh14612_F : X_LUT4
generic map(
INIT => X"E400",
LOC => "SLICE_X27Y20"
)
port map (
ADR0 => a(1),
ADR1 => Sh1102_0,
ADR2 => Sh1082_0,
ADR3 => a(2),
O => N414
);
Sh13628_G : X_LUT4
generic map(
INIT => X"F5A0",
LOC => "SLICE_X27Y16"
)
port map (
ADR0 => a(2),
ADR1 => VCC,
ADR2 => Sh124,
ADR3 => Sh96,
O => N305
);
Sh136_XUSED : X_BUF
generic map(
LOC => "SLICE_X27Y16",
PATHPULSE => 638 ps
)
port map (
I => Sh136_F5MUX_6643,
O => Sh136
);
Sh136_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X27Y16"
)
port map (
IA => N304,
IB => N305,
SEL => Sh136_BXINV_6635,
O => Sh136_F5MUX_6643
);
Sh136_BXINV : X_BUF
generic map(
LOC => "SLICE_X27Y16",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh136_BXINV_6635
);
Sh13628_F : X_LUT4
generic map(
INIT => X"BB88",
LOC => "SLICE_X27Y16"
)
port map (
ADR0 => Sh100,
ADR1 => a(2),
ADR2 => VCC,
ADR3 => Sh104,
O => N304
);
Sh14712_G : X_LUT4
generic map(
INIT => X"88A0",
LOC => "SLICE_X25Y18"
)
port map (
ADR0 => a(2),
ADR1 => Sh1012_0,
ADR2 => Sh1032_0,
ADR3 => a(1),
O => N413
);
Sh14712_XUSED : X_BUF
generic map(
LOC => "SLICE_X25Y18",
PATHPULSE => 638 ps
)
port map (
I => Sh14712_F5MUX_6668,
O => Sh14712
);
Sh14712_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X25Y18"
)
port map (
IA => N412,
IB => N413,
SEL => Sh14712_BXINV_6661,
O => Sh14712_F5MUX_6668
);
Sh14712_BXINV : X_BUF
generic map(
LOC => "SLICE_X25Y18",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh14712_BXINV_6661
);
Sh14712_F : X_LUT4
generic map(
INIT => X"8A80",
LOC => "SLICE_X25Y18"
)
port map (
ADR0 => a(2),
ADR1 => Sh1092_0,
ADR2 => a(1),
ADR3 => Sh1112_0,
O => N412
);
Sh13728_G : X_LUT4
generic map(
INIT => X"E4E4",
LOC => "SLICE_X29Y14"
)
port map (
ADR0 => a(2),
ADR1 => Sh97,
ADR2 => Sh125,
ADR3 => VCC,
O => N307
);
Sh137_XUSED : X_BUF
generic map(
LOC => "SLICE_X29Y14",
PATHPULSE => 638 ps
)
port map (
I => Sh137_F5MUX_6693,
O => Sh137
);
Sh137_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X29Y14"
)
port map (
IA => N306,
IB => N307,
SEL => Sh137_BXINV_6685,
O => Sh137_F5MUX_6693
);
Sh137_BXINV : X_BUF
generic map(
LOC => "SLICE_X29Y14",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh137_BXINV_6685
);
Sh13728_F : X_LUT4
generic map(
INIT => X"D8D8",
LOC => "SLICE_X29Y14"
)
port map (
ADR0 => a(2),
ADR1 => Sh101,
ADR2 => Sh105,
ADR3 => VCC,
O => N306
);
Sh13929_G : X_LUT4
generic map(
INIT => X"CCAA",
LOC => "SLICE_X24Y24"
)
port map (
ADR0 => Sh99_0,
ADR1 => Sh127,
ADR2 => VCC,
ADR3 => a(2),
O => N299
);
Sh139_XUSED : X_BUF
generic map(
LOC => "SLICE_X24Y24",
PATHPULSE => 638 ps
)
port map (
I => Sh139_F5MUX_6718,
O => Sh139
);
Sh139_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X24Y24"
)
port map (
IA => N298,
IB => N299,
SEL => Sh139_BXINV_6710,
O => Sh139_F5MUX_6718
);
Sh139_BXINV : X_BUF
generic map(
LOC => "SLICE_X24Y24",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh139_BXINV_6710
);
Sh13929_F : X_LUT4
generic map(
INIT => X"EE22",
LOC => "SLICE_X24Y24"
)
port map (
ADR0 => Sh107,
ADR1 => a(2),
ADR2 => VCC,
ADR3 => Sh103_0,
O => N298
);
b_reg_mux0000_10_21_G : X_LUT4
generic map(
INIT => X"FEAE",
LOC => "SLICE_X14Y14"
)
port map (
ADR0 => b_reg_mux0000_10_10_0,
ADR1 => b_reg(10),
ADR2 => state_FSM_FFd2_4312,
ADR3 => state_FSM_FFd1_4311,
O => N529
);
b_reg_mux0000_10_21_F : X_LUT4
generic map(
INIT => X"AFAA",
LOC => "SLICE_X14Y14"
)
port map (
ADR0 => b_reg_mux0000_10_10_0,
ADR1 => VCC,
ADR2 => state_FSM_FFd2_4312,
ADR3 => b_reg(10),
O => N528
);
b_reg_10_FFX_RSTOR : X_BUF
generic map(
LOC => "SLICE_X14Y14",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_10_FFX_RST
);
b_reg_10 : X_FF
generic map(
LOC => "SLICE_X14Y14",
INIT => '0'
)
port map (
I => b_reg_10_DXMUX_6749,
CE => VCC,
CLK => b_reg_10_CLKINV_6731,
SET => GND,
RST => b_reg_10_FFX_RST,
O => b_reg(10)
);
b_reg_10_DXMUX : X_BUF
generic map(
LOC => "SLICE_X14Y14",
PATHPULSE => 638 ps
)
port map (
I => b_reg_10_F5MUX_6747,
O => b_reg_10_DXMUX_6749
);
b_reg_10_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X14Y14"
)
port map (
IA => N528,
IB => N529,
SEL => b_reg_10_BXINV_6740,
O => b_reg_10_F5MUX_6747
);
b_reg_10_BXINV : X_BUF
generic map(
LOC => "SLICE_X14Y14",
PATHPULSE => 638 ps
)
port map (
I => b_10_XORF_5798,
O => b_reg_10_BXINV_6740
);
b_reg_10_CLKINV : X_BUF
generic map(
LOC => "SLICE_X14Y14",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_10_CLKINV_6731
);
Sh10_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y13",
PATHPULSE => 638 ps
)
port map (
I => Sh10_F5MUX_6779,
O => Sh10
);
Sh10_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y13"
)
port map (
IA => N470,
IB => N471,
SEL => Sh10_BXINV_6772,
O => Sh10_F5MUX_6779
);
Sh10_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y13",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh10_BXINV_6772
);
Sh13_XUSED : X_BUF
generic map(
LOC => "SLICE_X14Y17",
PATHPULSE => 638 ps
)
port map (
I => Sh13_F5MUX_6804,
O => Sh13
);
Sh13_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X14Y17"
)
port map (
IA => N494,
IB => N495,
SEL => Sh13_BXINV_6797,
O => Sh13_F5MUX_6804
);
Sh13_BXINV : X_BUF
generic map(
LOC => "SLICE_X14Y17",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh13_BXINV_6797
);
Sh21_f5_G : X_LUT4
generic map(
INIT => X"7D28",
LOC => "SLICE_X14Y30"
)
port map (
ADR0 => b_reg_0_2_4323,
ADR1 => b_reg(18),
ADR2 => a_reg(18),
ADR3 => ab_xor_19_0,
O => N491
);
Sh21_XUSED : X_BUF
generic map(
LOC => "SLICE_X14Y30",
PATHPULSE => 638 ps
)
port map (
I => Sh21_F5MUX_6829,
O => Sh21
);
Sh21_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X14Y30"
)
port map (
IA => N490,
IB => N491,
SEL => Sh21_BXINV_6822,
O => Sh21_F5MUX_6829
);
Sh21_BXINV : X_BUF
generic map(
LOC => "SLICE_X14Y30",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh21_BXINV_6822
);
Sh21_f5_F : X_LUT4
generic map(
INIT => X"BE14",
LOC => "SLICE_X14Y30"
)
port map (
ADR0 => b_reg_0_2_4323,
ADR1 => b_reg(21),
ADR2 => a_reg(21),
ADR3 => ab_xor_20_0,
O => N490
);
Sh14_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y16",
PATHPULSE => 638 ps
)
port map (
I => Sh14_F5MUX_6854,
O => Sh14
);
Sh14_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y16"
)
port map (
IA => N486,
IB => N487,
SEL => Sh14_BXINV_6847,
O => Sh14_F5MUX_6854
);
Sh14_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y16",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh14_BXINV_6847
);
Sh14_f5_G : X_LUT4
generic map(
INIT => X"F066",
LOC => "SLICE_X12Y16"
)
port map (
ADR0 => b_reg(12),
ADR1 => a_reg(12),
ADR2 => ab_xor_11_0,
ADR3 => b_reg_0_3_4316,
O => N487
);
Sh22_XUSED : X_BUF
generic map(
LOC => "SLICE_X15Y31",
PATHPULSE => 638 ps
)
port map (
I => Sh22_F5MUX_6879,
O => Sh22_4347
);
Sh22_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X15Y31"
)
port map (
IA => N482,
IB => N483,
SEL => Sh22_BXINV_6872,
O => Sh22_F5MUX_6879
);
Sh22_BXINV : X_BUF
generic map(
LOC => "SLICE_X15Y31",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh22_BXINV_6872
);
Sh30_XUSED : X_BUF
generic map(
LOC => "SLICE_X14Y35",
PATHPULSE => 638 ps
)
port map (
I => Sh30_F5MUX_6904,
O => Sh30
);
Sh30_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X14Y35"
)
port map (
IA => N472,
IB => N473,
SEL => Sh30_BXINV_6897,
O => Sh30_F5MUX_6904
);
Sh30_BXINV : X_BUF
generic map(
LOC => "SLICE_X14Y35",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh30_BXINV_6897
);
Sh17_XUSED : X_BUF
generic map(
LOC => "SLICE_X14Y23",
PATHPULSE => 638 ps
)
port map (
I => Sh17_F5MUX_6929,
O => Sh17
);
Sh17_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X14Y23"
)
port map (
IA => N492,
IB => N493,
SEL => Sh17_BXINV_6922,
O => Sh17_F5MUX_6929
);
Sh17_BXINV : X_BUF
generic map(
LOC => "SLICE_X14Y23",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh17_BXINV_6922
);
Sh25_XUSED : X_BUF
generic map(
LOC => "SLICE_X15Y32",
PATHPULSE => 638 ps
)
port map (
I => Sh25_F5MUX_6954,
O => Sh25
);
Sh25_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X15Y32"
)
port map (
IA => N488,
IB => N489,
SEL => Sh25_BXINV_6947,
O => Sh25_F5MUX_6954
);
Sh25_BXINV : X_BUF
generic map(
LOC => "SLICE_X15Y32",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh25_BXINV_6947
);
Sh18_XUSED : X_BUF
generic map(
LOC => "SLICE_X13Y20",
PATHPULSE => 638 ps
)
port map (
I => Sh18_F5MUX_6979,
O => Sh18
);
Sh18_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X13Y20"
)
port map (
IA => N484,
IB => N485,
SEL => Sh18_BXINV_6972,
O => Sh18_F5MUX_6979
);
Sh18_BXINV : X_BUF
generic map(
LOC => "SLICE_X13Y20",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh18_BXINV_6972
);
Sh26_XUSED : X_BUF
generic map(
LOC => "SLICE_X14Y32",
PATHPULSE => 638 ps
)
port map (
I => Sh26_F5MUX_7004,
O => Sh26
);
Sh26_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X14Y32"
)
port map (
IA => N480,
IB => N481,
SEL => Sh26_BXINV_6997,
O => Sh26_F5MUX_7004
);
Sh26_BXINV : X_BUF
generic map(
LOC => "SLICE_X14Y32",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh26_BXINV_6997
);
Sh29_XUSED : X_BUF
generic map(
LOC => "SLICE_X15Y34",
PATHPULSE => 638 ps
)
port map (
I => Sh29_F5MUX_7029,
O => Sh29
);
Sh29_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X15Y34"
)
port map (
IA => N478,
IB => N479,
SEL => Sh29_BXINV_7022,
O => Sh29_F5MUX_7029
);
Sh29_BXINV : X_BUF
generic map(
LOC => "SLICE_X15Y34",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh29_BXINV_7022
);
Sh4_XUSED : X_BUF
generic map(
LOC => "SLICE_X15Y19",
PATHPULSE => 638 ps
)
port map (
I => Sh4_F5MUX_7054,
O => Sh4
);
Sh4_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X15Y19"
)
port map (
IA => N300,
IB => N301,
SEL => Sh4_BXINV_7047,
O => Sh4_F5MUX_7054
);
Sh4_BXINV : X_BUF
generic map(
LOC => "SLICE_X15Y19",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh4_BXINV_7047
);
Sh8_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y14",
PATHPULSE => 638 ps
)
port map (
I => Sh8_F5MUX_7079,
O => Sh8
);
Sh8_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y14"
)
port map (
IA => N324,
IB => N325,
SEL => Sh8_BXINV_7072,
O => Sh8_F5MUX_7079
);
Sh8_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y14",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh8_BXINV_7072
);
Sh96_XUSED : X_BUF
generic map(
LOC => "SLICE_X23Y27",
PATHPULSE => 638 ps
)
port map (
I => Sh96_F5MUX_7106,
O => Sh96
);
Sh96_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X23Y27"
)
port map (
IA => Sh962,
IB => Sh1262_rt_7104,
SEL => Sh96_BXINV_7096,
O => Sh96_F5MUX_7106
);
Sh96_BXINV : X_BUF
generic map(
LOC => "SLICE_X23Y27",
PATHPULSE => 638 ps
)
port map (
I => a(1),
O => Sh96_BXINV_7096
);
Sh96_YUSED : X_BUF
generic map(
LOC => "SLICE_X23Y27",
PATHPULSE => 638 ps
)
port map (
I => Sh962,
O => Sh962_0
);
Sh97_XUSED : X_BUF
generic map(
LOC => "SLICE_X24Y27",
PATHPULSE => 638 ps
)
port map (
I => Sh97_F5MUX_7131,
O => Sh97
);
Sh97_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X24Y27"
)
port map (
IA => Sh972_7119,
IB => Sh1272_rt_7129,
SEL => Sh97_BXINV_7121,
O => Sh97_F5MUX_7131
);
Sh97_BXINV : X_BUF
generic map(
LOC => "SLICE_X24Y27",
PATHPULSE => 638 ps
)
port map (
I => a(1),
O => Sh97_BXINV_7121
);
Sh100_XUSED : X_BUF
generic map(
LOC => "SLICE_X25Y27",
PATHPULSE => 638 ps
)
port map (
I => Sh100_F5MUX_7158,
O => Sh100
);
Sh100_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X25Y27"
)
port map (
IA => Sh1002,
IB => Sh1001_7156,
SEL => Sh100_BXINV_7151,
O => Sh100_F5MUX_7158
);
Sh100_BXINV : X_BUF
generic map(
LOC => "SLICE_X25Y27",
PATHPULSE => 638 ps
)
port map (
I => a(1),
O => Sh100_BXINV_7151
);
Sh100_YUSED : X_BUF
generic map(
LOC => "SLICE_X25Y27",
PATHPULSE => 638 ps
)
port map (
I => Sh1002,
O => Sh1002_0
);
Sh101_XUSED : X_BUF
generic map(
LOC => "SLICE_X22Y18",
PATHPULSE => 638 ps
)
port map (
I => Sh101_F5MUX_7185,
O => Sh101
);
Sh101_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X22Y18"
)
port map (
IA => Sh1012,
IB => Sh1011_rt_7183,
SEL => Sh101_BXINV_7175,
O => Sh101_F5MUX_7185
);
Sh101_BXINV : X_BUF
generic map(
LOC => "SLICE_X22Y18",
PATHPULSE => 638 ps
)
port map (
I => a(1),
O => Sh101_BXINV_7175
);
Sh101_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y18",
PATHPULSE => 638 ps
)
port map (
I => Sh1012,
O => Sh1012_0
);
Sh120_XUSED : X_BUF
generic map(
LOC => "SLICE_X21Y28",
PATHPULSE => 638 ps
)
port map (
I => Sh120_F5MUX_7212,
O => Sh120
);
Sh120_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X21Y28"
)
port map (
IA => Sh1202,
IB => Sh1182_rt_7210,
SEL => Sh120_BXINV_7202,
O => Sh120_F5MUX_7212
);
Sh120_BXINV : X_BUF
generic map(
LOC => "SLICE_X21Y28",
PATHPULSE => 638 ps
)
port map (
I => a(1),
O => Sh120_BXINV_7202
);
Sh120_YUSED : X_BUF
generic map(
LOC => "SLICE_X21Y28",
PATHPULSE => 638 ps
)
port map (
I => Sh1202,
O => Sh1202_0
);
Sh112_XUSED : X_BUF
generic map(
LOC => "SLICE_X25Y20",
PATHPULSE => 638 ps
)
port map (
I => Sh112_F5MUX_7239,
O => Sh112
);
Sh112_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X25Y20"
)
port map (
IA => Sh1122,
IB => Sh1102_rt_7237,
SEL => Sh112_BXINV_7229,
O => Sh112_F5MUX_7239
);
Sh112_BXINV : X_BUF
generic map(
LOC => "SLICE_X25Y20",
PATHPULSE => 638 ps
)
port map (
I => a(1),
O => Sh112_BXINV_7229
);
Sh112_YUSED : X_BUF
generic map(
LOC => "SLICE_X25Y20",
PATHPULSE => 638 ps
)
port map (
I => Sh1122,
O => Sh1122_0
);
Sh104_XUSED : X_BUF
generic map(
LOC => "SLICE_X20Y13",
PATHPULSE => 638 ps
)
port map (
I => Sh104_F5MUX_7266,
O => Sh104
);
Sh104_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X20Y13"
)
port map (
IA => Sh1042,
IB => Sh1022_rt_7264,
SEL => Sh104_BXINV_7256,
O => Sh104_F5MUX_7266
);
Sh104_BXINV : X_BUF
generic map(
LOC => "SLICE_X20Y13",
PATHPULSE => 638 ps
)
port map (
I => a(1),
O => Sh104_BXINV_7256
);
Sh104_YUSED : X_BUF
generic map(
LOC => "SLICE_X20Y13",
PATHPULSE => 638 ps
)
port map (
I => Sh1042,
O => Sh1042_0
);
Sh121_XUSED : X_BUF
generic map(
LOC => "SLICE_X23Y29",
PATHPULSE => 638 ps
)
port map (
I => Sh121_F5MUX_7293,
O => Sh121
);
Sh121_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X23Y29"
)
port map (
IA => Sh1212,
IB => Sh1192_rt_7291,
SEL => Sh121_BXINV_7283,
O => Sh121_F5MUX_7293
);
Sh121_BXINV : X_BUF
generic map(
LOC => "SLICE_X23Y29",
PATHPULSE => 638 ps
)
port map (
I => a(1),
O => Sh121_BXINV_7283
);
Sh121_YUSED : X_BUF
generic map(
LOC => "SLICE_X23Y29",
PATHPULSE => 638 ps
)
port map (
I => Sh1212,
O => Sh1212_0
);
Sh113_XUSED : X_BUF
generic map(
LOC => "SLICE_X24Y20",
PATHPULSE => 638 ps
)
port map (
I => Sh113_F5MUX_7320,
O => Sh113
);
Sh113_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X24Y20"
)
port map (
IA => Sh1132,
IB => Sh1112_rt_7318,
SEL => Sh113_BXINV_7310,
O => Sh113_F5MUX_7320
);
Sh113_BXINV : X_BUF
generic map(
LOC => "SLICE_X24Y20",
PATHPULSE => 638 ps
)
port map (
I => a(1),
O => Sh113_BXINV_7310
);
Sh113_YUSED : X_BUF
generic map(
LOC => "SLICE_X24Y20",
PATHPULSE => 638 ps
)
port map (
I => Sh1132,
O => Sh1132_0
);
Sh105_XUSED : X_BUF
generic map(
LOC => "SLICE_X20Y12",
PATHPULSE => 638 ps
)
port map (
I => Sh105_F5MUX_7347,
O => Sh105
);
Sh105_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X20Y12"
)
port map (
IA => Sh1052,
IB => Sh1032_rt_7345,
SEL => Sh105_BXINV_7337,
O => Sh105_F5MUX_7347
);
Sh105_BXINV : X_BUF
generic map(
LOC => "SLICE_X20Y12",
PATHPULSE => 638 ps
)
port map (
I => a(1),
O => Sh105_BXINV_7337
);
Sh105_YUSED : X_BUF
generic map(
LOC => "SLICE_X20Y12",
PATHPULSE => 638 ps
)
port map (
I => Sh1052,
O => Sh1052_0
);
Sh124_XUSED : X_BUF
generic map(
LOC => "SLICE_X22Y29",
PATHPULSE => 638 ps
)
port map (
I => Sh124_F5MUX_7374,
O => Sh124
);
Sh124_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X22Y29"
)
port map (
IA => Sh1242,
IB => Sh1222_rt_7372,
SEL => Sh124_BXINV_7364,
O => Sh124_F5MUX_7374
);
Sh124_BXINV : X_BUF
generic map(
LOC => "SLICE_X22Y29",
PATHPULSE => 638 ps
)
port map (
I => a(1),
O => Sh124_BXINV_7364
);
Sh124_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y29",
PATHPULSE => 638 ps
)
port map (
I => Sh1242,
O => Sh1242_0
);
Sh116_XUSED : X_BUF
generic map(
LOC => "SLICE_X25Y24",
PATHPULSE => 638 ps
)
port map (
I => Sh116_F5MUX_7401,
O => Sh116
);
Sh116_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X25Y24"
)
port map (
IA => Sh1162,
IB => Sh1142_rt_7399,
SEL => Sh116_BXINV_7391,
O => Sh116_F5MUX_7401
);
Sh116_BXINV : X_BUF
generic map(
LOC => "SLICE_X25Y24",
PATHPULSE => 638 ps
)
port map (
I => a(1),
O => Sh116_BXINV_7391
);
Sh116_YUSED : X_BUF
generic map(
LOC => "SLICE_X25Y24",
PATHPULSE => 638 ps
)
port map (
I => Sh1162,
O => Sh1162_0
);
Sh108_XUSED : X_BUF
generic map(
LOC => "SLICE_X22Y12",
PATHPULSE => 638 ps
)
port map (
I => Sh108_F5MUX_7428,
O => Sh108
);
Sh108_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X22Y12"
)
port map (
IA => Sh1082,
IB => Sh1062_rt_7426,
SEL => Sh108_BXINV_7418,
O => Sh108_F5MUX_7428
);
Sh108_BXINV : X_BUF
generic map(
LOC => "SLICE_X22Y12",
PATHPULSE => 638 ps
)
port map (
I => a(1),
O => Sh108_BXINV_7418
);
Sh108_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y12",
PATHPULSE => 638 ps
)
port map (
I => Sh1082,
O => Sh1082_0
);
Sh125_XUSED : X_BUF
generic map(
LOC => "SLICE_X23Y30",
PATHPULSE => 638 ps
)
port map (
I => Sh125_F5MUX_7455,
O => Sh125
);
Sh125_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X23Y30"
)
port map (
IA => Sh1252,
IB => Sh1232_rt_7453,
SEL => Sh125_BXINV_7445,
O => Sh125_F5MUX_7455
);
Sh125_BXINV : X_BUF
generic map(
LOC => "SLICE_X23Y30",
PATHPULSE => 638 ps
)
port map (
I => a(1),
O => Sh125_BXINV_7445
);
Sh125_YUSED : X_BUF
generic map(
LOC => "SLICE_X23Y30",
PATHPULSE => 638 ps
)
port map (
I => Sh1252,
O => Sh1252_0
);
Sh117_XUSED : X_BUF
generic map(
LOC => "SLICE_X25Y25",
PATHPULSE => 638 ps
)
port map (
I => Sh117_F5MUX_7482,
O => Sh117
);
Sh117_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X25Y25"
)
port map (
IA => Sh1172,
IB => Sh1152_rt_7480,
SEL => Sh117_BXINV_7472,
O => Sh117_F5MUX_7482
);
Sh117_BXINV : X_BUF
generic map(
LOC => "SLICE_X25Y25",
PATHPULSE => 638 ps
)
port map (
I => a(1),
O => Sh117_BXINV_7472
);
Sh117_YUSED : X_BUF
generic map(
LOC => "SLICE_X25Y25",
PATHPULSE => 638 ps
)
port map (
I => Sh1172,
O => Sh1172_0
);
Sh109_XUSED : X_BUF
generic map(
LOC => "SLICE_X22Y16",
PATHPULSE => 638 ps
)
port map (
I => Sh109_F5MUX_7509,
O => Sh109
);
Sh109_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X22Y16"
)
port map (
IA => Sh1092,
IB => Sh1072_rt_7507,
SEL => Sh109_BXINV_7499,
O => Sh109_F5MUX_7509
);
Sh109_BXINV : X_BUF
generic map(
LOC => "SLICE_X22Y16",
PATHPULSE => 638 ps
)
port map (
I => a(1),
O => Sh109_BXINV_7499
);
Sh109_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y16",
PATHPULSE => 638 ps
)
port map (
I => Sh1092,
O => Sh1092_0
);
Sh3_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y20",
PATHPULSE => 638 ps
)
port map (
I => Sh3_F5MUX_7534,
O => Sh3
);
Sh3_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y20"
)
port map (
IA => N308,
IB => N309,
SEL => Sh3_BXINV_7526,
O => Sh3_F5MUX_7534
);
Sh3_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y20",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh3_BXINV_7526
);
Sh7_XUSED : X_BUF
generic map(
LOC => "SLICE_X13Y17",
PATHPULSE => 638 ps
)
port map (
I => Sh7_F5MUX_7559,
O => Sh7
);
Sh7_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X13Y17"
)
port map (
IA => N336,
IB => N337,
SEL => Sh7_BXINV_7552,
O => Sh7_F5MUX_7559
);
Sh7_BXINV : X_BUF
generic map(
LOC => "SLICE_X13Y17",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh7_BXINV_7552
);
Sh11_XUSED : X_BUF
generic map(
LOC => "SLICE_X13Y12",
PATHPULSE => 638 ps
)
port map (
I => Sh11_F5MUX_7584,
O => Sh11
);
Sh11_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X13Y12"
)
port map (
IA => N348,
IB => N349,
SEL => Sh11_BXINV_7577,
O => Sh11_F5MUX_7584
);
Sh11_BXINV : X_BUF
generic map(
LOC => "SLICE_X13Y12",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh11_BXINV_7577
);
Sh15_XUSED : X_BUF
generic map(
LOC => "SLICE_X13Y16",
PATHPULSE => 638 ps
)
port map (
I => Sh15_F5MUX_7609,
O => Sh15
);
Sh15_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X13Y16"
)
port map (
IA => N346,
IB => N347,
SEL => Sh15_BXINV_7602,
O => Sh15_F5MUX_7609
);
Sh15_BXINV : X_BUF
generic map(
LOC => "SLICE_X13Y16",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh15_BXINV_7602
);
Sh23_XUSED : X_BUF
generic map(
LOC => "SLICE_X15Y33",
PATHPULSE => 638 ps
)
port map (
I => Sh23_F5MUX_7634,
O => Sh23_4457
);
Sh23_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X15Y33"
)
port map (
IA => N342,
IB => N343,
SEL => Sh23_BXINV_7627,
O => Sh23_F5MUX_7634
);
Sh23_BXINV : X_BUF
generic map(
LOC => "SLICE_X15Y33",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh23_BXINV_7627
);
Sh31_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y34",
PATHPULSE => 638 ps
)
port map (
I => Sh31_F5MUX_7659,
O => Sh31
);
Sh31_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y34"
)
port map (
IA => N338,
IB => N339,
SEL => Sh31_BXINV_7652,
O => Sh31_F5MUX_7659
);
Sh31_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y34",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh31_BXINV_7652
);
Sh19_XUSED : X_BUF
generic map(
LOC => "SLICE_X14Y22",
PATHPULSE => 638 ps
)
port map (
I => Sh19_F5MUX_7684,
O => Sh19
);
Sh19_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X14Y22"
)
port map (
IA => N344,
IB => N345,
SEL => Sh19_BXINV_7677,
O => Sh19_F5MUX_7684
);
Sh19_BXINV : X_BUF
generic map(
LOC => "SLICE_X14Y22",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh19_BXINV_7677
);
Sh27_XUSED : X_BUF
generic map(
LOC => "SLICE_X14Y34",
PATHPULSE => 638 ps
)
port map (
I => Sh27_F5MUX_7709,
O => Sh27
);
Sh27_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X14Y34"
)
port map (
IA => N340,
IB => N341,
SEL => Sh27_BXINV_7702,
O => Sh27_F5MUX_7709
);
Sh27_BXINV : X_BUF
generic map(
LOC => "SLICE_X14Y34",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh27_BXINV_7702
);
Sh12_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y15",
PATHPULSE => 638 ps
)
port map (
I => Sh12_F5MUX_7734,
O => Sh12
);
Sh12_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y15"
)
port map (
IA => N334,
IB => N335,
SEL => Sh12_BXINV_7727,
O => Sh12_F5MUX_7734
);
Sh12_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y15",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh12_BXINV_7727
);
Sh20_XUSED : X_BUF
generic map(
LOC => "SLICE_X15Y25",
PATHPULSE => 638 ps
)
port map (
I => Sh20_F5MUX_7759,
O => Sh20
);
Sh20_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X15Y25"
)
port map (
IA => N330,
IB => N331,
SEL => Sh20_BXINV_7752,
O => Sh20_F5MUX_7759
);
Sh20_BXINV : X_BUF
generic map(
LOC => "SLICE_X15Y25",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh20_BXINV_7752
);
Sh16_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y21",
PATHPULSE => 638 ps
)
port map (
I => Sh16_F5MUX_7784,
O => Sh16
);
Sh16_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y21"
)
port map (
IA => N332,
IB => N333,
SEL => Sh16_BXINV_7777,
O => Sh16_F5MUX_7784
);
Sh16_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y21",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh16_BXINV_7777
);
Sh24_XUSED : X_BUF
generic map(
LOC => "SLICE_X14Y33",
PATHPULSE => 638 ps
)
port map (
I => Sh24_F5MUX_7809,
O => Sh24
);
Sh24_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X14Y33"
)
port map (
IA => N328,
IB => N329,
SEL => Sh24_BXINV_7802,
O => Sh24_F5MUX_7809
);
Sh24_BXINV : X_BUF
generic map(
LOC => "SLICE_X14Y33",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh24_BXINV_7802
);
Sh28_XUSED : X_BUF
generic map(
LOC => "SLICE_X15Y35",
PATHPULSE => 638 ps
)
port map (
I => Sh28_F5MUX_7834,
O => Sh28
);
Sh28_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X15Y35"
)
port map (
IA => N326,
IB => N327,
SEL => Sh28_BXINV_7827,
O => Sh28_F5MUX_7834
);
Sh28_BXINV : X_BUF
generic map(
LOC => "SLICE_X15Y35",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh28_BXINV_7827
);
Sh123_XUSED : X_BUF
generic map(
LOC => "SLICE_X23Y28",
PATHPULSE => 638 ps
)
port map (
I => Sh123_F5MUX_7859,
O => Sh123
);
Sh123_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X23Y28"
)
port map (
IA => N496,
IB => N497,
SEL => Sh123_BXINV_7852,
O => Sh123_F5MUX_7859
);
Sh123_BXINV : X_BUF
generic map(
LOC => "SLICE_X23Y28",
PATHPULSE => 638 ps
)
port map (
I => a(1),
O => Sh123_BXINV_7852
);
Sh127_XUSED : X_BUF
generic map(
LOC => "SLICE_X21Y30",
PATHPULSE => 638 ps
)
port map (
I => Sh127_F5MUX_7884,
O => Sh127
);
Sh127_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X21Y30"
)
port map (
IA => N460,
IB => N461,
SEL => Sh127_BXINV_7877,
O => Sh127_F5MUX_7884
);
Sh127_BXINV : X_BUF
generic map(
LOC => "SLICE_X21Y30",
PATHPULSE => 638 ps
)
port map (
I => a(1),
O => Sh127_BXINV_7877
);
Sh145_XUSED : X_BUF
generic map(
LOC => "SLICE_X24Y15",
PATHPULSE => 638 ps
)
port map (
I => Sh145_F5MUX_7909,
O => Sh145
);
Sh145_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X24Y15"
)
port map (
IA => Sh145311_7899,
IB => Sh14531,
SEL => Sh145_BXINV_7901,
O => Sh145_F5MUX_7909
);
Sh145_BXINV : X_BUF
generic map(
LOC => "SLICE_X24Y15",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh145_BXINV_7901
);
Sh_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y35",
PATHPULSE => 638 ps
)
port map (
I => Sh_F5MUX_7934,
O => Sh
);
Sh_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y35"
)
port map (
IA => N410,
IB => N411,
SEL => Sh_BXINV_7927,
O => Sh_F5MUX_7934
);
Sh_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y35",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh_BXINV_7927
);
N291_XUSED : X_BUF
generic map(
LOC => "SLICE_X8Y3",
PATHPULSE => 638 ps
)
port map (
I => N291_F5MUX_7959,
O => N291
);
N291_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X8Y3"
)
port map (
IA => N464,
IB => N465,
SEL => N291_BXINV_7950,
O => N291_F5MUX_7959
);
N291_BXINV : X_BUF
generic map(
LOC => "SLICE_X8Y3",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd1_4311,
O => N291_BXINV_7950
);
N292_XUSED : X_BUF
generic map(
LOC => "SLICE_X8Y2",
PATHPULSE => 638 ps
)
port map (
I => N292_F5MUX_7984,
O => N292
);
N292_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X8Y2"
)
port map (
IA => N466,
IB => N467,
SEL => N292_BXINV_7975,
O => N292_F5MUX_7984
);
N292_BXINV : X_BUF
generic map(
LOC => "SLICE_X8Y2",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd1_4311,
O => N292_BXINV_7975
);
N281_XUSED : X_BUF
generic map(
LOC => "SLICE_X2Y20",
PATHPULSE => 638 ps
)
port map (
I => N281_F5MUX_8009,
O => N281
);
N281_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X2Y20"
)
port map (
IA => N456,
IB => N457,
SEL => N281_BXINV_8000,
O => N281_F5MUX_8009
);
N281_BXINV : X_BUF
generic map(
LOC => "SLICE_X2Y20",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd1_4311,
O => N281_BXINV_8000
);
b_reg_mux0000_3_24_SW0_G : X_LUT4
generic map(
INIT => X"2222",
LOC => "SLICE_X2Y20"
)
port map (
ADR0 => b_reg(3),
ADR1 => state_FSM_FFd2_4312,
ADR2 => VCC,
ADR3 => VCC,
O => N457
);
b_reg_mux0000_3_24_SW1_G : X_LUT4
generic map(
INIT => X"FFF0",
LOC => "SLICE_X2Y23"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => state_FSM_FFd2_4312,
ADR3 => b_reg(3),
O => N459
);
N282_XUSED : X_BUF
generic map(
LOC => "SLICE_X2Y23",
PATHPULSE => 638 ps
)
port map (
I => N282_F5MUX_8034,
O => N282
);
N282_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X2Y23"
)
port map (
IA => N458,
IB => N459,
SEL => N282_BXINV_8025,
O => N282_F5MUX_8034
);
N282_BXINV : X_BUF
generic map(
LOC => "SLICE_X2Y23",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd1_4311,
O => N282_BXINV_8025
);
b_reg_mux0000_3_24_SW1_F : X_LUT4
generic map(
INIT => X"B784",
LOC => "SLICE_X2Y23"
)
port map (
ADR0 => Madd_b_pre_cy_2_Q,
ADR1 => state_FSM_FFd2_4312,
ADR2 => swtch_led_3_OBUF_4256,
ADR3 => b_reg(3),
O => N458
);
b_reg_mux0000_4_34_SW0_G : X_LUT4
generic map(
INIT => X"0A0A",
LOC => "SLICE_X1Y20"
)
port map (
ADR0 => b_reg(4),
ADR1 => VCC,
ADR2 => state_FSM_FFd2_4312,
ADR3 => VCC,
O => N453
);
N278_XUSED : X_BUF
generic map(
LOC => "SLICE_X1Y20",
PATHPULSE => 638 ps
)
port map (
I => N278_F5MUX_8059,
O => N278
);
N278_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X1Y20"
)
port map (
IA => N452,
IB => N453,
SEL => N278_BXINV_8050,
O => N278_F5MUX_8059
);
N278_BXINV : X_BUF
generic map(
LOC => "SLICE_X1Y20",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd1_4311,
O => N278_BXINV_8050
);
b_reg_mux0000_4_34_SW0_F : X_LUT4
generic map(
INIT => X"FCAC",
LOC => "SLICE_X1Y20"
)
port map (
ADR0 => b_reg_mux0000_4_3_0,
ADR1 => b_reg(4),
ADR2 => state_FSM_FFd2_4312,
ADR3 => b_reg_mux0000_4_12_0,
O => N452
);
b_reg_mux0000_4_34_SW1_G : X_LUT4
generic map(
INIT => X"FFCC",
LOC => "SLICE_X0Y21"
)
port map (
ADR0 => VCC,
ADR1 => state_FSM_FFd2_4312,
ADR2 => VCC,
ADR3 => b_reg(4),
O => N455
);
N279_XUSED : X_BUF
generic map(
LOC => "SLICE_X0Y21",
PATHPULSE => 638 ps
)
port map (
I => N279_F5MUX_8084,
O => N279
);
N279_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X0Y21"
)
port map (
IA => N454,
IB => N455,
SEL => N279_BXINV_8075,
O => N279_F5MUX_8084
);
N279_BXINV : X_BUF
generic map(
LOC => "SLICE_X0Y21",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd1_4311,
O => N279_BXINV_8075
);
b_reg_mux0000_4_34_SW1_F : X_LUT4
generic map(
INIT => X"FCB8",
LOC => "SLICE_X0Y21"
)
port map (
ADR0 => b_reg_mux0000_4_12_0,
ADR1 => state_FSM_FFd2_4312,
ADR2 => b_reg(4),
ADR3 => b_reg_mux0000_4_3_0,
O => N454
);
Sh1307_G : X_LUT4
generic map(
INIT => X"BB88",
LOC => "SLICE_X26Y23"
)
port map (
ADR0 => Sh1162_0,
ADR1 => a(1),
ADR2 => VCC,
ADR3 => Sh1182_0,
O => N371
);
Sh1307_XUSED : X_BUF
generic map(
LOC => "SLICE_X26Y23",
PATHPULSE => 638 ps
)
port map (
I => Sh1307_F5MUX_8109,
O => Sh1307
);
Sh1307_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X26Y23"
)
port map (
IA => N370,
IB => N371,
SEL => Sh1307_BXINV_8101,
O => Sh1307_F5MUX_8109
);
Sh1307_BXINV : X_BUF
generic map(
LOC => "SLICE_X26Y23",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh1307_BXINV_8101
);
Sh1307_F : X_LUT4
generic map(
INIT => X"EE22",
LOC => "SLICE_X26Y23"
)
port map (
ADR0 => Sh1262_0,
ADR1 => a(1),
ADR2 => VCC,
ADR3 => Sh1242_0,
O => N370
);
Sh1601_G : X_LUT4
generic map(
INIT => X"DDDC",
LOC => "SLICE_X23Y12"
)
port map (
ADR0 => a(2),
ADR1 => Sh14412_0,
ADR2 => Sh14413_0,
ADR3 => Sh14416_4486,
O => N319
);
Sh160_XUSED : X_BUF
generic map(
LOC => "SLICE_X23Y12",
PATHPULSE => 638 ps
)
port map (
I => Sh160_F5MUX_8134,
O => Sh160
);
Sh160_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X23Y12"
)
port map (
IA => N318,
IB => N319,
SEL => Sh160_BXINV_8127,
O => Sh160_F5MUX_8134
);
Sh160_BXINV : X_BUF
generic map(
LOC => "SLICE_X23Y12",
PATHPULSE => 638 ps
)
port map (
I => a(4),
O => Sh160_BXINV_8127
);
Sh1601_F : X_LUT4
generic map(
INIT => X"FE54",
LOC => "SLICE_X23Y12"
)
port map (
ADR0 => a(2),
ADR1 => Sh12813_0,
ADR2 => Sh12816_0,
ADR3 => Sh1287_0,
O => N318
);
Sh1507_G : X_LUT4
generic map(
INIT => X"E4E4",
LOC => "SLICE_X29Y20"
)
port map (
ADR0 => a(1),
ADR1 => Sh1062_0,
ADR2 => Sh1042_0,
ADR3 => VCC,
O => N435
);
Sh1507_XUSED : X_BUF
generic map(
LOC => "SLICE_X29Y20",
PATHPULSE => 638 ps
)
port map (
I => Sh1507_F5MUX_8159,
O => Sh1507
);
Sh1507_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X29Y20"
)
port map (
IA => N434,
IB => N435,
SEL => Sh1507_BXINV_8151,
O => Sh1507_F5MUX_8159
);
Sh1507_BXINV : X_BUF
generic map(
LOC => "SLICE_X29Y20",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh1507_BXINV_8151
);
Sh1507_F : X_LUT4
generic map(
INIT => X"ACAC",
LOC => "SLICE_X29Y20"
)
port map (
ADR0 => Sh1122_0,
ADR1 => Sh1142_0,
ADR2 => a(1),
ADR3 => VCC,
O => N434
);
Sh1427_G : X_LUT4
generic map(
INIT => X"F0CC",
LOC => "SLICE_X28Y18"
)
port map (
ADR0 => VCC,
ADR1 => Sh982_4493,
ADR2 => Sh962_0,
ADR3 => a(1),
O => N417
);
Sh13820_XUSED : X_BUF
generic map(
LOC => "SLICE_X28Y18",
PATHPULSE => 638 ps
)
port map (
I => Sh13820_F5MUX_8184,
O => Sh13820
);
Sh13820_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X28Y18"
)
port map (
IA => N416,
IB => N417,
SEL => Sh13820_BXINV_8176,
O => Sh13820_F5MUX_8184
);
Sh13820_BXINV : X_BUF
generic map(
LOC => "SLICE_X28Y18",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh13820_BXINV_8176
);
Sh1427_F : X_LUT4
generic map(
INIT => X"EE44",
LOC => "SLICE_X28Y18"
)
port map (
ADR0 => a(1),
ADR1 => Sh1062_0,
ADR2 => VCC,
ADR3 => Sh1042_0,
O => N416
);
Sh1517_XUSED : X_BUF
generic map(
LOC => "SLICE_X23Y17",
PATHPULSE => 638 ps
)
port map (
I => Sh1517_F5MUX_8209,
O => Sh1517
);
Sh1517_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X23Y17"
)
port map (
IA => N432,
IB => N433,
SEL => Sh1517_BXINV_8201,
O => Sh1517_F5MUX_8209
);
Sh1517_BXINV : X_BUF
generic map(
LOC => "SLICE_X23Y17",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh1517_BXINV_8201
);
Sh162_XUSED : X_BUF
generic map(
LOC => "SLICE_X27Y15",
PATHPULSE => 638 ps
)
port map (
I => Sh162_F5MUX_8234,
O => Sh162
);
Sh162_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X27Y15"
)
port map (
IA => N316,
IB => N317,
SEL => Sh162_BXINV_8227,
O => Sh162_F5MUX_8234
);
Sh162_BXINV : X_BUF
generic map(
LOC => "SLICE_X27Y15",
PATHPULSE => 638 ps
)
port map (
I => a(4),
O => Sh162_BXINV_8227
);
Sh40_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y24",
PATHPULSE => 638 ps
)
port map (
I => Sh40_F5MUX_8259,
O => Sh40
);
Sh40_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y24"
)
port map (
IA => N368,
IB => N369,
SEL => Sh40_BXINV_8251,
O => Sh40_F5MUX_8259
);
Sh40_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y24",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh40_BXINV_8251
);
Sh32_XUSED : X_BUF
generic map(
LOC => "SLICE_X13Y26",
PATHPULSE => 638 ps
)
port map (
I => Sh32_F5MUX_8284,
O => Sh32
);
Sh32_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X13Y26"
)
port map (
IA => N352,
IB => N353,
SEL => Sh32_BXINV_8276,
O => Sh32_F5MUX_8284
);
Sh32_BXINV : X_BUF
generic map(
LOC => "SLICE_X13Y26",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh32_BXINV_8276
);
Sh163_XUSED : X_BUF
generic map(
LOC => "SLICE_X24Y16",
PATHPULSE => 638 ps
)
port map (
I => Sh163_F5MUX_8309,
O => Sh163
);
Sh163_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X24Y16"
)
port map (
IA => N310,
IB => N311,
SEL => Sh163_BXINV_8302,
O => Sh163_F5MUX_8309
);
Sh163_BXINV : X_BUF
generic map(
LOC => "SLICE_X24Y16",
PATHPULSE => 638 ps
)
port map (
I => a(4),
O => Sh163_BXINV_8302
);
Sh164_XUSED : X_BUF
generic map(
LOC => "SLICE_X25Y12",
PATHPULSE => 638 ps
)
port map (
I => Sh164_F5MUX_8334,
O => Sh164
);
Sh164_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X25Y12"
)
port map (
IA => N312,
IB => N313,
SEL => Sh164_BXINV_8327,
O => Sh164_F5MUX_8334
);
Sh164_BXINV : X_BUF
generic map(
LOC => "SLICE_X25Y12",
PATHPULSE => 638 ps
)
port map (
I => a(4),
O => Sh164_BXINV_8327
);
Sh4131_F : X_LUT4
generic map(
INIT => X"D8D8",
LOC => "SLICE_X15Y26"
)
port map (
ADR0 => b_reg(3),
ADR1 => Sh1,
ADR2 => Sh9,
ADR3 => VCC,
O => N424
);
Sh4131_G : X_LUT4
generic map(
INIT => X"ACAC",
LOC => "SLICE_X15Y26"
)
port map (
ADR0 => Sh29,
ADR1 => Sh5,
ADR2 => b_reg(3),
ADR3 => VCC,
O => N425
);
Sh41_XUSED : X_BUF
generic map(
LOC => "SLICE_X15Y26",
PATHPULSE => 638 ps
)
port map (
I => Sh41_F5MUX_8359,
O => Sh41
);
Sh41_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X15Y26"
)
port map (
IA => N424,
IB => N425,
SEL => Sh41_BXINV_8351,
O => Sh41_F5MUX_8359
);
Sh41_BXINV : X_BUF
generic map(
LOC => "SLICE_X15Y26",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh41_BXINV_8351
);
Sh1547_F : X_LUT4
generic map(
INIT => X"F0AA",
LOC => "SLICE_X27Y25"
)
port map (
ADR0 => Sh1182_0,
ADR1 => VCC,
ADR2 => Sh1162_0,
ADR3 => a(1),
O => N420
);
Sh1547_G : X_LUT4
generic map(
INIT => X"CFC0",
LOC => "SLICE_X27Y25"
)
port map (
ADR0 => VCC,
ADR1 => Sh1082_0,
ADR2 => a(1),
ADR3 => Sh1102_0,
O => N421
);
Sh1547_XUSED : X_BUF
generic map(
LOC => "SLICE_X27Y25",
PATHPULSE => 638 ps
)
port map (
I => Sh1547_F5MUX_8384,
O => Sh1547
);
Sh1547_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X27Y25"
)
port map (
IA => N420,
IB => N421,
SEL => Sh1547_BXINV_8376,
O => Sh1547_F5MUX_8384
);
Sh1547_BXINV : X_BUF
generic map(
LOC => "SLICE_X27Y25",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh1547_BXINV_8376
);
Sh1387_F : X_LUT4
generic map(
INIT => X"F3C0",
LOC => "SLICE_X26Y21"
)
port map (
ADR0 => VCC,
ADR1 => a(1),
ADR2 => Sh1002_0,
ADR3 => Sh1022_0,
O => N400
);
Sh1387_G : X_LUT4
generic map(
INIT => X"CCAA",
LOC => "SLICE_X26Y21"
)
port map (
ADR0 => Sh1262_0,
ADR1 => Sh1242_0,
ADR2 => VCC,
ADR3 => a(1),
O => N401
);
Sh13420_XUSED : X_BUF
generic map(
LOC => "SLICE_X26Y21",
PATHPULSE => 638 ps
)
port map (
I => Sh13420_F5MUX_8409,
O => Sh13420
);
Sh13420_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X26Y21"
)
port map (
IA => N400,
IB => N401,
SEL => Sh13420_BXINV_8401,
O => Sh13420_F5MUX_8409
);
Sh13420_BXINV : X_BUF
generic map(
LOC => "SLICE_X26Y21",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh13420_BXINV_8401
);
Sh3331_F : X_LUT4
generic map(
INIT => X"FA50",
LOC => "SLICE_X14Y27"
)
port map (
ADR0 => b_reg(3),
ADR1 => VCC,
ADR2 => Sh1,
ADR3 => Sh25,
O => N374
);
Sh3331_G : X_LUT4
generic map(
INIT => X"DD88",
LOC => "SLICE_X14Y27"
)
port map (
ADR0 => b_reg(3),
ADR1 => Sh21,
ADR2 => VCC,
ADR3 => Sh29,
O => N375
);
Sh33_XUSED : X_BUF
generic map(
LOC => "SLICE_X14Y27",
PATHPULSE => 638 ps
)
port map (
I => Sh33_F5MUX_8434,
O => Sh33
);
Sh33_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X14Y27"
)
port map (
IA => N374,
IB => N375,
SEL => Sh33_BXINV_8426,
O => Sh33_F5MUX_8434
);
Sh33_BXINV : X_BUF
generic map(
LOC => "SLICE_X14Y27",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh33_BXINV_8426
);
Sh1557_F : X_LUT4
generic map(
INIT => X"CFC0",
LOC => "SLICE_X27Y23"
)
port map (
ADR0 => VCC,
ADR1 => Sh1172_0,
ADR2 => a(1),
ADR3 => Sh1192_0,
O => N418
);
Sh1557_G : X_LUT4
generic map(
INIT => X"FC30",
LOC => "SLICE_X27Y23"
)
port map (
ADR0 => VCC,
ADR1 => a(1),
ADR2 => Sh1112_0,
ADR3 => Sh1092_0,
O => N419
);
Sh1557_XUSED : X_BUF
generic map(
LOC => "SLICE_X27Y23",
PATHPULSE => 638 ps
)
port map (
I => Sh1557_F5MUX_8459,
O => Sh1557
);
Sh1557_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X27Y23"
)
port map (
IA => N418,
IB => N419,
SEL => Sh1557_BXINV_8451,
O => Sh1557_F5MUX_8459
);
Sh1557_BXINV : X_BUF
generic map(
LOC => "SLICE_X27Y23",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh1557_BXINV_8451
);
Sh4231_G : X_LUT4
generic map(
INIT => X"AFA0",
LOC => "SLICE_X15Y29"
)
port map (
ADR0 => Sh30,
ADR1 => VCC,
ADR2 => b_reg(3),
ADR3 => Sh6,
O => N429
);
Sh42_XUSED : X_BUF
generic map(
LOC => "SLICE_X15Y29",
PATHPULSE => 638 ps
)
port map (
I => Sh42_F5MUX_8484,
O => Sh42
);
Sh42_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X15Y29"
)
port map (
IA => N428,
IB => N429,
SEL => Sh42_BXINV_8476,
O => Sh42_F5MUX_8484
);
Sh42_BXINV : X_BUF
generic map(
LOC => "SLICE_X15Y29",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh42_BXINV_8476
);
Sh4231_F : X_LUT4
generic map(
INIT => X"CCF0",
LOC => "SLICE_X15Y29"
)
port map (
ADR0 => VCC,
ADR1 => Sh2,
ADR2 => Sh10,
ADR3 => b_reg(3),
O => N428
);
Sh3431_G : X_LUT4
generic map(
INIT => X"FA0A",
LOC => "SLICE_X15Y30"
)
port map (
ADR0 => Sh30,
ADR1 => VCC,
ADR2 => b_reg(3),
ADR3 => Sh22_4347,
O => N379
);
Sh34_XUSED : X_BUF
generic map(
LOC => "SLICE_X15Y30",
PATHPULSE => 638 ps
)
port map (
I => Sh34_F5MUX_8509,
O => Sh34
);
Sh34_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X15Y30"
)
port map (
IA => N378,
IB => N379,
SEL => Sh34_BXINV_8501,
O => Sh34_F5MUX_8509
);
Sh34_BXINV : X_BUF
generic map(
LOC => "SLICE_X15Y30",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh34_BXINV_8501
);
Sh3431_F : X_LUT4
generic map(
INIT => X"F0CC",
LOC => "SLICE_X15Y30"
)
port map (
ADR0 => VCC,
ADR1 => Sh2,
ADR2 => Sh26,
ADR3 => b_reg(3),
O => N378
);
Sh5031_G : X_LUT4
generic map(
INIT => X"CCAA",
LOC => "SLICE_X12Y23"
)
port map (
ADR0 => Sh14,
ADR1 => Sh6,
ADR2 => VCC,
ADR3 => b_reg(3),
O => N377
);
Sh50_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y23",
PATHPULSE => 638 ps
)
port map (
I => Sh50_F5MUX_8534,
O => Sh50
);
Sh50_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y23"
)
port map (
IA => N376,
IB => N377,
SEL => Sh50_BXINV_8526,
O => Sh50_F5MUX_8534
);
Sh50_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y23",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh50_BXINV_8526
);
Sh5031_F : X_LUT4
generic map(
INIT => X"F0AA",
LOC => "SLICE_X12Y23"
)
port map (
ADR0 => Sh18,
ADR1 => VCC,
ADR2 => Sh10,
ADR3 => b_reg(3),
O => N376
);
Sh175_XUSED : X_BUF
generic map(
LOC => "SLICE_X25Y23",
PATHPULSE => 638 ps
)
port map (
I => Sh175_F5MUX_8559,
O => Sh175
);
Sh175_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X25Y23"
)
port map (
IA => N320,
IB => N321,
SEL => Sh175_BXINV_8552,
O => Sh175_F5MUX_8559
);
Sh175_BXINV : X_BUF
generic map(
LOC => "SLICE_X25Y23",
PATHPULSE => 638 ps
)
port map (
I => a(4),
O => Sh175_BXINV_8552
);
Sh1587_XUSED : X_BUF
generic map(
LOC => "SLICE_X28Y22",
PATHPULSE => 638 ps
)
port map (
I => Sh1587_F5MUX_8584,
O => Sh1587
);
Sh1587_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X28Y22"
)
port map (
IA => N426,
IB => N427,
SEL => Sh1587_BXINV_8576,
O => Sh1587_F5MUX_8584
);
Sh1587_BXINV : X_BUF
generic map(
LOC => "SLICE_X28Y22",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh1587_BXINV_8576
);
Sh4331_G : X_LUT4
generic map(
INIT => X"F0CC",
LOC => "SLICE_X12Y29"
)
port map (
ADR0 => VCC,
ADR1 => Sh7,
ADR2 => Sh31,
ADR3 => b_reg(3),
O => N383
);
Sh43_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y29",
PATHPULSE => 638 ps
)
port map (
I => Sh43_F5MUX_8609,
O => Sh43
);
Sh43_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y29"
)
port map (
IA => N382,
IB => N383,
SEL => Sh43_BXINV_8601,
O => Sh43_F5MUX_8609
);
Sh43_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y29",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh43_BXINV_8601
);
Sh4331_F : X_LUT4
generic map(
INIT => X"AAF0",
LOC => "SLICE_X12Y29"
)
port map (
ADR0 => Sh3,
ADR1 => VCC,
ADR2 => Sh11,
ADR3 => b_reg(3),
O => N382
);
Sh3531_G : X_LUT4
generic map(
INIT => X"FA0A",
LOC => "SLICE_X13Y31"
)
port map (
ADR0 => Sh31,
ADR1 => VCC,
ADR2 => b_reg(3),
ADR3 => Sh23_4457,
O => N357
);
Sh35_XUSED : X_BUF
generic map(
LOC => "SLICE_X13Y31",
PATHPULSE => 638 ps
)
port map (
I => Sh35_F5MUX_8634,
O => Sh35
);
Sh35_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X13Y31"
)
port map (
IA => N356,
IB => N357,
SEL => Sh35_BXINV_8626,
O => Sh35_F5MUX_8634
);
Sh35_BXINV : X_BUF
generic map(
LOC => "SLICE_X13Y31",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh35_BXINV_8626
);
Sh51_XUSED : X_BUF
generic map(
LOC => "SLICE_X13Y25",
PATHPULSE => 638 ps
)
port map (
I => Sh51_F5MUX_8659,
O => Sh51
);
Sh51_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X13Y25"
)
port map (
IA => N354,
IB => N355,
SEL => Sh51_BXINV_8651,
O => Sh51_F5MUX_8659
);
Sh51_BXINV : X_BUF
generic map(
LOC => "SLICE_X13Y25",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh51_BXINV_8651
);
Sh1597_XUSED : X_BUF
generic map(
LOC => "SLICE_X26Y26",
PATHPULSE => 638 ps
)
port map (
I => Sh1597_F5MUX_8684,
O => Sh1597
);
Sh1597_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X26Y26"
)
port map (
IA => N468,
IB => N469,
SEL => Sh1597_BXINV_8676,
O => Sh1597_F5MUX_8684
);
Sh1597_BXINV : X_BUF
generic map(
LOC => "SLICE_X26Y26",
PATHPULSE => 638 ps
)
port map (
I => a(3),
O => Sh1597_BXINV_8676
);
Sh178_XUSED : X_BUF
generic map(
LOC => "SLICE_X27Y14",
PATHPULSE => 638 ps
)
port map (
I => Sh178_F5MUX_8709,
O => Sh178
);
Sh178_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X27Y14"
)
port map (
IA => N322,
IB => N323,
SEL => Sh178_BXINV_8702,
O => Sh178_F5MUX_8709
);
Sh178_BXINV : X_BUF
generic map(
LOC => "SLICE_X27Y14",
PATHPULSE => 638 ps
)
port map (
I => a(4),
O => Sh178_BXINV_8702
);
Sh44_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y22",
PATHPULSE => 638 ps
)
port map (
I => Sh44_F5MUX_8734,
O => Sh44
);
Sh44_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y22"
)
port map (
IA => N386,
IB => N387,
SEL => Sh44_BXINV_8726,
O => Sh44_F5MUX_8734
);
Sh44_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y22",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh44_BXINV_8726
);
Sh60_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y27",
PATHPULSE => 638 ps
)
port map (
I => Sh60_F5MUX_8759,
O => Sh60
);
Sh60_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y27"
)
port map (
IA => N384,
IB => N385,
SEL => Sh60_BXINV_8751,
O => Sh60_F5MUX_8759
);
Sh60_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y27",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh60_BXINV_8751
);
Sh36_XUSED : X_BUF
generic map(
LOC => "SLICE_X13Y24",
PATHPULSE => 638 ps
)
port map (
I => Sh36_F5MUX_8784,
O => Sh36
);
Sh36_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X13Y24"
)
port map (
IA => N360,
IB => N361,
SEL => Sh36_BXINV_8776,
O => Sh36_F5MUX_8784
);
Sh36_BXINV : X_BUF
generic map(
LOC => "SLICE_X13Y24",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh36_BXINV_8776
);
Sh52_XUSED : X_BUF
generic map(
LOC => "SLICE_X13Y18",
PATHPULSE => 638 ps
)
port map (
I => Sh52_F5MUX_8809,
O => Sh52
);
Sh52_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X13Y18"
)
port map (
IA => N358,
IB => N359,
SEL => Sh52_BXINV_8801,
O => Sh52_F5MUX_8809
);
Sh52_BXINV : X_BUF
generic map(
LOC => "SLICE_X13Y18",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh52_BXINV_8801
);
Sh45_XUSED : X_BUF
generic map(
LOC => "SLICE_X16Y26",
PATHPULSE => 638 ps
)
port map (
I => Sh45_F5MUX_8834,
O => Sh45
);
Sh45_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X16Y26"
)
port map (
IA => N430,
IB => N431,
SEL => Sh45_BXINV_8826,
O => Sh45_F5MUX_8834
);
Sh45_BXINV : X_BUF
generic map(
LOC => "SLICE_X16Y26",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh45_BXINV_8826
);
Sh37_XUSED : X_BUF
generic map(
LOC => "SLICE_X14Y26",
PATHPULSE => 638 ps
)
port map (
I => Sh37_F5MUX_8859,
O => Sh37
);
Sh37_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X14Y26"
)
port map (
IA => N390,
IB => N391,
SEL => Sh37_BXINV_8851,
O => Sh37_F5MUX_8859
);
Sh37_BXINV : X_BUF
generic map(
LOC => "SLICE_X14Y26",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh37_BXINV_8851
);
Sh53_XUSED : X_BUF
generic map(
LOC => "SLICE_X15Y27",
PATHPULSE => 638 ps
)
port map (
I => Sh53_F5MUX_8884,
O => Sh53
);
Sh53_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X15Y27"
)
port map (
IA => N388,
IB => N389,
SEL => Sh53_BXINV_8876,
O => Sh53_F5MUX_8884
);
Sh53_BXINV : X_BUF
generic map(
LOC => "SLICE_X15Y27",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh53_BXINV_8876
);
Sh46_XUSED : X_BUF
generic map(
LOC => "SLICE_X14Y28",
PATHPULSE => 638 ps
)
port map (
I => Sh46_F5MUX_8909,
O => Sh46
);
Sh46_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X14Y28"
)
port map (
IA => N422,
IB => N423,
SEL => Sh46_BXINV_8901,
O => Sh46_F5MUX_8909
);
Sh46_BXINV : X_BUF
generic map(
LOC => "SLICE_X14Y28",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh46_BXINV_8901
);
Sh38_XUSED : X_BUF
generic map(
LOC => "SLICE_X14Y31",
PATHPULSE => 638 ps
)
port map (
I => Sh38_F5MUX_8934,
O => Sh38
);
Sh38_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X14Y31"
)
port map (
IA => N394,
IB => N395,
SEL => Sh38_BXINV_8926,
O => Sh38_F5MUX_8934
);
Sh38_BXINV : X_BUF
generic map(
LOC => "SLICE_X14Y31",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh38_BXINV_8926
);
Sh54_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y28",
PATHPULSE => 638 ps
)
port map (
I => Sh54_F5MUX_8959,
O => Sh54
);
Sh54_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y28"
)
port map (
IA => N392,
IB => N393,
SEL => Sh54_BXINV_8951,
O => Sh54_F5MUX_8959
);
Sh54_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y28",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh54_BXINV_8951
);
Sh47_XUSED : X_BUF
generic map(
LOC => "SLICE_X13Y21",
PATHPULSE => 638 ps
)
port map (
I => Sh47_F5MUX_8984,
O => Sh47
);
Sh47_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X13Y21"
)
port map (
IA => N398,
IB => N399,
SEL => Sh47_BXINV_8976,
O => Sh47_F5MUX_8984
);
Sh47_BXINV : X_BUF
generic map(
LOC => "SLICE_X13Y21",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh47_BXINV_8976
);
Sh63_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y33",
PATHPULSE => 638 ps
)
port map (
I => Sh63_F5MUX_9009,
O => Sh63
);
Sh63_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y33"
)
port map (
IA => N396,
IB => N397,
SEL => Sh63_BXINV_9001,
O => Sh63_F5MUX_9009
);
Sh63_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y33",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh63_BXINV_9001
);
Sh39_XUSED : X_BUF
generic map(
LOC => "SLICE_X13Y28",
PATHPULSE => 638 ps
)
port map (
I => Sh39_F5MUX_9034,
O => Sh39
);
Sh39_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X13Y28"
)
port map (
IA => N364,
IB => N365,
SEL => Sh39_BXINV_9026,
O => Sh39_F5MUX_9034
);
Sh39_BXINV : X_BUF
generic map(
LOC => "SLICE_X13Y28",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh39_BXINV_9026
);
Sh55_XUSED : X_BUF
generic map(
LOC => "SLICE_X13Y30",
PATHPULSE => 638 ps
)
port map (
I => Sh55_F5MUX_9059,
O => Sh55
);
Sh55_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X13Y30"
)
port map (
IA => N362,
IB => N363,
SEL => Sh55_BXINV_9051,
O => Sh55_F5MUX_9059
);
Sh55_BXINV : X_BUF
generic map(
LOC => "SLICE_X13Y30",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh55_BXINV_9051
);
Sh56_XUSED : X_BUF
generic map(
LOC => "SLICE_X13Y27",
PATHPULSE => 638 ps
)
port map (
I => Sh56_F5MUX_9084,
O => Sh56
);
Sh56_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X13Y27"
)
port map (
IA => N366,
IB => N367,
SEL => Sh56_BXINV_9076,
O => Sh56_F5MUX_9084
);
Sh56_BXINV : X_BUF
generic map(
LOC => "SLICE_X13Y27",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh56_BXINV_9076
);
Sh48_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y25",
PATHPULSE => 638 ps
)
port map (
I => Sh48_F5MUX_9109,
O => Sh48
);
Sh48_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y25"
)
port map (
IA => N350,
IB => N351,
SEL => Sh48_BXINV_9101,
O => Sh48_F5MUX_9109
);
Sh48_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y25",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh48_BXINV_9101
);
Sh49_XUSED : X_BUF
generic map(
LOC => "SLICE_X14Y24",
PATHPULSE => 638 ps
)
port map (
I => Sh49_F5MUX_9134,
O => Sh49
);
Sh49_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X14Y24"
)
port map (
IA => N372,
IB => N373,
SEL => Sh49_BXINV_9126,
O => Sh49_F5MUX_9134
);
Sh49_BXINV : X_BUF
generic map(
LOC => "SLICE_X14Y24",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh49_BXINV_9126
);
Sh59_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y31",
PATHPULSE => 638 ps
)
port map (
I => Sh59_F5MUX_9159,
O => Sh59
);
Sh59_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y31"
)
port map (
IA => N380,
IB => N381,
SEL => Sh59_BXINV_9151,
O => Sh59_F5MUX_9159
);
Sh59_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y31",
PATHPULSE => 638 ps
)
port map (
I => b_reg(2),
O => Sh59_BXINV_9151
);
N275_XUSED : X_BUF
generic map(
LOC => "SLICE_X3Y17",
PATHPULSE => 638 ps
)
port map (
I => N275_F5MUX_9184,
O => N275
);
N275_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X3Y17"
)
port map (
IA => N448,
IB => N449,
SEL => N275_BXINV_9175,
O => N275_F5MUX_9184
);
N275_BXINV : X_BUF
generic map(
LOC => "SLICE_X3Y17",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd1_4311,
O => N275_BXINV_9175
);
N276_XUSED : X_BUF
generic map(
LOC => "SLICE_X2Y17",
PATHPULSE => 638 ps
)
port map (
I => N276_F5MUX_9209,
O => N276
);
N276_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X2Y17"
)
port map (
IA => N450,
IB => N451,
SEL => N276_BXINV_9200,
O => N276_F5MUX_9209
);
N276_BXINV : X_BUF
generic map(
LOC => "SLICE_X2Y17",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd1_4311,
O => N276_BXINV_9200
);
b_reg_8_DXMUX : X_BUF
generic map(
LOC => "SLICE_X16Y15",
PATHPULSE => 638 ps
)
port map (
I => b_reg_8_F5MUX_9238,
O => b_reg_8_DXMUX_9240
);
b_reg_8_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X16Y15"
)
port map (
IA => N532,
IB => N533,
SEL => b_reg_8_BXINV_9231,
O => b_reg_8_F5MUX_9238
);
b_reg_8_BXINV : X_BUF
generic map(
LOC => "SLICE_X16Y15",
PATHPULSE => 638 ps
)
port map (
I => b_8_XORF_5755,
O => b_reg_8_BXINV_9231
);
b_reg_8_CLKINV : X_BUF
generic map(
LOC => "SLICE_X16Y15",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_8_CLKINV_9222
);
b_reg_9_DXMUX : X_BUF
generic map(
LOC => "SLICE_X16Y14",
PATHPULSE => 638 ps
)
port map (
I => b_reg_9_F5MUX_9274,
O => b_reg_9_DXMUX_9276
);
b_reg_9_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X16Y14"
)
port map (
IA => N530,
IB => N531,
SEL => b_reg_9_BXINV_9267,
O => b_reg_9_F5MUX_9274
);
b_reg_9_BXINV : X_BUF
generic map(
LOC => "SLICE_X16Y14",
PATHPULSE => 638 ps
)
port map (
I => b_8_XORG_5744,
O => b_reg_9_BXINV_9267
);
b_reg_9_CLKINV : X_BUF
generic map(
LOC => "SLICE_X16Y14",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_9_CLKINV_9258
);
N272_XUSED : X_BUF
generic map(
LOC => "SLICE_X3Y13",
PATHPULSE => 638 ps
)
port map (
I => N272_F5MUX_9306,
O => N272
);
N272_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X3Y13"
)
port map (
IA => N444,
IB => N445,
SEL => N272_BXINV_9297,
O => N272_F5MUX_9306
);
N272_BXINV : X_BUF
generic map(
LOC => "SLICE_X3Y13",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd1_4311,
O => N272_BXINV_9297
);
N273_XUSED : X_BUF
generic map(
LOC => "SLICE_X2Y13",
PATHPULSE => 638 ps
)
port map (
I => N273_F5MUX_9331,
O => N273
);
N273_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X2Y13"
)
port map (
IA => N446,
IB => N447,
SEL => N273_BXINV_9322,
O => N273_F5MUX_9331
);
N273_BXINV : X_BUF
generic map(
LOC => "SLICE_X2Y13",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd1_4311,
O => N273_BXINV_9322
);
Sh1_XUSED : X_BUF
generic map(
LOC => "SLICE_X13Y35",
PATHPULSE => 638 ps
)
port map (
I => Sh1_F5MUX_9356,
O => Sh1
);
Sh1_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X13Y35"
)
port map (
IA => N404,
IB => N405,
SEL => Sh1_BXINV_9349,
O => Sh1_F5MUX_9356
);
Sh1_BXINV : X_BUF
generic map(
LOC => "SLICE_X13Y35",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh1_BXINV_9349
);
Sh2_XUSED : X_BUF
generic map(
LOC => "SLICE_X13Y32",
PATHPULSE => 638 ps
)
port map (
I => Sh2_F5MUX_9381,
O => Sh2
);
Sh2_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X13Y32"
)
port map (
IA => Sh211,
IB => Sh210,
SEL => Sh2_BXINV_9374,
O => Sh2_F5MUX_9381
);
Sh2_BXINV : X_BUF
generic map(
LOC => "SLICE_X13Y32",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh2_BXINV_9374
);
Sh5_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y19",
PATHPULSE => 638 ps
)
port map (
I => Sh5_F5MUX_9406,
O => Sh5
);
Sh5_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y19"
)
port map (
IA => N476,
IB => N477,
SEL => Sh5_BXINV_9399,
O => Sh5_F5MUX_9406
);
Sh5_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y19",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh5_BXINV_9399
);
N269_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y8",
PATHPULSE => 638 ps
)
port map (
I => N269_F5MUX_9431,
O => N269
);
N269_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y8"
)
port map (
IA => N440,
IB => N441,
SEL => N269_BXINV_9422,
O => N269_F5MUX_9431
);
N269_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y8",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd1_4311,
O => N269_BXINV_9422
);
N270_XUSED : X_BUF
generic map(
LOC => "SLICE_X9Y3",
PATHPULSE => 638 ps
)
port map (
I => N270_F5MUX_9456,
O => N270
);
N270_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X9Y3"
)
port map (
IA => N442,
IB => N443,
SEL => N270_BXINV_9447,
O => N270_F5MUX_9456
);
N270_BXINV : X_BUF
generic map(
LOC => "SLICE_X9Y3",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd1_4311,
O => N270_BXINV_9447
);
Sh6_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y18",
PATHPULSE => 638 ps
)
port map (
I => Sh6_F5MUX_9481,
O => Sh6
);
Sh6_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y18"
)
port map (
IA => N462,
IB => N463,
SEL => Sh6_BXINV_9474,
O => Sh6_F5MUX_9481
);
Sh6_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y18",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh6_BXINV_9474
);
Sh9_XUSED : X_BUF
generic map(
LOC => "SLICE_X15Y15",
PATHPULSE => 638 ps
)
port map (
I => Sh9_F5MUX_9506,
O => Sh9
);
Sh9_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X15Y15"
)
port map (
IA => N474,
IB => N475,
SEL => Sh9_BXINV_9499,
O => Sh9_F5MUX_9506
);
Sh9_BXINV : X_BUF
generic map(
LOC => "SLICE_X15Y15",
PATHPULSE => 638 ps
)
port map (
I => b_reg(1),
O => Sh9_BXINV_9499
);
b_reg_0_1_DXMUX : X_BUF
generic map(
LOC => "SLICE_X14Y15",
PATHPULSE => 638 ps
)
port map (
I => b_reg_0_1_FXMUX_9537,
O => b_reg_0_1_DXMUX_9538
);
b_reg_0_1_XUSED : X_BUF
generic map(
LOC => "SLICE_X14Y15",
PATHPULSE => 638 ps
)
port map (
I => b_reg_0_1_FXMUX_9537,
O => b_reg_mux0000_0_Q
);
b_reg_0_1_FXMUX : X_BUF
generic map(
LOC => "SLICE_X14Y15",
PATHPULSE => 638 ps
)
port map (
I => b_reg_0_1_F5MUX_9536,
O => b_reg_0_1_FXMUX_9537
);
b_reg_0_1_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X14Y15"
)
port map (
IA => N524,
IB => N525,
SEL => b_reg_0_1_BXINV_9529,
O => b_reg_0_1_F5MUX_9536
);
b_reg_0_1_BXINV : X_BUF
generic map(
LOC => "SLICE_X14Y15",
PATHPULSE => 638 ps
)
port map (
I => b_0_XORF_5589,
O => b_reg_0_1_BXINV_9529
);
b_reg_0_1_CLKINV : X_BUF
generic map(
LOC => "SLICE_X14Y15",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_0_1_CLKINV_9521
);
hex_digit_i_0_DXMUX : X_BUF
generic map(
LOC => "SLICE_X28Y15",
PATHPULSE => 638 ps
)
port map (
I => hex_digit_i_0_F5MUX_9572,
O => hex_digit_i_0_DXMUX_9574
);
hex_digit_i_0_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X28Y15"
)
port map (
IA => Mmux_hex_digit_i_mux0001_4_9562,
IB => Mmux_hex_digit_i_mux0001_3_9570,
SEL => hex_digit_i_0_BXINV_9564,
O => hex_digit_i_0_F5MUX_9572
);
hex_digit_i_0_BXINV : X_BUF
generic map(
LOC => "SLICE_X28Y15",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt(9),
O => hex_digit_i_0_BXINV_9564
);
hex_digit_i_0_CLKINV : X_BUF
generic map(
LOC => "SLICE_X28Y15",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => hex_digit_i_0_CLKINV_9555
);
N266_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y11",
PATHPULSE => 638 ps
)
port map (
I => N266_F5MUX_9604,
O => N266
);
N266_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X12Y11"
)
port map (
IA => N436,
IB => N437,
SEL => N266_BXINV_9595,
O => N266_F5MUX_9604
);
N266_BXINV : X_BUF
generic map(
LOC => "SLICE_X12Y11",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd1_4311,
O => N266_BXINV_9595
);
N267_XUSED : X_BUF
generic map(
LOC => "SLICE_X13Y11",
PATHPULSE => 638 ps
)
port map (
I => N267_F5MUX_9629,
O => N267
);
N267_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X13Y11"
)
port map (
IA => N438,
IB => N439,
SEL => N267_BXINV_9620,
O => N267_F5MUX_9629
);
N267_BXINV : X_BUF
generic map(
LOC => "SLICE_X13Y11",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd1_4311,
O => N267_BXINV_9620
);
i_cnt_3_DXMUX : X_BUF
generic map(
LOC => "SLICE_X19Y14",
PATHPULSE => 638 ps
)
port map (
I => i_cnt_3_F5MUX_9658,
O => i_cnt_3_DXMUX_9660
);
i_cnt_3_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X19Y14"
)
port map (
IA => i_cnt_mux0001_0_561_9649,
IB => i_cnt_mux0001_0_56,
SEL => i_cnt_3_BXINV_9651,
O => i_cnt_3_F5MUX_9658
);
i_cnt_3_BXINV : X_BUF
generic map(
LOC => "SLICE_X19Y14",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd2_4312,
O => i_cnt_3_BXINV_9651
);
i_cnt_3_CLKINV : X_BUF
generic map(
LOC => "SLICE_X19Y14",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => i_cnt_3_CLKINV_9642
);
hex_digit_i_1_DXMUX : X_BUF
generic map(
LOC => "SLICE_X27Y12",
PATHPULSE => 638 ps
)
port map (
I => hex_digit_i_1_F5MUX_9694,
O => hex_digit_i_1_DXMUX_9696
);
hex_digit_i_1_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X27Y12"
)
port map (
IA => Mmux_hex_digit_i_mux0001_41_9684,
IB => Mmux_hex_digit_i_mux0001_31_9692,
SEL => hex_digit_i_1_BXINV_9686,
O => hex_digit_i_1_F5MUX_9694
);
hex_digit_i_1_BXINV : X_BUF
generic map(
LOC => "SLICE_X27Y12",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt(9),
O => hex_digit_i_1_BXINV_9686
);
hex_digit_i_1_CLKINV : X_BUF
generic map(
LOC => "SLICE_X27Y12",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => hex_digit_i_1_CLKINV_9677
);
hex_digit_i_2_DXMUX : X_BUF
generic map(
LOC => "SLICE_X27Y13",
PATHPULSE => 638 ps
)
port map (
I => hex_digit_i_2_F5MUX_9730,
O => hex_digit_i_2_DXMUX_9732
);
hex_digit_i_2_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X27Y13"
)
port map (
IA => Mmux_hex_digit_i_mux0001_42_9720,
IB => Mmux_hex_digit_i_mux0001_32_9728,
SEL => hex_digit_i_2_BXINV_9722,
O => hex_digit_i_2_F5MUX_9730
);
hex_digit_i_2_BXINV : X_BUF
generic map(
LOC => "SLICE_X27Y13",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt(9),
O => hex_digit_i_2_BXINV_9722
);
hex_digit_i_2_CLKINV : X_BUF
generic map(
LOC => "SLICE_X27Y13",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => hex_digit_i_2_CLKINV_9713
);
hex_digit_i_3_DXMUX : X_BUF
generic map(
LOC => "SLICE_X26Y12",
PATHPULSE => 638 ps
)
port map (
I => hex_digit_i_3_F5MUX_9766,
O => hex_digit_i_3_DXMUX_9768
);
hex_digit_i_3_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X26Y12"
)
port map (
IA => Mmux_hex_digit_i_mux0001_43_9756,
IB => Mmux_hex_digit_i_mux0001_33_9764,
SEL => hex_digit_i_3_BXINV_9758,
O => hex_digit_i_3_F5MUX_9766
);
hex_digit_i_3_BXINV : X_BUF
generic map(
LOC => "SLICE_X26Y12",
PATHPULSE => 638 ps
)
port map (
I => LED_flash_cnt(9),
O => hex_digit_i_3_BXINV_9758
);
hex_digit_i_3_CLKINV : X_BUF
generic map(
LOC => "SLICE_X26Y12",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => hex_digit_i_3_CLKINV_9749
);
Sh150_XUSED : X_BUF
generic map(
LOC => "SLICE_X27Y22",
PATHPULSE => 638 ps
)
port map (
I => Sh150,
O => Sh150_0
);
Sh150_YUSED : X_BUF
generic map(
LOC => "SLICE_X27Y22",
PATHPULSE => 638 ps
)
port map (
I => Sh15016_O_pack_1,
O => Sh15016_O
);
Sh143_XUSED : X_BUF
generic map(
LOC => "SLICE_X25Y22",
PATHPULSE => 638 ps
)
port map (
I => Sh143,
O => Sh143_0
);
Sh143_YUSED : X_BUF
generic map(
LOC => "SLICE_X25Y22",
PATHPULSE => 638 ps
)
port map (
I => Sh14316_pack_1,
O => Sh14316_4518
);
Sh144_XUSED : X_BUF
generic map(
LOC => "SLICE_X23Y13",
PATHPULSE => 638 ps
)
port map (
I => Sh144,
O => Sh144_0
);
Sh144_YUSED : X_BUF
generic map(
LOC => "SLICE_X23Y13",
PATHPULSE => 638 ps
)
port map (
I => Sh14416_pack_1,
O => Sh14416_4486
);
Sh154_XUSED : X_BUF
generic map(
LOC => "SLICE_X28Y25",
PATHPULSE => 638 ps
)
port map (
I => Sh154,
O => Sh154_0
);
Sh154_YUSED : X_BUF
generic map(
LOC => "SLICE_X28Y25",
PATHPULSE => 638 ps
)
port map (
I => Sh15416_O_pack_1,
O => Sh15416_O
);
Sh147_XUSED : X_BUF
generic map(
LOC => "SLICE_X25Y16",
PATHPULSE => 638 ps
)
port map (
I => Sh147,
O => Sh147_0
);
Sh147_YUSED : X_BUF
generic map(
LOC => "SLICE_X25Y16",
PATHPULSE => 638 ps
)
port map (
I => Sh14713_pack_1,
O => Sh14713_4500
);
Sh14832 : X_LUT4
generic map(
INIT => X"FE0E",
LOC => "SLICE_X24Y12"
)
port map (
ADR0 => Sh14816_0,
ADR1 => Sh14813_0,
ADR2 => a(2),
ADR3 => Sh1487_4504,
O => Sh148
);
Sh148_XUSED : X_BUF
generic map(
LOC => "SLICE_X24Y12",
PATHPULSE => 638 ps
)
port map (
I => Sh148,
O => Sh148_0
);
Sh148_YUSED : X_BUF
generic map(
LOC => "SLICE_X24Y12",
PATHPULSE => 638 ps
)
port map (
I => Sh1487_pack_1,
O => Sh1487_4504
);
Sh1487 : X_LUT4
generic map(
INIT => X"EE22",
LOC => "SLICE_X24Y12"
)
port map (
ADR0 => Sh112,
ADR1 => a(3),
ADR2 => VCC,
ADR3 => Sh104,
O => Sh1487_pack_1
);
Sh15932 : X_LUT4
generic map(
INIT => X"BBB8",
LOC => "SLICE_X25Y26"
)
port map (
ADR0 => Sh1597,
ADR1 => a(2),
ADR2 => Sh1313,
ADR3 => Sh1310_0,
O => Sh159
);
Sh159_XUSED : X_BUF
generic map(
LOC => "SLICE_X25Y26",
PATHPULSE => 638 ps
)
port map (
I => Sh159,
O => Sh159_0
);
Sh159_YUSED : X_BUF
generic map(
LOC => "SLICE_X25Y26",
PATHPULSE => 638 ps
)
port map (
I => Sh1313_pack_1,
O => Sh1313
);
Sh15916 : X_LUT4
generic map(
INIT => X"3202",
LOC => "SLICE_X25Y26"
)
port map (
ADR0 => Sh1272_0,
ADR1 => a(3),
ADR2 => a(1),
ADR3 => Sh1252_0,
O => Sh1313_pack_1
);
Sh731 : X_LUT4
generic map(
INIT => X"FC0C",
LOC => "SLICE_X15Y21"
)
port map (
ADR0 => VCC,
ADR1 => Sh41,
ADR2 => b_reg(4),
ADR3 => Sh57,
O => Sh73
);
Sh73_YUSED : X_BUF
generic map(
LOC => "SLICE_X15Y21",
PATHPULSE => 638 ps
)
port map (
I => Sh57_pack_1,
O => Sh57
);
Sh5731 : X_LUT4
generic map(
INIT => X"F0CC",
LOC => "SLICE_X15Y21"
)
port map (
ADR0 => VCC,
ADR1 => Sh5720_0,
ADR2 => Sh5320_0,
ADR3 => b_reg(2),
O => Sh57_pack_1
);
Sh741 : X_LUT4
generic map(
INIT => X"F5A0",
LOC => "SLICE_X14Y29"
)
port map (
ADR0 => b_reg(4),
ADR1 => VCC,
ADR2 => Sh58,
ADR3 => Sh42,
O => Sh74
);
Sh74_YUSED : X_BUF
generic map(
LOC => "SLICE_X14Y29",
PATHPULSE => 638 ps
)
port map (
I => Sh58_pack_1,
O => Sh58
);
Sh5831 : X_LUT4
generic map(
INIT => X"EE44",
LOC => "SLICE_X14Y29"
)
port map (
ADR0 => b_reg(2),
ADR1 => Sh5820_0,
ADR2 => VCC,
ADR3 => Sh5420_0,
O => Sh58_pack_1
);
Sh771 : X_LUT4
generic map(
INIT => X"FC0C",
LOC => "SLICE_X15Y23"
)
port map (
ADR0 => VCC,
ADR1 => Sh45,
ADR2 => b_reg(4),
ADR3 => Sh61,
O => Sh77
);
Sh77_YUSED : X_BUF
generic map(
LOC => "SLICE_X15Y23",
PATHPULSE => 638 ps
)
port map (
I => Sh61_pack_1,
O => Sh61
);
Sh6131 : X_LUT4
generic map(
INIT => X"CCAA",
LOC => "SLICE_X15Y23"
)
port map (
ADR0 => Sh337_0,
ADR1 => Sh5720_0,
ADR2 => VCC,
ADR3 => b_reg(2),
O => Sh61_pack_1
);
Sh781 : X_LUT4
generic map(
INIT => X"F5A0",
LOC => "SLICE_X16Y29"
)
port map (
ADR0 => b_reg(4),
ADR1 => VCC,
ADR2 => Sh62,
ADR3 => Sh46,
O => Sh78
);
Sh78_YUSED : X_BUF
generic map(
LOC => "SLICE_X16Y29",
PATHPULSE => 638 ps
)
port map (
I => Sh62_pack_1,
O => Sh62
);
Sh6231 : X_LUT4
generic map(
INIT => X"CACA",
LOC => "SLICE_X16Y29"
)
port map (
ADR0 => Sh347_0,
ADR1 => Sh5820_0,
ADR2 => b_reg(2),
ADR3 => VCC,
O => Sh62_pack_1
);
Sh14731_SW0 : X_LUT4
generic map(
INIT => X"AAAF",
LOC => "SLICE_X25Y17"
)
port map (
ADR0 => a(2),
ADR1 => VCC,
ADR2 => Sh14713_4500,
ADR3 => Sh14716_4501,
O => N249
);
N249_XUSED : X_BUF
generic map(
LOC => "SLICE_X25Y17",
PATHPULSE => 638 ps
)
port map (
I => N249,
O => N249_0
);
N249_YUSED : X_BUF
generic map(
LOC => "SLICE_X25Y17",
PATHPULSE => 638 ps
)
port map (
I => Sh14716_pack_1,
O => Sh14716_4501
);
Sh14716 : X_LUT4
generic map(
INIT => X"3120",
LOC => "SLICE_X25Y17"
)
port map (
ADR0 => a(1),
ADR1 => a(3),
ADR2 => Sh1132_0,
ADR3 => Sh1152_0,
O => Sh14716_pack_1
);
Sh1022 : X_LUT4
generic map(
INIT => X"8BD1",
LOC => "SLICE_X18Y12"
)
port map (
ADR0 => a(6),
ADR1 => N243_0,
ADR2 => a(5),
ADR3 => Mxor_ba_xor_Result_5_1_SW1_O,
O => Sh1022_10084
);
Sh1022_XUSED : X_BUF
generic map(
LOC => "SLICE_X18Y12",
PATHPULSE => 638 ps
)
port map (
I => Sh1022_10084,
O => Sh1022_0
);
Sh1022_YUSED : X_BUF
generic map(
LOC => "SLICE_X18Y12",
PATHPULSE => 638 ps
)
port map (
I => Mxor_ba_xor_Result_5_1_SW1_O_pack_1,
O => Mxor_ba_xor_Result_5_1_SW1_O
);
Mxor_ba_xor_Result_5_1_SW1 : X_LUT4
generic map(
INIT => X"88DD",
LOC => "SLICE_X18Y12"
)
port map (
ADR0 => a(0),
ADR1 => b_reg(5),
ADR2 => VCC,
ADR3 => b_reg(6),
O => Mxor_ba_xor_Result_5_1_SW1_O_pack_1
);
Sh1102 : X_LUT4
generic map(
INIT => X"8BD1",
LOC => "SLICE_X22Y19"
)
port map (
ADR0 => N231_0,
ADR1 => a(14),
ADR2 => Mxor_ba_xor_Result_13_1_SW1_O,
ADR3 => a(13),
O => Sh1102_10108
);
Sh1102_XUSED : X_BUF
generic map(
LOC => "SLICE_X22Y19",
PATHPULSE => 638 ps
)
port map (
I => Sh1102_10108,
O => Sh1102_0
);
Sh1102_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y19",
PATHPULSE => 638 ps
)
port map (
I => Mxor_ba_xor_Result_13_1_SW1_O_pack_1,
O => Mxor_ba_xor_Result_13_1_SW1_O
);
Mxor_ba_xor_Result_13_1_SW1 : X_LUT4
generic map(
INIT => X"F505",
LOC => "SLICE_X22Y19"
)
port map (
ADR0 => b_reg(14),
ADR1 => VCC,
ADR2 => a(0),
ADR3 => b_reg(13),
O => Mxor_ba_xor_Result_13_1_SW1_O_pack_1
);
Sh1032 : X_LUT4
generic map(
INIT => X"D18B",
LOC => "SLICE_X25Y13"
)
port map (
ADR0 => Mxor_ba_xor_Result_7_1_SW1_O,
ADR1 => a(7),
ADR2 => N254_0,
ADR3 => a(6),
O => Sh1032_10132
);
Sh1032_XUSED : X_BUF
generic map(
LOC => "SLICE_X25Y13",
PATHPULSE => 638 ps
)
port map (
I => Sh1032_10132,
O => Sh1032_0
);
Sh1032_YUSED : X_BUF
generic map(
LOC => "SLICE_X25Y13",
PATHPULSE => 638 ps
)
port map (
I => Mxor_ba_xor_Result_7_1_SW1_O_pack_1,
O => Mxor_ba_xor_Result_7_1_SW1_O
);
Mxor_ba_xor_Result_7_1_SW1 : X_LUT4
generic map(
INIT => X"AA0F",
LOC => "SLICE_X25Y13"
)
port map (
ADR0 => b_reg(6),
ADR1 => VCC,
ADR2 => b_reg(7),
ADR3 => a(0),
O => Mxor_ba_xor_Result_7_1_SW1_O_pack_1
);
Sh1112 : X_LUT4
generic map(
INIT => X"D81B",
LOC => "SLICE_X19Y20"
)
port map (
ADR0 => a(14),
ADR1 => N228_0,
ADR2 => Mxor_ba_xor_Result_15_1_SW1_O,
ADR3 => a(15),
O => Sh1112_10156
);
Sh1112_XUSED : X_BUF
generic map(
LOC => "SLICE_X19Y20",
PATHPULSE => 638 ps
)
port map (
I => Sh1112_10156,
O => Sh1112_0
);
Sh1112_YUSED : X_BUF
generic map(
LOC => "SLICE_X19Y20",
PATHPULSE => 638 ps
)
port map (
I => Mxor_ba_xor_Result_15_1_SW1_O_pack_1,
O => Mxor_ba_xor_Result_15_1_SW1_O
);
Mxor_ba_xor_Result_15_1_SW1 : X_LUT4
generic map(
INIT => X"C0CF",
LOC => "SLICE_X19Y20"
)
port map (
ADR0 => VCC,
ADR1 => b_reg(14),
ADR2 => a(0),
ADR3 => b_reg(15),
O => Mxor_ba_xor_Result_15_1_SW1_O_pack_1
);
Sh1062 : X_LUT4
generic map(
INIT => X"C5A3",
LOC => "SLICE_X20Y10"
)
port map (
ADR0 => Mxor_ba_xor_Result_9_1_SW1_O,
ADR1 => N237_0,
ADR2 => a(10),
ADR3 => a(9),
O => Sh1062_10180
);
Sh1062_XUSED : X_BUF
generic map(
LOC => "SLICE_X20Y10",
PATHPULSE => 638 ps
)
port map (
I => Sh1062_10180,
O => Sh1062_0
);
Sh1062_YUSED : X_BUF
generic map(
LOC => "SLICE_X20Y10",
PATHPULSE => 638 ps
)
port map (
I => Mxor_ba_xor_Result_9_1_SW1_O_pack_1,
O => Mxor_ba_xor_Result_9_1_SW1_O
);
Mxor_ba_xor_Result_9_1_SW1 : X_LUT4
generic map(
INIT => X"F055",
LOC => "SLICE_X20Y10"
)
port map (
ADR0 => b_reg(10),
ADR1 => VCC,
ADR2 => b_reg(9),
ADR3 => a(0),
O => Mxor_ba_xor_Result_9_1_SW1_O_pack_1
);
Sh1142 : X_LUT4
generic map(
INIT => X"A3C5",
LOC => "SLICE_X23Y25"
)
port map (
ADR0 => a(18),
ADR1 => a(17),
ADR2 => N217_0,
ADR3 => Mxor_ba_xor_Result_17_1_SW1_O,
O => Sh1142_10204
);
Sh1142_XUSED : X_BUF
generic map(
LOC => "SLICE_X23Y25",
PATHPULSE => 638 ps
)
port map (
I => Sh1142_10204,
O => Sh1142_0
);
Sh1142_YUSED : X_BUF
generic map(
LOC => "SLICE_X23Y25",
PATHPULSE => 638 ps
)
port map (
I => Mxor_ba_xor_Result_17_1_SW1_O_pack_1,
O => Mxor_ba_xor_Result_17_1_SW1_O
);
Mxor_ba_xor_Result_17_1_SW1 : X_LUT4
generic map(
INIT => X"F055",
LOC => "SLICE_X23Y25"
)
port map (
ADR0 => b_reg(18),
ADR1 => VCC,
ADR2 => b_reg(17),
ADR3 => a(0),
O => Mxor_ba_xor_Result_17_1_SW1_O_pack_1
);
Sh1222_XUSED : X_BUF
generic map(
LOC => "SLICE_X22Y28",
PATHPULSE => 638 ps
)
port map (
I => Sh1222_10228,
O => Sh1222_0
);
Sh1222_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y28",
PATHPULSE => 638 ps
)
port map (
I => Mxor_ba_xor_Result_25_1_SW1_O_pack_1,
O => Mxor_ba_xor_Result_25_1_SW1_O
);
Mxor_ba_xor_Result_25_1_SW1 : X_LUT4
generic map(
INIT => X"AF05",
LOC => "SLICE_X22Y28"
)
port map (
ADR0 => a(0),
ADR1 => VCC,
ADR2 => b_reg(26),
ADR3 => b_reg(25),
O => Mxor_ba_xor_Result_25_1_SW1_O_pack_1
);
Sh1072_XUSED : X_BUF
generic map(
LOC => "SLICE_X18Y13",
PATHPULSE => 638 ps
)
port map (
I => Sh1072_10252,
O => Sh1072_0
);
Sh1072_YUSED : X_BUF
generic map(
LOC => "SLICE_X18Y13",
PATHPULSE => 638 ps
)
port map (
I => Mxor_ba_xor_Result_11_1_SW1_O_pack_1,
O => Mxor_ba_xor_Result_11_1_SW1_O
);
Sh1152_XUSED : X_BUF
generic map(
LOC => "SLICE_X22Y24",
PATHPULSE => 638 ps
)
port map (
I => Sh1152_10276,
O => Sh1152_0
);
Sh1152_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y24",
PATHPULSE => 638 ps
)
port map (
I => Mxor_ba_xor_Result_19_1_SW1_O_pack_1,
O => Mxor_ba_xor_Result_19_1_SW1_O
);
Sh1232_XUSED : X_BUF
generic map(
LOC => "SLICE_X22Y31",
PATHPULSE => 638 ps
)
port map (
I => Sh1232_10300,
O => Sh1232_0
);
Sh1232_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y31",
PATHPULSE => 638 ps
)
port map (
I => N200_pack_1,
O => N200
);
Sh1182_XUSED : X_BUF
generic map(
LOC => "SLICE_X18Y33",
PATHPULSE => 638 ps
)
port map (
I => Sh1182_10324,
O => Sh1182_0
);
Sh1182_YUSED : X_BUF
generic map(
LOC => "SLICE_X18Y33",
PATHPULSE => 638 ps
)
port map (
I => Mxor_ba_xor_Result_21_1_SW1_O_pack_1,
O => Mxor_ba_xor_Result_21_1_SW1_O
);
Sh1262_XUSED : X_BUF
generic map(
LOC => "SLICE_X20Y31",
PATHPULSE => 638 ps
)
port map (
I => Sh1262_10348,
O => Sh1262_0
);
Sh1262_YUSED : X_BUF
generic map(
LOC => "SLICE_X20Y31",
PATHPULSE => 638 ps
)
port map (
I => Mxor_ba_xor_Result_29_1_SW1_O_pack_1,
O => Mxor_ba_xor_Result_29_1_SW1_O
);
Sh13016_XUSED : X_BUF
generic map(
LOC => "SLICE_X26Y17",
PATHPULSE => 638 ps
)
port map (
I => Sh13016,
O => Sh13016_0
);
Sh13016_YUSED : X_BUF
generic map(
LOC => "SLICE_X26Y17",
PATHPULSE => 638 ps
)
port map (
I => Sh982_pack_1,
O => Sh982_4493
);
Sh1192_XUSED : X_BUF
generic map(
LOC => "SLICE_X18Y28",
PATHPULSE => 638 ps
)
port map (
I => Sh1192_10396,
O => Sh1192_0
);
Sh1192_YUSED : X_BUF
generic map(
LOC => "SLICE_X18Y28",
PATHPULSE => 638 ps
)
port map (
I => Mxor_ba_xor_Result_23_1_SW1_O_pack_1,
O => Mxor_ba_xor_Result_23_1_SW1_O
);
Sh1272_XUSED : X_BUF
generic map(
LOC => "SLICE_X21Y31",
PATHPULSE => 638 ps
)
port map (
I => Sh1272_10420,
O => Sh1272_0
);
Sh1272_YUSED : X_BUF
generic map(
LOC => "SLICE_X21Y31",
PATHPULSE => 638 ps
)
port map (
I => N197_pack_1,
O => N197
);
Sh161_YUSED : X_BUF
generic map(
LOC => "SLICE_X20Y14",
PATHPULSE => 638 ps
)
port map (
I => Sh129_pack_1,
O => Sh129
);
Sh170_YUSED : X_BUF
generic map(
LOC => "SLICE_X27Y18",
PATHPULSE => 638 ps
)
port map (
I => Sh138_pack_1,
O => Sh138
);
Sh1437_XUSED : X_BUF
generic map(
LOC => "SLICE_X24Y22",
PATHPULSE => 638 ps
)
port map (
I => Sh1437_10492,
O => Sh1437_0
);
Sh1437_YUSED : X_BUF
generic map(
LOC => "SLICE_X24Y22",
PATHPULSE => 638 ps
)
port map (
I => Sh107_pack_1,
O => Sh107
);
Sh171_YUSED : X_BUF
generic map(
LOC => "SLICE_X27Y24",
PATHPULSE => 638 ps
)
port map (
I => Sh155_pack_1,
O => Sh155
);
Sh172_YUSED : X_BUF
generic map(
LOC => "SLICE_X23Y19",
PATHPULSE => 638 ps
)
port map (
I => Sh156_pack_1,
O => Sh156
);
Sh180_YUSED : X_BUF
generic map(
LOC => "SLICE_X23Y21",
PATHPULSE => 638 ps
)
port map (
I => Sh132_pack_1,
O => Sh132
);
Sh165_YUSED : X_BUF
generic map(
LOC => "SLICE_X23Y15",
PATHPULSE => 638 ps
)
port map (
I => Sh149_pack_1,
O => Sh149
);
Sh173_YUSED : X_BUF
generic map(
LOC => "SLICE_X20Y16",
PATHPULSE => 638 ps
)
port map (
I => Sh157_pack_1,
O => Sh157
);
Sh166_YUSED : X_BUF
generic map(
LOC => "SLICE_X26Y15",
PATHPULSE => 638 ps
)
port map (
I => Sh134_pack_1,
O => Sh134
);
Sh174_YUSED : X_BUF
generic map(
LOC => "SLICE_X26Y22",
PATHPULSE => 638 ps
)
port map (
I => Sh158_pack_1,
O => Sh158
);
Sh167_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y21",
PATHPULSE => 638 ps
)
port map (
I => Sh151_pack_1,
O => Sh151
);
Sh168_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y17",
PATHPULSE => 638 ps
)
port map (
I => Sh152_pack_1,
O => Sh152
);
Sh176_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y20",
PATHPULSE => 638 ps
)
port map (
I => Sh128_pack_1,
O => Sh128
);
Sh169_YUSED : X_BUF
generic map(
LOC => "SLICE_X23Y16",
PATHPULSE => 638 ps
)
port map (
I => Sh153_pack_1,
O => Sh153
);
Sh179_YUSED : X_BUF
generic map(
LOC => "SLICE_X25Y19",
PATHPULSE => 638 ps
)
port map (
I => Sh131_pack_1,
O => Sh131
);
b_reg_2_1_DYMUX : X_BUF
generic map(
LOC => "SLICE_X12Y10",
PATHPULSE => 638 ps
)
port map (
I => b_reg_2_1_GYMUX_10799,
O => b_reg_2_1_DYMUX_10800
);
b_reg_2_1_GYMUX : X_BUF
generic map(
LOC => "SLICE_X12Y10",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_2_Q,
O => b_reg_2_1_GYMUX_10799
);
b_reg_2_1_CLKINV : X_BUF
generic map(
LOC => "SLICE_X12Y10",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_2_1_CLKINV_10790
);
b_reg_3_1_DYMUX : X_BUF
generic map(
LOC => "SLICE_X3Y21",
PATHPULSE => 638 ps
)
port map (
I => b_reg_3_1_GYMUX_10823,
O => b_reg_3_1_DYMUX_10824
);
b_reg_3_1_GYMUX : X_BUF
generic map(
LOC => "SLICE_X3Y21",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_3_Q,
O => b_reg_3_1_GYMUX_10823
);
b_reg_3_1_CLKINV : X_BUF
generic map(
LOC => "SLICE_X3Y21",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_3_1_CLKINV_10814
);
b_reg_4_1_DYMUX : X_BUF
generic map(
LOC => "SLICE_X3Y19",
PATHPULSE => 638 ps
)
port map (
I => b_reg_4_1_GYMUX_10847,
O => b_reg_4_1_DYMUX_10848
);
b_reg_4_1_GYMUX : X_BUF
generic map(
LOC => "SLICE_X3Y19",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_4_Q,
O => b_reg_4_1_GYMUX_10847
);
b_reg_4_1_CLKINV : X_BUF
generic map(
LOC => "SLICE_X3Y19",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_4_1_CLKINV_10838
);
AN_1_DXMUX : X_BUF
generic map(
LOC => "SLICE_X30Y14",
PATHPULSE => 638 ps
)
port map (
I => Mrom_AN_mux00011,
O => AN_1_DXMUX_10889
);
AN_1_DYMUX : X_BUF
generic map(
LOC => "SLICE_X30Y14",
PATHPULSE => 638 ps
)
port map (
I => Mrom_AN_mux0001,
O => AN_1_DYMUX_10874
);
AN_1_SRINV : X_BUF
generic map(
LOC => "SLICE_X30Y14",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => AN_1_SRINV_10864
);
AN_1_CLKINV : X_BUF
generic map(
LOC => "SLICE_X30Y14",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => AN_1_CLKINV_10863
);
AN_3_DXMUX : X_BUF
generic map(
LOC => "SLICE_X30Y12",
PATHPULSE => 638 ps
)
port map (
I => Mrom_AN_mux00013,
O => AN_3_DXMUX_10929
);
AN_3_DYMUX : X_BUF
generic map(
LOC => "SLICE_X30Y12",
PATHPULSE => 638 ps
)
port map (
I => Mrom_AN_mux00012,
O => AN_3_DYMUX_10914
);
AN_3_SRINV : X_BUF
generic map(
LOC => "SLICE_X30Y12",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => AN_3_SRINV_10904
);
AN_3_CLKINV : X_BUF
generic map(
LOC => "SLICE_X30Y12",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => AN_3_CLKINV_10903
);
a_reg_1_DXMUX : X_BUF
generic map(
LOC => "SLICE_X13Y33",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(1),
O => a_reg_1_DXMUX_10970
);
a_reg_1_DYMUX : X_BUF
generic map(
LOC => "SLICE_X13Y33",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(0),
O => a_reg_1_DYMUX_10956
);
a_reg_1_SRINV : X_BUF
generic map(
LOC => "SLICE_X13Y33",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => a_reg_1_SRINV_10948
);
a_reg_1_CLKINV : X_BUF
generic map(
LOC => "SLICE_X13Y33",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => a_reg_1_CLKINV_10947
);
a_reg_3_DXMUX : X_BUF
generic map(
LOC => "SLICE_X2Y21",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(3),
O => a_reg_3_DXMUX_11012
);
a_reg_3_DYMUX : X_BUF
generic map(
LOC => "SLICE_X2Y21",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(2),
O => a_reg_3_DYMUX_10998
);
a_reg_3_SRINV : X_BUF
generic map(
LOC => "SLICE_X2Y21",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => a_reg_3_SRINV_10990
);
a_reg_3_CLKINV : X_BUF
generic map(
LOC => "SLICE_X2Y21",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => a_reg_3_CLKINV_10989
);
a_reg_5_DXMUX : X_BUF
generic map(
LOC => "SLICE_X15Y18",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(5),
O => a_reg_5_DXMUX_11054
);
a_reg_5_DYMUX : X_BUF
generic map(
LOC => "SLICE_X15Y18",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(4),
O => a_reg_5_DYMUX_11040
);
a_reg_5_SRINV : X_BUF
generic map(
LOC => "SLICE_X15Y18",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => a_reg_5_SRINV_11032
);
a_reg_5_CLKINV : X_BUF
generic map(
LOC => "SLICE_X15Y18",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => a_reg_5_CLKINV_11031
);
a_reg_7_DXMUX : X_BUF
generic map(
LOC => "SLICE_X17Y15",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(7),
O => a_reg_7_DXMUX_11096
);
a_reg_7_DYMUX : X_BUF
generic map(
LOC => "SLICE_X17Y15",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(6),
O => a_reg_7_DYMUX_11082
);
a_reg_7_SRINV : X_BUF
generic map(
LOC => "SLICE_X17Y15",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => a_reg_7_SRINV_11074
);
a_reg_7_CLKINV : X_BUF
generic map(
LOC => "SLICE_X17Y15",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => a_reg_7_CLKINV_11073
);
a_reg_9_DXMUX : X_BUF
generic map(
LOC => "SLICE_X16Y12",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(9),
O => a_reg_9_DXMUX_11138
);
a_reg_9_DYMUX : X_BUF
generic map(
LOC => "SLICE_X16Y12",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(8),
O => a_reg_9_DYMUX_11124
);
a_reg_9_SRINV : X_BUF
generic map(
LOC => "SLICE_X16Y12",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => a_reg_9_SRINV_11116
);
a_reg_9_CLKINV : X_BUF
generic map(
LOC => "SLICE_X16Y12",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => a_reg_9_CLKINV_11115
);
b_reg_7_DXMUX : X_BUF
generic map(
LOC => "SLICE_X12Y12",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_7_Q,
O => b_reg_7_DXMUX_11180
);
b_reg_7_DYMUX : X_BUF
generic map(
LOC => "SLICE_X12Y12",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_6_Q,
O => b_reg_7_DYMUX_11165
);
b_reg_7_SRINV : X_BUF
generic map(
LOC => "SLICE_X12Y12",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_7_SRINV_11156
);
b_reg_7_CLKINV : X_BUF
generic map(
LOC => "SLICE_X12Y12",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_7_CLKINV_11155
);
i_cnt_1_DXMUX : X_BUF
generic map(
LOC => "SLICE_X12Y32",
PATHPULSE => 638 ps
)
port map (
I => i_cnt_mux0001(2),
O => i_cnt_1_DXMUX_11221
);
i_cnt_1_DYMUX : X_BUF
generic map(
LOC => "SLICE_X12Y32",
PATHPULSE => 638 ps
)
port map (
I => i_cnt_mux0001(3),
O => i_cnt_1_DYMUX_11208
);
i_cnt_1_SRINV : X_BUF
generic map(
LOC => "SLICE_X12Y32",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => i_cnt_1_SRINV_11199
);
i_cnt_1_CLKINV : X_BUF
generic map(
LOC => "SLICE_X12Y32",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => i_cnt_1_CLKINV_11198
);
a_reg_11_DXMUX : X_BUF
generic map(
LOC => "SLICE_X14Y13",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(11),
O => a_reg_11_DXMUX_11263
);
a_reg_11_DYMUX : X_BUF
generic map(
LOC => "SLICE_X14Y13",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(10),
O => a_reg_11_DYMUX_11249
);
a_reg_11_SRINV : X_BUF
generic map(
LOC => "SLICE_X14Y13",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => a_reg_11_SRINV_11241
);
a_reg_11_CLKINV : X_BUF
generic map(
LOC => "SLICE_X14Y13",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => a_reg_11_CLKINV_11240
);
a_reg_mux0000_20_1 : X_LUT4
generic map(
INIT => X"BFB0",
LOC => "SLICE_X16Y32"
)
port map (
ADR0 => a(20),
ADR1 => state_FSM_FFd1_4311,
ADR2 => state_FSM_FFd2_4312,
ADR3 => a_reg(20),
O => a_reg_mux0000(20)
);
a_reg_21_FFY_RSTOR : X_BUF
generic map(
LOC => "SLICE_X16Y32",
PATHPULSE => 638 ps
)
port map (
I => a_reg_21_SRINV_11283,
O => a_reg_21_FFY_RST
);
a_reg_20 : X_FF
generic map(
LOC => "SLICE_X16Y32",
INIT => '0'
)
port map (
I => a_reg_21_DYMUX_11291,
CE => VCC,
CLK => a_reg_21_CLKINV_11282,
SET => GND,
RST => a_reg_21_FFY_RST,
O => a_reg(20)
);
a_reg_mux0000_21_1 : X_LUT4
generic map(
INIT => X"F7C4",
LOC => "SLICE_X16Y32"
)
port map (
ADR0 => state_FSM_FFd1_4311,
ADR1 => state_FSM_FFd2_4312,
ADR2 => a(21),
ADR3 => a_reg(21),
O => a_reg_mux0000(21)
);
a_reg_21_FFX_RSTOR : X_BUF
generic map(
LOC => "SLICE_X16Y32",
PATHPULSE => 638 ps
)
port map (
I => a_reg_21_SRINV_11283,
O => a_reg_21_FFX_RST
);
a_reg_21 : X_FF
generic map(
LOC => "SLICE_X16Y32",
INIT => '0'
)
port map (
I => a_reg_21_DXMUX_11305,
CE => VCC,
CLK => a_reg_21_CLKINV_11282,
SET => GND,
RST => a_reg_21_FFX_RST,
O => a_reg(21)
);
a_reg_21_DXMUX : X_BUF
generic map(
LOC => "SLICE_X16Y32",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(21),
O => a_reg_21_DXMUX_11305
);
a_reg_21_DYMUX : X_BUF
generic map(
LOC => "SLICE_X16Y32",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(20),
O => a_reg_21_DYMUX_11291
);
a_reg_21_SRINV : X_BUF
generic map(
LOC => "SLICE_X16Y32",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => a_reg_21_SRINV_11283
);
a_reg_21_CLKINV : X_BUF
generic map(
LOC => "SLICE_X16Y32",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => a_reg_21_CLKINV_11282
);
a_reg_13_FFY_RSTOR : X_BUF
generic map(
LOC => "SLICE_X16Y16",
PATHPULSE => 638 ps
)
port map (
I => a_reg_13_SRINV_11325,
O => a_reg_13_FFY_RST
);
a_reg_12 : X_FF
generic map(
LOC => "SLICE_X16Y16",
INIT => '0'
)
port map (
I => a_reg_13_DYMUX_11333,
CE => VCC,
CLK => a_reg_13_CLKINV_11324,
SET => GND,
RST => a_reg_13_FFY_RST,
O => a_reg(12)
);
a_reg_mux0000_12_1 : X_LUT4
generic map(
INIT => X"E2EE",
LOC => "SLICE_X16Y16"
)
port map (
ADR0 => a_reg(12),
ADR1 => state_FSM_FFd2_4312,
ADR2 => a(12),
ADR3 => state_FSM_FFd1_4311,
O => a_reg_mux0000(12)
);
a_reg_mux0000_13_1 : X_LUT4
generic map(
INIT => X"8F80",
LOC => "SLICE_X16Y16"
)
port map (
ADR0 => a(13),
ADR1 => state_FSM_FFd1_4311,
ADR2 => state_FSM_FFd2_4312,
ADR3 => a_reg(13),
O => a_reg_mux0000(13)
);
a_reg_13_FFX_RSTOR : X_BUF
generic map(
LOC => "SLICE_X16Y16",
PATHPULSE => 638 ps
)
port map (
I => a_reg_13_SRINV_11325,
O => a_reg_13_FFX_RST
);
a_reg_13 : X_FF
generic map(
LOC => "SLICE_X16Y16",
INIT => '0'
)
port map (
I => a_reg_13_DXMUX_11347,
CE => VCC,
CLK => a_reg_13_CLKINV_11324,
SET => GND,
RST => a_reg_13_FFX_RST,
O => a_reg(13)
);
a_reg_13_DXMUX : X_BUF
generic map(
LOC => "SLICE_X16Y16",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(13),
O => a_reg_13_DXMUX_11347
);
a_reg_13_DYMUX : X_BUF
generic map(
LOC => "SLICE_X16Y16",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(12),
O => a_reg_13_DYMUX_11333
);
a_reg_13_SRINV : X_BUF
generic map(
LOC => "SLICE_X16Y16",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => a_reg_13_SRINV_11325
);
a_reg_13_CLKINV : X_BUF
generic map(
LOC => "SLICE_X16Y16",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => a_reg_13_CLKINV_11324
);
a_reg_31_FFY_RSTOR : X_BUF
generic map(
LOC => "SLICE_X16Y35",
PATHPULSE => 638 ps
)
port map (
I => a_reg_31_SRINV_11367,
O => a_reg_31_FFY_RST
);
a_reg_30 : X_FF
generic map(
LOC => "SLICE_X16Y35",
INIT => '0'
)
port map (
I => a_reg_31_DYMUX_11375,
CE => VCC,
CLK => a_reg_31_CLKINV_11366,
SET => GND,
RST => a_reg_31_FFY_RST,
O => a_reg(30)
);
a_reg_mux0000_30_1 : X_LUT4
generic map(
INIT => X"B830",
LOC => "SLICE_X16Y35"
)
port map (
ADR0 => state_FSM_FFd1_4311,
ADR1 => state_FSM_FFd2_4312,
ADR2 => a_reg(30),
ADR3 => a(30),
O => a_reg_mux0000(30)
);
a_reg_mux0000_31_1 : X_LUT4
generic map(
INIT => X"BF8C",
LOC => "SLICE_X16Y35"
)
port map (
ADR0 => a(31),
ADR1 => state_FSM_FFd2_4312,
ADR2 => state_FSM_FFd1_4311,
ADR3 => a_reg(31),
O => a_reg_mux0000(31)
);
a_reg_31_FFX_RSTOR : X_BUF
generic map(
LOC => "SLICE_X16Y35",
PATHPULSE => 638 ps
)
port map (
I => a_reg_31_SRINV_11367,
O => a_reg_31_FFX_RST
);
a_reg_31 : X_FF
generic map(
LOC => "SLICE_X16Y35",
INIT => '0'
)
port map (
I => a_reg_31_DXMUX_11389,
CE => VCC,
CLK => a_reg_31_CLKINV_11366,
SET => GND,
RST => a_reg_31_FFX_RST,
O => a_reg(31)
);
a_reg_31_DXMUX : X_BUF
generic map(
LOC => "SLICE_X16Y35",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(31),
O => a_reg_31_DXMUX_11389
);
a_reg_31_DYMUX : X_BUF
generic map(
LOC => "SLICE_X16Y35",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(30),
O => a_reg_31_DYMUX_11375
);
a_reg_31_SRINV : X_BUF
generic map(
LOC => "SLICE_X16Y35",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => a_reg_31_SRINV_11367
);
a_reg_31_CLKINV : X_BUF
generic map(
LOC => "SLICE_X16Y35",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => a_reg_31_CLKINV_11366
);
a_reg_23_FFY_RSTOR : X_BUF
generic map(
LOC => "SLICE_X18Y31",
PATHPULSE => 638 ps
)
port map (
I => a_reg_23_SRINV_11409,
O => a_reg_23_FFY_RST
);
a_reg_22 : X_FF
generic map(
LOC => "SLICE_X18Y31",
INIT => '0'
)
port map (
I => a_reg_23_DYMUX_11417,
CE => VCC,
CLK => a_reg_23_CLKINV_11408,
SET => GND,
RST => a_reg_23_FFY_RST,
O => a_reg(22)
);
a_reg_mux0000_22_1 : X_LUT4
generic map(
INIT => X"C0AA",
LOC => "SLICE_X18Y31"
)
port map (
ADR0 => a_reg(22),
ADR1 => a(22),
ADR2 => state_FSM_FFd1_4311,
ADR3 => state_FSM_FFd2_4312,
O => a_reg_mux0000(22)
);
a_reg_mux0000_23_1 : X_LUT4
generic map(
INIT => X"F5CC",
LOC => "SLICE_X18Y31"
)
port map (
ADR0 => state_FSM_FFd1_4311,
ADR1 => a_reg(23),
ADR2 => a(23),
ADR3 => state_FSM_FFd2_4312,
O => a_reg_mux0000(23)
);
a_reg_23_DXMUX : X_BUF
generic map(
LOC => "SLICE_X18Y31",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(23),
O => a_reg_23_DXMUX_11431
);
a_reg_23_DYMUX : X_BUF
generic map(
LOC => "SLICE_X18Y31",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(22),
O => a_reg_23_DYMUX_11417
);
a_reg_23_SRINV : X_BUF
generic map(
LOC => "SLICE_X18Y31",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => a_reg_23_SRINV_11409
);
a_reg_23_CLKINV : X_BUF
generic map(
LOC => "SLICE_X18Y31",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => a_reg_23_CLKINV_11408
);
a_reg_15_DXMUX : X_BUF
generic map(
LOC => "SLICE_X15Y22",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(15),
O => a_reg_15_DXMUX_11473
);
a_reg_15_DYMUX : X_BUF
generic map(
LOC => "SLICE_X15Y22",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(14),
O => a_reg_15_DYMUX_11459
);
a_reg_15_SRINV : X_BUF
generic map(
LOC => "SLICE_X15Y22",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => a_reg_15_SRINV_11451
);
a_reg_15_CLKINV : X_BUF
generic map(
LOC => "SLICE_X15Y22",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => a_reg_15_CLKINV_11450
);
a_reg_mux0000_24_1 : X_LUT4
generic map(
INIT => X"BF8C",
LOC => "SLICE_X17Y33"
)
port map (
ADR0 => a(24),
ADR1 => state_FSM_FFd2_4312,
ADR2 => state_FSM_FFd1_4311,
ADR3 => a_reg(24),
O => a_reg_mux0000(24)
);
a_reg_25_DXMUX : X_BUF
generic map(
LOC => "SLICE_X17Y33",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(25),
O => a_reg_25_DXMUX_11515
);
a_reg_25_DYMUX : X_BUF
generic map(
LOC => "SLICE_X17Y33",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(24),
O => a_reg_25_DYMUX_11501
);
a_reg_25_SRINV : X_BUF
generic map(
LOC => "SLICE_X17Y33",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => a_reg_25_SRINV_11493
);
a_reg_25_CLKINV : X_BUF
generic map(
LOC => "SLICE_X17Y33",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => a_reg_25_CLKINV_11492
);
a_reg_17_DXMUX : X_BUF
generic map(
LOC => "SLICE_X13Y22",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(17),
O => a_reg_17_DXMUX_11557
);
a_reg_17_DYMUX : X_BUF
generic map(
LOC => "SLICE_X13Y22",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(16),
O => a_reg_17_DYMUX_11543
);
a_reg_17_SRINV : X_BUF
generic map(
LOC => "SLICE_X13Y22",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => a_reg_17_SRINV_11535
);
a_reg_17_CLKINV : X_BUF
generic map(
LOC => "SLICE_X13Y22",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => a_reg_17_CLKINV_11534
);
a_reg_27_DXMUX : X_BUF
generic map(
LOC => "SLICE_X18Y30",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(27),
O => a_reg_27_DXMUX_11599
);
a_reg_27_DYMUX : X_BUF
generic map(
LOC => "SLICE_X18Y30",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(26),
O => a_reg_27_DYMUX_11585
);
a_reg_27_SRINV : X_BUF
generic map(
LOC => "SLICE_X18Y30",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => a_reg_27_SRINV_11577
);
a_reg_27_CLKINV : X_BUF
generic map(
LOC => "SLICE_X18Y30",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => a_reg_27_CLKINV_11576
);
a_reg_19_DXMUX : X_BUF
generic map(
LOC => "SLICE_X14Y25",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(19),
O => a_reg_19_DXMUX_11641
);
a_reg_19_DYMUX : X_BUF
generic map(
LOC => "SLICE_X14Y25",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(18),
O => a_reg_19_DYMUX_11627
);
a_reg_19_SRINV : X_BUF
generic map(
LOC => "SLICE_X14Y25",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => a_reg_19_SRINV_11619
);
a_reg_19_CLKINV : X_BUF
generic map(
LOC => "SLICE_X14Y25",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => a_reg_19_CLKINV_11618
);
a_reg_29_DXMUX : X_BUF
generic map(
LOC => "SLICE_X17Y34",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(29),
O => a_reg_29_DXMUX_11683
);
a_reg_29_DYMUX : X_BUF
generic map(
LOC => "SLICE_X17Y34",
PATHPULSE => 638 ps
)
port map (
I => a_reg_mux0000(28),
O => a_reg_29_DYMUX_11669
);
a_reg_29_SRINV : X_BUF
generic map(
LOC => "SLICE_X17Y34",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => a_reg_29_SRINV_11661
);
a_reg_29_CLKINV : X_BUF
generic map(
LOC => "SLICE_X17Y34",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => a_reg_29_CLKINV_11660
);
b_reg_11_DYMUX : X_BUF
generic map(
LOC => "SLICE_X15Y11",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_11_Q,
O => b_reg_11_DYMUX_11706
);
b_reg_11_CLKINV : X_BUF
generic map(
LOC => "SLICE_X15Y11",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_11_CLKINV_11696
);
b_reg_21_DXMUX : X_BUF
generic map(
LOC => "SLICE_X19Y23",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_21_Q,
O => b_reg_21_DXMUX_11748
);
b_reg_21_DYMUX : X_BUF
generic map(
LOC => "SLICE_X19Y23",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_20_Q,
O => b_reg_21_DYMUX_11734
);
b_reg_21_SRINV : X_BUF
generic map(
LOC => "SLICE_X19Y23",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_21_SRINV_11726
);
b_reg_21_CLKINV : X_BUF
generic map(
LOC => "SLICE_X19Y23",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_21_CLKINV_11725
);
b_reg_13_DXMUX : X_BUF
generic map(
LOC => "SLICE_X18Y19",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_13_Q,
O => b_reg_13_DXMUX_11790
);
b_reg_13_DYMUX : X_BUF
generic map(
LOC => "SLICE_X18Y19",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_12_Q,
O => b_reg_13_DYMUX_11776
);
b_reg_13_SRINV : X_BUF
generic map(
LOC => "SLICE_X18Y19",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_13_SRINV_11768
);
b_reg_13_CLKINV : X_BUF
generic map(
LOC => "SLICE_X18Y19",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_13_CLKINV_11767
);
b_reg_31_DXMUX : X_BUF
generic map(
LOC => "SLICE_X19Y26",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_31_Q,
O => b_reg_31_DXMUX_11832
);
b_reg_31_DYMUX : X_BUF
generic map(
LOC => "SLICE_X19Y26",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_30_Q,
O => b_reg_31_DYMUX_11818
);
b_reg_31_SRINV : X_BUF
generic map(
LOC => "SLICE_X19Y26",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_31_SRINV_11810
);
b_reg_31_CLKINV : X_BUF
generic map(
LOC => "SLICE_X19Y26",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_31_CLKINV_11809
);
b_reg_23_DXMUX : X_BUF
generic map(
LOC => "SLICE_X19Y22",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_23_Q,
O => b_reg_23_DXMUX_11874
);
b_reg_23_DYMUX : X_BUF
generic map(
LOC => "SLICE_X19Y22",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_22_Q,
O => b_reg_23_DYMUX_11860
);
b_reg_23_SRINV : X_BUF
generic map(
LOC => "SLICE_X19Y22",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_23_SRINV_11852
);
b_reg_23_CLKINV : X_BUF
generic map(
LOC => "SLICE_X19Y22",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_23_CLKINV_11851
);
b_reg_15_DXMUX : X_BUF
generic map(
LOC => "SLICE_X19Y18",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_15_Q,
O => b_reg_15_DXMUX_11916
);
b_reg_15_DYMUX : X_BUF
generic map(
LOC => "SLICE_X19Y18",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_14_Q,
O => b_reg_15_DYMUX_11902
);
b_reg_15_SRINV : X_BUF
generic map(
LOC => "SLICE_X19Y18",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_15_SRINV_11894
);
b_reg_15_CLKINV : X_BUF
generic map(
LOC => "SLICE_X19Y18",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_15_CLKINV_11893
);
b_reg_25_DXMUX : X_BUF
generic map(
LOC => "SLICE_X19Y24",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_25_Q,
O => b_reg_25_DXMUX_11958
);
b_reg_25_DYMUX : X_BUF
generic map(
LOC => "SLICE_X19Y24",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_24_Q,
O => b_reg_25_DYMUX_11944
);
b_reg_25_SRINV : X_BUF
generic map(
LOC => "SLICE_X19Y24",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_25_SRINV_11936
);
b_reg_25_CLKINV : X_BUF
generic map(
LOC => "SLICE_X19Y24",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_25_CLKINV_11935
);
b_reg_17_DXMUX : X_BUF
generic map(
LOC => "SLICE_X18Y21",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_17_Q,
O => b_reg_17_DXMUX_12000
);
b_reg_17_DYMUX : X_BUF
generic map(
LOC => "SLICE_X18Y21",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_16_Q,
O => b_reg_17_DYMUX_11986
);
b_reg_17_SRINV : X_BUF
generic map(
LOC => "SLICE_X18Y21",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_17_SRINV_11978
);
b_reg_17_CLKINV : X_BUF
generic map(
LOC => "SLICE_X18Y21",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_17_CLKINV_11977
);
b_reg_27_DXMUX : X_BUF
generic map(
LOC => "SLICE_X19Y25",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_27_Q,
O => b_reg_27_DXMUX_12042
);
b_reg_27_DYMUX : X_BUF
generic map(
LOC => "SLICE_X19Y25",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_26_Q,
O => b_reg_27_DYMUX_12028
);
b_reg_27_SRINV : X_BUF
generic map(
LOC => "SLICE_X19Y25",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_27_SRINV_12020
);
b_reg_27_CLKINV : X_BUF
generic map(
LOC => "SLICE_X19Y25",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_27_CLKINV_12019
);
b_reg_19_DXMUX : X_BUF
generic map(
LOC => "SLICE_X18Y20",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_19_Q,
O => b_reg_19_DXMUX_12084
);
b_reg_19_DYMUX : X_BUF
generic map(
LOC => "SLICE_X18Y20",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_18_Q,
O => b_reg_19_DYMUX_12070
);
b_reg_19_SRINV : X_BUF
generic map(
LOC => "SLICE_X18Y20",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_19_SRINV_12062
);
b_reg_19_CLKINV : X_BUF
generic map(
LOC => "SLICE_X18Y20",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_19_CLKINV_12061
);
b_reg_29_DXMUX : X_BUF
generic map(
LOC => "SLICE_X19Y27",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_29_Q,
O => b_reg_29_DXMUX_12126
);
b_reg_29_DYMUX : X_BUF
generic map(
LOC => "SLICE_X19Y27",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_28_Q,
O => b_reg_29_DYMUX_12112
);
b_reg_29_SRINV : X_BUF
generic map(
LOC => "SLICE_X19Y27",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_29_SRINV_12104
);
b_reg_29_CLKINV : X_BUF
generic map(
LOC => "SLICE_X19Y27",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_29_CLKINV_12103
);
Sh1287_XUSED : X_BUF
generic map(
LOC => "SLICE_X24Y19",
PATHPULSE => 638 ps
)
port map (
I => Sh1287_12154,
O => Sh1287_0
);
Sh1287_YUSED : X_BUF
generic map(
LOC => "SLICE_X24Y19",
PATHPULSE => 638 ps
)
port map (
I => Sh13220_12146,
O => Sh13220_0
);
Sh110_XUSED : X_BUF
generic map(
LOC => "SLICE_X26Y20",
PATHPULSE => 638 ps
)
port map (
I => Sh110,
O => Sh110_0
);
Sh110_YUSED : X_BUF
generic map(
LOC => "SLICE_X26Y20",
PATHPULSE => 638 ps
)
port map (
I => Sh15013_12170,
O => Sh15013_0
);
Sh103_XUSED : X_BUF
generic map(
LOC => "SLICE_X24Y21",
PATHPULSE => 638 ps
)
port map (
I => Sh103,
O => Sh103_0
);
Sh103_YUSED : X_BUF
generic map(
LOC => "SLICE_X24Y21",
PATHPULSE => 638 ps
)
port map (
I => Sh14313_12194,
O => Sh14313_0
);
Sh15816_XUSED : X_BUF
generic map(
LOC => "SLICE_X22Y22",
PATHPULSE => 638 ps
)
port map (
I => Sh15816_12226,
O => Sh15816_0
);
Sh15816_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y22",
PATHPULSE => 638 ps
)
port map (
I => Sh15113_12219,
O => Sh15113_0
);
Sh1310_XUSED : X_BUF
generic map(
LOC => "SLICE_X24Y23",
PATHPULSE => 638 ps
)
port map (
I => Sh1310,
O => Sh1310_0
);
Sh1310_YUSED : X_BUF
generic map(
LOC => "SLICE_X24Y23",
PATHPULSE => 638 ps
)
port map (
I => Sh15116_12243,
O => Sh15116_0
);
Sh14813_XUSED : X_BUF
generic map(
LOC => "SLICE_X24Y13",
PATHPULSE => 638 ps
)
port map (
I => Sh14813_12274,
O => Sh14813_0
);
Sh14813_YUSED : X_BUF
generic map(
LOC => "SLICE_X24Y13",
PATHPULSE => 638 ps
)
port map (
I => Sh14412_12265,
O => Sh14412_0
);
Sh12816_XUSED : X_BUF
generic map(
LOC => "SLICE_X22Y13",
PATHPULSE => 638 ps
)
port map (
I => Sh12816,
O => Sh12816_0
);
Sh12816_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y13",
PATHPULSE => 638 ps
)
port map (
I => Sh14413_12289,
O => Sh14413_0
);
Sh14616_XUSED : X_BUF
generic map(
LOC => "SLICE_X28Y23",
PATHPULSE => 638 ps
)
port map (
I => Sh14616_12322,
O => Sh14616_0
);
Sh14616_YUSED : X_BUF
generic map(
LOC => "SLICE_X28Y23",
PATHPULSE => 638 ps
)
port map (
I => Sh15413_12315,
O => Sh15413_0
);
Sh106_XUSED : X_BUF
generic map(
LOC => "SLICE_X27Y17",
PATHPULSE => 638 ps
)
port map (
I => Sh106,
O => Sh106_0
);
Sh106_YUSED : X_BUF
generic map(
LOC => "SLICE_X27Y17",
PATHPULSE => 638 ps
)
port map (
I => Sh14613_12338,
O => Sh14613_0
);
Sh15516_XUSED : X_BUF
generic map(
LOC => "SLICE_X26Y25",
PATHPULSE => 638 ps
)
port map (
I => Sh15516_12370,
O => Sh15516_0
);
Sh15516_YUSED : X_BUF
generic map(
LOC => "SLICE_X26Y25",
PATHPULSE => 638 ps
)
port map (
I => Sh15513_12363,
O => Sh15513_0
);
Sh1527_XUSED : X_BUF
generic map(
LOC => "SLICE_X24Y17",
PATHPULSE => 638 ps
)
port map (
I => Sh1527_12394,
O => Sh1527_0
);
Sh1527_YUSED : X_BUF
generic map(
LOC => "SLICE_X24Y17",
PATHPULSE => 638 ps
)
port map (
I => Sh14816_12386,
O => Sh14816_0
);
Sh13013_XUSED : X_BUF
generic map(
LOC => "SLICE_X29Y22",
PATHPULSE => 638 ps
)
port map (
I => Sh13013,
O => Sh13013_0
);
Sh13013_YUSED : X_BUF
generic map(
LOC => "SLICE_X29Y22",
PATHPULSE => 638 ps
)
port map (
I => Sh15813_12411,
O => Sh15813_0
);
b_reg_0_2_DYMUX : X_BUF
generic map(
LOC => "SLICE_X15Y17",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_0_Q,
O => b_reg_0_2_DYMUX_12428
);
b_reg_0_2_CLKINV : X_BUF
generic map(
LOC => "SLICE_X15Y17",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_0_2_CLKINV_12425
);
b_reg_0_3_DYMUX : X_BUF
generic map(
LOC => "SLICE_X14Y16",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_0_Q,
O => b_reg_0_3_DYMUX_12442
);
b_reg_0_3_CLKINV : X_BUF
generic map(
LOC => "SLICE_X14Y16",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_0_3_CLKINV_12439
);
ab_xor_3_XUSED : X_BUF
generic map(
LOC => "SLICE_X3Y20",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_3_Q,
O => ab_xor_3_0
);
ab_xor_4_XUSED : X_BUF
generic map(
LOC => "SLICE_X13Y19",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_4_Q,
O => ab_xor_4_0
);
N247_XUSED : X_BUF
generic map(
LOC => "SLICE_X14Y19",
PATHPULSE => 638 ps
)
port map (
I => N247,
O => N247_0
);
N247_YUSED : X_BUF
generic map(
LOC => "SLICE_X14Y19",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_5_Q,
O => ab_xor_5_0
);
Mxor_ba_xor_Result_7_1_SW3 : X_LUT4
generic map(
INIT => X"C0F3",
LOC => "SLICE_X16Y13"
)
port map (
ADR0 => VCC,
ADR1 => a(0),
ADR2 => b_reg(7),
ADR3 => b_reg(8),
O => N261
);
N261_XUSED : X_BUF
generic map(
LOC => "SLICE_X16Y13",
PATHPULSE => 638 ps
)
port map (
I => N261,
O => N261_0
);
N261_YUSED : X_BUF
generic map(
LOC => "SLICE_X16Y13",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_7_Q,
O => ab_xor_7_0
);
Mxor_ba_xor_Result_7_1_SW2 : X_LUT4
generic map(
INIT => X"1D1D",
LOC => "SLICE_X15Y13"
)
port map (
ADR0 => b_reg(8),
ADR1 => a(0),
ADR2 => b_reg(7),
ADR3 => VCC,
O => N260
);
N260_XUSED : X_BUF
generic map(
LOC => "SLICE_X15Y13",
PATHPULSE => 638 ps
)
port map (
I => N260,
O => N260_0
);
N260_YUSED : X_BUF
generic map(
LOC => "SLICE_X15Y13",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_8_Q,
O => ab_xor_8_0
);
Mxor_ab_xor_Result_8_1 : X_LUT4
generic map(
INIT => X"5A5A",
LOC => "SLICE_X15Y13"
)
port map (
ADR0 => b_reg(8),
ADR1 => VCC,
ADR2 => a_reg(8),
ADR3 => VCC,
O => ab_xor_8_Q
);
Mxor_ba_xor_Result_8_1_SW1 : X_LUT4
generic map(
INIT => X"88BB",
LOC => "SLICE_X15Y12"
)
port map (
ADR0 => b_reg(8),
ADR1 => a(0),
ADR2 => VCC,
ADR3 => b_reg(9),
O => N241
);
N241_XUSED : X_BUF
generic map(
LOC => "SLICE_X15Y12",
PATHPULSE => 638 ps
)
port map (
I => N241,
O => N241_0
);
N241_YUSED : X_BUF
generic map(
LOC => "SLICE_X15Y12",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_9_Q,
O => ab_xor_9_0
);
Mxor_ab_xor_Result_9_1 : X_LUT4
generic map(
INIT => X"33CC",
LOC => "SLICE_X15Y12"
)
port map (
ADR0 => VCC,
ADR1 => a_reg(9),
ADR2 => VCC,
ADR3 => b_reg(9),
O => ab_xor_9_Q
);
Sh102_f51 : X_LUT4
generic map(
INIT => X"F3C0",
LOC => "SLICE_X26Y19"
)
port map (
ADR0 => VCC,
ADR1 => a(1),
ADR2 => Sh1002_0,
ADR3 => Sh1022_0,
O => Sh102
);
Sh102_XUSED : X_BUF
generic map(
LOC => "SLICE_X26Y19",
PATHPULSE => 638 ps
)
port map (
I => Sh102,
O => Sh102_0
);
Sh102_YUSED : X_BUF
generic map(
LOC => "SLICE_X26Y19",
PATHPULSE => 638 ps
)
port map (
I => Sh98,
O => Sh98_0
);
Sh98_f51 : X_LUT4
generic map(
INIT => X"AACC",
LOC => "SLICE_X26Y19"
)
port map (
ADR0 => Sh962_0,
ADR1 => Sh982_4493,
ADR2 => VCC,
ADR3 => a(1),
O => Sh98
);
Madd_a_lut_22_SW0 : X_LUT4
generic map(
INIT => X"1946",
LOC => "SLICE_X18Y27"
)
port map (
ADR0 => i_cnt(0),
ADR1 => i_cnt(3),
ADR2 => i_cnt(2),
ADR3 => i_cnt(1),
O => N520
);
N520_XUSED : X_BUF
generic map(
LOC => "SLICE_X18Y27",
PATHPULSE => 638 ps
)
port map (
I => N520,
O => N520_0
);
N520_YUSED : X_BUF
generic map(
LOC => "SLICE_X18Y27",
PATHPULSE => 638 ps
)
port map (
I => N286,
O => N286_0
);
Sh711_SW0 : X_LUT4
generic map(
INIT => X"EEF0",
LOC => "SLICE_X18Y27"
)
port map (
ADR0 => i_cnt(0),
ADR1 => i_cnt(3),
ADR2 => i_cnt(2),
ADR3 => i_cnt(1),
O => N286
);
Sh671_SW0 : X_LUT4
generic map(
INIT => X"F30C",
LOC => "SLICE_X20Y18"
)
port map (
ADR0 => VCC,
ADR1 => i_cnt(0),
ADR2 => i_cnt(2),
ADR3 => i_cnt(3),
O => N224
);
Madd_b_lut_15_SW0 : X_LUT4
generic map(
INIT => X"4343",
LOC => "SLICE_X20Y18"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(0),
ADR2 => i_cnt(2),
ADR3 => VCC,
O => N522
);
N522_XUSED : X_BUF
generic map(
LOC => "SLICE_X20Y18",
PATHPULSE => 638 ps
)
port map (
I => N522,
O => N522_0
);
N522_YUSED : X_BUF
generic map(
LOC => "SLICE_X20Y18",
PATHPULSE => 638 ps
)
port map (
I => N224,
O => N224_0
);
Sh781_SW0 : X_LUT4
generic map(
INIT => X"4341",
LOC => "SLICE_X12Y30"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(1),
ADR2 => i_cnt(3),
ADR3 => i_cnt(0),
O => N226
);
Madd_a_lut_28_SW0 : X_LUT4
generic map(
INIT => X"4637",
LOC => "SLICE_X12Y30"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(1),
ADR2 => i_cnt(3),
ADR3 => i_cnt(0),
O => N518
);
N518_XUSED : X_BUF
generic map(
LOC => "SLICE_X12Y30",
PATHPULSE => 638 ps
)
port map (
I => N518,
O => N518_0
);
N518_YUSED : X_BUF
generic map(
LOC => "SLICE_X12Y30",
PATHPULSE => 638 ps
)
port map (
I => N226,
O => N226_0
);
Mxor_ab_xor_Result_11_1 : X_LUT4
generic map(
INIT => X"33CC",
LOC => "SLICE_X14Y12"
)
port map (
ADR0 => VCC,
ADR1 => b_reg(11),
ADR2 => VCC,
ADR3 => a_reg(11),
O => ab_xor_11_Q
);
N258_XUSED : X_BUF
generic map(
LOC => "SLICE_X14Y12",
PATHPULSE => 638 ps
)
port map (
I => N258,
O => N258_0
);
N258_YUSED : X_BUF
generic map(
LOC => "SLICE_X14Y12",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_11_Q,
O => ab_xor_11_0
);
N257_XUSED : X_BUF
generic map(
LOC => "SLICE_X15Y14",
PATHPULSE => 638 ps
)
port map (
I => N257,
O => N257_0
);
N257_YUSED : X_BUF
generic map(
LOC => "SLICE_X15Y14",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_12_Q,
O => ab_xor_12_0
);
Sh1181_SW1 : X_LUT4
generic map(
INIT => X"BB11",
LOC => "SLICE_X22Y25"
)
port map (
ADR0 => a(0),
ADR1 => b_reg(20),
ADR2 => VCC,
ADR3 => b_reg(19),
O => N188
);
N188_XUSED : X_BUF
generic map(
LOC => "SLICE_X22Y25",
PATHPULSE => 638 ps
)
port map (
I => N188,
O => N188_0
);
N188_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y25",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_20_Q,
O => ab_xor_20_0
);
N235_XUSED : X_BUF
generic map(
LOC => "SLICE_X15Y16",
PATHPULSE => 638 ps
)
port map (
I => N235,
O => N235_0
);
N235_YUSED : X_BUF
generic map(
LOC => "SLICE_X15Y16",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_13_Q,
O => ab_xor_13_0
);
Mxor_ab_xor_Result_13_1 : X_LUT4
generic map(
INIT => X"6666",
LOC => "SLICE_X15Y16"
)
port map (
ADR0 => a_reg(13),
ADR1 => b_reg(13),
ADR2 => VCC,
ADR3 => VCC,
O => ab_xor_13_Q
);
N214_XUSED : X_BUF
generic map(
LOC => "SLICE_X17Y32",
PATHPULSE => 638 ps
)
port map (
I => N214,
O => N214_0
);
N214_YUSED : X_BUF
generic map(
LOC => "SLICE_X17Y32",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_21_Q,
O => ab_xor_21_0
);
N228_XUSED : X_BUF
generic map(
LOC => "SLICE_X15Y20",
PATHPULSE => 638 ps
)
port map (
I => N228,
O => N228_0
);
N228_YUSED : X_BUF
generic map(
LOC => "SLICE_X15Y20",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_15_Q,
O => ab_xor_15_0
);
N202_XUSED : X_BUF
generic map(
LOC => "SLICE_X19Y31",
PATHPULSE => 638 ps
)
port map (
I => N202,
O => N202_0
);
N202_YUSED : X_BUF
generic map(
LOC => "SLICE_X19Y31",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_23_Q,
O => ab_xor_23_0
);
N196_XUSED : X_BUF
generic map(
LOC => "SLICE_X17Y35",
PATHPULSE => 638 ps
)
port map (
I => N196,
O => N196_0
);
N196_YUSED : X_BUF
generic map(
LOC => "SLICE_X17Y35",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_31_Q,
O => ab_xor_31_0
);
N194_XUSED : X_BUF
generic map(
LOC => "SLICE_X14Y20",
PATHPULSE => 638 ps
)
port map (
I => N194,
O => N194_0
);
N194_YUSED : X_BUF
generic map(
LOC => "SLICE_X14Y20",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_16_Q,
O => ab_xor_16_0
);
N182_XUSED : X_BUF
generic map(
LOC => "SLICE_X18Y32",
PATHPULSE => 638 ps
)
port map (
I => N182,
O => N182_0
);
N182_YUSED : X_BUF
generic map(
LOC => "SLICE_X18Y32",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_24_Q,
O => ab_xor_24_0
);
N217_XUSED : X_BUF
generic map(
LOC => "SLICE_X13Y23",
PATHPULSE => 638 ps
)
port map (
I => N217,
O => N217_0
);
N217_YUSED : X_BUF
generic map(
LOC => "SLICE_X13Y23",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_17_Q,
O => ab_xor_17_0
);
N211_XUSED : X_BUF
generic map(
LOC => "SLICE_X16Y33",
PATHPULSE => 638 ps
)
port map (
I => N211,
O => N211_0
);
N211_YUSED : X_BUF
generic map(
LOC => "SLICE_X16Y33",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_25_Q,
O => ab_xor_25_0
);
N205_XUSED : X_BUF
generic map(
LOC => "SLICE_X18Y25",
PATHPULSE => 638 ps
)
port map (
I => N205,
O => N205_0
);
N205_YUSED : X_BUF
generic map(
LOC => "SLICE_X18Y25",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_19_Q,
O => ab_xor_19_0
);
N199_XUSED : X_BUF
generic map(
LOC => "SLICE_X19Y30",
PATHPULSE => 638 ps
)
port map (
I => N199,
O => N199_0
);
N199_YUSED : X_BUF
generic map(
LOC => "SLICE_X19Y30",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_27_Q,
O => ab_xor_27_0
);
N176_XUSED : X_BUF
generic map(
LOC => "SLICE_X18Y34",
PATHPULSE => 638 ps
)
port map (
I => N176,
O => N176_0
);
N176_YUSED : X_BUF
generic map(
LOC => "SLICE_X18Y34",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_28_Q,
O => ab_xor_28_0
);
N208_XUSED : X_BUF
generic map(
LOC => "SLICE_X16Y34",
PATHPULSE => 638 ps
)
port map (
I => N208,
O => N208_0
);
N208_YUSED : X_BUF
generic map(
LOC => "SLICE_X16Y34",
PATHPULSE => 638 ps
)
port map (
I => ab_xor_29_Q,
O => ab_xor_29_0
);
N191_XUSED : X_BUF
generic map(
LOC => "SLICE_X25Y21",
PATHPULSE => 638 ps
)
port map (
I => N191,
O => N191_0
);
N191_YUSED : X_BUF
generic map(
LOC => "SLICE_X25Y21",
PATHPULSE => 638 ps
)
port map (
I => N193,
O => N193_0
);
N179_XUSED : X_BUF
generic map(
LOC => "SLICE_X20Y28",
PATHPULSE => 638 ps
)
port map (
I => N179,
O => N179_0
);
N179_YUSED : X_BUF
generic map(
LOC => "SLICE_X20Y28",
PATHPULSE => 638 ps
)
port map (
I => N181,
O => N181_0
);
N289_XUSED : X_BUF
generic map(
LOC => "SLICE_X27Y21",
PATHPULSE => 638 ps
)
port map (
I => N289,
O => N289_0
);
N289_YUSED : X_BUF
generic map(
LOC => "SLICE_X27Y21",
PATHPULSE => 638 ps
)
port map (
I => N190,
O => N190_0
);
N288_XUSED : X_BUF
generic map(
LOC => "SLICE_X23Y26",
PATHPULSE => 638 ps
)
port map (
I => N288,
O => N288_0
);
N288_YUSED : X_BUF
generic map(
LOC => "SLICE_X23Y26",
PATHPULSE => 638 ps
)
port map (
I => N178,
O => N178_0
);
N185_XUSED : X_BUF
generic map(
LOC => "SLICE_X24Y25",
PATHPULSE => 638 ps
)
port map (
I => N185,
O => N185_0
);
N185_YUSED : X_BUF
generic map(
LOC => "SLICE_X24Y25",
PATHPULSE => 638 ps
)
port map (
I => N187,
O => N187_0
);
N173_XUSED : X_BUF
generic map(
LOC => "SLICE_X22Y30",
PATHPULSE => 638 ps
)
port map (
I => N173,
O => N173_0
);
N173_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y30",
PATHPULSE => 638 ps
)
port map (
I => N175,
O => N175_0
);
N264_XUSED : X_BUF
generic map(
LOC => "SLICE_X24Y26",
PATHPULSE => 638 ps
)
port map (
I => N264,
O => N264_0
);
N264_YUSED : X_BUF
generic map(
LOC => "SLICE_X24Y26",
PATHPULSE => 638 ps
)
port map (
I => N184,
O => N184_0
);
N263_XUSED : X_BUF
generic map(
LOC => "SLICE_X22Y27",
PATHPULSE => 638 ps
)
port map (
I => N263,
O => N263_0
);
N263_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y27",
PATHPULSE => 638 ps
)
port map (
I => N172,
O => N172_0
);
Sh80_YUSED : X_BUF
generic map(
LOC => "SLICE_X15Y24",
PATHPULSE => 638 ps
)
port map (
I => Sh64,
O => Sh64_0
);
Sh5320_XUSED : X_BUF
generic map(
LOC => "SLICE_X14Y21",
PATHPULSE => 638 ps
)
port map (
I => Sh5320,
O => Sh5320_0
);
Sh5320_YUSED : X_BUF
generic map(
LOC => "SLICE_X14Y21",
PATHPULSE => 638 ps
)
port map (
I => Sh5720,
O => Sh5720_0
);
Sh5420_XUSED : X_BUF
generic map(
LOC => "SLICE_X13Y29",
PATHPULSE => 638 ps
)
port map (
I => Sh5420,
O => Sh5420_0
);
Sh5420_YUSED : X_BUF
generic map(
LOC => "SLICE_X13Y29",
PATHPULSE => 638 ps
)
port map (
I => Sh5820,
O => Sh5820_0
);
N246_XUSED : X_BUF
generic map(
LOC => "SLICE_X16Y21",
PATHPULSE => 638 ps
)
port map (
I => N246,
O => N246_0
);
Sh84_XUSED : X_BUF
generic map(
LOC => "SLICE_X14Y18",
PATHPULSE => 638 ps
)
port map (
I => Sh84,
O => Sh84_0
);
N254_XUSED : X_BUF
generic map(
LOC => "SLICE_X25Y14",
PATHPULSE => 638 ps
)
port map (
I => N254,
O => N254_0
);
N254_YUSED : X_BUF
generic map(
LOC => "SLICE_X25Y14",
PATHPULSE => 638 ps
)
port map (
I => Sh991_13638,
O => Sh991_0
);
Sh99_XUSED : X_BUF
generic map(
LOC => "SLICE_X24Y18",
PATHPULSE => 638 ps
)
port map (
I => Sh99,
O => Sh99_0
);
Sh99_YUSED : X_BUF
generic map(
LOC => "SLICE_X24Y18",
PATHPULSE => 638 ps
)
port map (
I => Sh1011_pack_1,
O => Sh1011
);
b_reg_mux0000_2_13_XUSED : X_BUF
generic map(
LOC => "SLICE_X9Y2",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_2_13_13694,
O => b_reg_mux0000_2_13_0
);
b_reg_mux0000_2_13_YUSED : X_BUF
generic map(
LOC => "SLICE_X9Y2",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_2_5_13686,
O => b_reg_mux0000_2_5_0
);
b_reg_1_DXMUX : X_BUF
generic map(
LOC => "SLICE_X13Y15",
PATHPULSE => 638 ps
)
port map (
I => b_reg_1_F5MUX_13734,
O => b_reg_1_DXMUX_13736
);
b_reg_1_F5MUX : X_MUX2
generic map(
LOC => "SLICE_X13Y15"
)
port map (
IA => N498,
IB => N499,
SEL => b_reg_1_BXINV_13726,
O => b_reg_1_F5MUX_13734
);
b_reg_1_BXINV : X_BUF
generic map(
LOC => "SLICE_X13Y15",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd1_4311,
O => b_reg_1_BXINV_13726
);
b_reg_1_DYMUX : X_BUF
generic map(
LOC => "SLICE_X13Y15",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_0_Q,
O => b_reg_1_DYMUX_13719
);
b_reg_1_SRINV : X_BUF
generic map(
LOC => "SLICE_X13Y15",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_1_SRINV_13711
);
b_reg_1_CLKINV : X_BUF
generic map(
LOC => "SLICE_X13Y15",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_1_CLKINV_13710
);
b_reg_3_DXMUX : X_BUF
generic map(
LOC => "SLICE_X3Y18",
PATHPULSE => 638 ps
)
port map (
I => b_reg_3_1_GYMUX_10823,
O => b_reg_3_DXMUX_13760
);
b_reg_3_DYMUX : X_BUF
generic map(
LOC => "SLICE_X3Y18",
PATHPULSE => 638 ps
)
port map (
I => b_reg_2_1_GYMUX_10799,
O => b_reg_3_DYMUX_13752
);
b_reg_3_SRINV : X_BUF
generic map(
LOC => "SLICE_X3Y18",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_3_SRINV_13750
);
b_reg_3_CLKINV : X_BUF
generic map(
LOC => "SLICE_X3Y18",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_3_CLKINV_13749
);
b_reg_4_DXMUX : X_BUF
generic map(
LOC => "SLICE_X2Y16",
PATHPULSE => 638 ps
)
port map (
I => b_reg_4_1_GYMUX_10847,
O => b_reg_4_DXMUX_13793
);
b_reg_4_DYMUX : X_BUF
generic map(
LOC => "SLICE_X2Y16",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_5_Q,
O => b_reg_4_DYMUX_13785
);
b_reg_4_SRINV : X_BUF
generic map(
LOC => "SLICE_X2Y16",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_4_SRINV_13776
);
b_reg_4_CLKINV : X_BUF
generic map(
LOC => "SLICE_X2Y16",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => b_reg_4_CLKINV_13775
);
b_reg_mux0000_4_12_XUSED : X_BUF
generic map(
LOC => "SLICE_X0Y20",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_4_12_13821,
O => b_reg_mux0000_4_12_0
);
b_reg_mux0000_4_12_YUSED : X_BUF
generic map(
LOC => "SLICE_X0Y20",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_4_3_13813,
O => b_reg_mux0000_4_3_0
);
b_reg_mux0000_6_12_XUSED : X_BUF
generic map(
LOC => "SLICE_X2Y12",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_6_12_13845,
O => b_reg_mux0000_6_12_0
);
b_reg_mux0000_6_12_YUSED : X_BUF
generic map(
LOC => "SLICE_X2Y12",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_6_3_13837,
O => b_reg_mux0000_6_3_0
);
Mrom_b_rom000024 : X_LUT4
generic map(
INIT => X"427A",
LOC => "SLICE_X20Y22"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(0),
ADR2 => i_cnt(3),
ADR3 => i_cnt(1),
O => Mrom_b_rom000024_13869
);
Mrom_b_rom000024_XUSED : X_BUF
generic map(
LOC => "SLICE_X20Y22",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom000024_13869,
O => Mrom_b_rom000024_0
);
Mrom_b_rom000024_YUSED : X_BUF
generic map(
LOC => "SLICE_X20Y22",
PATHPULSE => 638 ps
)
port map (
I => N27,
O => N27_0
);
Mrom_a_rom00002321 : X_LUT4
generic map(
INIT => X"0800",
LOC => "SLICE_X20Y22"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(0),
ADR2 => i_cnt(3),
ADR3 => i_cnt(1),
O => N27
);
Mrom_b_rom00002921 : X_LUT4
generic map(
INIT => X"EEFF",
LOC => "SLICE_X20Y17"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(0),
ADR2 => VCC,
ADR3 => i_cnt(1),
O => N111
);
N111_XUSED : X_BUF
generic map(
LOC => "SLICE_X20Y17",
PATHPULSE => 638 ps
)
port map (
I => N111,
O => N111_0
);
N111_YUSED : X_BUF
generic map(
LOC => "SLICE_X20Y17",
PATHPULSE => 638 ps
)
port map (
I => N12,
O => N12_0
);
Mrom_a_rom00001611 : X_LUT4
generic map(
INIT => X"0011",
LOC => "SLICE_X20Y17"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(0),
ADR2 => VCC,
ADR3 => i_cnt(1),
O => N12
);
Mrom_b_rom00002311 : X_LUT4
generic map(
INIT => X"0A00",
LOC => "SLICE_X21Y10"
)
port map (
ADR0 => i_cnt(2),
ADR1 => VCC,
ADR2 => i_cnt(3),
ADR3 => i_cnt(1),
O => N20
);
N20_XUSED : X_BUF
generic map(
LOC => "SLICE_X21Y10",
PATHPULSE => 638 ps
)
port map (
I => N20,
O => N20_0
);
N20_YUSED : X_BUF
generic map(
LOC => "SLICE_X21Y10",
PATHPULSE => 638 ps
)
port map (
I => N17,
O => N17_0
);
Mrom_a_rom00001811 : X_LUT4
generic map(
INIT => X"5000",
LOC => "SLICE_X21Y10"
)
port map (
ADR0 => i_cnt(2),
ADR1 => VCC,
ADR2 => i_cnt(3),
ADR3 => i_cnt(1),
O => N17
);
Mrom_b_rom00005 : X_LUT4
generic map(
INIT => X"1261",
LOC => "SLICE_X18Y15"
)
port map (
ADR0 => i_cnt(1),
ADR1 => i_cnt(2),
ADR2 => i_cnt(0),
ADR3 => i_cnt(3),
O => Mrom_b_rom00005_13941
);
Mrom_b_rom00005_XUSED : X_BUF
generic map(
LOC => "SLICE_X18Y15",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom00005_13941,
O => Mrom_b_rom00005_0
);
Mrom_b_rom00005_YUSED : X_BUF
generic map(
LOC => "SLICE_X18Y15",
PATHPULSE => 638 ps
)
port map (
I => N222,
O => N222_0
);
Madd_a_lut_12_SW0 : X_LUT4
generic map(
INIT => X"501B",
LOC => "SLICE_X18Y15"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(2),
ADR2 => i_cnt(1),
ADR3 => i_cnt(0),
O => N222
);
i_cnt_mux0001_0_25 : X_LUT4
generic map(
INIT => X"8000",
LOC => "SLICE_X19Y13"
)
port map (
ADR0 => i_cnt(0),
ADR1 => state_FSM_FFd2_4312,
ADR2 => i_cnt(1),
ADR3 => i_cnt_mux0001_0_22_4123,
O => i_cnt_mux0001_0_25_13965
);
i_cnt_mux0001_0_25_XUSED : X_BUF
generic map(
LOC => "SLICE_X19Y13",
PATHPULSE => 638 ps
)
port map (
I => i_cnt_mux0001_0_25_13965,
O => i_cnt_mux0001_0_25_0
);
i_cnt_mux0001_0_25_YUSED : X_BUF
generic map(
LOC => "SLICE_X19Y13",
PATHPULSE => 638 ps
)
port map (
I => i_cnt_mux0001_0_22_pack_1,
O => i_cnt_mux0001_0_22_4123
);
i_cnt_mux0001_0_22 : X_LUT4
generic map(
INIT => X"3030",
LOC => "SLICE_X19Y13"
)
port map (
ADR0 => VCC,
ADR1 => i_cnt(3),
ADR2 => i_cnt(2),
ADR3 => VCC,
O => i_cnt_mux0001_0_22_pack_1
);
Sh1567 : X_LUT4
generic map(
INIT => X"CFC0",
LOC => "SLICE_X23Y20"
)
port map (
ADR0 => VCC,
ADR1 => Sh112,
ADR2 => a(3),
ADR3 => Sh120,
O => Sh1567_13989
);
Sh1567_XUSED : X_BUF
generic map(
LOC => "SLICE_X23Y20",
PATHPULSE => 638 ps
)
port map (
I => Sh1567_13989,
O => Sh1567_0
);
Sh1567_YUSED : X_BUF
generic map(
LOC => "SLICE_X23Y20",
PATHPULSE => 638 ps
)
port map (
I => Sh12813,
O => Sh12813_0
);
Sh1320 : X_LUT4
generic map(
INIT => X"F000",
LOC => "SLICE_X23Y20"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => a(3),
ADR3 => Sh120,
O => Sh12813
);
Sh1577 : X_LUT4
generic map(
INIT => X"CACA",
LOC => "SLICE_X22Y14"
)
port map (
ADR0 => Sh121,
ADR1 => Sh113,
ADR2 => a(3),
ADR3 => VCC,
O => Sh1577_14013
);
Sh1577_XUSED : X_BUF
generic map(
LOC => "SLICE_X22Y14",
PATHPULSE => 638 ps
)
port map (
I => Sh1577_14013,
O => Sh1577_0
);
Sh1577_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y14",
PATHPULSE => 638 ps
)
port map (
I => Sh12913,
O => Sh12913_0
);
Sh1330 : X_LUT4
generic map(
INIT => X"A0A0",
LOC => "SLICE_X22Y14"
)
port map (
ADR0 => Sh121,
ADR1 => VCC,
ADR2 => a(3),
ADR3 => VCC,
O => Sh12913
);
Sh1297_XUSED : X_BUF
generic map(
LOC => "SLICE_X22Y15",
PATHPULSE => 638 ps
)
port map (
I => Sh1297_14037,
O => Sh1297_0
);
Sh1297_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y15",
PATHPULSE => 638 ps
)
port map (
I => Sh12916,
O => Sh12916_0
);
Sh1333 : X_LUT4
generic map(
INIT => X"0F00",
LOC => "SLICE_X22Y15"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => a(3),
ADR3 => Sh97,
O => Sh12916
);
Sh1497_XUSED : X_BUF
generic map(
LOC => "SLICE_X24Y14",
PATHPULSE => 638 ps
)
port map (
I => Sh1497_14061,
O => Sh1497_0
);
Sh1497_YUSED : X_BUF
generic map(
LOC => "SLICE_X24Y14",
PATHPULSE => 638 ps
)
port map (
I => Sh1537_14053,
O => Sh1537_0
);
Sh186_YUSED : X_BUF
generic map(
LOC => "SLICE_X23Y18",
PATHPULSE => 638 ps
)
port map (
I => Sh185,
O => Sh185_0
);
Sh347_XUSED : X_BUF
generic map(
LOC => "SLICE_X15Y28",
PATHPULSE => 638 ps
)
port map (
I => Sh347,
O => Sh347_0
);
Sh347_YUSED : X_BUF
generic map(
LOC => "SLICE_X15Y28",
PATHPULSE => 638 ps
)
port map (
I => Sh337,
O => Sh337_0
);
Madd_b_pre_cy_4_XUSED : X_BUF
generic map(
LOC => "SLICE_X3Y15",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_pre_cy_4_Q,
O => Madd_b_pre_cy_4_0
);
Madd_b_pre_cy_4_YUSED : X_BUF
generic map(
LOC => "SLICE_X3Y15",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_pre_cy_2_pack_1,
O => Madd_b_pre_cy_2_Q
);
b_reg_mux0000_10_10_XUSED : X_BUF
generic map(
LOC => "SLICE_X2Y14",
PATHPULSE => 638 ps
)
port map (
I => b_reg_mux0000_10_10,
O => b_reg_mux0000_10_10_0
);
b_reg_mux0000_10_10_YUSED : X_BUF
generic map(
LOC => "SLICE_X2Y14",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_pre_cy_6_pack_1,
O => Madd_b_pre_cy_6_Q
);
N14_XUSED : X_BUF
generic map(
LOC => "SLICE_X18Y14",
PATHPULSE => 638 ps
)
port map (
I => N14,
O => N14_0
);
N14_YUSED : X_BUF
generic map(
LOC => "SLICE_X18Y14",
PATHPULSE => 638 ps
)
port map (
I => N514,
O => N514_0
);
i_cnt_2_DXMUX : X_BUF
generic map(
LOC => "SLICE_X19Y28",
PATHPULSE => 638 ps
)
port map (
I => i_cnt_mux0001(1),
O => i_cnt_2_DXMUX_14404
);
i_cnt_2_YUSED : X_BUF
generic map(
LOC => "SLICE_X19Y28",
PATHPULSE => 638 ps
)
port map (
I => N516_pack_3,
O => N516
);
i_cnt_2_CLKINV : X_BUF
generic map(
LOC => "SLICE_X19Y28",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => i_cnt_2_CLKINV_14388
);
Mrom_b_rom000012_XUSED : X_BUF
generic map(
LOC => "SLICE_X18Y18",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom000012_14432,
O => Mrom_b_rom000012_0
);
Mrom_b_rom000012_YUSED : X_BUF
generic map(
LOC => "SLICE_X18Y18",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom000010,
O => Mrom_a_rom000010_0
);
Mrom_b_rom000020_XUSED : X_BUF
generic map(
LOC => "SLICE_X19Y21",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom000020_14456,
O => Mrom_b_rom000020_0
);
Mrom_b_rom000020_YUSED : X_BUF
generic map(
LOC => "SLICE_X19Y21",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom000011_14449,
O => Mrom_a_rom000011_0
);
Mrom_b_rom00008_XUSED : X_BUF
generic map(
LOC => "SLICE_X16Y19",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom00008_14480,
O => Mrom_b_rom00008_0
);
Mrom_b_rom00008_YUSED : X_BUF
generic map(
LOC => "SLICE_X16Y19",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom000021,
O => Mrom_a_rom000021_0
);
Mrom_b_rom000013_XUSED : X_BUF
generic map(
LOC => "SLICE_X19Y29",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom000013_14504,
O => Mrom_b_rom000013_0
);
Mrom_b_rom000013_YUSED : X_BUF
generic map(
LOC => "SLICE_X19Y29",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom000030,
O => Mrom_a_rom000030_0
);
Mrom_b_rom000031_XUSED : X_BUF
generic map(
LOC => "SLICE_X21Y29",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom000031,
O => Mrom_b_rom000031_0
);
Mrom_b_rom000031_YUSED : X_BUF
generic map(
LOC => "SLICE_X21Y29",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom000031,
O => Mrom_a_rom000031_0
);
Mrom_b_rom000023_XUSED : X_BUF
generic map(
LOC => "SLICE_X20Y25",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom000023,
O => Mrom_b_rom000023_0
);
Mrom_b_rom000023_YUSED : X_BUF
generic map(
LOC => "SLICE_X20Y25",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom000025,
O => Mrom_a_rom000025_0
);
Mrom_b_rom000017_XUSED : X_BUF
generic map(
LOC => "SLICE_X20Y29",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom000017_14576,
O => Mrom_b_rom000017_0
);
Mrom_b_rom000017_YUSED : X_BUF
generic map(
LOC => "SLICE_X20Y29",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom000026,
O => Mrom_a_rom000026_0
);
Mrom_b_rom00007_XUSED : X_BUF
generic map(
LOC => "SLICE_X17Y14",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom00007,
O => Mrom_b_rom00007_0
);
Mrom_b_rom00007_YUSED : X_BUF
generic map(
LOC => "SLICE_X17Y14",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom000019,
O => Mrom_a_rom000019_0
);
Mrom_b_rom000030_XUSED : X_BUF
generic map(
LOC => "SLICE_X20Y27",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom000030,
O => Mrom_b_rom000030_0
);
Mrom_b_rom000030_YUSED : X_BUF
generic map(
LOC => "SLICE_X20Y27",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom000027,
O => Mrom_a_rom000027_0
);
N237_XUSED : X_BUF
generic map(
LOC => "SLICE_X18Y10",
PATHPULSE => 638 ps
)
port map (
I => N237,
O => N237_0
);
N237_YUSED : X_BUF
generic map(
LOC => "SLICE_X18Y10",
PATHPULSE => 638 ps
)
port map (
I => N251,
O => N251_0
);
Mrom_b_rom000028_XUSED : X_BUF
generic map(
LOC => "SLICE_X20Y23",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom000028,
O => Mrom_b_rom000028_0
);
Mrom_b_rom000028_YUSED : X_BUF
generic map(
LOC => "SLICE_X20Y23",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom000011_14665,
O => Mrom_b_rom000011_0
);
N231_XUSED : X_BUF
generic map(
LOC => "SLICE_X23Y14",
PATHPULSE => 638 ps
)
port map (
I => N231,
O => N231_0
);
N231_YUSED : X_BUF
generic map(
LOC => "SLICE_X23Y14",
PATHPULSE => 638 ps
)
port map (
I => N234,
O => N234_0
);
Mrom_b_rom000026_XUSED : X_BUF
generic map(
LOC => "SLICE_X22Y23",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom000026,
O => Mrom_b_rom000026_0
);
Mrom_b_rom000026_YUSED : X_BUF
generic map(
LOC => "SLICE_X22Y23",
PATHPULSE => 638 ps
)
port map (
I => N77,
O => N77_0
);
N33_XUSED : X_BUF
generic map(
LOC => "SLICE_X20Y15",
PATHPULSE => 638 ps
)
port map (
I => N33,
O => N33_0
);
N33_YUSED : X_BUF
generic map(
LOC => "SLICE_X20Y15",
PATHPULSE => 638 ps
)
port map (
I => N34,
O => N34_0
);
Mrom_b_rom000022_XUSED : X_BUF
generic map(
LOC => "SLICE_X19Y16",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom000022,
O => Mrom_b_rom000022_0
);
Mrom_b_rom000022_YUSED : X_BUF
generic map(
LOC => "SLICE_X19Y16",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom00001,
O => Mrom_a_rom00001_0
);
Mrom_b_rom000016_XUSED : X_BUF
generic map(
LOC => "SLICE_X18Y17",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom000016,
O => Mrom_b_rom000016_0
);
Mrom_b_rom000016_YUSED : X_BUF
generic map(
LOC => "SLICE_X18Y17",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom0000,
O => Mrom_a_rom0000_0
);
Mrom_b_rom000010_XUSED : X_BUF
generic map(
LOC => "SLICE_X18Y16",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom000010,
O => Mrom_b_rom000010_0
);
Mrom_b_rom000010_YUSED : X_BUF
generic map(
LOC => "SLICE_X18Y16",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom000013_14821,
O => Mrom_a_rom000013_0
);
Mrom_b_rom00006_XUSED : X_BUF
generic map(
LOC => "SLICE_X18Y23",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom00006,
O => Mrom_b_rom00006_0
);
Mrom_b_rom00006_YUSED : X_BUF
generic map(
LOC => "SLICE_X18Y23",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom000023_14845,
O => Mrom_a_rom000023_0
);
Mrom_b_rom00009_XUSED : X_BUF
generic map(
LOC => "SLICE_X19Y17",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom00009_14876,
O => Mrom_b_rom00009_0
);
Mrom_b_rom00009_YUSED : X_BUF
generic map(
LOC => "SLICE_X19Y17",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom000015_14869,
O => Mrom_a_rom000015_0
);
Mrom_b_rom000021_XUSED : X_BUF
generic map(
LOC => "SLICE_X18Y29",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom000021,
O => Mrom_b_rom000021_0
);
Mrom_b_rom000021_YUSED : X_BUF
generic map(
LOC => "SLICE_X18Y29",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom000024_14893,
O => Mrom_a_rom000024_0
);
Mrom_b_rom000014_XUSED : X_BUF
generic map(
LOC => "SLICE_X20Y20",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom000014_14924,
O => Mrom_b_rom000014_0
);
Mrom_b_rom000014_YUSED : X_BUF
generic map(
LOC => "SLICE_X20Y20",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom000016_14917,
O => Mrom_a_rom000016_0
);
Mrom_b_rom00001_XUSED : X_BUF
generic map(
LOC => "SLICE_X20Y19",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom00001,
O => Mrom_b_rom00001_0
);
Mrom_b_rom00001_YUSED : X_BUF
generic map(
LOC => "SLICE_X20Y19",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom000017_14941,
O => Mrom_a_rom000017_0
);
Mrom_a_rom000029_XUSED : X_BUF
generic map(
LOC => "SLICE_X16Y30",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom000029_14972,
O => Mrom_a_rom000029_0
);
Mrom_a_rom000029_YUSED : X_BUF
generic map(
LOC => "SLICE_X16Y30",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom000018_14965,
O => Mrom_a_rom000018_0
);
Mrom_b_rom000029_XUSED : X_BUF
generic map(
LOC => "SLICE_X18Y24",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom000029_14996,
O => Mrom_b_rom000029_0
);
Mrom_b_rom000029_YUSED : X_BUF
generic map(
LOC => "SLICE_X18Y24",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom00006,
O => Mrom_a_rom00006_0
);
Mrom_a_rom00009_XUSED : X_BUF
generic map(
LOC => "SLICE_X16Y20",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom00009_15020,
O => Mrom_a_rom00009_0
);
Mrom_a_rom00009_YUSED : X_BUF
generic map(
LOC => "SLICE_X16Y20",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom00008,
O => Mrom_a_rom00008_0
);
Mrom_a_rom00005_XUSED : X_BUF
generic map(
LOC => "SLICE_X19Y19",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom00005_15044,
O => Mrom_a_rom00005_0
);
Mrom_a_rom00005_YUSED : X_BUF
generic map(
LOC => "SLICE_X19Y19",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom000019,
O => Mrom_b_rom000019_0
);
Mrom_a_rom00002_XUSED : X_BUF
generic map(
LOC => "SLICE_X18Y22",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom00002_15068,
O => Mrom_a_rom00002_0
);
Mrom_a_rom00002_YUSED : X_BUF
generic map(
LOC => "SLICE_X18Y22",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom000027,
O => Mrom_b_rom000027_0
);
state_FSM_FFd2_DXMUX : X_BUF
generic map(
LOC => "SLICE_X15Y10",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd2_In,
O => state_FSM_FFd2_DXMUX_15109
);
state_FSM_FFd2_DYMUX : X_BUF
generic map(
LOC => "SLICE_X15Y10",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd2_4312,
O => state_FSM_FFd2_DYMUX_15095
);
state_FSM_FFd2_YUSED : X_BUF
generic map(
LOC => "SLICE_X15Y10",
PATHPULSE => 638 ps
)
port map (
I => state_cmp_eq0000_pack_4,
O => state_cmp_eq0000
);
state_FSM_FFd2_SRINV : X_BUF
generic map(
LOC => "SLICE_X15Y10",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => state_FSM_FFd2_SRINV_15086
);
state_FSM_FFd2_CLKINV : X_BUF
generic map(
LOC => "SLICE_X15Y10",
PATHPULSE => 638 ps
)
port map (
I => clk_25_BUFGP,
O => state_FSM_FFd2_CLKINV_15085
);
Mrom_b_rom0000_XUSED : X_BUF
generic map(
LOC => "SLICE_X19Y15",
PATHPULSE => 638 ps
)
port map (
I => Mrom_b_rom0000,
O => Mrom_b_rom0000_0
);
Mrom_b_rom0000_YUSED : X_BUF
generic map(
LOC => "SLICE_X19Y15",
PATHPULSE => 638 ps
)
port map (
I => Mrom_a_rom00004_15130,
O => Mrom_a_rom00004_0
);
N240_XUSED : X_BUF
generic map(
LOC => "SLICE_X19Y12",
PATHPULSE => 638 ps
)
port map (
I => N240,
O => N240_0
);
N240_YUSED : X_BUF
generic map(
LOC => "SLICE_X19Y12",
PATHPULSE => 638 ps
)
port map (
I => N243,
O => N243_0
);
Madd_a_lut_6_Q : X_LUT4
generic map(
INIT => X"665A",
LOC => "SLICE_X17Y19"
)
port map (
ADR0 => Mrom_a_rom00006_0,
ADR1 => Sh54,
ADR2 => Sh38,
ADR3 => b_reg(4),
O => Madd_a_lut(6)
);
Madd_b_lut_8_Q : X_LUT4
generic map(
INIT => X"1DE2",
LOC => "SLICE_X21Y16"
)
port map (
ADR0 => Sh136,
ADR1 => a(4),
ADR2 => Sh152,
ADR3 => Mrom_b_rom00008_0,
O => Madd_b_lut(8)
);
Sh13120_G : X_LUT4
generic map(
INIT => X"F3C0",
LOC => "SLICE_X26Y18"
)
port map (
ADR0 => VCC,
ADR1 => a(1),
ADR2 => Sh1212_0,
ADR3 => Sh1232_0,
O => N403
);
Sh13120_F : X_LUT4
generic map(
INIT => X"F0CC",
LOC => "SLICE_X26Y18"
)
port map (
ADR0 => VCC,
ADR1 => Sh1011,
ADR2 => Sh991_0,
ADR3 => a(1),
O => N402
);
Sh13_f5_G : X_LUT4
generic map(
INIT => X"5ACC",
LOC => "SLICE_X14Y17"
)
port map (
ADR0 => b_reg(10),
ADR1 => ab_xor_11_0,
ADR2 => a_reg(10),
ADR3 => b_reg_0_2_4323,
O => N495
);
Sh10_f5_G : X_LUT4
generic map(
INIT => X"A3AC",
LOC => "SLICE_X12Y13"
)
port map (
ADR0 => ab_xor_7_0,
ADR1 => a_reg(8),
ADR2 => b_reg_0_3_4316,
ADR3 => b_reg(8),
O => N471
);
Sh10_f5_F : X_LUT4
generic map(
INIT => X"B1E4",
LOC => "SLICE_X12Y13"
)
port map (
ADR0 => b_reg_0_3_4316,
ADR1 => b_reg(10),
ADR2 => ab_xor_9_0,
ADR3 => a_reg(10),
O => N470
);
Sh13_f5_F : X_LUT4
generic map(
INIT => X"AA3C",
LOC => "SLICE_X14Y17"
)
port map (
ADR0 => ab_xor_12_0,
ADR1 => a_reg(13),
ADR2 => b_reg(13),
ADR3 => b_reg_0_2_4323,
O => N494
);
Sh14_f5_F : X_LUT4
generic map(
INIT => X"CC5A",
LOC => "SLICE_X12Y16"
)
port map (
ADR0 => a_reg(14),
ADR1 => ab_xor_13_0,
ADR2 => b_reg(14),
ADR3 => b_reg_0_3_4316,
O => N486
);
Sh1641_G : X_LUT4
generic map(
INIT => X"BBB8",
LOC => "SLICE_X25Y12"
)
port map (
ADR0 => Sh1487_4504,
ADR1 => a(2),
ADR2 => Sh14813_0,
ADR3 => Sh14816_0,
O => N313
);
Sh1641_F : X_LUT4
generic map(
INIT => X"FCAA",
LOC => "SLICE_X25Y12"
)
port map (
ADR0 => Sh13220_0,
ADR1 => Sh12816_0,
ADR2 => Sh12813_0,
ADR3 => a(2),
O => N312
);
Sh1631_G : X_LUT4
generic map(
INIT => X"F0FE",
LOC => "SLICE_X24Y16"
)
port map (
ADR0 => Sh14716_4501,
ADR1 => Sh14713_4500,
ADR2 => Sh14712,
ADR3 => a(2),
O => N311
);
Sh1631_F : X_LUT4
generic map(
INIT => X"FCB8",
LOC => "SLICE_X24Y16"
)
port map (
ADR0 => Sh1313,
ADR1 => a(2),
ADR2 => Sh13120,
ADR3 => Sh1310_0,
O => N310
);
Sh3231_G : X_LUT4
generic map(
INIT => X"F5A0",
LOC => "SLICE_X13Y26"
)
port map (
ADR0 => b_reg(3),
ADR1 => VCC,
ADR2 => Sh20,
ADR3 => Sh28,
O => N353
);
Sh3231_F : X_LUT4
generic map(
INIT => X"E4E4",
LOC => "SLICE_X13Y26"
)
port map (
ADR0 => b_reg(3),
ADR1 => Sh,
ADR2 => Sh24,
ADR3 => VCC,
O => N352
);
Sh4031_G : X_LUT4
generic map(
INIT => X"B8B8",
LOC => "SLICE_X12Y24"
)
port map (
ADR0 => Sh28,
ADR1 => b_reg(3),
ADR2 => Sh4,
ADR3 => VCC,
O => N369
);
Sh4031_F : X_LUT4
generic map(
INIT => X"EE22",
LOC => "SLICE_X12Y24"
)
port map (
ADR0 => Sh8,
ADR1 => b_reg(3),
ADR2 => VCC,
ADR3 => Sh,
O => N368
);
Sh1621_G : X_LUT4
generic map(
INIT => X"DDDC",
LOC => "SLICE_X27Y15"
)
port map (
ADR0 => a(2),
ADR1 => Sh14612,
ADR2 => Sh14613_0,
ADR3 => Sh14616_0,
O => N317
);
Sh1621_F : X_LUT4
generic map(
INIT => X"FE0E",
LOC => "SLICE_X27Y15"
)
port map (
ADR0 => Sh13016_0,
ADR1 => Sh13013_0,
ADR2 => a(2),
ADR3 => Sh1307,
O => N316
);
Sh1517_G : X_LUT4
generic map(
INIT => X"E2E2",
LOC => "SLICE_X23Y17"
)
port map (
ADR0 => Sh1072_0,
ADR1 => a(1),
ADR2 => Sh1052_0,
ADR3 => VCC,
O => N433
);
Sh1517_F : X_LUT4
generic map(
INIT => X"DD88",
LOC => "SLICE_X23Y17"
)
port map (
ADR0 => a(1),
ADR1 => Sh1132_0,
ADR2 => VCC,
ADR3 => Sh1152_0,
O => N432
);
Sh1587_G : X_LUT4
generic map(
INIT => X"FC30",
LOC => "SLICE_X28Y22"
)
port map (
ADR0 => VCC,
ADR1 => a(1),
ADR2 => Sh1142_0,
ADR3 => Sh1122_0,
O => N427
);
Sh1751_G : X_LUT4
generic map(
INIT => X"FE32",
LOC => "SLICE_X25Y23"
)
port map (
ADR0 => Sh1310_0,
ADR1 => a(2),
ADR2 => Sh1313,
ADR3 => Sh1597,
O => N321
);
Sh1751_F : X_LUT4
generic map(
INIT => X"FE54",
LOC => "SLICE_X25Y23"
)
port map (
ADR0 => a(2),
ADR1 => Sh14313_0,
ADR2 => Sh14316_4518,
ADR3 => Sh1437_0,
O => N320
);
Sh1587_F : X_LUT4
generic map(
INIT => X"E2E2",
LOC => "SLICE_X28Y22"
)
port map (
ADR0 => Sh1222_0,
ADR1 => a(1),
ADR2 => Sh1202_0,
ADR3 => VCC,
O => N426
);
Sh3531_F : X_LUT4
generic map(
INIT => X"CFC0",
LOC => "SLICE_X13Y31"
)
port map (
ADR0 => VCC,
ADR1 => Sh27,
ADR2 => b_reg(3),
ADR3 => Sh3,
O => N356
);
Sh14731 : X_LUT4
generic map(
INIT => X"DDDC",
LOC => "SLICE_X25Y16"
)
port map (
ADR0 => a(2),
ADR1 => Sh14712,
ADR2 => Sh14713_4500,
ADR3 => Sh14716_4501,
O => Sh147
);
Sh14713 : X_LUT4
generic map(
INIT => X"C480",
LOC => "SLICE_X25Y16"
)
port map (
ADR0 => a(1),
ADR1 => a(3),
ADR2 => Sh1052_0,
ADR3 => Sh1072_0,
O => Sh14713_pack_1
);
Sh15432 : X_LUT4
generic map(
INIT => X"FE32",
LOC => "SLICE_X28Y25"
)
port map (
ADR0 => Sh15413_0,
ADR1 => a(2),
ADR2 => Sh15416_O,
ADR3 => Sh1547,
O => Sh154
);
Sh15416 : X_LUT4
generic map(
INIT => X"3022",
LOC => "SLICE_X28Y25"
)
port map (
ADR0 => Sh1222_0,
ADR1 => a(3),
ADR2 => Sh1202_0,
ADR3 => a(1),
O => Sh15416_O_pack_1
);
Sh14431 : X_LUT4
generic map(
INIT => X"DDDC",
LOC => "SLICE_X23Y13"
)
port map (
ADR0 => a(2),
ADR1 => Sh14412_0,
ADR2 => Sh14413_0,
ADR3 => Sh14416_4486,
O => Sh144
);
Sh14416 : X_LUT4
generic map(
INIT => X"3300",
LOC => "SLICE_X23Y13"
)
port map (
ADR0 => VCC,
ADR1 => a(3),
ADR2 => VCC,
ADR3 => Sh112,
O => Sh14416_pack_1
);
Sh14332 : X_LUT4
generic map(
INIT => X"FE54",
LOC => "SLICE_X25Y22"
)
port map (
ADR0 => a(2),
ADR1 => Sh14313_0,
ADR2 => Sh14316_4518,
ADR3 => Sh1437_0,
O => Sh143
);
Sh14316 : X_LUT4
generic map(
INIT => X"3210",
LOC => "SLICE_X25Y22"
)
port map (
ADR0 => a(1),
ADR1 => a(3),
ADR2 => Sh1112_0,
ADR3 => Sh1092_0,
O => Sh14316_pack_1
);
Sh15032 : X_LUT4
generic map(
INIT => X"AAFC",
LOC => "SLICE_X27Y22"
)
port map (
ADR0 => Sh1507,
ADR1 => Sh15013_0,
ADR2 => Sh15016_O,
ADR3 => a(2),
O => Sh150
);
Sh15016 : X_LUT4
generic map(
INIT => X"3202",
LOC => "SLICE_X27Y22"
)
port map (
ADR0 => Sh1182_0,
ADR1 => a(3),
ADR2 => a(1),
ADR3 => Sh1162_0,
O => Sh15016_O_pack_1
);
hex_digit_i_3 : X_FF
generic map(
LOC => "SLICE_X26Y12",
INIT => '0'
)
port map (
I => hex_digit_i_3_DXMUX_9768,
CE => VCC,
CLK => hex_digit_i_3_CLKINV_9749,
SET => GND,
RST => hex_digit_i_3_FFX_RSTAND_9773,
O => hex_digit_i(3)
);
hex_digit_i_3_FFX_RSTAND : X_BUF
generic map(
LOC => "SLICE_X26Y12",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => hex_digit_i_3_FFX_RSTAND_9773
);
Mmux_hex_digit_i_mux0001_43 : X_LUT4
generic map(
INIT => X"F5A0",
LOC => "SLICE_X26Y12"
)
port map (
ADR0 => LED_flash_cnt(8),
ADR1 => VCC,
ADR2 => b_reg(11),
ADR3 => b_reg(15),
O => Mmux_hex_digit_i_mux0001_43_9756
);
Mmux_hex_digit_i_mux0001_33 : X_LUT4
generic map(
INIT => X"EE22",
LOC => "SLICE_X26Y12"
)
port map (
ADR0 => b_reg(7),
ADR1 => LED_flash_cnt(8),
ADR2 => VCC,
ADR3 => b_reg(3),
O => Mmux_hex_digit_i_mux0001_33_9764
);
a_reg_mux0000_15_1 : X_LUT4
generic map(
INIT => X"F5CC",
LOC => "SLICE_X15Y22"
)
port map (
ADR0 => state_FSM_FFd1_4311,
ADR1 => a_reg(15),
ADR2 => a(15),
ADR3 => state_FSM_FFd2_4312,
O => a_reg_mux0000(15)
);
a_reg_mux0000_14_1 : X_LUT4
generic map(
INIT => X"DDF0",
LOC => "SLICE_X15Y22"
)
port map (
ADR0 => state_FSM_FFd1_4311,
ADR1 => a(14),
ADR2 => a_reg(14),
ADR3 => state_FSM_FFd2_4312,
O => a_reg_mux0000(14)
);
a_reg_14 : X_FF
generic map(
LOC => "SLICE_X15Y22",
INIT => '0'
)
port map (
I => a_reg_15_DYMUX_11459,
CE => VCC,
CLK => a_reg_15_CLKINV_11450,
SET => GND,
RST => a_reg_15_SRINV_11451,
O => a_reg(14)
);
a_reg_23 : X_FF
generic map(
LOC => "SLICE_X18Y31",
INIT => '0'
)
port map (
I => a_reg_23_DXMUX_11431,
CE => VCC,
CLK => a_reg_23_CLKINV_11408,
SET => GND,
RST => a_reg_23_SRINV_11409,
O => a_reg(23)
);
Mxor_ab_xor_Result_20_1 : X_LUT4
generic map(
INIT => X"3C3C",
LOC => "SLICE_X22Y25"
)
port map (
ADR0 => VCC,
ADR1 => b_reg(20),
ADR2 => a_reg(20),
ADR3 => VCC,
O => ab_xor_20_Q
);
Mxor_ba_xor_Result_11_1_SW2 : X_LUT4
generic map(
INIT => X"0F55",
LOC => "SLICE_X15Y14"
)
port map (
ADR0 => b_reg(12),
ADR1 => VCC,
ADR2 => b_reg(11),
ADR3 => a(0),
O => N257
);
Mxor_ab_xor_Result_12_1 : X_LUT4
generic map(
INIT => X"33CC",
LOC => "SLICE_X15Y14"
)
port map (
ADR0 => VCC,
ADR1 => b_reg(12),
ADR2 => VCC,
ADR3 => a_reg(12),
O => ab_xor_12_Q
);
Mxor_ba_xor_Result_11_1_SW3 : X_LUT4
generic map(
INIT => X"C5C5",
LOC => "SLICE_X14Y12"
)
port map (
ADR0 => b_reg(12),
ADR1 => b_reg(11),
ADR2 => a(0),
ADR3 => VCC,
O => N258
);
Sh1297 : X_LUT4
generic map(
INIT => X"CFC0",
LOC => "SLICE_X22Y15"
)
port map (
ADR0 => VCC,
ADR1 => Sh117,
ADR2 => a(3),
ADR3 => Sh125,
O => Sh1297_14037
);
LED_flash_cnt_4 : X_FF
generic map(
LOC => "SLICE_X31Y12",
INIT => '0'
)
port map (
I => LED_flash_cnt_4_DXMUX_4770,
CE => VCC,
CLK => LED_flash_cnt_4_CLKINV_4729,
SET => GND,
RST => LED_flash_cnt_4_SRINV_4730,
O => LED_flash_cnt(4)
);
LED_flash_cnt_9 : X_FF
generic map(
LOC => "SLICE_X31Y14",
INIT => '0'
)
port map (
I => LED_flash_cnt_8_DYMUX_4854,
CE => VCC,
CLK => LED_flash_cnt_8_CLKINV_4840,
SET => GND,
RST => LED_flash_cnt_8_SRINV_4841,
O => LED_flash_cnt(9)
);
LED_flash_cnt_7 : X_FF
generic map(
LOC => "SLICE_X31Y13",
INIT => '0'
)
port map (
I => LED_flash_cnt_6_DYMUX_4807,
CE => VCC,
CLK => LED_flash_cnt_6_CLKINV_4785,
SET => GND,
RST => LED_flash_cnt_6_SRINV_4786,
O => LED_flash_cnt(7)
);
LED_flash_cnt_1 : X_FF
generic map(
LOC => "SLICE_X31Y10",
INIT => '0'
)
port map (
I => LED_flash_cnt_0_DYMUX_4636,
CE => VCC,
CLK => LED_flash_cnt_0_CLKINV_4619,
SET => GND,
RST => LED_flash_cnt_0_SRINV_4620,
O => LED_flash_cnt(1)
);
Mcount_LED_flash_cnt_lut_0_INV_0 : X_LUT4
generic map(
INIT => X"0F0F",
LOC => "SLICE_X31Y10"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => LED_flash_cnt(0),
ADR3 => VCC,
O => Mcount_LED_flash_cnt_lut(0)
);
LED_flash_cnt_0 : X_FF
generic map(
LOC => "SLICE_X31Y10",
INIT => '0'
)
port map (
I => LED_flash_cnt_0_DXMUX_4658,
CE => VCC,
CLK => LED_flash_cnt_0_CLKINV_4619,
SET => GND,
RST => LED_flash_cnt_0_SRINV_4620,
O => LED_flash_cnt(0)
);
LED_flash_cnt_3 : X_FF
generic map(
LOC => "SLICE_X31Y11",
INIT => '0'
)
port map (
I => LED_flash_cnt_2_DYMUX_4695,
CE => VCC,
CLK => LED_flash_cnt_2_CLKINV_4673,
SET => GND,
RST => LED_flash_cnt_2_SRINV_4674,
O => LED_flash_cnt(3)
);
LED_flash_cnt_2 : X_FF
generic map(
LOC => "SLICE_X31Y11",
INIT => '0'
)
port map (
I => LED_flash_cnt_2_DXMUX_4714,
CE => VCC,
CLK => LED_flash_cnt_2_CLKINV_4673,
SET => GND,
RST => LED_flash_cnt_2_SRINV_4674,
O => LED_flash_cnt(2)
);
LED_flash_cnt_6 : X_FF
generic map(
LOC => "SLICE_X31Y13",
INIT => '0'
)
port map (
I => LED_flash_cnt_6_DXMUX_4826,
CE => VCC,
CLK => LED_flash_cnt_6_CLKINV_4785,
SET => GND,
RST => LED_flash_cnt_6_SRINV_4786,
O => LED_flash_cnt(6)
);
LED_flash_cnt_8 : X_FF
generic map(
LOC => "SLICE_X31Y14",
INIT => '0'
)
port map (
I => LED_flash_cnt_8_DXMUX_4875,
CE => VCC,
CLK => LED_flash_cnt_8_CLKINV_4840,
SET => GND,
RST => LED_flash_cnt_8_SRINV_4841,
O => LED_flash_cnt(8)
);
Madd_a_lut_1_Q : X_LUT4
generic map(
INIT => X"1ED2",
LOC => "SLICE_X17Y16"
)
port map (
ADR0 => Sh33,
ADR1 => b_reg(4),
ADR2 => Mrom_a_rom00001_0,
ADR3 => Sh49,
O => Madd_a_lut(1)
);
Madd_a_lut_0_Q : X_LUT4
generic map(
INIT => X"3C3C",
LOC => "SLICE_X17Y16"
)
port map (
ADR0 => VCC,
ADR1 => Sh64_0,
ADR2 => Mrom_a_rom0000_0,
ADR3 => VCC,
O => Madd_a_lut(0)
);
Madd_a_lut_3_Q : X_LUT4
generic map(
INIT => X"A695",
LOC => "SLICE_X17Y17"
)
port map (
ADR0 => N224_0,
ADR1 => b_reg(4),
ADR2 => Sh51,
ADR3 => Sh35,
O => Madd_a_lut(3)
);
Madd_a_lut_2_Q : X_LUT4
generic map(
INIT => X"47B8",
LOC => "SLICE_X17Y17"
)
port map (
ADR0 => Sh50,
ADR1 => b_reg(4),
ADR2 => Sh34,
ADR3 => Mrom_a_rom00002_0,
O => Madd_a_lut(2)
);
Madd_a_lut_4_Q : X_LUT4
generic map(
INIT => X"5A3C",
LOC => "SLICE_X17Y18"
)
port map (
ADR0 => Sh52,
ADR1 => Sh36,
ADR2 => Mrom_a_rom00004_0,
ADR3 => b_reg(4),
O => Madd_a_lut(4)
);
Madd_a_lut_7_Q : X_LUT4
generic map(
INIT => X"99A5",
LOC => "SLICE_X17Y19"
)
port map (
ADR0 => N286_0,
ADR1 => Sh55,
ADR2 => Sh39,
ADR3 => b_reg(4),
O => Madd_a_lut(7)
);
Madd_a_lut_9_Q : X_LUT4
generic map(
INIT => X"5A66",
LOC => "SLICE_X17Y20"
)
port map (
ADR0 => Mrom_a_rom00009_0,
ADR1 => Sh41,
ADR2 => Sh57,
ADR3 => b_reg(4),
O => Madd_a_lut(9)
);
Madd_a_lut_8_Q : X_LUT4
generic map(
INIT => X"4B78",
LOC => "SLICE_X17Y20"
)
port map (
ADR0 => Sh56,
ADR1 => b_reg(4),
ADR2 => Mrom_a_rom00008_0,
ADR3 => Sh40,
O => Madd_a_lut(8)
);
Madd_a_lut_11_Q : X_LUT4
generic map(
INIT => X"1ED2",
LOC => "SLICE_X17Y21"
)
port map (
ADR0 => Sh43,
ADR1 => b_reg(4),
ADR2 => Mrom_a_rom000011_0,
ADR3 => Sh59,
O => Madd_a_lut(11)
);
Madd_a_lut_10_Q : X_LUT4
generic map(
INIT => X"596A",
LOC => "SLICE_X17Y21"
)
port map (
ADR0 => Mrom_a_rom000010_0,
ADR1 => b_reg(4),
ADR2 => Sh58,
ADR3 => Sh42,
O => Madd_a_lut(10)
);
Madd_a_lut_12_Q : X_LUT4
generic map(
INIT => X"596A",
LOC => "SLICE_X17Y22"
)
port map (
ADR0 => N222_0,
ADR1 => b_reg(4),
ADR2 => Sh60,
ADR3 => Sh44,
O => Madd_a_lut(12)
);
Madd_a_lut_15_Q : X_LUT4
generic map(
INIT => X"47B8",
LOC => "SLICE_X17Y23"
)
port map (
ADR0 => Sh63,
ADR1 => b_reg(4),
ADR2 => Sh47,
ADR3 => Mrom_a_rom000015_0,
O => Madd_a_lut(15)
);
Madd_a_lut_14_Q : X_LUT4
generic map(
INIT => X"1ED2",
LOC => "SLICE_X17Y23"
)
port map (
ADR0 => Sh46,
ADR1 => b_reg(4),
ADR2 => N226_0,
ADR3 => Sh62,
O => Madd_a_lut(14)
);
Madd_a_lut_17_Q : X_LUT4
generic map(
INIT => X"569A",
LOC => "SLICE_X17Y24"
)
port map (
ADR0 => Mrom_a_rom000017_0,
ADR1 => b_reg(4),
ADR2 => Sh49,
ADR3 => Sh33,
O => Madd_a_lut(17)
);
Madd_a_lut_19_Q : X_LUT4
generic map(
INIT => X"4B78",
LOC => "SLICE_X17Y25"
)
port map (
ADR0 => Sh35,
ADR1 => b_reg(4),
ADR2 => Mrom_a_rom000019_0,
ADR3 => Sh51,
O => Madd_a_lut(19)
);
Madd_a_lut_18_Q : X_LUT4
generic map(
INIT => X"665A",
LOC => "SLICE_X17Y25"
)
port map (
ADR0 => Mrom_a_rom000018_0,
ADR1 => Sh34,
ADR2 => Sh50,
ADR3 => b_reg(4),
O => Madd_a_lut(18)
);
Madd_a_lut_21_Q : X_LUT4
generic map(
INIT => X"596A",
LOC => "SLICE_X17Y26"
)
port map (
ADR0 => Mrom_a_rom000021_0,
ADR1 => b_reg(4),
ADR2 => Sh37,
ADR3 => Sh53,
O => Madd_a_lut(21)
);
Madd_a_lut_20_Q : X_LUT4
generic map(
INIT => X"A665",
LOC => "SLICE_X17Y26"
)
port map (
ADR0 => Sh84_0,
ADR1 => i_cnt(1),
ADR2 => i_cnt(2),
ADR3 => i_cnt(3),
O => Madd_a_lut(20)
);
Madd_a_lut_22_Q : X_LUT4
generic map(
INIT => X"569A",
LOC => "SLICE_X17Y27"
)
port map (
ADR0 => N520_0,
ADR1 => b_reg(4),
ADR2 => Sh54,
ADR3 => Sh38,
O => Madd_a_lut(22)
);
Madd_a_lut_25_Q : X_LUT4
generic map(
INIT => X"5A66",
LOC => "SLICE_X17Y28"
)
port map (
ADR0 => Mrom_a_rom000025_0,
ADR1 => Sh57,
ADR2 => Sh41,
ADR3 => b_reg(4),
O => Madd_a_lut(25)
);
Madd_a_lut_24_Q : X_LUT4
generic map(
INIT => X"3C5A",
LOC => "SLICE_X17Y28"
)
port map (
ADR0 => Sh56,
ADR1 => Sh40,
ADR2 => Mrom_a_rom000024_0,
ADR3 => b_reg(4),
O => Madd_a_lut(24)
);
Madd_a_lut_27_Q : X_LUT4
generic map(
INIT => X"663C",
LOC => "SLICE_X17Y29"
)
port map (
ADR0 => Sh43,
ADR1 => Mrom_a_rom000027_0,
ADR2 => Sh59,
ADR3 => b_reg(4),
O => Madd_a_lut(27)
);
Madd_a_lut_29_Q : X_LUT4
generic map(
INIT => X"569A",
LOC => "SLICE_X17Y30"
)
port map (
ADR0 => Mrom_a_rom000029_0,
ADR1 => b_reg(4),
ADR2 => Sh61,
ADR3 => Sh45,
O => Madd_a_lut(29)
);
Madd_a_lut_28_Q : X_LUT4
generic map(
INIT => X"665A",
LOC => "SLICE_X17Y30"
)
port map (
ADR0 => N518_0,
ADR1 => Sh44,
ADR2 => Sh60,
ADR3 => b_reg(4),
O => Madd_a_lut(28)
);
Madd_a_lut_31_Q : X_LUT4
generic map(
INIT => X"596A",
LOC => "SLICE_X17Y31"
)
port map (
ADR0 => Mrom_a_rom000031_0,
ADR1 => b_reg(4),
ADR2 => Sh47,
ADR3 => Sh63,
O => Madd_a_lut(31)
);
Madd_a_lut_30_Q : X_LUT4
generic map(
INIT => X"5A66",
LOC => "SLICE_X17Y31"
)
port map (
ADR0 => Mrom_a_rom000030_0,
ADR1 => Sh62,
ADR2 => Sh46,
ADR3 => b_reg(4),
O => Madd_a_lut(30)
);
Madd_b_lut_1_Q : X_LUT4
generic map(
INIT => X"27D8",
LOC => "SLICE_X21Y12"
)
port map (
ADR0 => a(4),
ADR1 => Sh145,
ADR2 => Sh129,
ADR3 => Mrom_b_rom00001_0,
O => Madd_b_lut(1)
);
Madd_b_lut_3_Q : X_LUT4
generic map(
INIT => X"3336",
LOC => "SLICE_X21Y13"
)
port map (
ADR0 => N33_0,
ADR1 => Sh163,
ADR2 => N12_0,
ADR3 => i_cnt_mux0001_0_22_4123,
O => Madd_b_lut(3)
);
Madd_b_lut_2_Q : X_LUT4
generic map(
INIT => X"5A59",
LOC => "SLICE_X21Y13"
)
port map (
ADR0 => Sh162,
ADR1 => i_cnt(3),
ADR2 => N17_0,
ADR3 => N14_0,
O => Madd_b_lut(2)
);
Madd_b_lut_4_Q : X_LUT4
generic map(
INIT => X"5656",
LOC => "SLICE_X21Y14"
)
port map (
ADR0 => Sh164,
ADR1 => N20_0,
ADR2 => N12_0,
ADR3 => VCC,
O => Madd_b_lut(4)
);
Madd_b_lut_7_Q : X_LUT4
generic map(
INIT => X"369C",
LOC => "SLICE_X21Y15"
)
port map (
ADR0 => a(4),
ADR1 => Mrom_b_rom00007_0,
ADR2 => Sh135,
ADR3 => Sh151,
O => Madd_b_lut(7)
);
Madd_b_lut_6_Q : X_LUT4
generic map(
INIT => X"1BE4",
LOC => "SLICE_X21Y15"
)
port map (
ADR0 => a(4),
ADR1 => Sh134,
ADR2 => Sh150_0,
ADR3 => Mrom_b_rom00006_0,
O => Madd_b_lut(6)
);
Madd_b_lut_9_Q : X_LUT4
generic map(
INIT => X"4B78",
LOC => "SLICE_X21Y16"
)
port map (
ADR0 => Sh153,
ADR1 => a(4),
ADR2 => Mrom_b_rom00009_0,
ADR3 => Sh137,
O => Madd_b_lut(9)
);
Madd_b_lut_11_Q : X_LUT4
generic map(
INIT => X"656A",
LOC => "SLICE_X21Y17"
)
port map (
ADR0 => Mrom_b_rom000011_0,
ADR1 => Sh155,
ADR2 => a(4),
ADR3 => Sh139,
O => Madd_b_lut(11)
);
Madd_b_lut_10_Q : X_LUT4
generic map(
INIT => X"53AC",
LOC => "SLICE_X21Y17"
)
port map (
ADR0 => Sh154_0,
ADR1 => Sh138,
ADR2 => a(4),
ADR3 => Mrom_b_rom000010_0,
O => Madd_b_lut(10)
);
Madd_b_lut_13_Q : X_LUT4
generic map(
INIT => X"56A6",
LOC => "SLICE_X21Y18"
)
port map (
ADR0 => Mrom_b_rom000013_0,
ADR1 => Sh141,
ADR2 => a(4),
ADR3 => Sh157,
O => Madd_b_lut(13)
);
Madd_b_lut_12_Q : X_LUT4
generic map(
INIT => X"1DE2",
LOC => "SLICE_X21Y18"
)
port map (
ADR0 => Sh140,
ADR1 => a(4),
ADR2 => Sh156,
ADR3 => Mrom_b_rom000012_0,
O => Madd_b_lut(12)
);
Madd_b_lut_15_Q : X_LUT4
generic map(
INIT => X"95A6",
LOC => "SLICE_X21Y19"
)
port map (
ADR0 => Sh175,
ADR1 => i_cnt(1),
ADR2 => i_cnt(3),
ADR3 => N522_0,
O => Madd_b_lut(15)
);
Madd_b_lut_14_Q : X_LUT4
generic map(
INIT => X"4B78",
LOC => "SLICE_X21Y19"
)
port map (
ADR0 => Sh158,
ADR1 => a(4),
ADR2 => Mrom_b_rom000014_0,
ADR3 => Sh142,
O => Madd_b_lut(14)
);
Madd_b_lut_17_Q : X_LUT4
generic map(
INIT => X"35CA",
LOC => "SLICE_X21Y20"
)
port map (
ADR0 => Sh145,
ADR1 => Sh129,
ADR2 => a(4),
ADR3 => Mrom_b_rom000017_0,
O => Madd_b_lut(17)
);
Madd_b_lut_16_Q : X_LUT4
generic map(
INIT => X"4B78",
LOC => "SLICE_X21Y20"
)
port map (
ADR0 => Sh128,
ADR1 => a(4),
ADR2 => Mrom_b_rom000016_0,
ADR3 => Sh144_0,
O => Madd_b_lut(16)
);
Madd_b_lut_19_Q : X_LUT4
generic map(
INIT => X"569A",
LOC => "SLICE_X21Y21"
)
port map (
ADR0 => Mrom_b_rom000019_0,
ADR1 => a(4),
ADR2 => Sh147_0,
ADR3 => Sh131,
O => Madd_b_lut(19)
);
Madd_b_lut_18_Q : X_LUT4
generic map(
INIT => X"3336",
LOC => "SLICE_X21Y21"
)
port map (
ADR0 => N27_0,
ADR1 => Sh178,
ADR2 => N34_0,
ADR3 => N77_0,
O => Madd_b_lut(18)
);
Madd_b_lut_21_Q : X_LUT4
generic map(
INIT => X"1DE2",
LOC => "SLICE_X21Y22"
)
port map (
ADR0 => Sh149,
ADR1 => a(4),
ADR2 => Sh133,
ADR3 => Mrom_b_rom000021_0,
O => Madd_b_lut(21)
);
Madd_b_lut_20_Q : X_LUT4
generic map(
INIT => X"4B78",
LOC => "SLICE_X21Y22"
)
port map (
ADR0 => Sh132,
ADR1 => a(4),
ADR2 => Mrom_b_rom000020_0,
ADR3 => Sh148_0,
O => Madd_b_lut(20)
);
Madd_b_lut_23_Q : X_LUT4
generic map(
INIT => X"369C",
LOC => "SLICE_X21Y23"
)
port map (
ADR0 => a(4),
ADR1 => Mrom_b_rom000023_0,
ADR2 => Sh151,
ADR3 => Sh135,
O => Madd_b_lut(23)
);
Madd_b_lut_22_Q : X_LUT4
generic map(
INIT => X"1EB4",
LOC => "SLICE_X21Y23"
)
port map (
ADR0 => a(4),
ADR1 => Sh150_0,
ADR2 => Mrom_b_rom000022_0,
ADR3 => Sh134,
O => Madd_b_lut(22)
);
Madd_b_lut_25_Q : X_LUT4
generic map(
INIT => X"595A",
LOC => "SLICE_X21Y24"
)
port map (
ADR0 => Sh185_0,
ADR1 => i_cnt(2),
ADR2 => N20_0,
ADR3 => N111_0,
O => Madd_b_lut(25)
);
Madd_b_lut_24_Q : X_LUT4
generic map(
INIT => X"27D8",
LOC => "SLICE_X21Y24"
)
port map (
ADR0 => a(4),
ADR1 => Sh136,
ADR2 => Sh152,
ADR3 => Mrom_b_rom000024_0,
O => Madd_b_lut(24)
);
Madd_b_lut_27_Q : X_LUT4
generic map(
INIT => X"1ED2",
LOC => "SLICE_X21Y25"
)
port map (
ADR0 => Sh155,
ADR1 => a(4),
ADR2 => Mrom_b_rom000027_0,
ADR3 => Sh139,
O => Madd_b_lut(27)
);
Madd_b_lut_26_Q : X_LUT4
generic map(
INIT => X"596A",
LOC => "SLICE_X21Y25"
)
port map (
ADR0 => Mrom_b_rom000026_0,
ADR1 => a(4),
ADR2 => Sh138,
ADR3 => Sh154_0,
O => Madd_b_lut(26)
);
Madd_b_lut_29_Q : X_LUT4
generic map(
INIT => X"36C6",
LOC => "SLICE_X21Y26"
)
port map (
ADR0 => Sh157,
ADR1 => Mrom_b_rom000029_0,
ADR2 => a(4),
ADR3 => Sh141,
O => Madd_b_lut(29)
);
Madd_b_lut_28_Q : X_LUT4
generic map(
INIT => X"3C66",
LOC => "SLICE_X21Y26"
)
port map (
ADR0 => Sh156,
ADR1 => Mrom_b_rom000028_0,
ADR2 => Sh140,
ADR3 => a(4),
O => Madd_b_lut(28)
);
Madd_b_lut_31_Q : X_LUT4
generic map(
INIT => X"56A6",
LOC => "SLICE_X21Y27"
)
port map (
ADR0 => Mrom_b_rom000031_0,
ADR1 => Sh159_0,
ADR2 => a(4),
ADR3 => Sh143_0,
O => Madd_b_lut(31)
);
Madd_b_lut_30_Q : X_LUT4
generic map(
INIT => X"1ED2",
LOC => "SLICE_X21Y27"
)
port map (
ADR0 => Sh158,
ADR1 => a(4),
ADR2 => Mrom_b_rom000030_0,
ADR3 => Sh142,
O => Madd_b_lut(30)
);
din_lower_0_IFF_IMUX : X_BUF
generic map(
LOC => "IPAD60",
PATHPULSE => 638 ps
)
port map (
I => din_lower_0_INBUF,
O => Madd_b_pre_cy_0_Q
);
din_lower_1_IFF_IMUX : X_BUF
generic map(
LOC => "PAD83",
PATHPULSE => 638 ps
)
port map (
I => din_lower_1_INBUF,
O => swtch_led_1_OBUF_4254
);
din_lower_2_IFF_IMUX : X_BUF
generic map(
LOC => "IPAD86",
PATHPULSE => 638 ps
)
port map (
I => din_lower_2_INBUF,
O => Madd_b_pre_lut(2)
);
din_lower_3_IFF_IMUX : X_BUF
generic map(
LOC => "IPAD3",
PATHPULSE => 638 ps
)
port map (
I => din_lower_3_INBUF,
O => swtch_led_3_OBUF_4256
);
din_lower_4_IFF_IMUX : X_BUF
generic map(
LOC => "PAD94",
PATHPULSE => 638 ps
)
port map (
I => din_lower_4_INBUF,
O => swtch_led_4_OBUF_4257
);
din_lower_5_IFF_IMUX : X_BUF
generic map(
LOC => "PAD99",
PATHPULSE => 638 ps
)
port map (
I => din_lower_5_INBUF,
O => swtch_led_5_OBUF_4258
);
din_lower_6_IFF_IMUX : X_BUF
generic map(
LOC => "IPAD100",
PATHPULSE => 638 ps
)
port map (
I => din_lower_6_INBUF,
O => swtch_led_6_OBUF_4259
);
din_lower_7_IFF_IMUX : X_BUF
generic map(
LOC => "IPAD73",
PATHPULSE => 638 ps
)
port map (
I => din_lower_7_INBUF,
O => swtch_led_7_OBUF_4260
);
clr_IFF_IMUX : X_BUF
generic map(
LOC => "PAD11",
PATHPULSE => 638 ps
)
port map (
I => clr_INBUF,
O => clr_IBUF_3948
);
di_vld_IFF_IMUX : X_BUF
generic map(
LOC => "PAD72",
PATHPULSE => 638 ps
)
port map (
I => di_vld_INBUF,
O => di_vld_IBUF_4273
);
Sh22_f5_F : X_LUT4
generic map(
INIT => X"AA3C",
LOC => "SLICE_X15Y31"
)
port map (
ADR0 => ab_xor_21_0,
ADR1 => a_reg(22),
ADR2 => b_reg(22),
ADR3 => b_reg_0_2_4323,
O => N482
);
Sh22_f5_G : X_LUT4
generic map(
INIT => X"AA3C",
LOC => "SLICE_X15Y31"
)
port map (
ADR0 => ab_xor_19_0,
ADR1 => a_reg(20),
ADR2 => b_reg(20),
ADR3 => b_reg_0_2_4323,
O => N483
);
Sh30_f5_F : X_LUT4
generic map(
INIT => X"CC5A",
LOC => "SLICE_X14Y35"
)
port map (
ADR0 => b_reg(30),
ADR1 => ab_xor_29_0,
ADR2 => a_reg(30),
ADR3 => b_reg_0_3_4316,
O => N472
);
Sh30_f5_G : X_LUT4
generic map(
INIT => X"F066",
LOC => "SLICE_X14Y35"
)
port map (
ADR0 => a_reg(28),
ADR1 => b_reg(28),
ADR2 => ab_xor_27_0,
ADR3 => b_reg_0_3_4316,
O => N473
);
Sh17_f5_F : X_LUT4
generic map(
INIT => X"A3AC",
LOC => "SLICE_X14Y23"
)
port map (
ADR0 => ab_xor_16_0,
ADR1 => a_reg(17),
ADR2 => b_reg_0_2_4323,
ADR3 => b_reg(17),
O => N492
);
Sh17_f5_G : X_LUT4
generic map(
INIT => X"72D8",
LOC => "SLICE_X14Y23"
)
port map (
ADR0 => b_reg_0_2_4323,
ADR1 => b_reg(14),
ADR2 => ab_xor_15_0,
ADR3 => a_reg(14),
O => N493
);
Sh25_f5_F : X_LUT4
generic map(
INIT => X"F066",
LOC => "SLICE_X15Y32"
)
port map (
ADR0 => b_reg(25),
ADR1 => a_reg(25),
ADR2 => ab_xor_24_0,
ADR3 => b_reg_0_2_4323,
O => N488
);
Sh25_f5_G : X_LUT4
generic map(
INIT => X"72D8",
LOC => "SLICE_X15Y32"
)
port map (
ADR0 => b_reg_0_2_4323,
ADR1 => a_reg(22),
ADR2 => ab_xor_23_0,
ADR3 => b_reg(22),
O => N489
);
Sh18_f5_F : X_LUT4
generic map(
INIT => X"D1E2",
LOC => "SLICE_X13Y20"
)
port map (
ADR0 => a_reg(18),
ADR1 => b_reg_0_2_4323,
ADR2 => ab_xor_17_0,
ADR3 => b_reg(18),
O => N484
);
Sh18_f5_G : X_LUT4
generic map(
INIT => X"D1E2",
LOC => "SLICE_X13Y20"
)
port map (
ADR0 => b_reg(16),
ADR1 => b_reg_0_2_4323,
ADR2 => ab_xor_15_0,
ADR3 => a_reg(16),
O => N485
);
Sh26_f5_F : X_LUT4
generic map(
INIT => X"8DD8",
LOC => "SLICE_X14Y32"
)
port map (
ADR0 => b_reg_0_2_4323,
ADR1 => ab_xor_25_0,
ADR2 => a_reg(26),
ADR3 => b_reg(26),
O => N480
);
Sh26_f5_G : X_LUT4
generic map(
INIT => X"CC5A",
LOC => "SLICE_X14Y32"
)
port map (
ADR0 => b_reg(24),
ADR1 => ab_xor_23_0,
ADR2 => a_reg(24),
ADR3 => b_reg_0_2_4323,
O => N481
);
Sh29_f5_F : X_LUT4
generic map(
INIT => X"D1E2",
LOC => "SLICE_X15Y34"
)
port map (
ADR0 => b_reg(29),
ADR1 => b_reg_0_3_4316,
ADR2 => ab_xor_28_0,
ADR3 => a_reg(29),
O => N478
);
Sh29_f5_G : X_LUT4
generic map(
INIT => X"4EE4",
LOC => "SLICE_X15Y34"
)
port map (
ADR0 => b_reg_0_3_4316,
ADR1 => ab_xor_27_0,
ADR2 => b_reg(26),
ADR3 => a_reg(26),
O => N479
);
Sh4_F : X_LUT4
generic map(
INIT => X"F606",
LOC => "SLICE_X15Y19"
)
port map (
ADR0 => b_reg_4_1_4383,
ADR1 => a_reg(4),
ADR2 => b_reg_0_1_4382,
ADR3 => ab_xor_3_0,
O => N300
);
Sh4_G : X_LUT4
generic map(
INIT => X"2772",
LOC => "SLICE_X15Y19"
)
port map (
ADR0 => b_reg_0_2_4323,
ADR1 => a_reg(1),
ADR2 => a_reg(2),
ADR3 => b_reg_2_1_4381,
O => N301
);
Sh8_F : X_LUT4
generic map(
INIT => X"8DD8",
LOC => "SLICE_X12Y14"
)
port map (
ADR0 => b_reg_0_1_4382,
ADR1 => ab_xor_7_0,
ADR2 => a_reg(8),
ADR3 => b_reg(8),
O => N324
);
Sh8_G : X_LUT4
generic map(
INIT => X"AA3C",
LOC => "SLICE_X12Y14"
)
port map (
ADR0 => ab_xor_5_0,
ADR1 => a_reg(6),
ADR2 => b_reg(6),
ADR3 => b_reg_0_1_4382,
O => N325
);
Sh981 : X_LUT4
generic map(
INIT => X"66F0",
LOC => "SLICE_X23Y27"
)
port map (
ADR0 => b_reg(31),
ADR1 => a(31),
ADR2 => b_reg(0),
ADR3 => a(0),
O => Sh962
);
Sh1262_rt : X_LUT4
generic map(
INIT => X"AAAA",
LOC => "SLICE_X23Y27"
)
port map (
ADR0 => Sh1262_0,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => Sh1262_rt_7104
);
Sh972 : X_LUT4
generic map(
INIT => X"7272",
LOC => "SLICE_X24Y27"
)
port map (
ADR0 => a(0),
ADR1 => b_reg(0),
ADR2 => b_reg(1),
ADR3 => VCC,
O => Sh972_7119
);
Sh1272_rt : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X24Y27"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => Sh1272_0,
O => Sh1272_rt_7129
);
Sh1021 : X_LUT4
generic map(
INIT => X"B18D",
LOC => "SLICE_X25Y27"
)
port map (
ADR0 => N263_0,
ADR1 => a(3),
ADR2 => a(4),
ADR3 => N264_0,
O => Sh1002
);
Sh1001 : X_LUT4
generic map(
INIT => X"335A",
LOC => "SLICE_X25Y27"
)
port map (
ADR0 => a(2),
ADR1 => b_reg(1),
ADR2 => b_reg(2),
ADR3 => a(0),
O => Sh1001_7156
);
Sh1031 : X_LUT4
generic map(
INIT => X"D18B",
LOC => "SLICE_X22Y18"
)
port map (
ADR0 => a(4),
ADR1 => N246_0,
ADR2 => a(5),
ADR3 => N247_0,
O => Sh1012
);
Sh1011_rt : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X22Y18"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => Sh1011,
O => Sh1011_rt_7183
);
Sh1221 : X_LUT4
generic map(
INIT => X"B18D",
LOC => "SLICE_X21Y28"
)
port map (
ADR0 => N181_0,
ADR1 => a(23),
ADR2 => a(24),
ADR3 => N182_0,
O => Sh1202
);
Sh1182_rt : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X21Y28"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => Sh1182_0,
O => Sh1182_rt_7210
);
Sh1141 : X_LUT4
generic map(
INIT => X"AC35",
LOC => "SLICE_X25Y20"
)
port map (
ADR0 => a(16),
ADR1 => a(15),
ADR2 => N194_0,
ADR3 => N193_0,
O => Sh1122
);
Sh1102_rt : X_LUT4
generic map(
INIT => X"F0F0",
LOC => "SLICE_X25Y20"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => Sh1102_0,
ADR3 => VCC,
O => Sh1102_rt_7237
);
Sh1061 : X_LUT4
generic map(
INIT => X"8BD1",
LOC => "SLICE_X20Y13"
)
port map (
ADR0 => a(8),
ADR1 => N260_0,
ADR2 => a(7),
ADR3 => N261_0,
O => Sh1042
);
Sh1022_rt : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X20Y13"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => Sh1022_0,
O => Sh1022_rt_7264
);
Sh1231 : X_LUT4
generic map(
INIT => X"B18D",
LOC => "SLICE_X23Y29"
)
port map (
ADR0 => a(25),
ADR1 => N179_0,
ADR2 => N178_0,
ADR3 => a(24),
O => Sh1212
);
Sh1192_rt : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X23Y29"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => Sh1192_0,
O => Sh1192_rt_7291
);
Sh1151 : X_LUT4
generic map(
INIT => X"D18B",
LOC => "SLICE_X24Y20"
)
port map (
ADR0 => N191_0,
ADR1 => a(17),
ADR2 => N190_0,
ADR3 => a(16),
O => Sh1132
);
Sh1112_rt : X_LUT4
generic map(
INIT => X"F0F0",
LOC => "SLICE_X24Y20"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => Sh1112_0,
ADR3 => VCC,
O => Sh1112_rt_7318
);
Sh1071 : X_LUT4
generic map(
INIT => X"D81B",
LOC => "SLICE_X20Y12"
)
port map (
ADR0 => a(8),
ADR1 => N240_0,
ADR2 => N241_0,
ADR3 => a(9),
O => Sh1052
);
Sh1032_rt : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X20Y12"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => Sh1032_0,
O => Sh1032_rt_7345
);
Sh1261 : X_LUT4
generic map(
INIT => X"AC35",
LOC => "SLICE_X22Y29"
)
port map (
ADR0 => a(28),
ADR1 => a(27),
ADR2 => N176_0,
ADR3 => N175_0,
O => Sh1242
);
Sh1222_rt : X_LUT4
generic map(
INIT => X"AAAA",
LOC => "SLICE_X22Y29"
)
port map (
ADR0 => Sh1222_0,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => Sh1222_rt_7372
);
Sh1181 : X_LUT4
generic map(
INIT => X"E247",
LOC => "SLICE_X25Y24"
)
port map (
ADR0 => N188_0,
ADR1 => a(19),
ADR2 => N187_0,
ADR3 => a(20),
O => Sh1162
);
Sh1142_rt : X_LUT4
generic map(
INIT => X"F0F0",
LOC => "SLICE_X25Y24"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => Sh1142_0,
ADR3 => VCC,
O => Sh1142_rt_7399
);
Sh1101 : X_LUT4
generic map(
INIT => X"CA53",
LOC => "SLICE_X22Y12"
)
port map (
ADR0 => N258_0,
ADR1 => N257_0,
ADR2 => a(11),
ADR3 => a(12),
O => Sh1082
);
Sh1062_rt : X_LUT4
generic map(
INIT => X"CCCC",
LOC => "SLICE_X22Y12"
)
port map (
ADR0 => VCC,
ADR1 => Sh1062_0,
ADR2 => VCC,
ADR3 => VCC,
O => Sh1062_rt_7426
);
Sh1271 : X_LUT4
generic map(
INIT => X"8DB1",
LOC => "SLICE_X23Y30"
)
port map (
ADR0 => N172_0,
ADR1 => a(29),
ADR2 => a(28),
ADR3 => N173_0,
O => Sh1252
);
Sh1232_rt : X_LUT4
generic map(
INIT => X"F0F0",
LOC => "SLICE_X23Y30"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => Sh1232_0,
ADR3 => VCC,
O => Sh1232_rt_7453
);
Sh1191 : X_LUT4
generic map(
INIT => X"8BD1",
LOC => "SLICE_X25Y25"
)
port map (
ADR0 => N184_0,
ADR1 => a(21),
ADR2 => N185_0,
ADR3 => a(20),
O => Sh1172
);
Sh1152_rt : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X25Y25"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => Sh1152_0,
O => Sh1152_rt_7480
);
Sh1111 : X_LUT4
generic map(
INIT => X"B81D",
LOC => "SLICE_X22Y16"
)
port map (
ADR0 => N234_0,
ADR1 => a(12),
ADR2 => N235_0,
ADR3 => a(13),
O => Sh1092
);
Sh1072_rt : X_LUT4
generic map(
INIT => X"CCCC",
LOC => "SLICE_X22Y16"
)
port map (
ADR0 => VCC,
ADR1 => Sh1072_0,
ADR2 => VCC,
ADR3 => VCC,
O => Sh1072_rt_7507
);
Sh3_f51_F : X_LUT4
generic map(
INIT => X"7B48",
LOC => "SLICE_X12Y20"
)
port map (
ADR0 => b_reg_2_1_4381,
ADR1 => b_reg_0_3_4316,
ADR2 => a_reg(2),
ADR3 => ab_xor_3_0,
O => N308
);
Sh3_f51_G : X_LUT4
generic map(
INIT => X"3355",
LOC => "SLICE_X12Y20"
)
port map (
ADR0 => a_reg(1),
ADR1 => a_reg(0),
ADR2 => VCC,
ADR3 => b_reg(0),
O => N309
);
Sh7_f51_F : X_LUT4
generic map(
INIT => X"72D8",
LOC => "SLICE_X13Y17"
)
port map (
ADR0 => b_reg_0_3_4316,
ADR1 => a_reg(6),
ADR2 => ab_xor_7_0,
ADR3 => b_reg(6),
O => N336
);
Sh7_f51_G : X_LUT4
generic map(
INIT => X"B1E4",
LOC => "SLICE_X13Y17"
)
port map (
ADR0 => b_reg_0_3_4316,
ADR1 => b_reg(5),
ADR2 => ab_xor_4_0,
ADR3 => a_reg(5),
O => N337
);
Sh11_f51_F : X_LUT4
generic map(
INIT => X"74B8",
LOC => "SLICE_X13Y12"
)
port map (
ADR0 => a_reg(10),
ADR1 => b_reg_0_3_4316,
ADR2 => ab_xor_11_0,
ADR3 => b_reg(10),
O => N348
);
Sh11_f51_G : X_LUT4
generic map(
INIT => X"D1E2",
LOC => "SLICE_X13Y12"
)
port map (
ADR0 => a_reg(9),
ADR1 => b_reg_0_3_4316,
ADR2 => ab_xor_8_0,
ADR3 => b_reg(9),
O => N349
);
Sh15_f51_F : X_LUT4
generic map(
INIT => X"72D8",
LOC => "SLICE_X13Y16"
)
port map (
ADR0 => b_reg_0_3_4316,
ADR1 => b_reg(14),
ADR2 => ab_xor_15_0,
ADR3 => a_reg(14),
O => N346
);
Sh15_f51_G : X_LUT4
generic map(
INIT => X"BE14",
LOC => "SLICE_X13Y16"
)
port map (
ADR0 => b_reg_0_3_4316,
ADR1 => b_reg(13),
ADR2 => a_reg(13),
ADR3 => ab_xor_12_0,
O => N347
);
Sh23_f51_F : X_LUT4
generic map(
INIT => X"72D8",
LOC => "SLICE_X15Y33"
)
port map (
ADR0 => b_reg_0_3_4316,
ADR1 => a_reg(22),
ADR2 => ab_xor_23_0,
ADR3 => b_reg(22),
O => N342
);
Sh23_f51_G : X_LUT4
generic map(
INIT => X"B1E4",
LOC => "SLICE_X15Y33"
)
port map (
ADR0 => b_reg_0_3_4316,
ADR1 => b_reg(21),
ADR2 => ab_xor_20_0,
ADR3 => a_reg(21),
O => N343
);
Sh31_f51_F : X_LUT4
generic map(
INIT => X"66F0",
LOC => "SLICE_X12Y34"
)
port map (
ADR0 => a_reg(30),
ADR1 => b_reg(30),
ADR2 => ab_xor_31_0,
ADR3 => b_reg_0_3_4316,
O => N338
);
Sh31_f51_G : X_LUT4
generic map(
INIT => X"D1E2",
LOC => "SLICE_X12Y34"
)
port map (
ADR0 => a_reg(29),
ADR1 => b_reg_0_3_4316,
ADR2 => ab_xor_28_0,
ADR3 => b_reg(29),
O => N339
);
Sh19_f51_F : X_LUT4
generic map(
INIT => X"66F0",
LOC => "SLICE_X14Y22"
)
port map (
ADR0 => b_reg(18),
ADR1 => a_reg(18),
ADR2 => ab_xor_19_0,
ADR3 => b_reg_0_3_4316,
O => N344
);
Sh19_f51_G : X_LUT4
generic map(
INIT => X"A3AC",
LOC => "SLICE_X14Y22"
)
port map (
ADR0 => ab_xor_16_0,
ADR1 => a_reg(17),
ADR2 => b_reg_0_3_4316,
ADR3 => b_reg(17),
O => N345
);
Sh27_f51_F : X_LUT4
generic map(
INIT => X"66F0",
LOC => "SLICE_X14Y34"
)
port map (
ADR0 => a_reg(26),
ADR1 => b_reg(26),
ADR2 => ab_xor_27_0,
ADR3 => b_reg_0_3_4316,
O => N340
);
Sh27_f51_G : X_LUT4
generic map(
INIT => X"F066",
LOC => "SLICE_X14Y34"
)
port map (
ADR0 => a_reg(25),
ADR1 => b_reg(25),
ADR2 => ab_xor_24_0,
ADR3 => b_reg_0_3_4316,
O => N341
);
Sh12_F : X_LUT4
generic map(
INIT => X"8DD8",
LOC => "SLICE_X12Y15"
)
port map (
ADR0 => b_reg_0_1_4382,
ADR1 => ab_xor_11_0,
ADR2 => a_reg(12),
ADR3 => b_reg(12),
O => N334
);
Sh12_G : X_LUT4
generic map(
INIT => X"F606",
LOC => "SLICE_X12Y15"
)
port map (
ADR0 => a_reg(10),
ADR1 => b_reg(10),
ADR2 => b_reg_0_1_4382,
ADR3 => ab_xor_9_0,
O => N335
);
Sh20_F : X_LUT4
generic map(
INIT => X"BE14",
LOC => "SLICE_X15Y25"
)
port map (
ADR0 => b_reg_0_1_4382,
ADR1 => a_reg(20),
ADR2 => b_reg(20),
ADR3 => ab_xor_19_0,
O => N330
);
Sh20_G : X_LUT4
generic map(
INIT => X"B1E4",
LOC => "SLICE_X15Y25"
)
port map (
ADR0 => b_reg_0_1_4382,
ADR1 => a_reg(18),
ADR2 => ab_xor_17_0,
ADR3 => b_reg(18),
O => N331
);
Sh16_F : X_LUT4
generic map(
INIT => X"8DD8",
LOC => "SLICE_X12Y21"
)
port map (
ADR0 => b_reg_0_1_4382,
ADR1 => ab_xor_15_0,
ADR2 => a_reg(16),
ADR3 => b_reg(16),
O => N332
);
Sh16_G : X_LUT4
generic map(
INIT => X"8DD8",
LOC => "SLICE_X12Y21"
)
port map (
ADR0 => b_reg_0_1_4382,
ADR1 => ab_xor_13_0,
ADR2 => a_reg(14),
ADR3 => b_reg(14),
O => N333
);
Sh24_F : X_LUT4
generic map(
INIT => X"CC5A",
LOC => "SLICE_X14Y33"
)
port map (
ADR0 => b_reg(24),
ADR1 => ab_xor_23_0,
ADR2 => a_reg(24),
ADR3 => b_reg_0_1_4382,
O => N328
);
Sh24_G : X_LUT4
generic map(
INIT => X"BE14",
LOC => "SLICE_X14Y33"
)
port map (
ADR0 => b_reg_0_1_4382,
ADR1 => b_reg(22),
ADR2 => a_reg(22),
ADR3 => ab_xor_21_0,
O => N329
);
Sh28_F : X_LUT4
generic map(
INIT => X"CC5A",
LOC => "SLICE_X15Y35"
)
port map (
ADR0 => a_reg(28),
ADR1 => ab_xor_27_0,
ADR2 => b_reg(28),
ADR3 => b_reg_0_1_4382,
O => N326
);
Sh28_G : X_LUT4
generic map(
INIT => X"AA3C",
LOC => "SLICE_X15Y35"
)
port map (
ADR0 => ab_xor_25_0,
ADR1 => a_reg(26),
ADR2 => b_reg(26),
ADR3 => b_reg_0_1_4382,
O => N327
);
Sh123_f51_F : X_LUT4
generic map(
INIT => X"D18B",
LOC => "SLICE_X23Y28"
)
port map (
ADR0 => a(26),
ADR1 => N199_0,
ADR2 => a(27),
ADR3 => N200,
O => N496
);
Sh123_f51_G : X_LUT4
generic map(
INIT => X"B18D",
LOC => "SLICE_X23Y28"
)
port map (
ADR0 => a(25),
ADR1 => N179_0,
ADR2 => N178_0,
ADR3 => a(24),
O => N497
);
Sh127_f51_F : X_LUT4
generic map(
INIT => X"8DB1",
LOC => "SLICE_X21Y30"
)
port map (
ADR0 => N196_0,
ADR1 => a(31),
ADR2 => a(30),
ADR3 => N197,
O => N460
);
Sh127_f51_G : X_LUT4
generic map(
INIT => X"8BD1",
LOC => "SLICE_X21Y30"
)
port map (
ADR0 => a(29),
ADR1 => N172_0,
ADR2 => a(28),
ADR3 => N173_0,
O => N461
);
Sh145312 : X_LUT4
generic map(
INIT => X"F0CC",
LOC => "SLICE_X24Y15"
)
port map (
ADR0 => VCC,
ADR1 => Sh113,
ADR2 => Sh109,
ADR3 => a(2),
O => Sh145311_7899
);
Sh145311 : X_LUT4
generic map(
INIT => X"F0CC",
LOC => "SLICE_X24Y15"
)
port map (
ADR0 => VCC,
ADR1 => Sh105,
ADR2 => Sh101,
ADR3 => a(2),
O => Sh14531
);
Sh192_F : X_LUT4
generic map(
INIT => X"4EE4",
LOC => "SLICE_X12Y35"
)
port map (
ADR0 => b_reg_0_1_4382,
ADR1 => a_reg(0),
ADR2 => b_reg(31),
ADR3 => a_reg(31),
O => N410
);
Sh192_G : X_LUT4
generic map(
INIT => X"BE14",
LOC => "SLICE_X12Y35"
)
port map (
ADR0 => b_reg_0_1_4382,
ADR1 => b_reg(30),
ADR2 => a_reg(30),
ADR3 => ab_xor_29_0,
O => N411
);
b_reg_mux0000_2_37_SW0_F : X_LUT4
generic map(
INIT => X"FCAA",
LOC => "SLICE_X8Y3"
)
port map (
ADR0 => b_reg(2),
ADR1 => b_reg_mux0000_2_5_0,
ADR2 => b_reg_mux0000_2_13_0,
ADR3 => state_FSM_FFd2_4312,
O => N464
);
b_reg_mux0000_2_37_SW0_G : X_LUT4
generic map(
INIT => X"00CC",
LOC => "SLICE_X8Y3"
)
port map (
ADR0 => VCC,
ADR1 => b_reg(2),
ADR2 => VCC,
ADR3 => state_FSM_FFd2_4312,
O => N465
);
b_reg_mux0000_2_37_SW1_F : X_LUT4
generic map(
INIT => X"FCAA",
LOC => "SLICE_X8Y2"
)
port map (
ADR0 => b_reg(2),
ADR1 => b_reg_mux0000_2_5_0,
ADR2 => b_reg_mux0000_2_13_0,
ADR3 => state_FSM_FFd2_4312,
O => N466
);
b_reg_mux0000_2_37_SW1_G : X_LUT4
generic map(
INIT => X"FFCC",
LOC => "SLICE_X8Y2"
)
port map (
ADR0 => VCC,
ADR1 => b_reg(2),
ADR2 => VCC,
ADR3 => state_FSM_FFd2_4312,
O => N467
);
b_reg_mux0000_3_24_SW0_F : X_LUT4
generic map(
INIT => X"A5CC",
LOC => "SLICE_X2Y20"
)
port map (
ADR0 => Madd_b_pre_cy_2_Q,
ADR1 => b_reg(3),
ADR2 => swtch_led_3_OBUF_4256,
ADR3 => state_FSM_FFd2_4312,
O => N456
);
Sh5131_F : X_LUT4
generic map(
INIT => X"CACA",
LOC => "SLICE_X13Y25"
)
port map (
ADR0 => Sh19,
ADR1 => Sh11,
ADR2 => b_reg(3),
ADR3 => VCC,
O => N354
);
Sh5131_G : X_LUT4
generic map(
INIT => X"E4E4",
LOC => "SLICE_X13Y25"
)
port map (
ADR0 => b_reg(3),
ADR1 => Sh15,
ADR2 => Sh7,
ADR3 => VCC,
O => N355
);
Sh1597_F : X_LUT4
generic map(
INIT => X"F5A0",
LOC => "SLICE_X26Y26"
)
port map (
ADR0 => a(1),
ADR1 => VCC,
ADR2 => Sh1212_0,
ADR3 => Sh1232_0,
O => N468
);
Sh1597_G : X_LUT4
generic map(
INIT => X"E4E4",
LOC => "SLICE_X26Y26"
)
port map (
ADR0 => a(1),
ADR1 => Sh1152_0,
ADR2 => Sh1132_0,
ADR3 => VCC,
O => N469
);
Sh1781_F : X_LUT4
generic map(
INIT => X"DDDC",
LOC => "SLICE_X27Y14"
)
port map (
ADR0 => a(2),
ADR1 => Sh14612,
ADR2 => Sh14613_0,
ADR3 => Sh14616_0,
O => N322
);
Sh1781_G : X_LUT4
generic map(
INIT => X"FE0E",
LOC => "SLICE_X27Y14"
)
port map (
ADR0 => Sh13016_0,
ADR1 => Sh13013_0,
ADR2 => a(2),
ADR3 => Sh1307,
O => N323
);
Sh4431_F : X_LUT4
generic map(
INIT => X"CCF0",
LOC => "SLICE_X12Y22"
)
port map (
ADR0 => VCC,
ADR1 => Sh4,
ADR2 => Sh12,
ADR3 => b_reg(3),
O => N386
);
Sh4431_G : X_LUT4
generic map(
INIT => X"CCAA",
LOC => "SLICE_X12Y22"
)
port map (
ADR0 => Sh8,
ADR1 => Sh,
ADR2 => VCC,
ADR3 => b_reg(3),
O => N387
);
Sh6031_F : X_LUT4
generic map(
INIT => X"CCAA",
LOC => "SLICE_X12Y27"
)
port map (
ADR0 => Sh28,
ADR1 => Sh20,
ADR2 => VCC,
ADR3 => b_reg(3),
O => N384
);
Sh6031_G : X_LUT4
generic map(
INIT => X"AACC",
LOC => "SLICE_X12Y27"
)
port map (
ADR0 => Sh16,
ADR1 => Sh24,
ADR2 => VCC,
ADR3 => b_reg(3),
O => N385
);
Sh3631_F : X_LUT4
generic map(
INIT => X"EE44",
LOC => "SLICE_X13Y24"
)
port map (
ADR0 => b_reg(3),
ADR1 => Sh4,
ADR2 => VCC,
ADR3 => Sh28,
O => N360
);
Sh3631_G : X_LUT4
generic map(
INIT => X"FA0A",
LOC => "SLICE_X13Y24"
)
port map (
ADR0 => Sh,
ADR1 => VCC,
ADR2 => b_reg(3),
ADR3 => Sh24,
O => N361
);
Sh5231_F : X_LUT4
generic map(
INIT => X"F5A0",
LOC => "SLICE_X13Y18"
)
port map (
ADR0 => b_reg(3),
ADR1 => VCC,
ADR2 => Sh12,
ADR3 => Sh20,
O => N358
);
Sh5231_G : X_LUT4
generic map(
INIT => X"FA50",
LOC => "SLICE_X13Y18"
)
port map (
ADR0 => b_reg(3),
ADR1 => VCC,
ADR2 => Sh16,
ADR3 => Sh8,
O => N359
);
Sh4531_F : X_LUT4
generic map(
INIT => X"AACC",
LOC => "SLICE_X16Y26"
)
port map (
ADR0 => Sh5,
ADR1 => Sh13,
ADR2 => VCC,
ADR3 => b_reg(3),
O => N430
);
Sh4531_G : X_LUT4
generic map(
INIT => X"F0CC",
LOC => "SLICE_X16Y26"
)
port map (
ADR0 => VCC,
ADR1 => Sh9,
ADR2 => Sh1,
ADR3 => b_reg(3),
O => N431
);
Sh3731_F : X_LUT4
generic map(
INIT => X"FA50",
LOC => "SLICE_X14Y26"
)
port map (
ADR0 => b_reg(3),
ADR1 => VCC,
ADR2 => Sh5,
ADR3 => Sh29,
O => N390
);
Sh3731_G : X_LUT4
generic map(
INIT => X"FA50",
LOC => "SLICE_X14Y26"
)
port map (
ADR0 => b_reg(3),
ADR1 => VCC,
ADR2 => Sh1,
ADR3 => Sh25,
O => N391
);
Sh5331_F : X_LUT4
generic map(
INIT => X"AAF0",
LOC => "SLICE_X15Y27"
)
port map (
ADR0 => Sh13,
ADR1 => VCC,
ADR2 => Sh21,
ADR3 => b_reg(3),
O => N388
);
Sh5331_G : X_LUT4
generic map(
INIT => X"E4E4",
LOC => "SLICE_X15Y27"
)
port map (
ADR0 => b_reg(3),
ADR1 => Sh17,
ADR2 => Sh9,
ADR3 => VCC,
O => N389
);
Sh4631_F : X_LUT4
generic map(
INIT => X"AAF0",
LOC => "SLICE_X14Y28"
)
port map (
ADR0 => Sh6,
ADR1 => VCC,
ADR2 => Sh14,
ADR3 => b_reg(3),
O => N422
);
Sh4631_G : X_LUT4
generic map(
INIT => X"E4E4",
LOC => "SLICE_X14Y28"
)
port map (
ADR0 => b_reg(3),
ADR1 => Sh10,
ADR2 => Sh2,
ADR3 => VCC,
O => N423
);
Sh3831_F : X_LUT4
generic map(
INIT => X"EE22",
LOC => "SLICE_X14Y31"
)
port map (
ADR0 => Sh6,
ADR1 => b_reg(3),
ADR2 => VCC,
ADR3 => Sh30,
O => N394
);
Sh3831_G : X_LUT4
generic map(
INIT => X"D8D8",
LOC => "SLICE_X14Y31"
)
port map (
ADR0 => b_reg(3),
ADR1 => Sh26,
ADR2 => Sh2,
ADR3 => VCC,
O => N395
);
Sh5431_F : X_LUT4
generic map(
INIT => X"AAF0",
LOC => "SLICE_X12Y28"
)
port map (
ADR0 => Sh14,
ADR1 => VCC,
ADR2 => Sh22_4347,
ADR3 => b_reg(3),
O => N392
);
Sh5431_G : X_LUT4
generic map(
INIT => X"CCAA",
LOC => "SLICE_X12Y28"
)
port map (
ADR0 => Sh18,
ADR1 => Sh10,
ADR2 => VCC,
ADR3 => b_reg(3),
O => N393
);
Sh4731_F : X_LUT4
generic map(
INIT => X"E4E4",
LOC => "SLICE_X13Y21"
)
port map (
ADR0 => b_reg(3),
ADR1 => Sh15,
ADR2 => Sh7,
ADR3 => VCC,
O => N398
);
Sh4731_G : X_LUT4
generic map(
INIT => X"EE44",
LOC => "SLICE_X13Y21"
)
port map (
ADR0 => b_reg(3),
ADR1 => Sh11,
ADR2 => VCC,
ADR3 => Sh3,
O => N399
);
Sh6331_F : X_LUT4
generic map(
INIT => X"CCAA",
LOC => "SLICE_X12Y33"
)
port map (
ADR0 => Sh31,
ADR1 => Sh23_4457,
ADR2 => VCC,
ADR3 => b_reg(3),
O => N396
);
Sh6331_G : X_LUT4
generic map(
INIT => X"FC30",
LOC => "SLICE_X12Y33"
)
port map (
ADR0 => VCC,
ADR1 => b_reg(3),
ADR2 => Sh27,
ADR3 => Sh19,
O => N397
);
Sh3931_F : X_LUT4
generic map(
INIT => X"D8D8",
LOC => "SLICE_X13Y28"
)
port map (
ADR0 => b_reg(3),
ADR1 => Sh31,
ADR2 => Sh7,
ADR3 => VCC,
O => N364
);
Sh3931_G : X_LUT4
generic map(
INIT => X"DD88",
LOC => "SLICE_X13Y28"
)
port map (
ADR0 => b_reg(3),
ADR1 => Sh27,
ADR2 => VCC,
ADR3 => Sh3,
O => N365
);
Sh5531_F : X_LUT4
generic map(
INIT => X"CFC0",
LOC => "SLICE_X13Y30"
)
port map (
ADR0 => VCC,
ADR1 => Sh15,
ADR2 => b_reg(3),
ADR3 => Sh23_4457,
O => N362
);
Sh5531_G : X_LUT4
generic map(
INIT => X"FA0A",
LOC => "SLICE_X13Y30"
)
port map (
ADR0 => Sh19,
ADR1 => VCC,
ADR2 => b_reg(3),
ADR3 => Sh11,
O => N363
);
Sh5631_F : X_LUT4
generic map(
INIT => X"FA50",
LOC => "SLICE_X13Y27"
)
port map (
ADR0 => b_reg(3),
ADR1 => VCC,
ADR2 => Sh24,
ADR3 => Sh16,
O => N366
);
Sh5631_G : X_LUT4
generic map(
INIT => X"D8D8",
LOC => "SLICE_X13Y27"
)
port map (
ADR0 => b_reg(3),
ADR1 => Sh12,
ADR2 => Sh20,
ADR3 => VCC,
O => N367
);
Sh4831_F : X_LUT4
generic map(
INIT => X"BB88",
LOC => "SLICE_X12Y25"
)
port map (
ADR0 => Sh8,
ADR1 => b_reg(3),
ADR2 => VCC,
ADR3 => Sh16,
O => N350
);
Sh4831_G : X_LUT4
generic map(
INIT => X"F3C0",
LOC => "SLICE_X12Y25"
)
port map (
ADR0 => VCC,
ADR1 => b_reg(3),
ADR2 => Sh4,
ADR3 => Sh12,
O => N351
);
Sh4931_F : X_LUT4
generic map(
INIT => X"CCF0",
LOC => "SLICE_X14Y24"
)
port map (
ADR0 => VCC,
ADR1 => Sh9,
ADR2 => Sh17,
ADR3 => b_reg(3),
O => N372
);
Sh4931_G : X_LUT4
generic map(
INIT => X"F3C0",
LOC => "SLICE_X14Y24"
)
port map (
ADR0 => VCC,
ADR1 => b_reg(3),
ADR2 => Sh5,
ADR3 => Sh13,
O => N373
);
Sh5931_F : X_LUT4
generic map(
INIT => X"B8B8",
LOC => "SLICE_X12Y31"
)
port map (
ADR0 => Sh19,
ADR1 => b_reg(3),
ADR2 => Sh27,
ADR3 => VCC,
O => N380
);
Sh5931_G : X_LUT4
generic map(
INIT => X"E2E2",
LOC => "SLICE_X12Y31"
)
port map (
ADR0 => Sh23_4457,
ADR1 => b_reg(3),
ADR2 => Sh15,
ADR3 => VCC,
O => N381
);
b_reg_mux0000_5_24_SW0_F : X_LUT4
generic map(
INIT => X"AC5C",
LOC => "SLICE_X3Y17"
)
port map (
ADR0 => swtch_led_5_OBUF_4258,
ADR1 => b_reg(5),
ADR2 => state_FSM_FFd2_4312,
ADR3 => Madd_b_pre_cy_4_0,
O => N448
);
b_reg_mux0000_5_24_SW0_G : X_LUT4
generic map(
INIT => X"0F00",
LOC => "SLICE_X3Y17"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => state_FSM_FFd2_4312,
ADR3 => b_reg(5),
O => N449
);
b_reg_mux0000_5_24_SW1_F : X_LUT4
generic map(
INIT => X"B874",
LOC => "SLICE_X2Y17"
)
port map (
ADR0 => Madd_b_pre_cy_4_0,
ADR1 => state_FSM_FFd2_4312,
ADR2 => b_reg(5),
ADR3 => swtch_led_5_OBUF_4258,
O => N450
);
b_reg_mux0000_5_24_SW1_G : X_LUT4
generic map(
INIT => X"EEEE",
LOC => "SLICE_X2Y17"
)
port map (
ADR0 => b_reg(5),
ADR1 => state_FSM_FFd2_4312,
ADR2 => VCC,
ADR3 => VCC,
O => N451
);
b_reg_mux0000_8_21_F : X_LUT4
generic map(
INIT => X"BBAA",
LOC => "SLICE_X16Y15"
)
port map (
ADR0 => b_reg_mux0000_10_10_0,
ADR1 => state_FSM_FFd2_4312,
ADR2 => VCC,
ADR3 => b_reg(8),
O => N532
);
b_reg_mux0000_8_21_G : X_LUT4
generic map(
INIT => X"EFEA",
LOC => "SLICE_X16Y15"
)
port map (
ADR0 => b_reg_mux0000_10_10_0,
ADR1 => state_FSM_FFd1_4311,
ADR2 => state_FSM_FFd2_4312,
ADR3 => b_reg(8),
O => N533
);
b_reg_8 : X_FF
generic map(
LOC => "SLICE_X16Y15",
INIT => '0'
)
port map (
I => b_reg_8_DXMUX_9240,
CE => VCC,
CLK => b_reg_8_CLKINV_9222,
SET => GND,
RST => b_reg_8_FFX_RSTAND_9245,
O => b_reg(8)
);
b_reg_8_FFX_RSTAND : X_BUF
generic map(
LOC => "SLICE_X16Y15",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_8_FFX_RSTAND_9245
);
b_reg_mux0000_9_21_F : X_LUT4
generic map(
INIT => X"BABA",
LOC => "SLICE_X16Y14"
)
port map (
ADR0 => b_reg_mux0000_10_10_0,
ADR1 => state_FSM_FFd2_4312,
ADR2 => b_reg(9),
ADR3 => VCC,
O => N530
);
b_reg_mux0000_9_21_G : X_LUT4
generic map(
INIT => X"FEBA",
LOC => "SLICE_X16Y14"
)
port map (
ADR0 => b_reg_mux0000_10_10_0,
ADR1 => state_FSM_FFd2_4312,
ADR2 => b_reg(9),
ADR3 => state_FSM_FFd1_4311,
O => N531
);
b_reg_9 : X_FF
generic map(
LOC => "SLICE_X16Y14",
INIT => '0'
)
port map (
I => b_reg_9_DXMUX_9276,
CE => VCC,
CLK => b_reg_9_CLKINV_9258,
SET => GND,
RST => b_reg_9_FFX_RSTAND_9281,
O => b_reg(9)
);
b_reg_9_FFX_RSTAND : X_BUF
generic map(
LOC => "SLICE_X16Y14",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_9_FFX_RSTAND_9281
);
b_reg_mux0000_6_34_SW0_F : X_LUT4
generic map(
INIT => X"FCAC",
LOC => "SLICE_X3Y13"
)
port map (
ADR0 => b_reg_mux0000_6_3_0,
ADR1 => b_reg(6),
ADR2 => state_FSM_FFd2_4312,
ADR3 => b_reg_mux0000_6_12_0,
O => N444
);
b_reg_mux0000_6_34_SW0_G : X_LUT4
generic map(
INIT => X"0F00",
LOC => "SLICE_X3Y13"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => state_FSM_FFd2_4312,
ADR3 => b_reg(6),
O => N445
);
b_reg_mux0000_6_34_SW1_F : X_LUT4
generic map(
INIT => X"FCB8",
LOC => "SLICE_X2Y13"
)
port map (
ADR0 => b_reg_mux0000_6_12_0,
ADR1 => state_FSM_FFd2_4312,
ADR2 => b_reg(6),
ADR3 => b_reg_mux0000_6_3_0,
O => N446
);
b_reg_mux0000_6_34_SW1_G : X_LUT4
generic map(
INIT => X"EEEE",
LOC => "SLICE_X2Y13"
)
port map (
ADR0 => b_reg(6),
ADR1 => state_FSM_FFd2_4312,
ADR2 => VCC,
ADR3 => VCC,
O => N447
);
Sh1_f5_F : X_LUT4
generic map(
INIT => X"3F30",
LOC => "SLICE_X13Y35"
)
port map (
ADR0 => VCC,
ADR1 => a_reg(0),
ADR2 => b_reg_0_3_4316,
ADR3 => a_reg(1),
O => N404
);
Sh1_f5_G : X_LUT4
generic map(
INIT => X"4EE4",
LOC => "SLICE_X13Y35"
)
port map (
ADR0 => b_reg_0_3_4316,
ADR1 => ab_xor_31_0,
ADR2 => b_reg(30),
ADR3 => a_reg(30),
O => N405
);
Sh23 : X_LUT4
generic map(
INIT => X"A3AC",
LOC => "SLICE_X13Y32"
)
port map (
ADR0 => a_reg(1),
ADR1 => a_reg(2),
ADR2 => b_reg_0_3_4316,
ADR3 => b_reg_2_1_4381,
O => Sh211
);
Sh22 : X_LUT4
generic map(
INIT => X"7D28",
LOC => "SLICE_X13Y32"
)
port map (
ADR0 => b_reg_0_3_4316,
ADR1 => a_reg(31),
ADR2 => b_reg(31),
ADR3 => a_reg(0),
O => Sh210
);
Sh5_f5_F : X_LUT4
generic map(
INIT => X"DE12",
LOC => "SLICE_X12Y19"
)
port map (
ADR0 => a_reg(5),
ADR1 => b_reg_0_3_4316,
ADR2 => b_reg(5),
ADR3 => ab_xor_4_0,
O => N476
);
Sh5_f5_G : X_LUT4
generic map(
INIT => X"7B48",
LOC => "SLICE_X12Y19"
)
port map (
ADR0 => b_reg_2_1_4381,
ADR1 => b_reg_0_3_4316,
ADR2 => a_reg(2),
ADR3 => ab_xor_3_0,
O => N477
);
b_reg_mux0000_7_24_SW0_F : X_LUT4
generic map(
INIT => X"D872",
LOC => "SLICE_X12Y8"
)
port map (
ADR0 => state_FSM_FFd2_4312,
ADR1 => Madd_b_pre_cy_6_Q,
ADR2 => b_reg(7),
ADR3 => swtch_led_7_OBUF_4260,
O => N440
);
b_reg_mux0000_7_24_SW0_G : X_LUT4
generic map(
INIT => X"3030",
LOC => "SLICE_X12Y8"
)
port map (
ADR0 => VCC,
ADR1 => state_FSM_FFd2_4312,
ADR2 => b_reg(7),
ADR3 => VCC,
O => N441
);
b_reg_mux0000_7_24_SW1_F : X_LUT4
generic map(
INIT => X"D872",
LOC => "SLICE_X9Y3"
)
port map (
ADR0 => state_FSM_FFd2_4312,
ADR1 => Madd_b_pre_cy_6_Q,
ADR2 => b_reg(7),
ADR3 => swtch_led_7_OBUF_4260,
O => N442
);
b_reg_mux0000_7_24_SW1_G : X_LUT4
generic map(
INIT => X"FAFA",
LOC => "SLICE_X9Y3"
)
port map (
ADR0 => state_FSM_FFd2_4312,
ADR1 => VCC,
ADR2 => b_reg(7),
ADR3 => VCC,
O => N443
);
Sh6_f5_F : X_LUT4
generic map(
INIT => X"DE12",
LOC => "SLICE_X12Y18"
)
port map (
ADR0 => b_reg(6),
ADR1 => b_reg_0_3_4316,
ADR2 => a_reg(6),
ADR3 => ab_xor_5_0,
O => N462
);
Sh6_f5_G : X_LUT4
generic map(
INIT => X"D1E2",
LOC => "SLICE_X12Y18"
)
port map (
ADR0 => a_reg(4),
ADR1 => b_reg_0_3_4316,
ADR2 => ab_xor_3_0,
ADR3 => b_reg(4),
O => N463
);
Sh9_f5_F : X_LUT4
generic map(
INIT => X"BE14",
LOC => "SLICE_X15Y15"
)
port map (
ADR0 => b_reg_0_3_4316,
ADR1 => b_reg(9),
ADR2 => a_reg(9),
ADR3 => ab_xor_8_0,
O => N474
);
Sh9_f5_G : X_LUT4
generic map(
INIT => X"74B8",
LOC => "SLICE_X15Y15"
)
port map (
ADR0 => a_reg(6),
ADR1 => b_reg_0_3_4316,
ADR2 => ab_xor_7_0,
ADR3 => b_reg(6),
O => N475
);
b_reg_mux0000_0_F : X_LUT4
generic map(
INIT => X"444E",
LOC => "SLICE_X14Y15"
)
port map (
ADR0 => state_FSM_FFd2_4312,
ADR1 => b_reg(0),
ADR2 => Madd_b_pre_cy_0_Q,
ADR3 => state_FSM_FFd1_4311,
O => N524
);
b_reg_mux0000_0_G : X_LUT4
generic map(
INIT => X"EE4E",
LOC => "SLICE_X14Y15"
)
port map (
ADR0 => state_FSM_FFd2_4312,
ADR1 => b_reg(0),
ADR2 => Madd_b_pre_cy_0_Q,
ADR3 => state_FSM_FFd1_4311,
O => N525
);
b_reg_0_1 : X_FF
generic map(
LOC => "SLICE_X14Y15",
INIT => '0'
)
port map (
I => b_reg_0_1_DXMUX_9538,
CE => VCC,
CLK => b_reg_0_1_CLKINV_9521,
SET => GND,
RST => b_reg_0_1_FFX_RSTAND_9543,
O => b_reg_0_1_4382
);
b_reg_0_1_FFX_RSTAND : X_BUF
generic map(
LOC => "SLICE_X14Y15",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_0_1_FFX_RSTAND_9543
);
Mmux_hex_digit_i_mux0001_4 : X_LUT4
generic map(
INIT => X"FC30",
LOC => "SLICE_X28Y15"
)
port map (
ADR0 => VCC,
ADR1 => LED_flash_cnt(8),
ADR2 => b_reg(12),
ADR3 => b_reg(8),
O => Mmux_hex_digit_i_mux0001_4_9562
);
Mmux_hex_digit_i_mux0001_3 : X_LUT4
generic map(
INIT => X"E2E2",
LOC => "SLICE_X28Y15"
)
port map (
ADR0 => b_reg(4),
ADR1 => LED_flash_cnt(8),
ADR2 => b_reg(0),
ADR3 => VCC,
O => Mmux_hex_digit_i_mux0001_3_9570
);
hex_digit_i_0 : X_FF
generic map(
LOC => "SLICE_X28Y15",
INIT => '0'
)
port map (
I => hex_digit_i_0_DXMUX_9574,
CE => VCC,
CLK => hex_digit_i_0_CLKINV_9555,
SET => GND,
RST => hex_digit_i_0_FFX_RSTAND_9579,
O => hex_digit_i(0)
);
hex_digit_i_0_FFX_RSTAND : X_BUF
generic map(
LOC => "SLICE_X28Y15",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => hex_digit_i_0_FFX_RSTAND_9579
);
b_reg_mux0000_11_10_SW0_F : X_LUT4
generic map(
INIT => X"FAD8",
LOC => "SLICE_X12Y11"
)
port map (
ADR0 => state_FSM_FFd2_4312,
ADR1 => Madd_b_pre_cy_6_Q,
ADR2 => b_reg(11),
ADR3 => swtch_led_7_OBUF_4260,
O => N436
);
b_reg_mux0000_11_10_SW0_G : X_LUT4
generic map(
INIT => X"3300",
LOC => "SLICE_X12Y11"
)
port map (
ADR0 => VCC,
ADR1 => state_FSM_FFd2_4312,
ADR2 => VCC,
ADR3 => b_reg(11),
O => N437
);
b_reg_mux0000_11_10_SW1_F : X_LUT4
generic map(
INIT => X"FCAC",
LOC => "SLICE_X13Y11"
)
port map (
ADR0 => swtch_led_7_OBUF_4260,
ADR1 => b_reg(11),
ADR2 => state_FSM_FFd2_4312,
ADR3 => Madd_b_pre_cy_6_Q,
O => N438
);
b_reg_mux0000_11_10_SW1_G : X_LUT4
generic map(
INIT => X"FAFA",
LOC => "SLICE_X13Y11"
)
port map (
ADR0 => b_reg(11),
ADR1 => VCC,
ADR2 => state_FSM_FFd2_4312,
ADR3 => VCC,
O => N439
);
i_cnt_mux0001_0_562 : X_LUT4
generic map(
INIT => X"FCCC",
LOC => "SLICE_X19Y14"
)
port map (
ADR0 => VCC,
ADR1 => i_cnt(3),
ADR2 => state_FSM_FFd1_4311,
ADR3 => i_cnt_mux0001_0_25_0,
O => i_cnt_mux0001_0_561_9649
);
i_cnt_mux0001_0_561 : X_LUT4
generic map(
INIT => X"B080",
LOC => "SLICE_X19Y14"
)
port map (
ADR0 => N514_0,
ADR1 => i_cnt(3),
ADR2 => state_FSM_FFd1_4311,
ADR3 => i_cnt_mux0001_0_25_0,
O => i_cnt_mux0001_0_56
);
i_cnt_3 : X_FF
generic map(
LOC => "SLICE_X19Y14",
INIT => '0'
)
port map (
I => i_cnt_3_DXMUX_9660,
CE => VCC,
CLK => i_cnt_3_CLKINV_9642,
SET => GND,
RST => i_cnt_3_FFX_RSTAND_9665,
O => i_cnt(3)
);
i_cnt_3_FFX_RSTAND : X_BUF
generic map(
LOC => "SLICE_X19Y14",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => i_cnt_3_FFX_RSTAND_9665
);
Mmux_hex_digit_i_mux0001_41 : X_LUT4
generic map(
INIT => X"CCAA",
LOC => "SLICE_X27Y12"
)
port map (
ADR0 => b_reg(13),
ADR1 => b_reg(9),
ADR2 => VCC,
ADR3 => LED_flash_cnt(8),
O => Mmux_hex_digit_i_mux0001_41_9684
);
Mmux_hex_digit_i_mux0001_31 : X_LUT4
generic map(
INIT => X"F0AA",
LOC => "SLICE_X27Y12"
)
port map (
ADR0 => b_reg(5),
ADR1 => VCC,
ADR2 => b_reg(1),
ADR3 => LED_flash_cnt(8),
O => Mmux_hex_digit_i_mux0001_31_9692
);
hex_digit_i_1 : X_FF
generic map(
LOC => "SLICE_X27Y12",
INIT => '0'
)
port map (
I => hex_digit_i_1_DXMUX_9696,
CE => VCC,
CLK => hex_digit_i_1_CLKINV_9677,
SET => GND,
RST => hex_digit_i_1_FFX_RSTAND_9701,
O => hex_digit_i(1)
);
hex_digit_i_1_FFX_RSTAND : X_BUF
generic map(
LOC => "SLICE_X27Y12",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => hex_digit_i_1_FFX_RSTAND_9701
);
Mmux_hex_digit_i_mux0001_42 : X_LUT4
generic map(
INIT => X"FA50",
LOC => "SLICE_X27Y13"
)
port map (
ADR0 => LED_flash_cnt(8),
ADR1 => VCC,
ADR2 => b_reg(14),
ADR3 => b_reg(10),
O => Mmux_hex_digit_i_mux0001_42_9720
);
Mmux_hex_digit_i_mux0001_32 : X_LUT4
generic map(
INIT => X"AAF0",
LOC => "SLICE_X27Y13"
)
port map (
ADR0 => b_reg(2),
ADR1 => VCC,
ADR2 => b_reg(6),
ADR3 => LED_flash_cnt(8),
O => Mmux_hex_digit_i_mux0001_32_9728
);
hex_digit_i_2 : X_FF
generic map(
LOC => "SLICE_X27Y13",
INIT => '0'
)
port map (
I => hex_digit_i_2_DXMUX_9732,
CE => VCC,
CLK => hex_digit_i_2_CLKINV_9713,
SET => GND,
RST => hex_digit_i_2_FFX_RSTAND_9737,
O => hex_digit_i(2)
);
hex_digit_i_2_FFX_RSTAND : X_BUF
generic map(
LOC => "SLICE_X27Y13",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => hex_digit_i_2_FFX_RSTAND_9737
);
Sh1222 : X_LUT4
generic map(
INIT => X"C5A3",
LOC => "SLICE_X22Y28"
)
port map (
ADR0 => a(25),
ADR1 => a(26),
ADR2 => N211_0,
ADR3 => Mxor_ba_xor_Result_25_1_SW1_O,
O => Sh1222_10228
);
Mxor_ba_xor_Result_11_1_SW1 : X_LUT4
generic map(
INIT => X"A0AF",
LOC => "SLICE_X18Y13"
)
port map (
ADR0 => b_reg(10),
ADR1 => VCC,
ADR2 => a(0),
ADR3 => b_reg(11),
O => Mxor_ba_xor_Result_11_1_SW1_O_pack_1
);
Sh1072 : X_LUT4
generic map(
INIT => X"8BD1",
LOC => "SLICE_X18Y13"
)
port map (
ADR0 => N251_0,
ADR1 => a(11),
ADR2 => Mxor_ba_xor_Result_11_1_SW1_O,
ADR3 => a(10),
O => Sh1072_10252
);
Mxor_ba_xor_Result_19_1_SW1 : X_LUT4
generic map(
INIT => X"A0F5",
LOC => "SLICE_X22Y24"
)
port map (
ADR0 => a(0),
ADR1 => VCC,
ADR2 => b_reg(18),
ADR3 => b_reg(19),
O => Mxor_ba_xor_Result_19_1_SW1_O_pack_1
);
Sh1152 : X_LUT4
generic map(
INIT => X"8BD1",
LOC => "SLICE_X22Y24"
)
port map (
ADR0 => a(19),
ADR1 => N205_0,
ADR2 => a(18),
ADR3 => Mxor_ba_xor_Result_19_1_SW1_O,
O => Sh1152_10276
);
Mxor_ba_xor_Result_27_1_SW1 : X_LUT4
generic map(
INIT => X"88BB",
LOC => "SLICE_X22Y31"
)
port map (
ADR0 => b_reg(26),
ADR1 => a(0),
ADR2 => VCC,
ADR3 => b_reg(27),
O => N200_pack_1
);
Sh1232 : X_LUT4
generic map(
INIT => X"C5A3",
LOC => "SLICE_X22Y31"
)
port map (
ADR0 => a(26),
ADR1 => a(27),
ADR2 => N199_0,
ADR3 => N200,
O => Sh1232_10300
);
Mxor_ba_xor_Result_21_1_SW1 : X_LUT4
generic map(
INIT => X"AF05",
LOC => "SLICE_X18Y33"
)
port map (
ADR0 => a(0),
ADR1 => VCC,
ADR2 => b_reg(22),
ADR3 => b_reg(21),
O => Mxor_ba_xor_Result_21_1_SW1_O_pack_1
);
Sh1182 : X_LUT4
generic map(
INIT => X"D81B",
LOC => "SLICE_X18Y33"
)
port map (
ADR0 => a(21),
ADR1 => N214_0,
ADR2 => Mxor_ba_xor_Result_21_1_SW1_O,
ADR3 => a(22),
O => Sh1182_10324
);
Mxor_ba_xor_Result_29_1_SW1 : X_LUT4
generic map(
INIT => X"88DD",
LOC => "SLICE_X20Y31"
)
port map (
ADR0 => a(0),
ADR1 => b_reg(29),
ADR2 => VCC,
ADR3 => b_reg(30),
O => Mxor_ba_xor_Result_29_1_SW1_O_pack_1
);
Sh1262 : X_LUT4
generic map(
INIT => X"8DB1",
LOC => "SLICE_X20Y31"
)
port map (
ADR0 => a(30),
ADR1 => N208_0,
ADR2 => Mxor_ba_xor_Result_29_1_SW1_O,
ADR3 => a(29),
O => Sh1262_10348
);
Sh982 : X_LUT4
generic map(
INIT => X"B1E4",
LOC => "SLICE_X26Y17"
)
port map (
ADR0 => a(0),
ADR1 => b_reg(2),
ADR2 => b_reg(1),
ADR3 => a(2),
O => Sh982_pack_1
);
Sh1343 : X_LUT4
generic map(
INIT => X"5044",
LOC => "SLICE_X26Y17"
)
port map (
ADR0 => a(3),
ADR1 => Sh982_4493,
ADR2 => Sh962_0,
ADR3 => a(1),
O => Sh13016
);
Mxor_ba_xor_Result_23_1_SW1 : X_LUT4
generic map(
INIT => X"F033",
LOC => "SLICE_X18Y28"
)
port map (
ADR0 => VCC,
ADR1 => b_reg(23),
ADR2 => b_reg(22),
ADR3 => a(0),
O => Mxor_ba_xor_Result_23_1_SW1_O_pack_1
);
Sh1192 : X_LUT4
generic map(
INIT => X"8BD1",
LOC => "SLICE_X18Y28"
)
port map (
ADR0 => a(23),
ADR1 => N202_0,
ADR2 => a(22),
ADR3 => Mxor_ba_xor_Result_23_1_SW1_O,
O => Sh1192_10396
);
Mxor_ba_xor_Result_31_1_SW1 : X_LUT4
generic map(
INIT => X"AA33",
LOC => "SLICE_X21Y31"
)
port map (
ADR0 => b_reg(30),
ADR1 => b_reg(31),
ADR2 => VCC,
ADR3 => a(0),
O => N197_pack_1
);
Sh1272 : X_LUT4
generic map(
INIT => X"8DB1",
LOC => "SLICE_X21Y31"
)
port map (
ADR0 => N196_0,
ADR1 => a(31),
ADR2 => a(30),
ADR3 => N197,
O => Sh1272_10420
);
Sh12932 : X_LUT4
generic map(
INIT => X"AFAC",
LOC => "SLICE_X20Y14"
)
port map (
ADR0 => Sh1297_0,
ADR1 => Sh12913_0,
ADR2 => a(2),
ADR3 => Sh12916_0,
O => Sh129_pack_1
);
Sh1611 : X_LUT4
generic map(
INIT => X"CFC0",
LOC => "SLICE_X20Y14"
)
port map (
ADR0 => VCC,
ADR1 => Sh145,
ADR2 => a(4),
ADR3 => Sh129,
O => Sh161
);
Sh13831 : X_LUT4
generic map(
INIT => X"E4E4",
LOC => "SLICE_X27Y18"
)
port map (
ADR0 => a(2),
ADR1 => Sh13820,
ADR2 => Sh13420,
ADR3 => VCC,
O => Sh138_pack_1
);
Sh1701 : X_LUT4
generic map(
INIT => X"FA50",
LOC => "SLICE_X27Y18"
)
port map (
ADR0 => a(4),
ADR1 => VCC,
ADR2 => Sh138,
ADR3 => Sh154_0,
O => Sh170
);
Sh107_f51 : X_LUT4
generic map(
INIT => X"ACAC",
LOC => "SLICE_X24Y22"
)
port map (
ADR0 => Sh1052_0,
ADR1 => Sh1072_0,
ADR2 => a(1),
ADR3 => VCC,
O => Sh107_pack_1
);
Sh1437 : X_LUT4
generic map(
INIT => X"AFA0",
LOC => "SLICE_X24Y22"
)
port map (
ADR0 => Sh99_0,
ADR1 => VCC,
ADR2 => a(3),
ADR3 => Sh107,
O => Sh1437_10492
);
Sh15532 : X_LUT4
generic map(
INIT => X"FE54",
LOC => "SLICE_X27Y24"
)
port map (
ADR0 => a(2),
ADR1 => Sh15513_0,
ADR2 => Sh15516_0,
ADR3 => Sh1557,
O => Sh155_pack_1
);
Sh1711 : X_LUT4
generic map(
INIT => X"E4E4",
LOC => "SLICE_X27Y24"
)
port map (
ADR0 => a(4),
ADR1 => Sh139,
ADR2 => Sh155,
ADR3 => VCC,
O => Sh171
);
Sh15632 : X_LUT4
generic map(
INIT => X"B8B8",
LOC => "SLICE_X23Y19"
)
port map (
ADR0 => Sh1567_0,
ADR1 => a(2),
ADR2 => Sh1287_0,
ADR3 => VCC,
O => Sh156_pack_1
);
Sh1721 : X_LUT4
generic map(
INIT => X"FA0A",
LOC => "SLICE_X23Y19"
)
port map (
ADR0 => Sh140,
ADR1 => VCC,
ADR2 => a(4),
ADR3 => Sh156,
O => Sh172
);
Sh13232 : X_LUT4
generic map(
INIT => X"FCAA",
LOC => "SLICE_X23Y21"
)
port map (
ADR0 => Sh13220_0,
ADR1 => Sh12816_0,
ADR2 => Sh12813_0,
ADR3 => a(2),
O => Sh132_pack_1
);
Sh1801 : X_LUT4
generic map(
INIT => X"EE44",
LOC => "SLICE_X23Y21"
)
port map (
ADR0 => a(4),
ADR1 => Sh148_0,
ADR2 => VCC,
ADR3 => Sh132,
O => Sh180
);
Sh14932 : X_LUT4
generic map(
INIT => X"DD88",
LOC => "SLICE_X23Y15"
)
port map (
ADR0 => a(2),
ADR1 => Sh1497_0,
ADR2 => VCC,
ADR3 => Sh1537_0,
O => Sh149_pack_1
);
Sh1651 : X_LUT4
generic map(
INIT => X"EE44",
LOC => "SLICE_X23Y15"
)
port map (
ADR0 => a(4),
ADR1 => Sh133,
ADR2 => VCC,
ADR3 => Sh149,
O => Sh165
);
Sh15732 : X_LUT4
generic map(
INIT => X"FC0C",
LOC => "SLICE_X20Y16"
)
port map (
ADR0 => VCC,
ADR1 => Sh1297_0,
ADR2 => a(2),
ADR3 => Sh1577_0,
O => Sh157_pack_1
);
Sh1731 : X_LUT4
generic map(
INIT => X"FC0C",
LOC => "SLICE_X20Y16"
)
port map (
ADR0 => VCC,
ADR1 => Sh141,
ADR2 => a(4),
ADR3 => Sh157,
O => Sh173
);
Sh13432 : X_LUT4
generic map(
INIT => X"EEE4",
LOC => "SLICE_X26Y15"
)
port map (
ADR0 => a(2),
ADR1 => Sh13420,
ADR2 => Sh13013_0,
ADR3 => Sh13016_0,
O => Sh134_pack_1
);
Sh1661 : X_LUT4
generic map(
INIT => X"B8B8",
LOC => "SLICE_X26Y15"
)
port map (
ADR0 => Sh150_0,
ADR1 => a(4),
ADR2 => Sh134,
ADR3 => VCC,
O => Sh166
);
Sh15832 : X_LUT4
generic map(
INIT => X"DDD8",
LOC => "SLICE_X26Y22"
)
port map (
ADR0 => a(2),
ADR1 => Sh1587,
ADR2 => Sh15816_0,
ADR3 => Sh15813_0,
O => Sh158_pack_1
);
Sh1741 : X_LUT4
generic map(
INIT => X"FC0C",
LOC => "SLICE_X26Y22"
)
port map (
ADR0 => VCC,
ADR1 => Sh142,
ADR2 => a(4),
ADR3 => Sh158,
O => Sh174
);
Sh15132 : X_LUT4
generic map(
INIT => X"CCFA",
LOC => "SLICE_X22Y21"
)
port map (
ADR0 => Sh15113_0,
ADR1 => Sh1517,
ADR2 => Sh15116_0,
ADR3 => a(2),
O => Sh151_pack_1
);
Sh1671 : X_LUT4
generic map(
INIT => X"F0AA",
LOC => "SLICE_X22Y21"
)
port map (
ADR0 => Sh135,
ADR1 => VCC,
ADR2 => Sh151,
ADR3 => a(4),
O => Sh167
);
Sh15232 : X_LUT4
generic map(
INIT => X"CFC0",
LOC => "SLICE_X22Y17"
)
port map (
ADR0 => VCC,
ADR1 => Sh1527_0,
ADR2 => a(2),
ADR3 => Sh1567_0,
O => Sh152_pack_1
);
Sh1681 : X_LUT4
generic map(
INIT => X"F3C0",
LOC => "SLICE_X22Y17"
)
port map (
ADR0 => VCC,
ADR1 => a(4),
ADR2 => Sh152,
ADR3 => Sh136,
O => Sh168
);
Sh12832 : X_LUT4
generic map(
INIT => X"FE54",
LOC => "SLICE_X22Y20"
)
port map (
ADR0 => a(2),
ADR1 => Sh12813_0,
ADR2 => Sh12816_0,
ADR3 => Sh1287_0,
O => Sh128_pack_1
);
Sh1761 : X_LUT4
generic map(
INIT => X"FC30",
LOC => "SLICE_X22Y20"
)
port map (
ADR0 => VCC,
ADR1 => a(4),
ADR2 => Sh144_0,
ADR3 => Sh128,
O => Sh176
);
Sh15332 : X_LUT4
generic map(
INIT => X"E2E2",
LOC => "SLICE_X23Y16"
)
port map (
ADR0 => Sh1577_0,
ADR1 => a(2),
ADR2 => Sh1537_0,
ADR3 => VCC,
O => Sh153_pack_1
);
Sh1691 : X_LUT4
generic map(
INIT => X"F5A0",
LOC => "SLICE_X23Y16"
)
port map (
ADR0 => a(4),
ADR1 => VCC,
ADR2 => Sh153,
ADR3 => Sh137,
O => Sh169
);
Sh13132 : X_LUT4
generic map(
INIT => X"EEE2",
LOC => "SLICE_X25Y19"
)
port map (
ADR0 => Sh13120,
ADR1 => a(2),
ADR2 => Sh1310_0,
ADR3 => Sh1313,
O => Sh131_pack_1
);
Sh1791 : X_LUT4
generic map(
INIT => X"FD0D",
LOC => "SLICE_X25Y19"
)
port map (
ADR0 => N249_0,
ADR1 => Sh14712,
ADR2 => a(4),
ADR3 => Sh131,
O => Sh179
);
b_reg_mux0000_2_62 : X_LUT4
generic map(
INIT => X"FA50",
LOC => "SLICE_X12Y10"
)
port map (
ADR0 => b_2_Q,
ADR1 => VCC,
ADR2 => N291,
ADR3 => N292,
O => b_reg_mux0000_2_Q
);
b_reg_2_1 : X_FF
generic map(
LOC => "SLICE_X12Y10",
INIT => '0'
)
port map (
I => b_reg_2_1_DYMUX_10800,
CE => VCC,
CLK => b_reg_2_1_CLKINV_10790,
SET => GND,
RST => b_reg_2_1_FFY_RSTAND_10805,
O => b_reg_2_1_4381
);
b_reg_2_1_FFY_RSTAND : X_BUF
generic map(
LOC => "SLICE_X12Y10",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_2_1_FFY_RSTAND_10805
);
b_reg_mux0000_3_38 : X_LUT4
generic map(
INIT => X"F5A0",
LOC => "SLICE_X3Y21"
)
port map (
ADR0 => b_3_Q,
ADR1 => VCC,
ADR2 => N282,
ADR3 => N281,
O => b_reg_mux0000_3_Q
);
b_reg_3_1 : X_FF
generic map(
LOC => "SLICE_X3Y21",
INIT => '0'
)
port map (
I => b_reg_3_1_DYMUX_10824,
CE => VCC,
CLK => b_reg_3_1_CLKINV_10814,
SET => GND,
RST => b_reg_3_1_FFY_RSTAND_10829,
O => b_reg_3_1_4597
);
b_reg_3_1_FFY_RSTAND : X_BUF
generic map(
LOC => "SLICE_X3Y21",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_3_1_FFY_RSTAND_10829
);
b_reg_mux0000_4_57 : X_LUT4
generic map(
INIT => X"F0CC",
LOC => "SLICE_X3Y19"
)
port map (
ADR0 => VCC,
ADR1 => N278,
ADR2 => N279,
ADR3 => b_4_Q,
O => b_reg_mux0000_4_Q
);
b_reg_4_1 : X_FF
generic map(
LOC => "SLICE_X3Y19",
INIT => '0'
)
port map (
I => b_reg_4_1_DYMUX_10848,
CE => VCC,
CLK => b_reg_4_1_CLKINV_10838,
SET => GND,
RST => b_reg_4_1_FFY_RSTAND_10853,
O => b_reg_4_1_4383
);
b_reg_4_1_FFY_RSTAND : X_BUF
generic map(
LOC => "SLICE_X3Y19",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_4_1_FFY_RSTAND_10853
);
Mrom_AN_mux000111 : X_LUT4
generic map(
INIT => X"33FF",
LOC => "SLICE_X30Y14"
)
port map (
ADR0 => VCC,
ADR1 => LED_flash_cnt(8),
ADR2 => VCC,
ADR3 => LED_flash_cnt(9),
O => Mrom_AN_mux0001
);
AN_0 : X_FF
generic map(
LOC => "SLICE_X30Y14",
INIT => '1'
)
port map (
I => AN_1_DYMUX_10874,
CE => VCC,
CLK => AN_1_CLKINV_10863,
SET => AN_1_SRINV_10864,
RST => GND,
O => AN_0_4261
);
Mrom_AN_mux0001111 : X_LUT4
generic map(
INIT => X"CCFF",
LOC => "SLICE_X30Y14"
)
port map (
ADR0 => VCC,
ADR1 => LED_flash_cnt(8),
ADR2 => VCC,
ADR3 => LED_flash_cnt(9),
O => Mrom_AN_mux00011
);
AN_1 : X_FF
generic map(
LOC => "SLICE_X30Y14",
INIT => '1'
)
port map (
I => AN_1_DXMUX_10889,
CE => VCC,
CLK => AN_1_CLKINV_10863,
SET => AN_1_SRINV_10864,
RST => GND,
O => AN_1_4262
);
Mrom_AN_mux000121 : X_LUT4
generic map(
INIT => X"DDDD",
LOC => "SLICE_X30Y12"
)
port map (
ADR0 => LED_flash_cnt(8),
ADR1 => LED_flash_cnt(9),
ADR2 => VCC,
ADR3 => VCC,
O => Mrom_AN_mux00012
);
AN_2 : X_FF
generic map(
LOC => "SLICE_X30Y12",
INIT => '1'
)
port map (
I => AN_3_DYMUX_10914,
CE => VCC,
CLK => AN_3_CLKINV_10903,
SET => AN_3_SRINV_10904,
RST => GND,
O => AN_2_4263
);
Mrom_AN_mux000131 : X_LUT4
generic map(
INIT => X"EEEE",
LOC => "SLICE_X30Y12"
)
port map (
ADR0 => LED_flash_cnt(8),
ADR1 => LED_flash_cnt(9),
ADR2 => VCC,
ADR3 => VCC,
O => Mrom_AN_mux00013
);
AN_3 : X_FF
generic map(
LOC => "SLICE_X30Y12",
INIT => '1'
)
port map (
I => AN_3_DXMUX_10929,
CE => VCC,
CLK => AN_3_CLKINV_10903,
SET => AN_3_SRINV_10904,
RST => GND,
O => AN_3_4264
);
a_reg_0 : X_FF
generic map(
LOC => "SLICE_X13Y33",
INIT => '0'
)
port map (
I => a_reg_1_DYMUX_10956,
CE => VCC,
CLK => a_reg_1_CLKINV_10947,
SET => GND,
RST => a_reg_1_SRINV_10948,
O => a_reg(0)
);
a_reg_mux0000_0_1 : X_LUT4
generic map(
INIT => X"8F80",
LOC => "SLICE_X13Y33"
)
port map (
ADR0 => state_FSM_FFd1_4311,
ADR1 => a(0),
ADR2 => state_FSM_FFd2_4312,
ADR3 => a_reg(0),
O => a_reg_mux0000(0)
);
a_reg_mux0000_1_1 : X_LUT4
generic map(
INIT => X"A0CC",
LOC => "SLICE_X13Y33"
)
port map (
ADR0 => a(1),
ADR1 => a_reg(1),
ADR2 => state_FSM_FFd1_4311,
ADR3 => state_FSM_FFd2_4312,
O => a_reg_mux0000(1)
);
a_reg_1 : X_FF
generic map(
LOC => "SLICE_X13Y33",
INIT => '0'
)
port map (
I => a_reg_1_DXMUX_10970,
CE => VCC,
CLK => a_reg_1_CLKINV_10947,
SET => GND,
RST => a_reg_1_SRINV_10948,
O => a_reg(1)
);
a_reg_2 : X_FF
generic map(
LOC => "SLICE_X2Y21",
INIT => '0'
)
port map (
I => a_reg_3_DYMUX_10998,
CE => VCC,
CLK => a_reg_3_CLKINV_10989,
SET => GND,
RST => a_reg_3_SRINV_10990,
O => a_reg(2)
);
a_reg_mux0000_2_1 : X_LUT4
generic map(
INIT => X"D850",
LOC => "SLICE_X2Y21"
)
port map (
ADR0 => state_FSM_FFd2_4312,
ADR1 => a(2),
ADR2 => a_reg(2),
ADR3 => state_FSM_FFd1_4311,
O => a_reg_mux0000(2)
);
a_reg_mux0000_3_1 : X_LUT4
generic map(
INIT => X"ACFC",
LOC => "SLICE_X2Y21"
)
port map (
ADR0 => a(3),
ADR1 => a_reg(3),
ADR2 => state_FSM_FFd2_4312,
ADR3 => state_FSM_FFd1_4311,
O => a_reg_mux0000(3)
);
a_reg_3 : X_FF
generic map(
LOC => "SLICE_X2Y21",
INIT => '0'
)
port map (
I => a_reg_3_DXMUX_11012,
CE => VCC,
CLK => a_reg_3_CLKINV_10989,
SET => GND,
RST => a_reg_3_SRINV_10990,
O => a_reg(3)
);
a_reg_4 : X_FF
generic map(
LOC => "SLICE_X15Y18",
INIT => '0'
)
port map (
I => a_reg_5_DYMUX_11040,
CE => VCC,
CLK => a_reg_5_CLKINV_11031,
SET => GND,
RST => a_reg_5_SRINV_11032,
O => a_reg(4)
);
a_reg_mux0000_4_1 : X_LUT4
generic map(
INIT => X"A0CC",
LOC => "SLICE_X15Y18"
)
port map (
ADR0 => state_FSM_FFd1_4311,
ADR1 => a_reg(4),
ADR2 => a(4),
ADR3 => state_FSM_FFd2_4312,
O => a_reg_mux0000(4)
);
a_reg_mux0000_5_1 : X_LUT4
generic map(
INIT => X"E222",
LOC => "SLICE_X15Y18"
)
port map (
ADR0 => a_reg(5),
ADR1 => state_FSM_FFd2_4312,
ADR2 => state_FSM_FFd1_4311,
ADR3 => a(5),
O => a_reg_mux0000(5)
);
a_reg_5 : X_FF
generic map(
LOC => "SLICE_X15Y18",
INIT => '0'
)
port map (
I => a_reg_5_DXMUX_11054,
CE => VCC,
CLK => a_reg_5_CLKINV_11031,
SET => GND,
RST => a_reg_5_SRINV_11032,
O => a_reg(5)
);
a_reg_6 : X_FF
generic map(
LOC => "SLICE_X17Y15",
INIT => '0'
)
port map (
I => a_reg_7_DYMUX_11082,
CE => VCC,
CLK => a_reg_7_CLKINV_11073,
SET => GND,
RST => a_reg_7_SRINV_11074,
O => a_reg(6)
);
a_reg_mux0000_6_1 : X_LUT4
generic map(
INIT => X"B8FC",
LOC => "SLICE_X17Y15"
)
port map (
ADR0 => a(6),
ADR1 => state_FSM_FFd2_4312,
ADR2 => a_reg(6),
ADR3 => state_FSM_FFd1_4311,
O => a_reg_mux0000(6)
);
a_reg_mux0000_7_1 : X_LUT4
generic map(
INIT => X"FC5C",
LOC => "SLICE_X17Y15"
)
port map (
ADR0 => state_FSM_FFd1_4311,
ADR1 => a_reg(7),
ADR2 => state_FSM_FFd2_4312,
ADR3 => a(7),
O => a_reg_mux0000(7)
);
a_reg_7 : X_FF
generic map(
LOC => "SLICE_X17Y15",
INIT => '0'
)
port map (
I => a_reg_7_DXMUX_11096,
CE => VCC,
CLK => a_reg_7_CLKINV_11073,
SET => GND,
RST => a_reg_7_SRINV_11074,
O => a_reg(7)
);
a_reg_8 : X_FF
generic map(
LOC => "SLICE_X16Y12",
INIT => '0'
)
port map (
I => a_reg_9_DYMUX_11124,
CE => VCC,
CLK => a_reg_9_CLKINV_11115,
SET => GND,
RST => a_reg_9_SRINV_11116,
O => a_reg(8)
);
a_reg_mux0000_8_1 : X_LUT4
generic map(
INIT => X"AC0C",
LOC => "SLICE_X16Y12"
)
port map (
ADR0 => a(8),
ADR1 => a_reg(8),
ADR2 => state_FSM_FFd2_4312,
ADR3 => state_FSM_FFd1_4311,
O => a_reg_mux0000(8)
);
a_reg_mux0000_9_1 : X_LUT4
generic map(
INIT => X"D850",
LOC => "SLICE_X16Y12"
)
port map (
ADR0 => state_FSM_FFd2_4312,
ADR1 => a(9),
ADR2 => a_reg(9),
ADR3 => state_FSM_FFd1_4311,
O => a_reg_mux0000(9)
);
a_reg_9 : X_FF
generic map(
LOC => "SLICE_X16Y12",
INIT => '0'
)
port map (
I => a_reg_9_DXMUX_11138,
CE => VCC,
CLK => a_reg_9_CLKINV_11115,
SET => GND,
RST => a_reg_9_SRINV_11116,
O => a_reg(9)
);
b_reg_mux0000_6_57 : X_LUT4
generic map(
INIT => X"EE44",
LOC => "SLICE_X12Y12"
)
port map (
ADR0 => b_6_Q,
ADR1 => N272,
ADR2 => VCC,
ADR3 => N273,
O => b_reg_mux0000_6_Q
);
b_reg_6 : X_FF
generic map(
LOC => "SLICE_X12Y12",
INIT => '0'
)
port map (
I => b_reg_7_DYMUX_11165,
CE => VCC,
CLK => b_reg_7_CLKINV_11155,
SET => GND,
RST => b_reg_7_SRINV_11156,
O => b_reg(6)
);
b_reg_mux0000_7_38 : X_LUT4
generic map(
INIT => X"E4E4",
LOC => "SLICE_X12Y12"
)
port map (
ADR0 => b_7_Q,
ADR1 => N269,
ADR2 => N270,
ADR3 => VCC,
O => b_reg_mux0000_7_Q
);
b_reg_7 : X_FF
generic map(
LOC => "SLICE_X12Y12",
INIT => '0'
)
port map (
I => b_reg_7_DXMUX_11180,
CE => VCC,
CLK => b_reg_7_CLKINV_11155,
SET => GND,
RST => b_reg_7_SRINV_11156,
O => b_reg(7)
);
i_cnt_mux0001_3_1 : X_LUT4
generic map(
INIT => X"3CFC",
LOC => "SLICE_X12Y32"
)
port map (
ADR0 => VCC,
ADR1 => state_FSM_FFd2_4312,
ADR2 => i_cnt(0),
ADR3 => state_FSM_FFd1_4311,
O => i_cnt_mux0001(3)
);
i_cnt_0 : X_FF
generic map(
LOC => "SLICE_X12Y32",
INIT => '1'
)
port map (
I => i_cnt_1_DYMUX_11208,
CE => VCC,
CLK => i_cnt_1_CLKINV_11198,
SET => i_cnt_1_SRINV_11199,
RST => GND,
O => i_cnt(0)
);
i_cnt_mux0001_2_1 : X_LUT4
generic map(
INIT => X"6C44",
LOC => "SLICE_X12Y32"
)
port map (
ADR0 => state_FSM_FFd2_4312,
ADR1 => i_cnt(1),
ADR2 => i_cnt(0),
ADR3 => state_FSM_FFd1_4311,
O => i_cnt_mux0001(2)
);
i_cnt_1 : X_FF
generic map(
LOC => "SLICE_X12Y32",
INIT => '0'
)
port map (
I => i_cnt_1_DXMUX_11221,
CE => VCC,
CLK => i_cnt_1_CLKINV_11198,
SET => GND,
RST => i_cnt_1_SRINV_11199,
O => i_cnt(1)
);
a_reg_10 : X_FF
generic map(
LOC => "SLICE_X14Y13",
INIT => '0'
)
port map (
I => a_reg_11_DYMUX_11249,
CE => VCC,
CLK => a_reg_11_CLKINV_11240,
SET => GND,
RST => a_reg_11_SRINV_11241,
O => a_reg(10)
);
a_reg_mux0000_10_1 : X_LUT4
generic map(
INIT => X"CA0A",
LOC => "SLICE_X14Y13"
)
port map (
ADR0 => a_reg(10),
ADR1 => state_FSM_FFd1_4311,
ADR2 => state_FSM_FFd2_4312,
ADR3 => a(10),
O => a_reg_mux0000(10)
);
a_reg_mux0000_11_1 : X_LUT4
generic map(
INIT => X"BFB0",
LOC => "SLICE_X14Y13"
)
port map (
ADR0 => a(11),
ADR1 => state_FSM_FFd1_4311,
ADR2 => state_FSM_FFd2_4312,
ADR3 => a_reg(11),
O => a_reg_mux0000(11)
);
a_reg_11 : X_FF
generic map(
LOC => "SLICE_X14Y13",
INIT => '0'
)
port map (
I => a_reg_11_DXMUX_11263,
CE => VCC,
CLK => a_reg_11_CLKINV_11240,
SET => GND,
RST => a_reg_11_SRINV_11241,
O => a_reg(11)
);
a_reg_15 : X_FF
generic map(
LOC => "SLICE_X15Y22",
INIT => '0'
)
port map (
I => a_reg_15_DXMUX_11473,
CE => VCC,
CLK => a_reg_15_CLKINV_11450,
SET => GND,
RST => a_reg_15_SRINV_11451,
O => a_reg(15)
);
a_reg_24 : X_FF
generic map(
LOC => "SLICE_X17Y33",
INIT => '0'
)
port map (
I => a_reg_25_DYMUX_11501,
CE => VCC,
CLK => a_reg_25_CLKINV_11492,
SET => GND,
RST => a_reg_25_SRINV_11493,
O => a_reg(24)
);
a_reg_mux0000_25_1 : X_LUT4
generic map(
INIT => X"ACFC",
LOC => "SLICE_X17Y33"
)
port map (
ADR0 => a(25),
ADR1 => a_reg(25),
ADR2 => state_FSM_FFd2_4312,
ADR3 => state_FSM_FFd1_4311,
O => a_reg_mux0000(25)
);
a_reg_25 : X_FF
generic map(
LOC => "SLICE_X17Y33",
INIT => '0'
)
port map (
I => a_reg_25_DXMUX_11515,
CE => VCC,
CLK => a_reg_25_CLKINV_11492,
SET => GND,
RST => a_reg_25_SRINV_11493,
O => a_reg(25)
);
a_reg_16 : X_FF
generic map(
LOC => "SLICE_X13Y22",
INIT => '0'
)
port map (
I => a_reg_17_DYMUX_11543,
CE => VCC,
CLK => a_reg_17_CLKINV_11534,
SET => GND,
RST => a_reg_17_SRINV_11535,
O => a_reg(16)
);
a_reg_mux0000_16_1 : X_LUT4
generic map(
INIT => X"FC5C",
LOC => "SLICE_X13Y22"
)
port map (
ADR0 => state_FSM_FFd1_4311,
ADR1 => a_reg(16),
ADR2 => state_FSM_FFd2_4312,
ADR3 => a(16),
O => a_reg_mux0000(16)
);
a_reg_mux0000_17_1 : X_LUT4
generic map(
INIT => X"DFD0",
LOC => "SLICE_X13Y22"
)
port map (
ADR0 => state_FSM_FFd1_4311,
ADR1 => a(17),
ADR2 => state_FSM_FFd2_4312,
ADR3 => a_reg(17),
O => a_reg_mux0000(17)
);
a_reg_17 : X_FF
generic map(
LOC => "SLICE_X13Y22",
INIT => '0'
)
port map (
I => a_reg_17_DXMUX_11557,
CE => VCC,
CLK => a_reg_17_CLKINV_11534,
SET => GND,
RST => a_reg_17_SRINV_11535,
O => a_reg(17)
);
a_reg_26 : X_FF
generic map(
LOC => "SLICE_X18Y30",
INIT => '0'
)
port map (
I => a_reg_27_DYMUX_11585,
CE => VCC,
CLK => a_reg_27_CLKINV_11576,
SET => GND,
RST => a_reg_27_SRINV_11577,
O => a_reg(26)
);
a_reg_mux0000_26_1 : X_LUT4
generic map(
INIT => X"88F0",
LOC => "SLICE_X18Y30"
)
port map (
ADR0 => state_FSM_FFd1_4311,
ADR1 => a(26),
ADR2 => a_reg(26),
ADR3 => state_FSM_FFd2_4312,
O => a_reg_mux0000(26)
);
a_reg_mux0000_27_1 : X_LUT4
generic map(
INIT => X"F5CC",
LOC => "SLICE_X18Y30"
)
port map (
ADR0 => state_FSM_FFd1_4311,
ADR1 => a_reg(27),
ADR2 => a(27),
ADR3 => state_FSM_FFd2_4312,
O => a_reg_mux0000(27)
);
a_reg_27 : X_FF
generic map(
LOC => "SLICE_X18Y30",
INIT => '0'
)
port map (
I => a_reg_27_DXMUX_11599,
CE => VCC,
CLK => a_reg_27_CLKINV_11576,
SET => GND,
RST => a_reg_27_SRINV_11577,
O => a_reg(27)
);
a_reg_18 : X_FF
generic map(
LOC => "SLICE_X14Y25",
INIT => '0'
)
port map (
I => a_reg_19_DYMUX_11627,
CE => VCC,
CLK => a_reg_19_CLKINV_11618,
SET => GND,
RST => a_reg_19_SRINV_11619,
O => a_reg(18)
);
a_reg_mux0000_18_1 : X_LUT4
generic map(
INIT => X"88F0",
LOC => "SLICE_X14Y25"
)
port map (
ADR0 => a(18),
ADR1 => state_FSM_FFd1_4311,
ADR2 => a_reg(18),
ADR3 => state_FSM_FFd2_4312,
O => a_reg_mux0000(18)
);
a_reg_mux0000_19_1 : X_LUT4
generic map(
INIT => X"F7A2",
LOC => "SLICE_X14Y25"
)
port map (
ADR0 => state_FSM_FFd2_4312,
ADR1 => state_FSM_FFd1_4311,
ADR2 => a(19),
ADR3 => a_reg(19),
O => a_reg_mux0000(19)
);
a_reg_19 : X_FF
generic map(
LOC => "SLICE_X14Y25",
INIT => '0'
)
port map (
I => a_reg_19_DXMUX_11641,
CE => VCC,
CLK => a_reg_19_CLKINV_11618,
SET => GND,
RST => a_reg_19_SRINV_11619,
O => a_reg(19)
);
a_reg_28 : X_FF
generic map(
LOC => "SLICE_X17Y34",
INIT => '0'
)
port map (
I => a_reg_29_DYMUX_11669,
CE => VCC,
CLK => a_reg_29_CLKINV_11660,
SET => GND,
RST => a_reg_29_SRINV_11661,
O => a_reg(28)
);
a_reg_mux0000_28_1 : X_LUT4
generic map(
INIT => X"DF8A",
LOC => "SLICE_X17Y34"
)
port map (
ADR0 => state_FSM_FFd2_4312,
ADR1 => a(28),
ADR2 => state_FSM_FFd1_4311,
ADR3 => a_reg(28),
O => a_reg_mux0000(28)
);
a_reg_mux0000_29_1 : X_LUT4
generic map(
INIT => X"D580",
LOC => "SLICE_X17Y34"
)
port map (
ADR0 => state_FSM_FFd2_4312,
ADR1 => a(29),
ADR2 => state_FSM_FFd1_4311,
ADR3 => a_reg(29),
O => a_reg_mux0000(29)
);
a_reg_29 : X_FF
generic map(
LOC => "SLICE_X17Y34",
INIT => '0'
)
port map (
I => a_reg_29_DXMUX_11683,
CE => VCC,
CLK => a_reg_29_CLKINV_11660,
SET => GND,
RST => a_reg_29_SRINV_11661,
O => a_reg(29)
);
b_reg_mux0000_11_21 : X_LUT4
generic map(
INIT => X"CCAA",
LOC => "SLICE_X15Y11"
)
port map (
ADR0 => N266,
ADR1 => N267,
ADR2 => VCC,
ADR3 => b_11_Q,
O => b_reg_mux0000_11_Q
);
b_reg_11 : X_FF
generic map(
LOC => "SLICE_X15Y11",
INIT => '0'
)
port map (
I => b_reg_11_DYMUX_11706,
CE => VCC,
CLK => b_reg_11_CLKINV_11696,
SET => GND,
RST => b_reg_11_FFY_RSTAND_11711,
O => b_reg(11)
);
b_reg_11_FFY_RSTAND : X_BUF
generic map(
LOC => "SLICE_X15Y11",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_11_FFY_RSTAND_11711
);
b_reg_20 : X_FF
generic map(
LOC => "SLICE_X19Y23",
INIT => '0'
)
port map (
I => b_reg_21_DYMUX_11734,
CE => VCC,
CLK => b_reg_21_CLKINV_11725,
SET => GND,
RST => b_reg_21_SRINV_11726,
O => b_reg(20)
);
b_reg_mux0000_20_1 : X_LUT4
generic map(
INIT => X"F5CC",
LOC => "SLICE_X19Y23"
)
port map (
ADR0 => state_FSM_FFd1_4311,
ADR1 => b_reg(20),
ADR2 => b_20_Q,
ADR3 => state_FSM_FFd2_4312,
O => b_reg_mux0000_20_Q
);
b_reg_mux0000_21_1 : X_LUT4
generic map(
INIT => X"EE4E",
LOC => "SLICE_X19Y23"
)
port map (
ADR0 => state_FSM_FFd2_4312,
ADR1 => b_reg(21),
ADR2 => state_FSM_FFd1_4311,
ADR3 => b_21_Q,
O => b_reg_mux0000_21_Q
);
b_reg_21 : X_FF
generic map(
LOC => "SLICE_X19Y23",
INIT => '0'
)
port map (
I => b_reg_21_DXMUX_11748,
CE => VCC,
CLK => b_reg_21_CLKINV_11725,
SET => GND,
RST => b_reg_21_SRINV_11726,
O => b_reg(21)
);
b_reg_12 : X_FF
generic map(
LOC => "SLICE_X18Y19",
INIT => '0'
)
port map (
I => b_reg_13_DYMUX_11776,
CE => VCC,
CLK => b_reg_13_CLKINV_11767,
SET => GND,
RST => b_reg_13_SRINV_11768,
O => b_reg(12)
);
b_reg_mux0000_12_1 : X_LUT4
generic map(
INIT => X"CAFA",
LOC => "SLICE_X18Y19"
)
port map (
ADR0 => b_reg(12),
ADR1 => b_12_Q,
ADR2 => state_FSM_FFd2_4312,
ADR3 => state_FSM_FFd1_4311,
O => b_reg_mux0000_12_Q
);
b_reg_mux0000_13_1 : X_LUT4
generic map(
INIT => X"FC74",
LOC => "SLICE_X18Y19"
)
port map (
ADR0 => state_FSM_FFd1_4311,
ADR1 => state_FSM_FFd2_4312,
ADR2 => b_reg(13),
ADR3 => b_13_Q,
O => b_reg_mux0000_13_Q
);
b_reg_13 : X_FF
generic map(
LOC => "SLICE_X18Y19",
INIT => '0'
)
port map (
I => b_reg_13_DXMUX_11790,
CE => VCC,
CLK => b_reg_13_CLKINV_11767,
SET => GND,
RST => b_reg_13_SRINV_11768,
O => b_reg(13)
);
b_reg_30 : X_FF
generic map(
LOC => "SLICE_X19Y26",
INIT => '0'
)
port map (
I => b_reg_31_DYMUX_11818,
CE => VCC,
CLK => b_reg_31_CLKINV_11809,
SET => GND,
RST => b_reg_31_SRINV_11810,
O => b_reg(30)
);
b_reg_mux0000_30_1 : X_LUT4
generic map(
INIT => X"E444",
LOC => "SLICE_X19Y26"
)
port map (
ADR0 => state_FSM_FFd2_4312,
ADR1 => b_reg(30),
ADR2 => b_30_Q,
ADR3 => state_FSM_FFd1_4311,
O => b_reg_mux0000_30_Q
);
b_reg_mux0000_31_1 : X_LUT4
generic map(
INIT => X"C0AA",
LOC => "SLICE_X19Y26"
)
port map (
ADR0 => b_reg(31),
ADR1 => b_31_Q,
ADR2 => state_FSM_FFd1_4311,
ADR3 => state_FSM_FFd2_4312,
O => b_reg_mux0000_31_Q
);
b_reg_31 : X_FF
generic map(
LOC => "SLICE_X19Y26",
INIT => '0'
)
port map (
I => b_reg_31_DXMUX_11832,
CE => VCC,
CLK => b_reg_31_CLKINV_11809,
SET => GND,
RST => b_reg_31_SRINV_11810,
O => b_reg(31)
);
b_reg_22 : X_FF
generic map(
LOC => "SLICE_X19Y22",
INIT => '0'
)
port map (
I => b_reg_23_DYMUX_11860,
CE => VCC,
CLK => b_reg_23_CLKINV_11851,
SET => GND,
RST => b_reg_23_SRINV_11852,
O => b_reg(22)
);
b_reg_mux0000_22_1 : X_LUT4
generic map(
INIT => X"88F0",
LOC => "SLICE_X19Y22"
)
port map (
ADR0 => state_FSM_FFd1_4311,
ADR1 => b_22_Q,
ADR2 => b_reg(22),
ADR3 => state_FSM_FFd2_4312,
O => b_reg_mux0000_22_Q
);
b_reg_mux0000_23_1 : X_LUT4
generic map(
INIT => X"B380",
LOC => "SLICE_X19Y22"
)
port map (
ADR0 => b_23_Q,
ADR1 => state_FSM_FFd2_4312,
ADR2 => state_FSM_FFd1_4311,
ADR3 => b_reg(23),
O => b_reg_mux0000_23_Q
);
b_reg_23 : X_FF
generic map(
LOC => "SLICE_X19Y22",
INIT => '0'
)
port map (
I => b_reg_23_DXMUX_11874,
CE => VCC,
CLK => b_reg_23_CLKINV_11851,
SET => GND,
RST => b_reg_23_SRINV_11852,
O => b_reg(23)
);
b_reg_14 : X_FF
generic map(
LOC => "SLICE_X19Y18",
INIT => '0'
)
port map (
I => b_reg_15_DYMUX_11902,
CE => VCC,
CLK => b_reg_15_CLKINV_11893,
SET => GND,
RST => b_reg_15_SRINV_11894,
O => b_reg(14)
);
b_reg_mux0000_14_1 : X_LUT4
generic map(
INIT => X"FC74",
LOC => "SLICE_X19Y18"
)
port map (
ADR0 => state_FSM_FFd1_4311,
ADR1 => state_FSM_FFd2_4312,
ADR2 => b_reg(14),
ADR3 => b_14_Q,
O => b_reg_mux0000_14_Q
);
b_reg_mux0000_15_1 : X_LUT4
generic map(
INIT => X"CFAA",
LOC => "SLICE_X19Y18"
)
port map (
ADR0 => b_reg(15),
ADR1 => b_15_Q,
ADR2 => state_FSM_FFd1_4311,
ADR3 => state_FSM_FFd2_4312,
O => b_reg_mux0000_15_Q
);
b_reg_15 : X_FF
generic map(
LOC => "SLICE_X19Y18",
INIT => '0'
)
port map (
I => b_reg_15_DXMUX_11916,
CE => VCC,
CLK => b_reg_15_CLKINV_11893,
SET => GND,
RST => b_reg_15_SRINV_11894,
O => b_reg(15)
);
b_reg_24 : X_FF
generic map(
LOC => "SLICE_X19Y24",
INIT => '0'
)
port map (
I => b_reg_25_DYMUX_11944,
CE => VCC,
CLK => b_reg_25_CLKINV_11935,
SET => GND,
RST => b_reg_25_SRINV_11936,
O => b_reg(24)
);
b_reg_mux0000_24_1 : X_LUT4
generic map(
INIT => X"B830",
LOC => "SLICE_X19Y24"
)
port map (
ADR0 => b_24_Q,
ADR1 => state_FSM_FFd2_4312,
ADR2 => b_reg(24),
ADR3 => state_FSM_FFd1_4311,
O => b_reg_mux0000_24_Q
);
b_reg_mux0000_25_1 : X_LUT4
generic map(
INIT => X"E2EE",
LOC => "SLICE_X19Y24"
)
port map (
ADR0 => b_reg(25),
ADR1 => state_FSM_FFd2_4312,
ADR2 => b_25_Q,
ADR3 => state_FSM_FFd1_4311,
O => b_reg_mux0000_25_Q
);
b_reg_25 : X_FF
generic map(
LOC => "SLICE_X19Y24",
INIT => '0'
)
port map (
I => b_reg_25_DXMUX_11958,
CE => VCC,
CLK => b_reg_25_CLKINV_11935,
SET => GND,
RST => b_reg_25_SRINV_11936,
O => b_reg(25)
);
b_reg_16 : X_FF
generic map(
LOC => "SLICE_X18Y21",
INIT => '0'
)
port map (
I => b_reg_17_DYMUX_11986,
CE => VCC,
CLK => b_reg_17_CLKINV_11977,
SET => GND,
RST => b_reg_17_SRINV_11978,
O => b_reg(16)
);
b_reg_mux0000_16_1 : X_LUT4
generic map(
INIT => X"CFAA",
LOC => "SLICE_X18Y21"
)
port map (
ADR0 => b_reg(16),
ADR1 => b_16_Q,
ADR2 => state_FSM_FFd1_4311,
ADR3 => state_FSM_FFd2_4312,
O => b_reg_mux0000_16_Q
);
b_reg_mux0000_17_1 : X_LUT4
generic map(
INIT => X"EE2E",
LOC => "SLICE_X18Y21"
)
port map (
ADR0 => b_reg(17),
ADR1 => state_FSM_FFd2_4312,
ADR2 => state_FSM_FFd1_4311,
ADR3 => b_17_Q,
O => b_reg_mux0000_17_Q
);
b_reg_17 : X_FF
generic map(
LOC => "SLICE_X18Y21",
INIT => '0'
)
port map (
I => b_reg_17_DXMUX_12000,
CE => VCC,
CLK => b_reg_17_CLKINV_11977,
SET => GND,
RST => b_reg_17_SRINV_11978,
O => b_reg(17)
);
b_reg_26 : X_FF
generic map(
LOC => "SLICE_X19Y25",
INIT => '0'
)
port map (
I => b_reg_27_DYMUX_12028,
CE => VCC,
CLK => b_reg_27_CLKINV_12019,
SET => GND,
RST => b_reg_27_SRINV_12020,
O => b_reg(26)
);
b_reg_mux0000_26_1 : X_LUT4
generic map(
INIT => X"B830",
LOC => "SLICE_X19Y25"
)
port map (
ADR0 => state_FSM_FFd1_4311,
ADR1 => state_FSM_FFd2_4312,
ADR2 => b_reg(26),
ADR3 => b_26_Q,
O => b_reg_mux0000_26_Q
);
b_reg_mux0000_27_1 : X_LUT4
generic map(
INIT => X"DF8A",
LOC => "SLICE_X19Y25"
)
port map (
ADR0 => state_FSM_FFd2_4312,
ADR1 => b_27_Q,
ADR2 => state_FSM_FFd1_4311,
ADR3 => b_reg(27),
O => b_reg_mux0000_27_Q
);
b_reg_27 : X_FF
generic map(
LOC => "SLICE_X19Y25",
INIT => '0'
)
port map (
I => b_reg_27_DXMUX_12042,
CE => VCC,
CLK => b_reg_27_CLKINV_12019,
SET => GND,
RST => b_reg_27_SRINV_12020,
O => b_reg(27)
);
b_reg_18 : X_FF
generic map(
LOC => "SLICE_X18Y20",
INIT => '0'
)
port map (
I => b_reg_19_DYMUX_12070,
CE => VCC,
CLK => b_reg_19_CLKINV_12061,
SET => GND,
RST => b_reg_19_SRINV_12062,
O => b_reg(18)
);
b_reg_mux0000_18_1 : X_LUT4
generic map(
INIT => X"D8FA",
LOC => "SLICE_X18Y20"
)
port map (
ADR0 => state_FSM_FFd2_4312,
ADR1 => b_18_Q,
ADR2 => b_reg(18),
ADR3 => state_FSM_FFd1_4311,
O => b_reg_mux0000_18_Q
);
b_reg_mux0000_19_1 : X_LUT4
generic map(
INIT => X"B380",
LOC => "SLICE_X18Y20"
)
port map (
ADR0 => b_19_Q,
ADR1 => state_FSM_FFd2_4312,
ADR2 => state_FSM_FFd1_4311,
ADR3 => b_reg(19),
O => b_reg_mux0000_19_Q
);
b_reg_19 : X_FF
generic map(
LOC => "SLICE_X18Y20",
INIT => '0'
)
port map (
I => b_reg_19_DXMUX_12084,
CE => VCC,
CLK => b_reg_19_CLKINV_12061,
SET => GND,
RST => b_reg_19_SRINV_12062,
O => b_reg(19)
);
b_reg_28 : X_FF
generic map(
LOC => "SLICE_X19Y27",
INIT => '0'
)
port map (
I => b_reg_29_DYMUX_12112,
CE => VCC,
CLK => b_reg_29_CLKINV_12103,
SET => GND,
RST => b_reg_29_SRINV_12104,
O => b_reg(28)
);
b_reg_mux0000_28_1 : X_LUT4
generic map(
INIT => X"B8FC",
LOC => "SLICE_X19Y27"
)
port map (
ADR0 => b_28_Q,
ADR1 => state_FSM_FFd2_4312,
ADR2 => b_reg(28),
ADR3 => state_FSM_FFd1_4311,
O => b_reg_mux0000_28_Q
);
b_reg_mux0000_29_1 : X_LUT4
generic map(
INIT => X"D580",
LOC => "SLICE_X19Y27"
)
port map (
ADR0 => state_FSM_FFd2_4312,
ADR1 => b_29_Q,
ADR2 => state_FSM_FFd1_4311,
ADR3 => b_reg(29),
O => b_reg_mux0000_29_Q
);
b_reg_29 : X_FF
generic map(
LOC => "SLICE_X19Y27",
INIT => '0'
)
port map (
I => b_reg_29_DXMUX_12126,
CE => VCC,
CLK => b_reg_29_CLKINV_12103,
SET => GND,
RST => b_reg_29_SRINV_12104,
O => b_reg(29)
);
Sh13220 : X_LUT4
generic map(
INIT => X"FA50",
LOC => "SLICE_X24Y19"
)
port map (
ADR0 => a(3),
ADR1 => VCC,
ADR2 => Sh100,
ADR3 => Sh124,
O => Sh13220_12146
);
Sh1287 : X_LUT4
generic map(
INIT => X"EE44",
LOC => "SLICE_X24Y19"
)
port map (
ADR0 => a(3),
ADR1 => Sh124,
ADR2 => VCC,
ADR3 => Sh116,
O => Sh1287_12154
);
Sh15013 : X_LUT4
generic map(
INIT => X"88A0",
LOC => "SLICE_X26Y20"
)
port map (
ADR0 => a(3),
ADR1 => Sh1082_0,
ADR2 => Sh1102_0,
ADR3 => a(1),
O => Sh15013_12170
);
Sh110_f51 : X_LUT4
generic map(
INIT => X"CCF0",
LOC => "SLICE_X26Y20"
)
port map (
ADR0 => VCC,
ADR1 => Sh1082_0,
ADR2 => Sh1102_0,
ADR3 => a(1),
O => Sh110
);
Sh14313 : X_LUT4
generic map(
INIT => X"A808",
LOC => "SLICE_X24Y21"
)
port map (
ADR0 => a(3),
ADR1 => Sh1032_0,
ADR2 => a(1),
ADR3 => Sh1012_0,
O => Sh14313_12194
);
Sh103_f51 : X_LUT4
generic map(
INIT => X"EE44",
LOC => "SLICE_X24Y21"
)
port map (
ADR0 => a(1),
ADR1 => Sh1032_0,
ADR2 => VCC,
ADR3 => Sh1012_0,
O => Sh103
);
Sh15113 : X_LUT4
generic map(
INIT => X"E400",
LOC => "SLICE_X22Y22"
)
port map (
ADR0 => a(1),
ADR1 => Sh1112_0,
ADR2 => Sh1092_0,
ADR3 => a(3),
O => Sh15113_12219
);
Sh15816 : X_LUT4
generic map(
INIT => X"00E2",
LOC => "SLICE_X22Y22"
)
port map (
ADR0 => Sh1262_0,
ADR1 => a(1),
ADR2 => Sh1242_0,
ADR3 => a(3),
O => Sh15816_12226
);
Sh15116 : X_LUT4
generic map(
INIT => X"00E2",
LOC => "SLICE_X24Y23"
)
port map (
ADR0 => Sh1192_0,
ADR1 => a(1),
ADR2 => Sh1172_0,
ADR3 => a(3),
O => Sh15116_12243
);
Sh15913 : X_LUT4
generic map(
INIT => X"C0A0",
LOC => "SLICE_X24Y23"
)
port map (
ADR0 => Sh1192_0,
ADR1 => Sh1172_0,
ADR2 => a(3),
ADR3 => a(1),
O => Sh1310
);
Sh14412 : X_LUT4
generic map(
INIT => X"A808",
LOC => "SLICE_X24Y13"
)
port map (
ADR0 => a(2),
ADR1 => Sh108,
ADR2 => a(3),
ADR3 => Sh100,
O => Sh14412_12265
);
Sh14813 : X_LUT4
generic map(
INIT => X"CC00",
LOC => "SLICE_X24Y13"
)
port map (
ADR0 => VCC,
ADR1 => a(3),
ADR2 => VCC,
ADR3 => Sh108,
O => Sh14813_12274
);
Sh14413 : X_LUT4
generic map(
INIT => X"CC00",
LOC => "SLICE_X22Y13"
)
port map (
ADR0 => VCC,
ADR1 => a(3),
ADR2 => VCC,
ADR3 => Sh104,
O => Sh14413_12289
);
Sh1323 : X_LUT4
generic map(
INIT => X"2222",
LOC => "SLICE_X22Y13"
)
port map (
ADR0 => Sh96,
ADR1 => a(3),
ADR2 => VCC,
ADR3 => VCC,
O => Sh12816
);
Sh15413 : X_LUT4
generic map(
INIT => X"C840",
LOC => "SLICE_X28Y23"
)
port map (
ADR0 => a(1),
ADR1 => a(3),
ADR2 => Sh1142_0,
ADR3 => Sh1122_0,
O => Sh15413_12315
);
Sh14616 : X_LUT4
generic map(
INIT => X"3210",
LOC => "SLICE_X28Y23"
)
port map (
ADR0 => a(1),
ADR1 => a(3),
ADR2 => Sh1142_0,
ADR3 => Sh1122_0,
O => Sh14616_12322
);
Sh14613 : X_LUT4
generic map(
INIT => X"A808",
LOC => "SLICE_X27Y17"
)
port map (
ADR0 => a(3),
ADR1 => Sh1062_0,
ADR2 => a(1),
ADR3 => Sh1042_0,
O => Sh14613_12338
);
Sh106_f51 : X_LUT4
generic map(
INIT => X"EE44",
LOC => "SLICE_X27Y17"
)
port map (
ADR0 => a(1),
ADR1 => Sh1062_0,
ADR2 => VCC,
ADR3 => Sh1042_0,
O => Sh106
);
Sh15513 : X_LUT4
generic map(
INIT => X"E400",
LOC => "SLICE_X26Y25"
)
port map (
ADR0 => a(1),
ADR1 => Sh1152_0,
ADR2 => Sh1132_0,
ADR3 => a(3),
O => Sh15513_12363
);
Sh15516 : X_LUT4
generic map(
INIT => X"5140",
LOC => "SLICE_X26Y25"
)
port map (
ADR0 => a(3),
ADR1 => a(1),
ADR2 => Sh1212_0,
ADR3 => Sh1232_0,
O => Sh15516_12370
);
Sh14816 : X_LUT4
generic map(
INIT => X"0F00",
LOC => "SLICE_X24Y17"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => a(3),
ADR3 => Sh116,
O => Sh14816_12386
);
Sh1527 : X_LUT4
generic map(
INIT => X"CFC0",
LOC => "SLICE_X24Y17"
)
port map (
ADR0 => VCC,
ADR1 => Sh108,
ADR2 => a(3),
ADR3 => Sh116,
O => Sh1527_12394
);
Sh15813 : X_LUT4
generic map(
INIT => X"C0A0",
LOC => "SLICE_X29Y22"
)
port map (
ADR0 => Sh1182_0,
ADR1 => Sh1162_0,
ADR2 => a(3),
ADR3 => a(1),
O => Sh15813_12411
);
Sh1340 : X_LUT4
generic map(
INIT => X"D080",
LOC => "SLICE_X29Y22"
)
port map (
ADR0 => a(1),
ADR1 => Sh1202_0,
ADR2 => a(3),
ADR3 => Sh1222_0,
O => Sh13013
);
b_reg_0_2 : X_FF
generic map(
LOC => "SLICE_X15Y17",
INIT => '0'
)
port map (
I => b_reg_0_2_DYMUX_12428,
CE => VCC,
CLK => b_reg_0_2_CLKINV_12425,
SET => GND,
RST => b_reg_0_2_FFY_RSTAND_12433,
O => b_reg_0_2_4323
);
b_reg_0_2_FFY_RSTAND : X_BUF
generic map(
LOC => "SLICE_X15Y17",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_0_2_FFY_RSTAND_12433
);
b_reg_0_3 : X_FF
generic map(
LOC => "SLICE_X14Y16",
INIT => '0'
)
port map (
I => b_reg_0_3_DYMUX_12442,
CE => VCC,
CLK => b_reg_0_3_CLKINV_12439,
SET => GND,
RST => b_reg_0_3_FFY_RSTAND_12447,
O => b_reg_0_3_4316
);
b_reg_0_3_FFY_RSTAND : X_BUF
generic map(
LOC => "SLICE_X14Y16",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => b_reg_0_3_FFY_RSTAND_12447
);
Mxor_ab_xor_Result_3_1 : X_LUT4
generic map(
INIT => X"5A5A",
LOC => "SLICE_X3Y20"
)
port map (
ADR0 => b_reg_3_1_4597,
ADR1 => VCC,
ADR2 => a_reg(3),
ADR3 => VCC,
O => ab_xor_3_Q
);
Mxor_ab_xor_Result_4_1 : X_LUT4
generic map(
INIT => X"33CC",
LOC => "SLICE_X13Y19"
)
port map (
ADR0 => VCC,
ADR1 => b_reg_4_1_4383,
ADR2 => VCC,
ADR3 => a_reg(4),
O => ab_xor_4_Q
);
Mxor_ab_xor_Result_5_1 : X_LUT4
generic map(
INIT => X"33CC",
LOC => "SLICE_X14Y19"
)
port map (
ADR0 => VCC,
ADR1 => b_reg(5),
ADR2 => VCC,
ADR3 => a_reg(5),
O => ab_xor_5_Q
);
Mxor_ba_xor_Result_4_1_SW1 : X_LUT4
generic map(
INIT => X"AA33",
LOC => "SLICE_X14Y19"
)
port map (
ADR0 => b_reg(4),
ADR1 => b_reg(5),
ADR2 => VCC,
ADR3 => a(0),
O => N247
);
Mxor_ab_xor_Result_7_1 : X_LUT4
generic map(
INIT => X"3C3C",
LOC => "SLICE_X16Y13"
)
port map (
ADR0 => VCC,
ADR1 => a_reg(7),
ADR2 => b_reg(7),
ADR3 => VCC,
O => ab_xor_7_Q
);
Mxor_ba_xor_Result_12_1_SW1 : X_LUT4
generic map(
INIT => X"AA33",
LOC => "SLICE_X15Y16"
)
port map (
ADR0 => b_reg(12),
ADR1 => b_reg(13),
ADR2 => VCC,
ADR3 => a(0),
O => N235
);
Mxor_ab_xor_Result_21_1 : X_LUT4
generic map(
INIT => X"6666",
LOC => "SLICE_X17Y32"
)
port map (
ADR0 => a_reg(21),
ADR1 => b_reg(21),
ADR2 => VCC,
ADR3 => VCC,
O => ab_xor_21_Q
);
Mxor_ba_xor_Result_21_1_SW0 : X_LUT4
generic map(
INIT => X"0F33",
LOC => "SLICE_X17Y32"
)
port map (
ADR0 => VCC,
ADR1 => b_reg(22),
ADR2 => b_reg(21),
ADR3 => a(0),
O => N214
);
Mxor_ab_xor_Result_15_1 : X_LUT4
generic map(
INIT => X"5A5A",
LOC => "SLICE_X15Y20"
)
port map (
ADR0 => b_reg(15),
ADR1 => VCC,
ADR2 => a_reg(15),
ADR3 => VCC,
O => ab_xor_15_Q
);
Mxor_ba_xor_Result_15_1_SW0 : X_LUT4
generic map(
INIT => X"2727",
LOC => "SLICE_X15Y20"
)
port map (
ADR0 => a(0),
ADR1 => b_reg(14),
ADR2 => b_reg(15),
ADR3 => VCC,
O => N228
);
Mxor_ab_xor_Result_23_1 : X_LUT4
generic map(
INIT => X"6666",
LOC => "SLICE_X19Y31"
)
port map (
ADR0 => a_reg(23),
ADR1 => b_reg(23),
ADR2 => VCC,
ADR3 => VCC,
O => ab_xor_23_Q
);
Mxor_ba_xor_Result_23_1_SW0 : X_LUT4
generic map(
INIT => X"0F55",
LOC => "SLICE_X19Y31"
)
port map (
ADR0 => b_reg(23),
ADR1 => VCC,
ADR2 => b_reg(22),
ADR3 => a(0),
O => N202
);
Mxor_ab_xor_Result_31_1 : X_LUT4
generic map(
INIT => X"5A5A",
LOC => "SLICE_X17Y35"
)
port map (
ADR0 => a_reg(31),
ADR1 => VCC,
ADR2 => b_reg(31),
ADR3 => VCC,
O => ab_xor_31_Q
);
Mxor_ba_xor_Result_31_1_SW0 : X_LUT4
generic map(
INIT => X"05AF",
LOC => "SLICE_X17Y35"
)
port map (
ADR0 => a(0),
ADR1 => VCC,
ADR2 => b_reg(31),
ADR3 => b_reg(30),
O => N196
);
Mxor_ab_xor_Result_16_1 : X_LUT4
generic map(
INIT => X"0FF0",
LOC => "SLICE_X14Y20"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => a_reg(16),
ADR3 => b_reg(16),
O => ab_xor_16_Q
);
Sh1141_SW1 : X_LUT4
generic map(
INIT => X"AA33",
LOC => "SLICE_X14Y20"
)
port map (
ADR0 => b_reg(15),
ADR1 => b_reg(16),
ADR2 => VCC,
ADR3 => a(0),
O => N194
);
Mxor_ab_xor_Result_24_1 : X_LUT4
generic map(
INIT => X"5A5A",
LOC => "SLICE_X18Y32"
)
port map (
ADR0 => b_reg(24),
ADR1 => VCC,
ADR2 => a_reg(24),
ADR3 => VCC,
O => ab_xor_24_Q
);
Sh1221_SW1 : X_LUT4
generic map(
INIT => X"DD11",
LOC => "SLICE_X18Y32"
)
port map (
ADR0 => b_reg(24),
ADR1 => a(0),
ADR2 => VCC,
ADR3 => b_reg(23),
O => N182
);
Mxor_ab_xor_Result_17_1 : X_LUT4
generic map(
INIT => X"0FF0",
LOC => "SLICE_X13Y23"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => b_reg(17),
ADR3 => a_reg(17),
O => ab_xor_17_Q
);
Mxor_ba_xor_Result_17_1_SW0 : X_LUT4
generic map(
INIT => X"0F55",
LOC => "SLICE_X13Y23"
)
port map (
ADR0 => b_reg(18),
ADR1 => VCC,
ADR2 => b_reg(17),
ADR3 => a(0),
O => N217
);
Mxor_ab_xor_Result_25_1 : X_LUT4
generic map(
INIT => X"3C3C",
LOC => "SLICE_X16Y33"
)
port map (
ADR0 => VCC,
ADR1 => b_reg(25),
ADR2 => a_reg(25),
ADR3 => VCC,
O => ab_xor_25_Q
);
Mxor_ba_xor_Result_25_1_SW0 : X_LUT4
generic map(
INIT => X"2277",
LOC => "SLICE_X16Y33"
)
port map (
ADR0 => a(0),
ADR1 => b_reg(25),
ADR2 => VCC,
ADR3 => b_reg(26),
O => N211
);
Mxor_ab_xor_Result_19_1 : X_LUT4
generic map(
INIT => X"33CC",
LOC => "SLICE_X18Y25"
)
port map (
ADR0 => VCC,
ADR1 => b_reg(19),
ADR2 => VCC,
ADR3 => a_reg(19),
O => ab_xor_19_Q
);
Mxor_ba_xor_Result_19_1_SW0 : X_LUT4
generic map(
INIT => X"4477",
LOC => "SLICE_X18Y25"
)
port map (
ADR0 => b_reg(18),
ADR1 => a(0),
ADR2 => VCC,
ADR3 => b_reg(19),
O => N205
);
Mxor_ab_xor_Result_27_1 : X_LUT4
generic map(
INIT => X"5A5A",
LOC => "SLICE_X19Y30"
)
port map (
ADR0 => b_reg(27),
ADR1 => VCC,
ADR2 => a_reg(27),
ADR3 => VCC,
O => ab_xor_27_Q
);
Mxor_ba_xor_Result_27_1_SW0 : X_LUT4
generic map(
INIT => X"05F5",
LOC => "SLICE_X19Y30"
)
port map (
ADR0 => b_reg(27),
ADR1 => VCC,
ADR2 => a(0),
ADR3 => b_reg(26),
O => N199
);
Mxor_ab_xor_Result_28_1 : X_LUT4
generic map(
INIT => X"6666",
LOC => "SLICE_X18Y34"
)
port map (
ADR0 => a_reg(28),
ADR1 => b_reg(28),
ADR2 => VCC,
ADR3 => VCC,
O => ab_xor_28_Q
);
Sh1261_SW1 : X_LUT4
generic map(
INIT => X"F303",
LOC => "SLICE_X18Y34"
)
port map (
ADR0 => VCC,
ADR1 => b_reg(28),
ADR2 => a(0),
ADR3 => b_reg(27),
O => N176
);
Mxor_ab_xor_Result_29_1 : X_LUT4
generic map(
INIT => X"55AA",
LOC => "SLICE_X16Y34"
)
port map (
ADR0 => a_reg(29),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => b_reg(29),
O => ab_xor_29_Q
);
Mxor_ba_xor_Result_29_1_SW0 : X_LUT4
generic map(
INIT => X"0F33",
LOC => "SLICE_X16Y34"
)
port map (
ADR0 => VCC,
ADR1 => b_reg(30),
ADR2 => b_reg(29),
ADR3 => a(0),
O => N208
);
Sh1141_SW0 : X_LUT4
generic map(
INIT => X"0F33",
LOC => "SLICE_X25Y21"
)
port map (
ADR0 => VCC,
ADR1 => b_reg(16),
ADR2 => b_reg(15),
ADR3 => a(0),
O => N193
);
Sh1151_SW1 : X_LUT4
generic map(
INIT => X"CC55",
LOC => "SLICE_X25Y21"
)
port map (
ADR0 => b_reg(17),
ADR1 => b_reg(16),
ADR2 => VCC,
ADR3 => a(0),
O => N191
);
Sh1221_SW0 : X_LUT4
generic map(
INIT => X"2277",
LOC => "SLICE_X20Y28"
)
port map (
ADR0 => a(0),
ADR1 => b_reg(23),
ADR2 => VCC,
ADR3 => b_reg(24),
O => N181
);
Sh1231_SW1 : X_LUT4
generic map(
INIT => X"88DD",
LOC => "SLICE_X20Y28"
)
port map (
ADR0 => a(0),
ADR1 => b_reg(24),
ADR2 => VCC,
ADR3 => b_reg(25),
O => N179
);
Sh1151_SW0 : X_LUT4
generic map(
INIT => X"3355",
LOC => "SLICE_X27Y21"
)
port map (
ADR0 => b_reg(17),
ADR1 => b_reg(16),
ADR2 => VCC,
ADR3 => a(0),
O => N190
);
Mxor_ba_xor_Result_3_1_SW3 : X_LUT4
generic map(
INIT => X"F033",
LOC => "SLICE_X27Y21"
)
port map (
ADR0 => VCC,
ADR1 => b_reg(3),
ADR2 => b_reg(2),
ADR3 => a(0),
O => N289
);
Sh1231_SW0 : X_LUT4
generic map(
INIT => X"3355",
LOC => "SLICE_X23Y26"
)
port map (
ADR0 => b_reg(25),
ADR1 => b_reg(24),
ADR2 => VCC,
ADR3 => a(0),
O => N178
);
Mxor_ba_xor_Result_3_1_SW2 : X_LUT4
generic map(
INIT => X"3355",
LOC => "SLICE_X23Y26"
)
port map (
ADR0 => b_reg(3),
ADR1 => b_reg(2),
ADR2 => VCC,
ADR3 => a(0),
O => N288
);
Sh1181_SW0 : X_LUT4
generic map(
INIT => X"11BB",
LOC => "SLICE_X24Y25"
)
port map (
ADR0 => a(0),
ADR1 => b_reg(20),
ADR2 => VCC,
ADR3 => b_reg(19),
O => N187
);
Sh1191_SW1 : X_LUT4
generic map(
INIT => X"BB11",
LOC => "SLICE_X24Y25"
)
port map (
ADR0 => a(0),
ADR1 => b_reg(21),
ADR2 => VCC,
ADR3 => b_reg(20),
O => N185
);
Sh1261_SW0 : X_LUT4
generic map(
INIT => X"11BB",
LOC => "SLICE_X22Y30"
)
port map (
ADR0 => a(0),
ADR1 => b_reg(28),
ADR2 => VCC,
ADR3 => b_reg(27),
O => N175
);
Sh1271_SW1 : X_LUT4
generic map(
INIT => X"DD11",
LOC => "SLICE_X22Y30"
)
port map (
ADR0 => b_reg(29),
ADR1 => a(0),
ADR2 => VCC,
ADR3 => b_reg(28),
O => N173
);
Sh1191_SW0 : X_LUT4
generic map(
INIT => X"2277",
LOC => "SLICE_X24Y26"
)
port map (
ADR0 => a(0),
ADR1 => b_reg(20),
ADR2 => VCC,
ADR3 => b_reg(21),
O => N184
);
Mxor_ba_xor_Result_3_1_SW1 : X_LUT4
generic map(
INIT => X"AF05",
LOC => "SLICE_X24Y26"
)
port map (
ADR0 => a(0),
ADR1 => VCC,
ADR2 => b_reg(4),
ADR3 => b_reg(3),
O => N264
);
Sh1271_SW0 : X_LUT4
generic map(
INIT => X"3535",
LOC => "SLICE_X22Y27"
)
port map (
ADR0 => b_reg(29),
ADR1 => b_reg(28),
ADR2 => a(0),
ADR3 => VCC,
O => N172
);
Mxor_ba_xor_Result_3_1_SW0 : X_LUT4
generic map(
INIT => X"05F5",
LOC => "SLICE_X22Y27"
)
port map (
ADR0 => b_reg(4),
ADR1 => VCC,
ADR2 => a(0),
ADR3 => b_reg(3),
O => N263
);
Sh701 : X_LUT4
generic map(
INIT => X"AFA0",
LOC => "SLICE_X16Y22"
)
port map (
ADR0 => Sh54,
ADR1 => VCC,
ADR2 => b_reg(4),
ADR3 => Sh38,
O => Sh70
);
Sh861 : X_LUT4
generic map(
INIT => X"FA0A",
LOC => "SLICE_X16Y22"
)
port map (
ADR0 => Sh54,
ADR1 => VCC,
ADR2 => b_reg(4),
ADR3 => Sh38,
O => Sh86
);
Sh711 : X_LUT4
generic map(
INIT => X"FA0A",
LOC => "SLICE_X18Y26"
)
port map (
ADR0 => Sh39,
ADR1 => VCC,
ADR2 => b_reg(4),
ADR3 => Sh55,
O => Sh71
);
Sh871 : X_LUT4
generic map(
INIT => X"AFA0",
LOC => "SLICE_X18Y26"
)
port map (
ADR0 => Sh39,
ADR1 => VCC,
ADR2 => b_reg(4),
ADR3 => Sh55,
O => Sh87
);
Sh641 : X_LUT4
generic map(
INIT => X"AACC",
LOC => "SLICE_X15Y24"
)
port map (
ADR0 => Sh48,
ADR1 => Sh32,
ADR2 => VCC,
ADR3 => b_reg(4),
O => Sh64
);
Sh801 : X_LUT4
generic map(
INIT => X"CCAA",
LOC => "SLICE_X15Y24"
)
port map (
ADR0 => Sh48,
ADR1 => Sh32,
ADR2 => VCC,
ADR3 => b_reg(4),
O => Sh80
);
Sh721 : X_LUT4
generic map(
INIT => X"EE44",
LOC => "SLICE_X12Y26"
)
port map (
ADR0 => b_reg(4),
ADR1 => Sh40,
ADR2 => VCC,
ADR3 => Sh56,
O => Sh72
);
Sh881 : X_LUT4
generic map(
INIT => X"DD88",
LOC => "SLICE_X12Y26"
)
port map (
ADR0 => b_reg(4),
ADR1 => Sh40,
ADR2 => VCC,
ADR3 => Sh56,
O => Sh88
);
Sh617 : X_LUT4
generic map(
INIT => X"FA0A",
LOC => "SLICE_X14Y21"
)
port map (
ADR0 => Sh25,
ADR1 => VCC,
ADR2 => b_reg(3),
ADR3 => Sh17,
O => Sh5720
);
Sh577 : X_LUT4
generic map(
INIT => X"F5A0",
LOC => "SLICE_X14Y21"
)
port map (
ADR0 => b_reg(3),
ADR1 => VCC,
ADR2 => Sh13,
ADR3 => Sh21,
O => Sh5320
);
Sh651 : X_LUT4
generic map(
INIT => X"AFA0",
LOC => "SLICE_X16Y18"
)
port map (
ADR0 => Sh49,
ADR1 => VCC,
ADR2 => b_reg(4),
ADR3 => Sh33,
O => Sh65
);
Sh811 : X_LUT4
generic map(
INIT => X"FA0A",
LOC => "SLICE_X16Y18"
)
port map (
ADR0 => Sh49,
ADR1 => VCC,
ADR2 => b_reg(4),
ADR3 => Sh33,
O => Sh81
);
Sh627 : X_LUT4
generic map(
INIT => X"F5A0",
LOC => "SLICE_X13Y29"
)
port map (
ADR0 => b_reg(3),
ADR1 => VCC,
ADR2 => Sh18,
ADR3 => Sh26,
O => Sh5820
);
Sh587 : X_LUT4
generic map(
INIT => X"EE44",
LOC => "SLICE_X13Y29"
)
port map (
ADR0 => b_reg(3),
ADR1 => Sh22_4347,
ADR2 => VCC,
ADR3 => Sh14,
O => Sh5420
);
Sh661 : X_LUT4
generic map(
INIT => X"D8D8",
LOC => "SLICE_X16Y23"
)
port map (
ADR0 => b_reg(4),
ADR1 => Sh50,
ADR2 => Sh34,
ADR3 => VCC,
O => Sh66
);
Sh821 : X_LUT4
generic map(
INIT => X"E4E4",
LOC => "SLICE_X16Y23"
)
port map (
ADR0 => b_reg(4),
ADR1 => Sh50,
ADR2 => Sh34,
ADR3 => VCC,
O => Sh82
);
Sh901 : X_LUT4
generic map(
INIT => X"ACAC",
LOC => "SLICE_X16Y21"
)
port map (
ADR0 => Sh42,
ADR1 => Sh58,
ADR2 => b_reg(4),
ADR3 => VCC,
O => Sh90
);
Mxor_ba_xor_Result_4_1_SW0 : X_LUT4
generic map(
INIT => X"550F",
LOC => "SLICE_X16Y21"
)
port map (
ADR0 => b_reg(4),
ADR1 => VCC,
ADR2 => b_reg(5),
ADR3 => a(0),
O => N246
);
Sh671 : X_LUT4
generic map(
INIT => X"CACA",
LOC => "SLICE_X16Y17"
)
port map (
ADR0 => Sh35,
ADR1 => Sh51,
ADR2 => b_reg(4),
ADR3 => VCC,
O => Sh67
);
Sh831 : X_LUT4
generic map(
INIT => X"ACAC",
LOC => "SLICE_X16Y17"
)
port map (
ADR0 => Sh35,
ADR1 => Sh51,
ADR2 => b_reg(4),
ADR3 => VCC,
O => Sh83
);
Sh751 : X_LUT4
generic map(
INIT => X"AFA0",
LOC => "SLICE_X16Y25"
)
port map (
ADR0 => Sh59,
ADR1 => VCC,
ADR2 => b_reg(4),
ADR3 => Sh43,
O => Sh75
);
Sh911 : X_LUT4
generic map(
INIT => X"FA0A",
LOC => "SLICE_X16Y25"
)
port map (
ADR0 => Sh59,
ADR1 => VCC,
ADR2 => b_reg(4),
ADR3 => Sh43,
O => Sh91
);
Sh681 : X_LUT4
generic map(
INIT => X"FA50",
LOC => "SLICE_X14Y18"
)
port map (
ADR0 => b_reg(4),
ADR1 => VCC,
ADR2 => Sh36,
ADR3 => Sh52,
O => Sh68
);
Sh841 : X_LUT4
generic map(
INIT => X"F5A0",
LOC => "SLICE_X14Y18"
)
port map (
ADR0 => b_reg(4),
ADR1 => VCC,
ADR2 => Sh36,
ADR3 => Sh52,
O => Sh84
);
Sh761 : X_LUT4
generic map(
INIT => X"CACA",
LOC => "SLICE_X16Y27"
)
port map (
ADR0 => Sh44,
ADR1 => Sh60,
ADR2 => b_reg(4),
ADR3 => VCC,
O => Sh76
);
Sh921 : X_LUT4
generic map(
INIT => X"ACAC",
LOC => "SLICE_X16Y27"
)
port map (
ADR0 => Sh44,
ADR1 => Sh60,
ADR2 => b_reg(4),
ADR3 => VCC,
O => Sh92
);
Sh691 : X_LUT4
generic map(
INIT => X"CACA",
LOC => "SLICE_X16Y24"
)
port map (
ADR0 => Sh37,
ADR1 => Sh53,
ADR2 => b_reg(4),
ADR3 => VCC,
O => Sh69
);
Sh851 : X_LUT4
generic map(
INIT => X"ACAC",
LOC => "SLICE_X16Y24"
)
port map (
ADR0 => Sh37,
ADR1 => Sh53,
ADR2 => b_reg(4),
ADR3 => VCC,
O => Sh85
);
Sh931 : X_LUT4
generic map(
INIT => X"ACAC",
LOC => "SLICE_X16Y31"
)
port map (
ADR0 => Sh45,
ADR1 => Sh61,
ADR2 => b_reg(4),
ADR3 => VCC,
O => Sh93
);
Sh791 : X_LUT4
generic map(
INIT => X"ACAC",
LOC => "SLICE_X16Y31"
)
port map (
ADR0 => Sh63,
ADR1 => Sh47,
ADR2 => b_reg(4),
ADR3 => VCC,
O => Sh79
);
Sh941 : X_LUT4
generic map(
INIT => X"FA50",
LOC => "SLICE_X16Y28"
)
port map (
ADR0 => b_reg(4),
ADR1 => VCC,
ADR2 => Sh62,
ADR3 => Sh46,
O => Sh94
);
Sh891 : X_LUT4
generic map(
INIT => X"D8D8",
LOC => "SLICE_X16Y28"
)
port map (
ADR0 => b_reg(4),
ADR1 => Sh41,
ADR2 => Sh57,
ADR3 => VCC,
O => Sh89
);
Sh991 : X_LUT4
generic map(
INIT => X"4747",
LOC => "SLICE_X25Y14"
)
port map (
ADR0 => b_reg(0),
ADR1 => a(0),
ADR2 => b_reg(1),
ADR3 => VCC,
O => Sh991_13638
);
Mxor_ba_xor_Result_7_1_SW0 : X_LUT4
generic map(
INIT => X"0C3F",
LOC => "SLICE_X25Y14"
)
port map (
ADR0 => VCC,
ADR1 => a(0),
ADR2 => b_reg(6),
ADR3 => b_reg(7),
O => N254
);
Sh992 : X_LUT4
generic map(
INIT => X"D18B",
LOC => "SLICE_X24Y18"
)
port map (
ADR0 => N289_0,
ADR1 => a(3),
ADR2 => N288_0,
ADR3 => a(2),
O => Sh1011_pack_1
);
Sh99_f51 : X_LUT4
generic map(
INIT => X"F3C0",
LOC => "SLICE_X24Y18"
)
port map (
ADR0 => VCC,
ADR1 => a(1),
ADR2 => Sh991_0,
ADR3 => Sh1011,
O => Sh99
);
b_reg_mux0000_2_5 : X_LUT4
generic map(
INIT => X"0F0A",
LOC => "SLICE_X9Y2"
)
port map (
ADR0 => swtch_led_1_OBUF_4254,
ADR1 => VCC,
ADR2 => Madd_b_pre_lut(2),
ADR3 => Madd_b_pre_cy_0_Q,
O => b_reg_mux0000_2_5_13686
);
b_reg_mux0000_2_13 : X_LUT4
generic map(
INIT => X"0050",
LOC => "SLICE_X9Y2"
)
port map (
ADR0 => swtch_led_1_OBUF_4254,
ADR1 => VCC,
ADR2 => Madd_b_pre_lut(2),
ADR3 => Madd_b_pre_cy_0_Q,
O => b_reg_mux0000_2_13_13694
);
b_reg_0 : X_FF
generic map(
LOC => "SLICE_X13Y15",
INIT => '0'
)
port map (
I => b_reg_1_DYMUX_13719,
CE => VCC,
CLK => b_reg_1_CLKINV_13710,
SET => GND,
RST => b_reg_1_SRINV_13711,
O => b_reg(0)
);
b_reg_mux0000_1_38_F : X_LUT4
generic map(
INIT => X"9F90",
LOC => "SLICE_X13Y15"
)
port map (
ADR0 => swtch_led_1_OBUF_4254,
ADR1 => Madd_b_pre_cy_0_Q,
ADR2 => state_FSM_FFd2_4312,
ADR3 => b_reg(1),
O => N498
);
b_reg_mux0000_1_38_G : X_LUT4
generic map(
INIT => X"FA0A",
LOC => "SLICE_X13Y15"
)
port map (
ADR0 => b_reg(1),
ADR1 => VCC,
ADR2 => state_FSM_FFd2_4312,
ADR3 => b_1_Q,
O => N499
);
b_reg_1 : X_FF
generic map(
LOC => "SLICE_X13Y15",
INIT => '0'
)
port map (
I => b_reg_1_DXMUX_13736,
CE => VCC,
CLK => b_reg_1_CLKINV_13710,
SET => GND,
RST => b_reg_1_SRINV_13711,
O => b_reg(1)
);
b_reg_2 : X_FF
generic map(
LOC => "SLICE_X3Y18",
INIT => '0'
)
port map (
I => b_reg_3_DYMUX_13752,
CE => VCC,
CLK => b_reg_3_CLKINV_13749,
SET => GND,
RST => b_reg_3_SRINV_13750,
O => b_reg(2)
);
b_reg_3 : X_FF
generic map(
LOC => "SLICE_X3Y18",
INIT => '0'
)
port map (
I => b_reg_3_DXMUX_13760,
CE => VCC,
CLK => b_reg_3_CLKINV_13749,
SET => GND,
RST => b_reg_3_SRINV_13750,
O => b_reg(3)
);
b_reg_mux0000_5_38 : X_LUT4
generic map(
INIT => X"CFC0",
LOC => "SLICE_X2Y16"
)
port map (
ADR0 => VCC,
ADR1 => N276,
ADR2 => b_5_Q,
ADR3 => N275,
O => b_reg_mux0000_5_Q
);
b_reg_5 : X_FF
generic map(
LOC => "SLICE_X2Y16",
INIT => '0'
)
port map (
I => b_reg_4_DYMUX_13785,
CE => VCC,
CLK => b_reg_4_CLKINV_13775,
SET => GND,
RST => b_reg_4_SRINV_13776,
O => b_reg(5)
);
b_reg_4 : X_FF
generic map(
LOC => "SLICE_X2Y16",
INIT => '0'
)
port map (
I => b_reg_4_DXMUX_13793,
CE => VCC,
CLK => b_reg_4_CLKINV_13775,
SET => GND,
RST => b_reg_4_SRINV_13776,
O => b_reg(4)
);
b_reg_mux0000_4_3 : X_LUT4
generic map(
INIT => X"CCC0",
LOC => "SLICE_X0Y20"
)
port map (
ADR0 => VCC,
ADR1 => swtch_led_4_OBUF_4257,
ADR2 => swtch_led_3_OBUF_4256,
ADR3 => Madd_b_pre_cy_2_Q,
O => b_reg_mux0000_4_3_13813
);
b_reg_mux0000_4_12 : X_LUT4
generic map(
INIT => X"0003",
LOC => "SLICE_X0Y20"
)
port map (
ADR0 => VCC,
ADR1 => swtch_led_4_OBUF_4257,
ADR2 => swtch_led_3_OBUF_4256,
ADR3 => Madd_b_pre_cy_2_Q,
O => b_reg_mux0000_4_12_13821
);
b_reg_mux0000_6_3 : X_LUT4
generic map(
INIT => X"EE00",
LOC => "SLICE_X2Y12"
)
port map (
ADR0 => swtch_led_5_OBUF_4258,
ADR1 => Madd_b_pre_cy_4_0,
ADR2 => VCC,
ADR3 => swtch_led_6_OBUF_4259,
O => b_reg_mux0000_6_3_13837
);
b_reg_mux0000_6_12 : X_LUT4
generic map(
INIT => X"0011",
LOC => "SLICE_X2Y12"
)
port map (
ADR0 => swtch_led_5_OBUF_4258,
ADR1 => Madd_b_pre_cy_4_0,
ADR2 => VCC,
ADR3 => swtch_led_6_OBUF_4259,
O => b_reg_mux0000_6_12_13845
);
Sh1537 : X_LUT4
generic map(
INIT => X"E4E4",
LOC => "SLICE_X24Y14"
)
port map (
ADR0 => a(3),
ADR1 => Sh117,
ADR2 => Sh109,
ADR3 => VCC,
O => Sh1537_14053
);
Sh1497 : X_LUT4
generic map(
INIT => X"ACAC",
LOC => "SLICE_X24Y14"
)
port map (
ADR0 => Sh105,
ADR1 => Sh113,
ADR2 => a(3),
ADR3 => VCC,
O => Sh1497_14061
);
Sh1811 : X_LUT4
generic map(
INIT => X"EE22",
LOC => "SLICE_X20Y21"
)
port map (
ADR0 => Sh149,
ADR1 => a(4),
ADR2 => VCC,
ADR3 => Sh133,
O => Sh181
);
Sh1771 : X_LUT4
generic map(
INIT => X"F3C0",
LOC => "SLICE_X20Y21"
)
port map (
ADR0 => VCC,
ADR1 => a(4),
ADR2 => Sh129,
ADR3 => Sh145,
O => Sh177
);
Sh1821 : X_LUT4
generic map(
INIT => X"EE44",
LOC => "SLICE_X23Y23"
)
port map (
ADR0 => a(4),
ADR1 => Sh150_0,
ADR2 => VCC,
ADR3 => Sh134,
O => Sh182
);
Sh1831 : X_LUT4
generic map(
INIT => X"EE44",
LOC => "SLICE_X23Y23"
)
port map (
ADR0 => a(4),
ADR1 => Sh151,
ADR2 => VCC,
ADR3 => Sh135,
O => Sh183
);
Sh1901 : X_LUT4
generic map(
INIT => X"AFA0",
LOC => "SLICE_X20Y24"
)
port map (
ADR0 => Sh142,
ADR1 => VCC,
ADR2 => a(4),
ADR3 => Sh158,
O => Sh190
);
Sh1841 : X_LUT4
generic map(
INIT => X"F0CC",
LOC => "SLICE_X20Y24"
)
port map (
ADR0 => VCC,
ADR1 => Sh152,
ADR2 => Sh136,
ADR3 => a(4),
O => Sh184
);
Sh1851 : X_LUT4
generic map(
INIT => X"CFC0",
LOC => "SLICE_X23Y18"
)
port map (
ADR0 => VCC,
ADR1 => Sh137,
ADR2 => a(4),
ADR3 => Sh153,
O => Sh185
);
Sh1861 : X_LUT4
generic map(
INIT => X"CFC0",
LOC => "SLICE_X23Y18"
)
port map (
ADR0 => VCC,
ADR1 => Sh138,
ADR2 => a(4),
ADR3 => Sh154_0,
O => Sh186
);
Sh1871 : X_LUT4
generic map(
INIT => X"EE44",
LOC => "SLICE_X23Y24"
)
port map (
ADR0 => a(4),
ADR1 => Sh155,
ADR2 => VCC,
ADR3 => Sh139,
O => Sh187
);
Sh1881 : X_LUT4
generic map(
INIT => X"F5A0",
LOC => "SLICE_X23Y24"
)
port map (
ADR0 => a(4),
ADR1 => VCC,
ADR2 => Sh140,
ADR3 => Sh156,
O => Sh188
);
Sh6120 : X_LUT4
generic map(
INIT => X"E4E4",
LOC => "SLICE_X15Y28"
)
port map (
ADR0 => b_reg(3),
ADR1 => Sh29,
ADR2 => Sh21,
ADR3 => VCC,
O => Sh337
);
Sh6220 : X_LUT4
generic map(
INIT => X"FA0A",
LOC => "SLICE_X15Y28"
)
port map (
ADR0 => Sh30,
ADR1 => VCC,
ADR2 => b_reg(3),
ADR3 => Sh22_4347,
O => Sh347
);
Sh1891 : X_LUT4
generic map(
INIT => X"AACC",
LOC => "SLICE_X20Y26"
)
port map (
ADR0 => Sh141,
ADR1 => Sh157,
ADR2 => VCC,
ADR3 => a(4),
O => Sh189
);
Madd_b_pre_cy_2_11 : X_LUT4
generic map(
INIT => X"CCC0",
LOC => "SLICE_X3Y15"
)
port map (
ADR0 => VCC,
ADR1 => Madd_b_pre_lut(2),
ADR2 => swtch_led_1_OBUF_4254,
ADR3 => Madd_b_pre_cy_0_Q,
O => Madd_b_pre_cy_2_pack_1
);
Madd_b_pre_cy_4_11 : X_LUT4
generic map(
INIT => X"FFEE",
LOC => "SLICE_X3Y15"
)
port map (
ADR0 => swtch_led_3_OBUF_4256,
ADR1 => swtch_led_4_OBUF_4257,
ADR2 => VCC,
ADR3 => Madd_b_pre_cy_2_Q,
O => Madd_b_pre_cy_4_Q
);
Madd_b_pre_cy_6_11 : X_LUT4
generic map(
INIT => X"FFEE",
LOC => "SLICE_X2Y14"
)
port map (
ADR0 => swtch_led_5_OBUF_4258,
ADR1 => Madd_b_pre_cy_4_0,
ADR2 => VCC,
ADR3 => swtch_led_6_OBUF_4259,
O => Madd_b_pre_cy_6_pack_1
);
b_reg_mux0000_8_10 : X_LUT4
generic map(
INIT => X"0002",
LOC => "SLICE_X2Y14"
)
port map (
ADR0 => state_FSM_FFd2_4312,
ADR1 => state_FSM_FFd1_4311,
ADR2 => swtch_led_7_OBUF_4260,
ADR3 => Madd_b_pre_cy_6_Q,
O => b_reg_mux0000_10_10
);
hex2_7seg_Mrom_segment_data11 : X_LUT4
generic map(
INIT => X"0285",
LOC => "SLICE_X29Y9"
)
port map (
ADR0 => hex_digit_i(2),
ADR1 => hex_digit_i(0),
ADR2 => hex_digit_i(1),
ADR3 => hex_digit_i(3),
O => segment_g_i_OBUF_14282
);
hex2_7seg_Mrom_segment_data61 : X_LUT4
generic map(
INIT => X"4806",
LOC => "SLICE_X29Y9"
)
port map (
ADR0 => hex_digit_i(2),
ADR1 => hex_digit_i(0),
ADR2 => hex_digit_i(1),
ADR3 => hex_digit_i(3),
O => segment_a_i_OBUF_14289
);
hex2_7seg_Mrom_segment_data21 : X_LUT4
generic map(
INIT => X"5170",
LOC => "SLICE_X28Y9"
)
port map (
ADR0 => hex_digit_i(3),
ADR1 => hex_digit_i(1),
ADR2 => hex_digit_i(0),
ADR3 => hex_digit_i(2),
O => segment_e_i_OBUF_14306
);
hex2_7seg_Mrom_segment_data31 : X_LUT4
generic map(
INIT => X"C118",
LOC => "SLICE_X28Y9"
)
port map (
ADR0 => hex_digit_i(3),
ADR1 => hex_digit_i(1),
ADR2 => hex_digit_i(0),
ADR3 => hex_digit_i(2),
O => segment_d_i_OBUF_14313
);
hex2_7seg_Mrom_segment_data41 : X_LUT4
generic map(
INIT => X"A210",
LOC => "SLICE_X29Y8"
)
port map (
ADR0 => hex_digit_i(2),
ADR1 => hex_digit_i(0),
ADR2 => hex_digit_i(1),
ADR3 => hex_digit_i(3),
O => segment_c_i_OBUF_14330
);
hex2_7seg_Mrom_segment_data111 : X_LUT4
generic map(
INIT => X"08D4",
LOC => "SLICE_X29Y8"
)
port map (
ADR0 => hex_digit_i(2),
ADR1 => hex_digit_i(0),
ADR2 => hex_digit_i(1),
ADR3 => hex_digit_i(3),
O => segment_f_i_OBUF_14337
);
hex2_7seg_Mrom_segment_data51 : X_LUT4
generic map(
INIT => X"9E80",
LOC => "SLICE_X28Y12"
)
port map (
ADR0 => hex_digit_i(3),
ADR1 => hex_digit_i(1),
ADR2 => hex_digit_i(0),
ADR3 => hex_digit_i(2),
O => segment_b_i_OBUF_14349
);
i_cnt_mux0001_0_45_SW0 : X_LUT4
generic map(
INIT => X"BFF3",
LOC => "SLICE_X18Y14"
)
port map (
ADR0 => i_cnt_mux0001_0_25_0,
ADR1 => i_cnt(2),
ADR2 => i_cnt(1),
ADR3 => i_cnt(0),
O => N514
);
Mrom_b_rom0000821 : X_LUT4
generic map(
INIT => X"F033",
LOC => "SLICE_X18Y14"
)
port map (
ADR0 => VCC,
ADR1 => i_cnt(2),
ADR2 => i_cnt(1),
ADR3 => i_cnt(0),
O => N14
);
i_cnt_mux0001_1_27_SW0 : X_LUT4
generic map(
INIT => X"9975",
LOC => "SLICE_X19Y28"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(1),
ADR2 => i_cnt(3),
ADR3 => i_cnt(0),
O => N516_pack_3
);
i_cnt_mux0001_1_27 : X_LUT4
generic map(
INIT => X"44E4",
LOC => "SLICE_X19Y28"
)
port map (
ADR0 => state_FSM_FFd2_4312,
ADR1 => i_cnt(2),
ADR2 => state_FSM_FFd1_4311,
ADR3 => N516,
O => i_cnt_mux0001(1)
);
i_cnt_2 : X_FF
generic map(
LOC => "SLICE_X19Y28",
INIT => '0'
)
port map (
I => i_cnt_2_DXMUX_14404,
CE => VCC,
CLK => i_cnt_2_CLKINV_14388,
SET => GND,
RST => i_cnt_2_FFX_RSTAND_14409,
O => i_cnt(2)
);
i_cnt_2_FFX_RSTAND : X_BUF
generic map(
LOC => "SLICE_X19Y28",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_3948,
O => i_cnt_2_FFX_RSTAND_14409
);
Mrom_a_rom0000101 : X_LUT4
generic map(
INIT => X"504C",
LOC => "SLICE_X18Y18"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(2),
ADR2 => i_cnt(1),
ADR3 => i_cnt(0),
O => Mrom_a_rom000010
);
Mrom_b_rom000012 : X_LUT4
generic map(
INIT => X"0065",
LOC => "SLICE_X18Y18"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(2),
ADR2 => i_cnt(0),
ADR3 => i_cnt(1),
O => Mrom_b_rom000012_14432
);
Mrom_a_rom0000111 : X_LUT4
generic map(
INIT => X"54BD",
LOC => "SLICE_X19Y21"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(0),
ADR2 => i_cnt(1),
ADR3 => i_cnt(3),
O => Mrom_a_rom000011_14449
);
Mrom_b_rom000020 : X_LUT4
generic map(
INIT => X"50A9",
LOC => "SLICE_X19Y21"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(0),
ADR2 => i_cnt(1),
ADR3 => i_cnt(3),
O => Mrom_b_rom000020_14456
);
Mrom_a_rom0000211 : X_LUT4
generic map(
INIT => X"175D",
LOC => "SLICE_X16Y19"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(0),
ADR2 => i_cnt(2),
ADR3 => i_cnt(1),
O => Mrom_a_rom000021
);
Mrom_b_rom00008 : X_LUT4
generic map(
INIT => X"4F29",
LOC => "SLICE_X16Y19"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(0),
ADR2 => i_cnt(2),
ADR3 => i_cnt(1),
O => Mrom_b_rom00008_14480
);
Mrom_a_rom0000301 : X_LUT4
generic map(
INIT => X"176C",
LOC => "SLICE_X19Y29"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(1),
ADR2 => i_cnt(3),
ADR3 => i_cnt(0),
O => Mrom_a_rom000030
);
Mrom_b_rom000013 : X_LUT4
generic map(
INIT => X"456B",
LOC => "SLICE_X19Y29"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(1),
ADR2 => i_cnt(3),
ADR3 => i_cnt(0),
O => Mrom_b_rom000013_14504
);
Mrom_a_rom0000311 : X_LUT4
generic map(
INIT => X"0A21",
LOC => "SLICE_X21Y29"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(1),
ADR2 => i_cnt(3),
ADR3 => i_cnt(0),
O => Mrom_a_rom000031
);
Mrom_b_rom0000311 : X_LUT4
generic map(
INIT => X"0C50",
LOC => "SLICE_X21Y29"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(1),
ADR2 => i_cnt(3),
ADR3 => i_cnt(0),
O => Mrom_b_rom000031
);
Mrom_a_rom0000251 : X_LUT4
generic map(
INIT => X"0939",
LOC => "SLICE_X20Y25"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(1),
ADR2 => i_cnt(3),
ADR3 => i_cnt(0),
O => Mrom_a_rom000025
);
Mrom_b_rom0000232 : X_LUT4
generic map(
INIT => X"081A",
LOC => "SLICE_X20Y25"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(1),
ADR2 => i_cnt(3),
ADR3 => i_cnt(0),
O => Mrom_b_rom000023
);
Mrom_a_rom0000261 : X_LUT4
generic map(
INIT => X"2646",
LOC => "SLICE_X20Y29"
)
port map (
ADR0 => i_cnt(0),
ADR1 => i_cnt(3),
ADR2 => i_cnt(1),
ADR3 => i_cnt(2),
O => Mrom_a_rom000026
);
Mrom_b_rom0000171 : X_LUT4
generic map(
INIT => X"225D",
LOC => "SLICE_X20Y29"
)
port map (
ADR0 => i_cnt(0),
ADR1 => i_cnt(3),
ADR2 => i_cnt(1),
ADR3 => i_cnt(2),
O => Mrom_b_rom000017_14576
);
Mrom_a_rom0000191 : X_LUT4
generic map(
INIT => X"1473",
LOC => "SLICE_X17Y14"
)
port map (
ADR0 => i_cnt(0),
ADR1 => i_cnt(3),
ADR2 => i_cnt(1),
ADR3 => i_cnt(2),
O => Mrom_a_rom000019
);
Mrom_b_rom000071 : X_LUT4
generic map(
INIT => X"1403",
LOC => "SLICE_X17Y14"
)
port map (
ADR0 => i_cnt(0),
ADR1 => i_cnt(3),
ADR2 => i_cnt(1),
ADR3 => i_cnt(2),
O => Mrom_b_rom00007
);
Mrom_a_rom0000271 : X_LUT4
generic map(
INIT => X"0049",
LOC => "SLICE_X20Y27"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(1),
ADR2 => i_cnt(2),
ADR3 => i_cnt(0),
O => Mrom_a_rom000027
);
Mrom_b_rom0000301 : X_LUT4
generic map(
INIT => X"5D20",
LOC => "SLICE_X20Y27"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(1),
ADR2 => i_cnt(2),
ADR3 => i_cnt(0),
O => Mrom_b_rom000030
);
Mxor_ba_xor_Result_11_1_SW0 : X_LUT4
generic map(
INIT => X"5353",
LOC => "SLICE_X18Y10"
)
port map (
ADR0 => b_reg(10),
ADR1 => b_reg(11),
ADR2 => a(0),
ADR3 => VCC,
O => N251
);
Mxor_ba_xor_Result_9_1_SW0 : X_LUT4
generic map(
INIT => X"5353",
LOC => "SLICE_X18Y10"
)
port map (
ADR0 => b_reg(9),
ADR1 => b_reg(10),
ADR2 => a(0),
ADR3 => VCC,
O => N237
);
Mrom_b_rom00001111 : X_LUT4
generic map(
INIT => X"044A",
LOC => "SLICE_X20Y23"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(0),
ADR2 => i_cnt(3),
ADR3 => i_cnt(1),
O => Mrom_b_rom000011_14665
);
Mrom_b_rom0000281 : X_LUT4
generic map(
INIT => X"4459",
LOC => "SLICE_X20Y23"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(0),
ADR2 => i_cnt(2),
ADR3 => i_cnt(1),
O => Mrom_b_rom000028
);
Mxor_ba_xor_Result_12_1_SW0 : X_LUT4
generic map(
INIT => X"0F55",
LOC => "SLICE_X23Y14"
)
port map (
ADR0 => b_reg(13),
ADR1 => VCC,
ADR2 => b_reg(12),
ADR3 => a(0),
O => N234
);
Mxor_ba_xor_Result_13_1_SW0 : X_LUT4
generic map(
INIT => X"550F",
LOC => "SLICE_X23Y14"
)
port map (
ADR0 => b_reg(13),
ADR1 => VCC,
ADR2 => b_reg(14),
ADR3 => a(0),
O => N231
);
Mrom_b_rom00002611 : X_LUT4
generic map(
INIT => X"1050",
LOC => "SLICE_X22Y23"
)
port map (
ADR0 => i_cnt(0),
ADR1 => i_cnt(1),
ADR2 => i_cnt(3),
ADR3 => i_cnt(2),
O => N77
);
Mrom_b_rom0000262 : X_LUT4
generic map(
INIT => X"1C5A",
LOC => "SLICE_X22Y23"
)
port map (
ADR0 => i_cnt(0),
ADR1 => i_cnt(1),
ADR2 => i_cnt(3),
ADR3 => i_cnt(2),
O => Mrom_b_rom000026
);
Mrom_b_rom00001821 : X_LUT4
generic map(
INIT => X"0011",
LOC => "SLICE_X20Y15"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(3),
ADR2 => VCC,
ADR3 => i_cnt(1),
O => N34
);
Mrom_b_rom00002721 : X_LUT4
generic map(
INIT => X"0022",
LOC => "SLICE_X20Y15"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(2),
ADR2 => VCC,
ADR3 => i_cnt(1),
O => N33
);
state_FSM_Out21 : X_LUT4
generic map(
INIT => X"3300",
LOC => "SLICE_X3Y0"
)
port map (
ADR0 => VCC,
ADR1 => state_FSM_FFd2_4312,
ADR2 => VCC,
ADR3 => state_FSM_FFd1_4311,
O => do_rdy_OBUF_14756
);
Mrom_a_rom000011 : X_LUT4
generic map(
INIT => X"0B42",
LOC => "SLICE_X19Y16"
)
port map (
ADR0 => i_cnt(1),
ADR1 => i_cnt(0),
ADR2 => i_cnt(2),
ADR3 => i_cnt(3),
O => Mrom_a_rom00001
);
Mrom_b_rom0000221 : X_LUT4
generic map(
INIT => X"0182",
LOC => "SLICE_X19Y16"
)
port map (
ADR0 => i_cnt(1),
ADR1 => i_cnt(0),
ADR2 => i_cnt(2),
ADR3 => i_cnt(3),
O => Mrom_b_rom000022
);
Mrom_a_rom000012 : X_LUT4
generic map(
INIT => X"445C",
LOC => "SLICE_X18Y17"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(2),
ADR2 => i_cnt(0),
ADR3 => i_cnt(1),
O => Mrom_a_rom0000
);
Mrom_b_rom0000161 : X_LUT4
generic map(
INIT => X"3503",
LOC => "SLICE_X18Y17"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(2),
ADR2 => i_cnt(0),
ADR3 => i_cnt(1),
O => Mrom_b_rom000016
);
Mrom_a_rom000013 : X_LUT4
generic map(
INIT => X"2552",
LOC => "SLICE_X18Y16"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(2),
ADR2 => i_cnt(0),
ADR3 => i_cnt(1),
O => Mrom_a_rom000013_14821
);
Mrom_b_rom0000101 : X_LUT4
generic map(
INIT => X"5421",
LOC => "SLICE_X18Y16"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(2),
ADR2 => i_cnt(0),
ADR3 => i_cnt(1),
O => Mrom_b_rom000010
);
Mrom_a_rom000023 : X_LUT4
generic map(
INIT => X"42BF",
LOC => "SLICE_X18Y23"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(0),
ADR2 => i_cnt(1),
ADR3 => i_cnt(2),
O => Mrom_a_rom000023_14845
);
Mrom_b_rom000061 : X_LUT4
generic map(
INIT => X"1123",
LOC => "SLICE_X18Y23"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(0),
ADR2 => i_cnt(1),
ADR3 => i_cnt(3),
O => Mrom_b_rom00006
);
Mrom_a_rom000015 : X_LUT4
generic map(
INIT => X"0605",
LOC => "SLICE_X19Y17"
)
port map (
ADR0 => i_cnt(1),
ADR1 => i_cnt(0),
ADR2 => i_cnt(2),
ADR3 => i_cnt(3),
O => Mrom_a_rom000015_14869
);
Mrom_b_rom00009 : X_LUT4
generic map(
INIT => X"1993",
LOC => "SLICE_X19Y17"
)
port map (
ADR0 => i_cnt(1),
ADR1 => i_cnt(0),
ADR2 => i_cnt(2),
ADR3 => i_cnt(3),
O => Mrom_b_rom00009_14876
);
Mrom_a_rom000024 : X_LUT4
generic map(
INIT => X"3169",
LOC => "SLICE_X18Y29"
)
port map (
ADR0 => i_cnt(0),
ADR1 => i_cnt(3),
ADR2 => i_cnt(1),
ADR3 => i_cnt(2),
O => Mrom_a_rom000024_14893
);
Mrom_b_rom0000211 : X_LUT4
generic map(
INIT => X"0325",
LOC => "SLICE_X18Y29"
)
port map (
ADR0 => i_cnt(0),
ADR1 => i_cnt(3),
ADR2 => i_cnt(1),
ADR3 => i_cnt(2),
O => Mrom_b_rom000021
);
Mrom_a_rom000016 : X_LUT4
generic map(
INIT => X"0E71",
LOC => "SLICE_X20Y20"
)
port map (
ADR0 => i_cnt(1),
ADR1 => i_cnt(0),
ADR2 => i_cnt(2),
ADR3 => i_cnt(3),
O => Mrom_a_rom000016_14917
);
Mrom_b_rom000014 : X_LUT4
generic map(
INIT => X"114D",
LOC => "SLICE_X20Y20"
)
port map (
ADR0 => i_cnt(1),
ADR1 => i_cnt(0),
ADR2 => i_cnt(2),
ADR3 => i_cnt(3),
O => Mrom_b_rom000014_14924
);
Mrom_a_rom000017 : X_LUT4
generic map(
INIT => X"0E49",
LOC => "SLICE_X20Y19"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(0),
ADR2 => i_cnt(2),
ADR3 => i_cnt(1),
O => Mrom_a_rom000017_14941
);
Mrom_b_rom000011 : X_LUT4
generic map(
INIT => X"4709",
LOC => "SLICE_X20Y19"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(0),
ADR2 => i_cnt(2),
ADR3 => i_cnt(1),
O => Mrom_b_rom00001
);
Mrom_a_rom000018 : X_LUT4
generic map(
INIT => X"362C",
LOC => "SLICE_X16Y30"
)
port map (
ADR0 => i_cnt(0),
ADR1 => i_cnt(2),
ADR2 => i_cnt(1),
ADR3 => i_cnt(3),
O => Mrom_a_rom000018_14965
);
Mrom_a_rom000029 : X_LUT4
generic map(
INIT => X"2794",
LOC => "SLICE_X16Y30"
)
port map (
ADR0 => i_cnt(0),
ADR1 => i_cnt(2),
ADR2 => i_cnt(1),
ADR3 => i_cnt(3),
O => Mrom_a_rom000029_14972
);
Mrom_a_rom000061 : X_LUT4
generic map(
INIT => X"5255",
LOC => "SLICE_X18Y24"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(2),
ADR2 => i_cnt(0),
ADR3 => i_cnt(1),
O => Mrom_a_rom00006
);
Mrom_b_rom000029 : X_LUT4
generic map(
INIT => X"176A",
LOC => "SLICE_X18Y24"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(2),
ADR2 => i_cnt(0),
ADR3 => i_cnt(1),
O => Mrom_b_rom000029_14996
);
Mrom_a_rom000081 : X_LUT4
generic map(
INIT => X"190A",
LOC => "SLICE_X16Y20"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(0),
ADR2 => i_cnt(2),
ADR3 => i_cnt(1),
O => Mrom_a_rom00008
);
Mrom_a_rom00009 : X_LUT4
generic map(
INIT => X"1B18",
LOC => "SLICE_X16Y20"
)
port map (
ADR0 => i_cnt(3),
ADR1 => i_cnt(0),
ADR2 => i_cnt(2),
ADR3 => i_cnt(1),
O => Mrom_a_rom00009_15020
);
Mrom_b_rom0000191 : X_LUT4
generic map(
INIT => X"0DF6",
LOC => "SLICE_X19Y19"
)
port map (
ADR0 => i_cnt(1),
ADR1 => i_cnt(0),
ADR2 => i_cnt(2),
ADR3 => i_cnt(3),
O => Mrom_b_rom000019
);
Mrom_a_rom00005 : X_LUT4
generic map(
INIT => X"1620",
LOC => "SLICE_X19Y19"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(1),
ADR2 => i_cnt(0),
ADR3 => i_cnt(3),
O => Mrom_a_rom00005_15044
);
Mrom_b_rom0000271 : X_LUT4
generic map(
INIT => X"1491",
LOC => "SLICE_X18Y22"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(0),
ADR2 => i_cnt(1),
ADR3 => i_cnt(3),
O => Mrom_b_rom000027
);
Mrom_a_rom00002 : X_LUT4
generic map(
INIT => X"1146",
LOC => "SLICE_X18Y22"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(0),
ADR2 => i_cnt(1),
ADR3 => i_cnt(3),
O => Mrom_a_rom00002_15068
);
state_cmp_eq00001 : X_LUT4
generic map(
INIT => X"0008",
LOC => "SLICE_X15Y10"
)
port map (
ADR0 => i_cnt(2),
ADR1 => i_cnt(3),
ADR2 => i_cnt(1),
ADR3 => i_cnt(0),
O => state_cmp_eq0000_pack_4
);
state_FSM_FFd1 : X_FF
generic map(
LOC => "SLICE_X15Y10",
INIT => '0'
)
port map (
I => state_FSM_FFd2_DYMUX_15095,
CE => VCC,
CLK => state_FSM_FFd2_CLKINV_15085,
SET => GND,
RST => state_FSM_FFd2_SRINV_15086,
O => state_FSM_FFd1_4311
);
state_FSM_FFd2_In1 : X_LUT4
generic map(
INIT => X"5F44",
LOC => "SLICE_X15Y10"
)
port map (
ADR0 => state_FSM_FFd1_4311,
ADR1 => di_vld_IBUF_4273,
ADR2 => state_cmp_eq0000,
ADR3 => state_FSM_FFd2_4312,
O => state_FSM_FFd2_In
);
state_FSM_FFd2 : X_FF
generic map(
LOC => "SLICE_X15Y10",
INIT => '0'
)
port map (
I => state_FSM_FFd2_DXMUX_15109,
CE => VCC,
CLK => state_FSM_FFd2_CLKINV_15085,
SET => GND,
RST => state_FSM_FFd2_SRINV_15086,
O => state_FSM_FFd2_4312
);
Mrom_a_rom00004 : X_LUT4
generic map(
INIT => X"1738",
LOC => "SLICE_X19Y15"
)
port map (
ADR0 => i_cnt(1),
ADR1 => i_cnt(0),
ADR2 => i_cnt(2),
ADR3 => i_cnt(3),
O => Mrom_a_rom00004_15130
);
Mrom_b_rom000017 : X_LUT4
generic map(
INIT => X"0777",
LOC => "SLICE_X19Y15"
)
port map (
ADR0 => i_cnt(1),
ADR1 => i_cnt(0),
ADR2 => i_cnt(2),
ADR3 => i_cnt(3),
O => Mrom_b_rom0000
);
Mxor_ba_xor_Result_5_1_SW0 : X_LUT4
generic map(
INIT => X"0F55",
LOC => "SLICE_X19Y12"
)
port map (
ADR0 => b_reg(6),
ADR1 => VCC,
ADR2 => b_reg(5),
ADR3 => a(0),
O => N243
);
Mxor_ba_xor_Result_8_1_SW0 : X_LUT4
generic map(
INIT => X"3355",
LOC => "SLICE_X19Y12"
)
port map (
ADR0 => b_reg(9),
ADR1 => b_reg(8),
ADR2 => VCC,
ADR3 => a(0),
O => N240
);
LED_flash_cnt_0_G_X_LUT4 : X_LUT4
generic map(
INIT => X"CCCC",
LOC => "SLICE_X31Y10"
)
port map (
ADR0 => VCC,
ADR1 => LED_flash_cnt(1),
ADR2 => VCC,
ADR3 => VCC,
O => LED_flash_cnt_0_G
);
LED_flash_cnt_2_F_X_LUT4 : X_LUT4
generic map(
INIT => X"AAAA",
LOC => "SLICE_X31Y11"
)
port map (
ADR0 => LED_flash_cnt(2),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => LED_flash_cnt_2_F
);
LED_flash_cnt_2_G_X_LUT4 : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X31Y11"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => LED_flash_cnt(3),
O => LED_flash_cnt_2_G
);
LED_flash_cnt_4_F_X_LUT4 : X_LUT4
generic map(
INIT => X"AAAA",
LOC => "SLICE_X31Y12"
)
port map (
ADR0 => LED_flash_cnt(4),
ADR1 => VCC,
ADR2 => VCC,
ADR3 => VCC,
O => LED_flash_cnt_4_F
);
LED_flash_cnt_4_G_X_LUT4 : X_LUT4
generic map(
INIT => X"F0F0",
LOC => "SLICE_X31Y12"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => LED_flash_cnt(5),
ADR3 => VCC,
O => LED_flash_cnt_4_G
);
LED_flash_cnt_6_F_X_LUT4 : X_LUT4
generic map(
INIT => X"CCCC",
LOC => "SLICE_X31Y13"
)
port map (
ADR0 => VCC,
ADR1 => LED_flash_cnt(6),
ADR2 => VCC,
ADR3 => VCC,
O => LED_flash_cnt_6_F
);
LED_flash_cnt_6_G_X_LUT4 : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X31Y13"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => LED_flash_cnt(7),
O => LED_flash_cnt_6_G
);
LED_flash_cnt_8_F_X_LUT4 : X_LUT4
generic map(
INIT => X"FF00",
LOC => "SLICE_X31Y14"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => VCC,
ADR3 => LED_flash_cnt(8),
O => LED_flash_cnt_8_F
);
AN_0_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD33",
PATHPULSE => 638 ps
)
port map (
I => AN_0_4261,
O => AN_0_O
);
AN_1_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD44",
PATHPULSE => 638 ps
)
port map (
I => AN_1_4262,
O => AN_1_O
);
AN_2_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD51",
PATHPULSE => 638 ps
)
port map (
I => AN_2_4263,
O => AN_2_O
);
AN_3_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD45",
PATHPULSE => 638 ps
)
port map (
I => AN_3_4264,
O => AN_3_O
);
segment_a_i_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD48",
PATHPULSE => 638 ps
)
port map (
I => segment_a_i_OBUF_14289,
O => segment_a_i_O
);
segment_b_i_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD39",
PATHPULSE => 638 ps
)
port map (
I => segment_b_i_OBUF_14349,
O => segment_b_i_O
);
segment_c_i_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD53",
PATHPULSE => 638 ps
)
port map (
I => segment_c_i_OBUF_14330,
O => segment_c_i_O
);
segment_d_i_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD59",
PATHPULSE => 638 ps
)
port map (
I => segment_d_i_OBUF_14313,
O => segment_d_i_O
);
segment_e_i_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD56",
PATHPULSE => 638 ps
)
port map (
I => segment_e_i_OBUF_14306,
O => segment_e_i_O
);
segment_f_i_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD49",
PATHPULSE => 638 ps
)
port map (
I => segment_f_i_OBUF_14337,
O => segment_f_i_O
);
segment_g_i_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD52",
PATHPULSE => 638 ps
)
port map (
I => segment_g_i_OBUF_14282,
O => segment_g_i_O
);
do_rdy_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD79",
PATHPULSE => 638 ps
)
port map (
I => do_rdy_OBUF_14756,
O => do_rdy_O
);
swtch_led_0_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD69",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_pre_cy_0_Q,
O => swtch_led_0_O
);
swtch_led_1_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD58",
PATHPULSE => 638 ps
)
port map (
I => swtch_led_1_OBUF_4254,
O => swtch_led_1_O
);
swtch_led_2_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD64",
PATHPULSE => 638 ps
)
port map (
I => Madd_b_pre_lut(2),
O => swtch_led_2_O
);
swtch_led_3_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD65",
PATHPULSE => 638 ps
)
port map (
I => swtch_led_3_OBUF_4256,
O => swtch_led_3_O
);
swtch_led_4_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD68",
PATHPULSE => 638 ps
)
port map (
I => swtch_led_4_OBUF_4257,
O => swtch_led_4_O
);
swtch_led_5_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD71",
PATHPULSE => 638 ps
)
port map (
I => swtch_led_5_OBUF_4258,
O => swtch_led_5_O
);
swtch_led_6_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD70",
PATHPULSE => 638 ps
)
port map (
I => swtch_led_6_OBUF_4259,
O => swtch_led_6_O
);
swtch_led_7_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD96",
PATHPULSE => 638 ps
)
port map (
I => swtch_led_7_OBUF_4260,
O => swtch_led_7_O
);
NlwBlock_rc5_VCC : X_ONE
port map (
O => VCC
);
NlwBlock_rc5_GND : X_ZERO
port map (
O => GND
);
NlwBlockROC : X_ROC
generic map (ROC_WIDTH => 100 ns)
port map (O => GSR);
NlwBlockTOC : X_TOC
port map (O => GTS);
end Structure;
| lgpl-2.1 | 494ce869f49e27287d94946a84b44202 | 0.491322 | 2.794319 | false | false | false | false |
kdgwill/VHDL_Verilog_Encryptions_And_Ciphers | VHDL_RC5/Basys2Encryption/ARCHIVE/rc5.bak.vhd | 1 | 8,528 | --RC5 Encryption
--A = A + S[0];
--B = B + S[1];
--for i=1 to 12 do
----A = ((A XOR B) <<< B) + S[2*i];
----B = ((B XOR A) <<< A) + S[2*1+1];
--RC5 Decryption
--for i=12 to 1 do
----B = ((B - S[2×i +1]) >>> A) xor A;
----A = ((A - S[2×i]) >>> B) xor B;
--B = B - S[1];
--A = A - S[0];
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; -- we will use CONV_INTEGER
ENTITY rc5 IS
PORT (
-- Asynchronous reset and 25HzClock Signal
clr,clk_25 : IN STD_LOGIC;
--0 for encryption 1 for decryption
enc : IN STD_LOGIC;
-- 8-bit input
din_lower : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-- Input is Valid
di_vld : IN STD_LOGIC;
-- 7 Segment Display-bit output
segment_a_i : OUT STD_LOGIC;
segment_b_i : OUT STD_LOGIC;
segment_c_i : OUT STD_LOGIC;
segment_d_i : OUT STD_LOGIC;
segment_e_i : OUT STD_LOGIC;
segment_f_i : OUT STD_LOGIC;
segment_g_i : OUT STD_LOGIC;
-- 7 Segment Control
--Control Which of the four 7-Segment Display is active
AN : OUT STD_LOGIC_VECTOR(3 downto 0);
--Output is Ready
do_rdy : OUT STD_LOGIC;
--In Decryption Mode
dec_mode : OUT STD_LOGIC
);
END rc5;
ARCHITECTURE rtl OF rc5 IS
SIGNAL din : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL i_cnt : STD_LOGIC_VECTOR(3 DOWNTO 0); -- round counter
SIGNAL ab_xor : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_rot_left : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_rot_right : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_round : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); -- register A
SIGNAL ba_xor : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_rot_left : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_rot_right : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_round : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); -- register B
type rc5_rom_26 is array (0 to 25) of std_logic_vector(31 downto 0);
CONSTANT skey :rc5_rom_26:=rc5_rom_26'(
X"9BBBD8C8", X"1A37F7FB", X"46F8E8C5", X"460C6085",
X"70F83B8A", X"284B8303", X"513E1454", X"F621ED22",
X"3125065D", X"11A83A5D", X"D427686B", X"713AD82D",
X"4B792F99", X"2799A4DD", X"A7901C49", X"DEDE871A",
X"36C03196", X"A7EFC249", X"61A78BB8", X"3B0A1D2B",
X"4DBFCA76", X"AE162167", X"30D76B0A", X"43192304",
X"F6CC1431", X"65046380");
-- RC5 state machine has five states: idle, pre_round, round and ready
TYPE StateType IS(
ST_IDLE, -- In this state RC5 is ready for input
ST_PRE_ROUND, -- In this state RC5 pre-round op is performed
ST_ROUND_OP, -- In this state RC5 round op is performed. 12 rounds
ST_POST_ROUND, -- In this state RC5 post-round op is performed
ST_READY -- In this state RC5 has completed encryption
);
SIGNAL state : StateType;
--LED Control
SIGNAL hex_digit_i : STD_LOGIC_VECTOR(3 DOWNTO 0);
--Count to flash the LED
SIGNAL LED_flash_cnt : STD_LOGIC_VECTOR(9 DOWNTO 0);
BEGIN
din <= X"00000000000000" & din_lower;
WITH enc SELECT
a_round <= din(63 DOWNTO 32) + skey(0) WHEN '0',--A = A + S[0]
a_reg - skey(0) WHEN OTHERS; --A = A - S[0]
WITH enc SELECT
b_round <= din(31 DOWNTO 0) + skey(1) WHEN '0', --B = B + S[1]
b_reg - skey(1) WHEN OTHERS; --B = B - S[1]
WITH enc SELECT --A XOR B
ab_xor<=a_reg XOR b_reg WHEN '0',
a_rot_right XOR ba_xor WHEN OTHERS;
WITH enc SELECT --B XOR A
ba_xor <= b_reg XOR a WHEN '0',
b_rot_right XOR a_reg WHEN OTHERS;
WITH enc SELECT --B XOR A
a <= a_rot_left + skey(CONV_INTEGER(i_cnt & '0')) WHEN '0', --A + S[2*i]
a_reg - skey(CONV_INTEGER(i_cnt & '0')) WHEN OTHERS; -- A - S[2*i]
WITH enc SELECT --B XOR A
b <= b_rot_left + skey(CONV_INTEGER(i_cnt & '1')) WHEN '0', --B + S[2*i+1]
b_reg - skey(CONV_INTEGER(i_cnt & '1')) WHEN OTHERS; --B - S[2*i+1]
----------------------ENCRYPTION
ROT_A_LEFT : ENTITY work.rotLeft
PORT MAP(din=>ab_xor,amnt=>b_reg(4 DOWNTO 0),dout=>a_rot_left);--A <<< B
ROT_B_LEFT : ENTITY work.rotLeft
PORT MAP(din=>ba_xor,amnt=>a(4 DOWNTO 0),dout=>b_rot_left); --B <<< A
------------------------DECRYPTION
ROT_B_RIGHT : ENTITY work.rotRight
PORT MAP(din=>b,amnt=>a_reg(4 DOWNTO 0),dout=>b_rot_right); --B >>> A
ROT_A_RIGHT : ENTITY work.rotRight
PORT MAP(din=>a,amnt=>ba_xor(4 DOWNTO 0),dout=>a_rot_right); --A >>> B
A_register:
PROCESS(clr, clk_25,din) BEGIN
IF(clr='1') THEN
a_reg<=din(63 DOWNTO 32);
ELSIF(rising_edge(clk_25)) THEN
IF(state=ST_PRE_ROUND OR state=ST_POST_ROUND) THEN
a_reg<=a_round;
ELSIF(state=ST_ROUND_OP) THEN
if(enc = '0')then
a_reg<=a;
else
a_reg<=ab_xor;
end if;
END IF;
END IF;
END PROCESS;
B_register:
PROCESS(clr, clk_25,din) BEGIN
IF(clr='1') THEN
b_reg<=din(31 DOWNTO 0);
ELSIF(rising_edge(clk_25)) THEN
IF(state=ST_PRE_ROUND OR state=ST_POST_ROUND) THEN
b_reg<=b_round;
ELSIF(state=ST_ROUND_OP) THEN
if(enc = '0')then
b_reg<=b;
else
b_reg<=ba_xor;
end if;
END IF;
END IF;
END PROCESS;
State_Control:
PROCESS(clr, clk_25)
BEGIN
IF(clr='1') THEN
state<=ST_IDLE;
ELSIF(rising_edge(clk_25)) THEN
CASE state IS
WHEN ST_IDLE=> IF(di_vld='1') THEN
IF(enc = '0') THEN
state<=ST_PRE_ROUND;
ELSE
state<=ST_ROUND_OP;
END IF;
END IF;
WHEN ST_PRE_ROUND=> state<=ST_ROUND_OP;--Left because makes sense
WHEN ST_ROUND_OP=> IF(enc = '0') THEN
IF(i_cnt="1100") THEN
state<=ST_READY;
END IF;
ELSE
IF(i_cnt="0001") THEN
state<=ST_POST_ROUND;
END IF;
END IF;
WHEN ST_POST_ROUND=> state<=ST_READY; --Left because makes sense
WHEN ST_READY=> IF(di_vld='1') THEN
state<=ST_IDLE;
END IF;
END CASE;
END IF;
END PROCESS;
round_counter:
PROCESS(clk_25,clr, enc) BEGIN
IF(clr='1') THEN
i_cnt<="0001";
ELSIF(rising_edge(clk_25)) THEN
IF (state=ST_ROUND_OP) THEN
if(enc='0')then
IF(i_cnt="1100") THEN
i_cnt<="0001";
ELSE
i_cnt<=i_cnt+'1';
END IF;
else
IF(i_cnt="0001") THEN
i_cnt<="1100";
ELSE
i_cnt<=i_cnt-'1';
END IF;
END IF;
ELSIF(state=ST_PRE_ROUND)THEN
i_cnt<="0001";
ELSIF(state=ST_IDLE OR state = ST_READY)THEN
i_cnt<="1100";
END IF;
END IF;
END PROCESS;
dout<=a_reg & b_reg;
WITH state SELECT
do_rdy<='1' WHEN ST_READY,
'0' WHEN OTHERS;
dec_mode <= enc;
-------------------------------------------------
-------------------LED CONTROL-------------------
-------------------------------------------------
--hex to 7 Segment Display
hex2_7seg : ENTITY work.hex_7seg
--This is a new effective way to instantiate
--Rolls component and port map together
PORT MAP(
hex_digit => hex_digit_i,
segment_a => segment_a_i,
segment_b => segment_b_i,
segment_c => segment_c_i,
segment_d => segment_d_i,
segment_e => segment_e_i,
segment_f => segment_f_i,
segment_g => segment_g_i
);
--Flash the LED with the last 4 bytes of dout
PROCESS(clr,clk_25)
BEGIN
IF(clr='1')THEN
hex_digit_i <= (others => '0');
LED_flash_cnt <= (others => '0');
AN <= (others => '1');--All LED OFF
ELSIF(rising_edge(clk_25)) THEN
LED_flash_cnt <= LED_flash_cnt + '1';
CASE LED_flash_cnt(9 downto 8) IS
when "00" =>
--First 7-Seg-LED
hex_digit_i <= dout(15 downto 12);--LED output
AN <= "0111"; --Enables LED
when "01" =>
--Second 7-Seg-LED
hex_digit_i <= dout(11 downto 8);
AN <= "1011";
when "10" =>
--Third 7-Seg-LED
hex_digit_i <= dout(7 downto 4);
AN <= "1101";
when "11" =>
--Fourth 7-Seg-LED
hex_digit_i <= dout(3 downto 0);
AN <= "1110";
when others => null;
END CASE;
END IF;
END PROCESS;
END rtl; | lgpl-2.1 | f94b9fe0e79b6901d521de711115bdc8 | 0.543749 | 2.789921 | false | false | false | false |
nsauzede/cpu86 | top_rtl/uart_top_struct.vhd | 3 | 5,622 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY uart_top IS
PORT(
BR_clk : IN std_logic;
CTSn : IN std_logic := '1';
DCDn : IN std_logic := '1';
DSRn : IN std_logic := '1';
RIn : IN std_logic := '1';
abus : IN std_logic_vector (2 DOWNTO 0);
clk : IN std_logic;
csn : IN std_logic;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
rdn : IN std_logic;
resetn : IN std_logic;
sRX : IN std_logic;
wrn : IN std_logic;
B_CLK : OUT std_logic;
DTRn : OUT std_logic;
IRQ : OUT std_logic;
OUT1n : OUT std_logic;
OUT2n : OUT std_logic;
RTSn : OUT std_logic;
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
stx : OUT std_logic
);
-- Declarations
END uart_top ;
ARCHITECTURE struct OF uart_top IS
-- Internal signal declarations
SIGNAL BAUDCE : std_logic;
SIGNAL CS : std_logic;
SIGNAL RD : std_logic;
SIGNAL WR : std_logic;
SIGNAL rst : std_logic;
-- Component Declarations
COMPONENT uart_16750
PORT (
A : IN std_logic_vector (2 DOWNTO 0);
BAUDCE : IN std_logic;
CLK : IN std_logic;
CS : IN std_logic;
CTSN : IN std_logic;
DCDN : IN std_logic;
DIN : IN std_logic_vector (7 DOWNTO 0);
DSRN : IN std_logic;
RCLK : IN std_logic;
RD : IN std_logic;
RIN : IN std_logic;
RST : IN std_logic;
SIN : IN std_logic;
WR : IN std_logic;
BAUDOUTN : OUT std_logic;
DDIS : OUT std_logic;
DOUT : OUT std_logic_vector (7 DOWNTO 0);
DTRN : OUT std_logic;
INT : OUT std_logic;
OUT1N : OUT std_logic;
OUT2N : OUT std_logic;
RTSN : OUT std_logic;
SOUT : OUT std_logic
);
END COMPONENT;
BEGIN
rst <= not resetn; -- externally use active low reset
rd <= not rdn;
wr <= not wrn;
cs <= not csn;
BAUDCE <= '1';
-- Instance port mappings.
U_0 : uart_16750
PORT MAP (
CLK => clk,
RST => rst,
BAUDCE => BAUDCE,
CS => CS,
WR => WR,
RD => RD,
A => abus,
DIN => dbus_in,
DOUT => dbus_out,
DDIS => OPEN,
INT => IRQ,
OUT1N => OUT1n,
OUT2N => OUT2n,
RCLK => BR_clk,
BAUDOUTN => B_CLK,
RTSN => RTSn,
DTRN => DTRn,
CTSN => CTSn,
DSRN => DSRn,
DCDN => DCDn,
RIN => RIn,
SIN => sRX,
SOUT => stx
);
END struct;
| gpl-2.0 | 000c696ef368f30b6bcb9da70f93ebda | 0.396478 | 4.405956 | false | false | false | false |
CamelClarkson/MIPS | MIPS_Design/Src/Top_Level.vhd | 1 | 6,382 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/11/2016 12:58:50 PM
-- Design Name:
-- Module Name: Top_Level - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Top_Level is
Port (
iClk : in std_logic;
iRst : in std_logic;
iCommand32 : in std_logic_vector(31 downto 0);
Result : out std_logic_vector(31 downto 0)
);
end Top_Level;
architecture Structural of Top_Level is
component ALU is
Port ( A : in STD_LOGIC_VECTOR (31 downto 0); -- operands 1
B : in STD_LOGIC_VECTOR (31 downto 0); -- operands 2
P3 : in STD_LOGIC; -- Control signal 3
P2 : in STD_LOGIC; -- Conrtol signal 2
P1 : in STD_LOGIC; -- Conrtol signal 1
P0 : in STD_LOGIC; -- Conrtol signal 0
F : out STD_LOGIC_VECTOR (31 downto 0); -- ALU result
COUT : out STD_LOGIC; -- carry out
Overflow : out STD_LOGIC; -- overflow flag, which masks the overflow caused by slt
ZERO : out STD_LOGIC); -- zero flag
end component;
component Register_File is
Port (
i_Clk : in std_logic;
i_Rst : in std_logic;
i_regwrite : in std_logic;
i_rt : in std_logic_vector(4 downto 0);
i_rs : in std_logic_vector(4 downto 0);
i_rd : in std_logic_vector(4 downto 0);
i_rd_data : in std_logic_vector(31 downto 0);
o_rt_data : out std_logic_vector(31 downto 0);
o_rs_data : out std_logic_vector(31 downto 0)
);
end component;
component ALU_Ctrl_top is
Port (
Op5 : in STD_LOGIC; -- input of the ALU ctrl module
Op4 : in STD_LOGIC; -- input of the ALU ctrl module
Op3 : in STD_LOGIC; -- input of the ALU ctrl module
Op2 : in STD_LOGIC; -- input of the ALU ctrl module
Op1 : in STD_LOGIC; -- input of the ALU ctrl module
Op0 : in STD_LOGIC; -- input of the ALU ctrl module
RegDst : out STD_LOGIC; -- output the ALU ctrl module
ALUSrc : out STD_LOGIC; -- output the ALU ctrl module
MemtoReg : out STD_LOGIC; -- output the ALU ctrl module
RegWrite : out STD_LOGIC; -- output the ALU ctrl module
MemRead : out STD_LOGIC; -- output the ALU ctrl module
MemWrite : out STD_LOGIC; -- output the ALU ctrl module
Branch : out STD_LOGIC; -- output the ALU ctrl module
ALUOp1 : out STD_LOGIC; -- output the ALU ctrl module
ALUOp0 : out STD_LOGIC -- output the ALU ctrl module
);
end component;
component o_ALU_Control is
Port (
-- inputs
i_ALUOp : in STD_LOGIC_VECTOR(1 downto 0); -- From Main Control Unit
i_Inst_Funct : in STD_LOGIC_VECTOR(5 downto 0); -- From Instruction memory
-- outputs
o_ALU_Control : out STD_LOGIC_VECTOR(3 downto 0) -- Control lines to ALU
);
end component;
component mux_32bit is
port (
SEL: in STD_LOGIC;
A: in STD_LOGIC_VECTOR (31 downto 0);
B: in STD_LOGIC_VECTOR (31 downto 0);
OUTPUT: out STD_LOGIC_VECTOR (31 downto 0)
);
end component;
component extender_32bit is
port (
INPUT_16 :in std_logic_vector( 15 downto 0);
OUTPUT_32 :out std_logic_vector(31 downto 0)
);
end component;
component mux_5bit is
Port (
SEL: in STD_LOGIC;
A: in STD_LOGIC_VECTOR (4 downto 0);
B: in STD_LOGIC_VECTOR (4 downto 0);
OUTPUT: out STD_LOGIC_VECTOR (4 downto 0)
);
end component;
signal s_RegDst : std_logic;
signal s_rd : std_logic_vector(4 downto 0);
signal s_RegWrite : std_logic;
signal s_ALU_op : std_logic_vector(1 downto 0);
signal s_ALU_Control : std_logic_vector(3 downto 0);
signal s_rd_data : std_logic_vector(31 downto 0);
signal s_rt_data : std_logic_vector(31 downto 0);
signal s_rs_data : std_logic_vector(31 downto 0);
signal s_sign_ext : std_logic_vector(31 downto 0);
signal s_ALU_Src : std_logic;
signal s_B_ALU_data : std_logic_vector(31 downto 0);
begin
Inst_mux_32bit: mux_32bit
port map(
SEL => s_ALU_Src,
A => s_rt_data,
B => s_sign_ext,
OUTPUT => s_B_ALU_data
);
Inst_extender_32bit: extender_32bit
port map(
INPUT_16 => iCommand32(15 downto 0),
OUTPUT_32 => s_sign_ext
);
Inst_Register_File: Register_File
port map(
i_Clk => iClk,
i_Rst => iRst,
i_regwrite => s_RegWrite,
i_rt => iCommand32(20 downto 16),
i_rs => iCommand32(25 downto 21),
i_rd => s_rd,
i_rd_data => s_rd_data,
o_rt_data => s_rt_data,
o_rs_data => s_rs_data
);
Inst_ALU: ALU
port map( A => s_rs_data,
B => s_B_ALU_data,
P3 => s_ALU_Control(3),
P2 => s_ALU_Control(2),
P1 => s_ALU_Control(1),
P0 => s_ALU_Control(0),
F => Result,
COUT => open,
Overflow => open,
ZERO => open
);
Inst_mux_5bit: mux_5bit
port map(
SEL => s_RegDst,
A => iCommand32(20 downto 16),
B => iCommand32(15 downto 11),
OUTPUT => s_rd
);
Inst_ALU_Ctrl_top: ALU_Ctrl_top
port map(
Op5 => iCommand32(31),
Op4 => iCommand32(30),
Op3 => iCommand32(29),
Op2 => iCommand32(28),
Op1 => iCommand32(27),
Op0 => iCommand32(26),
RegDst => s_RegDst,
ALUSrc => s_ALU_Src,
MemtoReg => open,
RegWrite => s_RegWrite,
MemRead => open,
MemWrite => open,
Branch => open,
ALUOp1 => s_ALU_op(1),
ALUOp0 => s_ALU_op(0)
);
Inst_o_ALU_Control: o_ALU_Control
port map(
i_ALUOp => s_ALU_op,
i_Inst_Funct => iCommand32(5 downto 0),
-- outputs
o_ALU_Control => s_ALU_Control
);
end Structural;
| mit | 07291fb4c1c88d5cf4feaa57e8bcdd00 | 0.534002 | 3.421984 | false | false | false | false |
CamelClarkson/MIPS | Register_File/sources/Register.vhd | 2 | 10,074 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Register32X32 is
Port(
i_Clk : in std_logic;
i_Data : in std_logic_vector(31 downto 0);
i_Rst : in std_logic;
i_w_en : in std_logic_vector(31 downto 0);
i_rA_sel : in std_logic_vector(31 downto 0);
i_rB_sel : in std_logic_vector(31 downto 0);
o_Data_A : out std_logic_vector(31 downto 0);
o_Data_B : out std_logic_vector(31 downto 0)
);
end Register32X32;
architecture Behavioral of Register32X32 is
component Reg_Depth is
Port (
i_Clk : in std_logic;
i_Data : in std_logic_vector(31 downto 0);
i_Rst : in std_logic;
i_w_en : in std_logic;
i_rA_sel : in std_logic;
i_rB_sel : in std_logic;
o_Data_A : out std_logic_vector(31 downto 0);
o_Data_B : out std_logic_vector(31 downto 0)
);
end component;
begin
Inst_Reg_Depth31: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(31),
i_rA_sel => i_rA_sel(31),
i_rB_sel => i_rB_sel(31),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth30: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(30),
i_rA_sel => i_rA_sel(30),
i_rB_sel => i_rB_sel(30),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth29: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(29),
i_rA_sel => i_rA_sel(29),
i_rB_sel => i_rB_sel(29),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth28: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(28),
i_rA_sel => i_rA_sel(28),
i_rB_sel => i_rB_sel(28),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth27: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(27),
i_rA_sel => i_rA_sel(27),
i_rB_sel => i_rB_sel(27),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth26: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(26),
i_rA_sel => i_rA_sel(26),
i_rB_sel => i_rB_sel(26),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth25: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(25),
i_rA_sel => i_rA_sel(25),
i_rB_sel => i_rB_sel(25),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth24: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(24),
i_rA_sel => i_rA_sel(24),
i_rB_sel => i_rB_sel(24),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth23: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(23),
i_rA_sel => i_rA_sel(23),
i_rB_sel => i_rB_sel(23),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth22: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(22),
i_rA_sel => i_rA_sel(22),
i_rB_sel => i_rB_sel(22),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth21: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(21),
i_rA_sel => i_rA_sel(21),
i_rB_sel => i_rB_sel(21),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth20: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(20),
i_rA_sel => i_rA_sel(20),
i_rB_sel => i_rB_sel(20),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth19: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(19),
i_rA_sel => i_rA_sel(19),
i_rB_sel => i_rB_sel(19),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth18: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(18),
i_rA_sel => i_rA_sel(18),
i_rB_sel => i_rB_sel(18),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth17: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(17),
i_rA_sel => i_rA_sel(17),
i_rB_sel => i_rB_sel(17),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth16: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(16),
i_rA_sel => i_rA_sel(16),
i_rB_sel => i_rB_sel(16),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth15: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(15),
i_rA_sel => i_rA_sel(15),
i_rB_sel => i_rB_sel(15),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth14: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(14),
i_rA_sel => i_rA_sel(14),
i_rB_sel => i_rB_sel(14),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth13: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(13),
i_rA_sel => i_rA_sel(13),
i_rB_sel => i_rB_sel(13),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth12: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(12),
i_rA_sel => i_rA_sel(12),
i_rB_sel => i_rB_sel(12),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth11: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(11),
i_rA_sel => i_rA_sel(11),
i_rB_sel => i_rB_sel(11),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth10: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(10),
i_rA_sel => i_rA_sel(10),
i_rB_sel => i_rB_sel(10),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth9: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(9),
i_rA_sel => i_rA_sel(9),
i_rB_sel => i_rB_sel(9),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth8: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(8),
i_rA_sel => i_rA_sel(8),
i_rB_sel => i_rB_sel(8),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth7: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(7),
i_rA_sel => i_rA_sel(7),
i_rB_sel => i_rB_sel(7),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth6: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(6),
i_rA_sel => i_rA_sel(6),
i_rB_sel => i_rB_sel(6),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth5: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(5),
i_rA_sel => i_rA_sel(5),
i_rB_sel => i_rB_sel(5),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth4: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(4),
i_rA_sel => i_rA_sel(4),
i_rB_sel => i_rB_sel(4),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth3: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(3),
i_rA_sel => i_rA_sel(3),
i_rB_sel => i_rB_sel(3),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth2: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(2),
i_rA_sel => i_rA_sel(2),
i_rB_sel => i_rB_sel(2),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth1: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(1),
i_rA_sel => i_rA_sel(1),
i_rB_sel => i_rB_sel(1),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
Inst_Reg_Depth0: Reg_Depth
port map(
i_Clk => i_Clk,
i_Data => i_Data,
i_Rst => i_Rst,
i_w_en => i_w_en(0),
i_rA_sel => i_rA_sel(0),
i_rB_sel => i_rB_sel(0),
o_Data_A => o_Data_A,
o_Data_B => o_Data_B
);
end Behavioral;
| mit | ff760a825df7da73d93e0adf3b170eff | 0.421977 | 2.505347 | false | false | false | false |
kdgwill/VHDL_Verilog_Encryptions_And_Ciphers | VHDL_RC5/Encryption_Decryption/bak/rc5_dec.vhd | 1 | 8,077 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; -- we will use CONV_INTEGER
USE WORK.RC5_PKG.ALL;
ENTITY rc5_dec IS
PORT (
clr,clk : IN STD_LOGIC; -- Asynchronous reset and Clock Signal
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); -- 64-bit input
di_vld : IN STD_LOGIC; -- Valid Input
key_rdy : IN STD_LOGIC;
skey : IN rc5_rom_26;
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); -- 64-bit output
do_rdy : OUT STD_LOGIC --Output is Ready
);
END rc5_dec;
ARCHITECTURE rtl OF rc5_dec IS
SIGNAL i_cnt : STD_LOGIC_VECTOR(3 DOWNTO 0); -- round counter
SIGNAL ba_xor : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_rot : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_post : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); -- register B
SIGNAL ab_xor : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_rot : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_post : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); -- register A
---- define a type for round keys
--TYPE rom IS ARRAY (0 TO 25) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
--CONSTANT skey : rom:=rom'( X"9BBBD8C8", X"1A37F7FB", X"46F8E8C5", X"460C6085",
-- X"70F83B8A", X"284B8303", X"513E1454", X"F621ED22",
-- X"3125065D", X"11A83A5D", X"D427686B", X"713AD82D",
-- X"4B792F99", X"2799A4DD", X"A7901C49", X"DEDE871A",
-- X"36C03196", X"A7EFC249", X"61A78BB8", X"3B0A1D2B",
-- X"4DBFCA76", X"AE162167", X"30D76B0A", X"43192304",
-- X"F6CC1431",X"65046380");
----RC5 state machine has five states
--TYPE StateType IS(ST_IDLE, -- In this state RC5 is ready for input
-- ST_ROUND_OP, -- In this state RC5 round op is performed.
-- -- The state machine remains in this state
-- -- for twelve clock cycles.
-- ST_POST_ROUND, -- In this state RC5 post-round op is performed
-- ST_READY -- In this state RC5 has completed encryption
-- );
-- RC5 state machine has five states: idle, round, post_round and ready
SIGNAL state : dec_StateType;
BEGIN
--B = ((B - S[2×i +1]) >>> A) xor A;
b<=b_reg - skey(CONV_INTEGER(i_cnt & '1')); -- S[2*i+1]
WITH a_reg(4 DOWNTO 0) SELECT
b_rot<= b(0) & b(31 DOWNTO 01) WHEN "00001", --01
b(01 DOWNTO 0) & b(31 DOWNTO 02) WHEN "00010", --02
b(02 DOWNTO 0) & b(31 DOWNTO 03) WHEN "00011", --03
b(03 DOWNTO 0) & b(31 DOWNTO 04) WHEN "00100", --04
b(04 DOWNTO 0) & b(31 DOWNTO 05) WHEN "00101", --05
b(05 DOWNTO 0) & b(31 DOWNTO 06) WHEN "00110", --06
b(06 DOWNTO 0) & b(31 DOWNTO 07) WHEN "00111", --07
b(07 DOWNTO 0) & b(31 DOWNTO 08) WHEN "01000", --08
b(08 DOWNTO 0) & b(31 DOWNTO 09) WHEN "01001", --09
b(09 DOWNTO 0) & b(31 DOWNTO 10) WHEN "01010", --10
b(10 DOWNTO 0) & b(31 DOWNTO 11) WHEN "01011", --11
b(11 DOWNTO 0) & b(31 DOWNTO 12) WHEN "01100", --12
b(12 DOWNTO 0) & b(31 DOWNTO 13) WHEN "01101", --13
b(13 DOWNTO 0) & b(31 DOWNTO 14) WHEN "01110", --14
b(14 DOWNTO 0) & b(31 DOWNTO 15) WHEN "01111", --15
b(15 DOWNTO 0) & b(31 DOWNTO 16) WHEN "10000", --16
b(16 DOWNTO 0) & b(31 DOWNTO 17) WHEN "10001", --17
b(17 DOWNTO 0) & b(31 DOWNTO 18) WHEN "10010", --18
b(18 DOWNTO 0) & b(31 DOWNTO 19) WHEN "10011", --19
b(19 DOWNTO 0) & b(31 DOWNTO 20) WHEN "10100", --20
b(20 DOWNTO 0) & b(31 DOWNTO 21) WHEN "10101", --21
b(21 DOWNTO 0) & b(31 DOWNTO 22) WHEN "10110", --22
b(22 DOWNTO 0) & b(31 DOWNTO 23) WHEN "10111", --23
b(23 DOWNTO 0) & b(31 DOWNTO 24) WHEN "11000", --24
b(24 DOWNTO 0) & b(31 DOWNTO 25) WHEN "11001", --25
b(25 DOWNTO 0) & b(31 DOWNTO 26) WHEN "11010", --26
b(26 DOWNTO 0) & b(31 DOWNTO 27) WHEN "11011", --27
b(27 DOWNTO 0) & b(31 DOWNTO 28) WHEN "11100", --28
b(28 DOWNTO 0) & b(31 DOWNTO 29) WHEN "11101", --29
b(29 DOWNTO 0) & b(31 DOWNTO 30) WHEN "11110", --30
b(30 DOWNTO 0) & b(31) WHEN "11111", --31
b WHEN OTHERS; --32
ba_xor <= b_rot XOR a_reg;
b_post<=b_reg - skey(1); --B = B - S[1]
--A = ((A - S[2×i]) >>> B) xor B;
a<=a_reg - skey(CONV_INTEGER(i_cnt & '0')); -- S[2*i]
WITH ba_xor(4 DOWNTO 0) SELECT
a_rot<= a(0) & a(31 DOWNTO 01) WHEN "00001", --01
a(01 DOWNTO 0) & a(31 DOWNTO 02) WHEN "00010", --02
a(02 DOWNTO 0) & a(31 DOWNTO 03) WHEN "00011", --03
a(03 DOWNTO 0) & a(31 DOWNTO 04) WHEN "00100", --04
a(04 DOWNTO 0) & a(31 DOWNTO 05) WHEN "00101", --05
a(05 DOWNTO 0) & a(31 DOWNTO 06) WHEN "00110", --06
a(06 DOWNTO 0) & a(31 DOWNTO 07) WHEN "00111", --07
a(07 DOWNTO 0) & a(31 DOWNTO 08) WHEN "01000", --08
a(08 DOWNTO 0) & a(31 DOWNTO 09) WHEN "01001", --09
a(09 DOWNTO 0) & a(31 DOWNTO 10) WHEN "01010", --10
a(10 DOWNTO 0) & a(31 DOWNTO 11) WHEN "01011", --11
a(11 DOWNTO 0) & a(31 DOWNTO 12) WHEN "01100", --12
a(12 DOWNTO 0) & a(31 DOWNTO 13) WHEN "01101", --13
a(13 DOWNTO 0) & a(31 DOWNTO 14) WHEN "01110", --14
a(14 DOWNTO 0) & a(31 DOWNTO 15) WHEN "01111", --15
a(15 DOWNTO 0) & a(31 DOWNTO 16) WHEN "10000", --16
a(16 DOWNTO 0) & a(31 DOWNTO 17) WHEN "10001", --17
a(17 DOWNTO 0) & a(31 DOWNTO 18) WHEN "10010", --18
a(18 DOWNTO 0) & a(31 DOWNTO 19) WHEN "10011", --19
a(19 DOWNTO 0) & a(31 DOWNTO 20) WHEN "10100", --20
a(20 DOWNTO 0) & a(31 DOWNTO 21) WHEN "10101", --21
a(21 DOWNTO 0) & a(31 DOWNTO 22) WHEN "10110", --22
a(22 DOWNTO 0) & a(31 DOWNTO 23) WHEN "10111", --23
a(23 DOWNTO 0) & a(31 DOWNTO 24) WHEN "11000", --24
a(24 DOWNTO 0) & a(31 DOWNTO 25) WHEN "11001", --25
a(25 DOWNTO 0) & a(31 DOWNTO 26) WHEN "11010", --26
a(26 DOWNTO 0) & a(31 DOWNTO 27) WHEN "11011", --27
a(27 DOWNTO 0) & a(31 DOWNTO 28) WHEN "11100", --28
a(28 DOWNTO 0) & a(31 DOWNTO 29) WHEN "11101", --29
a(29 DOWNTO 0) & a(31 DOWNTO 30) WHEN "11110", --30
a(30 DOWNTO 0) & a(31) WHEN "11111", --31
a WHEN OTHERS; --32
ab_xor <= a_rot XOR ba_xor;
a_post<=a_reg - skey(0); --A = A - S[0]
A_register:
PROCESS(clr, clk) BEGIN
IF(clr='0') THEN
a_reg<=din(63 DOWNTO 32);
ELSIF(rising_edge(clk)) THEN --clk'EVENT AND clk='1' can introduce error
IF(state=ST_POST_ROUND) THEN
a_reg<=a_post;
ELSIF(state=ST_ROUND_OP) THEN
a_reg<=ab_xor;
END IF;
END IF;
END PROCESS;
B_register:
PROCESS(clr, clk) BEGIN
IF(clr='0') THEN
b_reg<=din(31 DOWNTO 0);
ELSIF(rising_edge(clk)) THEN
IF(state=ST_POST_ROUND) THEN
b_reg<=b_post;
ELSIF(state=ST_ROUND_OP) THEN
b_reg<=ba_xor;
END IF;
END IF;
END PROCESS;
State_Control:
PROCESS(clr, clk)
BEGIN
IF(clr='0') THEN
state<=ST_IDLE;
ELSIF(clk'EVENT AND clk='1') THEN
CASE state IS
WHEN ST_IDLE=> IF(di_vld='1' and key_rdy='1') THEN
state<=ST_ROUND_OP;
END IF;
WHEN ST_ROUND_OP=> IF(i_cnt="0001") THEN
state<=ST_POST_ROUND;
END IF;
WHEN ST_POST_ROUND=> state<=ST_READY;
WHEN ST_READY=> IF(di_vld='1' and key_rdy='1') THEN
state<=ST_ROUND_OP;--can assume new keys and skip idle state
--state<=ST_IDLE; --If Input Changes then restart
END IF;
END CASE;
END IF;
END PROCESS;
round_counter:
PROCESS(clr, clk) BEGIN
IF(clr='0') THEN
i_cnt<="1100";
ELSIF(rising_edge(clk) AND state=ST_ROUND_OP) THEN
IF(i_cnt="0001") THEN
i_cnt<="1100";
ELSE
i_cnt<=i_cnt-'1';
END IF;
END IF;
END PROCESS;
dout<=a_reg & b_reg;
WITH state SELECT
do_rdy<='1' WHEN ST_READY,
'0' WHEN OTHERS;
END rtl; | lgpl-2.1 | 4cc999ceca2b8fd297a19a1c6ad18097 | 0.556395 | 2.84903 | false | false | false | false |
VenturaSolutionsInc/VHDL | igmp/igmp_processor.vhd | 1 | 4,879 | -------------------------------------------------------------------------------
-- Title : IGMP processor
-- Project :
-------------------------------------------------------------------------------
--! @file : igmp_processor.vhd
-- Author : Colin W. Shea
-- Company
-- Last update : 2010-06-01
-- Platform : Virtex 4/5/6
-------------------------------------------------------------------------------
--
--* @brief parsing incoming data stream for igmp requests
--
--! @details: This module parses the incoming stream of igmp data and signals
--the igmp controller for the packet type ie which response needs to be generated.
--!
--!
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity igmp_processor is
generic (
gen_dataWidth : integer := 8
);
port (
dataClk : in std_logic;
reset : in std_logic;
in_destIP : in std_logic_vector(31 downto 0);
igmp_data : in std_logic_vector(gen_dataWidth - 1 downto 0);
igmp_vld : in std_logic;
igmp_sof : in std_logic;
igmp_eof : in std_logic;
respond : out std_logic;
rsptime : out std_logic_vector(gen_dataWidth - 1 downto 0)
);
end igmp_processor;
architecture rtl of igmp_processor is
signal igmp_data_r : std_logic_vector(gen_dataWidth - 1 downto 0) := (others => '0');
signal igmp_vld_r : std_logic := '0';
signal igmp_sof_r : std_logic := '0';
-- signal igmp_eof_r : std_logic;
signal igmp_data_r2 : std_logic_vector(gen_dataWidth - 1 downto 0) := (others => '0');
signal igmp_vld_r2 : std_logic := '0';
signal igmp_sof_r2 : std_logic := '0';
-- signal igmp_eof_r2 : std_logic;
signal destIP : std_logic_vector(31 downto 0) := (others => '0');
signal igmpState : std_logic_vector(2 downto 0) := (others => '0');
signal responseTime : std_logic_vector(7 downto 0) := (others => '0');
signal byteCount : integer range 0 to 2 := 0;
begin -- trl
register_in_coming_data : process(dataClk, reset)
begin
if(rising_edge(dataClk))then
if(reset = '1')then
igmp_data_r <= (others => '0');
igmp_vld_r <= '0';
igmp_sof_r <= '0';
-- igmp_eof_r <= '0';
igmp_data_r2 <= (others => '0');
igmp_vld_r2 <= '0';
igmp_sof_r2 <= '0';
-- igmp_eof_r2 <= '0';
else
igmp_data_r <= igmp_data;
igmp_vld_r <= igmp_vld;
igmp_sof_r <= igmp_sof;
-- igmp_eof_r <= igmp_eof;
igmp_data_r2 <= igmp_data_r;
igmp_vld_r2 <= igmp_vld_r;
igmp_sof_r2 <= igmp_sof_r;
-- igmp_eof_r2 <= igmp_eof_r;
end if;
end if;
end process;
process_imcoming_stream : process(dataClk, reset)
begin
if(rising_edge(dataClk))then
if(reset = '1')then
igmpState <= (others => '0');
byteCount <= 0;
respond <= '0';
rsptime <= (others => '0');
responseTime <= (others => '0');
destIP <= (others => '0');
else
if(igmp_vld_r2 = '1')then
case igmpState is
when "000" =>
respond <= '0';
if(igmp_sof_r2 = '1' and igmp_data_r2 = X"11")then
igmpState <= "001";
else
igmpState <= "000";
end if;
when "001" =>
responseTime <= igmp_data_r2;
igmpState <= "010";
byteCount <= 2;
when "010" =>
if(byteCount = 1)then
igmpState <= "011";
else
igmpState <= "010";
byteCount <= byteCount -1;
end if;
when "011" =>
destIP(31 downto 24) <= igmp_data_r2;
igmpState <= "100";
when "100" =>
destIP(23 downto 16) <= igmp_data_r2;
igmpState <= "101";
when "101" =>
destIP(15 downto 8) <= igmp_data_r2;
igmpState <= "110";
when "110" =>
destIP(7 downto 0) <= igmp_data_r2;
igmpState <= "111";
when "111" =>
if((destIP = in_destIP) or (destIP = X"00000000"))then
respond <= '1';
rsptime <= responseTime;
else
respond <= '0';
end if;
igmpState <= "000";
when others =>
igmpState <= "000";
end case;
else
respond <= '0';
end if;
end if;
end if;
end process;
end rtl;
| gpl-2.0 | d0d16316a89cbdf15e1bc5c589a5f9d3 | 0.440459 | 3.866086 | false | false | false | false |
hacklabmikkeli/knobs-galore | voice_allocator.vhdl | 2 | 7,565 | --
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
entity voice_allocator is
port (EN: in std_logic
;CLK: in std_logic
;TRANSFORM: in voice_transform_t
;KEY_CODE: in keys_signal
;KEY_EVENT: in key_event_t
;FREQ: out time_signal
;GATE: out std_logic
);
end entity;
architecture voice_allocator_impl of voice_allocator is
function key_to_freq_int(key: keys_signal)
return integer is
begin
case key is
when "000000" => return 87;
when "000001" => return 92;
when "000010" => return 97;
when "000011" => return 103;
when "000100" => return 109;
when "000101" => return 116;
when "000110" => return 123;
when "000111" => return 130;
when "001000" => return 138;
when "001001" => return 146;
when "001010" => return 155;
when "001011" => return 164;
when "001100" => return 174;
when "001101" => return 184;
when "001110" => return 195;
when "001111" => return 206;
when "010000" => return 219;
when "010001" => return 232;
when "010010" => return 246;
when "010011" => return 260;
when "010100" => return 276;
when "010101" => return 292;
when "010110" => return 310;
when "010111" => return 328;
when "011000" => return 348;
when "011001" => return 368;
when "011010" => return 390;
when "011011" => return 413;
when "011100" => return 438;
when "011101" => return 464;
when "011110" => return 492;
when "011111" => return 521;
when "100000" => return 552;
when "100001" => return 585;
when "100010" => return 620;
when "100011" => return 656;
when "100100" => return 696;
when others => return 0;
end case;
end function;
function key_to_freq(key: keys_signal)
return time_signal is
begin
return to_unsigned(key_to_freq_int(key), time_bits);
end function;
function sub_key_to_freq(key: keys_signal)
return time_signal is
begin
return to_unsigned(key_to_freq_int(key)/2, time_bits);
end function;
type key_code_vector is array(num_voices - 1 downto 0) of keys_signal;
subtype gate_vector is std_logic_vector(num_voices - 1 downto 0);
signal freq_buf: time_signal := (others => '0');
signal gate_buf: std_logic := '0';
signal key_codes: key_code_vector := (others => (others => '0'));
signal next_voice: unsigned(voices_bits - 1 downto 0) := (others=>'0');
signal current_voice: unsigned(voices_bits - 1 downto 0) := (others=>'0');
signal gates: gate_vector := (others => '0');
begin
process(CLK)
variable voice_aux: unsigned(voices_bits - 1 downto 0)
:= (others => '0');
variable freq_aux: time_signal := (others => '0');
begin
if EN = '1' and rising_edge(CLK) then
case TRANSFORM is
when voice_transform_oct =>
case KEY_EVENT is
when key_event_make =>
key_codes(to_integer(next_voice)) <= KEY_CODE;
gates(to_integer(next_voice)) <= '1';
voice_aux := next_voice + 1;
next_voice <= '0' & voice_aux(voices_bits - 2 downto 0);
when key_event_break =>
for i in key_codes'low to key_codes'high loop
if key_codes(i) = KEY_CODE then
gates(i) <= '0';
end if;
end loop;
when others =>
null;
end case;
if current_voice(voices_bits - 1) = '0' then
freq_buf <= key_to_freq(key_codes(to_integer(current_voice)));
gate_buf <= gates(to_integer(current_voice));
else
voice_aux := '0' & current_voice(voices_bits - 2 downto 0);
freq_aux := key_to_freq(key_codes(to_integer(voice_aux)));
freq_buf <= freq_aux(time_bits - 2 downto 0) & '0';
gate_buf <= gates(to_integer(voice_aux));
end if;
current_voice <= current_voice + 1;
when voice_transform_sub =>
case KEY_EVENT is
when key_event_make =>
key_codes(to_integer(next_voice)) <= KEY_CODE;
gates(to_integer(next_voice)) <= '1';
next_voice <= next_voice + 1;
when key_event_break =>
for i in key_codes'low to key_codes'high loop
if key_codes(i) = KEY_CODE then
gates(i) <= '0';
end if;
end loop;
when others =>
null;
end case;
freq_buf <= sub_key_to_freq(key_codes(to_integer(current_voice)));
gate_buf <= gates(to_integer(current_voice));
current_voice <= current_voice + 1;
when others =>
case KEY_EVENT is
when key_event_make =>
key_codes(to_integer(next_voice)) <= KEY_CODE;
gates(to_integer(next_voice)) <= '1';
next_voice <= next_voice + 1;
when key_event_break =>
for i in key_codes'low to key_codes'high loop
if key_codes(i) = KEY_CODE then
gates(i) <= '0';
end if;
end loop;
when others =>
null;
end case;
freq_buf <= key_to_freq(key_codes(to_integer(current_voice)));
gate_buf <= gates(to_integer(current_voice));
current_voice <= current_voice + 1;
end case;
end if;
end process;
FREQ <= freq_buf;
GATE <= gate_buf;
end architecture;
| gpl-3.0 | 078889b17ab69965546a2e599d73c024 | 0.474554 | 4.423977 | false | false | false | false |
nsauzede/cpu86 | papilio2_drigmorn1/ipcore_dir/blk_mem_40K/example_design/blk_mem_40K_prod.vhd | 1 | 10,369 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_40K_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : blk_mem_40K.mif
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : READ_FIRST
-- C_WRITE_WIDTH_A : 8
-- C_READ_WIDTH_A : 8
-- C_WRITE_DEPTH_A : 65536
-- C_READ_DEPTH_A : 65536
-- C_ADDRA_WIDTH : 16
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 8
-- C_READ_WIDTH_B : 8
-- C_WRITE_DEPTH_B : 65536
-- C_READ_DEPTH_B : 65536
-- C_ADDRB_WIDTH : 16
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY blk_mem_40K_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END blk_mem_40K_prod;
ARCHITECTURE xilinx OF blk_mem_40K_prod IS
COMPONENT blk_mem_40K_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : blk_mem_40K_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| gpl-2.0 | 8ea9a334d4b48ed64ff93afb47f46d69 | 0.480471 | 3.795388 | false | false | false | false |
kdgwill/VHDL_Verilog_Encryptions_And_Ciphers | VHDL_RC5/Encryption_Decryption/bak/rc5_key.vhd | 1 | 6,925 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; -- we will use CONV_INTEGER
USE WORK.RC5_PKG.ALL;
entity rc5_key is
port( clr,clk : in std_logic; -- Asynchronous reset and Clock Signal
key : in std_logic_vector(127 downto 0);
key_vld : in std_logic;
skey : out rc5_rom_26;
key_rdy : out std_logic);
end rc5_key;
architecture key_exp of rc5_key is
signal i_cnt : std_logic_vector(04 downto 00); -- s_array counter
signal j_cnt : std_logic_vector(04 downto 00); -- l_array counter
signal r_cnt : std_logic_vector(06 downto 00); -- overall counterer; counts to 78
signal a : std_logic_vector(31 downto 00);
signal a_circ : std_logic_vector(31 downto 00);
signal a_reg : std_logic_vector(31 downto 00); -- register A
signal b : std_logic_vector(31 downto 00);
signal b_circ : std_logic_vector(31 downto 00);
signal b_reg : std_logic_vector(31 downto 00); -- register B
signal temp : std_logic_vector(31 downto 00);
--Key Expansion state machine has five states: idle, key in, expansion and ready
signal state : rc5_key_StateType;
signal l : rc5_rom_4;
signal s : rc5_rom_26;
begin
-- it is not a data-dependent rotation!
--A = S[i] = (S[i] + A + B) <<< 3;
a <= s(conv_integer(i_cnt)) + a_reg + b_reg; --S + A + B
a_circ <= a(28 downto 0) & a(31 downto 29); --rot by 3
-- this is a data-dependent rotation!
--B = L[j] = (L[j] + A + B) <<< (A + B);
b <= l(conv_integer(j_cnt)) + a_circ + b_reg; --L + A + B
-- rot by A + B
temp <= a_circ + b_reg;
with temp(4 downto 0) select
b_circ <= b(30 downto 0) & b(31) when "00001", --01
b(29 downto 0) & b(31 downto 30) when "00010", --02
b(28 downto 0) & b(31 downto 29) when "00011", --03
b(27 downto 0) & b(31 downto 28) when "00100", --04
b(26 downto 0) & b(31 downto 27) when "00101", --05
b(25 downto 0) & b(31 downto 26) when "00110", --06
b(24 downto 0) & b(31 downto 25) when "00111", --07
b(23 downto 0) & b(31 downto 24) when "01000", --08
b(22 downto 0) & b(31 downto 23) when "01001", --09
b(21 downto 0) & b(31 downto 22) when "01010", --10
b(20 downto 0) & b(31 downto 21) when "01011", --11
b(19 downto 0) & b(31 downto 20) when "01100", --12
b(18 downto 0) & b(31 downto 19) when "01101", --13
b(17 downto 0) & b(31 downto 18) when "01110", --14
b(16 downto 0) & b(31 downto 17) when "01111", --15
b(15 downto 0) & b(31 downto 16) when "10000", --16
b(14 downto 0) & b(31 downto 15) when "10001", --17
b(13 downto 0) & b(31 downto 14) when "10010", --18
b(12 downto 0) & b(31 downto 13) when "10011", --19
b(11 downto 0) & b(31 downto 12) when "10100", --20
b(10 downto 0) & b(31 downto 11) when "10101", --21
b(09 downto 0) & b(31 downto 10) when "10110", --22
b(08 downto 0) & b(31 downto 09) when "10111", --23
b(07 downto 0) & b(31 downto 08) when "11000", --24
b(06 downto 0) & b(31 downto 07) when "11001", --25
b(05 downto 0) & b(31 downto 06) when "11010", --26
b(04 downto 0) & b(31 downto 05) when "11011", --27
b(03 downto 0) & b(31 downto 04) when "11100", --28
b(02 downto 0) & b(31 downto 03) when "11101", --29
b(01 downto 0) & b(31 downto 02) when "11110", --30
b(0) & b(31 downto 01) when "11111", --31
b when others;
state_block:
process(clr, clk)
begin
if (clr = '0') then
state <= st_idle;
elsif (rising_edge(clk)) then
case state is
when st_idle =>
if(key_vld = '1') then
state <= st_key_in;
end if;
when st_key_in =>
state <= st_key_exp;
when st_key_exp =>
if (r_cnt = "1001101") then
state <= st_ready;
end if;
when st_ready =>
IF( key_vld='1') THEN -- /= is not equals to
state <= st_key_in; --in event of new key start at key_in
--state otherwise would be a timing issue
--state<=ST_IDLE; --If Input Changes then restart
END IF;
end case;
end if;
end process;
a_reg_block:
process(clr, clk)
begin
if(clr = '0') then
a_reg <= (others => '0');
elsif (rising_edge(clk)) then
if (state = st_key_exp) then
a_reg <= a_circ;
end if;
end if;
end process;
b_reg_block:
process(clr, clk)
begin
if(clr = '0') then
b_reg <= (others => '0');
elsif (rising_edge(clk)) then
if (state = st_key_exp) then
b_reg <= b_circ;
end if;
end if;
end process;
s_array_counter_block:
process(clr, clk)
begin
if(clr='0') then i_cnt<=(others=>'0');
elsif(rising_edge(clk)) then
if(state=ST_KEY_EXP) then
if(i_cnt="11001") then i_cnt <= (others=>'0');
else i_cnt <= i_cnt + 1;
end if;
end if;
end if;
end process;
l_array_counter_block:
process(clr, clk)
begin
if(clr='0') then j_cnt<=(others=>'0');
elsif(rising_edge(clk)) then
if(j_cnt="00011") then j_cnt<=(others=>'0');
else j_cnt <= j_cnt + 1;
end if;
end if;
end process;
overall_counter_block:
process(clr, clk)
begin
if (clr = '0') then
r_cnt <= "0000000";
elsif (rising_edge(clk)) then
if (state = st_key_exp) then
r_cnt <= r_cnt + 1;
end if;
end if;
end process;
--S[0] = 0xB7E15163 (Pw)
--for i=1 to 25 do S[i] = S[i-1]+ 0x9E3779B9 (Qw)
--array s
process(clr, clk)
begin
if (clr = '0') then
s(0) <= X"b7e15163"; s(1) <= X"5618cb1c";s(2) <= X"f45044d5";
s(3) <= X"9287be8e";s(4) <= X"30bf3847";s(5) <= X"cef6b200";
s(6) <= X"6d2e2bb9";s(7) <= X"0b65a572";s(8) <= X"a99d1f2b";
s(9) <= X"47d498e4";s(10) <= X"e60c129d";s(11) <= X"84438c56";
s(12) <= X"227b060f";s(13) <= X"c0b27fc8";s(14) <= X"5ee9f981";
s(15) <= X"fd21733a";s(16) <= X"9b58ecf3";s(17) <= X"399066ac";
s(18) <= X"d7c7e065";s(19) <= X"75ff5a1e";s(20) <= X"1436d3d7";
s(21) <= X"b26e4d90";s(22) <= X"50a5c749";s(23) <= X"eedd4102";
s(24) <= X"8d14babb";s(25) <= X"2b4c3474";
elsif (rising_edge(clk)) then
if (state = st_key_exp) then
s(conv_integer(i_cnt)) <= a_circ;--i = (i + 1) mod 26;
end if;
end if;
end process;
--l array
process(clr, clk)
begin
if(clr = '0') then
l(0) <= (others=>'0');
l(1) <= (others=>'0');
l(2) <= (others=>'0');
l(3) <= (others=>'0');
elsif (rising_edge(clk)) then
if(state = st_key_in) then
l(0) <= key(31 downto 0);
l(1) <= key(63 downto 32);
l(2) <= key(95 downto 64);
l(3) <= key(127 downto 96);
elsif(state = st_key_exp) then
l(conv_integer(j_cnt)) <= b_circ; --j = (j + 1) mod 4;
end if;
end if;
end process;
skey <= s;
with state select
key_rdy <= '1' when st_ready,
'0' when others;
end key_exp; | lgpl-2.1 | 2d1def77346fa3ac097588dc5a5ebb49 | 0.54787 | 2.566716 | false | false | false | false |
nsauzede/cpu86 | papilio1/bbfifo_16x8.vhd | 2 | 8,392 | -- 'Bucket Brigade' FIFO
-- 16 deep
-- 8-bit data
--
-- Version : 1.10
-- Version Date : 3rd December 2003
-- Reason : '--translate' directives changed to '--synthesis translate' directives
--
-- Version : 1.00
-- Version Date : 14th October 2002
--
-- Start of design entry : 14th October 2002
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- [email protected]
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
-- third parties. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
------------------------------------------------------------------------------------
--
-- Main Entity for BBFIFO_16x8
--
entity bbfifo_16x8 is
Port ( data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
reset : in std_logic;
write : in std_logic;
read : in std_logic;
full : out std_logic;
half_full : out std_logic;
data_present : out std_logic;
clk : in std_logic);
end bbfifo_16x8;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for BBFIFO_16x8
--
architecture low_level_definition of bbfifo_16x8 is
--
------------------------------------------------------------------------------------
--
------------------------------------------------------------------------------------
--
-- Signals used in BBFIFO_16x8
--
------------------------------------------------------------------------------------
--
signal pointer : std_logic_vector(3 downto 0);
signal next_count : std_logic_vector(3 downto 0);
signal half_count : std_logic_vector(3 downto 0);
signal count_carry : std_logic_vector(2 downto 0);
signal pointer_zero : std_logic;
signal pointer_full : std_logic;
signal decode_data_present : std_logic;
signal data_present_int : std_logic;
signal valid_write : std_logic;
--
--
------------------------------------------------------------------------------------
--
-- Attributes to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation--
--
------------------------------------------------------------------------------------
--
attribute INIT : string;
attribute INIT of zero_lut : label is "0001";
attribute INIT of full_lut : label is "8000";
attribute INIT of dp_lut : label is "BFA0";
attribute INIT of valid_lut : label is "C4";
--
------------------------------------------------------------------------------------
--
-- Start of BBFIFO_16x8 circuit description
--
------------------------------------------------------------------------------------
--
begin
-- SRL16E data storage
data_width_loop: for i in 0 to 7 generate
--
attribute INIT : string;
attribute INIT of data_srl : label is "0000";
--
begin
data_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => data_in(i),
CE => valid_write,
CLK => clk,
A0 => pointer(0),
A1 => pointer(1),
A2 => pointer(2),
A3 => pointer(3),
Q => data_out(i) );
end generate data_width_loop;
-- 4-bit counter to act as data pointer
-- Counter is clock enabled by 'data_present'
-- Counter will be reset when 'reset' is active
-- Counter will increment when 'valid_write' is active
count_width_loop: for i in 0 to 3 generate
--
attribute INIT : string;
attribute INIT of count_lut : label is "6606";
--
begin
register_bit: FDRE
port map ( D => next_count(i),
Q => pointer(i),
CE => data_present_int,
R => reset,
C => clk);
count_lut: LUT4
--synthesis translate_off
generic map (INIT => X"6606")
--synthesis translate_on
port map( I0 => pointer(i),
I1 => read,
I2 => pointer_zero,
I3 => write,
O => half_count(i));
lsb_count: if i=0 generate
begin
count_muxcy: MUXCY
port map( DI => pointer(i),
CI => valid_write,
S => half_count(i),
O => count_carry(i));
count_xor: XORCY
port map( LI => half_count(i),
CI => valid_write,
O => next_count(i));
end generate lsb_count;
mid_count: if i>0 and i<3 generate
begin
count_muxcy: MUXCY
port map( DI => pointer(i),
CI => count_carry(i-1),
S => half_count(i),
O => count_carry(i));
count_xor: XORCY
port map( LI => half_count(i),
CI => count_carry(i-1),
O => next_count(i));
end generate mid_count;
upper_count: if i=3 generate
begin
count_xor: XORCY
port map( LI => half_count(i),
CI => count_carry(i-1),
O => next_count(i));
end generate upper_count;
end generate count_width_loop;
-- Detect when pointer is zero and maximum
zero_lut: LUT4
--synthesis translate_off
generic map (INIT => X"0001")
--synthesis translate_on
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
O => pointer_zero );
full_lut: LUT4
--synthesis translate_off
generic map (INIT => X"8000")
--synthesis translate_on
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
O => pointer_full );
-- Data Present status
dp_lut: LUT4
--synthesis translate_off
generic map (INIT => X"BFA0")
--synthesis translate_on
port map( I0 => write,
I1 => read,
I2 => pointer_zero,
I3 => data_present_int,
O => decode_data_present );
dp_flop: FDR
port map ( D => decode_data_present,
Q => data_present_int,
R => reset,
C => clk);
-- Valid write signal
valid_lut: LUT3
--synthesis translate_off
generic map (INIT => X"C4")
--synthesis translate_on
port map( I0 => pointer_full,
I1 => write,
I2 => read,
O => valid_write );
-- assign internal signals to outputs
full <= pointer_full;
half_full <= pointer(3);
data_present <= data_present_int;
end low_level_definition;
------------------------------------------------------------------------------------
--
-- END OF FILE BBFIFO_16x8.VHD
--
------------------------------------------------------------------------------------
| gpl-2.0 | b2851e2faa629872d5a07520323c8178 | 0.477359 | 4.288196 | false | false | false | false |
nsauzede/cpu86 | papilio2_drigmorn1/ipcore_dir/clk32to40/simulation/timing/clk32to40_tb.vhd | 2 | 6,460 | -- file: clk32to40_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity clk32to40_tb is
end clk32to40_tb;
architecture test of clk32to40_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 31.25 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bit of the sampling counter
signal COUNT : std_logic;
signal COUNTER_RESET : std_logic := '0';
signal timeout_counter : std_logic_vector (13 downto 0) := (others => '0');
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(1 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component clk32to40_exdes
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
report "Timing checks are not valid" severity note;
-- can't probe into hierarchy, wait "some time" for lock
wait for (PER1*2500);
wait for (PER1*20);
COUNTER_RESET <= '1';
wait for (PER1*19.5);
COUNTER_RESET <= '0';
wait for (PER1*1);
report "Timing checks are valid" severity note;
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : clk32to40_exdes
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT);
-- Freq Check
end test;
| gpl-2.0 | e7969baf6d41cb892eb9168f7d388e05 | 0.625542 | 4.194805 | false | false | false | false |
AUT-CEIT/Arch101 | sample-rtl/controller.vhd | 1 | 1,176 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 05-03-2017
-- Module Name: controller.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity controller is
port (register_load, register_shift : out std_logic;
clk, rst : in std_logic);
end entity;
architecture rtl of controller is
type state is (S0, S1, S2, S3, S4);
signal current_state : state;
signal next_state : state;
begin
-- next to current
process (clk, rst)
begin
if rst = '1' then
current_state <= S0;
elsif clk'event and clk = '1' then
current_state <= next_state;
end if;
end process;
-- next based on state
process (current_state)
begin
case current_state is
when S0 =>
next_state <= S1;
register_load <= '1';
register_shift <= '0';
when S1 =>
next_state <= S2;
register_load <= '0';
register_shift <= '1';
when S2 =>
next_state <= S3;
when S3 =>
next_state <= S4;
when S4 =>
next_state <= S0;
end case;
end process;
end architecture;
| gpl-3.0 | d4fae1b8ff17328647652119cd9e51fe | 0.541667 | 3.257618 | false | false | false | false |
nsauzede/cpu86 | papilio1/papilio1_top.vhd | 1 | 2,630 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:43:24 02/17/2015
-- Design Name:
-- Module Name: papilio1_top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
USE ieee.STD_LOGIC_UNSIGNED.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
ENTITY papilio1_top IS
Port ( rx : in STD_LOGIC;
tx : out STD_LOGIC;
W1A : inout STD_LOGIC_VECTOR (15 downto 0);
W1B : inout STD_LOGIC_VECTOR (15 downto 0);
W2C : inout STD_LOGIC_VECTOR (15 downto 0);
clk : in STD_LOGIC);
END papilio1_top ;
ARCHITECTURE struct OF papilio1_top IS
signal CLOCK_40MHZ : std_logic;
signal CTS : std_logic := '1';
signal PIN3 : std_logic;
signal RXD : std_logic;
signal LED1 : std_logic;
signal LED2N : std_logic;
signal LED3N : std_logic;
signal PIN4 : std_logic;
signal RTS : std_logic;
signal TXD : std_logic;
COMPONENT drigmorn1_top
PORT(
CLOCK_40MHZ : IN std_logic;
CTS : IN std_logic := '1';
PIN3 : IN std_logic;
RXD : IN std_logic;
LED1 : OUT std_logic;
LED2N : OUT std_logic;
LED3N : OUT std_logic;
PIN4 : OUT std_logic;
RTS : OUT std_logic;
TXD : OUT std_logic
);
END component ;
BEGIN
w1a(0) <= TXD;
tx <= TXD;
RXD <= rx;
CTS <= '1';
w1b(1) <= 'Z';
PIN3 <= not w1b(1); -- por
Inst_dcm32to40: entity work.dcm32to40 PORT MAP(
CLKIN_IN => clk,
CLKFX_OUT => CLOCK_40MHZ,
CLKIN_IBUFG_OUT => open,
CLK0_OUT => open
);
drigmorn1_top0 : drigmorn1_top
PORT map(
CLOCK_40MHZ => CLOCK_40MHZ,
CTS => CTS,
PIN3 => PIN3,
RXD => RXD,
LED1 => LED1,
LED2N => LED2N,
LED3N => LED3N,
PIN4 => PIN4,
RTS => RTS,
TXD => TXD
);
END struct;
| gpl-2.0 | 760ff1c13193bd4797981afeca52921e | 0.501521 | 3.384813 | false | false | false | false |
nsauzede/cpu86 | testbench/cpu86_top_tb_struct.vhd | 1 | 12,222 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- TestBench --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY std;
USE std.TEXTIO.all;
USE work.utils.all;
entity cpu86_top_tb is
end cpu86_top_tb ;
ARCHITECTURE struct OF cpu86_top_tb IS
-- Architecture declarations
signal dind1_s : std_logic;
signal dind2_s : std_logic;
-- Internal signal declarations
SIGNAL CE2 : std_logic := '1';
SIGNAL CLOCK_40MHZ : std_logic := '0';
SIGNAL CTS : std_logic;
SIGNAL RESET : std_logic;
SIGNAL TXD : std_logic;
SIGNAL abus : std_logic_vector(19 DOWNTO 0);
SIGNAL csramn : std_logic;
SIGNAL dbus : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_in : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_out : std_logic_vector(7 DOWNTO 0);
SIGNAL cpuerror : std_logic;
SIGNAL rdn : std_logic;
SIGNAL rdn_s : std_logic; -- Active Low Read Pulse (CLK)
SIGNAL rdrf : std_logic;
SIGNAL resoutn : std_logic;
SIGNAL rxenable : std_logic;
SIGNAL txcmd : std_logic;
SIGNAL txenable : std_logic;
SIGNAL udbus : Std_Logic_Vector(7 DOWNTO 0);
SIGNAL wrn : std_logic;
-- Component Declarations
COMPONENT cpu86_top
PORT (
CLOCK_40MHZ : IN std_logic ;
CTS : IN std_logic := '1';
RESET : IN std_logic ;
RXD : IN std_logic ;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
RTS : OUT std_logic ;
TXD : OUT std_logic ;
abus : OUT std_logic_vector (19 DOWNTO 0);
cpuerror : OUT std_logic ;
led2n : OUT std_logic; -- Connected to 16750 OUT1 signal
led3n : OUT std_logic; -- Connected to 16750 OUT2 signal
csramn : OUT std_logic ;
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
rdn : OUT std_logic ;
resoutn : OUT std_logic ;
wrn : OUT std_logic
);
END COMPONENT;
COMPONENT sram
GENERIC (
clear_on_power_up : boolean;
download_on_power_up : boolean;
trace_ram_load : boolean;
enable_nWE_only_control : boolean;
size : INTEGER;
adr_width : INTEGER;
width : INTEGER;
tAA_max : TIME;
tOHA_min : TIME;
tACE_max : TIME;
tDOE_max : TIME;
tLZOE_min : TIME;
tHZOE_max : TIME;
tLZCE_min : TIME;
tHZCE_max : TIME;
tWC_min : TIME;
tSCE_min : TIME;
tAW_min : TIME;
tHA_min : TIME;
tSA_min : TIME;
tPWE_min : TIME;
tSD_min : TIME;
tHD_min : TIME;
tHZWE_max : TIME;
tLZWE_min : TIME
);
PORT (
A : IN std_logic_vector (adr_width-1 DOWNTO 0);
CE2 : IN std_logic := '1';
download : IN boolean := FALSE;
download_filename : IN string := "loadfname.dat";
dump : IN boolean := FALSE;
dump_end : IN natural := size-1;
dump_filename : IN string := "dumpfname.dat";
dump_start : IN natural := 0;
nCE : IN std_logic := '1';
nOE : IN std_logic := '1';
nWE : IN std_logic := '1';
D : INOUT std_logic_vector (width-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT tester
PORT (
resoutn : IN std_logic ;
CTS : OUT std_logic ;
RESET : OUT std_logic ;
rxenable : OUT std_logic ;
CLOCK_40MHZ : BUFFER std_logic ;
txenable : BUFFER std_logic ;
txcmd : OUT std_logic
);
END COMPONENT;
COMPONENT uartrx
PORT (
clk : IN std_logic;
enable : IN std_logic;
rdn : IN std_logic;
resetn : IN std_logic;
rx : IN std_logic;
dbus : OUT std_logic_vector (7 DOWNTO 0);
ferror : OUT std_logic;
rdrf : OUT std_logic
);
END COMPONENT;
BEGIN
-- Architecture concurrent statements
process (wrn,dbus_out)
begin
case wrn is
when '0' => dbus<= dbus_out after 10 ns; -- drive porta
when '1' => dbus<= (others => 'Z') after 10 ns;
when others => dbus<= (others => 'X') after 10 ns;
end case;
end process;
dbus_in <= dbus; -- drive internal dbus
assert not ((NOW > 0 ns) and cpuerror='1') report "**** CPU Error flag asserted ****" severity failure;
-- UART Monitor
-- Display string after 80 characters or CR character is received
process (rdrf,resoutn)
variable L : line;
variable i_v : integer;
begin
if resoutn='0' then
i_v := 0; -- clear character counter
elsif (rising_edge(rdrf)) then -- possible, pulse is wide!
if i_v=0 then
write(L,string'("RD UART : "));
if (udbus/=X"0D" and udbus/=X"0A") then
write(L,std_to_char(udbus));
end if;
i_v := i_v+1;
elsif (i_v=80 or udbus=X"0D") then
writeline(output,L);
i_v:=0;
else
if (udbus/=X"0D" and udbus/=X"0A") then
write(L,std_to_char(udbus));
end if;
i_v := i_v+1;
end if;
end if;
end process;
process (CLOCK_40MHZ,resoutn) -- First/Second delay
begin
if (resoutn='0') then
dind1_s <= '0';
dind2_s <= '0';
elsif (rising_edge(CLOCK_40MHZ)) then
dind1_s <= rdrf;
dind2_s <= dind1_s;
end if;
end process;
rdn_s <= '0' when (dind1_s='1' and dind2_s='0') else '1';
CE2 <= '1';
-- Instance port mappings.
U_0 : cpu86_top
PORT MAP (
CLOCK_40MHZ => CLOCK_40MHZ,
CTS => CTS,
RESET => RESET,
RXD => txcmd,
dbus_in => dbus_in,
RTS => OPEN,
TXD => TXD,
abus => abus,
cpuerror => cpuerror,
led2n => OPEN,
led3n => OPEN,
csramn => csramn,
dbus_out => dbus_out,
rdn => rdn,
resoutn => resoutn,
wrn => wrn
);
U_12 : sram
GENERIC MAP (
clear_on_power_up => TRUE,
download_on_power_up => TRUE,
trace_ram_load => FALSE,
enable_nWE_only_control => FALSE,
size => 262144,
adr_width => 18,
width => 8,
tAA_max => 20 NS,
tOHA_min => 3 NS,
tACE_max => 20 NS,
tDOE_max => 8 NS,
tLZOE_min => 0 NS,
tHZOE_max => 8 NS,
tLZCE_min => 3 NS,
tHZCE_max => 10 NS,
tWC_min => 20 NS,
tSCE_min => 18 NS,
tAW_min => 15 NS,
tHA_min => 0 NS,
tSA_min => 0 NS,
tPWE_min => 13 NS,
tSD_min => 10 NS,
tHD_min => 0 NS,
tHZWE_max => 10 NS,
tLZWE_min => 0 NS
)
PORT MAP (
download_filename => OPEN,
nCE => csramn,
nOE => rdn,
nWE => wrn,
A => abus(17 DOWNTO 0),
D => dbus,
CE2 => CE2,
download => OPEN,
dump => OPEN,
dump_start => OPEN,
dump_end => OPEN,
dump_filename => OPEN
);
U_1 : tester
PORT MAP (
resoutn => resoutn,
CTS => CTS,
RESET => RESET,
rxenable => rxenable,
CLOCK_40MHZ => CLOCK_40MHZ,
txenable => txenable,
txcmd => txcmd
);
U_3 : uartrx
PORT MAP (
clk => CLOCK_40MHZ,
enable => rxenable,
resetn => resoutn,
dbus => udbus,
rdn => rdn_s,
rdrf => rdrf,
ferror => OPEN,
rx => TXD
);
END struct;
| gpl-2.0 | 59089100bb87fd3e3b248493420d632a | 0.38398 | 4.535065 | false | false | false | false |
kdgwill/VHDL_Verilog_Encryptions_And_Ciphers | VHDL_RC5/Encryption_Decryption/bak/rc5_dec_2.bak.vhd | 1 | 7,167 | --RC5 Decryption
--for i=12 to 1 do
----B = ((B - S[2×i +1]) >>> A) xor A;
----A = ((A - S[2×i]) >>> B) xor B;
--B = B - S[1];
--A = A - S[0];
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; -- we will use CONV_INTEGER
USE WORK.RC5_PKG.ALL;
ENTITY rc5_dec IS
PORT (
clr,clk : IN STD_LOGIC; -- Asynchronous reset and Clock Signal
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); -- 64-bit input
di_vld : IN STD_LOGIC; -- Valid Input
key_rdy : IN STD_LOGIC;
skey : IN rc5_rom_26;
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); -- 64-bit output
do_rdy : OUT STD_LOGIC --Output is Ready
);
END rc5_dec;
ARCHITECTURE rtl OF rc5_dec IS
SIGNAL i_cnt : STD_LOGIC_VECTOR(3 DOWNTO 0); -- round counter
SIGNAL ba_xor : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_rot : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_post : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); -- register B
SIGNAL ab_xor : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_rot : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_post : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); -- register A
-- RC5 state machine has five states: idle, round, post_round and ready
SIGNAL state : dec_StateType;
BEGIN
--B = ((B - S[2×i +1]) >>> A) xor A;
b<=b_reg - skey(CONV_INTEGER(i_cnt & '1')); --B - S[2*i+1]
WITH a_reg(4 DOWNTO 0) SELECT --B >>> A
b_rot<= b(0) & b(31 DOWNTO 01) WHEN "00001", --01
b(01 DOWNTO 0) & b(31 DOWNTO 02) WHEN "00010", --02
b(02 DOWNTO 0) & b(31 DOWNTO 03) WHEN "00011", --03
b(03 DOWNTO 0) & b(31 DOWNTO 04) WHEN "00100", --04
b(04 DOWNTO 0) & b(31 DOWNTO 05) WHEN "00101", --05
b(05 DOWNTO 0) & b(31 DOWNTO 06) WHEN "00110", --06
b(06 DOWNTO 0) & b(31 DOWNTO 07) WHEN "00111", --07
b(07 DOWNTO 0) & b(31 DOWNTO 08) WHEN "01000", --08
b(08 DOWNTO 0) & b(31 DOWNTO 09) WHEN "01001", --09
b(09 DOWNTO 0) & b(31 DOWNTO 10) WHEN "01010", --10
b(10 DOWNTO 0) & b(31 DOWNTO 11) WHEN "01011", --11
b(11 DOWNTO 0) & b(31 DOWNTO 12) WHEN "01100", --12
b(12 DOWNTO 0) & b(31 DOWNTO 13) WHEN "01101", --13
b(13 DOWNTO 0) & b(31 DOWNTO 14) WHEN "01110", --14
b(14 DOWNTO 0) & b(31 DOWNTO 15) WHEN "01111", --15
b(15 DOWNTO 0) & b(31 DOWNTO 16) WHEN "10000", --16
b(16 DOWNTO 0) & b(31 DOWNTO 17) WHEN "10001", --17
b(17 DOWNTO 0) & b(31 DOWNTO 18) WHEN "10010", --18
b(18 DOWNTO 0) & b(31 DOWNTO 19) WHEN "10011", --19
b(19 DOWNTO 0) & b(31 DOWNTO 20) WHEN "10100", --20
b(20 DOWNTO 0) & b(31 DOWNTO 21) WHEN "10101", --21
b(21 DOWNTO 0) & b(31 DOWNTO 22) WHEN "10110", --22
b(22 DOWNTO 0) & b(31 DOWNTO 23) WHEN "10111", --23
b(23 DOWNTO 0) & b(31 DOWNTO 24) WHEN "11000", --24
b(24 DOWNTO 0) & b(31 DOWNTO 25) WHEN "11001", --25
b(25 DOWNTO 0) & b(31 DOWNTO 26) WHEN "11010", --26
b(26 DOWNTO 0) & b(31 DOWNTO 27) WHEN "11011", --27
b(27 DOWNTO 0) & b(31 DOWNTO 28) WHEN "11100", --28
b(28 DOWNTO 0) & b(31 DOWNTO 29) WHEN "11101", --29
b(29 DOWNTO 0) & b(31 DOWNTO 30) WHEN "11110", --30
b(30 DOWNTO 0) & b(31) WHEN "11111", --31
b WHEN OTHERS; --32
ba_xor <= b_rot XOR a_reg; --B XOR A
--A = ((A - S[2×i]) >>> B) xor B;
a<=a_reg - skey(CONV_INTEGER(i_cnt & '0')); -- A - S[2*i]
WITH ba_xor(4 DOWNTO 0) SELECT --A >>> B
a_rot<= a(0) & a(31 DOWNTO 01) WHEN "00001", --01
a(01 DOWNTO 0) & a(31 DOWNTO 02) WHEN "00010", --02
a(02 DOWNTO 0) & a(31 DOWNTO 03) WHEN "00011", --03
a(03 DOWNTO 0) & a(31 DOWNTO 04) WHEN "00100", --04
a(04 DOWNTO 0) & a(31 DOWNTO 05) WHEN "00101", --05
a(05 DOWNTO 0) & a(31 DOWNTO 06) WHEN "00110", --06
a(06 DOWNTO 0) & a(31 DOWNTO 07) WHEN "00111", --07
a(07 DOWNTO 0) & a(31 DOWNTO 08) WHEN "01000", --08
a(08 DOWNTO 0) & a(31 DOWNTO 09) WHEN "01001", --09
a(09 DOWNTO 0) & a(31 DOWNTO 10) WHEN "01010", --10
a(10 DOWNTO 0) & a(31 DOWNTO 11) WHEN "01011", --11
a(11 DOWNTO 0) & a(31 DOWNTO 12) WHEN "01100", --12
a(12 DOWNTO 0) & a(31 DOWNTO 13) WHEN "01101", --13
a(13 DOWNTO 0) & a(31 DOWNTO 14) WHEN "01110", --14
a(14 DOWNTO 0) & a(31 DOWNTO 15) WHEN "01111", --15
a(15 DOWNTO 0) & a(31 DOWNTO 16) WHEN "10000", --16
a(16 DOWNTO 0) & a(31 DOWNTO 17) WHEN "10001", --17
a(17 DOWNTO 0) & a(31 DOWNTO 18) WHEN "10010", --18
a(18 DOWNTO 0) & a(31 DOWNTO 19) WHEN "10011", --19
a(19 DOWNTO 0) & a(31 DOWNTO 20) WHEN "10100", --20
a(20 DOWNTO 0) & a(31 DOWNTO 21) WHEN "10101", --21
a(21 DOWNTO 0) & a(31 DOWNTO 22) WHEN "10110", --22
a(22 DOWNTO 0) & a(31 DOWNTO 23) WHEN "10111", --23
a(23 DOWNTO 0) & a(31 DOWNTO 24) WHEN "11000", --24
a(24 DOWNTO 0) & a(31 DOWNTO 25) WHEN "11001", --25
a(25 DOWNTO 0) & a(31 DOWNTO 26) WHEN "11010", --26
a(26 DOWNTO 0) & a(31 DOWNTO 27) WHEN "11011", --27
a(27 DOWNTO 0) & a(31 DOWNTO 28) WHEN "11100", --28
a(28 DOWNTO 0) & a(31 DOWNTO 29) WHEN "11101", --29
a(29 DOWNTO 0) & a(31 DOWNTO 30) WHEN "11110", --30
a(30 DOWNTO 0) & a(31) WHEN "11111", --31
a WHEN OTHERS; --32
ab_xor <= a_rot XOR ba_xor; -- A XOR B
b_post<=b_reg - skey(1); --B = B - S[1]
a_post<=a_reg - skey(0); --A = A - S[0]
A_register:
PROCESS(clr, clk) BEGIN
IF(clr='0') THEN
a_reg<=din(63 DOWNTO 32);
ELSIF(rising_edge(clk)) THEN --clk'EVENT AND clk='1' can introduce error
IF(state=ST_POST_ROUND) THEN
a_reg<=a_post;
ELSIF(state=ST_ROUND_OP) THEN
a_reg<=ab_xor;
END IF;
END IF;
END PROCESS;
B_register:
PROCESS(clr, clk) BEGIN
IF(clr='0') THEN
b_reg<=din(31 DOWNTO 0);
ELSIF(rising_edge(clk)) THEN
IF(state=ST_POST_ROUND) THEN
b_reg<=b_post;
ELSIF(state=ST_ROUND_OP) THEN
b_reg<=ba_xor;
END IF;
END IF;
END PROCESS;
State_Control:
PROCESS(clr, clk)
BEGIN
IF(clr='0') THEN
state<=ST_IDLE;
ELSIF(clk'EVENT AND clk='1') THEN
CASE state IS
WHEN ST_IDLE=> IF(di_vld='1' and key_rdy='1') THEN
state<=ST_ROUND_OP;
END IF;
WHEN ST_ROUND_OP=> IF(i_cnt="0001") THEN
state<=ST_POST_ROUND;
END IF;
WHEN ST_POST_ROUND=> state<=ST_READY;
WHEN ST_READY=> IF(di_vld='1' and key_rdy='1') THEN
state<=ST_ROUND_OP;--can assume new keys and skip idle state
--state<=ST_IDLE; --If Input Changes then restart
END IF;
END CASE;
END IF;
END PROCESS;
round_counter:
PROCESS(clr, clk) BEGIN
IF(clr='0') THEN
i_cnt<="1100";
ELSIF(rising_edge(clk) AND state=ST_ROUND_OP) THEN
IF(i_cnt="0001") THEN
i_cnt<="1100";
ELSE
i_cnt<=i_cnt-'1';
END IF;
END IF;
END PROCESS;
dout<=a_reg & b_reg;
WITH state SELECT
do_rdy<='1' WHEN ST_READY,
'0' WHEN OTHERS;
END rtl; | lgpl-2.1 | 0b36df22447069f8d8b36373ea7c1a81 | 0.555602 | 2.735496 | false | false | false | false |
willprice/vhdl-computer | src/rtl/comparator_1bit.vhd | 1 | 1,047 | ------------------------------------------------------------------------------
-- @file comparator_1bit.vhd
-- @brief A very simple 1 bit comparator with LT, EQ, and GT output bits.
-- @see comparator_1bit.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--
-- @brief Acts as a 1 bit comparator. Comp is compared with base.
-- lt is set iff comp is less than base.
-- likewise for gt.
--
entity comparator_1bit is
port(
base : in std_logic;
comp : in std_logic;
lt : out std_logic;
gt : out std_logic;
eq : out std_logic
);
end entity comparator_1bit;
architecture rtl of comparator_1bit is
-- factord out common signals for lt, gt and eq
signal not_base : std_logic;
signal not_comp : std_logic;
begin
not_base <= not base;
not_comp <= not comp;
eq <= (base and comp) or (not_base and not_comp);
lt <= base and not_comp;
gt <= not_base and comp;
end architecture rtl;
| gpl-3.0 | f22ed125d37f8425084d69d610c2a9c3 | 0.531996 | 3.863469 | false | false | false | false |
nsauzede/cpu86 | papilio2_drigmorn1/ipcore_dir/clk32to40/example_design/clk32to40_exdes.vhd | 2 | 5,575 | -- file: clk32to40_exdes.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard example design
------------------------------------------------------------------------------
-- This example design instantiates the created clocking network, where each
-- output clock drives a counter. The high bit of each counter is ported.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk32to40_exdes is
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic
);
end clk32to40_exdes;
architecture xilinx of clk32to40_exdes is
-- Parameters for the counters
---------------------------------
-- Counter width
constant C_W : integer := 16;
-- Reset for counters when lock status changes
signal reset_int : std_logic := '0';
-- Declare the clocks and counter
signal clk : std_logic;
signal clk_int : std_logic;
signal clk_n : std_logic;
signal counter : std_logic_vector(C_W-1 downto 0) := (others => '0');
signal rst_sync : std_logic;
signal rst_sync_int : std_logic;
signal rst_sync_int1 : std_logic;
signal rst_sync_int2 : std_logic;
component clk32to40 is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end component;
begin
-- Create reset for the counters
reset_int <= COUNTER_RESET;
process (clk, reset_int) begin
if (reset_int = '1') then
rst_sync <= '1';
rst_sync_int <= '1';
rst_sync_int1 <= '1';
rst_sync_int2 <= '1';
elsif (clk 'event and clk='1') then
rst_sync <= '0';
rst_sync_int <= rst_sync;
rst_sync_int1 <= rst_sync_int;
rst_sync_int2 <= rst_sync_int1;
end if;
end process;
-- Instantiation of the clocking network
----------------------------------------
clknetwork : clk32to40
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Clock out ports
CLK_OUT1 => clk_int);
clk_n <= not clk;
clkout_oddr : ODDR2
port map
(Q => CLK_OUT(1),
C0 => clk,
C1 => clk_n,
CE => '1',
D0 => '1',
D1 => '0',
R => '0',
S => '0');
-- Connect the output clocks to the design
-------------------------------------------
clk <= clk_int;
-- Output clock sampling
-------------------------------------
process (clk, rst_sync_int2) begin
if (rst_sync_int2 = '1') then
counter <= (others => '0') after TCQ;
elsif (rising_edge(clk)) then
counter <= counter + 1 after TCQ;
end if;
end process;
-- alias the high bit to the output
COUNT <= counter(C_W-1);
end xilinx;
| gpl-2.0 | bc00f936ad8bf61b8fd32f35ffea5e0f | 0.599641 | 3.999283 | false | false | false | false |
nsauzede/cpu86 | papilio2_drigmorn1/ipcore_dir/blk_mem_40K/simulation/bmg_stim_gen.vhd | 2 | 7,816 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SRAM
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(8,8);
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL COUNT_NO : INTEGER :=0;
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
BEGIN
WRITE_ADDR_INT(15 DOWNTO 0) <= WRITE_ADDR(15 DOWNTO 0);
READ_ADDR_INT(15 DOWNTO 0) <= READ_ADDR(15 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
DINA <= DINA_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 65536
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 65536 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 8,
DOUT_WIDTH => 8,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
WR_RD_PROCESS: PROCESS (CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
ELSIF(COUNT_NO < 4) THEN
DO_WRITE <= '1';
DO_READ <= '0';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO< 8) THEN
DO_WRITE <= '0';
DO_READ <= '1';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO=8) THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLK,
RST => RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
WEA(0) <= IF_THEN_ELSE(DO_WRITE='1','1','0') ;
END ARCHITECTURE;
| gpl-2.0 | 080e8b354e11ee572dd67b752bef7a76 | 0.540942 | 3.732569 | false | false | false | false |
hacklabmikkeli/knobs-galore | preset_selector.vhdl | 2 | 5,513 | --
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
entity preset_selector is
port (EN: in std_logic
;CLK: in std_logic
;KEY_CODE: in keys_signal
;KEY_EVENT: in key_event_t
;PARAMS: out synthesis_params
);
end entity;
architecture preset_selector_impl of preset_selector is
subtype quantized_t is unsigned(2 downto 0);
function time_unquantize(quantized: quantized_t)
return ctl_signal is
begin
case quantized is
when "000" => return x"01";
when "001" => return x"02";
when "010" => return x"04";
when "011" => return x"08";
when "100" => return x"10";
when "101" => return x"20";
when "110" => return x"80";
when "111" => return x"F0";
when others => return x"FF";
end case;
end function;
function level_unquantize(quantized: quantized_t)
return ctl_signal is
begin
case quantized is
when "000" => return x"00";
when "001" => return x"20";
when "010" => return x"40";
when "011" => return x"60";
when "100" => return x"80";
when "101" => return x"A0";
when "110" => return x"C0";
when "111" => return x"E0";
when others => return x"FF";
end case;
end function;
signal mode: mode_t := mode_saw;
signal transform: voice_transform_t := voice_transform_none;
signal q_cutoff_base: quantized_t := "000";
signal q_cutoff_env: quantized_t := "111";
signal q_cutoff_attack: quantized_t := "111";
signal q_cutoff_decay: quantized_t := "000";
signal q_cutoff_sustain: quantized_t := "111";
signal q_cutoff_rel: quantized_t := "111";
signal q_gain_attack: quantized_t := "111";
signal q_gain_decay: quantized_t := "111";
signal q_gain_sustain: quantized_t := "111";
signal q_gain_rel: quantized_t := "111";
begin
process(CLK)
begin
if EN = '1' and rising_edge(CLK) then
if KEY_EVENT = key_event_make then
case KEY_CODE is
-- Preset editing
when "001100" => mode <= mode - 1;
when "001101" => mode <= mode + 1;
when "001001" => transform <= transform - 1;
when "001010" => transform <= transform + 1;
when "001111" => q_cutoff_base <= q_cutoff_base - 1;
when "001110" => q_cutoff_base <= q_cutoff_base + 1;
when "100010" => q_cutoff_env <= q_cutoff_env - 1;
when "001000" => q_cutoff_env <= q_cutoff_env + 1;
when "000010" => q_cutoff_attack <= q_cutoff_attack + 1;
when "000011" => q_cutoff_attack <= q_cutoff_attack - 1;
when "000001" => q_cutoff_decay <= q_cutoff_decay + 1;
when "000000" => q_cutoff_decay <= q_cutoff_decay - 1;
when "000111" => q_cutoff_sustain <= q_cutoff_sustain - 1;
when "000110" => q_cutoff_sustain <= q_cutoff_sustain + 1;
when "000101" => q_cutoff_rel <= q_cutoff_rel + 1;
when "000100" => q_cutoff_rel <= q_cutoff_rel - 1;
when "010000" => q_gain_attack <= q_gain_attack + 1;
when "010001" => q_gain_attack <= q_gain_attack - 1;
when "010010" => q_gain_decay <= q_gain_decay + 1;
when "010011" => q_gain_decay <= q_gain_decay - 1;
when "010111" => q_gain_sustain <= q_gain_sustain - 1;
when "010110" => q_gain_sustain <= q_gain_sustain + 1;
when "010101" => q_gain_rel <= q_gain_rel + 1;
when "010100" => q_gain_rel <= q_gain_rel - 1;
when others => null;
end case;
end if;
end if;
end process;
PARAMS <= (mode
,transform
,level_unquantize(q_cutoff_base)
,level_unquantize(q_cutoff_env)
,time_unquantize(q_cutoff_attack)
,time_unquantize(q_cutoff_decay)
,level_unquantize(q_cutoff_sustain)
,time_unquantize(q_cutoff_rel)
,time_unquantize(q_gain_attack)
,time_unquantize(q_gain_decay)
,level_unquantize(q_gain_sustain)
,time_unquantize(q_gain_rel)
);
end architecture;
| gpl-3.0 | 245180cd9a5e96992c4a36ce0d447e25 | 0.520406 | 3.882394 | false | false | false | false |
nsauzede/cpu86 | papilio2_lcd/cpu86instr.vhd | 3 | 24,202 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE cpu86instr IS
-----------------------------------------------------------------------------
-- INC/DEC Word Register
-----------------------------------------------------------------------------
constant INCREG0 : std_logic_vector(7 downto 0) := X"40"; -- Inc Register
constant INCREG1 : std_logic_vector(7 downto 0) := X"41";
constant INCREG2 : std_logic_vector(7 downto 0) := X"42";
constant INCREG3 : std_logic_vector(7 downto 0) := X"43";
constant INCREG4 : std_logic_vector(7 downto 0) := X"44";
constant INCREG5 : std_logic_vector(7 downto 0) := X"45";
constant INCREG6 : std_logic_vector(7 downto 0) := X"46";
constant INCREG7 : std_logic_vector(7 downto 0) := X"47";
constant DECREG0 : std_logic_vector(7 downto 0) := X"48"; -- DEC Register
constant DECREG1 : std_logic_vector(7 downto 0) := X"49";
constant DECREG2 : std_logic_vector(7 downto 0) := X"4A";
constant DECREG3 : std_logic_vector(7 downto 0) := X"4B";
constant DECREG4 : std_logic_vector(7 downto 0) := X"4C";
constant DECREG5 : std_logic_vector(7 downto 0) := X"4D";
constant DECREG6 : std_logic_vector(7 downto 0) := X"4E";
constant DECREG7 : std_logic_vector(7 downto 0) := X"4F";
-----------------------------------------------------------------------------
-- IN
-----------------------------------------------------------------------------
constant INFIXED0 : std_logic_vector(7 downto 0) := X"E4"; -- Fixed Port Byte
constant INFIXED1 : std_logic_vector(7 downto 0) := X"E5"; -- Fixed Port Word
constant INDX0 : std_logic_vector(7 downto 0) := X"EC"; -- DX Byte
constant INDX1 : std_logic_vector(7 downto 0) := X"ED"; -- DX Word
-----------------------------------------------------------------------------
-- OUT
-----------------------------------------------------------------------------
constant OUTFIXED0 : std_logic_vector(7 downto 0) := X"E6"; -- Fixed Port Byte
constant OUTFIXED1 : std_logic_vector(7 downto 0) := X"E7"; -- Fixed Port Word
constant OUTDX0 : std_logic_vector(7 downto 0) := X"EE"; -- DX Byte
constant OUTDX1 : std_logic_vector(7 downto 0) := X"EF"; -- DX Word
-----------------------------------------------------------------------------
-- Move Immediate to Register
-----------------------------------------------------------------------------
constant MOVI2R0 : std_logic_vector(7 downto 0) := X"B0"; -- Immediate to Register
constant MOVI2R1 : std_logic_vector(7 downto 0) := X"B1"; -- Byte
constant MOVI2R2 : std_logic_vector(7 downto 0) := X"B2";
constant MOVI2R3 : std_logic_vector(7 downto 0) := X"B3";
constant MOVI2R4 : std_logic_vector(7 downto 0) := X"B4";
constant MOVI2R5 : std_logic_vector(7 downto 0) := X"B5";
constant MOVI2R6 : std_logic_vector(7 downto 0) := X"B6";
constant MOVI2R7 : std_logic_vector(7 downto 0) := X"B7";
constant MOVI2R8 : std_logic_vector(7 downto 0) := X"B8"; -- Word
constant MOVI2R9 : std_logic_vector(7 downto 0) := X"B9";
constant MOVI2R10 : std_logic_vector(7 downto 0) := X"BA";
constant MOVI2R11 : std_logic_vector(7 downto 0) := X"BB";
constant MOVI2R12 : std_logic_vector(7 downto 0) := X"BC";
constant MOVI2R13 : std_logic_vector(7 downto 0) := X"BD";
constant MOVI2R14 : std_logic_vector(7 downto 0) := X"BE";
constant MOVI2R15 : std_logic_vector(7 downto 0) := X"BF";
-----------------------------------------------------------------------------
-- Move Immediate to Register/memory
-----------------------------------------------------------------------------
constant MOVI2RM0 : std_logic_vector(7 downto 0) := X"C6";
constant MOVI2RM1 : std_logic_vector(7 downto 0) := X"C7"; -- Word
-----------------------------------------------------------------------------
-- Segment Register to Register or Memory
-----------------------------------------------------------------------------
constant MOVS2RM : std_logic_vector(7 downto 0) := X"8C";
-----------------------------------------------------------------------------
-- Register or Memory to Segment Register
-----------------------------------------------------------------------------
constant MOVRM2S : std_logic_vector(7 downto 0) := X"8E";
-----------------------------------------------------------------------------
-- Memory to Accumulator ADDRL,ADDRH
-----------------------------------------------------------------------------
constant MOVM2A0 : std_logic_vector(7 downto 0) := X"A0";
constant MOVM2A1 : std_logic_vector(7 downto 0) := X"A1";
-----------------------------------------------------------------------------
-- Accumulator to Memory to Accumulator ADDRL,ADDRH
-----------------------------------------------------------------------------
constant MOVA2M0 : std_logic_vector(7 downto 0) := X"A2";
constant MOVA2M1 : std_logic_vector(7 downto 0) := X"A3";
-----------------------------------------------------------------------------
-- Register/Memory to/from Register
-----------------------------------------------------------------------------
constant MOVRM2R0 : std_logic_vector(7 downto 0) := X"88";
constant MOVRM2R1 : std_logic_vector(7 downto 0) := X"89";
constant MOVRM2R2 : std_logic_vector(7 downto 0) := X"8A";
constant MOVRM2R3 : std_logic_vector(7 downto 0) := X"8B";
-----------------------------------------------------------------------------
-- Segment Override Prefix
-----------------------------------------------------------------------------
constant SEGOPES : std_logic_vector(7 downto 0) := X"26";
constant SEGOPCS : std_logic_vector(7 downto 0) := X"2E";
constant SEGOPSS : std_logic_vector(7 downto 0) := X"36";
constant SEGOPDS : std_logic_vector(7 downto 0) := X"3E";
-----------------------------------------------------------------------------
-- ADD/ADC/SUB/SBB/CMP/AND/OR/XOR Register/Memory to Register
-----------------------------------------------------------------------------
constant ADDRM2R0 : std_logic_vector(7 downto 0) := X"00";
constant ADDRM2R1 : std_logic_vector(7 downto 0) := X"01";
constant ADDRM2R2 : std_logic_vector(7 downto 0) := X"02";
constant ADDRM2R3 : std_logic_vector(7 downto 0) := X"03";
constant ADCRM2R0 : std_logic_vector(7 downto 0) := X"10";
constant ADCRM2R1 : std_logic_vector(7 downto 0) := X"11";
constant ADCRM2R2 : std_logic_vector(7 downto 0) := X"12";
constant ADCRM2R3 : std_logic_vector(7 downto 0) := X"13";
constant SUBRM2R0 : std_logic_vector(7 downto 0) := X"28";
constant SUBRM2R1 : std_logic_vector(7 downto 0) := X"29";
constant SUBRM2R2 : std_logic_vector(7 downto 0) := X"2A";
constant SUBRM2R3 : std_logic_vector(7 downto 0) := X"2B";
constant SBBRM2R0 : std_logic_vector(7 downto 0) := X"18";
constant SBBRM2R1 : std_logic_vector(7 downto 0) := X"19";
constant SBBRM2R2 : std_logic_vector(7 downto 0) := X"1A";
constant SBBRM2R3 : std_logic_vector(7 downto 0) := X"1B";
constant CMPRM2R0 : std_logic_vector(7 downto 0) := X"38";
constant CMPRM2R1 : std_logic_vector(7 downto 0) := X"39";
constant CMPRM2R2 : std_logic_vector(7 downto 0) := X"3A";
constant CMPRM2R3 : std_logic_vector(7 downto 0) := X"3B";
constant ANDRM2R0 : std_logic_vector(7 downto 0) := X"20";
constant ANDRM2R1 : std_logic_vector(7 downto 0) := X"21";
constant ANDRM2R2 : std_logic_vector(7 downto 0) := X"22";
constant ANDRM2R3 : std_logic_vector(7 downto 0) := X"23";
constant ORRM2R0 : std_logic_vector(7 downto 0) := X"08";
constant ORRM2R1 : std_logic_vector(7 downto 0) := X"09";
constant ORRM2R2 : std_logic_vector(7 downto 0) := X"0A";
constant ORRM2R3 : std_logic_vector(7 downto 0) := X"0B";
constant XORRM2R0 : std_logic_vector(7 downto 0) := X"30";
constant XORRM2R1 : std_logic_vector(7 downto 0) := X"31";
constant XORRM2R2 : std_logic_vector(7 downto 0) := X"32";
constant XORRM2R3 : std_logic_vector(7 downto 0) := X"33";
-----------------------------------------------------------------------------
-- OPCODE 80,81,83, ADD/ADC/SUB/SBB/CMP/AND/OR/XOR Immediate to Reg/Mem
-- Instruction defined in reg field
-----------------------------------------------------------------------------
constant O80I2RM : std_logic_vector(7 downto 0) := X"80";
constant O81I2RM : std_logic_vector(7 downto 0) := X"81";
constant O83I2RM : std_logic_vector(7 downto 0) := X"83";
-----------------------------------------------------------------------------
-- ADD/ADC/SUB/SBB/CMP/AND/OR/XOR Immediate with ACCU
-----------------------------------------------------------------------------
constant ADDI2AX0 : std_logic_vector(7 downto 0) := X"04";
constant ADDI2AX1 : std_logic_vector(7 downto 0) := X"05";
constant ADCI2AX0 : std_logic_vector(7 downto 0) := X"14";
constant ADCI2AX1 : std_logic_vector(7 downto 0) := X"15";
constant SUBI2AX0 : std_logic_vector(7 downto 0) := X"2C";
constant SUBI2AX1 : std_logic_vector(7 downto 0) := X"2D";
constant SBBI2AX0 : std_logic_vector(7 downto 0) := X"1C";
constant SBBI2AX1 : std_logic_vector(7 downto 0) := X"1D";
constant CMPI2AX0 : std_logic_vector(7 downto 0) := X"3C";
constant CMPI2AX1 : std_logic_vector(7 downto 0) := X"3D";
constant ANDI2AX0 : std_logic_vector(7 downto 0) := X"24";
constant ANDI2AX1 : std_logic_vector(7 downto 0) := X"25";
constant ORI2AX0 : std_logic_vector(7 downto 0) := X"0C";
constant ORI2AX1 : std_logic_vector(7 downto 0) := X"0D";
constant XORI2AX0 : std_logic_vector(7 downto 0) := X"34";
constant XORI2AX1 : std_logic_vector(7 downto 0) := X"35";
-----------------------------------------------------------------------------
-- TEST (Same as AND but without returning any results)
-----------------------------------------------------------------------------
constant TESTRMR0 : std_logic_vector(7 downto 0) := X"84";
constant TESTRMR1 : std_logic_vector(7 downto 0) := X"85";
constant TESTI2AX0 : std_logic_vector(7 downto 0) := X"A8";
constant TESTI2AX1 : std_logic_vector(7 downto 0) := X"A9";
-----------------------------------------------------------------------------
-- NOT/TEST F6/F7 Shared Instructions
-- TEST regfield=000
-- NOT regfield=010
-- MUL regfield=100
-- IMUL regfield=101
-- DIV regfield=110
-- IDIV regfield=111
-----------------------------------------------------------------------------
constant F6INSTR : std_logic_vector(7 downto 0) := X"F6"; -- Byte
constant F7INSTR : std_logic_vector(7 downto 0) := X"F7"; -- Word
-----------------------------------------------------------------------------
-- Carry Flag CLC/CMC/STC
-----------------------------------------------------------------------------
constant CLC : std_logic_vector(7 downto 0) := X"F8";
constant CMC : std_logic_vector(7 downto 0) := X"F5";
constant STC : std_logic_vector(7 downto 0) := X"F9";
constant CLD : std_logic_vector(7 downto 0) := X"FC";
constant STDx : std_logic_vector(7 downto 0) := X"FD";
constant CLI : std_logic_vector(7 downto 0) := X"FA";
constant STI : std_logic_vector(7 downto 0) := X"FB";
-----------------------------------------------------------------------------
-- 8080 Instruction LAHF/SAHF
-----------------------------------------------------------------------------
constant LAHF : std_logic_vector(7 downto 0) := X"9F";
constant SAHF : std_logic_vector(7 downto 0) := X"9E";
-----------------------------------------------------------------------------
-- Conditional Jumps Jxxx
-----------------------------------------------------------------------------
constant JZ : std_logic_vector(7 downto 0) := X"74";
constant JL : std_logic_vector(7 downto 0) := X"7C";
constant JLE : std_logic_vector(7 downto 0) := X"7E";
constant JB : std_logic_vector(7 downto 0) := X"72";
constant JBE : std_logic_vector(7 downto 0) := X"76";
constant JP : std_logic_vector(7 downto 0) := X"7A";
constant JO : std_logic_vector(7 downto 0) := X"70";
constant JS : std_logic_vector(7 downto 0) := X"78";
constant JNE : std_logic_vector(7 downto 0) := X"75";
constant JNL : std_logic_vector(7 downto 0) := X"7D";
constant JNLE : std_logic_vector(7 downto 0) := X"7F";
constant JNB : std_logic_vector(7 downto 0) := X"73";
constant JNBE : std_logic_vector(7 downto 0) := X"77";
constant JNP : std_logic_vector(7 downto 0) := X"7B";
constant JNO : std_logic_vector(7 downto 0) := X"71";
constant JNS : std_logic_vector(7 downto 0) := X"79";
constant JMPS : std_logic_vector(7 downto 0) := X"EB"; -- Short Jump within segment , SignExt DISPL
constant JMP : std_logic_vector(7 downto 0) := X"E9"; -- Long Jump within segment, No SignExt DISPL
constant JMPDIS : std_logic_vector(7 downto 0) := X"EA"; -- Jump Inter Segment (CS:IP given)
-----------------------------------------------------------------------------
-- Push/Pop Flags
-----------------------------------------------------------------------------
constant PUSHF : std_logic_vector(7 downto 0) := X"9C";
constant POPF : std_logic_vector(7 downto 0) := X"9D";
-----------------------------------------------------------------------------
-- PUSH Register
-----------------------------------------------------------------------------
constant PUSHAX : std_logic_vector(7 downto 0) := X"50";
constant PUSHCX : std_logic_vector(7 downto 0) := X"51";
constant PUSHDX : std_logic_vector(7 downto 0) := X"52";
constant PUSHBX : std_logic_vector(7 downto 0) := X"53";
constant PUSHSP : std_logic_vector(7 downto 0) := X"54";
constant PUSHBP : std_logic_vector(7 downto 0) := X"55";
constant PUSHSI : std_logic_vector(7 downto 0) := X"56";
constant PUSHDI : std_logic_vector(7 downto 0) := X"57";
constant PUSHES : std_logic_vector(7 downto 0) := X"06";
constant PUSHCS : std_logic_vector(7 downto 0) := X"0E";
constant PUSHSS : std_logic_vector(7 downto 0) := X"16";
constant PUSHDS : std_logic_vector(7 downto 0) := X"1E";
-----------------------------------------------------------------------------
-- Pop Register
-----------------------------------------------------------------------------
constant POPAX : std_logic_vector(7 downto 0) := X"58";
constant POPCX : std_logic_vector(7 downto 0) := X"59";
constant POPDX : std_logic_vector(7 downto 0) := X"5A";
constant POPBX : std_logic_vector(7 downto 0) := X"5B";
constant POPSP : std_logic_vector(7 downto 0) := X"5C";
constant POPBP : std_logic_vector(7 downto 0) := X"5D";
constant POPSI : std_logic_vector(7 downto 0) := X"5E";
constant POPDI : std_logic_vector(7 downto 0) := X"5F";
constant POPES : std_logic_vector(7 downto 0) := X"07";
constant POPSS : std_logic_vector(7 downto 0) := X"17";
constant POPDS : std_logic_vector(7 downto 0) := X"1F";
constant POPRM : std_logic_vector(7 downto 0) := X"8F";
-----------------------------------------------------------------------------
-- Exchange Register
-----------------------------------------------------------------------------
constant XCHGW : std_logic_vector(7 downto 0) := X"86";
constant XCHGB : std_logic_vector(7 downto 0) := X"87";
constant XCHGAX : std_logic_vector(7 downto 0) := X"90";
constant XCHGCX : std_logic_vector(7 downto 0) := X"91";
constant XCHGDX : std_logic_vector(7 downto 0) := X"92";
constant XCHGBX : std_logic_vector(7 downto 0) := X"93";
constant XCHGSP : std_logic_vector(7 downto 0) := X"94";
constant XCHGBP : std_logic_vector(7 downto 0) := X"95";
constant XCHGSI : std_logic_vector(7 downto 0) := X"96";
constant XCHGDI : std_logic_vector(7 downto 0) := X"97";
-----------------------------------------------------------------------------
-- Load Effective Address
-----------------------------------------------------------------------------
constant LEA : std_logic_vector(7 downto 0) := X"8D";
constant LDS : std_logic_vector(7 downto 0) := X"C5";
constant LES : std_logic_vector(7 downto 0) := X"C4";
-----------------------------------------------------------------------------
-- Convert Instructions
-----------------------------------------------------------------------------
constant CBW : std_logic_vector(7 downto 0) := X"98";
constant CWD : std_logic_vector(7 downto 0) := X"99";
constant AAS : std_logic_vector(7 downto 0) := X"3F";
constant DAS : std_logic_vector(7 downto 0) := X"2F";
constant AAA : std_logic_vector(7 downto 0) := X"37";
constant DAA : std_logic_vector(7 downto 0) := X"27";
constant AAM : std_logic_vector(7 downto 0) := X"D4";
constant AAD : std_logic_vector(7 downto 0) := X"D5";
constant XLAT : std_logic_vector(7 downto 0) := X"D7";
-----------------------------------------------------------------------------
-- Misc Instructions
-----------------------------------------------------------------------------
constant NOP : std_logic_vector(7 downto 0) := X"90"; -- No Operatio
constant LOCKBUS : std_logic_vector(7 downto 0) := X"F0"; -- Assert /LOCK signal
constant WAITx : std_logic_vector(7 downto 0) := X"9B"; -- WAIT is not implemented, result in NOP
constant HLT : std_logic_vector(7 downto 0) := X"F4"; -- Halt Instruction, wait NMI, INTR, Reset
-----------------------------------------------------------------------------
-- Loop Instructions
-----------------------------------------------------------------------------
constant LOOPCX : std_logic_vector(7 downto 0) := X"E2";
constant LOOPZ : std_logic_vector(7 downto 0) := X"E1";
constant LOOPNZ : std_logic_vector(7 downto 0) := X"E0";
constant JCXZ : std_logic_vector(7 downto 0) := X"E3";
-----------------------------------------------------------------------------
-- CALL Instructions
-----------------------------------------------------------------------------
constant CALL : std_logic_vector(7 downto 0) := X"E8"; -- Direct within Segment
constant CALLDIS : std_logic_vector(7 downto 0) := X"9A"; -- Direct Inter Segment
-----------------------------------------------------------------------------
-- RET Instructions
-----------------------------------------------------------------------------
constant RET : std_logic_vector(7 downto 0) := X"C3"; -- Within Segment
constant RETDIS : std_logic_vector(7 downto 0) := X"CB"; -- Direct Inter Segment
constant RETO : std_logic_vector(7 downto 0) := X"C2"; -- Within Segment + Offset
constant RETDISO : std_logic_vector(7 downto 0) := X"CA"; -- Direct Inter Segment +Offset
-----------------------------------------------------------------------------
-- INT Instructions
-----------------------------------------------------------------------------
constant INT : std_logic_vector(7 downto 0) := X"CD"; -- type=second byte
constant INT3 : std_logic_vector(7 downto 0) := X"CC"; -- type=3
constant INTO : std_logic_vector(7 downto 0) := X"CE"; -- type=4
constant IRET : std_logic_vector(7 downto 0) := X"CF"; -- Interrupt Return
-----------------------------------------------------------------------------
-- String/Repeat Instructions
-----------------------------------------------------------------------------
constant MOVSB : std_logic_vector(7 downto 0) := X"A4";
constant MOVSW : std_logic_vector(7 downto 0) := X"A5";
constant CMPSB : std_logic_vector(7 downto 0) := X"A6";
constant CMPSW : std_logic_vector(7 downto 0) := X"A7";
constant SCASB : std_logic_vector(7 downto 0) := X"AE";
constant SCASW : std_logic_vector(7 downto 0) := X"AF";
constant LODSB : std_logic_vector(7 downto 0) := X"AC";
constant LODSW : std_logic_vector(7 downto 0) := X"AD";
constant STOSB : std_logic_vector(7 downto 0) := X"AA";
constant STOSW : std_logic_vector(7 downto 0) := X"AB";
constant REPNE : std_logic_vector(7 downto 0) := X"F2"; -- stop if zf=1
constant REPE : std_logic_vector(7 downto 0) := X"F3"; -- stop if zf/=1
-----------------------------------------------------------------------------
-- Shift/Rotate Instructions
-- Operation define in MODRM REG bits
-- Note REG=110 is undefined
-----------------------------------------------------------------------------
constant SHFTROT0 : std_logic_vector(7 downto 0) := X"D0";
constant SHFTROT1 : std_logic_vector(7 downto 0) := X"D1";
constant SHFTROT2 : std_logic_vector(7 downto 0) := X"D2";
constant SHFTROT3 : std_logic_vector(7 downto 0) := X"D3";
-----------------------------------------------------------------------------
-- FF/FE Instructions. Use regfiled to decode operation
-- INC reg=000 (FF/FE)
-- DEC reg=001 (FF/FE)
-- CALL reg=010 (FF) Indirect within segment
-- CALL reg=011 (FF) Indirect Intersegment
-- JMP reg=100 (FF) Indirect within segment
-- JMP reg=101 (FF) Indirect Intersegment
-- PUSH reg=110 (FF)
-----------------------------------------------------------------------------
constant FEINSTR : std_logic_vector(7 downto 0) := X"FE";
constant FFINSTR : std_logic_vector(7 downto 0) := X"FF";
END cpu86instr;
| gpl-2.0 | 758a146d6cf34890e954566718c6811b | 0.470498 | 3.763334 | false | false | false | false |
CamelClarkson/MIPS | Register_File/sources/32x32_Mem.vhd | 2 | 10,087 | ----------------------------------------------------------------------------------
--MIPS Register File Test Bench
--By: Kevin Mottler
--Camel Clarkson 32 Bit MIPS Design Group
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--Declares the entity Reg_Depth. This is the 32-bit memory/depth at each address of the register
entity Reg_Depth is
Port (
i_Clk : in std_logic; --Input clock
i_Data : in std_logic_vector(31 downto 0); --Input Data
i_Rst : in std_logic; --Input Reset (Active High)
i_w_en : in std_logic; --Read/Write enable
i_rA_sel : in std_logic; --Select bit for tri state buffer for data A
i_rB_sel : in std_logic; --Select bit for tri state buffer for Data B
o_Data_A : out std_logic_vector(31 downto 0);
o_Data_B : out std_logic_vector(31 downto 0)
);
end Reg_Depth;
architecture structural of Reg_Depth is
--Declares the RFC component
component RFC is
Port (
iClk : in std_logic;
i_Rst : in std_logic;
w_sel : in std_logic;
i_data : in std_logic;
R_sel_A : in std_logic;
R_sel_B : in std_logic;
A : out std_logic;
B : out std_logic
);
end component;
begin
--Instatiates 32 RFCs that control the memory. 32 of them are instatiated because there are 32-bits at each depth
--because they are 1 bit each. 32 bit values are routed to i_data, R_sel_A, and R_sel_B to select which data is outputted,
--or written to.
Inst_RFC31: RFC
port map(
iClk => i_Clk, --Input Clock
i_Rst => i_Rst, --asynchronous reset
w_sel => i_w_en, --Read/Write enable
i_data => i_Data(31),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(31),
B => o_Data_B(31)
);
Inst_RFC30: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(30),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(30),
B => o_Data_B(30)
);
Inst_RFC29: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(29),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(29),
B => o_Data_B(29)
);
Inst_RFC28: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(28),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(28),
B => o_Data_B(28)
);
Inst_RFC27: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(27),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(27),
B => o_Data_B(27)
);
Inst_RFC26: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(26),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(26),
B => o_Data_B(26)
);
Inst_RFC25: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(25),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(25),
B => o_Data_B(25)
);
Inst_RFC24: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(24),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(24),
B => o_Data_B(24)
);
Inst_RFC23: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(23),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(23),
B => o_Data_B(23)
);
Inst_RFC22: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(22),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(22),
B => o_Data_B(22)
);
Inst_RFC21: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(21),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(21),
B => o_Data_B(21)
);
Inst_RFC20: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(20),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(20),
B => o_Data_B(20)
);
Inst_RFC19: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(19),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(19),
B => o_Data_B(19)
);
Inst_RFC18: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(18),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(18),
B => o_Data_B(18)
);
Inst_RFC17: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(17),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(17),
B => o_Data_B(17)
);
Inst_RFC16: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(16),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(16),
B => o_Data_B(16)
);
Inst_RFC15: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(15),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(15),
B => o_Data_B(15)
);
Inst_RFC14: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(14),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(14),
B => o_Data_B(14)
);
Inst_RFC13: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(13),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(13),
B => o_Data_B(13)
);
Inst_RFC12: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(12),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(12),
B => o_Data_B(12)
);
Inst_RFC11: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(11),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(11),
B => o_Data_B(11)
);
Inst_RFC10: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(10),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(10),
B => o_Data_B(10)
);
Inst_RFC9: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(9),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(9),
B => o_Data_B(9)
);
Inst_RFC8: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(8),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(8),
B => o_Data_B(8)
);
Inst_RFC7: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(7),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(7),
B => o_Data_B(7)
);
Inst_RFC6: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(6),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(6),
B => o_Data_B(6)
);
Inst_RFC5: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(5),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(5),
B => o_Data_B(5)
);
Inst_RFC4: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(4),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(4),
B => o_Data_B(4)
);
Inst_RFC3: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(3),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(3),
B => o_Data_B(3)
);
Inst_RFC2: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(2),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(2),
B => o_Data_B(2)
);
Inst_RFC1: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(1),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(1),
B => o_Data_B(1)
);
Inst_RFC0: RFC
port map(
iClk => i_Clk,
i_Rst => i_Rst,
w_sel => i_w_en,
i_data => i_Data(0),
R_sel_A => i_rA_sel,
R_sel_B => i_rB_sel,
A => o_Data_A(0),
B => o_Data_B(0)
);
end structural;
| mit | 53945dffdad7aa6ac53f1af5dbe3deb7 | 0.391791 | 2.721802 | false | false | false | false |
nsauzede/cpu86 | papilio2/papilio1_tb.vhd | 1 | 12,907 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- TestBench --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.STD_LOGIC_UNSIGNED.all;
LIBRARY std;
USE std.TEXTIO.all;
USE work.utils.all;
entity papilio1_tb is
end papilio1_tb ;
ARCHITECTURE struct OF papilio1_tb IS
-- Architecture declarations
signal dind1_s : std_logic;
signal dind2_s : std_logic;
-- Internal signal declarations
SIGNAL CLOCK_40MHZ : std_logic := '0';
SIGNAL CLOCK_32MHZ : std_logic := '0';
SIGNAL CTS : std_logic;
SIGNAL resetn : std_logic;
SIGNAL TXD : std_logic;
SIGNAL cpuerror : std_logic;
SIGNAL rdn_s : std_logic; -- Active Low Read Pulse (CLK)
SIGNAL rdrf : std_logic;
SIGNAL rxenable : std_logic;
SIGNAL txcmd : std_logic;
SIGNAL txenable : std_logic;
SIGNAL udbus : Std_Logic_Vector(7 DOWNTO 0);
CONSTANT DIVIDER_c : std_logic_vector(7 downto 0):="01000001"; -- 65, baudrate divider 40MHz
SIGNAL divtx_s : std_logic_vector(3 downto 0);
SIGNAL divcnt_s : std_logic_vector(7 downto 0);
SIGNAL rxclk16_s : std_logic;
SIGNAL tdre_s : std_logic;
SIGNAL wrn_s : std_logic;
SIGNAL char_s : std_logic_vector(7 downto 0);
signal rx : STD_LOGIC;
signal tx : STD_LOGIC;
signal W1A : STD_LOGIC_VECTOR (15 downto 0);
signal W1B : STD_LOGIC_VECTOR (15 downto 0);
signal W2C : STD_LOGIC_VECTOR (15 downto 0);
signal clk : STD_LOGIC;
-- Component Declarations
COMPONENT papilio1_top
Port ( rx : in STD_LOGIC;
tx : out STD_LOGIC;
W1A : inout STD_LOGIC_VECTOR (15 downto 0);
W1B : inout STD_LOGIC_VECTOR (15 downto 0);
W2C : inout STD_LOGIC_VECTOR (15 downto 0);
clk : in STD_LOGIC);
END COMPONENT;
component Aaatop
Port (
CLK : in STD_LOGIC;
txd : inout std_logic;
rxd : in std_logic;
ARD_RESET : out STD_LOGIC;
DUO_SW1 : in STD_LOGIC;
sram_addr : out std_logic_vector(20 downto 0);
sram_data : inout std_logic_vector(7 downto 0);
sram_ce : out std_logic;
sram_we : out std_logic;
sram_oe : out std_logic;
Arduino : inout STD_LOGIC_VECTOR (53 downto 0)
);
end component;
COMPONENT uartrx
PORT (
clk : IN std_logic;
enable : IN std_logic;
rdn : IN std_logic;
resetn : IN std_logic;
rx : IN std_logic;
dbus : OUT std_logic_vector (7 DOWNTO 0);
ferror : OUT std_logic;
rdrf : OUT std_logic
);
END COMPONENT;
COMPONENT uarttx
PORT (
clk : in std_logic ;
enable : in std_logic ; -- 1 x bit_rate transmit clock enable
resetn : in std_logic ;
dbus : in std_logic_vector (7 downto 0); -- input to txshift register
tdre : out std_logic ;
wrn : in std_logic ;
tx : out std_logic);
END COMPONENT;
BEGIN
CLOCK_40MHZ <= not CLOCK_40MHZ after 12.5 ns; -- 40MHz
-- CLOCK_40MHZ <= not CLOCK_40MHZ after 25 ns; -- 20MHz
CLOCK_32MHZ <= not CLOCK_32MHZ after 15.625 ns; -- 32MHz
process
variable L : line;
procedure write_to_uart (char_in : IN character) is
begin
char_s <=to_std_logic_vector(char_in);
wait until rising_edge(CLOCK_40MHZ);
wrn_s <= '0';
wait until rising_edge(CLOCK_40MHZ);
wrn_s <= '1';
wait until rising_edge(CLOCK_40MHZ);
wait until rising_edge(tdre_s);
end;
begin
CTS <= '1';
resetn <= '0'; -- PIN3 on Drigmorn1 connected to PIN2
wait for 100 ns;
resetn <= '1';
wrn_s <= '1'; -- Active low write strobe to TX UART
char_s <= (others => '1');
wait for 25.1 ms; -- wait for > prompt before issuing commands
-- write_to_uart('R');
write_to_uart('H');
wait for 47 ms; -- wait for > prompt before issuing commands
write_to_uart('D'); -- Issue Fill Memory command
write_to_uart('M');
write_to_uart('0');
write_to_uart('1');
write_to_uart('0');
write_to_uart('0');
wait for 1 ms;
write_to_uart('0');
write_to_uart('1');
write_to_uart('2');
write_to_uart('4');
wait for 50 ms; -- wait for > prompt before issuing commands
wait;
end process;
------------------------------------------------------------------------------
-- 8 bits divider
-- Generate rxenable clock (16 x baudrate)
------------------------------------------------------------------------------
process (CLOCK_40MHZ,resetn) -- First divider
begin
if (resetn='0') then
divcnt_s <= (others => '0');
rxclk16_s <= '0'; -- Receive clock (x16, pulse)
elsif (rising_edge(CLOCK_40MHZ)) then
if divcnt_s=DIVIDER_c then
divcnt_s <= (others => '0');
rxclk16_s <= '1';
else
rxclk16_s <= '0';
divcnt_s <= divcnt_s + '1';
end if;
end if;
end process;
rxenable <= rxclk16_s;
------------------------------------------------------------------------------
-- divider by 16
-- rxclk16/16=txclk
------------------------------------------------------------------------------
process (CLOCK_40MHZ,resetn)
begin
if (resetn='0') then
divtx_s <= (others => '0');
elsif (rising_edge(CLOCK_40MHZ)) then
if rxclk16_s='1' then
divtx_s <= divtx_s + '1';
if divtx_s="0000" then
txenable <= '1';
end if;
else
txenable <= '0';
end if;
end if;
end process;
assert not ((NOW > 0 ns) and cpuerror='1') report "**** CPU Error flag asserted ****" severity error;
------------------------------------------------------------------------------
-- UART Monitor
-- Display string on console after 80 characters or when CR character is received
------------------------------------------------------------------------------
process (rdrf,resetn)
variable L : line;
variable i_v : integer;
begin
if resetn='0' then
i_v := 0; -- clear character counter
elsif (rising_edge(rdrf)) then -- possible, pulse is wide!
if i_v=0 then
write(L,string'("RD UART : "));
if (udbus/=X"0D" and udbus/=X"0A") then
write(L,std_to_char(udbus));
end if;
i_v := i_v+1;
elsif (i_v=80 or udbus=X"0D") then
writeline(output,L);
i_v:=0;
else
if (udbus/=X"0D" and udbus/=X"0A") then
write(L,std_to_char(udbus));
end if;
i_v := i_v+1;
end if;
end if;
end process;
process (CLOCK_40MHZ,resetn) -- First/Second delay
begin
if (resetn='0') then
dind1_s <= '0';
dind2_s <= '0';
elsif (rising_edge(CLOCK_40MHZ)) then
dind1_s <= rdrf;
dind2_s <= dind1_s;
end if;
end process;
rdn_s <= '0' when (dind1_s='1' and dind2_s='0') else '1';
------------------------------------------------------------------------------
-- Top Level CPU+RAM+UART
------------------------------------------------------------------------------
U_0 : Aaatop Port map(
CLK => clk,
txd => tx,
rxd => rx,
ARD_RESET => open,
DUO_SW1 => '0',
sram_addr => open,
sram_data => open,
sram_ce => open,
sram_we => open,
sram_oe => open,
Arduino => open
);
clk <= CLOCK_32MHZ;
TXD <= tx;
rx <= txcmd;
-- w1b(1) <= resetn;
-- CTS => CTS,
-- PIN3 => resetn,
-- RXD => txcmd,
--TXD => TXD,
-- LED1 => cpuerror,
------------------------------------------------------------------------------
-- TX Uart
------------------------------------------------------------------------------
U_1 : uarttx
port map (
clk => CLOCK_40MHZ,
enable => txenable,
resetn => resetn,
dbus => char_s,
tdre => tdre_s,
wrn => wrn_s,
tx => txcmd
);
------------------------------------------------------------------------------
-- RX Uart
------------------------------------------------------------------------------
U_2 : uartrx
PORT MAP (
clk => CLOCK_40MHZ,
enable => rxenable,
resetn => resetn,
dbus => udbus,
rdn => rdn_s,
rdrf => rdrf,
ferror => OPEN,
rx => TXD
);
END struct;
| gpl-2.0 | 5f79f8207e35027b728b6d0549ccc0ac | 0.383358 | 4.700291 | false | false | false | false |
andykarpov/radio-86rk-wxeda | src/keyboard/PS2Controller.vhd | 1 | 5,734 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity PS2Controller is
port (Reset : in STD_LOGIC;
Clock : in STD_LOGIC;
PS2Clock : inout STD_LOGIC;
PS2Data : inout STD_LOGIC;
Send : in STD_LOGIC;
Command : in STD_LOGIC_VECTOR(7 downto 0);
PS2Busy : out STD_LOGIC;
PS2Error : buffer STD_LOGIC;
DataReady : out STD_LOGIC;
DataByte : out STD_LOGIC_VECTOR(7 downto 0));
end PS2Controller;
architecture Behavioral of PS2Controller is
constant ClockFreq : natural := 50; -- MHz
constant Time100us : natural := 100 * ClockFreq;
constant Time20us : natural := 20 * ClockFreq;
constant DebounceDelay : natural := 16;
type StateType is (Idle, ReceiveData, InhibitComunication, RequestToSend, SendData, CheckAck, WaitRiseClock);
signal State : StateType;
signal BitsRead : natural range 0 to 10;
signal BitsSent : natural range 0 to 10;
signal Byte : STD_LOGIC_VECTOR(7 downto 0);
signal CountOnes : STD_LOGIC; -- One bit only to know if even or odd number of ones
signal DReady : STD_LOGIC;
signal PS2ClockPrevious : STD_LOGIC;
signal PS2ClockOut : STD_LOGIC;
signal PS2Clock_Z : STD_LOGIC;
signal PS2Clock_D : STD_LOGIC;
signal PS2DataOut : STD_LOGIC;
signal PS2Data_Z : STD_LOGIC;
signal PS2Data_D : STD_LOGIC;
signal TimeCounter : natural range 0 to Time100us;
begin
DebounceClock: entity work.Debouncer
generic map (Delay => DebounceDelay)
port map (Clock => Clock,
Reset => Reset,
Input => PS2Clock,
Output => PS2Clock_D);
DebounceData: entity work.Debouncer
generic map (Delay => DebounceDelay)
port map (Clock => Clock,
Reset => Reset,
Input => PS2Data,
Output => PS2Data_D);
PS2Clock <= PS2ClockOut when PS2Clock_Z <= '0' else 'Z';
PS2Data <= PS2DataOut when PS2Data_Z <= '0' else 'Z';
process(Reset, Clock)
begin
if Reset = '1' then
PS2Clock_Z <= '1';
PS2ClockOut <= '1';
PS2Data_Z <= '1';
PS2DataOut <= '1';
DataReady <= '0';
DReady <= '0';
DataByte <= (others => '0');
PS2Busy <= '0';
PS2Error <= '0';
BitsRead <= 0;
BitsSent <= 0;
CountOnes <= '0';
TimeCounter <= 0;
PS2ClockPrevious <= '1';
Byte <= x"FF";
State <= InhibitComunication;
elsif rising_edge(Clock) then
PS2ClockPrevious <= PS2Clock_D;
case State is
when Idle =>
DataReady <= '0';
DReady <= '0';
BitsRead <= 0;
PS2Error <= '0';
CountOnes <= '0';
if PS2Data_D = '0' then -- Start bit
PS2Busy <= '1';
State <= ReceiveData;
elsif Send = '1' then
Byte <= Command;
PS2Busy <= '1';
TimeCounter <= 0;
State <= InhibitComunication;
else
State <= Idle;
end if;
when ReceiveData =>
if PS2ClockPrevious = '1' and PS2Clock_D = '0' then -- falling edge
case BitsRead is
when 1 to 8 => -- 8 Data bits
Byte(BitsRead - 1) <= PS2Data_D;
if PS2Data_D = '1' then
CountOnes <= not CountOnes;
end if;
when 9 => -- Parity bit
case CountOnes is
when '0' =>
if PS2Data_D = '0' then
PS2Error <= '1'; -- Error when CountOnes is even (0)
else -- and parity bit is unasserted
PS2Error <= '0';
end if;
when others =>
if PS2Data_D = '1' then
PS2Error <= '1'; -- Error when CountOnes is odd (1)
else -- and parity bit is asserted
PS2Error <= '0';
end if;
end case;
when 10 => -- Stop bit
if PS2Error = '0' then
DataByte <= Byte;
DReady <= '1';
else
DReady <= '0';
end if;
State <= WaitRiseClock;
when others => null;
end case;
BitsRead <= BitsRead + 1;
end if;
when InhibitComunication =>
PS2Clock_Z <= '0';
PS2ClockOut <= '0';
if TimeCounter = Time100us then
TimeCounter <= 0;
State <= RequestToSend;
else
TimeCounter <= TimeCounter + 1;
end if;
when RequestToSend =>
PS2Clock_Z <= '1';
PS2Data_Z <= '0';
PS2DataOut <= '0'; -- Sets the start bit, valid when PS2Clock is high
if TimeCounter = Time20us then
TimeCounter <= 0;
PS2ClockOut <= '1';
BitsSent <= 1;
State <= SendData;
else
TimeCounter <= TimeCounter + 1;
end if;
when SendData =>
PS2Clock_Z <= '1';
if PS2ClockPrevious = '1' and PS2Clock_D = '0' then -- falling edge
case BitsSent is
when 1 to 8 => -- 8 Data bits
if Byte(BitsSent - 1) = '0' then
PS2DataOut <= '0';
else
CountOnes <= not CountOnes;
PS2DataOut <= '1';
end if;
when 9 => -- Parity bit
if CountOnes = '0' then
PS2DataOut <= '1';
else
PS2DataOut <= '0';
end if;
when 10 => -- Stop bit
PS2DataOut <= '1';
State <= CheckAck;
when others => null;
end case;
BitsSent <= BitsSent + 1;
end if;
when CheckAck =>
PS2Data_Z <= '1';
if PS2ClockPrevious = '1' and PS2Clock_D = '0' then
if PS2Data_D = '1' then -- no Acknowledge received
PS2Error <= '1';
end if;
State <= WaitRiseClock;
end if;
when WaitRiseClock =>
if PS2ClockPrevious = '0' and PS2Clock_D = '1' then
PS2Busy <= '0';
DataReady <= DReady;
State <= Idle;
end if;
when others => null;
end case;
end if;
end process;
end Behavioral; | bsd-2-clause | 4f92a81268cbaf7d3c29b65e53524fe7 | 0.55354 | 3.20873 | false | false | false | false |
CamelClarkson/MIPS | Register_File/sources/Register_File.vhd | 2 | 2,893 | ----------------------------------------------------------------------------------
--MIPS Register File Test Bench
--By: Kevin Mottler
--Camel Clarkson 32 Bit MIPS Design Group
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--Top Level Register_File entity
entity Register_File is
Port (
i_Clk : in std_logic;
i_Rst : in std_logic;
i_regwrite : in std_logic;
i_rt : in std_logic_vector(4 downto 0);
i_rs : in std_logic_vector(4 downto 0);
i_rd : in std_logic_vector(4 downto 0);
i_rd_data : in std_logic_vector(31 downto 0);
o_rt_data : out std_logic_vector(31 downto 0);
o_rs_data : out std_logic_vector(31 downto 0)
);
end Register_File;
architecture Structural of Register_File is
--Creates signals for addresses for the Decoder/Muxiplier
signal s_rd_addr : std_logic_vector(31 downto 0);
signal s_rt_addr : std_logic_vector(31 downto 0);
signal s_rs_addr : std_logic_vector(31 downto 0);
--Declares 32 registers with a 32 bit depth
component Register32X32 is
Port(
i_Clk : in std_logic;
i_Data : in std_logic_vector(31 downto 0);
i_Rst : in std_logic;
i_w_en : in std_logic_vector(31 downto 0);
i_rA_sel : in std_logic_vector(31 downto 0);
i_rB_sel : in std_logic_vector(31 downto 0);
o_Data_A : out std_logic_vector(31 downto 0);
o_Data_B : out std_logic_vector(31 downto 0)
);
end component;
component Decoder is
Port (
i_w_Addr : in std_logic_vector(4 downto 0);
o_w_Addr : out std_logic_vector(31 downto 0)
);
end component;
component W_Decoder is
Port (
i_w_Addr : in std_logic_vector(5 downto 0);
o_w_Addr : out std_logic_vector(31 downto 0)
);
end component;
begin
--Decodes the 6 bit write address to a 32 bit binary value to enable writing to a register
Inst_Decoder_W: W_Decoder
port map(
i_w_Addr => i_regwrite & i_rd,
o_w_Addr => s_rd_Addr
);
--Decodes the 5 bit rt address to a 32 bit binary value used to enable the i_rA_sel input of the Register32X32 instatiation
Inst_Decoder_rt: Decoder
port map(
i_w_Addr => i_rt,
o_w_Addr => s_rt_addr
);
--Decodes the 5 bit rd address to a 32 bit binary value used to enable the i_rB_sel input of the Register32X32 instatiation
Inst_Decoder_rd: Decoder
port map(
i_w_Addr => i_rs,
o_w_Addr => s_rs_addr
);
--Instatiates the Register32X32 component, a 32 address register, 32 bit depth memory
Inst_Register32X32: Register32X32
port map(
i_Clk => i_Clk,
i_Data => i_rd_data,
i_Rst => i_Rst,
i_w_en => s_rd_Addr,
i_rA_sel => s_rt_addr,
i_rB_sel => s_rs_addr,
o_Data_A => o_rt_Data,
o_Data_B => o_rs_Data
);
end Structural;
| mit | 515261da90f930223a4c3fbfdd178aa3 | 0.590736 | 3.21802 | false | false | false | false |
CamelClarkson/MIPS | SLT_MUX.vhd | 2 | 3,779 | ----------------------------------------------------------------------------------
-- Clarkson University
-- EE466/566 Computer Architecture Fall 2016
-- Project Name: Project1, 4-Bit ALU Design
--
-- Student Name : Zhiliu Yang
-- Student ID : 0754659
-- Major : Electrical and Computer Engineering
-- Email : [email protected]
-- Instructor Name: Dr. Chen Liu
-- Date : 09-25-2016
--
-- Create Date: 09/25/2016 04:25:05 PM
-- Design Name:
-- Module Name: ALU4Bit - ALU_Func
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SLT_MUX is
Port ( F_pre : in STD_LOGIC_VECTOR (31 downto 0); -- before merge in the slt
P3 : in STD_LOGIC;
P2 : in STD_LOGIC;
P1 : in STD_LOGIC;
P0 : in STD_LOGIC;
Overflow : in STD_LOGIC;
SltOpVal : out STD_LOGIC;
F : out STD_LOGIC_VECTOR (31 downto 0)); --after merge in the slt
end SLT_MUX;
architecture SLTM_Func of SLT_MUX is
signal SltOpVal_wire : STD_LOGIC; -- set less than operation valid, valid is 1
signal Set : STD_LOGIC; -- set when the sign of the F_pre xor overflow is 1
--Because 0 in 32bit is 0000_0000_0000_0000_0000_0000_0000_0000, sign bit is 0.
--When A = B, result of subject is 0, will not Set.
begin
SltOpVal_wire <= (not P3) and P2 and P1 and P0;
SltOpVal <= SltOpVal_wire;
Set <= F_pre(31) xor Overflow; -- operand A less than operand B
F(31) <= (not SltOpVal_wire) and F_pre(31);
F(30) <= (not SltOpVal_wire) and F_pre(30);
F(29) <= (not SltOpVal_wire) and F_pre(29);
F(28) <= (not SltOpVal_wire) and F_pre(28);
F(27) <= (not SltOpVal_wire) and F_pre(27);
F(26) <= (not SltOpVal_wire) and F_pre(26);
F(25) <= (not SltOpVal_wire) and F_pre(25);
F(24) <= (not SltOpVal_wire) and F_pre(24);
F(23) <= (not SltOpVal_wire) and F_pre(23);
F(22) <= (not SltOpVal_wire) and F_pre(22);
F(21) <= (not SltOpVal_wire) and F_pre(21);
F(20) <= (not SltOpVal_wire) and F_pre(20);
F(19) <= (not SltOpVal_wire) and F_pre(19);
F(18) <= (not SltOpVal_wire) and F_pre(18);
F(17) <= (not SltOpVal_wire) and F_pre(17);
F(16) <= (not SltOpVal_wire) and F_pre(16);
F(15) <= (not SltOpVal_wire) and F_pre(15);
F(14) <= (not SltOpVal_wire) and F_pre(14);
F(13) <= (not SltOpVal_wire) and F_pre(13);
F(12) <= (not SltOpVal_wire) and F_pre(12);
F(11) <= (not SltOpVal_wire) and F_pre(11);
F(10) <= (not SltOpVal_wire) and F_pre(10);
F(9) <= (not SltOpVal_wire) and F_pre(9);
F(8) <= (not SltOpVal_wire) and F_pre(8);
F(7) <= (not SltOpVal_wire) and F_pre(7);
F(6) <= (not SltOpVal_wire) and F_pre(6);
F(5) <= (not SltOpVal_wire) and F_pre(5);
F(4) <= (not SltOpVal_wire) and F_pre(4);
F(3) <= (not SltOpVal_wire) and F_pre(3);
F(2) <= (not SltOpVal_wire) and F_pre(2);
F(1) <= (not SltOpVal_wire) and F_pre(1);
F(0) <= (SltOpVal_wire and Set) or ((not SltOpVal_wire) and F_pre(0));
end SLTM_Func;
| mit | dcd3786c5c03eb1fd50a9edb2c5c70ab | 0.54353 | 3.120562 | false | false | false | false |
os-cillation/easyfpga-sdk-java | templates/templates/wishbone_slave_template.vhd | 1 | 3,782 | -- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
--===========================================================================--
-- Type and component definition package
--===========================================================================--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.constants.all;
use work.interfaces.all;
package %wbs_package_name is
type %wbs_reg_type is record
%wbs_register_typedef
end record;
component %wbs_component_name
port (
-- register outputs
%register_output_definitions
-- wishbone interface
wbs_in : in wbs_in_type;
wbs_out : out wbs_out_type
);
end component;
end package;
--===========================================================================--
-- Entity
--===========================================================================--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.interfaces.all;
use work.constants.all;
use work.%wbs_package_name.all;
-------------------------------------------------------------------------------
entity %wbs_component_name is
-------------------------------------------------------------------------------
port (
-- register outputs
%register_output_definitions
-- wishbone interface
wbs_in : in wbs_in_type;
wbs_out : out wbs_out_type
);
end %wbs_component_name;
-------------------------------------------------------------------------------
architecture behavioral of %wbs_component_name is
-------------------------------------------------------------------------------
----------------------------------------------
-- register addresses
----------------------------------------------
%register_address_constants
----------------------------------------------
-- signals
----------------------------------------------
signal reg_out_s, reg_in_s : %wbs_reg_type;
%signal_definitions
begin
-------------------------------------------------------------------------------
-- Concurrent
-------------------------------------------------------------------------------
-- register address decoder/comparator
%address_comparators
-- register enable signals
%register_enables
-- acknowledge output
wbs_out.ack <= wbs_in.stb;
-- register inputs always get data from wbs_in
%register_inputs
-- register output -> wbs_out via demultiplexer
%register_out_demux
-- register outputs -> non-wishbone outputs
%register_outputs
-------------------------------------------------------------------------------
REGISTERS : process(wbs_in.clk)
-------------------------------------------------------------------------------
begin
-- everything sync to clk
if (rising_edge(wbs_in.clk)) then
-- reset all registers
if (wbs_in.rst = '1') then
%register_reset_assignments
%register_store_conditions
-- hold
else
reg_out_s <= reg_out_s;
end if;
end if;
end process REGISTERS;
end behavioral;
| gpl-3.0 | 221925dcd4dd961cfef2ff1731008123 | 0.468006 | 5.209366 | false | false | false | false |
kdgwill/VHDL_Verilog_Encryptions_And_Ciphers | VHDL_RC5/Key_Generation/rc5_key_timesim.vhd | 1 | 17,035 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.20131013
-- \ \ Application: netgen
-- / / Filename: rc5_key_timesim.vhd
-- /___/ /\ Timestamp: Tue Mar 17 11:00:30 2015
-- \ \ / \
-- \___\/\___\
--
-- Command : -intstyle ise -s 4 -pcf rc5_key.pcf -rpw 100 -tpw 0 -ar Structure -tm rc5_key -insert_pp_buffers true -w -dir netgen/par -ofmt vhdl -sim rc5_key.ncd rc5_key_timesim.vhd
-- Device : 3s250eft256-4 (PRODUCTION 1.27 2013-10-13)
-- Input file : rc5_key.ncd
-- Output file : C:\SkyDrive\School\Polytechnic\EL6463_AdvancedHardwareDesign\Labs\Lab5\rc5_key_expansion\netgen\par\rc5_key_timesim.vhd
-- # of Entities : 1
-- Design Name : rc5_key
-- Xilinx : C:\Xilinx\14.7\ISE_DS\ISE\
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity rc5_key is
port (
clk : in STD_LOGIC := 'X';
clr : in STD_LOGIC := 'X';
key_vld : in STD_LOGIC := 'X';
key_rdy : out STD_LOGIC;
key : in STD_LOGIC_VECTOR ( 127 downto 0 )
);
end rc5_key;
architecture Structure of rc5_key is
signal clr_IBUF_96 : STD_LOGIC;
signal key_vld_IBUF_97 : STD_LOGIC;
signal clk_BUFGP : STD_LOGIC;
signal state_cmp_eq0001_0 : STD_LOGIC;
signal state_FSM_FFd2_109 : STD_LOGIC;
signal state_FSM_FFd2_In16_O : STD_LOGIC;
signal state_FSM_FFd2_In40_0 : STD_LOGIC;
signal state_FSM_FFd2_In4_0 : STD_LOGIC;
signal state_FSM_FFd1_113 : STD_LOGIC;
signal clk_INBUF : STD_LOGIC;
signal key_rdy_O : STD_LOGIC;
signal clr_INBUF : STD_LOGIC;
signal key_vld_INBUF : STD_LOGIC;
signal clk_BUFGP_BUFG_S_INVNOT : STD_LOGIC;
signal clk_BUFGP_BUFG_I0_INV : STD_LOGIC;
signal r_cnt_4_FFX_RST : STD_LOGIC;
signal r_cnt_4_DXMUX_175 : STD_LOGIC;
signal Mcount_r_cnt_cy_3_pack_2 : STD_LOGIC;
signal r_cnt_4_CLKINV_157 : STD_LOGIC;
signal r_cnt_4_CEINV_156 : STD_LOGIC;
signal r_cnt_3_DXMUX_221 : STD_LOGIC;
signal r_cnt_3_DYMUX_206 : STD_LOGIC;
signal r_cnt_3_SRINVNOT : STD_LOGIC;
signal r_cnt_3_CLKINV_196 : STD_LOGIC;
signal r_cnt_3_CEINV_195 : STD_LOGIC;
signal r_cnt_6_DXMUX_267 : STD_LOGIC;
signal r_cnt_6_DYMUX_252 : STD_LOGIC;
signal r_cnt_6_SRINVNOT : STD_LOGIC;
signal r_cnt_6_CLKINV_242 : STD_LOGIC;
signal r_cnt_6_CEINV_241 : STD_LOGIC;
signal state_FSM_FFd2_DXMUX_313 : STD_LOGIC;
signal state_FSM_FFd2_In : STD_LOGIC;
signal state_FSM_FFd2_DYMUX_299 : STD_LOGIC;
signal state_FSM_FFd2_In16_O_pack_3 : STD_LOGIC;
signal state_FSM_FFd2_SRINVNOT : STD_LOGIC;
signal state_FSM_FFd2_CLKINV_289 : STD_LOGIC;
signal state_cmp_eq0001 : STD_LOGIC;
signal state_FSM_FFd2_In40_332 : STD_LOGIC;
signal r_cnt_1_DXMUX_385 : STD_LOGIC;
signal r_cnt_1_DYMUX_368 : STD_LOGIC;
signal state_FSM_FFd2_In4_365 : STD_LOGIC;
signal r_cnt_1_SRINVNOT : STD_LOGIC;
signal r_cnt_1_CLKINV_357 : STD_LOGIC;
signal r_cnt_1_CEINV_356 : STD_LOGIC;
signal key_rdy_OBUF_402 : STD_LOGIC;
signal GND : STD_LOGIC;
signal VCC : STD_LOGIC;
signal r_cnt : STD_LOGIC_VECTOR ( 6 downto 0 );
signal Mcount_r_cnt_cy : STD_LOGIC_VECTOR ( 3 downto 3 );
signal Result : STD_LOGIC_VECTOR ( 6 downto 1 );
begin
clk_BUFGP_IBUFG : X_BUF
generic map(
LOC => "IPAD21",
PATHPULSE => 638 ps
)
port map (
I => clk,
O => clk_INBUF
);
key_rdy_OBUF : X_OBUF
generic map(
LOC => "PAD39"
)
port map (
I => key_rdy_O,
O => key_rdy
);
clr_IBUF : X_BUF
generic map(
LOC => "PAD43",
PATHPULSE => 638 ps
)
port map (
I => clr,
O => clr_INBUF
);
key_vld_IBUF : X_BUF
generic map(
LOC => "PAD42",
PATHPULSE => 638 ps
)
port map (
I => key_vld,
O => key_vld_INBUF
);
clk_BUFGP_BUFG : X_BUFGMUX
generic map(
LOC => "BUFGMUX_X2Y10"
)
port map (
I0 => clk_BUFGP_BUFG_I0_INV,
I1 => GND,
S => clk_BUFGP_BUFG_S_INVNOT,
O => clk_BUFGP
);
clk_BUFGP_BUFG_SINV : X_INV
generic map(
LOC => "BUFGMUX_X2Y10",
PATHPULSE => 638 ps
)
port map (
I => '1',
O => clk_BUFGP_BUFG_S_INVNOT
);
clk_BUFGP_BUFG_I0_USED : X_BUF
generic map(
LOC => "BUFGMUX_X2Y10",
PATHPULSE => 638 ps
)
port map (
I => clk_INBUF,
O => clk_BUFGP_BUFG_I0_INV
);
r_cnt_4_FFX_RSTOR : X_INV
generic map(
LOC => "SLICE_X40Y65",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_96,
O => r_cnt_4_FFX_RST
);
r_cnt_4 : X_FF
generic map(
LOC => "SLICE_X40Y65",
INIT => '0'
)
port map (
I => r_cnt_4_DXMUX_175,
CE => r_cnt_4_CEINV_156,
CLK => r_cnt_4_CLKINV_157,
SET => GND,
RST => r_cnt_4_FFX_RST,
O => r_cnt(4)
);
r_cnt_4_DXMUX : X_BUF
generic map(
LOC => "SLICE_X40Y65",
PATHPULSE => 638 ps
)
port map (
I => Result(4),
O => r_cnt_4_DXMUX_175
);
r_cnt_4_YUSED : X_BUF
generic map(
LOC => "SLICE_X40Y65",
PATHPULSE => 638 ps
)
port map (
I => Mcount_r_cnt_cy_3_pack_2,
O => Mcount_r_cnt_cy(3)
);
r_cnt_4_CLKINV : X_BUF
generic map(
LOC => "SLICE_X40Y65",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => r_cnt_4_CLKINV_157
);
r_cnt_4_CEINV : X_BUF
generic map(
LOC => "SLICE_X40Y65",
PATHPULSE => 638 ps
)
port map (
I => state_cmp_eq0001_0,
O => r_cnt_4_CEINV_156
);
Mcount_r_cnt_xor_4_11 : X_LUT4
generic map(
INIT => X"3C3C",
LOC => "SLICE_X40Y65"
)
port map (
ADR0 => VCC,
ADR1 => r_cnt(4),
ADR2 => Mcount_r_cnt_cy(3),
ADR3 => VCC,
O => Result(4)
);
r_cnt_3_DXMUX : X_BUF
generic map(
LOC => "SLICE_X41Y67",
PATHPULSE => 638 ps
)
port map (
I => Result(3),
O => r_cnt_3_DXMUX_221
);
r_cnt_3_DYMUX : X_BUF
generic map(
LOC => "SLICE_X41Y67",
PATHPULSE => 638 ps
)
port map (
I => Result(2),
O => r_cnt_3_DYMUX_206
);
r_cnt_3_SRINV : X_INV
generic map(
LOC => "SLICE_X41Y67",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_96,
O => r_cnt_3_SRINVNOT
);
r_cnt_3_CLKINV : X_BUF
generic map(
LOC => "SLICE_X41Y67",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => r_cnt_3_CLKINV_196
);
r_cnt_3_CEINV : X_BUF
generic map(
LOC => "SLICE_X41Y67",
PATHPULSE => 638 ps
)
port map (
I => state_cmp_eq0001_0,
O => r_cnt_3_CEINV_195
);
Mcount_r_cnt_xor_5_11 : X_LUT4
generic map(
INIT => X"3CF0",
LOC => "SLICE_X41Y64"
)
port map (
ADR0 => VCC,
ADR1 => Mcount_r_cnt_cy(3),
ADR2 => r_cnt(5),
ADR3 => r_cnt(4),
O => Result(5)
);
r_cnt_6_DXMUX : X_BUF
generic map(
LOC => "SLICE_X41Y64",
PATHPULSE => 638 ps
)
port map (
I => Result(6),
O => r_cnt_6_DXMUX_267
);
r_cnt_6_DYMUX : X_BUF
generic map(
LOC => "SLICE_X41Y64",
PATHPULSE => 638 ps
)
port map (
I => Result(5),
O => r_cnt_6_DYMUX_252
);
r_cnt_6_SRINV : X_INV
generic map(
LOC => "SLICE_X41Y64",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_96,
O => r_cnt_6_SRINVNOT
);
r_cnt_6_CLKINV : X_BUF
generic map(
LOC => "SLICE_X41Y64",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => r_cnt_6_CLKINV_242
);
r_cnt_6_CEINV : X_BUF
generic map(
LOC => "SLICE_X41Y64",
PATHPULSE => 638 ps
)
port map (
I => state_cmp_eq0001_0,
O => r_cnt_6_CEINV_241
);
state_FSM_FFd2_DXMUX : X_BUF
generic map(
LOC => "SLICE_X40Y67",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd2_In,
O => state_FSM_FFd2_DXMUX_313
);
state_FSM_FFd2_DYMUX : X_BUF
generic map(
LOC => "SLICE_X40Y67",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd2_109,
O => state_FSM_FFd2_DYMUX_299
);
state_FSM_FFd2_YUSED : X_BUF
generic map(
LOC => "SLICE_X40Y67",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd2_In16_O_pack_3,
O => state_FSM_FFd2_In16_O
);
state_FSM_FFd2_SRINV : X_INV
generic map(
LOC => "SLICE_X40Y67",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_96,
O => state_FSM_FFd2_SRINVNOT
);
state_FSM_FFd2_CLKINV : X_BUF
generic map(
LOC => "SLICE_X40Y67",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => state_FSM_FFd2_CLKINV_289
);
state_cmp_eq0001_XUSED : X_BUF
generic map(
LOC => "SLICE_X40Y64",
PATHPULSE => 638 ps
)
port map (
I => state_cmp_eq0001,
O => state_cmp_eq0001_0
);
state_cmp_eq0001_YUSED : X_BUF
generic map(
LOC => "SLICE_X40Y64",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd2_In40_332,
O => state_FSM_FFd2_In40_0
);
r_cnt_1_DXMUX : X_BUF
generic map(
LOC => "SLICE_X41Y65",
PATHPULSE => 638 ps
)
port map (
I => Result(1),
O => r_cnt_1_DXMUX_385
);
r_cnt_1_DYMUX : X_INV
generic map(
LOC => "SLICE_X41Y65",
PATHPULSE => 638 ps
)
port map (
I => r_cnt(0),
O => r_cnt_1_DYMUX_368
);
r_cnt_1_YUSED : X_BUF
generic map(
LOC => "SLICE_X41Y65",
PATHPULSE => 638 ps
)
port map (
I => state_FSM_FFd2_In4_365,
O => state_FSM_FFd2_In4_0
);
r_cnt_1_SRINV : X_INV
generic map(
LOC => "SLICE_X41Y65",
PATHPULSE => 638 ps
)
port map (
I => clr_IBUF_96,
O => r_cnt_1_SRINVNOT
);
r_cnt_1_CLKINV : X_BUF
generic map(
LOC => "SLICE_X41Y65",
PATHPULSE => 638 ps
)
port map (
I => clk_BUFGP,
O => r_cnt_1_CLKINV_357
);
r_cnt_1_CEINV : X_BUF
generic map(
LOC => "SLICE_X41Y65",
PATHPULSE => 638 ps
)
port map (
I => state_cmp_eq0001_0,
O => r_cnt_1_CEINV_356
);
r_cnt_1 : X_FF
generic map(
LOC => "SLICE_X41Y65",
INIT => '0'
)
port map (
I => r_cnt_1_DXMUX_385,
CE => r_cnt_1_CEINV_356,
CLK => r_cnt_1_CLKINV_357,
SET => GND,
RST => r_cnt_1_SRINVNOT,
O => r_cnt(1)
);
state_FSM_FFd2 : X_FF
generic map(
LOC => "SLICE_X40Y67",
INIT => '0'
)
port map (
I => state_FSM_FFd2_DXMUX_313,
CE => VCC,
CLK => state_FSM_FFd2_CLKINV_289,
SET => GND,
RST => state_FSM_FFd2_SRINVNOT,
O => state_FSM_FFd2_109
);
clr_IFF_IMUX : X_BUF
generic map(
LOC => "PAD43",
PATHPULSE => 638 ps
)
port map (
I => clr_INBUF,
O => clr_IBUF_96
);
key_vld_IFF_IMUX : X_BUF
generic map(
LOC => "PAD42",
PATHPULSE => 638 ps
)
port map (
I => key_vld_INBUF,
O => key_vld_IBUF_97
);
Mcount_r_cnt_cy_3_11 : X_LUT4
generic map(
INIT => X"8000",
LOC => "SLICE_X40Y65"
)
port map (
ADR0 => r_cnt(3),
ADR1 => r_cnt(2),
ADR2 => r_cnt(0),
ADR3 => r_cnt(1),
O => Mcount_r_cnt_cy_3_pack_2
);
Mcount_r_cnt_xor_2_11 : X_LUT4
generic map(
INIT => X"5AAA",
LOC => "SLICE_X41Y67"
)
port map (
ADR0 => r_cnt(2),
ADR1 => VCC,
ADR2 => r_cnt(1),
ADR3 => r_cnt(0),
O => Result(2)
);
r_cnt_2 : X_FF
generic map(
LOC => "SLICE_X41Y67",
INIT => '0'
)
port map (
I => r_cnt_3_DYMUX_206,
CE => r_cnt_3_CEINV_195,
CLK => r_cnt_3_CLKINV_196,
SET => GND,
RST => r_cnt_3_SRINVNOT,
O => r_cnt(2)
);
Mcount_r_cnt_xor_3_11 : X_LUT4
generic map(
INIT => X"7F80",
LOC => "SLICE_X41Y67"
)
port map (
ADR0 => r_cnt(1),
ADR1 => r_cnt(0),
ADR2 => r_cnt(2),
ADR3 => r_cnt(3),
O => Result(3)
);
r_cnt_3 : X_FF
generic map(
LOC => "SLICE_X41Y67",
INIT => '0'
)
port map (
I => r_cnt_3_DXMUX_221,
CE => r_cnt_3_CEINV_195,
CLK => r_cnt_3_CLKINV_196,
SET => GND,
RST => r_cnt_3_SRINVNOT,
O => r_cnt(3)
);
r_cnt_5 : X_FF
generic map(
LOC => "SLICE_X41Y64",
INIT => '0'
)
port map (
I => r_cnt_6_DYMUX_252,
CE => r_cnt_6_CEINV_241,
CLK => r_cnt_6_CLKINV_242,
SET => GND,
RST => r_cnt_6_SRINVNOT,
O => r_cnt(5)
);
Mcount_r_cnt_xor_6_11 : X_LUT4
generic map(
INIT => X"6AAA",
LOC => "SLICE_X41Y64"
)
port map (
ADR0 => r_cnt(6),
ADR1 => Mcount_r_cnt_cy(3),
ADR2 => r_cnt(5),
ADR3 => r_cnt(4),
O => Result(6)
);
r_cnt_6 : X_FF
generic map(
LOC => "SLICE_X41Y64",
INIT => '0'
)
port map (
I => r_cnt_6_DXMUX_267,
CE => r_cnt_6_CEINV_241,
CLK => r_cnt_6_CLKINV_242,
SET => GND,
RST => r_cnt_6_SRINVNOT,
O => r_cnt(6)
);
state_FSM_FFd2_In16 : X_LUT4
generic map(
INIT => X"FF7F",
LOC => "SLICE_X40Y67"
)
port map (
ADR0 => r_cnt(3),
ADR1 => r_cnt(2),
ADR2 => r_cnt(6),
ADR3 => r_cnt(1),
O => state_FSM_FFd2_In16_O_pack_3
);
state_FSM_FFd1 : X_FF
generic map(
LOC => "SLICE_X40Y67",
INIT => '0'
)
port map (
I => state_FSM_FFd2_DYMUX_299,
CE => VCC,
CLK => state_FSM_FFd2_CLKINV_289,
SET => GND,
RST => state_FSM_FFd2_SRINVNOT,
O => state_FSM_FFd1_113
);
state_FSM_FFd2_In43 : X_LUT4
generic map(
INIT => X"FECC",
LOC => "SLICE_X40Y67"
)
port map (
ADR0 => state_FSM_FFd2_In4_0,
ADR1 => state_FSM_FFd2_In40_0,
ADR2 => state_FSM_FFd2_In16_O,
ADR3 => state_FSM_FFd2_109,
O => state_FSM_FFd2_In
);
state_FSM_FFd2_In40 : X_LUT4
generic map(
INIT => X"0F0C",
LOC => "SLICE_X40Y64"
)
port map (
ADR0 => VCC,
ADR1 => state_FSM_FFd2_109,
ADR2 => state_FSM_FFd1_113,
ADR3 => key_vld_IBUF_97,
O => state_FSM_FFd2_In40_332
);
state_FSM_Out01 : X_LUT4
generic map(
INIT => X"CC00",
LOC => "SLICE_X40Y64"
)
port map (
ADR0 => VCC,
ADR1 => state_FSM_FFd2_109,
ADR2 => VCC,
ADR3 => state_FSM_FFd1_113,
O => state_cmp_eq0001
);
state_FSM_FFd2_In4 : X_LUT4
generic map(
INIT => X"FFF3",
LOC => "SLICE_X41Y65"
)
port map (
ADR0 => VCC,
ADR1 => r_cnt(0),
ADR2 => r_cnt(5),
ADR3 => r_cnt(4),
O => state_FSM_FFd2_In4_365
);
r_cnt_0 : X_FF
generic map(
LOC => "SLICE_X41Y65",
INIT => '0'
)
port map (
I => r_cnt_1_DYMUX_368,
CE => r_cnt_1_CEINV_356,
CLK => r_cnt_1_CLKINV_357,
SET => GND,
RST => r_cnt_1_SRINVNOT,
O => r_cnt(0)
);
Mcount_r_cnt_xor_1_11 : X_LUT4
generic map(
INIT => X"5A5A",
LOC => "SLICE_X41Y65"
)
port map (
ADR0 => r_cnt(1),
ADR1 => VCC,
ADR2 => r_cnt(0),
ADR3 => VCC,
O => Result(1)
);
state_FSM_Out31 : X_LUT4
generic map(
INIT => X"0F00",
LOC => "SLICE_X45Y67"
)
port map (
ADR0 => VCC,
ADR1 => VCC,
ADR2 => state_FSM_FFd2_109,
ADR3 => state_FSM_FFd1_113,
O => key_rdy_OBUF_402
);
key_rdy_OUTPUT_OFF_OMUX : X_BUF
generic map(
LOC => "PAD39",
PATHPULSE => 638 ps
)
port map (
I => key_rdy_OBUF_402,
O => key_rdy_O
);
NlwBlock_rc5_key_GND : X_ZERO
port map (
O => GND
);
NlwBlock_rc5_key_VCC : X_ONE
port map (
O => VCC
);
NlwBlockROC : X_ROC
generic map (ROC_WIDTH => 100 ns)
port map (O => GSR);
NlwBlockTOC : X_TOC
port map (O => GTS);
end Structure;
| lgpl-2.1 | f06431d79446aac3f560857f58e1e9b3 | 0.502847 | 2.890718 | false | false | false | false |
nsauzede/cpu86 | papilio2_lcd/ipcore_dir/clk32to40.vhd | 4 | 6,374 | -- file: clk32to40.vhd
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--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____40.000______0.000______50.0______700.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________32____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk32to40 is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk32to40;
architecture xilinx of clk32to40 is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk32to40,clk_wiz_v3_6,{component_name=clk32to40,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=31.25,clkin2_period=31.25,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 4,
CLKFX_MULTIPLY => 5,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
-- no phase alignment active, connect to ground
clkfb <= '0';
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkfx);
end xilinx;
| gpl-2.0 | 66f7dd2802b07dc0208f5f1897be43e7 | 0.560872 | 4.252168 | false | false | false | false |
nsauzede/cpu86 | papilio2_lcd/slib_input_sync.vhd | 3 | 1,612 | --
-- Input synchronization
--
-- Author: Sebastian Witt
-- Data: 27.01.2008
-- Version: 1.0
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_input_sync is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
D : in std_logic; -- Signal input
Q : out std_logic -- Signal output
);
end slib_input_sync;
architecture rtl of slib_input_sync is
signal iD : std_logic_vector(1 downto 0);
begin
IS_D: process (RST, CLK)
begin
if (RST = '1') then
iD <= (others => '0');
elsif (CLK'event and CLK='1') then
iD(0) <= D;
iD(1) <= iD(0);
end if;
end process;
-- Output ports
Q <= iD(1);
end rtl;
| gpl-2.0 | 4390a724482919ab10132d75d739a2ec | 0.598015 | 3.630631 | false | false | false | false |
nsauzede/cpu86 | mx_sdram/max1k_88_top.vhd | 1 | 8,985 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity max1k_88_top is
port(
USER_BTN : in std_logic := '0';
LED : out std_logic_vector(7 downto 0);
RsTx : out std_logic;
RsRx : in std_logic;
CLK12M : in std_logic := '0';
SDRAM_ADDR : out std_logic_vector(13 downto 0);
SDRAM_BA : out std_logic_vector(1 downto 0);
SDRAM_CASn : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CSn : out std_logic;
SDRAM_DQ : inout std_logic_vector(15 downto 0);
SDRAM_DQM : out std_logic_vector(1 downto 0);
SDRAM_RASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_CLK : out std_logic
);
end entity;
architecture behavioral of max1k_88_top is
COMPONENT NIOS_sdram_controller_0
PORT
(
az_addr : IN STD_LOGIC_VECTOR(21 DOWNTO 0);
az_be_n : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
az_cs : IN STD_LOGIC;
az_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
az_rd_n : IN STD_LOGIC;
az_wr_n : IN STD_LOGIC;
clk : IN STD_LOGIC;
reset_n : IN STD_LOGIC;
za_data : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
za_valid : OUT STD_LOGIC;
za_waitrequest : OUT STD_LOGIC;
zs_addr : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
zs_ba : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zs_cas_n : OUT STD_LOGIC;
zs_cke : OUT STD_LOGIC;
zs_cs_n : OUT STD_LOGIC;
zs_dq : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
zs_dqm : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zs_ras_n : OUT STD_LOGIC;
zs_we_n : OUT STD_LOGIC
);
END COMPONENT;
signal clk40 : std_logic;
signal dbus_in : std_logic_vector (7 DOWNTO 0);
signal intr : std_logic;
signal nmi : std_logic;
signal por : std_logic := '1';
signal ipor : std_logic_vector(7 DOWNTO 0) := (others => '1');
signal abus : std_logic_vector (19 DOWNTO 0);
SIGNAL dbus_in_cpu : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_out : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_rom : std_logic_vector(7 DOWNTO 0);
signal cpuerror : std_logic;
signal inta : std_logic;
signal iom : std_logic;
signal rdn : std_logic;
signal resoutn : std_logic := '0';
signal wran : std_logic;
signal wrn : std_logic;
SIGNAL wea : std_logic_VECTOR(0 DOWNTO 0);
SIGNAL sel_s : std_logic_vector(5 DOWNTO 0) := "111111";
signal csromn : std_logic;
signal csisramn : std_logic;
signal csesdramn : std_logic;
SIGNAL dout : std_logic;
SIGNAL dout1 : std_logic;
SIGNAL wrcom : std_logic;
signal rxclk_s : std_logic;
SIGNAL DCDn : std_logic := '1';
SIGNAL DSRn : std_logic := '1';
SIGNAL RIn : std_logic := '1';
SIGNAL cscom1 : std_logic;
SIGNAL dbus_com1 : std_logic_vector(7 DOWNTO 0);
signal CTS : std_logic := '1';
signal DTRn : std_logic;
signal IRQ : std_logic;
signal OUT1n : std_logic;
signal OUT2n : std_logic;
signal RTSn : std_logic;
signal stx : std_logic;
signal za_data : std_logic_vector(15 DOWNTO 0);
signal za_valid : std_logic;
signal za_waitrequest : std_logic;
signal az_addr : std_logic_vector(21 DOWNTO 0);
signal az_be_n : std_logic_vector(1 DOWNTO 0);
signal az_cs : std_logic;
signal az_data : std_logic_vector(15 DOWNTO 0);
signal az_rd_n : std_logic;
signal az_wr_n : std_logic;
signal clk_int80 : std_logic;
signal reset_n : std_logic;
signal pll_sys_locked : std_logic;
begin
-- clk40 <= CLK12M;
--clk40/baudrate static SDRAM access status :
--1M/960 : 80cyc80=GOOD
--4M/3840 : 20cyc80=GOOD
--5M/4800 : 16cyc80=BAD0 20cyc100=GOOD
--8M/7680 : 10cyc80=BAD1
--10M/9600 : 08cyc80=BAD? 10cyc100=BAD0
pll0: entity work.pll12to40 PORT MAP (
inclk0 => CLK12M,
c0 => clk40,
c1 => clk_int80,
c2 => SDRAM_CLK,
locked => pll_sys_locked
);
-- led <= dbus_out;
-- led <= ipor;
RsTx <= stx;
-- led <= rxclk_s & DTRn & IRQ & OUT1n & OUT2n & RTSn & stx & ipor(0);
led <= RsRx & DTRn & IRQ & OUT1n & OUT2n & RTSn & stx & ipor(0);
nmi <= '0';
intr <= '0';
dout <= '0';
dout1 <= '0';
DCDn <= '0';
DSRn <= '0';
RIn <= '0';
CTS <= '1';
por <= ipor(0) or not pll_sys_locked;
process(clk40)
begin
if rising_edge(clk40) then
if USER_BTN='0' then
ipor <= (others => '1');
else
ipor <= '0' & ipor(7 downto 1);
end if;
end if;
end process;
U_1 : entity work.cpu86
PORT MAP (
clk => clk40,
dbus_in => dbus_in_cpu,
intr => intr,
nmi => nmi,
por => por,
abus => abus,
cpuerror => cpuerror,
dbus_out => dbus_out,
inta => inta,
iom => iom,
rdn => rdn,
resoutn => resoutn,
wran => wran,
wrn => wrn
);
wea(0) <= not wrn and not csisramn;
ram0: ENTITY work.ram PORT map(
address => abus(14 downto 0),
clock => clk40,
data => dbus_out,
wren => wea(0),
q => dbus_in
);
wrcom <= wrn or cscom1;
rom0: entity work.bootstrap port map(
abus => abus(7 downto 0),
dbus => dbus_rom
);
-- chip_select
-- Comport, uart_16550
-- COM1, 0x3F8-0x3FF
cscom1 <= '0' when (abus(15 downto 4)=x"03f" AND iom='1') else '1';
-- internal SRAM
-- below 0x4000
csisramn <= '0' when (abus(19 downto 16)=x"0" AND iom='0') else '1';
-- Bootstrap ROM 256 bytes
-- FFFFF-FF=FFF00
csromn <= '0' when ((abus(19 downto 8)=X"FFF") AND iom='0') else '1';
-- external SDRAM as I/O
-- 0x408-0x40F
-- csesdramn <= '0' when (abus(15 downto 4)=x"040" AND iom='1') else '1';
-- external SDRAM 256 bytes
-- 040FF-FF=04000
-- csesdramn <= '0' when ((abus(19 downto 16)=X"1") AND iom='0') else '1';
-- external SDRAM as memory
-- all memory except isram and rom
csesdramn <= '0' when (csisramn='1' AND csromn='1' AND iom='0') else '1';
-- dbus_in_cpu multiplexer
-- sel_s <= cscom1 & csromn & csisramn & csspin & csesdramn & csbutled;
sel_s <= cscom1 & csromn & csisramn & "1" & csesdramn & "1";
-- sel_s <= "1" & csromn & csisramn & "111";
-- process(sel_s,dbus_com1,dbus_in,dbus_rom,dbus_esram,dbus_spi,buttons)
process(sel_s,dbus_com1,dbus_in,dbus_rom,dbus_in_cpu,za_data)
begin
case sel_s is
when "011111" => dbus_in_cpu <= dbus_com1; -- UART
when "101111" => dbus_in_cpu <= dbus_rom; -- BootStrap Loader
when "110111" => dbus_in_cpu <= dbus_in; -- Embedded SRAM
-- when "111011" => dbus_in_cpu <= dbus_spi; -- SPI
when "111101" => dbus_in_cpu <= za_data(7 downto 0); -- External SDRAM
-- when "111110" => dbus_in_cpu <= x"0" & buttons; -- butled
when others => dbus_in_cpu <= dbus_in_cpu; -- default : latch
end case;
end process;
U_0 : entity work.uart_top
PORT MAP (
BR_clk => rxclk_s,
CTSn => CTS,
DCDn => DCDn,
DSRn => DSRn,
RIn => RIn,
abus => abus(2 DOWNTO 0),
clk => clk40,
csn => cscom1,
dbus_in => dbus_out,
rdn => rdn,
resetn => resoutn,
sRX => RsRx,
wrn => wrn,
B_CLK => rxclk_s,
DTRn => DTRn,
IRQ => IRQ,
OUT1n => OUT1n,
OUT2n => OUT2n,
-- RTSn => RTS,
RTSn => RTSn,
dbus_out => dbus_com1,
stx => stx
);
reset_n <= resoutn;
az_addr(21 downto 20) <= (others => '0');
az_addr(19 downto 0) <= abus(19 downto 0);
az_be_n <= (others => '0');
az_data(15 downto 8) <= (others => '0');
az_data(7 downto 0) <= dbus_out;
az_cs <= csesdramn; -- STRANGE! the controller seems to not use az_cs ? only az_rd_n and az_wr_n
az_rd_n <= rdn or az_cs;
az_wr_n <= wrn or az_cs;
sdram0 : NIOS_sdram_controller_0 port map (
-- inputs:
az_addr => az_addr,
az_be_n => az_be_n,
az_cs => az_cs,
az_data => az_data,
az_rd_n => az_rd_n,
az_wr_n => az_wr_n,
clk => clk_int80,
reset_n => reset_n,
-- outputs:
za_data => za_data,
za_valid => za_valid,
za_waitrequest => za_waitrequest,
zs_addr => SDRAM_ADDR(11 downto 0), -- comment this line, if the full address width of 14 bits is required
-- zs_addr => SDRAM_ADDR, -- uncomment this line, if the full address width of 14 bits is required
zs_ba => SDRAM_BA,
zs_cas_n => SDRAM_CASn,
zs_cke => SDRAM_CKE,
zs_cs_n => SDRAM_CSn,
zs_dq => SDRAM_DQ,
zs_dqm => SDRAM_DQM,
zs_ras_n => SDRAM_RASn,
zs_we_n => SDRAM_WEn
);
SDRAM_ADDR(13) <= '0'; -- comment this line, if the full address width of 14 bits is required
SDRAM_ADDR(12) <= '0'; -- comment this line, if the full address width of 14 bits is required
end architecture;
| gpl-2.0 | ff7f2ee77e2078751d61ec62e158a15e | 0.554925 | 2.807813 | false | false | false | false |
andykarpov/radio-86rk-wxeda | src/keyboard/KeyboardMapper.vhd | 1 | 4,084 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity KeyboardMapper is
port (Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
PS2Busy : in STD_LOGIC;
PS2Error : in STD_LOGIC;
DataReady : in STD_LOGIC;
DataByte : in STD_LOGIC_VECTOR(7 downto 0);
Send : out STD_LOGIC;
Command : out STD_LOGIC_VECTOR(7 downto 0);
CodeReady : out STD_LOGIC;
ScanCode : out STD_LOGIC_VECTOR(9 downto 0));
end KeyboardMapper;
-- ScanCode(9) = 1 -> Extended
-- = 0 -> Regular (Not Extended)
-- ScanCode(8) = 1 -> Break
-- = 0 -> Make
-- ScanCode(7 downto 0) -> Key Code
architecture Behavioral of KeyboardMapper is
type StateType is (ResetKbd, ResetAck, WaitForBAT, Start, Extended, ExtendedBreak, Break, LEDs, CheckAck);
signal State : StateType;
signal CapsLock : STD_LOGIC;
signal NumLock : STD_LOGIC;
signal ScrollLock : STD_LOGIC;
signal PauseON : STD_LOGIC;
signal i : natural range 0 to 7;
begin
process(Reset, PS2Error, Clock)
begin
if Reset = '1' or PS2Error = '1' then
CapsLock <= '0';
NumLock <= '0';
ScrollLock <= '0';
PauseON <= '0';
i <= 0;
Send <= '0';
Command <= (others => '0');
CodeReady <= '0';
ScanCode <= (others => '0');
State <= Start;
elsif rising_edge(Clock) then
case State is
when ResetKbd =>
if PS2Busy = '0' then
Send <= '1';
Command <= x"FF";
State <= ResetAck;
end if;
when ResetAck =>
Send <= '0';
if Dataready = '1' then
if DataByte = x"FA" then
State <= WaitForBAT;
else
State <= ResetKbd;
end if;
end if;
when WaitForBAT =>
if DataReady = '1' then
if DataByte = x"AA" then -- BAT(self test) completed successfully
State <= Start;
else
State <= ResetKbd;
end if;
end if;
when Start =>
CodeReady <= '0';
if DataReady = '1' then
case DataByte is
when x"E0" =>
State <= Extended;
when x"F0" =>
State <= Break;
when x"FA" => --Acknowledge
null;
when x"AA" =>
State <= Start;
when x"FC" =>
State <= ResetKbd;
when x"58" =>
Send <= '1';
Command <= x"ED";
CapsLock <= not CapsLock;
ScanCode <= "00" & DataByte;
CodeReady <= '1';
State <= LEDs;
when x"77" =>
Send <= '1';
Command <= x"ED";
NumLock <= not NumLock;
ScanCode <= "00" & DataByte;
CodeReady <= '1';
State <= LEDs;
when x"7E" =>
Send <= '1';
Command <= x"ED";
ScrollLock <= not ScrollLock;
ScanCode <= "00" & DataByte;
CodeReady <= '1';
State <= LEDs;
when others =>
ScanCode <= "00" & DataByte;
CodeReady <= '1';
State <= Start;
end case;
end if;
when Extended =>
if DataReady = '1' then
if DataByte = x"F0" then
State <= ExtendedBreak;
else
ScanCode <= "10" & DataByte;
CodeReady <= '1';
State <= Start;
end if;
end if;
when ExtendedBreak =>
if DataReady = '1' then
ScanCode <= "11" & DataByte;
CodeReady <= '1';
State <= Start;
end if;
when Break =>
if DataReady = '1' then
ScanCode <= "01" & DataByte;
CodeReady <= '1';
State <= Start;
end if;
when LEDs =>
Send <= '0';
CodeReady <= '0';
if Dataready = '1' then
if DataByte = x"FA" then
Send <= '1';
Command <= "00000" & CapsLock & NumLock & ScrollLock;
State <= CheckAck;
elsif DataByte = x"FE" then
Send <= '1';
end if;
end if;
when CheckAck =>
Send <= '0';
if Dataready = '1' then
if DataByte = x"FA" then
State <= Start;
elsif DataByte = x"FE" then
Send <= '1';
end if;
end if;
when others => null;
end case;
end if;
end process;
end Behavioral; | bsd-2-clause | 24d03d2cae48261645157cb2bf3a750d | 0.518609 | 3.254183 | false | false | false | false |
VenturaSolutionsInc/VHDL | igmp/igmp_controller_tb.vhd | 1 | 4,114 | -------------------------------------------------------------------------------
-- Title : Testbench for design "igmp_wrapper"
-- Project :
-------------------------------------------------------------------------------
-- File : igmp_wrapper_tb.vhd
-- Author : Colin Shea <[email protected]>
-- Company :
-- Created : 2010-06-27
-- Last update: 2010-08-11
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2010
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-06-27 1.0 colinshea Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity igmp_wrapper_tb is
end igmp_wrapper_tb;
-------------------------------------------------------------------------------
architecture testbench of igmp_wrapper_tb is
-- component generics
constant gen_dataWidth : integer := 8;
signal srcMAC : std_logic_vector(47 downto 0):=X"010040506660";
signal destMAC : std_logic_vector(47 downto 0):=X"01005E1C1901";
signal vlanEn : std_logic := '1';
signal vlanId : std_logic_vector(11 downto 0):=X"06A";
signal srcIP : std_logic_vector(31 downto 0):=X"C0A80164";
signal destIP : std_logic_vector(31 downto 0):=X"EF9C1901";
signal tx_ready_n : std_logic;
signal tx_sof : std_logic;
signal tx_eof : std_logic;
signal tx_vld : std_logic;
signal tx_data : std_logic_vector(7 downto 0);
signal igmp_sof : std_logic;
signal igmp_eof : std_logic;
signal igmp_vld : std_logic;
signal igmp_data : std_logic_vector(7 downto 0);
-- component ports
signal dataClk : std_logic;
signal reset : std_logic;
signal join : std_logic;
signal leave : std_logic;
signal respond : std_logic;
signal rspTime : std_logic_vector(7 downto 0);
-- signal destIP : std_logic_vector(31 downto 0);
-- signal destMAC : std_logic_vector(47 downto 0);
-- signal messageSent : std_logic;
-- signal out_join : std_logic;
-- signal out_leave : std_logic;
-- signal out_destMAC_o : std_logic_vector(47 downto 0);
-- signal out_destIP_o : std_logic_vector(31 downto 0);
signal out_enProc : std_logic;
signal out_enCommand : std_logic;
begin -- testbench
igmp_wrapper_1: entity work.igmp_wrapper
port map (
dataClk => dataClk,
reset => reset,
join => join,
leave => leave,
srcMAC => srcMAC,
srcIP => srcIP,
destMAC => destMAC,
destIP => destIP,
vlanEn => vlanEn,
vlanId => vlanId,
tx_ready_n => tx_ready_n,
tx_data => tx_data,
tx_vld => tx_vld,
tx_sof => tx_sof,
tx_eof => tx_eof,
igmp_data => igmp_data,
igmp_vld => igmp_vld,
igmp_sof => igmp_sof,
igmp_eof => igmp_eof,
out_enProc => out_enProc,
out_enCommand => out_enCommand
);
process
begin
dataClk <= '1';
wait for 4 ns;
dataClk <= '0';
wait for 4 ns;
end process;
process
begin
reset <= '1';
rspTime <= (others => '0');
leave <= '0';
join <= '0';
respond <= '0';
tx_ready_n <= '1';
wait for 24 ns;
reset <= '0';
join <= '1';
tx_ready_n <= '0';
wait for 8 ns;
join <= '0';
wait for 1 ms;
respond <= '1';
rspTime <= X"0A";
wait for 8 ns;
respond <= '0';
wait for 1 sec;
wait for 750 ns;
leave <= '1';
wait for 8 ns;
leave <= '0';
wait;
end process;
end testbench;
| gpl-2.0 | 113ae43a80fc083ab2e0d0ebdcdd3eed | 0.459407 | 3.951969 | false | false | false | false |
nsauzede/cpu86 | papilio1_0_rom/ipcore_dir/dcm32to40.vhd | 2 | 3,201 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application : xaw2vhdl
-- / / Filename : dcm32to40.vhd
-- /___/ /\ Timestamp : 02/13/2015 16:28:25
-- \ \ / \
-- \___\/\___\
--
--Command: xaw2vhdl-st C:\nico\perso\hack\hackerspace\fpga\x86\cpu86\papilio1\ipcore_dir\.\dcm32to40.xaw C:\nico\perso\hack\hackerspace\fpga\x86\cpu86\papilio1\ipcore_dir\.\dcm32to40
--Design Name: dcm32to40
--Device: xc3s500e-4cp132
--
-- Module dcm32to40
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
-- Period Jitter (unit interval) for block DCM_SP_INST = 0.04 UI
-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 0.92 ns
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity dcm32to40 is
port ( CLKIN_IN : in std_logic;
RST_IN : in std_logic;
CLKFX_OUT : out std_logic;
CLKIN_IBUFG_OUT : out std_logic;
CLK0_OUT : out std_logic);
end dcm32to40;
architecture BEHAVIORAL of dcm32to40 is
signal CLKFB_IN : std_logic;
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal CLK0_BUF : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
CLK0_OUT <= CLKFB_IN;
CLKFX_BUFG_INST : BUFG
port map (I=>CLKFX_BUF,
O=>CLKFX_OUT);
CLKIN_IBUFG_INST : IBUFG
port map (I=>CLKIN_IN,
O=>CLKIN_IBUFG);
CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLKFB_IN);
DCM_SP_INST : DCM_SP
generic map( CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 4,
CLKFX_MULTIPLY => 5,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.250,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>CLKFB_IN,
CLKIN=>CLKIN_IBUFG,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>RST_IN,
CLKDV=>open,
CLKFX=>CLKFX_BUF,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>open,
PSDONE=>open,
STATUS=>open);
end BEHAVIORAL;
| gpl-2.0 | 13e4101940cca57361bfd4524f9654f7 | 0.468604 | 3.666667 | false | false | false | false |
kdgwill/VHDL_Verilog_Encryptions_And_Ciphers | VHDL_RC5/Encryption_Decryption/tb_rc5.vhd | 1 | 1,496 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE WORK.RC5_PKG.ALL;
ENTITY tb_rc5 IS
PORT (
clr, clk : IN STD_LOGIC; -- Asynchronous reset and Clock Signal
enc : IN STD_LOGIC; -- Encryption or decryption?
key_vld : IN STD_LOGIC; -- Indicate the input is user key
data_vld : IN STD_LOGIC; -- Indicate the input is user data
din : IN STD_LOGIC_VECTOR(63 downto 0);
dout : OUT STD_LOGIC_VECTOR(63 downto 0);
data_rdy : OUT STD_LOGIC; -- Indicate the output data is ready
key_rdy : OUT STD_LOGIC -- Indicate the key generation is completed
);
END tb_rc5;
ARCHITECTURE struct OF tb_rc5 IS -- Structural description
signal skey : rc5_rom_26;
signal key_ready : std_logic;
signal dout_enc : std_logic_vector(63 downto 0);
signal dout_dec : std_logic_vector(63 downto 0);
signal dec_rdy : std_logic;
signal enc_rdy : std_logic;
signal enc_clr : std_logic;
signal dec_clr : std_logic;
--Key will be attached to din twice
signal key : std_logic_vector(127 downto 0);
BEGIN
key(127 downto 64) <= din;
key( 63 downto 0) <= din;
U1: rc5_key
PORT MAP(clr=>clr, clk=>clk, key=>key, key_vld=>key_vld, --Input
skey=>skey, key_rdy=>key_ready); --Output
U2: rc5
PORT MAP(clr=>clr, clk=>clk, enc=>enc, din=>din, di_vld=>data_vld, key_rdy=>key_ready, skey=>skey, --Input
dout=>dout, do_rdy=>data_rdy); --Output
key_rdy <= key_ready;
END struct; | lgpl-2.1 | c788fc5cb2c997f6e741e34e045d6dc1 | 0.625 | 3.004016 | false | false | false | false |
nsauzede/cpu86 | papilio2_lcd/drigmorn1_top.vhd | 1 | 11,954 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Toplevel : CPU86, 256Byte ROM, 16550 UART, 40K8 SRAM (all blockrams used)--
-------------------------------------------------------------------------------
-- Revision History: --
-- --
-- Date: Revision Author --
-- --
-- 30 Dec 2007 0.1 H. Tiggeler First version --
-- 17 May 2008 0.75 H. Tiggeler Updated for CPU86 ver0.75 --
-- 27 Jun 2008 0.79 H. Tiggeler Changed UART to Opencores 16750 --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
ENTITY drigmorn1_top IS
PORT(
sram_addr : out std_logic_vector(20 downto 0);
sram_data : inout std_logic_vector(7 downto 0);
sram_ce : out std_logic;
sram_we : out std_logic;
sram_oe : out std_logic;
vramaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
vramdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLOCK_40MHZ : IN std_logic;
CTS : IN std_logic := '1';
PIN3 : IN std_logic;
RXD : IN std_logic;
LED1 : OUT std_logic;
LED2N : OUT std_logic;
LED3N : OUT std_logic;
PIN4 : OUT std_logic;
RTS : OUT std_logic;
TXD : OUT std_logic
);
END drigmorn1_top ;
ARCHITECTURE struct OF drigmorn1_top IS
-- Architecture declarations
signal csromn : std_logic;
signal csesramn : std_logic;
signal csisramn : std_logic;
-- Internal signal declarations
signal vramaddr2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal vrambase : STD_LOGIC_VECTOR(15 DOWNTO 0):=x"4000";
SIGNAL DCDn : std_logic := '1';
SIGNAL DSRn : std_logic := '1';
SIGNAL RIn : std_logic := '1';
SIGNAL abus : std_logic_vector(19 DOWNTO 0);
SIGNAL clk : std_logic;
SIGNAL cscom1 : std_logic;
SIGNAL dbus_com1 : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_in : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_in_cpu : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_out : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_rom : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_esram : std_logic_vector(7 DOWNTO 0);
SIGNAL dout : std_logic;
SIGNAL dout1 : std_logic;
SIGNAL intr : std_logic;
SIGNAL iom : std_logic;
SIGNAL nmi : std_logic;
SIGNAL por : std_logic;
SIGNAL rdn : std_logic;
SIGNAL resoutn : std_logic;
SIGNAL sel_s : std_logic_vector(2 DOWNTO 0);
SIGNAL wea : std_logic_VECTOR(0 DOWNTO 0);
SIGNAL wran : std_logic;
SIGNAL wrcom : std_logic;
SIGNAL wrn : std_logic;
signal rxclk_s : std_logic;
-- Component Declarations
COMPONENT cpu86
PORT(
clk : IN std_logic;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
intr : IN std_logic;
nmi : IN std_logic;
por : IN std_logic;
abus : OUT std_logic_vector (19 DOWNTO 0);
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
cpuerror : OUT std_logic;
inta : OUT std_logic;
iom : OUT std_logic;
rdn : OUT std_logic;
resoutn : OUT std_logic;
wran : OUT std_logic;
wrn : OUT std_logic
);
END COMPONENT;
-- COMPONENT blk_mem_40K
-- PORT (
-- addra : IN std_logic_VECTOR (15 DOWNTO 0);
-- clka : IN std_logic;
-- dina : IN std_logic_VECTOR (7 DOWNTO 0);
-- wea : IN std_logic_VECTOR (0 DOWNTO 0);
-- douta : OUT std_logic_VECTOR (7 DOWNTO 0)
-- );
-- END COMPONENT;
component blk_mem_40K
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END component;
COMPONENT bootstrap
PORT (
abus : IN std_logic_vector (7 DOWNTO 0);
dbus : OUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
COMPONENT uart_top
PORT (
BR_clk : IN std_logic ;
CTSn : IN std_logic := '1';
DCDn : IN std_logic := '1';
DSRn : IN std_logic := '1';
RIn : IN std_logic := '1';
abus : IN std_logic_vector (2 DOWNTO 0);
clk : IN std_logic ;
csn : IN std_logic ;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
rdn : IN std_logic ;
resetn : IN std_logic ;
sRX : IN std_logic ;
wrn : IN std_logic ;
B_CLK : OUT std_logic ;
DTRn : OUT std_logic ;
IRQ : OUT std_logic ;
OUT1n : OUT std_logic ;
OUT2n : OUT std_logic ;
RTSn : OUT std_logic ;
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
stx : OUT std_logic
);
END COMPONENT;
BEGIN
sram_addr <= '0' & abus;
---- sram_data <= dbus_.
-- dbus_esram <= sram_data;
-- sram_data <= (others => 'Z') when rdn='0' else sram_data;
-- sram_ce <= csesramn;
-- sram_we <= wrn;
-- sram_oe <= rdn;
process(csesramn,wrn,rdn,dbus_out,sram_data)
begin
sram_ce <= '1';
sram_we <= '1';
sram_oe <= '1';
sram_data <= (others => 'Z');
if csesramn='0' then
sram_ce <= '0';
if wrn='0' then
sram_data <= dbus_out;
sram_we <= '0';
else
if rdn='0' then
dbus_esram <= sram_data;
sram_oe <= '0';
end if;
end if;
end if;
end process;
-- Architecture concurrent statements
-- HDL Embedded Text Block 4 mux
-- dmux 1
process(sel_s,dbus_com1,dbus_in,dbus_rom,dbus_esram)
begin
case sel_s is
when "011" => dbus_in_cpu <= dbus_com1; -- UART
when "101" => dbus_in_cpu <= dbus_rom; -- BootStrap Loader
when "110" => dbus_in_cpu <= dbus_in; -- Embedded SRAM
when others => dbus_in_cpu <= dbus_esram; -- External SRAM
end case;
end process;
-- HDL Embedded Text Block 7 clogic
clk <= CLOCK_40MHZ;
wrcom <= not wrn;
wea(0)<= not wrn;
PIN4 <= resoutn; -- For debug only
-- dbus_in_cpu multiplexer
sel_s <= cscom1 & csromn & csisramn;
-- chip_select
-- Comport, uart_16550
-- COM1, 0x3F8-0x3FF
cscom1 <= '0' when (abus(15 downto 3)="0000001111111" AND iom='1') else '1';
-- Bootstrap ROM 256 bytes
-- FFFFF-FF=FFF00
csromn <= '0' when ((abus(19 downto 8)=X"FFF") AND iom='0') else '1';
-- external SRAM
-- 0x5F8-0x5FF
csesramn <= '0' when (csromn='1' and csisramn='1' AND iom='0') else '1';
-- csesramn <= not (cscom1 and csromnn and csiramn);
-- internal SRAM
-- below 0x4000
csisramn <= '0' when (abus(19 downto 14)="000000" AND iom='0') else '1';
nmi <= '0';
intr <= '0';
dout <= '0';
dout1 <= '0';
DCDn <= '0';
DSRn <= '0';
RIn <= '0';
por <= NOT(PIN3);
-- Instance port mappings.
U_1 : cpu86
PORT MAP (
clk => clk,
dbus_in => dbus_in_cpu,
intr => intr,
nmi => nmi,
por => por,
abus => abus,
cpuerror => LED1,
dbus_out => dbus_out,
inta => OPEN,
iom => iom,
rdn => rdn,
resoutn => resoutn,
wran => wran,
wrn => wrn
);
-- U_3 : blk_mem_40K
-- PORT MAP (
-- clka => clk,
-- dina => dbus_out,
-- addra => abus(15 DOWNTO 0),
-- wea => wea,
-- douta => dbus_in
-- );
vramaddr2 <= vramaddr + vrambase;
U_3 : blk_mem_40K
PORT MAP (
clka => clk,
dina => dbus_out,
addra => abus(15 DOWNTO 0),
wea => wea,
douta => dbus_in
,
clkb => clk,
dinb => (others => '0'),
addrb => vramaddr2,
web => (others => '0'),
doutb => vramdata
);
U_2 : bootstrap
PORT MAP (
abus => abus(7 DOWNTO 0),
dbus => dbus_rom
);
U_0 : uart_top
PORT MAP (
BR_clk => rxclk_s,
CTSn => CTS,
DCDn => DCDn,
DSRn => DSRn,
RIn => RIn,
abus => abus(2 DOWNTO 0),
clk => clk,
csn => cscom1,
dbus_in => dbus_out,
rdn => rdn,
resetn => resoutn,
sRX => RXD,
wrn => wrn,
B_CLK => rxclk_s,
DTRn => OPEN,
IRQ => OPEN,
OUT1n => led2n,
OUT2n => led3n,
RTSn => RTS,
dbus_out => dbus_com1,
stx => TXD
);
END struct;
| gpl-2.0 | ad301cfb2f7c3300e9f5b5fb358092c3 | 0.453237 | 3.857373 | false | false | false | false |
nsauzede/cpu86 | papilio2_drigmorn1/drigmorn1_top.vhd | 1 | 10,820 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Toplevel : CPU86, 256Byte ROM, 16550 UART, 40K8 SRAM (all blockrams used)--
-------------------------------------------------------------------------------
-- Revision History: --
-- --
-- Date: Revision Author --
-- --
-- 30 Dec 2007 0.1 H. Tiggeler First version --
-- 17 May 2008 0.75 H. Tiggeler Updated for CPU86 ver0.75 --
-- 27 Jun 2008 0.79 H. Tiggeler Changed UART to Opencores 16750 --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY drigmorn1_top IS
PORT(
sram_addr : out std_logic_vector(20 downto 0);
sram_data : inout std_logic_vector(7 downto 0);
sram_ce : out std_logic;
sram_we : out std_logic;
sram_oe : out std_logic;
CLOCK_40MHZ : IN std_logic;
CTS : IN std_logic := '1';
PIN3 : IN std_logic;
RXD : IN std_logic;
LED1 : OUT std_logic;
LED2N : OUT std_logic;
LED3N : OUT std_logic;
PIN4 : OUT std_logic;
RTS : OUT std_logic;
TXD : OUT std_logic
);
END drigmorn1_top ;
ARCHITECTURE struct OF drigmorn1_top IS
-- Architecture declarations
signal csromn : std_logic;
signal csesramn : std_logic;
signal csisramn : std_logic;
-- Internal signal declarations
SIGNAL DCDn : std_logic := '1';
SIGNAL DSRn : std_logic := '1';
SIGNAL RIn : std_logic := '1';
SIGNAL abus : std_logic_vector(19 DOWNTO 0);
SIGNAL clk : std_logic;
SIGNAL cscom1 : std_logic;
SIGNAL dbus_com1 : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_in : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_in_cpu : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_out : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_rom : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_esram : std_logic_vector(7 DOWNTO 0);
SIGNAL dout : std_logic;
SIGNAL dout1 : std_logic;
SIGNAL intr : std_logic;
SIGNAL iom : std_logic;
SIGNAL nmi : std_logic;
SIGNAL por : std_logic;
SIGNAL rdn : std_logic;
SIGNAL resoutn : std_logic;
SIGNAL sel_s : std_logic_vector(2 DOWNTO 0);
SIGNAL wea : std_logic_VECTOR(0 DOWNTO 0);
SIGNAL wran : std_logic;
SIGNAL wrcom : std_logic;
SIGNAL wrn : std_logic;
signal rxclk_s : std_logic;
-- Component Declarations
COMPONENT cpu86
PORT(
clk : IN std_logic;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
intr : IN std_logic;
nmi : IN std_logic;
por : IN std_logic;
abus : OUT std_logic_vector (19 DOWNTO 0);
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
cpuerror : OUT std_logic;
inta : OUT std_logic;
iom : OUT std_logic;
rdn : OUT std_logic;
resoutn : OUT std_logic;
wran : OUT std_logic;
wrn : OUT std_logic
);
END COMPONENT;
COMPONENT blk_mem_40K
PORT (
addra : IN std_logic_VECTOR (15 DOWNTO 0);
clka : IN std_logic;
dina : IN std_logic_VECTOR (7 DOWNTO 0);
wea : IN std_logic_VECTOR (0 DOWNTO 0);
douta : OUT std_logic_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
COMPONENT bootstrap
PORT (
abus : IN std_logic_vector (7 DOWNTO 0);
dbus : OUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
COMPONENT uart_top
PORT (
BR_clk : IN std_logic ;
CTSn : IN std_logic := '1';
DCDn : IN std_logic := '1';
DSRn : IN std_logic := '1';
RIn : IN std_logic := '1';
abus : IN std_logic_vector (2 DOWNTO 0);
clk : IN std_logic ;
csn : IN std_logic ;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
rdn : IN std_logic ;
resetn : IN std_logic ;
sRX : IN std_logic ;
wrn : IN std_logic ;
B_CLK : OUT std_logic ;
DTRn : OUT std_logic ;
IRQ : OUT std_logic ;
OUT1n : OUT std_logic ;
OUT2n : OUT std_logic ;
RTSn : OUT std_logic ;
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
stx : OUT std_logic
);
END COMPONENT;
BEGIN
sram_addr <= '0' & abus;
---- sram_data <= dbus_
-- dbus_esram <= sram_data;
-- sram_data <= (others => 'Z') when rdn='0' else sram_data;
-- sram_ce <= csesramn;
-- sram_we <= wrn;
-- sram_oe <= rdn;
process(csesramn,wrn,rdn,dbus_out,sram_data)
begin
sram_ce <= '1';
sram_we <= '1';
sram_oe <= '1';
sram_data <= (others => 'Z');
if csesramn='0' then
sram_ce <= '0';
if wrn='0' then
sram_data <= dbus_out;
sram_we <= '0';
else
if rdn='0' then
dbus_esram <= sram_data;
sram_oe <= '0';
end if;
end if;
end if;
end process;
-- Architecture concurrent statements
-- HDL Embedded Text Block 4 mux
-- dmux 1
process(sel_s,dbus_com1,dbus_in,dbus_rom,dbus_esram)
begin
case sel_s is
when "011" => dbus_in_cpu <= dbus_com1; -- UART
when "101" => dbus_in_cpu <= dbus_rom; -- BootStrap Loader
when "110" => dbus_in_cpu <= dbus_in; -- Embedded SRAM
when others => dbus_in_cpu <= dbus_esram; -- External SRAM
end case;
end process;
-- HDL Embedded Text Block 7 clogic
clk <= CLOCK_40MHZ;
wrcom <= not wrn;
wea(0)<= not wrn;
PIN4 <= resoutn; -- For debug only
-- dbus_in_cpu multiplexer
sel_s <= cscom1 & csromn & csisramn;
-- chip_select
-- Comport, uart_16550
-- COM1, 0x3F8-0x3FF
cscom1 <= '0' when (abus(15 downto 3)="0000001111111" AND iom='1') else '1';
-- Bootstrap ROM 256 bytes
-- FFFFF-FF=FFF00
csromn <= '0' when ((abus(19 downto 8)=X"FFF") AND iom='0') else '1';
-- external SRAM
-- 0x5F8-0x5FF
csesramn <= '0' when (csromn='1' and csisramn='1' AND iom='0') else '1';
-- csesramn <= not (cscom1 and csromnn and csiramn);
-- internal SRAM
-- below 0x4000
csisramn <= '0' when (abus(19 downto 14)="000000" AND iom='0') else '1';
nmi <= '0';
intr <= '0';
dout <= '0';
dout1 <= '0';
DCDn <= '0';
DSRn <= '0';
RIn <= '0';
por <= NOT(PIN3);
-- Instance port mappings.
U_1 : cpu86
PORT MAP (
clk => clk,
dbus_in => dbus_in_cpu,
intr => intr,
nmi => nmi,
por => por,
abus => abus,
cpuerror => LED1,
dbus_out => dbus_out,
inta => OPEN,
iom => iom,
rdn => rdn,
resoutn => resoutn,
wran => wran,
wrn => wrn
);
U_3 : blk_mem_40K
PORT MAP (
clka => clk,
dina => dbus_out,
addra => abus(15 DOWNTO 0),
wea => wea,
douta => dbus_in
);
U_2 : bootstrap
PORT MAP (
abus => abus(7 DOWNTO 0),
dbus => dbus_rom
);
U_0 : uart_top
PORT MAP (
BR_clk => rxclk_s,
CTSn => CTS,
DCDn => DCDn,
DSRn => DSRn,
RIn => RIn,
abus => abus(2 DOWNTO 0),
clk => clk,
csn => cscom1,
dbus_in => dbus_out,
rdn => rdn,
resetn => resoutn,
sRX => RXD,
wrn => wrn,
B_CLK => rxclk_s,
DTRn => OPEN,
IRQ => OPEN,
OUT1n => led2n,
OUT2n => led3n,
RTSn => RTS,
dbus_out => dbus_com1,
stx => TXD
);
END struct;
| gpl-2.0 | 4435f6976f366c74c38e9af3ece3a3ce | 0.442052 | 3.956124 | false | false | false | false |
nsauzede/cpu86 | papilio1/papilio1_tb.vhd | 1 | 10,675 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:17:57 02/17/2015
-- Design Name:
-- Module Name: C:/nico/perso/hack/hackerspace/fpga/x86/cpu86/papilio1/papilio1_tb.vhd
-- Project Name: papilio1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: papilio1_top
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.STD_LOGIC_UNSIGNED.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
LIBRARY std;
USE std.TEXTIO.all;
USE work.utils.all;
ENTITY papilio1_tb IS
END papilio1_tb;
ARCHITECTURE behavior OF papilio1_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT papilio1_top
PORT(
rx : IN std_logic;
tx : OUT std_logic;
W1A : INOUT std_logic_vector(15 downto 0);
W1B : INOUT std_logic_vector(15 downto 0);
W2C : INOUT std_logic_vector(15 downto 0);
clk : IN std_logic
);
END COMPONENT;
COMPONENT uartrx
PORT (
clk : IN std_logic;
enable : IN std_logic;
rdn : IN std_logic;
resetn : IN std_logic;
rx : IN std_logic;
dbus : OUT std_logic_vector (7 DOWNTO 0);
ferror : OUT std_logic;
rdrf : OUT std_logic
);
END COMPONENT;
COMPONENT uarttx
PORT (
clk : in std_logic ;
enable : in std_logic ; -- 1 x bit_rate transmit clock enable
resetn : in std_logic ;
dbus : in std_logic_vector (7 downto 0); -- input to txshift register
tdre : out std_logic ;
wrn : in std_logic ;
tx : out std_logic);
END COMPONENT;
--Inputs
signal rx : std_logic := '0';
signal clk : std_logic := '0';
--BiDirs
signal W1A : std_logic_vector(15 downto 0);
signal W1B : std_logic_vector(15 downto 0);
signal W2C : std_logic_vector(15 downto 0);
--Outputs
signal tx : std_logic;
-- Clock period definitions
constant clk_period : time := 31.25 ns;
-- Architecture declarations
signal dind1_s : std_logic;
signal dind2_s : std_logic;
-- Internal signal declarations
SIGNAL CLOCK_40MHZ : std_logic := '0';
SIGNAL CTS : std_logic;
SIGNAL resetn : std_logic;
SIGNAL TXD : std_logic;
SIGNAL cpuerror : std_logic;
SIGNAL rdn_s : std_logic; -- Active Low Read Pulse (CLK)
SIGNAL rdrf : std_logic;
SIGNAL rxenable : std_logic;
SIGNAL txcmd : std_logic;
SIGNAL txenable : std_logic;
SIGNAL udbus : Std_Logic_Vector(7 DOWNTO 0);
CONSTANT DIVIDER_c : std_logic_vector(7 downto 0):="01000001"; -- 65, baudrate divider 40MHz
SIGNAL divtx_s : std_logic_vector(3 downto 0);
SIGNAL divcnt_s : std_logic_vector(7 downto 0);
SIGNAL rxclk16_s : std_logic;
SIGNAL tdre_s : std_logic;
SIGNAL wrn_s : std_logic;
SIGNAL char_s : std_logic_vector(7 downto 0);
BEGIN
CLOCK_40MHZ <= not CLOCK_40MHZ after 12.5 ns; -- 40MHz
process
variable L : line;
procedure write_to_uart (char_in : IN character) is
begin
char_s <=to_std_logic_vector(char_in);
wait until rising_edge(CLOCK_40MHZ);
wrn_s <= '0';
wait until rising_edge(CLOCK_40MHZ);
wrn_s <= '1';
wait until rising_edge(CLOCK_40MHZ);
wait until rising_edge(tdre_s);
end;
begin
CTS <= '1';
resetn <= '0'; -- PIN3 on Drigmorn1 connected to PIN2
wait for 100 ns;
resetn <= '1';
wrn_s <= '1'; -- Active low write strobe to TX UART
char_s <= (others => '1');
wait for 25.1 ms; -- wait for > prompt before issuing commands
write_to_uart('R');
wait for 47 ms; -- wait for > prompt before issuing commands
write_to_uart('D'); -- Issue Fill Memory command
write_to_uart('M');
write_to_uart('0');
write_to_uart('1');
write_to_uart('0');
write_to_uart('0');
wait for 1 ms;
write_to_uart('0');
write_to_uart('1');
write_to_uart('2');
write_to_uart('4');
wait for 50 ms; -- wait for > prompt before issuing commands
wait;
end process;
------------------------------------------------------------------------------
-- 8 bits divider
-- Generate rxenable clock (16 x baudrate)
------------------------------------------------------------------------------
process (CLOCK_40MHZ,resetn) -- First divider
begin
if (resetn='0') then
divcnt_s <= (others => '0');
rxclk16_s <= '0'; -- Receive clock (x16, pulse)
elsif (rising_edge(CLOCK_40MHZ)) then
if divcnt_s=DIVIDER_c then
divcnt_s <= (others => '0');
rxclk16_s <= '1';
else
rxclk16_s <= '0';
divcnt_s <= divcnt_s + '1';
end if;
end if;
end process;
rxenable <= rxclk16_s;
------------------------------------------------------------------------------
-- divider by 16
-- rxclk16/16=txclk
------------------------------------------------------------------------------
process (CLOCK_40MHZ,resetn)
begin
if (resetn='0') then
divtx_s <= (others => '0');
elsif (rising_edge(CLOCK_40MHZ)) then
if rxclk16_s='1' then
divtx_s <= divtx_s + '1';
if divtx_s="0000" then
txenable <= '1';
end if;
else
txenable <= '0';
end if;
end if;
end process;
assert not ((NOW > 0 ns) and cpuerror='1') report "**** CPU Error flag asserted ****" severity error;
------------------------------------------------------------------------------
-- UART Monitor
-- Display string on console after 80 characters or when CR character is received
------------------------------------------------------------------------------
process (rdrf,resetn)
variable L : line;
variable i_v : integer;
begin
if resetn='0' then
i_v := 0; -- clear character counter
elsif (rising_edge(rdrf)) then -- possible, pulse is wide!
if i_v=0 then
write(L,string'("RD UART : "));
if (udbus/=X"0D" and udbus/=X"0A") then
write(L,std_to_char(udbus));
end if;
i_v := i_v+1;
elsif (i_v=80 or udbus=X"0D") then
writeline(output,L);
i_v:=0;
else
if (udbus/=X"0D" and udbus/=X"0A") then
write(L,std_to_char(udbus));
end if;
i_v := i_v+1;
end if;
end if;
end process;
process (CLOCK_40MHZ,resetn) -- First/Second delay
begin
if (resetn='0') then
dind1_s <= '0';
dind2_s <= '0';
elsif (rising_edge(CLOCK_40MHZ)) then
dind1_s <= rdrf;
dind2_s <= dind1_s;
end if;
end process;
rdn_s <= '0' when (dind1_s='1' and dind2_s='0') else '1';
-- Instantiate the Unit Under Test (UUT)
uut: papilio1_top PORT MAP (
rx => rx,
tx => tx,
W1A => W1A,
W1B => W1B,
W2C => W2C,
clk => clk
);
w1b(1) <= resetn;
-- CTS => CTS,
TXD <= tx;
rx <= txcmd;
cpuerror <= w1b(0);
------------------------------------------------------------------------------
-- TX Uart
------------------------------------------------------------------------------
U_1 : uarttx
port map (
clk => CLOCK_40MHZ,
enable => txenable, -- default, working in simu but non-working in real-life ?
-- enable => rxenable,
resetn => resetn,
dbus => char_s,
tdre => tdre_s,
wrn => wrn_s,
tx => txcmd
);
------------------------------------------------------------------------------
-- RX Uart
------------------------------------------------------------------------------
U_2 : uartrx
PORT MAP (
clk => CLOCK_40MHZ,
enable => rxenable,
-- enable => txenable,
resetn => resetn,
dbus => udbus,
rdn => rdn_s,
rdrf => rdrf,
ferror => OPEN,
rx => TXD
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
END;
| gpl-2.0 | 3d7e0736723d63f781f8ce411294dcc9 | 0.417799 | 4.449771 | false | false | false | false |
hacklabmikkeli/knobs-galore | delta_sigma_dac_test.vhdl | 2 | 1,910 | --
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.common.all;
entity delta_sigma_dac_test is
end entity;
architecture delta_sigma_dac_test_impl of delta_sigma_dac_test is
signal THETA: ctl_signal := (others => '0');
signal Zctl: voice_signal := (others => '0');
signal Z: audio_signal := (others => '0');
signal CLK: std_logic := '1';
signal Vout: std_logic;
constant count: natural := 30;
begin
waveshaper_sin : entity work.waveshaper(waveshaper_sin)
port map ('1', CLK, THETA, Zctl, (others => '0'), open);
delta_sigma_dac : entity work.delta_sigma_dac(delta_sigma_dac_impl)
port map ('1', CLK, Z, Vout);
process begin
for k in 0 to ctl_max - 1 loop
THETA <= to_unsigned(k, ctl_bits);
for i in 1 to count loop
CLK <= not CLK;
wait for 1 ns;
end loop;
end loop;
assert false report "end of test" severity note;
wait;
end process;
Z <= (others => '0');
end architecture;
| gpl-3.0 | 3a7791801c86be5cc3f193358ac503e3 | 0.625654 | 3.70155 | false | true | false | false |
nsauzede/cpu86 | papilio2_lcd/divider_rtl_ser.vhd | 3 | 10,831 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY divider IS
GENERIC(
WIDTH_DIVID : integer := 32; -- Width Dividend
WIDTH_DIVIS : integer := 16; -- Width Divisor
WIDTH_SHORT : Integer := 8 -- Check Overflow against short Byte/Word
);
PORT(
clk : IN std_logic; -- System Clock
reset : IN std_logic; -- Active high
dividend : IN std_logic_vector (WIDTH_DIVID-1 DOWNTO 0);
divisor : IN std_logic_vector (WIDTH_DIVIS-1 DOWNTO 0);
quotient : OUT std_logic_vector (WIDTH_DIVIS-1 DOWNTO 0);
remainder : OUT std_logic_vector (WIDTH_DIVIS-1 DOWNTO 0);
twocomp : IN std_logic;
w : IN std_logic; -- UNUSED!
overflow : OUT std_logic;
start : IN std_logic;
done : OUT std_logic
);
END divider ;
ARCHITECTURE rtl_ser OF divider IS
signal dividend_s : std_logic_vector(WIDTH_DIVID downto 0);
signal divisor_s : std_logic_vector(WIDTH_DIVIS downto 0);
signal divis_rect_s : std_logic_vector(WIDTH_DIVIS-1 downto 0);
signal signquot_s : std_logic;
signal signremain_s : std_logic;
signal accumulator_s : std_logic_vector(WIDTH_DIVID downto 0);
signal aluout_s : std_logic_vector(WIDTH_DIVIS downto 0);
signal newaccu_s : std_logic_vector(WIDTH_DIVID downto 0);
signal quot_s : std_logic_vector (WIDTH_DIVIS-1 downto 0);
signal remain_s : std_logic_vector (WIDTH_DIVIS-1 downto 0);
constant null_s : std_logic_vector(31 downto 0) := X"00000000";
signal count_s : std_logic_vector (3 downto 0); -- Number of iterations
signal overflow_s : std_logic; --_vector (WIDTH_DIVIS downto 0);
signal sremainder_s : std_logic_vector (WIDTH_DIVIS-1 downto 0);
signal squotient_s : std_logic_vector (WIDTH_DIVIS-1 downto 0);
signal signfailure_s : std_logic;
signal zeroq_s : std_logic;
signal zeror_s : std_logic;
signal zerod_s : std_logic;
signal pos_s : std_logic;
signal neg_s : std_logic;
type states is (s0,s1,s2);
signal state,nextstate: states;
function rectifyd (r : in std_logic_vector (WIDTH_DIVID downto 0); -- Rectifier for dividend + 1 bit
twoc: in std_logic) -- Signed/Unsigned
return std_logic_vector is
variable rec_v : std_logic_vector (WIDTH_DIVID downto 0);
begin
if ((r(WIDTH_DIVID) and twoc)='1') then
rec_v := not(r);
else
rec_v := r;
end if;
return (rec_v + (r(WIDTH_DIVID) and twoc));
end;
function rectifys (r : in std_logic_vector (WIDTH_DIVIS-1 downto 0); -- Rectifier for divisor
twoc: in std_logic) -- Signed/Unsigned
return std_logic_vector is
variable rec_v : std_logic_vector (WIDTH_DIVIS-1 downto 0);
begin
if ((r(WIDTH_DIVIS-1) and twoc)='1') then
rec_v := not(r);
else
rec_v := r;
end if;
return (rec_v + (r(WIDTH_DIVIS-1) and twoc));
end;
begin
-- Sign Quotient
signquot_s <= (dividend(WIDTH_DIVID-1) xor divisor(WIDTH_DIVIS-1)) and twocomp;
-- Sign Remainder
signremain_s <= dividend(WIDTH_DIVID-1) and twocomp;
dividend_s <= '0'÷nd when twocomp='0' else rectifyd(dividend(WIDTH_DIVID-1)÷nd, twocomp);
divisor_s <= ('1'&divisor) when (divisor(WIDTH_DIVIS-1) and twocomp)='1' else not('0'&divisor) + '1';
-- Subtractor (Adder, WIDTH_DIVIS+1)
aluout_s <= accumulator_s(WIDTH_DIVID downto WIDTH_DIVID-WIDTH_DIVIS) + divisor_s;
-- Append Quotient section to aluout_s
newaccu_s <= aluout_s & accumulator_s(WIDTH_DIVID-WIDTH_DIVIS-1 downto 0);
process (clk,reset)
begin
if (reset='1') then
accumulator_s <= (others => '0');
elsif (rising_edge(clk)) then
if start='1' then
accumulator_s <= dividend_s(WIDTH_DIVID-1 downto 0) & '0'; -- Load Dividend in remainder +shl
elsif pos_s='1' then -- Positive, remain=shl(remain,1)
accumulator_s <= newaccu_s(WIDTH_DIVID-1 downto 0) & '1'; -- Use sub result
elsif neg_s='1' then -- Negative, shl(remainder,0)
accumulator_s <= accumulator_s(WIDTH_DIVID-1 downto 0) & '0';-- Use original remainder
end if;
end if;
end process;
-- 2 Process Control FSM
process (clk,reset)
begin
if (reset = '1') then
state <= s0;
count_s <= (others => '0');
elsif (rising_edge(clk)) then
state <= nextstate;
if (state=s1) then
count_s <= count_s - '1';
elsif (state=s0) then
count_s <= CONV_STD_LOGIC_VECTOR(WIDTH_DIVIS-1, 4); -- extra step CAN REDUCE BY 1 since DONE is latched!!
end if;
end if;
end process;
process(state,start,aluout_s,count_s)
begin
case state is
when s0 =>
pos_s <= '0';
neg_s <= '0';
if start='1' then
nextstate <= s1;
else
nextstate <= s0;
end if;
when s1 =>
neg_s <= aluout_s(WIDTH_DIVIS);
pos_s <= not(aluout_s(WIDTH_DIVIS));
if (count_s=null_s(3 downto 0)) then nextstate <= s2; -- Done
else nextstate <= s1; -- Next sub&shift
end if;
when s2=>
pos_s <= '0';
neg_s <= '0';
nextstate <= s0;
when others =>
pos_s <= '0';
neg_s <= '0';
nextstate <= s0;
end case;
end process;
-- Correct remainder (SHR,1)
remain_s <= accumulator_s(WIDTH_DIVID downto WIDTH_DIVID-WIDTH_DIVIS+1);
-- Overflow if remainder>divisor or divide by 0 or sign error. Change all to positive.
divis_rect_s <= rectifys(divisor, twocomp);
overflow_s <= '1' when ((remain_s>=divis_rect_s) or (zerod_s='1')) else '0';
-- bottom part of remainder is quotient
quot_s <= accumulator_s(WIDTH_DIVIS-1 downto 0);
-- Remainder Result
sremainder_s <= ((not(remain_s)) + '1') when signremain_s='1' else remain_s;
remainder <= sremainder_s;
-- Qotient Result
squotient_s <= ((not(quot_s)) + '1') when signquot_s='1' else quot_s;
quotient <= squotient_s;
-- Detect zero vector
zeror_s <= '1' when (twocomp='1' and sremainder_s=null_s(WIDTH_DIVIS-1 downto 0)) else '0';
zeroq_s <= '1' when (twocomp='1' and squotient_s=null_s(WIDTH_DIVIS-1 downto 0)) else '0';
zerod_s <= '1' when (divisor=null_s(WIDTH_DIVIS-1 downto 0)) else '0';
-- Detect Sign failure
signfailure_s <= '1' when (signquot_s='1' and squotient_s(WIDTH_DIVIS-1)='0' and zeroq_s='0') or
(signremain_s='1' and sremainder_s(WIDTH_DIVIS-1)='0' and zeror_s='0') else '0';
done <= '1' when state=s2 else '0';
overflow <= '1' when (overflow_s='1' or signfailure_s='1') else '0';
end architecture rtl_ser;
| gpl-2.0 | 3608b68eafbb190fa60eb397a6451740 | 0.461453 | 4.143458 | false | false | false | false |
kdgwill/VHDL_Verilog_Encryptions_And_Ciphers | VHDL_RC5/Basys2Encryption/hex2sevenseg.vhd | 1 | 1,774 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
-- Hexadecimal to 7 Segment Decoder for LED Display
ENTITY hex_7seg IS
PORT(
hex_digit : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
segment_a,
segment_b,
segment_c,
segment_d,
segment_e,
segment_f,
segment_g : OUT std_logic);
END hex_7seg;
ARCHITECTURE behavioral OF hex_7seg IS
SIGNAL segment_data : STD_LOGIC_VECTOR(6 DOWNTO 0);
BEGIN
PROCESS (Hex_digit)
-- HEX to 7 Segment Decoder for LED Display
BEGIN
-- Hex-digit is the four bit binary value to display in hexadecimal
CASE Hex_digit IS
WHEN "0000" =>
segment_data <= "0000001";
WHEN "0001" =>
segment_data <= "1001111";
WHEN "0010" =>
segment_data <= "0010010";
WHEN "0011" =>
segment_data <= "0000110";
WHEN "0100" =>
segment_data <= "1001100";
WHEN "0101" =>
segment_data <= "0100100";
WHEN "0110" =>
segment_data <= "0100000";
WHEN "0111" =>
segment_data <= "0001111";
WHEN "1000" =>
segment_data <= "0000000";
WHEN "1001" =>
segment_data <= "0000100";
WHEN "1010" =>
segment_data <= "0001000";
WHEN "1011" =>
segment_data <= "1100000";
WHEN "1100" =>
segment_data <= "0110001";
WHEN "1101" =>
segment_data <= "1000010";
WHEN "1110" =>
segment_data <= "0110000";
WHEN "1111" =>
segment_data <= "0111000";
WHEN OTHERS =>
segment_data <= "1111111";
END CASE;
END PROCESS;
-- extract segment data bits
-- LED driver circuit
segment_a <= segment_data(6);
segment_b <= segment_data(5);
segment_c <= segment_data(4);
segment_d <= segment_data(3);
segment_e <= segment_data(2);
segment_f <= segment_data(1);
segment_g <= segment_data(0);
END behavioral; | lgpl-2.1 | 40e3f8cd723ea729136de5ada5678d60 | 0.620068 | 3.017007 | false | false | false | false |
nsauzede/cpu86 | p2_lcd_spi/lcdctl.vhd | 1 | 4,704 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity lcdctl is
Port ( clk,reset : in STD_LOGIC;
vramaddr : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
vramdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ud : out STD_LOGIC;
rl : out STD_LOGIC;
enab : out STD_LOGIC;
vsync : out STD_LOGIC;
hsync : out STD_LOGIC;
ck : out STD_LOGIC;
r : out std_logic_vector(5 downto 0);
g : out std_logic_vector(5 downto 0);
b : out std_logic_vector(5 downto 0)
);
end lcdctl;
architecture Behavioral of lcdctl is
signal clk_fast : std_logic := '0';
signal ired : std_logic_vector(5 downto 0) := "000000";
signal igreen : std_logic_vector(5 downto 0) := "000000";
signal iblue : std_logic_vector(5 downto 0) := "000000";
signal fg_r : std_logic_vector(5 downto 0) := "000000";
signal fg_g : std_logic_vector(5 downto 0) := "000000";
signal fg_b : std_logic_vector(5 downto 0) := "000000";
signal bg_r : std_logic_vector(5 downto 0) := "000000";
signal bg_g : std_logic_vector(5 downto 0) := "000000";
signal bg_b : std_logic_vector(5 downto 0) := "000000";
signal lcdvsync : STD_LOGIC;
signal lcdhsync : STD_LOGIC;
signal char_addr: std_logic_vector(6 downto 0);
signal char_attr: std_logic_vector(7 downto 0) := x"42";
signal attr_not_char: std_logic := '1';
signal rom_addr: std_logic_vector(10 downto 0);
signal row_addr: std_logic_vector(3 downto 0);
signal bit_addr: std_logic_vector(2 downto 0);
signal font_word: std_logic_vector(7 downto 0);
signal font_bit: std_logic;
signal video_on: std_logic;
signal dout: std_logic_vector(7 downto 0) := "01100010";
signal addr_read: std_logic_vector(12 downto 0);
signal pixel_x, pixel_y: std_logic_vector(9 downto 0);
signal ipixel_x, ipixel_y: std_logic_vector(9 downto 0);
begin
ud <= '1';
rl <= '1';
enab <= '0';
ck <= clk_fast;
r <= ired;
g <= igreen;
b <= iblue;
hsync<=lcdhsync;
vsync<=lcdvsync;
sync0: entity work.vga_sync
port map(
clock=>clk_fast,
reset=>reset,
hsync=>lcdhsync, vsync=>lcdvsync,
video_on=>video_on,
pixel_tick=>open,
pixel_x=>pixel_x, pixel_y=>pixel_y
);
-- instantiate frame buffer
-- frame_buffer_unit: entity work.blk_mem_gen_v7_3
-- port map (
-- clka => clk,
-- wea => (others => '0'),
-- addra => (others => '0'),
-- dina => (others => '0'),
-- clkb => clk,
-- addrb => addr_read,
-- doutb => dout
-- );
vramaddr <= "111" & addr_read;
dout <= vramdata;
-- instantiate font ROM
font_unit: entity work.font_rom
port map(
clock => clk_fast,
addr => rom_addr,
data => font_word
);
-- tile RAM read
-- addr_read <= ((pixel_y(9 downto 4) & "000000") + ("00" & pixel_y(9 downto 4) & "0000") + ("00000" & pixel_x(9 downto 3))) & attr_not_char;
addr_read <= ((pixel_y(9 downto 4) * "000101") + ("00000" & pixel_x(9 downto 3))) & attr_not_char;
-- addr_read <= pixel_y(8 downto 4) & pixel_x(9 downto 3) & attr_not_char; -- ok but stride=256 instead of 80*2=160
process(clk,clk_fast,video_on)
begin
if rising_edge(clk) then
if video_on='0' then
attr_not_char <= '0';
clk_fast <= '0';
else
if clk_fast='0' then
char_attr <= dout(7 downto 0);
attr_not_char <= '1';
else
char_addr <= dout(6 downto 0);
attr_not_char <= '0';
end if;
end if;
clk_fast <= not clk_fast;
end if;
end process;
fg_r <= (others => '1') when char_attr(0)='1' else (others => '0');
fg_g <= (others => '1') when char_attr(1)='1' else (others => '0');
fg_b <= (others => '1') when char_attr(2)='1' else (others => '0');
bg_r <= (others => '1') when char_attr(3)='1' else (others => '0');
bg_g <= (others => '1') when char_attr(4)='1' else (others => '0');
bg_b <= (others => '1') when char_attr(5)='1' else (others => '0');
-- font ROM interface
row_addr <= pixel_y(3 downto 0);
rom_addr <= char_addr & row_addr;
-- bit_addr <= std_logic_vector(unsigned(pixel_x(2 downto 0)) - 1);
bit_addr <= std_logic_vector(unsigned(pixel_x(2 downto 0))-2);
font_bit <= font_word(to_integer(unsigned(not bit_addr)));
-- rgb multiplexing
process(font_bit,video_on,fg_r,fg_g,fg_b,bg_r,bg_g,bg_b)
begin
if video_on='0' then
ired <= (others => '0');
igreen <= (others => '0');
iblue <= (others => '0');
elsif font_bit = '1' then
ired <= fg_r;
igreen <= fg_g;
iblue <= fg_b;
-- ired <= (others => '1');
-- igreen <= (others => '1');
-- iblue <= (others => '1');
else
ired <= bg_r;
igreen <= bg_g;
iblue <= bg_b;
-- ired <= (others => '0');
-- igreen <= (others => '0');
-- iblue <= (others => '0');
end if;
end process;
end Behavioral;
| gpl-2.0 | 0a6dcf963978d7abee478b005950abba | 0.59375 | 2.686465 | false | false | false | false |
nsauzede/cpu86 | p2_vga_spi/ipcore_dir/blk_mem_40K.vhd | 1 | 6,130 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2020 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file blk_mem_40K.vhd when simulating
-- the core, blk_mem_40K. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY blk_mem_40K IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END blk_mem_40K;
ARCHITECTURE blk_mem_40K_a OF blk_mem_40K IS
-- synthesis translate_off
COMPONENT wrapped_blk_mem_40K
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_blk_mem_40K USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 16,
c_addrb_width => 16,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 1,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "blk_mem_40K.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 2,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 65536,
c_read_depth_b => 65536,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 65536,
c_write_depth_b => 65536,
c_write_mode_a => "READ_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_blk_mem_40K
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb
);
-- synthesis translate_on
END blk_mem_40K_a;
| gpl-2.0 | f3b18822c2fd68aa5b9fef0939d438cd | 0.537357 | 3.816936 | false | false | false | false |
nsauzede/cpu86 | papilio2_vga/vga_sync.vhd | 2 | 3,571 | --
-- Copyright 2011, Kevin Lindsey
-- See LICENSE file for licensing information
--
-- Based on code from P. P. Chu, "FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version", 2008
-- Chapters 12-13
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vga_sync is
port(
clock: in std_logic;
reset: in std_logic;
hsync, vsync: out std_logic;
video_on: out std_logic;
pixel_tick: out std_logic;
pixel_x, pixel_y: out std_logic_vector(9 downto 0)
);
end vga_sync;
architecture arch of vga_sync is
-- VGA 640x480
-- horizontal timings, in pixels
constant h_display_area: integer := 640;
constant h_front_porch: integer := 16;
constant h_sync: integer := 96;
constant h_back_porch: integer := 48;
-- vertical timings, in lines
constant v_display_area: integer := 480;
constant v_front_porch: integer := 10;
constant v_sync: integer := 2;
constant v_back_porch: integer := 33;
-- derived horizontal constants
constant hsync_start: integer := h_display_area + h_front_porch;
constant hsync_end: integer := hsync_start + h_sync;
constant end_of_line: integer := hsync_end + h_back_porch - 1;
-- derived vertical constants
constant vsync_start: integer := v_display_area + v_front_porch;
constant vsync_end: integer := vsync_start + v_sync;
constant end_of_frame: integer := vsync_start + v_back_porch - 1;
-- mod-2 counter
signal mod2_reg, mod2_next: std_logic;
-- sync counters
signal v_count_reg, v_count_next: unsigned(9 downto 0);
signal h_count_reg, h_count_next: unsigned(9 downto 0);
-- output buffer
signal v_sync_reg, h_sync_reg: std_logic;
signal v_sync_next, h_sync_next: std_logic;
-- status signals
signal h_end, v_end, p_tick: std_logic;
begin
-- registers
process(clock, reset)
begin
if reset = '1' then
mod2_reg <= '0';
v_count_reg <= (others => '0');
h_count_reg <= (others => '0');
v_sync_reg <= '0';
h_sync_reg <= '0';
elsif clock'event and clock = '1' then
mod2_reg <= mod2_next;
v_count_reg <= v_count_next;
h_count_reg <= h_count_next;
v_sync_reg <= v_sync_next;
h_sync_reg <= h_sync_next;
end if;
end process;
-- mod-2 circuit to generate 25.125MHz enable tick
mod2_next <= not mod2_reg;
-- 25.125MHz pixel tick
p_tick <= '1' when mod2_reg = '1' else '0';
-- status
h_end <=
'1' when h_count_reg = end_of_line else
'0';
v_end <=
'1' when v_count_reg = end_of_frame else
'0';
-- mod-800 horizontal sync counter
process(h_count_reg, h_end, p_tick)
begin
if p_tick = '1' then
if h_end = '1' then
h_count_next <= (others => '0');
else
h_count_next <= h_count_reg + 1;
end if;
else
h_count_next <= h_count_reg;
end if;
end process;
-- mod-525 vertical sync counter
process(v_count_reg, h_end, v_end, p_tick)
begin
if p_tick = '1' and h_end = '1' then
if v_end = '1' then
v_count_next <= (others => '0');
else
v_count_next <= v_count_reg + 1;
end if;
else
v_count_next <= v_count_reg;
end if;
end process;
-- hsync and vsync, buffered to avoid glitch
h_sync_next <=
'1' when hsync_start <= h_count_reg and h_count_reg < hsync_end else
'0';
v_sync_next <=
'1' when vsync_start <= v_count_reg and v_count_reg < vsync_end else
'0';
-- video on/off
video_on <=
'1' when h_count_reg < h_display_area and v_count_reg < v_display_area else
'0';
-- output signals
hsync <= h_sync_reg;
vsync <= v_sync_reg;
pixel_x <= std_logic_vector(h_count_reg);
pixel_y <= std_logic_vector(v_count_reg);
pixel_tick <= p_tick;
end arch;
| gpl-2.0 | d34698221828caaba3e6c98ecd9ec953 | 0.642397 | 2.67892 | false | false | false | false |
nsauzede/cpu86 | papilio2_lcd/dataregfile_rtl.vhd | 3 | 10,670 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
USE work.cpu86pack.ALL;
ENTITY dataregfile IS
PORT(
dibus : IN std_logic_vector (15 DOWNTO 0);
selalua : IN std_logic_vector (3 DOWNTO 0);
selalub : IN std_logic_vector (3 DOWNTO 0);
seldreg : IN std_logic_vector (2 DOWNTO 0);
w : IN std_logic;
wrd : IN std_logic;
alu_inbusa : OUT std_logic_vector (15 DOWNTO 0);
alu_inbusb : OUT std_logic_vector (15 DOWNTO 0);
bp_s : OUT std_logic_vector (15 DOWNTO 0);
bx_s : OUT std_logic_vector (15 DOWNTO 0);
di_s : OUT std_logic_vector (15 DOWNTO 0);
si_s : OUT std_logic_vector (15 DOWNTO 0);
reset : IN std_logic;
clk : IN std_logic;
data_in : IN std_logic_vector (15 DOWNTO 0);
mdbus_in : IN std_logic_vector (15 DOWNTO 0);
sp_s : OUT std_logic_vector (15 DOWNTO 0);
ax_s : OUT std_logic_vector (15 DOWNTO 0);
cx_s : OUT std_logic_vector (15 DOWNTO 0);
dx_s : OUT std_logic_vector (15 DOWNTO 0)
);
END dataregfile ;
architecture rtl of dataregfile is
signal axreg_s : std_logic_vector(15 downto 0);
signal cxreg_s : std_logic_vector(15 downto 0);
signal dxreg_s : std_logic_vector(15 downto 0);
signal bxreg_s : std_logic_vector(15 downto 0);
signal spreg_s : std_logic_vector(15 downto 0);
signal bpreg_s : std_logic_vector(15 downto 0);
signal sireg_s : std_logic_vector(15 downto 0);
signal direg_s : std_logic_vector(15 downto 0);
signal seldreg_s : std_logic_vector(3 downto 0); -- w & seldreg
signal selalua_s : std_logic_vector(4 downto 0); -- w & dibus & selalua
signal selalub_s : std_logic_vector(4 downto 0); -- w & dibus & selalub
signal alu_inbusb_s: std_logic_vector (15 downto 0);
begin
----------------------------------------------------------------------------
-- 8 registers of 16 bits each
----------------------------------------------------------------------------
seldreg_s <= w & seldreg;
process (clk,reset)
begin
if reset='1' then
axreg_s <= (others => '0');
cxreg_s <= (others => '0');
dxreg_s <= (others => '0');
bxreg_s <= (others => '0');
spreg_s <= (others => '0');
bpreg_s <= (others => '0');
sireg_s <= (others => '0');
direg_s <= (others => '0');
elsif rising_edge(clk) then
if (wrd='1') then
case seldreg_s is
when "0000" => axreg_s(7 downto 0) <= dibus(7 downto 0); -- w=0 8 bits write
when "0001" => cxreg_s(7 downto 0) <= dibus(7 downto 0);
when "0010" => dxreg_s(7 downto 0) <= dibus(7 downto 0);
when "0011" => bxreg_s(7 downto 0) <= dibus(7 downto 0);
when "0100" => axreg_s(15 downto 8) <= dibus(7 downto 0);
when "0101" => cxreg_s(15 downto 8) <= dibus(7 downto 0);
when "0110" => dxreg_s(15 downto 8) <= dibus(7 downto 0);
when "0111" => bxreg_s(15 downto 8) <= dibus(7 downto 0);
when "1000" => axreg_s <= dibus; -- w=1 16 bits write
when "1001" => cxreg_s <= dibus;
when "1010" => dxreg_s <= dibus;
when "1011" => bxreg_s <= dibus;
when "1100" => spreg_s <= dibus;
when "1101" => bpreg_s <= dibus;
when "1110" => sireg_s <= dibus;
when others => direg_s <= dibus;
end case;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Output Port A
----------------------------------------------------------------------------
selalua_s <= w & selalua;
process (selalua_s,axreg_s,cxreg_s,dxreg_s,bxreg_s,spreg_s,bpreg_s,sireg_s,direg_s,mdbus_in)
begin
case selalua_s is
when "00000" => alu_inbusa <= X"00" & axreg_s(7 downto 0); -- Select 8 bits MSB=0
when "00001" => alu_inbusa <= X"00" & cxreg_s(7 downto 0);
when "00010" => alu_inbusa <= X"00" & dxreg_s(7 downto 0);
when "00011" => alu_inbusa <= X"00" & bxreg_s(7 downto 0);
when "00100" => alu_inbusa <= X"00" & axreg_s(15 downto 8); -- AH
when "00101" => alu_inbusa <= X"00" & cxreg_s(15 downto 8); -- CH
when "00110" => alu_inbusa <= X"00" & dxreg_s(15 downto 8); -- DH
when "00111" => alu_inbusa <= X"00" & bxreg_s(15 downto 8); -- BH
when "10000" => alu_inbusa <= axreg_s;
when "10001" => alu_inbusa <= cxreg_s;
when "10010" => alu_inbusa <= dxreg_s;
when "10011" => alu_inbusa <= bxreg_s;
when "10100" => alu_inbusa <= spreg_s;
when "10101" => alu_inbusa <= bpreg_s;
when "10110" => alu_inbusa <= sireg_s;
when "10111" => alu_inbusa <= direg_s;
when others => alu_inbusa <= mdbus_in(15 downto 0); -- Pass through
end case;
end process;
----------------------------------------------------------------------------
-- Output Port B
----------------------------------------------------------------------------
selalub_s <= w & selalub;
process (selalub_s,axreg_s,cxreg_s,dxreg_s,bxreg_s,spreg_s,bpreg_s,sireg_s,direg_s,mdbus_in,data_in)
begin
case selalub_s is
when "00000" => alu_inbusb_s <= X"00" & axreg_s(7 downto 0);
when "00001" => alu_inbusb_s <= X"00" & cxreg_s(7 downto 0);
when "00010" => alu_inbusb_s <= X"00" & dxreg_s(7 downto 0);
when "00011" => alu_inbusb_s <= X"00" & bxreg_s(7 downto 0);
when "00100" => alu_inbusb_s <= X"00" & axreg_s(15 downto 8);
when "00101" => alu_inbusb_s <= X"00" & cxreg_s(15 downto 8);
when "00110" => alu_inbusb_s <= X"00" & dxreg_s(15 downto 8);
when "00111" => alu_inbusb_s <= X"00" & bxreg_s(15 downto 8);
when "10000" => alu_inbusb_s <= axreg_s;
when "10001" => alu_inbusb_s <= cxreg_s;
when "10010" => alu_inbusb_s <= dxreg_s;
when "10011" => alu_inbusb_s <= bxreg_s;
when "10100" => alu_inbusb_s <= spreg_s;
when "10101" => alu_inbusb_s <= bpreg_s;
when "10110" => alu_inbusb_s <= sireg_s;
when "10111" => alu_inbusb_s <= direg_s;
when "01000" => alu_inbusb_s <= X"00"& data_in(7 downto 0); -- Pass data_in to ALU (port B only)
when "11000" => alu_inbusb_s <= data_in; -- Pass data_in to ALU (port B only)
when "01001" => alu_inbusb_s <= X"0001"; -- Used for INC/DEC byte function
when "11001" => alu_inbusb_s <= X"0001"; -- Used for INC/DEC word function
when "11010" => alu_inbusb_s <= X"0002"; -- Used for POP/PUSH function
when others => alu_inbusb_s <= mdbus_in(15 downto 0); -- Pass through
end case;
end process;
alu_inbusb <= alu_inbusb_s; -- connect to entity
bx_s <= bxreg_s; -- Used for EA calculation
bp_s <= bpreg_s;
si_s <= sireg_s;
di_s <= direg_s;
sp_s <= spreg_s; -- Used for eamux, PUSH and POP instructions
ax_s <= axreg_s; -- Used for datapath FSM
cx_s <= cxreg_s;
dx_s <= dxreg_s; -- Used for IN/OUT instructions & Divider
end rtl;
| gpl-2.0 | be37590e06be41b8bc26e63759177262 | 0.434114 | 3.943089 | false | false | false | false |
andykarpov/radio-86rk-wxeda | src/keyboard/Keyboard.vhd | 1 | 1,302 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Keyboard is
port (Reset : in STD_LOGIC;
Clock : in STD_LOGIC;
PS2Clock : inout STD_LOGIC;
PS2Data : inout STD_LOGIC;
CodeReady : out STD_LOGIC;
ScanCode : out STD_LOGIC_VECTOR(9 downto 0));
end Keyboard;
architecture Behavioral of Keyboard is
signal Send : STD_LOGIC;
signal Command : STD_LOGIC_VECTOR(7 downto 0);
signal PS2Busy : STD_LOGIC;
signal PS2Error : STD_LOGIC;
signal DataReady : STD_LOGIC;
signal DataByte : STD_LOGIC_VECTOR(7 downto 0);
begin
PS2_Controller: entity work.PS2Controller
port map (Reset => Reset,
Clock => Clock,
PS2Clock => PS2Clock,
PS2Data => PS2Data,
Send => Send,
Command => Command,
PS2Busy => PS2Busy,
PS2Error => PS2Error,
DataReady => DataReady,
DataByte => DataByte);
Keyboard_Mapper: entity work.KeyboardMapper
port map (Clock => Clock,
Reset => Reset,
PS2Busy => PS2Busy,
PS2Error => PS2Error,
DataReady => DataReady,
DataByte => DataByte,
Send => Send,
Command => Command,
CodeReady => CodeReady,
ScanCode => ScanCode);
end Behavioral;
| bsd-2-clause | 651b39931fa805f2a8cd075b18a70baf | 0.620584 | 3.417323 | false | false | false | false |
kdgwill/VHDL_Verilog_Encryptions_And_Ciphers | VHDL_RC5/Basys2Encryption/ARCHIVE/rc5.bak.2.vhd | 1 | 11,593 | --RC5 Encryption
--A = A + S[0];
--B = B + S[1];
--for i=1 to 12 do
----A = ((A XOR B) <<< B) + S[2*i];
----B = ((B XOR A) <<< A) + S[2*1+1];
--RC5 Decryption
--for i=12 to 1 do
----B = ((B - S[2×i +1]) >>> A) xor A;
----A = ((A - S[2×i]) >>> B) xor B;
--B = B - S[1];
--A = A - S[0];
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; -- we will use CONV_INTEGER
ENTITY rc5 IS
PORT (
-- Asynchronous reset and 25HzClock Signal
clr,clk_25 : IN STD_LOGIC;
--0 for encryption 1 for decryption
enc : IN STD_LOGIC;
-- 8-bit input
din_lower : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-- Input is Valid
di_vld : IN STD_LOGIC;
-- 7 Segment Display-bit output
segment_a_i : OUT STD_LOGIC;
segment_b_i : OUT STD_LOGIC;
segment_c_i : OUT STD_LOGIC;
segment_d_i : OUT STD_LOGIC;
segment_e_i : OUT STD_LOGIC;
segment_f_i : OUT STD_LOGIC;
segment_g_i : OUT STD_LOGIC;
-- 7 Segment Control
--Control Which of the four 7-Segment Display is active
AN : OUT STD_LOGIC_VECTOR(3 downto 0);
--Output is Ready
do_rdy : OUT STD_LOGIC;
--In Decryption Mode
dec_mode : OUT STD_LOGIC
);
END rc5;
ARCHITECTURE rtl OF rc5 IS
SIGNAL din : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL i_cnt : STD_LOGIC_VECTOR(3 DOWNTO 0); -- round counter
SIGNAL r_cnt : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL ab_xor : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_rot_left : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_rot_right : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_round : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); -- register A
SIGNAL a_enc : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_dec : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL ab_xor_enc : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL ab_xor_dec : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_round_enc : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_round_dec : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL ba_xor : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_rot_left : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_rot_right : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_round : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); -- register B
SIGNAL b_enc : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_dec : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL ba_xor_enc : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL ba_xor_dec : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_round_enc : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_round_dec : STD_LOGIC_VECTOR(31 DOWNTO 0);
type rc5_rom_26 is array (0 to 25) of std_logic_vector(31 downto 0);
CONSTANT skey :rc5_rom_26:=rc5_rom_26'(
X"9BBBD8C8", X"1A37F7FB", X"46F8E8C5", X"460C6085",
X"70F83B8A", X"284B8303", X"513E1454", X"F621ED22",
X"3125065D", X"11A83A5D", X"D427686B", X"713AD82D",
X"4B792F99", X"2799A4DD", X"A7901C49", X"DEDE871A",
X"36C03196", X"A7EFC249", X"61A78BB8", X"3B0A1D2B",
X"4DBFCA76", X"AE162167", X"30D76B0A", X"43192304",
X"F6CC1431", X"65046380");
-- RC5 state machine has five states: idle, pre_round, round and ready
TYPE StateType IS(
ST_IDLE, -- In this state RC5 is ready for input
ST_PRE_ROUND, -- In this state RC5 pre-round op is performed
ST_ROUND_OP, -- In this state RC5 round op is performed. 12 rounds
ST_POST_ROUND, -- In this state RC5 post-round op is performed
ST_READY -- In this state RC5 has completed encryption
);
SIGNAL state : StateType;
--LED Control
SIGNAL hex_digit_i : STD_LOGIC_VECTOR(3 DOWNTO 0);
--Count to flash the LED
SIGNAL LED_flash_cnt : STD_LOGIC_VECTOR(9 DOWNTO 0);
BEGIN
din <= X"00000000000000" & din_lower;
VAL_GEN:
PROCESS(clr,clk_25,
a_round ,
b_round ,
ab_xor ,
ba_xor ,
a ,
b ,
a_round_enc,
a_round_dec,
b_round_enc,
b_round_dec,
ab_xor_enc ,
ab_xor_dec ,
ba_xor_enc ,
ba_xor_dec ,
a_enc ,
a_dec ,
b_enc ,
b_dec )BEGIN
IF(clr='1') THEN
a_round_enc <= (others=> '0');
a_round_dec <= (others=> '0');
b_round_enc <= (others=> '0');
b_round_dec <= (others=> '0');
ab_xor_enc <= (others=> '0');
ab_xor_dec <= (others=> '0');
ba_xor_enc <= (others=> '0');
ba_xor_dec <= (others=> '0');
a_enc <= (others=> '0');
a_dec <= (others=> '0');
b_enc <= (others=> '0');
b_dec <= (others=> '0');
ELSIF(rising_edge(clk_25)) THEN
IF(enc='0')THEN
a_round_enc <= din(63 DOWNTO 32) + skey(0);
b_round_enc <= din(31 DOWNTO 0) + skey(1);
ab_xor_enc <= a_reg XOR b_reg;
ba_xor_enc <= b_reg XOR a;
a_enc <= a_rot_left + skey(CONV_INTEGER(i_cnt & '0')); --A + S[2*i]
b_enc <= b_rot_left + skey(CONV_INTEGER(i_cnt & '1'));--B + S[2*i+1]
a_round_dec <= (others=>'0');
b_round_dec <= (others=>'0');
ab_xor_dec <= (others=>'0');
ba_xor_dec <= (others=>'0');
a_dec <= (others=>'0');
b_dec <= (others=>'0');
ELSE
a_round_enc <= (others=>'0');
b_round_enc <= (others=>'0');
ab_xor_enc <= (others=>'0');
ba_xor_enc <= (others=>'0');
a_enc <= (others=>'0');
b_enc <= (others=>'0');
a_round_dec <= a_reg - skey(0);
b_round_dec <= b_reg - skey(1);
ab_xor_dec <= a_rot_right XOR ba_xor;
ba_xor_dec <= b_rot_right XOR a_reg;
a_dec <= a_reg - skey(CONV_INTEGER(i_cnt & '0')); -- A - S[2*i]
b_dec <= b_reg - skey(CONV_INTEGER(i_cnt & '1')); --B - S[2*i+1]
END IF;
END IF;
END PROCESS;
VAL_ASSIGN:
PROCESS(clr,clk_25,
a_round ,
b_round ,
ab_xor ,
ba_xor ,
a ,
b ,
a_round_enc,
a_round_dec,
b_round_enc,
b_round_dec,
ab_xor_enc ,
ab_xor_dec ,
ba_xor_enc ,
ba_xor_dec ,
a_enc ,
a_dec ,
b_enc ,
b_dec
)BEGIN
IF(clr='1') THEN
a_round <= (others=>'0');
b_round <= (others=>'0');
ab_xor <= (others=>'0');
ba_xor <= (others=>'0');
a <= (others=>'0');
b <= (others=>'0');
ELSIF(rising_edge(clk_25)) THEN
IF(enc='0')THEN
a_round <= a_round_enc;--A = A + S[0]
b_round <= b_round_enc;--B = B + S[1]
ab_xor <= ab_xor_enc; --A XOR B
ba_xor <= ba_xor_enc;--B XOR A
a <= a_enc;
b <= b_enc;
ELSE
a_round <= a_round_dec;--A = A - S[0]
b_round <= b_round_dec;--B = B - S[1]
ab_xor <= ab_xor_dec;--A XOR B
ba_xor <= ba_xor_dec; --B XOR A
a <= a_dec;
b <= b_dec;
END IF;
END IF;
END PROCESS;
----------------------ENCRYPTION
ROT_A_LEFT : ENTITY work.rotLeft
PORT MAP(clk=>clk_25, clr=>clr, din=>ab_xor_enc, amnt=>b_reg(4 DOWNTO 0),dout=>a_rot_left);--A <<< B
ROT_B_LEFT : ENTITY work.rotLeft
PORT MAP(clk=>clk_25, clr=>clr, din=>ba_xor_enc, amnt=>a_enc(4 DOWNTO 0),dout=>b_rot_left); --B <<< A
------------------------DECRYPTION
ROT_B_RIGHT : ENTITY work.rotRight
PORT MAP(clk=>clk_25, clr=>clr, din=>b_dec, amnt=>a_reg(4 DOWNTO 0),dout=>b_rot_right); --B >>> A
ROT_A_RIGHT : ENTITY work.rotRight
PORT MAP(clk=>clk_25, clr=>clr, din=>a_dec, amnt=>ba_xor_dec(4 DOWNTO 0),dout=>a_rot_right); --A >>> B
A_register:
PROCESS(clr, clk_25) BEGIN
IF(clr='1') THEN
a_reg<=din(63 DOWNTO 32);
ELSIF(rising_edge(clk_25)) THEN
IF(state=ST_PRE_ROUND OR state=ST_POST_ROUND) THEN
a_reg<=a_round;
ELSIF(state=ST_ROUND_OP) THEN
if(enc = '0')then
a_reg<=a;
else
a_reg<=ab_xor;
end if;
END IF;
END IF;
END PROCESS;
B_register:
PROCESS(clr, clk_25) BEGIN
IF(clr='1') THEN
b_reg<=din(31 DOWNTO 0);
ELSIF(rising_edge(clk_25)) THEN
IF(state=ST_PRE_ROUND OR state=ST_POST_ROUND) THEN
b_reg<=b_round;
ELSIF(state=ST_ROUND_OP) THEN
if(enc = '0')then
b_reg<=b;
else
b_reg<=ba_xor;
end if;
END IF;
END IF;
END PROCESS;
State_Control:
PROCESS(clr, clk_25)
BEGIN
IF(clr='1') THEN
state<=ST_IDLE;
ELSIF(rising_edge(clk_25)) THEN
CASE state IS
WHEN ST_IDLE=> IF(di_vld='1') THEN
IF(enc = '0') THEN
state<=ST_PRE_ROUND;
ELSE
state<=ST_ROUND_OP;
END IF;
END IF;
WHEN ST_PRE_ROUND=> state<=ST_ROUND_OP;--Left because makes sense
WHEN ST_ROUND_OP=> IF(enc = '0') THEN
IF(i_cnt="1100") THEN
state<=ST_READY;
END IF;
ELSE
IF(i_cnt="0001") THEN
state<=ST_POST_ROUND;
END IF;
END IF;
WHEN ST_POST_ROUND=> state<=ST_READY; --Left because makes sense
WHEN ST_READY=> IF(di_vld='1') THEN
state<=ST_IDLE;
END IF;
END CASE;
END IF;
END PROCESS;
round_counter:
PROCESS(clk_25,clr) BEGIN
IF(clr='1') THEN
i_cnt<="0001";
r_cnt<="0001";
ELSIF(rising_edge(clk_25)) THEN
IF (state=ST_ROUND_OP) THEN
if(enc='0')then
IF(i_cnt="1100") THEN
i_cnt<="0001";
r_cnt<="0001";
ELSIF(r_cnt=X"4")THEN
i_cnt<=i_cnt+'1';
r_cnt <= X"1";
ELSE
r_cnt <= r_cnt + '1';
END IF;
else
IF(i_cnt="0001") THEN
i_cnt<="1100";
r_cnt<="0001";
ELSIF(r_cnt=X"7")THEN
i_cnt<=i_cnt-'1';
r_cnt <= X"1";
ELSE
r_cnt <= r_cnt + '1';
END IF;
END IF;
ELSIF(state=ST_PRE_ROUND)THEN
i_cnt<="0001";
r_cnt<="0001";
ELSIF(state=ST_IDLE OR state = ST_READY)THEN
i_cnt<="1100";
r_cnt<="0001";
END IF;
END IF;
END PROCESS;
dout<=a_reg & b_reg;
WITH state SELECT
do_rdy<='1' WHEN ST_READY,
'0' WHEN OTHERS;
dec_mode <= enc;
-------------------------------------------------
-------------------LED CONTROL-------------------
-------------------------------------------------
--hex to 7 Segment Display
hex2_7seg : ENTITY work.hex_7seg
--This is a new effective way to instantiate
--Rolls component and port map together
PORT MAP(
hex_digit => hex_digit_i,
segment_a => segment_a_i,
segment_b => segment_b_i,
segment_c => segment_c_i,
segment_d => segment_d_i,
segment_e => segment_e_i,
segment_f => segment_f_i,
segment_g => segment_g_i
);
--Flash the LED with the last 4 bytes of dout
PROCESS(clr,clk_25)
BEGIN
IF(clr='1')THEN
hex_digit_i <= (others => '0');
LED_flash_cnt <= (others => '0');
AN <= (others => '1');--All LED OFF
ELSIF(rising_edge(clk_25)) THEN
LED_flash_cnt <= LED_flash_cnt + '1';
CASE LED_flash_cnt(9 downto 8) IS
when "00" =>
--First 7-Seg-LED
hex_digit_i <= dout(15 downto 12);--LED output
AN <= "0111"; --Enables LED
when "01" =>
--Second 7-Seg-LED
hex_digit_i <= dout(11 downto 8);
AN <= "1011";
when "10" =>
--Third 7-Seg-LED
hex_digit_i <= dout(7 downto 4);
AN <= "1101";
when "11" =>
--Fourth 7-Seg-LED
hex_digit_i <= dout(3 downto 0);
AN <= "1110";
when others => null;
END CASE;
END IF;
END PROCESS;
END rtl;
| lgpl-2.1 | 3c95be7167ab202469ed710e285935b5 | 0.526007 | 2.627011 | false | false | false | false |
nsauzede/cpu86 | papilio2/aaatop.vhd | 1 | 9,350 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:17:25 02/11/2015
-- Design Name:
-- Module Name: aaatop - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
----------------------------------------------------------------------------------
-- LED example, by Jerome Cornet
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity Aaatop is
Port (
CLK : in STD_LOGIC;
txd : inout std_logic;
rxd : in std_logic;
ARD_RESET : out STD_LOGIC;
DUO_SW1 : in STD_LOGIC;
-- DUO_LED : out std_logic;
sram_addr : out std_logic_vector(20 downto 0);
sram_data : inout std_logic_vector(7 downto 0);
sram_ce : out std_logic;
sram_we : out std_logic;
sram_oe : out std_logic;
Arduino : inout STD_LOGIC_VECTOR (53 downto 0)
);
end Aaatop;
architecture Behavioral of Aaatop is
signal CLOCK_40MHZ : std_logic;
signal CTS : std_logic := '1';
signal PIN3 : std_logic;
signal LED1 : std_logic;
signal LED2N : std_logic;
signal LED3N : std_logic;
signal PIN4 : std_logic;
signal RTS : std_logic;
component clk32to40
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end component;
-- Architecture declarations
signal csromn : std_logic := '1';
signal csesramn : std_logic;
-- Internal signal declarations
SIGNAL DCDn : std_logic := '1';
SIGNAL DSRn : std_logic := '1';
SIGNAL RIn : std_logic := '1';
SIGNAL abus : std_logic_vector(19 DOWNTO 0);
SIGNAL cscom1 : std_logic;
SIGNAL dbus_com1 : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_in : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_in_cpu : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_out : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_rom : std_logic_vector(7 DOWNTO 0) := X"FF";
SIGNAL dbus_esram : std_logic_vector(7 DOWNTO 0) := X"EE";
SIGNAL dout : std_logic;
SIGNAL dout1 : std_logic;
SIGNAL intr : std_logic;
SIGNAL iom : std_logic;
SIGNAL nmi : std_logic;
SIGNAL por : std_logic;
SIGNAL rdn : std_logic;
SIGNAL resoutn : std_logic;
SIGNAL sel_s : std_logic_vector(2 DOWNTO 0);
SIGNAL wea : std_logic_VECTOR(0 DOWNTO 0);
SIGNAL wran : std_logic;
SIGNAL wrcom : std_logic;
SIGNAL wrn : std_logic;
signal rxclk_s : std_logic;
-- Component Declarations
COMPONENT cpu86
PORT(
clk : IN std_logic;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
intr : IN std_logic;
nmi : IN std_logic;
por : IN std_logic;
abus : OUT std_logic_vector (19 DOWNTO 0);
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
cpuerror : OUT std_logic;
inta : OUT std_logic;
iom : OUT std_logic;
rdn : OUT std_logic;
resoutn : OUT std_logic;
wran : OUT std_logic;
wrn : OUT std_logic
);
END COMPONENT;
COMPONENT blk_mem_40K
PORT (
addra : IN std_logic_VECTOR (15 DOWNTO 0);
clka : IN std_logic;
dina : IN std_logic_VECTOR (7 DOWNTO 0);
wea : IN std_logic_VECTOR (0 DOWNTO 0);
douta : OUT std_logic_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
-- COMPONENT bootstrap
-- PORT (
-- abus : IN std_logic_vector (7 DOWNTO 0);
-- dbus : OUT std_logic_vector (7 DOWNTO 0)
-- );
-- END COMPONENT;
-- COMPONENT esram
-- PORT (
-- addra : IN std_logic_VECTOR (7 DOWNTO 0);
-- clka : IN std_logic;
-- dina : IN std_logic_VECTOR (7 DOWNTO 0);
-- wea : IN std_logic_VECTOR (0 DOWNTO 0);
-- douta : OUT std_logic_VECTOR (7 DOWNTO 0)
-- );
-- END COMPONENT;
COMPONENT uart_top
PORT (
BR_clk : IN std_logic ;
CTSn : IN std_logic := '1';
DCDn : IN std_logic := '1';
DSRn : IN std_logic := '1';
RIn : IN std_logic := '1';
abus : IN std_logic_vector (2 DOWNTO 0);
clk : IN std_logic ;
csn : IN std_logic ;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
rdn : IN std_logic ;
resetn : IN std_logic ;
sRX : IN std_logic ;
wrn : IN std_logic ;
B_CLK : OUT std_logic ;
DTRn : OUT std_logic ;
IRQ : OUT std_logic ;
OUT1n : OUT std_logic ;
OUT2n : OUT std_logic ;
RTSn : OUT std_logic ;
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
stx : OUT std_logic
);
END COMPONENT;
begin
ARD_RESET <= not(DUO_SW1);
sram_addr <= '0' & abus;
CTS <= '1';
-- w1b(1) <= 'Z';
-- PIN3 <= not w1b(1); -- por
PIN3 <= '1';
dcm0: clk32to40
port map
(-- Clock in ports
CLK_IN1 => clk,
-- Clock out ports
CLK_OUT1 => CLOCK_40MHZ);
-- Architecture concurrent statements
-- HDL Embedded Text Block 4 mux
-- dmux 1
process(sel_s,dbus_com1,dbus_in,dbus_rom,dbus_esram)
begin
case sel_s is
when "011" => dbus_in_cpu <= dbus_esram; -- esram
when "101" => dbus_in_cpu <= dbus_com1; -- UART
when "110" => dbus_in_cpu <= dbus_rom; -- BootStrap Loader
when others=> dbus_in_cpu <= dbus_in; -- Embedded SRAM
end case;
end process;
process(csesramn,wrn,rdn,dbus_out,sram_data)
begin
sram_ce <= '1';
sram_we <= '1';
sram_oe <= '1';
sram_data <= (others => 'Z');
if csesramn='0' then
sram_ce <= '0';
if wrn='0' then
sram_data <= dbus_out;
sram_we <= '0';
else
if rdn='0' then
dbus_esram <= sram_data;
sram_oe <= '0';
end if;
end if;
end if;
end process;
-- HDL Embedded Text Block 7 clogic
wrcom <= not wrn;
wea(0)<= not wrn;
PIN4 <= resoutn; -- For debug only
-- dbus_in_cpu multiplexer
sel_s <= csesramn & cscom1 & csromn;
-- chip_select
-- Comport, uart_16550
-- COM1, 0x3F8-0x3FF
cscom1 <= '0' when (abus(15 downto 3)="0000001111111" AND iom='1') else '1';
-- Bootstrap ROM 256 bytes
-- FFFFF-FF=FFF00
-- csromn <= '0' when ((abus(19 downto 8)=X"FFF") AND iom='0') else '1';
-- esram 256 bytes
-- 0xEEE00
-- csesramn <= '0' when ((abus(19 downto 8)=X"EEE") AND iom='0') else '1';
csesramn <= '0' when ((abus(19)='0') AND iom='0') else '1';
nmi <= '0';
intr <= '0';
dout <= '0';
dout1 <= '0';
DCDn <= '0';
DSRn <= '0';
RIn <= '0';
por <= NOT(PIN3);
-- Instance port mappings.
U_1 : cpu86
PORT MAP (
clk => CLOCK_40MHZ,
dbus_in => dbus_in_cpu,
intr => intr,
nmi => nmi,
por => por,
abus => abus,
cpuerror => LED1,
dbus_out => dbus_out,
inta => OPEN,
iom => iom,
rdn => rdn,
resoutn => resoutn,
wran => wran,
wrn => wrn
);
U_3 : blk_mem_40K
PORT MAP (
clka => CLOCK_40MHZ,
dina => dbus_out,
addra => abus(15 DOWNTO 0),
wea => wea,
douta => dbus_in
);
-- esram0 : esram
-- PORT map (
-- addra => abus(15 downto 0),
-- clka => CLOCK_40MHZ,
-- dina => dbus_out,
-- wea => wea_esram,
-- douta => dbus_in_esram
-- );
-- U_2 : bootstrap
-- PORT MAP (
-- abus => abus(7 DOWNTO 0),
-- dbus => dbus_rom
-- );
U_0 : uart_top
PORT MAP (
BR_clk => rxclk_s,
CTSn => CTS,
DCDn => DCDn,
DSRn => DSRn,
RIn => RIn,
abus => abus(2 DOWNTO 0),
clk => CLOCK_40MHZ,
csn => cscom1,
dbus_in => dbus_out,
rdn => rdn,
resetn => resoutn,
sRX => RXD,
wrn => wrn,
B_CLK => rxclk_s,
DTRn => OPEN,
IRQ => OPEN,
OUT1n => led2n,
OUT2n => led3n,
RTSn => RTS,
dbus_out => dbus_com1,
stx => TXD
);
end Behavioral;
| gpl-2.0 | 8542b064f47997d1491388a0f8e868c6 | 0.486203 | 3.402475 | false | false | false | false |
andykarpov/radio-86rk-wxeda | src/keyboard/Debouncer.vhd | 1 | 792 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Debouncer is
generic (Delay : positive);
port (Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
Input : in STD_LOGIC;
Output : out STD_LOGIC);
end Debouncer;
architecture Behavioral of Debouncer is
signal DelayCounter : natural range 0 to Delay;
signal Internal : STD_LOGIC;
begin
process(Clock, Reset)
begin
if Reset = '1' then
Output <= '0';
Internal <= '0';
DelayCounter <= 0;
elsif rising_edge(Clock) then
if Input /= Internal then
Internal <= Input;
DelayCounter <= 0;
elsif DelayCounter = Delay then
Output <= Internal;
else
DelayCounter <= DelayCounter + 1;
end if;
end if;
end process;
end Behavioral; | bsd-2-clause | 443f82e9d9be18427aa5cd0cc7d43c9b | 0.670455 | 3.286307 | false | false | false | false |
nsauzede/cpu86 | papilio2_lcd/cpu86pack.vhd | 3 | 17,116 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
PACKAGE cpu86pack IS
constant RESET_CS_C : std_logic_vector(15 downto 0) := (others => '1'); -- FFFF:0000
constant RESET_IP_C : std_logic_vector(15 downto 0) := (others => '0');
constant RESET_ES_C : std_logic_vector(15 downto 0) := (others => '0');
constant RESET_SS_C : std_logic_vector(15 downto 0) := (others => '0');
constant RESET_DS_C : std_logic_vector(15 downto 0) := (others => '0');
constant RESET_VECTOR_C : std_logic_vector(19 downto 0) := (RESET_CS_C & X"0") + (X"0" & RESET_IP_C);
constant MUL_MCD_C : std_logic_vector(4 downto 0) := "00010"; -- mul MCP
-- Serial Divider delay
-- changed later to done signal
-- You can gain 1 clk cycle, done can be asserted 1 cycle earlier
constant DIV_MCD_C : std_logic_vector(4 downto 0) := "10011"; -- div waitstates 19!
constant ONE : std_logic := '1';
constant ZERO : std_logic := '0';
constant ZEROVECTOR_C : std_logic_vector(31 downto 0) := X"00000000";
-- Minimum value for MAX_WS="000", this result in a 2 cycle rd/wr strobe
-- Total Read cycle is 1 cycle for address setup + 2 cycles for rd/wr strobe, thus
-- minimum bus cycle is 3 clk cycles.
constant WS_WIDTH : integer := 3; -- 2^WS_WIDTH=MAX Waitstates
constant MAX_WS : std_logic_vector(WS_WIDTH-1 downto 0) := "000"; -- 3 clk bus cycles
constant DONTCARE : std_logic_vector(31 downto 0):=X"FFFFFFFF";
-- Status record containing some data and flag register
type instruction_type is record
ireg : std_logic_vector(7 downto 0); -- Instruction register
xmod : std_logic_vector(1 downto 0); -- mod is a reserved word
reg : std_logic_vector(2 downto 0); -- between mode and rm
rm : std_logic_vector(2 downto 0);
data : std_logic_vector(15 downto 0);
disp : std_logic_vector(15 downto 0);
nb : std_logic_vector(2 downto 0); -- Number of bytes
end record;
-- Status record containing some data and flag register
type status_out_type is record
ax : std_logic_vector(15 downto 0);
cx_one : std_logic; -- '1' if CX=0001
cx_zero : std_logic; -- '1' if CX=0000
cl : std_logic_vector(7 downto 0); -- 5 bits shift/rotate counter
flag : std_logic_vector(15 downto 0);
div_err : std_logic; -- Divider overflow
end record;
--------------------------------------------------------------------------------------
-- Data Path Records
--------------------------------------------------------------------------------------
type path_in_type is record
datareg_input : std_logic_vector(6 downto 0); -- dimux(3) & w & seldreg(3)
alu_operation : std_logic_vector(14 downto 0);-- selalua(4) & selalub(4) & aluopr(7)
dbus_output : std_logic_vector(1 downto 0); -- (Odd/Even) domux setting
segreg_input : std_logic_vector(3 downto 0); -- simux & selsreg
ea_output : std_logic_vector(9 downto 0); -- dispmux(3) & eamux(4) & [flag]&segop(2)
end record;
-- Write Strobe Record for Data Path
type write_in_type is record
wrd : std_logic; -- Write datareg
wralu : std_logic; -- Write ALU result
wrcc : std_logic; -- Write Flag register
wrs : std_logic; -- Write Segment register
wrip : std_logic; -- Write Instruction Pointer
wrop : std_logic; -- Write Segment Prefix register, Set Prefix Flag
wrtemp: std_logic; -- Write to ALU_TEMP register
end record;
constant SET_OPFLAG : std_logic:='1'; -- Override Prefix Flag
-- DIMUX
constant DATAIN_IN : std_logic_vector(2 downto 0) := "000";
constant EABUS_IN : std_logic_vector(2 downto 0) := "001";
constant ALUBUS_IN : std_logic_vector(2 downto 0) := "010";
constant MDBUS_IN : std_logic_vector(2 downto 0) := "011";
constant ES_IN : std_logic_vector(2 downto 0) := "100";
constant CS_IN : std_logic_vector(2 downto 0) := "101";
constant SS_IN : std_logic_vector(2 downto 0) := "110";
constant DS_IN : std_logic_vector(2 downto 0) := "111";
-- SIMUX Segment Register input Mux
constant SDATAIN_IN : std_logic_vector(1 downto 0) := "00";
constant SEABUS_IN : std_logic_vector(1 downto 0) := "01"; -- Effective Address
constant SALUBUS_IN : std_logic_vector(1 downto 0) := "10";
constant SMDBUS_IN : std_logic_vector(1 downto 0) := "11";
-- DOMUX (Note bit 2=odd/even)
constant ALUBUS_OUT : std_logic_vector(1 downto 0) := "00";
constant CCBUS_OUT : std_logic_vector(1 downto 0) := "01";
constant DIBUS_OUT : std_logic_vector(1 downto 0) := "10";
constant IPBUS_OUT : std_logic_vector(1 downto 0) := "11";
-- dispmux(3) & eamux(4) & poflag & segop[1:0]
-- note some bits may be dontcare!
constant NB_ES_IP : std_logic_vector(9 downto 0) := "0000000000"; -- IPREG+NB ADDR=ES:IP
constant NB_CS_IP : std_logic_vector(9 downto 0) := "0000000001";
constant NB_SS_IP : std_logic_vector(9 downto 0) := "0000000010";
constant NB_DS_IP : std_logic_vector(9 downto 0) := "0000000011";
constant NB_ES_EA : std_logic_vector(9 downto 0) := "0000001000"; -- IPREG+NB ADDR=EA
constant NB_CS_EA : std_logic_vector(9 downto 0) := "0000001001";
constant NB_SS_EA : std_logic_vector(9 downto 0) := "0000001010";
constant NB_DS_EA : std_logic_vector(9 downto 0) := "0000001011";
constant DISP_ES_EA : std_logic_vector(9 downto 0) := "0010001000"; -- IPREG+DISP ADDR=EA
constant DISP_CS_EA : std_logic_vector(9 downto 0) := "0010001001";
constant DISP_SS_EA : std_logic_vector(9 downto 0) := "0010001010";
constant DISP_DS_EA : std_logic_vector(9 downto 0) := "0010001011";
constant DISP_CS_IP : std_logic_vector(9 downto 0) := "0010000001"; -- Used for Jx instructions
constant PORT_00_DX : std_logic_vector(6 downto 0) := "0000010"; -- EAMUX IN/OUT instruction
constant PORT_00_EA : std_logic_vector(6 downto 0) := "0000001"; -- EAMUX Segm=00 00:IP or 00:DISP
constant NB_SS_SP : std_logic_vector(6 downto 0) := "0000100"; -- IP=IP+NBREQ, EAMUX=SS:SP , 100, 101, 110 unused
constant LD_SS_SP : std_logic_vector(6 downto 0) := "0100100"; -- Load new IP from MDBUS & out=SS:SP
constant LD_MD_IP : std_logic_vector(9 downto 0) := "0100000001"; -- Load new IP from MDBUS (e.g. RET instruction)
constant LD_CS_IP : std_logic_vector(9 downto 0) := "0110000001"; -- Load new IP (e.g. RET instruction)
constant EA_CS_IP : std_logic_vector(9 downto 0) := "1000001001"; -- Load new IP (e.g. RET instruction)
constant IPB_CS_IP : std_logic_vector(9 downto 0) := "1110000001"; -- Select IPBUS=IPREG
constant MD_EA2_DS : std_logic_vector(9 downto 0) := "0100011011"; -- IP<-MD, addr=DS:EA2
-- SELALUA/B or SELDREG(2 downto 0)
constant REG_AX : std_logic_vector(3 downto 0) := "0000"; -- W=1 Into ALUBUS A or B
constant REG_CX : std_logic_vector(3 downto 0) := "0001";
constant REG_DX : std_logic_vector(3 downto 0) := "0010";
constant REG_BX : std_logic_vector(3 downto 0) := "0011";
constant REG_SP : std_logic_vector(3 downto 0) := "0100";
constant REG_BP : std_logic_vector(3 downto 0) := "0101";
constant REG_SI : std_logic_vector(3 downto 0) := "0110";
constant REG_DI : std_logic_vector(3 downto 0) := "0111";
constant REG_DATAIN : std_logic_vector(3 downto 0) := "1000"; -- Pass data_in to ALU
constant REG_MDBUS : std_logic_vector(3 downto 0) := "1111"; -- Pass memory bus (mdbus) to ALU
-- Only for SELALUB
constant REG_CONST1 : std_logic_vector(3 downto 0) := "1001"; -- Used for INC/DEC function, W=0/1
constant REG_CONST2 : std_logic_vector(3 downto 0) := "1010"; -- Used for POP/PUSH function W=1
-- W+SELDREG
constant REG_AH : std_logic_vector(3 downto 0) := "0100"; -- W=1 SELDREG=AH
---------------------------------------------------------------
-- ALU Operations
-- Use ireg(5 downto 3) / modrm(5 downto 3) / ireg(3 downto 0)
-- Constants for
---------------------------------------------------------------
constant ALU_ADD : std_logic_vector(6 downto 0) := "0000000";
constant ALU_OR : std_logic_vector(6 downto 0) := "0000001";
constant ALU_ADC : std_logic_vector(6 downto 0) := "0000010";
constant ALU_SBB : std_logic_vector(6 downto 0) := "0000011";
constant ALU_AND : std_logic_vector(6 downto 0) := "0000100";
constant ALU_SUB : std_logic_vector(6 downto 0) := "0000101";
constant ALU_XOR : std_logic_vector(6 downto 0) := "0000110";
constant ALU_CMP : std_logic_vector(6 downto 0) := "0000111"; -- See also ALU_CMPS
constant ALU_TEST0 : std_logic_vector(6 downto 0) := "0001000";
constant ALU_TEST1 : std_logic_vector(6 downto 0) := "0001101";
-- Random assignment, these can be changed.
constant ALU_PUSH : std_logic_vector(6 downto 0) := "0001001"; -- Used for PUSH (SUB)
constant ALU_POP : std_logic_vector(6 downto 0) := "0001010"; -- Used for POP (ADD)
constant ALU_REGL : std_logic_vector(6 downto 0) := "0001011"; -- alureg(15..0) (latched alu_busb)
constant ALU_REGH : std_logic_vector(6 downto 0) := "0111011"; -- alureg(31..16) (latched alu_busa)
constant ALU_PASSA : std_logic_vector(6 downto 0) := "0001100"; -- abus_s only
constant ALU_TEMP : std_logic_vector(6 downto 0) := "1111001"; -- Used to select temp/scratchpad register (80186 only)
-- CONST & instr.irg(3 downto 0)
constant ALU_SAHF : std_logic_vector(6 downto 0) := "0001110"; -- AH -> Flags
-- CONST & instr.irg(3 downto 0)
constant ALU_LAHF : std_logic_vector(6 downto 0) := "0001111"; -- Flags->ALUBUS (->AH)
-- CONSTANT & instr.ireg(1) & modrm.reg(5 downto 3)
-- CONSTANT=001
constant ALU_ROL1 : std_logic_vector(6 downto 0) := "0010000"; -- count=1
constant ALU_ROR1 : std_logic_vector(6 downto 0) := "0010001";
constant ALU_RCL1 : std_logic_vector(6 downto 0) := "0010010";
constant ALU_RCR1 : std_logic_vector(6 downto 0) := "0010011";
constant ALU_SHL1 : std_logic_vector(6 downto 0) := "0010100";
constant ALU_SHR1 : std_logic_vector(6 downto 0) := "0010101";
constant ALU_SAR1 : std_logic_vector(6 downto 0) := "0010111";
constant ALU_ROL : std_logic_vector(6 downto 0) := "0011000"; -- Count in CL
constant ALU_ROR : std_logic_vector(6 downto 0) := "0011001";
constant ALU_RCL : std_logic_vector(6 downto 0) := "0011010";
constant ALU_RCR : std_logic_vector(6 downto 0) := "0011011";
constant ALU_SHL : std_logic_vector(6 downto 0) := "0011100";
constant ALU_SHR : std_logic_vector(6 downto 0) := "0011101";
constant ALU_SAR : std_logic_vector(6 downto 0) := "0011111";
-- CONST & modrm.reg(5 downto 3)/instr.ireg(5 downto 3)
constant ALU_INC : std_logic_vector(6 downto 0) := "0100000"; -- Increment
constant ALU_DEC : std_logic_vector(6 downto 0) := "0100001"; -- Decrement also used for LOOP/JCXZ
constant ALU_CLRTIF : std_logic_vector(6 downto 0) := "0100010"; -- Clear TF/IF flag, used for INT
constant ALU_CMPS : std_logic_vector(6 downto 0) := "0100111"; -- Compare String ALUREG-MDBUS
constant ALU_SCAS : std_logic_vector(6 downto 0) := "0101111"; -- AX/AL-MDBUS, no SEXT
-- CONST & instr.irg(3 downto 0)
constant ALU_CMC : std_logic_vector(6 downto 0) := "0100101"; -- Complement Carry
constant ALU_CLC : std_logic_vector(6 downto 0) := "0101000"; -- Clear Carry
constant ALU_STC : std_logic_vector(6 downto 0) := "0101001"; -- Set Carry
constant ALU_CLI : std_logic_vector(6 downto 0) := "0101010"; -- Clear interrupt
constant ALU_STI : std_logic_vector(6 downto 0) := "0101011"; -- Set Interrupt
constant ALU_CLD : std_logic_vector(6 downto 0) := "0101100"; -- Clear Direction
constant ALU_STD : std_logic_vector(6 downto 0) := "0101101"; -- Set Direction
-- CONST & modrm.reg(5 downto 3)
constant ALU_TEST2 : std_logic_vector(6 downto 0) := "0110000"; -- F6/F7
constant ALU_NOT : std_logic_vector(6 downto 0) := "0110010"; -- F6/F7
constant ALU_NEG : std_logic_vector(6 downto 0) := "0110011"; -- F6/F7
constant ALU_MUL : std_logic_vector(6 downto 0) := "0110100"; -- F6/F7
constant ALU_IMUL : std_logic_vector(6 downto 0) := "0110101"; -- F6/F7
constant ALU_DIV : std_logic_vector(6 downto 0) := "0110110"; -- F6/F7
constant ALU_IDIV : std_logic_vector(6 downto 0) := "0110111"; -- F6/F7
-- Second cycle write DX
constant ALU_MUL2 : std_logic_vector(6 downto 0) := "0111100"; -- F6/F7
constant ALU_IMUL2 : std_logic_vector(6 downto 0) := "0111101"; -- F6/F7
constant ALU_DIV2 : std_logic_vector(6 downto 0) := "0111110"; -- F6/F7
constant ALU_IDIV2 : std_logic_vector(6 downto 0) := "0111111"; -- F6/F7
-- CONST & instr.ireg(3 downto 0)
constant ALU_SEXT : std_logic_vector(6 downto 0) := "0111000"; -- Used for CBW
constant ALU_SEXTW : std_logic_vector(6 downto 0) := "0111001"; -- Used for CWD
-- CONSTANT & & instr.ireg(1) & instr.ireg(5 downto 3)
constant ALU_AAM : std_logic_vector(6 downto 0) := "1000010";
constant ALU_AAD : std_logic_vector(6 downto 0) := "1001010";
constant ALU_DAA : std_logic_vector(6 downto 0) := "1001100";
constant ALU_DAS : std_logic_vector(6 downto 0) := "1001101";
constant ALU_AAA : std_logic_vector(6 downto 0) := "1001110";
constant ALU_AAS : std_logic_vector(6 downto 0) := "1001111";
constant ALU_ADD_SE : std_logic_vector(6 downto 0) := "1100000";
constant ALU_OR_SE : std_logic_vector(6 downto 0) := "1100001";
constant ALU_ADC_SE : std_logic_vector(6 downto 0) := "1100010";
constant ALU_SBB_SE : std_logic_vector(6 downto 0) := "1100011";
constant ALU_AND_SE : std_logic_vector(6 downto 0) := "1100100";
constant ALU_SUB_SE : std_logic_vector(6 downto 0) := "1100101";
constant ALU_XOR_SE : std_logic_vector(6 downto 0) := "1100110";
constant ALU_CMP_SE : std_logic_vector(6 downto 0) := "1100111";
END cpu86pack;
| gpl-2.0 | 16ebfa5d9524a586fe2a7513cf1deb46 | 0.56713 | 3.480984 | false | false | false | false |
nsauzede/cpu86 | papilio2_vga/aaatop.vhd | 1 | 6,122 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:17:25 02/11/2015
-- Design Name:
-- Module Name: aaatop - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
----------------------------------------------------------------------------------
-- LED example, by Jerome Cornet
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity Aaatop is
Port (
CLK,reset : in STD_LOGIC;
tx : inout std_logic;
rx : in std_logic;
ARDUINO_RESET : out STD_LOGIC;
DUO_SW1 : in STD_LOGIC;
-- DUO_LED : out std_logic;
sram_addr : out std_logic_vector(20 downto 0);
sram_data : inout std_logic_vector(7 downto 0);
sram_ce : out std_logic;
sram_we : out std_logic;
sram_oe : out std_logic;
SW_LEFT : in STD_LOGIC;
SW_UP : in STD_LOGIC;
SW_DOWN : in STD_LOGIC;
SW_RIGHT : in STD_LOGIC;
LED1 : inout STD_LOGIC;
LED2 : inout STD_LOGIC;
LED3 : inout STD_LOGIC;
LED4 : inout STD_LOGIC;
VGA_HSYNC : out STD_LOGIC;
VGA_VSYNC : out STD_LOGIC;
VGA_BLUE : out std_logic_vector(3 downto 0);
VGA_GREEN : out std_logic_vector(3 downto 0);
VGA_RED : out std_logic_vector(3 downto 0)
-- Arduino : inout STD_LOGIC_VECTOR (21 downto 0)
-- Arduino : inout STD_LOGIC_VECTOR (53 downto 0)
);
end Aaatop;
architecture Behavioral of Aaatop is
signal CLOCK_40MHZ : std_logic;
signal CTS : std_logic := '1';
signal PIN3 : std_logic;
signal LED1P : std_logic;
signal LED2N : std_logic;
signal LED3N : std_logic;
signal PIN4 : std_logic;
signal RTS : std_logic;
signal vramaddr : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal vramdata : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal pixel_x, pixel_y: std_logic_vector(9 downto 0);
signal clock, video_on, pixel_tick: std_logic;
signal rgb_reg, rgb_next: std_logic_vector(2 downto 0);
signal hsync, vsync: std_logic;
signal rgb: std_logic_vector(2 downto 0);
signal buttons: std_logic_vector(3 downto 0);
COMPONENT drigmorn1_top
PORT(
sram_addr : out std_logic_vector(20 downto 0);
sram_data : inout std_logic_vector(7 downto 0);
sram_ce : out std_logic;
sram_we : out std_logic;
sram_oe : out std_logic;
vramaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
vramdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLOCK_40MHZ : IN std_logic;
CTS : IN std_logic := '1';
PIN3 : IN std_logic;
RXD : IN std_logic;
LED1 : OUT std_logic;
LED2N : OUT std_logic;
LED3N : OUT std_logic;
PIN4 : OUT std_logic;
RTS : OUT std_logic;
TXD : OUT std_logic
);
END component ;
component clk32to40
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic
);
end component;
begin
CTS <= '1';
-- PIN3 <= not Arduino(40); -- por
-- PIN3 <= reset; -- por
PIN3 <= '1'; -- por
-- Arduino(38) <= Arduino(40);
-- Arduino(42) <= Arduino(44);
-- Arduino(46) <= Arduino(48);
-- Arduino(50) <= Arduino(52);
-- Arduino(38) <= LED1;
-- Arduino(42) <= LED2N;
-- Arduino(46) <= LED3N;
-- Arduino(50) <= '0';
-- sram_addr <= (others => '0');
-- sram_ce <= '0';
-- sram_we <= '0';
-- sram_oe <= '0';
drigmorn1_top0 : drigmorn1_top
PORT map(
sram_addr => sram_addr,
sram_data => sram_data,
sram_ce => sram_ce,
sram_we => sram_we,
sram_oe => sram_oe,
vramaddr => vramaddr,
vramdata => vramdata,
CLOCK_40MHZ => CLOCK_40MHZ,
CTS => CTS,
PIN3 => PIN3,
RXD => RX,
LED1 => LED1P,
LED2N => LED2N,
LED3N => LED3N,
PIN4 => PIN4,
RTS => RTS,
TXD => TX
);
dcm0: clk32to40
port map
(-- Clock in ports
CLK_IN1 => clk,
-- Clock out ports
CLK_OUT1 => CLOCK_40MHZ,
CLK_OUT2 => clock
);
-- VGA signals
vga_sync_unit: entity work.vga_sync
port map(
clock => clock,
reset => reset,
hsync => hsync,
vsync => vsync,
video_on => video_on,
pixel_tick => pixel_tick,
pixel_x => pixel_x,
pixel_y => pixel_y
);
-- font generator
font_gen_unit: entity work.font_generator
port map(
clock => pixel_tick,
vramaddr => vramaddr,
vramdata => vramdata,
video_on => video_on,
buttons => buttons,
pixel_x => pixel_x,
pixel_y => pixel_y,
rgb_text => rgb_next
);
ARDUINO_RESET <= not(DUO_SW1);
buttons <= sw_left & sw_right & sw_up & sw_down;
-- led1 <= buttons(0);
-- led2 <= buttons(1);
-- led3 <= buttons(2);
-- led4 <= buttons(3);
-- rgb buffer
process(clock)
begin
if clock'event and clock = '1' then
if pixel_tick = '1' then
rgb_reg <= rgb_next;
end if;
end if;
end process;
rgb <= rgb_reg;
vga_hsync <= hsync;
vga_vsync <= vsync;
vga_blue <= (others => rgb(0));--blue
vga_green <= (others => rgb(1));--green
vga_red <= (others => rgb(2));--red
end Behavioral;
| gpl-2.0 | f62d96d7c7fbbe23f6e01652e6b5d63f | 0.529402 | 3.282574 | false | false | false | false |
nsauzede/cpu86 | p2_lcd_spi/aaatop.vhd | 1 | 5,506 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:17:25 02/11/2015
-- Design Name:
-- Module Name: aaatop - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
----------------------------------------------------------------------------------
-- LED example, by Jerome Cornet
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity Aaatop is
Port (
CLK,reset : in STD_LOGIC;
txd : inout std_logic;
rxd : in std_logic;
ARD_RESET : out STD_LOGIC;
DUO_SW1 : in STD_LOGIC;
-- DUO_LED : out std_logic;
sram_addr : out std_logic_vector(20 downto 0);
sram_data : inout std_logic_vector(7 downto 0);
sram_ce : out std_logic;
sram_we : out std_logic;
sram_oe : out std_logic;
W1A : inout STD_LOGIC_VECTOR (7 downto 0);
W1B : inout STD_LOGIC_VECTOR (7 downto 0);
W2C : inout STD_LOGIC_VECTOR (15 downto 0);
W2D : inout STD_LOGIC_VECTOR (15 downto 0);
Arduino : inout STD_LOGIC_VECTOR (21 downto 0)
-- Arduino : inout STD_LOGIC_VECTOR (53 downto 0)
);
end Aaatop;
architecture Behavioral of Aaatop is
signal CLOCK_40MHZ : std_logic;
signal CTS : std_logic := '1';
signal PIN3 : std_logic;
signal LED1 : std_logic;
signal LED2N : std_logic;
signal LED3N : std_logic;
signal PIN4 : std_logic;
signal RTS : std_logic;
signal SD_MISO : std_logic;
signal SD_MOSI : std_logic;
signal SD_SCK : std_logic;
signal SD_nCS : std_logic;
signal buttons : std_logic_vector(5 downto 0);
signal audio_left : STD_LOGIC;
signal audio_right : STD_LOGIC;
signal ud : STD_LOGIC;
signal rl : STD_LOGIC;
signal enab : STD_LOGIC;
signal vsync : STD_LOGIC;
signal hsync : STD_LOGIC;
signal ck : STD_LOGIC;
signal r : std_logic_vector(5 downto 0);
signal g : std_logic_vector(5 downto 0);
signal b : std_logic_vector(5 downto 0);
signal vramaddr : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal vramdata : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal spi_clk : std_logic := '1';
signal spi_csn : std_logic := '1';
signal spi_mosi : std_logic := '1';
signal spi_miso : std_logic := '1';
signal buttons2 : STD_LOGIC_VECTOR (3 downto 0);
signal leds : STD_LOGIC_VECTOR (3 downto 0);
component clk32to40
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end component;
begin
ARD_RESET <= not(DUO_SW1);
CTS <= '1';
-- PIN3 <= not Arduino(40); -- por
-- PIN3 <= reset; -- por
PIN3 <= '1'; -- por
-- Arduino(38) <= Arduino(40);
-- Arduino(42) <= Arduino(44);
-- Arduino(46) <= Arduino(48);
-- Arduino(50) <= Arduino(52);
-- Arduino(38) <= LED1;
-- Arduino(42) <= LED2N;
-- Arduino(46) <= LED3N;
-- Arduino(50) <= '0';
-- sram_addr <= (others => '0');
-- sram_ce <= '0';
-- sram_we <= '0';
-- sram_oe <= '0';
drigmorn1_top0 : entity work.drigmorn1_top
PORT map(
sram_addr => sram_addr,
sram_data => sram_data,
sram_ce => sram_ce,
sram_we => sram_we,
sram_oe => sram_oe,
vramaddr => vramaddr,
vramdata => vramdata,
spi_cs => spi_csn,
spi_clk => spi_clk,
spi_mosi => spi_mosi,
spi_miso => spi_miso,
buttons => buttons2,
leds => leds,
CLOCK_40MHZ => CLOCK_40MHZ,
CTS => CTS,
PIN3 => PIN3,
RXD => RXD,
LED1 => LED1,
LED2N => LED2N,
LED3N => LED3N,
PIN4 => PIN4,
RTS => RTS,
TXD => TXD
);
dcm0: clk32to40
port map
(-- Clock in ports
CLK_IN1 => clk,
-- Clock out ports
CLK_OUT1 => CLOCK_40MHZ);
winglcd0 : entity work.winglcdsndbut Port map(
W1A => w2c,
W1B => w2d,
buttons => buttons,
audio_left => audio_left,
audio_right => audio_right,
ud => ud,
rl => rl,
enab => enab,
vsync => vsync,
hsync => hsync,
ck => ck,
r => r,
g => g,
b => b
);
w1a(0) <= vsync;
w1a(5) <= hsync;
w1a(7) <= r(0);
lcdctl0 : entity work.lcdctl Port map(
clk => CLOCK_40MHZ,
-- clk => clk,
reset=>reset,
vramaddr => vramaddr,
vramdata => vramdata,
ud => ud,
rl => rl,
enab => enab,
vsync => vsync,
hsync => hsync,
ck => ck,
r => r,
g => g,
b => b
);
--microSDwing
--0 not used in SPI
--1 MISO
--2 SCK
--3 MOSI
--4 CSN
spi_miso <= w1a(1);
w1a(2) <= spi_clk;
w1a(3) <= spi_mosi;
w1a(4) <= spi_csn;
butled1: entity work.wingbutled
Port map (
io => w1b,
buttons => buttons2,
leds => leds
);
-- leds <= buttons2;
end Behavioral;
| gpl-2.0 | b3581f51b99a8de478631d44c577347c | 0.536687 | 3.191884 | false | false | false | false |
VenturaSolutionsInc/VHDL | igmp/igmp_assembler.vhd | 1 | 14,155 | -------------------------------------------------------------------------------
-- Title : IGMP Assembler
-- Project :
-------------------------------------------------------------------------------
--! @file : igmp_assembler.vhd
-- Author : Colin W. Shea
-- Company
-- Last update : 2010-03-15
-- Platform : Virtex 4/5/6
-------------------------------------------------------------------------------
--
--* @brief Assemble the IGMP Packet
--
--! @details: This module creates the IGMP packet for the join, report, and leave.
--! All values are prestored in constants and used as needed.
--!
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity igmp_assembler is
generic (
gen_dataWidth : integer := 8
);
port (
dataClk : in std_logic;
reset : in std_logic;
-- packet constuctor information signals
srcMAC : in std_logic_vector(47 downto 0);
destMAC : in std_logic_vector(47 downto 0);
vlanEn : in std_logic;
vlanId : in std_logic_vector(11 downto 0);
srcIP : in std_logic_vector(31 downto 0);
destIP : in std_logic_vector(31 downto 0);
-- control signals
join : in std_logic;
leave : in std_logic;
tx_ready_n : in std_logic;
messageSent : out std_logic;
tx_sof : out std_logic;
tx_eof : out std_logic;
tx_vld : out std_logic;
tx_data : out std_logic_vector(7 downto 0)
);
end igmp_assembler;
architecture rtl of igmp_assembler is
type ipv4Header is array(9 downto 0) of std_logic_vector(7 downto 0);
constant headerValues : ipv4Header := (X"45", X"00", X"00", X"1C", X"00", X"00", X"40", X"00", X"01", X"02");
constant c_vlanType : std_logic_vector(15 downto 0) := X"8100";
constant c_packetType : std_logic_vector(15 downto 0) := X"0800";
signal assembly_state : std_logic_vector(3 downto 0) := (others => '0');
signal byteCount : integer range 0 to 9 := 0;
signal done : std_logic := '0';
signal ipv4_layer_checksum_join, ipv4_layer_checksum_leave : std_logic_vector(15 downto 0) := (others => '0');
signal igmp_layer_checksum_join, igmp_layer_checksum_leave : std_logic_vector(15 downto 0) := (others => '0');
signal join_r, join_r2, leave_r, leave_r2, join_hold, leave_hold, rsp_hold : std_logic := '0';
signal igmpType : std_logic_vector(7 downto 0) := (others => '0');
signal ipv4Checksum : std_logic_vector(15 downto 0) := (others => '0');
signal igmpChecksum : std_logic_vector(15 downto 0) := (others => '0');
signal ipv4Address : std_logic_vector(31 downto 0) := (others => '0');
signal groupaddress : std_logic_vector(31 downto 0) := (others => '0');
-- 2 1 0
signal currentState : std_logic_vector(2 downto 0) := (others => '0');
signal startChecksum : std_logic := '0';
-- bit 2 join
-- bit 1 leave
signal srcMAC_r : std_logic_vector(47 downto 0);
signal destMAC_r : std_logic_vector(47 downto 0);
signal vlanEn_r : std_logic;
signal vlanId_r : std_logic_vector(11 downto 0);
signal srcIP_r : std_logic_vector(31 downto 0);
signal destIP_r : std_logic_vector(31 downto 0);
signal tx_ready_n_r : std_logic;
begin
register_and_hold_join_rsp_leave : process(dataClk, reset)
begin
if(rising_edge(dataClk))then
if(reset = '1')then
--rsp_r <= '0';
--rsp_r2 <= '0';
join_r <= '0';
leave_r <= '0';
join_r2 <= '0';
leave_r2 <= '0';
else
join_r <= join;
leave_r <= leave;
join_r2 <= join_r;
leave_r2 <= leave_r;
srcMAC_r <= srcMAC;
destMAC_r <= destMAC;
vlanEn_r <= vlanEn;
vlanId_r <= vlanId;
srcIP_r <= srcIP;
destIP_r <= destIP;
tx_ready_n_r <= tx_ready_n;
end if;
end if;
end process;
new_one : process(dataClk, reset)
begin
if(rising_edge(dataClk))then
if(reset = '1')then
-- tx_ready_n <= '0';
tx_data <= (others => '0');
tx_eof <= '0';
tx_sof <= '0';
tx_vld <= '0';
assembly_state <= (others => '0');
igmpType <= (others => '0');
byteCount <= 0;
ipv4Checksum <= (others => '0');
igmpChecksum <= (others => '0');
groupAddress <= (others => '0');
ipv4Address <= (others => '0');
currentState <= "000";
messageSent <= '0';
startChecksum <= '0';
else
if(tx_ready_n_r = '0')then
messageSent <= '0';
case assembly_state is
when "0001" =>
startChecksum <= '0';
if(done = '1')then
if(currentState = "100" or currentState = "001")then
ipv4Checksum <= ipv4_layer_checksum_join;
igmpChecksum <= igmp_layer_checksum_join;
ipv4Address <= destIP_r;
groupAddress <= destIP_r;
assembly_state <= "0010";
igmpType <= X"16";
byteCount <= 6;
elsif(currentState = "010")then
ipv4Checksum <= ipv4_layer_checksum_leave;
igmpChecksum <= igmp_layer_checksum_leave;
ipv4Address <= X"E0000002";
groupAddress <= destIP_r;
assembly_state <= "0010";
igmpType <= X"17";
byteCount <= 6;
else
ipv4Checksum <= (others => '0');
igmpChecksum <= (others => '0');
assembly_state <= (others => '0');
igmpType <= (others => '0');
byteCount <= 0;
end if;
end if;
when "0010" =>
assembly_state <= "0010";
if(byteCount = 6)then
tx_sof <= '1';
tx_data <= destMAC_r(47 downto 40);
byteCount <= byteCount - 1;
elsif(byteCount > 1)then
tx_sof <= '0';
tx_data <= destMAC_r((8*byteCount)-1 downto 8*(byteCount - 1));
byteCount <= byteCount - 1;
elsif(byteCount = 1)then
tx_data <= destMAC_r(7 downto 0);
assembly_state <= "0011";
byteCount <= 6;
end if;
tx_vld <= '1';
when "0011" =>
assembly_state <= "0011";
if(byteCount = 6)then
tx_data <= srcMAC_r(47 downto 40);
byteCount <= byteCount - 1;
elsif(byteCount > 1)then
tx_sof <= '0';
tx_data <= srcMAC_r((8*byteCount)-1 downto 8*(byteCount - 1));
byteCount <= byteCount - 1;
elsif(byteCount = 1)then
tx_data <= srcMAC_r(7 downto 0);
if(vlanEn_r = '1')then
assembly_state <= "0100";
byteCount <= 3;
else
assembly_state <= "0101";
byteCount <= 2;
end if;
-- else
-- assembly_state <= "000000010";
end if;
tx_vld <= '1';
when "0100" =>
assembly_state <= "0100";
tx_vld <= '1';
if(byteCount = 3)then
tx_data <= c_vlanType(15 downto 8);
byteCount <= byteCount - 1;
elsif(byteCount = 2)then
tx_data <= c_vlanType(7 downto 0);
byteCount <= byteCount - 1;
elsif(byteCount = 1)then
tx_data <= "0000" & vlanId_r(11 downto 8);
byteCount <= byteCount - 1;
elsif(byteCount = 0)then
tx_data <= vlanId_r(7 downto 0);
byteCount <= 2;
assembly_state <= "0101";
end if;
when "0101" =>
assembly_state <= "0101";
tx_vld <= '1';
if(byteCount = 2)then
tx_data <= c_packetType(15 downto 8);
byteCount <= byteCount - 1;
else
tx_data <= c_packetType(7 downto 0);
assembly_state <= "0110";
byteCount <= 9;
end if;
when "0110" =>
if(byteCount = 0)then
assembly_state <= "0111";
byteCount <= 1;
else
byteCount <= byteCount - 1;
end if;
tx_data <= headerValues(byteCount);
tx_vld <= '1';
when "0111" =>
if(byteCount = 0)then
assembly_state <= "1000";
byteCount <= 3;
else
byteCount <= byteCount-1;
assembly_state <= "0111";
end if;
tx_data <= ipv4Checksum(((byteCount+1)*8)-1 downto byteCount*8);
tx_vld <= '1';
when "1000" =>
if(byteCount = 0)then
assembly_state <= "1001";
byteCount <= 3;
else
assembly_state <= "1000";
byteCount <= byteCount - 1;
end if;
tx_vld <= '1';
tx_data <= srcIP_r(((byteCount+1)*8)-1 downto byteCount*8);
when "1001" =>
if(byteCount = 0)then
assembly_state <= "1100";
byteCount <= 1;
else
assembly_state <= "1001";
byteCount <= byteCount - 1;
end if;
tx_data <= ipv4Address((byteCount+1)*8-1 downto byteCount*8);
tx_vld <= '1';
when "1100" =>
byteCount <= 1;
assembly_state <= "1101";
tx_data <= igmpType;
tx_vld <= '1';
when "1101" =>
tx_data <= X"00";
tx_vld <= '1';
assembly_state <= "1110";
when "1110" =>
if(byteCount = 0)then
byteCount <= 3;
assembly_state <= "1111";
else
byteCount <= byteCount - 1;
assembly_state <= "1110";
end if;
tx_data <= igmpChecksum(8*(byteCount+1)-1 downto byteCount*8);
tx_vld <= '1';
when "1111" =>
if(byteCount = 0)then
byteCount <= 0;
messageSent <= '1';
assembly_state <= "0000"; --(others => '0');
currentState <= "000";
tx_eof <= '1';
else
byteCount <= byteCount - 1;
assembly_state <= "1111";
end if;
tx_data <= groupAddress(8*(byteCount+1)-1 downto byteCount*8);
tx_vld <= '1';
when "0000" =>
tx_eof <= '0';
tx_vld <= '0';
if((join_r = '1' and join_r2 = '0') or (leave_r = '1' and leave_r2 = '0'))then
currentState <= join_r & leave_r & '0';
assembly_state <= "0001";
else
assembly_state <= "0000";
end if;
if(join_r = '1')then
startChecksum <= '1';
else
startChecksum <= '0';
end if;
when others =>
end case;
else
tx_vld <= '0';
tx_sof <= '0';
tx_eof <= '0';
end if;
-- tx_sof <= '0';
-- tx_eof <= '0';
-- tx_vld <= '0';
end if;
end if;
end process;
create_checksum : entity work.checksum
port map (
dataClk => dataClk,
reset => reset,
start_checksum => startChecksum,
multicast_ip => destIP,
source_ip => srcIP,
checksum_done => done,
ipv4_layer_checksum_j => ipv4_layer_checksum_join,
ipv4_layer_checksum_l => ipv4_layer_checksum_leave,
igmp_layer_checksum_j => igmp_layer_checksum_join,
igmp_layer_checksum_l => igmp_layer_checksum_leave
);
end rtl;
| gpl-2.0 | facdefd5ed4b34bc6c047e1173ebfdc3 | 0.389332 | 4.52092 | false | false | false | false |
nsauzede/cpu86 | papilio2/ipcore_dir/blk_mem_40K.vhd | 1 | 5,774 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file blk_mem_40K.vhd when simulating
-- the core, blk_mem_40K. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY blk_mem_40K IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END blk_mem_40K;
ARCHITECTURE blk_mem_40K_a OF blk_mem_40K IS
-- synthesis translate_off
COMPONENT wrapped_blk_mem_40K
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_blk_mem_40K USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 16,
c_addrb_width => 16,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "90",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "blk_mem_40K.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 0,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 65536,
c_read_depth_b => 65536,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 65536,
c_write_depth_b => 65536,
c_write_mode_a => "READ_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_blk_mem_40K
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- synthesis translate_on
END blk_mem_40K_a;
| gpl-2.0 | 603c9b89bebf25fa24dfe64f5f18719c | 0.518705 | 3.849333 | false | false | false | false |
ismailalmahdi/HMAC-SHA384-VHDL | hmac_sha384_TB.vhd | 1 | 1,960 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use work.HMACSHA384_ISMAIL.all;
entity hmac_sha384_TB is
end entity;
architecture behavioral of hmac_sha384_TB is
-- component
component hmac_sha384
port (clk: in std_logic;
salt : in std_logic_vector(383 downto 0);
pepper : in std_logic_vector(1023 downto 0);
small_msg: in std_logic_vector((6*4)-1 downto 0);
medium_msg: in std_logic_vector((46*4)-1 downto 0);
big_msg: in std_logic_vector((126*4)-1 downto 0);
hashed_code: out std_logic_vector(383 downto 0));
end component;
-- wires
signal clk : std_logic := '1';
signal salt : std_logic_vector(383 downto 0);
signal pepper : std_logic_vector(1023 downto 0);
signal small_msg : std_logic_vector((6*4)-1 downto 0);
signal medium_msg : std_logic_vector((46*4)-1 downto 0);
signal big_msg : std_logic_vector((126*4)-1 downto 0);
signal hashed_code : std_logic_vector(383 downto 0);
begin
uut : hmac_sha384 PORT MAP (
clk => clk,
salt => salt,
pepper => pepper,
small_msg => small_msg,
medium_msg => medium_msg,
big_msg => big_msg,
hashed_code => hashed_code
);
salt <= x"6a09a667f3bcc908bb67ae8584"
&x"caa73b3c6ef372fe94f82ba54f53"
&x"fa5f1d36f1510e527fade682d19b0"
&x"5688c2b3e6c1f";
pepper <= x"E67FF540BA6F5C5B9FEFC68B395EC32843C4FA76355D8183146B0F7B531F2DCE810B3226EFCE3D6BE3F90F0298DBE6AF2FD41AD0B7847D8F8F0E7526CE7A85129EA6B45C3BFB9272B25CD24958C7856DF3A57A6BF748CA22D842EC5C82E09E8FF16EEB2D58DF82B9B73B452BA14D2DBF19016A21BA2E5EB5DADAFC3F921B3F11";
small_msg <= x"616263";
medium_msg <=x"746869732069732074657374696e67206d657373616765";
big_msg <= x"69736d61696c616c6d616"
&x"864695468656562616e4166697"
&x"14472617673696e746573747465"
&x"7374746573747465737474657374"
&x"746573747465737474657374";
clk <= not clk after 16.66666667 ps;
end;
| mit | cdd81535eff11c811cf40ea35d775b40 | 0.703061 | 2.652233 | false | false | false | false |
kdgwill/VHDL_Verilog_Encryptions_And_Ciphers | VHDL_Trivium/tb_trivium.vhd | 1 | 9,938 | -----------------------------------------------------------------------------------
--Project Main Module--------------------------------------------------------------
--By Kyle D. Williams, 05/10/2015--------------------------------------------------
--PROJECT DESCRIPTION--------------------------------------------------------------
--1--Trivium Cipher----------------------------------------------------------------
--2--LOAD KEY DATA-----------------------------------------------------------------
--2--1--Use switches to set data---------------------------------------------------
--2--2--Use BTN-3 to shift data over 8 bits at a time until 10 shifts--------------
--2--3--Use BTN-2 to Skip or quickly complete data input---------------------------
--3--LOAD INITIALIZATION VECTOR----------------------------------------------------
--3--1--Use switches to set data---------------------------------------------------
--3--2--Use BTN-3 to shift data over 8 bits at a time until 10 shifts--------------
--3--3--Use BTN-2 to Skip or quickly complete data input---------------------------
--4--CIPHER STREAM APPEARS ON LED--------------------------------------------------
--4--1--use BT3 ir BT2 to cycle endless stream-------------------------------------
--5--USE BTN0 to reset-------------------------------------------------------------
-----------------------------------------------------------------------------------
----------------Define Libraries to be used----------------------------------------
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;--used for conv_std_logic_vector
entity tb_trivium is
port(
--Basic System Clock
clk_25 : in std_logic;
--Active low reset
rst : in std_logic;
--Next 8 bit input
nxt : in std_logic;
--Skip to next input i.e complete shift and go to iv input
skp : in std_logic;
--Use switches to shift in either
--80-bit in key or
--80-bit Initialization vector
input : in std_logic_vector(7 downto 0);
-- 7 Segment Display-bit output
segment_a_i : out std_logic;
segment_b_i : out std_logic;
segment_c_i : out std_logic;
segment_d_i : out std_logic;
segment_e_i : out std_logic;
segment_f_i : out std_logic;
segment_g_i : out std_logic;
-- 7 Segment Control
--Control Which of the four 7-Segment Display is active
AN : out std_logic_vector(3 downto 0);
--OUTPUT FOR DISPLAYING LED ON
swtch_led : out std_logic_vector(7 DOWNTO 0));
end tb_trivium;
architecture behavioral of tb_trivium is
--I/O CONTROLS
--used to check prev button state to determine button press
signal nxt_buf_cur : std_logic;
signal nxt_buf_prev : std_logic;
--used to check prev button state to determine button press
signal skp_buf_cur : std_logic;
signal skp_buf_prev : std_logic;
--STATE CONTROLS
-- trivium state machine has five states: keyInput, iv_input, run
TYPE StateType IS(
ST_IDLE, -- In this The System in powering on
ST_KEY_INPUT,-- In this state the key is added
ST_IV_INPUT, -- In this state the initialization vector is added
ST_RUN_SYST, -- In this Trivium is free to run its cipher
ST_READY -- In this state Trivium is producing proper encryption pattern
);
signal state : StateType;
--TRIVIUM CONTROLS
--Secret 80-bit key input port
signal key : std_logic_vector(79 downto 0);
--80-bit Initialization vector input port
signal IV : std_logic_vector(79 downto 0);
--shift in input counter for key and iv since input is 8 and size is 80
signal inputCnt : integer;
--reset for trivium active low
signal trivRst : std_logic;
--Output Data Valid
signal o_rdy : std_logic;
--Bit Stream
signal z_out : std_logic_vector(15 downto 0);
--This grants the ability to cycle through the buttons
signal hld : std_logic;
--LED CONTROLS
--LED Control
signal hex_digit_i : std_logic_vector(4 DOWNTO 0);
--Count to flash the LED
signal LED_flash_cnt : std_logic_vector(9 DOWNTO 0);
begin
state_control:
process(rst, clk_25) begin
if(rst='1') then
state<=ST_IDLE;
trivRst <= '1';
elsif(rising_edge(clk_25))then
case state is
when ST_IDLE=>
state<=ST_KEY_INPUT;
trivRst <= '1';
when ST_KEY_INPUT=>
--need to add or skip to if block
if(inputCnt = 10)then --10 = 80bits/(8 input bits)
state<=ST_IV_INPUT;
else
state<=ST_KEY_INPUT;
end if;
trivRst <= '1';
when ST_IV_INPUT=>
--need to add or skip to if block
if(inputCnt = 10)then --10 = 80bits/(8 input bits)
state<=ST_RUN_SYST;
trivRst <= '0';
else
state<= ST_IV_INPUT;
trivRst <= '1';
end if;
when ST_RUN_SYST=>
if(o_rdy = '1')then --Output ready to propogate
state<=ST_READY;
else
state<=ST_RUN_SYST;
end if;
trivRst <= '0';
when ST_READY=>
state<= ST_READY;
trivRst <= '0';
end case;
end if;
end process;
shift_in_input:
process(rst,clk_25)begin
if(rst='1')then
key <= (others => '0');
IV <= (others => '0');
inputCnt <= 0;
nxt_buf_cur <= '0';
skp_buf_cur <= '0';
nxt_buf_prev <= '0';
skp_buf_prev <= '0';
hld <= '1';
elsif(rising_edge(clk_25))then
case state is
when ST_KEY_INPUT | ST_IV_INPUT =>
--we check button press by determining if current state is 0 and prev state is 1
--first we impliment skp if it is tru then input count is automatically 10
if(skp_buf_prev = '1' and skp_buf_cur = '0')then
inputCnt <= 10;
elsif(nxt_buf_prev = '1' and nxt_buf_cur = '0')then
--count button presses
inputCnt <= inputCnt + 1;
--always shift into input
if(state = ST_KEY_INPUT)then
key(79 downto 0) <= key(71 downto 0) & input(7 downto 0);
else
IV(79 downto 0) <= IV(71 downto 0) & input(7 downto 0);
end if;
end if;
--Reset input count if it is too high
if(inputCnt = 10)then
inputCnt<=0;
end if;
when ST_READY =>
--Lets give the user the ability to cycle through the cipher 16 bits at a time
--And only if the previous 16 bits had already been ciphered
if(((skp_buf_prev = '1' and skp_buf_cur = '0') or
(nxt_buf_prev = '1' and nxt_buf_cur = '0'))
)then
hld <= '0';
else
hld <= '1';
end if;
when others =>
inputCnt <= 0;
end case;
--The press buttons on the Basys2 have capacitors in parallel with them
--As such their is no issue with bouncing and no debounce logic is needed.
nxt_buf_cur <= nxt;
skp_buf_cur <= skp;
--update prev button press
nxt_buf_prev <= nxt_buf_cur;
skp_buf_prev <= skp_buf_cur;
end if;
end process;
-------------------------------------------------
-------------------TRIVIUM-----------------------
-------------------------------------------------
--Trivium encryption algorithm
trivium : entity work.trivium
port map(
clk => clk_25,
rst => trivRst,
hld => hld,
key => key, --Secret 80-bit key input port
IV => IV, --80-bit Initialization vector input port
o_vld=> o_rdy, --Output Data Ready
z => z_Out --Cipher stream output
);
-------------------------------------------------
-------------------LED CONTROL-------------------
-------------------------------------------------
--hex to 7 Segment Display
hex2_7seg : entity work.hex_7seg
port map(
hex_digit => hex_digit_i,
segment_a => segment_a_i,
segment_b => segment_b_i,
segment_c => segment_c_i,
segment_d => segment_d_i,
segment_e => segment_e_i,
segment_f => segment_f_i,
segment_g => segment_g_i
);
--Flash the LED with the last 4 bytes of dout
process(rst,clk_25)
begin
if(rst='1')then
hex_digit_i <= (others => '0');
LED_flash_cnt <= (others => '0');
AN <= (others => '1');--All LED OFF
elsif(rising_edge(clk_25)) then
LED_flash_cnt <= LED_flash_cnt + '1';
if(state=ST_READY)then
case LED_flash_cnt(9 downto 8) is
when "00" =>
--First 7-Seg-LED
hex_digit_i <= '0' & z_out(15 downto 12);--LED output
AN <= "0111"; --Enables LED active low
when "01" =>
--Second 7-Seg-LED
hex_digit_i <= '0' & z_out(11 downto 8);
AN <= "1011";
when "10" =>
--Third 7-Seg-LED
hex_digit_i <= '0' & z_out( 7 downto 4);
AN <= "1101";
when "11" =>
--Fourth 7-Seg-LED
hex_digit_i <= '0' & z_out( 3 downto 0);
AN <= "1110";
when others => null;
end case;
elsif(state=ST_KEY_INPUT OR state=ST_IV_INPUT)then
--In the event that the system is in keyinput or iv state
--make the first two leds display LD and the last two count the numbers up
case LED_flash_cnt(9 downto 8) is
when "00" =>
--First 7-Seg-LED
hex_digit_i <= "10000";--Display 'L'
AN <= "0111";--Enables LED active low
when "01" =>
--Second 7-Seg-LED
hex_digit_i <= "01101";--Display 'd'
AN <= "1011";
when "10" =>
--Third 7-Seg-LED
hex_digit_i <= "10001";--Display '-'
AN <= "1101";
when "11" =>
--Fourth 7-Seg-LED
--the Mod operator and conv_integer function is incredibly costly
hex_digit_i <= conv_std_logic_vector(inputCnt,5);
AN <= "1110";
when others => null;
end case;
else
--Just turn everything off otherwise
hex_digit_i <= (others=>'1');
AN <= (others=>'1');
end if;
end if;
end process;
--Quick trick to enable led over switches if active
swtch_led <= input;
end behavioral; | lgpl-2.1 | cad51d9d25f5bf1db96e00d9848c2e62 | 0.518716 | 3.417469 | false | false | false | false |
nsauzede/cpu86 | papilio2_vga/font_rom.vhd | 4 | 49,333 | -- Listing 13.1
-- ROM with synchonous read (inferring Block RAM)
-- character ROM
-- - 8-by-16 (8-by-2^4) font
-- - 128 (2^7) characters
-- - ROM size: 512-by-8 (2^11-by-8) bits
-- 16K bits: 1 BRAM
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity font_rom is
port(
clock: in std_logic;
addr: in std_logic_vector(10 downto 0);
data: out std_logic_vector(7 downto 0)
);
end font_rom;
architecture arch of font_rom is
constant ADDR_WIDTH: integer:=11;
constant DATA_WIDTH: integer:=8;
signal addr_reg: std_logic_vector(ADDR_WIDTH-1 downto 0);
type rom_type is array (0 to 2**ADDR_WIDTH-1)
of std_logic_vector(DATA_WIDTH-1 downto 0);
-- ROM definition - 2^11-by-8
constant ROM: rom_type := (
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x01
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"10000001", -- 3 * *
"10100101", -- 4 * * * *
"10000001", -- 5 * *
"10000001", -- 6 * *
"10111101", -- 7 * **** *
"10011001", -- 8 * ** *
"10000001", -- 9 * *
"10000001", -- a * *
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x02
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"11111111", -- 3 ********
"11011011", -- 4 ** ** **
"11111111", -- 5 ********
"11111111", -- 6 ********
"11000011", -- 7 ** **
"11100111", -- 8 *** ***
"11111111", -- 9 ********
"11111111", -- a ********
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x03
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"01101100", -- 4 ** **
"11111110", -- 5 *******
"11111110", -- 6 *******
"11111110", -- 7 *******
"11111110", -- 8 *******
"01111100", -- 9 *****
"00111000", -- a ***
"00010000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x04
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01111100", -- 6 *****
"11111110", -- 7 *******
"01111100", -- 8 *****
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x05
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"00111100", -- 5 ****
"11100111", -- 6 *** ***
"11100111", -- 7 *** ***
"11100111", -- 8 *** ***
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x06
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"01111110", -- 5 ******
"11111111", -- 6 ********
"11111111", -- 7 ********
"01111110", -- 8 ******
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x07
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00011000", -- 6 **
"00111100", -- 7 ****
"00111100", -- 8 ****
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x08
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11111111", -- 5 ********
"11100111", -- 6 *** ***
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11100111", -- 9 *** ***
"11111111", -- a ********
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x09
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00111100", -- 5 ****
"01100110", -- 6 ** **
"01000010", -- 7 * *
"01000010", -- 8 * *
"01100110", -- 9 ** **
"00111100", -- a ****
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0a
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11000011", -- 5 ** **
"10011001", -- 6 * ** *
"10111101", -- 7 * **** *
"10111101", -- 8 * **** *
"10011001", -- 9 * ** *
"11000011", -- a ** **
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x0b
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001110", -- 3 ***
"00011010", -- 4 ** *
"00110010", -- 5 ** *
"01111000", -- 6 ****
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0c
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"01111110", -- 9 ******
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0d
"00000000", -- 0
"00000000", -- 1
"00111111", -- 2 ******
"00110011", -- 3 ** **
"00111111", -- 4 ******
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"01110000", -- 9 ***
"11110000", -- a ****
"11100000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0e
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"01100011", -- 3 ** **
"01111111", -- 4 *******
"01100011", -- 5 ** **
"01100011", -- 6 ** **
"01100011", -- 7 ** **
"01100011", -- 8 ** **
"01100111", -- 9 ** ***
"11100111", -- a *** ***
"11100110", -- b *** **
"11000000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00011000", -- 4 **
"11011011", -- 5 ** ** **
"00111100", -- 6 ****
"11100111", -- 7 *** ***
"00111100", -- 8 ****
"11011011", -- 9 ** ** **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x10
"00000000", -- 0
"10000000", -- 1 *
"11000000", -- 2 **
"11100000", -- 3 ***
"11110000", -- 4 ****
"11111000", -- 5 *****
"11111110", -- 6 *******
"11111000", -- 7 *****
"11110000", -- 8 ****
"11100000", -- 9 ***
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x11
"00000000", -- 0
"00000010", -- 1 *
"00000110", -- 2 **
"00001110", -- 3 ***
"00011110", -- 4 ****
"00111110", -- 5 *****
"11111110", -- 6 *******
"00111110", -- 7 *****
"00011110", -- 8 ****
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x12
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x13
"00000000", -- 0
"00000000", -- 1
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"00000000", -- 9
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x14
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"11011011", -- 3 ** ** **
"11011011", -- 4 ** ** **
"11011011", -- 5 ** ** **
"01111011", -- 6 **** **
"00011011", -- 7 ** **
"00011011", -- 8 ** **
"00011011", -- 9 ** **
"00011011", -- a ** **
"00011011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x15
"00000000", -- 0
"01111100", -- 1 *****
"11000110", -- 2 ** **
"01100000", -- 3 **
"00111000", -- 4 ***
"01101100", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"01101100", -- 8 ** **
"00111000", -- 9 ***
"00001100", -- a **
"11000110", -- b ** **
"01111100", -- c *****
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x16
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"11111110", -- 8 *******
"11111110", -- 9 *******
"11111110", -- a *******
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x17
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"01111110", -- b ******
"00110000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x18
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x19
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"01111110", -- 9 ******
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00001100", -- 6 **
"11111110", -- 7 *******
"00001100", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1b
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00110000", -- 5 **
"01100000", -- 6 **
"11111110", -- 7 *******
"01100000", -- 8 **
"00110000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11111110", -- 9 *******
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1d
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00100100", -- 5 * *
"01100110", -- 6 ** **
"11111111", -- 7 ********
"01100110", -- 8 ** **
"00100100", -- 9 * *
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"00111000", -- 6 ***
"01111100", -- 7 *****
"01111100", -- 8 *****
"11111110", -- 9 *******
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11111110", -- 4 *******
"11111110", -- 5 *******
"01111100", -- 6 *****
"01111100", -- 7 *****
"00111000", -- 8 ***
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x20
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x21
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"00111100", -- 4 ****
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x22
"00000000", -- 0
"01100110", -- 1 ** **
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"00100100", -- 4 * *
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x23
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"11111110", -- 5 *******
"01101100", -- 6 ** **
"01101100", -- 7 ** **
"01101100", -- 8 ** **
"11111110", -- 9 *******
"01101100", -- a ** **
"01101100", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x24
"00011000", -- 0 **
"00011000", -- 1 **
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"01111100", -- 6 *****
"00000110", -- 7 **
"00000110", -- 8 **
"10000110", -- 9 * **
"11000110", -- a ** **
"01111100", -- b *****
"00011000", -- c **
"00011000", -- d **
"00000000", -- e
"00000000", -- f
-- code x25
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11000010", -- 4 ** *
"11000110", -- 5 ** **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"10000110", -- b * **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x26
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"00111000", -- 5 ***
"01110110", -- 6 *** **
"11011100", -- 7 ** ***
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x27
"00000000", -- 0
"00110000", -- 1 **
"00110000", -- 2 **
"00110000", -- 3 **
"01100000", -- 4 **
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x28
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00011000", -- a **
"00001100", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x29
"00000000", -- 0
"00000000", -- 1
"00110000", -- 2 **
"00011000", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01100110", -- 5 ** **
"00111100", -- 6 ****
"11111111", -- 7 ********
"00111100", -- 8 ****
"01100110", -- 9 ** **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2b
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00011000", -- 6 **
"01111110", -- 7 ******
"00011000", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00110000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2d
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"01111110", -- 7 ******
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000010", -- 4 *
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x30
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11001110", -- 5 ** ***
"11011110", -- 6 ** ****
"11110110", -- 7 **** **
"11100110", -- 8 *** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x31
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2
"00111000", -- 3
"01111000", -- 4 **
"00011000", -- 5 ***
"00011000", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01111110", -- b **
"00000000", -- c **
"00000000", -- d ******
"00000000", -- e
"00000000", -- f
-- code x32
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x33
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00111100", -- 6 ****
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x34
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011100", -- 3 ***
"00111100", -- 4 ****
"01101100", -- 5 ** **
"11001100", -- 6 ** **
"11111110", -- 7 *******
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00011110", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x35
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x36
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01100000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x37
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x38
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111100", -- 6 *****
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x39
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111110", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00001100", -- a **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3b
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000110", -- 3 **
"00001100", -- 4 **
"00011000", -- 5 **
"00110000", -- 6 **
"01100000", -- 7 **
"00110000", -- 8 **
"00011000", -- 9 **
"00001100", -- a **
"00000110", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3d
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111110", -- 5 ******
"00000000", -- 6
"00000000", -- 7
"01111110", -- 8 ******
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01100000", -- 3 **
"00110000", -- 4 **
"00011000", -- 5 **
"00001100", -- 6 **
"00000110", -- 7 **
"00001100", -- 8 **
"00011000", -- 9 **
"00110000", -- a **
"01100000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3f
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"00001100", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x40
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11011110", -- 6 ** ****
"11011110", -- 7 ** ****
"11011110", -- 8 ** ****
"11011100", -- 9 ** ***
"11000000", -- a **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x41
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00111000", -- 3 ***
"01101100", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x42
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11111100", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x43
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11000010", -- 9 ** *
"01100110", -- a ** **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x44
"00000000", -- 0
"00000000", -- 1
"11111000", -- 2 *****
"01101100", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01101100", -- a ** **
"11111000", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x45
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x46
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x47
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11011110", -- 7 ** ****
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"01100110", -- a ** **
"00111010", -- b *** *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x48
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11111110", -- 6 *******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x49
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4a
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4b
"00000000", -- 0
"00000000", -- 1
"11100110", -- 2 *** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01101100", -- 5 ** **
"01111000", -- 6 ****
"01111000", -- 7 ****
"01101100", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4c
"00000000", -- 0
"00000000", -- 1
"11110000", -- 2 ****
"01100000", -- 3 **
"01100000", -- 4 **
"01100000", -- 5 **
"01100000", -- 6 **
"01100000", -- 7 **
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4d
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11100111", -- 3 *** ***
"11111111", -- 4 ********
"11111111", -- 5 ********
"11011011", -- 6 ** ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11000011", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4e
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11100110", -- 3 *** **
"11110110", -- 4 **** **
"11111110", -- 5 *******
"11011110", -- 6 ** ****
"11001110", -- 7 ** ***
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4f
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x50
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x510
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11010110", -- 9 ** * **
"11011110", -- a ** ****
"01111100", -- b *****
"00001100", -- c **
"00001110", -- d ***
"00000000", -- e
"00000000", -- f
-- code x52
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01101100", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x53
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"01100000", -- 5 **
"00111000", -- 6 ***
"00001100", -- 7 **
"00000110", -- 8 **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x54
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11011011", -- 3 ** ** **
"10011001", -- 4 * ** *
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x55
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x56
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x57
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11111111", -- 9 ********
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x58
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"01100110", -- 4 ** **
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00111100", -- 8 ****
"01100110", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x59
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"01100110", -- 5 ** **
"00111100", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5a
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11000011", -- 3 ** **
"10000110", -- 4 * **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000001", -- 9 ** *
"11000011", -- a ** **
"11111111", -- b ********
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5b
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00110000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"10000000", -- 3 *
"11000000", -- 4 **
"11100000", -- 5 ***
"01110000", -- 6 ***
"00111000", -- 7 ***
"00011100", -- 8 ***
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5d
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5e
"00010000", -- 0 *
"00111000", -- 1 ***
"01101100", -- 2 ** **
"11000110", -- 3 ** **
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"11111111", -- d ********
"00000000", -- e
"00000000", -- f
-- code x60
"00110000", -- 0 **
"00110000", -- 1 **
"00011000", -- 2 **
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x61
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111000", -- 5 ****
"00001100", -- 6 **
"01111100", -- 7 *****
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x62
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01111000", -- 5 ****
"01101100", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x63
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000000", -- 7 **
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x64
"00000000", -- 0
"00000000", -- 1
"00011100", -- 2 ***
"00001100", -- 3 **
"00001100", -- 4 **
"00111100", -- 5 ****
"01101100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x65
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x66
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01100100", -- 4 ** *
"01100000", -- 5 **
"11110000", -- 6 ****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x67
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"11001100", -- d ** **
"01111000", -- e ****
"00000000", -- f
-- code x68
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01101100", -- 5 ** **
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x69
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00000000", -- 4
"00111000", -- 5 ***
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6a
"00000000", -- 0
"00000000", -- 1
"00000110", -- 2 **
"00000110", -- 3 **
"00000000", -- 4
"00001110", -- 5 ***
"00000110", -- 6 **
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00000110", -- a **
"00000110", -- b **
"01100110", -- c ** **
"01100110", -- d ** **
"00111100", -- e ****
"00000000", -- f
-- code x6b
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01100110", -- 5 ** **
"01101100", -- 6 ** **
"01111000", -- 7 ****
"01111000", -- 8 ****
"01101100", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6c
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6d
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11100110", -- 5 *** **
"11111111", -- 6 ********
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11011011", -- a ** ** **
"11011011", -- b ** ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x70
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"01100000", -- c **
"01100000", -- d **
"11110000", -- e ****
"00000000", -- f
-- code x71
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"00001100", -- d **
"00011110", -- e ****
"00000000", -- f
-- code x72
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x73
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"01100000", -- 7 **
"00111000", -- 8 ***
"00001100", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x74
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00110000", -- 3 **
"00110000", -- 4 **
"11111100", -- 5 ******
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110110", -- a ** **
"00011100", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x75
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11001100", -- 5 ** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x76
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x77
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11111111", -- a ********
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x78
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"00111100", -- 9 ****
"01100110", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x79
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111110", -- b ******
"00000110", -- c **
"00001100", -- d **
"11111000", -- e *****
"00000000", -- f
-- code x7a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11111110", -- 5 *******
"11001100", -- 6 ** **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7b
"00000000", -- 0
"00000000", -- 1
"00001110", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"01110000", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00001110", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7c
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7d
"00000000", -- 0
"00000000", -- 1
"01110000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00001110", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01110000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7e
"00000000", -- 0
"00000000", -- 1
"01110110", -- 2 *** **
"11011100", -- 3 ** ***
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01101100", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000" -- f
);
begin
-- addr register to infer block RAM
process(clock)
begin
if clock'event and clock = '1' then
addr_reg <= addr;
end if;
end process;
data <= ROM(to_integer(unsigned(addr_reg)));
end arch;
| gpl-2.0 | 6a6287419bdc75dd5e9ae15077947e2a | 0.404658 | 2.734494 | false | false | false | false |
nsauzede/cpu86 | top_rtl/Bootstrap_rtl.vhd | 8 | 12,612 | --***********************************************************
-- CPU86 ROM File
-- Module Name : bootstrap
--***********************************************************
library ieee;
use ieee.std_logic_1164.ALL;
entity bootstrap is
port(abus : in std_logic_vector(7 downto 0);
dbus : out std_logic_vector(7 downto 0));
end bootstrap;
architecture rtl of bootstrap is
begin
process(abus)
begin
case abus is
when "00000000" => dbus <= X"90";
when "00000001" => dbus <= X"90";
when "00000010" => dbus <= X"90";
when "00000011" => dbus <= X"90";
when "00000100" => dbus <= X"90";
when "00000101" => dbus <= X"90";
when "00000110" => dbus <= X"90";
when "00000111" => dbus <= X"90";
when "00001000" => dbus <= X"90";
when "00001001" => dbus <= X"90";
when "00001010" => dbus <= X"90";
when "00001011" => dbus <= X"90";
when "00001100" => dbus <= X"90";
when "00001101" => dbus <= X"90";
when "00001110" => dbus <= X"90";
when "00001111" => dbus <= X"90";
when "00010000" => dbus <= X"90";
when "00010001" => dbus <= X"90";
when "00010010" => dbus <= X"90";
when "00010011" => dbus <= X"90";
when "00010100" => dbus <= X"90";
when "00010101" => dbus <= X"90";
when "00010110" => dbus <= X"90";
when "00010111" => dbus <= X"90";
when "00011000" => dbus <= X"90";
when "00011001" => dbus <= X"90";
when "00011010" => dbus <= X"90";
when "00011011" => dbus <= X"90";
when "00011100" => dbus <= X"90";
when "00011101" => dbus <= X"90";
when "00011110" => dbus <= X"90";
when "00011111" => dbus <= X"90";
when "00100000" => dbus <= X"90";
when "00100001" => dbus <= X"90";
when "00100010" => dbus <= X"90";
when "00100011" => dbus <= X"90";
when "00100100" => dbus <= X"90";
when "00100101" => dbus <= X"90";
when "00100110" => dbus <= X"90";
when "00100111" => dbus <= X"90";
when "00101000" => dbus <= X"90";
when "00101001" => dbus <= X"90";
when "00101010" => dbus <= X"90";
when "00101011" => dbus <= X"90";
when "00101100" => dbus <= X"90";
when "00101101" => dbus <= X"90";
when "00101110" => dbus <= X"90";
when "00101111" => dbus <= X"90";
when "00110000" => dbus <= X"90";
when "00110001" => dbus <= X"90";
when "00110010" => dbus <= X"90";
when "00110011" => dbus <= X"90";
when "00110100" => dbus <= X"90";
when "00110101" => dbus <= X"90";
when "00110110" => dbus <= X"90";
when "00110111" => dbus <= X"90";
when "00111000" => dbus <= X"90";
when "00111001" => dbus <= X"90";
when "00111010" => dbus <= X"90";
when "00111011" => dbus <= X"90";
when "00111100" => dbus <= X"90";
when "00111101" => dbus <= X"90";
when "00111110" => dbus <= X"90";
when "00111111" => dbus <= X"90";
when "01000000" => dbus <= X"90";
when "01000001" => dbus <= X"90";
when "01000010" => dbus <= X"90";
when "01000011" => dbus <= X"90";
when "01000100" => dbus <= X"90";
when "01000101" => dbus <= X"90";
when "01000110" => dbus <= X"90";
when "01000111" => dbus <= X"90";
when "01001000" => dbus <= X"90";
when "01001001" => dbus <= X"90";
when "01001010" => dbus <= X"90";
when "01001011" => dbus <= X"90";
when "01001100" => dbus <= X"90";
when "01001101" => dbus <= X"90";
when "01001110" => dbus <= X"90";
when "01001111" => dbus <= X"90";
when "01010000" => dbus <= X"90";
when "01010001" => dbus <= X"90";
when "01010010" => dbus <= X"90";
when "01010011" => dbus <= X"90";
when "01010100" => dbus <= X"90";
when "01010101" => dbus <= X"90";
when "01010110" => dbus <= X"90";
when "01010111" => dbus <= X"90";
when "01011000" => dbus <= X"90";
when "01011001" => dbus <= X"90";
when "01011010" => dbus <= X"90";
when "01011011" => dbus <= X"90";
when "01011100" => dbus <= X"90";
when "01011101" => dbus <= X"90";
when "01011110" => dbus <= X"90";
when "01011111" => dbus <= X"90";
when "01100000" => dbus <= X"90";
when "01100001" => dbus <= X"90";
when "01100010" => dbus <= X"90";
when "01100011" => dbus <= X"90";
when "01100100" => dbus <= X"90";
when "01100101" => dbus <= X"90";
when "01100110" => dbus <= X"90";
when "01100111" => dbus <= X"90";
when "01101000" => dbus <= X"90";
when "01101001" => dbus <= X"90";
when "01101010" => dbus <= X"90";
when "01101011" => dbus <= X"90";
when "01101100" => dbus <= X"90";
when "01101101" => dbus <= X"90";
when "01101110" => dbus <= X"90";
when "01101111" => dbus <= X"90";
when "01110000" => dbus <= X"90";
when "01110001" => dbus <= X"90";
when "01110010" => dbus <= X"90";
when "01110011" => dbus <= X"90";
when "01110100" => dbus <= X"90";
when "01110101" => dbus <= X"90";
when "01110110" => dbus <= X"90";
when "01110111" => dbus <= X"90";
when "01111000" => dbus <= X"90";
when "01111001" => dbus <= X"90";
when "01111010" => dbus <= X"90";
when "01111011" => dbus <= X"90";
when "01111100" => dbus <= X"90";
when "01111101" => dbus <= X"90";
when "01111110" => dbus <= X"90";
when "01111111" => dbus <= X"90";
when "10000000" => dbus <= X"90";
when "10000001" => dbus <= X"90";
when "10000010" => dbus <= X"90";
when "10000011" => dbus <= X"90";
when "10000100" => dbus <= X"90";
when "10000101" => dbus <= X"90";
when "10000110" => dbus <= X"90";
when "10000111" => dbus <= X"90";
when "10001000" => dbus <= X"90";
when "10001001" => dbus <= X"90";
when "10001010" => dbus <= X"90";
when "10001011" => dbus <= X"90";
when "10001100" => dbus <= X"90";
when "10001101" => dbus <= X"90";
when "10001110" => dbus <= X"90";
when "10001111" => dbus <= X"90";
when "10010000" => dbus <= X"90";
when "10010001" => dbus <= X"90";
when "10010010" => dbus <= X"90";
when "10010011" => dbus <= X"90";
when "10010100" => dbus <= X"90";
when "10010101" => dbus <= X"90";
when "10010110" => dbus <= X"90";
when "10010111" => dbus <= X"90";
when "10011000" => dbus <= X"90";
when "10011001" => dbus <= X"90";
when "10011010" => dbus <= X"90";
when "10011011" => dbus <= X"90";
when "10011100" => dbus <= X"90";
when "10011101" => dbus <= X"90";
when "10011110" => dbus <= X"90";
when "10011111" => dbus <= X"90";
when "10100000" => dbus <= X"90";
when "10100001" => dbus <= X"90";
when "10100010" => dbus <= X"90";
when "10100011" => dbus <= X"90";
when "10100100" => dbus <= X"90";
when "10100101" => dbus <= X"90";
when "10100110" => dbus <= X"90";
when "10100111" => dbus <= X"90";
when "10101000" => dbus <= X"90";
when "10101001" => dbus <= X"90";
when "10101010" => dbus <= X"90";
when "10101011" => dbus <= X"90";
when "10101100" => dbus <= X"90";
when "10101101" => dbus <= X"90";
when "10101110" => dbus <= X"90";
when "10101111" => dbus <= X"90";
when "10110000" => dbus <= X"90";
when "10110001" => dbus <= X"90";
when "10110010" => dbus <= X"90";
when "10110011" => dbus <= X"90";
when "10110100" => dbus <= X"90";
when "10110101" => dbus <= X"90";
when "10110110" => dbus <= X"90";
when "10110111" => dbus <= X"90";
when "10111000" => dbus <= X"90";
when "10111001" => dbus <= X"90";
when "10111010" => dbus <= X"90";
when "10111011" => dbus <= X"90";
when "10111100" => dbus <= X"90";
when "10111101" => dbus <= X"90";
when "10111110" => dbus <= X"90";
when "10111111" => dbus <= X"90";
when "11000000" => dbus <= X"90";
when "11000001" => dbus <= X"90";
when "11000010" => dbus <= X"90";
when "11000011" => dbus <= X"90";
when "11000100" => dbus <= X"90";
when "11000101" => dbus <= X"90";
when "11000110" => dbus <= X"90";
when "11000111" => dbus <= X"90";
when "11001000" => dbus <= X"90";
when "11001001" => dbus <= X"90";
when "11001010" => dbus <= X"90";
when "11001011" => dbus <= X"90";
when "11001100" => dbus <= X"90";
when "11001101" => dbus <= X"90";
when "11001110" => dbus <= X"90";
when "11001111" => dbus <= X"90";
when "11010000" => dbus <= X"90";
when "11010001" => dbus <= X"90";
when "11010010" => dbus <= X"90";
when "11010011" => dbus <= X"90";
when "11010100" => dbus <= X"90";
when "11010101" => dbus <= X"90";
when "11010110" => dbus <= X"90";
when "11010111" => dbus <= X"90";
when "11011000" => dbus <= X"90";
when "11011001" => dbus <= X"90";
when "11011010" => dbus <= X"90";
when "11011011" => dbus <= X"90";
when "11011100" => dbus <= X"90";
when "11011101" => dbus <= X"90";
when "11011110" => dbus <= X"90";
when "11011111" => dbus <= X"90";
when "11100000" => dbus <= X"90";
when "11100001" => dbus <= X"90";
when "11100010" => dbus <= X"90";
when "11100011" => dbus <= X"90";
when "11100100" => dbus <= X"90";
when "11100101" => dbus <= X"90";
when "11100110" => dbus <= X"90";
when "11100111" => dbus <= X"90";
when "11101000" => dbus <= X"90";
when "11101001" => dbus <= X"90";
when "11101010" => dbus <= X"90";
when "11101011" => dbus <= X"90";
when "11101100" => dbus <= X"90";
when "11101101" => dbus <= X"90";
when "11101110" => dbus <= X"90";
when "11101111" => dbus <= X"90";
when "11110000" => dbus <= X"EA";
when "11110001" => dbus <= X"00";
when "11110010" => dbus <= X"04";
when "11110011" => dbus <= X"00";
when "11110100" => dbus <= X"00";
when "11110101" => dbus <= X"00";
when others => dbus <= "--------";
end case;
end process;
end rtl;
| gpl-2.0 | 6cd547372e0749d7a419492f56a7eba1 | 0.390422 | 3.795366 | false | false | false | false |
VenturaSolutionsInc/VHDL | igmp/igmp_processor_tb.vhd | 1 | 3,806 | -------------------------------------------------------------------------------
-- Title : Testbench for design "igmp_processor"
-- Project :
-------------------------------------------------------------------------------
-- File : igmp_processor_tb.vhd
-- Author : <sheac@DRESDEN>
-- Company :
-- Created : 2010-06-26
-- Last update: 2010-06-27
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2010
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-06-26 1.0 sheac Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity igmp_processor_tb is
end igmp_processor_tb;
architecture testbench of igmp_processor_tb is
component igmp_processor
generic (
gen_dataWidth : integer);
port (
dataClk : in std_logic;
reset : in std_logic;
in_destIP : in std_logic_vector(31 downto 0);
igmp_data : in std_logic_vector(gen_dataWidth - 1 downto 0);
igmp_vld : in std_logic;
igmp_sof : in std_logic;
igmp_eof : in std_logic;
respond : out std_logic;
rsptime : out std_logic_vector(gen_dataWidth - 1 downto 0));
end component;
-- component generics
constant gen_dataWidth : integer := 8;
-- component ports
signal dataClk : std_logic;
signal reset : std_logic;
signal in_destIP : std_logic_vector(31 downto 0);
signal igmp_data : std_logic_vector(gen_dataWidth - 1 downto 0);
signal igmp_vld : std_logic;
signal igmp_sof : std_logic;
signal igmp_eof : std_logic;
signal respond : std_logic;
signal rsptime : std_logic_vector(gen_dataWidth - 1 downto 0);
begin -- testbench
-- component instantiation
DUT: igmp_processor
generic map (
gen_dataWidth => gen_dataWidth)
port map (
dataClk => dataClk,
reset => reset,
in_destIP => in_destIP,
igmp_data => igmp_data,
igmp_vld => igmp_vld,
igmp_sof => igmp_sof,
igmp_eof => igmp_eof,
respond => respond,
rsptime => rsptime);
process
begin
dataClk <= '1';
wait for 4 ns;
dataClk <= '0';
wait for 4 ns;
end process;
in_destIP <= X"E1234223";
process
begin
reset <= '1';
igmp_data <= (others => '0');
igmp_vld <= '0';
igmp_sof <= '0';
igmp_eof <= '0';
wait for 24 ns;
reset <= '0';
wait for 16 ns;
igmp_data <= X"11";
igmp_vld <= '1';
igmp_sof <= '1';
igmp_eof <= '0';
wait for 8 ns;
igmp_data <= X"64";
igmp_vld <= '1';
igmp_sof <= '0';
igmp_eof <= '0';
wait for 8 ns;
igmp_data <= X"12";
igmp_vld <= '1';
igmp_sof <= '0';
igmp_eof <= '0';
wait for 8 ns;
igmp_data <= X"56";
igmp_vld <= '1';
igmp_sof <= '0';
igmp_eof <= '0';
wait for 8 ns;
igmp_data <= X"E1";
igmp_vld <= '1';
igmp_sof <= '0';
igmp_eof <= '0';
wait for 8 ns;
igmp_data <= X"23";
igmp_vld <= '1';
igmp_sof <= '0';
igmp_eof <= '0';
wait for 8 ns;
igmp_data <= X"42";
igmp_vld <= '1';
igmp_sof <= '0';
igmp_eof <= '0';
wait for 8 ns;
igmp_data <= X"23";
igmp_vld <= '1';
igmp_sof <= '0';
igmp_eof <= '1';
wait for 8 ns;
igmp_eof <= '0';
wait;
end process;
end testbench;
| gpl-2.0 | 3fa3a5d933ae5fa941b947e91702dad4 | 0.45113 | 3.775794 | false | false | false | false |
ismailalmahdi/HMAC-SHA384-VHDL | hmac_sha384.vhd | 1 | 1,162 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
use work.HMACSHA384_ISMAIL.all;
entity hmac_sha384 is
port ( clk: in std_logic;
salt : in std_logic_vector(383 downto 0);
pepper : in std_logic_vector(1023 downto 0);
small_msg: in std_logic_vector((6*4)-1 downto 0);
medium_msg: in std_logic_vector((46*4)-1 downto 0);
big_msg: in std_logic_vector((126*4)-1 downto 0);
hashed_code: out std_logic_vector(383 downto 0));
end entity ; -- main
architecture sha_behaviour of hmac_sha384 is
type msg is (small, medium, big);
signal cur_state, next_state : msg := small;
begin
p0: process(clk) is
begin
if (rising_edge(clk)) then
cur_state <= next_state;
end if;
end process;
p1: process (small_msg,medium_msg,big_msg,cur_state) is
begin
case (cur_state) is
when small =>
next_state <= medium;
hashed_code <= hmacsha384(salt,pepper,small_msg);
when medium =>
next_state <= big;
hashed_code <= hmacsha384(salt,pepper,medium_msg);
when big =>
next_state <= small;
hashed_code <= hmacsha384(salt,pepper,big_msg);
end case;
end process;
end architecture;
| mit | 20259a235cd46e19e6d239529d8c5aba | 0.663511 | 2.941772 | false | false | false | false |
nsauzede/cpu86 | papilio1/kcuart_tx.vhd | 1 | 11,705 | -- Constant (K) Compact UART Transmitter
--
-- Version : 1.10
-- Version Date : 3rd December 2003
-- Reason : '--translate' directives changed to '--synthesis translate' directives
--
-- Version : 1.00
-- Version Date : 14th October 2002
--
-- Start of design entry : 2nd October 2002
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- [email protected]
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
-- third parties. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
------------------------------------------------------------------------------------
--
-- Main Entity for KCUART_TX
--
entity kcuart_tx is
Port ( data_in : in std_logic_vector(7 downto 0);
send_character : in std_logic;
en_16_x_baud : in std_logic;
serial_out : out std_logic;
Tx_complete : out std_logic;
clk : in std_logic);
end kcuart_tx;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for KCUART_TX
--
architecture low_level_definition of kcuart_tx is
--
------------------------------------------------------------------------------------
--
------------------------------------------------------------------------------------
--
-- Signals used in KCUART_TX
--
------------------------------------------------------------------------------------
--
signal data_01 : std_logic;
signal data_23 : std_logic;
signal data_45 : std_logic;
signal data_67 : std_logic;
signal data_0123 : std_logic;
signal data_4567 : std_logic;
signal data_01234567 : std_logic;
signal bit_select : std_logic_vector(2 downto 0);
signal next_count : std_logic_vector(2 downto 0);
signal mask_count : std_logic_vector(2 downto 0);
signal mask_count_carry : std_logic_vector(2 downto 0);
signal count_carry : std_logic_vector(2 downto 0);
signal ready_to_start : std_logic;
signal decode_Tx_start : std_logic;
signal Tx_start : std_logic;
signal decode_Tx_run : std_logic;
signal Tx_run : std_logic;
signal decode_hot_state : std_logic;
signal hot_state : std_logic;
signal hot_delay : std_logic;
signal Tx_bit : std_logic;
signal decode_Tx_stop : std_logic;
signal Tx_stop : std_logic;
signal decode_Tx_complete : std_logic;
--
--
------------------------------------------------------------------------------------
--
-- Attributes to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation--
--
------------------------------------------------------------------------------------
--
attribute INIT : string;
attribute INIT of mux1_lut : label is "E4FF";
attribute INIT of mux2_lut : label is "E4FF";
attribute INIT of mux3_lut : label is "E4FF";
attribute INIT of mux4_lut : label is "E4FF";
attribute INIT of ready_lut : label is "10";
attribute INIT of start_lut : label is "0190";
attribute INIT of run_lut : label is "1540";
attribute INIT of hot_state_lut : label is "94";
attribute INIT of delay14_srl : label is "0000";
attribute INIT of stop_lut : label is "0180";
attribute INIT of complete_lut : label is "8";
--
------------------------------------------------------------------------------------
--
-- Start of KCUART_TX circuit description
--
------------------------------------------------------------------------------------
--
begin
-- 8 to 1 multiplexer to convert parallel data to serial
mux1_lut: LUT4
--synthesis translate_off
generic map (INIT => X"E4FF")
--synthesis translate_on
port map( I0 => bit_select(0),
I1 => data_in(0),
I2 => data_in(1),
I3 => Tx_run,
O => data_01 );
mux2_lut: LUT4
--synthesis translate_off
generic map (INIT => X"E4FF")
--synthesis translate_on
port map( I0 => bit_select(0),
I1 => data_in(2),
I2 => data_in(3),
I3 => Tx_run,
O => data_23 );
mux3_lut: LUT4
--synthesis translate_off
generic map (INIT => X"E4FF")
--synthesis translate_on
port map( I0 => bit_select(0),
I1 => data_in(4),
I2 => data_in(5),
I3 => Tx_run,
O => data_45 );
mux4_lut: LUT4
--synthesis translate_off
generic map (INIT => X"E4FF")
--synthesis translate_on
port map( I0 => bit_select(0),
I1 => data_in(6),
I2 => data_in(7),
I3 => Tx_run,
O => data_67 );
mux5_muxf5: MUXF5
port map( I1 => data_23,
I0 => data_01,
S => bit_select(1),
O => data_0123 );
mux6_muxf5: MUXF5
port map( I1 => data_67,
I0 => data_45,
S => bit_select(1),
O => data_4567 );
mux7_muxf6: MUXF6
port map( I1 => data_4567,
I0 => data_0123,
S => bit_select(2),
O => data_01234567 );
-- Register serial output and force start and stop bits
pipeline_serial: FDRS
port map ( D => data_01234567,
Q => serial_out,
R => Tx_start,
S => Tx_stop,
C => clk);
-- 3-bit counter
-- Counter is clock enabled by en_16_x_baud
-- Counter will be reset when 'Tx_start' is active
-- Counter will increment when Tx_bit is active
-- Tx_run must be active to count
-- count_carry(2) indicates when terminal count (7) is reached and Tx_bit=1 (ie overflow)
count_width_loop: for i in 0 to 2 generate
--
attribute INIT : string;
attribute INIT of count_lut : label is "8";
--
begin
register_bit: FDRE
port map ( D => next_count(i),
Q => bit_select(i),
CE => en_16_x_baud,
R => Tx_start,
C => clk);
count_lut: LUT2
--synthesis translate_off
generic map (INIT => X"8")
--synthesis translate_on
port map( I0 => bit_select(i),
I1 => Tx_run,
O => mask_count(i));
mask_and: MULT_AND
port map( I0 => bit_select(i),
I1 => Tx_run,
LO => mask_count_carry(i));
lsb_count: if i=0 generate
begin
count_muxcy: MUXCY
port map( DI => mask_count_carry(i),
CI => Tx_bit,
S => mask_count(i),
O => count_carry(i));
count_xor: XORCY
port map( LI => mask_count(i),
CI => Tx_bit,
O => next_count(i));
end generate lsb_count;
upper_count: if i>0 generate
begin
count_muxcy: MUXCY
port map( DI => mask_count_carry(i),
CI => count_carry(i-1),
S => mask_count(i),
O => count_carry(i));
count_xor: XORCY
port map( LI => mask_count(i),
CI => count_carry(i-1),
O => next_count(i));
end generate upper_count;
end generate count_width_loop;
-- Ready to start decode
ready_lut: LUT3
--synthesis translate_off
generic map (INIT => X"10")
--synthesis translate_on
port map( I0 => Tx_run,
I1 => Tx_start,
I2 => send_character,
O => ready_to_start );
-- Start bit enable
start_lut: LUT4
--synthesis translate_off
generic map (INIT => X"0190")
--synthesis translate_on
port map( I0 => Tx_bit,
I1 => Tx_stop,
I2 => ready_to_start,
I3 => Tx_start,
O => decode_Tx_start );
Tx_start_reg: FDE
port map ( D => decode_Tx_start,
Q => Tx_start,
CE => en_16_x_baud,
C => clk);
-- Run bit enable
run_lut: LUT4
--synthesis translate_off
generic map (INIT => X"1540")
--synthesis translate_on
port map( I0 => count_carry(2),
I1 => Tx_bit,
I2 => Tx_start,
I3 => Tx_run,
O => decode_Tx_run );
Tx_run_reg: FDE
port map ( D => decode_Tx_run,
Q => Tx_run,
CE => en_16_x_baud,
C => clk);
-- Bit rate enable
hot_state_lut: LUT3
--synthesis translate_off
generic map (INIT => X"94")
--synthesis translate_on
port map( I0 => Tx_stop,
I1 => ready_to_start,
I2 => Tx_bit,
O => decode_hot_state );
hot_state_reg: FDE
port map ( D => decode_hot_state,
Q => hot_state,
CE => en_16_x_baud,
C => clk);
delay14_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => hot_state,
CE => en_16_x_baud,
CLK => clk,
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '1',
Q => hot_delay );
Tx_bit_reg: FDE
port map ( D => hot_delay,
Q => Tx_bit,
CE => en_16_x_baud,
C => clk);
-- Stop bit enable
stop_lut: LUT4
--synthesis translate_off
generic map (INIT => X"0180")
--synthesis translate_on
port map( I0 => Tx_bit,
I1 => Tx_run,
I2 => count_carry(2),
I3 => Tx_stop,
O => decode_Tx_stop );
Tx_stop_reg: FDE
port map ( D => decode_Tx_stop,
Q => Tx_stop,
CE => en_16_x_baud,
C => clk);
-- Tx_complete strobe
complete_lut: LUT2
--synthesis translate_off
generic map (INIT => X"8")
--synthesis translate_on
port map( I0 => count_carry(2),
I1 => en_16_x_baud,
O => decode_Tx_complete );
Tx_complete_reg: FD
port map ( D => decode_Tx_complete,
Q => Tx_complete,
C => clk);
end low_level_definition;
------------------------------------------------------------------------------------
--
-- END OF FILE KCUART_TX.VHD
--
------------------------------------------------------------------------------------
| gpl-2.0 | 834afc54c72f3761da4bbd878a8f1e4e | 0.480735 | 3.870701 | false | false | false | false |
willprice/vhdl-computer | src/rtl/adder_full.vhd | 1 | 1,027 | ------------------------------------------------------------------------------
-- @file adder_full.vhd
-- @brief Implementes a simple 1 bit half adder that can be used to make full
-- adders and vector adders.
-- @see adder_full_tb
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--
-- Computes the sum and carry bit for two input bits and a carry in bit.
--
entity adder_full is
port(
in_0 : in std_logic;
in_1 : in std_logic;
carry_in : in std_logic;
sum : out std_logic;
carry_out : out std_logic
);
end entity adder_full;
architecture rtl of adder_full is
signal i0_xor_i1 : std_logic;
signal i0_and_i1 : std_logic;
signal ci_and_xor: std_logic;
begin
i0_xor_i1 <= in_0 xor in_1;
i0_and_i1 <= in_0 and in_1;
ci_and_xor <= i0_xor_i1 and carry_in;
sum <= i0_xor_i1 xor carry_in;
carry_out <= ci_and_xor or i0_and_i1;
end architecture rtl;
| gpl-3.0 | 53c459542a193e7bc9cbba6bc77b1ae5 | 0.515093 | 3.389439 | false | false | false | false |
nsauzede/cpu86 | papilio1/uart_rx.vhd | 1 | 5,120 | -- UART Receiver with integral 16 byte FIFO buffer
--
-- 8 bit, no parity, 1 stop bit
--
-- Version : 1.00
-- Version Date : 16th October 2002
--
-- Start of design entry : 16th October 2002
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- [email protected]
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
-- third parties. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
------------------------------------------------------------------------------------
--
-- Main Entity for UART_RX
--
entity uart_rx is
Port ( serial_in : in std_logic;
data_out : out std_logic_vector(7 downto 0);
read_buffer : in std_logic;
reset_buffer : in std_logic;
en_16_x_baud : in std_logic;
buffer_data_present : out std_logic;
buffer_full : out std_logic;
buffer_half_full : out std_logic;
clk : in std_logic);
end uart_rx;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for UART_RX
--
architecture macro_level_definition of uart_rx is
--
------------------------------------------------------------------------------------
--
-- Components used in UART_RX and defined in subsequent entities.
--
------------------------------------------------------------------------------------
--
-- Constant (K) Compact UART Receiver
--
component kcuart_rx
Port ( serial_in : in std_logic;
data_out : out std_logic_vector(7 downto 0);
data_strobe : out std_logic;
en_16_x_baud : in std_logic;
clk : in std_logic);
end component;
--
-- 'Bucket Brigade' FIFO
--
component bbfifo_16x8
Port ( data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
reset : in std_logic;
write : in std_logic;
read : in std_logic;
full : out std_logic;
half_full : out std_logic;
data_present : out std_logic;
clk : in std_logic);
end component;
--
------------------------------------------------------------------------------------
--
-- Signals used in UART_RX
--
------------------------------------------------------------------------------------
--
signal uart_data_out : std_logic_vector(7 downto 0);
signal fifo_write : std_logic;
--
------------------------------------------------------------------------------------
--
-- Start of UART_RX circuit description
--
------------------------------------------------------------------------------------
--
begin
-- 8 to 1 multiplexer to convert parallel data to serial
kcuart: kcuart_rx
port map ( serial_in => serial_in,
data_out => uart_data_out,
data_strobe => fifo_write,
en_16_x_baud => en_16_x_baud,
clk => clk );
buf: bbfifo_16x8
port map ( data_in => uart_data_out,
data_out => data_out,
reset => reset_buffer,
write => fifo_write,
read => read_buffer,
full => buffer_full,
half_full => buffer_half_full,
data_present => buffer_data_present,
clk => clk);
end macro_level_definition;
------------------------------------------------------------------------------------
--
-- END OF FILE UART_RX.VHD
--
------------------------------------------------------------------------------------
| gpl-2.0 | 3d18ab8f3542e21efc05ef4086d684e5 | 0.45 | 4.612613 | false | false | false | false |
VenturaSolutionsInc/VHDL | igmp/igmp_wrapper.vhd | 1 | 4,100 | -------------------------------------------------------------------------------
-- Title : IGMP Wrapper
-- Project :
-------------------------------------------------------------------------------
--! @file : igmp_wrapper.vhd
-- Author : Colin W. Shea
-- Company
-- Last update : 2010-03-15
-- Platform : Virtex 4/5/6
-------------------------------------------------------------------------------
--
--* @brief
--
--! @details:
--!
--!
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity igmp_wrapper is
generic (
gen_dataWidth : integer := 8;
simulation : boolean := false
);
port (
dataClk : in std_logic;
reset : in std_logic;
join : in std_logic;
leave : in std_logic;
--
srcMAC : in std_logic_vector(47 downto 0);
srcIP : in std_logic_vector(31 downto 0);
destMAC : in std_logic_vector(47 downto 0);
destIP : in std_logic_vector(31 downto 0);
vlanEn : in std_logic;
vlanId : in std_logic_vector(11 downto 0);
--
tx_ready_n : in std_logic;
tx_data : out std_logic_vector(7 downto 0);
tx_vld : out std_logic;
tx_sof : out std_logic;
tx_eof : out std_logic;
-- incoming igmp data
igmp_data : in std_logic_vector(7 downto 0);
igmp_vld : in std_logic;
igmp_sof : in std_logic;
igmp_eof : in std_logic;
-- enable processing of packets
out_enProc : out std_logic;
-- enable new commands to be accepted
out_enCommand : out std_logic
);
end igmp_wrapper;
architecture rtl of igmp_wrapper is
signal rspTime_i : std_logic_vector(7 downto 0) := (others => '0');
signal respond_i : std_logic := '0';
signal messageSent_i : std_logic := '0';
signal destMAC_i : std_logic_vector(47 downto 0) := (others => '0');
signal destIP_i : std_logic_vector(31 downto 0) := (others => '0');
signal join_i : std_logic := '0';
signal leave_i : std_logic := '0';
begin -- rtl
igmp_processor_module : entity work.igmp_processor
generic map (
gen_dataWidth => gen_dataWidth)
port map (
dataClk => dataClk,
reset => reset,
in_destIP => destIP,
igmp_data => igmp_data,
igmp_vld => igmp_vld,
igmp_sof => igmp_sof,
igmp_eof => igmp_eof,
respond => respond_i,
rsptime => rsptime_i
);
igmp_controller_module : entity work.igmp_controller
generic map (
gen_dataWidth => gen_dataWidth,
simulation => simulation)
port map (
dataClk => dataClk,
reset => reset,
join => join,
leave => leave,
respond => respond_i,
rspTime => rspTime_i,
destIP => destIP,
destMAC => destMAC,
messageSent => messageSent_i,
out_join => join_i,
out_leave => leave_i,
out_destMAC_o => destMAC_i,
out_destIP_o => destIP_i,
out_enProc => out_enProc,
out_enCommand => out_enCommand
);
igmp_assembler_module : entity work.igmp_assembler
generic map (
gen_dataWidth => gen_dataWidth)
port map (
dataClk => dataClk,
reset => reset,
srcMAC => srcMAC,
destMAC => destMAC_i,
vlanEn => vlanEn,
vlanId => vlanId,
srcIP => srcIP,
destIP => destIP_i,
join => join_i,
leave => leave_i,
tx_ready_n => tx_ready_n,
messageSent => messageSent_i,
tx_sof => tx_sof,
tx_eof => tx_eof,
tx_vld => tx_vld,
tx_data => tx_data
);
end rtl;
| gpl-2.0 | ea99091597aa0c0177e2d40649d42be7 | 0.453902 | 3.957529 | false | false | false | false |
nsauzede/cpu86 | papilio2_lcd/segregfile_rtl.vhd | 3 | 5,118 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
USE work.cpu86pack.ALL;
ENTITY segregfile IS
PORT(
selsreg : IN std_logic_vector (1 DOWNTO 0);
sibus : IN std_logic_vector (15 DOWNTO 0);
wrs : IN std_logic;
reset : IN std_logic;
clk : IN std_logic;
sdbus : OUT std_logic_vector (15 DOWNTO 0);
dimux : IN std_logic_vector (2 DOWNTO 0);
es_s : OUT std_logic_vector (15 DOWNTO 0);
cs_s : OUT std_logic_vector (15 DOWNTO 0);
ss_s : OUT std_logic_vector (15 DOWNTO 0);
ds_s : OUT std_logic_vector (15 DOWNTO 0)
);
END segregfile ;
architecture rtl of segregfile is
signal esreg_s : std_logic_vector(15 downto 0);
signal csreg_s : std_logic_vector(15 downto 0);
signal ssreg_s : std_logic_vector(15 downto 0);
signal dsreg_s : std_logic_vector(15 downto 0);
signal sdbus_s : std_logic_vector (15 downto 0); -- internal sdbus
signal dimux_s : std_logic_vector (2 downto 0); -- replaced dimux
begin
----------------------------------------------------------------------------
-- 4 registers of 16 bits each
----------------------------------------------------------------------------
process (clk,reset)
begin
if reset='1' then
esreg_s <= RESET_ES_C;
csreg_s <= RESET_CS_C; -- Only CS set after reset
ssreg_s <= RESET_SS_C;
dsreg_s <= RESET_DS_C;
elsif rising_edge(clk) then
if (wrs='1') then
case selsreg is
when "00" => esreg_s <= sibus;
when "01" => csreg_s <= sibus;
when "10" => ssreg_s <= sibus;
when others => dsreg_s <= sibus;
end case;
end if;
end if;
end process;
dimux_s <= dimux;
process (dimux_s,esreg_s,csreg_s,ssreg_s,dsreg_s)
begin
case dimux_s is -- Only 2 bits required
when "100" => sdbus_s <= esreg_s;
when "101" => sdbus_s <= csreg_s;
when "110" => sdbus_s <= ssreg_s;
when others => sdbus_s <= dsreg_s;
end case;
end process;
sdbus <= sdbus_s; -- Connect to entity
es_s <= esreg_s;
cs_s <= csreg_s;
ss_s <= ssreg_s;
ds_s <= dsreg_s;
end rtl;
| gpl-2.0 | 61dea0eb0d5317d9e3b98fccb907b0a1 | 0.415397 | 4.485539 | false | false | false | false |
willprice/vhdl-computer | src/test/ff_jk_tb.vhd | 1 | 954 | --------------------------------------------------------------------------------
-- @file ff_jk_tb.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;
entity ff_jk_tb is
end;
architecture testbench of ff_jk_tb is
component ff_jk is
port(
clk : in std_logic;
j : in std_logic;
k : in std_logic;
q : buffer std_logic;
not_q : out std_logic
);
end component ff_jk;
signal clk : std_logic;
signal j : std_logic;
signal k : std_logic;
signal q : std_logic;
signal not_q : std_logic;
begin
DUT : ff_jk port map(
clk => clk,
j => j,
k => k,
q => q,
not_q => not_q
);
test_hold_state_does_not_invoke_a_change: process(clk)
begin
j <= '0';
k <= '0';
end process;
end; | gpl-3.0 | a901cd8e0548a5a8a7ae11d10e7162b2 | 0.417191 | 3.613636 | false | false | false | false |
CamelClarkson/MIPS | MIPS_Design/Src/LE.vhd | 2 | 1,716 | ----------------------------------------------------------------------------------
-- Clarkson University
-- EE466/566 Computer Architecture Fall 2016
-- Project Name: Project1, 4-Bit ALU Design
--
-- Student Name : Zhiliu Yang
-- Student ID : 0754659
-- Major : Electrical and Computer Engineering
-- Email : [email protected]
-- Instructor Name: Dr. Chen Liu
-- Date : 09-25-2016
--
-- Create Date: 09/25/2016 04:10:39 PM
-- Design Name:
-- Module Name: LE - LE_Func
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity LE is
Port (
P3 : in STD_LOGIC;
P2 : in STD_LOGIC;
P1 : in STD_LOGIC;
P0 : in STD_LOGIC;
A : in STD_LOGIC;
B : in STD_LOGIC;
X : out STD_LOGIC);
end LE;
architecture LE_Func of LE is
signal Temp1 : STD_LOGIC;
signal Temp2 : STD_LOGIC;
signal Temp3 : STD_LOGIC;
signal Temp4 : STD_LOGIC;
signal Temp5 : STD_LOGIC;
begin
Temp1 <= P3 and (not A) and (not B);
Temp2 <= P0 and A;
Temp3 <= P1 and A;
Temp4 <= (not P3) and A and B;
Temp5 <= (not P1) and P0 and B;
X <= (((Temp1 or Temp2) or Temp3) or Temp4) or Temp5;
end LE_Func;
| mit | 6ddf2a63380031834d4a420c25226307 | 0.570513 | 3.459677 | false | false | false | false |
AUT-CEIT/Arch101 | memory/memory.vhd | 1 | 1,521 | --------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 16-03-2017
-- Module Name: memory.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity memory is
generic (blocksize : integer := 1024);
port (clk, readmem, writemem : in std_logic;
addressbus: in std_logic_vector (15 downto 0);
databus : inout std_logic_vector (15 downto 0);
memdataready : out std_logic);
end entity memory;
architecture behavioral of memory is
type mem is array (0 to blocksize - 1) of std_logic_vector (15 downto 0);
begin
process (clk)
variable buffermem : mem := (others => (others => '0'));
variable ad : integer;
variable init : boolean := true;
begin
if init = true then
-- some initiation
buffermem(0) := "0000000000000000";
init := false;
end if;
memdataready <= '0';
if clk'event and clk = '1' then
ad := to_integer(unsigned(addressbus));
if readmem = '1' then -- Readiing :)
memdataready <= '1';
if ad >= blocksize then
databus <= (others => 'Z');
else
databus <= buffermem(ad);
end if;
elsif writemem = '1' then -- Writing :)
memdataready <= '1';
if ad < blocksize then
buffermem(ad) := databus;
end if;
elsif readmem = '0' then
databus <= (others => 'Z');
end if;
end if;
end process;
end architecture behavioral;
| gpl-3.0 | 41db535213b4ceb1b375eafddbd7f186 | 0.568047 | 3.529002 | false | false | false | false |
nsauzede/cpu86 | papilio2_lcd/d_table.vhd | 3 | 37,240 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity d_table is
port ( addr : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(3 downto 0));
end d_table;
architecture rtl of d_table is
begin
process(addr)
begin
case addr is
when "1110101100000000" => dout <= "0000";
when "1110100100000000" => dout <= "0000";
when "1111111111100000" => dout <= "0000";
when "1111111100100110" => dout <= "0000";
when "1111111100100000" => dout <= "0000";
when "1111111101100000" => dout <= "0000";
when "1111111110100000" => dout <= "0000";
when "1110101000000000" => dout <= "0110";
when "1111111100101110" => dout <= "0000";
when "1111111100101000" => dout <= "0000";
when "1111111101101000" => dout <= "0000";
when "1111111110101000" => dout <= "0000";
when "1110100000000000" => dout <= "0000";
when "1111111111010000" => dout <= "0000";
when "1111111100010110" => dout <= "0000";
when "1111111100010000" => dout <= "0000";
when "1111111101010000" => dout <= "0000";
when "1111111110010000" => dout <= "0000";
when "1001101000000000" => dout <= "0110";
when "1111111100011110" => dout <= "0000";
when "1111111100011000" => dout <= "0000";
when "1111111101011000" => dout <= "0000";
when "1111111110011000" => dout <= "0000";
when "1100001100000000" => dout <= "0000";
when "1100001000000000" => dout <= "0010";
when "1100101100000000" => dout <= "0000";
when "1100101000000000" => dout <= "0010";
when "0111010000000000" => dout <= "0000";
when "0111110000000000" => dout <= "0000";
when "0111111000000000" => dout <= "0000";
when "0111001000000000" => dout <= "0000";
when "0111011000000000" => dout <= "0000";
when "0111101000000000" => dout <= "0000";
when "0111000000000000" => dout <= "0000";
when "0111100000000000" => dout <= "0000";
when "0111010100000000" => dout <= "0000";
when "0111110100000000" => dout <= "0000";
when "0111111100000000" => dout <= "0000";
when "0111001100000000" => dout <= "0000";
when "0111011100000000" => dout <= "0000";
when "0111101100000000" => dout <= "0000";
when "0111000100000000" => dout <= "0000";
when "0111100100000000" => dout <= "0000";
when "1110001100000000" => dout <= "0000";
when "1110001000000000" => dout <= "0000";
when "1110000100000000" => dout <= "0000";
when "1110000000000000" => dout <= "0000";
when "1100110100000000" => dout <= "0000";
when "1100110000000000" => dout <= "0000";
when "1100111000000000" => dout <= "0000";
when "1100111100000000" => dout <= "0000";
when "1111100000000000" => dout <= "0000";
when "1111010100000000" => dout <= "0000";
when "1111100100000000" => dout <= "0000";
when "1111110000000000" => dout <= "0000";
when "1111110100000000" => dout <= "0000";
when "1111101000000000" => dout <= "0000";
when "1111101100000000" => dout <= "0000";
when "1111010000000000" => dout <= "0000";
when "1001101100000000" => dout <= "0000";
when "1111000000000000" => dout <= "0000";
when "1001000000000000" => dout <= "0000";
when "0010011000000000" => dout <= "0000";
when "0010111000000000" => dout <= "0000";
when "0011011000000000" => dout <= "0000";
when "0011111000000000" => dout <= "0000";
when "1000100011000000" => dout <= "0000";
when "1000100000000000" => dout <= "0000";
when "1000100001000000" => dout <= "0000";
when "1000100010000000" => dout <= "0000";
when "1000100000000110" => dout <= "0000";
when "1000100111000000" => dout <= "0000";
when "1000100100000000" => dout <= "0000";
when "1000100101000000" => dout <= "0000";
when "1000100110000000" => dout <= "0000";
when "1000100100000110" => dout <= "0000";
when "1000101011000000" => dout <= "0000";
when "1000101000000000" => dout <= "0000";
when "1000101001000000" => dout <= "0000";
when "1000101010000000" => dout <= "0000";
when "1000101000000110" => dout <= "0000";
when "1000101111000000" => dout <= "0000";
when "1000101100000000" => dout <= "0000";
when "1000101101000000" => dout <= "0000";
when "1000101110000000" => dout <= "0000";
when "1000101100000110" => dout <= "0000";
when "1100011000000000" => dout <= "0011";
when "1100011001000000" => dout <= "0101";
when "1100011010000000" => dout <= "0111";
when "1100011000000110" => dout <= "0111";
when "1100011100000000" => dout <= "0100";
when "1100011101000000" => dout <= "0110";
when "1100011110000000" => dout <= "1000";
when "1100011100000110" => dout <= "1000";
when "1011000000000000" => dout <= "0001";
when "1011000100000000" => dout <= "0001";
when "1011001000000000" => dout <= "0001";
when "1011001100000000" => dout <= "0001";
when "1011010000000000" => dout <= "0001";
when "1011010100000000" => dout <= "0001";
when "1011011000000000" => dout <= "0001";
when "1011011100000000" => dout <= "0001";
when "1011100000000000" => dout <= "0010";
when "1011100100000000" => dout <= "0010";
when "1011101000000000" => dout <= "0010";
when "1011101100000000" => dout <= "0010";
when "1011110000000000" => dout <= "0010";
when "1011110100000000" => dout <= "0010";
when "1011111000000000" => dout <= "0010";
when "1011111100000000" => dout <= "0010";
when "1010000000000000" => dout <= "0000";
when "1010000100000000" => dout <= "0000";
when "1010001000000000" => dout <= "0000";
when "1010001100000000" => dout <= "0000";
when "1000111011000000" => dout <= "0000";
when "1000111000000000" => dout <= "0000";
when "1000111001000000" => dout <= "0000";
when "1000111010000000" => dout <= "0000";
when "1000111000000110" => dout <= "0000";
when "1000110011000000" => dout <= "0000";
when "1000110000000000" => dout <= "0000";
when "1000110001000000" => dout <= "0000";
when "1000110010000000" => dout <= "0000";
when "1000110000000110" => dout <= "0000";
when "1111111100110000" => dout <= "0000";
when "1111111101110000" => dout <= "0000";
when "1111111110110000" => dout <= "0000";
when "1111111100110110" => dout <= "0000";
when "0101000000000000" => dout <= "0000";
when "0101000100000000" => dout <= "0000";
when "0101001000000000" => dout <= "0000";
when "0101001100000000" => dout <= "0000";
when "0101010000000000" => dout <= "0000";
when "0101010100000000" => dout <= "0000";
when "0101011000000000" => dout <= "0000";
when "0101011100000000" => dout <= "0000";
when "0000011000000000" => dout <= "0000";
when "0000111000000000" => dout <= "0000";
when "0001011000000000" => dout <= "0000";
when "0001111000000000" => dout <= "0000";
when "1000111100000000" => dout <= "0000";
when "1000111101000000" => dout <= "0000";
when "1000111110000000" => dout <= "0000";
when "1000111100000110" => dout <= "0000";
when "1000111111000000" => dout <= "0000";
when "0101100000000000" => dout <= "0000";
when "0101100100000000" => dout <= "0000";
when "0101101000000000" => dout <= "0000";
when "0101101100000000" => dout <= "0000";
when "0101110000000000" => dout <= "0000";
when "0101110100000000" => dout <= "0000";
when "0101111000000000" => dout <= "0000";
when "0101111100000000" => dout <= "0000";
when "0000011100000000" => dout <= "0000";
when "0001011100000000" => dout <= "0000";
when "0001111100000000" => dout <= "0000";
when "1000011011000000" => dout <= "0000";
when "1000011000000000" => dout <= "0000";
when "1000011001000000" => dout <= "0000";
when "1000011010000000" => dout <= "0000";
when "1000011000000110" => dout <= "0000";
when "1000011111000000" => dout <= "0000";
when "1000011100000000" => dout <= "0000";
when "1000011101000000" => dout <= "0000";
when "1000011110000000" => dout <= "0000";
when "1000011100000110" => dout <= "0000";
when "1001000100000000" => dout <= "0000";
when "1001001000000000" => dout <= "0000";
when "1001001100000000" => dout <= "0000";
when "1001010000000000" => dout <= "0000";
when "1001010100000000" => dout <= "0000";
when "1001011000000000" => dout <= "0000";
when "1001011100000000" => dout <= "0000";
when "1110010000000000" => dout <= "0000";
when "1110010100000000" => dout <= "0000";
when "1110110000000000" => dout <= "0000";
when "1110110100000000" => dout <= "0000";
when "1110011000000000" => dout <= "0000";
when "1110011100000000" => dout <= "0000";
when "1110111100000000" => dout <= "0000";
when "1110111000000000" => dout <= "0000";
when "1101011100000000" => dout <= "0000";
when "1001111100000000" => dout <= "0000";
when "1001111000000000" => dout <= "0000";
when "1001110000000000" => dout <= "0000";
when "1001110100000000" => dout <= "0000";
when "1000110100000110" => dout <= "0000";
when "1000110111000000" => dout <= "0000";
when "1000110100000000" => dout <= "0000";
when "1000110101000000" => dout <= "0000";
when "1000110110000000" => dout <= "0000";
when "1100010100000110" => dout <= "0000";
when "1100010100000000" => dout <= "0000";
when "1100010101000000" => dout <= "0000";
when "1100010110000000" => dout <= "0000";
when "1100010000000110" => dout <= "0000";
when "1100010000000000" => dout <= "0000";
when "1100010001000000" => dout <= "0000";
when "1100010010000000" => dout <= "0000";
when "0000000011000000" => dout <= "0000";
when "0000000000000110" => dout <= "0000";
when "0000000000000000" => dout <= "0000";
when "0000000001000000" => dout <= "0000";
when "0000000010000000" => dout <= "0000";
when "0000000111000000" => dout <= "0000";
when "0000000100000110" => dout <= "0000";
when "0000000100000000" => dout <= "0000";
when "0000000101000000" => dout <= "0000";
when "0000000110000000" => dout <= "0000";
when "0000001011000000" => dout <= "0000";
when "0000001000000110" => dout <= "0000";
when "0000001000000000" => dout <= "0000";
when "0000001001000000" => dout <= "0000";
when "0000001010000000" => dout <= "0000";
when "0000001111000000" => dout <= "0000";
when "0000001100000110" => dout <= "0000";
when "0000001100000000" => dout <= "0000";
when "0000001101000000" => dout <= "0000";
when "0000001110000000" => dout <= "0000";
when "1000000011000000" => dout <= "0011";
when "1000000000000110" => dout <= "0111";
when "1000000000000000" => dout <= "0011";
when "1000000001000000" => dout <= "0101";
when "1000000010000000" => dout <= "0111";
when "1000000111000000" => dout <= "0100";
when "1000000100000110" => dout <= "1000";
when "1000000100000000" => dout <= "0100";
when "1000000101000000" => dout <= "0110";
when "1000000110000000" => dout <= "1000";
when "1000001111000000" => dout <= "0011";
when "1000001100000110" => dout <= "0111";
when "1000001100000000" => dout <= "0011";
when "1000001101000000" => dout <= "0101";
when "1000001110000000" => dout <= "0111";
when "0000010000000000" => dout <= "0001";
when "0000010100000000" => dout <= "0010";
when "0001000011000000" => dout <= "0000";
when "0001000000000110" => dout <= "0000";
when "0001000000000000" => dout <= "0000";
when "0001000001000000" => dout <= "0000";
when "0001000010000000" => dout <= "0000";
when "0001000111000000" => dout <= "0000";
when "0001000100000110" => dout <= "0000";
when "0001000100000000" => dout <= "0000";
when "0001000101000000" => dout <= "0000";
when "0001000110000000" => dout <= "0000";
when "0001001011000000" => dout <= "0000";
when "0001001000000110" => dout <= "0000";
when "0001001000000000" => dout <= "0000";
when "0001001001000000" => dout <= "0000";
when "0001001010000000" => dout <= "0000";
when "0001001111000000" => dout <= "0000";
when "0001001100000110" => dout <= "0000";
when "0001001100000000" => dout <= "0000";
when "0001001101000000" => dout <= "0000";
when "0001001110000000" => dout <= "0000";
when "1000000011010000" => dout <= "0011";
when "1000000000010110" => dout <= "0111";
when "1000000000010000" => dout <= "0011";
when "1000000001010000" => dout <= "0101";
when "1000000010010000" => dout <= "0111";
when "1000000111010000" => dout <= "0100";
when "1000000100010110" => dout <= "1000";
when "1000000100010000" => dout <= "0100";
when "1000000101010000" => dout <= "0110";
when "1000000110010000" => dout <= "1000";
when "1000001111010000" => dout <= "0011";
when "1000001100010110" => dout <= "0111";
when "1000001100010000" => dout <= "0011";
when "1000001101010000" => dout <= "0101";
when "1000001110010000" => dout <= "0111";
when "0001010000000000" => dout <= "0001";
when "0001010100000000" => dout <= "0010";
when "0010100011000000" => dout <= "0000";
when "0010100000000110" => dout <= "0000";
when "0010100000000000" => dout <= "0000";
when "0010100001000000" => dout <= "0000";
when "0010100010000000" => dout <= "0000";
when "0010100111000000" => dout <= "0000";
when "0010100100000110" => dout <= "0000";
when "0010100100000000" => dout <= "0000";
when "0010100101000000" => dout <= "0000";
when "0010100110000000" => dout <= "0000";
when "0010101011000000" => dout <= "0000";
when "0010101000000110" => dout <= "0000";
when "0010101000000000" => dout <= "0000";
when "0010101001000000" => dout <= "0000";
when "0010101010000000" => dout <= "0000";
when "0010101111000000" => dout <= "0000";
when "0010101100000110" => dout <= "0000";
when "0010101100000000" => dout <= "0000";
when "0010101101000000" => dout <= "0000";
when "0010101110000000" => dout <= "0000";
when "1000000011101000" => dout <= "0011";
when "1000000000101110" => dout <= "0111";
when "1000000000101000" => dout <= "0011";
when "1000000001101000" => dout <= "0101";
when "1000000010101000" => dout <= "0111";
when "1000000111101000" => dout <= "0100";
when "1000000100101110" => dout <= "1000";
when "1000000100101000" => dout <= "0100";
when "1000000101101000" => dout <= "0110";
when "1000000110101000" => dout <= "1000";
when "1000001111101000" => dout <= "0011";
when "1000001100101110" => dout <= "0111";
when "1000001100101000" => dout <= "0011";
when "1000001101101000" => dout <= "0101";
when "1000001110101000" => dout <= "0111";
when "0010110000000000" => dout <= "0001";
when "0010110100000000" => dout <= "0010";
when "0001100011000000" => dout <= "0000";
when "0001100000000110" => dout <= "0000";
when "0001100000000000" => dout <= "0000";
when "0001100001000000" => dout <= "0000";
when "0001100010000000" => dout <= "0000";
when "0001100111000000" => dout <= "0000";
when "0001100100000110" => dout <= "0000";
when "0001100100000000" => dout <= "0000";
when "0001100101000000" => dout <= "0000";
when "0001100110000000" => dout <= "0000";
when "0001101011000000" => dout <= "0000";
when "0001101000000110" => dout <= "0000";
when "0001101000000000" => dout <= "0000";
when "0001101001000000" => dout <= "0000";
when "0001101010000000" => dout <= "0000";
when "0001101111000000" => dout <= "0000";
when "0001101100000110" => dout <= "0000";
when "0001101100000000" => dout <= "0000";
when "0001101101000000" => dout <= "0000";
when "0001101110000000" => dout <= "0000";
when "1000000011011000" => dout <= "0011";
when "1000000000011110" => dout <= "0111";
when "1000000000011000" => dout <= "0011";
when "1000000001011000" => dout <= "0101";
when "1000000010011000" => dout <= "0111";
when "1000000111011000" => dout <= "0100";
when "1000000100011110" => dout <= "1000";
when "1000000100011000" => dout <= "0100";
when "1000000101011000" => dout <= "0110";
when "1000000110011000" => dout <= "1000";
when "1000001111011000" => dout <= "0011";
when "1000001100011110" => dout <= "0111";
when "1000001100011000" => dout <= "0011";
when "1000001101011000" => dout <= "0101";
when "1000001110011000" => dout <= "0111";
when "0001110000000000" => dout <= "0001";
when "0001110100000000" => dout <= "0010";
when "1111111011000000" => dout <= "0000";
when "1111111000000110" => dout <= "0000";
when "1111111000000000" => dout <= "0000";
when "1111111001000000" => dout <= "0000";
when "1111111010000000" => dout <= "0000";
when "1111111100000110" => dout <= "0000";
when "1111111100000000" => dout <= "0000";
when "1111111101000000" => dout <= "0000";
when "1111111110000000" => dout <= "0000";
when "0100000000000000" => dout <= "0000";
when "0100000100000000" => dout <= "0000";
when "0100001000000000" => dout <= "0000";
when "0100001100000000" => dout <= "0000";
when "0100010000000000" => dout <= "0000";
when "0100010100000000" => dout <= "0000";
when "0100011000000000" => dout <= "0000";
when "0100011100000000" => dout <= "0000";
when "1111111011001000" => dout <= "0000";
when "1111111000001110" => dout <= "0000";
when "1111111000001000" => dout <= "0000";
when "1111111001001000" => dout <= "0000";
when "1111111010001000" => dout <= "0000";
when "1111111100001110" => dout <= "0000";
when "1111111100001000" => dout <= "0000";
when "1111111101001000" => dout <= "0000";
when "1111111110001000" => dout <= "0000";
when "0100100000000000" => dout <= "0000";
when "0100100100000000" => dout <= "0000";
when "0100101000000000" => dout <= "0000";
when "0100101100000000" => dout <= "0000";
when "0100110000000000" => dout <= "0000";
when "0100110100000000" => dout <= "0000";
when "0100111000000000" => dout <= "0000";
when "0100111100000000" => dout <= "0000";
when "0011101011000000" => dout <= "0000";
when "0011101000000110" => dout <= "0000";
when "0011101000000000" => dout <= "0000";
when "0011101001000000" => dout <= "0000";
when "0011101010000000" => dout <= "0000";
when "0011101111000000" => dout <= "0000";
when "0011101100000110" => dout <= "0000";
when "0011101100000000" => dout <= "0000";
when "0011101101000000" => dout <= "0000";
when "0011101110000000" => dout <= "0000";
when "0011100000000110" => dout <= "0000";
when "0011100000000000" => dout <= "0000";
when "0011100001000000" => dout <= "0000";
when "0011100010000000" => dout <= "0000";
when "0011100011000000" => dout <= "0000";
when "0011100100000110" => dout <= "0000";
when "0011100100000000" => dout <= "0000";
when "0011100101000000" => dout <= "0000";
when "0011100110000000" => dout <= "0000";
when "0011100111000000" => dout <= "0000";
when "1000000011111000" => dout <= "0011";
when "1000000000111110" => dout <= "0111";
when "1000000000111000" => dout <= "0011";
when "1000000001111000" => dout <= "0101";
when "1000000010111000" => dout <= "0111";
when "1000000111111000" => dout <= "0100";
when "1000000100111110" => dout <= "1000";
when "1000000100111000" => dout <= "0100";
when "1000000101111000" => dout <= "0110";
when "1000000110111000" => dout <= "1000";
when "1000001111111000" => dout <= "0011";
when "1000001100111110" => dout <= "0111";
when "1000001100111000" => dout <= "0011";
when "1000001101111000" => dout <= "0101";
when "1000001110111000" => dout <= "0111";
when "0011110000000000" => dout <= "0001";
when "0011110100000000" => dout <= "0010";
when "1111011011011000" => dout <= "0000";
when "1111011000011110" => dout <= "0000";
when "1111011000011000" => dout <= "0000";
when "1111011001011000" => dout <= "0000";
when "1111011010011000" => dout <= "0000";
when "1111011111011000" => dout <= "0000";
when "1111011100011110" => dout <= "0000";
when "1111011100011000" => dout <= "0000";
when "1111011101011000" => dout <= "0000";
when "1111011110011000" => dout <= "0000";
when "0011011100000000" => dout <= "0000";
when "0010011100000000" => dout <= "0000";
when "0011111100000000" => dout <= "0000";
when "0010111100000000" => dout <= "0000";
when "1111011011100000" => dout <= "0000";
when "1111011000100110" => dout <= "0000";
when "1111011000100000" => dout <= "0000";
when "1111011001100000" => dout <= "0000";
when "1111011010100000" => dout <= "0000";
when "1111011111100000" => dout <= "0000";
when "1111011100100110" => dout <= "0000";
when "1111011100100000" => dout <= "0000";
when "1111011101100000" => dout <= "0000";
when "1111011110100000" => dout <= "0000";
when "1111011011101000" => dout <= "0000";
when "1111011000101110" => dout <= "0000";
when "1111011000101000" => dout <= "0000";
when "1111011001101000" => dout <= "0000";
when "1111011010101000" => dout <= "0000";
when "1111011111101000" => dout <= "0000";
when "1111011100101110" => dout <= "0000";
when "1111011100101000" => dout <= "0000";
when "1111011101101000" => dout <= "0000";
when "1111011110101000" => dout <= "0000";
when "1111011011110000" => dout <= "0000";
when "1111011000110110" => dout <= "0000";
when "1111011000110000" => dout <= "0000";
when "1111011001110000" => dout <= "0000";
when "1111011010110000" => dout <= "0000";
when "1111011111110000" => dout <= "0000";
when "1111011100110110" => dout <= "0000";
when "1111011100110000" => dout <= "0000";
when "1111011101110000" => dout <= "0000";
when "1111011110110000" => dout <= "0000";
when "1111011011111000" => dout <= "0000";
when "1111011000111110" => dout <= "0000";
when "1111011000111000" => dout <= "0000";
when "1111011001111000" => dout <= "0000";
when "1111011010111000" => dout <= "0000";
when "1111011111111000" => dout <= "0000";
when "1111011100111110" => dout <= "0000";
when "1111011100111000" => dout <= "0000";
when "1111011101111000" => dout <= "0000";
when "1111011110111000" => dout <= "0000";
when "1101010000000000" => dout <= "0000";
when "1101010100000000" => dout <= "0000";
when "1001100000000000" => dout <= "0000";
when "1001100100000000" => dout <= "0000";
when "1101000011000000" => dout <= "0000";
when "1101000000000110" => dout <= "0000";
when "1101000000000000" => dout <= "0000";
when "1101000001000000" => dout <= "0000";
when "1101000010000000" => dout <= "0000";
when "1101000111000000" => dout <= "0000";
when "1101000100000110" => dout <= "0000";
when "1101000100000000" => dout <= "0000";
when "1101000101000000" => dout <= "0000";
when "1101000110000000" => dout <= "0000";
when "1101001011000000" => dout <= "0000";
when "1101001000000110" => dout <= "0000";
when "1101001000000000" => dout <= "0000";
when "1101001001000000" => dout <= "0000";
when "1101001010000000" => dout <= "0000";
when "1101001111000000" => dout <= "0000";
when "1101001100000110" => dout <= "0000";
when "1101001100000000" => dout <= "0000";
when "1101001101000000" => dout <= "0000";
when "1101001110000000" => dout <= "0000";
when "0010000011000000" => dout <= "0000";
when "0010000000000110" => dout <= "0000";
when "0010000000000000" => dout <= "0000";
when "0010000001000000" => dout <= "0000";
when "0010000010000000" => dout <= "0000";
when "0010000111000000" => dout <= "0000";
when "0010000100000110" => dout <= "0000";
when "0010000100000000" => dout <= "0000";
when "0010000101000000" => dout <= "0000";
when "0010000110000000" => dout <= "0000";
when "0010001011000000" => dout <= "0000";
when "0010001000000110" => dout <= "0000";
when "0010001000000000" => dout <= "0000";
when "0010001001000000" => dout <= "0000";
when "0010001010000000" => dout <= "0000";
when "0010001111000000" => dout <= "0000";
when "0010001100000110" => dout <= "0000";
when "0010001100000000" => dout <= "0000";
when "0010001101000000" => dout <= "0000";
when "0010001110000000" => dout <= "0000";
when "1000000011100000" => dout <= "0011";
when "1000000000100110" => dout <= "0111";
when "1000000000100000" => dout <= "0011";
when "1000000001100000" => dout <= "0101";
when "1000000010100000" => dout <= "0111";
when "1000000111100000" => dout <= "0100";
when "1000000100100110" => dout <= "1000";
when "1000000100100000" => dout <= "0100";
when "1000000101100000" => dout <= "0110";
when "1000000110100000" => dout <= "1000";
when "1000001111100000" => dout <= "0011";
when "1000001100100110" => dout <= "0111";
when "1000001100100000" => dout <= "0011";
when "1000001101100000" => dout <= "0101";
when "1000001110100000" => dout <= "0111";
when "0010010000000000" => dout <= "0001";
when "0010010100000000" => dout <= "0010";
when "0000100000000110" => dout <= "0000";
when "0000100000000000" => dout <= "0000";
when "0000100001000000" => dout <= "0000";
when "0000100010000000" => dout <= "0000";
when "0000100011000000" => dout <= "0000";
when "0000100100000110" => dout <= "0000";
when "0000100100000000" => dout <= "0000";
when "0000100101000000" => dout <= "0000";
when "0000100110000000" => dout <= "0000";
when "0000100111000000" => dout <= "0000";
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when "0000101000000110" => dout <= "0000";
when "0000101000000000" => dout <= "0000";
when "0000101001000000" => dout <= "0000";
when "0000101010000000" => dout <= "0000";
when "0000101111000000" => dout <= "0000";
when "0000101100000110" => dout <= "0000";
when "0000101100000000" => dout <= "0000";
when "0000101101000000" => dout <= "0000";
when "0000101110000000" => dout <= "0000";
when "1000000011001000" => dout <= "0011";
when "1000000000001110" => dout <= "0111";
when "1000000000001000" => dout <= "0011";
when "1000000001001000" => dout <= "0101";
when "1000000010001000" => dout <= "0111";
when "1000000111001000" => dout <= "0100";
when "1000000100001110" => dout <= "1000";
when "1000000100001000" => dout <= "0100";
when "1000000101001000" => dout <= "0110";
when "1000000110001000" => dout <= "1000";
when "1000001111001000" => dout <= "0011";
when "1000001100001110" => dout <= "0111";
when "1000001100001000" => dout <= "0011";
when "1000001101001000" => dout <= "0101";
when "1000001110001000" => dout <= "0111";
when "0000110000000000" => dout <= "0001";
when "0000110100000000" => dout <= "0010";
when "1000010000000110" => dout <= "0000";
when "1000010000000000" => dout <= "0000";
when "1000010001000000" => dout <= "0000";
when "1000010010000000" => dout <= "0000";
when "1000010100000110" => dout <= "0000";
when "1000010100000000" => dout <= "0000";
when "1000010101000000" => dout <= "0000";
when "1000010110000000" => dout <= "0000";
when "1000010011000000" => dout <= "0000";
when "1000010111000000" => dout <= "0000";
when "1111011011000000" => dout <= "0011";
when "1111011000000110" => dout <= "0111";
when "1111011000000000" => dout <= "0011";
when "1111011001000000" => dout <= "0101";
when "1111011010000000" => dout <= "0111";
when "1111011111000000" => dout <= "0100";
when "1111011100000110" => dout <= "1000";
when "1111011100000000" => dout <= "0100";
when "1111011101000000" => dout <= "0110";
when "1111011110000000" => dout <= "1000";
when "1010100000000000" => dout <= "0001";
when "1010100100000000" => dout <= "0010";
when "0011000000000110" => dout <= "0000";
when "0011000000000000" => dout <= "0000";
when "0011000001000000" => dout <= "0000";
when "0011000010000000" => dout <= "0000";
when "0011000011000000" => dout <= "0000";
when "0011000100000110" => dout <= "0000";
when "0011000100000000" => dout <= "0000";
when "0011000101000000" => dout <= "0000";
when "0011000110000000" => dout <= "0000";
when "0011000111000000" => dout <= "0000";
when "0011001011000000" => dout <= "0000";
when "0011001000000110" => dout <= "0000";
when "0011001000000000" => dout <= "0000";
when "0011001001000000" => dout <= "0000";
when "0011001010000000" => dout <= "0000";
when "0011001111000000" => dout <= "0000";
when "0011001100000110" => dout <= "0000";
when "0011001100000000" => dout <= "0000";
when "0011001101000000" => dout <= "0000";
when "0011001110000000" => dout <= "0000";
when "1000000011110000" => dout <= "0011";
when "1000000000110110" => dout <= "0111";
when "1000000000110000" => dout <= "0011";
when "1000000001110000" => dout <= "0101";
when "1000000010110000" => dout <= "0111";
when "1000000111110000" => dout <= "0100";
when "1000000100110110" => dout <= "1000";
when "1000000100110000" => dout <= "0100";
when "1000000101110000" => dout <= "0110";
when "1000000110110000" => dout <= "1000";
when "1000001111110000" => dout <= "0011";
when "1000001100110110" => dout <= "0111";
when "1000001100110000" => dout <= "0011";
when "1000001101110000" => dout <= "0101";
when "1000001110110000" => dout <= "0111";
when "0011010000000000" => dout <= "0001";
when "0011010100000000" => dout <= "0010";
when "1111011011010000" => dout <= "0000";
when "1111011000010110" => dout <= "0000";
when "1111011000010000" => dout <= "0000";
when "1111011001010000" => dout <= "0000";
when "1111011010010000" => dout <= "0000";
when "1111011111010000" => dout <= "0000";
when "1111011100010110" => dout <= "0000";
when "1111011100010000" => dout <= "0000";
when "1111011101010000" => dout <= "0000";
when "1111011110010000" => dout <= "0000";
when "1010010000000000" => dout <= "0000";
when "1010010100000000" => dout <= "0000";
when "1010011000000000" => dout <= "0000";
when "1010011100000000" => dout <= "0000";
when "1010111000000000" => dout <= "0000";
when "1010111100000000" => dout <= "0000";
when "1010110000000000" => dout <= "0000";
when "1010110100000000" => dout <= "0000";
when "1010101000000000" => dout <= "0000";
when "1010101100000000" => dout <= "0000";
when "1111001000000000" => dout <= "0000";
when "1111001100000000" => dout <= "0000";
when "0110000000000000" => dout <= "0000";
when "0110000100000000" => dout <= "0000";
when "1100100000000000" => dout <= "0000";
when "1100100100000000" => dout <= "0000";
when "0110001000000000" => dout <= "0000";
when "0110110000000000" => dout <= "0000";
when "0110110100000000" => dout <= "0000";
when "0110111000000000" => dout <= "0000";
when "0110111100000000" => dout <= "0000";
when "0000111100000000" => dout <= "0000";
when "0110001100000000" => dout <= "0000";
when "0110010000000000" => dout <= "0000";
when "0110010100000000" => dout <= "0000";
when "0110011000000000" => dout <= "0000";
when "0110011100000000" => dout <= "0000";
when "1000001000000000" => dout <= "0000";
when "1101011000000000" => dout <= "0000";
when "1111000100000000" => dout <= "0000";
when "1100000000000000" => dout <= "0000";
when "1100000100000000" => dout <= "0000";
when others => dout <= "----";
end case;
end process;
end rtl; | gpl-2.0 | 22034d64efe92134eac68b6c16317798 | 0.534989 | 4.381176 | false | false | false | false |
nsauzede/cpu86 | papilio2_drigmorn1/aaatop.vhd | 1 | 3,714 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:17:25 02/11/2015
-- Design Name:
-- Module Name: aaatop - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
----------------------------------------------------------------------------------
-- LED example, by Jerome Cornet
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity Aaatop is
Port (
CLK : in STD_LOGIC;
txd : inout std_logic;
rxd : in std_logic;
ARD_RESET : out STD_LOGIC;
DUO_SW1 : in STD_LOGIC;
-- DUO_LED : out std_logic;
sram_addr : out std_logic_vector(20 downto 0);
sram_data : inout std_logic_vector(7 downto 0);
sram_ce : out std_logic;
sram_we : out std_logic;
sram_oe : out std_logic;
Arduino : inout STD_LOGIC_VECTOR (53 downto 0)
);
end Aaatop;
architecture Behavioral of Aaatop is
signal CLOCK_40MHZ : std_logic;
signal CTS : std_logic := '1';
signal PIN3 : std_logic;
signal LED1 : std_logic;
signal LED2N : std_logic;
signal LED3N : std_logic;
signal PIN4 : std_logic;
signal RTS : std_logic;
COMPONENT drigmorn1_top
PORT(
sram_addr : out std_logic_vector(20 downto 0);
sram_data : inout std_logic_vector(7 downto 0);
sram_ce : out std_logic;
sram_we : out std_logic;
sram_oe : out std_logic;
CLOCK_40MHZ : IN std_logic;
CTS : IN std_logic := '1';
PIN3 : IN std_logic;
RXD : IN std_logic;
LED1 : OUT std_logic;
LED2N : OUT std_logic;
LED3N : OUT std_logic;
PIN4 : OUT std_logic;
RTS : OUT std_logic;
TXD : OUT std_logic
);
END component ;
component clk32to40
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end component;
begin
ARD_RESET <= not(DUO_SW1);
CTS <= '1';
PIN3 <= not Arduino(40); -- por
-- Arduino(38) <= Arduino(40);
-- Arduino(42) <= Arduino(44);
-- Arduino(46) <= Arduino(48);
-- Arduino(50) <= Arduino(52);
Arduino(38) <= LED1;
Arduino(42) <= LED2N;
Arduino(46) <= LED3N;
Arduino(50) <= '0';
-- sram_addr <= (others => '0');
-- sram_ce <= '0';
-- sram_we <= '0';
-- sram_oe <= '0';
drigmorn1_top0 : drigmorn1_top
PORT map(
sram_addr => sram_addr,
sram_data => sram_data,
sram_ce => sram_ce,
sram_we => sram_we,
sram_oe => sram_oe,
CLOCK_40MHZ => CLOCK_40MHZ,
CTS => CTS,
PIN3 => PIN3,
RXD => RXD,
LED1 => LED1,
LED2N => LED2N,
LED3N => LED3N,
PIN4 => PIN4,
RTS => RTS,
TXD => TXD
);
dcm0: clk32to40
port map
(-- Clock in ports
CLK_IN1 => clk,
-- Clock out ports
CLK_OUT1 => CLOCK_40MHZ);
end Behavioral;
| gpl-2.0 | 7d8de3fe666e5047691b4b04788bd5a7 | 0.516963 | 3.26362 | false | false | false | false |
nsauzede/cpu86 | papilio2_drigmorn1/ipcore_dir/blk_mem_40K/simulation/blk_mem_40K_synth.vhd | 2 | 8,184 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_40K_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY blk_mem_40K_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE blk_mem_40K_synth_ARCH OF blk_mem_40K_synth IS
COMPONENT blk_mem_40K_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 8,
READ_WIDTH => 8 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: blk_mem_40K_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| gpl-2.0 | f7e9498850be6e282aa702a71d9e6adf | 0.545088 | 3.735281 | false | false | false | false |
nsauzede/cpu86 | papilio1/papilio1_tb2.vhd | 1 | 10,611 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:17:57 02/17/2015
-- Design Name:
-- Module Name: C:/nico/perso/hack/hackerspace/fpga/x86/cpu86/papilio1/papilio1_tb.vhd
-- Project Name: papilio1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: papilio1_top
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.STD_LOGIC_UNSIGNED.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
LIBRARY std;
USE std.TEXTIO.all;
USE work.utils.all;
ENTITY papilio1_tb2 IS
END papilio1_tb2;
ARCHITECTURE behavior OF papilio1_tb2 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT papilio1_top
PORT(
rx : IN std_logic;
tx : OUT std_logic;
W1A : INOUT std_logic_vector(15 downto 0);
W1B : INOUT std_logic_vector(15 downto 0);
W2C : INOUT std_logic_vector(15 downto 0);
clk : IN std_logic
);
END COMPONENT;
COMPONENT uartrx
PORT (
clk : IN std_logic;
enable : IN std_logic;
rdn : IN std_logic;
resetn : IN std_logic;
rx : IN std_logic;
dbus : OUT std_logic_vector (7 DOWNTO 0);
ferror : OUT std_logic;
rdrf : OUT std_logic
);
END COMPONENT;
COMPONENT uarttx
PORT (
clk : in std_logic ;
enable : in std_logic ; -- 1 x bit_rate transmit clock enable
resetn : in std_logic ;
dbus : in std_logic_vector (7 downto 0); -- input to txshift register
tdre : out std_logic ;
wrn : in std_logic ;
tx : out std_logic);
END COMPONENT;
--Inputs
signal rx : std_logic := '0';
signal clk : std_logic := '0';
--BiDirs
signal W1A : std_logic_vector(15 downto 0);
signal W1B : std_logic_vector(15 downto 0);
signal W2C : std_logic_vector(15 downto 0);
--Outputs
signal tx : std_logic;
-- Clock period definitions
constant clk_period : time := 31.25 ns;
-- Architecture declarations
signal dind1_s : std_logic;
signal dind2_s : std_logic;
-- Internal signal declarations
SIGNAL CLOCK_40MHZ : std_logic := '0';
SIGNAL CTS : std_logic;
SIGNAL resetn : std_logic;
SIGNAL TXD : std_logic;
SIGNAL cpuerror : std_logic;
SIGNAL rdn_s : std_logic; -- Active Low Read Pulse (CLK)
SIGNAL rdrf : std_logic;
SIGNAL rxenable : std_logic;
SIGNAL txcmd : std_logic;
SIGNAL txenable : std_logic;
SIGNAL udbus : Std_Logic_Vector(7 DOWNTO 0);
CONSTANT DIVIDER_c : std_logic_vector(7 downto 0):="01000001"; -- 65, baudrate divider 40MHz
SIGNAL divtx_s : std_logic_vector(3 downto 0);
SIGNAL divcnt_s : std_logic_vector(7 downto 0);
SIGNAL rxclk16_s : std_logic;
SIGNAL tdre_s : std_logic;
SIGNAL wrn_s : std_logic;
SIGNAL char_s : std_logic_vector(7 downto 0);
BEGIN
CLOCK_40MHZ <= not CLOCK_40MHZ after 12.5 ns; -- 40MHz
process
variable L : line;
procedure write_to_uart (char_in : IN character) is
begin
char_s <=to_std_logic_vector(char_in);
wait until rising_edge(CLOCK_40MHZ);
wrn_s <= '0';
wait until rising_edge(CLOCK_40MHZ);
wrn_s <= '1';
wait until rising_edge(CLOCK_40MHZ);
wait until rising_edge(tdre_s);
end;
begin
CTS <= '1';
resetn <= '0'; -- PIN3 on Drigmorn1 connected to PIN2
wait for 100 ns;
resetn <= '1';
wrn_s <= '1'; -- Active low write strobe to TX UART
char_s <= (others => '1');
wait for 25.1 ms; -- wait for > prompt before issuing commands
write_to_uart('R');
wait for 47 ms; -- wait for > prompt before issuing commands
write_to_uart('D'); -- Issue Fill Memory command
write_to_uart('M');
write_to_uart('0');
write_to_uart('1');
write_to_uart('0');
write_to_uart('0');
wait for 1 ms;
write_to_uart('0');
write_to_uart('1');
write_to_uart('2');
write_to_uart('4');
wait for 50 ms; -- wait for > prompt before issuing commands
wait;
end process;
------------------------------------------------------------------------------
-- 8 bits divider
-- Generate rxenable clock (16 x baudrate)
------------------------------------------------------------------------------
process (CLOCK_40MHZ,resetn) -- First divider
begin
if (resetn='0') then
divcnt_s <= (others => '0');
rxclk16_s <= '0'; -- Receive clock (x16, pulse)
elsif (rising_edge(CLOCK_40MHZ)) then
if divcnt_s=DIVIDER_c then
divcnt_s <= (others => '0');
rxclk16_s <= '1';
else
rxclk16_s <= '0';
divcnt_s <= divcnt_s + '1';
end if;
end if;
end process;
rxenable <= rxclk16_s;
------------------------------------------------------------------------------
-- divider by 16
-- rxclk16/16=txclk
------------------------------------------------------------------------------
process (CLOCK_40MHZ,resetn)
begin
if (resetn='0') then
divtx_s <= (others => '0');
elsif (rising_edge(CLOCK_40MHZ)) then
if rxclk16_s='1' then
divtx_s <= divtx_s + '1';
if divtx_s="0000" then
txenable <= '1';
end if;
else
txenable <= '0';
end if;
end if;
end process;
assert not ((NOW > 0 ns) and cpuerror='1') report "**** CPU Error flag asserted ****" severity error;
------------------------------------------------------------------------------
-- UART Monitor
-- Display string on console after 80 characters or when CR character is received
------------------------------------------------------------------------------
process (rdrf,resetn)
variable L : line;
variable i_v : integer;
begin
if resetn='0' then
i_v := 0; -- clear character counter
elsif (rising_edge(rdrf)) then -- possible, pulse is wide!
if i_v=0 then
write(L,string'("RD UART : "));
if (udbus/=X"0D" and udbus/=X"0A") then
write(L,std_to_char(udbus));
end if;
i_v := i_v+1;
elsif (i_v=80 or udbus=X"0D") then
writeline(output,L);
i_v:=0;
else
if (udbus/=X"0D" and udbus/=X"0A") then
write(L,std_to_char(udbus));
end if;
i_v := i_v+1;
end if;
end if;
end process;
process (CLOCK_40MHZ,resetn) -- First/Second delay
begin
if (resetn='0') then
dind1_s <= '0';
dind2_s <= '0';
elsif (rising_edge(CLOCK_40MHZ)) then
dind1_s <= rdrf;
dind2_s <= dind1_s;
end if;
end process;
rdn_s <= '0' when (dind1_s='1' and dind2_s='0') else '1';
-- Instantiate the Unit Under Test (UUT)
uut: papilio1_top PORT MAP (
rx => rx,
tx => tx,
W1A => W1A,
W1B => W1B,
W2C => W2C,
clk => clk
);
w1b(1) <= resetn;
-- CTS => CTS,
TXD <= tx;
rx <= txcmd;
cpuerror <= w1b(0);
------------------------------------------------------------------------------
-- TX Uart
------------------------------------------------------------------------------
U_1 : uarttx
port map (
clk => CLOCK_40MHZ,
enable => txenable, -- default, working in simu but non-working in real-life ?
resetn => resetn,
dbus => char_s,
tdre => tdre_s,
wrn => wrn_s,
tx => txcmd
);
------------------------------------------------------------------------------
-- RX Uart
------------------------------------------------------------------------------
U_2 : uartrx
PORT MAP (
clk => CLOCK_40MHZ,
enable => rxenable,
resetn => resetn,
dbus => udbus,
rdn => rdn_s,
rdrf => rdrf,
ferror => OPEN,
rx => TXD
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
END;
| gpl-2.0 | 2c345b012ceba20e54ccc18cdb10b32c | 0.417962 | 4.447192 | false | false | false | false |
nsauzede/cpu86 | mx_sdram/pll12to40_inst.vhd | 1 | 142 | pll12to40_inst : pll12to40 PORT MAP (
inclk0 => inclk0_sig,
c0 => c0_sig,
c1 => c1_sig,
c2 => c2_sig,
locked => locked_sig
);
| gpl-2.0 | 422bb3130065b8d82787ea1faa3ce63a | 0.56338 | 2.028571 | false | false | false | false |
nsauzede/cpu86 | papilio1/uart_tx.vhd | 1 | 5,192 | -- UART Transmitter with integral 16 byte FIFO buffer
--
-- 8 bit, no parity, 1 stop bit
--
-- Version : 1.00
-- Version Date : 14th October 2002
--
-- Start of design entry : 14th October 2002
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- [email protected]
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
-- third parties. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
------------------------------------------------------------------------------------
--
-- Main Entity for UART_TX
--
entity uart_tx is
Port ( data_in : in std_logic_vector(7 downto 0);
write_buffer : in std_logic;
reset_buffer : in std_logic;
en_16_x_baud : in std_logic;
serial_out : out std_logic;
buffer_full : out std_logic;
buffer_half_full : out std_logic;
clk : in std_logic);
end uart_tx;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for UART_TX
--
architecture macro_level_definition of uart_tx is
--
------------------------------------------------------------------------------------
--
-- Components used in UART_TX and defined in subsequent entities.
--
------------------------------------------------------------------------------------
--
-- Constant (K) Compact UART Transmitter
--
component kcuart_tx
Port ( data_in : in std_logic_vector(7 downto 0);
send_character : in std_logic;
en_16_x_baud : in std_logic;
serial_out : out std_logic;
Tx_complete : out std_logic;
clk : in std_logic);
end component;
--
-- 'Bucket Brigade' FIFO
--
component bbfifo_16x8
Port ( data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
reset : in std_logic;
write : in std_logic;
read : in std_logic;
full : out std_logic;
half_full : out std_logic;
data_present : out std_logic;
clk : in std_logic);
end component;
--
------------------------------------------------------------------------------------
--
-- Signals used in UART_TX
--
------------------------------------------------------------------------------------
--
signal fifo_data_out : std_logic_vector(7 downto 0);
signal fifo_data_present : std_logic;
signal fifo_read : std_logic;
--
------------------------------------------------------------------------------------
--
-- Start of UART_TX circuit description
--
------------------------------------------------------------------------------------
--
begin
-- 8 to 1 multiplexer to convert parallel data to serial
kcuart: kcuart_tx
port map ( data_in => fifo_data_out,
send_character => fifo_data_present,
en_16_x_baud => en_16_x_baud,
serial_out => serial_out,
Tx_complete => fifo_read,
clk => clk);
buf: bbfifo_16x8
port map ( data_in => data_in,
data_out => fifo_data_out,
reset => reset_buffer,
write => write_buffer,
read => fifo_read,
full => buffer_full,
half_full => buffer_half_full,
data_present => fifo_data_present,
clk => clk);
end macro_level_definition;
------------------------------------------------------------------------------------
--
-- END OF FILE UART_TX.VHD
--
------------------------------------------------------------------------------------
| gpl-2.0 | 9c76969762ad056cc2dec9b8302e0bf9 | 0.454353 | 4.586572 | false | false | false | false |
CamelClarkson/MIPS | Register_File/sim/MIPS_Register_TB.vhd | 1 | 3,865 | ----------------------------------------------------------------------------------
--MIPS Register File Test Bench
--By: Kevin Mottler
--Camel Clarkson 32 Bit MIPS Design Group
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MIPS_Register_TB is
end MIPS_Register_TB;
architecture Behavioral of MIPS_Register_TB is
component Register_File is
Port (
i_Clk : in std_logic;
i_Rst : in std_logic;
i_regwrite : in std_logic;
i_rt : in std_logic_vector(4 downto 0);
i_rs : in std_logic_vector(4 downto 0);
i_rd : in std_logic_vector(4 downto 0);
i_rd_data : in std_logic_vector(31 downto 0);
o_rt_data : out std_logic_vector(31 downto 0);
o_rs_data : out std_logic_vector(31 downto 0)
);
end component;
signal s_i_Clk : std_logic := '0';
signal s_i_rt : std_logic_vector(4 downto 0);
signal s_i_rs : std_logic_vector(4 downto 0);
signal s_i_rd_data : std_logic_vector(31 downto 0);
signal s_i_rd : std_logic_vector(4 downto 0);
signal s_i_RW : std_logic;
signal s_i_Rst : std_logic;
signal s_o_rt_data : std_logic_vector(31 downto 0);
signal s_o_rs_data : std_logic_vector(31 downto 0);
constant clk_period : time := 10 ns;
begin
UUT: Register_File
port map(
i_Clk => s_i_Clk,
i_Rst => s_i_Rst,
i_regwrite => s_i_RW,
i_rt => s_i_rt,
i_rs => s_i_rs,
i_rd => s_i_rd,
i_rd_data => s_i_rd_data,
o_rt_data => s_o_rt_data,
o_rs_data => s_o_rs_data
);
s_i_Clk <= not s_i_Clk after 5 ns;
Tests: process
begin
s_i_rt <= "00110";
s_i_rs <= "00111";
s_i_rd_data <= X"ABCD1234";
s_i_rd <= "00111";
s_i_RW <= '0';
s_i_Rst <= '1';
wait for 5 ns;
s_i_rt <= "00111";
s_i_rs <= "00111";
s_i_rd_data <= X"22223333";
s_i_rd <= "00110";
s_i_RW <= '0';
s_i_Rst <= '0';
wait for 5 ns;
s_i_rt <= "00111";
s_i_rs <= "00111";
s_i_rd_data <= X"ABCD1234";
s_i_rd <= "00110";
s_i_RW <= '1';
s_i_Rst <= '0';
wait for 5 ns;
s_i_rt <= "00110";
s_i_rs <= "00110";
s_i_rd_data <= X"12345678";
s_i_rd <= "00110";
s_i_RW <= '0';
s_i_Rst <= '0';
wait for 5 ns;
s_i_rt <= "00110";
s_i_rs <= "00110";
s_i_rd_data <= X"FFFFEEEE";
s_i_rd <= "00101";
s_i_RW <= '1';
s_i_Rst <= '0';
wait for 5 ns;
s_i_rt <= "00101";
s_i_rs <= "00101";
s_i_rd_data <= X"ABCD1234";
s_i_rd <= "00110";
s_i_RW <= '0';
s_i_Rst <= '0';
wait for 5 ns;
s_i_rt <= "00101";
s_i_rs <= "00101";
s_i_rd_data <= X"FFFFFFFF";
s_i_rd <= "00111";
s_i_RW <= '1';
s_i_Rst <= '0';
wait for 5 ns;
s_i_rt <= "00101";
s_i_rs <= "00111";
s_i_rd_data <= X"FFFFFFFF";
s_i_rd <= "00111";
s_i_RW <= '0';
s_i_Rst <= '0';
wait for 5 ns;
s_i_rt <= "01100";
s_i_rs <= "00101";
s_i_rd_data <= X"FEEDBEEF";
s_i_rd <= "01100";
s_i_RW <= '1';
s_i_Rst <= '0';
wait for 5 ns;
s_i_rt <= "01100";
s_i_rs <= "00111";
s_i_rd_data <= X"FFFFFFFF";
s_i_rd <= "00111";
s_i_RW <= '1';
s_i_Rst <= '0';
wait for 5 ns;
s_i_rt <= "00110";
s_i_rs <= "00111";
s_i_rd_data <= X"ABCD1234";
s_i_rd <= "00111";
s_i_RW <= '0';
s_i_Rst <= '1';
wait for 5 ns;
s_i_rt <= "01100";
s_i_rs <= "00101";
s_i_rd_data <= X"FEEDBEEF";
s_i_rd <= "01100";
s_i_RW <= '1';
s_i_Rst <= '0';
wait for 5 ns;
wait;
end process;
end Behavioral;
| mit | 2f8afb02d6964fe0edd1fe45ac833e19 | 0.441656 | 2.643639 | false | false | false | false |
nsauzede/cpu86 | p2_vga_spi/aaatop.vhd | 1 | 5,429 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:17:25 02/11/2015
-- Design Name:
-- Module Name: aaatop - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
----------------------------------------------------------------------------------
-- LED example, by Jerome Cornet
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity Aaatop is
Port (
CLK,reset : in STD_LOGIC;
tx : inout std_logic;
rx : in std_logic;
ARDUINO_RESET : out STD_LOGIC;
DUO_SW1 : in STD_LOGIC;
-- DUO_LED : out std_logic;
sram_addr : out std_logic_vector(20 downto 0);
sram_data : inout std_logic_vector(7 downto 0);
sram_ce : out std_logic;
sram_we : out std_logic;
sram_oe : out std_logic;
SD_MISO : in std_logic;
SD_MOSI : out std_logic;
SD_SCK : out std_logic;
SD_nCS : out std_logic;
SW_LEFT : in STD_LOGIC;
SW_UP : in STD_LOGIC;
SW_DOWN : in STD_LOGIC;
SW_RIGHT : in STD_LOGIC;
LED1 : inout STD_LOGIC;
LED2 : inout STD_LOGIC;
LED3 : inout STD_LOGIC;
LED4 : inout STD_LOGIC;
VGA_HSYNC : out STD_LOGIC;
VGA_VSYNC : out STD_LOGIC;
VGA_BLUE : out std_logic_vector(3 downto 0);
VGA_GREEN : out std_logic_vector(3 downto 0);
VGA_RED : out std_logic_vector(3 downto 0)
-- Arduino : inout STD_LOGIC_VECTOR (21 downto 0)
-- Arduino : inout STD_LOGIC_VECTOR (53 downto 0)
);
end Aaatop;
architecture Behavioral of Aaatop is
signal CLOCK_40MHZ : std_logic;
signal CTS : std_logic := '1';
signal PIN3 : std_logic;
signal LED1P : std_logic;
signal LED2N : std_logic;
signal LED3N : std_logic;
signal PIN4 : std_logic;
signal RTS : std_logic;
signal vramaddr : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal vramdata : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal pixel_x, pixel_y: std_logic_vector(9 downto 0);
signal clock, video_on, pixel_tick: std_logic;
signal rgb_reg, rgb_next: std_logic_vector(2 downto 0);
signal hsync, vsync: std_logic;
signal rgb: std_logic_vector(2 downto 0);
signal buttons: std_logic_vector(3 downto 0);
signal leds: std_logic_vector(3 downto 0);
begin
CTS <= '1';
-- PIN3 <= not Arduino(40); -- por
-- PIN3 <= reset; -- por
PIN3 <= '1'; -- por
-- Arduino(38) <= Arduino(40);
-- Arduino(42) <= Arduino(44);
-- Arduino(46) <= Arduino(48);
-- Arduino(50) <= Arduino(52);
-- Arduino(38) <= LED1;
-- Arduino(42) <= LED2N;
-- Arduino(46) <= LED3N;
-- Arduino(50) <= '0';
-- sram_addr <= (others => '0');
-- sram_ce <= '0';
-- sram_we <= '0';
-- sram_oe <= '0';
drigmorn1_top0: ENTITY work.drigmorn1_top
PORT map(
sram_addr => sram_addr,
sram_data => sram_data,
sram_ce => sram_ce,
sram_we => sram_we,
sram_oe => sram_oe,
vramaddr => vramaddr,
vramdata => vramdata,
spi_cs => SD_nCS,
spi_clk => SD_SCK,
spi_mosi => SD_MOSI,
spi_miso => SD_MISO,
buttons => buttons,
leds => leds,
CLOCK_40MHZ => CLOCK_40MHZ,
CTS => CTS,
PIN3 => PIN3,
RXD => RX,
LED1 => LED1P,
LED2N => LED2N,
LED3N => LED3N,
PIN4 => PIN4,
RTS => RTS,
TXD => TX
);
dcm0: entity work.clk32to40
port map
(-- Clock in ports
CLK_IN1 => clk,
-- Clock out ports
CLK_OUT1 => CLOCK_40MHZ,
CLK_OUT2 => clock
);
-- VGA signals
vga_sync_unit: entity work.vga_sync
port map(
clock => clock,
reset => reset,
hsync => hsync,
vsync => vsync,
video_on => video_on,
pixel_tick => pixel_tick,
pixel_x => pixel_x,
pixel_y => pixel_y
);
-- font generator
font_gen_unit: entity work.font_generator
port map(
clock => pixel_tick,
vramaddr => vramaddr,
vramdata => vramdata,
video_on => video_on,
pixel_x => pixel_x,
pixel_y => pixel_y,
rgb_text => rgb_next
);
ARDUINO_RESET <= not(DUO_SW1);
buttons <= sw_left & sw_right & sw_up & sw_down;
led1 <= leds(0);
led2 <= leds(1);
led3 <= leds(2);
led4 <= leds(3);
-- rgb buffer
process(clock)
begin
if clock'event and clock = '1' then
if pixel_tick = '1' then
rgb_reg <= rgb_next;
end if;
end if;
end process;
rgb <= rgb_reg;
vga_hsync <= hsync;
vga_vsync <= vsync;
vga_blue <= (others => rgb(0));--blue
vga_green <= (others => rgb(1));--green
vga_red <= (others => rgb(2));--red
end Behavioral;
| gpl-2.0 | 37108f9afedab2956c8b9fdb8151ddd2 | 0.537115 | 3.227705 | false | false | false | false |
da-steve101/binary_connect_cifar | src/main/vhdl/GenericAddSub16.vhd | 1 | 20,907 | --------------------------------------------------------------------------------
-- Xilinx_GenericAddSub_16_fixed_01_slice4_init
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors:
-- >> University of Kassel, Germany
-- >> Digital Technology Group
-- >> Author(s):
-- >> Marco Kleinlein <[email protected]>
--------------------------------------------------------------------------------
library UNISIM;
use UNISIM.Vcomponents.all;
--------------------------------------------------------------------------------
-- combinatorial
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;
entity Xilinx_GenericAddSub_16_fixed_01_slice4_init is
port ( x_in : in std_logic_vector(3 downto 0);
y_in : in std_logic_vector(3 downto 0);
neg_x_in : in std_logic;
neg_y_in : in std_logic;
carry_in : in std_logic;
carry_out : out std_logic;
sum_out : out std_logic_vector(3 downto 0) );
end entity;
architecture arch of Xilinx_GenericAddSub_16_fixed_01_slice4_init is
signal cc_di : std_logic_vector(3 downto 0);
signal cc_s : std_logic_vector(3 downto 0);
signal cc_o : std_logic_vector(3 downto 0);
signal cc_co : std_logic_vector(3 downto 0);
signal lut_o5 : std_logic_vector(3 downto 0);
signal lut_o6 : std_logic_vector(3 downto 0);
begin
cc_di <= lut_o5;
cc_s <= lut_o6;
lut_bit_0: LUT6_2
generic map ( init => x"099609960a5a0a5a")
port map ( i0 => y_in(0),
i1 => x_in(0),
i2 => neg_y_in,
i3 => neg_x_in,
i4 => '1',
i5 => '1',
o5 => lut_o5(0),
o6 => lut_o6(0));
lut_bit_1: LUT6_2
generic map ( init => x"099609960a5a0a5a")
port map ( i0 => y_in(1),
i1 => x_in(1),
i2 => neg_y_in,
i3 => neg_x_in,
i4 => '1',
i5 => '1',
o5 => lut_o5(1),
o6 => lut_o6(1));
lut_bit_2: LUT6_2
generic map ( init => x"099609960a5a0a5a")
port map ( i0 => y_in(2),
i1 => x_in(2),
i2 => neg_y_in,
i3 => neg_x_in,
i4 => '1',
i5 => '1',
o5 => lut_o5(2),
o6 => lut_o6(2));
lut_bit_3: LUT6_2
generic map ( init => x"099609960a5a0a5a")
port map ( i0 => y_in(3),
i1 => x_in(3),
i2 => neg_y_in,
i3 => neg_x_in,
i4 => '1',
i5 => '1',
o5 => lut_o5(3),
o6 => lut_o6(3));
slice_cc: CARRY4
port map ( ci => carry_in,
co => cc_co,
cyinit => '0',
di => cc_di,
o => cc_o,
s => cc_s);
carry_out <= cc_co(3);
sum_out <= cc_o(3 downto 0);
end architecture;
--------------------------------------------------------------------------------
-- Xilinx_GenericAddSub_16_fixed_01_slice4
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors:
-- >> University of Kassel, Germany
-- >> Digital Technology Group
-- >> Author(s):
-- >> Marco Kleinlein <[email protected]>
--------------------------------------------------------------------------------
library UNISIM;
use UNISIM.Vcomponents.all;
--------------------------------------------------------------------------------
-- combinatorial
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;
entity Xilinx_GenericAddSub_16_fixed_01_slice4 is
port ( x_in : in std_logic_vector(3 downto 0);
y_in : in std_logic_vector(3 downto 0);
neg_x_in : in std_logic;
neg_y_in : in std_logic;
carry_in : in std_logic;
carry_out : out std_logic;
sum_out : out std_logic_vector(3 downto 0) );
end entity;
architecture arch of Xilinx_GenericAddSub_16_fixed_01_slice4 is
signal cc_di : std_logic_vector(3 downto 0);
signal cc_s : std_logic_vector(3 downto 0);
signal cc_o : std_logic_vector(3 downto 0);
signal cc_co : std_logic_vector(3 downto 0);
signal lut_o5 : std_logic_vector(3 downto 0);
signal lut_o6 : std_logic_vector(3 downto 0);
begin
cc_di <= lut_o5;
cc_s <= lut_o6;
lut_bit_0: LUT6_2
generic map ( init => x"099609960a5a0a5a")
port map ( i0 => y_in(0),
i1 => x_in(0),
i2 => neg_y_in,
i3 => neg_x_in,
i4 => '1',
i5 => '1',
o5 => lut_o5(0),
o6 => lut_o6(0));
lut_bit_1: LUT6_2
generic map ( init => x"099609960a5a0a5a")
port map ( i0 => y_in(1),
i1 => x_in(1),
i2 => neg_y_in,
i3 => neg_x_in,
i4 => '1',
i5 => '1',
o5 => lut_o5(1),
o6 => lut_o6(1));
lut_bit_2: LUT6_2
generic map ( init => x"099609960a5a0a5a")
port map ( i0 => y_in(2),
i1 => x_in(2),
i2 => neg_y_in,
i3 => neg_x_in,
i4 => '1',
i5 => '1',
o5 => lut_o5(2),
o6 => lut_o6(2));
lut_bit_3: LUT6_2
generic map ( init => x"099609960a5a0a5a")
port map ( i0 => y_in(3),
i1 => x_in(3),
i2 => neg_y_in,
i3 => neg_x_in,
i4 => '1',
i5 => '1',
o5 => lut_o5(3),
o6 => lut_o6(3));
slice_cc: CARRY4
port map ( ci => carry_in,
co => cc_co,
cyinit => '0',
di => cc_di,
o => cc_o,
s => cc_s);
carry_out <= cc_co(3);
sum_out <= cc_o(3 downto 0);
end architecture;
--------------------------------------------------------------------------------
-- Xilinx_GenericAddSub_16_fixed_01
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors:
-- >> University of Kassel, Germany
-- >> Digital Technology Group
-- >> Author(s):
-- >> Marco Kleinlein <[email protected]>
--------------------------------------------------------------------------------
-- combinatorial
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;
entity Xilinx_GenericAddSub_16_fixed_01 is
port ( x_i : in std_logic_vector(15 downto 0);
y_i : in std_logic_vector(15 downto 0);
sum_o : out std_logic_vector(15 downto 0);
c_o : out std_logic );
end entity;
architecture arch of Xilinx_GenericAddSub_16_fixed_01 is
component Xilinx_GenericAddSub_16_fixed_01_slice4_init is
port ( x_in : in std_logic_vector(3 downto 0);
y_in : in std_logic_vector(3 downto 0);
neg_x_in : in std_logic;
neg_y_in : in std_logic;
carry_in : in std_logic;
carry_out : out std_logic;
sum_out : out std_logic_vector(3 downto 0) );
end component;
component Xilinx_GenericAddSub_16_fixed_01_slice4 is
port ( x_in : in std_logic_vector(3 downto 0);
y_in : in std_logic_vector(3 downto 0);
neg_x_in : in std_logic;
neg_y_in : in std_logic;
carry_in : in std_logic;
carry_out : out std_logic;
sum_out : out std_logic_vector(3 downto 0) );
end component;
signal carry_0, carry_1, carry_2, carry_3 : std_logic;
signal sum_t : std_logic_vector(15 downto 0);
signal x : std_logic_vector(15 downto 0);
signal y : std_logic_vector(15 downto 0);
begin
x(15 downto 0) <= x_i;
y(15 downto 0) <= y_i;
slice_0: Xilinx_GenericAddSub_16_fixed_01_slice4_init
port map ( carry_in => '1',
carry_out => carry_0,
neg_x_in => '0',
neg_y_in => '1',
sum_out => sum_t(3 downto 0),
x_in => x(3 downto 0),
y_in => y(3 downto 0));
slice_1: Xilinx_GenericAddSub_16_fixed_01_slice4
port map ( carry_in => carry_0,
carry_out => carry_1,
neg_x_in => '0',
neg_y_in => '1',
sum_out => sum_t(7 downto 4),
x_in => x(7 downto 4),
y_in => y(7 downto 4));
slice_2: Xilinx_GenericAddSub_16_fixed_01_slice4
port map ( carry_in => carry_1,
carry_out => carry_2,
neg_x_in => '0',
neg_y_in => '1',
sum_out => sum_t(11 downto 8),
x_in => x(11 downto 8),
y_in => y(11 downto 8));
slice_3: Xilinx_GenericAddSub_16_fixed_01_slice4
port map ( carry_in => carry_2,
carry_out => carry_3,
neg_x_in => '0',
neg_y_in => '1',
sum_out => sum_t(15 downto 12),
x_in => x(15 downto 12),
y_in => y(15 downto 12));
sum_o <= sum_t(15 downto 0);
c_o <= carry_3;
end architecture;
--------------------------------------------------------------------------------
-- Xilinx_GenericAddSub_16_dss_slice4_dss_init
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors:
-- >> University of Kassel, Germany
-- >> Digital Technology Group
-- >> Author(s):
-- >> Marco Kleinlein <[email protected]>
--------------------------------------------------------------------------------
library UNISIM;
use UNISIM.Vcomponents.all;
--------------------------------------------------------------------------------
-- combinatorial
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;
entity Xilinx_GenericAddSub_16_dss_slice4_dss_init is
port ( x_in : in std_logic_vector(3 downto 0);
y_in : in std_logic_vector(3 downto 0);
neg_x_in : in std_logic;
neg_y_in : in std_logic;
carry_in : in std_logic;
carry_out : out std_logic;
sum_out : out std_logic_vector(3 downto 0);
bbus_in : in std_logic_vector(3 downto 0);
bbus_out : out std_logic_vector(3 downto 0) );
end entity;
architecture arch of Xilinx_GenericAddSub_16_dss_slice4_dss_init is
signal cc_di : std_logic_vector(3 downto 0);
signal cc_s : std_logic_vector(3 downto 0);
signal cc_o : std_logic_vector(3 downto 0);
signal cc_co : std_logic_vector(3 downto 0);
signal lut_o5 : std_logic_vector(3 downto 0);
signal lut_o6 : std_logic_vector(3 downto 0);
signal bb_t : std_logic_vector(3 downto 0);
begin
cc_di <= bbus_in;
cc_s <= lut_o6;
lut_bit_0: LUT6_2
generic map ( init => x"666666661bd81bd8")
port map ( i0 => y_in(0),
i1 => x_in(0),
i2 => neg_y_in,
i3 => neg_x_in,
i4 => bbus_in(0),
i5 => '1',
o5 => bb_t(0),
o6 => lut_o6(0));
lut_bit_1: LUT6_2
generic map ( init => x"6669999672487248")
port map ( i0 => y_in(1),
i1 => x_in(1),
i2 => neg_y_in,
i3 => neg_x_in,
i4 => bbus_in(1),
i5 => '1',
o5 => bb_t(1),
o6 => lut_o6(1));
lut_bit_2: LUT6_2
generic map ( init => x"9669699612481248")
port map ( i0 => y_in(2),
i1 => x_in(2),
i2 => neg_y_in,
i3 => neg_x_in,
i4 => bbus_in(2),
i5 => '1',
o5 => bb_t(2),
o6 => lut_o6(2));
lut_bit_3: LUT6_2
generic map ( init => x"9669699612481248")
port map ( i0 => y_in(3),
i1 => x_in(3),
i2 => neg_y_in,
i3 => neg_x_in,
i4 => bbus_in(3),
i5 => '1',
o5 => bb_t(3),
o6 => lut_o6(3));
slice_cc: CARRY4
port map ( ci => carry_in,
co => cc_co,
cyinit => '0',
di => cc_di,
o => cc_o,
s => cc_s);
carry_out <= cc_co(3);
sum_out <= cc_o(3 downto 0);
bbus_out <= bb_t;
end architecture;
--------------------------------------------------------------------------------
-- Xilinx_GenericAddSub_16_dss_slice4_dss
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors:
-- >> University of Kassel, Germany
-- >> Digital Technology Group
-- >> Author(s):
-- >> Marco Kleinlein <[email protected]>
--------------------------------------------------------------------------------
library UNISIM;
use UNISIM.Vcomponents.all;
--------------------------------------------------------------------------------
-- combinatorial
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;
entity Xilinx_GenericAddSub_16_dss_slice4_dss is
port ( x_in : in std_logic_vector(3 downto 0);
y_in : in std_logic_vector(3 downto 0);
neg_x_in : in std_logic;
neg_y_in : in std_logic;
carry_in : in std_logic;
carry_out : out std_logic;
sum_out : out std_logic_vector(3 downto 0);
bbus_in : in std_logic_vector(3 downto 0);
bbus_out : out std_logic_vector(3 downto 0) );
end entity;
architecture arch of Xilinx_GenericAddSub_16_dss_slice4_dss is
signal cc_di : std_logic_vector(3 downto 0);
signal cc_s : std_logic_vector(3 downto 0);
signal cc_o : std_logic_vector(3 downto 0);
signal cc_co : std_logic_vector(3 downto 0);
signal lut_o5 : std_logic_vector(3 downto 0);
signal lut_o6 : std_logic_vector(3 downto 0);
signal bb_t : std_logic_vector(3 downto 0);
begin
cc_di <= bbus_in;
cc_s <= lut_o6;
lut_bit_0: LUT6_2
generic map ( init => x"9669699612481248")
port map ( i0 => y_in(0),
i1 => x_in(0),
i2 => neg_y_in,
i3 => neg_x_in,
i4 => bbus_in(0),
i5 => '1',
o5 => bb_t(0),
o6 => lut_o6(0));
lut_bit_1: LUT6_2
generic map ( init => x"9669699612481248")
port map ( i0 => y_in(1),
i1 => x_in(1),
i2 => neg_y_in,
i3 => neg_x_in,
i4 => bbus_in(1),
i5 => '1',
o5 => bb_t(1),
o6 => lut_o6(1));
lut_bit_2: LUT6_2
generic map ( init => x"9669699612481248")
port map ( i0 => y_in(2),
i1 => x_in(2),
i2 => neg_y_in,
i3 => neg_x_in,
i4 => bbus_in(2),
i5 => '1',
o5 => bb_t(2),
o6 => lut_o6(2));
lut_bit_3: LUT6_2
generic map ( init => x"9669699612481248")
port map ( i0 => y_in(3),
i1 => x_in(3),
i2 => neg_y_in,
i3 => neg_x_in,
i4 => bbus_in(3),
i5 => '1',
o5 => bb_t(3),
o6 => lut_o6(3));
slice_cc: CARRY4
port map ( ci => carry_in,
co => cc_co,
cyinit => '0',
di => cc_di,
o => cc_o,
s => cc_s);
carry_out <= cc_co(3);
sum_out <= cc_o(3 downto 0);
bbus_out <= bb_t;
end architecture;
--------------------------------------------------------------------------------
-- Xilinx_GenericAddSub_16_dss
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved
-- Authors:
-- >> University of Kassel, Germany
-- >> Digital Technology Group
-- >> Author(s):
-- >> Marco Kleinlein <[email protected]>
--------------------------------------------------------------------------------
-- combinatorial
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;
entity Xilinx_GenericAddSub_16_dss is
port ( x_i : in std_logic_vector(15 downto 0);
y_i : in std_logic_vector(15 downto 0);
neg_x_i : in std_logic;
neg_y_i : in std_logic;
sum_o : out std_logic_vector(15 downto 0);
c_o : out std_logic );
end entity;
architecture arch of Xilinx_GenericAddSub_16_dss is
component Xilinx_GenericAddSub_16_dss_slice4_dss_init is
port ( x_in : in std_logic_vector(3 downto 0);
y_in : in std_logic_vector(3 downto 0);
neg_x_in : in std_logic;
neg_y_in : in std_logic;
carry_in : in std_logic;
carry_out : out std_logic;
sum_out : out std_logic_vector(3 downto 0);
bbus_in : in std_logic_vector(3 downto 0);
bbus_out : out std_logic_vector(3 downto 0) );
end component;
component Xilinx_GenericAddSub_16_dss_slice4_dss is
port ( x_in : in std_logic_vector(3 downto 0);
y_in : in std_logic_vector(3 downto 0);
neg_x_in : in std_logic;
neg_y_in : in std_logic;
carry_in : in std_logic;
carry_out : out std_logic;
sum_out : out std_logic_vector(3 downto 0);
bbus_in : in std_logic_vector(3 downto 0);
bbus_out : out std_logic_vector(3 downto 0) );
end component;
signal carry : std_logic_vector(4 downto 0);
signal sum_t : std_logic_vector(15 downto 0);
signal x : std_logic_vector(15 downto 0);
signal y : std_logic_vector(15 downto 0);
signal neg_x : std_logic;
signal neg_y : std_logic;
signal bbus : std_logic_vector(16 downto 0);
begin
x(15 downto 0) <= x_i;
y(15 downto 0) <= y_i;
neg_x <= neg_x_i;
neg_y <= neg_y_i;
bbus(0) <= '0';
slice_0: Xilinx_GenericAddSub_16_dss_slice4_dss_init
port map ( bbus_in => bbus(3 downto 0),
bbus_out => bbus(4 downto 1),
carry_in => '0',
carry_out => carry(0),
neg_x_in => neg_x,
neg_y_in => neg_y,
sum_out => sum_t(3 downto 0),
x_in => x(3 downto 0),
y_in => y(3 downto 0));
slice_1: Xilinx_GenericAddSub_16_dss_slice4_dss
port map ( bbus_in => bbus(7 downto 4),
bbus_out => bbus(8 downto 5),
carry_in => carry(0),
carry_out => carry(1),
neg_x_in => neg_x,
neg_y_in => neg_y,
sum_out => sum_t(7 downto 4),
x_in => x(7 downto 4),
y_in => y(7 downto 4));
slice_2: Xilinx_GenericAddSub_16_dss_slice4_dss
port map ( bbus_in => bbus(11 downto 8),
bbus_out => bbus(12 downto 9),
carry_in => carry(1),
carry_out => carry(2),
neg_x_in => neg_x,
neg_y_in => neg_y,
sum_out => sum_t(11 downto 8),
x_in => x(11 downto 8),
y_in => y(11 downto 8));
slice_3: Xilinx_GenericAddSub_16_dss_slice4_dss
port map ( bbus_in => bbus(15 downto 12),
bbus_out => bbus(16 downto 13),
carry_in => carry(2),
carry_out => carry(3),
neg_x_in => neg_x,
neg_y_in => neg_y,
sum_out => sum_t(15 downto 12),
x_in => x(15 downto 12),
y_in => y(15 downto 12));
sum_o <= sum_t(15 downto 0);
c_o <= carry(4);
end architecture;
| gpl-3.0 | 916fb83dc36047826735de64ee1be67e | 0.44961 | 3.368294 | false | false | false | false |
nsauzede/cpu86 | p2_vga_spi/font_generator.vhd | 1 | 2,161 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity font_generator is
port(
clock: in std_logic;
vramaddr : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
vramdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
video_on: in std_logic;
pixel_x, pixel_y: in std_logic_vector(9 downto 0);
rgb_text: out std_logic_vector(2 downto 0)
);
end font_generator;
architecture Behavioral of font_generator is
-- component blk_mem_gen_v7_3
-- port (
-- clka: in std_logic;
-- wea: in std_logic_vector(0 downto 0);
-- addra: in std_logic_vector(11 downto 0);
-- dina: in std_logic_vector(6 downto 0);
-- clkb: in std_logic;
-- addrb: in std_logic_vector(11 downto 0);
-- doutb: out std_logic_vector(6 downto 0)
-- );
-- end component;
signal char_addr: std_logic_vector(6 downto 0);
signal rom_addr: std_logic_vector(10 downto 0);
signal row_addr: std_logic_vector(3 downto 0);
signal bit_addr: std_logic_vector(2 downto 0);
signal font_word: std_logic_vector(7 downto 0);
signal font_bit: std_logic;
signal addr_read: std_logic_vector(11 downto 0);
signal dout: std_logic_vector(6 downto 0) := "1000010";
begin
-- instantiate font ROM
font_unit: entity work.font_rom
port map(
clock => clock,
addr => rom_addr,
data => font_word
);
-- instantiate frame buffer
-- frame_buffer_unit: blk_mem_gen_v7_3
-- port map (
-- clka => clock,
-- wea => (others => '1'),
-- addra => addr_write,
-- dina => din,
-- clkb => clock,
-- addrb => addr_read,
-- doutb => dout
-- );
vramaddr <= x"0" & addr_read;
dout <= vramdata(6 downto 0);
-- dout <= "1000010";
-- tile RAM read
addr_read <= pixel_y(8 downto 4) & pixel_x(9 downto 3);
char_addr <= dout;
-- font ROM interface
row_addr <= pixel_y(3 downto 0);
rom_addr <= char_addr & row_addr;
bit_addr <= std_logic_vector(unsigned(pixel_x(2 downto 0)) - 1);
font_bit <= font_word(to_integer(unsigned(not bit_addr)));
-- rgb multiplexing
process(video_on, font_bit)
begin
if video_on = '0' then
rgb_text <= "000";
elsif font_bit = '1' then
rgb_text <= "111";
else
rgb_text <= "000";
end if;
end process;
end Behavioral;
| gpl-2.0 | 99ceed606fe32d47686891d9104a532d | 0.64137 | 2.728535 | false | false | false | false |
nsauzede/cpu86 | papilio2_vga/font_generator.vhd | 1 | 2,718 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity font_generator is
port(
clock: in std_logic;
vramaddr : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
vramdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
video_on: in std_logic;
buttons: in std_logic_vector(3 downto 0);
pixel_x, pixel_y: in std_logic_vector(9 downto 0);
rgb_text: out std_logic_vector(2 downto 0)
);
end font_generator;
architecture Behavioral of font_generator is
-- component blk_mem_gen_v7_3
-- port (
-- clka: in std_logic;
-- wea: in std_logic_vector(0 downto 0);
-- addra: in std_logic_vector(11 downto 0);
-- dina: in std_logic_vector(6 downto 0);
-- clkb: in std_logic;
-- addrb: in std_logic_vector(11 downto 0);
-- doutb: out std_logic_vector(6 downto 0)
-- );
-- end component;
signal char_addr: std_logic_vector(6 downto 0);
signal rom_addr: std_logic_vector(10 downto 0);
signal row_addr: std_logic_vector(3 downto 0);
signal bit_addr: std_logic_vector(2 downto 0);
signal font_word: std_logic_vector(7 downto 0);
signal font_bit: std_logic;
signal addr_write: std_logic_vector(11 downto 0) := (others => '0');
signal addr_read: std_logic_vector(11 downto 0);
signal din: std_logic_vector(6 downto 0) := "1000001";
signal dout: std_logic_vector(6 downto 0) := "1000010";
signal bbut0: std_logic_vector(3 downto 0) := "0000";
signal bbut1: std_logic_vector(3 downto 0) := "0000";
begin
-- instantiate font ROM
font_unit: entity work.font_rom
port map(
clock => clock,
addr => rom_addr,
data => font_word
);
-- instantiate frame buffer
-- frame_buffer_unit: blk_mem_gen_v7_3
-- port map (
-- clka => clock,
-- wea => (others => '1'),
-- addra => addr_write,
-- dina => din,
-- clkb => clock,
-- addrb => addr_read,
-- doutb => dout
-- );
vramaddr <= x"0" & addr_read;
dout <= vramdata(6 downto 0);
-- dout <= "1000010";
din(3 downto 0) <= buttons;
addr_write(3 downto 0) <= buttons;
-- addr_write <= to_unsigned(addr_write,12) + 1 when bbut0="1110" else addr_write;
process(clock, buttons) begin
if rising_edge(clock) then
bbut0 <= bbut0(2 downto 0) & buttons(0);
end if;
end process;
-- tile RAM read
addr_read <= pixel_y(8 downto 4) & pixel_x(9 downto 3);
char_addr <= dout;
-- font ROM interface
row_addr <= pixel_y(3 downto 0);
rom_addr <= char_addr & row_addr;
bit_addr <= std_logic_vector(unsigned(pixel_x(2 downto 0)) - 1);
font_bit <= font_word(to_integer(unsigned(not bit_addr)));
-- rgb multiplexing
process(video_on, font_bit)
begin
if video_on = '0' then
rgb_text <= "000";
elsif font_bit = '1' then
rgb_text <= "111";
else
rgb_text <= "000";
end if;
end process;
end Behavioral;
| gpl-2.0 | b045488fff5f4aa4ebfb2302c964c3e3 | 0.647167 | 2.731658 | false | false | false | false |
nsauzede/cpu86 | papilio1/testbench/Drigmorn1_tb.vhd | 2 | 12,028 | -------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- TestBench --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.STD_LOGIC_UNSIGNED.all;
LIBRARY std;
USE std.TEXTIO.all;
USE work.utils.all;
entity Drigmorn1_tb is
end Drigmorn1_tb ;
ARCHITECTURE struct OF Drigmorn1_tb IS
-- Architecture declarations
signal dind1_s : std_logic;
signal dind2_s : std_logic;
-- Internal signal declarations
SIGNAL CLOCK_40MHZ : std_logic := '0';
SIGNAL CTS : std_logic;
SIGNAL resetn : std_logic;
SIGNAL TXD : std_logic;
SIGNAL cpuerror : std_logic;
SIGNAL rdn_s : std_logic; -- Active Low Read Pulse (CLK)
SIGNAL rdrf : std_logic;
SIGNAL rxenable : std_logic;
SIGNAL txcmd : std_logic;
SIGNAL txenable : std_logic;
SIGNAL udbus : Std_Logic_Vector(7 DOWNTO 0);
CONSTANT DIVIDER_c : std_logic_vector(7 downto 0):="01000001"; -- 65, baudrate divider 40MHz
SIGNAL divtx_s : std_logic_vector(3 downto 0);
SIGNAL divcnt_s : std_logic_vector(7 downto 0);
SIGNAL rxclk16_s : std_logic;
SIGNAL tdre_s : std_logic;
SIGNAL wrn_s : std_logic;
SIGNAL char_s : std_logic_vector(7 downto 0);
-- Component Declarations
COMPONENT drigmorn1_top
PORT(
CLOCK_40MHZ : IN std_logic;
CTS : IN std_logic := '1';
PIN3 : IN std_logic;
RXD : IN std_logic;
LED1 : OUT std_logic;
LED2N : OUT std_logic;
LED3N : OUT std_logic;
PIN4 : OUT std_logic;
RTS : OUT std_logic;
TXD : OUT std_logic
);
END COMPONENT;
COMPONENT uartrx
PORT (
clk : IN std_logic;
enable : IN std_logic;
rdn : IN std_logic;
resetn : IN std_logic;
rx : IN std_logic;
dbus : OUT std_logic_vector (7 DOWNTO 0);
ferror : OUT std_logic;
rdrf : OUT std_logic
);
END COMPONENT;
COMPONENT uarttx
PORT (
clk : in std_logic ;
enable : in std_logic ; -- 1 x bit_rate transmit clock enable
resetn : in std_logic ;
dbus : in std_logic_vector (7 downto 0); -- input to txshift register
tdre : out std_logic ;
wrn : in std_logic ;
tx : out std_logic);
END COMPONENT;
BEGIN
CLOCK_40MHZ <= not CLOCK_40MHZ after 12.5 ns; -- 40MHz
process
variable L : line;
procedure write_to_uart (char_in : IN character) is
begin
char_s <=to_std_logic_vector(char_in);
wait until rising_edge(CLOCK_40MHZ);
wrn_s <= '0';
wait until rising_edge(CLOCK_40MHZ);
wrn_s <= '1';
wait until rising_edge(CLOCK_40MHZ);
wait until rising_edge(tdre_s);
end;
begin
CTS <= '1';
resetn <= '0'; -- PIN3 on Drigmorn1 connected to PIN2
wait for 100 ns;
resetn <= '1';
wrn_s <= '1'; -- Active low write strobe to TX UART
char_s <= (others => '1');
wait for 25.1 ms; -- wait for > prompt before issuing commands
write_to_uart('R');
wait for 47 ms; -- wait for > prompt before issuing commands
write_to_uart('D'); -- Issue Fill Memory command
write_to_uart('M');
write_to_uart('0');
write_to_uart('1');
write_to_uart('0');
write_to_uart('0');
wait for 1 ms;
write_to_uart('0');
write_to_uart('1');
write_to_uart('2');
write_to_uart('4');
wait for 50 ms; -- wait for > prompt before issuing commands
wait;
end process;
------------------------------------------------------------------------------
-- 8 bits divider
-- Generate rxenable clock (16 x baudrate)
------------------------------------------------------------------------------
process (CLOCK_40MHZ,resetn) -- First divider
begin
if (resetn='0') then
divcnt_s <= (others => '0');
rxclk16_s <= '0'; -- Receive clock (x16, pulse)
elsif (rising_edge(CLOCK_40MHZ)) then
if divcnt_s=DIVIDER_c then
divcnt_s <= (others => '0');
rxclk16_s <= '1';
else
rxclk16_s <= '0';
divcnt_s <= divcnt_s + '1';
end if;
end if;
end process;
rxenable <= rxclk16_s;
------------------------------------------------------------------------------
-- divider by 16
-- rxclk16/16=txclk
------------------------------------------------------------------------------
process (CLOCK_40MHZ,resetn)
begin
if (resetn='0') then
divtx_s <= (others => '0');
elsif (rising_edge(CLOCK_40MHZ)) then
if rxclk16_s='1' then
divtx_s <= divtx_s + '1';
if divtx_s="0000" then
txenable <= '1';
end if;
else
txenable <= '0';
end if;
end if;
end process;
assert not ((NOW > 0 ns) and cpuerror='1') report "**** CPU Error flag asserted ****" severity error;
------------------------------------------------------------------------------
-- UART Monitor
-- Display string on console after 80 characters or when CR character is received
------------------------------------------------------------------------------
process (rdrf,resetn)
variable L : line;
variable i_v : integer;
begin
if resetn='0' then
i_v := 0; -- clear character counter
elsif (rising_edge(rdrf)) then -- possible, pulse is wide!
if i_v=0 then
write(L,string'("RD UART : "));
if (udbus/=X"0D" and udbus/=X"0A") then
write(L,std_to_char(udbus));
end if;
i_v := i_v+1;
elsif (i_v=80 or udbus=X"0D") then
writeline(output,L);
i_v:=0;
else
if (udbus/=X"0D" and udbus/=X"0A") then
write(L,std_to_char(udbus));
end if;
i_v := i_v+1;
end if;
end if;
end process;
process (CLOCK_40MHZ,resetn) -- First/Second delay
begin
if (resetn='0') then
dind1_s <= '0';
dind2_s <= '0';
elsif (rising_edge(CLOCK_40MHZ)) then
dind1_s <= rdrf;
dind2_s <= dind1_s;
end if;
end process;
rdn_s <= '0' when (dind1_s='1' and dind2_s='0') else '1';
------------------------------------------------------------------------------
-- Top Level CPU+RAM+UART
------------------------------------------------------------------------------
U_0 : drigmorn1_top
PORT MAP (
CLOCK_40MHZ => CLOCK_40MHZ,
CTS => CTS,
PIN3 => resetn,
PIN4 => OPEN,
RXD => txcmd,
RTS => OPEN,
TXD => TXD,
LED1 => cpuerror,
led2n => OPEN,
led3n => OPEN
);
------------------------------------------------------------------------------
-- TX Uart
------------------------------------------------------------------------------
U_1 : uarttx
port map (
clk => CLOCK_40MHZ,
enable => txenable,
resetn => resetn,
dbus => char_s,
tdre => tdre_s,
wrn => wrn_s,
tx => txcmd
);
------------------------------------------------------------------------------
-- RX Uart
------------------------------------------------------------------------------
U_2 : uartrx
PORT MAP (
clk => CLOCK_40MHZ,
enable => rxenable,
resetn => resetn,
dbus => udbus,
rdn => rdn_s,
rdrf => rdrf,
ferror => OPEN,
rx => TXD
);
END struct;
| gpl-2.0 | 9c7cc5376b3e07cfac0e4a0483056cfa | 0.363651 | 5.032636 | false | false | false | false |
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