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nulldozer/purisc
|
Global_memory/MAGIC_global/ROUTE_global.vhd
| 2 | 13,554 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ROUTE_global is
PORT(
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
hazard : IN STD_LOGIC;
hazard_advanced : IN STD_LOGIC;
ram_0_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_0_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_1_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_1_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_2_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_2_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_3_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_3_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_4_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_4_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_5_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_5_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_6_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_6_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_7_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_7_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_0_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_1_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_2_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_3_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_4_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_5_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_6_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
ram_7_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0);
OUTPUT_A : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
OUTPUT_B : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
OUTPUT_C : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
OUTPUT_0 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
OUTPUT_1 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end;
architecture control of ROUTE_global is
--******************************************PROTOTYPE FOR REFERENCE************************************************
-- RAM 0 -----> ram_0_sel_vector = A0 A1 B0 B1 C0 C1 D0 D1 E0 E1
-- RAM 1 -----> ram_1_sel_vector = A0 A1 B0 B1 C0 C1 D0 D1 E0 E1
-- RAM 2 -----> ram_2_sel_vector = A0 A1 B0 B1 C0 C1 D0 D1 E0 E1
-- RAM 3 -----> ram_3_sel_vector = A0 A1 B0 B1 C0 C1 D0 D1 E0 E1
-- RAM 4 -----> ram_4_sel_vector = A0 A1 B0 B1 C0 C1 D0 D1 E0 E1
-- RAM 5 -----> ram_5_sel_vector = A0 A1 B0 B1 C0 C1 D0 D1 E0 E1
-- RAM 6 -----> ram_6_sel_vector = A0 A1 B0 B1 C0 C1 D0 D1 E0 E1
-- RAM 7 -----> ram_7_sel_vector = A0 A1 B0 B1 C0 C1 D0 D1 E0 E1
component ROUTE_SIGNAL_global
PORT(
ram_0_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_0_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_1_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_1_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_2_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_2_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_3_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_3_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_4_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_4_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_5_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_5_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_6_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_6_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_7_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ram_7_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
select_vector : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
hazard : IN STD_LOGIC;
hazard_advanced : IN STD_LOGIC;
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
OUTPUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal select_a : std_logic_vector (15 downto 0);
signal select_b : std_logic_vector (15 downto 0);
signal select_c : std_logic_vector (15 downto 0);
signal select_0 : std_logic_vector (15 downto 0);
signal select_1 : std_logic_vector (15 downto 0);
signal select_a_1hot : std_logic_vector (15 downto 0);
signal select_b_1hot : std_logic_vector (15 downto 0);
signal select_c_1hot : std_logic_vector (15 downto 0);
signal select_0_1hot : std_logic_vector (15 downto 0);
signal select_1_1hot : std_logic_vector (15 downto 0);
begin
select_a <= ram_0_sel_vector(9 downto 8) & ram_1_sel_vector(9 downto 8) &
ram_2_sel_vector(9 downto 8) & ram_3_sel_vector(9 downto 8) &
ram_4_sel_vector(9 downto 8) & ram_5_sel_vector(9 downto 8) &
ram_6_sel_vector(9 downto 8) & ram_7_sel_vector(9 downto 8);
select_b <= ram_0_sel_vector(7 downto 6) & ram_1_sel_vector(7 downto 6) &
ram_2_sel_vector(7 downto 6) & ram_3_sel_vector(7 downto 6) &
ram_4_sel_vector(7 downto 6) & ram_5_sel_vector(7 downto 6) &
ram_6_sel_vector(7 downto 6) & ram_7_sel_vector(7 downto 6);
select_c <= ram_0_sel_vector(5 downto 4) & ram_1_sel_vector(5 downto 4) &
ram_2_sel_vector(5 downto 4) & ram_3_sel_vector(5 downto 4) &
ram_4_sel_vector(5 downto 4) & ram_5_sel_vector(5 downto 4) &
ram_6_sel_vector(5 downto 4) & ram_7_sel_vector(5 downto 4);
select_0 <= ram_0_sel_vector(3 downto 2) & ram_1_sel_vector(3 downto 2) &
ram_2_sel_vector(3 downto 2) & ram_3_sel_vector(3 downto 2) &
ram_4_sel_vector(3 downto 2) & ram_5_sel_vector(3 downto 2) &
ram_6_sel_vector(3 downto 2) & ram_7_sel_vector(3 downto 2);
select_1 <= ram_0_sel_vector(1 downto 0) & ram_1_sel_vector(1 downto 0) &
ram_2_sel_vector(1 downto 0) & ram_3_sel_vector(1 downto 0) &
ram_4_sel_vector(1 downto 0) & ram_5_sel_vector(1 downto 0) &
ram_6_sel_vector(1 downto 0) & ram_7_sel_vector(1 downto 0);
select_a_1hot <= select_a(15) & (not(select_a(15) and select_a(14)) and select_a(14)) &
select_a(13) & (not(select_a(13) and select_a(12)) and select_a(12)) &
select_a(11) & (not(select_a(11) and select_a(10)) and select_a(10)) &
select_a(9) & (not(select_a(9) and select_a(8)) and select_a(8)) &
select_a(7) & (not(select_a(7) and select_a(6)) and select_a(6)) &
select_a(5) & (not(select_a(5) and select_a(4)) and select_a(4)) &
select_a(3) & (not(select_a(3) and select_a(2)) and select_a(2)) &
select_a(1) & (not(select_a(1) and select_a(0)) and select_a(0));
select_b_1hot <= select_b(15) & (not(select_b(15) and select_b(14)) and select_b(14)) &
select_b(13) & (not(select_b(13) and select_b(12)) and select_b(12)) &
select_b(11) & (not(select_b(11) and select_b(10)) and select_b(10)) &
select_b(9) & (not(select_b(9) and select_b(8)) and select_b(8)) &
select_b(7) & (not(select_b(7) and select_b(6)) and select_b(6)) &
select_b(5) & (not(select_b(5) and select_b(4)) and select_b(4)) &
select_b(3) & (not(select_b(3) and select_b(2)) and select_b(2)) &
select_b(1) & (not(select_b(1) and select_b(0)) and select_b(0));
select_c_1hot <= select_c(15) & (not(select_c(15) and select_c(14)) and select_c(14)) &
select_c(13) & (not(select_c(13) and select_c(12)) and select_c(12)) &
select_c(11) & (not(select_c(11) and select_c(10)) and select_c(10)) &
select_c(9) & (not(select_c(9) and select_c(8)) and select_c(8)) &
select_c(7) & (not(select_c(7) and select_c(6)) and select_c(6)) &
select_c(5) & (not(select_c(5) and select_c(4)) and select_c(4)) &
select_c(3) & (not(select_c(3) and select_c(2)) and select_c(2)) &
select_c(1) & (not(select_c(1) and select_c(0)) and select_c(0));
select_0_1hot <= select_0(15) & (not(select_0(15) and select_0(14)) and select_0(14)) &
select_0(13) & (not(select_0(13) and select_0(12)) and select_0(12)) &
select_0(11) & (not(select_0(11) and select_0(10)) and select_0(10)) &
select_0(9) & (not(select_0(9) and select_0(8)) and select_0(8)) &
select_0(7) & (not(select_0(7) and select_0(6)) and select_0(6)) &
select_0(5) & (not(select_0(5) and select_0(4)) and select_0(4)) &
select_0(3) & (not(select_0(3) and select_0(2)) and select_0(2)) &
select_0(1) & (not(select_0(1) and select_0(0)) and select_0(0));
select_1_1hot <= select_1(15) & (not(select_1(15) and select_1(14)) and select_1(14)) &
select_1(13) & (not(select_1(13) and select_1(12)) and select_1(12)) &
select_1(11) & (not(select_1(11) and select_1(10)) and select_1(10)) &
select_1(9) & (not(select_1(9) and select_1(8)) and select_1(8)) &
select_1(7) & (not(select_1(7) and select_1(6)) and select_1(6)) &
select_1(5) & (not(select_1(5) and select_1(4)) and select_1(4)) &
select_1(3) & (not(select_1(3) and select_1(2)) and select_1(2)) &
select_1(1) & (not(select_1(1) and select_1(0)) and select_1(0));
route_a : ROUTE_SIGNAL_global PORT MAP (
ram_0_out_a => ram_0_out_a,
ram_0_out_b => ram_0_out_b,
ram_1_out_a => ram_1_out_a,
ram_1_out_b => ram_1_out_b,
ram_2_out_a => ram_2_out_a,
ram_2_out_b => ram_2_out_b,
ram_3_out_a => ram_3_out_a,
ram_3_out_b => ram_3_out_b,
ram_4_out_a => ram_4_out_a,
ram_4_out_b => ram_4_out_b,
ram_5_out_a => ram_5_out_a,
ram_5_out_b => ram_5_out_b,
ram_6_out_a => ram_6_out_a,
ram_6_out_b => ram_6_out_b,
ram_7_out_a => ram_7_out_a,
ram_7_out_b => ram_7_out_b,
select_vector => select_a_1hot,
hazard => hazard,
hazard_advanced => hazard_advanced,
CLK => CLK,
RESET_n => RESET_n,
OUTPUT => OUTPUT_A
);
route_b : ROUTE_SIGNAL_global PORT MAP (
ram_0_out_a => ram_0_out_a,
ram_0_out_b => ram_0_out_b,
ram_1_out_a => ram_1_out_a,
ram_1_out_b => ram_1_out_b,
ram_2_out_a => ram_2_out_a,
ram_2_out_b => ram_2_out_b,
ram_3_out_a => ram_3_out_a,
ram_3_out_b => ram_3_out_b,
ram_4_out_a => ram_4_out_a,
ram_4_out_b => ram_4_out_b,
ram_5_out_a => ram_5_out_a,
ram_5_out_b => ram_5_out_b,
ram_6_out_a => ram_6_out_a,
ram_6_out_b => ram_6_out_b,
ram_7_out_a => ram_7_out_a,
ram_7_out_b => ram_7_out_b,
select_vector => select_b_1hot,
hazard => hazard,
hazard_advanced => hazard_advanced,
CLK => CLK,
RESET_n => RESET_n,
OUTPUT => OUTPUT_B
);
route_c : ROUTE_SIGNAL_global PORT MAP (
ram_0_out_a => ram_0_out_a,
ram_0_out_b => ram_0_out_b,
ram_1_out_a => ram_1_out_a,
ram_1_out_b => ram_1_out_b,
ram_2_out_a => ram_2_out_a,
ram_2_out_b => ram_2_out_b,
ram_3_out_a => ram_3_out_a,
ram_3_out_b => ram_3_out_b,
ram_4_out_a => ram_4_out_a,
ram_4_out_b => ram_4_out_b,
ram_5_out_a => ram_5_out_a,
ram_5_out_b => ram_5_out_b,
ram_6_out_a => ram_6_out_a,
ram_6_out_b => ram_6_out_b,
ram_7_out_a => ram_7_out_a,
ram_7_out_b => ram_7_out_b,
select_vector => select_c_1hot,
hazard => hazard,
hazard_advanced => hazard_advanced,
CLK => CLK,
RESET_n => RESET_n,
OUTPUT => OUTPUT_C
);
route_0 : ROUTE_SIGNAL_global PORT MAP (
ram_0_out_a => ram_0_out_a,
ram_0_out_b => ram_0_out_b,
ram_1_out_a => ram_1_out_a,
ram_1_out_b => ram_1_out_b,
ram_2_out_a => ram_2_out_a,
ram_2_out_b => ram_2_out_b,
ram_3_out_a => ram_3_out_a,
ram_3_out_b => ram_3_out_b,
ram_4_out_a => ram_4_out_a,
ram_4_out_b => ram_4_out_b,
ram_5_out_a => ram_5_out_a,
ram_5_out_b => ram_5_out_b,
ram_6_out_a => ram_6_out_a,
ram_6_out_b => ram_6_out_b,
ram_7_out_a => ram_7_out_a,
ram_7_out_b => ram_7_out_b,
select_vector => select_0_1hot,
hazard => hazard,
hazard_advanced => hazard_advanced,
CLK => CLK,
RESET_n => RESET_n,
OUTPUT => OUTPUT_0
);
route_1 : ROUTE_SIGNAL_global PORT MAP (
ram_0_out_a => ram_0_out_a,
ram_0_out_b => ram_0_out_b,
ram_1_out_a => ram_1_out_a,
ram_1_out_b => ram_1_out_b,
ram_2_out_a => ram_2_out_a,
ram_2_out_b => ram_2_out_b,
ram_3_out_a => ram_3_out_a,
ram_3_out_b => ram_3_out_b,
ram_4_out_a => ram_4_out_a,
ram_4_out_b => ram_4_out_b,
ram_5_out_a => ram_5_out_a,
ram_5_out_b => ram_5_out_b,
ram_6_out_a => ram_6_out_a,
ram_6_out_b => ram_6_out_b,
ram_7_out_a => ram_7_out_a,
ram_7_out_b => ram_7_out_b,
select_vector => select_1_1hot,
hazard => hazard,
hazard_advanced => hazard_advanced,
CLK => CLK,
RESET_n => RESET_n,
OUTPUT => OUTPUT_1
);
end;
|
gpl-2.0
|
d0550a7a9567d58611cf688ce6a3ea57
| 0.524864 | 2.560257 | false | false | false | false |
bobxiv/DispositivosLogicosProgramables-FICH
|
Practica/segmentos.vhd
| 1 | 3,260 |
--------------------------------------------------------------------------------
-- Company: Universidad de Valencia
-- Engineer: Alfredo Rosado
--
-- Create Date: 12:28:58 10/14/06
-- Design Name:
-- Module Name: segmentos - Behavioral
-- Project Name: Practica 1 de lab DCSE. Ingenieria Electronica.
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity segmentos is
Port ( Reloj : in std_logic;
Reset : in std_logic;
interruptor : in std_logic_vector(3 downto 0);
abcdefgdp : out std_logic_vector(7 downto 0);
anodos : buffer std_logic_vector(3 downto 0));
end segmentos;
architecture Behavioral of segmentos is
signal relojint : std_logic:='0';
signal a, b, c, d, valor_disp : std_logic_vector (3 downto 0):="0000";
signal contador_anodo : std_logic_vector(1 downto 0):= "00";
signal contador : integer:=0;
component sieteseg is port (
bin_u: in std_logic_vector (3 downto 0);
bcd_u: out std_logic_vector (7 downto 0)
);
end component;
begin
p1: process (reloj)
begin
if rising_edge(reloj) then
if contador < 200000 then
contador <= contador + 1;
elsif contador = 200000 then
contador <= 0;
relojint <= not relojint;
end if;
end if;
end process;
p2: process (reset, relojint)
begin
if reset = '1' then
contador_anodo <= (others => '0');
elsif rising_edge(relojint) then
if contador_anodo < 3 then
contador_anodo <= contador_anodo + 1;
else contador_anodo <= (others => '0');
end if;
end if;
end process;
pa: process (reset,interruptor(0))
begin
if reset = '1' then
a <= "0000";
elsif rising_edge(interruptor(0)) then
if a < 9 then
a <= a +1;
else a <= (others => '0');
end if;
end if;
end process;
pb: process (reset, interruptor(1))
begin
if reset = '1' then
b <= "0001";
elsif rising_edge(interruptor(1)) then
if b < 9 then
b <= b +1;
else b <= (others => '0');
end if;
end if;
end process;
pc: process (reset,interruptor(2))
begin
if reset = '1' then
c <= "0010";
elsif rising_edge(interruptor(2)) then
if c < 9 then
c <= c +1;
else c <= (others => '0');
end if;
end if;
end process;
pd: process (reset,interruptor(3))
begin
if reset = '1' then
d <= "0011";
elsif rising_edge(interruptor(3)) then
if d < 9 then
d <= d +1;
else d <= (others => '0');
end if;
end if;
end process;
with contador_anodo select
valor_disp <= a when "00",
b when "01",
c when "10",
d when "11",
(others=>'0') when others;
with contador_anodo select
anodos <="0111" when "00",
"1011" when "01",
"1101" when "10",
"1110" when "11",
(others=>'0') when others;
conversora: sieteseg port map (valor_disp,abcdefgdp);
end Behavioral;
|
gpl-3.0
|
4b308c37e9b162dc317d85ec097b052c
| 0.58865 | 3.289606 | false | false | false | false |
michaelmiehling/A25_VME_TB
|
16x004-01_src/Source/pcie_sim.vhd
| 1 | 103,031 |
--------------------------------------------------------------------------------
-- Title : PCIe simulation model
-- Project : -
--------------------------------------------------------------------------------
-- File : pcie_sim.vhd
-- Author : Susanne Reinfelder
-- Email : [email protected]
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 2017-05-26
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6
-- Synthesis : -
--------------------------------------------------------------------------------
-- Description :
-- PCIe simulation model for x1, x2, x4 and x8 configurations.
-- The BFM shared memory is configured to be 2 MBytes. It is mapped into
-- the first 2 MBytes of I/O space and also the first 2 MBytes of memory
-- space. The BFM is assigned to device number 0 on internal bus number 0.
--------------------------------------------------------------------------------
-- Hierarchy :
--------------------------------------------------------------------------------
-- Copyright (C) 2017, MEN Mikro Elektronik Nuremberg GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.altpcietb_bfm_constants.all;
use work.altpcietb_bfm_log.all;
use work.altpcietb_bfm_shmem.all;
use work.altpcietb_bfm_rdwr.all;
use work.altpcietb_bfm_configure.all;
use work.utils_pkg.all;
use work.pcie_sim_pkg.all;
use work.print_pkg.all;
use work.terminal_pkg.all;
entity pcie_sim is
generic(
BFM_LANE_WIDTH : integer range 8 downto 0 := 1 -- set configuration: 1=x1, 2=x2, 4=x4 and 8=x8
);
port(
rst_i : in std_logic;
pcie_rstn_i : in std_logic;
clk_i : in std_logic;
ep_clk250_i : in std_logic; -- endpoint SERDES 250MHz clk output
ep_clk500_i : in std_logic; -- endpoint SERDES 500MHz clk output
-- PCIe lanes
bfm_tx_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0);
bfm_rx_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0);
-- PCIe SERDES connection, in/out references are BFM view
ep_rate_ext_i : in std_logic; -- endpoint rate_ext
ep_powerdown_ext_i : in std_logic_vector(2*BFM_LANE_WIDTH -1 downto 0); -- 2bits per lane, [1:0]=lane0, [3:2]=lane1 etc.
ep_txdatak_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txdata_i : in std_logic_vector(8*BFM_LANE_WIDTH -1 downto 0); -- 8bits per lane, [7:0]=lane0, [15:8]=lane1 etc.
ep_txcompl_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txelecidle_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txdetectrx_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_rxpolarity_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_ltssm_i : in std_logic_vector(4 downto 0);
ep_rxvalid_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_rxstatus_o : out std_logic_vector(3*BFM_LANE_WIDTH -1 downto 0); -- 3bits per lane, [2:0]=lane0, [5:3]=lane1 etc.
ep_rxdatak_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bits per lane, [0]=lane0, [1]=lane1 etc.
ep_rxdata_o : out std_logic_vector(8*BFM_LANE_WIDTH -1 downto 0); -- 8bits per lane, [7:0]=lane0, [15:8]=lane1 etc.
ep_rxelecidle_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_phystatus_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
-- MEN terminal connection, in/out references are terminal view
term_out : in terminal_out_type;
term_in : out terminal_in_type
);
end entity pcie_sim;
architecture pcie_sim_arch of pcie_sim is
type bar_addr_array is array (5 downto 0) of std_logic_vector(31 downto 0);
type bar_limit_array is array (5 downto 0) of natural;
-- +----------------------------------------------------------------------------
-- | components
-- +----------------------------------------------------------------------------
component altpcietb_bfm_rp_top_x8_pipen1b is
port(
signal rxdata4_ext : in std_logic_vector(7 downto 0);
signal rx_in7 : in std_logic;
signal phystatus5_ext : in std_logic;
signal rxdata5_ext : in std_logic_vector(7 downto 0);
signal phystatus1_ext : in std_logic;
signal pipe_mode : in std_logic;
signal rxstatus3_ext : in std_logic_vector(2 downto 0);
signal pcie_rstn : in std_logic;
signal rxelecidle7_ext : in std_logic;
signal rxelecidle0_ext : in std_logic;
signal clk500_in : in std_logic;
signal rxelecidle3_ext : in std_logic;
signal rxdatak1_ext : in std_logic;
signal phystatus0_ext : in std_logic;
signal rx_in0 : in std_logic;
signal rx_in5 : in std_logic;
signal rxelecidle5_ext : in std_logic;
signal rxvalid1_ext : in std_logic;
signal rx_in2 : in std_logic;
signal rx_in3 : in std_logic;
signal rxdatak3_ext : in std_logic;
signal clk250_in : in std_logic;
signal phystatus6_ext : in std_logic;
signal rxdata6_ext : in std_logic_vector(7 downto 0);
signal rxdata3_ext : in std_logic_vector(7 downto 0);
signal rxstatus5_ext : in std_logic_vector(2 downto 0);
signal rxstatus1_ext : in std_logic_vector(2 downto 0);
signal rxdata0_ext : in std_logic_vector(7 downto 0);
signal rxvalid7_ext : in std_logic;
signal phystatus7_ext : in std_logic;
signal rxdata2_ext : in std_logic_vector(7 downto 0);
signal rxvalid5_ext : in std_logic;
signal rxvalid0_ext : in std_logic;
signal rxdatak2_ext : in std_logic;
signal rxstatus4_ext : in std_logic_vector(2 downto 0);
signal rxdatak7_ext : in std_logic;
signal rxstatus0_ext : in std_logic_vector(2 downto 0);
signal phystatus3_ext : in std_logic;
signal rxelecidle4_ext : in std_logic;
signal phystatus2_ext : in std_logic;
signal rxvalid4_ext : in std_logic;
signal rx_in6 : in std_logic;
signal rx_in1 : in std_logic;
signal rxstatus2_ext : in std_logic_vector(2 downto 0);
signal rxdata7_ext : in std_logic_vector(7 downto 0);
signal rxdatak0_ext : in std_logic;
signal rxelecidle1_ext : in std_logic;
signal rxdata1_ext : in std_logic_vector(7 downto 0);
signal rxstatus6_ext : in std_logic_vector(2 downto 0);
signal test_in : in std_logic_vector(31 downto 0);
signal rx_in4 : in std_logic;
signal rxdatak4_ext : in std_logic;
signal rxelecidle2_ext : in std_logic;
signal rxdatak5_ext : in std_logic;
signal rxstatus7_ext : in std_logic_vector(2 downto 0);
signal rxelecidle6_ext : in std_logic;
signal rxvalid3_ext : in std_logic;
signal rxvalid2_ext : in std_logic;
signal phystatus4_ext : in std_logic;
signal rxvalid6_ext : in std_logic;
signal local_rstn : in std_logic;
signal rxdatak6_ext : in std_logic;
signal tx_out6 : out std_logic;
signal tx_out4 : out std_logic;
signal txdatak4_ext : out std_logic;
signal txelecidle0_ext : out std_logic;
signal txdatak1_ext : out std_logic;
signal test_out : out std_logic_vector(511 downto 0);
signal txelecidle2_ext : out std_logic;
signal txdatak7_ext : out std_logic;
signal txdatak2_ext : out std_logic;
signal txcompl4_ext : out std_logic;
signal rxpolarity5_ext : out std_logic;
signal rxpolarity4_ext : out std_logic;
signal powerdown7_ext : out std_logic_vector(1 downto 0);
signal txdetectrx7_ext : out std_logic;
signal txelecidle1_ext : out std_logic;
signal tx_out3 : out std_logic;
signal rxpolarity3_ext : out std_logic;
signal txdata0_ext : out std_logic_vector(7 downto 0);
signal txdetectrx1_ext : out std_logic;
signal powerdown0_ext : out std_logic_vector(1 downto 0);
signal txdata1_ext : out std_logic_vector(7 downto 0);
signal txdatak6_ext : out std_logic;
signal txdata3_ext : out std_logic_vector(7 downto 0);
signal txcompl7_ext : out std_logic;
signal txdata4_ext : out std_logic_vector(7 downto 0);
signal powerdown3_ext : out std_logic_vector(1 downto 0);
signal txcompl5_ext : out std_logic;
signal txcompl0_ext : out std_logic;
signal txdetectrx5_ext : out std_logic;
signal txcompl1_ext : out std_logic;
signal powerdown1_ext : out std_logic_vector(1 downto 0);
signal txelecidle7_ext : out std_logic;
signal swdn_out : out std_logic_vector(5 downto 0);
signal txelecidle6_ext : out std_logic;
signal tx_out0 : out std_logic;
signal powerdown6_ext : out std_logic_vector(1 downto 0);
signal rxpolarity0_ext : out std_logic;
signal tx_out2 : out std_logic;
signal txdetectrx2_ext : out std_logic;
signal txdata5_ext : out std_logic_vector(7 downto 0);
signal txelecidle3_ext : out std_logic;
signal txdatak3_ext : out std_logic;
signal txdetectrx0_ext : out std_logic;
signal rxpolarity6_ext : out std_logic;
signal powerdown2_ext : out std_logic_vector(1 downto 0);
signal rate_ext : out std_logic;
signal txcompl3_ext : out std_logic;
signal txdetectrx6_ext : out std_logic;
signal tx_out5 : out std_logic;
signal rxpolarity2_ext : out std_logic;
signal tx_out7 : out std_logic;
signal tx_out1 : out std_logic;
signal txdetectrx3_ext : out std_logic;
signal txdata6_ext : out std_logic_vector(7 downto 0);
signal txcompl2_ext : out std_logic;
signal rxpolarity1_ext : out std_logic;
signal txelecidle4_ext : out std_logic;
signal txdata2_ext : out std_logic_vector(7 downto 0);
signal powerdown4_ext : out std_logic_vector(1 downto 0);
signal txcompl6_ext : out std_logic;
signal txdatak5_ext : out std_logic;
signal txdata7_ext : out std_logic_vector(7 downto 0);
signal txdatak0_ext : out std_logic;
signal rxpolarity7_ext : out std_logic;
signal powerdown5_ext : out std_logic_vector(1 downto 0);
signal txdetectrx4_ext : out std_logic;
signal txelecidle5_ext : out std_logic
);
end component altpcietb_bfm_rp_top_x8_pipen1b;
component altpcietb_pipe_phy is
generic(
APIPE_WIDTH : natural;
BPIPE_WIDTH : natural;
LANE_NUM : natural
);
port(
signal b_powerdown : in std_logic_vector(1 downto 0);
signal a_txdatak : in std_logic_vector(0 downto 0);
signal pipe_mode : in std_logic;
signal a_powerdown : in std_logic_vector(1 downto 0);
signal b_txcompl : in std_logic;
signal b_lane_conn : in std_logic;
signal b_txdetectrx : in std_logic;
signal pclk_a : in std_logic;
signal b_txelecidle : in std_logic;
signal a_lane_conn : in std_logic;
signal resetn : in std_logic;
signal a_txdata : in std_logic_vector(7 downto 0);
signal b_rate : in std_logic;
signal a_txcompl : in std_logic;
signal pclk_b : in std_logic;
signal a_txelecidle : in std_logic;
signal a_txdetectrx : in std_logic;
signal a_rxpolarity : in std_logic;
signal b_txdata : in std_logic_vector(7 downto 0);
signal b_rxpolarity : in std_logic;
signal b_txdatak : in std_logic_vector(0 downto 0);
signal a_rate : in std_logic;
signal a_rxvalid : out std_logic;
signal a_rxstatus : out std_logic_vector(2 downto 0);
signal b_phystatus : out std_logic;
signal b_rxvalid : out std_logic;
signal a_rxdatak : out std_logic_vector(0 downto 0);
signal b_rxelecidle : out std_logic;
signal b_rxdatak : out std_logic_vector(0 downto 0);
signal a_rxdata : out std_logic_vector(7 downto 0);
signal b_rxdata : out std_logic_vector(7 downto 0);
signal a_rxelecidle : out std_logic;
signal a_phystatus : out std_logic;
signal b_rxstatus : out std_logic_vector(2 downto 0)
);
end component altpcietb_pipe_phy;
component altpcietb_ltssm_mon is
port(
signal rp_clk : in std_logic;
signal ep_ltssm : in std_logic_vector (4 downto 0);
signal rstn : in std_logic;
signal rp_ltssm : in std_logic_vector (4 downto 0);
signal dummy_out : out std_logic
);
end component altpcietb_ltssm_mon;
-- +----------------------------------------------------------------------------
-- | functions
-- +----------------------------------------------------------------------------
function get_bar_limit(bar_addr : std_logic_vector(31 downto 0); bar_num : natural)
return natural is
variable var_log2_size : natural;
variable var_is_mem : std_logic;
variable var_is_pref : std_logic;
variable var_is_64b : std_logic;
begin
ebfm_cfg_decode_bar(
bar_table => BAR_TABLE_POINTER,
bar_num => bar_num,
log2_size => var_log2_size,
is_mem => var_is_mem,
is_pref => var_is_pref,
is_64b => var_is_64b
);
return var_log2_size;
end function get_bar_limit;
-- +----------------------------------------------------------------------------
-- | procedures
-- +----------------------------------------------------------------------------
procedure get_pcie_addr_and_offset(
pcie_addr : in std_logic_vector(31 downto 0);
bar_addr : in bar_addr_array;
bar_limit : in bar_limit_array;
bar_num : out natural;
bar_offset : out natural
) is
variable var_act_limit : natural := 0;
variable var_act_addr : std_logic_vector(31 downto 0) := (others => '0');
variable var_act_offset : std_logic_vector(31 downto 0) := (others => '0');
variable var_bar_num : natural := 6;
begin
-- loop through all BARs and check for matches
-- address must match from MSB of address to actual limit value
-- address offset for BAR is from limit downto 0
loop_1 : for i in 0 to 5 loop
var_act_limit := bar_limit(i);
var_act_offset := ZERO_32BIT(31 downto var_act_limit) & pcie_addr(var_act_limit -1 downto 0);
var_act_addr := pcie_addr(31 downto var_act_limit) & ZERO_32BIT(var_act_limit -1 downto 0);
if bar_addr(i) = var_act_addr then
var_bar_num := i;
exit loop_1;
else
-- set to invalid value to denote error condition
var_bar_num := 6;
end if;
end loop;
if var_bar_num = 6 then
report "ERROR (pcie_sim.vhd->get_pcie_addr_and_offset(): given PCIe address does not match stored BAR addresses" severity error;
else
bar_num := var_bar_num;
bar_offset := to_integer(unsigned(var_act_offset));
end if;
end procedure get_pcie_addr_and_offset;
-- +----------------------------------------------------------------------------
-- | constants
-- +----------------------------------------------------------------------------
-- +----------------------------------------------------------------------------
-- | internal signals
-- +----------------------------------------------------------------------------
-- BFM connections
signal bfm_rate_int : std_logic;
signal bfm_pipe_mode_int : std_logic;
signal bfm_pclk_int : std_logic;
signal lane_pclk_int : std_logic;
signal bfm_rstn_delayed : std_logic := '0';
signal bfm_txcompl_0_int : std_logic;
signal bfm_txcompl_1_int : std_logic;
signal bfm_txcompl_2_int : std_logic;
signal bfm_txcompl_3_int : std_logic;
signal bfm_txcompl_4_int : std_logic;
signal bfm_txcompl_5_int : std_logic;
signal bfm_txcompl_6_int : std_logic;
signal bfm_txcompl_7_int : std_logic;
signal bfm_txdetectrx_0_int : std_logic;
signal bfm_txdetectrx_1_int : std_logic;
signal bfm_txdetectrx_2_int : std_logic;
signal bfm_txdetectrx_3_int : std_logic;
signal bfm_txdetectrx_4_int : std_logic;
signal bfm_txdetectrx_5_int : std_logic;
signal bfm_txdetectrx_6_int : std_logic;
signal bfm_txdetectrx_7_int : std_logic;
signal bfm_txelecidle_0_int : std_logic;
signal bfm_txelecidle_1_int : std_logic;
signal bfm_txelecidle_2_int : std_logic;
signal bfm_txelecidle_3_int : std_logic;
signal bfm_txelecidle_4_int : std_logic;
signal bfm_txelecidle_5_int : std_logic;
signal bfm_txelecidle_6_int : std_logic;
signal bfm_txelecidle_7_int : std_logic;
signal bfm_rxpolarity_0_int : std_logic;
signal bfm_rxpolarity_1_int : std_logic;
signal bfm_rxpolarity_2_int : std_logic;
signal bfm_rxpolarity_3_int : std_logic;
signal bfm_rxpolarity_4_int : std_logic;
signal bfm_rxpolarity_5_int : std_logic;
signal bfm_rxpolarity_6_int : std_logic;
signal bfm_rxpolarity_7_int : std_logic;
signal bfm_phystatus_0_int : std_logic;
signal bfm_phystatus_1_int : std_logic;
signal bfm_phystatus_2_int : std_logic;
signal bfm_phystatus_3_int : std_logic;
signal bfm_phystatus_4_int : std_logic;
signal bfm_phystatus_5_int : std_logic;
signal bfm_phystatus_6_int : std_logic;
signal bfm_phystatus_7_int : std_logic;
signal bfm_rxvalid_0_int : std_logic;
signal bfm_rxvalid_1_int : std_logic;
signal bfm_rxvalid_2_int : std_logic;
signal bfm_rxvalid_3_int : std_logic;
signal bfm_rxvalid_4_int : std_logic;
signal bfm_rxvalid_5_int : std_logic;
signal bfm_rxvalid_6_int : std_logic;
signal bfm_rxvalid_7_int : std_logic;
signal bfm_rxelecidle_0_int : std_logic;
signal bfm_rxelecidle_1_int : std_logic;
signal bfm_rxelecidle_2_int : std_logic;
signal bfm_rxelecidle_3_int : std_logic;
signal bfm_rxelecidle_4_int : std_logic;
signal bfm_rxelecidle_5_int : std_logic;
signal bfm_rxelecidle_6_int : std_logic;
signal bfm_rxelecidle_7_int : std_logic;
signal bfm_rxdatak_0_int : std_logic;
signal bfm_rxdatak_1_int : std_logic;
signal bfm_rxdatak_2_int : std_logic;
signal bfm_rxdatak_3_int : std_logic;
signal bfm_rxdatak_4_int : std_logic;
signal bfm_rxdatak_5_int : std_logic;
signal bfm_rxdatak_6_int : std_logic;
signal bfm_rxdatak_7_int : std_logic;
signal bfm_rx_int : std_logic_vector(7 downto 0) := (others => '1');
signal bfm_tx_int : std_logic_vector(7 downto 0) := (others => 'Z');
signal bfm_test_in_int : std_logic_vector(31 downto 0);
signal bfm_irq_int : std_logic_vector(5 downto 0);
signal bfm_ltssm_rp : std_logic_vector(4 downto 0);
signal test_out_int : std_logic_vector(511 downto 0);
signal bfm_txdata_0_int : std_logic_vector(7 downto 0);
signal bfm_txdata_1_int : std_logic_vector(7 downto 0);
signal bfm_txdata_2_int : std_logic_vector(7 downto 0);
signal bfm_txdata_3_int : std_logic_vector(7 downto 0);
signal bfm_txdata_4_int : std_logic_vector(7 downto 0);
signal bfm_txdata_5_int : std_logic_vector(7 downto 0);
signal bfm_txdata_6_int : std_logic_vector(7 downto 0);
signal bfm_txdata_7_int : std_logic_vector(7 downto 0);
signal bfm_txdatak_0_int : std_logic_vector(0 downto 0);
signal bfm_txdatak_1_int : std_logic_vector(0 downto 0);
signal bfm_txdatak_2_int : std_logic_vector(0 downto 0);
signal bfm_txdatak_3_int : std_logic_vector(0 downto 0);
signal bfm_txdatak_4_int : std_logic_vector(0 downto 0);
signal bfm_txdatak_5_int : std_logic_vector(0 downto 0);
signal bfm_txdatak_6_int : std_logic_vector(0 downto 0);
signal bfm_txdatak_7_int : std_logic_vector(0 downto 0);
signal bfm_powerdown_0_int : std_logic_vector(1 downto 0);
signal bfm_powerdown_1_int : std_logic_vector(1 downto 0);
signal bfm_powerdown_2_int : std_logic_vector(1 downto 0);
signal bfm_powerdown_3_int : std_logic_vector(1 downto 0);
signal bfm_powerdown_4_int : std_logic_vector(1 downto 0);
signal bfm_powerdown_5_int : std_logic_vector(1 downto 0);
signal bfm_powerdown_6_int : std_logic_vector(1 downto 0);
signal bfm_powerdown_7_int : std_logic_vector(1 downto 0);
signal bfm_rxdata_0_int : std_logic_vector(7 downto 0);
signal bfm_rxdata_1_int : std_logic_vector(7 downto 0);
signal bfm_rxdata_2_int : std_logic_vector(7 downto 0);
signal bfm_rxdata_3_int : std_logic_vector(7 downto 0);
signal bfm_rxdata_4_int : std_logic_vector(7 downto 0);
signal bfm_rxdata_5_int : std_logic_vector(7 downto 0);
signal bfm_rxdata_6_int : std_logic_vector(7 downto 0);
signal bfm_rxdata_7_int : std_logic_vector(7 downto 0);
signal bfm_rxstatus_0_int : std_logic_vector(2 downto 0);
signal bfm_rxstatus_1_int : std_logic_vector(2 downto 0);
signal bfm_rxstatus_2_int : std_logic_vector(2 downto 0);
signal bfm_rxstatus_3_int : std_logic_vector(2 downto 0);
signal bfm_rxstatus_4_int : std_logic_vector(2 downto 0);
signal bfm_rxstatus_5_int : std_logic_vector(2 downto 0);
signal bfm_rxstatus_6_int : std_logic_vector(2 downto 0);
signal bfm_rxstatus_7_int : std_logic_vector(2 downto 0);
signal bar_addr : bar_addr_array;
signal bar_limit : bar_limit_array;
begin
-- +----------------------------------------------------------------------------
-- | concurrent section
-- +----------------------------------------------------------------------------
assert (BFM_LANE_WIDTH = 1 or BFM_LANE_WIDTH = 2 or BFM_LANE_WIDTH = 4 or BFM_LANE_WIDTH = 8)
report "ERROR (pcie_sim.vhd): invalid value for generic BFM_LANE_WIDTH; use 1, 2, 4, or 8!" severity failure;
-- clock switch
bfm_pclk_int <= ep_clk500_i when bfm_rate_int = '1' else ep_clk250_i;
lane_pclk_int <= ep_clk500_i when ep_rate_ext_i = '1' else ep_clk250_i;
-- delay reset for BFM by 100 ns
bfm_rstn_delayed <= transport pcie_rstn_i after 100 ns;
bfm_pipe_mode_int <= '1';
bfm_test_in_int(31 downto 8) <= (others => '0');
bfm_test_in_int(7) <= not bfm_pipe_mode_int; -- disable entrance to low power mode
bfm_test_in_int(6) <= '0';
bfm_test_in_int(5) <= '1'; -- disable polling.compliance
bfm_test_in_int(4) <= '0';
bfm_test_in_int(3) <= not bfm_pipe_mode_int; -- forces all lanes to detect the receiver
bfm_test_in_int(2 downto 1) <= (others => '0');
bfm_test_in_int(0) <= '1'; -- speed up simulation by making counters faster than normal
bfm_ltssm_rp <= test_out_int(324 downto 320);
bfm_rx_o(BFM_LANE_WIDTH -1 downto 0) <= bfm_rx_int(BFM_LANE_WIDTH -1 downto 0);
bfm_tx_int(BFM_LANE_WIDTH -1 downto 0) <= bfm_tx_i(BFM_LANE_WIDTH -1 downto 0);
-- +----------------------------------------------------------------------------
-- | process section
-- +----------------------------------------------------------------------------
main : process
variable first_be_en : std_logic_vector(3 downto 0);
variable byte_count : integer;
variable addr32_int : std_logic_vector(31 downto 0);
variable bfm_id : integer := 0;
variable success_int : boolean := false;
variable return_data32 : std_logic_vector(31 downto 0) := (others => '0');
variable return_data_vec : dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
variable data_vec : dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
variable var_bar_num : natural;
variable var_bar_offset : natural;
variable var_bar0_addr : std_logic_vector(31 downto 0) := x"ffff_ffff";
variable var_bar1_addr : std_logic_vector(31 downto 0) := x"ffff_ffff";
variable var_bar2_addr : std_logic_vector(31 downto 0) := x"ffff_ffff";
variable var_bar3_addr : std_logic_vector(31 downto 0) := x"ffff_ffff";
variable var_bar4_addr : std_logic_vector(31 downto 0) := x"ffff_ffff";
variable var_bar5_addr : std_logic_vector(31 downto 0) := x"ffff_ffff";
variable var_bar0_limit : natural := 0;
variable var_bar1_limit : natural := 0;
variable var_bar2_limit : natural := 0;
variable var_bar3_limit : natural := 0;
variable var_bar4_limit : natural := 0;
variable var_bar5_limit : natural := 0;
begin
-- reset all
term_in.busy <= '1';
term_in.done <= true;
wait until rst_i = '0';
wait_clk(clk_i,1);
if term_out.start /= true then
wait until term_out.start = true;
end if;
loop
wait on term_out.start;
term_in.busy <= '1';
term_in.err <= 0;
success_int := false;
---------------------------
-- check for wrong values
---------------------------
assert term_out.typ <= 2 report "ERROR (pcie_sim): illegal value for signal term_out.typ" severity failure;
assert term_out.wr <= 2 report "ERROR (pcie_sim): illegal value for signal term_out.wr" severity failure;
if term_out.typ = 0 then
assert term_out.numb = 1 report "ERROR (pcie_sim): illegal combination for signals term_out.typ and term_out.numb => bytewise burst is impossible" severity failure;
end if;
if term_out.typ = 1 then
assert term_out.numb = 1 report "ERROR (pcie_sim): illegal combination for signals term_out.typ and term_out.numb => wordwise burst is impossible" severity failure;
end if;
assert term_out.numb <= 1024 report "ERROR (pcie_sim): maximum value for signal term_out.numb is 1024" severity failure;
----------------------------
-- set values for this run
----------------------------
addr32_int := term_out.adr(31 downto 2) & "00";
bfm_id := to_integer(unsigned(term_out.tga(3 downto 2)));
if term_out.typ = 0 then -- byte
byte_count := 1;
if term_out.adr(1 downto 0) = "01" then
first_be_en := "0010";
elsif term_out.adr(1 downto 0) = "10" then
first_be_en := "0100";
elsif term_out.adr(1 downto 0) = "11" then
first_be_en := "1000";
else
first_be_en := "0001";
end if;
elsif term_out.typ = 1 then -- word
byte_count := 2;
if term_out.adr(1) = '0' then
first_be_en := "0011";
else
first_be_en := "1100";
end if;
else -- long word
byte_count := term_out.numb *4;
first_be_en := x"F";
end if;
for i in 0 to term_out.numb -1 loop
data_vec(i) := std_logic_vector(unsigned(term_out.dat) + to_unsigned(i,32));
return_data_vec(i) := (others => '0');
wait for 0 ns;
end loop;
if term_out.wr = 0 then -- read
if term_out.tga(1 downto 0) = IO_TRANSFER then -- I/O
report "ERROR(pcie_sim): I/O transfer not supported" severity error;
elsif term_out.tga(1 downto 0) = MEM32_TRANSFER then -- memory
get_pcie_addr_and_offset(
pcie_addr => addr32_int,
bar_addr => bar_addr,
bar_limit => bar_limit,
bar_num => var_bar_num,
bar_offset => var_bar_offset
);
if term_out.numb = 1 then
bfm_rd_mem32(
bar_num => var_bar_num,
bar_offset => var_bar_offset,
byte_en => first_be_en,
ref_data32 => term_out.dat,
data32_out => return_data32,
success => success_int
);
else
bfm_rd_mem32(
bar_num => var_bar_num,
bar_offset => var_bar_offset,
byte_count => byte_count,
ref_data32 => data_vec,
data32_out => return_data_vec,
success => success_int
);
end if;
elsif term_out.tga(1 downto 0) = CONFIG_TRANSFER then -- configuration type 0
return_data32 := x"FADE_FADE";
bfm_rd_config(
byte_en => first_be_en,
pcie_addr => addr32_int(31 downto 2),
ref_data32 => term_out.dat,
data32_out => return_data32,
success => success_int
);
else
assert false report "ERROR (pcie_sim): term_out.tga(1 downto 0) = 11 is reserved for reads" severity failure;
end if;
elsif term_out.wr = 1 then -- write
if term_out.tga(1 downto 0) = IO_TRANSFER then -- I/O
report "ERROR(pcie_sim): I/O transfer not supported" severity error;
elsif term_out.tga(1 downto 0) = MEM32_TRANSFER then -- memory
get_pcie_addr_and_offset(
pcie_addr => term_out.adr,
bar_addr => bar_addr,
bar_limit => bar_limit,
bar_num => var_bar_num,
bar_offset => var_bar_offset
);
if term_out.numb = 1 then
bfm_wr_mem32(
pcie_addr => term_out.adr(1 downto 0),
bar_num => var_bar_num,
bar_offset => var_bar_offset,
byte_count => byte_count,
data32 => term_out.dat,
success => success_int
);
else
bfm_wr_mem32(
bar_num => var_bar_num,
bar_offset => var_bar_offset,
byte_count => byte_count,
data32 => data_vec,
success => success_int
);
end if;
elsif term_out.tga(1 downto 0) = CONFIG_TRANSFER then -- configuration type 0
bfm_wr_config(
byte_en => first_be_en,
pcie_addr => addr32_int(31 downto 2),
data32 => term_out.dat,
success => success_int
);
else
-- => term_out.tga(1 downto 0) = SETUP_CYCLE then -- BFM setup
if term_out.txt >= 2 then
print("pcie_sim.vhd: starting SETUP_CYCLE");
end if;
if term_out.adr(2 downto 0) = "000" then -- BAR0
var_bar0_addr := term_out.dat;
var_bar0_limit := get_bar_limit(bar_addr => var_bar0_addr, bar_num => 0);
bar_addr(0) <= var_bar0_addr;
bar_limit(0) <= var_bar0_limit;
success_int := true;
elsif term_out.adr(2 downto 0) = "001" then -- BAR1
var_bar1_addr := term_out.dat;
var_bar1_limit := get_bar_limit(bar_addr => var_bar1_addr, bar_num => 1);
bar_addr(1) <= var_bar1_addr;
bar_limit(1) <= var_bar1_limit;
success_int := true;
elsif term_out.adr(2 downto 0) = "010" then -- BAR2
var_bar2_addr := term_out.dat;
var_bar2_limit := get_bar_limit(bar_addr => var_bar2_addr, bar_num => 2);
bar_addr(2) <= var_bar2_addr;
bar_limit(2) <= var_bar2_limit;
success_int := true;
elsif term_out.adr(2 downto 0) = "011" then -- BAR3
var_bar3_addr := term_out.dat;
var_bar3_limit := get_bar_limit(bar_addr => var_bar3_addr, bar_num => 3);
bar_addr(3) <= var_bar3_addr;
bar_limit(3) <= var_bar3_limit;
success_int := true;
elsif term_out.adr(2 downto 0) = "100" then -- BAR4
var_bar4_addr := term_out.dat;
var_bar4_limit := get_bar_limit(bar_addr => var_bar4_addr, bar_num => 4);
bar_addr(4) <= var_bar4_addr;
bar_limit(4) <= var_bar4_limit;
success_int := true;
elsif term_out.adr(2 downto 0) = "101" then -- BAR5
var_bar5_addr := term_out.dat;
var_bar5_limit := get_bar_limit(bar_addr => var_bar5_addr, bar_num => 5);
bar_addr(5) <= var_bar5_addr;
bar_limit(5) <= var_bar5_limit;
success_int := true;
else
report "ERROR: pcie_sim.vhd: term_out.tga is set to SETUP_CYCLE but term_out.adr has an invalid value!" &
" Use values 000 to 101." severity error;
end if;
wait_clk(clk_i,1);
end if;
else -- wait
wait_clk(clk_i,term_out.numb);
end if;
--------------------------------------
-- return values and finish transfer
--------------------------------------
term_in.dat <= return_data32;
if success_int then
term_in.err <= 0;
else
term_in.err <= 1;
end if;
term_in.busy <= '0';
term_in.done <= term_out.start;
end loop;
end process main;
-- +----------------------------------------------------------------------------
-- | component instanciation section
-- +----------------------------------------------------------------------------
bfm_inst: altpcietb_bfm_rp_top_x8_pipen1b
port map(
pcie_rstn => bfm_rstn_delayed, --pcie_rstn_i,
local_rstn => '1',
clk250_in => ep_clk250_i,
clk500_in => ep_clk500_i,
pipe_mode => bfm_pipe_mode_int,
rxdata4_ext => bfm_rxdata_4_int,
rx_in7 => bfm_rx_int(7),
phystatus5_ext => bfm_phystatus_5_int,
rxdata5_ext => bfm_rxdata_5_int,
phystatus1_ext => bfm_phystatus_1_int,
rxstatus3_ext => bfm_rxstatus_3_int,
rxelecidle7_ext => bfm_rxelecidle_7_int,
rxelecidle0_ext => bfm_rxelecidle_0_int,
rxelecidle3_ext => bfm_rxelecidle_3_int,
rxdatak1_ext => bfm_rxdatak_1_int,
phystatus0_ext => bfm_phystatus_0_int,
rx_in0 => bfm_rx_int(0),
rx_in5 => bfm_rx_int(5),
rxelecidle5_ext => bfm_rxelecidle_5_int,
rxvalid1_ext => bfm_rxvalid_1_int,
rx_in2 => bfm_rx_int(2),
rx_in3 => bfm_rx_int(3),
rxdatak3_ext => bfm_rxdatak_3_int,
phystatus6_ext => bfm_phystatus_6_int,
rxdata6_ext => bfm_rxdata_6_int,
rxdata3_ext => bfm_rxdata_3_int,
rxstatus5_ext => bfm_rxstatus_5_int,
rxstatus1_ext => bfm_rxstatus_1_int,
rxdata0_ext => bfm_rxdata_0_int,
rxvalid7_ext => bfm_rxvalid_7_int,
phystatus7_ext => bfm_phystatus_7_int,
rxdata2_ext => bfm_rxdata_2_int,
rxvalid5_ext => bfm_rxvalid_5_int,
rxvalid0_ext => bfm_rxvalid_0_int,
rxdatak2_ext => bfm_rxdatak_2_int,
rxstatus4_ext => bfm_rxstatus_4_int,
rxdatak7_ext => bfm_rxdatak_7_int,
rxstatus0_ext => bfm_rxstatus_0_int,
phystatus3_ext => bfm_phystatus_3_int,
rxelecidle4_ext => bfm_rxelecidle_4_int,
phystatus2_ext => bfm_phystatus_2_int,
rxvalid4_ext => bfm_rxvalid_4_int,
rx_in6 => bfm_rx_int(6),
rx_in1 => bfm_rx_int(1),
rxstatus2_ext => bfm_rxstatus_2_int,
rxdata7_ext => bfm_rxdata_7_int,
rxdatak0_ext => bfm_rxdatak_0_int,
rxelecidle1_ext => bfm_rxelecidle_1_int,
rxdata1_ext => bfm_rxdata_1_int,
rxstatus6_ext => bfm_rxstatus_6_int,
test_in => bfm_test_in_int,
rx_in4 => bfm_rx_int(4),
rxdatak4_ext => bfm_rxdatak_4_int,
rxelecidle2_ext => bfm_rxelecidle_2_int,
rxdatak5_ext => bfm_rxdatak_5_int,
rxstatus7_ext => bfm_rxstatus_7_int,
rxelecidle6_ext => bfm_rxelecidle_6_int,
rxvalid3_ext => bfm_rxvalid_3_int,
rxvalid2_ext => bfm_rxvalid_2_int,
phystatus4_ext => bfm_phystatus_4_int,
rxvalid6_ext => bfm_rxvalid_6_int,
rxdatak6_ext => bfm_rxdatak_6_int,
tx_out6 => bfm_tx_int(6),
tx_out4 => bfm_tx_int(4),
txdatak4_ext => bfm_txdatak_4_int(0),
txelecidle0_ext => bfm_txelecidle_0_int,
txdatak1_ext => bfm_txdatak_1_int(0),
test_out => test_out_int,
txelecidle2_ext => bfm_txelecidle_2_int,
txdatak7_ext => bfm_txdatak_7_int(0),
txdatak2_ext => bfm_txdatak_2_int(0),
txcompl4_ext => bfm_txcompl_4_int,
rxpolarity5_ext => bfm_rxpolarity_5_int,
rxpolarity4_ext => bfm_rxpolarity_4_int,
powerdown7_ext => bfm_powerdown_7_int,
txdetectrx7_ext => bfm_txdetectrx_7_int,
txelecidle1_ext => bfm_txelecidle_1_int,
tx_out3 => bfm_tx_int(3),
rxpolarity3_ext => bfm_rxpolarity_3_int,
txdata0_ext => bfm_txdata_0_int,
txdetectrx1_ext => bfm_txdetectrx_1_int,
powerdown0_ext => bfm_powerdown_0_int,
txdata1_ext => bfm_txdata_1_int,
txdatak6_ext => bfm_txdatak_6_int(0),
txdata3_ext => bfm_txdata_3_int,
txcompl7_ext => bfm_txcompl_7_int,
txdata4_ext => bfm_txdata_4_int,
powerdown3_ext => bfm_powerdown_3_int,
txcompl5_ext => bfm_txcompl_5_int,
txcompl0_ext => bfm_txcompl_0_int,
txdetectrx5_ext => bfm_txdetectrx_5_int,
txcompl1_ext => bfm_txcompl_1_int,
powerdown1_ext => bfm_powerdown_1_int,
txelecidle7_ext => bfm_txelecidle_7_int,
swdn_out => bfm_irq_int,
txelecidle6_ext => bfm_txelecidle_6_int,
tx_out0 => bfm_tx_int(0),
powerdown6_ext => bfm_powerdown_6_int,
rxpolarity0_ext => bfm_rxpolarity_0_int,
tx_out2 => bfm_tx_int(2),
txdetectrx2_ext => bfm_txdetectrx_2_int,
txdata5_ext => bfm_txdata_5_int,
txelecidle3_ext => bfm_txelecidle_3_int,
txdatak3_ext => bfm_txdatak_3_int(0),
txdetectrx0_ext => bfm_txdetectrx_0_int,
rxpolarity6_ext => bfm_rxpolarity_6_int,
powerdown2_ext => bfm_powerdown_2_int,
rate_ext => bfm_rate_int,
txcompl3_ext => bfm_txcompl_3_int,
txdetectrx6_ext => bfm_txdetectrx_6_int,
tx_out5 => bfm_tx_int(5),
rxpolarity2_ext => bfm_rxpolarity_2_int,
tx_out7 => bfm_tx_int(7),
tx_out1 => bfm_tx_int(1),
txdetectrx3_ext => bfm_txdetectrx_3_int,
txdata6_ext => bfm_txdata_6_int,
txcompl2_ext => bfm_txcompl_2_int,
rxpolarity1_ext => bfm_rxpolarity_1_int,
txelecidle4_ext => bfm_txelecidle_4_int,
txdata2_ext => bfm_txdata_2_int,
powerdown4_ext => bfm_powerdown_4_int,
txcompl6_ext => bfm_txcompl_6_int,
txdatak5_ext => bfm_txdatak_5_int(0),
txdata7_ext => bfm_txdata_7_int,
txdatak0_ext => bfm_txdatak_0_int(0),
rxpolarity7_ext => bfm_rxpolarity_7_int,
powerdown5_ext => bfm_powerdown_5_int,
txdetectrx4_ext => bfm_txdetectrx_4_int,
txelecidle5_ext => bfm_txelecidle_5_int
);
----------------------
-- use LTSSM monitor
----------------------
ltssm_mon : altpcietb_ltssm_mon
port map(
ep_ltssm => ep_ltssm_i,
rp_clk => bfm_pclk_int,
rp_ltssm => bfm_ltssm_rp,
rstn => pcie_rstn_i,
dummy_out => open
);
------------------------
-- manage unused lanes
------------------------
--manage_lanes: if BFM_LANE_WIDTH = 1 generate
manage_x1_lanes: if BFM_LANE_WIDTH = 1 generate
-- x1 configuration, BFM connected with 1 lane, using dummy transceiver for lanes 2 to 8
x1_lane_0 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 0
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(1 downto 0),
a_txdatak(0) => ep_txdatak_i(0),
a_txdata => ep_txdata_i(7 downto 0),
a_txcompl => ep_txcompl_i(0),
a_txelecidle => ep_txelecidle_i(0),
a_txdetectrx => ep_txdetectrx_i(0),
a_rxpolarity => ep_rxpolarity_i(0),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_0_int,
b_txcompl => bfm_txcompl_0_int,
b_txdetectrx => bfm_txdetectrx_0_int,
b_txelecidle => bfm_txelecidle_0_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_0_int,
b_rxpolarity => bfm_rxpolarity_0_int,
b_txdatak => bfm_txdatak_0_int,
a_rxvalid => ep_rxvalid_o(0),
a_rxstatus => ep_rxstatus_o(2 downto 0),
a_rxdatak(0) => ep_rxdatak_o(0),
a_rxdata => ep_rxdata_o(7 downto 0),
a_rxelecidle => ep_rxelecidle_o(0),
a_phystatus => ep_phystatus_o(0),
b_phystatus => bfm_phystatus_0_int,
b_rxvalid => bfm_rxvalid_0_int,
b_rxelecidle => bfm_rxelecidle_0_int,
b_rxdatak(0) => bfm_rxdatak_0_int,
b_rxdata => bfm_rxdata_0_int,
b_rxstatus => bfm_rxstatus_0_int
);
x1_lane_1 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 1
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_1_int,
b_txcompl => bfm_txcompl_1_int,
b_txdetectrx => bfm_txdetectrx_1_int,
b_txelecidle => bfm_txelecidle_1_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_1_int,
b_rxpolarity => bfm_rxpolarity_1_int,
b_txdatak => bfm_txdatak_1_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_1_int,
b_rxvalid => bfm_rxvalid_1_int,
b_rxelecidle => bfm_rxelecidle_1_int,
b_rxdatak(0) => bfm_rxdatak_1_int,
b_rxdata => bfm_rxdata_1_int,
b_rxstatus => bfm_rxstatus_1_int
);
x1_lane_2 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 2
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_2_int,
b_txcompl => bfm_txcompl_2_int,
b_txdetectrx => bfm_txdetectrx_2_int,
b_txelecidle => bfm_txelecidle_2_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_2_int,
b_rxpolarity => bfm_rxpolarity_2_int,
b_txdatak => bfm_txdatak_2_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_2_int,
b_rxvalid => bfm_rxvalid_2_int,
b_rxelecidle => bfm_rxelecidle_2_int,
b_rxdatak(0) => bfm_rxdatak_2_int,
b_rxdata => bfm_rxdata_2_int,
b_rxstatus => bfm_rxstatus_2_int
);
x1_lane_3 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 3
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_3_int,
b_txcompl => bfm_txcompl_3_int,
b_txdetectrx => bfm_txdetectrx_3_int,
b_txelecidle => bfm_txelecidle_3_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_3_int,
b_rxpolarity => bfm_rxpolarity_3_int,
b_txdatak => bfm_txdatak_3_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_3_int,
b_rxvalid => bfm_rxvalid_3_int,
b_rxelecidle => bfm_rxelecidle_3_int,
b_rxdatak(0) => bfm_rxdatak_3_int,
b_rxdata => bfm_rxdata_3_int,
b_rxstatus => bfm_rxstatus_3_int
);
x1_lane_4 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 4
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_4_int,
b_txcompl => bfm_txcompl_4_int,
b_txdetectrx => bfm_txdetectrx_4_int,
b_txelecidle => bfm_txelecidle_4_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_4_int,
b_rxpolarity => bfm_rxpolarity_4_int,
b_txdatak => bfm_txdatak_4_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_4_int,
b_rxvalid => bfm_rxvalid_4_int,
b_rxelecidle => bfm_rxelecidle_4_int,
b_rxdatak(0) => bfm_rxdatak_4_int,
b_rxdata => bfm_rxdata_4_int,
b_rxstatus => bfm_rxstatus_4_int
);
x1_lane_5 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 5
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_5_int,
b_txcompl => bfm_txcompl_5_int,
b_txdetectrx => bfm_txdetectrx_5_int,
b_txelecidle => bfm_txelecidle_5_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_5_int,
b_rxpolarity => bfm_rxpolarity_5_int,
b_txdatak => bfm_txdatak_5_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_5_int,
b_rxvalid => bfm_rxvalid_5_int,
b_rxelecidle => bfm_rxelecidle_5_int,
b_rxdatak(0) => bfm_rxdatak_5_int,
b_rxdata => bfm_rxdata_5_int,
b_rxstatus => bfm_rxstatus_5_int
);
x1_lane_6 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 6
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_6_int,
b_txcompl => bfm_txcompl_6_int,
b_txdetectrx => bfm_txdetectrx_6_int,
b_txelecidle => bfm_txelecidle_6_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_6_int,
b_rxpolarity => bfm_rxpolarity_6_int,
b_txdatak => bfm_txdatak_6_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_6_int,
b_rxvalid => bfm_rxvalid_6_int,
b_rxelecidle => bfm_rxelecidle_6_int,
b_rxdatak(0) => bfm_rxdatak_6_int,
b_rxdata => bfm_rxdata_6_int,
b_rxstatus => bfm_rxstatus_6_int
);
x1_lane_7 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 7
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_7_int,
b_txcompl => bfm_txcompl_7_int,
b_txdetectrx => bfm_txdetectrx_7_int,
b_txelecidle => bfm_txelecidle_7_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_7_int,
b_rxpolarity => bfm_rxpolarity_7_int,
b_txdatak => bfm_txdatak_7_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_7_int,
b_rxvalid => bfm_rxvalid_7_int,
b_rxelecidle => bfm_rxelecidle_7_int,
b_rxdatak(0) => bfm_rxdatak_7_int,
b_rxdata => bfm_rxdata_7_int,
b_rxstatus => bfm_rxstatus_7_int
);
end generate manage_x1_lanes;
--elsif BFM_LANE_WIDTH = 2 generate
manage_x2_lanes : if BFM_LANE_WIDTH = 2 generate
-- x2 configuration, BFM connected with 2 lanes, using dummy transceiver for lanes 3 to 8
x2_lane_0 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 0
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(1 downto 0),
a_txdatak(0) => ep_txdatak_i(0),
a_txdata => ep_txdata_i(7 downto 0),
a_txcompl => ep_txcompl_i(0),
a_txelecidle => ep_txelecidle_i(0),
a_txdetectrx => ep_txdetectrx_i(0),
a_rxpolarity => ep_rxpolarity_i(0),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_0_int,
b_txcompl => bfm_txcompl_0_int,
b_txdetectrx => bfm_txdetectrx_0_int,
b_txelecidle => bfm_txelecidle_0_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_0_int,
b_rxpolarity => bfm_rxpolarity_0_int,
b_txdatak => bfm_txdatak_0_int,
a_rxvalid => ep_rxvalid_o(0),
a_rxstatus => ep_rxstatus_o(2 downto 0),
a_rxdatak(0) => ep_rxdatak_o(0),
a_rxdata => ep_rxdata_o(7 downto 0),
a_rxelecidle => ep_rxelecidle_o(0),
a_phystatus => ep_phystatus_o(0),
b_phystatus => bfm_phystatus_0_int,
b_rxvalid => bfm_rxvalid_0_int,
b_rxelecidle => bfm_rxelecidle_0_int,
b_rxdatak(0) => bfm_rxdatak_0_int,
b_rxdata => bfm_rxdata_0_int,
b_rxstatus => bfm_rxstatus_0_int
);
x2_lane_1 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 1
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(3 downto 2),
a_txdatak(0) => ep_txdatak_i(1),
a_txdata => ep_txdata_i(15 downto 8),
a_txcompl => ep_txcompl_i(1),
a_txelecidle => ep_txelecidle_i(1),
a_txdetectrx => ep_txdetectrx_i(1),
a_rxpolarity => ep_rxpolarity_i(1),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_0_int,
b_txcompl => bfm_txcompl_0_int,
b_txdetectrx => bfm_txdetectrx_0_int,
b_txelecidle => bfm_txelecidle_0_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_0_int,
b_rxpolarity => bfm_rxpolarity_0_int,
b_txdatak => bfm_txdatak_0_int,
a_rxvalid => ep_rxvalid_o(1),
a_rxstatus => ep_rxstatus_o(5 downto 3),
a_rxdatak(0) => ep_rxdatak_o(1),
a_rxdata => ep_rxdata_o(15 downto 8),
a_rxelecidle => ep_rxelecidle_o(1),
a_phystatus => ep_phystatus_o(1),
b_phystatus => bfm_phystatus_0_int,
b_rxvalid => bfm_rxvalid_0_int,
b_rxelecidle => bfm_rxelecidle_0_int,
b_rxdatak(0) => bfm_rxdatak_0_int,
b_rxdata => bfm_rxdata_0_int,
b_rxstatus => bfm_rxstatus_0_int
);
x2_lane_2 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 2
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_2_int,
b_txcompl => bfm_txcompl_2_int,
b_txdetectrx => bfm_txdetectrx_2_int,
b_txelecidle => bfm_txelecidle_2_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_2_int,
b_rxpolarity => bfm_rxpolarity_2_int,
b_txdatak => bfm_txdatak_2_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_2_int,
b_rxvalid => bfm_rxvalid_2_int,
b_rxelecidle => bfm_rxelecidle_2_int,
b_rxdatak(0) => bfm_rxdatak_2_int,
b_rxdata => bfm_rxdata_2_int,
b_rxstatus => bfm_rxstatus_2_int
);
x2_lane_3 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 3
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_3_int,
b_txcompl => bfm_txcompl_3_int,
b_txdetectrx => bfm_txdetectrx_3_int,
b_txelecidle => bfm_txelecidle_3_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_3_int,
b_rxpolarity => bfm_rxpolarity_3_int,
b_txdatak => bfm_txdatak_3_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_3_int,
b_rxvalid => bfm_rxvalid_3_int,
b_rxelecidle => bfm_rxelecidle_3_int,
b_rxdatak(0) => bfm_rxdatak_3_int,
b_rxdata => bfm_rxdata_3_int,
b_rxstatus => bfm_rxstatus_3_int
);
x2_lane_4 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 4
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_4_int,
b_txcompl => bfm_txcompl_4_int,
b_txdetectrx => bfm_txdetectrx_4_int,
b_txelecidle => bfm_txelecidle_4_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_4_int,
b_rxpolarity => bfm_rxpolarity_4_int,
b_txdatak => bfm_txdatak_4_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_4_int,
b_rxvalid => bfm_rxvalid_4_int,
b_rxelecidle => bfm_rxelecidle_4_int,
b_rxdatak(0) => bfm_rxdatak_4_int,
b_rxdata => bfm_rxdata_4_int,
b_rxstatus => bfm_rxstatus_4_int
);
x2_lane_5 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 5
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_5_int,
b_txcompl => bfm_txcompl_5_int,
b_txdetectrx => bfm_txdetectrx_5_int,
b_txelecidle => bfm_txelecidle_5_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_5_int,
b_rxpolarity => bfm_rxpolarity_5_int,
b_txdatak => bfm_txdatak_5_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_5_int,
b_rxvalid => bfm_rxvalid_5_int,
b_rxelecidle => bfm_rxelecidle_5_int,
b_rxdatak(0) => bfm_rxdatak_5_int,
b_rxdata => bfm_rxdata_5_int,
b_rxstatus => bfm_rxstatus_5_int
);
x2_lane_6 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 6
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_6_int,
b_txcompl => bfm_txcompl_6_int,
b_txdetectrx => bfm_txdetectrx_6_int,
b_txelecidle => bfm_txelecidle_6_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_6_int,
b_rxpolarity => bfm_rxpolarity_6_int,
b_txdatak => bfm_txdatak_6_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_6_int,
b_rxvalid => bfm_rxvalid_6_int,
b_rxelecidle => bfm_rxelecidle_6_int,
b_rxdatak(0) => bfm_rxdatak_6_int,
b_rxdata => bfm_rxdata_6_int,
b_rxstatus => bfm_rxstatus_6_int
);
x2_lane_7 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 7
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_7_int,
b_txcompl => bfm_txcompl_7_int,
b_txdetectrx => bfm_txdetectrx_7_int,
b_txelecidle => bfm_txelecidle_7_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_7_int,
b_rxpolarity => bfm_rxpolarity_7_int,
b_txdatak => bfm_txdatak_7_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_7_int,
b_rxvalid => bfm_rxvalid_7_int,
b_rxelecidle => bfm_rxelecidle_7_int,
b_rxdatak(0) => bfm_rxdatak_7_int,
b_rxdata => bfm_rxdata_7_int,
b_rxstatus => bfm_rxstatus_7_int
);
end generate manage_x2_lanes;
--elsif BFM_LANE_WIDTH = 4 generate
manage_x4_lanes: if BFM_LANE_WIDTH = 4 generate
-- x4 configuration, BFM connected with 4 lanes, using dummy transceiver for lanes 5 to 8
x4_lane_0 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 0
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(1 downto 0),
a_txdatak(0) => ep_txdatak_i(0),
a_txdata => ep_txdata_i(7 downto 0),
a_txcompl => ep_txcompl_i(0),
a_txelecidle => ep_txelecidle_i(0),
a_txdetectrx => ep_txdetectrx_i(0),
a_rxpolarity => ep_rxpolarity_i(0),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_0_int,
b_txcompl => bfm_txcompl_0_int,
b_txdetectrx => bfm_txdetectrx_0_int,
b_txelecidle => bfm_txelecidle_0_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_0_int,
b_rxpolarity => bfm_rxpolarity_0_int,
b_txdatak => bfm_txdatak_0_int,
a_rxvalid => ep_rxvalid_o(0),
a_rxstatus => ep_rxstatus_o(2 downto 0),
a_rxdatak(0) => ep_rxdatak_o(0),
a_rxdata => ep_rxdata_o(7 downto 0),
a_rxelecidle => ep_rxelecidle_o(0),
a_phystatus => ep_phystatus_o(0),
b_phystatus => bfm_phystatus_0_int,
b_rxvalid => bfm_rxvalid_0_int,
b_rxelecidle => bfm_rxelecidle_0_int,
b_rxdatak(0) => bfm_rxdatak_0_int,
b_rxdata => bfm_rxdata_0_int,
b_rxstatus => bfm_rxstatus_0_int
);
x4_lane_1 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 1
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(3 downto 2),
a_txdatak(0) => ep_txdatak_i(1),
a_txdata => ep_txdata_i(15 downto 8),
a_txcompl => ep_txcompl_i(1),
a_txelecidle => ep_txelecidle_i(1),
a_txdetectrx => ep_txdetectrx_i(1),
a_rxpolarity => ep_rxpolarity_i(1),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_0_int,
b_txcompl => bfm_txcompl_0_int,
b_txdetectrx => bfm_txdetectrx_0_int,
b_txelecidle => bfm_txelecidle_0_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_0_int,
b_rxpolarity => bfm_rxpolarity_0_int,
b_txdatak => bfm_txdatak_0_int,
a_rxvalid => ep_rxvalid_o(1),
a_rxstatus => ep_rxstatus_o(5 downto 3),
a_rxdatak(0) => ep_rxdatak_o(1),
a_rxdata => ep_rxdata_o(15 downto 8),
a_rxelecidle => ep_rxelecidle_o(1),
a_phystatus => ep_phystatus_o(1),
b_phystatus => bfm_phystatus_0_int,
b_rxvalid => bfm_rxvalid_0_int,
b_rxelecidle => bfm_rxelecidle_0_int,
b_rxdatak(0) => bfm_rxdatak_0_int,
b_rxdata => bfm_rxdata_0_int,
b_rxstatus => bfm_rxstatus_0_int
);
x4_lane_2 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 2
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(5 downto 4),
a_txdatak(0) => ep_txdatak_i(2),
a_txdata => ep_txdata_i(23 downto 16),
a_txcompl => ep_txcompl_i(2),
a_txelecidle => ep_txelecidle_i(2),
a_txdetectrx => ep_txdetectrx_i(2),
a_rxpolarity => ep_rxpolarity_i(2),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_0_int,
b_txcompl => bfm_txcompl_0_int,
b_txdetectrx => bfm_txdetectrx_0_int,
b_txelecidle => bfm_txelecidle_0_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_0_int,
b_rxpolarity => bfm_rxpolarity_0_int,
b_txdatak => bfm_txdatak_0_int,
a_rxvalid => ep_rxvalid_o(2),
a_rxstatus => ep_rxstatus_o(8 downto 6),
a_rxdatak(0) => ep_rxdatak_o(2),
a_rxdata => ep_rxdata_o(23 downto 16),
a_rxelecidle => ep_rxelecidle_o(2),
a_phystatus => ep_phystatus_o(2),
b_phystatus => bfm_phystatus_0_int,
b_rxvalid => bfm_rxvalid_0_int,
b_rxelecidle => bfm_rxelecidle_0_int,
b_rxdatak(0) => bfm_rxdatak_0_int,
b_rxdata => bfm_rxdata_0_int,
b_rxstatus => bfm_rxstatus_0_int
);
x4_lane_3 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 3
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(7 downto 6),
a_txdatak(0) => ep_txdatak_i(3),
a_txdata => ep_txdata_i(31 downto 24),
a_txcompl => ep_txcompl_i(3),
a_txelecidle => ep_txelecidle_i(3),
a_txdetectrx => ep_txdetectrx_i(3),
a_rxpolarity => ep_rxpolarity_i(3),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_0_int,
b_txcompl => bfm_txcompl_0_int,
b_txdetectrx => bfm_txdetectrx_0_int,
b_txelecidle => bfm_txelecidle_0_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_0_int,
b_rxpolarity => bfm_rxpolarity_0_int,
b_txdatak => bfm_txdatak_0_int,
a_rxvalid => ep_rxvalid_o(3),
a_rxstatus => ep_rxstatus_o(11 downto 9),
a_rxdatak(0) => ep_rxdatak_o(3),
a_rxdata => ep_rxdata_o(31 downto 24),
a_rxelecidle => ep_rxelecidle_o(3),
a_phystatus => ep_phystatus_o(3),
b_phystatus => bfm_phystatus_0_int,
b_rxvalid => bfm_rxvalid_0_int,
b_rxelecidle => bfm_rxelecidle_0_int,
b_rxdatak(0) => bfm_rxdatak_0_int,
b_rxdata => bfm_rxdata_0_int,
b_rxstatus => bfm_rxstatus_0_int
);
x4_lane_4 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 4
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_4_int,
b_txcompl => bfm_txcompl_4_int,
b_txdetectrx => bfm_txdetectrx_4_int,
b_txelecidle => bfm_txelecidle_4_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_4_int,
b_rxpolarity => bfm_rxpolarity_4_int,
b_txdatak => bfm_txdatak_4_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_4_int,
b_rxvalid => bfm_rxvalid_4_int,
b_rxelecidle => bfm_rxelecidle_4_int,
b_rxdatak(0) => bfm_rxdatak_4_int,
b_rxdata => bfm_rxdata_4_int,
b_rxstatus => bfm_rxstatus_4_int
);
x4_lane_5 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 5
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_5_int,
b_txcompl => bfm_txcompl_5_int,
b_txdetectrx => bfm_txdetectrx_5_int,
b_txelecidle => bfm_txelecidle_5_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_5_int,
b_rxpolarity => bfm_rxpolarity_5_int,
b_txdatak => bfm_txdatak_5_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_5_int,
b_rxvalid => bfm_rxvalid_5_int,
b_rxelecidle => bfm_rxelecidle_5_int,
b_rxdatak(0) => bfm_rxdatak_5_int,
b_rxdata => bfm_rxdata_5_int,
b_rxstatus => bfm_rxstatus_5_int
);
x4_lane_6 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 6
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_6_int,
b_txcompl => bfm_txcompl_6_int,
b_txdetectrx => bfm_txdetectrx_6_int,
b_txelecidle => bfm_txelecidle_6_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_6_int,
b_rxpolarity => bfm_rxpolarity_6_int,
b_txdatak => bfm_txdatak_6_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_6_int,
b_rxvalid => bfm_rxvalid_6_int,
b_rxelecidle => bfm_rxelecidle_6_int,
b_rxdatak(0) => bfm_rxdatak_6_int,
b_rxdata => bfm_rxdata_6_int,
b_rxstatus => bfm_rxstatus_6_int
);
x4_lane_7 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 7
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_7_int,
b_txcompl => bfm_txcompl_7_int,
b_txdetectrx => bfm_txdetectrx_7_int,
b_txelecidle => bfm_txelecidle_7_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_7_int,
b_rxpolarity => bfm_rxpolarity_7_int,
b_txdatak => bfm_txdatak_7_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_7_int,
b_rxvalid => bfm_rxvalid_7_int,
b_rxelecidle => bfm_rxelecidle_7_int,
b_rxdatak(0) => bfm_rxdatak_7_int,
b_rxdata => bfm_rxdata_7_int,
b_rxstatus => bfm_rxstatus_7_int
);
end generate manage_x4_lanes;
--else generate
manage_x8_lanes: if BFM_LANE_WIDTH = 8 generate
-- x8 configuration, BFM connected with maximum lanes, no dummy transceiver necessary
x8_lane_0 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 0
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(1 downto 0),
a_txdatak(0) => ep_txdatak_i(0),
a_txdata => ep_txdata_i(7 downto 0),
a_txcompl => ep_txcompl_i(0),
a_txelecidle => ep_txelecidle_i(0),
a_txdetectrx => ep_txdetectrx_i(0),
a_rxpolarity => ep_rxpolarity_i(0),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_0_int,
b_txcompl => bfm_txcompl_0_int,
b_txdetectrx => bfm_txdetectrx_0_int,
b_txelecidle => bfm_txelecidle_0_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_0_int,
b_rxpolarity => bfm_rxpolarity_0_int,
b_txdatak => bfm_txdatak_0_int,
a_rxvalid => ep_rxvalid_o(0),
a_rxstatus => ep_rxstatus_o(2 downto 0),
a_rxdatak(0) => ep_rxdatak_o(0),
a_rxdata => ep_rxdata_o(7 downto 0),
a_rxelecidle => ep_rxelecidle_o(0),
a_phystatus => ep_phystatus_o(0),
b_phystatus => bfm_phystatus_0_int,
b_rxvalid => bfm_rxvalid_0_int,
b_rxelecidle => bfm_rxelecidle_0_int,
b_rxdatak(0) => bfm_rxdatak_0_int,
b_rxdata => bfm_rxdata_0_int,
b_rxstatus => bfm_rxstatus_0_int
);
x8_lane_1 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 1
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(3 downto 2),
a_txdatak(0) => ep_txdatak_i(1),
a_txdata => ep_txdata_i(15 downto 8),
a_txcompl => ep_txcompl_i(1),
a_txelecidle => ep_txelecidle_i(1),
a_txdetectrx => ep_txdetectrx_i(1),
a_rxpolarity => ep_rxpolarity_i(1),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_0_int,
b_txcompl => bfm_txcompl_0_int,
b_txdetectrx => bfm_txdetectrx_0_int,
b_txelecidle => bfm_txelecidle_0_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_0_int,
b_rxpolarity => bfm_rxpolarity_0_int,
b_txdatak => bfm_txdatak_0_int,
a_rxvalid => ep_rxvalid_o(1),
a_rxstatus => ep_rxstatus_o(5 downto 3),
a_rxdatak(0) => ep_rxdatak_o(1),
a_rxdata => ep_rxdata_o(15 downto 8),
a_rxelecidle => ep_rxelecidle_o(1),
a_phystatus => ep_phystatus_o(1),
b_phystatus => bfm_phystatus_0_int,
b_rxvalid => bfm_rxvalid_0_int,
b_rxelecidle => bfm_rxelecidle_0_int,
b_rxdatak(0) => bfm_rxdatak_0_int,
b_rxdata => bfm_rxdata_0_int,
b_rxstatus => bfm_rxstatus_0_int
);
x8_lane_2 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 2
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(5 downto 4),
a_txdatak(0) => ep_txdatak_i(2),
a_txdata => ep_txdata_i(23 downto 16),
a_txcompl => ep_txcompl_i(2),
a_txelecidle => ep_txelecidle_i(2),
a_txdetectrx => ep_txdetectrx_i(2),
a_rxpolarity => ep_rxpolarity_i(2),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_0_int,
b_txcompl => bfm_txcompl_0_int,
b_txdetectrx => bfm_txdetectrx_0_int,
b_txelecidle => bfm_txelecidle_0_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_0_int,
b_rxpolarity => bfm_rxpolarity_0_int,
b_txdatak => bfm_txdatak_0_int,
a_rxvalid => ep_rxvalid_o(2),
a_rxstatus => ep_rxstatus_o(8 downto 6),
a_rxdatak(0) => ep_rxdatak_o(2),
a_rxdata => ep_rxdata_o(23 downto 16),
a_rxelecidle => ep_rxelecidle_o(2),
a_phystatus => ep_phystatus_o(2),
b_phystatus => bfm_phystatus_0_int,
b_rxvalid => bfm_rxvalid_0_int,
b_rxelecidle => bfm_rxelecidle_0_int,
b_rxdatak(0) => bfm_rxdatak_0_int,
b_rxdata => bfm_rxdata_0_int,
b_rxstatus => bfm_rxstatus_0_int
);
x8_lane_3 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 3
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(7 downto 6),
a_txdatak(0) => ep_txdatak_i(3),
a_txdata => ep_txdata_i(31 downto 24),
a_txcompl => ep_txcompl_i(3),
a_txelecidle => ep_txelecidle_i(3),
a_txdetectrx => ep_txdetectrx_i(3),
a_rxpolarity => ep_rxpolarity_i(3),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_0_int,
b_txcompl => bfm_txcompl_0_int,
b_txdetectrx => bfm_txdetectrx_0_int,
b_txelecidle => bfm_txelecidle_0_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_0_int,
b_rxpolarity => bfm_rxpolarity_0_int,
b_txdatak => bfm_txdatak_0_int,
a_rxvalid => ep_rxvalid_o(3),
a_rxstatus => ep_rxstatus_o(11 downto 9),
a_rxdatak(0) => ep_rxdatak_o(3),
a_rxdata => ep_rxdata_o(31 downto 24),
a_rxelecidle => ep_rxelecidle_o(3),
a_phystatus => ep_phystatus_o(3),
b_phystatus => bfm_phystatus_0_int,
b_rxvalid => bfm_rxvalid_0_int,
b_rxelecidle => bfm_rxelecidle_0_int,
b_rxdatak(0) => bfm_rxdatak_0_int,
b_rxdata => bfm_rxdata_0_int,
b_rxstatus => bfm_rxstatus_0_int
);
x8_lane_4 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 4
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(9 downto 8),
a_txdatak(0) => ep_txdatak_i(4),
a_txdata => ep_txdata_i(39 downto 32),
a_txcompl => ep_txcompl_i(4),
a_txelecidle => ep_txelecidle_i(4),
a_txdetectrx => ep_txdetectrx_i(4),
a_rxpolarity => ep_rxpolarity_i(4),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_4_int,
b_txcompl => bfm_txcompl_4_int,
b_txdetectrx => bfm_txdetectrx_4_int,
b_txelecidle => bfm_txelecidle_4_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_4_int,
b_rxpolarity => bfm_rxpolarity_4_int,
b_txdatak => bfm_txdatak_4_int,
a_rxvalid => ep_rxvalid_o(4),
a_rxstatus => ep_rxstatus_o(14 downto 12),
a_rxdatak(0) => ep_rxdatak_o(4),
a_rxdata => ep_rxdata_o(39 downto 32),
a_rxelecidle => ep_rxelecidle_o(4),
a_phystatus => ep_phystatus_o(4),
b_phystatus => bfm_phystatus_4_int,
b_rxvalid => bfm_rxvalid_4_int,
b_rxelecidle => bfm_rxelecidle_4_int,
b_rxdatak(0) => bfm_rxdatak_4_int,
b_rxdata => bfm_rxdata_4_int,
b_rxstatus => bfm_rxstatus_4_int
);
x8_lane_5 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 5
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(11 downto 10),
a_txdatak(0) => ep_txdatak_i(5),
a_txdata => ep_txdata_i(47 downto 40),
a_txcompl => ep_txcompl_i(5),
a_txelecidle => ep_txelecidle_i(5),
a_txdetectrx => ep_txdetectrx_i(5),
a_rxpolarity => ep_rxpolarity_i(5),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_5_int,
b_txcompl => bfm_txcompl_5_int,
b_txdetectrx => bfm_txdetectrx_5_int,
b_txelecidle => bfm_txelecidle_5_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_5_int,
b_rxpolarity => bfm_rxpolarity_5_int,
b_txdatak => bfm_txdatak_5_int,
a_rxvalid => ep_rxvalid_o(5),
a_rxstatus => ep_rxstatus_o(17 downto 15),
a_rxdatak(0) => ep_rxdatak_o(5),
a_rxdata => ep_rxdata_o(47 downto 40),
a_rxelecidle => ep_rxelecidle_o(5),
a_phystatus => ep_phystatus_o(5),
b_phystatus => bfm_phystatus_5_int,
b_rxvalid => bfm_rxvalid_5_int,
b_rxelecidle => bfm_rxelecidle_5_int,
b_rxdatak(0) => bfm_rxdatak_5_int,
b_rxdata => bfm_rxdata_5_int,
b_rxstatus => bfm_rxstatus_5_int
);
x8_lane_6 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 6
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(13 downto 12),
a_txdatak(0) => ep_txdatak_i(6),
a_txdata => ep_txdata_i(55 downto 48),
a_txcompl => ep_txcompl_i(6),
a_txelecidle => ep_txelecidle_i(6),
a_txdetectrx => ep_txdetectrx_i(6),
a_rxpolarity => ep_rxpolarity_i(6),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_6_int,
b_txcompl => bfm_txcompl_6_int,
b_txdetectrx => bfm_txdetectrx_6_int,
b_txelecidle => bfm_txelecidle_6_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_6_int,
b_rxpolarity => bfm_rxpolarity_6_int,
b_txdatak => bfm_txdatak_6_int,
a_rxvalid => ep_rxvalid_o(6),
a_rxstatus => ep_rxstatus_o(20 downto 18),
a_rxdatak(0) => ep_rxdatak_o(6),
a_rxdata => ep_rxdata_o(55 downto 48),
a_rxelecidle => ep_rxelecidle_o(6),
a_phystatus => ep_phystatus_o(6),
b_phystatus => bfm_phystatus_6_int,
b_rxvalid => bfm_rxvalid_6_int,
b_rxelecidle => bfm_rxelecidle_6_int,
b_rxdatak(0) => bfm_rxdatak_6_int,
b_rxdata => bfm_rxdata_6_int,
b_rxstatus => bfm_rxstatus_6_int
);
x8_lane_7 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 7
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(15 downto 14),
a_txdatak(0) => ep_txdatak_i(7),
a_txdata => ep_txdata_i(63 downto 56),
a_txcompl => ep_txcompl_i(7),
a_txelecidle => ep_txelecidle_i(7),
a_txdetectrx => ep_txdetectrx_i(7),
a_rxpolarity => ep_rxpolarity_i(7),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_7_int,
b_txcompl => bfm_txcompl_7_int,
b_txdetectrx => bfm_txdetectrx_7_int,
b_txelecidle => bfm_txelecidle_7_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_7_int,
b_rxpolarity => bfm_rxpolarity_7_int,
b_txdatak => bfm_txdatak_7_int,
a_rxvalid => ep_rxvalid_o(7),
a_rxstatus => ep_rxstatus_o(23 downto 21),
a_rxdatak(0) => ep_rxdatak_o(7),
a_rxdata => ep_rxdata_o(63 downto 56),
a_rxelecidle => ep_rxelecidle_o(7),
a_phystatus => ep_phystatus_o(7),
b_phystatus => bfm_phystatus_7_int,
b_rxvalid => bfm_rxvalid_7_int,
b_rxelecidle => bfm_rxelecidle_7_int,
b_rxdatak(0) => bfm_rxdatak_7_int,
b_rxdata => bfm_rxdata_7_int,
b_rxstatus => bfm_rxstatus_7_int
);
--end generate manage_lanes;
end generate manage_x8_lanes;
end architecture pcie_sim_arch;
|
gpl-3.0
|
d7641c587be50563b87573e5aeaaff74
| 0.470082 | 3.733954 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_delay_GNPJ4Y7BVC.vhd
| 4 | 1,152 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNPJ4Y7BVC is
generic ( ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 1;
BitPattern : string := "00000000000000000000000000100000";
width : positive := 32);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector((width)-1 downto 0);
output : out std_logic_vector((width)-1 downto 0);
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_delay_GNPJ4Y7BVC is
Begin
-- Delay Element, with reset value
DelayWithInit : alt_dspbuilder_SInitDelay generic map (
LPM_WIDTH => 32,
LPM_DELAY => 1,
SequenceLength => 1,
SequenceValue => "1",
ResetValue => "00000000000000000000000000100000")
port map (
dataa => input,
clock => clock,
ena => ena,
sclr => sclr,
aclr => aclr,
user_aclr => '0',
result => output);
end architecture;
|
mit
|
0264990eb9f78b052f611300b83bf90a
| 0.650174 | 3.130435 | false | false | false | false |
michaelmiehling/A25_VME_TB
|
16x010-00_src/Source/print_pkg.vhd
| 1 | 32,985 |
---------------------------------------------------------------
-- Title : Print Package
-- Project : none
---------------------------------------------------------------
-- File : print_pkg.vhd
-- Author : Michael Miehling
-- Email : [email protected]
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 26/08/03
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description :
--
-- several procedures and functions for screen printing
---------------------------------------------------------------
-- Hierarchy:
--
-- none
---------------------------------------------------------------
-- Copyright (C) 2001, MEN Mikroelektronik Nuernberg GmbH
--
-- All rights reserved. Reproduction in whole or part is
-- prohibited without the written permission of the
-- copyright owner.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.9 $
--
-- $Log: print_pkg.vhd,v $
-- Revision 1.9 2015/11/12 14:57:26 AGeissler
-- R1: Missing now procedure with one string
-- M1: Overload existing print_now_s with sting instead of integer
--
-- Revision 1.8 2015/11/12 13:56:46 AGeissler
-- R1: Missing character to std_logic_vector conversion function
-- M1: Added functions std_logic_vector_to_char and char_to_std_logic_vector
-- R2: Missing now procedures
-- M2: Added for each procedure a equivalent one, with an additional time print
--
-- Revision 1.7 2015/11/12 11:04:50 AGeissler
-- R1: The user shall decide, when and if spaces are used
-- M1: Removed spaces from print procedures
--
-- Revision 1.6 2015/03/10 10:20:34 AGeissler
-- R1: Improvement
-- M1.1: Added overloaded function for print_s_hb, print_s_hw, print_s_hl with std_logic_vector as parameter
-- M1.2: Replaced print_s_bit with print_s_std as a overloaded function with a std_logic as parameter
-- M1.3: Added short description for each function
--
-- Revision 1.5 2015/03/10 09:25:56 AGeissler
-- R1: Missing function to print an single bit
-- M1: Added function print_s_bit
--
-- Revision 1.4 2014/12/02 17:27:10 AGeissler
-- R1: Missing print functions for integer in hex with different sizes
-- M1: Added print functions print_s_hb, print_s_hw, print_s_hl
--
-- Revision 1.3 2014/11/24 11:26:00 AGeissler
-- R1: Missing function to print two strings for example text + time
-- (print_s(" it took ", time'image(tmp_time));)
-- M1: Added procedure print_s
--
-- Revision 1.2 2006/03/01 09:34:09 mmiehling
-- added print_now_s
--
-- Revision 1.1 2005/10/20 10:42:26 mmiehling
-- Initial Revision
--
-- Revision 1.1 2005/09/15 12:05:59 MMiehling
-- Initial Revision
--
-- Revision 1.2 2004/05/13 14:22:49 MMiehling
-- multifunction device support
--
-- Revision 1.1 2004/04/14 09:42:28 MMiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_textio.all;
USE ieee.numeric_std.all;
LIBRARY std;
USE std.textio.all;
PACKAGE print_pkg IS
PROCEDURE print_mtest ( source : string;
address : std_logic_vector;
is_data : std_logic_vector;
should_data : std_logic_vector;
arg : boolean);
PROCEDURE print (s: IN string);
PROCEDURE print_s (s: IN string; s2: IN string);
PROCEDURE print_s_s (s: IN string; s2: IN string; s3: IN string);
PROCEDURE print_s_i (s: IN string; s2: IN integer);
PROCEDURE print_s_h (s: IN string; s2: IN integer);
PROCEDURE print_s_hb (s: IN string; s2: IN integer);
PROCEDURE print_s_hw (s: IN string; s2: IN integer);
PROCEDURE print_s_hl (s: IN string; s2: IN integer);
PROCEDURE print_s_hb (s: IN string; s2: IN std_logic_vector(7 DOWNTO 0));
PROCEDURE print_s_hw (s: IN string; s2: IN std_logic_vector(15 DOWNTO 0));
PROCEDURE print_s_hl (s: IN string; s2: IN std_logic_vector(31 DOWNTO 0));
PROCEDURE print_s_dl (s: IN string; s2: IN std_logic_vector);
PROCEDURE print_cycle ( header : string;
address : std_logic_vector;
data : std_logic_vector;
sel_o_int : std_logic_vector(3 DOWNTO 0);
ende : string);
PROCEDURE print_s_std (s: IN string; bit: IN std_logic);
PROCEDURE print_s_std (s: IN string; vec: IN std_logic_vector);
PROCEDURE print_time (s: IN string);
PROCEDURE print_sum (intext: IN string; mstr_err: IN integer; wb_err: IN integer);
-- now procedures
PROCEDURE print_now (s: IN string);
PROCEDURE print_now_s (s: IN string; s2: IN integer);
PROCEDURE print_now_s (s: IN string; s2: IN string);
PROCEDURE print_now_s_s (s: IN string; s2: IN string; s3: IN string);
PROCEDURE print_now_s_i (s: IN string; s2: IN integer);
PROCEDURE print_now_s_h (s: IN string; s2: IN integer);
PROCEDURE print_now_s_hb (s: IN string; s2: IN integer);
PROCEDURE print_now_s_hw (s: IN string; s2: IN integer);
PROCEDURE print_now_s_hl (s: IN string; s2: IN integer);
PROCEDURE print_now_s_hb (s: IN string; s2: IN std_logic_vector(7 DOWNTO 0));
PROCEDURE print_now_s_hw (s: IN string; s2: IN std_logic_vector(15 DOWNTO 0));
PROCEDURE print_now_s_hl (s: IN string; s2: IN std_logic_vector(31 DOWNTO 0));
PROCEDURE print_now_s_dl (s: IN string; s2: IN std_logic_vector);
PROCEDURE print_now_s_std (s: IN string; bit: IN std_logic);
PROCEDURE print_now_s_std (s: IN string; vec: IN std_logic_vector);
FUNCTION char_to_std_logic_vector(arg : character) RETURN std_logic_vector;
FUNCTION std_logic_vector_to_char(arg : std_logic_vector(7 DOWNTO 0)) RETURN character;
END print_pkg;
PACKAGE BODY print_pkg IS
----------------------------------------------------------------------------------------------------------------------------------------
-- print a string with the current simulation time
PROCEDURE print_time(s: IN string) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
WRITELINE(output,l);
END print_time;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a string and a std_logic
PROCEDURE print_s_std(s: IN string; bit: IN std_logic) IS
VARIABLE l: line;
VARIABLE s2: string(1 TO 3);
BEGIN
WRITE(l, s);
IF bit = '1' THEN
s2 := "'1'";
ELSE
s2 := "'0'";
END IF;
WRITE(l, s2);
WRITELINE(output,l);
END print_s_std;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a string and a std_logic_vector as a hexadecimal number
PROCEDURE print_s_std(s: IN string; vec: IN std_logic_vector) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
HWRITE(l, vec);
WRITELINE(output,l);
END print_s_std;
----------------------------------------------------------------------------------------------------------------------------------------
-- print wishbone information
PROCEDURE print_cycle( header : string;
address : std_logic_vector;
data : std_logic_vector;
sel_o_int: std_logic_vector(3 DOWNTO 0);
ende : string) IS
VARIABLE l : line;
BEGIN
WRITE(l,header);
WRITE(l,string'(" "));
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l,string'(" ADR: "));
HWRITE(l,address,justified=>left);
WRITE(l,string'(" DATA: "));
IF address(1) = '0' THEN
CASE sel_o_int IS
WHEN "1111" => HWRITE(l,data);
WHEN "0001" => HWRITE(l,data(7 DOWNTO 0));
WRITE(l,string'(" "));
WHEN "0010" => HWRITE(l,data(15 DOWNTO 8));
WRITE(l,string'(" "));
WHEN "0100" => HWRITE(l,data(23 DOWNTO 16));
WRITE(l,string'(" "));
WHEN "1000" => HWRITE(l,data(31 DOWNTO 24));
WRITE(l,string'(" "));
WHEN "0011" => HWRITE(l,data(15 DOWNTO 0));
WRITE(l,string'(" "));
WHEN "1100" => HWRITE(l,data(31 DOWNTO 16));
WRITE(l,string'(" "));
WHEN OTHERS => ASSERT FALSE REPORT "PRINT_PKG Error: sel_o is undefined" SEVERITY error;
END CASE;
ELSE
HWRITE(l,data);
END IF;
WRITE(l,string'(" "));
WRITE(l,ende);
WRITELINE(output,l);
END print_cycle;
----------------------------------------------------------------------------------------------------------------------------------------
-- print the result of a memory test
PROCEDURE print_mtest( source : string;
address : std_logic_vector;
is_data : std_logic_vector;
should_data : std_logic_vector;
arg : boolean) IS
VARIABLE tranx : line;
BEGIN
WRITE(tranx,source);
WRITE(tranx,now, justified=>right,field =>10, unit=> ns );
WRITE(tranx,string'(" Memory Test "));
WRITE(tranx,string'(" ADR: "));
HWRITE(tranx,address,justified=>left);
IF NOT arg THEN
WRITE(tranx,string'(" DATA should be: "));
HWRITE(tranx,should_data);
WRITE(tranx, string'(" is "));
ELSE
WRITE(tranx,string'(" DATA: "));
END IF;
HWRITE(tranx,is_data);
WRITE(tranx,string'(" "));
IF arg THEN
WRITE(tranx,string'("OK"));
ELSE
WRITE(tranx,string'("ERROR!"));
END IF;
WRITELINE(output,tranx);
END print_mtest;
----------------------------------------------------------------------------------------------------------------------------------------
-- print string
PROCEDURE print(s: IN string) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
WRITELINE(output,l);
END print;
----------------------------------------------------------------------------------------------------------------------------------------
-- print two strings (for example to print string and time = print_s(" it took ", time'image(tmp_time));
PROCEDURE print_s(s: IN string;s2: IN string) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
WRITE(l, s2);
WRITELINE(output,l);
END print_s;
----------------------------------------------------------------------------------------------------------------------------------------
-- print three strings (for example to print string, value and type = print_s(" it took ", integer, "ns");
PROCEDURE print_s_s(s: IN string; s2: IN string; s3: IN string) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
WRITE(l, s2);
WRITE(l, s3);
WRITELINE(output,l);
END print_s_s;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a integer as a decimal number
PROCEDURE print_s_i(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
WRITE(l, s2);
WRITELINE(output,l);
END print_s_i;
----------------------------------------------------------------------------------------------------------------------------------------
-- print an integer as a hexadecimal number with 8 digits (equal to print_s_hl but is needed to be backward compatible)
PROCEDURE print_s_h(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
HWRITE(l, std_logic_vector(to_unsigned(s2,32)));
WRITELINE(output,l);
END print_s_h;
----------------------------------------------------------------------------------------------------------------------------------------
-- print an integer as a hexadecimal number with 2 digits
PROCEDURE print_s_hb(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
HWRITE(l, std_logic_vector(to_unsigned(s2,8)));
WRITELINE(output,l);
END print_s_hb;
----------------------------------------------------------------------------------------------------------------------------------------
-- print an integer as a hexadecimal number with 4 digits
PROCEDURE print_s_hw(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
HWRITE(l, std_logic_vector(to_unsigned(s2,16)));
WRITELINE(output,l);
END print_s_hw;
----------------------------------------------------------------------------------------------------------------------------------------
-- print an integer as a hexadecimal number with 8 digits
PROCEDURE print_s_hl(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
HWRITE(l, std_logic_vector(to_unsigned(s2,32)));
WRITELINE(output,l);
END print_s_hl;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a std_logic_vector as a hexadecimal number with 2 digits
PROCEDURE print_s_hb(s: IN string;s2: IN std_logic_vector(7 DOWNTO 0)) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
HWRITE(l, s2);
WRITELINE(output,l);
END print_s_hb;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a std_logic_vector as a hexadecimal number with 4 digits
PROCEDURE print_s_hw(s: IN string;s2: IN std_logic_vector(15 DOWNTO 0)) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
HWRITE(l, s2);
WRITELINE(output,l);
END print_s_hw;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a std_logic_vector as a hexadecimal number with 8 digits
PROCEDURE print_s_hl(s: IN string;s2: IN std_logic_vector(31 DOWNTO 0)) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
HWRITE(l, s2);
WRITELINE(output,l);
END print_s_hl;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a std_logic_vector as a decimal number
PROCEDURE print_s_dl(s: IN string;s2: IN std_logic_vector) IS
VARIABLE l: line;
BEGIN
WRITE(l, s);
WRITE(l, to_integer(unsigned(s2)));
WRITELINE(output,l);
END print_s_dl;
----------------------------------------------------------------------------------------------------------------------------------------
-- print the result of a test case
PROCEDURE print_sum(intext: IN string; mstr_err: IN integer; wb_err: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l, string'(" "));
WRITELINE(output,l);
IF mstr_err = 0 AND wb_err = 0 THEN
WRITE(l, string'(" P A S S "));
WRITE(l, intext);
WRITELINE(output,l);
ELSE
WRITE(l, string'(" F A I L "));
WRITE(l, intext);
WRITELINE(output,l);
WRITE(l, string'(" Number of PCI errors: "));
WRITE(l, mstr_err);
WRITELINE(output,l);
WRITE(l, string'(" Number of WB errors: "));
WRITE(l, wb_err);
WRITELINE(output,l);
END IF;
WRITE(l, string'("*************************************************************************************************************"));
WRITELINE(output,l);
END print_sum;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a string with the current simulation time
PROCEDURE print_now(s: IN string) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
WRITELINE(output,l);
END print_now;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a string and an integer as decimal number withthe current simulation time
PROCEDURE print_now_s(s: IN string; s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
WRITE(l, s2);
WRITELINE(output,l);
END print_now_s;
----------------------------------------------------------------------------------------------------------------------------------------
-- print two strings (for example to print string and time = print_s(" it took ", time'image(tmp_time));
PROCEDURE print_now_s(s: IN string;s2: IN string) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
WRITE(l, s2);
WRITELINE(output,l);
END print_now_s;
----------------------------------------------------------------------------------------------------------------------------------------
-- print three strings (for example to print string, value and type = print_s(" it took ", integer, "ns");
PROCEDURE print_now_s_s(s: IN string; s2: IN string; s3: IN string) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
WRITE(l, s2);
WRITE(l, s3);
WRITELINE(output,l);
END print_now_s_s;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a integer as a decimal number
PROCEDURE print_now_s_i(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
WRITE(l, s2);
WRITELINE(output,l);
END print_now_s_i;
----------------------------------------------------------------------------------------------------------------------------------------
-- print an integer as a hexadecimal number with 8 digits (equal to print_s_hl but is needed to be backward compatible)
PROCEDURE print_now_s_h(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
HWRITE(l, std_logic_vector(to_unsigned(s2,32)));
WRITELINE(output,l);
END print_now_s_h;
----------------------------------------------------------------------------------------------------------------------------------------
-- print an integer as a hexadecimal number with 2 digits
PROCEDURE print_now_s_hb(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
HWRITE(l, std_logic_vector(to_unsigned(s2,8)));
WRITELINE(output,l);
END print_now_s_hb;
----------------------------------------------------------------------------------------------------------------------------------------
-- print an integer as a hexadecimal number with 4 digits
PROCEDURE print_now_s_hw(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
HWRITE(l, std_logic_vector(to_unsigned(s2,16)));
WRITELINE(output,l);
END print_now_s_hw;
----------------------------------------------------------------------------------------------------------------------------------------
-- print an integer as a hexadecimal number with 8 digits
PROCEDURE print_now_s_hl(s: IN string;s2: IN integer) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
HWRITE(l, std_logic_vector(to_unsigned(s2,32)));
WRITELINE(output,l);
END print_now_s_hl;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a std_logic_vector as a hexadecimal number with 2 digits
PROCEDURE print_now_s_hb(s: IN string;s2: IN std_logic_vector(7 DOWNTO 0)) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
HWRITE(l, s2);
WRITELINE(output,l);
END print_now_s_hb;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a std_logic_vector as a hexadecimal number with 4 digits
PROCEDURE print_now_s_hw(s: IN string;s2: IN std_logic_vector(15 DOWNTO 0)) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
HWRITE(l, s2);
WRITELINE(output,l);
END print_now_s_hw;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a std_logic_vector as a hexadecimal number with 8 digits
PROCEDURE print_now_s_hl(s: IN string;s2: IN std_logic_vector(31 DOWNTO 0)) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
HWRITE(l, s2);
WRITELINE(output,l);
END print_now_s_hl;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a std_logic_vector as a decimal number
PROCEDURE print_now_s_dl(s: IN string;s2: IN std_logic_vector) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
WRITE(l, to_integer(unsigned(s2)));
WRITELINE(output,l);
END print_now_s_dl;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a string and a std_logic
PROCEDURE print_now_s_std(s: IN string; bit: IN std_logic) IS
VARIABLE l: line;
VARIABLE s2: string(1 TO 3);
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
IF bit = '1' THEN
s2 := "'1'";
ELSE
s2 := "'0'";
END IF;
WRITE(l, s2);
WRITELINE(output,l);
END print_now_s_std;
----------------------------------------------------------------------------------------------------------------------------------------
-- print a string and a std_logic_vector as a hexadecimal number
PROCEDURE print_now_s_std(s: IN string; vec: IN std_logic_vector) IS
VARIABLE l: line;
BEGIN
WRITE(l,now, justified=>right,field =>10, unit=> ns );
WRITE(l, string'(" "));
WRITE(l, s);
HWRITE(l, vec);
WRITELINE(output,l);
END print_now_s_std;
----------------------------------------------------------------------------------------------------------------------------------------
-- function to convert character to std_logic_vector
FUNCTION char_to_std_logic_vector( arg : character) RETURN std_logic_vector IS
BEGIN
RETURN std_logic_vector(to_unsigned(character'POS(arg), 8));
END FUNCTION char_to_std_logic_vector;
----------------------------------------------------------------------------------------------------------------------------------------
-- function to convert std_logic_vector to character
FUNCTION std_logic_vector_to_char( arg : std_logic_vector(7 DOWNTO 0) ) RETURN character IS
BEGIN
CASE arg IS
-- NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL,
-- BS, HT, LF, VT, FF, CR, SO, SI,
WHEN "00000000" =>
RETURN NUL;
WHEN "00000001" =>
RETURN SOH;
WHEN "00000010" =>
RETURN STX;
WHEN "00000011" =>
RETURN ETX;
WHEN "00000100" =>
RETURN EOT;
WHEN "00000101"=>
RETURN ENQ;
WHEN "00000110" =>
RETURN ACK;
WHEN "00000111" =>
RETURN BEL;
WHEN "00001000" =>
RETURN BS;
WHEN "00001001" =>
RETURN HT;
WHEN "00001010" =>
RETURN LF;
WHEN "00001011" =>
RETURN VT;
WHEN "00001100" =>
RETURN FF;
WHEN "00001101" =>
RETURN CR;
WHEN "00001110" =>
RETURN SO;
WHEN "00001111" =>
RETURN SI;
-- DLE, DC1, DC2, DC3, DC4, NAK, SYN, ETB,
-- CAN, EM, SUB, ESC, FSP, GSP, RSP, USP,
WHEN "00010000" =>
RETURN DLE;
WHEN "00010001" =>
RETURN DC1;
WHEN "00010010" =>
RETURN DC2;
WHEN "00010011" =>
RETURN DC3;
WHEN "00010100" =>
RETURN DC4;
WHEN "00010101" =>
RETURN NAK;
WHEN "00010110" =>
RETURN SYN;
WHEN "00010111" =>
RETURN ETB;
WHEN "00011000" =>
RETURN CAN;
WHEN "00011001" =>
RETURN EM;
WHEN "00011010" =>
RETURN SUB;
WHEN "00011011" =>
RETURN ESC;
WHEN "00011100" =>
RETURN FSP;
WHEN "00011101" =>
RETURN GSP;
WHEN "00011110" =>
RETURN RSP;
WHEN "00011111" =>
RETURN USP;
-- ' ', '!', '"', '#', '$', '%', '&', ''',
-- '(', ')', '*', '+', ',', '-', '.', '/',
WHEN "00100000" =>
RETURN ' ';
WHEN "00100001" =>
RETURN '!';
WHEN "00100010" =>
RETURN '"'; --"
WHEN "00100011" =>
RETURN '#';
WHEN "00100100" =>
RETURN '$';
WHEN "00100101" =>
RETURN '%';
WHEN "00100110" =>
RETURN '&';
WHEN "00100111" =>
RETURN ''';
WHEN "00101000" =>
RETURN '(';
WHEN "00101001" =>
RETURN ')';
WHEN "00101010" =>
RETURN '*';
WHEN "00101011" =>
RETURN '+';
WHEN "00101100" =>
RETURN ',';
WHEN "00101101" =>
RETURN '-';
WHEN "00101110" =>
RETURN '.';
WHEN "00101111" =>
RETURN '/';
-- '0', '1', '2', '3', '4', '5', '6', '7',
-- '8', '9', ':', ';', '<', '=', '>', '?',
WHEN "00110000" =>
RETURN '0';
WHEN "00110001" =>
RETURN '1';
WHEN "00110010" =>
RETURN '2';
WHEN "00110011" =>
RETURN '3';
WHEN "00110100" =>
RETURN '4';
WHEN "00110101" =>
RETURN '5';
WHEN "00110110" =>
RETURN '6';
WHEN "00110111" =>
RETURN '7';
WHEN "00111000" =>
RETURN '8';
WHEN "00111001" =>
RETURN '9';
WHEN "00111010" =>
RETURN ':';
WHEN "00111011" =>
RETURN ';';
WHEN "00111100" =>
RETURN '<';
WHEN "00111101" =>
RETURN '=';
WHEN "00111110" =>
RETURN '>';
WHEN "00111111" =>
RETURN '?';
-- '@', 'A', 'B', 'C', 'D', 'E', 'F', 'G',
-- 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O',
WHEN "01000000" =>
RETURN '@';
WHEN "01000001" =>
RETURN 'A';
WHEN "01000010" =>
RETURN 'B';
WHEN "01000011" =>
RETURN 'C';
WHEN "01000100" =>
RETURN 'D';
WHEN "01000101" =>
RETURN 'E';
WHEN "01000110" =>
RETURN 'F';
WHEN "01000111" =>
RETURN 'G';
WHEN "01001000" =>
RETURN 'H';
WHEN "01001001" =>
RETURN 'I';
WHEN "01001010" =>
RETURN 'J';
WHEN "01001011" =>
RETURN 'K';
WHEN "01001100" =>
RETURN 'L';
WHEN "01001101" =>
RETURN 'M';
WHEN "01001110" =>
RETURN 'N';
WHEN "01001111" =>
RETURN 'O';
-- 'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W',
-- 'X', 'Y', 'Z', '[', '\', ']', '^', '_',
WHEN "01010000" =>
RETURN 'P';
WHEN "01010001" =>
RETURN 'Q';
WHEN "01010010" =>
RETURN 'R';
WHEN "01010011" =>
RETURN 'S';
WHEN "01010100" =>
RETURN 'T';
WHEN "01010101" =>
RETURN 'U';
WHEN "01010110" =>
RETURN 'V';
WHEN "01010111" =>
RETURN 'W';
WHEN "01011000" =>
RETURN 'X';
WHEN "01011001" =>
RETURN 'Y';
WHEN "01011010" =>
RETURN 'Z';
WHEN "01011011" =>
RETURN '[';
WHEN "01011100" =>
RETURN '\';
WHEN "01011101" =>
RETURN ']';
WHEN "01011110" =>
RETURN '^';
WHEN "01011111" =>
RETURN '_';
-- '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
-- 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
WHEN "01100000" =>
RETURN '`';
WHEN "01100001" =>
RETURN 'a';
WHEN "01100010" =>
RETURN 'b';
WHEN "01100011" =>
RETURN 'c';
WHEN "01100100" =>
RETURN 'd';
WHEN "01100101" =>
RETURN 'e';
WHEN "01100110" =>
RETURN 'f';
WHEN "01100111" =>
RETURN 'g';
WHEN "01101000" =>
RETURN 'h';
WHEN "01101001" =>
RETURN 'i';
WHEN "01101010" =>
RETURN 'j';
WHEN "01101011" =>
RETURN 'k';
WHEN "01101100" =>
RETURN 'l';
WHEN "01101101" =>
RETURN 'm';
WHEN "01101110" =>
RETURN 'n';
WHEN "01101111" =>
RETURN 'o';
-- 'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
-- 'x', 'y', 'z', '{', '|', '}', '~', DEL,
WHEN "01110000" =>
RETURN 'p';
WHEN "01110001" =>
RETURN 'q';
WHEN "01110010" =>
RETURN 'r';
WHEN "01110011" =>
RETURN 's';
WHEN "01110100" =>
RETURN 't';
WHEN "01110101" =>
RETURN 'u';
WHEN "01110110" =>
RETURN 'v';
WHEN "01110111" =>
RETURN 'w';
WHEN "01111000" =>
RETURN 'x';
WHEN "01111001" =>
RETURN 'y';
WHEN "01111010" =>
RETURN 'z';
WHEN "01111011" =>
RETURN '{';
WHEN "01111100" =>
RETURN '|';
WHEN "01111101" =>
RETURN '}';
WHEN "01111110" =>
RETURN '~';
WHEN "01111111" =>
RETURN DEL;
WHEN OTHERS =>
RETURN '0';
END CASE;
-- missing characters:
-- C128, C129, C130, C131, C132, C133, C134, C135,
-- C136, C137, C138, C139, C140, C141, C142, C143,
-- C144, C145, C146, C147, C148, C149, C150, C151,
-- C152, C153, C154, C155, C156, C157, C158, C159,
-- ' ', '¡', '¢', '£', '¤', '¥', '¦', '§',
-- '¨', '©', 'ª', '«', '¬', '', '®', '¯',
-- '°', '±', '²', '³', '´', 'µ', '¶', '·',
-- '¸', '¹', 'º', '»', '¼', '½', '¾', '¿',
-- 'À', 'Á', 'Â', 'Ã', 'Ä', 'Å', 'Æ', 'Ç',
-- 'È', 'É', 'Ê', 'Ë', 'Ì', 'Í', 'Î', 'Ï',
-- 'Ð', 'Ñ', 'Ò', 'Ó', 'Ô', 'Õ', 'Ö', '×',
-- 'Ø', 'Ù', 'Ú', 'Û', 'Ü', 'Ý', 'Þ', 'ß',
-- 'à', 'á', 'â', 'ã', 'ä', 'å', 'æ', 'ç',
-- 'è', 'é', 'ê', 'ë', 'ì', 'í', 'î', 'ï',
-- 'ð', 'ñ', 'ò', 'ó', 'ô', 'õ', 'ö', '÷',
-- 'ø', 'ù', 'ú', 'û', 'ü', 'ý', 'þ', 'ÿ');
END FUNCTION std_logic_vector_to_char;
END;
|
gpl-3.0
|
ec722278da19909a89439978d0e25825
| 0.427619 | 4.129836 | false | false | false | false |
Ttl/bf_cpu
|
testbenches/cpu_tb.vhd
| 1 | 2,101 |
-- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE std.textio.all;
ENTITY cpu_tb IS
END cpu_tb;
ARCHITECTURE behavior OF cpu_tb IS
signal clk, reset, tx, rx : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
signal uart_tx_req, uart_tx_end, uart_rx_ready : std_logic;
signal uart_tx_data, uart_rx_data : std_logic_vector(7 downto 0);
BEGIN
-- Component Instantiation
uut: entity work.cpu
Generic map ( INSTRUCTIONS => "scripts/branch.mif"
)
Port map(clk => clk,
reset => reset,
tx => rx,
rx => tx
);
uart1 : entity work.uart
Generic map(
CLK_FREQ => 100,
SER_FREQ => 2000000,
PARITY_BIT => false
)
Port map (
clk => clk,
rst => reset,
rx => rx,
tx => tx,
tx_req => uart_tx_req,
tx_end => uart_tx_end,
tx_data => uart_tx_data,
rx_ready => uart_rx_ready,
rx_data => uart_rx_data
);
-- Print received bytes
uart_process : process
begin
wait until uart_rx_ready = '1';
wait for clk_period;
if to_integer(unsigned(uart_rx_data)) > 31 and to_integer(unsigned(uart_rx_data)) < 127 then
report "Received ASCII: "&character'image(character'val(to_integer(unsigned(uart_rx_data))));
else
report "Received Dec: "&integer'image(to_integer(unsigned(uart_rx_data)));
end if;
end process;
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Test Bench Statements
tb : PROCESS
BEGIN
reset <= '1';
uart_tx_req <= '0';
wait for 100 ns; -- wait until global set/reset completes
reset <= '0';
-- Send character
uart_tx_req <= '1';
uart_tx_data <= x"41"; -- A
wait for clk_period;
uart_tx_req <= '0';
wait until uart_tx_end = '1';
wait; -- will wait forever
END PROCESS tb;
-- End Test Bench
END;
|
lgpl-3.0
|
6c7e54903f801fc9d8b13e025e49676c
| 0.572109 | 3.41626 | false | false | false | false |
michaelmiehling/A25_VME_TB
|
Testbench/vme_sim_mon.vhd
| 1 | 10,071 |
---------------------------------------------------------------
-- Title : VME bus monitor
-- Project : A15
---------------------------------------------------------------
-- File : vme_sim_mon.vhd
-- Author : Michael Miehling
-- Email : [email protected]
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 02/09/03
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description :
--
--
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
-- Copyright (C) 2001, MEN Mikroelektronik Nuernberg GmbH
--
-- All rights reserved. Reproduction in whole or part is
-- prohibited without the written permission of the
-- copyright owner.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.1 $
--
-- $Log: vme_sim_mon.vhd,v $
-- Revision 1.1 2012/03/29 10:28:46 MMiehling
-- Initial Revision
--
-- Revision 1.2 2006/05/18 14:31:24 MMiehling
-- changed comment
--
-- Revision 1.1 2005/10/28 17:52:14 mmiehling
-- Initial Revision
--
-- Revision 1.1 2004/07/27 17:28:12 mmiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee,work;
USE ieee.std_logic_1164.ALL;
USE work.vme_sim_pack.ALL;
USE ieee.std_logic_unsigned.ALL;
USE std.textio.all;
USE work.print_pkg.all;
ENTITY vme_sim_mon IS
PORT (
rstn : IN std_logic;
asn_in : IN std_logic;
dsan_in : IN std_logic;
dsbn_in : IN std_logic;
writen_in : IN std_logic;
dtackn_in : IN std_logic;
berrn_in : IN std_logic;
addr_in : IN std_logic_vector(31 DOWNTO 0);
data_in : IN std_logic_vector(31 DOWNTO 0);
am_in : IN std_logic_vector(5 DOWNTO 0);
iackn : IN std_logic;
vb_irq1n : IN std_logic;
vb_irq2n : IN std_logic;
vb_irq3n : IN std_logic;
vb_irq4n : IN std_logic;
vb_irq5n : IN std_logic;
vb_irq6n : IN std_logic;
vb_irq7n : IN std_logic;
bbsyn_in : IN std_logic;
vme_mon_out : OUT vme_mon_out_type
);
END vme_sim_mon;
ARCHITECTURE vme_sim_mon_arch OF vme_sim_mon IS
BEGIN
vme_mon_out.err <= 0;
irq_1 : PROCESS
BEGIN
WAIT until falling_edge(vb_irq1n);
print_time("vme_sim_mon: IRQ1 was asserted");
WAIT until rising_edge(vb_irq1n);
print_time("vme_sim_mon: IRQ1 was deasserted");
END PROCESS irq_1;
irq_2 : PROCESS
BEGIN
WAIT until falling_edge(vb_irq2n);
print_time("vme_sim_mon: IRQ2 was asserted");
WAIT until rising_edge(vb_irq2n);
print_time("vme_sim_mon: IRQ2 was deasserted");
END PROCESS irq_2;
irq_3 : PROCESS
BEGIN
WAIT until falling_edge(vb_irq3n);
print_time("vme_sim_mon: IRQ3 was asserted");
WAIT until rising_edge(vb_irq3n);
print_time("vme_sim_mon: IRQ3 was deasserted");
END PROCESS irq_3;
irq_4 : PROCESS
BEGIN
WAIT until falling_edge(vb_irq4n);
print_time("vme_sim_mon: IRQ4 was asserted");
WAIT until rising_edge(vb_irq4n);
print_time("vme_sim_mon: IRQ4 was deasserted");
END PROCESS irq_4;
irq_5 : PROCESS
BEGIN
WAIT until falling_edge(vb_irq5n);
print_time("vme_sim_mon: IRQ5 was asserted");
WAIT until rising_edge(vb_irq5n);
print_time("vme_sim_mon: IRQ5 was deasserted");
END PROCESS irq_5;
irq_6 : PROCESS
BEGIN
WAIT until falling_edge(vb_irq6n);
print_time("vme_sim_mon: IRQ6 was asserted");
WAIT until rising_edge(vb_irq6n);
print_time("vme_sim_mon: IRQ6 was deasserted");
END PROCESS irq_6;
irq_7 : PROCESS
BEGIN
WAIT until falling_edge(vb_irq7n);
print_time("vme_sim_mon: IRQ7 was asserted");
WAIT until rising_edge(vb_irq7n);
print_time("vme_sim_mon: IRQ7 was deasserted");
END PROCESS irq_7;
d_timing : PROCESS
VARIABLE zeit : time;
BEGIN
WAIT until rstn = '1';
LOOP
WAIT until falling_edge(dtackn_in);
IF writen_in = '1' THEN -- read
IF NOT data_in'stable(time_27) THEN
print_time("vme_sim_mon: Data[31:0] was not stable for time(27)!");
END IF;
zeit:=now;
WAIT until rising_edge(dsan_in) OR rising_edge(dsbn_in);
IF data_in'last_active > (now-zeit) THEN
print_time("vme_sim_mon: Data[31:0] was not stable for time(20)!");
END IF;
WAIT until rising_edge(dtackn_in);
IF NOT is_x(data_in)THEN
print_time("vme_sim_mon: Data[31:0] was not 'Z' (time(31))!");
END IF;
ELSE
IF NOT data_in'stable(time_28) THEN
print_time("vme_sim_mon: Data[31:0] was not stable for time(28)!");
END IF;
IF NOT dsan_in'stable(time_28) THEN
print_time("vme_sim_mon: dsan was not stable for time(28)!");
END IF;
IF NOT dsbn_in'stable(time_28) THEN
print_time("vme_sim_mon: dsbn was not stable for time(28)!");
END IF;
IF NOT data_in'stable(time_28 + time_8) THEN
print_time("vme_sim_mon: dsbn was not stable for time(28)!");
END IF;
IF NOT (dsan_in = '0' OR dsbn_in = '0') THEN
print_time("vme_sim_mon: dsan or dsbn must be asserted!");
END IF;
END IF;
END LOOP;
END PROCESS d_timing;
adr_timing : PROCESS
VARIABLE zeit : time;
BEGIN
WAIT until rstn = '1';
LOOP
WAIT until falling_edge(asn_in);
zeit := now;
WAIT until falling_edge(dtackn_in);
IF addr_in'last_active > (now-zeit + time_4) THEN
print_time("vme_sim_mon: addr_in was not stable for time(4) or time(14)!");
END IF;
WAIT until rising_edge(asn_in);
END LOOP;
END PROCESS adr_timing;
--adr_x : PROCESS
-- BEGIN
-- LOOP
-- WAIT on addr_in;
-- IF is_x(addr_in)THEN
-- print_time("vme_sim_mon: addr_in[31:0] was 'X'!");
-- END IF;
-- END LOOP;
-- END PROCESS adr_x;
--
--dat_x : PROCESS
-- BEGIN
-- LOOP
-- WAIT on data_in;
-- IF is_x(data_in)THEN
-- print_time("vme_sim_mon: data_in[31:0] was 'X'!");
-- END IF;
-- END LOOP;
-- END PROCESS dat_x;
asn_timing : PROCESS
BEGIN
WAIT until rstn = '1';
LOOP
IF asn_in /= '0' THEN
WAIT until asn_in = '0';
END IF;
WAIT FOR time_19;
IF NOT asn_in'stable(time_19) then
print_time("vme_sim_mon: ASn was not long enough asserted (time(19))!");
END IF;
IF asn_in = '0' THEN
WAIT until asn_in /= '0';
END IF;
END LOOP;
END PROCESS asn_timing;
am_timing : PROCESS
VARIABLE am_time : time;
BEGIN
WAIT until rstn = '1';
LOOP
IF asn_in /= '0' THEN
WAIT until asn_in = '0';
END IF;
am_time := now;
IF is_x(am_in) THEN
print_time("vme_sim_mon: AM[5:0] is not a real value ('0' or '1')!");
END IF;
IF NOT am_in'stable(time_4) then
print_time("vme_sim_mon: AM[5:0] was not stable for time(4)!");
ASSERT FALSE REPORT " Timingfehler! " SEVERITY error;
END IF;
IF is_x(addr_in) THEN
print_time("vme_sim_mon: AM[5:0] is not a real value ('0' or '1')!");
END IF;
IF NOT addr_in'stable(time_4) then
print_time("vme_sim_mon: ADDR[31:0] was not stable for time(4)!");
END IF;
IF dtackn_in /= '0' THEN
WAIT until dtackn_in = '0';
END IF;
IF am_in'last_active < (time_4 + (now - am_time)) then
print_time("vme_sim_mon: AM[5:0] was not stable during access (time(4), time(16))!");
END IF;
IF addr_in'last_active < (time_4 + (now - am_time)) then
print_time("vme_sim_mon: ADDR[31:0] was not stable during access (time(4), time(16))!");
END IF;
IF asn_in = '0' THEN
WAIT until asn_in /= '0';
END IF;
-- WAIT FOR 5 ns; -- this time is not allowed!!!
IF NOT is_x(addr_in) THEN
print("vme_sim_mon: Adr[31:0] is not 'Z' after asn goes high (time(24a))!");
ASSERT FALSE REPORT " Timingfehler! " SEVERITY warning;
END IF;
IF NOT is_x(am_in) THEN
print("vme_sim_mon: AM[5:0] is not 'Z' after asn goes high (time(24a))!");
ASSERT FALSE REPORT " Timingfehler! " SEVERITY warning;
END IF;
IF NOT is_x(data_in) THEN
print("vme_sim_mon: Data_in[31:0] is not 'Z' after asn goes high (time(24a))!");
ASSERT FALSE REPORT " Timingfehler! " SEVERITY warning;
END IF;
END LOOP;
END PROCESS am_timing;
--write_timing : PROCESS
-- VARIABLE write_time : time;
-- BEGIN
-- IF arst_sig = '1' THEN
-- IF dsan_in = '1' THEN
-- WAIT until dsan_in = '0';
-- write_time := now;
-- IF NOT writen_in'stable(time_12) then
-- print("vme_sim_mon: WRITEN was not stable for time(12)!");
-- ASSERT FALSE REPORT " Timingfehler! " SEVERITY error;
-- END IF;
-- IF dsan_in = '0' THEN
-- WAIT until dsan_in = '1';
-- END IF;
-- IF dsbn_in = '0' THEN
-- WAIT until dsbn_in = '1';
-- END IF;
-- WAIT FOR time_23;
-- IF writen_in'last_active > (time_12 + (now - write_time)) then
-- print("vme_sim_mon: WRITEN was not stable during access (time(12), time(23))!");
-- ASSERT FALSE REPORT " Timingfehler! " SEVERITY error;
-- END IF;
-- END IF;
-- end if;
-- END PROCESS write_timing;
END vme_sim_mon_arch;
|
gpl-3.0
|
d46cd916505bb5a733e47187fbcd392e
| 0.521199 | 3.415056 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_logical_bit_op_GNUQ2R64DV.vhd
| 8 | 804 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_logical_bit_op_GNUQ2R64DV is
generic ( LogicalOp : string := "AltOR";
number_inputs : positive := 2);
port(
result : out std_logic;
data0 : in std_logic;
data1 : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_logical_bit_op_GNUQ2R64DV is
Begin
-- Logical Bit Operation - Simulink Block "LogicalBitOperator"
LogicalBitOperatori : alt_dspbuilder_SBitLogical generic map (
LPM_WIDTH => 2,
LOP => AltOR)
port map (
dataa(0) => data0,
dataa(1) => data1,
result => result);
end architecture;
|
mit
|
96e90a6e32cf41e8aa7d0efa887e99b6
| 0.677861 | 3.116279 | false | false | false | false |
michaelmiehling/A25_VME_TB
|
Testbench/A25_top_sim.vhd
| 1 | 55,722 |
--------------------------------------------------------------------------------
-- Title : Toplevel File of A25 FPGA
-- Project : 1614_CERN_A25
--------------------------------------------------------------------------------
-- File : A25_top.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 2016-06-03
--------------------------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
--------------------------------------------------------------------------------
-- Description :
--
--------------------------------------------------------------------------------
-- Hierarchy:
--
-- A25_top
-- wbb2vme_top
-- sram
-- ip_16z091_01_top
-- iram_wb
-- pll_pcie
-- z126_01_top
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.wb_pkg.ALL;
USE work.fpga_pkg_2.ALL;
USE work.z126_01_pkg.ALL;
USE work.vme_pkg.ALL;
ENTITY A25_top IS
GENERIC (
SIMULATION : boolean := FALSE;
FPGA_FAMILY : family_type := CYCLONE4;
BFM_LANE_WIDTH : integer range 8 downto 0 := 1; -- set configuration: 1=x1, 2=x2, 4=x4 and 8=x8
sets : std_logic_vector(3 DOWNTO 0) := "1110";
timeout : integer := 5000 );
PORT (
clk_16mhz : IN std_logic;
led_green_n : OUT std_logic;
led_red_n : OUT std_logic;
hreset_n : IN std_logic; -- reset
v2p_rstn : OUT std_logic; -- connected to hreset_req1_n
fpga_test : INOUT std_logic_vector(5 DOWNTO 1);
-- pcie
refclk : IN std_logic; -- 100 MHz pcie clock
pcie_rx : IN std_logic_vector(3 DOWNTO 0); -- PCIe receive line
pcie_tx : OUT std_logic_vector(3 DOWNTO 0); -- PCIe transmit line
-- sram
sr_clk : OUT std_logic;
sr_a : OUT std_logic_vector(18 DOWNTO 0);
sr_d : INOUT std_logic_vector(15 DOWNTO 0);
sr_bwa_n : OUT std_logic;
sr_bwb_n : OUT std_logic;
sr_bw_n : OUT std_logic;
sr_cs1_n : OUT std_logic;
sr_adsc_n : OUT std_logic;
sr_oe_n : OUT std_logic;
-- vmebus
vme_ga : IN std_logic_vector(4 DOWNTO 0); -- geographical addresses
vme_gap : IN std_logic; -- geographical addresses
vme_a : INOUT std_logic_vector(31 DOWNTO 0);
vme_a_dir : OUT std_logic;
vme_a_oe_n : OUT std_logic;
vme_d : INOUT std_logic_vector(31 DOWNTO 0);
vme_d_dir : OUT std_logic;
vme_d_oe_n : OUT std_logic;
vme_am_dir : OUT std_logic;
vme_am : INOUT std_logic_vector(5 DOWNTO 0);
vme_am_oe_n : OUT std_logic;
vme_write_n : INOUT std_logic;
vme_iack_n : INOUT std_logic;
vme_irq_i_n : IN std_logic_vector(7 DOWNTO 1);
vme_irq_o : OUT std_logic_vector(7 DOWNTO 1); -- high active on A25
vme_as_i_n : IN std_logic;
vme_as_o_n : OUT std_logic;
vme_as_oe : OUT std_logic; -- high active on A25
vme_retry_o_n : OUT std_logic;
vme_retry_oe : OUT std_logic; -- high active on A25
vme_retry_i_n : IN std_logic;
vme_sysres_i_n : IN std_logic;
vme_sysres_o : OUT std_logic; -- high active on A25
vme_ds_i_n : IN std_logic_vector(1 DOWNTO 0);
vme_ds_o_n : OUT std_logic_vector(1 DOWNTO 0);
vme_ds_oe : OUT std_logic; -- high active on A25
vme_berr_i_n : IN std_logic;
vme_berr_o : OUT std_logic; -- high active on A25
vme_dtack_i_n : IN std_logic;
vme_dtack_o : OUT std_logic; -- high active on A25
vme_scon : OUT std_logic; -- high active on A25
vme_sysfail_i_n : IN std_logic;
vme_sysfail_o : OUT std_logic; -- high active on A25
vme_bbsy_i_n : IN std_logic;
vme_bbsy_o : OUT std_logic; -- high active on A25
vme_bclr_i_n : IN std_logic; -- bus clear input
vme_bclr_o_n : OUT std_logic; -- bus clear output
vme_br_i_n : IN std_logic_vector(3 DOWNTO 0);
vme_br_o : OUT std_logic_vector(3 DOWNTO 0); -- high active on A25
vme_iack_i_n : IN std_logic;
vme_iack_o_n : OUT std_logic;
vme_acfail_i_n : IN std_logic;
vme_sysclk : OUT std_logic;
vme_bg_i_n : IN std_logic_vector(3 DOWNTO 0);
vme_bg_o_n : OUT std_logic_vector(3 DOWNTO 0);
-- Hard IP BFM connections
ep_rxvalid_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_rxstatus_i : in std_logic_vector(3*BFM_LANE_WIDTH -1 downto 0); -- 3bits per lane, [2:0]=lane0, [5:3]=lane1 etc.
ep_rxdatak_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bits per lane, [0]=lane0, [1]=lane1 etc.
ep_rxdata_i : in std_logic_vector(8*BFM_LANE_WIDTH -1 downto 0); -- 8bits per lane, [7:0]=lane0, [15:8]=lane1 etc.
ep_rxelecidle_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_phystatus_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_clk250_o : out std_logic; -- endpoint SERDES 250MHz clk output
ep_clk500_o : out std_logic; -- endpoint SERDES 500MHz clk output
ep_rate_ext_o : out std_logic; -- endpoint rate_ext
ep_powerdown_ext_o : out std_logic_vector(2*BFM_LANE_WIDTH -1 downto 0); -- 2bits per lane, [1:0]=lane0, [3:2]=lane1 etc.
ep_txdatak_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txdata_o : out std_logic_vector(8*BFM_LANE_WIDTH -1 downto 0); -- 8bits per lane, [7:0]=lane0, [15:8]=lane1 etc.
ep_txcompl_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txelecidle_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txdetectrx_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_rxpolarity_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_ltssm_o : out std_logic_vector(4 downto 0)
);
END A25_top;
ARCHITECTURE A25_top_arch OF A25_top IS
CONSTANT NR_OF_WB_SLAVES : natural range 63 DOWNTO 1 := 10;
COMPONENT ip_16z091_01_top
GENERIC(
SIMULATION : std_logic := '0'; -- =1 simulation,=0 synthesis
FPGA_FAMILY : family_type := NONE;
IRQ_WIDTH : integer range 32 downto 1 := 1;
-- only use one of the following 3:
-- 001 := 1 lane, 010 := 2 lanes, 100 := 4 lanes
USE_LANES : std_logic_vector(2 downto 0) := "001";
NR_OF_WB_SLAVES : natural range 63 DOWNTO 1 := 12;
NR_OF_BARS_USED : natural range 6 downto 1 := 5;
VENDOR_ID : natural := 16#1A88#;
DEVICE_ID : natural := 16#4D45#;
REVISION_ID : natural := 16#0#;
CLASS_CODE : natural := 16#068000#;
SUBSYSTEM_VENDOR_ID : natural := 16#9B#;
SUBSYSTEM_DEVICE_ID : natural := 16#5A91#;
BAR_MASK_0 : std_logic_vector(31 downto 0) := x"FF000008";
BAR_MASK_1 : std_logic_vector(31 downto 0) := x"FF000008";
BAR_MASK_2 : std_logic_vector(31 downto 0) := x"FF000000";
BAR_MASK_3 : std_logic_vector(31 downto 0) := x"FF000000";
BAR_MASK_4 : std_logic_vector(31 downto 0) := x"FF000001";
BAR_MASK_5 : std_logic_vector(31 downto 0) := x"FF000001";
PCIE_REQUEST_LENGTH : std_logic_vector(9 downto 0) := "0000100000"; -- 32DW = 128Byte
RX_LPM_WIDTHU : integer range 10 DOWNTO 5 := 10;
TX_HEADER_LPM_WIDTHU : integer range 10 DOWNTO 5 := 5;
TX_DATA_LPM_WIDTHU : integer range 10 DOWNTO 5 := 10;
BFM_LANE_WIDTH : integer range 8 downto 0 := 1; -- set configuration: 1=x1, 2=x2, 4=x4 and 8=x8
GP_DEBUG_PORT_WIDTH : positive := 1
);
PORT(
-- Hard IP ports:
clk_50 : in std_logic; -- 50 MHz clock for reconfig_clk and cal_blk_clk
clk_125 : in std_logic; -- 125 MHz clock for fixed_clk
ref_clk : in std_logic; -- 100 MHz reference clock
clk_500 : in std_logic; -- 500 Hz clock
ext_rst_n : in std_logic;
rx_0 : in std_logic;
rx_1 : in std_logic;
rx_2 : in std_logic;
rx_3 : in std_logic;
tx_0 : out std_logic;
tx_1 : out std_logic;
tx_2 : out std_logic;
tx_3 : out std_logic;
-- Wishbone ports:
wb_clk : in std_logic;
wb_rst : in std_logic;
-- Wishbone master
wbm_ack : in std_logic;
wbm_dat_i : in std_logic_vector(31 downto 0);
wbm_stb : out std_logic;
wbm_cyc_o : out std_logic_vector(NR_OF_WB_SLAVES - 1 downto 0);
wbm_we : out std_logic;
wbm_sel : out std_logic_vector(3 downto 0);
wbm_adr : out std_logic_vector(31 downto 0);
wbm_dat_o : out std_logic_vector(31 downto 0);
wbm_cti : out std_logic_vector(2 downto 0);
wbm_tga : out std_logic;
-- Wishbone slave
wbs_cyc : in std_logic;
wbs_stb : in std_logic;
wbs_we : in std_logic;
wbs_sel : in std_logic_vector(3 downto 0);
wbs_adr : in std_logic_vector(31 downto 0);
wbs_dat_i : in std_logic_vector(31 downto 0);
wbs_cti : in std_logic_vector(2 downto 0);
wbs_tga : in std_logic; -- 0: memory, 1: I/O
wbs_ack : out std_logic;
wbs_err : out std_logic;
wbs_dat_o : out std_logic_vector(31 downto 0);
-- interrupt
irq_req_i : in std_logic_vector(IRQ_WIDTH -1 downto 0);
-- error
error_timeout : out std_logic;
error_cor_ext_rcv : out std_logic_vector(1 downto 0);
error_cor_ext_rpl : out std_logic;
error_rpl : out std_logic;
error_r2c0 : out std_logic;
error_msi_num : out std_logic;
-- Hard IP BFM connections
ep_rxvalid_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_rxstatus_i : in std_logic_vector(3*BFM_LANE_WIDTH -1 downto 0); -- 3bits per lane, [2:0]=lane0, [5:3]=lane1 etc.
ep_rxdatak_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bits per lane, [0]=lane0, [1]=lane1 etc.
ep_rxdata_i : in std_logic_vector(8*BFM_LANE_WIDTH -1 downto 0); -- 8bits per lane, [7:0]=lane0, [15:8]=lane1 etc.
ep_rxelecidle_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_phystatus_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_clk250_o : out std_logic; -- endpoint SERDES 250MHz clk output
ep_clk500_o : out std_logic; -- endpoint SERDES 500MHz clk output
ep_rate_ext_o : out std_logic; -- endpoint rate_ext
ep_powerdown_ext_o : out std_logic_vector(2*BFM_LANE_WIDTH -1 downto 0); -- 2bits per lane, [1:0]=lane0, [3:2]=lane1 etc.
ep_txdatak_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txdata_o : out std_logic_vector(8*BFM_LANE_WIDTH -1 downto 0); -- 8bits per lane, [7:0]=lane0, [15:8]=lane1 etc.
ep_txcompl_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txelecidle_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txdetectrx_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_rxpolarity_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_ltssm_o : out std_logic_vector(4 downto 0);
-- debug port
gp_debug_port : out std_logic_vector(GP_DEBUG_PORT_WIDTH -1 downto 0); -- general purpose debug port
link_train_active : out std_logic
);
END COMPONENT;
COMPONENT wb_bus
GENERIC (
sets : std_logic_vector(3 DOWNTO 0) := "1110";
timeout : integer := 5000 );
PORT (
clk : IN std_logic;
rst : IN std_logic;
-- Master Bus
wbmo_0 : IN wbo_type;
wbmi_0 : OUT wbi_type;
wbmo_0_cyc : IN std_logic_vector(3 DOWNTO 0);
wbmo_1 : IN wbo_type;
wbmi_1 : OUT wbi_type;
wbmo_1_cyc : IN std_logic_vector(1 DOWNTO 0);
wbmo_2 : IN wbo_type;
wbmi_2 : OUT wbi_type;
wbmo_2_cyc : IN std_logic_vector(2 DOWNTO 0);
-- Slave Bus
wbso_0 : IN wbi_type;
wbsi_0 : OUT wbo_type;
wbsi_0_cyc : OUT std_logic;
wbso_1 : IN wbi_type;
wbsi_1 : OUT wbo_type;
wbsi_1_cyc : OUT std_logic;
wbso_2 : IN wbi_type;
wbsi_2 : OUT wbo_type;
wbsi_2_cyc : OUT std_logic;
wbso_3 : IN wbi_type;
wbsi_3 : OUT wbo_type;
wbsi_3_cyc : OUT std_logic;
wbso_4 : IN wbi_type;
wbsi_4 : OUT wbo_type;
wbsi_4_cyc : OUT std_logic
);
END COMPONENT;
COMPONENT pll_pcie
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC ;
c4 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT iram_wb
GENERIC
(
FPGA_FAMILY: family_type := CYCLONE; -- ACEX,CYCLONE,CYCLONE2,CYCLONE3,ARRIA_GX
read_only: natural := 0; -- 0=R/W, 1=R/O
USEDW_WIDTH: positive := 6; -- 2**(USEDW_WIDTH + 2) bytes
LOCATION: string := "iram.hex" -- string shall be empty if no HEX file
);
PORT
(
clk : IN std_logic; -- Wishbone clock
rst : IN std_logic; -- global async high active reset
-- Wishbone signals
stb_i : IN std_logic; -- request
cyc_i : IN std_logic; -- chip select
ack_o : OUT std_logic; -- acknowledge
err_o : OUT std_logic; -- error
we_i : IN std_logic; -- write=1 read=0
sel_i : IN std_logic_vector(3 DOWNTO 0); -- byte enables
adr_i : IN std_logic_vector((USEDW_WIDTH + 1) DOWNTO 2);
dat_i : IN std_logic_vector(31 DOWNTO 0); -- data in
dat_o : OUT std_logic_vector(31 DOWNTO 0) -- data out
);
END COMPONENT;
COMPONENT sram
PORT (
clk66 : IN std_logic; -- 66 MHz
rst : IN std_logic; -- global reset signal (asynch)
-- local bus
stb_i : IN std_logic;
ack_o : OUT std_logic;
we_i : IN std_logic; -- high active write enable
sel_i : IN std_logic_vector(3 DOWNTO 0); -- high active byte enables
cyc_i : IN std_logic;
dat_o : OUT std_logic_vector(31 DOWNTO 0);
dat_i : IN std_logic_vector(31 DOWNTO 0);
adr_i : IN std_logic_vector(19 DOWNTO 0);
-- pins to sram
bwn : OUT std_logic; -- global byte write enable:
bwan : OUT std_logic; -- byte a write enable:
bwbn : OUT std_logic; -- byte b write enable:
adscn : OUT std_logic; -- Synchronous Address Status Controller: .
roen : OUT std_logic; -- data port output enable: .
ra : OUT std_logic_vector(18 DOWNTO 0); -- address lines:
rd_in : IN std_logic_vector(15 DOWNTO 0); -- data lines:
rd_out : OUT std_logic_vector(15 DOWNTO 0); -- data lines:
rd_oe : OUT std_logic
);
END COMPONENT;
COMPONENT z126_01_top
GENERIC (
SIMULATION : boolean := FALSE; -- true => use the altasmi parallel of an older quartus version (11.1 SP2) the new one can not be simulated
-- (only the M25P32 is supported for simulation!!)
-- false => use the newest altasmi parallel (13.0)
FPGA_FAMILY : family_type := CYCLONE5; -- see SUPPORTED_FPGA_FAMILIES for supported FPGA family types
FLASH_TYPE : flash_type := M25P32; -- see SUPPORTED_DEVICES for supported serial flash device types
USE_DIRECT_INTERFACE : boolean := TRUE; -- true => the direct interfaces is included and arbitrated with the indirect interface
-- false => only the indirect interface is available (reducing resource consumption)
USE_REMOTE_UPDATE : boolean := TRUE; -- true => the remote update controller is included and more than one FPGA image can be selected
-- false => only the FPGA Fallback Image can be used for FPGA configuration (reducing resource consumption)
LOAD_FPGA_IMAGE : boolean := TRUE; -- true => after configuration of the FPGA Fallback Image the FPGA Image is loaded immediately (can only be set when USE_REMOTE_UPDATE = TRUE)
-- false => after configuration the FPGA stays in the FPGA Fallback Image, FPGA Image must be loaded by software
LOAD_FPGA_IMAGE_ADR : std_logic_vector(23 DOWNTO 0) := (OTHERS=>'0') -- if LOAD_FPGA_IMAGE = TRUE this address is the offset to the FPGA Image in the serial flash
);
PORT (
clk_40mhz : IN std_logic; -- serial flash clock (maximum 40 MHz)
rst_clk_40mhz : IN std_logic; -- this reset should be a power up reset to
-- reduce the reconfiguration (load FPGA Image) time when LOAD_FPGA_IMAGE = TRUE.
-- this reset must be deasserted synchronous to the clk_40mhz
clk_dir : IN std_logic; -- wishbone clock for direct interface
rst_dir : IN std_logic; -- wishbone async high active reset
-- this reset must be deasserted synchronous to the clk_dir
clk_indi : IN std_logic; -- wishbone clock for indirect interface
rst_indi : IN std_logic; -- wishbone async high active reset
-- this reset must be deasserted synchronous to the clk_indi
board_status : OUT std_logic_vector(1 DOWNTO 0);
-- wishbone signals slave interface 0 (direct addressing)
wbs_stb_dir : IN std_logic; -- request
wbs_ack_dir : OUT std_logic; -- acknoledge
wbs_we_dir : IN std_logic; -- write=1 read=0
wbs_sel_dir : IN std_logic_vector(3 DOWNTO 0); -- byte enables
wbs_cyc_dir : IN std_logic; -- chip select
wbs_dat_o_dir : OUT std_logic_vector(31 DOWNTO 0); -- data out
wbs_dat_i_dir : IN std_logic_vector(31 DOWNTO 0); -- data in
wbs_adr_dir : IN std_logic_vector(31 DOWNTO 0); -- address
wbs_err_dir : OUT std_logic; -- error
-- wishbone signals slave interface 1 (indirect addressing)
wbs_stb_indi : IN std_logic; -- request
wbs_ack_indi : OUT std_logic; -- acknoledge
wbs_we_indi : IN std_logic; -- write=1 read=0
wbs_sel_indi : IN std_logic_vector(3 DOWNTO 0); -- byte enables
wbs_cyc_indi : IN std_logic; -- chip select
wbs_dat_o_indi : OUT std_logic_vector(31 DOWNTO 0); -- data out
wbs_dat_i_indi : IN std_logic_vector(31 DOWNTO 0); -- data in
wbs_adr_indi : IN std_logic_vector(31 DOWNTO 0); -- address
wbs_err_indi : OUT std_logic -- error
);
END COMPONENT;
COMPONENT wbb2vme_top
GENERIC (
A16_REG_MAPPING : boolean := TRUE; -- if true, access to vme slave A16 space goes to vme runtime registers and above 0x800 to sram (compatible to old revisions)
-- if false, access to vme slave A16 space goes to sram
LONGADD_SIZE : integer range 3 TO 8:=3;
USE_LONGADD : boolean := TRUE -- If FALSE, bits (7 DOWNTO 5) of SIGNAL longadd will be allocated to vme_adr_out(31 DOWNTO 29)
);
PORT (
clk : IN std_logic; -- 66 MHz
rst : IN std_logic; -- global reset signal (asynch)
startup_rst : IN std_logic; -- powerup reset
postwr : OUT std_logic; -- posted write
vme_irq : OUT std_logic_vector(7 DOWNTO 0); -- interrupt request to pci-bus
berr_irq : OUT std_logic; -- signal berrn interrupt request
locmon_irq : OUT std_logic_vector(1 DOWNTO 0); -- interrupt request location monitor to pci-bus
mailbox_irq : OUT std_logic_vector(1 DOWNTO 0); -- interrupt request mailbox to pci-bus
dma_irq : OUT std_logic; -- interrupt request dma to pci-bus
prevent_sysrst : IN std_logic; -- if "1", sysrst_n_out will not be activated after powerup,
-- if "0", sysrst_n_out will be activated if in slot1 and system reset is active (sysc_bit or rst)
test_vec : OUT test_vec_type;
-- vmectrl slave
wbs_stb_i : IN std_logic;
wbs_ack_o : OUT std_logic;
wbs_err_o : OUT std_logic;
wbs_we_i : IN std_logic;
wbs_sel_i : IN std_logic_vector(3 DOWNTO 0);
wbs_cyc_i : IN std_logic;
wbs_adr_i : IN std_logic_vector(31 DOWNTO 0);
wbs_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbs_dat_i : IN std_logic_vector(31 DOWNTO 0);
wbs_tga_i : IN std_logic_vector(8 DOWNTO 0);
-- vmectrl master
wbm_ctrl_stb_o : OUT std_logic;
wbm_ctrl_ack_i : IN std_logic;
wbm_ctrl_err_i : IN std_logic;
wbm_ctrl_we_o : OUT std_logic;
wbm_ctrl_sel_o : OUT std_logic_vector(3 DOWNTO 0);
wbm_ctrl_cyc_sram : OUT std_logic;
wbm_ctrl_cyc_pci : OUT std_logic;
wbm_ctrl_adr_o : OUT std_logic_vector(31 DOWNTO 0);
wbm_ctrl_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbm_ctrl_dat_i : IN std_logic_vector(31 DOWNTO 0);
wbm_dma_stb_o : OUT std_logic;
wbm_dma_ack_i : IN std_logic;
wbm_dma_we_o : OUT std_logic;
wbm_dma_cti : OUT std_logic_vector(2 DOWNTO 0);
wbm_dma_tga_o : OUT std_logic_vector(8 DOWNTO 0);
wbm_dma_err_i : IN std_logic;
wbm_dma_sel_o : OUT std_logic_vector(3 DOWNTO 0);
wbm_dma_cyc_sram : OUT std_logic;
wbm_dma_cyc_vme : OUT std_logic;
wbm_dma_cyc_pci : OUT std_logic;
wbm_dma_adr_o : OUT std_logic_vector(31 DOWNTO 0);
wbm_dma_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbm_dma_dat_i : IN std_logic_vector(31 DOWNTO 0);
-- vmebus
va : INOUT std_logic_vector(31 DOWNTO 0); -- address
vd : INOUT std_logic_vector(31 DOWNTO 0); -- data
vam : INOUT std_logic_vector(5 DOWNTO 0); -- address modifier
writen : INOUT std_logic; -- write enable
iackn : INOUT std_logic; -- Handler's output
irq_i_n : IN std_logic_vector(7 DOWNTO 1); -- interrupt request inputs
irq_o_n : OUT std_logic_vector(7 DOWNTO 1); -- interrupt request outputs
as_o_n : OUT std_logic; -- address strobe out
as_oe_n : OUT std_logic; -- address strobe output enable
as_i_n : IN std_logic; -- address strobe in
sysresn : OUT std_logic; -- system reset out
sysresin : IN std_logic; -- system reset in
ds_o_n : OUT std_logic_vector(1 DOWNTO 0); -- data strobe outputs
ds_i_n : IN std_logic_vector(1 DOWNTO 0); -- data strobe inputs
ds_oe_n : OUT std_logic; -- data strobe output enable
berrn : OUT std_logic; -- bus error out
berrin : IN std_logic; -- bus error in
dtackn : OUT std_logic; -- dtack out
dtackin : IN std_logic; -- dtack in
slot01n : OUT std_logic; -- indicates whether controller has detected position in slot 1 (low active)
sysfail_i_n : IN std_logic; -- system failure interrupt input
sysfail_o_n : OUT std_logic; -- system failure interrupt output
bbsyn : OUT std_logic; -- bus busy out
bbsyin : IN std_logic; -- bus busy in
bclr_i_n : IN std_logic; -- bus clear input
bclr_o_n : OUT std_logic; -- bus clear output
retry_i_n : IN std_logic; -- bus retry input
retry_o_n : OUT std_logic; -- bus retry output
retry_oe_n : OUT std_logic; -- bus retry output enable
br_i_n : IN std_logic_vector(3 DOWNTO 0); -- bus request inputs
br_o_n : OUT std_logic_vector(3 DOWNTO 0); -- bus request outputs
iackin : IN std_logic; -- Interrupter's input
iackoutn : OUT std_logic; -- Interrupter's output
acfailn : IN std_logic; -- from Power Supply
bg_i_n : IN std_logic_vector(3 DOWNTO 0); -- bus grant input
bg_o_n : OUT std_logic_vector(3 DOWNTO 0); -- bus grant output
ga : IN std_logic_vector(4 DOWNTO 0); -- geographical addresses
gap : IN std_logic; -- geographical addresses parity
-- vme status signals
vme_berr : OUT std_logic; -- indicates vme bus error (=MSTR(2)), must be cleared by sw
vme_mstr_busy : OUT std_logic; -- indicates vme bus master is active
--data bus bus control signals for vmebus drivers
d_dir : OUT std_logic; -- external driver control data direction (1: drive to vmebus 0: drive to fpga)
d_oe_n : OUT std_logic; -- external driver control data output enable low active
am_dir : OUT std_logic; -- external driver control address modifier direction (1: drive to vmebus 0: drive to fpga)
am_oe_n : OUT std_logic; -- external driver control address modifier output enable low activ
a_dir : OUT std_logic; -- external driver control address direction (1: drive to vmebus 0: drive to fpga)
a_oe_n : OUT std_logic; -- external driver control address output enable low activ
v2p_rstn : OUT std_logic -- Reset from VMEbus to System on board
);
END COMPONENT;
CONSTANT CONST_500HZ : integer := 66667; -- half 500Hz clock period counter value at 66MHz
SIGNAL sys_clk : std_logic; -- system clock 66 MHz
SIGNAL sys_rst : std_logic; -- system async reset
SIGNAL rst_33 : std_logic; -- reset synchronized to clk_33
SIGNAL clk_33 : std_logic; -- 33 MHz clock for 16z066
SIGNAL clk_50 : std_logic; -- 50 MHz clock for reconfig_clk and cal_blk_clk
SIGNAL clk_125 : std_logic; -- 125 MHz clock for fixed_clk
SIGNAL clk_500 : std_logic; -- 500 Hz clock
SIGNAL cnt_500hz : integer;
-- MASTER SIGNALS
SIGNAL wbmo_0 : wbo_type;
SIGNAL wbmi_0 : wbi_type;
SIGNAL wbmo_0_cyc : std_logic_vector(3 DOWNTO 0);
SIGNAL wbmo_0_cyc_int : std_logic_vector(9 DOWNTO 0);
SIGNAL wbmo_1 : wbo_type;
SIGNAL wbmi_1 : wbi_type;
SIGNAL wbmo_1_cyc : std_logic_vector(1 DOWNTO 0);
SIGNAL wbmo_2 : wbo_type;
SIGNAL wbmi_2 : wbi_type;
SIGNAL wbmo_2_cyc : std_logic_vector(2 DOWNTO 0);
-- SLAVE SIGNALS
SIGNAL wbso_0 : wbi_type;
SIGNAL wbsi_0 : wbo_type;
SIGNAL wbsi_0_cyc : std_logic;
SIGNAL wbso_1 : wbi_type;
SIGNAL wbsi_1 : wbo_type;
SIGNAL wbsi_1_cyc : std_logic;
SIGNAL wbso_2 : wbi_type;
SIGNAL wbsi_2 : wbo_type;
SIGNAL wbsi_2_cyc : std_logic;
SIGNAL wbso_3 : wbi_type;
SIGNAL wbsi_3 : wbo_type;
SIGNAL wbsi_3_cyc : std_logic;
SIGNAL wbso_4 : wbi_type;
SIGNAL wbsi_4 : wbo_type;
SIGNAL wbsi_4_cyc : std_logic;
SIGNAL pll_locked : std_logic;
SIGNAL sr_d_oe : std_logic;
SIGNAL board_status : std_logic_vector(1 DOWNTO 0);
SIGNAL sr_d_out : std_logic_vector(15 DOWNTO 0);
SIGNAL sr_d_in : std_logic_vector(15 DOWNTO 0);
SIGNAL vme_irq : std_logic_vector(7 DOWNTO 0); -- interrupt request to pci-bus
SIGNAL berr_irq : std_logic; -- signal berrn interrupt request
SIGNAL locmon_irq : std_logic_vector(1 DOWNTO 0); -- interrupt request location monitor to pci-bus
SIGNAL mailbox_irq : std_logic_vector(1 DOWNTO 0); -- interrupt request mailbox to pci-bus
SIGNAL mailbox_irq_i : std_logic;
SIGNAL dma_irq : std_logic;
SIGNAL slot01n : std_logic;
SIGNAL test_vec : test_vec_type;
SIGNAL pll_locked_inv : std_logic;
SIGNAL startup_rst : std_logic:='1';
SIGNAL porst : std_logic;
SIGNAL porst_n_q : std_logic:='0';
SIGNAL porst_n : std_logic:='0';
SIGNAL link_train_active : std_logic;
SIGNAL vme_berr : std_logic;
SIGNAL vme_mstr_busy : std_logic;
SIGNAL led_cnt : std_logic_vector(17 DOWNTO 0); -- 2^18 = 3.9 ms
-- high active signals on A25
SIGNAL vme_irq_o_n : std_logic_vector(7 DOWNTO 1);
SIGNAL vme_as_oe_n : std_logic;
SIGNAL vme_retry_oe_n : std_logic;
SIGNAL vme_sysres_o_n : std_logic;
SIGNAL vme_ds_oe_n : std_logic;
SIGNAL vme_scon_n : std_logic;
SIGNAL vme_sysfail_o_n : std_logic;
SIGNAL vme_bbsy_o_n : std_logic;
SIGNAL vme_dtack_o_n : std_logic;
SIGNAL vme_berr_o_n : std_logic;
SIGNAL vme_br_o_n : std_logic_vector(3 DOWNTO 0);
BEGIN
vme_irq_o <= NOT vme_irq_o_n ;
vme_as_oe <= NOT vme_as_oe_n ;
vme_retry_oe <= NOT vme_retry_oe_n ;
vme_sysres_o <= NOT vme_sysres_o_n ;
vme_ds_oe <= NOT vme_ds_oe_n ;
vme_scon <= NOT vme_scon_n ;
vme_sysfail_o <= NOT vme_sysfail_o_n;
vme_bbsy_o <= NOT vme_bbsy_o_n ;
vme_br_o <= NOT vme_br_o_n ;
vme_berr_o <= NOT vme_berr_o_n;
vme_dtack_o <= NOT vme_dtack_o_n;
led_red_n <= NOT vme_berr;
-- led_green_n <= slot01;
vme_sysclk <= clk_16mhz;
vme_scon_n <= slot01n;
-- counter for extending vme master active pulses to at least 3 ms
PROCESS(sys_clk, sys_rst)
BEGIN
IF sys_rst = '1' THEN
led_cnt <= (OTHERS => '0');
led_green_n <= '1';
ELSIF sys_clk'event AND sys_clk = '1' THEN
IF vme_mstr_busy = '1' THEN -- if master is active, start counter to extend pulse for 3 ms
led_cnt <= (OTHERS => '1');
led_green_n <= '0'; -- switch on LED
ELSIF led_cnt = 0 THEN -- is 3 ms over?
led_cnt <= (OTHERS => '0');
led_green_n <= '1'; -- switch off LED
ELSE
led_cnt <= led_cnt - '1'; -- count for 3 ms
led_green_n <= '0';
END IF;
END IF;
END PROCESS;
pll_locked_inv <= NOT pll_locked;
startup_rst <= pll_locked_inv;
wbso_3.err <= '0';
wbso_4.err <= '0';
wbmo_0.bte <= "00";
wbmo_1.bte <= "00";
wbmo_2.bte <= "00";
wbmo_1.cti <= "000";
fpga_test(1) <= 'Z';
fpga_test(2) <= 'Z';
fpga_test(3) <= 'Z';
fpga_test(4) <= 'Z';
fpga_test(5) <= 'Z';
-- generate power on reset in order to start application fpga load as early as possible
PROCESS (clk_16mhz)
BEGIN
IF clk_16mhz'EVENT AND clk_16mhz = '1' THEN
porst_n_q <= '1';
porst_n <= porst_n_q;
END IF;
END PROCESS;
porst <= NOT porst_n;
-- synchronize reset to 33 MHz clock
PROCESS(clk_33, pll_locked)
BEGIN
IF pll_locked = '0' THEN
rst_33 <= '1';
ELSIF clk_33'EVENT AND clk_33 = '1' THEN
rst_33 <= '0';
END IF;
END PROCESS;
PROCESS(sys_clk, hreset_n, pll_locked)
BEGIN
IF hreset_n = '0' OR pll_locked = '0' THEN
sys_rst <= '1';
ELSIF sys_clk'EVENT AND sys_clk = '1' THEN
sys_rst <= '0';
END IF;
END PROCESS;
PROCESS(sys_clk, sys_rst)
BEGIN
IF sys_rst = '1' THEN
cnt_500hz <= 0;
clk_500 <= '0';
ELSIF sys_clk'EVENT AND sys_clk = '1' THEN
IF cnt_500hz = 0 THEN
cnt_500hz <= CONST_500HZ;
clk_500 <= NOT clk_500;
ELSE
cnt_500hz <= cnt_500hz - 1;
END IF;
END IF;
END PROCESS;
pll: pll_pcie
PORT MAP (
areset => porst,
inclk0 => clk_16mhz, -- 16 MHz
c0 => clk_125, -- 125 MHz
c1 => clk_50, -- 50 MHz
c2 => sys_clk, -- 66 MHz
c3 => sr_clk, -- 66 MHz phase shifted to sys_clk
c4 => clk_33, -- 33 MHz
locked => pll_locked
);
wbmo_0_cyc <= -- +-Module Name--------------+-cyc-+---offset-+-----size-+-bar-+
"0001" WHEN wbmo_0_cyc_int(0) = '1' ELSE -- | Chameleon Table | 0 | 0 | 200 | 0 |
"0010" WHEN wbmo_0_cyc_int(1) = '1' ELSE -- | 16Z126_SERFLASH | 1 | 200 | 20 | 0 |
"0100" WHEN wbmo_0_cyc_int(2) = '1' ELSE -- | 16z002-01 VME | 2 | 10000 | 10000 | 0 |
"0100" WHEN wbmo_0_cyc_int(3) = '1' ELSE -- |16z002-01 VME A16D16 | 3 | 20000 | 10000 | 0 |
"0100" WHEN wbmo_0_cyc_int(4) = '1' ELSE -- |16z002-01 VME A16D32 | 4 | 30000 | 10000 | 0 |
"1000" WHEN wbmo_0_cyc_int(5) = '1' ELSE -- | 16z002-01 VME SRAM | 5 | 0 | 100000 | 1 |
"0100" WHEN wbmo_0_cyc_int(6) = '1' ELSE -- |16z002-01 VME A24D16 | 6 | 0 | 1000000 | 2 |
"0100" WHEN wbmo_0_cyc_int(7) = '1' ELSE -- |16z002-01 VME A24D32 | 7 | 1000000 | 1000000 | 2 |
"0100" WHEN wbmo_0_cyc_int(8) = '1' ELSE -- | 16z002-01 VME A32 | 8 | 0 | 20000000 | 3 |
"0100" WHEN wbmo_0_cyc_int(9) = '1' ELSE -- |16z002-01 VME CR/CSR | 9 | 0 | 01000000 | 4 |
"0000"; -- +--------------------------+-----+----------+----------+-----+
wbmo_1.tga <= (OTHERS => '0');
wbmo_0.tga(7) <= '0'; -- indicate access from PCIE
wbmo_0.tga(8) <= '0'; -- unused
wbmo_0.tga(6 DOWNTO 0) <= -- +-Module Name--------------+-cyc-+---offset-+-----size-+-bar-+
CONST_VME_A24D16 WHEN wbmo_0_cyc_int(6) = '1' ELSE -- |16z002-01 VME A24D16 | 6 | 0 | 1000000 | 2 |
CONST_VME_A16D16 WHEN wbmo_0_cyc_int(3) = '1' ELSE -- |16z002-01 VME A16D16 | 3 | 20000 | 10000 | 0 |
CONST_VME_A16D32 WHEN wbmo_0_cyc_int(4) = '1' ELSE -- |16z002-01 VME A16D32 | 4 | 30000 | 10000 | 0 |
CONST_VME_IACK WHEN wbmo_0_cyc_int(2) = '1'
AND wbmo_0.adr(8) = '1' ELSE -- |16z002-01 VME IACK | 2 | 10100 | 10 | 0 |
CONST_VME_REGS WHEN wbmo_0_cyc_int(2) = '1' ELSE -- |16z002-01 VME REGS | 2 | 10000 | 10000 | 0 |
CONST_VME_A32D32 WHEN wbmo_0_cyc_int(8) = '1' ELSE -- |16z002-01 VME A32 | 8 | 0 | 20000000 | 3 |
CONST_VME_A24D32 WHEN wbmo_0_cyc_int(7) = '1' ELSE -- |16z002-01 VME A24D32 | 7 | 1000000 | 1000000 | 2 |
CONST_VME_CRCSR WHEN wbmo_0_cyc_int(9) = '1' ELSE -- |16z002-01 VME CRCSR | 9 | 0 | 1000000 | 4 |
(OTHERS => '0'); -- +--------------------------+-----+----------+----------+-----+
pcie: ip_16z091_01_top
GENERIC MAP (
SIMULATION => '1',
FPGA_FAMILY => CYCLONE4,
IRQ_WIDTH => 13,
USE_LANES => "001",-- x1 for simulation
--USE_LANES => "100",-- x1 for simulation
NR_OF_WB_SLAVES => NR_OF_WB_SLAVES,
NR_OF_BARS_USED => 5,
VENDOR_ID => 16#1A88#,
DEVICE_ID => 16#4D45#,
REVISION_ID => 16#1#,
CLASS_CODE => 16#068000#,
SUBSYSTEM_VENDOR_ID => 16#D5#,
SUBSYSTEM_DEVICE_ID => 16#5A91#,
BAR_MASK_0 => x"FFFC0000", -- 256k
BAR_MASK_1 => x"FFF00000", -- 1M
BAR_MASK_2 => x"FE000000", -- 32M
BAR_MASK_3 => x"E0000000", -- 512M
BAR_MASK_4 => x"FF000000", -- 16M
BAR_MASK_5 => x"FFFFF000",
PCIE_REQUEST_LENGTH => "0000100000", -- 32DW = 128Byte
RX_LPM_WIDTHU => 10,
TX_HEADER_LPM_WIDTHU => 5,
TX_DATA_LPM_WIDTHU => 10,
BFM_LANE_WIDTH => BFM_LANE_WIDTH,
GP_DEBUG_PORT_WIDTH => 1
)
PORT MAP (
-- Hard IP ports:
clk_50 => clk_50,
clk_125 => clk_125,
ref_clk => refclk,
clk_500 => clk_500,
ext_rst_n => hreset_n,
rx_0 => pcie_rx(0),
rx_1 => pcie_rx(1),
rx_2 => pcie_rx(2),
rx_3 => pcie_rx(3),
tx_0 => pcie_tx(0),
tx_1 => pcie_tx(1),
tx_2 => pcie_tx(2),
tx_3 => pcie_tx(3),
wb_clk => sys_clk,
wb_rst => sys_rst,
wbm_ack => wbmi_0.ack,
wbm_dat_i => wbmi_0.dat,
wbm_stb => wbmo_0.stb,
wbm_cyc_o => wbmo_0_cyc_int,
wbm_we => wbmo_0.we ,
wbm_sel => wbmo_0.sel,
wbm_adr => wbmo_0.adr,
wbm_dat_o => wbmo_0.dat,
wbm_cti => wbmo_0.cti,
wbm_tga => open,
wbs_cyc => wbsi_4_cyc,
wbs_stb => wbsi_4.stb,
wbs_we => wbsi_4.we ,
wbs_sel => wbsi_4.sel,
wbs_adr => wbsi_4.adr,
wbs_dat_i => wbsi_4.dat,
wbs_cti => wbsi_4.cti,
wbs_tga => wbsi_4.tga(0),
wbs_ack => wbso_4.ack,
wbs_err => open,
wbs_dat_o => wbso_4.dat,
irq_req_i(0) => vme_irq(0) ,
irq_req_i(1) => vme_irq(1) ,
irq_req_i(2) => vme_irq(2) ,
irq_req_i(3) => vme_irq(3) ,
irq_req_i(4) => vme_irq(4) ,
irq_req_i(5) => vme_irq(5) ,
irq_req_i(6) => vme_irq(6) ,
irq_req_i(7) => vme_irq(7) ,
irq_req_i(8) => berr_irq ,
irq_req_i(9) => dma_irq ,
irq_req_i(10) => locmon_irq(0) ,
irq_req_i(11) => locmon_irq(1) ,
irq_req_i(12) => mailbox_irq_i ,
error_timeout => open,
error_cor_ext_rcv => open,
error_cor_ext_rpl => open,
error_rpl => open,
error_r2c0 => open,
error_msi_num => open,
-- Hard IP BFM connections
ep_rxvalid_i => ep_rxvalid_i,
ep_rxstatus_i => ep_rxstatus_i,
ep_rxdatak_i => ep_rxdatak_i,
ep_rxdata_i => ep_rxdata_i,
ep_rxelecidle_i => ep_rxelecidle_i,
ep_phystatus_i => ep_phystatus_i,
ep_clk250_o => ep_clk250_o,
ep_clk500_o => ep_clk500_o,
ep_rate_ext_o => ep_rate_ext_o,
ep_powerdown_ext_o => ep_powerdown_ext_o,
ep_txdatak_o => ep_txdatak_o,
ep_txdata_o => ep_txdata_o,
ep_txcompl_o => ep_txcompl_o,
ep_txelecidle_o => ep_txelecidle_o,
ep_txdetectrx_o => ep_txdetectrx_o,
ep_rxpolarity_o => ep_rxpolarity_o,
ep_ltssm_o => ep_ltssm_o,
gp_debug_port => open,
link_train_active => link_train_active
);
mailbox_irq_i <= mailbox_irq(0) OR mailbox_irq(1);
cham: iram_wb
GENERIC MAP (
FPGA_FAMILY => FPGA_FAMILY,
read_only => 1,
USEDW_WIDTH => 9, -- 0x200 = 512
LOCATION => "../../A25_VME/Source/chameleon.hex"
)
PORT MAP (
clk => sys_clk,
rst => sys_rst,
stb_i => wbsi_0.stb,
cyc_i => wbsi_0_cyc,
ack_o => wbso_0.ack,
err_o => wbso_0.err,
we_i => wbsi_0.we,
sel_i => wbsi_0.sel,
adr_i => wbsi_0.adr(10 DOWNTO 2),
dat_i => wbsi_0.dat,
dat_o => wbso_0.dat
);
srami: sram
PORT MAP (
clk66 => sys_clk,
rst => sys_rst,
stb_i => wbsi_3.stb,
ack_o => wbso_3.ack,
we_i => wbsi_3.we,
sel_i => wbsi_3.sel,
cyc_i => wbsi_3_cyc,
dat_o => wbso_3.dat,
dat_i => wbsi_3.dat,
adr_i => wbsi_3.adr(19 DOWNTO 0),
bwn => sr_bw_n,
bwan => sr_bwa_n,
bwbn => sr_bwb_n,
adscn => sr_adsc_n,
roen => sr_oe_n,
ra => sr_a,
rd_in => sr_d_in,
rd_out => sr_d_out,
rd_oe => sr_d_oe
);
sr_cs1_n <= '0'; --sys_rst; -- selected if FPGA reset is released
srdat: PROCESS(sr_d_oe, sr_d_out, sr_d)
BEGIN
IF sr_d_oe = '1' THEN
sr_d <= sr_d_out;
sr_d_in <= sr_d;
ELSE
sr_d <= (OTHERS => 'Z');
sr_d_in <= sr_d;
END IF;
END PROCESS;
sflash: z126_01_top
GENERIC MAP (
SIMULATION => true,
FPGA_FAMILY => CYCLONE4,
FLASH_TYPE => M25P32,
USE_DIRECT_INTERFACE => FALSE,
USE_REMOTE_UPDATE => TRUE,
LOAD_FPGA_IMAGE => TRUE,
LOAD_FPGA_IMAGE_ADR => X"200100"
)
PORT MAP (
clk_40mhz => clk_33,
rst_clk_40mhz => rst_33,
clk_dir => sys_clk,
rst_dir => sys_rst,
clk_indi => sys_clk,
rst_indi => sys_rst,
board_status => board_status,
wbs_stb_dir => '0',
wbs_ack_dir => OPEN,
wbs_we_dir => '0',
wbs_sel_dir => (OTHERS => '0'),
wbs_cyc_dir => '0',
wbs_dat_o_dir => OPEN,
wbs_dat_i_dir => (OTHERS => '0'),
wbs_adr_dir => (OTHERS => '0'),
wbs_err_dir => OPEN,
-- wishbone signals slave interface 1 (indirect addressing)
wbs_stb_indi => wbsi_1.stb,
wbs_ack_indi => wbso_1.ack,
wbs_we_indi => wbsi_1.we,
wbs_sel_indi => wbsi_1.sel,
wbs_cyc_indi => wbsi_1_cyc,
wbs_dat_o_indi => wbso_1.dat,
wbs_dat_i_indi => wbsi_1.dat,
wbs_adr_indi => wbsi_1.adr,
wbs_err_indi => wbso_1.err
);
vme: wbb2vme_top
GENERIC MAP(
A16_REG_MAPPING => true,
LONGADD_SIZE => 3,
USE_LONGADD => TRUE
)
PORT MAP (
clk => sys_clk,
rst => sys_rst,
startup_rst => startup_rst,
postwr => open,
vme_irq => vme_irq ,
berr_irq => berr_irq,
locmon_irq => locmon_irq ,
mailbox_irq => mailbox_irq,
dma_irq => dma_irq ,
prevent_sysrst => '0',
test_vec => test_vec,
-- vmectrl slave
wbs_stb_i => wbsi_2.stb,
wbs_ack_o => wbso_2.ack,
wbs_err_o => wbso_2.err,
wbs_we_i => wbsi_2.we,
wbs_sel_i => wbsi_2.sel,
wbs_cyc_i => wbsi_2_cyc,
wbs_adr_i => wbsi_2.adr,
wbs_dat_o => wbso_2.dat,
wbs_dat_i => wbsi_2.dat,
wbs_tga_i => wbsi_2.tga,
-- vmectrl master
wbm_ctrl_stb_o => wbmo_1.stb,
wbm_ctrl_ack_i => wbmi_1.ack,
wbm_ctrl_err_i => wbmi_1.err,
wbm_ctrl_we_o => wbmo_1.we,
wbm_ctrl_sel_o => wbmo_1.sel,
wbm_ctrl_cyc_sram => wbmo_1_cyc(0),
wbm_ctrl_cyc_pci => wbmo_1_cyc(1),
wbm_ctrl_adr_o => wbmo_1.adr,
wbm_ctrl_dat_o => wbmo_1.dat,
wbm_ctrl_dat_i => wbmi_1.dat,
wbm_dma_stb_o => wbmo_2.stb,
wbm_dma_ack_i => wbmi_2.ack,
wbm_dma_we_o => wbmo_2.we,
wbm_dma_cti => wbmo_2.cti,
wbm_dma_tga_o => wbmo_2.tga,
wbm_dma_err_i => wbmi_2.err,
wbm_dma_sel_o => wbmo_2.sel,
wbm_dma_cyc_vme => wbmo_2_cyc(0),
wbm_dma_cyc_sram => wbmo_2_cyc(1),
wbm_dma_cyc_pci => wbmo_2_cyc(2),
wbm_dma_adr_o => wbmo_2.adr,
wbm_dma_dat_o => wbmo_2.dat,
wbm_dma_dat_i => wbmi_2.dat,
va => vme_a,
vd => vme_d,
vam => vme_am,
writen => vme_write_n,
iackn => vme_iack_n,
irq_i_n => vme_irq_i_n,
irq_o_n => vme_irq_o_n,
as_o_n => vme_as_o_n,
as_oe_n => vme_as_oe_n,
as_i_n => vme_as_i_n,
sysresn => vme_sysres_o_n,
sysresin => vme_sysres_i_n,
ds_o_n => vme_ds_o_n,
ds_i_n => vme_ds_i_n,
ds_oe_n => vme_ds_oe_n,
berrn => vme_berr_o_n,
berrin => vme_berr_i_n,
dtackn => vme_dtack_o_n,
dtackin => vme_dtack_i_n,
slot01n => slot01n,
sysfail_i_n => vme_sysfail_i_n,
sysfail_o_n => vme_sysfail_o_n,
bbsyn => vme_bbsy_o_n,
bbsyin => vme_bbsy_i_n,
bclr_i_n => vme_bclr_i_n,
bclr_o_n => vme_bclr_o_n,
retry_i_n => vme_retry_i_n ,
retry_o_n => vme_retry_o_n ,
retry_oe_n => vme_retry_oe_n ,
br_i_n => vme_br_i_n,
br_o_n => vme_br_o_n,
iackin => vme_iack_i_n,
iackoutn => vme_iack_o_n,
acfailn => vme_acfail_i_n,
bg_i_n => vme_bg_i_n,
bg_o_n => vme_bg_o_n,
ga => vme_ga,
gap => vme_gap,
vme_berr => vme_berr,
vme_mstr_busy => vme_mstr_busy,
d_dir => vme_d_dir ,
d_oe_n => vme_d_oe_n ,
am_dir => vme_am_dir ,
am_oe_n => vme_am_oe_n,
a_dir => vme_a_dir ,
a_oe_n => vme_a_oe_n ,
v2p_rstn => v2p_rstn
);
wbb : wb_bus
GENERIC MAP (
sets => sets,
timeout => timeout
)
PORT MAP (
clk => sys_clk,
rst => sys_rst,
wbmo_0 => wbmo_0,
wbmi_0 => wbmi_0,
wbmo_0_cyc => wbmo_0_cyc,
wbmo_1 => wbmo_1,
wbmi_1 => wbmi_1,
wbmo_1_cyc => wbmo_1_cyc,
wbmo_2 => wbmo_2,
wbmi_2 => wbmi_2,
wbmo_2_cyc => wbmo_2_cyc,
wbso_0 => wbso_0,
wbsi_0 => wbsi_0,
wbsi_0_cyc => wbsi_0_cyc,
wbso_1 => wbso_1,
wbsi_1 => wbsi_1,
wbsi_1_cyc => wbsi_1_cyc,
wbso_2 => wbso_2,
wbsi_2 => wbsi_2,
wbsi_2_cyc => wbsi_2_cyc,
wbso_3 => wbso_3,
wbsi_3 => wbsi_3,
wbsi_3_cyc => wbsi_3_cyc,
wbso_4 => wbso_4,
wbsi_4 => wbsi_4,
wbsi_4_cyc => wbsi_4_cyc
);
-------------------------------------------------------------------------------------------------------------
END A25_top_arch;
-- CONFIGURATION wbm_cfg OF pcies_wbm_ctrl IS
-- FOR pcies_wbm_ctrl_arch
-- FOR wb_adr_dec_inst : pcies_wb_adr_dec
-- USE ENTITY work.pcies_wb_adr_dec(wb_adr_dec_arch);
-- END FOR;
-- END FOR;
-- END CONFIGURATION wbm_cfg;
--
-- CONFIGURATION pcies_wbm_cfg OF pcies_wbm IS
-- FOR pcies_wbm_arch
-- FOR wbm : pcies_wbm_ctrl
-- USE CONFIGURATION work.wbm_cfg;
-- END FOR;
-- END FOR;
-- END CONFIGURATION pcies_wbm_cfg;
--
-- CONFIGURATION pcies2wbb_cfg OF pcies2wbb_top IS
-- FOR pcies2wbb_top_arch
-- FOR pcies_wbm_i : pcies_wbm
-- USE CONFIGURATION work.pcies_wbm_cfg;
-- END FOR;
-- END FOR;
-- END CONFIGURATION pcies2wbb_cfg;
--
-- CONFIGURATION top_cfg of A25_top IS
-- FOR A25_top_arch
-- FOR pcie : pcies2wbb_top
-- USE CONFIGURATION work.pcies2wbb_cfg;
-- END FOR;
-- END FOR;
-- END CONFIGURATION top_cfg;
-- Configurations for 16z091-01 address decoder
CONFIGURATION z091_01_wb_master_cfg OF z091_01_wb_master IS
FOR z091_01_wb_master_arch
FOR z091_01_wb_adr_dec_comp : z091_01_wb_adr_dec
USE ENTITY work.z091_01_wb_adr_dec(a25_arch);
END FOR;
END FOR;
END CONFIGURATION z091_01_wb_master_cfg;
CONFIGURATION ip_16z091_01_cfg OF ip_16z091_01 IS
FOR ip_16z091_01_arch
FOR wb_master_comp : z091_01_wb_master
USE CONFIGURATION work.z091_01_wb_master_cfg;
END FOR;
END FOR;
END CONFIGURATION ip_16z091_01_cfg;
CONFIGURATION ip_16z091_01_top_cfg OF ip_16z091_01_top IS
FOR ip_16z091_01_top_arch
FOR ip_16z091_01_comp : ip_16z091_01
USE CONFIGURATION work.ip_16z091_01_cfg;
END FOR;
END FOR;
END CONFIGURATION ip_16z091_01_top_cfg;
CONFIGURATION top_cfg OF A25_top IS
FOR A25_top_arch
FOR pcie : ip_16z091_01_top
USE CONFIGURATION work.ip_16z091_01_top_cfg;
END FOR;
END FOR;
END CONFIGURATION top_cfg;
|
gpl-3.0
|
b807392920d4f9999cbe9502ddcf7f41
| 0.468774 | 3.491353 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/altera_lnsim/ama_accumulator_function/_primary.vhd
| 5 | 2,278 |
library verilog;
use verilog.vl_types.all;
entity ama_accumulator_function is
generic(
width_result : integer := 1;
accumulator : string := "NO";
accum_direction : string := "ADD";
loadconst_value : integer := 0;
accum_sload_register: string := "UNREGISTERED";
accum_sload_aclr: string := "NONE";
double_accum : string := "NO";
use_sload_accum_port: string := "NO";
output_register : string := "UNREGISTERED";
output_aclr : string := "NONE";
latency : integer := 0;
accum_sload_latency_clock: string := "UNREGISTERED";
accum_sload_latency_aclr: string := "NONE";
width_result_msb: vl_notype
);
port(
clock : in vl_logic_vector(3 downto 0);
aclr : in vl_logic_vector(3 downto 0);
ena : in vl_logic_vector(3 downto 0);
accum_sload : in vl_logic;
sload_accum : in vl_logic;
data_result : in vl_logic_vector;
prev_result : in vl_logic_vector;
result : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width_result : constant is 1;
attribute mti_svvh_generic_type of accumulator : constant is 1;
attribute mti_svvh_generic_type of accum_direction : constant is 1;
attribute mti_svvh_generic_type of loadconst_value : constant is 1;
attribute mti_svvh_generic_type of accum_sload_register : constant is 1;
attribute mti_svvh_generic_type of accum_sload_aclr : constant is 1;
attribute mti_svvh_generic_type of double_accum : constant is 1;
attribute mti_svvh_generic_type of use_sload_accum_port : constant is 1;
attribute mti_svvh_generic_type of output_register : constant is 1;
attribute mti_svvh_generic_type of output_aclr : constant is 1;
attribute mti_svvh_generic_type of latency : constant is 1;
attribute mti_svvh_generic_type of accum_sload_latency_clock : constant is 1;
attribute mti_svvh_generic_type of accum_sload_latency_aclr : constant is 1;
attribute mti_svvh_generic_type of width_result_msb : constant is 3;
end ama_accumulator_function;
|
mit
|
34a79653740d2674befc4d0c9ddbe764
| 0.627744 | 3.841484 | false | false | false | false |
freecores/t48
|
rtl/vhdl/cond_branch.vhd
| 1 | 6,872 |
-------------------------------------------------------------------------------
--
-- The Conditional Branch Logic unit.
-- Decisions whether to take a jump or not are made here.
--
-- $Id: cond_branch.vhd,v 1.3 2005-06-11 10:08:43 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t48_pack.word_t;
use work.t48_cond_branch_pack.all;
entity t48_cond_branch is
port (
-- Global Interface -------------------------------------------------------
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
-- Decoder Interface ------------------------------------------------------
compute_take_i : in boolean;
branch_cond_i : in branch_conditions_t;
take_branch_o : out boolean;
accu_i : in word_t;
t0_i : in std_logic;
t1_i : in std_logic;
int_n_i : in std_logic;
f0_i : in std_logic;
f1_i : in std_logic;
tf_i : in std_logic;
carry_i : in std_logic;
comp_value_i : in comp_value_t
);
end t48_cond_branch;
library ieee;
use ieee.numeric_std.all;
use work.t48_pack.res_active_c;
use work.t48_pack.clk_active_c;
architecture rtl of t48_cond_branch is
-- marker for branch taken
signal take_branch_s,
take_branch_q : boolean;
begin
-----------------------------------------------------------------------------
-- Process decide_take
--
-- Purpose:
-- Decides whether a branch has to be taken or not.
--
decide_take: process (accu_i,
branch_cond_i,
t0_i, t1_i,
int_n_i,
f0_i, f1_i,
tf_i,
carry_i,
comp_value_i)
variable or_v : std_logic;
begin
-- default assignment
take_branch_s <= false;
or_v := '0';
case branch_cond_i is
-- Branch On: Accumulator Bit -------------------------------------------
when COND_ON_BIT =>
if accu_i(TO_INTEGER(UNSIGNED(comp_value_i))) = '1' then
take_branch_s <= true;
end if;
-- Branch On: Accumulator Zero ------------------------------------------
when COND_Z =>
for i in accu_i'range loop
or_v := or_v or accu_i(i);
end loop;
take_branch_s <= or_v = not comp_value_i(0);
-- Branch On: Carry -----------------------------------------------------
when COND_C =>
take_branch_s <= carry_i = comp_value_i(0);
-- Branch On: Flag 0 ----------------------------------------------------
when COND_F0 =>
take_branch_s <= f0_i = '1';
-- Branch On: Flag 1 ----------------------------------------------------
when COND_F1 =>
take_branch_s <= f1_i = '1';
-- Branch On: Interrupt -------------------------------------------------
when COND_INT =>
take_branch_s <= int_n_i = '0';
-- Branch On: Test 0 ----------------------------------------------------
when COND_T0 =>
take_branch_s <= t0_i = comp_value_i(0);
-- Branch On: Test 1 ----------------------------------------------------
when COND_T1 =>
take_branch_s <= t1_i = comp_value_i(0);
-- Branch On: Timer Flag ------------------------------------------------
when COND_TF =>
take_branch_s <= tf_i = '1';
when others =>
-- pragma translate_off
assert false
report "Unknown branch condition specified!"
severity error;
-- pragma translate_on
end case;
end process decide_take;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process reg
--
-- Purpose:
-- Implement the marker register.
--
reg: process (res_i, clk_i)
begin
if res_i = res_active_c then
take_branch_q <= false;
elsif clk_i'event and clk_i = clk_active_c then
if en_clk_i then
if compute_take_i then
take_branch_q <= take_branch_s;
end if;
end if;
end if;
end process reg;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output Mapping.
-----------------------------------------------------------------------------
take_branch_o <= take_branch_q;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.2 2004/04/24 23:44:25 arniml
-- move from std_logic_arith to numeric_std
--
-- Revision 1.1 2004/03/23 21:31:52 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
gpl-2.0
|
7fcf421692b24c81933035f1f7f860b1
| 0.486612 | 4.368722 | false | false | false | false |
Ttl/bf_cpu
|
memory.vhd
| 1 | 1,451 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.bfconfig.all;
use std.textio.all;
entity memory is
Generic (
CONTENTS : string := "scripts/instructions.mif"
);
Port ( clk : in STD_LOGIC;
a1 : in pctype;
wd : in STD_LOGIC_VECTOR (7 downto 0);
d1 : out STD_LOGIC_VECTOR (7 downto 0);
we : in STD_LOGIC);
end memory;
architecture Behavioral of memory is
type memtype is array(0 to 2**INST_MEM_SIZE-1) of std_logic_vector(7 downto 0);
impure function init_mem(mif_file_name : in string) return memtype is
file mif_file : text open read_mode is mif_file_name;
variable mif_line : line;
variable temp_bv : bit_vector(7 downto 0);
variable temp_mem : memtype;
variable i : integer := 0;
begin
for j in 0 to memtype'length-1 loop
if not endfile(mif_file) then
readline(mif_file, mif_line);
read(mif_line, temp_bv);
temp_mem(j) := to_stdlogicvector(temp_bv);
else
temp_mem(j) := (others => '0');
end if;
end loop;
return temp_mem;
end function;
signal mem : memtype := init_mem(CONTENTS);
begin
process(clk, we, a1, mem)
begin
if rising_edge(clk) then
if we = '1' then
mem(to_integer(unsigned(a1))) <= wd;
end if;
d1 <= mem(to_integer(unsigned(a1)));
end if;
end process;
end Behavioral;
|
lgpl-3.0
|
70ec365453b0a1a7906d364493599215
| 0.595451 | 3.343318 | false | false | false | false |
cathalmccabe/PYNQ
|
boards/ip/audio_direct_1.1/src/pdm_ser.vhd
| 8 | 4,223 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:24:56 01/31/2014
-- Design Name:
-- Module Name: pdm_ser - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity pdm_ser is
generic(
C_NR_OF_BITS : integer := 16;
C_SYS_CLK_FREQ_MHZ : integer := 100;
C_PDM_FREQ_MHZ : integer range 1 to 3 := 3
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
en_i : in std_logic;
done_o : out std_logic;
data_i : in std_logic_vector(15 downto 0);
-- PWM
pwm_audio_o : out std_logic;
pwm_audio_t : out std_logic;
pwm_audio_i : in std_logic
--pwm_sdaudio_o : out std_logic
);
end pdm_ser;
architecture Behavioral of pdm_ser is
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
signal cnt_clk : integer range 0 to 127 := 0;
signal clk_int, clk_intt : std_logic := '0';
signal pdm_clk_rising, pdm_clk_falling : std_logic;
signal pdm_s_tmp : std_logic_vector((C_NR_OF_BITS-1) downto 0);
signal cnt_bits : integer range 0 to 31 := 0;
signal pwm_int : std_logic;
signal done_int : std_logic;
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
-- enable audio
--pwm_sdaudio_o <= '1';
-- counter for the number of sampled bits
CNT: process(clk_i) begin
if rising_edge(clk_i) then
if pdm_clk_rising = '1' then
if cnt_bits = (C_NR_OF_BITS-1) then
cnt_bits <= 0;
else
cnt_bits <= cnt_bits + 1;
end if;
end if;
end if;
end process CNT;
-- done gen
process(clk_i)
begin
if rising_edge(clk_i) then
if pdm_clk_rising = '1' then
if cnt_bits = (C_NR_OF_BITS-1) then
done_o <= '1';
end if;
else
done_o <= '0';
end if;
end if;
end process;
------------------------------------------------------------------------
-- Serializer
------------------------------------------------------------------------
SHFT_OUT: process(clk_i)
begin
if rising_edge(clk_i) then
if pdm_clk_rising = '1' then
if cnt_bits = (C_NR_OF_BITS-2) then -- end of deserialization
pdm_s_tmp <= data_i;
else
pdm_s_tmp <= pdm_s_tmp(C_NR_OF_BITS-2 downto 0) & '0';
end if;
end if;
end if;
end process SHFT_OUT;
-- output the serial pdm data
pwm_audio_o <= '0';
pwm_audio_t <= --clk_int when en_i = '0' else
'0' when pdm_s_tmp(C_NR_OF_BITS-1) = '0' and en_i = '1' else '1';
------------------------------------------------------------------------
-- slave clock generator
------------------------------------------------------------------------
CLK_CNT: process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' or cnt_clk = ((C_SYS_CLK_FREQ_MHZ/(C_PDM_FREQ_MHZ*2))-1) then
cnt_clk <= 0;
clk_int <= not clk_int;
else
cnt_clk <= cnt_clk + 1;
end if;
clk_intt <= clk_int;
end if;
end process CLK_CNT;
pdm_clk_rising <= '1' when clk_int = '1' and clk_intt = '0' else '0';
--pdm_clk_falling <= '1' when cnt_clk = ((clk_div/2)-1) else '0';
end Behavioral;
|
bsd-3-clause
|
3df2c88405d9bcf08a5e1e07e29acd97
| 0.459152 | 3.787444 | false | false | false | false |
Bourgeoisie/ECE368-RISC16
|
368RISC/ipcore_dir/instruct_blk_mem_gen_v7_3/simulation/bmg_stim_gen.vhd
| 1 | 12,278 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Simple Dual Port RAM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SDP Configuration
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLKA : IN STD_LOGIC;
CLKB : IN STD_LOGIC;
TB_RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
ADDRB: OUT STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL DO_READ_R : STD_LOGIC := '0';
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(5 DOWNTO 0) :=(OTHERS => '0');
SIGNAL PORTA_WR : STD_LOGIC:='0';
SIGNAL COUNT : INTEGER :=0;
SIGNAL INCR_WR_CNT : STD_LOGIC:='0';
SIGNAL PORTA_WR_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_RD : STD_LOGIC:='0';
SIGNAL COUNT_RD : INTEGER :=0;
SIGNAL INCR_RD_CNT : STD_LOGIC:='0';
SIGNAL PORTB_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL LATCH_PORTA_WR_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_RD_HAPPENED : STD_LOGIC := '0';
SIGNAL PORTA_WR_L1 :STD_LOGIC := '0';
SIGNAL PORTA_WR_L2 :STD_LOGIC := '0';
SIGNAL PORTB_RD_R2 :STD_LOGIC := '0';
SIGNAL PORTB_RD_R1 :STD_LOGIC := '0';
SIGNAL LATCH_PORTB_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTA_WR_HAPPENED : STD_LOGIC := '0';
SIGNAL PORTB_RD_L1 : STD_LOGIC := '0';
SIGNAL PORTB_RD_L2 : STD_LOGIC := '0';
SIGNAL PORTA_WR_R2 : STD_LOGIC := '0';
SIGNAL PORTA_WR_R1 : STD_LOGIC := '0';
CONSTANT WR_RD_DEEP_COUNT :INTEGER :=8;
CONSTANT WR_DEEP_COUNT : INTEGER := if_then_else((4 <= 4),WR_RD_DEEP_COUNT,
((16/16)*WR_RD_DEEP_COUNT));
CONSTANT RD_DEEP_COUNT : INTEGER := if_then_else((4 <= 4),WR_RD_DEEP_COUNT,
((16/16)*WR_RD_DEEP_COUNT));
BEGIN
ADDRA <= WRITE_ADDR(3 DOWNTO 0) ;
DINA <= DINA_INT ;
ADDRB <= READ_ADDR(3 DOWNTO 0) when (DO_READ='1') else (OTHERS=>'0');
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 16 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 16,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 16,
DOUT_WIDTH => 16 ,
DATA_PART_CNT => 1,
SEED => 2)
PORT MAP (
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
PORTA_WR_PROCESS: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTA_WR<='1';
ELSE
PORTA_WR<=PORTB_RD_COMPLETE;
END IF;
END IF;
END PROCESS;
PORTB_RD_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTB_RD<='0';
ELSE
PORTB_RD<=PORTA_WR_L2;
END IF;
END IF;
END PROCESS;
PORTB_RD_COMPLETE_LATCH: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
LATCH_PORTB_RD_COMPLETE<='0';
ELSIF(PORTB_RD_COMPLETE='1') THEN
LATCH_PORTB_RD_COMPLETE <='1';
ELSIF(PORTA_WR_HAPPENED='1') THEN
LATCH_PORTB_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_RD_L1 <='0';
PORTB_RD_L2 <='0';
ELSE
PORTB_RD_L1 <= LATCH_PORTB_RD_COMPLETE;
PORTB_RD_L2 <= PORTB_RD_L1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_R1 <='0';
PORTA_WR_R2 <='0';
ELSE
PORTA_WR_R1 <= PORTA_WR;
PORTA_WR_R2 <= PORTA_WR_R1;
END IF;
END IF;
END PROCESS;
PORTA_WR_HAPPENED <= PORTA_WR_R2;
PORTA_WR_COMPLETE_LATCH: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
LATCH_PORTA_WR_COMPLETE<='0';
ELSIF(PORTA_WR_COMPLETE='1') THEN
LATCH_PORTA_WR_COMPLETE <='1';
--ELSIF(PORTB_RD_HAPPENED='1') THEN
ELSE
LATCH_PORTA_WR_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_L1 <='0';
PORTA_WR_L2 <='0';
ELSE
PORTA_WR_L1 <= LATCH_PORTA_WR_COMPLETE;
PORTA_WR_L2 <= PORTA_WR_L1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_RD_R1 <='0';
PORTB_RD_R2 <='0';
ELSE
PORTB_RD_R1 <= PORTB_RD;
PORTB_RD_R2 <= PORTB_RD_R1;
END IF;
END IF;
END PROCESS;
PORTB_RD_HAPPENED <= PORTB_RD_R2;
PORTB_RD_COMPLETE <= '1' when (count_rd=RD_DEEP_COUNT) else '0';
start_rd_counter: process(clkb)
begin
if(rising_edge(clkb)) then
if(tb_rst='1') then
incr_rd_cnt <= '0';
elsif(portb_rd ='1') then
incr_rd_cnt <='1';
elsif(portb_rd_complete='1') then
incr_rd_cnt <='0';
end if;
end if;
end process;
RD_COUNTER: process(clkb)
begin
if(rising_edge(clkb)) then
if(tb_rst='1') then
count_rd <= 0;
elsif(incr_rd_cnt='1') then
count_rd<=count_rd+1;
end if;
--if(count_rd=(wr_rd_deep_count)) then
if(count_rd=(RD_DEEP_COUNT)) then
count_rd<=0;
end if;
end if;
end process;
DO_READ<='1' when (count_rd <RD_DEEP_COUNT and incr_rd_cnt='1') else '0';
PORTA_WR_COMPLETE <= '1' when (count=WR_DEEP_COUNT) else '0';
start_counter: process(clka)
begin
if(rising_edge(clka)) then
if(tb_rst='1') then
incr_wr_cnt <= '0';
elsif(porta_wr ='1') then
incr_wr_cnt <='1';
elsif(porta_wr_complete='1') then
incr_wr_cnt <='0';
end if;
end if;
end process;
COUNTER: process(clka)
begin
if(rising_edge(clka)) then
if(tb_rst='1') then
count <= 0;
elsif(incr_wr_cnt='1') then
count<=count+1;
end if;
if(count=(WR_DEEP_COUNT)) then
count<=0;
end if;
end if;
end process;
DO_WRITE<='1' when (count <WR_DEEP_COUNT and incr_wr_cnt='1') else '0';
BEGIN_SHIFT_REG: FOR I IN 0 TO 5 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLKB,
RST => TB_RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=5)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLKB,
RST =>TB_RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
REGCE_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
DO_READ_R <= '0';
ELSE
DO_READ_R <= DO_READ;
END IF;
END IF;
END PROCESS;
WEA(0) <= DO_WRITE ;
END ARCHITECTURE;
|
mit
|
fac18c8d920955ca819f9b0ccd8d5e2b
| 0.542515 | 3.544457 | false | false | false | false |
nulldozer/purisc
|
convert_to_seven_seg.vhd
| 2 | 965 |
library ieee;
use ieee.std_logic_1164.all;
entity convert_to_seven_seg is
port (
data_in : in std_logic_vector(3 downto 0);
hex_out : out std_logic_vector(6 downto 0)
);
end;
architecture FUCKFUCKFUCKFUCKFUCKFUCKFUCKFUCK of convert_to_seven_seg is
begin
hex_out <= "1111001" when data_in = "0001" else
"0100100" when data_in = "0010" else
"0110000" when data_in = "0011" else
"0011001" when data_in = "0100" else
"0010010" when data_in = "0101" else
"0000010" when data_in = "0110" else
"1111000" when data_in = "0111" else
"0000000" when data_in = "1000" else
"0011000" when data_in = "1001" else
"0001000" when data_in = "1010" else
"0000011" when data_in = "1011" else
"1000110" when data_in = "1100" else
"0100001" when data_in = "1101" else
"0000110" when data_in = "1110" else
"0001110" when data_in = "1111" else
"1000000" when data_in = "0000" else
"1111111";
end;
|
gpl-2.0
|
6b8d56955dd87b46ebc97e8f396d3b91
| 0.634197 | 2.906627 | false | false | false | false |
sukinull/hls_stream
|
Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/vhdl/axi_sg_updt_q_mngr.vhd
| 1 | 36,509 |
-------------------------------------------------------------------------------
-- axi_sg_updt_q_mngr
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_q_mngr.vhd
-- Description: This entity is the descriptor update queue manager
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Created top level for descriptor update queue management
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 11/15/10 v2_01_a
-- ^^^^^^
-- CR582800
-- Converted all stream paraters ***_DATA_WIDTH to ***_TDATA_WIDTH
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_sg_pkg.all;
library lib_pkg_v1_0;
library lib_fifo_v1_0;
use lib_fifo_v1_0.sync_fifo_fg;
use lib_pkg_v1_0.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_q_mngr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXI_SG_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_CH1_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_SG_CH2_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_FAMILY : string := "virtex6"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
--***********************************-- --
--** Channel 1 Control **-- --
--***********************************-- --
ch1_updt_curdesc_wren : out std_logic ; --
ch1_updt_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_updt_active : in std_logic ; --
ch1_updt_queue_empty : out std_logic ; --
ch1_updt_ioc : out std_logic ; --
ch1_updt_ioc_irq_set : in std_logic ; --
--
ch1_dma_interr : out std_logic ; --
ch1_dma_slverr : out std_logic ; --
ch1_dma_decerr : out std_logic ; --
ch1_dma_interr_set : in std_logic ; --
ch1_dma_slverr_set : in std_logic ; --
ch1_dma_decerr_set : in std_logic ; --
--
--***********************************-- --
--** Channel 2 Control **-- --
--***********************************-- --
ch2_updt_active : in std_logic ; --
ch2_updt_curdesc_wren : out std_logic ; --
ch2_updt_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_updt_queue_empty : out std_logic ; --
ch2_updt_ioc : out std_logic ; --
ch2_updt_ioc_irq_set : in std_logic ; --
--
ch2_dma_interr : out std_logic ; --
ch2_dma_slverr : out std_logic ; --
ch2_dma_decerr : out std_logic ; --
ch2_dma_interr_set : in std_logic ; --
ch2_dma_slverr_set : in std_logic ; --
ch2_dma_decerr_set : in std_logic ; --
--
--***********************************-- --
--** Channel 1 Update Interface In **-- --
--***********************************-- --
s_axis_ch1_updt_aclk : in std_logic ; --
-- Update Pointer Stream --
s_axis_ch1_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); --
s_axis_ch1_updtptr_tvalid : in std_logic ; --
s_axis_ch1_updtptr_tready : out std_logic ; --
s_axis_ch1_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_ch1_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_ch1_updtsts_tvalid : in std_logic ; --
s_axis_ch1_updtsts_tready : out std_logic ; --
s_axis_ch1_updtsts_tlast : in std_logic ; --
--
--***********************************-- --
--** Channel 2 Update Interface In **-- --
--***********************************-- --
s_axis_ch2_updt_aclk : in std_logic ; --
-- Update Pointer Stream --
s_axis_ch2_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); --
s_axis_ch2_updtptr_tvalid : in std_logic ; --
s_axis_ch2_updtptr_tready : out std_logic ; --
s_axis_ch2_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_ch2_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_ch2_updtsts_tvalid : in std_logic ; --
s_axis_ch2_updtsts_tready : out std_logic ; --
s_axis_ch2_updtsts_tlast : in std_logic ; --
--
--***************************************-- --
--** Update Interface to AXI DataMover **-- --
--***************************************-- --
-- S2MM Stream Out To DataMover --
s_axis_s2mm_tdata : out std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
s_axis_s2mm_tlast : out std_logic ; --
s_axis_s2mm_tvalid : out std_logic ; --
s_axis_s2mm_tready : in std_logic --
);
end axi_sg_updt_q_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_q_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal m_axis_ch1_updt_tdata : std_logic_vector(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_ch1_updt_tlast : std_logic := '0';
signal m_axis_ch1_updt_tvalid : std_logic := '0';
signal m_axis_ch1_updt_tready : std_logic := '0';
signal m_axis_ch2_updt_tdata : std_logic_vector(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_ch2_updt_tlast : std_logic := '0';
signal m_axis_ch2_updt_tvalid : std_logic := '0';
signal m_axis_ch2_updt_tready : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
--*****************************************************************************
--** CHANNEL 1 **
--*****************************************************************************
-------------------------------------------------------------------------------
-- If Channel 1 is enabled then instantiate descriptor update logic.
-------------------------------------------------------------------------------
GEN_CH1_UPDATE_Q_IF : if C_INCLUDE_CH1 = 1 generate
begin
--*****************************************************************************
--** CHANNEL 1 - DESCRIPTOR QUEUE **
--*****************************************************************************
-- If Descriptor Update queueing enabled then instantiate Queue Logic
GEN_CH1_QUEUE : if C_SG_UPDT_DESC2QUEUE /= 0 generate
begin
-------------------------------------------------------------------------------
I_CH1_UPDT_DESC_QUEUE : entity axi_vdma_v6_2.axi_sg_updt_queue
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_SG_UPDT_DESC2QUEUE => C_SG_UPDT_DESC2QUEUE ,
C_SG_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
s_axis_updt_aclk => s_axis_ch1_updt_aclk ,
--********************************--
--** Control and Status **--
--********************************--
updt_curdesc_wren => ch1_updt_curdesc_wren ,
updt_curdesc => ch1_updt_curdesc ,
updt_active => ch1_updt_active ,
updt_queue_empty => ch1_updt_queue_empty ,
updt_ioc => ch1_updt_ioc ,
updt_ioc_irq_set => ch1_updt_ioc_irq_set ,
dma_interr => ch1_dma_interr ,
dma_slverr => ch1_dma_slverr ,
dma_decerr => ch1_dma_decerr ,
dma_interr_set => ch1_dma_interr_set ,
dma_slverr_set => ch1_dma_slverr_set ,
dma_decerr_set => ch1_dma_decerr_set ,
--********************************--
--** Update Interfaces In **--
--********************************--
-- Update Pointer Stream
s_axis_updtptr_tdata => s_axis_ch1_updtptr_tdata ,
s_axis_updtptr_tvalid => s_axis_ch1_updtptr_tvalid ,
s_axis_updtptr_tready => s_axis_ch1_updtptr_tready ,
s_axis_updtptr_tlast => s_axis_ch1_updtptr_tlast ,
-- Update Status Stream
s_axis_updtsts_tdata => s_axis_ch1_updtsts_tdata ,
s_axis_updtsts_tvalid => s_axis_ch1_updtsts_tvalid ,
s_axis_updtsts_tready => s_axis_ch1_updtsts_tready ,
s_axis_updtsts_tlast => s_axis_ch1_updtsts_tlast ,
--********************************--
--** Update Interfaces Out **--
--********************************--
-- S2MM Stream Out To DataMover
m_axis_updt_tdata => m_axis_ch1_updt_tdata ,
m_axis_updt_tlast => m_axis_ch1_updt_tlast ,
m_axis_updt_tvalid => m_axis_ch1_updt_tvalid ,
m_axis_updt_tready => m_axis_ch1_updt_tready
);
end generate GEN_CH1_QUEUE;
--*****************************************************************************
--** CHANNEL 1 - NO DESCRIPTOR QUEUE **
--*****************************************************************************
-- No update queue enabled, therefore map internal stream logic
-- directly to channel port.
GEN_CH1_NO_QUEUE : if C_SG_UPDT_DESC2QUEUE = 0 generate
begin
I_NO_CH1_UPDT_DESC_QUEUE : entity axi_vdma_v6_2.axi_sg_updt_noqueue
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
--********************************--
--** Control and Status **--
--********************************--
updt_curdesc_wren => ch1_updt_curdesc_wren ,
updt_curdesc => ch1_updt_curdesc ,
updt_active => ch1_updt_active ,
updt_queue_empty => ch1_updt_queue_empty ,
updt_ioc => ch1_updt_ioc ,
updt_ioc_irq_set => ch1_updt_ioc_irq_set ,
dma_interr => ch1_dma_interr ,
dma_slverr => ch1_dma_slverr ,
dma_decerr => ch1_dma_decerr ,
dma_interr_set => ch1_dma_interr_set ,
dma_slverr_set => ch1_dma_slverr_set ,
dma_decerr_set => ch1_dma_decerr_set ,
--********************************--
--** Update Interfaces In **--
--********************************--
-- Update Pointer Stream
s_axis_updtptr_tdata => s_axis_ch1_updtptr_tdata ,
s_axis_updtptr_tvalid => s_axis_ch1_updtptr_tvalid ,
s_axis_updtptr_tready => s_axis_ch1_updtptr_tready ,
s_axis_updtptr_tlast => s_axis_ch1_updtptr_tlast ,
-- Update Status Stream
s_axis_updtsts_tdata => s_axis_ch1_updtsts_tdata ,
s_axis_updtsts_tvalid => s_axis_ch1_updtsts_tvalid ,
s_axis_updtsts_tready => s_axis_ch1_updtsts_tready ,
s_axis_updtsts_tlast => s_axis_ch1_updtsts_tlast ,
--********************************--
--** Update Interfaces Out **--
--********************************--
-- S2MM Stream Out To DataMover
m_axis_updt_tdata => m_axis_ch1_updt_tdata ,
m_axis_updt_tlast => m_axis_ch1_updt_tlast ,
m_axis_updt_tvalid => m_axis_ch1_updt_tvalid ,
m_axis_updt_tready => m_axis_ch1_updt_tready
);
end generate GEN_CH1_NO_QUEUE;
end generate GEN_CH1_UPDATE_Q_IF;
-- Channel 1 NOT included therefore tie ch1 outputs off
GEN_NO_CH1_UPDATE_Q_IF : if C_INCLUDE_CH1 = 0 generate
begin
ch1_updt_curdesc_wren <= '0';
ch1_updt_curdesc <= (others => '0');
ch1_updt_queue_empty <= '1';
ch1_updt_ioc <= '0';
ch1_dma_interr <= '0';
ch1_dma_slverr <= '0';
ch1_dma_decerr <= '0';
m_axis_ch1_updt_tdata <= (others => '0');
m_axis_ch1_updt_tlast <= '0';
m_axis_ch1_updt_tvalid <= '0';
s_axis_ch1_updtptr_tready <= '0';
s_axis_ch1_updtsts_tready <= '0';
end generate GEN_NO_CH1_UPDATE_Q_IF;
--*****************************************************************************
--** CHANNEL 2 **
--*****************************************************************************
-------------------------------------------------------------------------------
-- If Channel 2 is enabled then instantiate descriptor update logic.
-------------------------------------------------------------------------------
GEN_CH2_UPDATE_Q_IF : if C_INCLUDE_CH2 = 1 generate
begin
--*************************************************************************
--** CHANNEL 2 - DESCRIPTOR QUEUE **
--*************************************************************************
-- If Descriptor Update queueing enabled then instantiate Queue Logic
GEN_CH2_QUEUE : if C_SG_UPDT_DESC2QUEUE /= 0 generate
begin
---------------------------------------------------------------------------
I_CH2_UPDT_DESC_QUEUE : entity axi_vdma_v6_2.axi_sg_updt_queue
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_SG_UPDT_DESC2QUEUE => C_SG_UPDT_DESC2QUEUE ,
C_SG_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
C_FAMILY => C_FAMILY
)
port map(
---------------------------------------------------------------
-- AXI Scatter Gather Interface
---------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
s_axis_updt_aclk => s_axis_ch2_updt_aclk ,
--********************************--
--** Control and Status **--
--********************************--
updt_curdesc_wren => ch2_updt_curdesc_wren ,
updt_curdesc => ch2_updt_curdesc ,
updt_active => ch2_updt_active ,
updt_queue_empty => ch2_updt_queue_empty ,
updt_ioc => ch2_updt_ioc ,
updt_ioc_irq_set => ch2_updt_ioc_irq_set ,
dma_interr => ch2_dma_interr ,
dma_slverr => ch2_dma_slverr ,
dma_decerr => ch2_dma_decerr ,
dma_interr_set => ch2_dma_interr_set ,
dma_slverr_set => ch2_dma_slverr_set ,
dma_decerr_set => ch2_dma_decerr_set ,
--********************************--
--** Update Interfaces In **--
--********************************--
-- Update Pointer Stream
s_axis_updtptr_tdata => s_axis_ch2_updtptr_tdata ,
s_axis_updtptr_tvalid => s_axis_ch2_updtptr_tvalid ,
s_axis_updtptr_tready => s_axis_ch2_updtptr_tready ,
s_axis_updtptr_tlast => s_axis_ch2_updtptr_tlast ,
-- Update Status Stream
s_axis_updtsts_tdata => s_axis_ch2_updtsts_tdata ,
s_axis_updtsts_tvalid => s_axis_ch2_updtsts_tvalid ,
s_axis_updtsts_tready => s_axis_ch2_updtsts_tready ,
s_axis_updtsts_tlast => s_axis_ch2_updtsts_tlast ,
--********************************--
--** Update Interfaces Out **--
--********************************--
-- S2MM Stream Out To DataMover
m_axis_updt_tdata => m_axis_ch2_updt_tdata ,
m_axis_updt_tlast => m_axis_ch2_updt_tlast ,
m_axis_updt_tvalid => m_axis_ch2_updt_tvalid ,
m_axis_updt_tready => m_axis_ch2_updt_tready
);
end generate GEN_CH2_QUEUE;
--*****************************************************************************
--** CHANNEL 2 - NO DESCRIPTOR QUEUE **
--*****************************************************************************
-- No update queue enabled, therefore map internal stream logic
-- directly to channel port.
GEN_CH2_NO_QUEUE : if C_SG_UPDT_DESC2QUEUE = 0 generate
I_NO_CH2_UPDT_DESC_QUEUE : entity axi_vdma_v6_2.axi_sg_updt_noqueue
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH
)
port map(
---------------------------------------------------------------
-- AXI Scatter Gather Interface
---------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
--********************************--
--** Control and Status **--
--********************************--
updt_curdesc_wren => ch2_updt_curdesc_wren ,
updt_curdesc => ch2_updt_curdesc ,
updt_active => ch2_updt_active ,
updt_queue_empty => ch2_updt_queue_empty ,
updt_ioc => ch2_updt_ioc ,
updt_ioc_irq_set => ch2_updt_ioc_irq_set ,
dma_interr => ch2_dma_interr ,
dma_slverr => ch2_dma_slverr ,
dma_decerr => ch2_dma_decerr ,
dma_interr_set => ch2_dma_interr_set ,
dma_slverr_set => ch2_dma_slverr_set ,
dma_decerr_set => ch2_dma_decerr_set ,
--********************************--
--** Update Interfaces In **--
--********************************--
-- Update Pointer Stream
s_axis_updtptr_tdata => s_axis_ch2_updtptr_tdata ,
s_axis_updtptr_tvalid => s_axis_ch2_updtptr_tvalid ,
s_axis_updtptr_tready => s_axis_ch2_updtptr_tready ,
s_axis_updtptr_tlast => s_axis_ch2_updtptr_tlast ,
-- Update Status Stream
s_axis_updtsts_tdata => s_axis_ch2_updtsts_tdata ,
s_axis_updtsts_tvalid => s_axis_ch2_updtsts_tvalid ,
s_axis_updtsts_tready => s_axis_ch2_updtsts_tready ,
s_axis_updtsts_tlast => s_axis_ch2_updtsts_tlast ,
--********************************--
--** Update Interfaces Out **--
--********************************--
-- S2MM Stream Out To DataMover
m_axis_updt_tdata => m_axis_ch2_updt_tdata ,
m_axis_updt_tlast => m_axis_ch2_updt_tlast ,
m_axis_updt_tvalid => m_axis_ch2_updt_tvalid ,
m_axis_updt_tready => m_axis_ch2_updt_tready
);
end generate GEN_CH2_NO_QUEUE;
end generate GEN_CH2_UPDATE_Q_IF;
-- Channel 2 NOT included therefore tie ch2 outputs off
GEN_NO_CH2_UPDATE_Q_IF : if C_INCLUDE_CH2 = 0 generate
begin
ch2_updt_curdesc_wren <= '0';
ch2_updt_curdesc <= (others => '0');
ch2_updt_queue_empty <= '1';
ch2_updt_ioc <= '0';
ch2_dma_interr <= '0';
ch2_dma_slverr <= '0';
ch2_dma_decerr <= '0';
m_axis_ch2_updt_tdata <= (others => '0');
m_axis_ch2_updt_tlast <= '0';
m_axis_ch2_updt_tvalid <= '0';
s_axis_ch2_updtptr_tready <= '0';
s_axis_ch2_updtsts_tready <= '0';
end generate GEN_NO_CH2_UPDATE_Q_IF;
-------------------------------------------------------------------------------
-- MUX For DataMover
-------------------------------------------------------------------------------
TO_DATAMVR_MUX : process(ch1_updt_active,
ch2_updt_active,
m_axis_ch1_updt_tdata,
m_axis_ch1_updt_tlast,
m_axis_ch1_updt_tvalid,
m_axis_ch2_updt_tdata,
m_axis_ch2_updt_tlast,
m_axis_ch2_updt_tvalid)
begin
if(ch1_updt_active = '1')then
s_axis_s2mm_tdata <= m_axis_ch1_updt_tdata;
s_axis_s2mm_tlast <= m_axis_ch1_updt_tlast;
s_axis_s2mm_tvalid <= m_axis_ch1_updt_tvalid;
elsif(ch2_updt_active = '1')then
s_axis_s2mm_tdata <= m_axis_ch2_updt_tdata;
s_axis_s2mm_tlast <= m_axis_ch2_updt_tlast;
s_axis_s2mm_tvalid <= m_axis_ch2_updt_tvalid;
else
s_axis_s2mm_tdata <= (others => '0');
s_axis_s2mm_tlast <= '0';
s_axis_s2mm_tvalid <= '0';
end if;
end process TO_DATAMVR_MUX;
m_axis_ch1_updt_tready <= s_axis_s2mm_tready;
m_axis_ch2_updt_tready <= s_axis_s2mm_tready;
end implementation;
|
gpl-2.0
|
aee539368f1827e33e790559436305d8
| 0.353776 | 4.89528 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_sLpmAddSub.vhd
| 8 | 4,640 |
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;
library LPM;
use LPM.LPM_COMPONENTS.all;
library altera;
use altera.alt_dspbuilder_package.all;
ENTITY alt_dspbuilder_sLpmAddSub IS
GENERIC
(
width : positive :=8;
isunsigned : natural :=0;
pipeline : natural :=0;
or_aclr_inputs : boolean := true
);
PORT
(
add_sub : in std_logic ;
dataa : in std_logic_vector (width-1 DOWNTO 0);
datab : in std_logic_vector (width-1 DOWNTO 0);
cin : in std_logic ;
clock : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
clken : in std_logic ;
result : out std_logic_vector (width-1 DOWNTO 0);
cout : out std_logic
);
END alt_dspbuilder_sLpmAddSub;
ARCHITECTURE SYN OF alt_dspbuilder_sLpmAddSub IS
signal aclr_i : std_logic;
BEGIN
or_aclrs: if (or_aclr_inputs=true) generate
aclr_i <= aclr or user_aclr;
end generate or_aclrs;
only_user_aclr: if(or_aclr_inputs=false) generate
aclr_i <= user_aclr;
end generate only_user_aclr;
gnp:if (0=pipeline) generate
gsn:if (0=isunsigned) generate
U0 : lpm_add_sub
GENERIC MAP (
lpm_width => width,
lpm_direction => "UNUSED",
lpm_type => "LPM_ADD_SUB",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO",
lpm_representation => "SIGNED",
lpm_pipeline => 0
)
PORT MAP (
dataa => dataa,
add_sub => add_sub,
datab => datab,
cin => cin,
overflow => cout,
result => result
);
end generate gsn;
gusn:if (0<isunsigned) generate
U0 : lpm_add_sub
GENERIC MAP (
lpm_width => width,
lpm_direction => "UNUSED",
lpm_type => "LPM_ADD_SUB",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO",
lpm_representation => "UNSIGNED",
lpm_pipeline => 0
)
PORT MAP (
dataa => dataa,
add_sub => add_sub,
datab => datab,
cin => cin,
cout => cout,
result => result
);
end generate gusn;
end generate gnp;
gp:if (pipeline>0) generate
gsn:if (0=isunsigned) generate
U0 : lpm_add_sub
GENERIC MAP (
lpm_width => width,
lpm_direction => "UNUSED",
lpm_type => "LPM_ADD_SUB",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO",
lpm_representation => "SIGNED",
lpm_pipeline => pipeline
)
PORT MAP (
dataa => dataa,
add_sub => add_sub,
datab => datab,
cin => cin,
clken => clken,
aclr => aclr_i,
clock => clock,
overflow => cout,
result => result
);
end generate gsn;
gusn:if (0<isunsigned) generate
U0 : lpm_add_sub
GENERIC MAP (
lpm_width => width,
lpm_direction => "UNUSED",
lpm_type => "LPM_ADD_SUB",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO",
lpm_representation => "UNSIGNED",
lpm_pipeline => pipeline
)
PORT MAP (
dataa => dataa,
add_sub => add_sub,
datab => datab,
cin => cin,
clken => clken,
aclr => aclr_i,
clock => clock,
cout => cout,
result => result
);
end generate gusn;
end generate gp;
END SYN;
|
mit
|
4d3792e6082705449901ae42bd672873
| 0.541164 | 3.650669 | false | false | false | false |
nulldozer/purisc
|
Global_memory/MAGIC_global/SETUP_global.vhd
| 2 | 12,850 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SETUP_global is
PORT(
CLK : IN STD_LOGIC;
ADDRESS_A : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_W : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
W_EN : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
STALL : OUT STD_LOGIC;
HAZARD : IN STD_LOGIC;
ram_0_port_a : OUT STD_LOGIC_VECTOR (11 downto 0);
ram_0_port_b : OUT STD_LOGIC_VECTOR (11 downto 0);
ram_0_wren_a : OUT STD_LOGIC;
ram_0_wren_b : OUT STD_LOGIC;
ram_1_port_a : OUT STD_LOGIC_VECTOR (11 downto 0);
ram_1_port_b : OUT STD_LOGIC_VECTOR (11 downto 0);
ram_1_wren_a : OUT STD_LOGIC;
ram_1_wren_b : OUT STD_LOGIC;
ram_2_port_a : OUT STD_LOGIC_VECTOR (11 downto 0);
ram_2_port_b : OUT STD_LOGIC_VECTOR (11 downto 0);
ram_2_wren_a : OUT STD_LOGIC;
ram_2_wren_b : OUT STD_LOGIC;
ram_3_port_a : OUT STD_LOGIC_VECTOR (11 downto 0);
ram_3_port_b : OUT STD_LOGIC_VECTOR (11 downto 0);
ram_3_wren_a : OUT STD_LOGIC;
ram_3_wren_b : OUT STD_LOGIC;
ram_4_port_a : OUT STD_LOGIC_VECTOR (11 downto 0);
ram_4_port_b : OUT STD_LOGIC_VECTOR (11 downto 0);
ram_4_wren_a : OUT STD_LOGIC;
ram_4_wren_b : OUT STD_LOGIC;
ram_5_port_a : OUT STD_LOGIC_VECTOR (11 downto 0);
ram_5_port_b : OUT STD_LOGIC_VECTOR (11 downto 0);
ram_5_wren_a : OUT STD_LOGIC;
ram_5_wren_b : OUT STD_LOGIC;
ram_6_port_a : OUT STD_LOGIC_VECTOR (11 downto 0);
ram_6_port_b : OUT STD_LOGIC_VECTOR (11 downto 0);
ram_6_wren_a : OUT STD_LOGIC;
ram_6_wren_b : OUT STD_LOGIC;
ram_7_port_a : OUT STD_LOGIC_VECTOR (11 downto 0);
ram_7_port_b : OUT STD_LOGIC_VECTOR (11 downto 0);
ram_7_wren_a : OUT STD_LOGIC;
ram_7_wren_b : OUT STD_LOGIC;
ram_0_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_1_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_2_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_3_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_4_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_5_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_6_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
ram_7_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
end;
architecture control of SETUP_global is
component address_transcode_global
PORT (
ADDRESS : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ROW : OUT STD_LOGIC_VECTOR (11 downto 0);
COL : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
end component;
component create_opcode_global
PORT (
COL_A : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COL_B : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COL_C : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COL_D : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COL_E : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
COL_W : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
W_EN : IN STD_LOGIC;
OPCODE_0 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_1 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_2 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_3 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_4 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_5 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_6 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
OPCODE_7 : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
end component;
component FLOW_global
PORT(
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
OPCODE : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
ROW_A : IN STD_LOGIC_VECTOR(11 downto 0);
ROW_B : IN STD_LOGIC_VECTOR(11 downto 0);
ROW_C : IN STD_LOGIC_VECTOR(11 downto 0);
ROW_D : IN STD_LOGIC_VECTOR(11 downto 0);
ROW_E : IN STD_LOGIC_VECTOR(11 downto 0);
ROW_W : IN STD_LOGIC_VECTOR(11 downto 0);
HAZARD : IN STD_LOGIC;
EQUALITY : OUT STD_LOGIC;
ADDRESS_A : OUT STD_LOGIC_VECTOR(11 downto 0);
ADDRESS_B : OUT STD_LOGIC_VECTOR(11 downto 0);
SEL_VECTOR : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
WREN_A : OUT STD_LOGIC;
WREN_B : OUT STD_LOGIC
);
end component;
signal COL_A : std_logic_vector (2 downto 0);
signal COL_B : std_logic_vector (2 downto 0);
signal COL_C : std_logic_vector (2 downto 0);
signal COL_D : std_logic_vector (2 downto 0);
signal COL_E : std_logic_vector (2 downto 0);
signal COL_W : std_logic_vector (2 downto 0);
signal ROW_A : std_logic_vector (11 downto 0);
signal ROW_B : std_logic_vector (11 downto 0);
signal ROW_C : std_logic_vector (11 downto 0);
signal ROW_D : std_logic_vector (11 downto 0);
signal ROW_E : std_logic_vector (11 downto 0);
signal ROW_W : std_logic_vector (11 downto 0);
signal OPCODE_0 : std_logic_vector (5 downto 0);
signal OPCODE_1 : std_logic_vector (5 downto 0);
signal OPCODE_2 : std_logic_vector (5 downto 0);
signal OPCODE_3 : std_logic_vector (5 downto 0);
signal OPCODE_4 : std_logic_vector (5 downto 0);
signal OPCODE_5 : std_logic_vector (5 downto 0);
signal OPCODE_6 : std_logic_vector (5 downto 0);
signal OPCODE_7 : std_logic_vector (5 downto 0);
signal equality_0 : std_logic;
signal equality_1 : std_logic;
signal equality_2 : std_logic;
signal equality_3 : std_logic;
signal equality_4 : std_logic;
signal equality_5 : std_logic;
signal equality_6 : std_logic;
signal equality_7 : std_logic;
begin
transcode_a : address_transcode_global PORT MAP (
ADDRESS => ADDRESS_A,
ROW => ROW_A,
COL => COL_A
);
transcode_b : address_transcode_global PORT MAP (
ADDRESS => ADDRESS_B,
ROW => ROW_B,
COL => COL_B
);
transcode_c : address_transcode_global PORT MAP (
ADDRESS => ADDRESS_C,
ROW => ROW_C,
COL => COL_C
);
transcode_d : address_transcode_global PORT MAP (
ADDRESS => ADDRESS_0,
ROW => ROW_D,
COL => COL_D
);
transcode_e : address_transcode_global PORT MAP (
ADDRESS => ADDRESS_1,
ROW => ROW_E,
COL => COL_E
);
transcode_w : address_transcode_global PORT MAP (
ADDRESS => ADDRESS_W,
ROW => ROW_W,
COL => COL_W
);
opcodery : create_opcode_global PORT MAP (
COL_A => COL_A,
COL_B => COL_B,
COL_C => COL_C,
COL_D => COL_D,
COL_E => COL_E,
COL_W => COL_W,
W_EN => W_EN,
OPCODE_0 => OPCODE_0,
OPCODE_1 => OPCODE_1,
OPCODE_2 => OPCODE_2,
OPCODE_3 => OPCODE_3,
OPCODE_4 => OPCODE_4,
OPCODE_5 => OPCODE_5,
OPCODE_6 => OPCODE_6,
OPCODE_7 => OPCODE_7
);
RAM_0_CONTROL : FLOW_global PORT MAP (
CLK => CLK,
RESET_n => RESET_n,
OPCODE => OPCODE_0,
ROW_A => std_logic_vector(ROW_A),
ROW_B => std_logic_vector(ROW_B),
ROW_C => std_logic_vector(ROW_C),
ROW_D => std_logic_vector(ROW_D),
ROW_E => std_logic_vector(ROW_E),
ROW_W => std_logic_vector(ROW_W),
HAZARD => HAZARD,
EQUALITY => equality_0,
ADDRESS_A => ram_0_port_a,
ADDRESS_B => ram_0_port_b,
SEL_VECTOR => ram_0_sel_vector,
WREN_A => ram_0_wren_a,
WREN_B => ram_0_wren_b
);
RAM_1_CONTROL : FLOW_global PORT MAP (
CLK => CLK,
RESET_n => RESET_n,
OPCODE => OPCODE_1,
ROW_A => std_logic_vector(ROW_A),
ROW_B => std_logic_vector(ROW_B),
ROW_C => std_logic_vector(ROW_C),
ROW_D => std_logic_vector(ROW_D),
ROW_E => std_logic_vector(ROW_E),
ROW_W => std_logic_vector(ROW_W),
HAZARD => HAZARD,
EQUALITY => equality_1,
ADDRESS_A => ram_1_port_a,
ADDRESS_B => ram_1_port_b,
SEL_VECTOR => ram_1_sel_vector,
WREN_A => ram_1_wren_a,
WREN_B => ram_1_wren_b
);
RAM_2_CONTROL : FLOW_global PORT MAP (
CLK => CLK,
RESET_n => RESET_n,
OPCODE => OPCODE_2,
ROW_A => std_logic_vector(ROW_A),
ROW_B => std_logic_vector(ROW_B),
ROW_C => std_logic_vector(ROW_C),
ROW_D => std_logic_vector(ROW_D),
ROW_E => std_logic_vector(ROW_E),
ROW_W => std_logic_vector(ROW_W),
HAZARD => HAZARD,
EQUALITY => equality_2,
ADDRESS_A => ram_2_port_a,
ADDRESS_B => ram_2_port_b,
SEL_VECTOR => ram_2_sel_vector,
WREN_A => ram_2_wren_a,
WREN_B => ram_2_wren_b
);
RAM_3_CONTROL : FLOW_global PORT MAP (
CLK => CLK,
RESET_n => RESET_n,
OPCODE => OPCODE_3,
ROW_A => std_logic_vector(ROW_A),
ROW_B => std_logic_vector(ROW_B),
ROW_C => std_logic_vector(ROW_C),
ROW_D => std_logic_vector(ROW_D),
ROW_E => std_logic_vector(ROW_E),
ROW_W => std_logic_vector(ROW_W),
HAZARD => HAZARD,
EQUALITY => equality_3,
ADDRESS_A => ram_3_port_a,
ADDRESS_B => ram_3_port_b,
SEL_VECTOR => ram_3_sel_vector,
WREN_A => ram_3_wren_a,
WREN_B => ram_3_wren_b
);
RAM_4_CONTROL : FLOW_global PORT MAP (
CLK => CLK,
RESET_n => RESET_n,
OPCODE => OPCODE_4,
ROW_A => std_logic_vector(ROW_A),
ROW_B => std_logic_vector(ROW_B),
ROW_C => std_logic_vector(ROW_C),
ROW_D => std_logic_vector(ROW_D),
ROW_E => std_logic_vector(ROW_E),
ROW_W => std_logic_vector(ROW_W),
HAZARD => HAZARD,
EQUALITY => equality_4,
ADDRESS_A => ram_4_port_a,
ADDRESS_B => ram_4_port_b,
SEL_VECTOR => ram_4_sel_vector,
WREN_A => ram_4_wren_a,
WREN_B => ram_4_wren_b
);
RAM_5_CONTROL : FLOW_global PORT MAP (
CLK => CLK,
RESET_n => RESET_n,
OPCODE => OPCODE_5,
ROW_A => std_logic_vector(ROW_A),
ROW_B => std_logic_vector(ROW_B),
ROW_C => std_logic_vector(ROW_C),
ROW_D => std_logic_vector(ROW_D),
ROW_E => std_logic_vector(ROW_E),
ROW_W => std_logic_vector(ROW_W),
HAZARD => HAZARD,
EQUALITY => equality_5,
ADDRESS_A => ram_5_port_a,
ADDRESS_B => ram_5_port_b,
SEL_VECTOR => ram_5_sel_vector,
WREN_A => ram_5_wren_a,
WREN_B => ram_5_wren_b
);
RAM_6_CONTROL : FLOW_global PORT MAP (
CLK => CLK,
RESET_n => RESET_n,
OPCODE => OPCODE_6,
ROW_A => std_logic_vector(ROW_A),
ROW_B => std_logic_vector(ROW_B),
ROW_C => std_logic_vector(ROW_C),
ROW_D => std_logic_vector(ROW_D),
ROW_E => std_logic_vector(ROW_E),
ROW_W => std_logic_vector(ROW_W),
HAZARD => HAZARD,
EQUALITY => equality_6,
ADDRESS_A => ram_6_port_a,
ADDRESS_B => ram_6_port_b,
SEL_VECTOR => ram_6_sel_vector,
WREN_A => ram_6_wren_a,
WREN_B => ram_6_wren_b
);
RAM_7_CONTROL : FLOW_global PORT MAP (
CLK => CLK,
RESET_n => RESET_n,
OPCODE => OPCODE_7,
ROW_A => std_logic_vector(ROW_A),
ROW_B => std_logic_vector(ROW_B),
ROW_C => std_logic_vector(ROW_C),
ROW_D => std_logic_vector(ROW_D),
ROW_E => std_logic_vector(ROW_E),
ROW_W => std_logic_vector(ROW_W),
HAZARD => HAZARD,
EQUALITY => equality_7,
ADDRESS_A => ram_7_port_a,
ADDRESS_B => ram_7_port_b,
SEL_VECTOR => ram_7_sel_vector,
WREN_A => ram_7_wren_a,
WREN_B => ram_7_wren_b
);
STALL <= not (equality_0 and equality_1 and equality_2 and equality_3 and equality_4 and equality_5 and equality_6 and equality_7);
end;
|
gpl-2.0
|
7383a97437d6fc82fcda926220e0ba90
| 0.515486 | 3.052257 | false | false | false | false |
Caneda/Caneda
|
libraries/hdl/vhdl/synchronous/counter x n.vhd
| 1 | 725 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
ENTITY counter IS
GENERIC ( WIDTH : integer := 32);
PORT (CLK : IN std_logic;
RST : IN std_logic;
LOAD : IN std_logic;
DATA : IN unsigned(WIDTH-1 DOWNTO 0);
Q : OUT unsigned(WIDTH-1 DOWNTO 0));
END counter;
ARCHITECTURE rtl OF counter IS
signal count : unsigned(WIDTH-1 DOWNTO 0);
BEGIN
process(RST, CLK) is
begin
if(RST = '1') then
count <= (others => '0');
elsif(CLK = '1' and CLK'event) then
if(LOAD = '1') then
count <= DATA;
else
count <= count + 1;
end if;
end if;
end process;
Q <= count;
END rtl;
|
gpl-2.0
|
d8953703d2e41f831b424779440012be
| 0.53931 | 3.485577 | false | false | false | false |
straywarrior/MadeCPUin21days
|
IF_ID_REG.vhd
| 1 | 2,369 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: StrayWarrior
--
-- Create Date: 13:39:51 11/14/2015
-- Design Name:
-- Module Name: IF_ID_REG - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity IF_ID_REG is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
pc_in : in STD_LOGIC_VECTOR (15 downto 0);
inst_in : in STD_LOGIC_VECTOR (15 downto 0);
stall : in STD_LOGIC;
clear : in STD_LOGIC;
pc_out : out STD_LOGIC_VECTOR (15 downto 0);
inst_out : out STD_LOGIC_VECTOR (15 downto 0);
rx : out STD_LOGIC_VECTOR (3 downto 0);
ry : out STD_LOGIC_VECTOR (3 downto 0)
);
end IF_ID_REG;
architecture Behavioral of IF_ID_REG is
begin
process (clear, reset, clk)
begin
if (reset = '0') then
pc_out <= (others => '0');
inst_out <= (11 => '1', others => '0');
rx <= (others => '0');
ry <= (others => '0');
elsif (clk'event and clk = '1') then
if (stall = '0' and clear = '0') then
pc_out <= pc_in;
inst_out <= inst_in;
rx(2 downto 0) <= inst_in(10 downto 8);
rx(3) <= '0';
ry(2 downto 0) <= inst_in(7 downto 5);
ry(3) <= '0';
elsif (stall = '0' and clear = '1') then
-- Clear the IF/ID
pc_out <= (others => '0');
inst_out <= (11 => '1', others => '0');
rx <= (others => '0');
ry <= (others => '0');
else
-- Insert a bubble here
null;
end if;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
a69455981710faf8f5f24141f2e1005e
| 0.497678 | 3.616794 | false | false | false | false |
nulldozer/purisc
|
Compute_Group/MAGIC_clocked/RAM_0.vhd
| 1 | 10,398 |
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: RAM_0.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 14.0.0 Build 200 06/17/2014 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus II License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY RAM_0 IS
PORT
(
aclr : IN STD_LOGIC := '0';
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END RAM_0;
ARCHITECTURE SYN OF ram_0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
q_a <= sub_wire0(31 DOWNTO 0);
q_b <= sub_wire1(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK0",
init_file => "RAM_0.mif",
intended_device_family => "Cyclone IV E",
lpm_type => "altsyncram",
numwords_a => 1024,
numwords_b => 1024,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "CLEAR0",
outdata_aclr_b => "CLEAR0",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_mixed_ports => "OLD_DATA",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => 10,
widthad_b => 10,
width_a => 32,
width_b => 32,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK0"
)
PORT MAP (
aclr0 => aclr,
address_a => address_a,
address_b => address_b,
clock0 => clock,
data_a => data_a,
data_b => data_b,
wren_a => wren_a,
wren_b => wren_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "1"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "32768"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "RAM_0.mif"
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "1"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: INIT_FILE STRING "RAM_0.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "CLEAR0"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "CLEAR0"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
-- Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL "address_a[9..0]"
-- Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL "address_b[9..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data_a 0 0 32 0 INPUT NODEFVAL "data_a[31..0]"
-- Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL "data_b[31..0]"
-- Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL "q_a[31..0]"
-- Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]"
-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
-- Retrieval info: CONNECT: @aclr0 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0
-- Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 32 0 data_a 0 0 32 0
-- Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-- Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0
-- Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_0.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_0_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
|
gpl-2.0
|
345df2f1cf1e7c5014ca3a7ca703fa94
| 0.666282 | 3.290506 | false | false | false | false |
nulldozer/purisc
|
Compute_Group/CORE/purisc_core.vhd
| 1 | 6,794 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity purisc_core is
port(
clk, reset_n : in std_logic;
r_addr_a, r_addr_b, r_addr_c, r_addr_0, r_addr_1 : out std_logic_vector(31 downto 0);
w_data, w_addr : out std_logic_vector(31 downto 0);
we : out std_logic;
stall : in std_logic;
id : in std_logic_vector(2 downto 0);
r_data_a, r_data_b, r_data_c,
r_data_0, r_data_1 : in std_logic_vector(31 downto 0)
);
end entity;
architecture arch of purisc_core is
--top core signals
signal start_address : std_logic_vector(31 downto 0);
--ri output signals
signal ri_a : std_logic_vector(31 downto 0);
signal ri_b : std_logic_vector(31 downto 0);
signal ri_c : std_logic_vector(31 downto 0);
signal ri_next_pc : std_logic_vector(31 downto 0);
--rd output signals
signal rd_a : std_logic_vector(31 downto 0);
signal rd_b : std_logic_vector(31 downto 0);
signal rd_c : std_logic_vector(31 downto 0);
signal rd_addr_a : std_logic_vector(31 downto 0);
signal rd_addr_b : std_logic_vector(31 downto 0);
signal rd_addr_c : std_logic_vector(31 downto 0);
signal rd_next_pc : std_logic_vector(31 downto 0);
signal rd_ubranch : std_logic;
signal rd_noop : std_logic;
--ex output signals
signal ex_b : std_logic_vector(31 downto 0); --ex_b is another name for for ex_w_addr
signal ex_db : std_logic_vector(31 downto 0); --ex_b is another name for for ex_w_data
signal ex_cbranch : std_logic;
signal ex_cbranch_addr : std_logic_vector(31 downto 0);
signal ex_noop : std_logic;
--ex input signals
signal ex_da_in, ex_db_in : std_logic_vector(31 downto 0);
--ex output signals
signal ex_w_data, ex_w_addr : std_logic_vector(31 downto 0);
signal ex_we : std_logic;
--ri stage
component read_instruction_stage is
port(
clk : in std_logic;
reset_n : in std_logic;
stall : in std_logic;
start_address : in std_logic_vector(31 downto 0);
cbranch : in std_logic;
cbranch_addr : in std_logic_vector(31 downto 0);
ubranch : in std_logic;
ubranch_addr : in std_logic_vector(31 downto 0);
--outputs
next_pc : out std_logic_vector(31 downto 0);
--memory
r_addr_inst : out std_logic_vector(31 downto 0)
);
end component;
--rd stage
component read_data_stage is
port(
clk : in std_logic;
reset_n : in std_logic;
stall : in std_logic;
-- inputs
start_address : in std_logic_vector(31 downto 0);
ex_w_addr : in std_logic_vector(31 downto 0);
ex_w_data : in std_logic_vector(31 downto 0);
ex_we : in std_logic;
a_in : in std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0);
c_in : in std_logic_vector(31 downto 0);
addr_a : in std_logic_vector(31 downto 0);
addr_b : in std_logic_vector(31 downto 0);
addr_c : in std_logic_vector(31 downto 0);
next_pc : in std_logic_vector(31 downto 0);
ubranch_in : in std_logic;
cbranch_in : in std_logic;
--outputs
a_out : out std_logic_vector(31 downto 0);
b_out : out std_logic_vector(31 downto 0);
c_out : out std_logic_vector(31 downto 0);
addr_a_out : out std_logic_vector(31 downto 0);
addr_b_out : out std_logic_vector(31 downto 0);
addr_c_out : out std_logic_vector(31 downto 0);
ubranch_out : out std_logic;
noop_out : out std_logic;
r_addr_0 : out std_logic_vector(31 downto 0);
r_addr_1 : out std_logic_vector(31 downto 0);
next_pc_out : out std_logic_vector(31 downto 0)
);
end component;
--ex stage
component execute_stage is
port(
clk : in std_logic;
reset_n : in std_logic;
stall : in std_logic;
noop_in : in std_logic;
--inputs
ubranch_in : in std_logic;
cbranch_in : in std_logic;
start_address : in std_logic_vector(31 downto 0);
ex_w_addr : in std_logic_vector(31 downto 0);
ex_w_data : in std_logic_vector(31 downto 0);
ex_we : in std_logic;
a_in : in std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0);
c_in : in std_logic_vector(31 downto 0);
addr_a : in std_logic_vector(31 downto 0);
addr_b : in std_logic_vector(31 downto 0);
addr_c : in std_logic_vector(31 downto 0);
next_pc : in std_logic_vector(31 downto 0);
--outputs
cbranch_out : out std_logic;
cbranch_addr : out std_logic_vector(31 downto 0);
-- memory
da_in : in std_logic_vector(31 downto 0);
db_in : in std_logic_vector(31 downto 0);
w_data : out std_logic_vector(31 downto 0);
w_addr : out std_logic_vector(31 downto 0);
we_out : out std_logic
);
end component;
begin
ri : read_instruction_stage port map (
--in
clk => clk,
reset_n => reset_n,
stall => stall,
start_address => start_address,
cbranch => ex_cbranch,
cbranch_addr => ex_cbranch_addr,
ubranch => rd_ubranch,
ubranch_addr => rd_c,
next_pc => ri_next_pc,
r_addr_inst => ri_a
);
rd : read_data_stage port map (
clk => clk,
reset_n => reset_n,
stall => stall,
-- inputs
start_address => start_address,
ex_w_addr => ex_w_addr,
ex_w_data => ex_w_data,
ex_we => ex_we,
a_in => r_data_a,
b_in => r_data_b,
c_in => r_data_c,
addr_a => ri_a,
addr_b => ri_b,
addr_c => ri_c,
next_pc => ri_next_pc,
ubranch_in => rd_ubranch,
cbranch_in => ex_cbranch,
--outputs
a_out => rd_a,
b_out => rd_b,
c_out => rd_c,
addr_a_out => rd_addr_a,
addr_b_out => rd_addr_b,
addr_c_out => rd_addr_c,
ubranch_out => rd_ubranch,
noop_out => rd_noop,
r_addr_0 => r_addr_0,
r_addr_1 => r_addr_1,
next_pc_out => rd_next_pc
);
ex : execute_stage port map (
clk => clk,
reset_n => reset_n,
stall => stall,
noop_in => rd_noop,
--inputs
ubranch_in => rd_ubranch,
cbranch_in => ex_cbranch,
start_address => start_address,
ex_w_addr => ex_w_addr,
ex_w_data => ex_w_data,
ex_we => ex_we,
a_in => rd_a,
b_in => rd_b,
c_in => rd_c,
addr_a => rd_addr_a,
addr_b => rd_addr_b,
addr_c => rd_addr_c,
next_pc => rd_next_pc,
--outputs
cbranch_addr => ex_cbranch_addr,
cbranch_out => ex_cbranch,
-- memory
da_in => r_data_0,
db_in => r_data_1,
w_data => ex_w_data,
w_addr => ex_w_addr,
we_out => ex_we
);
-- hard coded start address offset (this should be half of local memory size)
start_address <= "00000000000000000000000000000000" when id(0)='0' else
"00000000000000000001000000000000";
--address calculation for cache
ri_b <= std_logic_vector(unsigned(ri_a) + 1);
ri_c <= std_logic_vector(unsigned(ri_a) + 2);
--connecting modules to top level io
w_data <= ex_w_data;
w_addr <= ex_w_addr;
we <= ex_we;
--alternate names
r_addr_a <= ri_a;
r_addr_b <= ri_b;
r_addr_c <= ri_c;
end architecture;
|
gpl-2.0
|
b4b4de369ea9dc723bef4217b63dfd72
| 0.620253 | 2.614082 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/altera_lnsim/generic_m10k/_primary.vhd
| 5 | 9,371 |
library verilog;
use verilog.vl_types.all;
entity generic_m10k is
generic(
operation_mode : string := "single_port";
mixed_port_feed_through_mode: string := "dont_care";
ram_block_type : string := "auto";
logical_ram_name: string := "ram_name";
init_file : string := "init_file.hex";
init_file_layout: string := "none";
ecc_pipeline_stage_enabled: string := "false";
enable_ecc : string := "false";
width_eccstatus : integer := 2;
data_interleave_width_in_bits: integer := 1;
data_interleave_offset_in_bits: integer := 1;
port_a_logical_ram_depth: integer := 0;
port_a_logical_ram_width: integer := 0;
port_a_first_address: integer := 0;
port_a_last_address: integer := 0;
port_a_first_bit_number: integer := 0;
port_a_data_out_clear: string := "none";
port_a_data_out_clock: string := "none";
port_a_data_width: integer := 1;
port_a_address_width: integer := 1;
port_a_byte_enable_mask_width: integer := 1;
port_b_logical_ram_depth: integer := 0;
port_b_logical_ram_width: integer := 0;
port_b_first_address: integer := 0;
port_b_last_address: integer := 0;
port_b_first_bit_number: integer := 0;
port_b_address_clear: string := "none";
port_b_data_out_clear: string := "none";
port_b_data_in_clock: string := "clock1";
port_b_address_clock: string := "clock1";
port_b_write_enable_clock: string := "clock1";
port_b_read_enable_clock: string := "clock1";
port_b_byte_enable_clock: string := "clock1";
port_b_data_out_clock: string := "none";
port_b_data_width: integer := 1;
port_b_address_width: integer := 1;
port_b_byte_enable_mask_width: integer := 1;
port_a_read_during_write_mode: string := "new_data_no_nbe_read";
port_b_read_during_write_mode: string := "new_data_no_nbe_read";
power_up_uninitialized: string := "false";
lpm_type : string := "arriav_ram_block";
lpm_hint : string := "true";
connectivity_checking: string := "off";
mem_init0 : string := "";
mem_init1 : string := "";
mem_init2 : string := "";
mem_init3 : string := "";
mem_init4 : string := "";
port_a_byte_size: integer := 0;
port_b_byte_size: integer := 0;
clk0_input_clock_enable: string := "none";
clk0_core_clock_enable: string := "none";
clk0_output_clock_enable: string := "none";
clk1_input_clock_enable: string := "none";
clk1_core_clock_enable: string := "none";
clk1_output_clock_enable: string := "none";
bist_ena : string := "false";
port_a_address_clear: string := "none";
port_a_data_in_clock: string := "clock0";
port_a_address_clock: string := "clock0";
port_a_write_enable_clock: string := "clock0";
port_a_byte_enable_clock: string := "clock0";
port_a_read_enable_clock: string := "clock0"
);
port(
portadatain : in vl_logic_vector;
portaaddr : in vl_logic_vector;
portawe : in vl_logic;
portare : in vl_logic;
portbdatain : in vl_logic_vector;
portbaddr : in vl_logic_vector;
portbwe : in vl_logic;
portbre : in vl_logic;
clk0 : in vl_logic;
clk1 : in vl_logic;
ena0 : in vl_logic;
ena1 : in vl_logic;
ena2 : in vl_logic;
ena3 : in vl_logic;
clr0 : in vl_logic;
clr1 : in vl_logic;
nerror : in vl_logic;
portabyteenamasks: in vl_logic_vector;
portbbyteenamasks: in vl_logic_vector;
portaaddrstall : in vl_logic;
portbaddrstall : in vl_logic;
devclrn : in vl_logic;
devpor : in vl_logic;
eccstatus : out vl_logic_vector;
portadataout : out vl_logic_vector;
portbdataout : out vl_logic_vector;
dftout : out vl_logic_vector(8 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of operation_mode : constant is 1;
attribute mti_svvh_generic_type of mixed_port_feed_through_mode : constant is 1;
attribute mti_svvh_generic_type of ram_block_type : constant is 1;
attribute mti_svvh_generic_type of logical_ram_name : constant is 1;
attribute mti_svvh_generic_type of init_file : constant is 1;
attribute mti_svvh_generic_type of init_file_layout : constant is 1;
attribute mti_svvh_generic_type of ecc_pipeline_stage_enabled : constant is 1;
attribute mti_svvh_generic_type of enable_ecc : constant is 1;
attribute mti_svvh_generic_type of width_eccstatus : constant is 1;
attribute mti_svvh_generic_type of data_interleave_width_in_bits : constant is 1;
attribute mti_svvh_generic_type of data_interleave_offset_in_bits : constant is 1;
attribute mti_svvh_generic_type of port_a_logical_ram_depth : constant is 1;
attribute mti_svvh_generic_type of port_a_logical_ram_width : constant is 1;
attribute mti_svvh_generic_type of port_a_first_address : constant is 1;
attribute mti_svvh_generic_type of port_a_last_address : constant is 1;
attribute mti_svvh_generic_type of port_a_first_bit_number : constant is 1;
attribute mti_svvh_generic_type of port_a_data_out_clear : constant is 1;
attribute mti_svvh_generic_type of port_a_data_out_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_data_width : constant is 1;
attribute mti_svvh_generic_type of port_a_address_width : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_enable_mask_width : constant is 1;
attribute mti_svvh_generic_type of port_b_logical_ram_depth : constant is 1;
attribute mti_svvh_generic_type of port_b_logical_ram_width : constant is 1;
attribute mti_svvh_generic_type of port_b_first_address : constant is 1;
attribute mti_svvh_generic_type of port_b_last_address : constant is 1;
attribute mti_svvh_generic_type of port_b_first_bit_number : constant is 1;
attribute mti_svvh_generic_type of port_b_address_clear : constant is 1;
attribute mti_svvh_generic_type of port_b_data_out_clear : constant is 1;
attribute mti_svvh_generic_type of port_b_data_in_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_address_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_write_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_read_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_data_out_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_data_width : constant is 1;
attribute mti_svvh_generic_type of port_b_address_width : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_enable_mask_width : constant is 1;
attribute mti_svvh_generic_type of port_a_read_during_write_mode : constant is 1;
attribute mti_svvh_generic_type of port_b_read_during_write_mode : constant is 1;
attribute mti_svvh_generic_type of power_up_uninitialized : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of connectivity_checking : constant is 1;
attribute mti_svvh_generic_type of mem_init0 : constant is 1;
attribute mti_svvh_generic_type of mem_init1 : constant is 1;
attribute mti_svvh_generic_type of mem_init2 : constant is 1;
attribute mti_svvh_generic_type of mem_init3 : constant is 1;
attribute mti_svvh_generic_type of mem_init4 : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_size : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_size : constant is 1;
attribute mti_svvh_generic_type of clk0_input_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk0_core_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk0_output_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_input_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_core_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_output_clock_enable : constant is 1;
attribute mti_svvh_generic_type of bist_ena : constant is 1;
attribute mti_svvh_generic_type of port_a_address_clear : constant is 1;
attribute mti_svvh_generic_type of port_a_data_in_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_address_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_write_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_read_enable_clock : constant is 1;
end generic_m10k;
|
mit
|
2b532376c85d51bcb2e5f0d4e7a3ae35
| 0.63323 | 3.442689 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
Test_Pattern_Generator_dspbuilder/hdl/Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP.vhd
| 2 | 15,793 |
-- Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.10:05:29
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP is
port (
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset
check_en : out std_logic; -- check_en.wire
pixel_num : in std_logic_vector(47 downto 0) := (others => '0'); -- pixel_num.wire
ready : in std_logic := '0'; -- ready.wire
data_en : out std_logic; -- data_en.wire
counter : in std_logic_vector(23 downto 0) := (others => '0'); -- counter.wire
ctrl_en : out std_logic -- ctrl_en.wire
);
end entity Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP;
architecture rtl of Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component StateMachineEditor is
port (
clock : in std_logic := 'X'; -- clk
counter : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
data_end : in std_logic := 'X'; -- wire
ready : in std_logic := 'X'; -- wire
reset : in std_logic := 'X'; -- wire
state : out std_logic_vector(2 downto 0) -- wire
);
end component StateMachineEditor;
component alt_dspbuilder_pipelined_adder_GNTWZRTG4I is
generic (
width : natural := 0;
pipeline : integer := 0
);
port (
aclr : in std_logic := 'X'; -- clk
add_sub : in std_logic := 'X'; -- wire
cin : in std_logic := 'X'; -- wire
clock : in std_logic := 'X'; -- clk
cout : out std_logic; -- wire
dataa : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
datab : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
result : out std_logic_vector(width-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_pipelined_adder_GNTWZRTG4I;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component alt_dspbuilder_case_statement_GN4KF5KLTA is
generic (
number_outputs : integer := 8;
hasDefault : natural := 0;
pipeline : natural := 0;
width : integer := 8
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
input : in std_logic_vector(2 downto 0) := (others => 'X'); -- wire
r0 : out std_logic; -- wire
r1 : out std_logic; -- wire
r2 : out std_logic; -- wire
r3 : out std_logic; -- wire
r4 : out std_logic -- wire
);
end component alt_dspbuilder_case_statement_GN4KF5KLTA;
component alt_dspbuilder_if_statement_GNIV4UP6ZO is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNIV4UP6ZO;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_single_pulse_GN2XGKTRR3 is
generic (
delay : positive := 1;
signal_type : string := "Impulse";
impulse_width : positive := 1
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
result : out std_logic; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_single_pulse_GN2XGKTRR3;
component alt_dspbuilder_constant_GNQJ63TWA6 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNQJ63TWA6;
component alt_dspbuilder_port_GNUJT4YY5I is
port (
input : in std_logic_vector(47 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(47 downto 0) -- wire
);
end component alt_dspbuilder_port_GNUJT4YY5I;
component alt_dspbuilder_cast_GNKIWLRTQI is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(47 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNKIWLRTQI;
component alt_dspbuilder_cast_GN5P6ORZXA is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN5P6ORZXA;
component alt_dspbuilder_cast_GNLWRZWTQF is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(2 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(2 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNLWRZWTQF;
signal pipelined_adder1user_aclrgnd_output_wire : std_logic; -- Pipelined_Adder1user_aclrGND:output -> Pipelined_Adder1:user_aclr
signal pipelined_adder1enavcc_output_wire : std_logic; -- Pipelined_Adder1enaVCC:output -> Pipelined_Adder1:ena
signal single_pulsesclrgnd_output_wire : std_logic; -- Single_PulsesclrGND:output -> Single_Pulse:sclr
signal single_pulseenavcc_output_wire : std_logic; -- Single_PulseenaVCC:output -> Single_Pulse:ena
signal counter_0_output_wire : std_logic_vector(23 downto 0); -- counter_0:output -> [If_Statement6:a, cast27:input]
signal constant15_output_wire : std_logic_vector(23 downto 0); -- Constant15:output -> Pipelined_Adder1:datab
signal pipelined_adder1_result_wire : std_logic_vector(23 downto 0); -- Pipelined_Adder1:result -> If_Statement6:b
signal single_pulse_result_wire : std_logic; -- Single_Pulse:result -> State_Machine_Editor:reset
signal ready_0_output_wire : std_logic; -- ready_0:output -> State_Machine_Editor:ready
signal if_statement6_true_wire : std_logic; -- If_Statement6:true -> State_Machine_Editor:data_end
signal case_statement_r1_wire : std_logic; -- Case_Statement:r1 -> ctrl_en_0:input
signal case_statement_r2_wire : std_logic; -- Case_Statement:r2 -> data_en_0:input
signal case_statement_r3_wire : std_logic; -- Case_Statement:r3 -> check_en_0:input
signal pixel_num_0_output_wire : std_logic_vector(47 downto 0); -- pixel_num_0:output -> cast26:input
signal cast26_output_wire : std_logic_vector(23 downto 0); -- cast26:output -> Pipelined_Adder1:dataa
signal cast27_output_wire : std_logic_vector(23 downto 0); -- cast27:output -> State_Machine_Editor:counter
signal state_machine_editor_state_wire : std_logic_vector(2 downto 0); -- State_Machine_Editor:state -> cast28:input
signal cast28_output_wire : std_logic_vector(2 downto 0); -- cast28:output -> Case_Statement:input
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Case_Statement:clock, Pipelined_Adder1:clock, Single_Pulse:clock, State_Machine_Editor:clock]
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Case_Statement:aclr, Pipelined_Adder1:aclr, Single_Pulse:aclr]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
ctrl_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => case_statement_r1_wire, -- input.wire
output => ctrl_en -- output.wire
);
state_machine_editor : component StateMachineEditor
port map (
clock => clock_0_clock_output_clk, -- clock.clk
reset => single_pulse_result_wire, -- reset.wire
ready => ready_0_output_wire, -- ready.wire
counter => cast27_output_wire, -- counter.wire
data_end => if_statement6_true_wire, -- data_end.wire
state => state_machine_editor_state_wire -- state.wire
);
pipelined_adder1 : component alt_dspbuilder_pipelined_adder_GNTWZRTG4I
generic map (
width => 24,
pipeline => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => cast26_output_wire, -- dataa.wire
datab => constant15_output_wire, -- datab.wire
result => pipelined_adder1_result_wire, -- result.wire
user_aclr => pipelined_adder1user_aclrgnd_output_wire, -- user_aclr.wire
ena => pipelined_adder1enavcc_output_wire -- ena.wire
);
pipelined_adder1user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => pipelined_adder1user_aclrgnd_output_wire -- output.wire
);
pipelined_adder1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => pipelined_adder1enavcc_output_wire -- output.wire
);
case_statement : component alt_dspbuilder_case_statement_GN4KF5KLTA
generic map (
number_outputs => 5,
hasDefault => 1,
pipeline => 0,
width => 3
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
input => cast28_output_wire, -- input.wire
r0 => open, -- r0.wire
r1 => case_statement_r1_wire, -- r1.wire
r2 => case_statement_r2_wire, -- r2.wire
r3 => case_statement_r3_wire, -- r3.wire
r4 => open -- r4.wire
);
data_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => case_statement_r2_wire, -- input.wire
output => data_en -- output.wire
);
if_statement6 : component alt_dspbuilder_if_statement_GNIV4UP6ZO
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "a=b",
number_inputs => 2,
width => 24
)
port map (
true => if_statement6_true_wire, -- true.wire
a => counter_0_output_wire, -- a.wire
b => pipelined_adder1_result_wire -- b.wire
);
counter_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => counter, -- input.wire
output => counter_0_output_wire -- output.wire
);
single_pulse : component alt_dspbuilder_single_pulse_GN2XGKTRR3
generic map (
delay => 1,
signal_type => "Step Down",
impulse_width => 1
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
result => single_pulse_result_wire, -- result.wire
sclr => single_pulsesclrgnd_output_wire, -- sclr.wire
ena => single_pulseenavcc_output_wire -- ena.wire
);
single_pulsesclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => single_pulsesclrgnd_output_wire -- output.wire
);
single_pulseenavcc : component alt_dspbuilder_vcc_GN
port map (
output => single_pulseenavcc_output_wire -- output.wire
);
constant15 : component alt_dspbuilder_constant_GNQJ63TWA6
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000100",
width => 24
)
port map (
output => constant15_output_wire -- output.wire
);
check_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => case_statement_r3_wire, -- input.wire
output => check_en -- output.wire
);
pixel_num_0 : component alt_dspbuilder_port_GNUJT4YY5I
port map (
input => pixel_num, -- input.wire
output => pixel_num_0_output_wire -- output.wire
);
ready_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => ready, -- input.wire
output => ready_0_output_wire -- output.wire
);
cast26 : component alt_dspbuilder_cast_GNKIWLRTQI
generic map (
round => 0,
saturate => 0
)
port map (
input => pixel_num_0_output_wire, -- input.wire
output => cast26_output_wire -- output.wire
);
cast27 : component alt_dspbuilder_cast_GN5P6ORZXA
generic map (
round => 0,
saturate => 0
)
port map (
input => counter_0_output_wire, -- input.wire
output => cast27_output_wire -- output.wire
);
cast28 : component alt_dspbuilder_cast_GNLWRZWTQF
generic map (
round => 0,
saturate => 0
)
port map (
input => state_machine_editor_state_wire, -- input.wire
output => cast28_output_wire -- output.wire
);
end architecture rtl; -- of Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_CTRL_TOP
|
mit
|
8c7a92592dfad7b61121aacbaeed2c1c
| 0.552713 | 3.40293 | false | false | false | false |
Caneda/Caneda
|
libraries/hdl/vhdl/synchronous/flipflop sr with enable.vhd
| 1 | 180 |
process(CLK, RST)
begin
if(RST = '1') then
Q <= '0';
elsif(CLK = '1' and CLK'event) then
if(EN = '1') then
Q <= D;
end if;
end if;
end process;
|
gpl-2.0
|
394ea27766900ffa192ddb7b91036bc3
| 0.472222 | 2.8125 | false | false | false | false |
Raane/Term-Assigment-TFE4140-mod-anal-dig-sys
|
Project/liaison/src/liaison.vhd
| 1 | 2,998 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity liaison is
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
di_ready : in STD_LOGIC;
mp_data : in STD_LOGIC_VECTOR(3 downto 0);
do_ready : out STD_LOGIC;
voted_data : out STD_LOGIC
);
end liaison;
architecture liaison of liaison is
signal voted_data_bit: STD_LOGIC;
signal status: STD_LOGIC_VECTOR (2 downto 0);
signal control_signals: STD_LOGIC_VECTOR (9 downto 0);
signal ECC_signal: STD_LOGIC_VECTOR(3 downto 0);
signal voted_data_out: STD_LOGIC_VECTOR (7 downto 0);
signal status_out: STD_LOGIC_VECTOR (2 downto 0);
signal ECC_out: STD_LOGIC_VECTOR (3 downto 0);
signal voted_data_selector: STD_LOGIC_VECTOR (3 downto 0);
-- Declare aliases for the input votes
alias a is mp_data(0);
alias b is mp_data(1);
alias c is mp_data(2);
alias d is mp_data(3);
begin
-- Add all entities to the top level
onebitvoter: entity work.onebitvoter
port map(
clk => clk,
reset => reset,
a => a,
b => b,
c => c,
d => d,
y => voted_data_bit,
status => status
);
controller: entity work.controller
port map(
clk => clk,
reset => reset,
di_ready => di_ready,
do_ready => do_ready,
control_signals => control_signals,
voted_data_selector => voted_data_selector
);
registers: entity work.registers
port map(
clk => clk,
reset => reset,
voted_data_bit => voted_data_bit,
status => status,
control_signals => control_signals,
ECC_signal => ECC_signal,
voted_data_out => voted_data_out,
status_out => status_out,
ECC_out => ECC_out
);
ECC: entity work.ECC
port map(
voted_data_out => voted_data_out,
status_out => status_out,
ECC_signal => ECC_signal
);
-- End of entity declarations
-- Add a process for the mux that will control the serial output from liaison
process(voted_data_selector, voted_data_out, status_out, ECC_out)
begin
case voted_data_selector is
when "0000" => -- 00
voted_data <= voted_data_out(0);
when "0001" => -- 01
voted_data <= voted_data_out(1);
when "0010" => -- 02
voted_data <= voted_data_out(2);
when "0011" => -- 03
voted_data <= voted_data_out(3);
when "0100" => -- 04
voted_data <= voted_data_out(4);
when "0101" => -- 05
voted_data <= voted_data_out(5);
when "0110" => -- 06
voted_data <= voted_data_out(6);
when "0111" => -- 07
voted_data <= voted_data_out(7);
when "1000" => -- 08
voted_data <= status_out(0);
when "1001" => -- 09
voted_data <= status_out(1);
when "1010" => -- 10
voted_data <= status_out(2);
when "1011" => -- 11
voted_data <= ECC_out(0);
when "1100" => -- 12
voted_data <= ECC_out(1);
when "1101" => -- 13
voted_data <= ECC_out(2);
when "1110" => -- 14
voted_data <= ECC_out(3);
when others =>
voted_data <= '-'; -- should not be reached, but useful to detect glitches
end case; -- when implementing and perfecting output throughput
end process;
end liaison;
|
apache-2.0
|
e3ef28eb805dab0c9c4845645873bea6
| 0.622748 | 2.913508 | false | false | false | false |
Ttl/bf_cpu
|
decoder.vhd
| 1 | 1,708 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Decoder reads the instruction from RAM and outputs
-- the datapath control signals for executing that
-- instruction
entity decoder is
Port ( instr : in STD_LOGIC_VECTOR(7 downto 0);
d_alutoreg : out STD_LOGIC;
d_alua : out STD_LOGIC_VECTOR(1 downto 0);
d_alub : out STD_LOGIC_VECTOR(1 downto 0);
d_write : out STD_LOGIC;
d_read : out STD_LOGIC;
d_jumpf : out STD_LOGIC;
d_jumpb : out STD_LOGIC
);
end decoder;
architecture Behavioral of decoder is
begin
process(instr)
begin
-- d_alutoreg
-- 0 : write alu result to mem(pointer)
-- 1 : write alu result to pointer
-- d_alua
-- 00 : mem(pointer)
-- 01 : pointer
-- 10 : read from input
-- 11 : illegal
-- d_alub
-- 00 : 0
-- 01 : 1
-- 10 : Illegal
-- 11 : -1
-- d_write
-- 1 : write alu result to output
d_alutoreg <= '0';
d_alub <= "00";
d_alua <= "00";
d_write <= '0';
d_read <= '0';
d_jumpf <= '0';
d_jumpb <= '0';
case instr is
-- <
when x"3C" =>
d_alutoreg <= '1';
d_alua <= "01";
d_alub <= "11";
-- >
when x"3E" =>
d_alutoreg <= '1';
d_alua <= "01";
d_alub <= "01";
-- +
when x"2B" =>
d_alub <= "01";
-- -
when x"2D" =>
d_alub <= "11";
-- .
when x"2E" =>
d_write <= '1';
-- ,
when x"2C" =>
d_read <= '1';
d_alua <= "10";
-- [
when x"5B" =>
d_jumpf <= '1';
-- ]
when x"5D" =>
d_jumpb <= '1';
when others =>
-- nop
end case;
end process;
end Behavioral;
|
lgpl-3.0
|
2db654779476a862862173506a8656b2
| 0.472482 | 3.151292 | false | false | false | false |
freecores/t48
|
rtl/vhdl/system/t8050_wb.vhd
| 1 | 9,691 |
-------------------------------------------------------------------------------
--
-- T8048 Microcontroller System
-- 8050 toplevel with Wishbone interface
--
-- $Id: t8050_wb.vhd,v 1.5 2006-07-14 01:14:22 arniml Exp $
-- $Name: not supported by cvs2svn $
--
-- Copyright (c) 2005, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity t8050_wb is
generic (
gate_port_input_g : integer := 1
);
port (
-- T48 Interface ----------------------------------------------------------
xtal_i : in std_logic;
reset_n_i : in std_logic;
t0_i : in std_logic;
t0_o : out std_logic;
t0_dir_o : out std_logic;
int_n_i : in std_logic;
ea_i : in std_logic;
rd_n_o : out std_logic;
psen_n_o : out std_logic;
wr_n_o : out std_logic;
ale_o : out std_logic;
t1_i : in std_logic;
p2_i : in std_logic_vector( 7 downto 0);
p2_o : out std_logic_vector( 7 downto 0);
p2l_low_imp_o : out std_logic;
p2h_low_imp_o : out std_logic;
p1_i : in std_logic_vector( 7 downto 0);
p1_o : out std_logic_vector( 7 downto 0);
p1_low_imp_o : out std_logic;
prog_n_o : out std_logic;
-- Wishbone Interface -----------------------------------------------------
wb_cyc_o : out std_logic;
wb_stb_o : out std_logic;
wb_we_o : out std_logic;
wb_adr_o : out std_logic_vector(23 downto 0);
wb_ack_i : in std_logic;
wb_dat_i : in std_logic_vector( 7 downto 0);
wb_dat_o : out std_logic_vector( 7 downto 0)
);
end t8050_wb;
library ieee;
use ieee.numeric_std.all;
use work.t48_core_comp_pack.t48_core;
use work.t48_core_comp_pack.syn_rom;
use work.t48_core_comp_pack.syn_ram;
use work.t48_system_comp_pack.t48_wb_master;
architecture struct of t8050_wb is
-- Address width of internal ROM
constant rom_addr_width_c : natural := 12;
signal xtal3_s : std_logic;
signal dmem_addr_s : std_logic_vector( 7 downto 0);
signal dmem_we_s : std_logic;
signal dmem_data_from_s : std_logic_vector( 7 downto 0);
signal dmem_data_to_s : std_logic_vector( 7 downto 0);
signal pmem_addr_s : std_logic_vector(11 downto 0);
signal pmem_data_s : std_logic_vector( 7 downto 0);
signal ea_s : std_logic;
signal ale_s : std_logic;
signal wr_n_s : std_logic;
signal rd_n_s : std_logic;
signal db_bus_to_t48,
db_bus_from_t48 : std_logic_vector( 7 downto 0);
signal wb_en_clk_s : std_logic;
signal xtal_en_s : std_logic;
signal p1_in_s,
p1_out_s : std_logic_vector( 7 downto 0);
signal p2_in_s,
p2_out_s : std_logic_vector( 7 downto 0);
begin
-----------------------------------------------------------------------------
-- Check generics for valid values.
-----------------------------------------------------------------------------
-- pragma translate_off
assert gate_port_input_g = 0 or gate_port_input_g = 1
report "gate_port_input_g must be either 1 or 0!"
severity failure;
-- pragma translate_on
t48_core_b : t48_core
generic map (
xtal_div_3_g => 1,
register_mnemonic_g => 1,
include_port1_g => 1,
include_port2_g => 1,
include_bus_g => 1,
include_timer_g => 1,
sample_t1_state_g => 4
)
port map (
xtal_i => xtal_i,
xtal_en_i => xtal_en_s,
reset_i => reset_n_i,
t0_i => t0_i,
t0_o => t0_o,
t0_dir_o => t0_dir_o,
int_n_i => int_n_i,
ea_i => ea_s,
rd_n_o => rd_n_s,
psen_n_o => psen_n_o,
wr_n_o => wr_n_s,
ale_o => ale_s,
db_i => db_bus_to_t48,
db_o => db_bus_from_t48,
db_dir_o => open,
t1_i => t1_i,
p2_i => p2_in_s,
p2_o => p2_out_s,
p2l_low_imp_o => p2l_low_imp_o,
p2h_low_imp_o => p2h_low_imp_o,
p1_i => p1_in_s,
p1_o => p1_out_s,
p1_low_imp_o => p1_low_imp_o,
prog_n_o => prog_n_o,
clk_i => xtal_i,
en_clk_i => xtal3_s,
xtal3_o => xtal3_s,
dmem_addr_o => dmem_addr_s,
dmem_we_o => dmem_we_s,
dmem_data_i => dmem_data_from_s,
dmem_data_o => dmem_data_to_s,
pmem_addr_o => pmem_addr_s,
pmem_data_i => pmem_data_s
);
-----------------------------------------------------------------------------
-- Gate port 1 and 2 input bus with respetive output value
-----------------------------------------------------------------------------
gate_ports: if gate_port_input_g = 1 generate
p1_in_s <= p1_i and p1_out_s;
p2_in_s <= p2_i and p2_out_s;
end generate;
pass_ports: if gate_port_input_g = 0 generate
p1_in_s <= p1_i;
p2_in_s <= p2_i;
end generate;
p1_o <= p1_out_s;
p2_o <= p2_out_s;
ale_o <= ale_s;
wr_n_o <= wr_n_s;
rd_n_o <= rd_n_s;
-----------------------------------------------------------------------------
-- Generate clock enable
-----------------------------------------------------------------------------
xtal_en_s <= wb_en_clk_s;
-----------------------------------------------------------------------------
-- Process ea
--
-- Purpose:
-- Detects access to external program memory.
-- Either by ea_i = '1' or when program memory address leaves address
-- range of internal ROM.
--
ea: process (ea_i,
pmem_addr_s)
begin
if ea_i = '1' then
-- Forced external access
ea_s <= '1';
-- elsif unsigned(pmem_addr_s(11 downto rom_addr_width_c)) = 0 then
else
-- Internal access
ea_s <= '0';
-- else
-- -- Access to program memory out of internal range
-- ea_s <= '1';
end if;
end process ea;
--
-----------------------------------------------------------------------------
wb_master_b : t48_wb_master
port map (
xtal_i => xtal_i,
res_i => reset_n_i,
en_clk_o => wb_en_clk_s,
ale_i => ale_s,
rd_n_i => rd_n_s,
wr_n_i => wr_n_s,
adr_i => p2_out_s(4),
db_bus_i => db_bus_from_t48,
db_bus_o => db_bus_to_t48,
wb_cyc_o => wb_cyc_o,
wb_stb_o => wb_stb_o,
wb_we_o => wb_we_o,
wb_adr_o => wb_adr_o,
wb_ack_i => wb_ack_i,
wb_dat_i => wb_dat_i,
wb_dat_o => wb_dat_o
);
rom_4k_b : syn_rom
generic map (
address_width_g => rom_addr_width_c
)
port map (
clk_i => xtal_i,
rom_addr_i => pmem_addr_s(rom_addr_width_c-1 downto 0),
rom_data_o => pmem_data_s
);
ram_256_b : syn_ram
generic map (
address_width_g => 8
)
port map (
clk_i => xtal_i,
res_i => reset_n_i,
ram_addr_i => dmem_addr_s(7 downto 0),
ram_data_i => dmem_data_to_s,
ram_we_i => dmem_we_s,
ram_data_o => dmem_data_from_s
);
end struct;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.4 2006/06/20 00:58:49 arniml
-- new input xtal_en_i
--
-- Revision 1.3 2005/11/01 21:39:14 arniml
-- wire signals for P2 low impedance marker issue
--
-- Revision 1.2 2005/06/11 10:16:05 arniml
-- introduce prefix 't48_' for wb_master entity and configuration
--
-- Revision 1.1 2005/05/08 10:36:59 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
gpl-2.0
|
7fdae03d6d649c3513ed9d194edcdf8e
| 0.507584 | 3.309768 | false | false | false | false |
Bourgeoisie/ECE368-RISC16
|
368RISC/Data Path/datapath.vhd
| 1 | 1,776 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:09:48 04/20/2015
-- Design Name:
-- Module Name: datapath - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;
USE work.UMDRISC_pkg.ALL;
use work.all;
entity datapath is
--Package declarations
port(
clk: in std_logic;
rst: in std_logic
--Inputs for each cycle of the pipeline
--##############################################
--=============================================
--Fetch Input
--=============================================
-- !---No Inputs Yet----!
--=============================================
--Decode Input
--=============================================
-- !---No Inputs Yet----!
--=============================================
--Operand Access
--=============================================
-- !---No Inputs Yet----!
--=============================================
--Execute
--=============================================
-- !---No Inputs Yet----!
--=============================================
--Writeback
--=============================================
---No Inputs Yet----!
--##############################################
);
end datapath;
architecture Behavioral of datapath is
--Signals between entities
--Group 1&2 has two signals:
--reg_a & reg_b //addresses of register A and register B
--im_S and im_L //4 & 8 bit size (respectively)
begin
end Behavioral;
|
mit
|
9a1c763a81047c8095a6adee4e266c29
| 0.363739 | 4.774194 | false | false | false | false |
michaelmiehling/A25_VME_TB
|
Testbench/SN74LVTH245.vhd
| 1 | 7,320 |
---------------------------------------------------------------
-- Title :
-- Project :
---------------------------------------------------------------
-- File : SN74LVTH245.vhd
-- Author : Michael Miehling
-- Email : [email protected]
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 09/02/12
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description :
--
--
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
-- Copyright (C) 2001, MEN Mikroelektronik Nuernberg GmbH
--
-- All rights reserved. Reproduction in whole or part is
-- prohibited without the written permission of the
-- copyright owner.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.1 $
--
-- $Log: SN74LVTH245.vhd,v $
-- Revision 1.1 2012/03/29 10:28:42 MMiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SN74LVTH245 IS
GENERIC (
OP_COND : integer:=1; -- 0=min, 1=typ, 2=max
WIDTH : integer:=8
);
PORT (
dir : IN std_logic; -- direction: 0= B data to A, 1= A data to B
oe_n : IN std_logic; -- output enable: 0= driver is active, 1= tri-state
a : INOUT std_logic_vector(WIDTH-1 DOWNTO 0); -- port A
b : INOUT std_logic_vector(WIDTH-1 DOWNTO 0) -- port B
);
END SN74LVTH245;
ARCHITECTURE SN74LVTH245_arch OF SN74LVTH245 IS
CONSTANT tPLH_max : time:= 3.5 ns;
CONSTANT tPHL_max : time:= 3.5 ns;
CONSTANT tPZH_max : time:= 5.5 ns;
CONSTANT tPZL_max : time:= 5.5 ns;
CONSTANT tPHZ_max : time:= 5.9 ns;
CONSTANT tPLZ_max : time:= 5.0 ns;
CONSTANT tPLH_min : time:= 1.2 ns;
CONSTANT tPHL_min : time:= 1.2 ns;
CONSTANT tPZH_min : time:= 1.3 ns;
CONSTANT tPZL_min : time:= 1.7 ns;
CONSTANT tPHZ_min : time:= 2.2 ns;
CONSTANT tPLZ_min : time:= 2.2 ns;
CONSTANT tPLH_typ : time:= 2.3 ns;
CONSTANT tPHL_typ : time:= 2.1 ns;
CONSTANT tPZH_typ : time:= 3.2 ns;
CONSTANT tPZL_typ : time:= 3.4 ns;
CONSTANT tPHZ_typ : time:= 3.5 ns;
CONSTANT tPLZ_typ : time:= 3.4 ns;
SIGNAL oe_n_in : std_logic;
SIGNAL dir_in : std_logic;
SIGNAL a_out : std_logic_vector(WIDTH-1 DOWNTO 0);
SIGNAL b_out : std_logic_vector(WIDTH-1 DOWNTO 0);
SIGNAL a_int : std_logic_vector(WIDTH-1 DOWNTO 0);
SIGNAL b_int : std_logic_vector(WIDTH-1 DOWNTO 0);
SIGNAL tPLH : time;
SIGNAL tPHL : time;
SIGNAL tPZH : time;
SIGNAL tPZL : time;
SIGNAL tPHZ : time;
SIGNAL tPLZ : time;
SIGNAL pwr_rst : std_logic;
BEGIN
tPLH <= tPLH_min WHEN OP_COND = 0 ELSE
tPLH_typ WHEN OP_COND = 1 ELSE
tPLH_max;
tPHL <= tPHL_min WHEN OP_COND = 0 ELSE
tPHL_typ WHEN OP_COND = 1 ELSE
tPHL_max;
tPZH <= tPZH_min WHEN OP_COND = 0 ELSE
tPZH_typ WHEN OP_COND = 1 ELSE
tPZH_max;
tPZL <= tPZL_min WHEN OP_COND = 0 ELSE
tPZL_typ WHEN OP_COND = 1 ELSE
tPZL_max;
tPHZ <= tPHZ_min WHEN OP_COND = 0 ELSE
tPHZ_typ WHEN OP_COND = 1 ELSE
tPHZ_max;
tPLZ <= tPLZ_min WHEN OP_COND = 0 ELSE
tPLZ_typ WHEN OP_COND = 1 ELSE
tPLZ_max;
a <= a_out;
b <= b_out;
a_int <= transport to_x01(a) after 1 ps;
b_int <= transport to_x01(b) after 1 ps;
oe_n_in <= to_x01(oe_n);
dir_in <= to_x01(dir);
pwr_rst <= '1', '0' AFTER 2 ps;
gen: FOR i IN 0 TO (WIDTH-1) GENERATE
PROCESS(pwr_rst, dir_in, oe_n_in, a_int, b_int, a_out(i), b_out(i))
BEGIN
IF pwr_rst'event AND dir_in = '0' AND oe_n_in = '1' THEN
a_out(i) <= 'H';
ELSIF pwr_rst'event AND dir_in = '0' AND oe_n_in = '0' THEN
a_out(i) <= b_int(i);
ELSIF (pwr_rst'event OR dir_in'event) AND dir_in = '1' THEN
a_out(i) <= 'H';
ELSIF (b_int(i)'event AND b_int(i) = '1' AND oe_n_in = '0' AND dir_in = '0') OR -- b 0->1
(dir_in'event AND dir_in = '0' AND oe_n_in = '0' AND b_int(i) = '1') THEN -- dir_in 1->0
a_out(i) <= transport b_int(i) AFTER tPLH;
ELSIF (b_int(i)'event AND b_int(i) = '0' AND oe_n_in = '0' AND dir_in = '0') OR -- b 1->0
(dir_in'event AND dir_in = '0' AND oe_n_in = '0' AND b_int(i) = '0') THEN -- dir_in 0->1
a_out(i) <= transport b_int(i) AFTER tPHL;
ELSIF (oe_n_in'event AND oe_n_in = '0' AND b_int(i) = '1' AND dir_in = '0') THEN -- oe_n_in 1->0 b=1
a_out(i) <= transport b_int(i) AFTER tPZH;
ELSIF (oe_n_in'event AND oe_n_in = '0' AND b_int(i) = '0' AND dir_in = '0') THEN -- oe_n_in 1->0 b=0
a_out(i) <= transport b_int(i) AFTER tPZL;
ELSIF (oe_n_in'event AND oe_n_in = '1' AND a_int(i) = '1' AND dir_in = '0') THEN -- oe_n_in 0->1 a=1
a_out(i) <= transport 'H' AFTER tPHZ;
ELSIF (oe_n_in'event AND oe_n_in = '1' AND a_int(i) = '0' AND dir_in = '0') THEN -- oe_n_in 0->1 a=0
a_out(i) <= transport 'H' AFTER tPLZ;
END IF;
IF pwr_rst'event AND dir_in = '1' AND oe_n_in = '1' THEN
b_out(i) <= 'H';
ELSIF pwr_rst'event AND dir_in = '1' AND oe_n_in = '0' THEN
b_out(i) <= a_int(i);
ELSIF (pwr_rst'event OR dir_in'event) AND dir_in = '0' THEN
b_out(i) <= 'H';
ELSIF (a_int(i)'event AND a_int(i) = '1' AND oe_n_in = '0' AND dir_in = '1') OR -- a 0->1
(dir_in'event AND dir_in = '1' AND oe_n_in = '0' AND a_int(i) = '1') THEN -- dir_in 0->1
b_out(i) <= transport a_int(i) AFTER tPLH;
ELSIF (a_int(i)'event AND a_int(i) = '0' AND oe_n_in = '0' AND dir_in = '1') OR -- a 1->0
(dir_in'event AND dir_in = '1' AND oe_n_in = '0' AND a_int(i) = '0') THEN -- dir_in 1->0
b_out(i) <= transport a_int(i) AFTER tPHL;
ELSIF (oe_n_in'event AND oe_n_in = '0' AND a_int(i) = '1' AND dir_in = '1') THEN -- oe_n_in 1->0 a=1
b_out(i) <= transport a_int(i) AFTER tPZH;
ELSIF (oe_n_in'event AND oe_n_in = '0' AND a_int(i) = '0' AND dir_in = '1') THEN -- oe_n_in 1->0 a=0
b_out(i) <= transport a_int(i) AFTER tPZL;
ELSIF (oe_n_in'event AND oe_n_in = '1' AND b_int(i) = '1' AND dir_in = '1') THEN -- oe_n_in 0->1 b=1
b_out(i) <= transport 'H' AFTER tPHZ;
ELSIF (oe_n_in'event AND oe_n_in = '1' AND b_int(i) = '0' AND dir_in = '1') THEN -- oe_n_in 0->1 b=0
b_out(i) <= transport 'H' AFTER tPLZ;
END IF;
END PROCESS;
END GENERATE gen;
END SN74LVTH245_arch;
|
gpl-3.0
|
45ccc977bf604c6895c6402abf78b0e0
| 0.463798 | 3.096447 | false | false | false | false |
nulldozer/purisc
|
Compute_Group/MAGIC_clocked/HAZARD_RESOLVE.vhd
| 2 | 2,329 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity HAZARD_RESOLVE is
PORT(
select_signal : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
hazard : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
hazard_advanced : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
end;
architecture resolve of HAZARD_RESOLVE is
signal data_present : std_logic;
signal buffer_output : std_logic_vector(31 downto 0);
signal data_buffer : std_logic_vector(31 downto 0);
signal hazard_rising_edge : std_logic;
signal hazard_artifial_delay : std_logic;
begin
process (CLK, RESET_n) begin
if (RESET_n = '0') then
hazard_artifial_delay <= '0';
elsif (rising_edge(CLK)) then
hazard_artifial_delay <= hazard_advanced;
end if;
end process;
--edge capture
hazard_rising_edge <= hazard_advanced and (hazard_advanced xor hazard);
data_present <= select_signal(15) or select_signal(14) or select_signal(13) or select_signal(12) or
select_signal(11) or select_signal(10) or select_signal(9) or select_signal(8) or
select_signal(7) or select_signal(6) or select_signal(5) or select_signal(4) or
select_signal(3) or select_signal(2) or select_signal(1) or select_signal(0);
buffering : process (CLK, RESET_n, hazard, data_present, data) begin
if (RESET_n = '0') then
buffer_output <= "00000000000000000000000000000000";
elsif (rising_edge(CLK)) then
if (data_present = '1' and hazard = '1') then
buffer_output <= data;
end if;
end if;
end process;
hazard_detect : process (hazard, data, data_buffer, RESET_n, buffer_output, data_present, CLK) begin
if (RESET_n = '0') then
data_buffer <= "00000000000000000000000000000000";
elsif (rising_edge(CLK))then --was on rising edge hazard
if (hazard_rising_edge = '1') then --this if never existed
if (data_present = '1') then
data_buffer <= data;
else
data_buffer <= buffer_output;
end if;
end if;
end if;
if (hazard = '0')then
if (data_present = '1') then
data_out <= data;
else
data_out <= buffer_output;
end if;
else
data_out <= data_buffer;
end if;
end process;
end;
|
gpl-2.0
|
f8ada2690746577c667c58d405b4bb83
| 0.641906 | 3.101198 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/altera_lnsim/ama_systolic_adder_function/_primary.vhd
| 5 | 4,135 |
library verilog;
use verilog.vl_types.all;
entity ama_systolic_adder_function is
generic(
width_data_in : integer := 1;
width_chainin : integer := 1;
width_data_out : integer := 1;
number_of_adder_input: integer := 1;
systolic_delay1 : string := "UNREGISTERED";
systolic_aclr1 : string := "NONE";
systolic_delay3 : string := "UNREGISTERED";
systolic_aclr3 : string := "NONE";
adder1_direction: string := "NONE";
adder3_direction: string := "NONE";
port_addnsub1 : string := "PORT_UNUSED";
addnsub_multiplier_register1: string := "CLOCK0";
addnsub_multiplier_aclr1: string := "ACLR3";
port_addnsub3 : string := "PORT_UNUSED";
addnsub_multiplier_register3: string := "CLOCK0";
addnsub_multiplier_aclr3: string := "ACLR3";
latency : integer := 0;
addnsub_multiplier_latency_clock1: string := "UNREGISTERED";
addnsub_multiplier_latency_aclr1: string := "NONE";
addnsub_multiplier_latency_clock3: string := "UNREGISTERED";
addnsub_multiplier_latency_aclr3: string := "NONE";
width_data_in_msb: vl_notype;
width_data_out_msb: vl_notype;
width_chainin_msb: vl_notype;
width_systolic : vl_notype;
width_systolic_msb: vl_notype;
input_ext_width : vl_notype
);
port(
data_in_0 : in vl_logic_vector;
data_in_1 : in vl_logic_vector;
data_in_2 : in vl_logic_vector;
data_in_3 : in vl_logic_vector;
chainin : in vl_logic_vector;
clock : in vl_logic_vector(3 downto 0);
aclr : in vl_logic_vector(3 downto 0);
ena : in vl_logic_vector(3 downto 0);
data_out : out vl_logic_vector;
addnsub1 : in vl_logic;
addnsub3 : in vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width_data_in : constant is 1;
attribute mti_svvh_generic_type of width_chainin : constant is 1;
attribute mti_svvh_generic_type of width_data_out : constant is 1;
attribute mti_svvh_generic_type of number_of_adder_input : constant is 1;
attribute mti_svvh_generic_type of systolic_delay1 : constant is 1;
attribute mti_svvh_generic_type of systolic_aclr1 : constant is 1;
attribute mti_svvh_generic_type of systolic_delay3 : constant is 1;
attribute mti_svvh_generic_type of systolic_aclr3 : constant is 1;
attribute mti_svvh_generic_type of adder1_direction : constant is 1;
attribute mti_svvh_generic_type of adder3_direction : constant is 1;
attribute mti_svvh_generic_type of port_addnsub1 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_register1 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_aclr1 : constant is 1;
attribute mti_svvh_generic_type of port_addnsub3 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_register3 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_aclr3 : constant is 1;
attribute mti_svvh_generic_type of latency : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_latency_clock1 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_latency_aclr1 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_latency_clock3 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_latency_aclr3 : constant is 1;
attribute mti_svvh_generic_type of width_data_in_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_out_msb : constant is 3;
attribute mti_svvh_generic_type of width_chainin_msb : constant is 3;
attribute mti_svvh_generic_type of width_systolic : constant is 3;
attribute mti_svvh_generic_type of width_systolic_msb : constant is 3;
attribute mti_svvh_generic_type of input_ext_width : constant is 3;
end ama_systolic_adder_function;
|
mit
|
4eee3c200864a984e8ce959489261fc2
| 0.652963 | 3.715184 | false | false | false | false |
Bourgeoisie/ECE368-RISC16
|
368RISC/Data Path/Fetch/fetch.vhd
| 1 | 2,692 |
--This VHD is credit to Group 1 & Group 2 for their design work
--=============================
--Author: Brett Bourgeois
--Date: 4/01/15
--Desc: Fetch
--=============================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;
USE work.UMDRISC_pkg.ALL;
use work.all;
entity fetch_struct is
Port (
----Inputs----
clk : in STD_LOGIC;
rst : in STD_LOGIC;
PC_En : in STD_LOGIC;
----Output----
pc_out : out std_logic_vector (4 downto 0);
ADRS_IMM : out std_logic_vector (3 downto 0);
ADRS_A : out std_logic_vector (3 downto 0);
ADRS_B : out std_logic_vector (3 downto 0);
Instruction_out : out std_logic_vector (15 downto 0);
OPcode_out : out std_logic_vector (3 downto 0)
);
end fetch_struct;
architecture structural of fetch_struct is
--================
--Signals--
--================
signal Instruction: std_logic_vector (15 downto 0) := (others => '0');
signal Instruction_mem: std_logic_vector (15 downto 0) := (others => '0');
signal PC_Current: std_logic_vector (4 downto 0) := (others => '0');
signal PC_New: std_logic_vector (4 downto 0) := (others => '0');
signal Opcode_sig: std_logic_vector (3 downto 0) := (others => '0');
-----------
begin
pc_out <= PC_Current;
Instruction_out <= Instruction;
Opcode_out <= Opcode_sig;
--assignment statements
--Instantiate components
--instantiated_name: entity work.<entity_name_being_instantiated>
--==================
-- Counter -> Program Counter
--==================
--!!!!!!!!!!!!!!!!!!!!!!!!
--Make an incrementing program counter!!!
--!!!!!!!!!!!!!!!!!!!!!!!!
PC: entity work.pcounter
generic map( regSize => BITREG_5)
port map(
--Standard Input
CLK => CLK,
RST => RST,
--Data in
PC_En => PC_En,
--Data out
PROGRAM_COUNTER => PC_Current);
--==================
-- Block RAM/ROM -> Insruction Memory
--==================
InMem: entity work.Instruct_Memory
port map
(
clkb => CLK,
addrb => PC_Current,
doutb => Instruction_mem,
clka => CLK,
addra => (others => '0'),
dina => (others => '0'),
wea(0) => '0'
);
--==================
-- Shift Register -> Hold instruction
--==================
InReg: entity work.Reg
generic map( regSize => BITREG_16)
port map(
--Standard Input
CLK => CLK,
RST => RST,
DataIn => Instruction_mem(15 downto 0),
--Split up the instruction into it's associated parts
--i.e RA, RB, IMM, OPCode
Full_Instr => Instruction,
DataOut(15 downto 12) => Opcode_sig,
DataOut(11 downto 8)=> ADRS_A,
DataOut(7 downto 4) => ADRS_B,
DataOut(3 downto 0) => ADRS_IMM);
end structural;
|
mit
|
d115506ea0b5cff1f9811f26ed0f98a0
| 0.558692 | 3.537451 | false | false | false | false |
freecores/t48
|
rtl/vhdl/psw.vhd
| 1 | 7,279 |
-------------------------------------------------------------------------------
--
-- The Program Status Word (PSW).
-- Implements the PSW with its special bits.
--
-- $Id: psw.vhd,v 1.8 2005-06-11 10:08:43 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t48_pack.word_t;
entity t48_psw is
port (
-- Global Interface -------------------------------------------------------
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
-- T48 Bus Interface ------------------------------------------------------
data_i : in word_t;
data_o : out word_t;
read_psw_i : in boolean;
read_sp_i : in boolean;
write_psw_i : in boolean;
write_sp_i : in boolean;
-- Decoder Interface ------------------------------------------------------
special_data_i : in std_logic;
inc_stackp_i : in boolean;
dec_stackp_i : in boolean;
write_carry_i : in boolean;
write_aux_carry_i : in boolean;
write_f0_i : in boolean;
write_bs_i : in boolean;
carry_o : out std_logic;
aux_carry_i : in std_logic;
aux_carry_o : out std_logic;
f0_o : out std_logic;
bs_o : out std_logic
);
end t48_psw;
library ieee;
use ieee.numeric_std.all;
use work.t48_pack.clk_active_c;
use work.t48_pack.res_active_c;
use work.t48_pack.bus_idle_level_c;
use work.t48_pack.nibble_t;
architecture rtl of t48_psw is
-- special bit positions in PSW
constant carry_c : natural := 3;
constant aux_carry_c : natural := 2;
constant f0_c : natural := 1;
constant bs_c : natural := 0;
-- the PSW register
signal psw_q : nibble_t;
-- the Stack Pointer
signal sp_q : unsigned(2 downto 0);
-- pragma translate_off
signal psw_s : word_t;
-- pragma translate_on
begin
-----------------------------------------------------------------------------
-- Process psw_reg
--
-- Purpose:
-- Implements the PSW register.
--
psw_reg: process (res_i, clk_i)
begin
if res_i = res_active_c then
psw_q <= (others => '0');
sp_q <= (others => '0');
elsif clk_i'event and clk_i = clk_active_c then
if en_clk_i then
-- T48 bus access
if write_psw_i then
psw_q <= data_i(7 downto 4);
end if;
if write_sp_i then
sp_q <= unsigned(data_i(2 downto 0));
end if;
-- increment Stack Pointer
if inc_stackp_i then
sp_q <= sp_q + 1;
end if;
-- decrement Stack Pointer
if dec_stackp_i then
sp_q <= sp_q - 1;
end if;
-- access to special bits
if write_carry_i then
psw_q(carry_c) <= special_data_i;
end if;
--
if write_aux_carry_i then
psw_q(aux_carry_c) <= aux_carry_i;
end if;
--
if write_f0_i then
psw_q(f0_c) <= special_data_i;
end if;
--
if write_bs_i then
psw_q(bs_c) <= special_data_i;
end if;
end if;
end if;
end process psw_reg;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process data_out
--
-- Purpose:
-- Output multiplexer for T48 Data Bus.
--
data_out: process (read_psw_i,
read_sp_i,
psw_q,
sp_q)
begin
data_o <= (others => bus_idle_level_c);
if read_psw_i then
data_o(7 downto 4) <= psw_q;
end if;
if read_sp_i then
data_o(3 downto 0) <= '1' & std_logic_vector(sp_q);
end if;
end process data_out;
--
-----------------------------------------------------------------------------
-- pragma translate_off
tb: process (psw_q, sp_q)
begin
psw_s(7 downto 4) <= psw_q;
psw_s(3) <= '1';
psw_s(2 downto 0) <= std_logic_vector(sp_q);
end process tb;
-- pragma translate_on
-----------------------------------------------------------------------------
-- Output mapping.
-----------------------------------------------------------------------------
carry_o <= psw_q(carry_c);
aux_carry_o <= psw_q(aux_carry_c);
f0_o <= psw_q(f0_c);
bs_o <= psw_q(bs_c);
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.7 2004/07/11 16:51:33 arniml
-- cleanup copyright notice
--
-- Revision 1.6 2004/04/24 23:44:25 arniml
-- move from std_logic_arith to numeric_std
--
-- Revision 1.5 2004/04/24 11:25:39 arniml
-- removed dummy_s - workaround not longer needed for GHDL 0.11.1
--
-- Revision 1.4 2004/04/18 18:59:01 arniml
-- add temporary workaround for GHDL 0.11
--
-- Revision 1.3 2004/04/04 14:15:45 arniml
-- add dump_compare support
--
-- Revision 1.2 2004/03/28 21:28:13 arniml
-- take auxiliary carry from direct ALU connection
--
-- Revision 1.1 2004/03/23 21:31:53 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
gpl-2.0
|
6fbe3f76f5e72d87485479fa5305c126
| 0.523286 | 3.855403 | false | false | false | false |
dominiklohmann/mikrorechner
|
vhdl/procPkg.vhd
| 1 | 2,417 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package procPkg is
constant opcAdd : std_logic_vector (4 downto 0) := "00000";
constant opcSub : std_logic_vector (4 downto 0) := "00001";
constant opcAnd : std_logic_vector (4 downto 0) := "00010";
constant opcOr : std_logic_vector (4 downto 0) := "00011";
constant opcXor : std_logic_vector (4 downto 0) := "00100";
constant opcNot : std_logic_vector (4 downto 0) := "00101";
constant opcShl : std_logic_vector (4 downto 0) := "00110";
constant opcShr : std_logic_vector (4 downto 0) := "00111";
constant opcMove : std_logic_vector (4 downto 0) := "10000";
constant opcAkkuLoad : std_logic_vector (4 downto 0) := "10001";
constant opcAkkuStore : std_logic_vector (4 downto 0) := "10010";
constant opcLoadMemory : std_logic_vector (4 downto 0) := "10111";
constant opcStoreMemory : std_logic_vector (4 downto 0) := "10100";
constant opciStore : std_logic_vector (4 downto 0) := "10101";
constant opciLoad : std_logic_vector (4 downto 0) := "10110";
constant opcJmp : std_logic_vector (4 downto 0) := "11000";
constant opcNoOp : std_logic_vector (4 downto 0) := "11110";
constant opcHALTSTOP : std_logic_vector (4 downto 0) := "11111";
constant aluAdd : std_logic_vector (3 downto 0) := "0000";
constant aluSub : std_logic_vector (3 downto 0) := "0001";
constant aluAnd : std_logic_vector (3 downto 0) := "0010";
constant aluOr : std_logic_vector (3 downto 0) := "0011";
constant aluXor : std_logic_vector (3 downto 0) := "0100";
constant aluNot : std_logic_vector (3 downto 0) := "0101";
constant aluShl : std_logic_vector (3 downto 0) := "0110";
constant aluShr : std_logic_vector (3 downto 0) := "0111";
-- component decl. ------------------------------------------------------
component procIdea is
port( clk : in std_logic; -- clock
nRst : in std_logic; -- not reset
iAddr : out std_logic_vector(31 downto 0); -- instMem address
iData : in std_logic_vector(31 downto 0); -- instMem data
dnWE : out std_logic; -- dataMem write-ena
dnOE : out std_logic; -- dataMem output-ena
dAddr : out std_logic_vector(31 downto 0); -- dataMem address
dData : inout std_logic_vector(31 downto 0)); -- dataMem data
end component procIdea;
end package procPkg;
------------------------------------------------------------------------------
-- procPkg.vhd - end
|
mit
|
3096214416f12d08ebdc6f415199f844
| 0.630947 | 2.922612 | false | false | false | false |
straywarrior/MadeCPUin21days
|
EXE_MEM_REG.vhd
| 1 | 2,988 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: StrayWarrior
--
-- Create Date: 14:18:20 11/14/2015
-- Design Name:
-- Module Name: EXE_MEM_REG - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity EXE_MEM_REG is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
clear : in STD_LOGIC;
stall : in STD_LOGIC;
RegWE_in : in STD_LOGIC;
RegDest_in : in STD_LOGIC_VECTOR (3 downto 0);
RegMemDIn_in : in STD_LOGIC_VECTOR (3 downto 0);
MemRd_in : in STD_LOGIC;
MemWE_in : in STD_LOGIC;
MemDIn_in : in STD_LOGIC_VECTOR (15 downto 0);
ALUout_in : in STD_LOGIC_VECTOR (15 downto 0);
RegWE_out : out STD_LOGIC;
RegDest_out : out STD_LOGIC_VECTOR (3 downto 0);
RegMemDIn_out : out STD_LOGIC_VECTOR (3 downto 0);
MemRd_out : out STD_LOGIC;
MemWE_out : out STD_LOGIC;
MemDIn_out : out STD_LOGIC_VECTOR (15 downto 0);
ALUout_out : out STD_LOGIC_VECTOR (15 downto 0)
);
end EXE_MEM_REG;
architecture Behavioral of EXE_MEM_REG is
begin
process (clear, clk)
begin
if (reset = '0') then
RegWE_out <= '0';
RegDest_out <= (others => '1');
RegMemDIn_out <= (others => '1');
MemRd_out <= '0';
MemWE_out <= '0';
MemDIn_out <= (others => '0');
ALUout_out <= (others => '0');
elsif (clk'event and clk = '1') then
if (clear = '0' and stall = '0') then
RegWE_out <= RegWE_in;
RegDest_out <= RegDest_in;
RegMemDIn_out <= RegMemDIn_in;
MemRd_out <= MemRd_in;
MemWE_out <= MemWE_in;
MemDIn_out <= MemDIn_in;
ALUout_out <= ALUout_in;
elsif (clear = '1' and stall = '0') then
RegWE_out <= '0';
RegDest_out <= (others => '1');
RegMemDIn_out <= (others => '1');
MemRd_out <= '0';
MemWE_out <= '0';
MemDIn_out <= (others => '0');
ALUout_out <= (others => '0');
else
-- Insert a bubble here
null;
end if;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
eb008e0537aff3bc36dfe0de38b03b12
| 0.483601 | 3.994652 | false | false | false | false |
sukinull/hls_stream
|
Vivado/example.hls/example.hls.srcs/sources_1/bd/tutorial/ip/tutorial_axi_vdma_0_0/sim/tutorial_axi_vdma_0_0.vhd
| 1 | 21,337 |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_vdma:6.2
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_vdma_v6_2;
USE axi_vdma_v6_2.axi_vdma;
ENTITY tutorial_axi_vdma_0_0 IS
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axis_mm2s_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mm2s_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
mm2s_introut : OUT STD_LOGIC
);
END tutorial_axi_vdma_0_0;
ARCHITECTURE tutorial_axi_vdma_0_0_arch OF tutorial_axi_vdma_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tutorial_axi_vdma_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_vdma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_ENABLE_VIDPRMTR_READS : INTEGER;
C_DYNAMIC_RESOLUTION : INTEGER;
C_NUM_FSTORES : INTEGER;
C_USE_FSYNC : INTEGER;
C_USE_MM2S_FSYNC : INTEGER;
C_USE_S2MM_FSYNC : INTEGER;
C_FLUSH_ON_FSYNC : INTEGER;
C_INCLUDE_INTERNAL_GENLOCK : INTEGER;
C_INCLUDE_SG : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_MM2S_GENLOCK_MODE : INTEGER;
C_MM2S_GENLOCK_NUM_MASTERS : INTEGER;
C_MM2S_GENLOCK_REPEAT_EN : INTEGER;
C_MM2S_SOF_ENABLE : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_LINEBUFFER_DEPTH : INTEGER;
C_MM2S_LINEBUFFER_THRESH : INTEGER;
C_MM2S_MAX_BURST_LENGTH : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TUSER_BITS : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_S2MM_GENLOCK_MODE : INTEGER;
C_S2MM_GENLOCK_NUM_MASTERS : INTEGER;
C_S2MM_GENLOCK_REPEAT_EN : INTEGER;
C_S2MM_SOF_ENABLE : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_LINEBUFFER_DEPTH : INTEGER;
C_S2MM_LINEBUFFER_THRESH : INTEGER;
C_S2MM_MAX_BURST_LENGTH : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TUSER_BITS : INTEGER;
C_ENABLE_DEBUG_ALL : INTEGER;
C_ENABLE_DEBUG_INFO_0 : INTEGER;
C_ENABLE_DEBUG_INFO_1 : INTEGER;
C_ENABLE_DEBUG_INFO_2 : INTEGER;
C_ENABLE_DEBUG_INFO_3 : INTEGER;
C_ENABLE_DEBUG_INFO_4 : INTEGER;
C_ENABLE_DEBUG_INFO_5 : INTEGER;
C_ENABLE_DEBUG_INFO_6 : INTEGER;
C_ENABLE_DEBUG_INFO_7 : INTEGER;
C_ENABLE_DEBUG_INFO_8 : INTEGER;
C_ENABLE_DEBUG_INFO_9 : INTEGER;
C_ENABLE_DEBUG_INFO_10 : INTEGER;
C_ENABLE_DEBUG_INFO_11 : INTEGER;
C_ENABLE_DEBUG_INFO_12 : INTEGER;
C_ENABLE_DEBUG_INFO_13 : INTEGER;
C_ENABLE_DEBUG_INFO_14 : INTEGER;
C_ENABLE_DEBUG_INFO_15 : INTEGER;
C_INSTANCE : STRING;
C_FAMILY : STRING
);
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axis_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
s_axis_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mm2s_fsync : IN STD_LOGIC;
mm2s_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mm2s_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
s2mm_fsync : IN STD_LOGIC;
s2mm_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
s2mm_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
mm2s_buffer_empty : OUT STD_LOGIC;
mm2s_buffer_almost_empty : OUT STD_LOGIC;
s2mm_buffer_full : OUT STD_LOGIC;
s2mm_buffer_almost_full : OUT STD_LOGIC;
mm2s_fsync_out : OUT STD_LOGIC;
s2mm_fsync_out : OUT STD_LOGIC;
mm2s_prmtr_update : OUT STD_LOGIC;
s2mm_prmtr_update : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_vdma_tstvec : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END COMPONENT axi_vdma;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIS_MM2S_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_frame_ptr_out: SIGNAL IS "xilinx.com:signal:video_frame_ptr:1.0 MM2S_FRAME_PTR_OUT FRAME_PTR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TUSER";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT";
BEGIN
U0 : axi_vdma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 9,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 1,
C_ENABLE_VIDPRMTR_READS => 1,
C_DYNAMIC_RESOLUTION => 1,
C_NUM_FSTORES => 3,
C_USE_FSYNC => 1,
C_USE_MM2S_FSYNC => 0,
C_USE_S2MM_FSYNC => 2,
C_FLUSH_ON_FSYNC => 1,
C_INCLUDE_INTERNAL_GENLOCK => 1,
C_INCLUDE_SG => 0,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_INCLUDE_MM2S => 1,
C_MM2S_GENLOCK_MODE => 0,
C_MM2S_GENLOCK_NUM_MASTERS => 1,
C_MM2S_GENLOCK_REPEAT_EN => 0,
C_MM2S_SOF_ENABLE => 1,
C_INCLUDE_MM2S_DRE => 1,
C_INCLUDE_MM2S_SF => 0,
C_MM2S_LINEBUFFER_DEPTH => 4096,
C_MM2S_LINEBUFFER_THRESH => 4,
C_MM2S_MAX_BURST_LENGTH => 8,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 64,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_M_AXIS_MM2S_TUSER_BITS => 1,
C_INCLUDE_S2MM => 0,
C_S2MM_GENLOCK_MODE => 0,
C_S2MM_GENLOCK_NUM_MASTERS => 1,
C_S2MM_GENLOCK_REPEAT_EN => 1,
C_S2MM_SOF_ENABLE => 1,
C_INCLUDE_S2MM_DRE => 0,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_LINEBUFFER_DEPTH => 512,
C_S2MM_LINEBUFFER_THRESH => 4,
C_S2MM_MAX_BURST_LENGTH => 8,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 64,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_TUSER_BITS => 1,
C_ENABLE_DEBUG_ALL => 0,
C_ENABLE_DEBUG_INFO_0 => 0,
C_ENABLE_DEBUG_INFO_1 => 0,
C_ENABLE_DEBUG_INFO_2 => 0,
C_ENABLE_DEBUG_INFO_3 => 0,
C_ENABLE_DEBUG_INFO_4 => 0,
C_ENABLE_DEBUG_INFO_5 => 0,
C_ENABLE_DEBUG_INFO_6 => 0,
C_ENABLE_DEBUG_INFO_7 => 0,
C_ENABLE_DEBUG_INFO_8 => 0,
C_ENABLE_DEBUG_INFO_9 => 0,
C_ENABLE_DEBUG_INFO_10 => 0,
C_ENABLE_DEBUG_INFO_11 => 0,
C_ENABLE_DEBUG_INFO_12 => 0,
C_ENABLE_DEBUG_INFO_13 => 0,
C_ENABLE_DEBUG_INFO_14 => 0,
C_ENABLE_DEBUG_INFO_15 => 0,
C_INSTANCE => "axi_vdma",
C_FAMILY => "zynq"
)
PORT MAP (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => '0',
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axis_mm2s_aclk => m_axis_mm2s_aclk,
m_axi_s2mm_aclk => '0',
s_axis_s2mm_aclk => '0',
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
mm2s_fsync => '0',
mm2s_frame_ptr_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
mm2s_frame_ptr_out => mm2s_frame_ptr_out,
s2mm_fsync => '0',
s2mm_frame_ptr_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
m_axi_sg_arready => '0',
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_rlast => '0',
m_axi_sg_rvalid => '0',
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tuser => m_axis_mm2s_tuser,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axi_s2mm_awready => '0',
m_axi_s2mm_wready => '0',
m_axi_s2mm_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_s2mm_bvalid => '0',
s_axis_s2mm_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_s2mm_tkeep => X"F",
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_s2mm_tvalid => '0',
s_axis_s2mm_tlast => '0',
mm2s_introut => mm2s_introut
);
END tutorial_axi_vdma_0_0_arch;
|
gpl-2.0
|
8966417c306defdfac9804da698877f5
| 0.660027 | 2.845692 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/altera_lnsim/generic_28nm_hp_mlab_cell_impl/_primary.vhd
| 5 | 2,780 |
library verilog;
use verilog.vl_types.all;
entity generic_28nm_hp_mlab_cell_impl is
generic(
logical_ram_name: string := "lutram";
logical_ram_depth: integer := 0;
logical_ram_width: integer := 0;
first_address : integer := 0;
last_address : integer := 0;
first_bit_number: integer := 0;
mixed_port_feed_through_mode: string := "new";
init_file : string := "NONE";
data_width : integer := 20;
address_width : integer := 6;
byte_enable_mask_width: integer := 1;
byte_size : integer := 1;
port_b_data_out_clock: string := "none";
port_b_data_out_clear: string := "none";
lpm_type : string := "common_28nm_mlab_cell";
lpm_hint : string := "true";
mem_init0 : string := ""
);
port(
portadatain : in vl_logic_vector;
portaaddr : in vl_logic_vector;
portabyteenamasks: in vl_logic_vector;
portbaddr : in vl_logic_vector;
clk0 : in vl_logic;
clk1 : in vl_logic;
ena0 : in vl_logic;
ena1 : in vl_logic;
ena2 : in vl_logic;
clr : in vl_logic;
devclrn : in vl_logic;
devpor : in vl_logic;
portbdataout : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of logical_ram_name : constant is 1;
attribute mti_svvh_generic_type of logical_ram_depth : constant is 1;
attribute mti_svvh_generic_type of logical_ram_width : constant is 1;
attribute mti_svvh_generic_type of first_address : constant is 1;
attribute mti_svvh_generic_type of last_address : constant is 1;
attribute mti_svvh_generic_type of first_bit_number : constant is 1;
attribute mti_svvh_generic_type of mixed_port_feed_through_mode : constant is 1;
attribute mti_svvh_generic_type of init_file : constant is 1;
attribute mti_svvh_generic_type of data_width : constant is 1;
attribute mti_svvh_generic_type of address_width : constant is 1;
attribute mti_svvh_generic_type of byte_enable_mask_width : constant is 1;
attribute mti_svvh_generic_type of byte_size : constant is 1;
attribute mti_svvh_generic_type of port_b_data_out_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_data_out_clear : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of mem_init0 : constant is 1;
end generic_28nm_hp_mlab_cell_impl;
|
mit
|
3687849acc1b4d5a5cd5fd04f492cfc5
| 0.597122 | 3.624511 | false | false | false | false |
sukinull/hls_stream
|
Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/v_cresample_v4_0/25f1d393/hdl/v_cresample_v4_0_vh_rfs.vhd
| 1 | 577,272 |
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|
gpl-2.0
|
3e0643d0e82a0dfbfa50a26253511646
| 0.955513 | 1.825712 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_delay_GNNBTO2F3L.vhd
| 4 | 1,062 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNNBTO2F3L is
generic ( ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "000000000000000000000010";
width : positive := 24);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector((width)-1 downto 0);
output : out std_logic_vector((width)-1 downto 0);
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_delay_GNNBTO2F3L is
Begin
-- Delay Element
Delay1i : alt_dspbuilder_SDelay generic map (
LPM_WIDTH => 24,
LPM_DELAY => 1,
SequenceLength => 1,
SequenceValue => "1")
port map (
dataa => input,
clock => clock,
ena => ena,
sclr => sclr,
aclr => aclr,
user_aclr => '0',
result => output);
end architecture;
|
mit
|
1905daed9ec8ee4f77cc741f898939ca
| 0.635593 | 2.958217 | false | false | false | false |
michaelmiehling/A25_VME_TB
|
Testbench/a25_tb.vhd
| 1 | 36,338 |
---------------------------------------------------------------
-- Title : Testbench A25
-- Project :
---------------------------------------------------------------
-- File : a25_tb.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 31/01/12
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description :
--
--
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.fpga_pkg_2.ALL;
USE work.vme_sim_pack.all;
USE work.terminal_pkg.all;
use work.pcie_sim_pkg.all;
ENTITY a25_tb IS
generic(
BFM_LANE_WIDTH : integer range 8 downto 0 := 1 -- set configuration: 1=x1, 2=x2, 4=x4 and 8=x8
);
END a25_tb;
ARCHITECTURE a25_tb_arch OF a25_tb IS
COMPONENT A25_top
GENERIC (
SIMULATION : boolean := FALSE;
FPGA_FAMILY : family_type := CYCLONE4;
BFM_LANE_WIDTH : integer range 8 downto 0 := 1; -- set configuration: 1=x1, 2=x2, 4=x4 and 8=x8
sets : std_logic_vector(3 DOWNTO 0) := "1110";
timeout : integer := 5000 );
PORT (
clk_16mhz : IN std_logic;
led_green_n : OUT std_logic;
led_red_n : OUT std_logic;
hreset_n : IN std_logic; -- reset
v2p_rstn : OUT std_logic; -- connected to hreset_req1_n
fpga_test : INOUT std_logic_vector(5 DOWNTO 1);
-- pcie
refclk : IN std_logic; -- 100 MHz pcie clock
pcie_rx : IN std_logic_vector(3 DOWNTO 0); -- PCIe receive line
pcie_tx : OUT std_logic_vector(3 DOWNTO 0); -- PCIe transmit line
-- sram bus
sr_clk : OUT std_logic;
sr_a : OUT std_logic_vector(18 DOWNTO 0);
sr_d : INOUT std_logic_vector(15 DOWNTO 0);
sr_bwa_n : OUT std_logic;
sr_bwb_n : OUT std_logic;
sr_bw_n : OUT std_logic;
sr_cs1_n : OUT std_logic;
sr_adsc_n : OUT std_logic;
sr_oe_n : OUT std_logic;
-- vmebus
vme_ga : IN std_logic_vector(4 DOWNTO 0); -- geographical addresses
vme_gap : IN std_logic; -- geographical addresses
vme_a : INOUT std_logic_vector(31 DOWNTO 0);
vme_a_dir : OUT std_logic;
vme_a_oe_n : OUT std_logic;
vme_d : INOUT std_logic_vector(31 DOWNTO 0);
vme_d_dir : OUT std_logic;
vme_d_oe_n : OUT std_logic;
vme_am_dir : OUT std_logic;
vme_am : INOUT std_logic_vector(5 DOWNTO 0);
vme_am_oe_n : OUT std_logic;
vme_write_n : INOUT std_logic;
vme_iack_n : INOUT std_logic;
vme_irq_i_n : IN std_logic_vector(7 DOWNTO 1);
vme_irq_o : OUT std_logic_vector(7 DOWNTO 1); -- high active on A25
vme_as_i_n : IN std_logic;
vme_as_o_n : OUT std_logic;
vme_as_oe : OUT std_logic; -- high active on A25
vme_retry_o_n : OUT std_logic;
vme_retry_oe : OUT std_logic; -- high active on A25
vme_retry_i_n : IN std_logic;
vme_sysres_i_n : IN std_logic;
vme_sysres_o : OUT std_logic; -- high active on A25
vme_ds_i_n : IN std_logic_vector(1 DOWNTO 0);
vme_ds_o_n : OUT std_logic_vector(1 DOWNTO 0);
vme_ds_oe : OUT std_logic; -- high active on A25
vme_berr_i_n : IN std_logic;
vme_berr_o : OUT std_logic; -- high active on A25
vme_dtack_i_n : IN std_logic;
vme_dtack_o : OUT std_logic; -- high active on A25
vme_scon : OUT std_logic; -- high active on A25
vme_sysfail_i_n : IN std_logic;
vme_sysfail_o : OUT std_logic; -- high active on A25
vme_bbsy_i_n : IN std_logic;
vme_bbsy_o : OUT std_logic; -- high active on A25
vme_bclr_i_n : IN std_logic; -- bus clear input
vme_bclr_o_n : OUT std_logic; -- bus clear output
vme_br_i_n : IN std_logic_vector(3 DOWNTO 0);
vme_br_o : OUT std_logic_vector(3 DOWNTO 0); -- high active on A25
vme_iack_i_n : IN std_logic;
vme_iack_o_n : OUT std_logic;
vme_acfail_i_n : IN std_logic;
vme_sysclk : OUT std_logic;
vme_bg_i_n : IN std_logic_vector(3 DOWNTO 0);
vme_bg_o_n : OUT std_logic_vector(3 DOWNTO 0);
-- Hard IP BFM connections
ep_rxvalid_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_rxstatus_i : in std_logic_vector(3*BFM_LANE_WIDTH -1 downto 0); -- 3bits per lane, [2:0]=lane0, [5:3]=lane1 etc.
ep_rxdatak_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bits per lane, [0]=lane0, [1]=lane1 etc.
ep_rxdata_i : in std_logic_vector(8*BFM_LANE_WIDTH -1 downto 0); -- 8bits per lane, [7:0]=lane0, [15:8]=lane1 etc.
ep_rxelecidle_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_phystatus_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_clk250_o : out std_logic; -- endpoint SERDES 250MHz clk output
ep_clk500_o : out std_logic; -- endpoint SERDES 500MHz clk output
ep_rate_ext_o : out std_logic; -- endpoint rate_ext
ep_powerdown_ext_o : out std_logic_vector(2*BFM_LANE_WIDTH -1 downto 0); -- 2bits per lane, [1:0]=lane0, [3:2]=lane1 etc.
ep_txdatak_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txdata_o : out std_logic_vector(8*BFM_LANE_WIDTH -1 downto 0); -- 8bits per lane, [7:0]=lane0, [15:8]=lane1 etc.
ep_txcompl_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txelecidle_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txdetectrx_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_rxpolarity_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_ltssm_o : out std_logic_vector(4 downto 0)
);
END COMPONENT;
COMPONENT MT58L512L18F
GENERIC (
-- Clock
tKC : TIME := 8.0 ns; -- Timing are for -6.8
tKH : TIME := 1.8 ns;
tKL : TIME := 1.8 ns;
-- Output Times
tKQHZ : TIME := 3.8 ns;
-- Setup Times
tAS : TIME := 1.8 ns;
tADSS : TIME := 1.8 ns;
tAAS : TIME := 1.8 ns;
tWS : TIME := 1.8 ns;
tDS : TIME := 1.8 ns;
tCES : TIME := 1.8 ns;
-- Hold Times
tAH : TIME := 0.5 ns;
tADSH : TIME := 0.5 ns;
tAAH : TIME := 0.5 ns;
tWH : TIME := 0.5 ns;
tDH : TIME := 0.5 ns;
tCEH : TIME := 0.5 ns;
-- Bus Width and Data Bus
addr_bits : INTEGER := 19;
data_bits : INTEGER := 18
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
Mode : IN STD_LOGIC;
Adv_n : IN STD_LOGIC;
Clk : IN STD_LOGIC;
Adsc_n : IN STD_LOGIC;
Adsp_n : IN STD_LOGIC;
Bwa_n : IN STD_LOGIC;
Bwb_n : IN STD_LOGIC;
Bwe_n : IN STD_LOGIC;
Gw_n : IN STD_LOGIC;
Ce_n : IN STD_LOGIC;
Ce2 : IN STD_LOGIC;
Ce2_n : IN STD_LOGIC;
Oe_n : IN STD_LOGIC;
Zz : IN STD_LOGIC
);
END COMPONENT;
COMPONENT vmebus
PORT (
slot1 : IN boolean:=TRUE; -- if true dut is in slot1
vme_slv_in : IN vme_slv_in_type;
vme_slv_out : OUT vme_slv_out_type;
vme_mon_out : OUT vme_mon_out_type;
terminal_in_x : OUT terminal_in_type;
terminal_out_x : IN terminal_out_type;
-- the VME signals:
vb_am : INOUT std_logic_vector(5 DOWNTO 0);
vb_data : INOUT std_logic_vector(31 DOWNTO 0);
vb_adr : INOUT std_logic_vector(31 DOWNTO 0);
vb_writen : INOUT std_logic;
vb_iackn : INOUT std_logic;
vb_asn : INOUT std_logic;
vb_dsan : INOUT std_logic;
vb_dsbn : INOUT std_logic;
vb_bbsyn : INOUT std_logic;
vb_berrn : INOUT std_logic;
vb_brn : INOUT std_logic_vector(3 DOWNTO 0);
vb_dtackn : INOUT std_logic;
vb_sysresn : INOUT std_logic;
vb_irq1n : INOUT std_logic;
vb_irq2n : INOUT std_logic;
vb_irq3n : INOUT std_logic;
vb_irq4n : INOUT std_logic;
vb_irq5n : INOUT std_logic;
vb_irq6n : INOUT std_logic;
vb_irq7n : INOUT std_logic;
vb_bgin : OUT std_logic_vector(3 DOWNTO 0);
vb_bgout : IN std_logic_vector(3 DOWNTO 0);
vb_iackin : OUT std_logic;
vb_iackout : IN std_logic;
vb_acfailn : INOUT std_logic
);
END COMPONENT;
COMPONENT SN74LVTH245
GENERIC (
OP_COND : integer:=1; -- 0=min, 1=typ, 2=max
WIDTH : integer:=8
);
PORT (
dir : IN std_logic; -- direction: 0= B data to A, 1= A data to B
oe_n : IN std_logic; -- output enable: 0= driver is active, 1= tri-state
a : INOUT std_logic_vector(WIDTH-1 DOWNTO 0); -- port A
b : INOUT std_logic_vector(WIDTH-1 DOWNTO 0) -- port B
);
END COMPONENT;
COMPONENT SN74ABT125
GENERIC (
OP_COND : integer:=1; -- 0=min, 1=typ, 2=max
WIDTH : integer:=8
);
PORT (
oe_n : IN std_logic_vector(WIDTH-1 DOWNTO 0); -- output enable: 0= driver is active, 1= tri-state
a : IN std_logic_vector(WIDTH-1 DOWNTO 0); -- port A
b : OUT std_logic_vector(WIDTH-1 DOWNTO 0) -- port B
);
END COMPONENT;
COMPONENT terminal
PORT (
hreset_n : OUT std_logic;
slot1 : OUT boolean:=TRUE; -- if true dut is in slot1
en_clk : OUT boolean;
terminal_in_0 : IN terminal_in_type;
terminal_out_0 : OUT terminal_out_type;
terminal_in_1 : IN terminal_in_type;
terminal_out_1 : OUT terminal_out_type;
v2p_rstn : IN std_logic; -- connected to hreset_req1_n
vme_slv_in : OUT vme_slv_in_type;
vme_slv_out : IN vme_slv_out_type;
vme_mon_out : IN vme_mon_out_type;
vme_ga : OUT std_logic_vector(4 DOWNTO 0); -- geographical addresses
vme_gap : OUT std_logic -- geographical addresses
);
END COMPONENT;
component pcie_sim
generic(
BFM_LANE_WIDTH : integer range 8 downto 0 := 1 -- set configuration: 1=x1, 2=x2, 4=x4 and 8=x8
);
port(
rst_i : in std_logic;
pcie_rstn_i : in std_logic;
clk_i : in std_logic;
ep_clk250_i : in std_logic; -- endpoint SERDES 250MHz clk output
ep_clk500_i : in std_logic; -- endpoint SERDES 500MHz clk output
-- PCIe lanes
bfm_tx_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0);
bfm_rx_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0);
-- PCIe SERDES connection, in/out references are BFM view
ep_rate_ext_i : in std_logic; -- endpoint rate_ext
ep_powerdown_ext_i : in std_logic_vector(2*BFM_LANE_WIDTH -1 downto 0); -- 2bits per lane, [1:0]=lane0, [3:2]=lane1 etc.
ep_txdatak_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txdata_i : in std_logic_vector(8*BFM_LANE_WIDTH -1 downto 0); -- 8bits per lane, [7:0]=lane0, [15:8]=lane1 etc.
ep_txcompl_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txelecidle_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txdetectrx_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_rxpolarity_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_ltssm_i : in std_logic_vector(4 downto 0);
ep_rxvalid_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_rxstatus_o : out std_logic_vector(3*BFM_LANE_WIDTH -1 downto 0); -- 3bits per lane, [2:0]=lane0, [5:3]=lane1 etc.
ep_rxdatak_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bits per lane, [0]=lane0, [1]=lane1 etc.
ep_rxdata_o : out std_logic_vector(8*BFM_LANE_WIDTH -1 downto 0); -- 8bits per lane, [7:0]=lane0, [15:8]=lane1 etc.
ep_rxelecidle_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_phystatus_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
-- MEN terminal connection, in/out references are terminal view
term_out : in terminal_out_type;
term_in : out terminal_in_type
);
end component;
CONSTANT T_FPGA_TO_SRAM : time := 0 ns;
SIGNAL clk_125 : std_logic:='1';
SIGNAL clk_250 : std_logic:='0';
SIGNAL clk_16mhz_int : std_logic:='0';
SIGNAL clk_16mhz : std_logic:='0';
SIGNAL en_clk : boolean;
SIGNAL led_green_n : std_logic;
SIGNAL led_red_n : std_logic;
SIGNAL hreset_n : std_logic; -- reset
SIGNAL hreset : std_logic; -- reset
SIGNAL v2p_rstn : std_logic; -- connected to hreset_req1_n
SIGNAL refclk : std_logic:='0'; -- 100 MHz pcie clock
SIGNAL pcie_rx : std_logic_vector(3 DOWNTO 0); -- PCIe receive line
SIGNAL pcie_tx : std_logic_vector(3 DOWNTO 0); -- PCIe transmit line
SIGNAL sr_clk : std_logic;
SIGNAL trans_sr_clk : std_logic;
SIGNAL sr_a : std_logic_vector(18 DOWNTO 0);
SIGNAL sr_d : std_logic_vector(15 DOWNTO 0);
SIGNAL sr_bwa_n : std_logic;
SIGNAL sr_bwb_n : std_logic;
SIGNAL sr_bw_n : std_logic;
SIGNAL sr_cs1_n : std_logic;
SIGNAL sr_adsc_n : std_logic;
SIGNAL sr_oe_n : std_logic;
SIGNAL vme_ga : std_logic_vector(4 DOWNTO 0);
SIGNAL vme_gap : std_logic;
SIGNAL vme_a : std_logic_vector(31 DOWNTO 0);
SIGNAL vme_a_dir : std_logic;
SIGNAL vme_a_oe_n : std_logic;
SIGNAL vme_d : std_logic_vector(31 DOWNTO 0);
SIGNAL vme_d_dir : std_logic;
SIGNAL vme_d_oe_n : std_logic;
SIGNAL vme_am_dir : std_logic;
SIGNAL vme_am : std_logic_vector(5 DOWNTO 0);
SIGNAL vme_am_oe_n : std_logic;
SIGNAL vme_write_n : std_logic;
SIGNAL vme_iack_n : std_logic;
SIGNAL vme_irq_i_n : std_logic_vector(7 DOWNTO 1);
SIGNAL vme_irq_o_n : std_logic_vector(7 DOWNTO 1);
SIGNAL vme_as_i_n : std_logic;
SIGNAL vme_as_o_n : std_logic;
SIGNAL vme_as_oe : std_logic;
SIGNAL vme_as_oe_n : std_logic;
SIGNAL vme_retry_o_n : std_logic;
SIGNAL vme_retry_oe_n : std_logic;
SIGNAL vme_retry_i_n : std_logic;
SIGNAL vme_sysres_i_n : std_logic;
SIGNAL vme_sysres_o_n : std_logic;
SIGNAL vme_ds_i_n : std_logic_vector(1 DOWNTO 0);
SIGNAL vme_ds_o_n : std_logic_vector(1 DOWNTO 0);
SIGNAL vme_ds_oe_n : std_logic;
SIGNAL vme_berr_i_n : std_logic;
SIGNAL vme_berr_o_n : std_logic;
SIGNAL vme_berr_o : std_logic;
SIGNAL vme_dtack_i_n : std_logic;
SIGNAL vme_dtack_o_n : std_logic;
SIGNAL vme_dtack_o : std_logic;
SIGNAL vme_scon_n : std_logic;
SIGNAL vme_sysfail_i_n : std_logic;
SIGNAL vme_sysfail_o_n : std_logic;
SIGNAL vme_bbsy_i_n : std_logic;
SIGNAL vme_bbsy_o_n : std_logic;
SIGNAL vme_bclr_i_n : std_logic; -- bus clear input
SIGNAL vme_bclr_o_n : std_logic; -- bus clear output
SIGNAL vme_br_i_n : std_logic_vector(3 DOWNTO 0);
SIGNAL vme_br_o_n : std_logic_vector(3 DOWNTO 0);
SIGNAL vme_iack_i_n : std_logic;
SIGNAL vme_iack_o_n : std_logic;
SIGNAL vme_acfail_i_n : std_logic;
SIGNAL vme_sysclk : std_logic;
SIGNAL vme_bg_i_n : std_logic_vector(3 DOWNTO 0);
SIGNAL vme_bg_o_n : std_logic_vector(3 DOWNTO 0);
-- high active signals on A25
SIGNAL vme_irq_o : std_logic_vector(7 DOWNTO 1);
SIGNAL vme_retry_oe : std_logic;
SIGNAL vme_sysres_o : std_logic;
SIGNAL vme_ds_oe : std_logic;
SIGNAL vme_scon : std_logic;
SIGNAL vme_sysfail_o : std_logic;
SIGNAL vme_bbsy_o : std_logic;
SIGNAL vme_br_o : std_logic_vector(3 DOWNTO 0);
SIGNAL terminal_in_0 : terminal_in_type;
SIGNAL terminal_out_0 : terminal_out_type;
SIGNAL terminal_in_1 : terminal_in_type;
SIGNAL terminal_out_1 : terminal_out_type;
SIGNAL vme_slv_in : vme_slv_in_type;
SIGNAL vme_slv_out : vme_slv_out_type;
SIGNAL vme_mon_out : vme_mon_out_type;
SIGNAL Addr : std_logic_vector(18 DOWNTO 0);
SIGNAL Adsc_n : std_logic;
SIGNAL Bwa_n : std_logic;
SIGNAL Bwb_n : std_logic;
SIGNAL Bwe_n : std_logic;
SIGNAL Oe_n : std_logic;
SIGNAL ce_n : std_logic;
SIGNAL vb_am : std_logic_vector(5 DOWNTO 0);
SIGNAL vb_data : std_logic_vector(31 DOWNTO 0);
SIGNAL vb_adr : std_logic_vector(31 DOWNTO 0);
SIGNAL vb_writen : std_logic;
SIGNAL vb_iackn : std_logic;
SIGNAL vb_asn : std_logic;
SIGNAL vb_dsan : std_logic;
SIGNAL vb_dsbn : std_logic;
SIGNAL vb_bbsyn : std_logic;
SIGNAL vb_berrn : std_logic;
SIGNAL vb_brn : std_logic_vector(3 DOWNTO 0);
SIGNAL vb_dtackn : std_logic;
SIGNAL vb_sysresn : std_logic;
SIGNAL vb_irq1n : std_logic;
SIGNAL vb_irq2n : std_logic;
SIGNAL vb_irq3n : std_logic;
SIGNAL vb_irq4n : std_logic;
SIGNAL vb_irq5n : std_logic;
SIGNAL vb_irq6n : std_logic;
SIGNAL vb_irq7n : std_logic;
SIGNAL vb_bgin : std_logic_vector(3 DOWNTO 0);
SIGNAL vb_bgout : std_logic_vector(3 DOWNTO 0);
SIGNAL vb_iackin : std_logic;
SIGNAL vb_iackout : std_logic;
SIGNAL vb_acfailn : std_logic;
SIGNAL vb_sysclk : std_logic;
SIGNAL vb_sysfailn : std_logic;
SIGNAL dummy : std_logic:='1';
SIGNAL slot1 : boolean;
-- Hard IP BFM connections
signal ep_rxvalid_int : std_logic_vector(BFM_LANE_WIDTH -1 downto 0);
signal ep_rxstatus_int : std_logic_vector(3*BFM_LANE_WIDTH -1 downto 0);
signal ep_rxdatak_int : std_logic_vector(BFM_LANE_WIDTH -1 downto 0);
signal ep_rxdata_int : std_logic_vector(8*BFM_LANE_WIDTH -1 downto 0);
signal ep_rxelecidle_int : std_logic_vector(BFM_LANE_WIDTH -1 downto 0);
signal ep_phystatus_int : std_logic_vector(BFM_LANE_WIDTH -1 downto 0);
signal ep_clk250_int : std_logic;
signal ep_clk500_int : std_logic;
signal ep_rate_ext_int : std_logic;
signal ep_powerdown_ext_int : std_logic_vector(2*BFM_LANE_WIDTH -1 downto 0);
signal ep_txdatak_int : std_logic_vector(BFM_LANE_WIDTH -1 downto 0);
signal ep_txdata_int : std_logic_vector(8*BFM_LANE_WIDTH -1 downto 0);
signal ep_txcompl_int : std_logic_vector(BFM_LANE_WIDTH -1 downto 0);
signal ep_txelecidle_int : std_logic_vector(BFM_LANE_WIDTH -1 downto 0);
signal ep_txdetectrx_int : std_logic_vector(BFM_LANE_WIDTH -1 downto 0);
signal ep_rxpolarity_int : std_logic_vector(BFM_LANE_WIDTH -1 downto 0);
signal ep_ltssm_int : std_logic_vector(4 downto 0);
BEGIN
-- high active signals on A25
vme_irq_o_n <= NOT vme_irq_o ;
vme_retry_oe_n <= NOT vme_retry_oe ;
vme_sysres_o_n <= NOT vme_sysres_o ;
vme_ds_oe_n <= NOT vme_ds_oe ;
vme_scon_n <= NOT vme_scon ;
vme_sysfail_o_n <= NOT vme_sysfail_o ;
vme_bbsy_o_n <= NOT vme_bbsy_o ;
vme_br_o_n <= NOT vme_br_o ;
vme_as_oe_n <= NOT vme_as_oe;
vme_dtack_o_n <= NOT vme_dtack_o;
vme_berr_o_n <= NOT vme_berr_o;
a25: A25_top
GENERIC MAP (
SIMULATION => TRUE,
FPGA_FAMILY => CYCLONE4,
BFM_LANE_WIDTH => BFM_LANE_WIDTH,
sets => "1110",
timeout => 5000
)
PORT MAP (
clk_16mhz => clk_16mhz ,
led_green_n => led_green_n ,
led_red_n => led_red_n ,
hreset_n => hreset_n ,
v2p_rstn => v2p_rstn ,
fpga_test => open,
refclk => refclk ,
pcie_rx => pcie_rx ,
pcie_tx => pcie_tx ,
sr_clk => sr_clk ,
sr_a => sr_a ,
sr_d => sr_d ,
sr_bwa_n => sr_bwa_n ,
sr_bwb_n => sr_bwb_n ,
sr_bw_n => sr_bw_n ,
sr_cs1_n => sr_cs1_n ,
sr_adsc_n => sr_adsc_n ,
sr_oe_n => sr_oe_n ,
vme_ga => vme_ga,
vme_gap => vme_gap,
vme_a => vme_a ,
vme_a_dir => vme_a_dir ,
vme_a_oe_n => vme_a_oe_n ,
vme_d => vme_d ,
vme_d_dir => vme_d_dir ,
vme_d_oe_n => vme_d_oe_n ,
vme_am_dir => vme_am_dir ,
vme_am => vme_am ,
vme_am_oe_n => vme_am_oe_n ,
vme_write_n => vme_write_n ,
vme_iack_n => vme_iack_n ,
vme_irq_i_n => vme_irq_i_n ,
vme_irq_o => vme_irq_o ,
vme_as_i_n => vme_as_i_n ,
vme_as_o_n => vme_as_o_n ,
vme_as_oe => vme_as_oe ,
vme_retry_o_n => vme_retry_o_n ,
vme_retry_oe => vme_retry_oe ,
vme_retry_i_n => vme_retry_i_n ,
vme_sysres_i_n => vme_sysres_i_n ,
vme_sysres_o => vme_sysres_o ,
vme_ds_i_n => vme_ds_i_n ,
vme_ds_o_n => vme_ds_o_n ,
vme_ds_oe => vme_ds_oe ,
vme_berr_i_n => vme_berr_i_n ,
vme_berr_o => vme_berr_o ,
vme_dtack_i_n => vme_dtack_i_n ,
vme_dtack_o => vme_dtack_o ,
vme_scon => vme_scon ,
vme_sysfail_i_n => vme_sysfail_i_n ,
vme_sysfail_o => vme_sysfail_o ,
vme_bbsy_i_n => vme_bbsy_i_n ,
vme_bbsy_o => vme_bbsy_o ,
vme_bclr_i_n => vme_bclr_i_n ,
vme_bclr_o_n => vme_bclr_o_n ,
vme_br_i_n => vme_br_i_n ,
vme_br_o => vme_br_o ,
vme_iack_i_n => vme_iack_i_n ,
vme_iack_o_n => vme_iack_o_n ,
vme_acfail_i_n => vme_acfail_i_n ,
vme_sysclk => vme_sysclk ,
vme_bg_i_n => vme_bg_i_n ,
vme_bg_o_n => vme_bg_o_n,
-- Hard IP BFM connections
ep_rxvalid_i => ep_rxvalid_int,
ep_rxstatus_i => ep_rxstatus_int,
ep_rxdatak_i => ep_rxdatak_int,
ep_rxdata_i => ep_rxdata_int,
ep_rxelecidle_i => ep_rxelecidle_int,
ep_phystatus_i => ep_phystatus_int,
ep_clk250_o => ep_clk250_int,
ep_clk500_o => ep_clk500_int,
ep_rate_ext_o => ep_rate_ext_int,
ep_powerdown_ext_o => ep_powerdown_ext_int,
ep_txdatak_o => ep_txdatak_int,
ep_txdata_o => ep_txdata_int,
ep_txcompl_o => ep_txcompl_int,
ep_txelecidle_o => ep_txelecidle_int,
ep_txdetectrx_o => ep_txdetectrx_int,
ep_rxpolarity_o => ep_rxpolarity_int,
ep_ltssm_o => ep_ltssm_int
);
clk_16mhz_int <= NOT clk_16mhz_int AFTER 31.25 ns;
clk_16mhz <= clk_16mhz_int WHEN en_clk ELSE '0';
refclk <= NOT refclk AFTER 5 ns;
clk_125 <= NOT clk_125 AFTER 4 ns; -- 125 MHz
clk_250 <= NOT clk_250 AFTER 2 ns; -- 250 MHz
hreset <= NOT hreset_n;
pcie_sim_inst: pcie_sim
generic map(
BFM_LANE_WIDTH => BFM_LANE_WIDTH
)
port map(
rst_i => hreset,
pcie_rstn_i => hreset_n,
clk_i => refclk,
ep_clk250_i => ep_clk250_int,
ep_clk500_i => ep_clk500_int,
-- PCIe lanes
bfm_tx_i => pcie_tx(BFM_LANE_WIDTH -1 downto 0),
bfm_rx_o => pcie_rx(BFM_LANE_WIDTH -1 downto 0),
-- PCIe SERDES connection, in/out references are BFM view
ep_rate_ext_i => ep_rate_ext_int,
ep_powerdown_ext_i => ep_powerdown_ext_int,
ep_txdatak_i => ep_txdatak_int,
ep_txdata_i => ep_txdata_int,
ep_txcompl_i => ep_txcompl_int,
ep_txelecidle_i => ep_txelecidle_int,
ep_txdetectrx_i => ep_txdetectrx_int,
ep_rxpolarity_i => ep_rxpolarity_int,
ep_ltssm_i => ep_ltssm_int,
ep_rxvalid_o => ep_rxvalid_int,
ep_rxstatus_o => ep_rxstatus_int,
ep_rxdatak_o => ep_rxdatak_int,
ep_rxdata_o => ep_rxdata_int,
ep_rxelecidle_o => ep_rxelecidle_int,
ep_phystatus_o => ep_phystatus_int,
-- MEN terminal connection, in/out references are terminal view
term_out => terminal_out_0,
term_in => terminal_in_0
);
trans_sr_clk <= transport sr_clk AFTER 12 ns;
Addr <= transport sr_a AFTER (T_FPGA_TO_SRAM);
Adsc_n <= transport sr_adsc_n AFTER (T_FPGA_TO_SRAM);
Bwa_n <= transport sr_bwa_n AFTER (T_FPGA_TO_SRAM);
Bwb_n <= transport sr_bwb_n AFTER (T_FPGA_TO_SRAM);
Bwe_n <= transport sr_bw_n AFTER (T_FPGA_TO_SRAM);
Oe_n <= transport sr_oe_n AFTER (T_FPGA_TO_SRAM);
ce_n <= '1', '0' AFTER 28 ns;
sram : MT58L512L18F
GENERIC MAP (
addr_bits => 19,
data_bits => 16
)
PORT MAP(
Clk => trans_sr_clk,
Dq => sr_d ,
Addr => Addr ,
Adsc_n => adsc_n,
Bwa_n => Bwa_n ,
Bwb_n => Bwb_n ,
Bwe_n => Bwe_n ,
Oe_n => Oe_n ,
Adsp_n => '1',
Mode => '0',
Adv_n => '1',
Gw_n => '1',
Ce_n => ce_n,
Ce2 => '1',
Ce2_n => '0',
Zz => '0'
);
vme_bus : vmebus
PORT MAP (
slot1 => slot1, -- if true dut is in slot1
vme_slv_in => vme_slv_in ,
vme_slv_out => vme_slv_out,
vme_mon_out => vme_mon_out,
terminal_in_x => terminal_in_1 ,
terminal_out_x => terminal_out_1 ,
vb_am => vb_am ,
vb_data => vb_data ,
vb_adr => vb_adr ,
vb_writen => vb_writen ,
vb_iackn => vb_iackn ,
vb_asn => vb_asn ,
vb_dsan => vb_dsan ,
vb_dsbn => vb_dsbn ,
vb_bbsyn => vb_bbsyn ,
vb_berrn => vb_berrn ,
vb_brn => vb_brn ,
vb_dtackn => vb_dtackn ,
vb_sysresn => vb_sysresn ,
vb_irq1n => vb_irq1n ,
vb_irq2n => vb_irq2n ,
vb_irq3n => vb_irq3n ,
vb_irq4n => vb_irq4n ,
vb_irq5n => vb_irq5n ,
vb_irq6n => vb_irq6n ,
vb_irq7n => vb_irq7n ,
vb_bgin => vb_bgin ,
vb_bgout => vb_bgout ,
vb_iackin => vb_iackin ,
vb_iackout => vb_iackout ,
vb_acfailn => vb_acfailn
);
bus_drv_ctrl_out: SN74ABT125
GENERIC MAP (
OP_COND => 2,
WIDTH => 21
)
PORT MAP (
oe_n(0) => vme_irq_o_n(1),
oe_n(1) => vme_irq_o_n(2),
oe_n(2) => vme_irq_o_n(3),
oe_n(3) => vme_irq_o_n(4),
oe_n(4) => vme_irq_o_n(5),
oe_n(5) => vme_irq_o_n(6),
oe_n(6) => vme_irq_o_n(7),
oe_n(7) => vme_as_oe_n,
oe_n(8) => vme_dtack_o_n,
oe_n(9) => vme_ds_o_n(0),
oe_n(10) => vme_ds_o_n(1),
oe_n(11) => vme_sysclk,
oe_n(12) => vme_berr_o_n,
oe_n(13) => vme_sysres_o_n,
oe_n(14) => vme_sysfail_o_n,
oe_n(15) => vme_br_o_n(0),
oe_n(16) => vme_br_o_n(1),
oe_n(17) => vme_br_o_n(2),
oe_n(18) => vme_br_o_n(3),
oe_n(19) => '1',
oe_n(20) => vme_bbsy_o_n,
a(0) => vme_irq_o_n(1),
a(1) => vme_irq_o_n(2),
a(2) => vme_irq_o_n(3),
a(3) => vme_irq_o_n(4),
a(4) => vme_irq_o_n(5),
a(5) => vme_irq_o_n(6),
a(6) => vme_irq_o_n(7),
a(7) => vme_as_o_n,
a(8) => vme_dtack_o_n,
a(9) => vme_ds_o_n(0),
a(10) => vme_ds_o_n(1),
a(11) => vme_sysclk,
a(12) => vme_berr_o_n,
a(13) => vme_sysres_o_n,
a(14) => vme_sysfail_o_n,
a(15) => vme_br_o_n(0),
a(16) => vme_br_o_n(1),
a(17) => vme_br_o_n(2),
a(18) => vme_br_o_n(3),
a(19) => '1',
a(20) => vme_bbsy_o_n,
b(0) => vb_irq1n,
b(1) => vb_irq2n,
b(2) => vb_irq3n,
b(3) => vb_irq4n,
b(4) => vb_irq5n,
b(5) => vb_irq6n,
b(6) => vb_irq7n,
b(7) => vb_asn,
b(8) => vb_dtackn,
b(9) => vb_dsan,
b(10) => vb_dsbn,
b(11) => vb_sysclk,
b(12) => vb_berrn,
b(13) => vb_sysresn,
b(14) => vb_sysfailn,
b(15) => vb_brn(0),
b(16) => vb_brn(1),
b(17) => vb_brn(2),
b(18) => vb_brn(3),
b(19) => vb_acfailn,
b(20) => vb_bbsyn
);
vb_irq1n <= 'H';
bus_drv_ctrl_in: SN74LVTH245
GENERIC MAP (
OP_COND => 2,
WIDTH => 29
)
PORT MAP(
dir => '1', -- a->b
oe_n => '0',
a(0) => vb_irq1n,
a(1) => vb_irq2n,
a(2) => vb_irq3n,
a(3) => vb_irq4n,
a(4) => vb_irq5n,
a(5) => vb_irq6n,
a(6) => vb_irq7n,
a(7) => vb_iackin,
a(8) => vme_iack_o_n,
a(9) => vb_asn,
a(10) => vb_dtackn,
a(11) => vb_dsan,
a(12) => vb_dsbn,
a(13) => vb_berrn,
a(14) => vb_sysresn,
a(15) => dummy,
a(16) => vme_bg_o_n(0),
a(17) => vme_bg_o_n(1),
a(18) => vme_bg_o_n(2),
a(19) => vme_bg_o_n(3),
a(20) => vb_bgin(0),
a(21) => vb_bgin(1),
a(22) => vb_bgin(2),
a(23) => vb_bgin(3),
a(24) => vb_bbsyn,
a(25) => vb_brn(0),
a(26) => vb_brn(1),
a(27) => vb_brn(2),
a(28) => vb_brn(3),
b(0) => vme_irq_i_n(1),
b(1) => vme_irq_i_n(2),
b(2) => vme_irq_i_n(3),
b(3) => vme_irq_i_n(4),
b(4) => vme_irq_i_n(5),
b(5) => vme_irq_i_n(6),
b(6) => vme_irq_i_n(7),
b(7) => vme_iack_i_n,
b(8) => vb_iackout,
b(9) => vme_as_i_n,
b(10) => vme_dtack_i_n,
b(11) => vme_ds_i_n(0),
b(12) => vme_ds_i_n(1),
b(13) => vme_berr_i_n,
b(14) => vme_sysres_i_n,
b(15) => vme_sysfail_i_n,
b(16) => vb_bgout(0),
b(17) => vb_bgout(1),
b(18) => vb_bgout(2),
b(19) => vb_bgout(3),
b(20) => vme_bg_i_n(0),
b(21) => vme_bg_i_n(1),
b(22) => vme_bg_i_n(2),
b(23) => vme_bg_i_n(3),
b(24) => vme_bbsy_i_n,
b(25) => vme_br_i_n(0),
b(26) => vme_br_i_n(1),
b(27) => vme_br_i_n(2),
b(28) => vme_br_i_n(3)
);
bus_drv_am: SN74LVTH245
GENERIC MAP (
OP_COND => 2,
WIDTH => 8
)
PORT MAP(
dir => vme_am_dir,
oe_n => vme_am_oe_n,
a(0) => vme_am(0),
a(1) => vme_am(1),
a(2) => vme_am(2),
a(3) => vme_am(3),
a(4) => vme_am(4),
a(5) => vme_am(5),
a(6) => vme_iack_n,
a(7) => vme_write_n,
b(0) => vb_am(0),
b(1) => vb_am(1),
b(2) => vb_am(2),
b(3) => vb_am(3),
b(4) => vb_am(4),
b(5) => vb_am(5),
b(6) => vb_iackn,
b(7) => vb_writen
);
bus_drv_adr: SN74LVTH245
GENERIC MAP (
OP_COND => 2,
WIDTH => 32
)
PORT MAP(
dir => vme_a_dir,
oe_n => vme_a_oe_n,
a => vme_a,
b => vb_adr
);
bus_drv_dat: SN74LVTH245
GENERIC MAP (
OP_COND => 2,
WIDTH => 32
)
PORT MAP(
dir => vme_d_dir,
oe_n => vme_d_oe_n,
a => vme_d,
b => vb_data
);
term: terminal
PORT MAP (
hreset_n => hreset_n ,
slot1 => slot1,
en_clk => en_clk,
terminal_in_0 => terminal_in_0 ,
terminal_out_0 => terminal_out_0,
terminal_in_1 => terminal_in_1 ,
terminal_out_1 => terminal_out_1,
vme_slv_in => vme_slv_in ,
vme_slv_out => vme_slv_out,
vme_mon_out => vme_mon_out,
v2p_rstn => v2p_rstn ,
vme_ga => vme_ga,
vme_gap => vme_gap
);
END a25_tb_arch;
CONFIGURATION a25_tb_conf of a25_tb IS
FOR a25_tb_arch
FOR a25 : A25_top
USE CONFIGURATION work.top_cfg;
END FOR;
END FOR;
END CONFIGURATION a25_tb_conf;
|
gpl-3.0
|
95650e4086c50fcaded6440b786cbdc5
| 0.479636 | 3.001156 | false | false | false | false |
freecores/t48
|
rtl/vhdl/t8243/t8243_core.vhd
| 1 | 9,699 |
-------------------------------------------------------------------------------
--
-- The T8243 Core
-- This is the core module implementing all functionality of the
-- original 8243 chip.
--
-- $Id: t8243_core.vhd,v 1.2 2006-12-18 01:18:58 arniml Exp $
-- $Name: not supported by cvs2svn $
--
-- Copyright (c) 2006, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee. std_logic_1164.all;
entity t8243_core is
generic (
clk_fall_level_g : integer := 0
);
port (
-- System Interface -------------------------------------------------------
clk_i : in std_logic;
clk_rise_en_i : in std_logic;
clk_fall_en_i : in std_logic;
reset_n_i : in std_logic;
-- Control Interface ------------------------------------------------------
cs_n_i : in std_logic;
prog_n_i : in std_logic;
-- Port 2 Interface -------------------------------------------------------
p2_i : in std_logic_vector(3 downto 0);
p2_o : out std_logic_vector(3 downto 0);
p2_en_o : out std_logic;
-- Port 4 Interface -------------------------------------------------------
p4_i : in std_logic_vector(3 downto 0);
p4_o : out std_logic_vector(3 downto 0);
p4_en_o : out std_logic;
-- Port 5 Interface -------------------------------------------------------
p5_i : in std_logic_vector(3 downto 0);
p5_o : out std_logic_vector(3 downto 0);
p5_en_o : out std_logic;
-- Port 6 Interface -------------------------------------------------------
p6_i : in std_logic_vector(3 downto 0);
p6_o : out std_logic_vector(3 downto 0);
p6_en_o : out std_logic;
-- Port 7 Interface -------------------------------------------------------
p7_i : in std_logic_vector(3 downto 0);
p7_o : out std_logic_vector(3 downto 0);
p7_en_o : out std_logic
);
end t8243_core;
library ieee;
use ieee.numeric_std.all;
architecture rtl of t8243_core is
function int2stdlogic_f(level_i : in integer) return std_logic is
begin
if level_i = 0 then
return '0';
else
return '1';
end if;
end;
constant clk_fall_level_c : std_logic := int2stdlogic_f(clk_fall_level_g);
type instr_t is (INSTR_READ, INSTR_WRITE, INSTR_ORLD, INSTR_ANLD);
signal instr_q : instr_t;
constant port_4_c : integer := 4;
constant port_5_c : integer := 5;
constant port_6_c : integer := 6;
constant port_7_c : integer := 7;
subtype port_range_t is natural range port_7_c downto port_4_c;
signal px_sel_q : std_logic_vector(port_range_t);
signal px_en_q : std_logic_vector(port_range_t);
signal p2_en_q : std_logic;
subtype port_vector_t is std_logic_vector(3 downto 0);
type four_ports_t is array (port_range_t) of port_vector_t;
signal px_latch_q : four_ports_t;
signal data_s : port_vector_t;
signal p2_s,
p4_s,
p5_s,
p6_s,
p7_s : port_vector_t;
begin
-- get rid of H and L
p2_s <= to_X01(p2_i);
p4_s <= to_X01(p4_i);
p5_s <= to_X01(p5_i);
p6_s <= to_X01(p6_i);
p7_s <= to_X01(p7_i);
-----------------------------------------------------------------------------
-- Process ctrl_seq
--
-- Purpose:
-- Implements the sequential elements that control the T8243 core.
-- * latch port number
-- * latch instruction
--
ctrl_seq: process (clk_i, cs_n_i)
begin
if cs_n_i = '1' then
px_sel_q <= (others => '0');
p2_en_q <= '0';
instr_q <= INSTR_WRITE;
elsif clk_i'event and clk_i = clk_fall_level_c then
if cs_n_i = '0' and clk_fall_en_i = '1' then
-- enable addressed port ----------------------------------------------
px_sel_q <= (others => '0');
px_sel_q(to_integer(unsigned(p2_s(1 downto 0))) +
port_range_t'low) <= '1';
p2_en_q <= '0';
-- decode instruction -------------------------------------------------
case p2_s(3 downto 2) is
when "00" =>
instr_q <= INSTR_READ;
p2_en_q <= '1';
when "01" =>
instr_q <= INSTR_WRITE;
when "10" =>
instr_q <= INSTR_ORLD;
when "11" =>
instr_q <= INSTR_ANLD;
when others =>
null;
end case;
end if;
end if;
end process ctrl_seq;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process port_seq
--
-- Purpose:
-- Implements the sequential elements of the four ports.
--
port_seq: process (clk_i, reset_n_i)
begin
if reset_n_i = '0' then
px_en_q <= (others => '0');
px_latch_q <= (others => (others => '0'));
elsif rising_edge(clk_i) then
if cs_n_i = '0' and clk_rise_en_i = '1' then
for idx in port_range_t loop
if px_sel_q(idx) = '1' then
if instr_q = INSTR_READ then
-- port is being read from, switch off output enable
px_en_q(idx) <= '0';
else
-- port is being written to, enable output
px_en_q(idx) <= '1';
-- and latch value
px_latch_q(idx) <= data_s;
end if;
end if;
end loop;
end if;
end if;
end process port_seq;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process data_gen
--
-- Purpose:
-- Generates the data for the four port latches.
-- * determines data inputs
-- * calculates result of instruction
--
-- Multiplexes the read value for P2.
--
data_gen: process (px_sel_q,
instr_q,
p2_s,
px_latch_q,
p4_s, p5_s, p6_s, p7_s)
variable port_v : port_vector_t;
begin
-- select addressed port
case px_sel_q is
when "0001" =>
port_v := px_latch_q(port_4_c);
p2_o <= p4_s;
when "0010" =>
port_v := px_latch_q(port_5_c);
p2_o <= p5_s;
when "0100" =>
port_v := px_latch_q(port_6_c);
p2_o <= p6_s;
when "1000" =>
port_v := px_latch_q(port_7_c);
p2_o <= p7_s;
when others =>
port_v := (others => '-');
p2_o <= (others => '-');
end case;
case instr_q is
when INSTR_WRITE =>
data_s <= p2_s;
when INSTR_ORLD =>
data_s <= p2_s or port_v;
when INSTR_ANLD =>
data_s <= p2_s and port_v;
when others =>
data_s <= (others => '-');
end case;
end process;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output mapping
-----------------------------------------------------------------------------
p2_en_o <= '1'
when cs_n_i = '0' and prog_n_i = '0' and p2_en_q = '1' else
'0';
p4_o <= px_latch_q(port_4_c);
p4_en_o <= px_en_q(port_4_c);
p5_o <= px_latch_q(port_5_c);
p5_en_o <= px_en_q(port_5_c);
p6_o <= px_latch_q(port_6_c);
p6_en_o <= px_en_q(port_6_c);
p7_o <= px_latch_q(port_7_c);
p7_en_o <= px_en_q(port_7_c);
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.1 2006/07/13 22:53:56 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
gpl-2.0
|
ecb45b1b5425cdf63a7cbc36bc4bc6ca
| 0.482936 | 3.675256 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/altera_lnsim/ama_adder_function/_primary.vhd
| 5 | 3,856 |
library verilog;
use verilog.vl_types.all;
entity ama_adder_function is
generic(
width_data_in : integer := 1;
width_data_out : integer := 1;
number_of_adder_input: integer := 1;
adder1_direction: string := "NONE";
adder3_direction: string := "NONE";
representation : string := "UNSIGNED";
port_addnsub1 : string := "PORT_UNUSED";
addnsub_multiplier_register1: string := "CLOCK0";
addnsub_multiplier_aclr1: string := "ACLR3";
port_addnsub3 : string := "PORT_UNUSED";
addnsub_multiplier_register3: string := "CLOCK0";
addnsub_multiplier_aclr3: string := "ACLR3";
latency : integer := 0;
addnsub_multiplier_latency_clock1: string := "UNREGISTERED";
addnsub_multiplier_latency_aclr1: string := "NONE";
addnsub_multiplier_latency_clock3: string := "UNREGISTERED";
addnsub_multiplier_latency_aclr3: string := "NONE";
width_data_in_msb: vl_notype;
width_data_out_msb: vl_notype;
width_adder_lvl_1: vl_notype;
width_adder_lvl_1_msb: vl_notype;
width_adder_lvl_2: vl_notype;
width_adder_lvl_2_msb: vl_notype;
width_data_out_wire: vl_notype;
width_data_out_wire_msb: vl_notype
);
port(
data_in_0 : in vl_logic_vector;
data_in_1 : in vl_logic_vector;
data_in_2 : in vl_logic_vector;
data_in_3 : in vl_logic_vector;
data_out : out vl_logic_vector;
clock : in vl_logic_vector(3 downto 0);
aclr : in vl_logic_vector(3 downto 0);
ena : in vl_logic_vector(3 downto 0);
addnsub1 : in vl_logic;
addnsub3 : in vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width_data_in : constant is 1;
attribute mti_svvh_generic_type of width_data_out : constant is 1;
attribute mti_svvh_generic_type of number_of_adder_input : constant is 1;
attribute mti_svvh_generic_type of adder1_direction : constant is 1;
attribute mti_svvh_generic_type of adder3_direction : constant is 1;
attribute mti_svvh_generic_type of representation : constant is 1;
attribute mti_svvh_generic_type of port_addnsub1 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_register1 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_aclr1 : constant is 1;
attribute mti_svvh_generic_type of port_addnsub3 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_register3 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_aclr3 : constant is 1;
attribute mti_svvh_generic_type of latency : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_latency_clock1 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_latency_aclr1 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_latency_clock3 : constant is 1;
attribute mti_svvh_generic_type of addnsub_multiplier_latency_aclr3 : constant is 1;
attribute mti_svvh_generic_type of width_data_in_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_out_msb : constant is 3;
attribute mti_svvh_generic_type of width_adder_lvl_1 : constant is 3;
attribute mti_svvh_generic_type of width_adder_lvl_1_msb : constant is 3;
attribute mti_svvh_generic_type of width_adder_lvl_2 : constant is 3;
attribute mti_svvh_generic_type of width_adder_lvl_2_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_out_wire : constant is 3;
attribute mti_svvh_generic_type of width_data_out_wire_msb : constant is 3;
end ama_adder_function;
|
mit
|
5671d6924e15186e83cf7eb02a4c161b
| 0.654564 | 3.607109 | false | false | false | false |
Ttl/bf_cpu
|
testbenches/cache_tb.vhd
| 1 | 3,499 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY cache_tb IS
END cache_tb;
ARCHITECTURE behavior OF cache_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT cache
Generic (WIDTH : natural := 13; -- Length of address
DWIDTH : natural := 13; -- Length of one entry
ADR_LENGTH : natural := 4); -- Log2 of number of entries in the cache
PORT(
clk : IN std_logic;
reset : IN std_logic;
addr : IN std_logic_vector(12 downto 0);
din : IN std_logic_vector(12 downto 0);
push : IN std_logic;
valid : OUT std_logic;
dout : OUT std_logic_vector(12 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal addr : std_logic_vector(12 downto 0) := (others => '0');
signal din : std_logic_vector(12 downto 0) := (others => '0');
signal push : std_logic := '0';
--Outputs
signal valid : std_logic;
signal dout : std_logic_vector(12 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: cache
Generic map (WIDTH => 13, -- Length of address
DWIDTH => 13, -- Length of one entry
ADR_LENGTH => 4) -- Log2 of number of entries in the cache
PORT MAP (
clk => clk,
reset => reset,
addr => addr,
din => din,
push => push,
valid => valid,
dout => dout
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <= '1';
-- hold reset state for 100 ns.
wait for 100 ns;
reset <= '0';
addr <= (others => '0');
din <= "0000000000001";
-- Write one entry
push <= '1';
-- Check that valid is zero
assert valid = '0' report "valid not zero" severity failure;
wait for clk_period;
push <= '0'; -- Deassert push
wait for clk_period;
-- Test correctness
assert valid = '1' report "valid not one" severity failure;
assert dout = "0000000000001" report "Output invalid" severity failure;
-- Set addr and din for new entry
addr <= (1 => '1', others => '0');
din <= "1111111111111";
wait for clk_period;
-- Add second entry
push <= '1';
assert valid = '0' report "valid not zero" severity failure;
wait for clk_period;
push <= '0'; -- Deassert push
wait for clk_period;
-- Test correctness
assert valid = '1' report "valid not one" severity failure;
assert dout = "1111111111111" report "Output invalid" severity failure;
-- Test correctness of the first entry
addr <= (others => '0');
wait for clk_period;
assert valid = '1' report "valid not one" severity failure;
assert dout = "0000000000001" report "Output invalid" severity failure;
-- Try addr with lower bits same
addr <= "1000000000000";
wait for clk_period;
assert valid = '0' report "valid not zero, different tag bits test" severity failure;
wait for clk_period;
assert false report "Completed succesfully" severity failure;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
lgpl-3.0
|
3e288e1fb4ea9da62f55cc65eb1c0fa3
| 0.584167 | 3.998857 | false | false | false | false |
straywarrior/MadeCPUin21days
|
ID_EXE_REG.vhd
| 1 | 4,006 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: StrayWarrior
--
-- Create Date: 14:18:20 11/14/2015
-- Design Name:
-- Module Name: ID_EXE_REG - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ID_EXE_REG is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
clear : in STD_LOGIC;
stall : in STD_LOGIC;
RegWE_in : in STD_LOGIC;
RegDest_in : in STD_LOGIC_VECTOR (3 downto 0);
MemRd_in : in STD_LOGIC;
MemWE_in : in STD_LOGIC;
MemDIn_in : in STD_LOGIC_VECTOR (15 downto 0);
opcode_in : in STD_LOGIC_VECTOR (3 downto 0);
operandA_in : in STD_LOGIC_VECTOR (15 downto 0);
operandB_in : in STD_LOGIC_VECTOR (15 downto 0);
RegOpA_in : in STD_LOGIC_VECTOR (3 downto 0);
RegOpB_in : in STD_LOGIC_VECTOR (3 downto 0);
RegMemDIn_in : in STD_LOGIC_VECTOR (3 downto 0);
RegWE_out : out STD_LOGIC;
RegDest_out : out STD_LOGIC_VECTOR (3 downto 0);
MemRd_out : out STD_LOGIC;
MemWE_out : out STD_LOGIC;
MemDIn_out : out STD_LOGIC_VECTOR (15 downto 0);
RegMemDIn_out : out STD_LOGIC_VECTOR (3 downto 0);
opcode_out : out STD_LOGIC_VECTOR (3 downto 0);
operandA_out : out STD_LOGIC_VECTOR (15 downto 0);
operandB_out : out STD_LOGIC_VECTOR (15 downto 0);
RegOpA_out : out STD_LOGIC_VECTOR (3 downto 0);
RegOpB_out : out STD_LOGIC_VECTOR (3 downto 0)
);
end ID_EXE_REG;
architecture Behavioral of ID_EXE_REG is
begin
process (clear, reset, clk)
begin
if (reset = '0') then
RegWE_out <= '0';
RegDest_out <= (others => '1');
MemRd_out <= '0';
MemWE_out <= '0';
MemDIn_out <= (others => '0');
RegMemDIn_out <= (others => '0');
opcode_out <= (others => '1');
operandA_out <= (others => '0');
operandB_out <= (others => '0');
RegOpA_out <= (others => '1');
RegOpB_out <= (others => '1');
elsif (clk'event and clk = '1') then
if (clear = '0' and stall = '0') then
RegWE_out <= RegWE_in;
RegDest_out <= RegDest_in;
MemRd_out <= MemRd_in;
MemWE_out <= MemWE_in;
MemDIn_out <= MemDIn_in;
opcode_out <= opcode_in;
operandA_out <= operandA_in;
operandB_out <= operandB_in;
RegOpA_out <= RegOpA_in;
RegOpB_out <= RegOpB_in;
RegMemDIn_out <= RegMemDIn_in;
elsif (clear = '1' and stall = '0') then
RegWE_out <= '0';
RegDest_out <= (others => '1');
MemRd_out <= '0';
MemWE_out <= '0';
MemDIn_out <= (others => '0');
RegMemDIn_out <= (others => '0');
opcode_out <= (others => '1');
operandA_out <= (others => '0');
operandB_out <= (others => '0');
RegOpA_out <= (others => '1');
RegOpB_out <= (others => '1');
else
-- Insert a bubble here
null;
end if;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
68d3846c42faea20e09d7f8d99b072eb
| 0.482277 | 3.962413 | false | false | false | false |
freecores/t48
|
bench/vhdl/tb_t8039.vhd
| 1 | 9,368 |
-------------------------------------------------------------------------------
--
-- The testbench for t8039.
--
-- $Id: tb_t8039.vhd,v 1.5 2008-04-28 22:13:33 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity tb_t8039 is
end tb_t8039;
use work.t48_core_comp_pack.generic_ram_ena;
use work.t48_system_comp_pack.t8039;
use work.t48_tb_pack.all;
architecture behav of tb_t8039 is
-- clock period, 11 MHz
constant period_c : time := 90 ns;
component lpm_rom
generic (
LPM_WIDTH : positive;
LPM_TYPE : string := "LPM_ROM";
LPM_WIDTHAD : positive;
LPM_NUMWORDS : natural := 0;
LPM_FILE : string;
LPM_ADDRESS_CONTROL : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_HINT : string := "UNUSED"
);
port (
address : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
inclock : in std_logic;
outclock : in std_logic;
memenab : in std_logic;
q : out std_logic_vector(LPM_WIDTH-1 downto 0)
);
end component;
signal xtal_s : std_logic;
signal res_n_s : std_logic;
signal int_n_s : std_logic;
signal ale_s : std_logic;
signal psen_n_s : std_logic;
signal prog_n_s : std_logic;
signal t0_b : std_logic;
signal p1_b : std_logic_vector( 7 downto 0);
signal p2_b : std_logic_vector( 7 downto 0);
signal db_b : std_logic_vector( 7 downto 0);
signal ext_mem_addr_s : std_logic_vector(11 downto 0);
signal ext_ram_data_from_s : std_logic_vector( 7 downto 0);
signal ext_ram_we_s : std_logic;
signal ext_rom_data_s : std_logic_vector( 7 downto 0);
signal rd_n_s : std_logic;
signal wr_n_s : std_logic;
signal zero_s : std_logic;
signal one_s : std_logic;
begin
zero_s <= '0';
one_s <= '1';
p2_b <= (others => 'H');
p1_b <= (others => 'H');
-----------------------------------------------------------------------------
-- External ROM, 4k bytes
-- Initialized by file t3x_ext_rom.hex.
-----------------------------------------------------------------------------
ext_rom_b : lpm_rom
generic map (
LPM_WIDTH => 8,
LPM_TYPE => "LPM_ROM",
LPM_WIDTHAD => 12,
LPM_NUMWORDS => 2 ** 12,
LPM_FILE => "rom_t3x_ext.hex",
LPM_ADDRESS_CONTROL => "REGISTERED",
LPM_OUTDATA => "UNREGISTERED",
LPM_HINT => "UNUSED"
)
port map (
address => ext_mem_addr_s,
inclock => xtal_s,
outclock => zero_s, -- unused
memenab => one_s,
q => ext_rom_data_s
);
ext_ram_b : generic_ram_ena
generic map (
addr_width_g => 8,
data_width_g => 8
)
port map (
clk_i => xtal_s,
a_i => ext_mem_addr_s(7 downto 0),
we_i => ext_ram_we_s,
ena_i => one_s,
d_i => db_b,
d_o => ext_ram_data_from_s
);
t8039_b : t8039
port map (
xtal_i => xtal_s,
reset_n_i => res_n_s,
t0_b => t0_b,
int_n_i => int_n_s,
ea_i => one_s,
rd_n_o => rd_n_s,
psen_n_o => psen_n_s,
wr_n_o => wr_n_s,
ale_o => ale_s,
db_b => db_b,
t1_i => p1_b(1),
p2_b => p2_b,
p1_b => p1_b,
prog_n_o => prog_n_s
);
-----------------------------------------------------------------------------
-- Read from external memory
--
db_b <= ext_rom_data_s
when psen_n_s = '0' else
(others => 'Z');
db_b <= ext_ram_data_from_s
when rd_n_s = '0' else
(others => 'Z');
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- External memory access signals
--
ext_mem: process (wr_n_s,
ale_s,
p2_b,
db_b)
begin
ext_mem_addr_s(11 downto 8) <= To_X01Z(p2_b(3 downto 0));
if ale_s'event and ale_s = '0' then
if not is_X(db_b) then
ext_mem_addr_s(7 downto 0) <= db_b;
else
ext_mem_addr_s(7 downto 0) <= (others => '0');
end if;
end if;
if wr_n_s'event and wr_n_s = '1' then
ext_ram_we_s <= '0';
end if;
if wr_n_s'event and wr_n_s = '0' then
ext_ram_we_s <= '1';
end if;
end process ext_mem;
--
-----------------------------------------------------------------------------
t0_b <= p1_b(0);
-----------------------------------------------------------------------------
-- The clock generator
--
clk_gen: process
begin
xtal_s <= '0';
wait for period_c/2;
xtal_s <= '1';
wait for period_c/2;
end process clk_gen;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- The reset generator
--
res_gen: process
begin
res_n_s <= '0';
wait for 5 * period_c;
res_n_s <= '1';
wait;
end process res_gen;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- The interrupt generator
--
int_gen: process
begin
int_n_s <= '1';
wait for 750 * period_c;
int_n_s <= '0';
wait for 45 * period_c;
end process int_gen;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- End of simulation detection
--
eos: process
begin
outer: loop
wait on tb_accu_s;
if tb_accu_s = "10101010" then
wait on tb_accu_s;
if tb_accu_s = "01010101" then
wait on tb_accu_s;
if tb_accu_s = "00000001" then
-- wait for instruction strobe of this move
wait until tb_istrobe_s'event and tb_istrobe_s = '1';
-- wait for next strobe
wait until tb_istrobe_s'event and tb_istrobe_s = '1';
assert false
report "Simulation Result: PASS."
severity note;
else
assert false
report "Simulation Result: FAIL."
severity note;
end if;
assert false
report "End of simulation reached."
severity failure;
end if;
end if;
end loop;
end process eos;
--
-----------------------------------------------------------------------------
end behav;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.4 2006/06/22 00:21:58 arniml
-- cleanup & enhance external access
--
-- Revision 1.3 2006/06/21 01:04:05 arniml
-- replaced syn_ram and syn_rom with generic_ram_ena and t48_rom/t49_rom/t3x_rom
--
-- Revision 1.2 2005/11/01 21:22:28 arniml
-- fix address assignment
--
-- Revision 1.1 2004/04/18 19:00:07 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
gpl-2.0
|
aaf1d97bce075edcd7757ca0f36b0169
| 0.475662 | 3.891982 | false | false | false | false |
sukinull/hls_stream
|
Vivado/example.hls/example.hls.srcs/sources_1/bd/tutorial/ip/tutorial_v_tc_0_0/synth/tutorial_v_tc_0_0.vhd
| 1 | 17,753 |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:v_tc:6.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY v_tc_v6_1;
USE v_tc_v6_1.v_tc;
ENTITY tutorial_v_tc_0_0 IS
PORT (
clk : IN STD_LOGIC;
clken : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aclken : IN STD_LOGIC;
gen_clken : IN STD_LOGIC;
hsync_out : OUT STD_LOGIC;
hblank_out : OUT STD_LOGIC;
vsync_out : OUT STD_LOGIC;
vblank_out : OUT STD_LOGIC;
active_video_out : OUT STD_LOGIC;
resetn : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
irq : OUT STD_LOGIC;
fsync_in : IN STD_LOGIC;
fsync_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END tutorial_v_tc_0_0;
ARCHITECTURE tutorial_v_tc_0_0_arch OF tutorial_v_tc_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tutorial_v_tc_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT v_tc IS
GENERIC (
C_HAS_AXI4_LITE : INTEGER;
C_HAS_INTC_IF : INTEGER;
C_GEN_INTERLACED : INTEGER;
C_GEN_HACTIVE_SIZE : INTEGER;
C_GEN_VACTIVE_SIZE : INTEGER;
C_GEN_CPARITY : INTEGER;
C_GEN_FIELDID_POLARITY : INTEGER;
C_GEN_VBLANK_POLARITY : INTEGER;
C_GEN_HBLANK_POLARITY : INTEGER;
C_GEN_VSYNC_POLARITY : INTEGER;
C_GEN_HSYNC_POLARITY : INTEGER;
C_GEN_AVIDEO_POLARITY : INTEGER;
C_GEN_ACHROMA_POLARITY : INTEGER;
C_GEN_VIDEO_FORMAT : INTEGER;
C_GEN_HFRAME_SIZE : INTEGER;
C_GEN_F0_VFRAME_SIZE : INTEGER;
C_GEN_F1_VFRAME_SIZE : INTEGER;
C_GEN_HSYNC_START : INTEGER;
C_GEN_HSYNC_END : INTEGER;
C_GEN_F0_VBLANK_HSTART : INTEGER;
C_GEN_F0_VBLANK_HEND : INTEGER;
C_GEN_F0_VSYNC_VSTART : INTEGER;
C_GEN_F0_VSYNC_VEND : INTEGER;
C_GEN_F0_VSYNC_HSTART : INTEGER;
C_GEN_F0_VSYNC_HEND : INTEGER;
C_GEN_F1_VBLANK_HSTART : INTEGER;
C_GEN_F1_VBLANK_HEND : INTEGER;
C_GEN_F1_VSYNC_VSTART : INTEGER;
C_GEN_F1_VSYNC_VEND : INTEGER;
C_GEN_F1_VSYNC_HSTART : INTEGER;
C_GEN_F1_VSYNC_HEND : INTEGER;
C_FSYNC_HSTART0 : INTEGER;
C_FSYNC_VSTART0 : INTEGER;
C_FSYNC_HSTART1 : INTEGER;
C_FSYNC_VSTART1 : INTEGER;
C_FSYNC_HSTART2 : INTEGER;
C_FSYNC_VSTART2 : INTEGER;
C_FSYNC_HSTART3 : INTEGER;
C_FSYNC_VSTART3 : INTEGER;
C_FSYNC_HSTART4 : INTEGER;
C_FSYNC_VSTART4 : INTEGER;
C_FSYNC_HSTART5 : INTEGER;
C_FSYNC_VSTART5 : INTEGER;
C_FSYNC_HSTART6 : INTEGER;
C_FSYNC_VSTART6 : INTEGER;
C_FSYNC_HSTART7 : INTEGER;
C_FSYNC_VSTART7 : INTEGER;
C_FSYNC_HSTART8 : INTEGER;
C_FSYNC_VSTART8 : INTEGER;
C_FSYNC_HSTART9 : INTEGER;
C_FSYNC_VSTART9 : INTEGER;
C_FSYNC_HSTART10 : INTEGER;
C_FSYNC_VSTART10 : INTEGER;
C_FSYNC_HSTART11 : INTEGER;
C_FSYNC_VSTART11 : INTEGER;
C_FSYNC_HSTART12 : INTEGER;
C_FSYNC_VSTART12 : INTEGER;
C_FSYNC_HSTART13 : INTEGER;
C_FSYNC_VSTART13 : INTEGER;
C_FSYNC_HSTART14 : INTEGER;
C_FSYNC_VSTART14 : INTEGER;
C_FSYNC_HSTART15 : INTEGER;
C_FSYNC_VSTART15 : INTEGER;
C_MAX_PIXELS : INTEGER;
C_MAX_LINES : INTEGER;
C_NUM_FSYNCS : INTEGER;
C_INTERLACE_EN : INTEGER;
C_GEN_AUTO_SWITCH : INTEGER;
C_DETECT_EN : INTEGER;
C_SYNC_EN : INTEGER;
C_GENERATE_EN : INTEGER;
C_DET_HSYNC_EN : INTEGER;
C_DET_VSYNC_EN : INTEGER;
C_DET_HBLANK_EN : INTEGER;
C_DET_VBLANK_EN : INTEGER;
C_DET_AVIDEO_EN : INTEGER;
C_DET_ACHROMA_EN : INTEGER;
C_GEN_HSYNC_EN : INTEGER;
C_GEN_VSYNC_EN : INTEGER;
C_GEN_HBLANK_EN : INTEGER;
C_GEN_VBLANK_EN : INTEGER;
C_GEN_AVIDEO_EN : INTEGER;
C_GEN_ACHROMA_EN : INTEGER;
C_GEN_FIELDID_EN : INTEGER;
C_DET_FIELDID_EN : INTEGER
);
PORT (
clk : IN STD_LOGIC;
clken : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aclken : IN STD_LOGIC;
det_clken : IN STD_LOGIC;
gen_clken : IN STD_LOGIC;
intc_if : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
field_id_in : IN STD_LOGIC;
hsync_in : IN STD_LOGIC;
hblank_in : IN STD_LOGIC;
vsync_in : IN STD_LOGIC;
vblank_in : IN STD_LOGIC;
active_video_in : IN STD_LOGIC;
active_chroma_in : IN STD_LOGIC;
field_id_out : OUT STD_LOGIC;
hsync_out : OUT STD_LOGIC;
hblank_out : OUT STD_LOGIC;
vsync_out : OUT STD_LOGIC;
vblank_out : OUT STD_LOGIC;
active_video_out : OUT STD_LOGIC;
active_chroma_out : OUT STD_LOGIC;
resetn : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
irq : OUT STD_LOGIC;
fsync_in : IN STD_LOGIC;
fsync_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT v_tc;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF tutorial_v_tc_0_0_arch: ARCHITECTURE IS "v_tc,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF tutorial_v_tc_0_0_arch : ARCHITECTURE IS "tutorial_v_tc_0_0,v_tc,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF tutorial_v_tc_0_0_arch: ARCHITECTURE IS "tutorial_v_tc_0_0,v_tc,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=v_tc,x_ipVersion=6.1,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_HAS_AXI4_LITE=1,C_HAS_INTC_IF=0,C_GEN_INTERLACED=0,C_GEN_HACTIVE_SIZE=1920,C_GEN_VACTIVE_SIZE=1080,C_GEN_CPARITY=0,C_GEN_FIELDID_POLARITY=1,C_GEN_VBLANK_POLARITY=1,C_GEN_HBLANK_POLARITY=1,C_GEN_VSYNC_POLARITY=1,C_GEN_HSYNC_POLARITY=1,C_GEN_AVIDEO_POLARITY=1,C_GEN_ACHROMA_POLARITY=1,C_GEN_VIDEO_FORMAT=2,C_GEN_HFRAME_SIZE=2200,C_GEN_F0_VFRAME_SIZE=1125,C_GEN_F1_VFRAME_SIZE=1125,C_GEN_HSYNC_START=2008,C_GEN_HSYNC_END=2052,C_GEN_F0_VBLANK_HSTART=1920,C_GEN_F0_VBLANK_HEND=1920,C_GEN_F0_VSYNC_VSTART=1083,C_GEN_F0_VSYNC_VEND=1088,C_GEN_F0_VSYNC_HSTART=1920,C_GEN_F0_VSYNC_HEND=1920,C_GEN_F1_VBLANK_HSTART=1920,C_GEN_F1_VBLANK_HEND=1920,C_GEN_F1_VSYNC_VSTART=1083,C_GEN_F1_VSYNC_VEND=1088,C_GEN_F1_VSYNC_HSTART=1920,C_GEN_F1_VSYNC_HEND=1920,C_FSYNC_HSTART0=0,C_FSYNC_VSTART0=0,C_FSYNC_HSTART1=0,C_FSYNC_VSTART1=0,C_FSYNC_HSTART2=0,C_FSYNC_VSTART2=0,C_FSYNC_HSTART3=0,C_FSYNC_VSTART3=0,C_FSYNC_HSTART4=0,C_FSYNC_VSTART4=0,C_FSYNC_HSTART5=0,C_FSYNC_VSTART5=0,C_FSYNC_HSTART6=0,C_FSYNC_VSTART6=0,C_FSYNC_HSTART7=0,C_FSYNC_VSTART7=0,C_FSYNC_HSTART8=0,C_FSYNC_VSTART8=0,C_FSYNC_HSTART9=0,C_FSYNC_VSTART9=0,C_FSYNC_HSTART10=0,C_FSYNC_VSTART10=0,C_FSYNC_HSTART11=0,C_FSYNC_VSTART11=0,C_FSYNC_HSTART12=0,C_FSYNC_VSTART12=0,C_FSYNC_HSTART13=0,C_FSYNC_VSTART13=0,C_FSYNC_HSTART14=0,C_FSYNC_VSTART14=0,C_FSYNC_HSTART15=0,C_FSYNC_VSTART15=0,C_MAX_PIXELS=4096,C_MAX_LINES=4096,C_NUM_FSYNCS=1,C_INTERLACE_EN=0,C_GEN_AUTO_SWITCH=0,C_DETECT_EN=0,C_SYNC_EN=0,C_GENERATE_EN=1,C_DET_HSYNC_EN=1,C_DET_VSYNC_EN=1,C_DET_HBLANK_EN=1,C_DET_VBLANK_EN=1,C_DET_AVIDEO_EN=1,C_DET_ACHROMA_EN=0,C_GEN_HSYNC_EN=1,C_GEN_VSYNC_EN=1,C_GEN_HBLANK_EN=1,C_GEN_VBLANK_EN=1,C_GEN_AVIDEO_EN=1,C_GEN_ACHROMA_EN=0,C_GEN_FIELDID_EN=0,C_DET_FIELDID_EN=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF clken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 clken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s_axi_aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 s_axi_aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF hsync_out: SIGNAL IS "xilinx.com:interface:video_timing:2.0 vtiming_out HSYNC";
ATTRIBUTE X_INTERFACE_INFO OF hblank_out: SIGNAL IS "xilinx.com:interface:video_timing:2.0 vtiming_out HBLANK";
ATTRIBUTE X_INTERFACE_INFO OF vsync_out: SIGNAL IS "xilinx.com:interface:video_timing:2.0 vtiming_out VSYNC";
ATTRIBUTE X_INTERFACE_INFO OF vblank_out: SIGNAL IS "xilinx.com:interface:video_timing:2.0 vtiming_out VBLANK";
ATTRIBUTE X_INTERFACE_INFO OF active_video_out: SIGNAL IS "xilinx.com:interface:video_timing:2.0 vtiming_out ACTIVE_VIDEO";
ATTRIBUTE X_INTERFACE_INFO OF resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 resetn_intf RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s_axi_aresetn_intf RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl RREADY";
ATTRIBUTE X_INTERFACE_INFO OF irq: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IRQ INTERRUPT";
BEGIN
U0 : v_tc
GENERIC MAP (
C_HAS_AXI4_LITE => 1,
C_HAS_INTC_IF => 0,
C_GEN_INTERLACED => 0,
C_GEN_HACTIVE_SIZE => 1920,
C_GEN_VACTIVE_SIZE => 1080,
C_GEN_CPARITY => 0,
C_GEN_FIELDID_POLARITY => 1,
C_GEN_VBLANK_POLARITY => 1,
C_GEN_HBLANK_POLARITY => 1,
C_GEN_VSYNC_POLARITY => 1,
C_GEN_HSYNC_POLARITY => 1,
C_GEN_AVIDEO_POLARITY => 1,
C_GEN_ACHROMA_POLARITY => 1,
C_GEN_VIDEO_FORMAT => 2,
C_GEN_HFRAME_SIZE => 2200,
C_GEN_F0_VFRAME_SIZE => 1125,
C_GEN_F1_VFRAME_SIZE => 1125,
C_GEN_HSYNC_START => 2008,
C_GEN_HSYNC_END => 2052,
C_GEN_F0_VBLANK_HSTART => 1920,
C_GEN_F0_VBLANK_HEND => 1920,
C_GEN_F0_VSYNC_VSTART => 1083,
C_GEN_F0_VSYNC_VEND => 1088,
C_GEN_F0_VSYNC_HSTART => 1920,
C_GEN_F0_VSYNC_HEND => 1920,
C_GEN_F1_VBLANK_HSTART => 1920,
C_GEN_F1_VBLANK_HEND => 1920,
C_GEN_F1_VSYNC_VSTART => 1083,
C_GEN_F1_VSYNC_VEND => 1088,
C_GEN_F1_VSYNC_HSTART => 1920,
C_GEN_F1_VSYNC_HEND => 1920,
C_FSYNC_HSTART0 => 0,
C_FSYNC_VSTART0 => 0,
C_FSYNC_HSTART1 => 0,
C_FSYNC_VSTART1 => 0,
C_FSYNC_HSTART2 => 0,
C_FSYNC_VSTART2 => 0,
C_FSYNC_HSTART3 => 0,
C_FSYNC_VSTART3 => 0,
C_FSYNC_HSTART4 => 0,
C_FSYNC_VSTART4 => 0,
C_FSYNC_HSTART5 => 0,
C_FSYNC_VSTART5 => 0,
C_FSYNC_HSTART6 => 0,
C_FSYNC_VSTART6 => 0,
C_FSYNC_HSTART7 => 0,
C_FSYNC_VSTART7 => 0,
C_FSYNC_HSTART8 => 0,
C_FSYNC_VSTART8 => 0,
C_FSYNC_HSTART9 => 0,
C_FSYNC_VSTART9 => 0,
C_FSYNC_HSTART10 => 0,
C_FSYNC_VSTART10 => 0,
C_FSYNC_HSTART11 => 0,
C_FSYNC_VSTART11 => 0,
C_FSYNC_HSTART12 => 0,
C_FSYNC_VSTART12 => 0,
C_FSYNC_HSTART13 => 0,
C_FSYNC_VSTART13 => 0,
C_FSYNC_HSTART14 => 0,
C_FSYNC_VSTART14 => 0,
C_FSYNC_HSTART15 => 0,
C_FSYNC_VSTART15 => 0,
C_MAX_PIXELS => 4096,
C_MAX_LINES => 4096,
C_NUM_FSYNCS => 1,
C_INTERLACE_EN => 0,
C_GEN_AUTO_SWITCH => 0,
C_DETECT_EN => 0,
C_SYNC_EN => 0,
C_GENERATE_EN => 1,
C_DET_HSYNC_EN => 1,
C_DET_VSYNC_EN => 1,
C_DET_HBLANK_EN => 1,
C_DET_VBLANK_EN => 1,
C_DET_AVIDEO_EN => 1,
C_DET_ACHROMA_EN => 0,
C_GEN_HSYNC_EN => 1,
C_GEN_VSYNC_EN => 1,
C_GEN_HBLANK_EN => 1,
C_GEN_VBLANK_EN => 1,
C_GEN_AVIDEO_EN => 1,
C_GEN_ACHROMA_EN => 0,
C_GEN_FIELDID_EN => 0,
C_DET_FIELDID_EN => 0
)
PORT MAP (
clk => clk,
clken => clken,
s_axi_aclk => s_axi_aclk,
s_axi_aclken => s_axi_aclken,
det_clken => '1',
gen_clken => gen_clken,
field_id_in => '0',
hsync_in => '0',
hblank_in => '0',
vsync_in => '0',
vblank_in => '0',
active_video_in => '0',
active_chroma_in => '0',
hsync_out => hsync_out,
hblank_out => hblank_out,
vsync_out => vsync_out,
vblank_out => vblank_out,
active_video_out => active_video_out,
resetn => resetn,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
irq => irq,
fsync_in => fsync_in,
fsync_out => fsync_out
);
END tutorial_v_tc_0_0_arch;
|
gpl-2.0
|
af6cb0c882b65dd5ba8bca11d40c4716
| 0.655157 | 3.010003 | false | false | false | false |
michaelmiehling/A25_VME_TB
|
16x010-00_src/Source/mti_pkg.vhd
| 1 | 4,176 |
--*****************************************************************************
--
-- Micron Semiconductor Products, Inc.
--
-- Copyright 1997, Micron Semiconductor Products, Inc.
-- All rights reserved.
--
--*****************************************************************************
LIBRARY work;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE mti_pkg IS
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER;
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER;
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER;
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR);
END mti_pkg;
PACKAGE BODY mti_pkg IS
-- Convert BIT to INTEGER
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
IF input = '1' THEN
result := weight;
ELSE
result := 0; -- if unknowns, default to logic 0
END IF;
RETURN result;
END TO_INTEGER;
-- Convert BIT_VECTOR to INTEGER
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' THEN
result := result + weight;
ELSE
result := result + 0; -- if unknowns, default to logic 0
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
-- Convert STD_LOGIC_VECTOR to INTEGER
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' THEN
result := result + weight;
ELSE
result := result + 0; -- if unknowns, default to logic 0
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
-- Conver integer to bit_vector
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR) IS
VARIABLE work,offset,outputlen,j : INTEGER := 0;
BEGIN
--length of vector
IF output'LENGTH > 32 THEN
outputlen := 32;
offset := output'LENGTH - 32;
IF input >= 0 THEN
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '0';
END LOOP;
ELSE
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '1';
END LOOP;
END IF;
ELSE
outputlen := output'LENGTH;
END IF;
--positive value
IF (input >= 0) THEN
work := input;
j := outputlen - 1;
FOR i IN 1 to 32 LOOP
IF j >= 0 then
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '0';
ELSE
output(output'HIGH-j-offset) := '1';
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '0';
END IF;
--negative value
ELSE
work := (-input) - 1;
j := outputlen - 1;
FOR i IN 1 TO 32 LOOP
IF j>= 0 THEN
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '1';
ELSE
output(output'HIGH-j-offset) := '0';
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '1';
END IF;
END IF;
END TO_BITVECTOR;
END mti_pkg;
|
gpl-3.0
|
8f6a380c7f815137435fdf3948028ebe
| 0.457615 | 4.692135 | false | false | false | false |
sukinull/hls_stream
|
Vivado/example.hls/example.hls.srcs/sources_1/bd/tutorial/ip/tutorial_zed_hdmi_out_0_0/synth/tutorial_zed_hdmi_out_0_0.vhd
| 1 | 5,860 |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: avnet:zedboard:zed_hdmi_out:2.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.zed_hdmi_out;
ENTITY tutorial_zed_hdmi_out_0_0 IS
PORT (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
audio_spdif : IN STD_LOGIC;
video_vsync : IN STD_LOGIC;
video_hsync : IN STD_LOGIC;
video_de : IN STD_LOGIC;
video_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
io_hdmio_spdif : OUT STD_LOGIC;
io_hdmio_video : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
io_hdmio_vsync : OUT STD_LOGIC;
io_hdmio_hsync : OUT STD_LOGIC;
io_hdmio_de : OUT STD_LOGIC;
io_hdmio_clk : OUT STD_LOGIC
);
END tutorial_zed_hdmi_out_0_0;
ARCHITECTURE tutorial_zed_hdmi_out_0_0_arch OF tutorial_zed_hdmi_out_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tutorial_zed_hdmi_out_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT zed_hdmi_out IS
GENERIC (
C_DATA_WIDTH : INTEGER; -- Video Data Width
C_FAMILY : STRING
);
PORT (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
audio_spdif : IN STD_LOGIC;
video_vsync : IN STD_LOGIC;
video_hsync : IN STD_LOGIC;
video_de : IN STD_LOGIC;
video_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
io_hdmio_spdif : OUT STD_LOGIC;
io_hdmio_video : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
io_hdmio_vsync : OUT STD_LOGIC;
io_hdmio_hsync : OUT STD_LOGIC;
io_hdmio_de : OUT STD_LOGIC;
io_hdmio_clk : OUT STD_LOGIC
);
END COMPONENT zed_hdmi_out;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF tutorial_zed_hdmi_out_0_0_arch: ARCHITECTURE IS "zed_hdmi_out,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF tutorial_zed_hdmi_out_0_0_arch : ARCHITECTURE IS "tutorial_zed_hdmi_out_0_0,zed_hdmi_out,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF video_vsync: SIGNAL IS "xilinx.com:interface:vid_io:1.0 VID_IO_IN VSYNC";
ATTRIBUTE X_INTERFACE_INFO OF video_hsync: SIGNAL IS "xilinx.com:interface:vid_io:1.0 VID_IO_IN HSYNC";
ATTRIBUTE X_INTERFACE_INFO OF video_de: SIGNAL IS "xilinx.com:interface:vid_io:1.0 VID_IO_IN ACTIVE_VIDEO";
ATTRIBUTE X_INTERFACE_INFO OF video_data: SIGNAL IS "xilinx.com:interface:vid_io:1.0 VID_IO_IN DATA";
ATTRIBUTE X_INTERFACE_INFO OF io_hdmio_spdif: SIGNAL IS "avnet.com:interface:avnet_hdmi:1.0 IO_HDMIO SPDIF";
ATTRIBUTE X_INTERFACE_INFO OF io_hdmio_video: SIGNAL IS "avnet.com:interface:avnet_hdmi:1.0 IO_HDMIO DATA";
ATTRIBUTE X_INTERFACE_INFO OF io_hdmio_vsync: SIGNAL IS "avnet.com:interface:avnet_hdmi:1.0 IO_HDMIO VSYNC";
ATTRIBUTE X_INTERFACE_INFO OF io_hdmio_hsync: SIGNAL IS "avnet.com:interface:avnet_hdmi:1.0 IO_HDMIO HSYNC";
ATTRIBUTE X_INTERFACE_INFO OF io_hdmio_de: SIGNAL IS "avnet.com:interface:avnet_hdmi:1.0 IO_HDMIO DE";
ATTRIBUTE X_INTERFACE_INFO OF io_hdmio_clk: SIGNAL IS "avnet.com:interface:avnet_hdmi:1.0 IO_HDMIO CLK";
BEGIN
U0 : zed_hdmi_out
GENERIC MAP (
C_DATA_WIDTH => 16,
C_FAMILY => "zynq"
)
PORT MAP (
clk => clk,
reset => reset,
audio_spdif => audio_spdif,
video_vsync => video_vsync,
video_hsync => video_hsync,
video_de => video_de,
video_data => video_data,
io_hdmio_spdif => io_hdmio_spdif,
io_hdmio_video => io_hdmio_video,
io_hdmio_vsync => io_hdmio_vsync,
io_hdmio_hsync => io_hdmio_hsync,
io_hdmio_de => io_hdmio_de,
io_hdmio_clk => io_hdmio_clk
);
END tutorial_zed_hdmi_out_0_0_arch;
|
gpl-2.0
|
7fcb27c594a6767a465f6073c32f9d35
| 0.708362 | 3.557984 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/altera_lnsim/ama_latency_function/_primary.vhd
| 5 | 1,256 |
library verilog;
use verilog.vl_types.all;
entity ama_latency_function is
generic(
width_data_in : integer := 1;
width_data_out : integer := 1;
latency : integer := 0;
latency_clock : string := "UNREGISTERED";
latency_aclr : string := "NONE";
width_data_in_msb: vl_notype;
width_data_out_msb: vl_notype
);
port(
clock : in vl_logic_vector(3 downto 0);
aclr : in vl_logic_vector(3 downto 0);
ena : in vl_logic_vector(3 downto 0);
data_in : in vl_logic_vector;
data_out : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width_data_in : constant is 1;
attribute mti_svvh_generic_type of width_data_out : constant is 1;
attribute mti_svvh_generic_type of latency : constant is 1;
attribute mti_svvh_generic_type of latency_clock : constant is 1;
attribute mti_svvh_generic_type of latency_aclr : constant is 1;
attribute mti_svvh_generic_type of width_data_in_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_out_msb : constant is 3;
end ama_latency_function;
|
mit
|
ab77cd9383f1c817353ed1ca5f580850
| 0.607484 | 3.651163 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/StateMachineEditor1_import.vhd
| 2 | 1,173 |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity StateMachineEditor1_import is
port (
clock : in std_logic;
col_select : in std_logic_vector(3-1 downto 0);
data : out std_logic_vector(24-1 downto 0);
data_en : in std_logic;
reset : in std_logic
);
end entity StateMachineEditor1_import;
architecture rtl of StateMachineEditor1_import is
component StateMachineEditor1_import_GN is
port (
clock : in std_logic;
col_select : in std_logic_vector(3-1 downto 0);
data : out std_logic_vector(24-1 downto 0);
data_en : in std_logic;
reset : in std_logic
);
end component StateMachineEditor1_import_GN;
begin
StateMachineEditor1_import_GN_0: if true generate
inst_StateMachineEditor1_import_GN_0: StateMachineEditor1_import_GN
port map(clock => clock, col_select => col_select, data => data, data_en => data_en, reset => reset);
end generate;
end architecture rtl;
|
mit
|
c69f883c62230e60c8baf4afdc6c9e3e
| 0.73913 | 3.34188 | false | false | false | false |
michaelmiehling/A25_VME_TB
|
Testbench/SN74ABT125.vhd
| 1 | 5,058 |
---------------------------------------------------------------
-- Title : Bus Buffer Gates with 3-state outputs
-- Project :
---------------------------------------------------------------
-- File : SN74ABT125.vhd
-- Author : Michael Miehling
-- Email : [email protected]
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 09/02/12
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description :
--
--
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
-- Copyright (C) 2001, MEN Mikroelektronik Nuernberg GmbH
--
-- All rights reserved. Reproduction in whole or part is
-- prohibited without the written permission of the
-- copyright owner.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.1 $
--
-- $Log: SN74ABT125.vhd,v $
-- Revision 1.1 2012/03/29 10:28:41 MMiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SN74ABT125 IS
GENERIC (
OP_COND : integer:=1; -- 0=min, 1=typ, 2=max
WIDTH : integer:=8
);
PORT (
oe_n : IN std_logic_vector(WIDTH-1 DOWNTO 0); -- output enable: 0= driver is active, 1= tri-state
a : IN std_logic_vector(WIDTH-1 DOWNTO 0); -- port A
b : OUT std_logic_vector(WIDTH-1 DOWNTO 0) -- port B
);
END SN74ABT125;
ARCHITECTURE SN74ABT125_arch OF SN74ABT125 IS
CONSTANT tPLH_max : time:= 4.9 ns;
CONSTANT tPHL_max : time:= 4.9 ns;
CONSTANT tPZH_max : time:= 5.9 ns;
CONSTANT tPZL_max : time:= 6.8 ns;
CONSTANT tPHZ_max : time:= 6.2 ns;
CONSTANT tPLZ_max : time:= 6.2 ns;
CONSTANT tPLH_min : time:= 1 ns;
CONSTANT tPHL_min : time:= 1 ns;
CONSTANT tPZH_min : time:= 1 ns;
CONSTANT tPZL_min : time:= 1 ns;
CONSTANT tPHZ_min : time:= 1 ns;
CONSTANT tPLZ_min : time:= 1 ns;
CONSTANT tPLH_typ : time:= 3.2 ns;
CONSTANT tPHL_typ : time:= 2.5 ns;
CONSTANT tPZH_typ : time:= 3.6 ns;
CONSTANT tPZL_typ : time:= 2.5 ns;
CONSTANT tPHZ_typ : time:= 3.8 ns;
CONSTANT tPLZ_typ : time:= 3.3 ns;
SIGNAL b_out : std_logic_vector(WIDTH-1 DOWNTO 0);
SIGNAL oe_n_in : std_logic_vector(WIDTH-1 DOWNTO 0);
SIGNAL a_in : std_logic_vector(WIDTH-1 DOWNTO 0);
SIGNAL tPLH : time;
SIGNAL tPHL : time;
SIGNAL tPZH : time;
SIGNAL tPZL : time;
SIGNAL tPHZ : time;
SIGNAL tPLZ : time;
SIGNAL pwr_rst : std_logic;
BEGIN
tPLH <= tPLH_min WHEN OP_COND = 0 ELSE
tPLH_typ WHEN OP_COND = 1 ELSE
tPLH_max;
tPHL <= tPHL_min WHEN OP_COND = 0 ELSE
tPHL_typ WHEN OP_COND = 1 ELSE
tPHL_max;
tPZH <= tPZH_min WHEN OP_COND = 0 ELSE
tPZH_typ WHEN OP_COND = 1 ELSE
tPZH_max;
tPZL <= tPZL_min WHEN OP_COND = 0 ELSE
tPZL_typ WHEN OP_COND = 1 ELSE
tPZL_max;
tPHZ <= tPHZ_min WHEN OP_COND = 0 ELSE
tPHZ_typ WHEN OP_COND = 1 ELSE
tPHZ_max;
tPLZ <= tPLZ_min WHEN OP_COND = 0 ELSE
tPLZ_typ WHEN OP_COND = 1 ELSE
tPLZ_max;
oe_n_in <= to_x01(oe_n);
a_in <= to_x01(a);
pwr_rst <= '1', '0' AFTER 2 ps;
b <= b_out;
gen: FOR i IN 0 TO WIDTH-1 GENERATE
PROCESS(pwr_rst, oe_n_in(i), a_in(i), b_out(i))
BEGIN
IF pwr_rst'event AND oe_n_in(i) = '1' THEN
b_out(i) <= 'H';
ELSIF pwr_rst'event AND oe_n_in(i) = '0' THEN
b_out(i) <= a_in(i);
ELSIF (a_in(i)'event AND a_in(i) = '1' AND oe_n_in(i) = '0' ) THEN -- a 0->1
b_out(i) <= transport a_in(i) AFTER tPLH;
ELSIF (a_in(i)'event AND a_in(i) = '0' AND oe_n_in(i) = '0') THEN -- a 1->0
b_out(i) <= transport a_in(i) AFTER tPHL;
ELSIF (oe_n_in'event AND oe_n_in(i) = '0' AND a_in(i) = '1') THEN -- oe_n_in 1->0 a=1
b_out(i) <= transport a_in(i) AFTER tPZH;
ELSIF (oe_n_in'event AND oe_n_in(i) = '0' AND a(i) = '0') THEN -- oe_n_in 1->0 a=0
b_out(i) <= transport a_in(i) AFTER tPZL;
ELSIF (oe_n_in'event AND oe_n_in(i) = '1' AND b_out(i) = '1') THEN -- oe_n_in 0->1 b=1
b_out(i) <= transport 'H' AFTER tPHZ;
ELSIF (oe_n_in'event AND oe_n_in(i) = '1' AND b_out(i) = '0') THEN -- oe_n_in 0->1 b=0
b_out(i) <= transport 'H' AFTER tPLZ;
END IF;
END PROCESS;
END GENERATE gen;
END SN74ABT125_arch;
|
gpl-3.0
|
ded6a14772430b1feb8f1ead4c5e1743
| 0.456505 | 3.433809 | false | false | false | false |
adelapie/desl
|
tb_des_loop.vhd
| 1 | 2,732 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_des_loop IS
END tb_des_loop;
ARCHITECTURE behavior OF tb_des_loop IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT des_loop
PORT(
clk : IN std_logic;
rst : IN std_logic;
mode : IN std_logic;
key_in : IN std_logic_vector(55 downto 0);
blk_in : IN std_logic_vector(63 downto 0);
blk_out : OUT std_logic_vector(63 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal mode : std_logic := '0';
signal key_in : std_logic_vector(55 downto 0) := (others => '0');
signal blk_in : std_logic_vector(63 downto 0) := (others => '0');
--Outputs
signal blk_out : std_logic_vector(63 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: des_loop PORT MAP (
clk => clk,
rst => rst,
mode => mode,
key_in => key_in,
blk_in => blk_in,
blk_out => blk_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + clk_period;
mode <= '0';
blk_in <= X"4E45565251554954";
key_in <= "00000000111111110000000000101010010100000000000110010100";
rst <= '1';
wait for clk_period;
rst <= '0';
wait for clk_period*16;
assert blk_out = X"72c6e3c6d2168e78"
report "ENCRYPT ERROR" severity FAILURE;
wait for clk_period;
mode <= '1';
blk_in <= X"72c6e3c6d2168e78";
key_in <= "00000000111111110000000000101010010100000000000110010100";
rst <= '1';
wait for clk_period;
rst <= '0';
wait for clk_period*16;
assert blk_out = X"4E45565251554954"
report "DECRYPT ERROR" severity FAILURE;
wait;
end process;
END;
|
gpl-3.0
|
0edc868a47fa6d9e8eee769f7b19e4ab
| 0.63287 | 3.480255 | false | false | false | false |
michaelmiehling/A25_VME_TB
|
Testbench/M25P32/mem_util_pkg.vhd
| 1 | 5,403 |
-------------------------------------------------------
-- Author: Hugues CREUSY
--February 2004
-- VHDL model
-- project: M25P32 50 MHz,
-- release: 1.0
-----------------------------------------------------
-- Unit : Package mem_util_pkg
-----------------------------------------------------
-------------------------------------------------------------
-- These VHDL models are provided "as is" without warranty
-- of any kind, included but not limited to, implied warranty
-- of merchantability and fitness for a particular purpose.
-------------------------------------------------------------
-------------------------------------------------------------------------
-- Memory utilization package
-------------------------------------------------------------------------
library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
-------------------------------------------------------------------------
-- PACKAGE
-------------------------------------------------------------------------
PACKAGE mem_util_pkg IS
TYPE PAGE is ARRAY (natural range <>) of std_logic_vector(7 downto 0);
--------------------------------------------------------------------
-- To convert a standard logic vector (ie a binary word) into
-- a natural
---------------------------------------------------------------------
FUNCTION TO_natural(vecteur_bit : std_logic_vector ) RETURN natural ;
---------------------------------------------------------------------
---------------------------------------------------------------------------
-- To increase the adress pointing vector
---------------------------------------------------------------------------
FUNCTION add_inc(vecteur_bit : std_logic_vector ) RETURN std_logic_vector ;
---------------------------------------------------------------------------
--------------------------------------------------------------------
-- To get the number of bits used to code the memory
-- which size (number of bytes) is a parameter
--------------------------------------------------------------------
FUNCTION TO_bit_code(nb_octets: positive) RETURN natural ;
--------------------------------------------------------------------
------------------------------------------------------------------------
-- To get the first adress of the sector pointed by anyone of its bytes.
------------------------------------------------------------------------
FUNCTION add_sector(vecteur_bit: std_logic_vector;
NB_byte_mem,NB_byte_sect: positive) RETURN natural;
------------------------------------------------------------------------
--------------------------------------------------------------------------
-- To convert an integer (ARG) into a standard logic vector with its size.
--------------------------------------------------------------------------
FUNCTION TO_std_logic_vector(ARG: INTEGER; SIZE: INTEGER)
RETURN STD_LOGIC_VECTOR;
--------------------------------------------------------------------------
END mem_util_pkg;
---------------------------------------------------------------
-- Package body
---------------------------------------------------------------
PACKAGE BODY mem_util_pkg IS
----------------------------------------------------------------
FUNCTION TO_natural(vecteur_bit : std_logic_vector ) RETURN natural IS
VARIABLE val_vecteur: natural := 0;
BEGIN
FOR J IN vecteur_bit'RANGE LOOP
val_vecteur := val_vecteur * 2;
val_vecteur := val_vecteur + std_logic'pos(vecteur_bit(J)) - 2;
END LOOP;
RETURN val_vecteur;
END TO_natural;
---------------------------------------------------------------
FUNCTION add_inc(vecteur_bit : std_logic_vector ) RETURN std_logic_vector IS
VARIABLE val_vecteur: std_logic_vector(vecteur_bit'RANGE);
BEGIN
val_vecteur := vecteur_bit;
FOR J IN vecteur_bit'REVERSE_RANGE LOOP
val_vecteur(J) := "XOR"( vecteur_bit(J), '1' );
IF (val_vecteur(J) = '1') THEN
EXIT;
END IF;
END LOOP;
RETURN val_vecteur;
END add_inc;
-----------------------------------------------------------------
FUNCTION TO_bit_code(nb_octets: positive) RETURN natural IS
VARIABLE val_add, add_bit_code: natural ;
BEGIN
val_add := nb_octets;
add_bit_code := 0;
IF ((val_add rem 2)/=0) THEN
val_add := val_add - 1 ;
add_bit_code := add_bit_code + 1 ;
END IF;
WHILE ( val_add > 1 ) LOOP
val_add := (val_add/2);
add_bit_code := add_bit_code + 1;
END LOOP;
RETURN add_bit_code;
END TO_bit_code;
---------------------------------------------------------------
FUNCTION TO_std_logic_vector(ARG: INTEGER; SIZE: INTEGER)
RETURN STD_LOGIC_VECTOR IS
variable result: STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable temp: integer;
begin
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
else
temp := (temp - 1) / 2;
end if;
end loop;
return result;
END TO_std_logic_vector;
------------------------------------------------------------
FUNCTION add_sector(vecteur_bit:std_logic_vector;NB_byte_mem,NB_byte_sect:positive)
RETURN natural IS
VARIABLE addr_sector,deb_sect: natural := 0;
BEGIN
addr_sector := TO_natural(vecteur_bit);
FOR i IN 1 TO (NB_byte_mem/NB_byte_sect) LOOP
IF ((i-1)*NB_byte_sect<=addr_sector AND addr_sector < i*NB_byte_sect) THEN
deb_sect:=(i-1)*NB_byte_sect;
END IF;
END LOOP;
RETURN deb_sect;
END add_sector;
--------------------------------------------------------------
END mem_util_pkg;
|
gpl-3.0
|
563c19f81ab70fe8839f7ff903f4e478
| 0.419952 | 4.718777 | false | false | false | false |
nulldozer/purisc
|
Compute_Group/CORE/execute_stage.vhd
| 1 | 2,962 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity execute_stage is
port(
clk : in std_logic;
reset_n : in std_logic;
stall : in std_logic;
noop_in : in std_logic;
--inputs
ubranch_in : in std_logic;
cbranch_in : in std_logic;
ex_w_addr : in std_logic_vector(31 downto 0);
ex_w_data : in std_logic_vector(31 downto 0);
ex_we : in std_logic;
start_address : in std_logic_vector(31 downto 0);
a_in : in std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0);
c_in : in std_logic_vector(31 downto 0);
addr_a : in std_logic_vector(31 downto 0);
addr_b : in std_logic_vector(31 downto 0);
addr_c : in std_logic_vector(31 downto 0);
next_pc : in std_logic_vector(31 downto 0);
--outputs
cbranch_out : out std_logic;
cbranch_addr : out std_logic_vector(31 downto 0);
-- memory
da_in : in std_logic_vector(31 downto 0);
db_in : in std_logic_vector(31 downto 0);
w_data : out std_logic_vector(31 downto 0);
w_addr : out std_logic_vector(31 downto 0);
we_out : out std_logic
);
end entity;
architecture a1 of execute_stage is
--signals
signal da_fwd : std_logic_vector(31 downto 0);
signal db_fwd : std_logic_vector(31 downto 0);
-- --for self-modifying instruction forwarding
-- signal a_fwd : std_logic_vector(31 downto 0);
-- signal b_fwd : std_logic_vector(31 downto 0);
-- signal c_fwd : std_logic_vector(31 downto 0);
signal sub : signed(31 downto 0);
signal cbranch : std_logic;
signal we : std_logic;
begin
--determine forwarding
da_fwd <= ex_w_data when (a_in = ex_w_addr and ex_we = '1') else da_in;
db_fwd <= ex_w_data when (b_in = ex_w_addr and ex_we = '1') else db_in;
-- --self-modifying instruction forwarding (NOT USED. To enable this, replace instances of a with a_fwd, b with b_fwd ...)
-- a_fwd <= ex_db when (addr_a = ex_b) else a_in;
-- b_fwd <= ex_db when (addr_b = ex_b) else b_in;
-- c_fwd <= ex_db when (addr_c = ex_b) else c_in;
--'execute'
sub <= signed(db_fwd) - signed(da_fwd);
--determine cbranch
cbranch <= '1' when (sub <= 0 and not(noop_in = '1') and not(ubranch_in = '1') and not(next_pc = c_in)) else '0';
--determine whether to write
we <= '1' when (not(noop_in = '1') and not(cbranch_in = '1')) else '0';
process(clk, reset_n, start_address) begin
if(reset_n = '0') then
--initial values
w_data <= "00000000000000000000000000000000";
w_addr <= std_logic_vector(unsigned(start_address) + to_unsigned(7,32)); --as if the third instruction is executing
we_out <= '0';
cbranch_out <= '0';
elsif (rising_edge(clk)) then
if(stall = '0') then
cbranch_out <= cbranch;
cbranch_addr <= c_in;
if(not(noop_in = '1')) then w_addr <= b_in; end if; --to prevent undefined address output after reset
w_data <= std_logic_vector(sub);
we_out <= we;
else
--hold previous outputs on stall (automatic)
end if;
end if;
end process;
end architecture;
|
gpl-2.0
|
4420b7d022f4f43431fdaf136cdfe054
| 0.644159 | 2.742593 | false | false | false | false |
sukinull/hls_stream
|
Vivado/example.hls/example.hls.srcs/sources_1/bd/tutorial/ip/tutorial_proc_sys_reset_0/synth/tutorial_proc_sys_reset_0.vhd
| 1 | 6,670 |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY tutorial_proc_sys_reset_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END tutorial_proc_sys_reset_0;
ARCHITECTURE tutorial_proc_sys_reset_0_arch OF tutorial_proc_sys_reset_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tutorial_proc_sys_reset_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF tutorial_proc_sys_reset_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF tutorial_proc_sys_reset_0_arch : ARCHITECTURE IS "tutorial_proc_sys_reset_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF tutorial_proc_sys_reset_0_arch: ARCHITECTURE IS "tutorial_proc_sys_reset_0,proc_sys_reset,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END tutorial_proc_sys_reset_0_arch;
|
gpl-2.0
|
2f8675536df7e4e36af611f1be3f25a1
| 0.715292 | 3.504992 | false | false | false | false |
sukinull/hls_stream
|
Vivado/example.hls/example.hls.srcs/sources_1/bd/tutorial/ip/tutorial_axi_vdma_0_0/synth/tutorial_axi_vdma_0_0.vhd
| 1 | 23,418 |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_vdma:6.2
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_vdma_v6_2;
USE axi_vdma_v6_2.axi_vdma;
ENTITY tutorial_axi_vdma_0_0 IS
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axis_mm2s_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mm2s_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
mm2s_introut : OUT STD_LOGIC
);
END tutorial_axi_vdma_0_0;
ARCHITECTURE tutorial_axi_vdma_0_0_arch OF tutorial_axi_vdma_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tutorial_axi_vdma_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_vdma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_ENABLE_VIDPRMTR_READS : INTEGER;
C_DYNAMIC_RESOLUTION : INTEGER;
C_NUM_FSTORES : INTEGER;
C_USE_FSYNC : INTEGER;
C_USE_MM2S_FSYNC : INTEGER;
C_USE_S2MM_FSYNC : INTEGER;
C_FLUSH_ON_FSYNC : INTEGER;
C_INCLUDE_INTERNAL_GENLOCK : INTEGER;
C_INCLUDE_SG : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_MM2S_GENLOCK_MODE : INTEGER;
C_MM2S_GENLOCK_NUM_MASTERS : INTEGER;
C_MM2S_GENLOCK_REPEAT_EN : INTEGER;
C_MM2S_SOF_ENABLE : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_LINEBUFFER_DEPTH : INTEGER;
C_MM2S_LINEBUFFER_THRESH : INTEGER;
C_MM2S_MAX_BURST_LENGTH : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TUSER_BITS : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_S2MM_GENLOCK_MODE : INTEGER;
C_S2MM_GENLOCK_NUM_MASTERS : INTEGER;
C_S2MM_GENLOCK_REPEAT_EN : INTEGER;
C_S2MM_SOF_ENABLE : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_LINEBUFFER_DEPTH : INTEGER;
C_S2MM_LINEBUFFER_THRESH : INTEGER;
C_S2MM_MAX_BURST_LENGTH : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TUSER_BITS : INTEGER;
C_ENABLE_DEBUG_ALL : INTEGER;
C_ENABLE_DEBUG_INFO_0 : INTEGER;
C_ENABLE_DEBUG_INFO_1 : INTEGER;
C_ENABLE_DEBUG_INFO_2 : INTEGER;
C_ENABLE_DEBUG_INFO_3 : INTEGER;
C_ENABLE_DEBUG_INFO_4 : INTEGER;
C_ENABLE_DEBUG_INFO_5 : INTEGER;
C_ENABLE_DEBUG_INFO_6 : INTEGER;
C_ENABLE_DEBUG_INFO_7 : INTEGER;
C_ENABLE_DEBUG_INFO_8 : INTEGER;
C_ENABLE_DEBUG_INFO_9 : INTEGER;
C_ENABLE_DEBUG_INFO_10 : INTEGER;
C_ENABLE_DEBUG_INFO_11 : INTEGER;
C_ENABLE_DEBUG_INFO_12 : INTEGER;
C_ENABLE_DEBUG_INFO_13 : INTEGER;
C_ENABLE_DEBUG_INFO_14 : INTEGER;
C_ENABLE_DEBUG_INFO_15 : INTEGER;
C_INSTANCE : STRING;
C_FAMILY : STRING
);
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axis_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
s_axis_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mm2s_fsync : IN STD_LOGIC;
mm2s_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mm2s_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
s2mm_fsync : IN STD_LOGIC;
s2mm_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
s2mm_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
mm2s_buffer_empty : OUT STD_LOGIC;
mm2s_buffer_almost_empty : OUT STD_LOGIC;
s2mm_buffer_full : OUT STD_LOGIC;
s2mm_buffer_almost_full : OUT STD_LOGIC;
mm2s_fsync_out : OUT STD_LOGIC;
s2mm_fsync_out : OUT STD_LOGIC;
mm2s_prmtr_update : OUT STD_LOGIC;
s2mm_prmtr_update : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_vdma_tstvec : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END COMPONENT axi_vdma;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF tutorial_axi_vdma_0_0_arch: ARCHITECTURE IS "axi_vdma,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF tutorial_axi_vdma_0_0_arch : ARCHITECTURE IS "tutorial_axi_vdma_0_0,axi_vdma,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF tutorial_axi_vdma_0_0_arch: ARCHITECTURE IS "tutorial_axi_vdma_0_0,axi_vdma,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_vdma,x_ipVersion=6.2,x_ipCoreRevision=2,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=9,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=1,C_ENABLE_VIDPRMTR_READS=1,C_DYNAMIC_RESOLUTION=1,C_NUM_FSTORES=3,C_USE_FSYNC=1,C_USE_MM2S_FSYNC=0,C_USE_S2MM_FSYNC=2,C_FLUSH_ON_FSYNC=1,C_INCLUDE_INTERNAL_GENLOCK=1,C_INCLUDE_SG=0,C_M_AXI_SG_ADDR_WIDTH=32,C_M_AXI_SG_DATA_WIDTH=32,C_INCLUDE_MM2S=1,C_MM2S_GENLOCK_MODE=0,C_MM2S_GENLOCK_NUM_MASTERS=1,C_MM2S_GENLOCK_REPEAT_EN=0,C_MM2S_SOF_ENABLE=1,C_INCLUDE_MM2S_DRE=1,C_INCLUDE_MM2S_SF=0,C_MM2S_LINEBUFFER_DEPTH=4096,C_MM2S_LINEBUFFER_THRESH=4,C_MM2S_MAX_BURST_LENGTH=8,C_M_AXI_MM2S_ADDR_WIDTH=32,C_M_AXI_MM2S_DATA_WIDTH=64,C_M_AXIS_MM2S_TDATA_WIDTH=32,C_M_AXIS_MM2S_TUSER_BITS=1,C_INCLUDE_S2MM=0,C_S2MM_GENLOCK_MODE=0,C_S2MM_GENLOCK_NUM_MASTERS=1,C_S2MM_GENLOCK_REPEAT_EN=1,C_S2MM_SOF_ENABLE=1,C_INCLUDE_S2MM_DRE=0,C_INCLUDE_S2MM_SF=1,C_S2MM_LINEBUFFER_DEPTH=512,C_S2MM_LINEBUFFER_THRESH=4,C_S2MM_MAX_BURST_LENGTH=8,C_M_AXI_S2MM_ADDR_WIDTH=32,C_M_AXI_S2MM_DATA_WIDTH=64,C_S_AXIS_S2MM_TDATA_WIDTH=32,C_S_AXIS_S2MM_TUSER_BITS=1,C_ENABLE_DEBUG_ALL=0,C_ENABLE_DEBUG_INFO_0=0,C_ENABLE_DEBUG_INFO_1=0,C_ENABLE_DEBUG_INFO_2=0,C_ENABLE_DEBUG_INFO_3=0,C_ENABLE_DEBUG_INFO_4=0,C_ENABLE_DEBUG_INFO_5=0,C_ENABLE_DEBUG_INFO_6=0,C_ENABLE_DEBUG_INFO_7=0,C_ENABLE_DEBUG_INFO_8=0,C_ENABLE_DEBUG_INFO_9=0,C_ENABLE_DEBUG_INFO_10=0,C_ENABLE_DEBUG_INFO_11=0,C_ENABLE_DEBUG_INFO_12=0,C_ENABLE_DEBUG_INFO_13=0,C_ENABLE_DEBUG_INFO_14=0,C_ENABLE_DEBUG_INFO_15=0,C_INSTANCE=axi_vdma,C_FAMILY=zynq}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIS_MM2S_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_frame_ptr_out: SIGNAL IS "xilinx.com:signal:video_frame_ptr:1.0 MM2S_FRAME_PTR_OUT FRAME_PTR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TUSER";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT";
BEGIN
U0 : axi_vdma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 9,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 1,
C_ENABLE_VIDPRMTR_READS => 1,
C_DYNAMIC_RESOLUTION => 1,
C_NUM_FSTORES => 3,
C_USE_FSYNC => 1,
C_USE_MM2S_FSYNC => 0,
C_USE_S2MM_FSYNC => 2,
C_FLUSH_ON_FSYNC => 1,
C_INCLUDE_INTERNAL_GENLOCK => 1,
C_INCLUDE_SG => 0,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_INCLUDE_MM2S => 1,
C_MM2S_GENLOCK_MODE => 0,
C_MM2S_GENLOCK_NUM_MASTERS => 1,
C_MM2S_GENLOCK_REPEAT_EN => 0,
C_MM2S_SOF_ENABLE => 1,
C_INCLUDE_MM2S_DRE => 1,
C_INCLUDE_MM2S_SF => 0,
C_MM2S_LINEBUFFER_DEPTH => 4096,
C_MM2S_LINEBUFFER_THRESH => 4,
C_MM2S_MAX_BURST_LENGTH => 8,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 64,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_M_AXIS_MM2S_TUSER_BITS => 1,
C_INCLUDE_S2MM => 0,
C_S2MM_GENLOCK_MODE => 0,
C_S2MM_GENLOCK_NUM_MASTERS => 1,
C_S2MM_GENLOCK_REPEAT_EN => 1,
C_S2MM_SOF_ENABLE => 1,
C_INCLUDE_S2MM_DRE => 0,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_LINEBUFFER_DEPTH => 512,
C_S2MM_LINEBUFFER_THRESH => 4,
C_S2MM_MAX_BURST_LENGTH => 8,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 64,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_TUSER_BITS => 1,
C_ENABLE_DEBUG_ALL => 0,
C_ENABLE_DEBUG_INFO_0 => 0,
C_ENABLE_DEBUG_INFO_1 => 0,
C_ENABLE_DEBUG_INFO_2 => 0,
C_ENABLE_DEBUG_INFO_3 => 0,
C_ENABLE_DEBUG_INFO_4 => 0,
C_ENABLE_DEBUG_INFO_5 => 0,
C_ENABLE_DEBUG_INFO_6 => 0,
C_ENABLE_DEBUG_INFO_7 => 0,
C_ENABLE_DEBUG_INFO_8 => 0,
C_ENABLE_DEBUG_INFO_9 => 0,
C_ENABLE_DEBUG_INFO_10 => 0,
C_ENABLE_DEBUG_INFO_11 => 0,
C_ENABLE_DEBUG_INFO_12 => 0,
C_ENABLE_DEBUG_INFO_13 => 0,
C_ENABLE_DEBUG_INFO_14 => 0,
C_ENABLE_DEBUG_INFO_15 => 0,
C_INSTANCE => "axi_vdma",
C_FAMILY => "zynq"
)
PORT MAP (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => '0',
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axis_mm2s_aclk => m_axis_mm2s_aclk,
m_axi_s2mm_aclk => '0',
s_axis_s2mm_aclk => '0',
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
mm2s_fsync => '0',
mm2s_frame_ptr_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
mm2s_frame_ptr_out => mm2s_frame_ptr_out,
s2mm_fsync => '0',
s2mm_frame_ptr_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
m_axi_sg_arready => '0',
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_rlast => '0',
m_axi_sg_rvalid => '0',
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tuser => m_axis_mm2s_tuser,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axi_s2mm_awready => '0',
m_axi_s2mm_wready => '0',
m_axi_s2mm_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_s2mm_bvalid => '0',
s_axis_s2mm_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_s2mm_tkeep => X"F",
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_s2mm_tvalid => '0',
s_axis_s2mm_tlast => '0',
mm2s_introut => mm2s_introut
);
END tutorial_axi_vdma_0_0_arch;
|
gpl-2.0
|
66965357081a909c6517b749dd724817
| 0.669314 | 2.771689 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/altera_lnsim/altera_syncram/_primary.vhd
| 5 | 9,140 |
library verilog;
use verilog.vl_types.all;
entity altera_syncram is
generic(
width_a : integer := 1;
widthad_a : integer := 1;
numwords_a : integer := 0;
outdata_reg_a : string := "UNREGISTERED";
address_aclr_a : string := "NONE";
outdata_aclr_a : string := "NONE";
indata_aclr_a : string := "NONE";
wrcontrol_aclr_a: string := "NONE";
byteena_aclr_a : string := "NONE";
width_byteena_a : integer := 1;
width_b : integer := 1;
widthad_b : integer := 1;
numwords_b : integer := 0;
rdcontrol_reg_b : string := "CLOCK1";
address_reg_b : string := "CLOCK1";
outdata_reg_b : string := "UNREGISTERED";
outdata_aclr_b : string := "NONE";
rdcontrol_aclr_b: string := "NONE";
indata_reg_b : string := "CLOCK1";
byteena_reg_b : string := "CLOCK1";
indata_aclr_b : string := "NONE";
wrcontrol_aclr_b: string := "NONE";
address_aclr_b : string := "NONE";
byteena_aclr_b : string := "NONE";
width_byteena_b : integer := 1;
clock_enable_input_a: string := "NORMAL";
clock_enable_output_a: string := "NORMAL";
clock_enable_input_b: string := "NORMAL";
clock_enable_output_b: string := "NORMAL";
clock_enable_core_a: string := "USE_INPUT_CLKEN";
clock_enable_core_b: string := "USE_INPUT_CLKEN";
read_during_write_mode_port_a: string := "NEW_DATA_NO_NBE_READ";
read_during_write_mode_port_b: string := "NEW_DATA_NO_NBE_READ";
read_during_write_mode_mixed_ports: string := "DONT_CARE";
enable_ecc : string := "FALSE";
width_eccstatus : integer := 3;
ecc_pipeline_stage_enabled: string := "FALSE";
operation_mode : string := "BIDIR_DUAL_PORT";
byte_size : integer := 0;
ram_block_type : string := "AUTO";
init_file : string := "UNUSED";
init_file_layout: string := "UNUSED";
maximum_depth : integer := 0;
intended_device_family: string := "Stratix V";
lpm_hint : string := "UNUSED";
lpm_type : string := "altsyncram";
implement_in_les: string := "OFF";
power_up_uninitialized: string := "FALSE";
sim_show_memory_data_in_port_b_layout: string := "OFF";
is_lutram : vl_notype;
is_bidir_and_wrcontrol_addb_clk0: vl_notype;
is_bidir_and_wrcontrol_addb_clk1: vl_notype;
dual_port_addreg_b_clk0: vl_notype;
dual_port_addreg_b_clk1: vl_notype;
i_byte_size_tmp : vl_notype;
i_lutram_read : vl_notype;
enable_mem_data_b_reading: vl_notype;
wrcontrol_wraddress_reg_b: vl_notype;
is_write_on_positive_edge: integer := 1;
lutram_single_port_fast_read: vl_notype;
lutram_dual_port_fast_read: vl_notype;
s3_address_aclr_a: vl_notype;
s3_address_aclr_b: vl_notype;
i_address_aclr_family_a: vl_notype;
i_address_aclr_family_b: vl_notype
);
port(
wren_a : in vl_logic;
wren_b : in vl_logic;
rden_a : in vl_logic;
rden_b : in vl_logic;
data_a : in vl_logic_vector;
data_b : in vl_logic_vector;
address_a : in vl_logic_vector;
address_b : in vl_logic_vector;
clock0 : in vl_logic;
clock1 : in vl_logic;
clocken0 : in vl_logic;
clocken1 : in vl_logic;
clocken2 : in vl_logic;
clocken3 : in vl_logic;
aclr0 : in vl_logic;
aclr1 : in vl_logic;
byteena_a : in vl_logic_vector;
byteena_b : in vl_logic_vector;
addressstall_a : in vl_logic;
addressstall_b : in vl_logic;
q_a : out vl_logic_vector;
q_b : out vl_logic_vector;
eccstatus : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width_a : constant is 1;
attribute mti_svvh_generic_type of widthad_a : constant is 1;
attribute mti_svvh_generic_type of numwords_a : constant is 1;
attribute mti_svvh_generic_type of outdata_reg_a : constant is 1;
attribute mti_svvh_generic_type of address_aclr_a : constant is 1;
attribute mti_svvh_generic_type of outdata_aclr_a : constant is 1;
attribute mti_svvh_generic_type of indata_aclr_a : constant is 1;
attribute mti_svvh_generic_type of wrcontrol_aclr_a : constant is 1;
attribute mti_svvh_generic_type of byteena_aclr_a : constant is 1;
attribute mti_svvh_generic_type of width_byteena_a : constant is 1;
attribute mti_svvh_generic_type of width_b : constant is 1;
attribute mti_svvh_generic_type of widthad_b : constant is 1;
attribute mti_svvh_generic_type of numwords_b : constant is 1;
attribute mti_svvh_generic_type of rdcontrol_reg_b : constant is 1;
attribute mti_svvh_generic_type of address_reg_b : constant is 1;
attribute mti_svvh_generic_type of outdata_reg_b : constant is 1;
attribute mti_svvh_generic_type of outdata_aclr_b : constant is 1;
attribute mti_svvh_generic_type of rdcontrol_aclr_b : constant is 1;
attribute mti_svvh_generic_type of indata_reg_b : constant is 1;
attribute mti_svvh_generic_type of byteena_reg_b : constant is 1;
attribute mti_svvh_generic_type of indata_aclr_b : constant is 1;
attribute mti_svvh_generic_type of wrcontrol_aclr_b : constant is 1;
attribute mti_svvh_generic_type of address_aclr_b : constant is 1;
attribute mti_svvh_generic_type of byteena_aclr_b : constant is 1;
attribute mti_svvh_generic_type of width_byteena_b : constant is 1;
attribute mti_svvh_generic_type of clock_enable_input_a : constant is 1;
attribute mti_svvh_generic_type of clock_enable_output_a : constant is 1;
attribute mti_svvh_generic_type of clock_enable_input_b : constant is 1;
attribute mti_svvh_generic_type of clock_enable_output_b : constant is 1;
attribute mti_svvh_generic_type of clock_enable_core_a : constant is 1;
attribute mti_svvh_generic_type of clock_enable_core_b : constant is 1;
attribute mti_svvh_generic_type of read_during_write_mode_port_a : constant is 1;
attribute mti_svvh_generic_type of read_during_write_mode_port_b : constant is 1;
attribute mti_svvh_generic_type of read_during_write_mode_mixed_ports : constant is 1;
attribute mti_svvh_generic_type of enable_ecc : constant is 1;
attribute mti_svvh_generic_type of width_eccstatus : constant is 1;
attribute mti_svvh_generic_type of ecc_pipeline_stage_enabled : constant is 1;
attribute mti_svvh_generic_type of operation_mode : constant is 1;
attribute mti_svvh_generic_type of byte_size : constant is 1;
attribute mti_svvh_generic_type of ram_block_type : constant is 1;
attribute mti_svvh_generic_type of init_file : constant is 1;
attribute mti_svvh_generic_type of init_file_layout : constant is 1;
attribute mti_svvh_generic_type of maximum_depth : constant is 1;
attribute mti_svvh_generic_type of intended_device_family : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of implement_in_les : constant is 1;
attribute mti_svvh_generic_type of power_up_uninitialized : constant is 1;
attribute mti_svvh_generic_type of sim_show_memory_data_in_port_b_layout : constant is 1;
attribute mti_svvh_generic_type of is_lutram : constant is 3;
attribute mti_svvh_generic_type of is_bidir_and_wrcontrol_addb_clk0 : constant is 3;
attribute mti_svvh_generic_type of is_bidir_and_wrcontrol_addb_clk1 : constant is 3;
attribute mti_svvh_generic_type of dual_port_addreg_b_clk0 : constant is 3;
attribute mti_svvh_generic_type of dual_port_addreg_b_clk1 : constant is 3;
attribute mti_svvh_generic_type of i_byte_size_tmp : constant is 3;
attribute mti_svvh_generic_type of i_lutram_read : constant is 3;
attribute mti_svvh_generic_type of enable_mem_data_b_reading : constant is 3;
attribute mti_svvh_generic_type of wrcontrol_wraddress_reg_b : constant is 3;
attribute mti_svvh_generic_type of is_write_on_positive_edge : constant is 1;
attribute mti_svvh_generic_type of lutram_single_port_fast_read : constant is 3;
attribute mti_svvh_generic_type of lutram_dual_port_fast_read : constant is 3;
attribute mti_svvh_generic_type of s3_address_aclr_a : constant is 3;
attribute mti_svvh_generic_type of s3_address_aclr_b : constant is 3;
attribute mti_svvh_generic_type of i_address_aclr_family_a : constant is 3;
attribute mti_svvh_generic_type of i_address_aclr_family_b : constant is 3;
end altera_syncram;
|
mit
|
e059d6b75cdcd6abf7eab7a5700b7cd7
| 0.630525 | 3.47793 | false | false | false | false |
dominiklohmann/mikrorechner
|
vhdl/procSim.vhd
| 1 | 2,476 |
-- procSim.vhd
--
-- entity procSim -testbench for pipeline processor
-- architecture tb_noIO -
------------------------------------------------------------------------------
library ieee; -- packages:
use ieee.std_logic_1164.all; -- std_logic
use ieee.numeric_std.all; -- (un)signed
use work.sramPkg.all; -- sram
use work.procPkg.all; -- pipeProc
-- entity --------------------------------------------------------------
------------------------------------------------------------------------------
entity procSim is
generic(clkPeriod : time := 20 ns; -- clock period
clkCycles : positive := 200); -- clock cycles
end entity procSim;
-- architecture --------------------------------------------------------------
------------------------------------------------------------------------------
architecture tb_noIO of procSim is
signal clk, nRst : std_logic;
signal const0, const1 : std_logic;
signal dnWE, dnOE : std_logic;
signal iAddr, dAddr : std_logic_vector(31 downto 0);
signal iData, dData : std_logic_vector(31 downto 0);
signal iCtrl, dCtrl : fileIOty;
begin
const0 <= '0';
const1 <= '1';
-- memories ------------------------------------------------------
instMemI: sram generic map ( addrWd => 16,
dataWd => 32,
fileID => "instMem.dat")
port map ( nCS => const0,
nWE => const1,
nOE => const0,
addr => iAddr(7 downto 0),
data => iData,
fileIO => iCtrl);
dataMemI: sram generic map ( addrWd => 16,
dataWd => 32,
fileID => "dataMem.dat")
port map ( nCS => const0,
nWE => dnWE,
nOE => dnOE,
addr => dAddr(7 downto 0),
data => dData,
fileIO => dCtrl);
-- pipe processor ------------------------------------------------------
procIdeaI: procIdea port map ( clk => clk,
nRst => nRst,
iAddr => iAddr,
iData => iData,
dnWE => dnWE,
dnOE => dnOE,
dAddr => dAddr,
dData => dData);
-- stimuli ------------------------------------------------------
stiP: process is
begin
clk <= '0';
nRst <= '0', '1' after 5 ns;
iCtrl <= load, none after 5 ns;
dCtrl <= load, none after 5 ns;
wait for clkPeriod/2;
for n in 1 to clkCycles loop
clk <= '0', '1' after clkPeriod/2;
wait for clkPeriod;
end loop;
wait;
end process stiP;
end architecture tb_noIO;
------------------------------------------------------------------------------
-- procSim.vhd - end
|
mit
|
809ffd387e0d7586c0e29262e367af2b
| 0.447092 | 3.63583 | false | false | false | false |
michaelmiehling/A25_VME_TB
|
16x004-01_src/Source/utils_pkg.vhd
| 2 | 6,951 |
-------------------------------------------------------------------------------
-- Title : utilitiy package for 16z091-00 PCIe test bench
-- Project : 16z091-00
-------------------------------------------------------------------------------
-- File : utils_pkg.vhd
-- Author : [email protected]
-- Organization: MEN Mikro Elektronik GmbH
-- Created : 2012-08-22
-------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6 Revision 2010.01
-- Synthesis :
-------------------------------------------------------------------------------
-- Description :
-- Contains useful procedures
-------------------------------------------------------------------------------
-- Hierarchy :
--
-------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
package utils_pkg is
procedure write_label(
constant use_time : in string;
constant string_in : in string;
integer_in : in integer
);
procedure wait_clk(
signal clk : in std_logic;
constant clk_cnt : in integer
);
procedure write_s_slvec(
string_in : in string;
slvec_in : in std_logic_vector
);
end utils_pkg;
package body utils_pkg is
-----------------------------------------------------------------------------------------------------------------------------------------
-- write_label:
-- This procedure prints out a box to the transcript which is formated according to the length of the input string.
-- use_time : provide time resolution or "none" if no time shall be printed
-- string_in : input string that will be printed to the box
-- integer_in : integer value that will be printed to the box, omitted if set to 0
-----------------------------------------------------------------------------------------------------------------------------------------
procedure write_label(
constant use_time : in string;
constant string_in : in string;
integer_in : in integer
) is
variable wrLine : line;
variable cnt : integer := 0;
constant LABEL_C : string := "-";
constant LABEL_STR : string := "--";
constant LABEL_STR1 : string := "---";
constant CORNER_C : string := "+";
constant HEADER_C : string := "=";
constant LINE_LEN : integer := 105;
constant T_WIDTH : integer := 15;
begin
write(wrLine, CORNER_C);
for i in string_in'range loop
write(wrLine, LABEL_C);
end loop;
if integer_in >= 0 then
for i in 0 to 9 loop
if (integer_in / (10**i)) /= 0 then cnt := i; end if;
end loop;
for j in 0 to cnt loop
write(wrLine, label_c);
end loop;
write(wrLine, LABEL_STR1);
else
write(wrLine, LABEL_STR);
end if;
if use_time /= "none" then
for i in 0 to T_WIDTH loop
write(wrLine, LABEL_C);
end loop;
end if;
write(wrLine, CORNER_C);
writeline(output,wrLine);
write(wrLine, string'("| "));
if use_time /= "none" then
if use_time = "fs" then
write(wrLine,now, justified=>right,field =>T_WIDTH, unit=> fs );
elsif use_time = "ps" then
write(wrLine,now, justified=>right,field =>T_WIDTH, unit=> ps );
elsif use_time = "us" then
write(wrLine,now, justified=>right,field =>T_WIDTH, unit=> us );
elsif use_time = "ms" then
write(wrLine,now, justified=>right,field =>T_WIDTH, unit=> ms );
else
write(wrLine,now, justified=>right,field =>T_WIDTH, unit=> ns );
end if;
write(wrLine, string'(" "));
end if;
write(wrLine, string_in);
if integer_in >= 0 then
write(wrLine, string'(" "));
write(wrLine, integer_in);
end if;
write(wrLine, string'(" |"));
writeline(output,wrLine);
write(wrLine, CORNER_C);
for i in string_in'range loop
write(wrLine, LABEL_C);
end loop;
if integer_in >= 0 then
for i in 0 to 9 loop
if (integer_in / (10**i)) /= 0 then cnt := i; end if;
end loop;
for j in 0 to cnt loop
write(wrLine, label_c);
end loop;
write(wrLine, LABEL_STR1);
else
write(wrLine, LABEL_STR);
end if;
if use_time /= "none" then
for i in 0 to T_WIDTH loop
write(wrLine, LABEL_C);
end loop;
end if;
write(wrLine, CORNER_C);
writeline(output,wrLine);
end procedure write_label;
-----------------------------------------------------------------------------------------------------------------------------------------
-- wait_clk:
-- This procedure waits for the given amount of input clock cycles.
-----------------------------------------------------------------------------------------------------------------------------------------
procedure wait_clk(
signal clk : in std_logic;
constant clk_cnt : in integer
) is
begin
for i in 1 to clk_cnt loop
wait until rising_edge(clk);
end loop;
end procedure wait_clk;
-----------------------------------------------------------------------------------------------------------------------------------------
-- write_s_slvec:
-- This procedure prints std_logic_vector values in a way that collisions (e.g. 'X' or 'U') can be detected.
-----------------------------------------------------------------------------------------------------------------------------------------
procedure write_s_slvec(
string_in : in string;
slvec_in : in std_logic_vector
) is
variable l : line;
begin
write(l,string_in);
write(l, std_ulogic_vector(slvec_in), justified => right, field => 10);
writeline(output,l);
end procedure write_s_slvec;
end;
|
gpl-3.0
|
b7fc15382703833596c9f12acc763420
| 0.468134 | 4.655727 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/altera_lnsim/ama_multiplier_function/_primary.vhd
| 5 | 3,682 |
library verilog;
use verilog.vl_types.all;
entity ama_multiplier_function is
generic(
width_data_in_a : integer := 1;
width_data_in_b : integer := 1;
width_data_out : integer := 1;
number_of_multipliers: integer := 1;
multiplier_input_representation_a: string := "UNSIGNED";
multiplier_input_representation_b: string := "UNSIGNED";
multiplier_register0: string := "UNREGISTERED";
multiplier_register1: string := "UNREGISTERED";
multiplier_register2: string := "UNREGISTERED";
multiplier_register3: string := "UNREGISTERED";
multiplier_aclr0: string := "NONE";
multiplier_aclr1: string := "NONE";
multiplier_aclr2: string := "NONE";
multiplier_aclr3: string := "NONE";
width_data_in_a_msb: vl_notype;
width_data_in_b_msb: vl_notype;
width_data_out_msb: vl_notype;
width_mult_input_a: vl_notype;
width_mult_input_a_msb: vl_notype;
width_mult_input_b: vl_notype;
width_mult_input_b_msb: vl_notype;
width_mult_output: vl_notype
);
port(
clock : in vl_logic_vector(3 downto 0);
aclr : in vl_logic_vector(3 downto 0);
ena : in vl_logic_vector(3 downto 0);
data_in_a0 : in vl_logic_vector;
data_in_a1 : in vl_logic_vector;
data_in_a2 : in vl_logic_vector;
data_in_a3 : in vl_logic_vector;
data_in_b0 : in vl_logic_vector;
data_in_b1 : in vl_logic_vector;
data_in_b2 : in vl_logic_vector;
data_in_b3 : in vl_logic_vector;
data_out_0 : out vl_logic_vector;
data_out_1 : out vl_logic_vector;
data_out_2 : out vl_logic_vector;
data_out_3 : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width_data_in_a : constant is 1;
attribute mti_svvh_generic_type of width_data_in_b : constant is 1;
attribute mti_svvh_generic_type of width_data_out : constant is 1;
attribute mti_svvh_generic_type of number_of_multipliers : constant is 1;
attribute mti_svvh_generic_type of multiplier_input_representation_a : constant is 1;
attribute mti_svvh_generic_type of multiplier_input_representation_b : constant is 1;
attribute mti_svvh_generic_type of multiplier_register0 : constant is 1;
attribute mti_svvh_generic_type of multiplier_register1 : constant is 1;
attribute mti_svvh_generic_type of multiplier_register2 : constant is 1;
attribute mti_svvh_generic_type of multiplier_register3 : constant is 1;
attribute mti_svvh_generic_type of multiplier_aclr0 : constant is 1;
attribute mti_svvh_generic_type of multiplier_aclr1 : constant is 1;
attribute mti_svvh_generic_type of multiplier_aclr2 : constant is 1;
attribute mti_svvh_generic_type of multiplier_aclr3 : constant is 1;
attribute mti_svvh_generic_type of width_data_in_a_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_in_b_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_out_msb : constant is 3;
attribute mti_svvh_generic_type of width_mult_input_a : constant is 3;
attribute mti_svvh_generic_type of width_mult_input_a_msb : constant is 3;
attribute mti_svvh_generic_type of width_mult_input_b : constant is 3;
attribute mti_svvh_generic_type of width_mult_input_b_msb : constant is 3;
attribute mti_svvh_generic_type of width_mult_output : constant is 3;
end ama_multiplier_function;
|
mit
|
88ab113af01b90d98be41e4d8d8702bb
| 0.641771 | 3.523445 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/altera_lnsim/altera_arriav_pll/_primary.vhd
| 5 | 70,296 |
library verilog;
use verilog.vl_types.all;
entity altera_arriav_pll is
generic(
number_of_counters: integer := 18;
number_of_fplls : integer := 1;
number_of_extclks: integer := 4;
number_of_dlls : integer := 2;
number_of_lvds : integer := 4;
pll_auto_clk_sw_en_0: string := "false";
pll_clk_loss_edge_0: string := "both_edges";
pll_clk_loss_sw_en_0: string := "false";
pll_clk_sw_dly_0: integer := 0;
pll_clkin_0_src_0: string := "clk_0";
pll_clkin_1_src_0: string := "clk_0";
pll_manu_clk_sw_en_0: string := "false";
pll_sw_refclk_src_0: string := "clk_0";
pll_auto_clk_sw_en_1: string := "false";
pll_clk_loss_edge_1: string := "both_edges";
pll_clk_loss_sw_en_1: string := "false";
pll_clk_sw_dly_1: integer := 0;
pll_clkin_0_src_1: string := "clk_1";
pll_clkin_1_src_1: string := "clk_1";
pll_manu_clk_sw_en_1: string := "false";
pll_sw_refclk_src_1: string := "clk_1";
pll_output_clock_frequency_0: string := "700.0 MHz";
reference_clock_frequency_0: string := "700.0 MHz";
mimic_fbclk_type_0: string := "gclk";
dsm_accumulator_reset_value_0: integer := 0;
forcelock_0 : string := "false";
nreset_invert_0 : string := "false";
pll_atb_0 : integer := 0;
pll_bwctrl_0 : integer := 1000;
pll_cmp_buf_dly_0: string := "0 ps";
pll_cp_comp_0 : string := "true";
pll_cp_current_0: integer := 20;
pll_ctrl_override_setting_0: string := "true";
pll_dsm_dither_0: string := "disable";
pll_dsm_out_sel_0: string := "disable";
pll_dsm_reset_0 : string := "false";
pll_ecn_bypass_0: string := "false";
pll_ecn_test_en_0: string := "false";
pll_enable_0 : string := "true";
pll_fbclk_mux_1_0: string := "fb";
pll_fbclk_mux_2_0: string := "m_cnt";
pll_fractional_carry_out_0: integer := 24;
pll_fractional_division_0: integer := 1;
pll_fractional_value_ready_0: string := "true";
pll_lf_testen_0 : string := "false";
pll_lock_fltr_cfg_0: integer := 25;
pll_lock_fltr_test_0: string := "false";
pll_m_cnt_bypass_en_0: string := "false";
pll_m_cnt_coarse_dly_0: string := "0 ps";
pll_m_cnt_fine_dly_0: string := "0 ps";
pll_m_cnt_hi_div_0: integer := 3;
pll_m_cnt_in_src_0: string := "ph_mux_clk";
pll_m_cnt_lo_div_0: integer := 3;
pll_m_cnt_odd_div_duty_en_0: string := "false";
pll_m_cnt_ph_mux_prst_0: integer := 0;
pll_m_cnt_prst_0: integer := 256;
pll_n_cnt_bypass_en_0: string := "true";
pll_n_cnt_coarse_dly_0: string := "0 ps";
pll_n_cnt_fine_dly_0: string := "0 ps";
pll_n_cnt_hi_div_0: integer := 1;
pll_n_cnt_lo_div_0: integer := 1;
pll_n_cnt_odd_div_duty_en_0: string := "false";
pll_ref_buf_dly_0: string := "0 ps";
pll_reg_boost_0 : integer := 0;
pll_regulator_bypass_0: string := "false";
pll_ripplecap_ctrl_0: integer := 0;
pll_slf_rst_0 : string := "false";
pll_tclk_mux_en_0: string := "false";
pll_tclk_sel_0 : string := "n_src";
pll_test_enable_0: string := "false";
pll_testdn_enable_0: string := "false";
pll_testup_enable_0: string := "false";
pll_unlock_fltr_cfg_0: integer := 1;
pll_vco_div_0 : integer := 0;
pll_vco_ph0_en_0: string := "true";
pll_vco_ph1_en_0: string := "true";
pll_vco_ph2_en_0: string := "true";
pll_vco_ph3_en_0: string := "true";
pll_vco_ph4_en_0: string := "true";
pll_vco_ph5_en_0: string := "true";
pll_vco_ph6_en_0: string := "true";
pll_vco_ph7_en_0: string := "true";
pll_vctrl_test_voltage_0: integer := 750;
vccd0g_atb_0 : string := "disable";
vccd0g_output_0 : integer := 0;
vccd1g_atb_0 : string := "disable";
vccd1g_output_0 : integer := 0;
vccm1g_tap_0 : integer := 2;
vccr_pd_0 : string := "false";
vcodiv_override_0: string := "false";
sim_use_fast_model_0: string := "false";
pll_output_clock_frequency_1: string := "300.0 MHz";
reference_clock_frequency_1: string := "100.0 MHz";
mimic_fbclk_type_1: string := "gclk";
dsm_accumulator_reset_value_1: integer := 0;
forcelock_1 : string := "false";
nreset_invert_1 : string := "false";
pll_atb_1 : integer := 0;
pll_bwctrl_1 : integer := 1000;
pll_cmp_buf_dly_1: string := "0 ps";
pll_cp_comp_1 : string := "true";
pll_cp_current_1: integer := 30;
pll_ctrl_override_setting_1: string := "false";
pll_dsm_dither_1: string := "disable";
pll_dsm_out_sel_1: string := "disable";
pll_dsm_reset_1 : string := "false";
pll_ecn_bypass_1: string := "false";
pll_ecn_test_en_1: string := "false";
pll_enable_1 : string := "false";
pll_fbclk_mux_1_1: string := "glb";
pll_fbclk_mux_2_1: string := "fb_1";
pll_fractional_carry_out_1: integer := 24;
pll_fractional_division_1: integer := 1;
pll_fractional_value_ready_1: string := "true";
pll_lf_testen_1 : string := "false";
pll_lock_fltr_cfg_1: integer := 25;
pll_lock_fltr_test_1: string := "false";
pll_m_cnt_bypass_en_1: string := "false";
pll_m_cnt_coarse_dly_1: string := "0 ps";
pll_m_cnt_fine_dly_1: string := "0 ps";
pll_m_cnt_hi_div_1: integer := 2;
pll_m_cnt_in_src_1: string := "ph_mux_clk";
pll_m_cnt_lo_div_1: integer := 1;
pll_m_cnt_odd_div_duty_en_1: string := "true";
pll_m_cnt_ph_mux_prst_1: integer := 0;
pll_m_cnt_prst_1: integer := 256;
pll_n_cnt_bypass_en_1: string := "true";
pll_n_cnt_coarse_dly_1: string := "0 ps";
pll_n_cnt_fine_dly_1: string := "0 ps";
pll_n_cnt_hi_div_1: integer := 256;
pll_n_cnt_lo_div_1: integer := 256;
pll_n_cnt_odd_div_duty_en_1: string := "false";
pll_ref_buf_dly_1: string := "0 ps";
pll_reg_boost_1 : integer := 0;
pll_regulator_bypass_1: string := "false";
pll_ripplecap_ctrl_1: integer := 0;
pll_slf_rst_1 : string := "false";
pll_tclk_mux_en_1: string := "false";
pll_tclk_sel_1 : string := "n_src";
pll_test_enable_1: string := "false";
pll_testdn_enable_1: string := "false";
pll_testup_enable_1: string := "false";
pll_unlock_fltr_cfg_1: integer := 2;
pll_vco_div_1 : integer := 1;
pll_vco_ph0_en_1: string := "true";
pll_vco_ph1_en_1: string := "true";
pll_vco_ph2_en_1: string := "true";
pll_vco_ph3_en_1: string := "true";
pll_vco_ph4_en_1: string := "true";
pll_vco_ph5_en_1: string := "true";
pll_vco_ph6_en_1: string := "true";
pll_vco_ph7_en_1: string := "true";
pll_vctrl_test_voltage_1: integer := 750;
vccd0g_atb_1 : string := "disable";
vccd0g_output_1 : integer := 0;
vccd1g_atb_1 : string := "disable";
vccd1g_output_1 : integer := 0;
vccm1g_tap_1 : integer := 2;
vccr_pd_1 : string := "false";
vcodiv_override_1: string := "false";
sim_use_fast_model_1: string := "false";
output_clock_frequency_0: string := "100.0 MHz";
enable_output_counter_0: string := "true";
phase_shift_0 : string := "0 ps";
duty_cycle_0 : integer := 50;
c_cnt_coarse_dly_0: string := "0 ps";
c_cnt_fine_dly_0: string := "0 ps";
c_cnt_in_src_0 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_0: integer := 0;
c_cnt_prst_0 : integer := 1;
cnt_fpll_src_0 : string := "fpll_0";
dprio0_cnt_bypass_en_0: string := "true";
dprio0_cnt_hi_div_0: integer := 3;
dprio0_cnt_lo_div_0: integer := 3;
dprio0_cnt_odd_div_even_duty_en_0: string := "false";
dprio1_cnt_bypass_en_0: vl_notype;
dprio1_cnt_hi_div_0: vl_notype;
dprio1_cnt_lo_div_0: vl_notype;
dprio1_cnt_odd_div_even_duty_en_0: vl_notype;
output_clock_frequency_1: string := "0 ps";
enable_output_counter_1: string := "true";
phase_shift_1 : string := "0 ps";
duty_cycle_1 : integer := 50;
c_cnt_coarse_dly_1: string := "0 ps";
c_cnt_fine_dly_1: string := "0 ps";
c_cnt_in_src_1 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_1: integer := 0;
c_cnt_prst_1 : integer := 1;
cnt_fpll_src_1 : string := "fpll_0";
dprio0_cnt_bypass_en_1: string := "true";
dprio0_cnt_hi_div_1: integer := 2;
dprio0_cnt_lo_div_1: integer := 1;
dprio0_cnt_odd_div_even_duty_en_1: string := "true";
dprio1_cnt_bypass_en_1: vl_notype;
dprio1_cnt_hi_div_1: vl_notype;
dprio1_cnt_lo_div_1: vl_notype;
dprio1_cnt_odd_div_even_duty_en_1: vl_notype;
output_clock_frequency_2: string := "0 ps";
enable_output_counter_2: string := "true";
phase_shift_2 : string := "0 ps";
duty_cycle_2 : integer := 50;
c_cnt_coarse_dly_2: string := "0 ps";
c_cnt_fine_dly_2: string := "0 ps";
c_cnt_in_src_2 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_2: integer := 0;
c_cnt_prst_2 : integer := 1;
cnt_fpll_src_2 : string := "fpll_0";
dprio0_cnt_bypass_en_2: string := "true";
dprio0_cnt_hi_div_2: integer := 1;
dprio0_cnt_lo_div_2: integer := 1;
dprio0_cnt_odd_div_even_duty_en_2: string := "false";
dprio1_cnt_bypass_en_2: vl_notype;
dprio1_cnt_hi_div_2: vl_notype;
dprio1_cnt_lo_div_2: vl_notype;
dprio1_cnt_odd_div_even_duty_en_2: vl_notype;
output_clock_frequency_3: string := "0 ps";
enable_output_counter_3: string := "true";
phase_shift_3 : string := "0 ps";
duty_cycle_3 : integer := 50;
c_cnt_coarse_dly_3: string := "0 ps";
c_cnt_fine_dly_3: string := "0 ps";
c_cnt_in_src_3 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_3: integer := 0;
c_cnt_prst_3 : integer := 1;
cnt_fpll_src_3 : string := "fpll_0";
dprio0_cnt_bypass_en_3: string := "false";
dprio0_cnt_hi_div_3: integer := 1;
dprio0_cnt_lo_div_3: integer := 1;
dprio0_cnt_odd_div_even_duty_en_3: string := "false";
dprio1_cnt_bypass_en_3: vl_notype;
dprio1_cnt_hi_div_3: vl_notype;
dprio1_cnt_lo_div_3: vl_notype;
dprio1_cnt_odd_div_even_duty_en_3: vl_notype;
output_clock_frequency_4: string := "0 ps";
enable_output_counter_4: string := "true";
phase_shift_4 : string := "0 ps";
duty_cycle_4 : integer := 50;
c_cnt_coarse_dly_4: string := "0 ps";
c_cnt_fine_dly_4: string := "0 ps";
c_cnt_in_src_4 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_4: integer := 0;
c_cnt_prst_4 : integer := 1;
cnt_fpll_src_4 : string := "fpll_0";
dprio0_cnt_bypass_en_4: string := "false";
dprio0_cnt_hi_div_4: integer := 1;
dprio0_cnt_lo_div_4: integer := 1;
dprio0_cnt_odd_div_even_duty_en_4: string := "false";
dprio1_cnt_bypass_en_4: vl_notype;
dprio1_cnt_hi_div_4: vl_notype;
dprio1_cnt_lo_div_4: vl_notype;
dprio1_cnt_odd_div_even_duty_en_4: vl_notype;
output_clock_frequency_5: string := "0 ps";
enable_output_counter_5: string := "true";
phase_shift_5 : string := "0 ps";
duty_cycle_5 : integer := 50;
c_cnt_coarse_dly_5: string := "0 ps";
c_cnt_fine_dly_5: string := "0 ps";
c_cnt_in_src_5 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_5: integer := 0;
c_cnt_prst_5 : integer := 1;
cnt_fpll_src_5 : string := "fpll_0";
dprio0_cnt_bypass_en_5: string := "false";
dprio0_cnt_hi_div_5: integer := 1;
dprio0_cnt_lo_div_5: integer := 1;
dprio0_cnt_odd_div_even_duty_en_5: string := "false";
dprio1_cnt_bypass_en_5: vl_notype;
dprio1_cnt_hi_div_5: vl_notype;
dprio1_cnt_lo_div_5: vl_notype;
dprio1_cnt_odd_div_even_duty_en_5: vl_notype;
output_clock_frequency_6: string := "0 ps";
enable_output_counter_6: string := "true";
phase_shift_6 : string := "0 ps";
duty_cycle_6 : integer := 50;
c_cnt_coarse_dly_6: string := "0 ps";
c_cnt_fine_dly_6: string := "0 ps";
c_cnt_in_src_6 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_6: integer := 0;
c_cnt_prst_6 : integer := 1;
cnt_fpll_src_6 : string := "fpll_0";
dprio0_cnt_bypass_en_6: string := "false";
dprio0_cnt_hi_div_6: integer := 1;
dprio0_cnt_lo_div_6: integer := 1;
dprio0_cnt_odd_div_even_duty_en_6: string := "false";
dprio1_cnt_bypass_en_6: vl_notype;
dprio1_cnt_hi_div_6: vl_notype;
dprio1_cnt_lo_div_6: vl_notype;
dprio1_cnt_odd_div_even_duty_en_6: vl_notype;
output_clock_frequency_7: string := "0 ps";
enable_output_counter_7: string := "true";
phase_shift_7 : string := "0 ps";
duty_cycle_7 : integer := 50;
c_cnt_coarse_dly_7: string := "0 ps";
c_cnt_fine_dly_7: string := "0 ps";
c_cnt_in_src_7 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_7: integer := 0;
c_cnt_prst_7 : integer := 1;
cnt_fpll_src_7 : string := "fpll_0";
dprio0_cnt_bypass_en_7: string := "false";
dprio0_cnt_hi_div_7: integer := 1;
dprio0_cnt_lo_div_7: integer := 1;
dprio0_cnt_odd_div_even_duty_en_7: string := "false";
dprio1_cnt_bypass_en_7: vl_notype;
dprio1_cnt_hi_div_7: vl_notype;
dprio1_cnt_lo_div_7: vl_notype;
dprio1_cnt_odd_div_even_duty_en_7: vl_notype;
output_clock_frequency_8: string := "0 ps";
enable_output_counter_8: string := "true";
phase_shift_8 : string := "0 ps";
duty_cycle_8 : integer := 50;
c_cnt_coarse_dly_8: string := "0 ps";
c_cnt_fine_dly_8: string := "0 ps";
c_cnt_in_src_8 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_8: integer := 0;
c_cnt_prst_8 : integer := 1;
cnt_fpll_src_8 : string := "fpll_0";
dprio0_cnt_bypass_en_8: string := "false";
dprio0_cnt_hi_div_8: integer := 1;
dprio0_cnt_lo_div_8: integer := 1;
dprio0_cnt_odd_div_even_duty_en_8: string := "false";
dprio1_cnt_bypass_en_8: vl_notype;
dprio1_cnt_hi_div_8: vl_notype;
dprio1_cnt_lo_div_8: vl_notype;
dprio1_cnt_odd_div_even_duty_en_8: vl_notype;
output_clock_frequency_9: string := "0 ps";
enable_output_counter_9: string := "true";
phase_shift_9 : string := "0 ps";
duty_cycle_9 : integer := 50;
c_cnt_coarse_dly_9: string := "0 ps";
c_cnt_fine_dly_9: string := "0 ps";
c_cnt_in_src_9 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_9: integer := 0;
c_cnt_prst_9 : integer := 1;
cnt_fpll_src_9 : string := "fpll_0";
dprio0_cnt_bypass_en_9: string := "false";
dprio0_cnt_hi_div_9: integer := 1;
dprio0_cnt_lo_div_9: integer := 1;
dprio0_cnt_odd_div_even_duty_en_9: string := "false";
dprio1_cnt_bypass_en_9: vl_notype;
dprio1_cnt_hi_div_9: vl_notype;
dprio1_cnt_lo_div_9: vl_notype;
dprio1_cnt_odd_div_even_duty_en_9: vl_notype;
output_clock_frequency_10: string := "0 ps";
enable_output_counter_10: string := "true";
phase_shift_10 : string := "0 ps";
duty_cycle_10 : integer := 50;
c_cnt_coarse_dly_10: string := "0 ps";
c_cnt_fine_dly_10: string := "0 ps";
c_cnt_in_src_10 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_10: integer := 0;
c_cnt_prst_10 : integer := 1;
cnt_fpll_src_10 : string := "fpll_0";
dprio0_cnt_bypass_en_10: string := "false";
dprio0_cnt_hi_div_10: integer := 1;
dprio0_cnt_lo_div_10: integer := 1;
dprio0_cnt_odd_div_even_duty_en_10: string := "false";
dprio1_cnt_bypass_en_10: vl_notype;
dprio1_cnt_hi_div_10: vl_notype;
dprio1_cnt_lo_div_10: vl_notype;
dprio1_cnt_odd_div_even_duty_en_10: vl_notype;
output_clock_frequency_11: string := "0 ps";
enable_output_counter_11: string := "true";
phase_shift_11 : string := "0 ps";
duty_cycle_11 : integer := 50;
c_cnt_coarse_dly_11: string := "0 ps";
c_cnt_fine_dly_11: string := "0 ps";
c_cnt_in_src_11 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_11: integer := 0;
c_cnt_prst_11 : integer := 1;
cnt_fpll_src_11 : string := "fpll_0";
dprio0_cnt_bypass_en_11: string := "false";
dprio0_cnt_hi_div_11: integer := 1;
dprio0_cnt_lo_div_11: integer := 1;
dprio0_cnt_odd_div_even_duty_en_11: string := "false";
dprio1_cnt_bypass_en_11: vl_notype;
dprio1_cnt_hi_div_11: vl_notype;
dprio1_cnt_lo_div_11: vl_notype;
dprio1_cnt_odd_div_even_duty_en_11: vl_notype;
output_clock_frequency_12: string := "0 ps";
enable_output_counter_12: string := "true";
phase_shift_12 : string := "0 ps";
duty_cycle_12 : integer := 50;
c_cnt_coarse_dly_12: string := "0 ps";
c_cnt_fine_dly_12: string := "0 ps";
c_cnt_in_src_12 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_12: integer := 0;
c_cnt_prst_12 : integer := 1;
cnt_fpll_src_12 : string := "fpll_0";
dprio0_cnt_bypass_en_12: string := "false";
dprio0_cnt_hi_div_12: integer := 1;
dprio0_cnt_lo_div_12: integer := 1;
dprio0_cnt_odd_div_even_duty_en_12: string := "false";
dprio1_cnt_bypass_en_12: vl_notype;
dprio1_cnt_hi_div_12: vl_notype;
dprio1_cnt_lo_div_12: vl_notype;
dprio1_cnt_odd_div_even_duty_en_12: vl_notype;
output_clock_frequency_13: string := "0 ps";
enable_output_counter_13: string := "true";
phase_shift_13 : string := "0 ps";
duty_cycle_13 : integer := 50;
c_cnt_coarse_dly_13: string := "0 ps";
c_cnt_fine_dly_13: string := "0 ps";
c_cnt_in_src_13 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_13: integer := 0;
c_cnt_prst_13 : integer := 1;
cnt_fpll_src_13 : string := "fpll_0";
dprio0_cnt_bypass_en_13: string := "false";
dprio0_cnt_hi_div_13: integer := 1;
dprio0_cnt_lo_div_13: integer := 1;
dprio0_cnt_odd_div_even_duty_en_13: string := "false";
dprio1_cnt_bypass_en_13: vl_notype;
dprio1_cnt_hi_div_13: vl_notype;
dprio1_cnt_lo_div_13: vl_notype;
dprio1_cnt_odd_div_even_duty_en_13: vl_notype;
output_clock_frequency_14: string := "0 ps";
enable_output_counter_14: string := "true";
phase_shift_14 : string := "0 ps";
duty_cycle_14 : integer := 50;
c_cnt_coarse_dly_14: string := "0 ps";
c_cnt_fine_dly_14: string := "0 ps";
c_cnt_in_src_14 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_14: integer := 0;
c_cnt_prst_14 : integer := 1;
cnt_fpll_src_14 : string := "fpll_0";
dprio0_cnt_bypass_en_14: string := "false";
dprio0_cnt_hi_div_14: integer := 1;
dprio0_cnt_lo_div_14: integer := 1;
dprio0_cnt_odd_div_even_duty_en_14: string := "false";
dprio1_cnt_bypass_en_14: vl_notype;
dprio1_cnt_hi_div_14: vl_notype;
dprio1_cnt_lo_div_14: vl_notype;
dprio1_cnt_odd_div_even_duty_en_14: vl_notype;
output_clock_frequency_15: string := "0 ps";
enable_output_counter_15: string := "true";
phase_shift_15 : string := "0 ps";
duty_cycle_15 : integer := 50;
c_cnt_coarse_dly_15: string := "0 ps";
c_cnt_fine_dly_15: string := "0 ps";
c_cnt_in_src_15 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_15: integer := 0;
c_cnt_prst_15 : integer := 1;
cnt_fpll_src_15 : string := "fpll_0";
dprio0_cnt_bypass_en_15: string := "false";
dprio0_cnt_hi_div_15: integer := 1;
dprio0_cnt_lo_div_15: integer := 1;
dprio0_cnt_odd_div_even_duty_en_15: string := "false";
dprio1_cnt_bypass_en_15: vl_notype;
dprio1_cnt_hi_div_15: vl_notype;
dprio1_cnt_lo_div_15: vl_notype;
dprio1_cnt_odd_div_even_duty_en_15: vl_notype;
output_clock_frequency_16: string := "0 ps";
enable_output_counter_16: string := "true";
phase_shift_16 : string := "0 ps";
duty_cycle_16 : integer := 50;
c_cnt_coarse_dly_16: string := "0 ps";
c_cnt_fine_dly_16: string := "0 ps";
c_cnt_in_src_16 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_16: integer := 0;
c_cnt_prst_16 : integer := 1;
cnt_fpll_src_16 : string := "fpll_0";
dprio0_cnt_bypass_en_16: string := "false";
dprio0_cnt_hi_div_16: integer := 1;
dprio0_cnt_lo_div_16: integer := 1;
dprio0_cnt_odd_div_even_duty_en_16: string := "false";
dprio1_cnt_bypass_en_16: vl_notype;
dprio1_cnt_hi_div_16: vl_notype;
dprio1_cnt_lo_div_16: vl_notype;
dprio1_cnt_odd_div_even_duty_en_16: vl_notype;
output_clock_frequency_17: string := "0 ps";
enable_output_counter_17: string := "true";
phase_shift_17 : string := "0 ps";
duty_cycle_17 : integer := 50;
c_cnt_coarse_dly_17: string := "0 ps";
c_cnt_fine_dly_17: string := "0 ps";
c_cnt_in_src_17 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_17: integer := 0;
c_cnt_prst_17 : integer := 1;
cnt_fpll_src_17 : string := "fpll_0";
dprio0_cnt_bypass_en_17: string := "false";
dprio0_cnt_hi_div_17: integer := 1;
dprio0_cnt_lo_div_17: integer := 1;
dprio0_cnt_odd_div_even_duty_en_17: string := "false";
dprio1_cnt_bypass_en_17: vl_notype;
dprio1_cnt_hi_div_17: vl_notype;
dprio1_cnt_lo_div_17: vl_notype;
dprio1_cnt_odd_div_even_duty_en_17: vl_notype;
dpa_output_clock_frequency_0: string := "0 ps";
pll_vcoph_div_0 : integer := 1;
dpa_output_clock_frequency_1: string := "0 ps";
pll_vcoph_div_1 : integer := 1;
enable_extclk_output_0: string := "false";
pll_extclk_cnt_src_0: string := "m0_cnt";
pll_extclk_enable_0: string := "true";
pll_extclk_invert_0: string := "false";
enable_extclk_output_1: string := "false";
pll_extclk_cnt_src_1: string := "vss";
pll_extclk_enable_1: string := "true";
pll_extclk_invert_1: string := "false";
enable_extclk_output_2: string := "false";
pll_extclk_cnt_src_2: string := "vss";
pll_extclk_enable_2: string := "true";
pll_extclk_invert_2: string := "false";
enable_extclk_output_3: string := "false";
pll_extclk_cnt_src_3: string := "vss";
pll_extclk_enable_3: string := "true";
pll_extclk_invert_3: string := "false";
enable_dll_output_0: string := "false";
pll_dll_src_value_0: string := "vss";
enable_dll_output_1: string := "false";
pll_dll_src_value_1: string := "vss";
enable_lvds_output_0: string := "false";
pll_loaden_coarse_dly_0: string := "0 ps";
pll_loaden_enable_disable_0: string := "true";
pll_loaden_fine_dly_0: string := "0 ps";
pll_lvdsclk_coarse_dly_0: string := "0 ps";
pll_lvdsclk_enable_disable_0: string := "true";
pll_lvdsclk_fine_dly_0: string := "0 ps";
enable_lvds_output_1: string := "false";
pll_loaden_coarse_dly_1: string := "0 ps";
pll_loaden_enable_disable_1: string := "true";
pll_loaden_fine_dly_1: string := "0 ps";
pll_lvdsclk_coarse_dly_1: string := "0 ps";
pll_lvdsclk_enable_disable_1: string := "true";
pll_lvdsclk_fine_dly_1: string := "0 ps";
enable_lvds_output_2: string := "false";
pll_loaden_coarse_dly_2: string := "0 ps";
pll_loaden_enable_disable_2: string := "true";
pll_loaden_fine_dly_2: string := "0 ps";
pll_lvdsclk_coarse_dly_2: string := "0 ps";
pll_lvdsclk_enable_disable_2: string := "true";
pll_lvdsclk_fine_dly_2: string := "0 ps";
enable_lvds_output_3: string := "false";
pll_loaden_coarse_dly_3: string := "0 ps";
pll_loaden_enable_disable_3: string := "true";
pll_loaden_fine_dly_3: string := "0 ps";
pll_lvdsclk_coarse_dly_3: string := "0 ps";
pll_lvdsclk_enable_disable_3: string := "true";
pll_lvdsclk_fine_dly_3: string := "0 ps"
);
port(
phout_0 : out vl_logic_vector(7 downto 0);
phout_1 : out vl_logic_vector(7 downto 0);
adjpllin : in vl_logic_vector;
cclk : in vl_logic_vector;
coreclkin : in vl_logic_vector;
extswitch : in vl_logic_vector;
iqtxrxclkin : in vl_logic_vector;
plliqclkin : in vl_logic_vector;
rxiqclkin : in vl_logic_vector;
clkin : in vl_logic_vector(3 downto 0);
refiqclk_0 : in vl_logic_vector(1 downto 0);
refiqclk_1 : in vl_logic_vector(1 downto 0);
clk0bad : out vl_logic_vector;
clk1bad : out vl_logic_vector;
pllclksel : out vl_logic_vector;
atpgmode : in vl_logic_vector;
clk : in vl_logic_vector;
fpllcsrtest : in vl_logic_vector;
iocsrclkin : in vl_logic_vector;
iocsrdatain : in vl_logic_vector;
iocsren : in vl_logic_vector;
iocsrrstn : in vl_logic_vector;
mdiodis : in vl_logic_vector;
phaseen : in vl_logic_vector;
read : in vl_logic_vector;
rstn : in vl_logic_vector;
scanen : in vl_logic_vector;
sershiftload : in vl_logic_vector;
shiftdonei : in vl_logic_vector;
updn : in vl_logic_vector;
write : in vl_logic_vector;
addr_0 : in vl_logic_vector(5 downto 0);
addr_1 : in vl_logic_vector(5 downto 0);
byteen_0 : in vl_logic_vector(1 downto 0);
byteen_1 : in vl_logic_vector(1 downto 0);
cntsel_0 : in vl_logic_vector(4 downto 0);
cntsel_1 : in vl_logic_vector(4 downto 0);
din_0 : in vl_logic_vector(15 downto 0);
din_1 : in vl_logic_vector(15 downto 0);
blockselect : out vl_logic_vector;
iocsrdataout : out vl_logic_vector;
iocsrenbuf : out vl_logic_vector;
iocsrrstnbuf : out vl_logic_vector;
phasedone : out vl_logic_vector;
dout_0 : out vl_logic_vector(15 downto 0);
dout_1 : out vl_logic_vector(15 downto 0);
dprioout_0 : out vl_logic_vector(815 downto 0);
dprioout_1 : out vl_logic_vector(815 downto 0);
fbclkfpll : in vl_logic_vector;
lvdfbin : in vl_logic_vector;
nresync : in vl_logic_vector;
pfden : in vl_logic_vector;
shiften_fpll : in vl_logic_vector;
zdb : in vl_logic_vector;
fblvdsout : out vl_logic_vector;
lock : out vl_logic_vector;
mcntout : out vl_logic_vector;
plniotribuf : out vl_logic_vector;
clken : in vl_logic_vector;
extclk : out vl_logic_vector;
dll_clkin : in vl_logic_vector;
clkout : out vl_logic_vector;
loaden : out vl_logic_vector;
lvdsclk : out vl_logic_vector;
divclk : out vl_logic_vector;
cascade_out : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of number_of_counters : constant is 1;
attribute mti_svvh_generic_type of number_of_fplls : constant is 1;
attribute mti_svvh_generic_type of number_of_extclks : constant is 1;
attribute mti_svvh_generic_type of number_of_dlls : constant is 1;
attribute mti_svvh_generic_type of number_of_lvds : constant is 1;
attribute mti_svvh_generic_type of pll_auto_clk_sw_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_loss_edge_0 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_loss_sw_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_sw_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_clkin_0_src_0 : constant is 1;
attribute mti_svvh_generic_type of pll_clkin_1_src_0 : constant is 1;
attribute mti_svvh_generic_type of pll_manu_clk_sw_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_sw_refclk_src_0 : constant is 1;
attribute mti_svvh_generic_type of pll_auto_clk_sw_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_loss_edge_1 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_loss_sw_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_sw_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_clkin_0_src_1 : constant is 1;
attribute mti_svvh_generic_type of pll_clkin_1_src_1 : constant is 1;
attribute mti_svvh_generic_type of pll_manu_clk_sw_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_sw_refclk_src_1 : constant is 1;
attribute mti_svvh_generic_type of pll_output_clock_frequency_0 : constant is 1;
attribute mti_svvh_generic_type of reference_clock_frequency_0 : constant is 1;
attribute mti_svvh_generic_type of mimic_fbclk_type_0 : constant is 1;
attribute mti_svvh_generic_type of dsm_accumulator_reset_value_0 : constant is 1;
attribute mti_svvh_generic_type of forcelock_0 : constant is 1;
attribute mti_svvh_generic_type of nreset_invert_0 : constant is 1;
attribute mti_svvh_generic_type of pll_atb_0 : constant is 1;
attribute mti_svvh_generic_type of pll_bwctrl_0 : constant is 1;
attribute mti_svvh_generic_type of pll_cmp_buf_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_cp_comp_0 : constant is 1;
attribute mti_svvh_generic_type of pll_cp_current_0 : constant is 1;
attribute mti_svvh_generic_type of pll_ctrl_override_setting_0 : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_dither_0 : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_out_sel_0 : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_reset_0 : constant is 1;
attribute mti_svvh_generic_type of pll_ecn_bypass_0 : constant is 1;
attribute mti_svvh_generic_type of pll_ecn_test_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_enable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_fbclk_mux_1_0 : constant is 1;
attribute mti_svvh_generic_type of pll_fbclk_mux_2_0 : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_carry_out_0 : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_division_0 : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_value_ready_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lf_testen_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lock_fltr_cfg_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lock_fltr_test_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_bypass_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_coarse_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_fine_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_hi_div_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_in_src_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_lo_div_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_odd_div_duty_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_ph_mux_prst_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_prst_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_bypass_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_coarse_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_fine_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_hi_div_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_lo_div_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_odd_div_duty_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_ref_buf_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_reg_boost_0 : constant is 1;
attribute mti_svvh_generic_type of pll_regulator_bypass_0 : constant is 1;
attribute mti_svvh_generic_type of pll_ripplecap_ctrl_0 : constant is 1;
attribute mti_svvh_generic_type of pll_slf_rst_0 : constant is 1;
attribute mti_svvh_generic_type of pll_tclk_mux_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_tclk_sel_0 : constant is 1;
attribute mti_svvh_generic_type of pll_test_enable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_testdn_enable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_testup_enable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_unlock_fltr_cfg_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_div_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph0_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph1_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph2_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph3_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph4_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph5_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph6_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph7_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vctrl_test_voltage_0 : constant is 1;
attribute mti_svvh_generic_type of vccd0g_atb_0 : constant is 1;
attribute mti_svvh_generic_type of vccd0g_output_0 : constant is 1;
attribute mti_svvh_generic_type of vccd1g_atb_0 : constant is 1;
attribute mti_svvh_generic_type of vccd1g_output_0 : constant is 1;
attribute mti_svvh_generic_type of vccm1g_tap_0 : constant is 1;
attribute mti_svvh_generic_type of vccr_pd_0 : constant is 1;
attribute mti_svvh_generic_type of vcodiv_override_0 : constant is 1;
attribute mti_svvh_generic_type of sim_use_fast_model_0 : constant is 1;
attribute mti_svvh_generic_type of pll_output_clock_frequency_1 : constant is 1;
attribute mti_svvh_generic_type of reference_clock_frequency_1 : constant is 1;
attribute mti_svvh_generic_type of mimic_fbclk_type_1 : constant is 1;
attribute mti_svvh_generic_type of dsm_accumulator_reset_value_1 : constant is 1;
attribute mti_svvh_generic_type of forcelock_1 : constant is 1;
attribute mti_svvh_generic_type of nreset_invert_1 : constant is 1;
attribute mti_svvh_generic_type of pll_atb_1 : constant is 1;
attribute mti_svvh_generic_type of pll_bwctrl_1 : constant is 1;
attribute mti_svvh_generic_type of pll_cmp_buf_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_cp_comp_1 : constant is 1;
attribute mti_svvh_generic_type of pll_cp_current_1 : constant is 1;
attribute mti_svvh_generic_type of pll_ctrl_override_setting_1 : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_dither_1 : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_out_sel_1 : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_reset_1 : constant is 1;
attribute mti_svvh_generic_type of pll_ecn_bypass_1 : constant is 1;
attribute mti_svvh_generic_type of pll_ecn_test_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_enable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_fbclk_mux_1_1 : constant is 1;
attribute mti_svvh_generic_type of pll_fbclk_mux_2_1 : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_carry_out_1 : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_division_1 : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_value_ready_1 : constant is 1;
attribute mti_svvh_generic_type of pll_lf_testen_1 : constant is 1;
attribute mti_svvh_generic_type of pll_lock_fltr_cfg_1 : constant is 1;
attribute mti_svvh_generic_type of pll_lock_fltr_test_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_bypass_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_coarse_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_fine_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_hi_div_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_in_src_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_lo_div_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_odd_div_duty_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_ph_mux_prst_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_prst_1 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_bypass_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_coarse_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_fine_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_hi_div_1 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_lo_div_1 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_odd_div_duty_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_ref_buf_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_reg_boost_1 : constant is 1;
attribute mti_svvh_generic_type of pll_regulator_bypass_1 : constant is 1;
attribute mti_svvh_generic_type of pll_ripplecap_ctrl_1 : constant is 1;
attribute mti_svvh_generic_type of pll_slf_rst_1 : constant is 1;
attribute mti_svvh_generic_type of pll_tclk_mux_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_tclk_sel_1 : constant is 1;
attribute mti_svvh_generic_type of pll_test_enable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_testdn_enable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_testup_enable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_unlock_fltr_cfg_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_div_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph0_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph1_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph2_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph3_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph4_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph5_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph6_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph7_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vctrl_test_voltage_1 : constant is 1;
attribute mti_svvh_generic_type of vccd0g_atb_1 : constant is 1;
attribute mti_svvh_generic_type of vccd0g_output_1 : constant is 1;
attribute mti_svvh_generic_type of vccd1g_atb_1 : constant is 1;
attribute mti_svvh_generic_type of vccd1g_output_1 : constant is 1;
attribute mti_svvh_generic_type of vccm1g_tap_1 : constant is 1;
attribute mti_svvh_generic_type of vccr_pd_1 : constant is 1;
attribute mti_svvh_generic_type of vcodiv_override_1 : constant is 1;
attribute mti_svvh_generic_type of sim_use_fast_model_1 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency_0 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_0 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_0 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_0 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_0 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_0 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_0 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_0 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_0 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_0 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_0 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_0 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_0 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_1 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_1 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_1 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_1 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_1 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_1 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_1 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_1 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_1 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_1 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_1 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_1 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_1 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_2 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_2 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_2 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_2 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_2 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_2 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_2 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_2 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_2 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_2 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_2 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_2 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_2 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_3 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_3 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_3 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_3 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_3 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_3 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_3 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_3 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_3 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_3 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_3 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_3 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_3 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_4 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_4 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_4 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_4 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_4 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_4 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_4 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_4 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_4 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_4 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_4 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_4 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_4 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_5 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_5 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_5 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_5 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_5 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_5 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_5 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_5 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_5 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_5 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_5 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_5 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_5 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_6 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_6 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_6 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_6 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_6 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_6 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_6 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_6 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_6 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_6 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_6 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_6 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_6 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_7 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_7 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_7 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_7 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_7 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_7 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_7 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_7 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_7 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_7 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_7 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_7 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_7 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_8 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_8 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_8 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_8 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_8 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_8 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_8 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_8 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_8 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_8 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_8 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_8 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_8 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_9 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_9 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_9 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_9 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_9 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_9 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_9 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_9 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_9 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_9 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_9 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_9 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_9 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_10 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_10 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_10 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_10 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_10 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_10 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_10 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_10 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_10 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_10 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_10 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_10 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_10 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_11 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_11 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_11 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_11 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_11 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_11 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_11 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_11 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_11 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_11 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_11 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_11 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_11 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_12 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_12 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_12 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_12 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_12 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_12 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_12 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_12 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_12 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_12 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_12 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_12 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_12 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_13 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_13 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_13 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_13 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_13 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_13 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_13 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_13 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_13 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_13 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_13 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_13 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_13 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_14 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_14 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_14 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_14 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_14 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_14 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_14 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_14 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_14 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_14 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_14 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_14 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_14 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_15 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_15 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_15 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_15 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_15 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_15 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_15 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_15 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_15 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_15 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_15 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_15 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_15 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_16 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_16 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_16 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_16 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_16 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_16 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_16 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_16 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_16 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_16 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_16 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_16 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_16 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_17 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_17 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_17 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_17 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_17 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_17 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_17 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_17 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_17 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_17 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_17 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_17 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_17 : constant is 3;
attribute mti_svvh_generic_type of dpa_output_clock_frequency_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vcoph_div_0 : constant is 1;
attribute mti_svvh_generic_type of dpa_output_clock_frequency_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vcoph_div_1 : constant is 1;
attribute mti_svvh_generic_type of enable_extclk_output_0 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_cnt_src_0 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_enable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_invert_0 : constant is 1;
attribute mti_svvh_generic_type of enable_extclk_output_1 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_cnt_src_1 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_enable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_invert_1 : constant is 1;
attribute mti_svvh_generic_type of enable_extclk_output_2 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_cnt_src_2 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_enable_2 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_invert_2 : constant is 1;
attribute mti_svvh_generic_type of enable_extclk_output_3 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_cnt_src_3 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_enable_3 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_invert_3 : constant is 1;
attribute mti_svvh_generic_type of enable_dll_output_0 : constant is 1;
attribute mti_svvh_generic_type of pll_dll_src_value_0 : constant is 1;
attribute mti_svvh_generic_type of enable_dll_output_1 : constant is 1;
attribute mti_svvh_generic_type of pll_dll_src_value_1 : constant is 1;
attribute mti_svvh_generic_type of enable_lvds_output_0 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_coarse_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_enable_disable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_fine_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_coarse_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_enable_disable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_fine_dly_0 : constant is 1;
attribute mti_svvh_generic_type of enable_lvds_output_1 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_coarse_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_enable_disable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_fine_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_coarse_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_enable_disable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_fine_dly_1 : constant is 1;
attribute mti_svvh_generic_type of enable_lvds_output_2 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_coarse_dly_2 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_enable_disable_2 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_fine_dly_2 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_coarse_dly_2 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_enable_disable_2 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_fine_dly_2 : constant is 1;
attribute mti_svvh_generic_type of enable_lvds_output_3 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_coarse_dly_3 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_enable_disable_3 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_fine_dly_3 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_coarse_dly_3 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_enable_disable_3 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_fine_dly_3 : constant is 1;
end altera_arriav_pll;
|
mit
|
4b585503838e6a93a3cff92b16a47201
| 0.643749 | 3.061806 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/altera_lnsim/altera_stratixv_pll/_primary.vhd
| 5 | 70,300 |
library verilog;
use verilog.vl_types.all;
entity altera_stratixv_pll is
generic(
number_of_counters: integer := 18;
number_of_fplls : integer := 1;
number_of_extclks: integer := 4;
number_of_dlls : integer := 2;
number_of_lvds : integer := 4;
pll_auto_clk_sw_en_0: string := "false";
pll_clk_loss_edge_0: string := "both_edges";
pll_clk_loss_sw_en_0: string := "false";
pll_clk_sw_dly_0: integer := 0;
pll_clkin_0_src_0: string := "clk_0";
pll_clkin_1_src_0: string := "clk_0";
pll_manu_clk_sw_en_0: string := "false";
pll_sw_refclk_src_0: string := "clk_0";
pll_auto_clk_sw_en_1: string := "false";
pll_clk_loss_edge_1: string := "both_edges";
pll_clk_loss_sw_en_1: string := "false";
pll_clk_sw_dly_1: integer := 0;
pll_clkin_0_src_1: string := "clk_1";
pll_clkin_1_src_1: string := "clk_1";
pll_manu_clk_sw_en_1: string := "false";
pll_sw_refclk_src_1: string := "clk_1";
pll_output_clock_frequency_0: string := "700.0 MHz";
reference_clock_frequency_0: string := "700.0 MHz";
mimic_fbclk_type_0: string := "gclk";
dsm_accumulator_reset_value_0: integer := 0;
forcelock_0 : string := "false";
nreset_invert_0 : string := "false";
pll_atb_0 : integer := 0;
pll_bwctrl_0 : integer := 1000;
pll_cmp_buf_dly_0: string := "0 ps";
pll_cp_comp_0 : string := "true";
pll_cp_current_0: integer := 20;
pll_ctrl_override_setting_0: string := "true";
pll_dsm_dither_0: string := "disable";
pll_dsm_out_sel_0: string := "disable";
pll_dsm_reset_0 : string := "false";
pll_ecn_bypass_0: string := "false";
pll_ecn_test_en_0: string := "false";
pll_enable_0 : string := "true";
pll_fbclk_mux_1_0: string := "fb";
pll_fbclk_mux_2_0: string := "m_cnt";
pll_fractional_carry_out_0: integer := 24;
pll_fractional_division_0: integer := 1;
pll_fractional_value_ready_0: string := "true";
pll_lf_testen_0 : string := "false";
pll_lock_fltr_cfg_0: integer := 25;
pll_lock_fltr_test_0: string := "false";
pll_m_cnt_bypass_en_0: string := "false";
pll_m_cnt_coarse_dly_0: string := "0 ps";
pll_m_cnt_fine_dly_0: string := "0 ps";
pll_m_cnt_hi_div_0: integer := 3;
pll_m_cnt_in_src_0: string := "ph_mux_clk";
pll_m_cnt_lo_div_0: integer := 3;
pll_m_cnt_odd_div_duty_en_0: string := "false";
pll_m_cnt_ph_mux_prst_0: integer := 0;
pll_m_cnt_prst_0: integer := 256;
pll_n_cnt_bypass_en_0: string := "true";
pll_n_cnt_coarse_dly_0: string := "0 ps";
pll_n_cnt_fine_dly_0: string := "0 ps";
pll_n_cnt_hi_div_0: integer := 1;
pll_n_cnt_lo_div_0: integer := 1;
pll_n_cnt_odd_div_duty_en_0: string := "false";
pll_ref_buf_dly_0: string := "0 ps";
pll_reg_boost_0 : integer := 0;
pll_regulator_bypass_0: string := "false";
pll_ripplecap_ctrl_0: integer := 0;
pll_slf_rst_0 : string := "false";
pll_tclk_mux_en_0: string := "false";
pll_tclk_sel_0 : string := "n_src";
pll_test_enable_0: string := "false";
pll_testdn_enable_0: string := "false";
pll_testup_enable_0: string := "false";
pll_unlock_fltr_cfg_0: integer := 1;
pll_vco_div_0 : integer := 0;
pll_vco_ph0_en_0: string := "true";
pll_vco_ph1_en_0: string := "true";
pll_vco_ph2_en_0: string := "true";
pll_vco_ph3_en_0: string := "true";
pll_vco_ph4_en_0: string := "true";
pll_vco_ph5_en_0: string := "true";
pll_vco_ph6_en_0: string := "true";
pll_vco_ph7_en_0: string := "true";
pll_vctrl_test_voltage_0: integer := 750;
vccd0g_atb_0 : string := "disable";
vccd0g_output_0 : integer := 0;
vccd1g_atb_0 : string := "disable";
vccd1g_output_0 : integer := 0;
vccm1g_tap_0 : integer := 2;
vccr_pd_0 : string := "false";
vcodiv_override_0: string := "false";
sim_use_fast_model_0: string := "false";
pll_output_clock_frequency_1: string := "300.0 MHz";
reference_clock_frequency_1: string := "100.0 MHz";
mimic_fbclk_type_1: string := "gclk";
dsm_accumulator_reset_value_1: integer := 0;
forcelock_1 : string := "false";
nreset_invert_1 : string := "false";
pll_atb_1 : integer := 0;
pll_bwctrl_1 : integer := 1000;
pll_cmp_buf_dly_1: string := "0 ps";
pll_cp_comp_1 : string := "true";
pll_cp_current_1: integer := 30;
pll_ctrl_override_setting_1: string := "false";
pll_dsm_dither_1: string := "disable";
pll_dsm_out_sel_1: string := "disable";
pll_dsm_reset_1 : string := "false";
pll_ecn_bypass_1: string := "false";
pll_ecn_test_en_1: string := "false";
pll_enable_1 : string := "false";
pll_fbclk_mux_1_1: string := "glb";
pll_fbclk_mux_2_1: string := "fb_1";
pll_fractional_carry_out_1: integer := 24;
pll_fractional_division_1: integer := 1;
pll_fractional_value_ready_1: string := "true";
pll_lf_testen_1 : string := "false";
pll_lock_fltr_cfg_1: integer := 25;
pll_lock_fltr_test_1: string := "false";
pll_m_cnt_bypass_en_1: string := "false";
pll_m_cnt_coarse_dly_1: string := "0 ps";
pll_m_cnt_fine_dly_1: string := "0 ps";
pll_m_cnt_hi_div_1: integer := 2;
pll_m_cnt_in_src_1: string := "ph_mux_clk";
pll_m_cnt_lo_div_1: integer := 1;
pll_m_cnt_odd_div_duty_en_1: string := "true";
pll_m_cnt_ph_mux_prst_1: integer := 0;
pll_m_cnt_prst_1: integer := 256;
pll_n_cnt_bypass_en_1: string := "true";
pll_n_cnt_coarse_dly_1: string := "0 ps";
pll_n_cnt_fine_dly_1: string := "0 ps";
pll_n_cnt_hi_div_1: integer := 256;
pll_n_cnt_lo_div_1: integer := 256;
pll_n_cnt_odd_div_duty_en_1: string := "false";
pll_ref_buf_dly_1: string := "0 ps";
pll_reg_boost_1 : integer := 0;
pll_regulator_bypass_1: string := "false";
pll_ripplecap_ctrl_1: integer := 0;
pll_slf_rst_1 : string := "false";
pll_tclk_mux_en_1: string := "false";
pll_tclk_sel_1 : string := "n_src";
pll_test_enable_1: string := "false";
pll_testdn_enable_1: string := "false";
pll_testup_enable_1: string := "false";
pll_unlock_fltr_cfg_1: integer := 2;
pll_vco_div_1 : integer := 1;
pll_vco_ph0_en_1: string := "true";
pll_vco_ph1_en_1: string := "true";
pll_vco_ph2_en_1: string := "true";
pll_vco_ph3_en_1: string := "true";
pll_vco_ph4_en_1: string := "true";
pll_vco_ph5_en_1: string := "true";
pll_vco_ph6_en_1: string := "true";
pll_vco_ph7_en_1: string := "true";
pll_vctrl_test_voltage_1: integer := 750;
vccd0g_atb_1 : string := "disable";
vccd0g_output_1 : integer := 0;
vccd1g_atb_1 : string := "disable";
vccd1g_output_1 : integer := 0;
vccm1g_tap_1 : integer := 2;
vccr_pd_1 : string := "false";
vcodiv_override_1: string := "false";
sim_use_fast_model_1: string := "false";
output_clock_frequency_0: string := "100.0 MHz";
enable_output_counter_0: string := "true";
phase_shift_0 : string := "0 ps";
duty_cycle_0 : integer := 50;
c_cnt_coarse_dly_0: string := "0 ps";
c_cnt_fine_dly_0: string := "0 ps";
c_cnt_in_src_0 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_0: integer := 0;
c_cnt_prst_0 : integer := 1;
cnt_fpll_src_0 : string := "fpll_0";
dprio0_cnt_bypass_en_0: string := "true";
dprio0_cnt_hi_div_0: integer := 3;
dprio0_cnt_lo_div_0: integer := 3;
dprio0_cnt_odd_div_even_duty_en_0: string := "false";
dprio1_cnt_bypass_en_0: vl_notype;
dprio1_cnt_hi_div_0: vl_notype;
dprio1_cnt_lo_div_0: vl_notype;
dprio1_cnt_odd_div_even_duty_en_0: vl_notype;
output_clock_frequency_1: string := "0 ps";
enable_output_counter_1: string := "true";
phase_shift_1 : string := "0 ps";
duty_cycle_1 : integer := 50;
c_cnt_coarse_dly_1: string := "0 ps";
c_cnt_fine_dly_1: string := "0 ps";
c_cnt_in_src_1 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_1: integer := 0;
c_cnt_prst_1 : integer := 1;
cnt_fpll_src_1 : string := "fpll_0";
dprio0_cnt_bypass_en_1: string := "true";
dprio0_cnt_hi_div_1: integer := 2;
dprio0_cnt_lo_div_1: integer := 1;
dprio0_cnt_odd_div_even_duty_en_1: string := "true";
dprio1_cnt_bypass_en_1: vl_notype;
dprio1_cnt_hi_div_1: vl_notype;
dprio1_cnt_lo_div_1: vl_notype;
dprio1_cnt_odd_div_even_duty_en_1: vl_notype;
output_clock_frequency_2: string := "0 ps";
enable_output_counter_2: string := "true";
phase_shift_2 : string := "0 ps";
duty_cycle_2 : integer := 50;
c_cnt_coarse_dly_2: string := "0 ps";
c_cnt_fine_dly_2: string := "0 ps";
c_cnt_in_src_2 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_2: integer := 0;
c_cnt_prst_2 : integer := 1;
cnt_fpll_src_2 : string := "fpll_0";
dprio0_cnt_bypass_en_2: string := "true";
dprio0_cnt_hi_div_2: integer := 1;
dprio0_cnt_lo_div_2: integer := 1;
dprio0_cnt_odd_div_even_duty_en_2: string := "false";
dprio1_cnt_bypass_en_2: vl_notype;
dprio1_cnt_hi_div_2: vl_notype;
dprio1_cnt_lo_div_2: vl_notype;
dprio1_cnt_odd_div_even_duty_en_2: vl_notype;
output_clock_frequency_3: string := "0 ps";
enable_output_counter_3: string := "true";
phase_shift_3 : string := "0 ps";
duty_cycle_3 : integer := 50;
c_cnt_coarse_dly_3: string := "0 ps";
c_cnt_fine_dly_3: string := "0 ps";
c_cnt_in_src_3 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_3: integer := 0;
c_cnt_prst_3 : integer := 1;
cnt_fpll_src_3 : string := "fpll_0";
dprio0_cnt_bypass_en_3: string := "false";
dprio0_cnt_hi_div_3: integer := 1;
dprio0_cnt_lo_div_3: integer := 1;
dprio0_cnt_odd_div_even_duty_en_3: string := "false";
dprio1_cnt_bypass_en_3: vl_notype;
dprio1_cnt_hi_div_3: vl_notype;
dprio1_cnt_lo_div_3: vl_notype;
dprio1_cnt_odd_div_even_duty_en_3: vl_notype;
output_clock_frequency_4: string := "0 ps";
enable_output_counter_4: string := "true";
phase_shift_4 : string := "0 ps";
duty_cycle_4 : integer := 50;
c_cnt_coarse_dly_4: string := "0 ps";
c_cnt_fine_dly_4: string := "0 ps";
c_cnt_in_src_4 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_4: integer := 0;
c_cnt_prst_4 : integer := 1;
cnt_fpll_src_4 : string := "fpll_0";
dprio0_cnt_bypass_en_4: string := "false";
dprio0_cnt_hi_div_4: integer := 1;
dprio0_cnt_lo_div_4: integer := 1;
dprio0_cnt_odd_div_even_duty_en_4: string := "false";
dprio1_cnt_bypass_en_4: vl_notype;
dprio1_cnt_hi_div_4: vl_notype;
dprio1_cnt_lo_div_4: vl_notype;
dprio1_cnt_odd_div_even_duty_en_4: vl_notype;
output_clock_frequency_5: string := "0 ps";
enable_output_counter_5: string := "true";
phase_shift_5 : string := "0 ps";
duty_cycle_5 : integer := 50;
c_cnt_coarse_dly_5: string := "0 ps";
c_cnt_fine_dly_5: string := "0 ps";
c_cnt_in_src_5 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_5: integer := 0;
c_cnt_prst_5 : integer := 1;
cnt_fpll_src_5 : string := "fpll_0";
dprio0_cnt_bypass_en_5: string := "false";
dprio0_cnt_hi_div_5: integer := 1;
dprio0_cnt_lo_div_5: integer := 1;
dprio0_cnt_odd_div_even_duty_en_5: string := "false";
dprio1_cnt_bypass_en_5: vl_notype;
dprio1_cnt_hi_div_5: vl_notype;
dprio1_cnt_lo_div_5: vl_notype;
dprio1_cnt_odd_div_even_duty_en_5: vl_notype;
output_clock_frequency_6: string := "0 ps";
enable_output_counter_6: string := "true";
phase_shift_6 : string := "0 ps";
duty_cycle_6 : integer := 50;
c_cnt_coarse_dly_6: string := "0 ps";
c_cnt_fine_dly_6: string := "0 ps";
c_cnt_in_src_6 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_6: integer := 0;
c_cnt_prst_6 : integer := 1;
cnt_fpll_src_6 : string := "fpll_0";
dprio0_cnt_bypass_en_6: string := "false";
dprio0_cnt_hi_div_6: integer := 1;
dprio0_cnt_lo_div_6: integer := 1;
dprio0_cnt_odd_div_even_duty_en_6: string := "false";
dprio1_cnt_bypass_en_6: vl_notype;
dprio1_cnt_hi_div_6: vl_notype;
dprio1_cnt_lo_div_6: vl_notype;
dprio1_cnt_odd_div_even_duty_en_6: vl_notype;
output_clock_frequency_7: string := "0 ps";
enable_output_counter_7: string := "true";
phase_shift_7 : string := "0 ps";
duty_cycle_7 : integer := 50;
c_cnt_coarse_dly_7: string := "0 ps";
c_cnt_fine_dly_7: string := "0 ps";
c_cnt_in_src_7 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_7: integer := 0;
c_cnt_prst_7 : integer := 1;
cnt_fpll_src_7 : string := "fpll_0";
dprio0_cnt_bypass_en_7: string := "false";
dprio0_cnt_hi_div_7: integer := 1;
dprio0_cnt_lo_div_7: integer := 1;
dprio0_cnt_odd_div_even_duty_en_7: string := "false";
dprio1_cnt_bypass_en_7: vl_notype;
dprio1_cnt_hi_div_7: vl_notype;
dprio1_cnt_lo_div_7: vl_notype;
dprio1_cnt_odd_div_even_duty_en_7: vl_notype;
output_clock_frequency_8: string := "0 ps";
enable_output_counter_8: string := "true";
phase_shift_8 : string := "0 ps";
duty_cycle_8 : integer := 50;
c_cnt_coarse_dly_8: string := "0 ps";
c_cnt_fine_dly_8: string := "0 ps";
c_cnt_in_src_8 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_8: integer := 0;
c_cnt_prst_8 : integer := 1;
cnt_fpll_src_8 : string := "fpll_0";
dprio0_cnt_bypass_en_8: string := "false";
dprio0_cnt_hi_div_8: integer := 1;
dprio0_cnt_lo_div_8: integer := 1;
dprio0_cnt_odd_div_even_duty_en_8: string := "false";
dprio1_cnt_bypass_en_8: vl_notype;
dprio1_cnt_hi_div_8: vl_notype;
dprio1_cnt_lo_div_8: vl_notype;
dprio1_cnt_odd_div_even_duty_en_8: vl_notype;
output_clock_frequency_9: string := "0 ps";
enable_output_counter_9: string := "true";
phase_shift_9 : string := "0 ps";
duty_cycle_9 : integer := 50;
c_cnt_coarse_dly_9: string := "0 ps";
c_cnt_fine_dly_9: string := "0 ps";
c_cnt_in_src_9 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_9: integer := 0;
c_cnt_prst_9 : integer := 1;
cnt_fpll_src_9 : string := "fpll_0";
dprio0_cnt_bypass_en_9: string := "false";
dprio0_cnt_hi_div_9: integer := 1;
dprio0_cnt_lo_div_9: integer := 1;
dprio0_cnt_odd_div_even_duty_en_9: string := "false";
dprio1_cnt_bypass_en_9: vl_notype;
dprio1_cnt_hi_div_9: vl_notype;
dprio1_cnt_lo_div_9: vl_notype;
dprio1_cnt_odd_div_even_duty_en_9: vl_notype;
output_clock_frequency_10: string := "0 ps";
enable_output_counter_10: string := "true";
phase_shift_10 : string := "0 ps";
duty_cycle_10 : integer := 50;
c_cnt_coarse_dly_10: string := "0 ps";
c_cnt_fine_dly_10: string := "0 ps";
c_cnt_in_src_10 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_10: integer := 0;
c_cnt_prst_10 : integer := 1;
cnt_fpll_src_10 : string := "fpll_0";
dprio0_cnt_bypass_en_10: string := "false";
dprio0_cnt_hi_div_10: integer := 1;
dprio0_cnt_lo_div_10: integer := 1;
dprio0_cnt_odd_div_even_duty_en_10: string := "false";
dprio1_cnt_bypass_en_10: vl_notype;
dprio1_cnt_hi_div_10: vl_notype;
dprio1_cnt_lo_div_10: vl_notype;
dprio1_cnt_odd_div_even_duty_en_10: vl_notype;
output_clock_frequency_11: string := "0 ps";
enable_output_counter_11: string := "true";
phase_shift_11 : string := "0 ps";
duty_cycle_11 : integer := 50;
c_cnt_coarse_dly_11: string := "0 ps";
c_cnt_fine_dly_11: string := "0 ps";
c_cnt_in_src_11 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_11: integer := 0;
c_cnt_prst_11 : integer := 1;
cnt_fpll_src_11 : string := "fpll_0";
dprio0_cnt_bypass_en_11: string := "false";
dprio0_cnt_hi_div_11: integer := 1;
dprio0_cnt_lo_div_11: integer := 1;
dprio0_cnt_odd_div_even_duty_en_11: string := "false";
dprio1_cnt_bypass_en_11: vl_notype;
dprio1_cnt_hi_div_11: vl_notype;
dprio1_cnt_lo_div_11: vl_notype;
dprio1_cnt_odd_div_even_duty_en_11: vl_notype;
output_clock_frequency_12: string := "0 ps";
enable_output_counter_12: string := "true";
phase_shift_12 : string := "0 ps";
duty_cycle_12 : integer := 50;
c_cnt_coarse_dly_12: string := "0 ps";
c_cnt_fine_dly_12: string := "0 ps";
c_cnt_in_src_12 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_12: integer := 0;
c_cnt_prst_12 : integer := 1;
cnt_fpll_src_12 : string := "fpll_0";
dprio0_cnt_bypass_en_12: string := "false";
dprio0_cnt_hi_div_12: integer := 1;
dprio0_cnt_lo_div_12: integer := 1;
dprio0_cnt_odd_div_even_duty_en_12: string := "false";
dprio1_cnt_bypass_en_12: vl_notype;
dprio1_cnt_hi_div_12: vl_notype;
dprio1_cnt_lo_div_12: vl_notype;
dprio1_cnt_odd_div_even_duty_en_12: vl_notype;
output_clock_frequency_13: string := "0 ps";
enable_output_counter_13: string := "true";
phase_shift_13 : string := "0 ps";
duty_cycle_13 : integer := 50;
c_cnt_coarse_dly_13: string := "0 ps";
c_cnt_fine_dly_13: string := "0 ps";
c_cnt_in_src_13 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_13: integer := 0;
c_cnt_prst_13 : integer := 1;
cnt_fpll_src_13 : string := "fpll_0";
dprio0_cnt_bypass_en_13: string := "false";
dprio0_cnt_hi_div_13: integer := 1;
dprio0_cnt_lo_div_13: integer := 1;
dprio0_cnt_odd_div_even_duty_en_13: string := "false";
dprio1_cnt_bypass_en_13: vl_notype;
dprio1_cnt_hi_div_13: vl_notype;
dprio1_cnt_lo_div_13: vl_notype;
dprio1_cnt_odd_div_even_duty_en_13: vl_notype;
output_clock_frequency_14: string := "0 ps";
enable_output_counter_14: string := "true";
phase_shift_14 : string := "0 ps";
duty_cycle_14 : integer := 50;
c_cnt_coarse_dly_14: string := "0 ps";
c_cnt_fine_dly_14: string := "0 ps";
c_cnt_in_src_14 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_14: integer := 0;
c_cnt_prst_14 : integer := 1;
cnt_fpll_src_14 : string := "fpll_0";
dprio0_cnt_bypass_en_14: string := "false";
dprio0_cnt_hi_div_14: integer := 1;
dprio0_cnt_lo_div_14: integer := 1;
dprio0_cnt_odd_div_even_duty_en_14: string := "false";
dprio1_cnt_bypass_en_14: vl_notype;
dprio1_cnt_hi_div_14: vl_notype;
dprio1_cnt_lo_div_14: vl_notype;
dprio1_cnt_odd_div_even_duty_en_14: vl_notype;
output_clock_frequency_15: string := "0 ps";
enable_output_counter_15: string := "true";
phase_shift_15 : string := "0 ps";
duty_cycle_15 : integer := 50;
c_cnt_coarse_dly_15: string := "0 ps";
c_cnt_fine_dly_15: string := "0 ps";
c_cnt_in_src_15 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_15: integer := 0;
c_cnt_prst_15 : integer := 1;
cnt_fpll_src_15 : string := "fpll_0";
dprio0_cnt_bypass_en_15: string := "false";
dprio0_cnt_hi_div_15: integer := 1;
dprio0_cnt_lo_div_15: integer := 1;
dprio0_cnt_odd_div_even_duty_en_15: string := "false";
dprio1_cnt_bypass_en_15: vl_notype;
dprio1_cnt_hi_div_15: vl_notype;
dprio1_cnt_lo_div_15: vl_notype;
dprio1_cnt_odd_div_even_duty_en_15: vl_notype;
output_clock_frequency_16: string := "0 ps";
enable_output_counter_16: string := "true";
phase_shift_16 : string := "0 ps";
duty_cycle_16 : integer := 50;
c_cnt_coarse_dly_16: string := "0 ps";
c_cnt_fine_dly_16: string := "0 ps";
c_cnt_in_src_16 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_16: integer := 0;
c_cnt_prst_16 : integer := 1;
cnt_fpll_src_16 : string := "fpll_0";
dprio0_cnt_bypass_en_16: string := "false";
dprio0_cnt_hi_div_16: integer := 1;
dprio0_cnt_lo_div_16: integer := 1;
dprio0_cnt_odd_div_even_duty_en_16: string := "false";
dprio1_cnt_bypass_en_16: vl_notype;
dprio1_cnt_hi_div_16: vl_notype;
dprio1_cnt_lo_div_16: vl_notype;
dprio1_cnt_odd_div_even_duty_en_16: vl_notype;
output_clock_frequency_17: string := "0 ps";
enable_output_counter_17: string := "true";
phase_shift_17 : string := "0 ps";
duty_cycle_17 : integer := 50;
c_cnt_coarse_dly_17: string := "0 ps";
c_cnt_fine_dly_17: string := "0 ps";
c_cnt_in_src_17 : string := "ph_mux_clk";
c_cnt_ph_mux_prst_17: integer := 0;
c_cnt_prst_17 : integer := 1;
cnt_fpll_src_17 : string := "fpll_0";
dprio0_cnt_bypass_en_17: string := "false";
dprio0_cnt_hi_div_17: integer := 1;
dprio0_cnt_lo_div_17: integer := 1;
dprio0_cnt_odd_div_even_duty_en_17: string := "false";
dprio1_cnt_bypass_en_17: vl_notype;
dprio1_cnt_hi_div_17: vl_notype;
dprio1_cnt_lo_div_17: vl_notype;
dprio1_cnt_odd_div_even_duty_en_17: vl_notype;
dpa_output_clock_frequency_0: string := "0 ps";
pll_vcoph_div_0 : integer := 1;
dpa_output_clock_frequency_1: string := "0 ps";
pll_vcoph_div_1 : integer := 1;
enable_extclk_output_0: string := "false";
pll_extclk_cnt_src_0: string := "m0_cnt";
pll_extclk_enable_0: string := "true";
pll_extclk_invert_0: string := "false";
enable_extclk_output_1: string := "false";
pll_extclk_cnt_src_1: string := "vss";
pll_extclk_enable_1: string := "true";
pll_extclk_invert_1: string := "false";
enable_extclk_output_2: string := "false";
pll_extclk_cnt_src_2: string := "vss";
pll_extclk_enable_2: string := "true";
pll_extclk_invert_2: string := "false";
enable_extclk_output_3: string := "false";
pll_extclk_cnt_src_3: string := "vss";
pll_extclk_enable_3: string := "true";
pll_extclk_invert_3: string := "false";
enable_dll_output_0: string := "false";
pll_dll_src_value_0: string := "vss";
enable_dll_output_1: string := "false";
pll_dll_src_value_1: string := "vss";
enable_lvds_output_0: string := "false";
pll_loaden_coarse_dly_0: string := "0 ps";
pll_loaden_enable_disable_0: string := "true";
pll_loaden_fine_dly_0: string := "0 ps";
pll_lvdsclk_coarse_dly_0: string := "0 ps";
pll_lvdsclk_enable_disable_0: string := "true";
pll_lvdsclk_fine_dly_0: string := "0 ps";
enable_lvds_output_1: string := "false";
pll_loaden_coarse_dly_1: string := "0 ps";
pll_loaden_enable_disable_1: string := "true";
pll_loaden_fine_dly_1: string := "0 ps";
pll_lvdsclk_coarse_dly_1: string := "0 ps";
pll_lvdsclk_enable_disable_1: string := "true";
pll_lvdsclk_fine_dly_1: string := "0 ps";
enable_lvds_output_2: string := "false";
pll_loaden_coarse_dly_2: string := "0 ps";
pll_loaden_enable_disable_2: string := "true";
pll_loaden_fine_dly_2: string := "0 ps";
pll_lvdsclk_coarse_dly_2: string := "0 ps";
pll_lvdsclk_enable_disable_2: string := "true";
pll_lvdsclk_fine_dly_2: string := "0 ps";
enable_lvds_output_3: string := "false";
pll_loaden_coarse_dly_3: string := "0 ps";
pll_loaden_enable_disable_3: string := "true";
pll_loaden_fine_dly_3: string := "0 ps";
pll_lvdsclk_coarse_dly_3: string := "0 ps";
pll_lvdsclk_enable_disable_3: string := "true";
pll_lvdsclk_fine_dly_3: string := "0 ps"
);
port(
phout_0 : out vl_logic_vector(7 downto 0);
phout_1 : out vl_logic_vector(7 downto 0);
adjpllin : in vl_logic_vector;
cclk : in vl_logic_vector;
coreclkin : in vl_logic_vector;
extswitch : in vl_logic_vector;
iqtxrxclkin : in vl_logic_vector;
plliqclkin : in vl_logic_vector;
rxiqclkin : in vl_logic_vector;
clkin : in vl_logic_vector(3 downto 0);
refiqclk_0 : in vl_logic_vector(1 downto 0);
refiqclk_1 : in vl_logic_vector(1 downto 0);
clk0bad : out vl_logic_vector;
clk1bad : out vl_logic_vector;
pllclksel : out vl_logic_vector;
atpgmode : in vl_logic_vector;
clk : in vl_logic_vector;
fpllcsrtest : in vl_logic_vector;
iocsrclkin : in vl_logic_vector;
iocsrdatain : in vl_logic_vector;
iocsren : in vl_logic_vector;
iocsrrstn : in vl_logic_vector;
mdiodis : in vl_logic_vector;
phaseen : in vl_logic_vector;
read : in vl_logic_vector;
rstn : in vl_logic_vector;
scanen : in vl_logic_vector;
sershiftload : in vl_logic_vector;
shiftdonei : in vl_logic_vector;
updn : in vl_logic_vector;
write : in vl_logic_vector;
addr_0 : in vl_logic_vector(5 downto 0);
addr_1 : in vl_logic_vector(5 downto 0);
byteen_0 : in vl_logic_vector(1 downto 0);
byteen_1 : in vl_logic_vector(1 downto 0);
cntsel_0 : in vl_logic_vector(4 downto 0);
cntsel_1 : in vl_logic_vector(4 downto 0);
din_0 : in vl_logic_vector(15 downto 0);
din_1 : in vl_logic_vector(15 downto 0);
blockselect : out vl_logic_vector;
iocsrdataout : out vl_logic_vector;
iocsrenbuf : out vl_logic_vector;
iocsrrstnbuf : out vl_logic_vector;
phasedone : out vl_logic_vector;
dout_0 : out vl_logic_vector(15 downto 0);
dout_1 : out vl_logic_vector(15 downto 0);
dprioout_0 : out vl_logic_vector(815 downto 0);
dprioout_1 : out vl_logic_vector(815 downto 0);
fbclkfpll : in vl_logic_vector;
lvdfbin : in vl_logic_vector;
nresync : in vl_logic_vector;
pfden : in vl_logic_vector;
shiften_fpll : in vl_logic_vector;
zdb : in vl_logic_vector;
fblvdsout : out vl_logic_vector;
lock : out vl_logic_vector;
mcntout : out vl_logic_vector;
plniotribuf : out vl_logic_vector;
clken : in vl_logic_vector;
extclk : out vl_logic_vector;
dll_clkin : in vl_logic_vector;
clkout : out vl_logic_vector;
loaden : out vl_logic_vector;
lvdsclk : out vl_logic_vector;
divclk : out vl_logic_vector;
cascade_out : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of number_of_counters : constant is 1;
attribute mti_svvh_generic_type of number_of_fplls : constant is 1;
attribute mti_svvh_generic_type of number_of_extclks : constant is 1;
attribute mti_svvh_generic_type of number_of_dlls : constant is 1;
attribute mti_svvh_generic_type of number_of_lvds : constant is 1;
attribute mti_svvh_generic_type of pll_auto_clk_sw_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_loss_edge_0 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_loss_sw_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_sw_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_clkin_0_src_0 : constant is 1;
attribute mti_svvh_generic_type of pll_clkin_1_src_0 : constant is 1;
attribute mti_svvh_generic_type of pll_manu_clk_sw_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_sw_refclk_src_0 : constant is 1;
attribute mti_svvh_generic_type of pll_auto_clk_sw_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_loss_edge_1 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_loss_sw_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_clk_sw_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_clkin_0_src_1 : constant is 1;
attribute mti_svvh_generic_type of pll_clkin_1_src_1 : constant is 1;
attribute mti_svvh_generic_type of pll_manu_clk_sw_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_sw_refclk_src_1 : constant is 1;
attribute mti_svvh_generic_type of pll_output_clock_frequency_0 : constant is 1;
attribute mti_svvh_generic_type of reference_clock_frequency_0 : constant is 1;
attribute mti_svvh_generic_type of mimic_fbclk_type_0 : constant is 1;
attribute mti_svvh_generic_type of dsm_accumulator_reset_value_0 : constant is 1;
attribute mti_svvh_generic_type of forcelock_0 : constant is 1;
attribute mti_svvh_generic_type of nreset_invert_0 : constant is 1;
attribute mti_svvh_generic_type of pll_atb_0 : constant is 1;
attribute mti_svvh_generic_type of pll_bwctrl_0 : constant is 1;
attribute mti_svvh_generic_type of pll_cmp_buf_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_cp_comp_0 : constant is 1;
attribute mti_svvh_generic_type of pll_cp_current_0 : constant is 1;
attribute mti_svvh_generic_type of pll_ctrl_override_setting_0 : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_dither_0 : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_out_sel_0 : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_reset_0 : constant is 1;
attribute mti_svvh_generic_type of pll_ecn_bypass_0 : constant is 1;
attribute mti_svvh_generic_type of pll_ecn_test_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_enable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_fbclk_mux_1_0 : constant is 1;
attribute mti_svvh_generic_type of pll_fbclk_mux_2_0 : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_carry_out_0 : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_division_0 : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_value_ready_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lf_testen_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lock_fltr_cfg_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lock_fltr_test_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_bypass_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_coarse_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_fine_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_hi_div_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_in_src_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_lo_div_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_odd_div_duty_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_ph_mux_prst_0 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_prst_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_bypass_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_coarse_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_fine_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_hi_div_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_lo_div_0 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_odd_div_duty_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_ref_buf_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_reg_boost_0 : constant is 1;
attribute mti_svvh_generic_type of pll_regulator_bypass_0 : constant is 1;
attribute mti_svvh_generic_type of pll_ripplecap_ctrl_0 : constant is 1;
attribute mti_svvh_generic_type of pll_slf_rst_0 : constant is 1;
attribute mti_svvh_generic_type of pll_tclk_mux_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_tclk_sel_0 : constant is 1;
attribute mti_svvh_generic_type of pll_test_enable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_testdn_enable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_testup_enable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_unlock_fltr_cfg_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_div_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph0_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph1_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph2_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph3_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph4_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph5_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph6_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph7_en_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vctrl_test_voltage_0 : constant is 1;
attribute mti_svvh_generic_type of vccd0g_atb_0 : constant is 1;
attribute mti_svvh_generic_type of vccd0g_output_0 : constant is 1;
attribute mti_svvh_generic_type of vccd1g_atb_0 : constant is 1;
attribute mti_svvh_generic_type of vccd1g_output_0 : constant is 1;
attribute mti_svvh_generic_type of vccm1g_tap_0 : constant is 1;
attribute mti_svvh_generic_type of vccr_pd_0 : constant is 1;
attribute mti_svvh_generic_type of vcodiv_override_0 : constant is 1;
attribute mti_svvh_generic_type of sim_use_fast_model_0 : constant is 1;
attribute mti_svvh_generic_type of pll_output_clock_frequency_1 : constant is 1;
attribute mti_svvh_generic_type of reference_clock_frequency_1 : constant is 1;
attribute mti_svvh_generic_type of mimic_fbclk_type_1 : constant is 1;
attribute mti_svvh_generic_type of dsm_accumulator_reset_value_1 : constant is 1;
attribute mti_svvh_generic_type of forcelock_1 : constant is 1;
attribute mti_svvh_generic_type of nreset_invert_1 : constant is 1;
attribute mti_svvh_generic_type of pll_atb_1 : constant is 1;
attribute mti_svvh_generic_type of pll_bwctrl_1 : constant is 1;
attribute mti_svvh_generic_type of pll_cmp_buf_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_cp_comp_1 : constant is 1;
attribute mti_svvh_generic_type of pll_cp_current_1 : constant is 1;
attribute mti_svvh_generic_type of pll_ctrl_override_setting_1 : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_dither_1 : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_out_sel_1 : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_reset_1 : constant is 1;
attribute mti_svvh_generic_type of pll_ecn_bypass_1 : constant is 1;
attribute mti_svvh_generic_type of pll_ecn_test_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_enable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_fbclk_mux_1_1 : constant is 1;
attribute mti_svvh_generic_type of pll_fbclk_mux_2_1 : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_carry_out_1 : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_division_1 : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_value_ready_1 : constant is 1;
attribute mti_svvh_generic_type of pll_lf_testen_1 : constant is 1;
attribute mti_svvh_generic_type of pll_lock_fltr_cfg_1 : constant is 1;
attribute mti_svvh_generic_type of pll_lock_fltr_test_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_bypass_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_coarse_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_fine_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_hi_div_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_in_src_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_lo_div_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_odd_div_duty_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_ph_mux_prst_1 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_prst_1 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_bypass_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_coarse_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_fine_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_hi_div_1 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_lo_div_1 : constant is 1;
attribute mti_svvh_generic_type of pll_n_cnt_odd_div_duty_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_ref_buf_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_reg_boost_1 : constant is 1;
attribute mti_svvh_generic_type of pll_regulator_bypass_1 : constant is 1;
attribute mti_svvh_generic_type of pll_ripplecap_ctrl_1 : constant is 1;
attribute mti_svvh_generic_type of pll_slf_rst_1 : constant is 1;
attribute mti_svvh_generic_type of pll_tclk_mux_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_tclk_sel_1 : constant is 1;
attribute mti_svvh_generic_type of pll_test_enable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_testdn_enable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_testup_enable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_unlock_fltr_cfg_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_div_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph0_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph1_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph2_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph3_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph4_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph5_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph6_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_ph7_en_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vctrl_test_voltage_1 : constant is 1;
attribute mti_svvh_generic_type of vccd0g_atb_1 : constant is 1;
attribute mti_svvh_generic_type of vccd0g_output_1 : constant is 1;
attribute mti_svvh_generic_type of vccd1g_atb_1 : constant is 1;
attribute mti_svvh_generic_type of vccd1g_output_1 : constant is 1;
attribute mti_svvh_generic_type of vccm1g_tap_1 : constant is 1;
attribute mti_svvh_generic_type of vccr_pd_1 : constant is 1;
attribute mti_svvh_generic_type of vcodiv_override_1 : constant is 1;
attribute mti_svvh_generic_type of sim_use_fast_model_1 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency_0 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_0 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_0 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_0 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_0 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_0 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_0 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_0 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_0 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_0 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_0 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_0 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_0 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_1 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_1 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_1 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_1 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_1 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_1 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_1 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_1 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_1 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_1 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_1 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_1 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_1 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_2 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_2 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_2 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_2 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_2 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_2 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_2 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_2 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_2 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_2 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_2 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_2 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_2 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_3 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_3 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_3 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_3 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_3 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_3 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_3 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_3 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_3 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_3 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_3 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_3 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_3 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_4 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_4 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_4 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_4 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_4 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_4 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_4 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_4 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_4 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_4 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_4 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_4 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_4 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_5 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_5 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_5 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_5 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_5 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_5 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_5 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_5 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_5 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_5 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_5 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_5 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_5 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_6 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_6 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_6 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_6 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_6 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_6 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_6 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_6 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_6 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_6 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_6 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_6 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_6 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_7 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_7 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_7 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_7 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_7 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_7 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_7 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_7 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_7 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_7 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_7 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_7 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_7 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_8 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_8 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_8 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_8 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_8 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_8 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_8 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_8 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_8 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_8 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_8 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_8 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_8 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_9 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_9 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_9 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_9 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_9 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_9 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_9 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_9 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_9 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_9 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_9 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_9 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_9 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_10 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_10 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_10 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_10 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_10 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_10 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_10 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_10 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_10 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_10 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_10 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_10 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_10 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_11 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_11 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_11 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_11 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_11 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_11 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_11 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_11 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_11 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_11 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_11 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_11 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_11 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_12 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_12 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_12 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_12 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_12 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_12 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_12 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_12 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_12 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_12 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_12 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_12 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_12 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_13 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_13 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_13 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_13 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_13 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_13 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_13 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_13 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_13 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_13 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_13 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_13 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_13 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_14 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_14 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_14 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_14 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_14 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_14 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_14 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_14 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_14 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_14 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_14 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_14 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_14 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_15 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_15 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_15 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_15 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_15 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_15 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_15 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_15 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_15 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_15 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_15 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_15 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_15 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_16 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_16 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_16 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_16 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_16 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_16 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_16 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_16 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_16 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_16 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_16 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_16 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_16 : constant is 3;
attribute mti_svvh_generic_type of output_clock_frequency_17 : constant is 1;
attribute mti_svvh_generic_type of enable_output_counter_17 : constant is 1;
attribute mti_svvh_generic_type of phase_shift_17 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle_17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_coarse_dly_17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_fine_dly_17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src_17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst_17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst_17 : constant is 1;
attribute mti_svvh_generic_type of cnt_fpll_src_17 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_bypass_en_17 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_hi_div_17 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_lo_div_17 : constant is 1;
attribute mti_svvh_generic_type of dprio0_cnt_odd_div_even_duty_en_17 : constant is 1;
attribute mti_svvh_generic_type of dprio1_cnt_bypass_en_17 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_hi_div_17 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_lo_div_17 : constant is 3;
attribute mti_svvh_generic_type of dprio1_cnt_odd_div_even_duty_en_17 : constant is 3;
attribute mti_svvh_generic_type of dpa_output_clock_frequency_0 : constant is 1;
attribute mti_svvh_generic_type of pll_vcoph_div_0 : constant is 1;
attribute mti_svvh_generic_type of dpa_output_clock_frequency_1 : constant is 1;
attribute mti_svvh_generic_type of pll_vcoph_div_1 : constant is 1;
attribute mti_svvh_generic_type of enable_extclk_output_0 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_cnt_src_0 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_enable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_invert_0 : constant is 1;
attribute mti_svvh_generic_type of enable_extclk_output_1 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_cnt_src_1 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_enable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_invert_1 : constant is 1;
attribute mti_svvh_generic_type of enable_extclk_output_2 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_cnt_src_2 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_enable_2 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_invert_2 : constant is 1;
attribute mti_svvh_generic_type of enable_extclk_output_3 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_cnt_src_3 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_enable_3 : constant is 1;
attribute mti_svvh_generic_type of pll_extclk_invert_3 : constant is 1;
attribute mti_svvh_generic_type of enable_dll_output_0 : constant is 1;
attribute mti_svvh_generic_type of pll_dll_src_value_0 : constant is 1;
attribute mti_svvh_generic_type of enable_dll_output_1 : constant is 1;
attribute mti_svvh_generic_type of pll_dll_src_value_1 : constant is 1;
attribute mti_svvh_generic_type of enable_lvds_output_0 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_coarse_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_enable_disable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_fine_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_coarse_dly_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_enable_disable_0 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_fine_dly_0 : constant is 1;
attribute mti_svvh_generic_type of enable_lvds_output_1 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_coarse_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_enable_disable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_fine_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_coarse_dly_1 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_enable_disable_1 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_fine_dly_1 : constant is 1;
attribute mti_svvh_generic_type of enable_lvds_output_2 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_coarse_dly_2 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_enable_disable_2 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_fine_dly_2 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_coarse_dly_2 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_enable_disable_2 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_fine_dly_2 : constant is 1;
attribute mti_svvh_generic_type of enable_lvds_output_3 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_coarse_dly_3 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_enable_disable_3 : constant is 1;
attribute mti_svvh_generic_type of pll_loaden_fine_dly_3 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_coarse_dly_3 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_enable_disable_3 : constant is 1;
attribute mti_svvh_generic_type of pll_lvdsclk_fine_dly_3 : constant is 1;
end altera_stratixv_pll;
|
mit
|
dba48a8dd75b2e996633bfc987ec657f
| 0.64377 | 3.06198 | false | false | false | false |
michaelmiehling/A25_VME_TB
|
Testbench/vme_sim_slave.vhd
| 1 | 18,644 |
---------------------------------------------------------------
-- Title : VME bus slave simmodel
-- Project : A15
---------------------------------------------------------------
-- File : vme_sim_slave.vhd
-- Author : Michael Miehling
-- Email : [email protected]
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 02/09/03
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description :
--
--
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
-- Copyright (C) 2001, MEN Mikroelektronik Nuernberg GmbH
--
-- All rights reserved. Reproduction in whole or part is
-- prohibited without the written permission of the
-- copyright owner.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.2 $
--
-- $Log: vme_sim_slave.vhd,v $
-- Revision 1.2 2013/04/18 15:11:16 MMiehling
-- added irq
--
-- Revision 1.1 2012/03/29 10:28:50 MMiehling
-- Initial Revision
--
-- Revision 1.3 2006/05/18 14:31:30 MMiehling
-- correct behaviour of iack
--
-- Revision 1.2 2006/05/15 10:36:23 MMiehling
-- now support of 0x0B, 0x0F, 0x3B, 0x3F => 32Bit Block Transfer
--
-- Revision 1.1 2005/10/28 17:52:18 mmiehling
-- Initial Revision
--
-- Revision 1.2 2004/08/13 15:36:06 mmiehling
-- updated
--
-- Revision 1.1 2004/07/27 17:28:15 mmiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee,work;
USE ieee.std_logic_1164.ALL;
USE work.vme_sim_pack.ALL;
USE ieee.std_logic_unsigned.ALL;
USE std.textio.all;
USE work.print_pkg.all;
ENTITY vme_sim_slave IS
PORT (
sysresin : IN std_logic;
asn_in : IN std_logic;
dsan_in : IN std_logic;
dsbn_in : IN std_logic;
writen_in : IN std_logic;
berrn_in : IN std_logic;
addr : INOUT std_logic_vector(31 DOWNTO 0);
data_in : IN std_logic_vector(31 DOWNTO 0);
am_in : IN std_logic_vector(5 DOWNTO 0);
iackn_in : IN std_logic; -- daisy-chain
iackn : IN std_logic; -- bussignal
irq_out : OUT std_logic_vector(7 DOWNTO 1);
dtackn_out : OUT std_logic;
data_out : OUT std_logic_vector(31 DOWNTO 0);
vb_irq1n : IN std_logic;
vb_irq2n : IN std_logic;
vb_irq3n : IN std_logic;
vb_irq4n : IN std_logic;
vb_irq5n : IN std_logic;
vb_irq6n : IN std_logic;
vb_irq7n : IN std_logic;
vme_slv_in : IN vme_slv_in_type;
vme_slv_out : OUT vme_slv_out_type
);
END vme_sim_slave;
ARCHITECTURE vme_sim_slave_arch OF vme_sim_slave IS
SUBTYPE irq_vec IS std_logic_vector(7 DOWNTO 0);
TYPE irq_id_type IS array (7 DOWNTO 1) OF irq_vec;
SIGNAL sim_slave_active : std_logic;
SIGNAL iackn_in_int : std_logic;
SIGNAL conf_ack : boolean;
BEGIN
iackn_in_int <= '0' WHEN iackn_in = '0' AND (dsan_in = '0' OR dsbn_in = '0') ELSE '1';
vme_slv_out.conf_ack <= conf_ack;
vme_slv_out.irq(1) <= vb_irq1n;
vme_slv_out.irq(2) <= vb_irq2n;
vme_slv_out.irq(3) <= vb_irq3n;
vme_slv_out.irq(4) <= vb_irq4n;
vme_slv_out.irq(5) <= vb_irq5n;
vme_slv_out.irq(6) <= vb_irq6n;
vme_slv_out.irq(7) <= vb_irq7n;
slave : PROCESS
VARIABLE asn_time : time;
VARIABLE zeit : time;
VARIABLE addr_int : std_logic_vector(31 DOWNTO 0);
VARIABLE first_d64_cycle : boolean;
VARIABLE am_int : std_logic_vector(5 DOWNTO 0);
VARIABLE i : integer;
VARIABLE ws, sd : integer;
VARIABLE lin:line;
VARIABLE data : std_logic_vector(31 DOWNTO 0);
VARIABLE check:boolean;
VARIABLE adr_int : std_logic_vector(31 DOWNTO 3);
VARIABLE end_of_acc : std_logic;
VARIABLE mem_head : head_ptr;
VARIABLE allocated : boolean;
VARIABLE irq_id : irq_id_type;
VARIABLE irq : integer;
BEGIN
mem_head := new head'(0,null);
sim_slave_active <= '0';
data_out <= (OTHERS => 'Z');
am_int := (others => '0');
first_d64_cycle := TRUE;
conf_ack <= vme_slv_in.conf_req;
addr <= (OTHERS => 'H');
dtackn_out <= 'H';
irq_out <= (OTHERS => 'H');
irq := 0;
WAIT UNTIL sysresin /= '0'; --ohne EVENT
gen_loop: LOOP -- main loop
data_out <= (OTHERS => 'Z');
IF asn_in /= '0' OR (vme_slv_in.conf_req/= conf_ack) THEN
WAIT until falling_edge(asn_in) OR vme_slv_in.conf_req'event;
END IF;
----------------------------------------------------------------------------------------
-- config access
----------------------------------------------------------------------------------------
IF vme_slv_in.conf_req /= conf_ack THEN
IF vme_slv_in.req_type = 1 THEN
--WRITE
adr_int:=vme_slv_in.adr(31 DOWNTO 3);
wr_data(conv_integer(adr_int), vme_slv_in.wr_dat, "1111", mem_head);
ELSIF vme_slv_in.req_type = 0 THEN
-- read from iram
rd_data(conv_integer(vme_slv_in.adr(31 DOWNTO 3)), data, allocated, mem_head);
vme_slv_out.rd_dat <= data;
ELSIF vme_slv_in.req_type = 2 THEN
-- set irq request
irq_out(vme_slv_in.irq) <= '0';
irq := vme_slv_in.irq;
irq_id(irq) := vme_slv_in.wr_dat(7 DOWNTO 0);
ELSIF vme_slv_in.req_type = 3 THEN
-- request of last address modifier used
vme_slv_out.rd_am <= am_int;
END IF;
conf_ack <= vme_slv_in.conf_req; -- handshake acknowledge
next gen_loop;
END IF;
----------------------------------------------------------------------------------------
-- vme access
----------------------------------------------------------------------------------------
addr_int := addr;
am_int := am_in;
first_d64_cycle := TRUE;
LOOP
asn_time := now;
IF NOT (dsan_in = '0' OR dsbn_in = '0') AND asn_in = '0' THEN
WAIT until (dsan_in = '0' OR dsbn_in = '0' OR asn_in /= '0');
END IF;
IF asn_in /= '0' THEN
exit;
END IF;
-- D64 burst
IF iackn /= '0' AND (
(addr_int(31 DOWNTO 28) = sl_base_A32 AND (am_int(5 DOWNTO 0) = AM_A32_NONPRIV_MBLT OR am_int(5 DOWNTO 0) = AM_A32_SUPER_MBLT)) or
(addr_int(23 DOWNTO 20) = sl_base_A24 AND (am_int(5 DOWNTO 0) = AM_A24_NONPRIV_MBLT OR am_int(5 DOWNTO 0) = AM_A24_SUPER_MBLT))) THEN
sim_slave_active <= '1';
IF writen_in = '1' THEN -- READ
WAIT FOR time_26;
IF first_d64_cycle = FALSE THEN
rd_data(conv_integer(addr_int(11 DOWNTO 2)), data, allocated, mem_head);
addr(31 DOWNTO 24) <= data(31 DOWNTO 24);
addr(23 DOWNTO 16) <= data(23 DOWNTO 16);
addr(15 DOWNTO 8) <= data(15 DOWNTO 8);
addr(7 DOWNTO 0) <= data(7 DOWNTO 0);
rd_data(conv_integer(addr_int(11 DOWNTO 2)+1), data, allocated, mem_head);
data_out(31 DOWNTO 24) <= data(31 DOWNTO 24);
data_out(23 DOWNTO 16) <= data(23 DOWNTO 16);
data_out(15 DOWNTO 8) <= data(15 DOWNTO 8);
data_out(7 DOWNTO 0) <= data(7 DOWNTO 0);
addr_int := addr_int + 8;
END IF;
WAIT FOR time_27;
dtackn_out <= '0';
IF dsan_in = '0' THEN
WAIT until rising_edge(dsan_in);
END IF;
IF dsbn_in = '0' THEN
WAIT until rising_edge(dsbn_in);
END IF;
data_out <= (OTHERS => 'H');
addr <= (OTHERS => 'H');
WAIT FOR 10 ns;
-- WAIT FOR 120 ns; -- extended to simulate slow slave with long dtackn active
dtackn_out <= 'H';
ELSE -- WRITE
IF first_d64_cycle = FALSE THEN
IF NOT (data_in'stable(time_8)) then
print("vme_sim: Data[31:0] was not stable for time(8)!");
ASSERT FALSE REPORT " Timingfehler! " SEVERITY error;
END IF;
IF NOT (addr'stable(time_8)) then
print("vme_sim: Addr[31:0] was not stable for time(8)!");
ASSERT FALSE REPORT " Timingfehler! " SEVERITY error;
END IF;
WAIT FOR time_28;
wr_data(conv_integer(addr_int(11 DOWNTO 2)), addr, "1111", mem_head);
wr_data(conv_integer(addr_int(11 DOWNTO 2)+1), data_in, "1111", mem_head);
addr_int := addr_int + 8;
ELSE
WAIT FOR time_28;
END IF;
dtackn_out <= '0';
IF dsan_in = '0' THEN
WAIT until rising_edge(dsan_in);
END IF;
IF dsbn_in = '0' THEN
WAIT until rising_edge(dsbn_in);
END IF;
WAIT FOR 10 ns;
-- WAIT FOR 120 ns; -- extended to simulate slow slave with long dtackn active
dtackn_out <= 'H';
END IF;
first_d64_cycle := FALSE;
-- all normal accesses
ELSIF iackn /= '0' AND ( (addr_int(15 DOWNTO 12) = sl_base_A16 AND am_int(5 DOWNTO 4) = "10") OR
(addr_int(23 DOWNTO 20) = sl_base_A24 AND am_int(5 DOWNTO 4) = "11") OR
(addr_int(23 DOWNTO 20) = sl_base_CRCSR AND am_int(5 DOWNTO 0) = AM_CRCSR) OR
(addr_int(31 DOWNTO 28) = sl_base_A32 AND am_int(5 DOWNTO 4) = "00") )THEN
sim_slave_active <= '1';
IF writen_in = '1' THEN -- READ
WAIT FOR (time_28 - time_27);
dtackn_out <= '0';
IF (dsbn_in = '0' AND dsan_in = '0' AND addr_int(1 DOWNTO 0) = "01") OR
(dsbn_in = '0' AND dsan_in /= '0' AND addr_int(1 DOWNTO 0) = "01") OR
(dsbn_in /= '0' AND dsan_in = '0' AND addr_int(1 DOWNTO 0) = "01") THEN
rd_data(conv_integer(addr_int(11 DOWNTO 2)), data, allocated, mem_head);
data_out(15 DOWNTO 0) <= data(31 DOWNTO 16);
data_out(31 DOWNTO 16) <= data(15 DOWNTO 0);
ELSE
rd_data(conv_integer(addr_int(11 DOWNTO 2)), data, allocated, mem_head);
data_out <= data;
END IF;
IF dsan_in = '0' THEN
WAIT until rising_edge(dsan_in);
END IF;
IF dsbn_in = '0' THEN
WAIT until rising_edge(dsbn_in);
END IF;
data_out <= (OTHERS => 'H');
WAIT FOR 10 ns;
dtackn_out <= 'H';
ELSE -- WRITE
IF NOT (data_in'stable(time_8)) then
print("vme_sim: Data[31:0] was not stable for time(8)!");
ASSERT FALSE REPORT " Timingfehler! " SEVERITY error;
END IF;
WAIT FOR time_28;
IF addr_int(0) = '1' THEN -- lwordn = '1' => D16
data := data_in(15 DOWNTO 8) & data_in(7 DOWNTO 0) & data_in(15 DOWNTO 8) & data_in(7 DOWNTO 0);
IF dsan_in /= '0' AND dsbn_in = '0' AND addr_int(1) = '0' THEN
wr_data(conv_integer(addr_int(11 DOWNTO 2)), data, "1000", mem_head);
ELSIF dsan_in = '0' AND dsbn_in /= '0' AND addr_int(1) = '0' THEN
wr_data(conv_integer(addr_int(11 DOWNTO 2)), data, "0100", mem_head);
ELSIF dsan_in /= '0' AND dsbn_in = '0' AND addr_int(1) = '1' THEN
wr_data(conv_integer(addr_int(11 DOWNTO 2)), data, "0010", mem_head);
ELSIF dsan_in = '0' AND dsbn_in /= '0' AND addr_int(1) = '1' THEN
wr_data(conv_integer(addr_int(11 DOWNTO 2)), data, "0001", mem_head);
ELSIF dsan_in = '0' AND dsbn_in = '0' AND addr_int(1) = '0' THEN
wr_data(conv_integer(addr_int(11 DOWNTO 2)), data, "1100", mem_head);
ELSIF dsan_in = '0' AND dsbn_in = '0' AND addr_int(1) = '1' THEN
wr_data(conv_integer(addr_int(11 DOWNTO 2)), data, "0011", mem_head);
END IF;
ELSE
data := data_in;
IF dsan_in = '0' AND dsbn_in = '0' AND addr_int(1) = '0' THEN
wr_data(conv_integer(addr_int(11 DOWNTO 2)), data, "1111", mem_head);
END IF;
END IF;
dtackn_out <= '0';
IF dsan_in = '0' THEN
WAIT until rising_edge(dsan_in);
END IF;
IF dsbn_in = '0' THEN
WAIT until rising_edge(dsbn_in);
END IF;
WAIT FOR 10 ns;
dtackn_out <= 'H';
END IF;
-- 0x0B, 0x0F, 0x3B, 0x3F => 32Bit Block Transfer
IF am_int = AM_A32_NONPRIV_BLT OR am_int = AM_A32_SUPER_BLT OR am_int = AM_A24_NONPRIV_BLT OR am_int = AM_A24_SUPER_BLT THEN
IF addr_int(0) = '0' THEN
addr_int := addr_int + 4;
ELSE
addr_int := addr_int + 2;
END IF;
END IF;
-- IACK-Cycle
ELSIF iackn = '0' THEN
IF iackn_in_int = '1' THEN
WAIT until (falling_edge(iackn_in_int) OR rising_edge(asn_in));
IF asn_in /= '0' THEN
exit;
END IF;
END IF;
sim_slave_active <= '1';
IF writen_in = '1' AND dsan_in = '0' AND dsbn_in /= '0' AND addr_int(0) = '1' THEN -- read iack D08
IF ((irq = 1 AND addr_int(3 DOWNTO 1) = "001") OR
(irq = 2 AND addr_int(3 DOWNTO 1) = "010") OR
(irq = 3 AND addr_int(3 DOWNTO 1) = "011") OR
(irq = 4 AND addr_int(3 DOWNTO 1) = "100") OR
(irq = 5 AND addr_int(3 DOWNTO 1) = "101") OR
(irq = 6 AND addr_int(3 DOWNTO 1) = "110") OR
(irq = 7 AND addr_int(3 DOWNTO 1) = "111")) THEN
WAIT FOR time_26;
data_out(7 DOWNTO 0) <= irq_id(irq); -- B(0)
data_out(31 DOWNTO 8) <= (OTHERS => '0');
WAIT FOR time_27;
irq_out <= (OTHERS => 'H');
irq := 0;
dtackn_out <= '0';
IF dsan_in = '0' THEN
WAIT until rising_edge(dsan_in);
END IF;
data_out <= (OTHERS => 'H');
WAIT FOR 10 ns;
dtackn_out <= 'H';
ELSE
WAIT until rising_edge(asn_in);
END IF;
ELSIF writen_in = '1' AND dsan_in = '0' AND dsbn_in = '0' AND addr_int(0) = '1' THEN -- read iack D16
IF ((irq = 1 AND addr_int(3 DOWNTO 1) = "001") OR
(irq = 2 AND addr_int(3 DOWNTO 1) = "010") OR
(irq = 3 AND addr_int(3 DOWNTO 1) = "011") OR
(irq = 4 AND addr_int(3 DOWNTO 1) = "100") OR
(irq = 5 AND addr_int(3 DOWNTO 1) = "101") OR
(irq = 6 AND addr_int(3 DOWNTO 1) = "110") OR
(irq = 7 AND addr_int(3 DOWNTO 1) = "111")) THEN
WAIT FOR time_26;
data_out(7 DOWNTO 0) <= irq_id(irq); -- B(0)
data_out(15 DOWNTO 8) <= irq_id(irq); -- B(0)
data_out(31 DOWNTO 16) <= (OTHERS => '0');
WAIT FOR time_27;
irq_out <= (OTHERS => 'H');
irq := 0;
dtackn_out <= '0';
IF dsan_in = '0' THEN
WAIT until rising_edge(dsan_in);
END IF;
data_out <= (OTHERS => 'H');
WAIT FOR 10 ns;
dtackn_out <= 'H';
ELSE
WAIT until rising_edge(asn_in);
END IF;
ELSIF writen_in = '1' AND dsan_in = '0' AND dsbn_in = '0' AND addr_int(0) = '1' THEN -- read iack D32
IF ((irq = 1 AND addr_int(3 DOWNTO 1) = "001") OR
(irq = 2 AND addr_int(3 DOWNTO 1) = "010") OR
(irq = 3 AND addr_int(3 DOWNTO 1) = "011") OR
(irq = 4 AND addr_int(3 DOWNTO 1) = "100") OR
(irq = 5 AND addr_int(3 DOWNTO 1) = "101") OR
(irq = 6 AND addr_int(3 DOWNTO 1) = "110") OR
(irq = 7 AND addr_int(3 DOWNTO 1) = "111")) THEN
WAIT FOR time_26;
data_out(7 DOWNTO 0) <= irq_id(irq); -- B(0)
data_out(15 DOWNTO 8) <= irq_id(irq); -- B(0)
data_out(23 DOWNTO 16) <= irq_id(irq); -- B(0)
data_out(31 DOWNTO 24) <= irq_id(irq); -- B(0)
WAIT FOR time_27;
irq_out <= (OTHERS => 'H');
irq := 0;
dtackn_out <= '0';
IF dsan_in = '0' THEN
WAIT until rising_edge(dsan_in);
END IF;
data_out <= (OTHERS => 'H');
WAIT FOR 10 ns;
dtackn_out <= 'H';
ELSE
WAIT until rising_edge(asn_in);
END IF;
ELSE
print("vme_sim: For IRQH D08(O) dsan=0, dsbn=1, writen=1, lwordn=1!");
ASSERT FALSE REPORT " Funktionsfehler! " SEVERITY error;
END IF;
ELSE -- if this slave is not addressed
WAIT until rising_edge(asn_in);
END IF;
sim_slave_active <= '0';
END LOOP;
END LOOP;
END PROCESS slave;
END vme_sim_slave_arch;
|
gpl-3.0
|
e2904b28ee44fd1f6078ef6e859175c2
| 0.441429 | 3.726564 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/altera_lnsim/ama_data_split_reg_ext_function/_primary.vhd
| 5 | 4,463 |
library verilog;
use verilog.vl_types.all;
entity ama_data_split_reg_ext_function is
generic(
width_data_in : integer := 1;
width_data_out : vl_notype;
register_clock_0: string := "UNREGISTERED";
register_aclr_0 : string := "NONE";
register_clock_1: string := "UNREGISTERED";
register_aclr_1 : string := "NONE";
register_clock_2: string := "UNREGISTERED";
register_aclr_2 : string := "NONE";
register_clock_3: string := "UNREGISTERED";
register_aclr_3 : string := "NONE";
number_of_multipliers: integer := 1;
port_sign : string := "PORT_UNUSED";
latency : integer := 0;
latency_clock_0 : string := "UNREGISTERED";
latency_aclr_0 : string := "NONE";
latency_clock_1 : string := "UNREGISTERED";
latency_aclr_1 : string := "NONE";
latency_clock_2 : string := "UNREGISTERED";
latency_aclr_2 : string := "NONE";
latency_clock_3 : string := "UNREGISTERED";
latency_aclr_3 : string := "NONE";
width_data_in_msb: vl_notype;
width_data_in_total_msb: vl_notype;
width_data_out_msb: vl_notype;
width_data_in_0_msb: vl_notype;
width_data_in_0_lsb: integer := 0;
width_data_in_1_msb: vl_notype;
width_data_in_1_lsb: vl_notype;
width_data_in_2_msb: vl_notype;
width_data_in_2_lsb: vl_notype;
width_data_in_3_msb: vl_notype;
width_data_in_3_lsb: vl_notype
);
port(
clock : in vl_logic_vector(3 downto 0);
aclr : in vl_logic_vector(3 downto 0);
ena : in vl_logic_vector(3 downto 0);
sign : in vl_logic;
data_in : in vl_logic_vector;
data_out_0 : out vl_logic_vector;
data_out_1 : out vl_logic_vector;
data_out_2 : out vl_logic_vector;
data_out_3 : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width_data_in : constant is 1;
attribute mti_svvh_generic_type of width_data_out : constant is 3;
attribute mti_svvh_generic_type of register_clock_0 : constant is 1;
attribute mti_svvh_generic_type of register_aclr_0 : constant is 1;
attribute mti_svvh_generic_type of register_clock_1 : constant is 1;
attribute mti_svvh_generic_type of register_aclr_1 : constant is 1;
attribute mti_svvh_generic_type of register_clock_2 : constant is 1;
attribute mti_svvh_generic_type of register_aclr_2 : constant is 1;
attribute mti_svvh_generic_type of register_clock_3 : constant is 1;
attribute mti_svvh_generic_type of register_aclr_3 : constant is 1;
attribute mti_svvh_generic_type of number_of_multipliers : constant is 1;
attribute mti_svvh_generic_type of port_sign : constant is 1;
attribute mti_svvh_generic_type of latency : constant is 1;
attribute mti_svvh_generic_type of latency_clock_0 : constant is 1;
attribute mti_svvh_generic_type of latency_aclr_0 : constant is 1;
attribute mti_svvh_generic_type of latency_clock_1 : constant is 1;
attribute mti_svvh_generic_type of latency_aclr_1 : constant is 1;
attribute mti_svvh_generic_type of latency_clock_2 : constant is 1;
attribute mti_svvh_generic_type of latency_aclr_2 : constant is 1;
attribute mti_svvh_generic_type of latency_clock_3 : constant is 1;
attribute mti_svvh_generic_type of latency_aclr_3 : constant is 1;
attribute mti_svvh_generic_type of width_data_in_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_in_total_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_out_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_in_0_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_in_0_lsb : constant is 1;
attribute mti_svvh_generic_type of width_data_in_1_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_in_1_lsb : constant is 3;
attribute mti_svvh_generic_type of width_data_in_2_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_in_2_lsb : constant is 3;
attribute mti_svvh_generic_type of width_data_in_3_msb : constant is 3;
attribute mti_svvh_generic_type of width_data_in_3_lsb : constant is 3;
end ama_data_split_reg_ext_function;
|
mit
|
ba6802abc13a0c61a8aa0086d3332c66
| 0.6406 | 3.427803 | false | false | false | false |
straywarrior/MadeCPUin21days
|
MEM_WB_REG.vhd
| 1 | 1,854 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: StrayWarrior
--
-- Create Date: 14:18:20 11/14/2015
-- Design Name:
-- Module Name: MEM_WB_REG - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MEM_WB_REG is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
RegWE_in : in STD_LOGIC;
RegDest_in : in STD_LOGIC_VECTOR (3 downto 0);
RegWriteVal_in : in STD_LOGIC_VECTOR (15 downto 0);
MemRd_in : in STD_LOGIC;
RegWE_out : out STD_LOGIC;
RegDest_out : out STD_LOGIC_VECTOR (3 downto 0);
RegWriteVal_out : out STD_LOGIC_VECTOR (15 downto 0);
MemRd_out : out STD_LOGIC
);
end MEM_WB_REG;
architecture Behavioral of MEM_WB_REG is
begin
process (reset, clk)
begin
if (reset = '0') then
RegWE_out <= '0';
RegDest_out <= (others => '1');
RegWriteVal_out <= (others => '0');
MemRd_out <= '0';
elsif (clk'event and clk = '1') then
RegWE_out <= RegWE_in;
RegDest_out <= RegDest_in;
RegWriteVal_out <= RegWriteVal_in;
MemRd_out <= MemRd_in;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
d1c422dad0f3d32dcc9cac258ae80682
| 0.53452 | 3.961538 | false | false | false | false |
nkkav/color_maker-s3esk
|
color_maker_top.vhd
| 1 | 3,132 |
library IEEE;
use IEEE.std_logic_1164.all;
entity color_maker_top is
port (
clk : in std_logic;
rst : in std_logic;
sldsw : in std_logic_vector(2 downto 0);
red : out std_logic;
green : out std_logic;
blue : out std_logic;
vs : out std_logic;
hs : out std_logic
);
end color_maker_top;
architecture top_level of color_maker_top is
--
-- Component declarations
component vga_controller is
generic (
H_S : integer := 800;
H_DISP : integer := 640;
H_FP : integer := 16;
H_PW : integer := 96;
H_BP : integer := 48;
V_S : integer := 521;
V_DISP : integer := 480;
V_FP : integer := 10;
V_PW : integer := 2;
V_BP : integer := 29
);
port (
clk : in std_logic;
rst : in std_logic;
hs : out std_logic;
vs : out std_logic;
blank : out std_logic;
hpix : out std_logic_vector(9 downto 0); -- horizontal coordinate
vpix : out std_logic_vector(9 downto 0) -- vertical coordinate
);
end component;
--
component color_maker is
port (
sldsw : in std_logic_vector(2 downto 0);
red : out std_logic;
green : out std_logic;
blue : out std_logic
);
end component;
--
component clockdiv
generic (
DIVPARAM : integer := 5_000_000
);
port (
clk_i : in std_logic;
rst : in std_logic;
clk_o : out std_logic
);
end component;
--
-- Signal declarations
signal clkdiv2 : std_logic;
signal hsSig : std_logic;
signal vsSig : std_logic;
signal redSig : std_logic;
signal greenSig : std_logic;
signal blueSig : std_logic;
signal vidonSig : std_logic;
signal hdrawSig : std_logic_vector(9 downto 0);
signal vdrawSig : std_logic_vector(9 downto 0);
--
begin
clockdiv_vga_instance : clockdiv
generic map (
DIVPARAM => 2
)
port map (
clk_i => clk,
rst => rst,
clk_o => clkdiv2
);
vgaSync_instance : vga_controller
generic map (
-- H_S => 1040,
-- H_DISP => 800,
-- H_FP => 56,
-- H_PW => 120,
-- H_BP => 64,
-- V_S => 666,
-- V_DISP => 600,
-- V_FP => 37,
-- V_PW => 6,
-- V_BP => 23
H_S => 800,
H_DISP => 640,
H_FP => 16,
H_PW => 96,
H_BP => 48,
V_S => 521,
V_DISP => 480,
V_FP => 10,
V_PW => 2,
V_BP => 29
)
port map (
clk => clkdiv2,
-- clk => clk,
rst => rst,
hs => hsSig,
vs => vsSig,
blank => vidonSig,
hpix => hdrawSig,
vpix => vdrawSig
);
color_maker_instance : color_maker
port map (
sldsw => sldsw,
red => redSig,
green => greenSig,
blue => blueSig
);
hs <= hsSig;
vs <= vsSig;
red <= redSig and vidonSig;
green <= greenSig and vidonSig;
blue <= blueSig and vidonSig;
end top_level;
|
bsd-3-clause
|
f2b4ad3052518777b8ab6bfd2f0d8f71
| 0.48659 | 3.199183 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/db/alt_dspbuilder_counter.vhd
| 2 | 5,666 |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_counter is
generic (
USE_USR_ACLR : string := "false";
USE_ENA : string := "false";
USE_CIN : string := "false";
USE_SSET : string := "false";
NDIRECTION : natural := 1;
SVALUE : string := "0";
USE_SLOAD : string := "false";
USE_SCLR : string := "false";
USE_COUT : string := "false";
MODULUS : integer := 256;
USE_CNT_ENA : string := "false";
WIDTH : natural := 8;
USE_ASET : string := "false";
USE_ALOAD : string := "false";
AVALUE : string := "0"
);
port (
user_aclr : in std_logic := '0';
clock : in std_logic := '0';
q : out std_logic_vector(width-1 downto 0);
direction : in std_logic := '0';
sclr : in std_logic := '0';
data : in std_logic_vector(width-1 downto 0) := (others=>'0');
aset : in std_logic := '0';
cout : out std_logic;
sset : in std_logic := '0';
aclr : in std_logic := '0';
cnt_ena : in std_logic := '0';
cin : in std_logic := '0';
ena : in std_logic := '0';
aload : in std_logic := '0';
sload : in std_logic := '0'
);
end entity alt_dspbuilder_counter;
architecture rtl of alt_dspbuilder_counter is
component alt_dspbuilder_counter_GNZKRIGTBB is
generic (
USE_USR_ACLR : string := "false";
USE_ENA : string := "false";
USE_CIN : string := "false";
USE_SSET : string := "false";
NDIRECTION : natural := 1;
SVALUE : string := "1";
USE_SLOAD : string := "true";
USE_SCLR : string := "false";
USE_COUT : string := "false";
MODULUS : integer := 65536;
USE_CNT_ENA : string := "true";
WIDTH : natural := 24;
USE_ASET : string := "false";
USE_ALOAD : string := "false";
AVALUE : string := "0"
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
cnt_ena : in std_logic := '0';
cout : out std_logic;
data : in std_logic_vector(24-1 downto 0) := (others=>'0');
q : out std_logic_vector(24-1 downto 0);
sload : in std_logic := '0'
);
end component alt_dspbuilder_counter_GNZKRIGTBB;
component alt_dspbuilder_counter_GNKAA2ZBZG is
generic (
USE_USR_ACLR : string := "false";
USE_ENA : string := "false";
USE_CIN : string := "false";
USE_SSET : string := "false";
NDIRECTION : natural := 1;
SVALUE : string := "1";
USE_SLOAD : string := "false";
USE_SCLR : string := "true";
USE_COUT : string := "false";
MODULUS : integer := 8388608;
USE_CNT_ENA : string := "true";
WIDTH : natural := 24;
USE_ASET : string := "false";
USE_ALOAD : string := "false";
AVALUE : string := "0"
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
cnt_ena : in std_logic := '0';
cout : out std_logic;
q : out std_logic_vector(24-1 downto 0);
sclr : in std_logic := '0'
);
end component alt_dspbuilder_counter_GNKAA2ZBZG;
begin
alt_dspbuilder_counter_GNZKRIGTBB_0: if ((USE_USR_ACLR = "false") and (USE_ENA = "false") and (USE_CIN = "false") and (USE_SSET = "false") and (NDIRECTION = 1) and (SVALUE = "1") and (USE_SLOAD = "true") and (USE_SCLR = "false") and (USE_COUT = "false") and (MODULUS = 65536) and (USE_CNT_ENA = "true") and (WIDTH = 24) and (USE_ASET = "false") and (USE_ALOAD = "false") and (AVALUE = "0")) generate
inst_alt_dspbuilder_counter_GNZKRIGTBB_0: alt_dspbuilder_counter_GNZKRIGTBB
generic map(USE_USR_ACLR => "false", USE_ENA => "false", USE_CIN => "false", USE_SSET => "false", NDIRECTION => 1, SVALUE => "1", USE_SLOAD => "true", USE_SCLR => "false", USE_COUT => "false", MODULUS => 65536, USE_CNT_ENA => "true", WIDTH => 24, USE_ASET => "false", USE_ALOAD => "false", AVALUE => "0")
port map(aclr => aclr, clock => clock, cnt_ena => cnt_ena, cout => cout, data => data, q => q, sload => sload);
end generate;
alt_dspbuilder_counter_GNKAA2ZBZG_1: if ((USE_USR_ACLR = "false") and (USE_ENA = "false") and (USE_CIN = "false") and (USE_SSET = "false") and (NDIRECTION = 1) and (SVALUE = "1") and (USE_SLOAD = "false") and (USE_SCLR = "true") and (USE_COUT = "false") and (MODULUS = 8388608) and (USE_CNT_ENA = "true") and (WIDTH = 24) and (USE_ASET = "false") and (USE_ALOAD = "false") and (AVALUE = "0")) generate
inst_alt_dspbuilder_counter_GNKAA2ZBZG_1: alt_dspbuilder_counter_GNKAA2ZBZG
generic map(USE_USR_ACLR => "false", USE_ENA => "false", USE_CIN => "false", USE_SSET => "false", NDIRECTION => 1, SVALUE => "1", USE_SLOAD => "false", USE_SCLR => "true", USE_COUT => "false", MODULUS => 8388608, USE_CNT_ENA => "true", WIDTH => 24, USE_ASET => "false", USE_ALOAD => "false", AVALUE => "0")
port map(aclr => aclr, clock => clock, cnt_ena => cnt_ena, cout => cout, q => q, sclr => sclr);
end generate;
assert not (((USE_USR_ACLR = "false") and (USE_ENA = "false") and (USE_CIN = "false") and (USE_SSET = "false") and (NDIRECTION = 1) and (SVALUE = "1") and (USE_SLOAD = "true") and (USE_SCLR = "false") and (USE_COUT = "false") and (MODULUS = 65536) and (USE_CNT_ENA = "true") and (WIDTH = 24) and (USE_ASET = "false") and (USE_ALOAD = "false") and (AVALUE = "0")) or ((USE_USR_ACLR = "false") and (USE_ENA = "false") and (USE_CIN = "false") and (USE_SSET = "false") and (NDIRECTION = 1) and (SVALUE = "1") and (USE_SLOAD = "false") and (USE_SCLR = "true") and (USE_COUT = "false") and (MODULUS = 8388608) and (USE_CNT_ENA = "true") and (WIDTH = 24) and (USE_ASET = "false") and (USE_ALOAD = "false") and (AVALUE = "0")))
report "Please run generate again" severity error;
end architecture rtl;
|
mit
|
5899c74a752b059db1206e7529aaa80b
| 0.613837 | 2.934231 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_cast_GN5EYRLJQW.vhd
| 4 | 857 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GN5EYRLJQW is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(24 downto 0);
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GN5EYRLJQW is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 25 ,
width_inr=> 0,
width_outl=> 24,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(24 downto 0) => input,
yout => output
);
end architecture;
|
mit
|
4a2fa56aa3cffedeff581ac41ed77ed3
| 0.65811 | 3.105072 | false | false | false | false |
bobxiv/DispositivosLogicosProgramables-FICH
|
Proyecto 1 DLP TP Calculadora/Src/InputModuleTest.vhd
| 1 | 4,102 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:27:52 10/09/2011
-- Design Name:
-- Module Name: C:/Users/BOB/Calculadora/Source/InputModuleTest.vhd
-- Project Name: Calculadora
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: InputFSM
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY CalculadoraTest IS
END CalculadoraTest;
ARCHITECTURE behavior OF CalculadoraTest IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT CalculadoraFSM
PORT(
input : IN std_logic;
clock : IN std_logic;
reset : IN std_logic;
output : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal input : std_logic := '0';
signal clock : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal output : std_logic_vector(15 downto 0);
-- Clock period definitions
constant clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: CalculadoraFSM PORT MAP (
input => input,
clock => clock,
reset => reset,
output => output
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
--wait for 100 ns;
-- Prueba de Multiplicacion: Resultado esperado 100100 -> Osea 36
-- bcd 1001 -> Osea 9
input <='1';
wait for 10 ns;
input <='0';
wait for 10 ns;
input <='0';
wait for 10 ns;
input <='1';
wait for 10 ns;
-- operacion Multiplicacion 10
input <='0';
wait for 10 ns;
input <='1';
wait for 10 ns;
-- bcd 0100 -> Osea 4
input <='0';
wait for 10 ns;
input <='0';
wait for 10 ns;
input <='1';
wait for 10 ns;
input <='0';
wait for 10 ns;
wait for 180 ns;-- Necesitamos un ciclo para realizar los calculos
-- y dejar 10 ns para mostrar los resultados
reset <= '1';--Reseteamos
wait for 10 ns;
reset <= '0';
-- Prueba de Suma: Resultado esperado 0011 -> Osea 3
-- bcd 0001 -> Osea 1
input <='1';
wait for 10 ns;
input <='0';
wait for 10 ns;
input <='0';
wait for 10 ns;
input <='0';
wait for 10 ns;
-- operacion Suma 00
input <='0';
wait for 10 ns;
input <='0';
wait for 10 ns;
-- bcd 0010 -> Osea 2
input <='0';
wait for 10 ns;
input <='1';
wait for 10 ns;
input <='0';
wait for 10 ns;
input <='0';
wait for 10 ns;
wait for 180 ns;-- Necesitamos un ciclo para realizar los calculos
-- y dejar 10 ns para mostrar los resultados
reset <= '1';--Reseteamos
wait for 10 ns;
reset <= '0';
-- Prueba de Resta: Resultado esperado 0010 -> Osea 2
-- bcd 0101 -> Osea 5
input <='1';
wait for 10 ns;
input <='0';
wait for 10 ns;
input <='1';
wait for 10 ns;
input <='0';
wait for 10 ns;
-- operacion Resta 01
input <='1';
wait for 10 ns;
input <='0';
wait for 10 ns;
-- bcd 0011 -> Osea 3
input <='1';
wait for 10 ns;
input <='1';
wait for 10 ns;
input <='0';
wait for 10 ns;
input <='0';
wait for 10 ns;
wait for clock_period*10;
-- insert stimulus here
wait;
end process;
END;
|
gpl-3.0
|
63a6de8b888324effd75f53e3a7fe5bb
| 0.559483 | 3.551515 | false | false | false | false |
freecores/t48
|
rtl/vhdl/system/t8048_notri.vhd
| 1 | 8,377 |
-------------------------------------------------------------------------------
--
-- T8048 Microcontroller System
-- 8048 toplevel without tri-states
--
-- $Id: t8048_notri.vhd,v 1.7 2006-07-14 01:13:32 arniml Exp $
-- $Name: not supported by cvs2svn $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity t8048_notri is
generic (
gate_port_input_g : integer := 1
);
port (
xtal_i : in std_logic;
xtal_en_i : in std_logic;
reset_n_i : in std_logic;
t0_i : in std_logic;
t0_o : out std_logic;
t0_dir_o : out std_logic;
int_n_i : in std_logic;
ea_i : in std_logic;
rd_n_o : out std_logic;
psen_n_o : out std_logic;
wr_n_o : out std_logic;
ale_o : out std_logic;
db_i : in std_logic_vector( 7 downto 0);
db_o : out std_logic_vector( 7 downto 0);
db_dir_o : out std_logic;
t1_i : in std_logic;
p2_i : in std_logic_vector( 7 downto 0);
p2_o : out std_logic_vector( 7 downto 0);
p2l_low_imp_o : out std_logic;
p2h_low_imp_o : out std_logic;
p1_i : in std_logic_vector( 7 downto 0);
p1_o : out std_logic_vector( 7 downto 0);
p1_low_imp_o : out std_logic;
prog_n_o : out std_logic
);
end t8048_notri;
library ieee;
use ieee.numeric_std.all;
use work.t48_core_comp_pack.t48_core;
use work.t48_core_comp_pack.t48_rom;
use work.t48_core_comp_pack.generic_ram_ena;
architecture struct of t8048_notri is
-- Address width of internal ROM
constant rom_addr_width_c : natural := 10;
signal xtal3_s : std_logic;
signal dmem_addr_s : std_logic_vector( 7 downto 0);
signal dmem_we_s : std_logic;
signal dmem_data_from_s : std_logic_vector( 7 downto 0);
signal dmem_data_to_s : std_logic_vector( 7 downto 0);
signal pmem_addr_s : std_logic_vector(11 downto 0);
signal pmem_data_s : std_logic_vector( 7 downto 0);
signal ea_s : std_logic;
signal p1_in_s,
p1_out_s : std_logic_vector( 7 downto 0);
signal p2_in_s,
p2_out_s : std_logic_vector( 7 downto 0);
signal vdd_s : std_logic;
begin
vdd_s <= '1';
-----------------------------------------------------------------------------
-- Check generics for valid values.
-----------------------------------------------------------------------------
-- pragma translate_off
assert gate_port_input_g = 0 or gate_port_input_g = 1
report "gate_port_input_g must be either 1 or 0!"
severity failure;
-- pragma translate_on
t48_core_b : t48_core
generic map (
xtal_div_3_g => 1,
register_mnemonic_g => 1,
include_port1_g => 1,
include_port2_g => 1,
include_bus_g => 1,
include_timer_g => 1,
sample_t1_state_g => 4
)
port map (
xtal_i => xtal_i,
xtal_en_i => xtal_en_i,
reset_i => reset_n_i,
t0_i => t0_i,
t0_o => t0_o,
t0_dir_o => t0_dir_o,
int_n_i => int_n_i,
ea_i => ea_s,
rd_n_o => rd_n_o,
psen_n_o => psen_n_o,
wr_n_o => wr_n_o,
ale_o => ale_o,
db_i => db_i,
db_o => db_o,
db_dir_o => db_dir_o,
t1_i => t1_i,
p2_i => p2_in_s,
p2_o => p2_out_s,
p2l_low_imp_o => p2l_low_imp_o,
p2h_low_imp_o => p2h_low_imp_o,
p1_i => p1_in_s,
p1_o => p1_out_s,
p1_low_imp_o => p1_low_imp_o,
prog_n_o => prog_n_o,
clk_i => xtal_i,
en_clk_i => xtal3_s,
xtal3_o => xtal3_s,
dmem_addr_o => dmem_addr_s,
dmem_we_o => dmem_we_s,
dmem_data_i => dmem_data_from_s,
dmem_data_o => dmem_data_to_s,
pmem_addr_o => pmem_addr_s,
pmem_data_i => pmem_data_s
);
-----------------------------------------------------------------------------
-- Gate port 1 and 2 input bus with respetive output value
-----------------------------------------------------------------------------
gate_ports: if gate_port_input_g = 1 generate
p1_in_s <= p1_i and p1_out_s;
p2_in_s <= p2_i and p2_out_s;
end generate;
pass_ports: if gate_port_input_g = 0 generate
p1_in_s <= p1_i;
p2_in_s <= p2_i;
end generate;
p1_o <= p1_out_s;
p2_o <= p2_out_s;
-----------------------------------------------------------------------------
-- Process ea
--
-- Purpose:
-- Detects access to external program memory.
-- Either by ea_i = '1' or when program memory address leaves address
-- range of internal ROM.
--
ea: process (ea_i,
pmem_addr_s)
begin
if ea_i = '1' then
-- Forced external access
ea_s <= '1';
elsif unsigned(pmem_addr_s(11 downto rom_addr_width_c)) = 0 then
-- Internal access
ea_s <= '0';
else
-- Access to program memory out of internal range
ea_s <= '1';
end if;
end process ea;
--
-----------------------------------------------------------------------------
rom_1k_b : t48_rom
port map (
clk_i => xtal_i,
rom_addr_i => pmem_addr_s(rom_addr_width_c-1 downto 0),
rom_data_o => pmem_data_s
);
ram_64_b : generic_ram_ena
generic map (
addr_width_g => 6,
data_width_g => 8
)
port map (
clk_i => xtal_i,
a_i => dmem_addr_s(5 downto 0),
we_i => dmem_we_s,
ena_i => vdd_s,
d_i => dmem_data_to_s,
d_o => dmem_data_from_s
);
end struct;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.6 2006/06/21 01:02:16 arniml
-- replaced syn_rom and syn_ram with t48_rom and generic_ram_ena
--
-- Revision 1.5 2006/06/20 00:47:08 arniml
-- new input xtal_en_i
--
-- Revision 1.4 2005/11/01 21:38:48 arniml
-- wire signals for P2 low impedance marker issue
--
-- Revision 1.3 2004/12/02 22:08:42 arniml
-- introduced generic gate_port_input_g
-- forces masking of P1 and P2 input bus
--
-- Revision 1.2 2004/12/01 23:08:08 arniml
-- update
--
-------------------------------------------------------------------------------
|
gpl-2.0
|
ef8bb6f3b00f3618139d3dd9f5fee266
| 0.527755 | 3.358861 | false | false | false | false |
sukinull/hls_stream
|
Vivado/example.hls/example.hls.srcs/sources_1/ipshared/avnet/zed_hdmi_out_v2_0/401115cc/hdl/vhdl/zed_hdmi_out.vhd
| 1 | 9,391 |
------------------------------------------------------------------
-- _____
-- / \
-- /____ \____
-- / \===\ \==/
-- /___\===\___\/ AVNET
-- \======/
-- \====/
-----------------------------------------------------------------
--
-- This design is the property of Avnet. Publication of this
-- design is not authorized without written consent from Avnet.
--
-- Please direct any questions to: [email protected]
--
-- Disclaimer:
-- Avnet, Inc. makes no warranty for the use of this code or design.
-- This code is provided "As Is". Avnet, Inc assumes no responsibility for
-- any errors, which may appear in this code, nor does it make a commitment
-- to update the information contained herein. Avnet, Inc specifically
-- disclaims any implied warranties of fitness for a particular purpose.
-- Copyright(c) 2011 Avnet, Inc.
-- All rights reserved.
--
------------------------------------------------------------------
--
-- Create Date: May 19, 2012
-- Design Name: ZedBoard HDMI Output
-- Module Name: zed_hdmi_out.vhd
-- Project Name: ZedBoard HDMI Output
-- Target Devices: Zynq-7000
--
-- Tool versions: ISE 14.3
--
-- Description: ZedBoard HDMI output interface.
--
-- Dependencies:
--
-- Revision: May 19, 2012: 1.02 Initial version
-- Dec 21, 2012: 2.01 Remove XSVI bus interface
-- Remove xsvi_ prefixes to video_
-- Rename active_video to de
-- Change IP_GROUP to FMC-IMAGEON
--
------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity zed_hdmi_out is
Generic
(
C_DATA_WIDTH : integer := 16;
C_FAMILY : string := "virtex6"
);
Port
(
clk : in std_logic;
reset : in std_logic;
-- Audio Input Port
audio_spdif : in std_logic;
-- Video Ports
video_vsync : in std_logic;
video_hsync : in std_logic;
video_de : in std_logic;
video_data : in std_logic_vector((C_DATA_WIDTH-1) downto 0);
-- I/O pins
io_hdmio_spdif : out std_logic;
io_hdmio_video : out std_logic_vector(15 downto 0);
io_hdmio_vsync : out std_logic;
io_hdmio_hsync : out std_logic;
io_hdmio_de : out std_logic;
io_hdmio_clk : out std_logic
);
end zed_hdmi_out;
architecture rtl of zed_hdmi_out is
signal clk_n : std_logic;
signal net0 : std_logic;
signal net1 : std_logic;
signal oe : std_logic;
signal oe_n : std_logic;
--
-- Audio Port
--
signal spdif_r : std_logic;
--
-- Video Port
--
signal video_r : std_logic_vector(15 downto 0);
signal vsync_r : std_logic;
signal hsync_r : std_logic;
signal de_r : std_logic;
--
-- IOB Registers
--
signal hdmi_spdif_o : std_logic;
signal hdmi_video_o : std_logic_vector(15 downto 0);
signal hdmi_vsync_o : std_logic;
signal hdmi_hsync_o : std_logic;
signal hdmi_de_o : std_logic;
signal hdmi_clk_o : std_logic;
signal hdmi_spdif_t : std_logic;
signal hdmi_video_t : std_logic_vector(15 downto 0);
signal hdmi_vsync_t : std_logic;
signal hdmi_hsync_t : std_logic;
signal hdmi_de_t : std_logic;
signal hdmi_clk_t : std_logic;
attribute IOB : string;
attribute IOB of hdmi_spdif_o : signal is "TRUE";
attribute IOB of hdmi_video_o : signal is "TRUE";
attribute IOB of hdmi_vsync_o : signal is "TRUE";
attribute IOB of hdmi_hsync_o : signal is "TRUE";
attribute IOB of hdmi_de_o : signal is "TRUE";
attribute IOB of hdmi_clk_o : signal is "TRUE";
begin
clk_n <= not clk;
oe <= '1';
oe_n <= not oe;
net0 <= '0';
net1 <= '1';
--
-- Audio Port
--
spdif_r <= audio_spdif;
--
-- Video Ports
--
VIDEO_PORTS_16BIT_GEN : if (C_DATA_WIDTH = 16) generate
video_ports_16bit_iregs_l : process (clk)
begin
if Rising_Edge(clk) then
video_r <= video_data(15 downto 0);
vsync_r <= video_vsync;
hsync_r <= video_hsync;
de_r <= video_de;
end if;
end process;
end generate VIDEO_PORTS_16BIT_GEN;
--
-- IOB Registers
--
io_oregs_l : process (clk)
begin
if Rising_Edge(clk) then
hdmi_spdif_o <= spdif_r;
hdmi_video_o <= video_r;
hdmi_vsync_o <= vsync_r;
hdmi_hsync_o <= hsync_r;
hdmi_de_o <= de_r;
--
hdmi_spdif_t <= oe_n;
hdmi_video_t <= (others => oe_n);
hdmi_vsync_t <= oe_n;
hdmi_hsync_t <= oe_n;
hdmi_de_t <= oe_n;
end if;
end process;
S3ADSP_GEN : if (C_FAMILY = "spartan3adsp") generate
ODDR_hdmi_clk_o : ODDR2
generic map (
DDR_ALIGNMENT => "NONE", -- "NONE", "C0" or "C1"
INIT => '1', -- Sets initial state of Q
SRTYPE => "ASYNC") -- Reset type
port map (
Q => hdmi_clk_o,
C0 => clk,
C1 => clk_n,
CE => net1,
D0 => net0,
D1 => net1,
R => net0,
S => net0);
ODDR_hdmi_clk_t : ODDR2
generic map (
DDR_ALIGNMENT => "NONE", -- "NONE", "C0" or "C1"
INIT => '1', -- Sets initial state of Q
SRTYPE => "ASYNC") -- Reset type
port map (
Q => hdmi_clk_t,
C0 => clk,
C1 => clk_n,
CE => net1,
D0 => oe_n,
D1 => oe_n,
R => net0,
S => net0);
end generate S3ADSP_GEN;
S6_GEN : if (C_FAMILY = "spartan6") generate
ODDR_hdmi_clk_o : ODDR2
generic map (
DDR_ALIGNMENT => "C0", -- "NONE", "C0" or "C1"
INIT => '1', -- Sets initial state of Q
SRTYPE => "ASYNC") -- Reset type
port map (
Q => hdmi_clk_o,
C0 => clk,
C1 => clk_n,
CE => net1,
D0 => net0,
D1 => net1,
R => net0,
S => net0);
ODDR_hdmi_clk_t : ODDR2
generic map (
DDR_ALIGNMENT => "C0", -- "NONE", "C0" or "C1"
INIT => '1', -- Sets initial state of Q
SRTYPE => "ASYNC") -- Reset type
port map (
Q => hdmi_clk_t,
C0 => clk,
C1 => clk_n,
CE => net1,
D0 => oe_n,
D1 => oe_n,
R => net0,
S => net0);
end generate S6_GEN;
V6_GEN : if (C_FAMILY = "virtex6" or C_FAMILY = "zynq" or C_FAMILY = "kintex7" or C_FAMILY = "artix7" or C_FAMILY = "virtex7") generate
ODDR_hdmi_clk_o : ODDR
generic map (
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '1', -- Sets initial state of Q
SRTYPE => "ASYNC") -- Reset type
port map (
Q => hdmi_clk_o,
C => clk,
CE => net1,
D1 => net0,
D2 => net1,
R => net0,
S => net0);
ODDR_hdmi_clk_t : ODDR
generic map (
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '1', -- Sets initial state of Q
SRTYPE => "ASYNC") -- Reset type
port map (
Q => hdmi_clk_t,
C => clk,
CE => net1,
D1 => oe_n,
D2 => oe_n,
R => net0,
S => net0);
end generate V6_GEN;
--
-- Tri-stateable outputs
-- Can be used to disable outputs to FMC connector
-- until FMC module is correctly identified.
--
OBUFT_hdmio_spdif : OBUFT
port map (
O => io_hdmio_spdif,
I => hdmi_spdif_o,
T => hdmi_spdif_t
);
IO1: for I in 0 to 15 generate
OBUFT_hdmio_video : OBUFT
port map (
O => io_hdmio_video(I),
I => hdmi_video_o(I),
T => hdmi_video_t(I)
);
end generate IO1;
OBUFT_hdmio_vsync : OBUFT
port map (
O => io_hdmio_vsync,
I => hdmi_vsync_o,
T => hdmi_vsync_t
);
OBUFT_hdmio_hsync : OBUFT
port map (
O => io_hdmio_hsync,
I => hdmi_hsync_o,
T => hdmi_hsync_t
);
OBUFT_hdmio_de : OBUFT
port map (
O => io_hdmio_de,
I => hdmi_de_o,
T => hdmi_de_t
);
OBUFT_hdmio_clk : OBUFT
port map (
O => io_hdmio_clk,
I => hdmi_clk_o,
T => hdmi_clk_t
);
end rtl;
|
gpl-2.0
|
68591fd47d1c00681531acc0bf598682
| 0.459057 | 3.675538 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_sImpulseAltr.vhd
| 8 | 2,714 |
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sImpulseAltr is
generic (
Impulsedelay : positive ;
Impulsewidth : positive
);
port (
clock : in std_logic;
ena : in std_logic :='1';
sclr : in std_logic :='0';
aclr : in std_logic :='0';
user_aclr : in std_logic :='0';
q : out std_logic
);
end alt_dspbuilder_sImpulseAltr ;
architecture syn of alt_dspbuilder_sImpulseAltr is
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
g1:if Impulsewidth=1 generate
gr:if Impulsedelay=1 generate
u0: alt_dspbuilder_sImpulse11Altr port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate gr;
grr:if Impulsedelay>1 generate
u0: alt_dspbuilder_sImpulsen1Altr generic map (Impulsedelay=>Impulsedelay)
port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate grr;
end generate g1;
gn:if Impulsewidth>1 generate
gr:if Impulsedelay=1 generate
u0: alt_dspbuilder_sImpulse1nAltr generic map (Impulsewidth=>Impulsewidth)
port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate gr;
grr:if Impulsedelay>1 generate
u0: alt_dspbuilder_sImpulsennAltr generic map (Impulsedelay=>Impulsedelay, Impulsewidth=>Impulsewidth)
port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate grr;
end generate gn;
end syn;
|
mit
|
fe2bb8853e490a56f167d5fc8bf453a1
| 0.649226 | 3.905036 | false | false | false | false |
Ttl/bf_cpu
|
cache.vhd
| 1 | 4,014 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity cache is
Generic (WIDTH : natural := 13; -- Length of address
DWIDTH : natural := 13; -- Length of one entry
CACHE_SIZE : natural := 4); -- Log2 of number of entries in the cache
Port ( clk, reset : in STD_LOGIC;
addr : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
din : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
push : in STD_LOGIC;
valid : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR (DWIDTH-1 downto 0));
end cache;
architecture Behavioral of cache is
type cache_type_data is array(0 to 2**CACHE_SIZE-1) of std_logic_vector(DWIDTH-1 downto 0);
type cache_type_tag is array(0 to 2**CACHE_SIZE-1) of std_logic_vector(WIDTH-1 downto CACHE_SIZE);
signal last_used : std_logic_vector(2**CACHE_SIZE-1 downto 0);
signal valid0, valid1 : std_logic_vector(2**CACHE_SIZE-1 downto 0);
signal cache0_d, cache1_d : cache_type_data;
signal cache0_t, cache1_t : cache_type_tag;
begin
process(clk, reset, addr, din, push)
begin
if rising_edge(clk) then
if reset = '1' then
for I in 0 to 2**CACHE_SIZE-1 loop
valid0(to_integer(to_unsigned(I, CACHE_SIZE))) <= '0';
valid1(to_integer(to_unsigned(I, CACHE_SIZE))) <= '0';
end loop;
end if;
-- Write to free location or replace randomly
if push = '1' then
if valid0(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) = '0' then
cache0_t(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) <= addr(WIDTH-1 downto CACHE_SIZE);
cache0_d(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) <= din;
valid0(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) <= '1';
last_used(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) <= '0';
elsif valid1(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) = '0' then
cache1_t(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) <= addr(WIDTH-1 downto CACHE_SIZE);
cache1_d(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) <= din;
valid1(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) <= '1';
last_used(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) <= '1';
else
-- Both locations are already occupied so replace the least recently used
if last_used(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) = '0' then
cache1_t(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) <= addr(WIDTH-1 downto CACHE_SIZE);
cache1_d(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) <= din;
valid1(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) <= '1';
last_used(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) <= '1';
else
cache0_t(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) <= addr(WIDTH-1 downto CACHE_SIZE);
cache0_d(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) <= din;
valid0(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) <= '1';
last_used(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) <= '0';
end if;
end if;
end if;
-- Set output if tag matches and entry is valid
if valid0(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) = '1'
and cache0_t(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) = addr(WIDTH-1 downto CACHE_SIZE) then
valid <= '1';
dout <= cache0_d(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0))));
elsif valid1(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) = '1'
and cache1_t(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0)))) = addr(WIDTH-1 downto CACHE_SIZE) then
valid <= '1';
dout <= cache1_d(to_integer(unsigned(addr(CACHE_SIZE-1 downto 0))));
else
valid <= '0';
dout <= (others => '-');
end if;
end if;
end process;
end Behavioral;
|
lgpl-3.0
|
7c5ae25cb187142217b4015718fff3e3
| 0.604883 | 3.342215 | false | false | false | false |
nkkav/color_maker-s3esk
|
vgactrl.vhd
| 1 | 4,561 |
-- Original source:
-- Mike Field
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--
-- VGA configuration parameters
--
-------------------------------------------
-- CONFIG #1: 640x480 @ 60Hz
-- Clock: 25MHz
-- ----------------------------------------
-- Name Description Cycles
-- ----------------------------------------
-- H_S Horizontal sync pulse 800
-- H_DISP Horizontal display 640
-- H_FP Horizontal front porch 16
-- H_PW Horizontal pulse width 96
-- H_BP Horizontal back porch 48
-- V_S Vertical sync pulse 521
-- V_DISP Vertical display 480
-- V_FP Vertical front porch 10
-- V_PW Vertical pulse width 2
-- V_BP Vertical back porch 29
-- ----------------------------------------
--
-------------------------------------------
-- CONFIG #2: 800x600 @ 72Hz
-- Clock: 50MHz
-- ----------------------------------------
-- Name Description Cycles
-- ----------------------------------------
-- H_S Horizontal sync pulse 1040
-- H_DISP Horizontal display 800
-- H_FP Horizontal front porch 56
-- H_PW Horizontal pulse width 120
-- H_BP Horizontal back porch 64
-- V_S Vertical sync pulse 666
-- V_DISP Vertical display 600
-- V_FP Vertical front porch 37
-- V_PW Vertical pulse width 6
-- V_BP Vertical back porch 23
-- ----------------------------------------
entity vga_controller is
generic (
-- horizontal timing
-- sync pulse
H_S : integer := 800;
-- display
H_DISP : integer := 640;
-- front porch
H_FP : integer := 16;
-- pulse width
H_PW : integer := 96;
-- back porch
H_BP : integer := 48;
-- vertical timing
-- sync pulse
V_S : integer := 521;
-- display
V_DISP : integer := 480;
-- front porch
V_FP : integer := 10;
-- pulse width
V_PW : integer := 2;
-- back porch
V_BP : integer := 29
);
port (
clk : in std_logic; -- assuming a clock of 25MHz
rst : in std_logic; -- reset (synchronous)
hs : out std_logic; -- Horizontal sync pulse. Active low
vs : out std_logic; -- Vertical sync pulse. Active low
blank : out std_logic; -- Blanking interval indicator. Active low.
-- Color to monitor should be black when active
-- (ie, AND this signal with your color signals).
hpix : out std_logic_vector(9 downto 0); -- horizontal coordinate
vpix : out std_logic_vector(9 downto 0) -- vertical coordinate
);
end vga_controller;
architecture behavioral of vga_controller is
--
-- Constants
constant hVisible : natural := H_DISP;
constant hSyncStart : natural := H_DISP+H_FP;
constant hSyncEnd : natural := H_DISP+H_FP+H_PW;
constant hTotalCount : natural := H_DISP+H_FP+H_PW+H_BP;
constant vVisible : natural := V_DISP;
constant vSyncStart : natural := V_DISP+V_FP;
constant vSyncEnd : natural := V_DISP+V_FP+V_PW;
constant vTotalCount : natural := V_DISP+V_FP+V_PW+V_BP;
--
-- Signals
signal nextHsync : std_logic;
signal nextVsync : std_logic;
signal vCounter : unsigned(10 downto 0) := (others => '0');
signal hCounter : unsigned(11 downto 0) := (others => '0');
--
begin
process (clk)
begin
if rising_edge(clk) then
hs <= nextHsync;
vs <= nextVsync;
hpix <= std_logic_vector(hCounter(9 downto 0));
vpix <= std_logic_vector(vCounter(9 downto 0));
--
if ((hCounter < hVisible) and (vCounter < vVisible)) then
blank <= '1';
else
blank <= '0';
end if;
--
if (hCounter /= hTotalCount-1) then
hcounter <= hcounter + 1;
else
hcounter <= (others => '0');
if (vCounter = vTotalCount-1) then
vCounter <= (others => '0');
else
vCounter <= vCounter + 1;
end if;
end if;
--
if ((hcounter >= hSyncStart) and (hcounter < hSyncEnd)) then
nextHsync <= '0';
else
nextHsync <= '1';
end if;
--
if ((vcounter >= vSyncStart) and (vcounter < vSyncEnd)) then
nextVsync <= '1';
else
nextVsync <= '0';
end if;
end if;
end process;
end behavioral;
|
bsd-3-clause
|
3c6472d8e7691198609f38a429f781f2
| 0.497698 | 3.885009 | false | false | false | false |
sukinull/hls_stream
|
Vivado/example.hls/example.hls.srcs/sources_1/bd/tutorial/ip/tutorial_rst_processing_system7_0_100M_0/synth/tutorial_rst_processing_system7_0_100M_0.vhd
| 1 | 6,835 |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY tutorial_rst_processing_system7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END tutorial_rst_processing_system7_0_100M_0;
ARCHITECTURE tutorial_rst_processing_system7_0_100M_0_arch OF tutorial_rst_processing_system7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tutorial_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF tutorial_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF tutorial_rst_processing_system7_0_100M_0_arch : ARCHITECTURE IS "tutorial_rst_processing_system7_0_100M_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF tutorial_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "tutorial_rst_processing_system7_0_100M_0,proc_sys_reset,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END tutorial_rst_processing_system7_0_100M_0_arch;
|
gpl-2.0
|
9c3942819863995c33cb4357acdc5f78
| 0.718947 | 3.471305 | false | false | false | false |
Bourgeoisie/ECE368-RISC16
|
368RISC/Modules/Reg_Reference.vhd
| 1 | 637 |
---- Engineer: Brett Bourgeois
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE work.UMDRISC_pkg.ALL;
entity Reg is
generic (regSize : integer:= BITREG_16);
port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
D : in STD_LOGIC_VECTOR(regSize downto 0);
Q : out STD_LOGIC_VECTOR(regSize downto 0)
);
end Reg;
architecture Behavioral of Reg is
begin
Process(CLK, RST)
begin
if(RST = '1') then
Q <= (others =>'0');
elsif (CLK'event and CLK = '0') then -- trigger on falling edge
Q <= D;
end if;
end process;
end Behavioral;
|
mit
|
f28412d37b39f2436bd908c344f882d2
| 0.638932 | 2.922018 | false | false | false | false |
Caneda/Caneda
|
libraries/hdl/vhdl/synchronous/counter x 4.vhd
| 1 | 623 |
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY counter IS
PORT (rst: IN std_logic;
clk: IN std_logic;
output: OUT std_logic_vector(3 DOWNTO 0));
END counter;
ARCHITECTURE rtl OF counter IS
signal aux: std_logic_vector(3 DOWNTO 0);
BEGIN
process (clk, rst)
begin
if(rst = '1') then
aux <= (others => '0');
elsif(clk'event and clk = '1') then
if(aux = "1111") then
aux <= (others => '0');
else
aux <= aux + 1;
end if;
end if;
output <= aux;
end process;
END rtl;
|
gpl-2.0
|
cc5dadf1a548bba9b7d44543098c4578
| 0.542536 | 3.38587 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
Test_Pattern_Generator_dspbuilder/hdl/alt_dspbuilder_testbench_clock_GNXGQJH2DS.vhd
| 10 | 2,722 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_testbench_clock_GNXGQJH2DS is
generic ( SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
RESET_REGISTER_CASCADE_DEPTH : natural := 0);
port(
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_clock_GNXGQJH2DS is
function alt_dspbuilder_testbench_clock_GNXGQJH2DS_offset_generate (
latency, cascade_depth: integer)
return integer is
begin
if latency > cascade_depth then
return latency - cascade_depth;
else
return 0;
end if;
end function alt_dspbuilder_testbench_clock_GNXGQJH2DS_offset_generate;
constant cPERIOD : time := 7.499999999999999 ns;
constant cPHASE_DELAY : time := 0 fs;
constant cINITIAL_CLOCK : std_logic := '1';
constant offset : integer := alt_dspbuilder_testbench_clock_GNXGQJH2DS_offset_generate(RESET_LATENCY, RESET_REGISTER_CASCADE_DEPTH);
Begin
-- clock generator
-- We want to start simulation after 4 cycles.
-- Start the salt generators 1 period early as they are read on falling edges
-- take into account any extra registering of resets that need to be compensated for in the msim testbench flow
tb_aclr <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY) * cPERIOD + cPHASE_DELAY - cPERIOD;
-- Start the system 1/2 a period early so it is ready on the next edge
-- we may need to offset this by the difference in the DUT reset latency (needed to align this reset correctly)
-- from the actual latency present in the reset synchronization circuitry
-- so the actual hardware comes out of reset exactly when the data capture elements (using reg_aclr_out)
-- are switched 'on'
aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + offset) * cPERIOD + cPHASE_DELAY - cPERIOD/2;
-- potentially delayed reset signal - delayed to hide any extra latency due to registered reset signal
-- this signal should be hooked up to data capture elements
-- will be identical to above system reset in default (unregistered) reset case
reg_aclr_out <= '1', '0' after (SIMULATION_START_CYCLE + RESET_LATENCY)* cPERIOD + cPHASE_DELAY - cPERIOD/2;
GEN_CLK: process
begin
wait for cPHASE_DELAY;
loop
clock_out <= cINITIAL_CLOCK;
wait for cPERIOD/2;
clock_out <= not cINITIAL_CLOCK;
wait for cPERIOD/2;
end loop;
end process GEN_CLK;
end architecture;
|
mit
|
974d7530d0d381cc742dfd9dfe21a8cf
| 0.708303 | 3.754483 | false | true | false | false |
cathalmccabe/PYNQ
|
boards/ip/audio_codec_ctrl_v1.0/src/common_types.vhd
| 4 | 3,530 |
--
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.family_support.all;
package common_types is
-- TYPE DECLARATIONS
type SLV32_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 31);
subtype SLV64_TYPE is std_logic_vector(0 to 63);
type SLV64_ARRAY_TYPE is array (natural range <>) of SLV64_TYPE;
type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-- FUNCTION GENERATIONS
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer;
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer;
function clog2(x : positive) return natural;
end common_types;
package body common_types is
-----------------------------------------------------------------------------
-- Function calc_num_ce
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The array is input to
-- the function and an integer is returned reflecting the total number of
-- Chip Enables required for the CE, RdCE, and WrCE Buses
-----------------------------------------------------------------------------
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer is
Variable ce_num_sum : integer := 0;
begin
for i in 0 to (ce_num_array'length)-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
return(ce_num_sum);
end function calc_num_ce;
-----------------------------------------------------------------------------
-- Function calc_start_ce_index
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The CE Size array is
-- input to the function and an integer index representing the index of the
-- target module in the ce_num_array. An integer is returned reflecting the
-- starting index of the assigned Chip Enables within the CE, RdCE, and
-- WrCE Buses.
-----------------------------------------------------------------------------
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer is
Variable ce_num_sum : integer := 0;
begin
If (index = 0) Then
ce_num_sum := 0;
else
for i in 0 to index-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
End if;
return(ce_num_sum);
end function calc_start_ce_index;
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
end common_types;
|
bsd-3-clause
|
98e9ef560daf78490a328cb5e8ee77f2
| 0.585269 | 3.900552 | false | false | false | false |
freecores/t48
|
bench/vhdl/tb_t8048.vhd
| 1 | 9,819 |
-------------------------------------------------------------------------------
--
-- The testbench for t8048.
--
-- $Id: tb_t8048.vhd,v 1.8 2008-04-28 22:10:13 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity tb_t8048 is
end tb_t8048;
use work.t48_core_comp_pack.generic_ram_ena;
use work.t48_system_comp_pack.t8048;
use work.t48_tb_pack.all;
architecture behav of tb_t8048 is
-- clock period, 11 MHz
constant period_c : time := 90 ns;
component lpm_rom
generic (
LPM_WIDTH : positive;
LPM_TYPE : string := "LPM_ROM";
LPM_WIDTHAD : positive;
LPM_NUMWORDS : natural := 0;
LPM_FILE : string;
LPM_ADDRESS_CONTROL : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_HINT : string := "UNUSED"
);
port (
address : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
inclock : in std_logic;
outclock : in std_logic;
memenab : in std_logic;
q : out std_logic_vector(LPM_WIDTH-1 downto 0)
);
end component;
signal xtal_s : std_logic;
signal res_n_s : std_logic;
signal int_n_s : std_logic;
signal ale_s : std_logic;
signal psen_n_s : std_logic;
signal prog_n_s : std_logic;
signal t0_b : std_logic;
signal p1_b : std_logic_vector( 7 downto 0);
signal p2_b : std_logic_vector( 7 downto 0);
signal db_b : std_logic_vector( 7 downto 0);
signal ext_mem_addr_s : std_logic_vector(11 downto 0);
signal ext_ram_data_from_s : std_logic_vector( 7 downto 0);
signal ext_ram_we_s : std_logic;
signal ext_rom_data_s : std_logic_vector( 7 downto 0);
signal rd_n_s : std_logic;
signal wr_n_s : std_logic;
signal zero_s : std_logic;
signal one_s : std_logic;
begin
zero_s <= '0';
one_s <= '1';
p2_b <= (others => 'H');
p1_b <= (others => 'H');
-----------------------------------------------------------------------------
-- External ROM, 3k bytes
-- Initialized by file t48_ext_rom.hex.
-----------------------------------------------------------------------------
ext_rom_b : lpm_rom
generic map (
LPM_WIDTH => 8,
LPM_TYPE => "LPM_ROM",
LPM_WIDTHAD => 12,
LPM_NUMWORDS => 3 * (2 ** 10),
LPM_FILE => "rom_t48_ext.hex",
LPM_ADDRESS_CONTROL => "REGISTERED",
LPM_OUTDATA => "UNREGISTERED",
LPM_HINT => "UNUSED"
)
port map (
address => ext_mem_addr_s,
inclock => xtal_s,
outclock => zero_s, -- unused
memenab => one_s,
q => ext_rom_data_s
);
ext_ram_b : generic_ram_ena
generic map (
addr_width_g => 8,
data_width_g => 8
)
port map (
clk_i => xtal_s,
a_i => ext_mem_addr_s(7 downto 0),
we_i => ext_ram_we_s,
ena_i => one_s,
d_i => db_b,
d_o => ext_ram_data_from_s
);
t8048_b : t8048
port map (
xtal_i => xtal_s,
reset_n_i => res_n_s,
t0_b => t0_b,
int_n_i => int_n_s,
ea_i => zero_s,
rd_n_o => rd_n_s,
psen_n_o => psen_n_s,
wr_n_o => wr_n_s,
ale_o => ale_s,
db_b => db_b,
t1_i => p1_b(1),
p2_b => p2_b,
p1_b => p1_b,
prog_n_o => prog_n_s
);
-----------------------------------------------------------------------------
-- Read from external memory
--
db_b <= ext_rom_data_s
when psen_n_s = '0' else
(others => 'Z');
db_b <= ext_ram_data_from_s
when rd_n_s = '0' else
(others => 'Z');
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- External RAM access signals
--
ext_ram: process (wr_n_s,
ale_s,
p2_b,
db_b)
begin
-- lowest 1k of external ROM is not used
ext_mem_addr_s(11 downto 8) <= To_X01Z(p2_b(3 downto 0));
if ale_s'event and ale_s = '0' then
if not is_X(db_b) then
ext_mem_addr_s(7 downto 0) <= db_b;
else
ext_mem_addr_s(7 downto 0) <= (others => '0');
end if;
end if;
if wr_n_s'event and wr_n_s = '1' then
ext_ram_we_s <= '0';
end if;
if wr_n_s'event and wr_n_s = '0' then
ext_ram_we_s <= '1';
end if;
end process ext_ram;
--
-----------------------------------------------------------------------------
t0_b <= p1_b(0);
-----------------------------------------------------------------------------
-- The clock generator
--
clk_gen: process
begin
xtal_s <= '0';
wait for period_c/2;
xtal_s <= '1';
wait for period_c/2;
end process clk_gen;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- The reset generator
--
res_gen: process
begin
res_n_s <= '0';
wait for 5 * period_c;
res_n_s <= '1';
wait;
end process res_gen;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- The interrupt generator
--
int_gen: process
begin
int_n_s <= '1';
wait for 750 * period_c;
int_n_s <= '0';
wait for 45 * period_c;
end process int_gen;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- End of simulation detection
--
eos: process
begin
outer: loop
wait on tb_accu_s;
if tb_accu_s = "10101010" then
wait on tb_accu_s;
if tb_accu_s = "01010101" then
wait on tb_accu_s;
if tb_accu_s = "00000001" then
-- wait for instruction strobe of this move
wait until tb_istrobe_s'event and tb_istrobe_s = '1';
-- wait for next strobe
wait until tb_istrobe_s'event and tb_istrobe_s = '1';
assert false
report "Simulation Result: PASS."
severity note;
else
assert false
report "Simulation Result: FAIL."
severity note;
end if;
assert false
report "End of simulation reached."
severity failure;
end if;
end if;
end loop;
end process eos;
--
-----------------------------------------------------------------------------
end behav;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.7 2006/06/24 00:51:50 arniml
-- comment added about lower 1k of external ROM
--
-- Revision 1.6 2006/06/22 00:21:28 arniml
-- added external ROM
--
-- Revision 1.5 2006/06/21 01:04:05 arniml
-- replaced syn_ram and syn_rom with generic_ram_ena and t48_rom/t49_rom/t3x_rom
--
-- Revision 1.4 2004/04/18 19:00:58 arniml
-- connect T0 and T1 to P1
--
-- Revision 1.3 2004/04/14 20:57:44 arniml
-- wait for instruction strobe after final end-of-simulation detection
-- this ensures that the last mov instruction is part of the dump and
-- enables 100% matching with i8039 simulator
--
-- Revision 1.2 2004/03/26 22:39:28 arniml
-- enhance simulation result string
--
-- Revision 1.1 2004/03/24 21:42:10 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
gpl-2.0
|
f3775622280c5b8cd764eee50e18c29b
| 0.486302 | 3.862707 | false | false | false | false |
sukinull/hls_stream
|
Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/vhdl/axi_sg_updt_sm.vhd
| 1 | 40,595 |
-------------------------------------------------------------------------------
-- axi_sg_updt_sm
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_sm.vhd
-- Description: This entity manages updating of descriptors.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_sm is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_SG_CH1_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to fetch
C_SG_CH1_FIRST_UPDATE_WORD : integer range 0 to 15 := 0;
-- Starting update word offset
C_SG_CH2_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to fetch
C_SG_CH2_FIRST_UPDATE_WORD : integer range 0 to 15 := 0
-- Starting update word offset
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
ftch_error : in std_logic ; --
--
-- Channel 1 Control and Status --
ch1_updt_queue_empty : in std_logic ; --
ch1_updt_curdesc_wren : in std_logic ; --
ch1_updt_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_updt_ioc : in std_logic ; --
ch1_dma_interr : in std_logic ; --
ch1_dma_slverr : in std_logic ; --
ch1_dma_decerr : in std_logic ; --
ch1_updt_active : out std_logic ; --
ch1_updt_idle : out std_logic ; --
ch1_updt_interr_set : out std_logic ; --
ch1_updt_slverr_set : out std_logic ; --
ch1_updt_decerr_set : out std_logic ; --
ch1_dma_interr_set : out std_logic ; --
ch1_dma_slverr_set : out std_logic ; --
ch1_dma_decerr_set : out std_logic ; --
ch1_updt_ioc_irq_set : out std_logic ; --
ch1_updt_done : out std_logic ; --
--
-- Channel 2 Control and Status --
ch2_updt_queue_empty : in std_logic ; --
ch2_updt_curdesc_wren : in std_logic ; --
ch2_updt_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_updt_ioc : in std_logic ; --
ch2_dma_interr : in std_logic ; --
ch2_dma_slverr : in std_logic ; --
ch2_dma_decerr : in std_logic ; --
ch2_updt_active : out std_logic ; --
ch2_updt_idle : out std_logic ; --
ch2_updt_interr_set : out std_logic ; --
ch2_updt_slverr_set : out std_logic ; --
ch2_updt_decerr_set : out std_logic ; --
ch2_dma_interr_set : out std_logic ; --
ch2_dma_slverr_set : out std_logic ; --
ch2_dma_decerr_set : out std_logic ; --
ch2_updt_ioc_irq_set : out std_logic ; --
ch2_updt_done : out std_logic ; --
--
-- DataMover Command --
updt_cmnd_wr : out std_logic ; --
updt_cmnd_data : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH --
+CMD_BASE_WIDTH)-1 downto 0) ; --
-- DataMover Status --
updt_done : in std_logic ; --
updt_error : in std_logic ; --
updt_interr : in std_logic ; --
updt_slverr : in std_logic ; --
updt_decerr : in std_logic ; --
updt_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) --
);
end axi_sg_updt_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Commmand TAG
constant UPDATE_CMD_TAG : std_logic_vector(3 downto 0) := (others => '0');
-- DataMover Command Type
constant UPDATE_CMD_TYPE : std_logic := '0';
-- DataMover Cmnd Reserved Bits
constant UPDATE_MSB_IGNORED : std_logic_vector(7 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant UPDATE_LSB_IGNORED : std_logic_vector(15 downto 0) := (others => '0');
-- DataMover Cmnd Bytes to Xfer for Channel 1
constant UPDATE_CH1_CMD_BTT : std_logic_vector(SG_BTT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_SG_CH1_WORDS_TO_UPDATE*4),SG_BTT_WIDTH));
-- DataMover Cmnd Bytes to Xfer for Channel 2
constant UPDATE_CH2_CMD_BTT : std_logic_vector(SG_BTT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_SG_CH2_WORDS_TO_UPDATE*4),SG_BTT_WIDTH));
-- DataMover Cmnd Reserved Bits
constant UPDATE_CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_SG_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_SG_ADDR_WIDTH)
:= (others => '0');
-- DataMover Cmnd Address Offset for channel 1
constant UPDATE_CH1_ADDR_OFFSET : integer := C_SG_CH1_FIRST_UPDATE_WORD*4;
-- DataMover Cmnd Address Offset for channel 2
constant UPDATE_CH2_ADDR_OFFSET : integer := C_SG_CH2_FIRST_UPDATE_WORD*4;
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
type SG_UPDATE_STATE_TYPE is (
IDLE,
GET_UPDATE_PNTR,
UPDATE_DESCRIPTOR,
UPDATE_STATUS,
UPDATE_ERROR
);
signal updt_cs : SG_UPDATE_STATE_TYPE;
signal updt_ns : SG_UPDATE_STATE_TYPE;
-- State Machine Signals
signal ch1_active_set : std_logic := '0';
signal ch2_active_set : std_logic := '0';
signal write_cmnd_cmb : std_logic := '0';
signal ch1_updt_sm_idle : std_logic := '0';
signal ch2_updt_sm_idle : std_logic := '0';
-- Misc Signals
signal ch1_active_i : std_logic := '0';
signal service_ch1 : std_logic := '0';
signal ch2_active_i : std_logic := '0';
signal service_ch2 : std_logic := '0';
signal update_address : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal update_cmd_btt : std_logic_vector
(SG_BTT_WIDTH-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ch1_updt_active <= ch1_active_i;
ch2_updt_active <= ch2_active_i;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch State Machine
-------------------------------------------------------------------------------
SG_UPDT_MACHINE : process(updt_cs,
ch1_active_i,
ch2_active_i,
service_ch1,
service_ch2,
ch1_updt_curdesc_wren,
ch2_updt_curdesc_wren,
updt_error,
updt_done)
begin
-- Default signal assignment
ch1_active_set <= '0';
ch2_active_set <= '0';
write_cmnd_cmb <= '0';
ch1_updt_sm_idle <= '0';
ch2_updt_sm_idle <= '0';
updt_ns <= updt_cs;
case updt_cs is
-------------------------------------------------------------------
when IDLE =>
ch1_updt_sm_idle <= not service_ch1;
ch2_updt_sm_idle <= not service_ch2;
-- error during update - therefore shut down
if(updt_error = '1')then
updt_ns <= UPDATE_ERROR;
-- If channel 1 is running and not idle and queue is not full
-- then fetch descriptor for channel 1
elsif(service_ch1 = '1')then
ch1_active_set <= '1';
updt_ns <= GET_UPDATE_PNTR;
-- If channel 2 is running and not idle and queue is not full
-- then fetch descriptor for channel 2
elsif(service_ch2 = '1')then
ch2_active_set <= '1';
updt_ns <= GET_UPDATE_PNTR;
else
updt_ns <= IDLE;
end if;
when GET_UPDATE_PNTR =>
if(ch1_updt_curdesc_wren = '1' or ch2_updt_curdesc_wren = '1')then
updt_ns <= UPDATE_DESCRIPTOR;
else
updt_ns <= GET_UPDATE_PNTR;
end if;
-------------------------------------------------------------------
when UPDATE_DESCRIPTOR =>
-- error during update - therefore shut down
if(updt_error = '1')then
updt_ns <= UPDATE_ERROR;
-- write command
else
ch1_updt_sm_idle <= not ch1_active_i and not service_ch1;
ch2_updt_sm_idle <= not ch2_active_i and not service_ch2;
write_cmnd_cmb <= '1';
updt_ns <= UPDATE_STATUS;
end if;
-------------------------------------------------------------------
when UPDATE_STATUS =>
ch1_updt_sm_idle <= not ch1_active_i and not service_ch1;
ch2_updt_sm_idle <= not ch2_active_i and not service_ch2;
-- error during update - therefore shut down
if(updt_error = '1')then
updt_ns <= UPDATE_ERROR;
-- wait until done with update
elsif(updt_done = '1')then
-- If just finished fethcing for channel 2 then...
if(ch2_active_i = '1')then
-- If ready, update descriptor for channel 1
if(service_ch1 = '1')then
ch1_active_set <= '1';
updt_ns <= GET_UPDATE_PNTR;
-- Otherwise return to IDLE
else
updt_ns <= IDLE;
end if;
-- If just finished fethcing for channel 1 then...
elsif(ch1_active_i = '1')then
-- If ready, update descriptor for channel 2
if(service_ch2 = '1')then
ch2_active_set <= '1';
updt_ns <= GET_UPDATE_PNTR;
-- Otherwise return to IDLE
else
updt_ns <= IDLE;
end if;
else
updt_ns <= IDLE;
end if;
else
updt_ns <= UPDATE_STATUS;
end if;
-------------------------------------------------------------------
when UPDATE_ERROR =>
ch1_updt_sm_idle <= '1';
ch2_updt_sm_idle <= '1';
updt_ns <= UPDATE_ERROR;
-------------------------------------------------------------------
when others =>
updt_ns <= IDLE;
end case;
end process SG_UPDT_MACHINE;
-------------------------------------------------------------------------------
-- Register states of state machine
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_cs <= IDLE;
else
updt_cs <= updt_ns;
end if;
end if;
end process REGISTER_STATE;
-------------------------------------------------------------------------------
-- Channel included therefore generate fetch logic
-------------------------------------------------------------------------------
GEN_CH1_UPDATE : if C_INCLUDE_CH1 = 1 generate
begin
-------------------------------------------------------------------------------
-- Active channel flag. Indicates which channel is active.
-- 0 = channel active
-- 1 = channel active
-------------------------------------------------------------------------------
CH1_ACTIVE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_active_i <= '0';
elsif(ch1_active_i = '1' and updt_done = '1')then
ch1_active_i <= '0';
elsif(ch1_active_set = '1')then
ch1_active_i <= '1';
end if;
end if;
end process CH1_ACTIVE_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 ready to be serviced?
-------------------------------------------------------------------------------
service_ch1 <= '1' when ch1_updt_queue_empty = '0' -- Queue not empty
and ftch_error = '0' -- No SG Fetch Error
else '0';
-------------------------------------------------------------------------------
-- Channel 1 Interrupt On Complete
-------------------------------------------------------------------------------
CH1_INTR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_ioc_irq_set <= '0';
-- Set interrupt on Done and Descriptor IOC set
elsif(updt_done = '1' and ch1_updt_ioc = '1')then
ch1_updt_ioc_irq_set <= '1';
else
ch1_updt_ioc_irq_set <= '0';
end if;
end if;
end process CH1_INTR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Internal Error
-------------------------------------------------------------------------------
CH1_INTERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_dma_interr_set <= '0';
-- Set internal error on desc updt Done and Internal Error
elsif(updt_done = '1' and ch1_dma_interr = '1')then
ch1_dma_interr_set <= '1';
end if;
end if;
end process CH1_INTERR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Slave Error
-------------------------------------------------------------------------------
CH1_SLVERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_dma_slverr_set <= '0';
-- Set slave error on desc updt Done and Slave Error
elsif(updt_done = '1' and ch1_dma_slverr = '1')then
ch1_dma_slverr_set <= '1';
end if;
end if;
end process CH1_SLVERR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Decode Error
-------------------------------------------------------------------------------
CH1_DECERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_dma_decerr_set <= '0';
-- Set decode error on desc updt Done and Decode Error
elsif(updt_done = '1' and ch1_dma_decerr = '1')then
ch1_dma_decerr_set <= '1';
end if;
end if;
end process CH1_DECERR_PROCESS;
-------------------------------------------------------------------------------
-- Log Fetch Errors
-------------------------------------------------------------------------------
-- Log Slave Errors reported during descriptor update
SLV_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_slverr_set <= '0';
elsif(ch1_active_i = '1' and updt_slverr = '1')then
ch1_updt_slverr_set <= '1';
end if;
end if;
end process SLV_SET_PROCESS;
-- Log Internal Errors reported during descriptor update
INT_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_interr_set <= '0';
elsif(ch1_active_i = '1' and updt_interr = '1')then
ch1_updt_interr_set <= '1';
end if;
end if;
end process INT_SET_PROCESS;
-- Log Decode Errors reported during descriptor update
DEC_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_decerr_set <= '0';
elsif(ch1_active_i = '1' and updt_decerr = '1')then
ch1_updt_decerr_set <= '1';
end if;
end if;
end process DEC_SET_PROCESS;
-- Indicate update is idle if state machine is idle and update queue is empty
IDLE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_error = '1' or ftch_error = '1')then
ch1_updt_idle <= '1';
elsif(service_ch1 = '1')then
ch1_updt_idle <= '0';
elsif(service_ch1 = '0' and ch1_updt_sm_idle = '1')then
ch1_updt_idle <= '1';
end if;
end if;
end process IDLE_PROCESS;
---------------------------------------------------------------------------
-- Indicate update is done to allow fetch of next descriptor
-- This is needed to prevent a partial descriptor being fetched
-- and then axi read is throttled for extended periods until the
-- remainder of the descriptor is fetched.
--
-- Note: Only used when fetch queue not inluded otherwise
-- tools optimize out this process
---------------------------------------------------------------------------
REG_CH1_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_done <= '0';
elsif(updt_done = '1' and ch1_active_i = '1')then
ch1_updt_done <= '1';
else
ch1_updt_done <= '0';
end if;
end if;
end process REG_CH1_DONE;
end generate GEN_CH1_UPDATE;
-------------------------------------------------------------------------------
-- Channel excluded therefore do not generate fetch logic
-------------------------------------------------------------------------------
GEN_NO_CH1_UPDATE : if C_INCLUDE_CH1 = 0 generate
begin
service_ch1 <= '0';
ch1_active_i <= '0';
ch1_updt_idle <= '0';
ch1_updt_interr_set <= '0';
ch1_updt_slverr_set <= '0';
ch1_updt_decerr_set <= '0';
ch1_dma_interr_set <= '0';
ch1_dma_slverr_set <= '0';
ch1_dma_decerr_set <= '0';
ch1_updt_ioc_irq_set <= '0';
ch1_updt_done <= '0';
end generate GEN_NO_CH1_UPDATE;
-------------------------------------------------------------------------------
-- Channel included therefore generate fetch logic
-------------------------------------------------------------------------------
GEN_CH2_UPDATE : if C_INCLUDE_CH2 = 1 generate
begin
-------------------------------------------------------------------------------
-- Active channel flag. Indicates which channel is active.
-- 0 = channel active
-- 1 = channel active
-------------------------------------------------------------------------------
CH2_ACTIVE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_active_i <= '0';
elsif(ch2_active_i = '1' and updt_done = '1')then
ch2_active_i <= '0';
elsif(ch2_active_set = '1')then
ch2_active_i <= '1';
end if;
end if;
end process CH2_ACTIVE_PROCESS;
-------------------------------------------------------------------------------
-- Channel 2 ready to be serviced?
-------------------------------------------------------------------------------
service_ch2 <= '1' when ch2_updt_queue_empty = '0' -- Queue not empty
and ftch_error = '0' -- No SG Fetch Error
else '0';
-------------------------------------------------------------------------------
-- Channel 2 Interrupt On Complete
-------------------------------------------------------------------------------
CH2_INTR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_ioc_irq_set <= '0';
-- Set interrupt on Done and Descriptor IOC set
elsif(updt_done = '1' and ch2_updt_ioc = '1')then
ch2_updt_ioc_irq_set <= '1';
else
ch2_updt_ioc_irq_set <= '0';
end if;
end if;
end process CH2_INTR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Internal Error
-------------------------------------------------------------------------------
CH2_INTERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_dma_interr_set <= '0';
-- Set internal error on desc updt Done and Internal Error
elsif(updt_done = '1' and ch2_dma_interr = '1')then
ch2_dma_interr_set <= '1';
end if;
end if;
end process CH2_INTERR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Slave Error
-------------------------------------------------------------------------------
CH2_SLVERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_dma_slverr_set <= '0';
-- Set slave error on desc updt Done and Slave Error
elsif(updt_done = '1' and ch2_dma_slverr = '1')then
ch2_dma_slverr_set <= '1';
end if;
end if;
end process CH2_SLVERR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Decode Error
-------------------------------------------------------------------------------
CH2_DECERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_dma_decerr_set <= '0';
-- Set decode error on desc updt Done and Decode Error
elsif(updt_done = '1' and ch2_dma_decerr = '1')then
ch2_dma_decerr_set <= '1';
end if;
end if;
end process CH2_DECERR_PROCESS;
-------------------------------------------------------------------------------
-- Log Fetch Errors
-------------------------------------------------------------------------------
-- Log Slave Errors reported during descriptor update
SLV_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_slverr_set <= '0';
elsif(ch2_active_i = '1' and updt_slverr = '1')then
ch2_updt_slverr_set <= '1';
end if;
end if;
end process SLV_SET_PROCESS;
-- Log Internal Errors reported during descriptor update
INT_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_interr_set <= '0';
elsif(ch2_active_i = '1' and updt_interr = '1')then
ch2_updt_interr_set <= '1';
end if;
end if;
end process INT_SET_PROCESS;
-- Log Decode Errors reported during descriptor update
DEC_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_decerr_set <= '0';
elsif(ch2_active_i = '1' and updt_decerr = '1')then
ch2_updt_decerr_set <= '1';
end if;
end if;
end process DEC_SET_PROCESS;
-- Indicate update is idle if state machine is idle and update queue is empty
IDLE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_error = '1' or ftch_error = '1')then
ch2_updt_idle <= '1';
elsif(service_ch2 = '1')then
ch2_updt_idle <= '0';
elsif(service_ch2 = '0' and ch2_updt_sm_idle = '1')then
ch2_updt_idle <= '1';
end if;
end if;
end process IDLE_PROCESS;
---------------------------------------------------------------------------
-- Indicate update is done to allow fetch of next descriptor
-- This is needed to prevent a partial descriptor being fetched
-- and then axi read is throttled for extended periods until the
-- remainder of the descriptor is fetched.
--
-- Note: Only used when fetch queue not inluded otherwise
-- tools optimize out this process
---------------------------------------------------------------------------
REG_CH2_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_done <= '0';
elsif(updt_done = '1' and ch2_active_i = '1')then
ch2_updt_done <= '1';
else
ch2_updt_done <= '0';
end if;
end if;
end process REG_CH2_DONE;
end generate GEN_CH2_UPDATE;
-------------------------------------------------------------------------------
-- Channel excluded therefore do not generate fetch logic
-------------------------------------------------------------------------------
GEN_NO_CH2_UPDATE : if C_INCLUDE_CH2 = 0 generate
begin
service_ch2 <= '0';
ch2_active_i <= '0';
ch2_updt_idle <= '0';
ch2_updt_interr_set <= '0';
ch2_updt_slverr_set <= '0';
ch2_updt_decerr_set <= '0';
ch2_dma_interr_set <= '0';
ch2_dma_slverr_set <= '0';
ch2_dma_decerr_set <= '0';
ch2_updt_ioc_irq_set <= '0';
ch2_updt_done <= '0';
end generate GEN_NO_CH2_UPDATE;
---------------------------------------------------------------------------
-- Register Current Update Address. Address captured from channel port
-- or queue by axi_sg_updt_queue
---------------------------------------------------------------------------
REG_UPDATE_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
update_address <= (others => '0');
-- Channel 1 descriptor update pointer
elsif(ch1_updt_curdesc_wren = '1')then
update_address <= std_logic_vector(unsigned(ch1_updt_curdesc)
+ UPDATE_CH1_ADDR_OFFSET);
-- Channel 2 descriptor update pointer
elsif(ch2_updt_curdesc_wren = '1')then
update_address <= std_logic_vector(unsigned(ch2_updt_curdesc)
+ UPDATE_CH2_ADDR_OFFSET);
end if;
end if;
end process REG_UPDATE_ADDRESS;
-- Assigne Bytes to Transfer (BTT)
update_cmd_btt <= UPDATE_CH1_CMD_BTT when ch1_active_i = '1'
else UPDATE_CH2_CMD_BTT;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- When command by sm, drive command to updt_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_cmnd_wr <= '0';
updt_cmnd_data <= (others => '0');
-- Fetch SM issued a command write
elsif(write_cmnd_cmb = '1')then
updt_cmnd_wr <= '1';
updt_cmnd_data <= UPDATE_CMD_RSVD
& UPDATE_CMD_TAG
& update_address
& UPDATE_MSB_IGNORED
& UPDATE_CMD_TYPE
& UPDATE_LSB_IGNORED
& update_cmd_btt;
else
updt_cmnd_wr <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
-------------------------------------------------------------------------------
-- Capture and hold fetch address in case an error occurs
-------------------------------------------------------------------------------
LOG_ERROR_ADDR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_error_addr <= (others => '0');
elsif(write_cmnd_cmb = '1')then
updt_error_addr <= update_address(C_M_AXI_SG_ADDR_WIDTH-1 downto SG_ADDR_LSB) & "000000";
end if;
end if;
end process LOG_ERROR_ADDR;
end implementation;
|
gpl-2.0
|
45a84b1cff4fdf4afe011f0846e8ed59
| 0.392807 | 4.688186 | false | false | false | false |
nulldozer/purisc
|
Compute_Group/CORE/read_data_stage.vhd
| 1 | 2,658 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity read_data_stage is
port(
clk : in std_logic;
reset_n : in std_logic;
stall : in std_logic;
-- inputs
start_address : in std_logic_vector(31 downto 0);
ex_w_addr : in std_logic_vector(31 downto 0);
ex_w_data : in std_logic_vector(31 downto 0);
ex_we : in std_logic;
a_in : in std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0);
c_in : in std_logic_vector(31 downto 0);
addr_a : in std_logic_vector(31 downto 0);
addr_b : in std_logic_vector(31 downto 0);
addr_c : in std_logic_vector(31 downto 0);
next_pc : in std_logic_vector(31 downto 0);
ubranch_in : in std_logic;
cbranch_in : in std_logic;
--outputs
a_out : out std_logic_vector(31 downto 0);
b_out : out std_logic_vector(31 downto 0);
c_out : out std_logic_vector(31 downto 0);
addr_a_out : out std_logic_vector(31 downto 0);
addr_b_out : out std_logic_vector(31 downto 0);
addr_c_out : out std_logic_vector(31 downto 0);
ubranch_out : out std_logic;
noop_out : out std_logic;
r_addr_0 : out std_logic_vector(31 downto 0);
r_addr_1 : out std_logic_vector(31 downto 0);
next_pc_out : out std_logic_vector(31 downto 0)
);
end entity;
architecture a1 of read_data_stage is
--signals
signal ubranch : std_logic;
signal noop : std_logic;
signal a_in_fwd : std_logic_vector(31 downto 0);
signal b_in_fwd : std_logic_vector(31 downto 0);
--components
begin
--determine forwarding (change inputs before they are used)
a_in_fwd <= ex_w_data when (ex_w_addr = addr_a and ex_we = '1') else a_in;
b_in_fwd <= ex_w_addr when (ex_w_addr = addr_b and ex_we = '1') else b_in;
--determine ubranch
ubranch <= '1' when (a_in_fwd = b_in_fwd and not(next_pc = c_in) and not(ubranch_in = '1') and not(cbranch_in = '1'))
else '0';
--determine noop
noop <= ubranch_in or cbranch_in; --the ubranch generated above
process(clk, reset_n, start_address) begin
if (reset_n = '0') then
--on boot
noop_out <= '1';
ubranch_out <= '0';
r_addr_0 <= std_logic_vector(unsigned(start_address) + to_unsigned(4,32));
r_addr_1 <= std_logic_vector(unsigned(start_address) + to_unsigned(5,32));
elsif (rising_edge(clk)) then
if(stall = '0') then
ubranch_out <= ubranch;
noop_out <= noop;
a_out <= a_in;
b_out <= b_in;
c_out <= c_in;
r_addr_0 <= a_in;
r_addr_1 <= b_in;
addr_a_out <= addr_a;
addr_b_out <= addr_b;
addr_c_out <= addr_c;
next_pc_out <= next_pc;
else
--hold previous outputs on stall (automatic)
end if;
end if;
end process;
end architecture;
|
gpl-2.0
|
b1f58ac24fd5915a2343c2577e1f221f
| 0.63544 | 2.593171 | false | false | false | false |
Bourgeoisie/ECE368-RISC16
|
368RISC/ipcore_dir/tmp/_cg/Instruct_Memory/simulation/Instruct_Memory_synth.vhd
| 2 | 8,927 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Instruct_Memory_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY Instruct_Memory_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
CLKB_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE Instruct_Memory_synth_ARCH OF Instruct_Memory_synth IS
COMPONENT Instruct_Memory_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ADDRB : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL CLKB: STD_LOGIC := '0';
SIGNAL RSTB: STD_LOGIC := '0';
SIGNAL ADDRB: STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB_R: STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTB: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL clkb_in_i: STD_LOGIC;
SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
-- clkb_buf: bufg
-- PORT map(
-- i => CLKB_IN,
-- o => clkb_in_i
-- );
clkb_in_i <= CLKB_IN;
CLKB <= clkb_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
RSTB <= RESETB_SYNC_R3 AFTER 50 ns;
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
RESETB_SYNC_R1 <= RESET_IN;
RESETB_SYNC_R2 <= RESETB_SYNC_R1;
RESETB_SYNC_R3 <= RESETB_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 16,
READ_WIDTH => 16 )
PORT MAP (
CLK => clkb_in_i,
RST => RSTB,
EN => CHECKER_EN_R,
DATA_IN => DOUTB,
STATUS => ISSUE_FLAG(0)
);
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
IF(RSTB='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLKA => clk_in_i,
CLKB => clkb_in_i,
TB_RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
ADDRB => ADDRB,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ADDRB_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
ADDRB_R <= ADDRB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: Instruct_Memory_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
CLKA => CLKA,
--Port B
ADDRB => ADDRB_R,
DOUTB => DOUTB,
CLKB => CLKB
);
END ARCHITECTURE;
|
mit
|
effc17e7a6593f6932a7ea39edef60ff
| 0.570292 | 3.605412 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_dividerAltr.vhd
| 4 | 4,072 |
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_dividerAltr is
generic (
widthin : natural :=8;
pipeline : natural :=0;
isunsigned : natural :=0
);
port
(
clock : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
clken : in std_logic ;
numer : in std_logic_vector (widthin-1 downto 0);
denom : in std_logic_vector (widthin-1 downto 0);
quotient : out std_logic_vector (widthin-1 downto 0);
remain : out std_logic_vector (widthin-1 downto 0)
);
end alt_dspbuilder_dividerAltr;
architecture syn of alt_dspbuilder_dividerAltr is
signal svcc : std_logic;
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
svcc <='1';
gsgn: if (isunsigned=0) generate
gcomb:if pipeline=0 generate
u0 : lpm_divide generic map (
lpm_widthn => widthin,
lpm_widthd => widthin,
lpm_type => "LPM_DIVIDE",
lpm_nrepresentation => "SIGNED",
lpm_hint => "LPM_REMAINDERPOSITIVE=FALSE",
lpm_drepresentation => "SIGNED"
)
port map (
denom => denom,
numer => numer,
quotient => quotient,
remain => remain
);
end generate gcomb;
gseq:if pipeline>0 generate
u0 : lpm_divide
generic map (
lpm_widthn => widthin,
lpm_widthd => widthin,
lpm_pipeline => pipeline,
lpm_type => "LPM_DIVIDE",
lpm_nrepresentation => "SIGNED",
lpm_hint => "LPM_REMAINDERPOSITIVE=FALSE",
lpm_drepresentation => "SIGNED"
)
port map (
clken => clken,
denom => denom,
aclr => aclr_i,
clock => clock,
numer => numer,
quotient => quotient,
remain => remain
);
end generate gseq;
end generate gsgn;
gugn: if (isunsigned>0) generate
gcomb:if pipeline=0 generate
u0 : lpm_divide generic map (
lpm_widthn => widthin,
lpm_widthd => widthin,
lpm_type => "LPM_DIVIDE",
lpm_nrepresentation => "UNSIGNED",
lpm_hint => "LPM_REMAINDERPOSITIVE=TRUE",
lpm_drepresentation => "UNSIGNED"
)
port map (
denom => denom,
numer => numer,
quotient => quotient,
remain => remain
);
end generate gcomb;
gseq:if pipeline>0 generate
u0 : lpm_divide
generic map (
lpm_widthn => widthin,
lpm_widthd => widthin,
lpm_pipeline => pipeline,
lpm_type => "LPM_DIVIDE",
lpm_nrepresentation => "UNSIGNED",
lpm_hint => "LPM_REMAINDERPOSITIVE=TRUE",
lpm_drepresentation => "UNSIGNED"
)
port map (
clken => svcc,
denom => denom,
aclr => aclr_i,
clock => clock,
numer => numer,
quotient => quotient,
remain => remain
);
end generate gseq;
end generate gugn;
end syn;
|
mit
|
bbf833f28f3ff2e6989fef8ab8d3e63b
| 0.59111 | 3.794967 | false | false | false | false |
michaelmiehling/A25_VME_TB
|
Testbench/vmebus.vhd
| 1 | 11,655 |
---------------------------------------------------------------
-- Title : External driver simulation model
-- Project : A15
---------------------------------------------------------------
-- File : vmebus.vhd
-- Author : Michael Miehling
-- Email : [email protected]
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 03/02/03
---------------------------------------------------------------
-- Simulator : Modelsim
-- Synthesis : -
---------------------------------------------------------------
-- Description :
--
--
---------------------------------------------------------------
-- Hierarchy:
--
-- tb_vme_ctrl
-- vmebus
-- vme_sim_mstr
-- vme_sim_slave
-- vme_sim_mon
---------------------------------------------------------------
-- Copyright (C) 2001, MEN Mikroelektronik Nuernberg GmbH
--
-- All rights reserved. Reproduction in whole or part is
-- prohibited without the written permission of the
-- copyright owner.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.2 $
--
-- $Log: vmebus.vhd,v $
-- Revision 1.2 2013/04/18 15:11:19 MMiehling
-- added slot 1/x support
--
-- Revision 1.1 2012/03/29 10:28:51 MMiehling
-- Initial Revision
--
-- Revision 1.2 2006/05/18 14:30:46 MMiehling
-- changed iack connection
--
-- Revision 1.1 2005/10/28 17:52:09 mmiehling
-- Initial Revision
--
-- Revision 1.1 2004/07/27 17:27:56 mmiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.vme_sim_pack.ALL;
USE work.terminal_pkg.all;
ENTITY vmebus IS
PORT (
slot1 : boolean:=TRUE; -- if true dut is in slot1
vme_slv_in : IN vme_slv_in_type;
vme_slv_out : OUT vme_slv_out_type;
vme_mon_out : OUT vme_mon_out_type;
terminal_in_x : OUT terminal_in_type;
terminal_out_x : IN terminal_out_type;
-- the VME signals:
vb_am : INOUT std_logic_vector(5 DOWNTO 0);
vb_data : INOUT std_logic_vector(31 DOWNTO 0);
vb_adr : INOUT std_logic_vector(31 DOWNTO 0);
vb_writen : INOUT std_logic;
vb_iackn : INOUT std_logic;
vb_asn : INOUT std_logic;
vb_dsan : INOUT std_logic;
vb_dsbn : INOUT std_logic;
vb_bbsyn : INOUT std_logic;
vb_berrn : INOUT std_logic;
vb_brn : INOUT std_logic_vector(3 DOWNTO 0);
vb_dtackn : INOUT std_logic;
vb_sysresn : INOUT std_logic;
vb_irq1n : INOUT std_logic;
vb_irq2n : INOUT std_logic;
vb_irq3n : INOUT std_logic;
vb_irq4n : INOUT std_logic;
vb_irq5n : INOUT std_logic;
vb_irq6n : INOUT std_logic;
vb_irq7n : INOUT std_logic;
vb_bgin : OUT std_logic_vector(3 DOWNTO 0);
vb_bgout : IN std_logic_vector(3 DOWNTO 0);
vb_iackin : OUT std_logic;
vb_iackout : IN std_logic;
vb_acfailn : INOUT std_logic
);
END vmebus;
ARCHITECTURE vmebus_arch OF vmebus IS
COMPONENT vme_sim_mstr
PORT (
sysresn : INOUT std_logic;
asn : INOUT std_logic;
dsan : INOUT std_logic;
dsbn : INOUT std_logic;
writen : INOUT std_logic;
dtackn : IN std_logic;
berrn : INOUT std_logic;
addr : INOUT std_logic_vector(31 DOWNTO 0);
data : INOUT std_logic_vector(31 DOWNTO 0);
am : INOUT std_logic_vector(5 DOWNTO 0);
iackn : INOUT std_logic;
iackout : OUT std_logic;
iackin : IN std_logic;
vb_irq1n : INOUT std_logic;
vb_irq2n : INOUT std_logic;
vb_irq3n : INOUT std_logic;
vb_irq4n : INOUT std_logic;
vb_irq5n : INOUT std_logic;
vb_irq6n : INOUT std_logic;
vb_irq7n : INOUT std_logic;
vb_acfailn : INOUT std_logic;
bg3n_in : IN std_logic;
bg3n_out : OUT std_logic;
brn : INOUT std_logic_vector(3 DOWNTO 0);
bbsyn : INOUT std_logic;
terminal_in_x : OUT terminal_in_type;
terminal_out_x : IN terminal_out_type
);
END COMPONENT;
COMPONENT vme_sim_slave
PORT (
sysresin : IN std_logic;
asn_in : IN std_logic;
dsan_in : IN std_logic;
dsbn_in : IN std_logic;
writen_in : IN std_logic;
berrn_in : IN std_logic;
addr : INOUT std_logic_vector(31 DOWNTO 0);
data_in : IN std_logic_vector(31 DOWNTO 0);
am_in : IN std_logic_vector(5 DOWNTO 0);
iackn_in : IN std_logic; -- daisy-chain
iackn : IN std_logic; -- bussignal
irq_out : OUT std_logic_vector(7 DOWNTO 1);
dtackn_out : OUT std_logic;
data_out : OUT std_logic_vector(31 DOWNTO 0);
vb_irq1n : IN std_logic;
vb_irq2n : IN std_logic;
vb_irq3n : IN std_logic;
vb_irq4n : IN std_logic;
vb_irq5n : IN std_logic;
vb_irq6n : IN std_logic;
vb_irq7n : IN std_logic;
vme_slv_in : IN vme_slv_in_type;
vme_slv_out : OUT vme_slv_out_type
);
END COMPONENT;
COMPONENT vme_sim_mon
PORT (
rstn : IN std_logic;
asn_in : IN std_logic;
dsan_in : IN std_logic;
dsbn_in : IN std_logic;
writen_in : IN std_logic;
dtackn_in : IN std_logic;
berrn_in : IN std_logic;
addr_in : IN std_logic_vector(31 DOWNTO 0);
data_in : IN std_logic_vector(31 DOWNTO 0);
am_in : IN std_logic_vector(5 DOWNTO 0);
iackn : IN std_logic;
vb_irq1n : IN std_logic;
vb_irq2n : IN std_logic;
vb_irq3n : IN std_logic;
vb_irq4n : IN std_logic;
vb_irq5n : IN std_logic;
vb_irq6n : IN std_logic;
vb_irq7n : IN std_logic;
bbsyn_in : IN std_logic;
vme_mon_out : OUT vme_mon_out_type
);
END COMPONENT;
SIGNAL bg3n_out : std_logic;
SIGNAL sim_iackout: std_logic;
SIGNAL sim_iackin : std_logic;
SIGNAL sim_bgout : std_logic;
SIGNAL sim_bgin : std_logic;
BEGIN
vb_am <= (OTHERS => 'H');
vb_data <= (OTHERS => 'H');
vb_adr <= (OTHERS => 'H');
vb_brn <= (OTHERS => 'H');
vb_bgin <= (OTHERS => 'H');
vb_writen <= 'H';
vb_iackn <= 'H';
vb_asn <= 'H';
vb_dsan <= 'H';
vb_dsbn <= 'H';
vb_bbsyn <= 'H';
vb_berrn <= 'H';
vb_dtackn <= 'H';
vb_sysresn <= 'H';
-- vb_irq1n <= 'H';
-- vb_irq2n <= 'H';
-- vb_irq3n <= 'H';
-- vb_irq4n <= 'H';
-- vb_irq5n <= 'H';
-- vb_irq6n <= 'H';
-- vb_irq7n <= 'H';
vb_acfailn <= 'H';
vmesimmstr : vme_sim_mstr
PORT MAP (
sysresn => vb_sysresn,
asn => vb_asn,
dsan => vb_dsan,
dsbn => vb_dsbn,
writen => vb_writen,
dtackn => vb_dtackn,
berrn => vb_berrn,
addr => vb_adr,
data => vb_data,
am => vb_am,
iackn => vb_iackn,
iackout => sim_iackout,
iackin => sim_iackin,
vb_irq1n => vb_irq1n,
vb_irq2n => vb_irq2n,
vb_irq3n => vb_irq3n,
vb_irq4n => vb_irq4n,
vb_irq5n => vb_irq5n,
vb_irq6n => vb_irq6n,
vb_irq7n => vb_irq7n,
vb_acfailn => vb_acfailn,
bg3n_in => sim_bgin,
bg3n_out => sim_bgout,
brn => vb_brn,
bbsyn => vb_bbsyn,
terminal_in_x => terminal_in_x ,
terminal_out_x => terminal_out_x
);
vmesimmon: vme_sim_mon
PORT MAP(
rstn => vb_sysresn,
asn_in => vb_asn,
dsan_in => vb_dsan,
dsbn_in => vb_dsbn,
writen_in => vb_writen,
dtackn_in => vb_dtackn,
berrn_in => vb_berrn,
addr_in => vb_adr,
data_in => vb_data,
am_in => vb_am,
iackn => vb_iackn,
vb_irq1n => vb_irq1n,
vb_irq2n => vb_irq2n,
vb_irq3n => vb_irq3n,
vb_irq4n => vb_irq4n,
vb_irq5n => vb_irq5n,
vb_irq6n => vb_irq6n,
vb_irq7n => vb_irq7n,
bbsyn_in => vb_bbsyn,
vme_mon_out => vme_mon_out
);
vb_slave : vme_sim_slave
PORT MAP(
sysresin => vb_sysresn,
asn_in => vb_asn,
dsan_in => vb_dsan,
dsbn_in => vb_dsbn,
writen_in => vb_writen,
berrn_in => vb_berrn,
addr => vb_adr,
data_in => vb_data,
am_in => vb_am,
iackn_in => sim_iackin,
iackn => vb_iackn,
dtackn_out => vb_dtackn,
data_out => vb_data,
irq_out(1) => vb_irq1n,
irq_out(2) => vb_irq2n,
irq_out(3) => vb_irq3n,
irq_out(4) => vb_irq4n,
irq_out(5) => vb_irq5n,
irq_out(6) => vb_irq6n,
irq_out(7) => vb_irq7n,
vb_irq1n => vb_irq1n,
vb_irq2n => vb_irq2n,
vb_irq3n => vb_irq3n,
vb_irq4n => vb_irq4n,
vb_irq5n => vb_irq5n,
vb_irq6n => vb_irq6n,
vb_irq7n => vb_irq7n,
vme_slv_in => vme_slv_in ,
vme_slv_out => vme_slv_out
);
sl1: PROCESS(slot1, vb_iackn, vb_iackout, vb_bgout, sim_iackout, sim_bgout)
BEGIN
IF slot1 THEN
----------------------------------------------------------------
-- slot 1 2
-- dut sim
----------------------------------------------------------------
IF vb_iackn = '0' THEN
vb_iackin <= '0'; -- connect vb_iackn bussignal to daisy chain slot1
ELSE
vb_iackin <= 'H';
END IF;
sim_iackin <= vb_iackout; -- connect iack daisy chain of dut(slot1) to sim
vb_bgin(3) <= '0'; -- dut is in slot1
sim_bgin <= vb_bgout(3); -- connect bg daisy chain of dut(slot1) to sim
ELSE
----------------------------------------------------------------
-- slot 1 2
-- sim dut
----------------------------------------------------------------
vb_iackin <= sim_iackout;
IF vb_iackn = '0' THEN
sim_iackin <= '0'; -- connect vb_iackn bussignal to daisy chain slot1
ELSE
sim_iackin <= 'H';
END IF;
vb_bgin(3) <= sim_bgout; -- connect bg daisy chain of sim(slot1) to dut
sim_bgin <= '0'; -- sim is in slot1
END IF;
END PROCESS sl1;
END vmebus_arch;
|
gpl-3.0
|
67dbf77459c09ba91f887fd4a7771ebe
| 0.430545 | 3.550107 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_sStepAltr.vhd
| 8 | 3,488 |
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sStepAltr is
generic (
StepDelay : positive ;
direction : natural
);
port (
clock : in std_logic;
ena : in std_logic :='1';
sclr : in std_logic :='0';
aclr : in std_logic :='0';
user_aclr : in std_logic :='0';
q : out std_logic
);
end alt_dspbuilder_sStepAltr ;
architecture syn of alt_dspbuilder_sStepAltr is
type States_StepAltr is (sclear, slow, shigh);
signal current_state : States_StepAltr;
signal next_state : States_StepAltr;
signal iq : std_logic;
signal count : std_logic_vector(ToNatural(nbitnecessary(StepDelay)-1) downto 0);
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
gr:if StepDelay=1 generate
process(clock,aclr_i)
begin
if aclr_i='1' then
iq <= '0';
elsif clock'event and clock='1' then
if (sclr='1') then
iq <= '0';
elsif (ena='1') then
iq <='1';
end if;
end if;
end process;
end generate gr;
grr:if StepDelay>1 generate
rp:process(clock,aclr_i)
begin
if aclr_i='1' then
count <= (others=>'0');
current_state <= sclear;
elsif clock'event and clock='1' then
if (sclr='1') then
count <= (others=>'0');
current_state <= sclear;
elsif (ena='1') then
count <= count+int2ustd(1,nbitnecessary(StepDelay));
current_state <= next_state;
end if;
end if;
end process;
cp:process(count, current_state, sclr,ena)
begin
case current_state is
when sclear =>
iq <= '0';
if (ena='1') and (sclr='0') then
next_state <= slow;
else
next_state <= sclear;
end if;
when slow =>
iq <= '0';
if (sclr='1') then
next_state <= sclear;
elsif (count=int2ustd(StepDelay-1,nbitnecessary(StepDelay))) and (ena ='1') then
next_state <= shigh;
else
next_state <= slow ;
end if;
when shigh =>
iq <= '1';
if (sclr='1') then
next_state <= sclear;
else
next_state <= shigh ;
end if;
end case;
end process;
end generate grr;
g1: if 1=direction generate
q <= iq;
end generate g1;
g0: if 0=direction generate
q <= not iq;
end generate g0;
end syn;
|
mit
|
1226d447f28afceee370e2d12ee803ba
| 0.605505 | 3.523232 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/db/alt_dspbuilder_multiplier.vhd
| 2 | 2,483 |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_multiplier is
generic (
DEDICATED_MULTIPLIER_CIRCUITRY : string := "AUTO";
SIGNED : natural := 0;
OUTPUTMSB : integer := 8;
AWIDTH : natural := 8;
BWIDTH : natural := 8;
OUTPUTLSB : integer := 0;
PIPELINE : integer := 0
);
port (
user_aclr : in std_logic := '0';
result : out std_logic_vector(OutputMsb-OutputLsb+1-1 downto 0);
clock : in std_logic := '0';
dataa : in std_logic_vector(aWidth-1 downto 0) := (others=>'0');
datab : in std_logic_vector(bWidth-1 downto 0) := (others=>'0');
aclr : in std_logic := '0';
ena : in std_logic := '0'
);
end entity alt_dspbuilder_multiplier;
architecture rtl of alt_dspbuilder_multiplier is
component alt_dspbuilder_multiplier_GNEIWYOKUR is
generic (
DEDICATED_MULTIPLIER_CIRCUITRY : string := "YES";
SIGNED : natural := 0;
OUTPUTMSB : integer := 47;
AWIDTH : natural := 24;
BWIDTH : natural := 24;
OUTPUTLSB : integer := 0;
PIPELINE : integer := 0
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
dataa : in std_logic_vector(24-1 downto 0) := (others=>'0');
datab : in std_logic_vector(24-1 downto 0) := (others=>'0');
ena : in std_logic := '0';
result : out std_logic_vector(48-1 downto 0);
user_aclr : in std_logic := '0'
);
end component alt_dspbuilder_multiplier_GNEIWYOKUR;
begin
alt_dspbuilder_multiplier_GNEIWYOKUR_0: if ((DEDICATED_MULTIPLIER_CIRCUITRY = "YES") and (SIGNED = 0) and (OUTPUTMSB = 47) and (AWIDTH = 24) and (BWIDTH = 24) and (OUTPUTLSB = 0) and (PIPELINE = 0)) generate
inst_alt_dspbuilder_multiplier_GNEIWYOKUR_0: alt_dspbuilder_multiplier_GNEIWYOKUR
generic map(DEDICATED_MULTIPLIER_CIRCUITRY => "YES", SIGNED => 0, OUTPUTMSB => 47, AWIDTH => 24, BWIDTH => 24, OUTPUTLSB => 0, PIPELINE => 0)
port map(aclr => aclr, clock => clock, dataa => dataa, datab => datab, ena => ena, result => result, user_aclr => user_aclr);
end generate;
assert not (((DEDICATED_MULTIPLIER_CIRCUITRY = "YES") and (SIGNED = 0) and (OUTPUTMSB = 47) and (AWIDTH = 24) and (BWIDTH = 24) and (OUTPUTLSB = 0) and (PIPELINE = 0)))
report "Please run generate again" severity error;
end architecture rtl;
|
mit
|
480149027b26da1cd731f4855294b81d
| 0.674184 | 3.337366 | false | false | false | false |
sukinull/hls_stream
|
Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/v_rgb2ycrcb_v7_1/3eff3f1c/hdl/v_rgb2ycrcb_v7_1_vh_rfs.vhd
| 1 | 335,143 |
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v4PEmDUM4i0x7O5bpMBpCziPh1PXQB48cud17PdnSIYQLvio5sUd0JILU8NDufY4SFqMD6ZpWJs6
y7NudQCK5Mp/YuoJO7E0WTGsXod01TzxeDG87Dgxa+PQz0joc2hg7a4tcpNMA2y/OkZ9+ZOWYY4u
IEoMvs9dIHTT3M+q0R2DGo3NW/VVBPf56ErzZxmMdqbLf6e53koAVDOjSAu/Nfsj4VC0U71At31A
JSzEvGce0D62RGlgRbH04f2ximi3fKAIJ5jKgUAi+fkatdwmyrOSzN2/UN1o3JsiT0wdRMWOKFTs
H5MzuvgCrKKk1IMhK6Qsum1qSX2Aa4pT1kgkRnSyu03VtdAjq+dhboNbISM7/vNC542Qfax6zA==
`protect end_protected
|
gpl-2.0
|
4c5d9b63a333d222b00a13fde49607f1
| 0.955186 | 1.828774 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_cast_GNCCZ56SYK.vhd
| 4 | 855 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNCCZ56SYK is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(23 downto 0);
output : out std_logic_vector(24 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNCCZ56SYK is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 24 ,
width_inr=> 0,
width_outl=> 25,
width_outr=> 0,
lpm_signed=> BusIsSigned ,
round=> round,
satur=> saturate)
port map (
xin(23 downto 0) => input,
yout => output
);
end architecture;
|
mit
|
e3bcf1e1046fe819c419e9596222c547
| 0.65731 | 3.131868 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_pipelined_adder_GNWEIMU3MK.vhd
| 8 | 1,300 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_pipelined_adder_GNWEIMU3MK is
generic ( width : natural := 0;
pipeline : integer := 0);
port(
aclr : in std_logic;
add_sub : in std_logic;
cin : in std_logic;
clock : in std_logic;
cout : out std_logic;
dataa : in std_logic_vector((width)-1 downto 0);
datab : in std_logic_vector((width)-1 downto 0);
ena : in std_logic;
result : out std_logic_vector((width)-1 downto 0);
user_aclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_pipelined_adder_GNWEIMU3MK is
signal cin_internal : std_logic;
Begin
cin_internal <= '1';
-- DSP Builder Block - Simulink Block "PipelinedAdder"
PipelinedAdderi : alt_dspbuilder_sLpmAddSub Generic map (
or_aclr_inputs => true,
width => width,
pipeline => pipeline,
IsUnsigned => 1 )
port map (
clock => clock,
clken => ena,
aclr => aclr,
user_aclr => user_aclr,
cin => cin_internal,
add_sub => '0' ,
dataa => dataa,
datab => datab,
cout => cout,
result => result);
end architecture;
|
mit
|
d142252756fdaea95b0522891d608517
| 0.636154 | 2.908277 | false | false | false | false |
michaelmiehling/A25_VME_TB
|
16x001-00_src/Source/iram32_pkg.vhd
| 1 | 21,311 |
---------------------------------------------------------------
-- Title : Wishbone RAM for simulation
-- Project : -
---------------------------------------------------------------
-- File : iram32_sim.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 13.12.2007
---------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : -
---------------------------------------------------------------
-- Description :
--
--
---------------------------------------------------------------
-- Hierarchy:
-- iram32_sim.vhd
-- iram_pkg.vhd
---------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE work.print_pkg.all;
USE work.conversions.to_hex_str;
PACKAGE iram32_pkg IS
CONSTANT ADR_BITS : integer := 32;
CONSTANT DAT_BITS : integer := 32;
CONSTANT SEL_BITS : integer := DAT_BITS/8;
CONSTANT ACC_REQ_BUFFER_SIZE : integer:=1000;
CONSTANT WRDAT_BUFFER_SIZE : integer:=1000;
CONSTANT WRADR_BUFFER_SIZE : integer:=1000;
CONSTANT DISABLE_DATA_WAITSTATES_FOR_NON_SPLIT_TRANSACTION: boolean := TRUE;
TYPE iram32_in_type IS record
d_waitstates : integer; -- number of waitstates for data phases
d_startdelay : integer; -- number of additional waitstates for first data phase acknowledge (a_startdelay will be added)
d_break_delay_position : integer; -- number of data phases of one access after which the break delay appears
d_break_delay_length : integer; -- number of clock cycles as length of break delay
a_waitstates : integer; -- number of waitstates for address phases
a_startdelay : integer; -- number of additional waitstates for first address phase acknowledge
a_break_delay_position : integer; -- number of data phases of one access after which the break delay appears
a_break_delay_length : integer; -- number of clock cycles as length of break delay
config : boolean; -- enable iram configuration
err_answer : boolean; -- if true, requests will be answered with error
conf_req : boolean; -- changes on signal will call iram subfunctions
write_req : boolean; -- if TRUE during conf_req state changes, write request to iram is requested
-- if FALSE during conf_req state changes, read request from iram is requested
adr : std_logic_vector(ADR_BITS-1 DOWNTO 0); -- address for config read write access
wr_dat : std_logic_vector(DAT_BITS-1 DOWNTO 0); -- write data to iram
dealloc_iram : boolean; -- if TRUE during conf_req state changes, iram contents will be cleared
external_ws : boolean; -- if TRUE, external waitstate interface is used for generation of waitstates
-- if FALSE, iram parameters a_waitstates, a_startdelay, d_waitstates, d_startdelay,
-- break_delay_position, break_delay_lengthare used for generation of waitstates
END record;
TYPE iram32_out_type IS record
conf_ack : boolean; -- if conf_req has changed state, subfunction end will result in conf_ack state change
rd_dat : std_logic_vector(DAT_BITS-1 DOWNTO 0); -- read data to iram
END record;
TYPE iram32_acc_req_type IS record
we : std_logic;
adr : std_logic_vector(ADR_BITS-1 DOWNTO 0);
cti : std_logic_vector(2 DOWNTO 0);
time_cnt : natural;
st_flag : boolean;
eob_flag : boolean;
END record;
TYPE iram32_acc_req_buffer IS array (0 TO ACC_REQ_BUFFER_SIZE-1) OF iram32_acc_req_type;
TYPE iram32_wrdat_type IS record
dat : std_logic_vector(DAT_BITS-1 DOWNTO 0);
sel : std_logic_vector((DAT_BITS/8)-1 DOWNTO 0);
END record;
TYPE iram32_wrdat_buffer IS array (0 TO ACC_REQ_BUFFER_SIZE-1) OF iram32_wrdat_type;
TYPE iram32_wradr_type IS record
adr : std_logic_vector(ADR_BITS-1 DOWNTO 0);
END record;
TYPE iram32_wradr_buffer IS array (0 TO ACC_REQ_BUFFER_SIZE-1) OF iram32_wradr_type;
TYPE iram32_mem_entry;
TYPE iram32_entry_ptr IS access iram32_mem_entry;
TYPE iram32_mem_entry IS record
address : integer;
data : std_logic_vector(DAT_BITS-1 DOWNTO 0);
nxt : iram32_entry_ptr;
END record;
TYPE iram32_head IS record
num_entries : integer;
list_ptr : iram32_entry_ptr;
END record;
TYPE iram32_head_ptr IS access iram32_head;
TYPE protected_shared_variable_natural IS protected
PROCEDURE set(value : natural);
impure FUNCTION get RETURN natural;
END protected protected_shared_variable_natural;
PROCEDURE incr( value : INOUT natural;
limit : IN natural;
wrap : IN boolean
) ;
CONSTANT WRAP_ON : boolean := TRUE;
CONSTANT WRAP_OFF: boolean := FALSE;
PROCEDURE gen_req(
SIGNAL req : OUT boolean;
SIGNAL ack : IN boolean
);
PROCEDURE gen_ack(
SIGNAL req : IN boolean;
SIGNAL ack : OUT boolean
);
PROCEDURE wr_data (
CONSTANT location : IN integer;
CONSTANT data : IN std_logic_vector(DAT_BITS-1 DOWNTO 0);
CONSTANT byte : IN std_logic_vector(SEL_BITS-1 DOWNTO 0);
VARIABLE first : INOUT iram32_head_ptr;
VARIABLE msg_on : IN boolean
);
PROCEDURE rd_data (
CONSTANT location : IN integer;
VARIABLE data : OUT std_logic_vector(DAT_BITS-1 DOWNTO 0);
VARIABLE allocated : OUT boolean;
VARIABLE first : INOUT iram32_head_ptr;
VARIABLE msg_on : IN boolean
);
PROCEDURE dealloc_data (
VARIABLE first : INOUT iram32_head_ptr
) ;
PROCEDURE rd_iram ( SIGNAL iram_in : OUT iram32_in_type;
SIGNAL iram_out : IN iram32_out_type;
adr : IN std_logic_vector(ADR_BITS-1 DOWNTO 0);
dat : OUT std_logic_vector(DAT_BITS-1 DOWNTO 0)
);
PROCEDURE wr_iram ( SIGNAL iram_in : OUT iram32_in_type;
SIGNAL iram_out : IN iram32_out_type;
adr : IN std_logic_vector(ADR_BITS-1 DOWNTO 0);
dat : IN std_logic_vector(DAT_BITS-1 DOWNTO 0)
) ;
PROCEDURE deallocate_iram (
SIGNAL iram_in : OUT iram32_in_type;
SIGNAL iram_out : IN iram32_out_type
) ;
PROCEDURE conf_iram32 ( SIGNAL iram_in : OUT iram32_in_type;
SIGNAL iram_out : IN iram32_out_type;
external_ws : IN boolean;
a_startdelay : IN integer;
a_waitstates : IN integer;
d_startdelay : IN integer;
d_waitstates : IN integer;
a_break_delay_pos : IN integer;
a_break_delay_len : IN integer;
d_break_delay_pos : IN integer;
d_break_delay_len : IN integer
);
END iram32_pkg;
PACKAGE BODY iram32_pkg IS
TYPE protected_shared_variable_natural IS protected BODY
VARIABLE stored: natural;
PROCEDURE set(value : natural) IS
BEGIN
stored := value;
END PROCEDURE set;
impure FUNCTION get RETURN natural IS
BEGIN
RETURN stored;
END FUNCTION get;
END protected BODY protected_shared_variable_natural;
--------------------------------------------------------------------------------------------
PROCEDURE incr( value : INOUT natural;
limit : IN natural;
wrap : IN boolean
) IS
BEGIN
IF value = limit-1 THEN
IF wrap THEN
value := 0;
END IF;
ELSE
value := value + 1;
END IF;
END PROCEDURE;
--------------------------------------------------------------------------------------------
PROCEDURE gen_req(
SIGNAL req : OUT boolean;
SIGNAL ack : IN boolean
) IS
BEGIN
IF ack /= FALSE THEN
WAIT until ack = FALSE;
END IF;
req <= TRUE;
WAIT until ack = TRUE;
req <= FALSE;
END PROCEDURE;
--------------------------------------------------------------------------------------------
PROCEDURE gen_ack(
SIGNAL req : IN boolean;
SIGNAL ack : OUT boolean
) IS
BEGIN
IF req /= TRUE THEN
WAIT until req = TRUE;
END IF;
ack <= TRUE;
WAIT until req = FALSE;
ack <= FALSE;
END PROCEDURE;
--------------------------------------------------------------------------------------------
PROCEDURE conf_iram32 ( SIGNAL iram_in : OUT iram32_in_type;
SIGNAL iram_out : IN iram32_out_type;
external_ws : IN boolean;
a_startdelay : IN integer;
a_waitstates : IN integer;
d_startdelay : IN integer;
d_waitstates : IN integer;
a_break_delay_pos : IN integer;
a_break_delay_len : IN integer;
d_break_delay_pos : IN integer;
d_break_delay_len : IN integer
) IS
BEGIN
IF iram_out.conf_ack /= FALSE THEN WAIT until iram_out.conf_ack = FALSE; END IF;
iram_in.write_req <= FALSE;
iram_in.adr <= (OTHERS => '0');
iram_in.config <= TRUE;
iram_in.a_startdelay <= a_startdelay;
iram_in.a_waitstates <= a_waitstates;
iram_in.d_startdelay <= d_startdelay;
iram_in.d_waitstates <= d_waitstates;
iram_in.a_break_delay_position <= a_break_delay_pos;
iram_in.a_break_delay_length <= a_break_delay_len;
iram_in.d_break_delay_position <= d_break_delay_pos;
iram_in.d_break_delay_length <= d_break_delay_len;
iram_in.external_ws <= external_ws;
iram_in.conf_req <= TRUE;
IF iram_out.conf_ack /= TRUE THEN
WAIT until iram_out.conf_ack = TRUE;
END IF;
iram_in.conf_req <= FALSE;
IF iram_out.conf_ack /= FALSE THEN
WAIT until iram_out.conf_ack = FALSE;
END IF;
iram_in.dealloc_iram <= FALSE;
iram_in.config <= FALSE;
WAIT FOR 1 us;
END PROCEDURE conf_iram32;
--------------------------------------------------------------------------------------------
PROCEDURE deallocate_iram (
SIGNAL iram_in : OUT iram32_in_type;
SIGNAL iram_out : IN iram32_out_type
) IS
BEGIN
IF iram_out.conf_ack /= FALSE THEN WAIT until iram_out.conf_ack = FALSE; END IF;
iram_in.write_req <= FALSE;
iram_in.wr_dat <= (OTHERS => '0');
iram_in.adr <= (OTHERS => '0');
iram_in.dealloc_iram <= TRUE;
iram_in.conf_req <= TRUE;
WAIT until iram_out.conf_ack = TRUE;
iram_in.conf_req <= FALSE;
WAIT until iram_out.conf_ack = FALSE;
iram_in.dealloc_iram <= FALSE;
END PROCEDURE deallocate_iram;
--------------------------------------------------------------------------------------------
PROCEDURE wr_iram ( SIGNAL iram_in : OUT iram32_in_type;
SIGNAL iram_out : IN iram32_out_type;
adr : IN std_logic_vector(ADR_BITS-1 DOWNTO 0);
dat : IN std_logic_vector(DAT_BITS-1 DOWNTO 0)
) IS
BEGIN
IF iram_out.conf_ack /= FALSE THEN WAIT until iram_out.conf_ack = FALSE; END IF;
iram_in.write_req <= TRUE;
iram_in.wr_dat <= dat;
iram_in.adr <= adr;
iram_in.conf_req <= TRUE;
WAIT until iram_out.conf_ack = TRUE;
iram_in.conf_req <= FALSE;
WAIT until iram_out.conf_ack = FALSE;
END PROCEDURE wr_iram;
--------------------------------------------------------------------------------------------
PROCEDURE rd_iram ( SIGNAL iram_in : OUT iram32_in_type;
SIGNAL iram_out : IN iram32_out_type;
adr : IN std_logic_vector(ADR_BITS-1 DOWNTO 0);
dat : OUT std_logic_vector(DAT_BITS-1 DOWNTO 0)
) IS
BEGIN
IF iram_out.conf_ack /= FALSE THEN WAIT until iram_out.conf_ack = FALSE; END IF;
iram_in.write_req <= FALSE;
iram_in.adr <= adr;
iram_in.conf_req <= TRUE;
WAIT until iram_out.conf_ack = TRUE;
iram_in.conf_req <= FALSE;
WAIT until iram_out.conf_ack = FALSE;
dat := iram_out.rd_dat;
END PROCEDURE rd_iram;
--------------------------------------------------------------------------------------------
PROCEDURE wr_data (
CONSTANT location : IN integer;
CONSTANT data : IN std_logic_vector(DAT_BITS-1 DOWNTO 0);
CONSTANT byte : IN std_logic_vector(SEL_BITS-1 DOWNTO 0);
VARIABLE first : INOUT iram32_head_ptr;
VARIABLE msg_on : IN boolean
) IS
VARIABLE temp_ptr : iram32_entry_ptr;
VARIABLE new_ptr : iram32_entry_ptr;
VARIABLE prev_ptr : iram32_entry_ptr;
VARIABLE done : boolean:=FALSE;
VARIABLE long_location: integer;
BEGIN
done:= FALSE; -- set done to true when allocation occurs
long_location := location/((data'high+1)/8);
IF msg_on THEN
print_cycle(" IRAM - wr_data: ", CONV_STD_LOGIC_VECTOR(location, ADR_BITS), data, byte(3 DOWNTO 0), " ");
END IF;
IF first.num_entries = 0 THEN -- first access to memory
first.list_ptr := new iram32_mem_entry;
first.num_entries := 1;
first.list_ptr.address := long_location;
FOR i IN byte'high DOWNTO byte'low LOOP
IF byte(i) = '1' THEN
first.list_ptr.data(i*8+7 DOWNTO i*8) := data(i*8+7 DOWNTO i*8);
END IF;
END LOOP;
first.list_ptr.nxt := null;
done := TRUE;
ELSIF long_location < first.list_ptr.address THEN -- address is lowest value so far in allocation to put at head of list
new_ptr := new iram32_mem_entry;
FOR i IN byte'high DOWNTO byte'low LOOP
IF byte(i) = '1' THEN
new_ptr.data(i*8+7 DOWNTO i*8) := data(i*8+7 DOWNTO i*8);
END IF;
END LOOP;
new_ptr.nxt := first.list_ptr;
new_ptr.address := long_location;
first.list_ptr := new_ptr;
first.num_entries := first.num_entries + 1;
done := TRUE;
ELSE -- location must be >= first.list_ptr.address
temp_ptr := first.list_ptr;
while temp_ptr /= null AND NOT done LOOP
IF temp_ptr.address = long_location THEN -- address already allocated
FOR i IN byte'high DOWNTO byte'low LOOP
IF byte(i) = '1' THEN
temp_ptr.data(i*8+7 DOWNTO i*8) := data(i*8+7 DOWNTO i*8);
END IF;
END LOOP;
done := TRUE;
ELSIF temp_ptr.address > long_location THEN
new_ptr := new iram32_mem_entry;
new_ptr.address := long_location;
FOR i IN byte'high DOWNTO byte'low LOOP
IF byte(i) = '1' THEN
new_ptr.data(i*8+7 DOWNTO i*8) := data(i*8+7 DOWNTO i*8);
END IF;
END LOOP;
new_ptr.nxt := temp_ptr;
prev_ptr.nxt := new_ptr; -- break pointer chain and insert new_ptr
first.num_entries := first.num_entries + 1;
done := TRUE;
ELSE
prev_ptr := temp_ptr;
temp_ptr := temp_ptr.nxt;
END IF;
END LOOP;
IF NOT done THEN
new_ptr := new iram32_mem_entry;
new_ptr.address := long_location;
FOR i IN byte'high DOWNTO byte'low LOOP
IF byte(i) = '1' THEN
new_ptr.data(i*8+7 DOWNTO i*8) := data(i*8+7 DOWNTO i*8);
END IF;
END LOOP;
new_ptr.nxt := null; -- add new_ptr TO END OF chain
prev_ptr.nxt := new_ptr;
first.num_entries := first.num_entries + 1;
done := TRUE;
END IF;
END IF;
END wr_data;
--------------------------------------------------------------------------------------------
PROCEDURE rd_data (
CONSTANT location : IN integer;
VARIABLE data : OUT std_logic_vector(DAT_BITS-1 DOWNTO 0);
VARIABLE allocated : OUT boolean;
VARIABLE first : INOUT iram32_head_ptr;
VARIABLE msg_on : IN boolean
) IS
VARIABLE temp_ptr : iram32_entry_ptr;
VARIABLE is_allocated : boolean;
VARIABLE data_int : std_logic_vector(data'range);
VARIABLE long_location: integer;
BEGIN
-- set allocated to true when read hits already allocated spot
is_allocated := FALSE;
long_location := location/((data'high+1)/8);
IF (first.list_ptr /= null AND first.num_entries /= 0 AND long_location >= first.list_ptr.address) THEN
temp_ptr := first.list_ptr;
while (temp_ptr /= null AND NOT is_allocated AND long_location >= temp_ptr.address) LOOP
IF temp_ptr.address = long_location THEN -- address has been allocated
data_int := temp_ptr.data;
is_allocated := TRUE;
ELSE
temp_ptr := temp_ptr.nxt;
END IF;
END LOOP;
END IF;
IF NOT is_allocated THEN
data_int := (data_int'range => '1');
END IF;
IF msg_on THEN
print_cycle(" IRAM - rd_data: ", CONV_STD_LOGIC_VECTOR(location, ADR_BITS), data_int, "1111", " ");
END IF;
allocated := is_allocated;
data := data_int;
END rd_data;
--------------------------------------------------------------------------------------------
PROCEDURE dealloc_data (
VARIABLE first : INOUT iram32_head_ptr
) IS
VARIABLE next_ptr : iram32_entry_ptr;
BEGIN
WHILE first.list_ptr.nxt /= NULL LOOP
next_ptr := first.list_ptr.nxt;
deallocate(first.list_ptr);
first.list_ptr := next_ptr;
END LOOP;
deallocate(first.list_ptr);
first.num_entries := 0;
END dealloc_data;
END;
|
gpl-3.0
|
9dd9804434094f90977b8295292e08bb
| 0.480409 | 4.491254 | false | false | false | false |
nulldozer/purisc
|
Compute_Group/MAGIC_clocked/RAM_2.vhd
| 1 | 10,399 |
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: RAM_2.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 14.0.0 Build 200 06/17/2014 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus II License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY RAM_2 IS
PORT
(
aclr : IN STD_LOGIC := '0';
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END RAM_2;
ARCHITECTURE SYN OF ram_2 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
q_a <= sub_wire0(31 DOWNTO 0);
q_b <= sub_wire1(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK0",
init_file => "RAM_2.mif",
intended_device_family => "Cyclone IV E",
lpm_type => "altsyncram",
numwords_a => 1024,
numwords_b => 1024,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "CLEAR0",
outdata_aclr_b => "CLEAR0",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_mixed_ports => "OLD_DATA",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => 10,
widthad_b => 10,
width_a => 32,
width_b => 32,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK0"
)
PORT MAP (
aclr0 => aclr,
address_a => address_a,
address_b => address_b,
clock0 => clock,
data_a => data_a,
data_b => data_b,
wren_a => wren_a,
wren_b => wren_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "1"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "32768"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "RAM_2.mif"
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "1"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: INIT_FILE STRING "RAM_2.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "CLEAR0"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "CLEAR0"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
-- Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL "address_a[9..0]"
-- Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL "address_b[9..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data_a 0 0 32 0 INPUT NODEFVAL "data_a[31..0]"
-- Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL "data_b[31..0]"
-- Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL "q_a[31..0]"
-- Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]"
-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
-- Retrieval info: CONNECT: @aclr0 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0
-- Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 32 0 data_a 0 0 32 0
-- Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-- Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0
-- Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_2.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_2.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_2_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
gpl-2.0
|
ae9487bf6d4e63a2e5c3190aa6357593
| 0.666314 | 3.290823 | false | false | false | false |
freecores/t48
|
bench/vhdl/tb_t8243.vhd
| 1 | 18,144 |
-------------------------------------------------------------------------------
--
-- The testbench for t8243 core.
--
-- $Id: tb_t8243.vhd,v 1.1 2006-07-14 01:02:47 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity tb_t8243 is
end tb_t8243;
use work.t48_core_comp_pack.all;
use work.t8243_comp_pack.t8243_sync_notri;
use work.t48_tb_pack.all;
architecture behav of tb_t8243 is
-- clock period, 11 MHz
constant period_c : time := 90 ns;
component if_timing
port(
xtal_i : in std_logic;
ale_i : in std_logic;
psen_n_i : in std_logic;
rd_n_i : in std_logic;
wr_n_i : in std_logic;
prog_n_i : in std_logic;
db_bus_i : in std_logic_vector(7 downto 0);
p2_i : in std_logic_vector(7 downto 0)
);
end component;
component lpm_rom
generic (
LPM_WIDTH : positive;
LPM_TYPE : string := "LPM_ROM";
LPM_WIDTHAD : positive;
LPM_NUMWORDS : natural := 0;
LPM_FILE : string;
LPM_ADDRESS_CONTROL : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_HINT : string := "UNUSED"
);
port (
address : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
inclock : in std_logic;
outclock : in std_logic;
memenab : in std_logic;
q : out std_logic_vector(LPM_WIDTH-1 downto 0)
);
end component;
signal xtal_s : std_logic;
signal xtal_n_s : std_logic;
signal res_n_s : std_logic;
signal xtal3_s : std_logic;
signal int_n_s : std_logic;
signal ale_s : std_logic;
signal rom_addr_s : std_logic_vector(11 downto 0);
signal rom_data_s : std_logic_vector( 7 downto 0);
signal ram_data_to_s : std_logic_vector( 7 downto 0);
signal ram_data_from_s : std_logic_vector( 7 downto 0);
signal ram_addr_s : std_logic_vector( 7 downto 0);
signal ram_we_s : std_logic;
signal p1_s : std_logic_vector( 7 downto 0);
signal t48_p1_s : std_logic_vector( 7 downto 0);
signal p1_low_imp_s : std_logic;
signal p2_s : std_logic_vector( 7 downto 0);
signal t48_p2_s : std_logic_vector( 7 downto 0);
signal p2l_low_imp_s : std_logic;
signal p2h_low_imp_s : std_logic;
signal psen_n_s : std_logic;
signal prog_n_s : std_logic;
signal bus_s : std_logic_vector( 7 downto 0);
signal t48_bus_s : std_logic_vector( 7 downto 0);
signal bus_dir_s : std_logic;
signal ext_mem_addr_q : std_logic_vector( 7 downto 0);
signal ext_ram_data_from_s : std_logic_vector( 7 downto 0);
signal ext_ram_we_q : std_logic;
signal rd_n_s : std_logic;
signal wr_n_s : std_logic;
signal ext_rom_data_s : std_logic_vector( 7 downto 0);
signal ext_rom_addr_s : std_logic_vector(11 downto 0);
signal tb_p1_q : std_logic_vector( 7 downto 0);
signal tb_p2_q : std_logic_vector( 7 downto 0);
signal ext_mem_sel_we_q : boolean;
signal ena_ext_ram_q : boolean;
signal ena_tb_periph_q : boolean;
signal t8243_p2_s : std_logic_vector(3 downto 0);
signal t8243_p2_en_s : std_logic;
signal p4_s,
p5_s,
p6_s,
p7_s : std_logic_vector(3 downto 0);
signal p4_p6_s,
p5_p7_s : std_logic_vector(3 downto 0);
signal p4_en_s,
p5_en_s,
p6_en_s,
p7_en_s : std_logic;
signal zero_s : std_logic;
signal one_s : std_logic;
signal zero_byte_s : std_logic_vector( 7 downto 0);
begin
zero_s <= '0';
one_s <= '1';
zero_byte_s <= (others => '0');
-----------------------------------------------------------------------------
-- Internal ROM, 2k bytes
-- Initialized by file rom_t49.hex.
-----------------------------------------------------------------------------
rom_internal_2k : lpm_rom
generic map (
LPM_WIDTH => 8,
LPM_TYPE => "LPM_ROM",
LPM_WIDTHAD => 11,
LPM_NUMWORDS => 2 ** 11,
LPM_FILE => "rom_t49.hex",
LPM_ADDRESS_CONTROL => "REGISTERED",
LPM_OUTDATA => "UNREGISTERED",
LPM_HINT => "UNUSED"
)
port map (
address => rom_addr_s(10 downto 0),
inclock => xtal_s,
outclock => zero_s, -- unused
memenab => one_s,
q => rom_data_s
);
-----------------------------------------------------------------------------
-- External ROM, 2k bytes
-- Initialized by file rom_t49_ext.hex.
-----------------------------------------------------------------------------
ext_rom_addr_s(11 downto 8) <= t48_p2_s(3 downto 0);
ext_rom_addr_s( 7 downto 0) <= ext_mem_addr_q;
rom_external_2k : lpm_rom
generic map (
LPM_WIDTH => 8,
LPM_TYPE => "LPM_ROM",
LPM_WIDTHAD => 11,
LPM_NUMWORDS => 2 ** 11,
LPM_FILE => "rom_t49_ext.hex",
LPM_ADDRESS_CONTROL => "REGISTERED",
LPM_OUTDATA => "UNREGISTERED",
LPM_HINT => "UNUSED"
)
port map (
address => ext_rom_addr_s(10 downto 0),
inclock => xtal_s,
outclock => zero_s, -- unused
memenab => one_s,
q => ext_rom_data_s
);
-----------------------------------------------------------------------------
-- Internal RAM, 256 bytes
-----------------------------------------------------------------------------
ram_256 : generic_ram_ena
generic map (
addr_width_g => 8,
data_width_g => 8
)
port map (
clk_i => xtal_s,
a_i => ram_addr_s,
we_i => ram_we_s,
ena_i => one_s,
d_i => ram_data_to_s,
d_o => ram_data_from_s
);
-----------------------------------------------------------------------------
-- External RAM, 256 bytes
-----------------------------------------------------------------------------
ext_ram_b : generic_ram_ena
generic map (
addr_width_g => 8,
data_width_g => 8
)
port map (
clk_i => xtal_s,
a_i => ext_mem_addr_q,
we_i => ext_ram_we_q,
ena_i => one_s,
d_i => bus_s,
d_o => ext_ram_data_from_s
);
t48_core_b : t48_core
generic map (
xtal_div_3_g => 1,
register_mnemonic_g => 1,
include_port1_g => 1,
include_port2_g => 1,
include_bus_g => 1,
include_timer_g => 1,
sample_t1_state_g => 4
)
port map (
xtal_i => xtal_s,
xtal_en_i => one_s,
reset_i => res_n_s,
t0_i => p1_s(0),
t0_o => open,
t0_dir_o => open,
int_n_i => int_n_s,
ea_i => rom_addr_s(11),
rd_n_o => rd_n_s,
psen_n_o => psen_n_s,
wr_n_o => wr_n_s,
ale_o => ale_s,
db_i => bus_s,
db_o => t48_bus_s,
db_dir_o => bus_dir_s,
t1_i => p1_s(1),
p2_i => p2_s,
p2_o => t48_p2_s,
p2l_low_imp_o => p2l_low_imp_s,
p2h_low_imp_o => p2h_low_imp_s,
p1_i => p1_s,
p1_o => t48_p1_s,
p1_low_imp_o => p1_low_imp_s,
prog_n_o => prog_n_s,
clk_i => xtal_s,
en_clk_i => xtal3_s,
xtal3_o => xtal3_s,
dmem_addr_o => ram_addr_s,
dmem_we_o => ram_we_s,
dmem_data_i => ram_data_from_s,
dmem_data_o => ram_data_to_s,
pmem_addr_o => rom_addr_s,
pmem_data_i => rom_data_s
);
if_timing_b : if_timing
port map (
xtal_i => xtal_s,
ale_i => ale_s,
psen_n_i => psen_n_s,
rd_n_i => rd_n_s,
wr_n_i => wr_n_s,
prog_n_i => prog_n_s,
db_bus_i => bus_s,
p2_i => t48_p2_s
);
t8243_sync_notri_b : t8243_sync_notri
port map (
clk_i => xtal_s,
clk_en_i => one_s,
reset_n_i => one_s,
cs_n_i => zero_s,
prog_n_i => prog_n_s,
p2_i => t48_p2_s(3 downto 0),
p2_o => t8243_p2_s,
p2_en_o => t8243_p2_en_s,
p4_i => p4_p6_s,
p4_o => p4_s,
p4_en_o => p4_en_s,
p5_i => p5_p7_s,
p5_o => p5_s,
p5_en_o => p5_en_s,
p6_i => p4_p6_s,
p6_o => p6_s,
p6_en_o => p6_en_s,
p7_i => p5_p7_s,
p7_o => p7_s,
p7_en_o => p7_en_s
);
p4_p6_s <= p4_s
when p4_en_s = '1' else
(others => 'Z');
p5_p7_s <= p5_s
when p5_en_s = '1' else
(others => 'Z');
p4_p6_s <= p6_s
when p6_en_s = '1' else
(others => 'Z');
p5_p7_s <= p7_s
when p7_en_s = '1' else
(others => 'Z');
-----------------------------------------------------------------------------
-- Port logic
--
ports: process (t48_p1_s,
p1_low_imp_s,
t48_p2_s,
p2l_low_imp_s,
p2h_low_imp_s)
function t48_port_f(t48_p : std_logic_vector;
low_imp : std_logic) return std_logic_vector is
variable p_v : std_logic_vector(t48_p'range);
begin
if low_imp = '1' then
p_v := t48_p;
else
for i in p_v'range loop
if t48_p(i) = '1' then
p_v(i) := 'H';
else
p_v(i) := t48_p(i);
end if;
end loop;
end if;
return p_v;
end;
begin
p1_s <= t48_port_f(t48_p => t48_p1_s,
low_imp => p1_low_imp_s);
p2_s(3 downto 0) <= t48_port_f(t48_p => t48_p2_s(3 downto 0),
low_imp => p2l_low_imp_s);
p2_s(7 downto 4) <= t48_port_f(t48_p => t48_p2_s(7 downto 4),
low_imp => p2h_low_imp_s);
end process ports;
--
-----------------------------------------------------------------------------
t8243_p2: process (t8243_p2_s,
t8243_p2_en_s)
begin
p2_s <= (others => 'Z');
if t8243_p2_en_s = '1' then
p2_s(3 downto 0) <= t8243_p2_s;
end if;
end process t8243_p2;
bus_s <= t48_bus_s
when bus_dir_s = '1' else
(others => 'Z');
bus_s <= ext_ram_data_from_s
when rd_n_s = '0' and ena_ext_ram_q else
(others => 'Z');
bus_s <= ext_rom_data_s
when psen_n_s = '0' else
(others => 'Z');
-----------------------------------------------------------------------------
-- External memory access signals
--
ext_mem: process (wr_n_s,
ext_mem_addr_q,
ena_ext_ram_q,
ale_s,
bus_s,
xtal_s)
begin
if ale_s'event and ale_s = '0' then
if not is_X(bus_s) then
ext_mem_addr_q <= bus_s;
else
ext_mem_addr_q <= (others => '0');
end if;
end if;
if wr_n_s'event and wr_n_s = '1' then
-- write enable for external RAM
if ena_ext_ram_q then
ext_ram_we_q <= '1';
end if;
-- process external memory selector
if ext_mem_addr_q = "11111111" then
ext_mem_sel_we_q <= true;
end if;
end if;
if xtal_s'event and xtal_s = '1' then
ext_ram_we_q <= '0';
ext_mem_sel_we_q <= false;
end if;
end process ext_mem;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process ext_mem_sel
--
-- Purpose:
-- Select external memory address space.
-- This is either
-- + external RAM
-- + testbench peripherals
--
ext_mem_sel: process (res_n_s, xtal_s)
begin
if res_n_s = '0' then
ena_ext_ram_q <= true;
ena_tb_periph_q <= false;
elsif xtal_s'event and xtal_s = '1' then
if ext_mem_sel_we_q then
if bus_s(0) = '1' then
ena_ext_ram_q <= true;
else
ena_ext_ram_q <= false;
end if;
if bus_s(1) = '1' then
ena_tb_periph_q <= true;
else
ena_tb_periph_q <= false;
end if;
end if;
end if;
end process ext_mem_sel;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process tb_periph
--
-- Purpose:
-- Implements the testbenc peripherals driving P1 and P2.
--
tb_periph: process (res_n_s, wr_n_s)
function oc_f (pX : std_logic_vector) return std_logic_vector is
variable r_v : std_logic_vector(pX'range);
begin
for i in pX'range loop
if pX(i) = '0' then
r_v(i) := '0';
else
r_v(i) := 'H';
end if;
end loop;
return r_v;
end;
begin
if res_n_s = '0' then
tb_p1_q <= (others => 'H');
tb_p2_q <= (others => 'H');
elsif wr_n_s'event and wr_n_s = '1' then
if ena_tb_periph_q then
case ext_mem_addr_q is
-- P1
when "00000000" =>
tb_p1_q <= oc_f(t48_bus_s);
-- P2
when "00000001" =>
tb_p2_q <= oc_f(t48_bus_s);
when others =>
null;
end case;
end if;
end if;
end process tb_periph;
--
-----------------------------------------------------------------------------
p1_s <= tb_p1_q;
p2_s <= tb_p2_q;
xtal_n_s <= not xtal_s;
-----------------------------------------------------------------------------
-- The clock generator
--
clk_gen: process
begin
xtal_s <= '0';
wait for period_c/2;
xtal_s <= '1';
wait for period_c/2;
end process clk_gen;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- The reset generator
--
res_gen: process
begin
res_n_s <= '0';
wait for 5 * period_c;
res_n_s <= '1';
wait;
end process res_gen;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- The interrupt generator
--
int_gen: process
begin
int_n_s <= '1';
wait for 750 * period_c;
int_n_s <= '0';
wait for 45 * period_c;
end process int_gen;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- End of simulation detection
--
eos: process
begin
outer: loop
wait on tb_accu_s;
if tb_accu_s = "10101010" then
wait on tb_accu_s;
if tb_accu_s = "01010101" then
wait on tb_accu_s;
if tb_accu_s = "00000001" then
-- wait for instruction strobe of this move
wait until tb_istrobe_s'event and tb_istrobe_s = '1';
-- wait for next strobe
wait until tb_istrobe_s'event and tb_istrobe_s = '1';
assert false
report "Simulation Result: PASS."
severity note;
else
assert false
report "Simulation Result: FAIL."
severity note;
end if;
assert false
report "End of simulation reached."
severity failure;
end if;
end if;
end loop;
end process eos;
--
-----------------------------------------------------------------------------
end behav;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
|
gpl-2.0
|
533442fe940fa6bf2e3e4c774a68493d
| 0.442626 | 3.439621 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/altera_lnsim/altera_pll/_primary.vhd
| 5 | 26,906 |
library verilog;
use verilog.vl_types.all;
entity altera_pll is
generic(
reference_clock_frequency: string := "0 ps";
fractional_vco_multiplier: string := "false";
pll_type : string := "General";
pll_subtype : string := "General";
number_of_clocks: integer := 1;
operation_mode : string := "internal feedback";
deserialization_factor: integer := 4;
data_rate : integer := 0;
sim_additional_refclk_cycles_to_lock: integer := 0;
output_clock_frequency0: string := "0 ps";
phase_shift0 : string := "0 ps";
duty_cycle0 : integer := 50;
output_clock_frequency1: string := "0 ps";
phase_shift1 : string := "0 ps";
duty_cycle1 : integer := 50;
output_clock_frequency2: string := "0 ps";
phase_shift2 : string := "0 ps";
duty_cycle2 : integer := 50;
output_clock_frequency3: string := "0 ps";
phase_shift3 : string := "0 ps";
duty_cycle3 : integer := 50;
output_clock_frequency4: string := "0 ps";
phase_shift4 : string := "0 ps";
duty_cycle4 : integer := 50;
output_clock_frequency5: string := "0 ps";
phase_shift5 : string := "0 ps";
duty_cycle5 : integer := 50;
output_clock_frequency6: string := "0 ps";
phase_shift6 : string := "0 ps";
duty_cycle6 : integer := 50;
output_clock_frequency7: string := "0 ps";
phase_shift7 : string := "0 ps";
duty_cycle7 : integer := 50;
output_clock_frequency8: string := "0 ps";
phase_shift8 : string := "0 ps";
duty_cycle8 : integer := 50;
output_clock_frequency9: string := "0 ps";
phase_shift9 : string := "0 ps";
duty_cycle9 : integer := 50;
output_clock_frequency10: string := "0 ps";
phase_shift10 : string := "0 ps";
duty_cycle10 : integer := 50;
output_clock_frequency11: string := "0 ps";
phase_shift11 : string := "0 ps";
duty_cycle11 : integer := 50;
output_clock_frequency12: string := "0 ps";
phase_shift12 : string := "0 ps";
duty_cycle12 : integer := 50;
output_clock_frequency13: string := "0 ps";
phase_shift13 : string := "0 ps";
duty_cycle13 : integer := 50;
output_clock_frequency14: string := "0 ps";
phase_shift14 : string := "0 ps";
duty_cycle14 : integer := 50;
output_clock_frequency15: string := "0 ps";
phase_shift15 : string := "0 ps";
duty_cycle15 : integer := 50;
output_clock_frequency16: string := "0 ps";
phase_shift16 : string := "0 ps";
duty_cycle16 : integer := 50;
output_clock_frequency17: string := "0 ps";
phase_shift17 : string := "0 ps";
duty_cycle17 : integer := 50;
m_cnt_hi_div : integer := 1;
m_cnt_lo_div : integer := 1;
m_cnt_bypass_en : string := "false";
m_cnt_odd_div_duty_en: string := "false";
n_cnt_hi_div : integer := 1;
n_cnt_lo_div : integer := 1;
n_cnt_bypass_en : string := "false";
n_cnt_odd_div_duty_en: string := "false";
c_cnt_hi_div0 : integer := 1;
c_cnt_lo_div0 : integer := 1;
c_cnt_bypass_en0: string := "false";
c_cnt_in_src0 : string := "ph_mux_clk";
c_cnt_odd_div_duty_en0: string := "false";
c_cnt_prst0 : integer := 1;
c_cnt_ph_mux_prst0: integer := 0;
c_cnt_hi_div1 : integer := 1;
c_cnt_lo_div1 : integer := 1;
c_cnt_bypass_en1: string := "false";
c_cnt_in_src1 : string := "ph_mux_clk";
c_cnt_odd_div_duty_en1: string := "false";
c_cnt_prst1 : integer := 1;
c_cnt_ph_mux_prst1: integer := 0;
c_cnt_hi_div2 : integer := 1;
c_cnt_lo_div2 : integer := 1;
c_cnt_bypass_en2: string := "false";
c_cnt_in_src2 : string := "ph_mux_clk";
c_cnt_odd_div_duty_en2: string := "false";
c_cnt_prst2 : integer := 1;
c_cnt_ph_mux_prst2: integer := 0;
c_cnt_hi_div3 : integer := 1;
c_cnt_lo_div3 : integer := 1;
c_cnt_bypass_en3: string := "false";
c_cnt_in_src3 : string := "ph_mux_clk";
c_cnt_odd_div_duty_en3: string := "false";
c_cnt_prst3 : integer := 1;
c_cnt_ph_mux_prst3: integer := 0;
c_cnt_hi_div4 : integer := 1;
c_cnt_lo_div4 : integer := 1;
c_cnt_bypass_en4: string := "false";
c_cnt_in_src4 : string := "ph_mux_clk";
c_cnt_odd_div_duty_en4: string := "false";
c_cnt_prst4 : integer := 1;
c_cnt_ph_mux_prst4: integer := 0;
c_cnt_hi_div5 : integer := 1;
c_cnt_lo_div5 : integer := 1;
c_cnt_bypass_en5: string := "false";
c_cnt_in_src5 : string := "ph_mux_clk";
c_cnt_odd_div_duty_en5: string := "false";
c_cnt_prst5 : integer := 1;
c_cnt_ph_mux_prst5: integer := 0;
c_cnt_hi_div6 : integer := 1;
c_cnt_lo_div6 : integer := 1;
c_cnt_bypass_en6: string := "false";
c_cnt_in_src6 : string := "ph_mux_clk";
c_cnt_odd_div_duty_en6: string := "false";
c_cnt_prst6 : integer := 1;
c_cnt_ph_mux_prst6: integer := 0;
c_cnt_hi_div7 : integer := 1;
c_cnt_lo_div7 : integer := 1;
c_cnt_bypass_en7: string := "false";
c_cnt_in_src7 : string := "ph_mux_clk";
c_cnt_odd_div_duty_en7: string := "false";
c_cnt_prst7 : integer := 1;
c_cnt_ph_mux_prst7: integer := 0;
c_cnt_hi_div8 : integer := 1;
c_cnt_lo_div8 : integer := 1;
c_cnt_bypass_en8: string := "false";
c_cnt_in_src8 : string := "ph_mux_clk";
c_cnt_odd_div_duty_en8: string := "false";
c_cnt_prst8 : integer := 1;
c_cnt_ph_mux_prst8: integer := 0;
c_cnt_hi_div9 : integer := 1;
c_cnt_lo_div9 : integer := 1;
c_cnt_bypass_en9: string := "false";
c_cnt_in_src9 : string := "ph_mux_clk";
c_cnt_odd_div_duty_en9: string := "false";
c_cnt_prst9 : integer := 1;
c_cnt_ph_mux_prst9: integer := 0;
c_cnt_hi_div10 : integer := 1;
c_cnt_lo_div10 : integer := 1;
c_cnt_bypass_en10: string := "false";
c_cnt_in_src10 : string := "ph_mux_clk";
c_cnt_odd_div_duty_en10: string := "false";
c_cnt_prst10 : integer := 1;
c_cnt_ph_mux_prst10: integer := 0;
c_cnt_hi_div11 : integer := 1;
c_cnt_lo_div11 : integer := 1;
c_cnt_bypass_en11: string := "false";
c_cnt_in_src11 : string := "ph_mux_clk";
c_cnt_odd_div_duty_en11: string := "false";
c_cnt_prst11 : integer := 1;
c_cnt_ph_mux_prst11: integer := 0;
c_cnt_hi_div12 : integer := 1;
c_cnt_lo_div12 : integer := 1;
c_cnt_bypass_en12: string := "false";
c_cnt_in_src12 : string := "ph_mux_clk";
c_cnt_odd_div_duty_en12: string := "false";
c_cnt_prst12 : integer := 1;
c_cnt_ph_mux_prst12: integer := 0;
c_cnt_hi_div13 : integer := 1;
c_cnt_lo_div13 : integer := 1;
c_cnt_bypass_en13: string := "false";
c_cnt_in_src13 : string := "ph_mux_clk";
c_cnt_odd_div_duty_en13: string := "false";
c_cnt_prst13 : integer := 1;
c_cnt_ph_mux_prst13: integer := 0;
c_cnt_hi_div14 : integer := 1;
c_cnt_lo_div14 : integer := 1;
c_cnt_bypass_en14: string := "false";
c_cnt_in_src14 : string := "ph_mux_clk";
c_cnt_odd_div_duty_en14: string := "false";
c_cnt_prst14 : integer := 1;
c_cnt_ph_mux_prst14: integer := 0;
c_cnt_hi_div15 : integer := 1;
c_cnt_lo_div15 : integer := 1;
c_cnt_bypass_en15: string := "false";
c_cnt_in_src15 : string := "ph_mux_clk";
c_cnt_odd_div_duty_en15: string := "false";
c_cnt_prst15 : integer := 1;
c_cnt_ph_mux_prst15: integer := 0;
c_cnt_hi_div16 : integer := 1;
c_cnt_lo_div16 : integer := 1;
c_cnt_bypass_en16: string := "false";
c_cnt_in_src16 : string := "ph_mux_clk";
c_cnt_odd_div_duty_en16: string := "false";
c_cnt_prst16 : integer := 1;
c_cnt_ph_mux_prst16: integer := 0;
c_cnt_hi_div17 : integer := 1;
c_cnt_lo_div17 : integer := 1;
c_cnt_bypass_en17: string := "false";
c_cnt_in_src17 : string := "ph_mux_clk";
c_cnt_odd_div_duty_en17: string := "false";
c_cnt_prst17 : integer := 1;
c_cnt_ph_mux_prst17: integer := 0;
pll_vco_div : integer := 1;
pll_output_clk_frequency: string := "0 MHz";
pll_cp_current : integer := 0;
pll_bwctrl : integer := 0;
pll_fractional_division: integer := 1;
pll_fractional_cout: integer := 24;
pll_dsm_out_sel : string := "1st_order";
mimic_fbclk_type: string := "gclk";
pll_fbclk_mux_1 : string := "glb";
pll_fbclk_mux_2 : string := "fb_1";
pll_m_cnt_in_src: string := "ph_mux_clk";
pll_vcoph_div : integer := 1;
refclk1_frequency: string := "0 MHz";
pll_clkin_0_src : string := "clk_0";
pll_clkin_1_src : string := "clk_0";
pll_clk_loss_sw_en: string := "false";
pll_auto_clk_sw_en: string := "false";
pll_manu_clk_sw_en: string := "false";
pll_clk_sw_dly : integer := 0
);
port(
refclk : in vl_logic;
refclk1 : in vl_logic;
fbclk : in vl_logic;
rst : in vl_logic;
phase_en : in vl_logic;
updn : in vl_logic;
num_phase_shifts: in vl_logic_vector(2 downto 0);
scanclk : in vl_logic;
cntsel : in vl_logic_vector(4 downto 0);
reconfig_to_pll : in vl_logic_vector(63 downto 0);
extswitch : in vl_logic;
adjpllin : in vl_logic;
cclk : in vl_logic;
outclk : out vl_logic_vector;
fboutclk : out vl_logic;
locked : out vl_logic;
phase_done : out vl_logic;
reconfig_from_pll: out vl_logic_vector(63 downto 0);
activeclk : out vl_logic;
clkbad : out vl_logic_vector(1 downto 0);
phout : out vl_logic_vector(7 downto 0);
lvds_clk : out vl_logic_vector(1 downto 0);
loaden : out vl_logic_vector(1 downto 0);
cascade_out : out vl_logic_vector;
zdbfbclk : inout vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of reference_clock_frequency : constant is 1;
attribute mti_svvh_generic_type of fractional_vco_multiplier : constant is 1;
attribute mti_svvh_generic_type of pll_type : constant is 1;
attribute mti_svvh_generic_type of pll_subtype : constant is 1;
attribute mti_svvh_generic_type of number_of_clocks : constant is 1;
attribute mti_svvh_generic_type of operation_mode : constant is 1;
attribute mti_svvh_generic_type of deserialization_factor : constant is 1;
attribute mti_svvh_generic_type of data_rate : constant is 1;
attribute mti_svvh_generic_type of sim_additional_refclk_cycles_to_lock : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency0 : constant is 1;
attribute mti_svvh_generic_type of phase_shift0 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle0 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency1 : constant is 1;
attribute mti_svvh_generic_type of phase_shift1 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle1 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency2 : constant is 1;
attribute mti_svvh_generic_type of phase_shift2 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle2 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency3 : constant is 1;
attribute mti_svvh_generic_type of phase_shift3 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle3 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency4 : constant is 1;
attribute mti_svvh_generic_type of phase_shift4 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle4 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency5 : constant is 1;
attribute mti_svvh_generic_type of phase_shift5 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle5 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency6 : constant is 1;
attribute mti_svvh_generic_type of phase_shift6 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle6 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency7 : constant is 1;
attribute mti_svvh_generic_type of phase_shift7 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle7 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency8 : constant is 1;
attribute mti_svvh_generic_type of phase_shift8 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle8 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency9 : constant is 1;
attribute mti_svvh_generic_type of phase_shift9 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle9 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency10 : constant is 1;
attribute mti_svvh_generic_type of phase_shift10 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle10 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency11 : constant is 1;
attribute mti_svvh_generic_type of phase_shift11 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle11 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency12 : constant is 1;
attribute mti_svvh_generic_type of phase_shift12 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle12 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency13 : constant is 1;
attribute mti_svvh_generic_type of phase_shift13 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle13 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency14 : constant is 1;
attribute mti_svvh_generic_type of phase_shift14 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle14 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency15 : constant is 1;
attribute mti_svvh_generic_type of phase_shift15 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle15 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency16 : constant is 1;
attribute mti_svvh_generic_type of phase_shift16 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle16 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency17 : constant is 1;
attribute mti_svvh_generic_type of phase_shift17 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle17 : constant is 1;
attribute mti_svvh_generic_type of m_cnt_hi_div : constant is 1;
attribute mti_svvh_generic_type of m_cnt_lo_div : constant is 1;
attribute mti_svvh_generic_type of m_cnt_bypass_en : constant is 1;
attribute mti_svvh_generic_type of m_cnt_odd_div_duty_en : constant is 1;
attribute mti_svvh_generic_type of n_cnt_hi_div : constant is 1;
attribute mti_svvh_generic_type of n_cnt_lo_div : constant is 1;
attribute mti_svvh_generic_type of n_cnt_bypass_en : constant is 1;
attribute mti_svvh_generic_type of n_cnt_odd_div_duty_en : constant is 1;
attribute mti_svvh_generic_type of c_cnt_hi_div0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_lo_div0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_bypass_en0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_odd_div_duty_en0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_hi_div1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_lo_div1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_bypass_en1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_odd_div_duty_en1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_hi_div2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_lo_div2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_bypass_en2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_odd_div_duty_en2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_hi_div3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_lo_div3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_bypass_en3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_odd_div_duty_en3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_hi_div4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_lo_div4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_bypass_en4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_odd_div_duty_en4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_hi_div5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_lo_div5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_bypass_en5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_odd_div_duty_en5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_hi_div6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_lo_div6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_bypass_en6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_odd_div_duty_en6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_hi_div7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_lo_div7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_bypass_en7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_odd_div_duty_en7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_hi_div8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_lo_div8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_bypass_en8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_odd_div_duty_en8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_hi_div9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_lo_div9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_bypass_en9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_odd_div_duty_en9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_hi_div10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_lo_div10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_bypass_en10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_odd_div_duty_en10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_hi_div11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_lo_div11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_bypass_en11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_odd_div_duty_en11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_hi_div12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_lo_div12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_bypass_en12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_odd_div_duty_en12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_hi_div13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_lo_div13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_bypass_en13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_odd_div_duty_en13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_hi_div14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_lo_div14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_bypass_en14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_odd_div_duty_en14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_hi_div15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_lo_div15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_bypass_en15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_odd_div_duty_en15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_hi_div16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_lo_div16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_bypass_en16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_odd_div_duty_en16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_hi_div17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_lo_div17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_bypass_en17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_odd_div_duty_en17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst17 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_div : constant is 1;
attribute mti_svvh_generic_type of pll_output_clk_frequency : constant is 1;
attribute mti_svvh_generic_type of pll_cp_current : constant is 1;
attribute mti_svvh_generic_type of pll_bwctrl : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_division : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_cout : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_out_sel : constant is 1;
attribute mti_svvh_generic_type of mimic_fbclk_type : constant is 1;
attribute mti_svvh_generic_type of pll_fbclk_mux_1 : constant is 1;
attribute mti_svvh_generic_type of pll_fbclk_mux_2 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_in_src : constant is 1;
attribute mti_svvh_generic_type of pll_vcoph_div : constant is 1;
attribute mti_svvh_generic_type of refclk1_frequency : constant is 1;
attribute mti_svvh_generic_type of pll_clkin_0_src : constant is 1;
attribute mti_svvh_generic_type of pll_clkin_1_src : constant is 1;
attribute mti_svvh_generic_type of pll_clk_loss_sw_en : constant is 1;
attribute mti_svvh_generic_type of pll_auto_clk_sw_en : constant is 1;
attribute mti_svvh_generic_type of pll_manu_clk_sw_en : constant is 1;
attribute mti_svvh_generic_type of pll_clk_sw_dly : constant is 1;
end altera_pll;
|
mit
|
3b375497bd404626848d25b9e2a55654
| 0.632833 | 3.165784 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_vecseq.vhd
| 20 | 2,951 |
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_vecseq is
generic (
SequenceLength : positive :=15;
SequenceValue : std_logic_vector := "100001110001001"
);
port (
clock : in std_logic ;
ena : in std_logic :='1';
sclr : in std_logic :='0';
aclr : in std_logic :='0';
yout : out std_logic
);
end alt_dspbuilder_vecseq;
architecture seq_SYNTH of alt_dspbuilder_vecseq is
signal clr_signal : STD_LOGIC;
signal lclr_signal : STD_LOGIC;
signal counter : std_logic_vector(ToNatural(nbitnecessary(SequenceLength)-1) downto 0);
signal yout_int : STD_LOGIC;
signal yout_comb : STD_LOGIC;
begin
u0: alt_dspbuilder_sAltrBitPropagate generic map(QTB=>DSPBuilderQTB, QTB_PRODUCT => DSPBuilderProduct, QTB_VERSION => DSPBuilderVersion)
port map (d => yout_int, r => yout);
fixed_constant:if SequenceLength=1 generate
yout_int <=SequenceValue(0);
end generate fixed_constant;
resetable_sequence:if SequenceLength>1 generate
process(clock, aclr)
begin
if aclr='1' then
yout_int <= '0';
counter <= (OTHERS => '0');
elsif clock'event and clock='1' then
if sclr='1' then
yout_int <= '0';
counter <= (OTHERS => '0');
elsif ena='1' then
if counter < int2ustd(SequenceLength-1 ,nbitnecessary(SequenceLength)+1) then
counter <= counter + '1';
else
counter <= (OTHERS => '0');
end if;
yout_int <= yout_comb;
end if;
end if;
end process;
gen:for i in 0 to SequenceLength-1 generate
yout_comb <= SequenceValue(i) when (counter=int2ustd(i,nbitnecessary(SequenceLength)+1)) else 'Z';
end generate;
end generate resetable_sequence;
end seq_SYNTH;
|
mit
|
433c1514928a4cd0976f666a47213880
| 0.649271 | 3.832468 | false | false | false | false |
Ttl/bf_cpu
|
control.vhd
| 1 | 7,949 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.bfconfig.all;
entity control is
Port ( clk, reset : in STD_LOGIC;
d_jumpf : in STD_LOGIC;
d_jumpb : in STD_LOGIC;
d_write : in STD_LOGIC;
d_read : in STD_LOGIC;
c_skip : out STD_LOGIC;
alu_z : in STD_LOGIC;
pc_out : out pctype;
uart_tx_end : in STD_LOGIC;
uart_rx_ready : in STD_LOGIC);
end control;
architecture Behavioral of control is
-- It takes two cycles to reverse the direction
type modetype is (M_RESET, M_RUN, M_JUMPF1, M_JUMPF2, M_JUMPB1, M_RXWAIT);
signal mode, mode_next : modetype := M_RESET;
signal pc : pctype := (others => '0');
signal pc_next : std_logic_vector(INST_MEM_SIZE downto 0);
signal pc_cache, pc_cache_next : pctype;
signal pc_overflow : std_logic;
signal brackets, brackets_next : unsigned(7 downto 0);
-- PC stack signals
signal stack_push_notpop : std_logic;
signal stack_enable : std_logic;
signal stack_pc : pctype;
-- Jumpf cache signals
signal cache_push, cache_valid : std_logic;
signal cache_out : pctype;
signal cache_ready, cache_ready_next : std_logic;
-- Skip one instruction when skipping instructions with jumpf cache
signal skip, skip_next : std_logic;
--pragma synthesis_off
signal mispredict, mispredict_next : unsigned(31 downto 0) := to_unsigned(0,32);
signal predict, predict_next : unsigned(31 downto 0) := to_unsigned(0,32);
signal cache_miss, cache_miss_next : unsigned(31 downto 0) := to_unsigned(0,32);
signal cache_hit, cache_hit_next : unsigned(31 downto 0) := to_unsigned(0,32);
signal cache_ready_prev : std_logic;
--pragma synthesis_on
begin
-- Stack for storing the program counter for faster return from branches
pcstack : entity work.stack
Port map( clk => clk,
reset => reset,
enable => stack_enable,
push_notpop => stack_push_notpop,
pcin => pc,
pcout => stack_pc
);
jumpf_cache: entity work.cache
Generic map(WIDTH => INST_MEM_SIZE, -- Length of address
DWIDTH => INST_MEM_SIZE, -- Length of one entry
CACHE_SIZE => JUMPF_CACHE_SIZE) -- Log2 of number of entries in the cache
Port map( clk => clk,
reset => reset,
addr => pc_cache,
din => pc,
push => cache_push,
valid => cache_valid,
dout => cache_out
);
pc_out <= pc_next(INST_MEM_SIZE-1 downto 0);
process(clk, mode_next, pc_next, pc_cache_next)
begin
if rising_edge(clk) then
if reset = '1' then
mode <= M_RESET;
else
mode <= mode_next;
end if;
-- Program ended enter infinite loop
if pc_overflow = '1' then
pc <= pc;
else
pc <= pc_next(INST_MEM_SIZE-1 downto 0);
end if;
pc_cache <= pc_cache_next;
brackets <= brackets_next;
cache_ready <= cache_ready_next;
skip <= skip_next;
--pragma synthesis_off
predict <= predict_next;
mispredict <= mispredict_next;
cache_hit <= cache_hit_next;
cache_miss <= cache_miss_next;
cache_ready_prev <= cache_ready;
--pragma synthesis_on
end if;
end process;
process(mode, pc, d_jumpf, d_jumpb, d_write, d_read,
stack_pc, alu_z, pc_cache, uart_tx_end, uart_rx_ready,
brackets, cache_valid, cache_ready, cache_out, skip)
begin
stack_push_notpop <= '0';
cache_push <= '0';
cache_ready_next <= '0';
c_skip <= '0';
brackets_next <= brackets;
pc_next <= std_logic_vector(unsigned('0'&pc)+1);
pc_overflow <= pc_next(INST_MEM_SIZE);
-- Save next PC so we can get back where we were
-- if jump was predicted incorrectly
pc_cache_next <= pc_cache;
mode_next <= M_RUN;
skip_next <= '0';
stack_enable <= '0';
case mode is
when M_RESET =>
pc_cache_next <= (others => '0');
brackets_next <= to_unsigned(0,8);
c_skip <= '1';
pc_next <= (others => '0');
mode_next <= M_RUN;
if d_write = '1' then
mode_next <= M_RUN;
elsif d_read = '1' then
mode_next <= M_RXWAIT;
elsif d_jumpf = '1' then
mode_next <= M_JUMPF2;
-- ] shouldn't never be first instruction
end if;
when M_JUMPF1 =>
if d_jumpf = '1' then
-- Two consecutive jumps, we need to push both of them to stack
stack_push_notpop <= '1';
stack_enable <= '1';
brackets_next <= brackets + 1;
end if;
if alu_z = '1' then
c_skip <= '1';
stack_push_notpop <= '0';
stack_enable <= '1';
mode_next <= M_JUMPF2;
else
-- Infinite loop, but do what we are told to do
if d_jumpb = '1' then
pc_next <= '0'&pc_cache;
end if;
mode_next <= M_RUN;
end if;
when M_JUMPF2 =>
-- Readying cache takes two clock cycles
cache_ready_next <= '1';
mode_next <= M_JUMPF2;
c_skip <= '1';
if d_jumpf = '1' then
brackets_next <= brackets + 1;
elsif d_jumpb = '1' then
brackets_next <= brackets - 1;
if brackets = 0 then
-- Store jump end address to speed up future jumps
cache_push <= '1';
mode_next <= M_RUN;
end if;
end if;
if cache_valid = '1' and cache_ready = '1' then
-- Skip the next instruction
--pragma synthesis_off
cache_hit_next <= cache_hit+1;
cache_miss_next <= cache_miss;
--pragma synthesis_on
skip_next <= '1';
mode_next <= M_RUN;
pc_next <= '0'&cache_out;
--pragma synthesis_off
elsif cache_ready = '1' and cache_ready_prev = '0' then
-- We need to check previous cache_ready value
-- to avoid double counting
cache_hit_next <= cache_hit;
cache_miss_next <= cache_miss+1;
--pragma synthesis_on
end if;
when M_JUMPB1 =>
mode_next <= M_RUN;
if alu_z = '1' then
--pragma synthesis_off
mispredict_next <= mispredict + 1;
predict_next <= predict;
--pragma synthesis_on
stack_push_notpop <= '0';
stack_enable <= '1';
c_skip <= '1';
-- Necessary
skip_next <= '1';
pc_next <= '0'&pc_cache;
else
--pragma synthesis_off
mispredict_next <= mispredict;
predict_next <= predict + 1;
--pragma synthesis_on
end if;
when M_RUN =>
brackets_next <= to_unsigned(0,8);
if d_jumpf = '1' then
-- Jump forward
pc_cache_next <= pc;
mode_next <= M_JUMPF1;
stack_push_notpop <= '1';
stack_enable <= '1';
elsif d_jumpb = '1' and skip = '0' then
pc_cache_next <= pc;
pc_next <= '0'&stack_pc;
-- We need to check alu_z on the next cycle
mode_next <= M_JUMPB1;
elsif d_write = '1' then
if uart_tx_end = '0' then
c_skip <= '1';
pc_next <= '0'&pc;
mode_next <= M_RUN;
else
mode_next <= M_RUN;
end if;
elsif d_read = '1' then
pc_next <= '0'&pc;
mode_next <= M_RXWAIT;
end if;
when M_RXWAIT =>
pc_next <= '0'&pc;
mode_next <= M_RXWAIT;
if uart_rx_ready = '1' then
pc_next <= std_logic_vector(unsigned('0'&pc)+1);
mode_next <= M_RUN;
end if;
end case;
end process;
end Behavioral;
|
lgpl-3.0
|
61ab4b1716b674ffbfdcf22e739d6a3a
| 0.523085 | 3.641319 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_sMultAltr.vhd
| 12 | 3,026 |
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
library LPM;
use LPM.LPM_COMPONENTS.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sMultAltr is
generic (
lpm_widtha : positive ;
lpm_widthb : positive ;
lpm_representation : string ;
lpm_hint : string ;
OutputMsb : natural ;
OutputLsb : natural ;
pipeline : natural
);
port (
clock : in std_logic;
ena : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
dataa : in std_logic_vector(lpm_widtha-1 downto 0);
datab : in std_logic_vector(lpm_widthb-1 downto 0);
result : out std_logic_vector(OutputMsb-OutputLsb downto 0)
);
end alt_dspbuilder_sMultAltr;
architecture synth of alt_dspbuilder_sMultAltr is
signal FullPrecisionResult : std_logic_vector(lpm_widtha+lpm_widthb-1 downto 0);
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
gcomb: if pipeline=0 generate
U0 : lpm_mult
GENERIC MAP (
lpm_widtha => lpm_widtha,
lpm_widthb => lpm_widthb,
lpm_widthp => lpm_widtha+lpm_widthb,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => lpm_representation,
lpm_hint => lpm_hint
)
PORT MAP (
dataa => dataa,
datab => datab,
result => FullPrecisionResult
);
end generate gcomb;
greg: if pipeline>0 generate
U0 : lpm_mult
GENERIC MAP (
lpm_widtha => lpm_widtha,
lpm_widthb => lpm_widthb,
lpm_widthp => lpm_widtha+lpm_widthb,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => lpm_representation,
lpm_hint => lpm_hint,
lpm_pipeline => pipeline
)
PORT MAP (
dataa => dataa,
datab => datab,
clken=> ena,
aclr => aclr_i,
clock => clock,
result => FullPrecisionResult);
end generate greg;
g:for i in OutputLsb to OutputMsb generate
result(i-OutputLsb) <= FullPrecisionResult(i);
end generate g;
end synth;
|
mit
|
cd171c05bfe089936201c3121530cbed
| 0.660939 | 3.543326 | false | false | false | false |
Raane/Term-Assigment-TFE4140-mod-anal-dig-sys
|
Project/liaison/src/controllerImproved.vhd
| 1 | 5,279 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity controller is
port(
di_ready : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
do_ready : out STD_LOGIC;
control_signals : out STD_LOGIC_VECTOR(9 downto 0);
voted_data_selector : out STD_LOGIC_VECTOR(4 downto 0)
);
end controller;
architecture controllerImproved of controller is
-- Next-signals used for clock updates
signal next_control_signals: std_logic_vector(9 downto 0);
signal next_vdsi: std_logic_vector(4 downto 0);
signal next_do_ready: std_logic;-- := '0';
signal do_ready_internal: std_logic; -- For internal use of do_ready
signal control_signals_internal : STD_LOGIC_VECTOR(9 downto 0); -- For internal use of control_signals
signal vdsi : STD_LOGIC_VECTOR(4 downto 0); -- For internal use of voted_data_selector (shortened to vdsi, i for internal)
begin
-- Setting output from internal output signals
do_ready <= do_ready_internal;
control_signals <= control_signals_internal;
voted_data_selector <= vdsi;
clock_tick : process(clk)
begin
if (rising_edge(clk)) then
if (reset = '1') then
control_signals_internal <= "0000000000";
vdsi <= "00000";
do_ready_internal <= '0';
else
-- Updating the controller's output values
-- based on current selected next-values
control_signals_internal <= next_control_signals;
vdsi <= next_vdsi;
do_ready_internal <= next_do_ready;
end if;
end if;
end process;
-- Selects register for input, and also activates do_ready after 8 cycles
handle_input : process(di_ready, control_signals_internal)
begin
case control_signals_internal is
when "0000000000" =>
if (di_ready = '1') then -- di_ready works only when system is idle, with value "0000000000"
next_control_signals <= "0010000000"; -- store as bit 7
else
next_control_signals <= "0000000000"; -- Stay idle, di_ready has not yet hit in
end if;
when "0010000000" =>
next_control_signals <= "0001000000"; -- store as bit 6
when "0001000000" =>
next_control_signals <= "0000100000"; -- store as bit 5
when "0000100000" =>
next_control_signals <= "0000010000"; -- store as bit 4
when "0000010000" =>
next_control_signals <= "0000001000"; -- store as bit 3
when "0000001000" =>
next_control_signals <= "0000000100"; -- store as bit 2
when "0000000100" =>
next_control_signals <= "0000000010"; -- store as bit 1
when "0000000010" =>
next_do_ready <= '1'; -- Setting do_ready 8 cycles after di_ready has initiated storing
next_vdsi <= "00111"; -- Set output from liasion to voted data bit 7 at the same time
next_control_signals <= "0000000001"; -- store as bit 0
when "0000000001" =>
next_control_signals <= "0100000000"; -- store status
when "0100000000" =>
next_control_signals <= "1000000000"; -- update ECC-registers
when others => -- Done running through register storing. Do nothing until di_ready has been set again.
next_control_signals <= "0000000000";
end case;
end process;
-- Setting next_do_ready to 0. Usually happens after do_ready has been set to '1', so that it will be set to '0' in next cycle.
-- shut_off_do_ready : process(do_ready_internal)
-- begin
-- next_do_ready <= '0';
-- end process;
handle_output : process (vdsi)
begin
case vdsi is
-- next_vdsi should already be "00111" at this point
--when "00111" =>
-- next_vdsi <= "00111"; -- set output from liaison to voted data bit 7, should be set already at beginning of counting
when "00111" =>
next_vdsi <= "00110"; -- set output from liaison to voted data bit 6
when "00110" =>
next_vdsi <= "00101"; -- set output from liaison to voted data bit 5
when "00101" =>
next_vdsi <= "00100"; -- set output from liaison to voted data bit 4
when "00100" =>
next_vdsi <= "00011"; -- set output from liaison to voted data bit 3
when "00011" =>
next_vdsi <= "00010"; -- set output from liaison to voted data bit 2
when "00010" =>
next_vdsi <= "00001"; -- set output from liaison to voted data bit 1
when "00001" =>
next_vdsi <= "00000"; -- set output from liaison to voted data bit 0
when "00000" =>
next_vdsi <= "01010"; -- set output from liaison to status bit 2
when "01010" =>
next_vdsi <= "01001"; -- set output from liaison to status bit 1
when "01001" =>
next_vdsi <= "01000"; -- set output from liaison to status bit 0
when "01000" =>
next_vdsi <= "10010"; -- set output from liaison to ECC bit 3
when "10010" =>
next_vdsi <= "10001"; -- set output from liaison to ECC bit 2
when "10001" =>
next_vdsi <= "10000"; -- set output from liaison to ECC bit 1
when "10000" =>
next_vdsi <= "01111"; -- set output from liaison to ECC bit 0
when others =>
-- Do nothing. The moment this usually happens is when vdsi has been set to "01111",
-- and next_vdsi (as well as do_ready) should be set at the same time in the handle_input_process
end case;
-- Sets do_ready to 0. Usually occurs cycle after it was set to '1'
--if (do_ready_internal = '1') then
next_do_ready <= '0';
--end if;
end process;
end controllerImproved;
|
apache-2.0
|
f20dc806264822dcfa5db8708090f71d
| 0.65126 | 3.493713 | false | false | false | false |
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_if_statement_GNZR777PB6.vhd
| 4 | 1,487 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNZR777PB6 is
generic ( use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 0;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "((a>b) or (a=b)) and (a<c)";
number_inputs : integer := 3;
width : natural := 24);
port(
true : out std_logic;
a : in std_logic_vector(23 downto 0);
b : in std_logic_vector(23 downto 0);
c : in std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_if_statement_GNZR777PB6 is
signal result : std_logic;
constant zero : STD_LOGIC_VECTOR(23 DOWNTO 0) := (others=>'0');
constant one : STD_LOGIC_VECTOR(23 DOWNTO 0) := (0 => '1', others => '0');
function myFunc ( Value: boolean )
return std_logic is
variable func_result : std_logic;
begin
if (Value) then
func_result := '1';
else
func_result := '0';
end if;
return func_result;
end;
function myFunc ( Value: std_logic )
return std_logic is
begin
return Value;
end;
Begin
-- DSP Builder Block - Simulink Block "IfStatement"
result <= myFunc(((a>b) or (a=b)) and (a<c)) ;
true <= result;
end architecture;
|
mit
|
effc8520beacd8e33aec948816a7cdbb
| 0.616005 | 3.184154 | false | false | false | false |
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