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peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1949.vhd
| 4 | 16,598 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1949.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c07s02b01x00p01n02i01949pkg is
--
-- Index types for array declarations
--
SUBTYPE st_ind1 IS INTEGER RANGE 1 TO 4; -- index from 1 (POSITIVE)
SUBTYPE st_ind2 IS INTEGER RANGE 0 TO 3; -- index from 0 (NATURAL)
SUBTYPE st_ind3 IS CHARACTER RANGE 'a' TO 'd'; -- non-INTEGER index
SUBTYPE st_ind4 IS INTEGER RANGE 0 DOWNTO -3; -- descending range
--
-- Logic types for subelements
--
SUBTYPE st_scl1 IS BIT;
SUBTYPE st_scl2 IS BOOLEAN;
-- -----------------------------------------------------------------------------------------
-- Composite type declarations
-- -----------------------------------------------------------------------------------------
--
-- Unconstrained arrays
--
TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF BIT;
TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF BOOLEAN;
TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF BIT;
TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF BOOLEAN;
--
-- Constrained arrays of scalars (make compatable with unconstrained types
--
SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1);
SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2);
SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3);
SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4);
-- -----------------------------------------------------------------------------------------
--
-- TYPE declarations for resolution function (Constrained types only)
--
TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
end;
use work.c07s02b01x00p01n02i01949pkg.all;
ENTITY c07s02b01x00p01n02i01949ent IS
END c07s02b01x00p01n02i01949ent;
ARCHITECTURE c07s02b01x00p01n02i01949arch OF c07s02b01x00p01n02i01949ent IS
--
-- CONSTANT Declarations
--
CONSTANT ARGA_C_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
CONSTANT ARGA_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
CONSTANT ARGB_C_csa1_1 : t_csa1_1 := ( '1', '0', '1', '0' );
CONSTANT ARGB_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
CONSTANT XOR_C_csa1_1 : t_csa1_1 := ( '0', '1', '1', '0' );
CONSTANT XOR_C_usa1_1 : t_usa1_1(st_ind1) := ( '0', '1', '1', '0' );
CONSTANT ARGA_C_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGA_C_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGB_C_csa1_2 : t_csa1_2 := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT ARGB_C_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT XOR_C_csa1_2 : t_csa1_2 := ( FALSE, TRUE, TRUE, FALSE );
CONSTANT XOR_C_usa1_2 : t_usa1_2(st_ind2) := ( FALSE, TRUE, TRUE, FALSE );
CONSTANT ARGA_C_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
CONSTANT ARGA_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
CONSTANT ARGB_C_csa1_3 : t_csa1_3 := ( '1', '0', '1', '0' );
CONSTANT ARGB_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
CONSTANT XOR_C_csa1_3 : t_csa1_3 := ( '0', '1', '1', '0' );
CONSTANT XOR_C_usa1_3 : t_usa1_3(st_ind3) := ( '0', '1', '1', '0' );
CONSTANT ARGA_C_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGA_C_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGB_C_csa1_4 : t_csa1_4 := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT ARGB_C_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, TRUE, FALSE );
CONSTANT XOR_C_csa1_4 : t_csa1_4 := ( FALSE, TRUE, TRUE, FALSE );
CONSTANT XOR_C_usa1_4 : t_usa1_4(st_ind4) := ( FALSE, TRUE, TRUE, FALSE );
--
-- SIGNAL Declarations
--
SIGNAL ARGA_S_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
SIGNAL ARGA_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
SIGNAL ARGB_S_csa1_1 : t_csa1_1 := ( '1', '0', '1', '0' );
SIGNAL ARGB_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
SIGNAL XOR_S_csa1_1 : t_csa1_1 := ( '0', '1', '1', '0' );
SIGNAL XOR_S_usa1_1 : t_usa1_1(st_ind1) := ( '0', '1', '1', '0' );
SIGNAL ARGA_S_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGA_S_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGB_S_csa1_2 : t_csa1_2 := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL ARGB_S_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL XOR_S_csa1_2 : t_csa1_2 := ( FALSE, TRUE, TRUE, FALSE );
SIGNAL XOR_S_usa1_2 : t_usa1_2(st_ind2) := ( FALSE, TRUE, TRUE, FALSE );
SIGNAL ARGA_S_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
SIGNAL ARGA_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
SIGNAL ARGB_S_csa1_3 : t_csa1_3 := ( '1', '0', '1', '0' );
SIGNAL ARGB_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
SIGNAL XOR_S_csa1_3 : t_csa1_3 := ( '0', '1', '1', '0' );
SIGNAL XOR_S_usa1_3 : t_usa1_3(st_ind3) := ( '0', '1', '1', '0' );
SIGNAL ARGA_S_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGA_S_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGB_S_csa1_4 : t_csa1_4 := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL ARGB_S_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, TRUE, FALSE );
SIGNAL XOR_S_csa1_4 : t_csa1_4 := ( FALSE, TRUE, TRUE, FALSE );
SIGNAL XOR_S_usa1_4 : t_usa1_4(st_ind4) := ( FALSE, TRUE, TRUE, FALSE );
BEGIN
TESTING: PROCESS
--
-- VARIABLE Declarations
--
VARIABLE ARGA_V_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
VARIABLE ARGA_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
VARIABLE ARGB_V_csa1_1 : t_csa1_1 := ( '1', '0', '1', '0' );
VARIABLE ARGB_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
VARIABLE XOR_V_csa1_1 : t_csa1_1 := ( '0', '1', '1', '0' );
VARIABLE XOR_V_usa1_1 : t_usa1_1(st_ind1) := ( '0', '1', '1', '0' );
VARIABLE ARGA_V_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGA_V_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGB_V_csa1_2 : t_csa1_2 := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE ARGB_V_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE XOR_V_csa1_2 : t_csa1_2 := ( FALSE, TRUE, TRUE, FALSE );
VARIABLE XOR_V_usa1_2 : t_usa1_2(st_ind2) := ( FALSE, TRUE, TRUE, FALSE );
VARIABLE ARGA_V_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
VARIABLE ARGA_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
VARIABLE ARGB_V_csa1_3 : t_csa1_3 := ( '1', '0', '1', '0' );
VARIABLE ARGB_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
VARIABLE XOR_V_csa1_3 : t_csa1_3 := ( '0', '1', '1', '0' );
VARIABLE XOR_V_usa1_3 : t_usa1_3(st_ind3) := ( '0', '1', '1', '0' );
VARIABLE ARGA_V_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGA_V_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGB_V_csa1_4 : t_csa1_4 := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE ARGB_V_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, FALSE, TRUE, FALSE );
VARIABLE XOR_V_csa1_4 : t_csa1_4 := ( FALSE, TRUE, TRUE, FALSE );
VARIABLE XOR_V_usa1_4 : t_usa1_4(st_ind4) := ( FALSE, TRUE, TRUE, FALSE );
BEGIN
--
-- Test XOR operator on: CONSTANTs
--
ASSERT ( ARGA_C_csa1_1 XOR ARGB_C_csa1_1 ) = XOR_C_csa1_1
REPORT "ERROR: composite XOR operator failed; CONSTANT; csa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_C_csa1_2 XOR ARGB_C_csa1_2 ) = XOR_C_csa1_2
REPORT "ERROR: composite XOR operator failed; CONSTANT; csa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_C_csa1_3 XOR ARGB_C_csa1_3 ) = XOR_C_csa1_3
REPORT "ERROR: composite XOR operator failed; CONSTANT; csa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_C_csa1_4 XOR ARGB_C_csa1_4 ) = XOR_C_csa1_4
REPORT "ERROR: composite XOR operator failed; CONSTANT; csa1_4"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_1 XOR ARGB_C_usa1_1 ) = XOR_C_usa1_1
REPORT "ERROR: composite XOR operator failed; CONSTANT; usa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_2 XOR ARGB_C_usa1_2 ) = XOR_C_usa1_2
REPORT "ERROR: composite XOR operator failed; CONSTANT; usa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_3 XOR ARGB_C_usa1_3 ) = XOR_C_usa1_3
REPORT "ERROR: composite XOR operator failed; CONSTANT; usa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_C_usa1_4 XOR ARGB_C_usa1_4 ) = XOR_C_usa1_4
REPORT "ERROR: composite XOR operator failed; CONSTANT; usa1_4"
SEVERITY FAILURE;
--
-- Test XOR operator on: SIGNALs
--
ASSERT ( ARGA_S_csa1_1 XOR ARGB_S_csa1_1 ) = XOR_S_csa1_1
REPORT "ERROR: composite XOR operator failed; SIGNAL; csa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_S_csa1_2 XOR ARGB_S_csa1_2 ) = XOR_S_csa1_2
REPORT "ERROR: composite XOR operator failed; SIGNAL; csa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_S_csa1_3 XOR ARGB_S_csa1_3 ) = XOR_S_csa1_3
REPORT "ERROR: composite XOR operator failed; SIGNAL; csa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_S_csa1_4 XOR ARGB_S_csa1_4 ) = XOR_S_csa1_4
REPORT "ERROR: composite XOR operator failed; SIGNAL; csa1_4"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_1 XOR ARGB_S_usa1_1 ) = XOR_S_usa1_1
REPORT "ERROR: composite XOR operator failed; SIGNAL; usa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_2 XOR ARGB_S_usa1_2 ) = XOR_S_usa1_2
REPORT "ERROR: composite XOR operator failed; SIGNAL; usa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_3 XOR ARGB_S_usa1_3 ) = XOR_S_usa1_3
REPORT "ERROR: composite XOR operator failed; SIGNAL; usa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_S_usa1_4 XOR ARGB_S_usa1_4 ) = XOR_S_usa1_4
REPORT "ERROR: composite XOR operator failed; SIGNAL; usa1_4"
SEVERITY FAILURE;
--
-- Test XOR operator on: VARIABLEs
--
ASSERT ( ARGA_V_csa1_1 XOR ARGB_V_csa1_1 ) = XOR_V_csa1_1
REPORT "ERROR: composite XOR operator failed; VARIABLE; csa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_V_csa1_2 XOR ARGB_V_csa1_2 ) = XOR_V_csa1_2
REPORT "ERROR: composite XOR operator failed; VARIABLE; csa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_V_csa1_3 XOR ARGB_V_csa1_3 ) = XOR_V_csa1_3
REPORT "ERROR: composite XOR operator failed; VARIABLE; csa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_V_csa1_4 XOR ARGB_V_csa1_4 ) = XOR_V_csa1_4
REPORT "ERROR: composite XOR operator failed; VARIABLE; csa1_4"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_1 XOR ARGB_V_usa1_1 ) = XOR_V_usa1_1
REPORT "ERROR: composite XOR operator failed; VARIABLE; usa1_1"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_2 XOR ARGB_V_usa1_2 ) = XOR_V_usa1_2
REPORT "ERROR: composite XOR operator failed; VARIABLE; usa1_2"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_3 XOR ARGB_V_usa1_3 ) = XOR_V_usa1_3
REPORT "ERROR: composite XOR operator failed; VARIABLE; usa1_3"
SEVERITY FAILURE;
ASSERT ( ARGA_V_usa1_4 XOR ARGB_V_usa1_4 ) = XOR_V_usa1_4
REPORT "ERROR: composite XOR operator failed; VARIABLE; usa1_4"
SEVERITY FAILURE;
wait for 5 ns;
assert NOT( ( ARGA_C_csa1_1 XOR ARGB_C_csa1_1 ) = XOR_C_csa1_1 and
( ARGA_C_csa1_2 XOR ARGB_C_csa1_2 ) = XOR_C_csa1_2 and
( ARGA_C_csa1_3 XOR ARGB_C_csa1_3 ) = XOR_C_csa1_3 and
( ARGA_C_csa1_4 XOR ARGB_C_csa1_4 ) = XOR_C_csa1_4 and
( ARGA_C_usa1_1 XOR ARGB_C_usa1_1 ) = XOR_C_usa1_1 and
( ARGA_C_usa1_2 XOR ARGB_C_usa1_2 ) = XOR_C_usa1_2 and
( ARGA_C_usa1_3 XOR ARGB_C_usa1_3 ) = XOR_C_usa1_3 and
( ARGA_C_usa1_4 XOR ARGB_C_usa1_4 ) = XOR_C_usa1_4 and
( ARGA_S_csa1_1 XOR ARGB_S_csa1_1 ) = XOR_S_csa1_1 and
( ARGA_S_csa1_2 XOR ARGB_S_csa1_2 ) = XOR_S_csa1_2 and
( ARGA_S_csa1_3 XOR ARGB_S_csa1_3 ) = XOR_S_csa1_3 and
( ARGA_S_csa1_4 XOR ARGB_S_csa1_4 ) = XOR_S_csa1_4 and
( ARGA_S_usa1_1 XOR ARGB_S_usa1_1 ) = XOR_S_usa1_1 and
( ARGA_S_usa1_2 XOR ARGB_S_usa1_2 ) = XOR_S_usa1_2 and
( ARGA_S_usa1_3 XOR ARGB_S_usa1_3 ) = XOR_S_usa1_3 and
( ARGA_S_usa1_4 XOR ARGB_S_usa1_4 ) = XOR_S_usa1_4 and
( ARGA_V_csa1_1 XOR ARGB_V_csa1_1 ) = XOR_V_csa1_1 and
( ARGA_V_csa1_2 XOR ARGB_V_csa1_2 ) = XOR_V_csa1_2 and
( ARGA_V_csa1_3 XOR ARGB_V_csa1_3 ) = XOR_V_csa1_3 and
( ARGA_V_csa1_4 XOR ARGB_V_csa1_4 ) = XOR_V_csa1_4 and
( ARGA_V_usa1_1 XOR ARGB_V_usa1_1 ) = XOR_V_usa1_1 and
( ARGA_V_usa1_2 XOR ARGB_V_usa1_2 ) = XOR_V_usa1_2 and
( ARGA_V_usa1_3 XOR ARGB_V_usa1_3 ) = XOR_V_usa1_3 and
( ARGA_V_usa1_4 XOR ARGB_V_usa1_4 ) = XOR_V_usa1_4 )
report "***PASSED TEST: c07s02b01x00p01n02i01949"
severity NOTE;
assert ( ( ARGA_C_csa1_1 XOR ARGB_C_csa1_1 ) = XOR_C_csa1_1 and
( ARGA_C_csa1_2 XOR ARGB_C_csa1_2 ) = XOR_C_csa1_2 and
( ARGA_C_csa1_3 XOR ARGB_C_csa1_3 ) = XOR_C_csa1_3 and
( ARGA_C_csa1_4 XOR ARGB_C_csa1_4 ) = XOR_C_csa1_4 and
( ARGA_C_usa1_1 XOR ARGB_C_usa1_1 ) = XOR_C_usa1_1 and
( ARGA_C_usa1_2 XOR ARGB_C_usa1_2 ) = XOR_C_usa1_2 and
( ARGA_C_usa1_3 XOR ARGB_C_usa1_3 ) = XOR_C_usa1_3 and
( ARGA_C_usa1_4 XOR ARGB_C_usa1_4 ) = XOR_C_usa1_4 and
( ARGA_S_csa1_1 XOR ARGB_S_csa1_1 ) = XOR_S_csa1_1 and
( ARGA_S_csa1_2 XOR ARGB_S_csa1_2 ) = XOR_S_csa1_2 and
( ARGA_S_csa1_3 XOR ARGB_S_csa1_3 ) = XOR_S_csa1_3 and
( ARGA_S_csa1_4 XOR ARGB_S_csa1_4 ) = XOR_S_csa1_4 and
( ARGA_S_usa1_1 XOR ARGB_S_usa1_1 ) = XOR_S_usa1_1 and
( ARGA_S_usa1_2 XOR ARGB_S_usa1_2 ) = XOR_S_usa1_2 and
( ARGA_S_usa1_3 XOR ARGB_S_usa1_3 ) = XOR_S_usa1_3 and
( ARGA_S_usa1_4 XOR ARGB_S_usa1_4 ) = XOR_S_usa1_4 and
( ARGA_V_csa1_1 XOR ARGB_V_csa1_1 ) = XOR_V_csa1_1 and
( ARGA_V_csa1_2 XOR ARGB_V_csa1_2 ) = XOR_V_csa1_2 and
( ARGA_V_csa1_3 XOR ARGB_V_csa1_3 ) = XOR_V_csa1_3 and
( ARGA_V_csa1_4 XOR ARGB_V_csa1_4 ) = XOR_V_csa1_4 and
( ARGA_V_usa1_1 XOR ARGB_V_usa1_1 ) = XOR_V_usa1_1 and
( ARGA_V_usa1_2 XOR ARGB_V_usa1_2 ) = XOR_V_usa1_2 and
( ARGA_V_usa1_3 XOR ARGB_V_usa1_3 ) = XOR_V_usa1_3 and
( ARGA_V_usa1_4 XOR ARGB_V_usa1_4 ) = XOR_V_usa1_4 )
report "***FAILED TEST: c07s02b01x00p01n02i01949 - Logical operator XOR for any user-defined one-dimensional array type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n02i01949arch;
|
gpl-2.0
|
8f53f1d6e647e4d976fcdeaf0b28db25
| 0.543921 | 2.614682 | false | false | false | false |
stnolting/neo430
|
rtl/core/neo430_package.vhd
| 1 | 54,859 |
-- #################################################################################################
-- # << NEO430 - Processor Package >> #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package neo430_package is
-- Processor Hardware Version -------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant hw_version_c : std_ulogic_vector(15 downto 0) := x"0408"; -- no touchy!
-- Danger Zone (Advanced Hardware Configuration) ------------------------------------------
-- -------------------------------------------------------------------------------------------
constant use_dsp_mul_c : boolean := false; -- use DSP blocks for MULDIV's multiplication core (default=false)
constant use_xalu_c : boolean := false; -- implement extended ALU function (default=false)
constant low_power_mode_c : boolean := false; -- can reduce switching activity, but will also decrease f_max and might increase area (default=false)
-- Internal Functions ---------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
function index_size_f(input : natural) return natural;
function is_power_of_two_f(num : natural; bit_width : natural) return boolean;
function bit_reversal_f(input : std_ulogic_vector) return std_ulogic_vector;
function set_bits_f(input : std_ulogic_vector) return natural;
function leading_zeros_f(input : std_ulogic_vector) return natural;
function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural;
function cond_sel_stdulogicvector_f(cond : boolean; val_t : std_ulogic_vector; val_f : std_ulogic_vector) return std_ulogic_vector;
function bool_to_ulogic_f(cond : boolean) return std_ulogic;
function bin_to_gray_f(input : std_ulogic_vector) return std_ulogic_vector;
function gray_to_bin_f(input : std_ulogic_vector) return std_ulogic_vector;
function int_to_hexchar_f(input : integer) return character;
function or_all_f(a : std_ulogic_vector) return std_ulogic;
function and_all_f(a : std_ulogic_vector) return std_ulogic;
function xor_all_f(a : std_ulogic_vector) return std_ulogic;
-- Address Space Layout (make sure this is always sync with neo430.h) ---------------------
-- -------------------------------------------------------------------------------------------
-- Main Memory: IMEM(ROM/RAM) --
constant imem_base_c : std_ulogic_vector(15 downto 0) := x"0000"; -- base address, fixed!
constant imem_max_size_c : natural := 48*1024; -- bytes, fixed!
-- Main Memory: DMEM(RAM) --
constant dmem_base_c : std_ulogic_vector(15 downto 0) := x"C000"; -- base address, fixed!
constant dmem_max_size_c : natural := 12*1024; -- bytes, fixed!
-- Boot ROM --
constant boot_base_c : std_ulogic_vector(15 downto 0) := x"F000"; -- bootloader base address, fixed!
constant boot_size_c : natural := 2*1024; -- bytes, max 2048 bytes!
constant boot_max_size_c : natural := 2*1024; -- bytes, fixed!
-- IO: Peripheral Devices ("IO") Area --
-- Each device must use 2 bytes or a multiple of 2 bytes as address space!
-- CONTROL register(s) (including the device enable) must be located at the base address of the device!
constant io_base_c : std_ulogic_vector(15 downto 0) := x"FF80";
constant io_size_c : natural := 128; -- bytes, fixed!
-- IO: Multiplier/Divider Unit (MULDIV) --
constant muldiv_base_c : std_ulogic_vector(15 downto 0) := x"FF80";
constant muldiv_size_c : natural := 8; -- bytes
constant muldiv_opa_resx_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(muldiv_base_c) + x"0000");
constant muldiv_opb_umul_resy_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(muldiv_base_c) + x"0002");
constant muldiv_opb_smul_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(muldiv_base_c) + x"0004");
constant muldiv_opb_udiv_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(muldiv_base_c) + x"0006");
-- IO: Frequency Generator (FREQ_GEN) --
constant freq_gen_base_c : std_ulogic_vector(15 downto 0) := x"FF88";
constant freq_gen_size_c : natural := 8; -- bytes
constant freq_gen_ctrl_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(freq_gen_base_c) + x"0000");
constant freq_gen_tw_ch0_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(freq_gen_base_c) + x"0002");
constant freq_gen_tw_ch1_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(freq_gen_base_c) + x"0004");
constant freq_gen_tw_ch2_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(freq_gen_base_c) + x"0006");
-- IO: Wishbone32 Interface (WB32) --
constant wb32_base_c : std_ulogic_vector(15 downto 0) := x"FF90";
constant wb32_size_c : natural := 16; -- bytes
constant wb32_ctrl_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(wb32_base_c) + x"0000");
constant wb32_rd_adr_lo_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(wb32_base_c) + x"0002");
constant wb32_rd_adr_hi_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(wb32_base_c) + x"0004");
constant wb32_wr_adr_lo_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(wb32_base_c) + x"0006");
constant wb32_wr_adr_hi_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(wb32_base_c) + x"0008");
constant wb32_data_lo_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(wb32_base_c) + x"000A");
constant wb32_data_hi_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(wb32_base_c) + x"000C");
--constant wb32_???_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(wb32_base_c) + x"000E");
-- IO: Universal asynchronous receiver and transmitter (UART) --
constant uart_base_c : std_ulogic_vector(15 downto 0) := x"FFA0";
constant uart_size_c : natural := 4; -- bytes
constant uart_ctrl_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(uart_base_c) + x"0000");
constant uart_rtx_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(uart_base_c) + x"0002");
-- IO: Serial Peripheral Interface (SPI) --
constant spi_base_c : std_ulogic_vector(15 downto 0) := x"FFA4";
constant spi_size_c : natural := 4; -- bytes
constant spi_ctrl_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(spi_base_c) + x"0000");
constant spi_rtx_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(spi_base_c) + x"0002");
-- IO: General purpose input/output port (GPIO) --
constant gpio_base_c : std_ulogic_vector(15 downto 0) := x"FFA8";
constant gpio_size_c : natural := 8; -- bytes
constant gpio_irqmask_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(gpio_base_c) + x"0000");
constant gpio_in_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(gpio_base_c) + x"0002");
constant gpio_out_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(gpio_base_c) + x"0004");
--constant gpio_???_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(gpio_base_c) + x"0006");
-- IO: High-Precision Timer (TIMER) --
constant timer_base_c : std_ulogic_vector(15 downto 0) := x"FFB0";
constant timer_size_c : natural := 8; -- bytes
constant timer_ctrl_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(timer_base_c) + x"0000");
constant timer_cnt_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(timer_base_c) + x"0002");
constant timer_thres_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(timer_base_c) + x"0004");
--constant timer_???_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(timer_base_c) + x"0006");
-- IO: Watchdog Timer (WDT) --
constant wdt_base_c : std_ulogic_vector(15 downto 0) := x"FFB8";
constant wdt_size_c : natural := 2; -- bytes
constant wdt_ctrl_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(wdt_base_c) + x"0000");
-- IO: Cyclic Redundancy Check (CRC) --
constant crc_base_c : std_ulogic_vector(15 downto 0) := x"FFC0";
constant crc_size_c : natural := 16; -- bytes
constant crc_poly_lo_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(crc_base_c) + x"0000");
constant crc_poly_hi_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(crc_base_c) + x"0002");
constant crc_crc16_in_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(crc_base_c) + x"0004");
constant crc_crc32_in_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(crc_base_c) + x"0006");
--constant crc_???_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(crc_base_c) + x"0008");
--constant crc_???_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(crc_base_c) + x"000A");
constant crc_resx_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(crc_base_c) + x"000C");
constant crc_resy_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(crc_base_c) + x"000E");
-- IO: Custom Functions Unit (CFU) --
constant cfu_base_c : std_ulogic_vector(15 downto 0) := x"FFD0";
constant cfu_size_c : natural := 16; -- bytes
constant cfu_reg0_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(cfu_base_c) + x"0000");
constant cfu_reg1_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(cfu_base_c) + x"0002");
constant cfu_reg2_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(cfu_base_c) + x"0004");
constant cfu_reg3_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(cfu_base_c) + x"0006");
constant cfu_reg4_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(cfu_base_c) + x"0008");
constant cfu_reg5_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(cfu_base_c) + x"000A");
constant cfu_reg6_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(cfu_base_c) + x"000C");
constant cfu_reg7_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(cfu_base_c) + x"000E");
-- IO: Pulse-Width Modulation Controller (PWM) --
constant pwm_base_c : std_ulogic_vector(15 downto 0) := x"FFE0";
constant pwm_size_c : natural := 8; -- bytes
constant pwm_ctrl_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(pwm_base_c) + x"0000");
constant pwm_ch10_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(pwm_base_c) + x"0002");
constant pwm_ch32_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(pwm_base_c) + x"0004");
--constant pwm_???_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(pwm_base_c) + x"0006");
-- IO: Two Wire Serial Interface (TWI) --
constant twi_base_c : std_ulogic_vector(15 downto 0) := x"FFE8";
constant twi_size_c : natural := 4; -- bytes
constant twi_ctrl_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(twi_base_c) + x"0000");
constant twi_rtx_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(twi_base_c) + x"0002");
-- IO: True Random Number Generator (TRNG) --
constant trng_base_c : std_ulogic_vector(15 downto 0) := x"FFEC";
constant trng_size_c : natural := 2; -- bytes
constant trng_ctrl_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(trng_base_c) + x"0000");
-- IO: External Interrupts Controller (EXIRQ) --
constant exirq_base_c : std_ulogic_vector(15 downto 0) := x"FFEE";
constant exirq_size_c : natural := 2; -- bytes
constant exirq_ctrl_addr_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(unsigned(exirq_base_c) + x"0000");
-- IO: System Configuration (SYSCONFIG) --
constant sysconfig_base_c : std_ulogic_vector(15 downto 0) := x"FFF0";
constant sysconfig_size_c : natural := 16; -- bytes
-- Clock Generator -------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant clk_div2_c : natural := 0;
constant clk_div4_c : natural := 1;
constant clk_div8_c : natural := 2;
constant clk_div64_c : natural := 3;
constant clk_div128_c : natural := 4;
constant clk_div1024_c : natural := 5;
constant clk_div2048_c : natural := 6;
constant clk_div4096_c : natural := 7;
-- Register Addresses ---------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant reg_pc_c : std_ulogic_vector(3 downto 0) := x"0"; -- program counter
constant reg_sp_c : std_ulogic_vector(3 downto 0) := x"1"; -- stack pointer
constant reg_sr_c : std_ulogic_vector(3 downto 0) := x"2"; -- status register
constant reg_cg_c : std_ulogic_vector(3 downto 0) := x"3"; -- constant generator
-- Status Register ------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant sreg_c_c : natural := 0; -- r/w: carry flag
constant sreg_z_c : natural := 1; -- r/w: zero flag
constant sreg_n_c : natural := 2; -- r/w: negative flag
constant sreg_i_c : natural := 3; -- r/w: global interrupt enable
constant sreg_s_c : natural := 4; -- r/w: CPU sleep flag
constant sreg_p_c : natural := 5; -- r/w: parity flag
constant sreg_v_c : natural := 8; -- r/w: overflow flag
constant sreg_q_c : natural := 14; -- -/w: clear pending IRQ buffer when set
constant sreg_r_c : natural := 15; -- r/w: enable write access to IMEM (ROM) when set
-- ALU Flag Bus ---------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant flag_c_c : natural := 0; -- carry flag
constant flag_z_c : natural := 1; -- zero flag
constant flag_n_c : natural := 2; -- negative flag
constant flag_v_c : natural := 3; -- overflow flag
constant flag_p_c : natural := 4; -- parity flag
-- Main Control Bus -----------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- register file --
constant ctrl_rf_in_sel_c : natural := 0; -- input source
constant ctrl_rf_adr0_c : natural := 1; -- source/destination register address bit 0
constant ctrl_rf_adr1_c : natural := 2; -- source/destination register address bit 1
constant ctrl_rf_adr2_c : natural := 3; -- source/destination register address bit 2
constant ctrl_rf_adr3_c : natural := 4; -- source/destination register address bit 3
constant ctrl_rf_as0_c : natural := 5; -- source addressing mode bit 0
constant ctrl_rf_as1_c : natural := 6; -- source addressing mode bit 1
constant ctrl_rf_fup_c : natural := 7; -- update ALU flags
constant ctrl_rf_wb_en_c : natural := 8; -- enable RF write back
constant ctrl_rf_dsleep_c : natural := 9; -- disable sleep mode
constant ctrl_rf_dgie_c : natural := 10; -- disable global interrupt enable
constant ctrl_rf_boot_c : natural := 11; -- inject PC boot address
-- alu --
constant ctrl_alu_in_sel_c : natural := 12; -- ALU OP input select
constant ctrl_alu_opa_wr_c : natural := 13; -- write ALU operand A
constant ctrl_alu_opb_wr_c : natural := 14; -- write ALU operand B
constant ctrl_alu_cmd0_c : natural := 15; -- ALU command bit 0
constant ctrl_alu_cmd1_c : natural := 16; -- ALU command bit 1
constant ctrl_alu_cmd2_c : natural := 17; -- ALU command bit 2
constant ctrl_alu_cmd3_c : natural := 18; -- ALU command bit 3
constant ctrl_alu_bw_c : natural := 19; -- byte(1)/word(0) operation
-- address generator --
constant ctrl_adr_off0_c : natural := 20; -- address offset selection bit 0
constant ctrl_adr_off1_c : natural := 21; -- address offset selection bit 1
constant ctrl_adr_off2_c : natural := 22; -- address offset selection bit 2
constant ctrl_adr_mar_sel_c : natural := 23; -- select input for MAR
constant ctrl_adr_bp_en_c : natural := 24; -- mem addr output select, 0:MAR, 1:bypass
constant ctrl_adr_ivec_oe_c : natural := 25; -- output IRQ if 1, else output PC
constant ctrl_adr_mar_wr_c : natural := 26; -- write MAR
-- memory interface --
constant ctrl_mem_wr_c : natural := 27; -- write to memory
constant ctrl_mem_rd_c : natural := 28; -- read from memory
-- bus size --
constant ctrl_width_c : natural := 29; -- control bus size
-- Condition Codes ------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant cond_ne_c : std_ulogic_vector(2 downto 0) := "000"; -- not equal
constant cond_eq_c : std_ulogic_vector(2 downto 0) := "001"; -- equal
constant cond_lo_c : std_ulogic_vector(2 downto 0) := "010"; -- lower
constant cond_hs_c : std_ulogic_vector(2 downto 0) := "011"; -- higher or same
constant cond_mi_c : std_ulogic_vector(2 downto 0) := "100"; -- negative
constant cond_ge_c : std_ulogic_vector(2 downto 0) := "101"; -- greater or equal
constant cond_le_c : std_ulogic_vector(2 downto 0) := "110"; -- less
constant cond_al_c : std_ulogic_vector(2 downto 0) := "111"; -- always
-- ALU Function Codes ---------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant alu_rrc_c : std_ulogic_vector(3 downto 0) := "0000"; -- r <= a >>> 1, rotate right through carry
constant alu_swap_c : std_ulogic_vector(3 downto 0) := "0001"; -- r <= swap bytes of a
constant alu_rra_c : std_ulogic_vector(3 downto 0) := "0010"; -- r <= a >>> 1, rotate right arithmetically
constant alu_sxt_c : std_ulogic_vector(3 downto 0) := "0011"; -- r <= a, sign extend byte
constant alu_mov_c : std_ulogic_vector(3 downto 0) := "0100"; -- r <= a
constant alu_add_c : std_ulogic_vector(3 downto 0) := "0101"; -- r <= a + b
constant alu_addc_c : std_ulogic_vector(3 downto 0) := "0110"; -- r <= a + b + carry
constant alu_subc_c : std_ulogic_vector(3 downto 0) := "0111"; -- r <= b - a - 1 + carry
constant alu_sub_c : std_ulogic_vector(3 downto 0) := "1000"; -- r <= b - a
constant alu_cmp_c : std_ulogic_vector(3 downto 0) := "1001"; -- b - a (no write back)
--constant alu_dadd_c : std_ulogic_vector(3 downto 0) := "1010"; -- r <= a + b (BCD) [NOT SUPPORTED!]
constant alu_bit_c : std_ulogic_vector(3 downto 0) := "1011"; -- a & b (no write back)
constant alu_bic_c : std_ulogic_vector(3 downto 0) := "1100"; -- r <= !a & b
constant alu_bis_c : std_ulogic_vector(3 downto 0) := "1101"; -- r <= a | b
constant alu_xor_c : std_ulogic_vector(3 downto 0) := "1110"; -- r <= a xor b
constant alu_and_c : std_ulogic_vector(3 downto 0) := "1111"; -- r <= a & b
-- The Core of the Problem: NEO430 Processor Top Entity -----------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_top
generic (
-- general configuration --
CLOCK_SPEED : natural := 100000000; -- main clock in Hz
IMEM_SIZE : natural := 4*1024; -- internal IMEM size in bytes, max 32kB (default=4kB)
DMEM_SIZE : natural := 2*1024; -- internal DMEM size in bytes, max 28kB (default=2kB)
-- additional configuration --
USER_CODE : std_ulogic_vector(15 downto 0) := x"0000"; -- custom user code
-- module configuration --
MULDIV_USE : boolean := true; -- implement multiplier/divider unit? (default=true)
WB32_USE : boolean := true; -- implement WB32 unit? (default=true)
WDT_USE : boolean := true; -- implement WDT? (default=true)
GPIO_USE : boolean := true; -- implement GPIO unit? (default=true)
TIMER_USE : boolean := true; -- implement timer? (default=true)
UART_USE : boolean := true; -- implement UART? (default=true)
CRC_USE : boolean := true; -- implement CRC unit? (default=true)
CFU_USE : boolean := false; -- implement custom functions unit? (default=false)
PWM_USE : boolean := true; -- implement PWM controller? (default=true)
TWI_USE : boolean := true; -- implement two wire serial interface? (default=true)
SPI_USE : boolean := true; -- implement SPI? (default=true)
TRNG_USE : boolean := false; -- implement TRNG? (default=false)
EXIRQ_USE : boolean := true; -- implement EXIRQ? (default=true)
FREQ_GEN_USE : boolean := true; -- implement FREQ_GEN? (default=true)
-- boot configuration --
BOOTLD_USE : boolean := true; -- implement and use bootloader? (default=true)
IMEM_AS_ROM : boolean := false -- implement IMEM as read-only memory? (default=false)
);
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
rst_i : in std_ulogic; -- global reset, async, low-active
-- gpio --
gpio_o : out std_ulogic_vector(15 downto 0); -- parallel output
gpio_i : in std_ulogic_vector(15 downto 0); -- parallel input
-- pwm channels --
pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels
-- arbitrary frequency generator --
freq_gen_o : out std_ulogic_vector(02 downto 0); -- programmable frequency output
-- serial com --
uart_txd_o : out std_ulogic; -- UART send data
uart_rxd_i : in std_ulogic; -- UART receive data
spi_sclk_o : out std_ulogic; -- serial clock line
spi_mosi_o : out std_ulogic; -- serial data line out
spi_miso_i : in std_ulogic; -- serial data line in
spi_cs_o : out std_ulogic_vector(05 downto 0); -- SPI CS
twi_sda_io : inout std_logic; -- twi serial data line
twi_scl_io : inout std_logic; -- twi serial clock line
-- 32-bit wishbone interface --
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
wb_we_o : out std_ulogic; -- read/write
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
wb_stb_o : out std_ulogic; -- strobe
wb_cyc_o : out std_ulogic; -- valid cycle
wb_ack_i : in std_ulogic; -- transfer acknowledge
-- external interrupts --
ext_irq_i : in std_ulogic_vector(07 downto 0); -- external interrupt request lines
ext_ack_o : out std_ulogic_vector(07 downto 0) -- external interrupt request acknowledges
);
end component;
-- Component: CPU Control -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_control
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
rst_i : in std_ulogic; -- global reset, low-active, async
-- memory interface --
instr_i : in std_ulogic_vector(15 downto 0); -- instruction word from memory
-- control --
sreg_i : in std_ulogic_vector(15 downto 0); -- current status register
ctrl_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- control signals
irq_vec_o : out std_ulogic_vector(01 downto 0); -- irq channel address
imm_o : out std_ulogic_vector(15 downto 0); -- branch offset
-- irq lines --
irq_i : in std_ulogic_vector(03 downto 0) -- IRQ lines
);
end component;
-- Component: Register File ---------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_reg_file
generic (
BOOTLD_USE : boolean := true; -- implement and use bootloader?
IMEM_AS_ROM : boolean := false -- implement IMEM as read-only memory?
);
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
rst_i : in std_ulogic; -- global reset, low-active, async
-- data input --
alu_i : in std_ulogic_vector(15 downto 0); -- data from alu
addr_i : in std_ulogic_vector(15 downto 0); -- data from addr unit
flag_i : in std_ulogic_vector(04 downto 0); -- new ALU flags
-- control --
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0);
-- data output --
data_o : out std_ulogic_vector(15 downto 0); -- read data
sreg_o : out std_ulogic_vector(15 downto 0) -- current SR
);
end component;
-- Component: Data ALU --------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_alu
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
-- operands --
reg_i : in std_ulogic_vector(15 downto 0); -- data from reg file
mem_i : in std_ulogic_vector(15 downto 0); -- data from memory
sreg_i : in std_ulogic_vector(15 downto 0); -- current SR
-- control --
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0);
-- results --
data_o : out std_ulogic_vector(15 downto 0); -- result
flag_o : out std_ulogic_vector(04 downto 0) -- new ALU flags
);
end component;
-- Component: Address Generator -----------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_addr_gen
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
-- data input --
reg_i : in std_ulogic_vector(15 downto 0); -- reg file input
mem_i : in std_ulogic_vector(15 downto 0); -- memory input
imm_i : in std_ulogic_vector(15 downto 0); -- branch offset
irq_sel_i : in std_ulogic_vector(01 downto 0); -- IRQ vector
-- control --
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0);
-- data output --
mem_addr_o : out std_ulogic_vector(15 downto 0); -- memory address
dwb_o : out std_ulogic_vector(15 downto 0) -- data write back output
);
end component;
-- Component: CPU core --------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_cpu
generic (
BOOTLD_USE : boolean := true; -- implement and use bootloader?
IMEM_AS_ROM : boolean := false -- implement IMEM as read-only memory?
);
port(
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
rst_i : in std_ulogic; -- global reset, low-active, async
-- memory interface --
mem_rd_o : out std_ulogic; -- memory read
mem_imwe_o : out std_ulogic; -- allow writing to IMEM
mem_wr_o : out std_ulogic_vector(01 downto 0); -- memory write
mem_addr_o : out std_ulogic_vector(15 downto 0); -- address
mem_data_o : out std_ulogic_vector(15 downto 0); -- write data
mem_data_i : in std_ulogic_vector(15 downto 0); -- read data
-- interrupt system --
irq_i : in std_ulogic_vector(03 downto 0) -- interrupt requests
);
end component;
-- Component: Instruction Memory RAM (IMEM) -----------------------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_imem
generic (
IMEM_SIZE : natural := 4*1024; -- internal IMEM size in bytes
IMEM_AS_ROM : boolean := false; -- implement IMEM as read-only memory?
BOOTLD_USE : boolean := true -- implement and use bootloader?
);
port (
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic_vector(01 downto 0); -- write enable
upen_i : in std_ulogic; -- update enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0) -- data out
);
end component;
-- Component: Data Memory RAM (DMEM) ------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_dmem
generic (
DMEM_SIZE : natural := 2*1024 -- internal DMEM size in bytes
);
port (
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic_vector(01 downto 0); -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0) -- data out
);
end component;
-- Component: Bootloader ROM --------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_boot_rom
port (
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_o : out std_ulogic_vector(15 downto 0) -- data out
);
end component;
-- Component: Multiplier/Divider (MULDIV) -------------------------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_muldiv
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0) -- data out
);
end component;
-- Component: 32bit Wishbone Interface (WB32) ---------------------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_wb_interface
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0); -- data out
-- wishbone interface --
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
wb_we_o : out std_ulogic; -- read/write
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
wb_stb_o : out std_ulogic; -- strobe
wb_cyc_o : out std_ulogic; -- valid cycle
wb_ack_i : in std_ulogic -- transfer acknowledge
);
end component;
-- Component: Universal Asynchornous Receiver/Transmitter (UART) --------------------------
-- -------------------------------------------------------------------------------------------
component neo430_uart
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0); -- data out
-- clock generator --
clkgen_en_o : out std_ulogic; -- enable clock generator
clkgen_i : in std_ulogic_vector(07 downto 0);
-- com lines --
uart_txd_o : out std_ulogic;
uart_rxd_i : in std_ulogic;
-- interrupts --
uart_irq_o : out std_ulogic -- uart rx/tx interrupt
);
end component;
-- Component: Serial Peripheral Interface (SPI) -------------------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_spi
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0); -- data out
-- clock generator --
clkgen_en_o : out std_ulogic; -- enable clock generator
clkgen_i : in std_ulogic_vector(07 downto 0);
-- com lines --
spi_sclk_o : out std_ulogic; -- SPI serial clock
spi_mosi_o : out std_ulogic; -- SPI master out, slave in
spi_miso_i : in std_ulogic; -- SPI master in, slave out
spi_cs_o : out std_ulogic_vector(05 downto 0); -- SPI CS
-- interrupt --
spi_irq_o : out std_ulogic -- transmission done interrupt
);
end component;
-- Component: General Purpose Input/Ouput Controller (GPIO) -------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_gpio
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0); -- data out
-- parallel io --
gpio_o : out std_ulogic_vector(15 downto 0);
gpio_i : in std_ulogic_vector(15 downto 0);
-- GPIO PWM --
gpio_pwm_i : in std_ulogic;
-- interrupt --
irq_o : out std_ulogic
);
end component;
-- Component: High-Precision Timer (TIMER) ------------------------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_timer
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0); -- data out
-- clock generator --
clkgen_en_o : out std_ulogic; -- enable clock generator
clkgen_i : in std_ulogic_vector(07 downto 0);
-- interrupt --
irq_o : out std_ulogic -- interrupt request
);
end component;
-- Component: Watchdog Timer (WDT) --------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_wdt
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rst_i : in std_ulogic; -- global (external) reset, low-active, use as async
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0); -- data out
-- clock generator --
clkgen_en_o : out std_ulogic; -- enable clock generator
clkgen_i : in std_ulogic_vector(07 downto 0);
-- system reset --
rst_o : out std_ulogic -- timeout reset, low_active, use as async
);
end component;
-- Component: Cyclic Redundancy Check Unit (CRC)-------------------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_crc
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0) -- data out
);
end component;
-- Component: Custom Functions Unit (CFU) -------------------------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_cfu
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0); -- data out
-- clock generator --
clkgen_en_o : out std_ulogic; -- enable clock generator
clkgen_i : in std_ulogic_vector(07 downto 0)
-- custom IOs --
-- ...
);
end component;
-- Component: PWM Controller (PWM) --------------------------------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_pwm
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0); -- data out
-- clock generator --
clkgen_en_o : out std_ulogic; -- enable clock generator
clkgen_i : in std_ulogic_vector(07 downto 0);
-- GPIO output PWM --
gpio_pwm_o : out std_ulogic;
-- pwm output channels --
pwm_o : out std_ulogic_vector(03 downto 0)
);
end component;
-- Component: Serial Two Wire Interfcae (TWI) ---------------------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_twi
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0); -- data out
-- clock generator --
clkgen_en_o : out std_ulogic; -- enable clock generator
clkgen_i : in std_ulogic_vector(07 downto 0);
-- com lines --
twi_sda_io : inout std_logic; -- serial data line
twi_scl_io : inout std_logic; -- serial clock line
-- interrupt --
twi_irq_o : out std_ulogic -- transfer done IRQ
);
end component;
-- Component: True Random Number Generator (TRNG) -----------------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_trng
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0) -- data out
);
end component;
-- Component: External Interrupts Controller (EXIRQ) --------------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_exirq
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0); -- data out
-- cpu interrupt --
cpu_irq_o : out std_ulogic;
-- external interrupt lines --
ext_irq_i : in std_ulogic_vector(7 downto 0); -- IRQ
ext_ack_o : out std_ulogic_vector(7 downto 0) -- acknowledge
);
end component;
-- Component: Arbitrary Frequency Generator (FREG_GEN)) -----------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_freq_gen
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0); -- data out
-- clock generator --
clkgen_en_o : out std_ulogic; -- enable clock generator
clkgen_i : in std_ulogic_vector(07 downto 0);
-- frequency generator --
freq_gen_o : out std_ulogic_vector(02 downto 0) -- programmable frequency output
);
end component;
-- Component: System Configuration (SYSCONFIG) --------------------------------------------
-- -------------------------------------------------------------------------------------------
component neo430_sysconfig
generic (
-- general configuration --
CLOCK_SPEED : natural := 100000000; -- main clock in Hz
IMEM_SIZE : natural := 4*1024; -- internal IMEM size in bytes
DMEM_SIZE : natural := 2*1024; -- internal DMEM size in bytes
-- additional configuration --
USER_CODE : std_ulogic_vector(15 downto 0) := x"0000"; -- custom user code
-- module configuration --
MULDIV_USE : boolean := true; -- implement multiplier/divider unit?
WB32_USE : boolean := true; -- implement WB32 unit?
WDT_USE : boolean := true; -- implement WDT?
GPIO_USE : boolean := true; -- implement GPIO unit?
TIMER_USE : boolean := true; -- implement timer?
UART_USE : boolean := true; -- implement UART?
CRC_USE : boolean := true; -- implement CRC unit?
CFU_USE : boolean := true; -- implement CF unit?
PWM_USE : boolean := true; -- implement PWM controller?
TWI_USE : boolean := true; -- implement TWI?
SPI_USE : boolean := true; -- implement SPI?
TRNG_USE : boolean := true; -- implement TRNG?
EXIRQ_USE : boolean := true; -- implement EXIRQ?
FREQ_GEN_USE : boolean := true; -- implement FREQ_GEN?
-- boot configuration --
BOOTLD_USE : boolean := true; -- implement and use bootloader?
IMEM_AS_ROM : boolean := false -- implement IMEM as read-only memory?
);
port (
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0) -- data out
);
end component;
end neo430_package;
package body neo430_package is
-- Function: Minimal required bit width ---------------------------------------------------
-- -------------------------------------------------------------------------------------------
function index_size_f(input : natural) return natural is
begin
for i in 0 to natural'high loop
if (2**i >= input) then
return i;
end if;
end loop; -- i
return 0;
end function index_size_f;
-- Function: Test if value (encoded with a certain bit width) is a power of 2 -------------
-- -------------------------------------------------------------------------------------------
function is_power_of_two_f(num : natural; bit_width : natural) return boolean is
begin
for i in 0 to bit_width loop
if ((2**i) = num) then
return true;
end if;
end loop; -- i
return false;
end function is_power_of_two_f;
-- Function: Bit reversal -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
function bit_reversal_f(input : std_ulogic_vector) return std_ulogic_vector is
variable output_v : std_ulogic_vector(input'range);
begin
for i in 0 to input'length-1 loop
output_v(input'length-i-1) := input(i);
end loop; -- i
return output_v;
end function bit_reversal_f;
-- Function: Count number of set bits (aka population count) ------------------------------
-- -------------------------------------------------------------------------------------------
function set_bits_f(input : std_ulogic_vector) return natural is
variable cnt_v : natural range 0 to input'length-1;
begin
cnt_v := 0;
for i in input'length-1 downto 0 loop
if (input(i) = '1') then
cnt_v := cnt_v + 1;
end if;
end loop; -- i
return cnt_v;
end function set_bits_f;
-- Function: Count leading zeros ----------------------------------------------------------
-- -------------------------------------------------------------------------------------------
function leading_zeros_f(input : std_ulogic_vector) return natural is
variable cnt_v : natural range 0 to input'length;
begin
cnt_v := 0;
for i in input'length-1 downto 0 loop
if (input(i) = '0') then
cnt_v := cnt_v + 1;
else
exit;
end if;
end loop; -- i
return cnt_v;
end function leading_zeros_f;
-- Function: Conditional select natural ---------------------------------------------------
-- -------------------------------------------------------------------------------------------
function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural is
begin
if (cond = true) then
return val_t;
else
return val_f;
end if;
end function cond_sel_natural_f;
-- Function: Conditional select std_ulogic_vector -----------------------------------------
-- -------------------------------------------------------------------------------------------
function cond_sel_stdulogicvector_f(cond : boolean; val_t : std_ulogic_vector; val_f : std_ulogic_vector) return std_ulogic_vector is
begin
if (cond = true) then
return val_t;
else
return val_f;
end if;
end function cond_sel_stdulogicvector_f;
-- Function: Convert BOOL to STD_ULOGIC ---------------------------------------------------
-- -------------------------------------------------------------------------------------------
function bool_to_ulogic_f(cond : boolean) return std_ulogic is
begin
if (cond = true) then
return '1';
else
return '0';
end if;
end function bool_to_ulogic_f;
-- Function: Binary to Gray ---------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
function bin_to_gray_f(input : std_ulogic_vector) return std_ulogic_vector is
variable output_v : std_ulogic_vector(input'range);
begin
output_v(input'length-1) := input(input'length-1); -- keep MSB
for i in input'length-2 downto 0 loop
output_v(i) := input(i) xor input(i+1);
end loop; -- i
return output_v;
end function bin_to_gray_f;
-- Function: Gray to Binary ---------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
function gray_to_bin_f(input : std_ulogic_vector) return std_ulogic_vector is
variable output_v : std_ulogic_vector(input'range);
begin
output_v(input'length-1) := input(input'length-1); -- keep MSB
for i in input'length-2 downto 0 loop
output_v(i) := output_v(i+1) xor input(i);
end loop; -- i
return output_v;
end function gray_to_bin_f;
-- Function: Integer (4-bit) to hex char --------------------------------------------------
-- -------------------------------------------------------------------------------------------
function int_to_hexchar_f(input : integer) return character is
variable output_v : character;
begin
case (input) is
when 0 => output_v := '0';
when 1 => output_v := '1';
when 2 => output_v := '2';
when 3 => output_v := '3';
when 4 => output_v := '4';
when 5 => output_v := '5';
when 6 => output_v := '6';
when 7 => output_v := '7';
when 8 => output_v := '8';
when 9 => output_v := '9';
when 10 => output_v := 'A';
when 11 => output_v := 'B';
when 12 => output_v := 'C';
when 13 => output_v := 'D';
when 14 => output_v := 'E';
when 15 => output_v := 'F';
when others => output_v := '?';
end case;
return output_v;
end function int_to_hexchar_f;
-- Function: OR all bits ------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
function or_all_f(a : std_ulogic_vector) return std_ulogic is
variable tmp_v : std_ulogic;
begin
tmp_v := a(a'low);
for i in a'low+1 to a'high loop
tmp_v := tmp_v or a(i);
end loop; -- i
return tmp_v;
end function or_all_f;
-- Function: AND all bits -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
function and_all_f(a : std_ulogic_vector) return std_ulogic is
variable tmp_v : std_ulogic;
begin
tmp_v := a(a'low);
for i in a'low+1 to a'high loop
tmp_v := tmp_v and a(i);
end loop; -- i
return tmp_v;
end function and_all_f;
-- Function: XOR all bits -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
function xor_all_f(a : std_ulogic_vector) return std_ulogic is
variable tmp_v : std_ulogic;
begin
tmp_v := a(a'low);
for i in a'low+1 to a'high loop
tmp_v := tmp_v xor a(i);
end loop; -- i
return tmp_v;
end function xor_all_f;
end neo430_package;
|
bsd-3-clause
|
63200daab841b94be992505a471b564d
| 0.523633 | 3.952378 | false | false | false | false |
beltagymohamed/FLOATING-POINT-MULTIPLIER-USING-FPGA
|
Multiplier/Project/VHDL/control.vhd
| 1 | 1,222 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity control is
port (clk,rst,en: in std_logic;
done_m: in std_logic;
done:out std_logic;
en_mul: out std_logic_vector(1 downto 0)
);
end control;
architecture arch_control of control is
type states is (idle,load,multiply,deploy);
signal State, NextState : states;
begin
FSM:process(State) begin
NextState<=idle;
done<='0';
en_mul<="00";
case State is
when idle =>
done<='0';
en_mul<="00";
if(en='1') then
NextState<=load;
else
NextState<=idle;
end if;
when load =>
NextState<=multiply;
done<='0';
en_mul<="01";
when multiply =>
done<='0';
en_mul<="11";
if(done_m='1') then
NextState<=deploy;
else
NextState<=multiply;
end if;
when deploy =>
done<='1';
en_mul<="11";
NextState<=idle;
end case;
end process;
transitions:process (clk, rst) begin
if rst='0'then
State <= idle;
elsif (clk'event and clk='1')then
State <= NextState;
end if;
end process;
end arch_control;
|
mit
|
92a6db7412c148afd4e6e7a98c61801f
| 0.540098 | 3.542029 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/v_source.vhd
| 4 | 1,665 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.math_real.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity v_source is
generic ( DC : voltage := 1.0; -- output peak amplitude
ac_mag : voltage := 1.0; -- AC magnitude
ac_phase : real := 0.0 ); -- AC phase [degree]
port ( terminal pos, neg : electrical );
end entity v_source;
----------------------------------------------------------------
architecture behavior of v_source is
quantity vout across iout through pos to neg;
-- declare quantity in frequency domain for AC analysis
quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
begin
if domain = quiescent_domain or domain = time_domain use
vout == DC;
else
vout == ac_spec; -- used for frequency (AC) analysis
end use;
end architecture behavior;
|
gpl-2.0
|
d54e39375971c346b86e8ebd5a8e764e
| 0.664865 | 4.1625 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_19_queue-b.vhd
| 4 | 6,914 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_queue-b.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library math;
architecture behavior of queue is
begin
queue_manager : process is
use qsim.queue_types.all, qsim.waiting_token_fifo_adt.all;
variable waiting_token, head_token : waiting_token_type;
variable waiting_token_fifo : fifo_type := new_fifo;
variable out_token_in_transit : boolean := false;
variable number_of_tokens_released : natural := 0;
variable current_queue_size : natural := 0;
variable maximum_queue_size : natural := 0;
variable waiting_time : natural; -- in time_unit
variable sum_of_waiting_times : real := 0.0; -- in time_unit
variable sum_of_squares_of_waiting_times : real := 0.0; --in time_unit**2
use std.textio.all;
file info_file : text;
variable L : line;
use math.math_real.sqrt;
procedure write_summary is
variable mean_waiting_time : real
:= sum_of_waiting_times / real(number_of_tokens_released);
variable std_dev_of_waiting_times : real
:= sqrt ( ( sum_of_squares_of_waiting_times
- sum_of_waiting_times**2 / real(number_of_tokens_released) )
/ real( number_of_tokens_released - 1 ) );
begin
write(L, string'("Summary information for queue "));
write(L, name);
write(L, string'(" up to time "));
write(L, now, unit => time_unit);
writeline(info_file, L);
write(L, string'(" Number of tokens currently waiting = "));
write(L, natural(current_queue_size));
writeline(info_file, L);
write(L, string'(" Number of tokens released = "));
write(L, natural(number_of_tokens_released));
writeline(info_file, L);
write(L, string'(" Maximum queue size = "));
write(L, natural(maximum_queue_size));
writeline(info_file, L);
write(L, string'(" Mean waiting time = "));
write(L, mean_waiting_time * time_unit, unit => time_unit);
writeline(info_file, L);
write(L, string'(" Standard deviation of waiting times = "));
write(L, std_dev_of_waiting_times * time_unit, unit => time_unit);
writeline(info_file, L);
writeline(info_file, L);
end procedure write_summary;
procedure write_trace_enqueue is
begin
write(L, string'("Queue "));
write(L, name);
write(L, string'(": at "));
write(L, now, unit => time_unit);
write(L, string'(" enqueued "));
write(L, waiting_token.token, time_unit);
writeline(info_file, L);
end procedure write_trace_enqueue;
procedure write_trace_dequeue is
begin
write(L, string'("Queue "));
write(L, name);
write(L, string'(": at "));
write(L, now, unit => time_unit);
write(L, string'(" dequeued "));
write(L, head_token.token, time_unit);
writeline(info_file, L);
end procedure write_trace_dequeue;
begin
file_open(info_file, info_file_name, write_mode);
loop
wait on info_detail'transaction, in_arc, out_ready;
if info_detail'active and info_detail = summary then
write_summary;
end if;
if in_arc'event then
waiting_token := waiting_token_type'( token => in_arc.token,
time_when_enqueued => now );
insert(waiting_token_fifo, waiting_token);
current_queue_size := current_queue_size + 1;
if current_queue_size > maximum_queue_size then
maximum_queue_size := current_queue_size;
end if;
if info_detail = trace then
write_trace_enqueue;
end if;
end if;
if out_ready and current_queue_size > 0 and not out_token_in_transit then
remove(waiting_token_fifo, head_token);
current_queue_size := current_queue_size - 1;
out_arc <= arc_type'( transaction => not out_arc.transaction'driving_value,
token => head_token.token );
out_token_in_transit := true;
number_of_tokens_released := number_of_tokens_released + 1;
waiting_time := (now - head_token.time_when_enqueued) / time_unit;
sum_of_waiting_times := sum_of_waiting_times + real(waiting_time);
sum_of_squares_of_waiting_times := sum_of_squares_of_waiting_times
+ real(waiting_time) ** 2;
if info_detail = trace then
write_trace_dequeue;
end if;
end if;
if out_token_in_transit and not out_ready then
out_token_in_transit := false;
end if;
end loop;
end process queue_manager;
end architecture behavior;
|
gpl-2.0
|
cf5f57e90de2cd060c6146fddfb09f0e
| 0.48814 | 4.68111 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_10.vhd
| 4 | 2,067 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ap_a_ap_a_10.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity ap_a_10 is
end entity ap_a_10;
library ieee;
use ieee.std_logic_1164.all;
library stimulus;
use stimulus.stimulus_generators.all;
architecture test of ap_a_10 is
signal a, b, c, d : std_ulogic;
signal test_vector : std_ulogic_vector(1 to 4);
begin
b1 : block is
signal y : std_ulogic;
begin
-- code from book
y <= a or b or c or d;
-- end code from book
end block b1;
b2 : block is
signal y : std_ulogic;
begin
-- code from book
y <= ( a or b ) or ( c or d );
-- end code from book
end block b2;
b3 : block is
signal y : std_ulogic;
begin
-- code from book (syntax error)
-- y <= a or b or c and d;
-- end code from book
end block b3;
b4 : block is
signal y : std_ulogic;
begin
-- code from book
y <= ( a or b ) or ( c and d );
-- end code from book
end block b4;
stimulus : all_possible_values(test_vector, 10 ns);
(a, b, c, d) <= test_vector;
end architecture test;
|
gpl-2.0
|
9669d3255f7e1d01a18026da735b3ee7
| 0.592646 | 3.691071 | false | true | false | false |
beltagymohamed/FLOATING-POINT-MULTIPLIER-USING-FPGA
|
Multiplier/Project/VHDL/mul_int2.vhd
| 1 | 1,471 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mul_int2 is
port (in1: in std_logic_vector(23 downto 0);
in2: in std_logic_vector(23 downto 0);
clk,rst: in std_logic;
done:out std_logic;
res: out std_logic_vector(47 downto 0)
);
end mul_int2;
architecture arch_mul_int2_1 of mul_int2 is
component shifter2
port (in1: in std_logic_vector(23 downto 0);
in2: in unsigned(4 downto 0);
rst: in std_logic;
res: out std_logic_vector (47 downto 0));
end component;
signal rsh: std_logic_vector(47 downto 0):=(others=>'0');
signal r: std_logic_vector(47 downto 0):=(others=>'0');
signal counter: unsigned(4 downto 0):="00000";
signal d: std_logic;
begin
sh: shifter2 port map(in1=>in2,in2=>counter,rst=>rst,res=>rsh );
res<=r(47 downto 0);
done<=d;
process (rst,clk)
begin
if rst='0' then
r<=(others=>'0');
counter<="00000";
d<='0';
else
if(rising_edge(clk)) then
if(in1(to_integer(counter))='1' and d='0') then
r<=std_logic_vector(unsigned(r)+unsigned(rsh));
end if;
if(counter="10111") then
d<='1';
else
counter<=counter+1;
end if;
end if;
end if;
end process;
end arch_mul_int2_1;
|
mit
|
32cdd1c50aa983d4f174f66264d9137c
| 0.525493 | 3.453052 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc476.vhd
| 4 | 3,394 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc476.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00476ent IS
END c03s02b01x01p19n01i00476ent;
ARCHITECTURE c03s02b01x01p19n01i00476arch OF c03s02b01x01p19n01i00476ent IS
type severity_level_vector is array (natural range <>) of severity_level;
function resolution2(i:in severity_level_vector) return severity_level is
variable temp : severity_level := note;
begin
return temp;
end resolution2;
subtype severity_level_state is resolution2 severity_level;
constant C66 : severity_level_state := note;
function complex_scalar(s : severity_level_state) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return severity_level_state is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : severity_level_state;
signal S2 : severity_level_state;
signal S3 : severity_level_state:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00476"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00476 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00476arch;
|
gpl-2.0
|
477e4596de99c047a8b1a3bb6013cdb1
| 0.663524 | 3.7012 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc468.vhd
| 4 | 3,364 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc468.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00468ent IS
END c03s02b01x01p19n01i00468ent;
ARCHITECTURE c03s02b01x01p19n01i00468arch of c03s02b01x01p19n01i00468ent IS
constant low_number : integer := 0;
constant hi_number : integer := 7;
subtype hi_to_low_range is integer range low_number to hi_number;
type time_vector is array (natural range <>) of time;
subtype time_vector_range is time_vector(hi_to_low_range);
constant C66: time_vector_range := (others => 3 ns);
function complex_scalar(s : time_vector_range) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return time_vector_range is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : time_vector_range;
signal S2 : time_vector_range;
signal S3 : time_vector_range:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00468"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00468 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00468arch;
|
gpl-2.0
|
24e7f767c80aabde53fc25d7a6ef884b
| 0.653092 | 3.621098 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc659.vhd
| 4 | 3,116 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc659.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:55 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:23 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:34 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00659ent IS
END c03s04b01x00p01n01i00659ent;
ARCHITECTURE c03s04b01x00p01n01i00659arch OF c03s04b01x00p01n01i00659ent IS
constant low_number : integer := 0;
constant hi_number : integer := 7;
subtype hi_to_low_range is integer range low_number to hi_number;
type time_vector is array (natural range <>) of time;
subtype time_vector_range is time_vector(hi_to_low_range);
constant C1 : time_vector_range := (others => 3 ns);
type time_vector_range_file is file of time_vector_range;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : time_vector_range_file open read_mode is "iofile.07";
variable v : time_vector_range := C1;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C1) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00659"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00659 - File reading of time_vector_range_file operation failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00659arch;
|
gpl-2.0
|
5c9e2fb1849b0e5cb58edd106c45c1f1
| 0.557766 | 3.924433 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc760.vhd
| 4 | 8,201 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc760.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p05n02i00760pkg is
--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level:= note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C10 : string := "shishir";
constant C11 : bit_vector := B"0011";
constant C12 : boolean_vector:= (true,false);
constant C13 : severity_level_vector := (note,error);
constant C14 : integer_vector:= (1,2,3,4);
constant C15 : real_vector := (1.0,2.0,3.0,4.0);
constant C16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
constant C17 : natural_vector:= (1,2,3,4);
constant C18 : positive_vector:= (1,2,3,4);
end c01s01b01x01p05n02i00760pkg;
use work.c01s01b01x01p05n02i00760pkg.ALL;
ENTITY c01s01b01x01p05n02i00760ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three : integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven : integer := 7;
eight : integer := 8;
nine : integer := 9;
fifteen :integer:= 15;
Cgen1 : boolean := true;
Cgen2 : bit := '1';
Cgen3 : character := 's';
Cgen4 : severity_level := note;
Cgen5 : integer := 3;
Cgen6 : real := 3.0;
Cgen7 : time := 3 ns;
Cgen8 : natural := 1;
Cgen9 : positive := 1;
Cgen10 : string := "shishir";
Cgen11 : bit_vector := B"0011";
Cgen12 : boolean_vector := (true,false);
Cgen13 : severity_level_vector := (note,error);
Cgen14 : integer_vector := (1,2,3,4);
Cgen15 : real_vector := (1.0,2.0,3.0,4.0);
Cgen16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
Cgen17 : natural_vector := (1,2,3,4);
Cgen18 : positive_vector := (1,2,3,4)
);
END c01s01b01x01p05n02i00760ent;
ARCHITECTURE c01s01b01x01p05n02i00760arch OF c01s01b01x01p05n02i00760ent IS
signal Vgen1 : boolean := true;
signal Vgen2 : bit := '1';
signal Vgen3 : character := 's';
signal Vgen4 : severity_level:= note;
signal Vgen5 : integer := 3;
signal Vgen6 : real := 3.0;
signal Vgen7 : time := 3 ns;
signal Vgen8 : natural := 1;
signal Vgen9 : positive := 1;
signal Vgen10 : string (one to seven) := "shishir";
signal Vgen11 : bit_vector(zero to three) := B"0011";
signal Vgen12 : boolean_vector(zero to one) := (true,false);
signal Vgen13 : severity_level_vector(zero to one) := (note,error);
signal Vgen14 : integer_vector(zero to three) := (1,2,3,4);
signal Vgen15 : real_vector(zero to three) := (1.0,2.0,3.0,4.0);
signal Vgen16 : time_vector(zero to three) := (1 ns, 2 ns, 3 ns, 4 ns);
signal Vgen17 : natural_vector(zero to three) := (1,2,3,4);
signal Vgen18 : positive_vector(zero to three) := (1,2,3,4);
BEGIN
assert Vgen1 = C1 report "Initializing signal with generic Vgen1 does not work" severity error;
assert Vgen2 = C2 report "Initializing signal with generic Vgen2 does not work" severity error;
assert Vgen3 = C3 report "Initializing signal with generic Vgen3 does not work" severity error;
assert Vgen4 = C4 report "Initializing signal with generic Vgen4 does not work" severity error;
assert Vgen5 = C5 report "Initializing signal with generic Vgen5 does not work" severity error;
assert Vgen6 = C6 report "Initializing signal with generic Vgen6 does not work" severity error;
assert Vgen7 = C7 report "Initializing signal with generic Vgen7 does not work" severity error;
assert Vgen8 = C8 report "Initializing signal with generic Vgen8 does not work" severity error;
assert Vgen9 = C9 report "Initializing signal with generic Vgen9 does not work" severity error;
assert Vgen10 = C10 report "Initializing signal with generic Vgen10 does not work" severity error;
assert Vgen11 = C11 report "Initializing signal with generic Vgen11 does not work" severity error;
assert Vgen12 = C12 report "Initializing signal with generic Vgen12 does not work" severity error;
assert Vgen13 = C13 report "Initializing signal with generic Vgen13 does not work" severity error;
assert Vgen14 = C14 report "Initializing signal with generic Vgen14 does not work" severity error;
assert Vgen15 = C15 report "Initializing signal with generic Vgen15 does not work" severity error;
assert Vgen16 = C16 report "Initializing signal with generic Vgen16 does not work" severity error;
assert Vgen17 = C17 report "Initializing signal with generic Vgen17 does not work" severity error;
assert Vgen18 = C18 report "Initializing signal with generic Vgen18 does not work" severity error;
TESTING: PROCESS
BEGIN
assert NOT( Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen10 = C10 and
Vgen11 = C11 and
Vgen12 = C12 and
Vgen13 = C13 and
Vgen14 = C14 and
Vgen15 = C15 and
Vgen16 = C16 and
Vgen17 = C17 and
Vgen18 = C18 )
report "***PASSED TEST: c01s01b01x01p05n02i00760"
severity NOTE;
assert( Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen10 = C10 and
Vgen11 = C11 and
Vgen12 = C12 and
Vgen13 = C13 and
Vgen14 = C14 and
Vgen15 = C15 and
Vgen16 = C16 and
Vgen17 = C17 and
Vgen18 = C18 )
report "***FAILED TEST: c01s01b01x01p05n02i00760 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00760arch;
|
gpl-2.0
|
52aea6ac89521d6e93750601f6e1e6b8
| 0.595537 | 3.717588 | false | false | false | false |
jakubcabal/pipemania-fpga-game
|
source/comp/video/cell_generator.vhd
| 1 | 17,170 |
--------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: CELL_GENERATOR
-- AUTHORS: Jakub Cabal <[email protected]>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/pipemania-fpga-game
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity CELL_GENERATOR is
Port (
CLK : in std_logic;
RST : in std_logic;
TYP_ROURY : in std_logic_vector(3 downto 0);
NATOCENI_ROURY : in std_logic_vector(1 downto 0);
ROURA_VODA1 : in std_logic_vector(5 downto 0);
ROURA_VODA2 : in std_logic_vector(5 downto 0);
ZDROJ_VODY1 : in std_logic_vector(3 downto 0);
ZDROJ_VODY2 : in std_logic_vector(3 downto 0);
KURZOR : in std_logic;
PIXEL_X2 : in std_logic_vector(9 downto 0);
PIXEL_Y2 : in std_logic_vector(9 downto 0);
PIXEL_SET_X : in std_logic;
PIXEL_SET_Y : in std_logic;
KOMP_SET_X : in std_logic;
KOMP_SET_Y : in std_logic;
KOMP_ON : in std_logic;
KOMP4_IS : in std_logic;
KOMP_IN : in std_logic_vector(5 downto 0);
GAME_ON : in std_logic;
LOAD_WATER : in std_logic_vector(7 downto 0);
RGB : out std_logic_vector(2 downto 0)
);
end CELL_GENERATOR;
architecture FULL of CELL_GENERATOR is
signal cell_x_l : unsigned(9 downto 0);
signal cell_x_r : unsigned(9 downto 0);
signal cell_y_t : unsigned(9 downto 0);
signal cell_y_b : unsigned(9 downto 0);
signal rom_addr : std_logic_vector(8 downto 0);
signal img_row : unsigned(4 downto 0);
signal img_col : unsigned(4 downto 0);
signal sig_komp_in : std_logic_vector(5 downto 0);
signal rom_data : std_logic_vector(31 downto 0);
signal rom_bit : std_logic;
signal sq_cell_on : std_logic;
signal sig_kurzor : std_logic;
signal sig_komp_on : std_logic;
signal pix_x : unsigned(9 downto 0);
signal pix_y : unsigned(9 downto 0);
signal pix_x2 : unsigned(9 downto 0);
signal pix_y2 : unsigned(9 downto 0);
signal sig_typ_roury : std_logic_vector(3 downto 0);
signal sig_typ_roury2 : std_logic_vector(3 downto 0);
signal sig_natoceni_roury : std_logic_vector(1 downto 0);
signal load_water_lenght : unsigned(9 downto 0);
signal load_water_on : std_logic;
signal roura_water_lr : std_logic;
signal roura_water_rl : std_logic;
signal roura_water_bt : std_logic;
signal roura_water_tb : std_logic;
signal roura_water_h : std_logic;
signal roura_water_v : std_logic;
signal roura_water_lenght_1 : unsigned(9 downto 0);
signal roura_water_lenght_2 : unsigned(9 downto 0);
signal roura_water_lenght_h : unsigned(9 downto 0);
signal roura_water_lenght_v : unsigned(9 downto 0);
signal mini_water_lenght : unsigned(9 downto 0);
signal first_water_lenght : unsigned(9 downto 0);
signal last_water_lenght : unsigned(9 downto 0);
signal roura_water_h_offset : unsigned(9 downto 0);
signal roura_water_v_offset : unsigned(9 downto 0);
signal white_point_is_reg : std_logic;
signal water_is : std_logic;
signal water_is_reg : std_logic;
signal game_field_text : std_logic;
signal game_field_text_reg : std_logic;
signal wall_is : std_logic;
signal wall_is_reg : std_logic;
signal kurzor_is : std_logic;
signal kurzor_is_reg : std_logic;
signal sq_cell_on_reg : std_logic;
signal rom_bit_reg : std_logic;
signal komp4_is_reg : std_logic;
begin
pix_x2 <= unsigned(PIXEL_X2);
pix_y2 <= unsigned(PIXEL_Y2);
sig_komp_on <= KOMP_ON;
sig_komp_in <= KOMP_IN;
process (CLK)
begin
if rising_edge(CLK) then
pix_x <= pix_x2;
pix_y <= pix_y2;
sig_kurzor <= KURZOR;
sig_typ_roury2 <= sig_typ_roury;
end if;
end process;
-- Nastaveni X souradnic pro okraje
process (CLK, RST)
begin
if (RST = '1') then
cell_x_l <= (others => '0');
cell_x_r <= (others => '0');
elsif (rising_edge(CLK)) then
if (PIXEL_SET_X = '1' AND GAME_ON = '1') then
cell_x_l <= pix_x;
cell_x_r <= pix_x + 31;
elsif (KOMP_SET_X = '1' AND KOMP_ON = '1') then
cell_x_l <= pix_x;
cell_x_r <= pix_x + 31;
end if;
end if;
end process;
-- Nastaveni Y souradnic pro okraje
process (CLK, RST)
begin
if (RST = '1') then
cell_y_t <= (others => '0');
cell_y_b <= (others => '0');
elsif (rising_edge(CLK)) then
if (PIXEL_SET_Y = '1' AND GAME_ON = '1') then
cell_y_t <= pix_y;
cell_y_b <= pix_y + 31;
elsif (KOMP_SET_Y = '1' AND KOMP_ON = '1') then
cell_y_t <= pix_y;
cell_y_b <= pix_y + 31;
end if;
end if;
end process;
-- volba natoceni roury
sig_natoceni_roury <= sig_komp_in(5 downto 4) when (KOMP_ON = '1')
else NATOCENI_ROURY;
-- volba typu roury
sig_typ_roury <= sig_komp_in(3 downto 0) when (KOMP_ON = '1')
else TYP_ROURY;
-- Pripraveni souradnic obrazku, rorace obrazku
pipe_rotate : process (sig_natoceni_roury, pix_x, pix_y, cell_y_t, cell_x_l)
begin
case sig_natoceni_roury is
when "00" => -- zahnuta zleva dolu 00
img_row <= pix_y(4 downto 0) - cell_y_t(4 downto 0);
img_col <= 31 - (pix_x(4 downto 0) - cell_x_l(4 downto 0));
when "01" => -- zahnuta zleva nahoru 01
img_col <= 31 - (pix_y(4 downto 0) - cell_y_t(4 downto 0));
img_row <= 31 - (pix_x(4 downto 0) - cell_x_l(4 downto 0));
when "10" => -- zahnuta zprava nahoru 10
img_row <= 31 - (pix_y(4 downto 0) - cell_y_t(4 downto 0));
img_col <= pix_x(4 downto 0) - cell_x_l(4 downto 0);
when others => -- zahnuta zprava dolu 11
img_row <= pix_y(4 downto 0) - cell_y_t(4 downto 0);
img_col <= pix_x(4 downto 0) - cell_x_l(4 downto 0);
end case;
end process;
-- Read ROM address
rom_addr <= sig_typ_roury & std_logic_vector(img_row);
rom_cell_i : entity work.BRAM_ROM_CELL
port map (
CLK => CLK,
ROM_ADDR => rom_addr,
ROM_DOUT => rom_data
);
-- Vyber konkretniho bitu ve vyctenem radku obrazku
rom_bit <= rom_data(to_integer(img_col));
-- Rika nam ze vykreslujeme pixeli, ktere se nachazi v policku
sq_cell_on <= '1' when ((cell_x_l <= pix_x) and (pix_x <= cell_x_r) and
(cell_y_t <= pix_y) and (pix_y <= cell_y_b))
else '0';
----------------------------------------------------------------------------
-- ZOBRAZOVANI VODY V BOCNI ODPOCITAVACI TRUBCE
----------------------------------------------------------------------------
load_water_lenght <= "00" & (unsigned(LOAD_WATER));
-- vykresleni vody ktera odpocitava kontrolu trubek
load_water_on <= '1' when ((35 <= pix_x) and (pix_x <= 60) and
((319 - load_water_lenght) <= pix_y) and
(pix_y <= 319))
else '0';
----------------------------------------------------------------------------
-- ZOBRAZOVANI VODY V TRUBKACH
----------------------------------------------------------------------------
-- zleva doprava
roura_water_lr <= '1' when (((cell_x_l + roura_water_h_offset) <= pix_x) and
(pix_x <= (cell_x_l + roura_water_h_offset + roura_water_lenght_h)) and
((cell_y_t + 14) <= pix_y) and (pix_y <= (cell_y_t + 17)))
else '0';
-- zprava doleva
roura_water_rl <= '1' when ((((cell_x_r - roura_water_h_offset) - roura_water_lenght_h) <= pix_x) and
(pix_x <= (cell_x_r - roura_water_h_offset)) and
((cell_y_t + 14) <= pix_y) and (pix_y <= (cell_y_t + 17)))
else '0';
-- zdola nahoru
roura_water_bt <= '1' when (((cell_x_l + 14) <= pix_x) and (pix_x <= (cell_x_l + 17)) and
(((cell_y_b - roura_water_v_offset) - roura_water_lenght_v) <= pix_y) and
(pix_y <= (cell_y_b - roura_water_v_offset)))
else '0';
-- zprava doleva
roura_water_tb <= '1' when (((cell_x_l + 14) <= pix_x) and (pix_x <= (cell_x_l + 17)) and
((cell_y_t + roura_water_v_offset) <= pix_y) and
(pix_y <= (cell_y_t + roura_water_v_offset + roura_water_lenght_v)))
else '0';
process (ROURA_VODA1, mini_water_lenght)
begin
if (ROURA_VODA1(5) = '1') then
first_water_lenght <= "0000001111";
last_water_lenght <= mini_water_lenght;
else
first_water_lenght <= mini_water_lenght;
last_water_lenght <= (others => '0');
end if;
end process;
roura_water_lenght_1 <= "00000" & (unsigned(ROURA_VODA1(5 downto 1)));
roura_water_lenght_2 <= "00000" & (unsigned(ROURA_VODA2(5 downto 1)));
mini_water_lenght <= "000000" & (unsigned(ROURA_VODA1(4 downto 1)));
process (ZDROJ_VODY1, sig_typ_roury2, ROURA_VODA1, roura_water_lr,
roura_water_rl, roura_water_lenght_1, first_water_lenght,
last_water_lenght)
begin
if ((sig_typ_roury2 = "0001" OR sig_typ_roury2 = "0011") AND ROURA_VODA1(0) = '1' AND ZDROJ_VODY1 = "0001") then
roura_water_h <= roura_water_lr;
roura_water_lenght_h <= roura_water_lenght_1;
roura_water_h_offset <= to_unsigned(0, 10);
elsif ((sig_typ_roury2 = "0001" OR sig_typ_roury2 = "0011") AND ROURA_VODA1(0) = '1' AND ZDROJ_VODY1 = "0010") then
roura_water_h <= roura_water_rl;
roura_water_lenght_h <= roura_water_lenght_1;
roura_water_h_offset <= to_unsigned(0, 10);
elsif (sig_typ_roury2 = "0010" AND ROURA_VODA1(0) = '1' AND (ZDROJ_VODY1 = "0101" OR ZDROJ_VODY1 = "0110")) then
roura_water_h <= roura_water_lr;
roura_water_lenght_h <= first_water_lenght;
roura_water_h_offset <= to_unsigned(0, 10);
elsif (sig_typ_roury2 = "0010" AND ROURA_VODA1(0) = '1' AND (ZDROJ_VODY1 = "0111" OR ZDROJ_VODY1 = "1000")) then
roura_water_h <= roura_water_rl;
roura_water_lenght_h <= first_water_lenght;
roura_water_h_offset <= to_unsigned(0, 10);
elsif (sig_typ_roury2 = "0010" AND ROURA_VODA1(0) = '1' AND ROURA_VODA1(5) = '1' AND (ZDROJ_VODY1 = "1001" OR ZDROJ_VODY1 = "1011")) then
roura_water_h <= roura_water_lr;
roura_water_lenght_h <= last_water_lenght;
roura_water_h_offset <= to_unsigned(16, 10);
elsif (sig_typ_roury2 = "0010" AND ROURA_VODA1(0) = '1' AND ROURA_VODA1(5) = '1' AND (ZDROJ_VODY1 = "1010" OR ZDROJ_VODY1 = "1100")) then
roura_water_h <= roura_water_rl;
roura_water_lenght_h <= last_water_lenght;
roura_water_h_offset <= to_unsigned(16, 10);
else
roura_water_h <= '0';
roura_water_lenght_h <= roura_water_lenght_1;
roura_water_h_offset <= to_unsigned(0, 10);
end if;
end process;
process (ZDROJ_VODY1, ZDROJ_VODY2, sig_typ_roury2, ROURA_VODA1, ROURA_VODA2,
roura_water_tb, roura_water_bt, roura_water_lenght_2,
first_water_lenght, last_water_lenght)
begin
if ((sig_typ_roury2 = "0001" OR sig_typ_roury2 = "0011") AND ROURA_VODA2(0) = '1' AND ZDROJ_VODY2 = "0011") then
roura_water_v <= roura_water_bt;
roura_water_lenght_v <= roura_water_lenght_2;
roura_water_v_offset <= to_unsigned(0, 10);
elsif ((sig_typ_roury2 = "0001" OR sig_typ_roury2 = "0011") AND ROURA_VODA2(0) = '1' AND ZDROJ_VODY2 = "0100") then
roura_water_v <= roura_water_tb;
roura_water_lenght_v <= roura_water_lenght_2;
roura_water_v_offset <= to_unsigned(0, 10);
elsif (sig_typ_roury2 = "0010" AND ROURA_VODA1(0) = '1' AND ROURA_VODA1(5) = '1' AND (ZDROJ_VODY1 = "0101" OR ZDROJ_VODY1 = "0111")) then
roura_water_v <= roura_water_bt;
roura_water_lenght_v <= last_water_lenght;
roura_water_v_offset <= to_unsigned(16, 10);
elsif (sig_typ_roury2 = "0010" AND ROURA_VODA1(0) = '1' AND ROURA_VODA1(5) = '1' AND (ZDROJ_VODY1 = "0110" OR ZDROJ_VODY1 = "1000")) then
roura_water_v <= roura_water_tb;
roura_water_lenght_v <= last_water_lenght;
roura_water_v_offset <= to_unsigned(16, 10);
elsif (sig_typ_roury2 = "0010" AND ROURA_VODA1(0) = '1' AND (ZDROJ_VODY1 = "1010" OR ZDROJ_VODY1 = "1001")) then
roura_water_v <= roura_water_bt;
roura_water_lenght_v <= first_water_lenght;
roura_water_v_offset <= to_unsigned(0, 10);
elsif (sig_typ_roury2 = "0010" AND ROURA_VODA1(0) = '1' AND (ZDROJ_VODY1 = "1011" OR ZDROJ_VODY1 = "1100")) then
roura_water_v <= roura_water_tb;
roura_water_lenght_v <= first_water_lenght;
roura_water_v_offset <= to_unsigned(0, 10);
else
roura_water_v <= '0';
roura_water_lenght_v <= roura_water_lenght_2;
roura_water_v_offset <= to_unsigned(0, 10);
end if;
end process;
----------------------------------------------------------------------------
-- RIZENI SIGNALU RBG
----------------------------------------------------------------------------
process (CLK)
begin
if (rising_edge(CLK)) then
-- bílé body v rozích obrazovky
if ((pix_x = 0 AND pix_y = 0) OR (pix_x = 0 AND pix_y = 478) OR
(pix_x = 638 AND pix_y = 0) OR (pix_x = 639 AND pix_y = 479)) then
white_point_is_reg <= '1';
else
white_point_is_reg <= '0';
end if;
end if;
end process;
water_is <= (load_water_on and GAME_ON) or -- voda nacitani
(roura_water_h and sq_cell_on and GAME_ON and not sig_komp_on) or -- voda roura nevertikalni
(roura_water_v and sq_cell_on and GAME_ON and not sig_komp_on); -- voda roura vertikalni
with sig_typ_roury2 select
game_field_text <= '1' when "0000",
'1' when "1001",
'1' when "1101",
'1' when "1110",
'1' when "1111",
'0' when others;
wall_is <= '1' when (sig_typ_roury2 = "1100") else '0';
kurzor_is <= sig_kurzor and not sig_komp_on;
process (CLK)
begin
if rising_edge(CLK) then
sq_cell_on_reg <= sq_cell_on;
rom_bit_reg <= rom_bit;
water_is_reg <= water_is;
game_field_text_reg <= game_field_text;
komp4_is_reg <= KOMP4_IS;
wall_is_reg <= wall_is;
kurzor_is_reg <= kurzor_is;
end if;
end process;
-- Nastaveni zobrazovane barvy
rbg_reg : process (CLK)
begin
if (rising_edge(CLK)) then
if (white_point_is_reg = '1') then -- bílé body v rozích obrazovky
RGB <= "111";
elsif (water_is_reg = '1') then -- vykreslování vody
RGB <= "011";
elsif (sq_cell_on_reg = '1' AND rom_bit_reg = '1') then
if (kurzor_is_reg = '1') then -- kurzor
RGB <= "101";
elsif (game_field_text_reg = '1') then -- herni pole a text
RGB <= "111";
elsif (wall_is_reg = '1') then -- zed
RGB <= "100";
elsif (komp4_is_reg = '1') then -- roura k vložení
RGB <= "010";
else -- jiné roury
RGB <= "001";
end if;
else -- černé pozadí
RGB <= "000";
end if;
end if;
end process;
end FULL;
|
mit
|
02c52339c70349546f6fbab5073563ff
| 0.494113 | 3.410736 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc519.vhd
| 4 | 32,609 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc519.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c03s03b00x00p03n01i00519pkg is
----------------------------------USING ONLY WHITE MATTER---------------------------------
------------------------------------------------------------------------------------------
---ACCESS TYPE FROM STANDARD PACKAGE
type boolean_ptr is access boolean ; --simple boolean type
type bit_ptr is access bit ; --simple bit type
type char_ptr is access character; --simple character type
type severity_level_ptr is access severity_level;--simple severity type
type integer_ptr is access integer; --simple integer type
type real_ptr is access real; --simple real type
type time_ptr is access time; --simple time type
type natural_ptr is access natural; --simple natural type
type positive_ptr is access positive; --simple positive type
type string_ptr is access string; --simple string type
type bit_vector_ptr is access bit_vector; --simple bit_vector type
------------------------------------------------------------------------------------------
--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
-------------------------------------------------------------------------------------------
--CONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
subtype boolean_vector_st is boolean_vector(0 to 15);
subtype severity_level_vector_st is severity_level_vector(0 to 15);
subtype integer_vector_st is integer_vector(0 to 15);
subtype real_vector_st is real_vector(0 to 15);
subtype time_vector_st is time_vector(0 to 15);
subtype natural_vector_st is natural_vector(0 to 15);
subtype positive_vector_st is positive_vector(0 to 15);
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------
--CONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type boolean_cons_vector is array (15 downto 0) of boolean;
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type integer_cons_vector is array (15 downto 0) of integer;
type real_cons_vector is array (15 downto 0) of real;
type time_cons_vector is array (15 downto 0) of time;
type natural_cons_vector is array (15 downto 0) of natural;
type positive_cons_vector is array (15 downto 0) of positive;
-------------------------------------------------------------------------------------------
--CONSTRAINED ARRAY OF ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type boolean_cons_vectorofvector is array (0 to 15) of boolean_cons_vector;
type severity_level_cons_vectorofvector is array (0 to 15) of severity_level_cons_vector;
type integer_cons_vectorofvector is array (0 to 15) of integer_cons_vector ;
type real_cons_vectorofvector is array (0 to 15) of real_cons_vector;
type time_cons_vectorofvector is array (0 to 15) of time_cons_vector;
type natural_cons_vectorofvector is array (0 to 15) of natural_cons_vector;
type positive_cons_vectorofvector is array (0 to 15) of positive_cons_vector;
-------------------------------------------------------------------------------------------
--UNCONSTRAINED 2-DIMENSIONAL ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type s2boolean_vector is array (natural range <>,natural range <>) of boolean;
type s2bit_vector is array (natural range <>,natural range <>) of bit;
type s2char_vector is array (natural range <>,natural range <>) of character;
type s2severity_level_vector is array (natural range <>,natural range <>) of severity_level;
type s2integer_vector is array (natural range <>,natural range <>) of integer;
type s2real_vector is array (natural range <>,natural range <>) of real;
type s2time_vector is array (natural range <>,natural range <>) of time;
type s2natural_vector is array (natural range <>,natural range <>) of natural;
type s2positive_vector is array (natural range <>,natural range <>) of positive;
-------------------------------------------------------------------------------------------
--CONSTRAINED 2-DIMENSIONAL ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type column is range 1 to 64;
type row is range 1 to 1024;
type s2boolean_cons_vector is array (row,column) of boolean;
type s2bit_cons_vector is array (row,column) of bit;
type s2char_cons_vector is array (row,column) of character;
type s2severity_level_cons_vector is array (row,column) of severity_level;
type s2integer_cons_vector is array (row,column) of integer;
type s2real_cons_vector is array (row,column) of real;
type s2time_cons_vector is array (row,column) of time;
type s2natural_cons_vector is array (row,column) of natural;
type s2positive_cons_vector is array (row,column) of positive;
-------------------------------------------------------------------------------------------
--RECORD WITH FIELDS FROM STANDARD PACKAGE
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
-------------------------------------------------------------------------------------------
--RECORD WITH FIELDS AS CONSTRAINT ARRAYS
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
-------------------------------------------------------------------------------------------
--RECORD WITH FIELDS AS CONSTRAINT ARRAYS
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
-------------------------------------------------------------------------------------------
--RECORD WITH FIELDS AS 2-DIMENSIONAL CONSTRAINED ARRAYS
type record_2cons_array is record
a:s2boolean_cons_vector;
b:s2bit_cons_vector;
c:s2char_cons_vector;
d:s2severity_level_cons_vector;
e:s2integer_cons_vector;
f:s2real_cons_vector;
g:s2time_cons_vector;
h:s2natural_cons_vector;
i:s2positive_cons_vector;
end record;
-------------------------------------------------------------------------------------------
--RECORD WITH FIELDS AS 2-DIMENSIONAL CONSTRAINED ARRAYS OF ARRAY
type record_cons_arrayofarray is record
a:boolean_cons_vectorofvector;
b:severity_level_cons_vectorofvector;
c:integer_cons_vectorofvector;
d:real_cons_vectorofvector;
e:time_cons_vectorofvector;
f:natural_cons_vectorofvector;
g:positive_cons_vectorofvector;
end record;
--------------------------------------------------------------------------------------------
type record_of_ptr is record
a:boolean_ptr ; --simple boolean type
b:bit_ptr; --simple bit type
c:char_ptr; --simple character type
e:severity_level_ptr; --simple severity type
f:integer_ptr; --simple integer type
g:real_ptr ; --simple real type
h:time_ptr; --simple time type
i:natural_ptr; --simple natural type
j:positive_ptr; --simple positive type
k:string_ptr; --simple string type
l:bit_vector_ptr; --simple bit_vector type
end record;
--------------------------------------------------------------------------------------------
type record_of_records is record
a: record_std_package;
c: record_cons_array;
e: record_2cons_array;
g: record_cons_arrayofarray;
h: record_of_ptr;
i: record_array_st;
end record;
--------------------------------------------------------------------------------------------
--ACCESS TYPES FOR ABOVE
--------------------------------------------------------------------------------------------
type boolean_vector_ptr is access boolean_vector;
type severity_level_vector_ptr is access severity_level_vector;
type integer_vector_ptr is access integer_vector;
type real_vector_ptr is access real_vector;
type time_vector_ptr is access time_vector;
type natural_vector_ptr is access natural_vector;
type positive_vector_ptr is access positive_vector;
--------------------------------------------------------------------------------------------
type boolean_cons_vector_ptr is access boolean_cons_vector;
type severity_level_cons_vector_ptr is access severity_level_cons_vector;
type integer_cons_vector_ptr is access integer_cons_vector;
type real_cons_vector_ptr is access real_cons_vector;
type time_cons_vector_ptr is access time_cons_vector;
type natural_cons_vector_ptr is access natural_cons_vector;
type positive_cons_vector_ptr is access positive_cons_vector;
--------------------------------------------------------------------------------------------
type boolean_cons_vectorofvector_ptr is access boolean_cons_vectorofvector;
type sev_lvl_cons_vecofvec_ptr is access severity_level_cons_vectorofvector;
type integer_cons_vectorofvector_ptr is access integer_cons_vectorofvector;
type real_cons_vectorofvector_ptr is access real_cons_vectorofvector;
type time_cons_vectorofvector_ptr is access time_cons_vectorofvector;
type natural_cons_vectorofvector_ptr is access natural_cons_vectorofvector;
type posi_cons_vecofvec_ptr is access positive_cons_vectorofvector;
--------------------------------------------------------------------------------------------
type s2boolean_vector_ptr is access boolean_vector;
type s2bit_vector_ptr is access s2bit_vector;
type s2char_vector_ptr is access s2char_vector;
type s2severity_level_vector_ptr is access s2severity_level_vector;
type s2integer_vector_ptr is access s2integer_vector;
type s2real_vector_ptr is access s2real_vector;
type s2time_vector_ptr is access s2time_vector;
type s2positive_vector_ptr is access s2positive_vector;
--------------------------------------------------------------------------------------------
type s2boolean_cons_vector_ptr is access s2boolean_cons_vector;
type s2bit_cons_vector_ptr is access s2bit_cons_vector;
type s2char_cons_vector_ptr is access s2char_cons_vector;
type s2sev_lvl_cons_vec_ptr is access s2severity_level_cons_vector;
type s2integer_cons_vector_ptr is access s2integer_cons_vector;
type s2real_cons_vector_ptr is access s2real_cons_vector;
type s2time_cons_vector_ptr is access s2time_cons_vector;
type s2natural_cons_vector_ptr is access natural_cons_vector;
type s2positive_cons_vector_ptr is access s2positive_cons_vector;
--------------------------------------------------------------------------------------------
type record_std_package_ptr is access record_std_package;
type record_cons_array_ptr is access record_cons_array;
type record_2cons_array_ptr is access record_2cons_array;
type record_cons_arrayofarray_ptr is access record_cons_arrayofarray;
type record_of_ptr_ptr is access record_of_ptr;
type record_of_records_ptr is access record_of_records;
--------------------------------------------------------------------------------------------
--------------------USING PARTIAL GRAY & PARTIAL WHITE MATTER-------------------------------
type four_value is ('Z','0','1','X'); --enumerated type
type four_value_map is array(four_value) of boolean;
subtype binary is four_value range '0' to '1';
type four_value_vector is array (natural range <>) of four_value; --unconstraint array of
type byte is array(0 to 7) of bit;
subtype word is bit_vector(0 to 15); --constrained array
function resolution(i:in four_value_vector) return four_value; --bus resolution
subtype four_value_state is resolution four_value; --function type
type state_vector is array (natural range <>) of four_value_state; --unconstraint array of
constant size :integer := 63;
type primary_memory is array(0 to size) of word; --array of an array
type primary_memory_module is --record with field
record --as an array
enable:binary;
memory_number:primary_memory;
end record;
type whole_memory is array(0 to size) of primary_memory_module; --array of a complex record
type current is range -2147483647 to +2147483647
units
nA;
uA = 1000 nA;
mA = 1000 uA;
A = 1000 mA;
end units;
type resistance is range -2147483647 to +2147483647
units
uOhm;
mOhm = 1000 uOhm;
Ohm = 1000 mOhm;
KOhm = 1000 Ohm;
end units;
subtype delay is integer range 1 to 10;
type four_value_ptr is access four_value;
type four_value_map_ptr is access four_value_map;
type binary_ptr is access binary;
type four_value_vector_ptr is access four_value_vector; --ennumerated type
type byte_ptr is access byte;
type word_ptr is access word;
type four_value_state_ptr is access four_value_state;
type state_vector_ptr is access state_vector; --type returned by resolu.
type primary_memory_ptr is access primary_memory;
type whole_memory_ptr is access whole_memory;
type current_ptr is access current;
type resistance_ptr is access resistance;
type delay_ptr is access delay;
-----------------------------------------------------------------------------------------
end c03s03b00x00p03n01i00519pkg;
package body c03s03b00x00p03n01i00519pkg is
function resolution(i:in four_value_vector) return four_value is
variable temp :four_value := 'Z';
begin
return temp;
end;
end c03s03b00x00p03n01i00519pkg;
use work.c03s03b00x00p03n01i00519pkg.all;
ENTITY c03s03b00x00p03n01i00519ent IS
END c03s03b00x00p03n01i00519ent;
ARCHITECTURE c03s03b00x00p03n01i00519arch OF c03s03b00x00p03n01i00519ent IS
BEGIN
TESTING: PROCESS
variable var1 : boolean_ptr ;
variable var2 : bit_ptr ;
variable var3 : char_ptr ;
variable var4 : severity_level_ptr ;
variable var5 : integer_ptr ;
variable var6 : real_ptr ;
variable var7 : time_ptr ;
variable var8 : natural_ptr ;
variable var9 : positive_ptr ;
variable var10 : string_ptr ;
variable var11 : bit_vector_ptr ;
variable var12 : boolean_vector_ptr ;
variable var13 : severity_level_vector_ptr ;
variable var14 : integer_vector_ptr ;
variable var15 : real_vector_ptr ;
variable var16 : time_vector_ptr ;
variable var17 : natural_vector_ptr ;
variable var18 : positive_vector_ptr ;
variable var19 : boolean_cons_vector_ptr ;
variable var20 : severity_level_cons_vector_ptr ;
variable var21 : integer_cons_vector_ptr ;
variable var22 : real_cons_vector_ptr ;
variable var23 : time_cons_vector_ptr ;
variable var24 : natural_cons_vector_ptr ;
variable var25 : positive_cons_vector_ptr ;
variable var26 : boolean_cons_vectorofvector_ptr ;
variable var27 : sev_lvl_cons_vecofvec_ptr ;
variable var28 : integer_cons_vectorofvector_ptr ;
variable var29 : real_cons_vectorofvector_ptr ;
variable var30 : time_cons_vectorofvector_ptr ;
variable var31 : natural_cons_vectorofvector_ptr ;
variable var32 : posi_cons_vecofvec_ptr ;
variable var33 : s2boolean_vector_ptr ;
variable var34 : s2bit_vector_ptr ;
variable var35 : s2char_vector_ptr ;
variable var36 : s2severity_level_vector_ptr ;
variable var37 : s2integer_vector_ptr ;
variable var38 : s2real_vector_ptr ;
variable var39 : s2time_vector_ptr ;
variable var40 : s2positive_vector_ptr ;
variable var41 : s2boolean_cons_vector_ptr ;
variable var42 : s2bit_cons_vector_ptr ;
variable var43 : s2char_cons_vector_ptr ;
variable var44 : s2sev_lvl_cons_vec_ptr ;
variable var45 : s2integer_cons_vector_ptr ;
variable var46 : s2real_cons_vector_ptr ;
variable var47 : s2time_cons_vector_ptr ;
variable var48 : s2natural_cons_vector_ptr ;
variable var49 : s2positive_cons_vector_ptr ;
variable var50 : record_std_package_ptr ;
variable var51 : record_cons_array_ptr ;
variable var52 : record_2cons_array_ptr ;
variable var53 : record_cons_arrayofarray_ptr ;
variable var54 : record_of_ptr_ptr ;
variable var55 : record_of_records_ptr ;
variable var56 : four_value_ptr ;
variable var57 : four_value_map_ptr ;
variable var58 : binary_ptr ;
variable var59 : four_value_vector_ptr ;
variable var60 : byte_ptr ;
variable var61 : word_ptr ;
variable var62 : four_value_state_ptr ;
variable var63 : state_vector_ptr ;
variable var64 : primary_memory_ptr ;
variable var65 : whole_memory_ptr ;
variable var66 : current_ptr ;
variable var67 : resistance_ptr ;
variable var68 : delay_ptr ;
BEGIN
assert (var1 = null)
report "var1 has not been set to null." severity FAILURE ;
assert (var2 = null)
report "var2 has not been set to null." severity FAILURE ;
assert (var3 = null)
report "var3 has not been set to null." severity FAILURE ;
assert (var4 = null)
report "var4 has not been set to null." severity FAILURE ;
assert (var5 = null)
report "var5 has not been set to null." severity FAILURE ;
assert (var6 = null)
report "var6 has not been set to null." severity FAILURE ;
assert (var7 = null)
report "var7 has not been set to null." severity FAILURE ;
assert (var8 = null)
report "var8 has not been set to null." severity FAILURE ;
assert (var9 = null)
report "var9 has not been set to null." severity FAILURE ;
assert (var10 = null)
report "var10 has not been set to null." severity FAILURE ;
assert (var11 = null)
report "var11 has not been set to null." severity FAILURE ;
assert (var12 = null)
report "var12 has not been set to null." severity FAILURE ;
assert (var13 = null)
report "var13 has not been set to null." severity FAILURE ;
assert (var14 = null)
report "var14 has not been set to null." severity FAILURE ;
assert (var15 = null)
report "var15 has not been set to null." severity FAILURE ;
assert (var16 = null)
report "var16 has not been set to null." severity FAILURE ;
assert (var17 = null)
report "var17 has not been set to null." severity FAILURE ;
assert (var18 = null)
report "var18 has not been set to null." severity FAILURE ;
assert (var19 = null)
report "var19 has not been set to null." severity FAILURE ;
assert (var20 = null)
report "var20 has not been set to null." severity FAILURE ;
assert (var21 = null)
report "var21 has not been set to null." severity FAILURE ;
assert (var22 = null)
report "var22 has not been set to null." severity FAILURE ;
assert (var23 = null)
report "var23 has not been set to null." severity FAILURE ;
assert (var24 = null)
report "var24 has not been set to null." severity FAILURE ;
assert (var25 = null)
report "var25 has not been set to null." severity FAILURE ;
assert (var26 = null)
report "var26 has not been set to null." severity FAILURE ;
assert (var27 = null)
report "var27 has not been set to null." severity FAILURE ;
assert (var28 = null)
report "var28 has not been set to null." severity FAILURE ;
assert (var29 = null)
report "var29 has not been set to null." severity FAILURE ;
assert (var30 = null)
report "var30 has not been set to null." severity FAILURE ;
assert (var31 = null)
report "var31 has not been set to null." severity FAILURE ;
assert (var32 = null)
report "var32 has not been set to null." severity FAILURE ;
assert (var33 = null)
report "var33 has not been set to null." severity FAILURE ;
assert (var34 = null)
report "var34 has not been set to null." severity FAILURE ;
assert (var35 = null)
report "var35 has not been set to null." severity FAILURE ;
assert (var36 = null)
report "var36 has not been set to null." severity FAILURE ;
assert (var37 = null)
report "var37 has not been set to null." severity FAILURE ;
assert (var38 = null)
report "var38 has not been set to null." severity FAILURE ;
assert (var39 = null)
report "var39 has not been set to null." severity FAILURE ;
assert (var40 = null)
report "var40 has not been set to null." severity FAILURE ;
assert (var41 = null)
report "var41 has not been set to null." severity FAILURE ;
assert (var42 = null)
report "var42 has not been set to null." severity FAILURE ;
assert (var43 = null)
report "var43 has not been set to null." severity FAILURE ;
assert (var44 = null)
report "var44 has not been set to null." severity FAILURE ;
assert (var45 = null)
report "var45 has not been set to null." severity FAILURE ;
assert (var46 = null)
report "var46 has not been set to null." severity FAILURE ;
assert (var47 = null)
report "var47 has not been set to null." severity FAILURE ;
assert (var48 = null)
report "var48 has not been set to null." severity FAILURE ;
assert (var49 = null)
report "var49 has not been set to null." severity FAILURE ;
assert (var50 = null)
report "var50 has not been set to null." severity FAILURE ;
assert (var51 = null)
report "var51 has not been set to null." severity FAILURE ;
assert (var52 = null)
report "var52 has not been set to null." severity FAILURE ;
assert (var53 = null)
report "var53 has not been set to null." severity FAILURE ;
assert (var54 = null)
report "var54 has not been set to null." severity FAILURE ;
assert (var55 = null)
report "var55 has not been set to null." severity FAILURE ;
assert (var56 = null)
report "var56 has not been set to null." severity FAILURE ;
assert (var57 = null)
report "var57 has not been set to null." severity FAILURE ;
assert (var58 = null)
report "var58 has not been set to null." severity FAILURE ;
assert (var59 = null)
report "var59 has not been set to null." severity FAILURE ;
assert (var60 = null)
report "var60 has not been set to null." severity FAILURE ;
assert (var61 = null)
report "var61 has not been set to null." severity FAILURE ;
assert (var62 = null)
report "var62 has not been set to null." severity FAILURE ;
assert (var63 = null)
report "var63 has not been set to null." severity FAILURE ;
assert (var64 = null)
report "var64 has not been set to null." severity FAILURE ;
assert (var65 = null)
report "var65 has not been set to null." severity FAILURE ;
assert (var66 = null)
report "var66 has not been set to null." severity FAILURE ;
assert (var67 = null)
report "var67 has not been set to null." severity FAILURE ;
assert (var68 = null)
report "var68 has not been set to null." severity FAILURE ;
assert NOT((var1 = null)
and (var2 = null)
and (var3 = null)
and (var4 = null)
and (var5 = null)
and (var6 = null)
and (var7 = null)
and (var8 = null)
and (var9 = null)
and (var10 = null)
and (var11 = null)
and (var12 = null)
and (var13 = null)
and (var14 = null)
and (var15 = null)
and (var16 = null)
and (var17 = null)
and (var18 = null)
and (var19 = null)
and (var20 = null)
and (var21 = null)
and (var22 = null)
and (var23 = null)
and (var24 = null)
and (var25 = null)
and (var26 = null)
and (var27 = null)
and (var28 = null)
and (var29 = null)
and (var30 = null)
and (var31 = null)
and (var32 = null)
and (var33 = null)
and (var34 = null)
and (var35 = null)
and (var36 = null)
and (var37 = null)
and (var38 = null)
and (var39 = null)
and (var40 = null)
and (var41 = null)
and (var42 = null)
and (var43 = null)
and (var44 = null)
and (var45 = null)
and (var46 = null)
and (var47 = null)
and (var48 = null)
and (var49 = null)
and (var50 = null)
and (var51 = null)
and (var52 = null)
and (var53 = null)
and (var54 = null)
and (var55 = null)
and (var56 = null)
and (var57 = null)
and (var58 = null)
and (var59 = null)
and (var60 = null)
and (var61 = null)
and (var62 = null)
and (var63 = null)
and (var64 = null)
and (var65 = null)
and (var66 = null)
and (var67 = null)
and (var68 = null))
report "***PASSED TEST: c03s03b00x00p03n01i00519"
severity NOTE;
assert ((var1 = null)
and (var2 = null)
and (var3 = null)
and (var4 = null)
and (var5 = null)
and (var6 = null)
and (var7 = null)
and (var8 = null)
and (var9 = null)
and (var10 = null)
and (var11 = null)
and (var12 = null)
and (var13 = null)
and (var14 = null)
and (var15 = null)
and (var16 = null)
and (var17 = null)
and (var18 = null)
and (var19 = null)
and (var20 = null)
and (var21 = null)
and (var22 = null)
and (var23 = null)
and (var24 = null)
and (var25 = null)
and (var26 = null)
and (var27 = null)
and (var28 = null)
and (var29 = null)
and (var30 = null)
and (var31 = null)
and (var32 = null)
and (var33 = null)
and (var34 = null)
and (var35 = null)
and (var36 = null)
and (var37 = null)
and (var38 = null)
and (var39 = null)
and (var40 = null)
and (var41 = null)
and (var42 = null)
and (var43 = null)
and (var44 = null)
and (var45 = null)
and (var46 = null)
and (var47 = null)
and (var48 = null)
and (var49 = null)
and (var50 = null)
and (var51 = null)
and (var52 = null)
and (var53 = null)
and (var54 = null)
and (var55 = null)
and (var56 = null)
and (var57 = null)
and (var58 = null)
and (var59 = null)
and (var60 = null)
and (var61 = null)
and (var62 = null)
and (var63 = null)
and (var64 = null)
and (var65 = null)
and (var66 = null)
and (var67 = null)
and (var68 = null))
report "***FAILED TEST: c03s03b00x00p03n01i00519 - The null value of an access type is the default initial value of the type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p03n01i00519arch;
|
gpl-2.0
|
233e39756b2368251777245ab08b9bf8
| 0.534822 | 4.425159 | false | false | false | false |
peteut/ghdl
|
libraries/ieee/math_real.vhdl
| 4 | 24,661 |
------------------------------------------------------------------------
--
-- Copyright 1996 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076.2-1996, IEEE Standard
-- VHDL Mathematical Packages. This source file may not be copied, sold, or
-- included with software that is sold without written permission from the IEEE
-- Standards Department. This source file may be used to implement this standard
-- and may be distributed in compiled form in any manner so long as the
-- compiled form does not allow direct decompilation of the original source file.
-- This source file may be copied for individual use between licensed users.
-- This source file is provided on an AS IS basis. The IEEE disclaims ANY
-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY
-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source
-- file shall indemnify and hold IEEE harmless from any damages or liability
-- arising out of the use thereof.
--
-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996,
-- MATH_REAL)
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
--
-- Purpose: This package defines a standard for designers to use in
-- describing VHDL models that make use of common REAL constants
-- and common REAL elementary mathematical functions.
--
-- Limitation: The values generated by the functions in this package may
-- vary from platform to platform, and the precision of results
-- is only guaranteed to be the minimum required by IEEE Std 1076-
-- 1993.
--
-- Notes:
-- No declarations or definitions shall be included in, or
-- excluded from, this package.
-- The "package declaration" defines the types, subtypes, and
-- declarations of MATH_REAL.
-- The standard mathematical definition and conventional meaning
-- of the mathematical functions that are part of this standard
-- represent the formal semantics of the implementation of the
-- MATH_REAL package declaration. The purpose of the MATH_REAL
-- package body is to provide a guideline for implementations to
-- verify their implementation of MATH_REAL. Tool developers may
-- choose to implement the package body in the most efficient
-- manner available to them.
--
-- -----------------------------------------------------------------------------
-- Version : 1.5
-- Date : 24 July 1996
-- -----------------------------------------------------------------------------
package MATH_REAL is
constant CopyRightNotice: STRING
:= "Copyright 1996 IEEE. All rights reserved.";
--
-- Constant Definitions
--
constant MATH_E : REAL := 2.71828_18284_59045_23536;
-- Value of e
constant MATH_1_OVER_E : REAL := 0.36787_94411_71442_32160;
-- Value of 1/e
constant MATH_PI : REAL := 3.14159_26535_89793_23846;
-- Value of pi
constant MATH_2_PI : REAL := 6.28318_53071_79586_47693;
-- Value of 2*pi
constant MATH_1_OVER_PI : REAL := 0.31830_98861_83790_67154;
-- Value of 1/pi
constant MATH_PI_OVER_2 : REAL := 1.57079_63267_94896_61923;
-- Value of pi/2
constant MATH_PI_OVER_3 : REAL := 1.04719_75511_96597_74615;
-- Value of pi/3
constant MATH_PI_OVER_4 : REAL := 0.78539_81633_97448_30962;
-- Value of pi/4
constant MATH_3_PI_OVER_2 : REAL := 4.71238_89803_84689_85769;
-- Value 3*pi/2
constant MATH_LOG_OF_2 : REAL := 0.69314_71805_59945_30942;
-- Natural log of 2
constant MATH_LOG_OF_10 : REAL := 2.30258_50929_94045_68402;
-- Natural log of 10
constant MATH_LOG2_OF_E : REAL := 1.44269_50408_88963_4074;
-- Log base 2 of e
constant MATH_LOG10_OF_E: REAL := 0.43429_44819_03251_82765;
-- Log base 10 of e
constant MATH_SQRT_2: REAL := 1.41421_35623_73095_04880;
-- square root of 2
constant MATH_1_OVER_SQRT_2: REAL := 0.70710_67811_86547_52440;
-- square root of 1/2
constant MATH_SQRT_PI: REAL := 1.77245_38509_05516_02730;
-- square root of pi
constant MATH_DEG_TO_RAD: REAL := 0.01745_32925_19943_29577;
-- Conversion factor from degree to radian
constant MATH_RAD_TO_DEG: REAL := 57.29577_95130_82320_87680;
-- Conversion factor from radian to degree
--
-- Function Declarations
--
function SIGN (X: in REAL ) return REAL;
-- Purpose:
-- Returns 1.0 if X > 0.0; 0.0 if X = 0.0; -1.0 if X < 0.0
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(SIGN(X)) <= 1.0
-- Notes:
-- None
function CEIL (X : in REAL ) return REAL;
-- Purpose:
-- Returns smallest INTEGER value (as REAL) not less than X
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- CEIL(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function FLOOR (X : in REAL ) return REAL;
-- Purpose:
-- Returns largest INTEGER value (as REAL) not greater than X
-- Special values:
-- FLOOR(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- FLOOR(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function ROUND (X : in REAL ) return REAL;
-- Purpose:
-- Rounds X to the nearest integer value (as real). If X is
-- halfway between two integers, rounding is away from 0.0
-- Special values:
-- ROUND(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ROUND(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function TRUNC (X : in REAL ) return REAL;
-- Purpose:
-- Truncates X towards 0.0 and returns truncated value
-- Special values:
-- TRUNC(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- TRUNC(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function "MOD" (X, Y: in REAL ) return REAL;
-- Purpose:
-- Returns floating point modulus of X/Y, with the same sign as
-- Y, and absolute value less than the absolute value of Y, and
-- for some INTEGER value N the result satisfies the relation
-- X = Y*N + MOD(X,Y)
-- Special values:
-- None
-- Domain:
-- X in REAL; Y in REAL and Y /= 0.0
-- Error conditions:
-- Error if Y = 0.0
-- Range:
-- ABS(MOD(X,Y)) < ABS(Y)
-- Notes:
-- None
function REALMAX (X, Y : in REAL ) return REAL;
-- Purpose:
-- Returns the algebraically larger of X and Y
-- Special values:
-- REALMAX(X,Y) = X when X = Y
-- Domain:
-- X in REAL; Y in REAL
-- Error conditions:
-- None
-- Range:
-- REALMAX(X,Y) is mathematically unbounded
-- Notes:
-- None
function REALMIN (X, Y : in REAL ) return REAL;
-- Purpose:
-- Returns the algebraically smaller of X and Y
-- Special values:
-- REALMIN(X,Y) = X when X = Y
-- Domain:
-- X in REAL; Y in REAL
-- Error conditions:
-- None
-- Range:
-- REALMIN(X,Y) is mathematically unbounded
-- Notes:
-- None
procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE; variable X:out REAL);
-- Purpose:
-- Returns, in X, a pseudo-random number with uniform
-- distribution in the open interval (0.0, 1.0).
-- Special values:
-- None
-- Domain:
-- 1 <= SEED1 <= 2147483562; 1 <= SEED2 <= 2147483398
-- Error conditions:
-- Error if SEED1 or SEED2 outside of valid domain
-- Range:
-- 0.0 < X < 1.0
-- Notes:
-- a) The semantics for this function are described by the
-- algorithm published by Pierre L'Ecuyer in "Communications
-- of the ACM," vol. 31, no. 6, June 1988, pp. 742-774.
-- The algorithm is based on the combination of two
-- multiplicative linear congruential generators for 32-bit
-- platforms.
--
-- b) Before the first call to UNIFORM, the seed values
-- (SEED1, SEED2) have to be initialized to values in the range
-- [1, 2147483562] and [1, 2147483398] respectively. The
-- seed values are modified after each call to UNIFORM.
--
-- c) This random number generator is portable for 32-bit
-- computers, and it has a period of ~2.30584*(10**18) for each
-- set of seed values.
--
-- d) For information on spectral tests for the algorithm, refer
-- to the L'Ecuyer article.
function SQRT (X : in REAL ) return REAL;
-- Purpose:
-- Returns square root of X
-- Special values:
-- SQRT(0.0) = 0.0
-- SQRT(1.0) = 1.0
-- Domain:
-- X >= 0.0
-- Error conditions:
-- Error if X < 0.0
-- Range:
-- SQRT(X) >= 0.0
-- Notes:
-- a) The upper bound of the reachable range of SQRT is
-- approximately given by:
-- SQRT(X) <= SQRT(REAL'HIGH)
function CBRT (X : in REAL ) return REAL;
-- Purpose:
-- Returns cube root of X
-- Special values:
-- CBRT(0.0) = 0.0
-- CBRT(1.0) = 1.0
-- CBRT(-1.0) = -1.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- CBRT(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of CBRT is approximately given by:
-- ABS(CBRT(X)) <= CBRT(REAL'HIGH)
function "**" (X : in INTEGER; Y : in REAL) return REAL;
-- Purpose:
-- Returns Y power of X ==> X**Y
-- Special values:
-- X**0.0 = 1.0; X /= 0
-- 0**Y = 0.0; Y > 0.0
-- X**1.0 = REAL(X); X >= 0
-- 1**Y = 1.0
-- Domain:
-- X > 0
-- X = 0 for Y > 0.0
-- X < 0 for Y = 0.0
-- Error conditions:
-- Error if X < 0 and Y /= 0.0
-- Error if X = 0 and Y <= 0.0
-- Range:
-- X**Y >= 0.0
-- Notes:
-- a) The upper bound of the reachable range for "**" is
-- approximately given by:
-- X**Y <= REAL'HIGH
function "**" (X : in REAL; Y : in REAL) return REAL;
-- Purpose:
-- Returns Y power of X ==> X**Y
-- Special values:
-- X**0.0 = 1.0; X /= 0.0
-- 0.0**Y = 0.0; Y > 0.0
-- X**1.0 = X; X >= 0.0
-- 1.0**Y = 1.0
-- Domain:
-- X > 0.0
-- X = 0.0 for Y > 0.0
-- X < 0.0 for Y = 0.0
-- Error conditions:
-- Error if X < 0.0 and Y /= 0.0
-- Error if X = 0.0 and Y <= 0.0
-- Range:
-- X**Y >= 0.0
-- Notes:
-- a) The upper bound of the reachable range for "**" is
-- approximately given by:
-- X**Y <= REAL'HIGH
function EXP (X : in REAL ) return REAL;
-- Purpose:
-- Returns e**X; where e = MATH_E
-- Special values:
-- EXP(0.0) = 1.0
-- EXP(1.0) = MATH_E
-- EXP(-1.0) = MATH_1_OVER_E
-- EXP(X) = 0.0 for X <= -LOG(REAL'HIGH)
-- Domain:
-- X in REAL such that EXP(X) <= REAL'HIGH
-- Error conditions:
-- Error if X > LOG(REAL'HIGH)
-- Range:
-- EXP(X) >= 0.0
-- Notes:
-- a) The usable domain of EXP is approximately given by:
-- X <= LOG(REAL'HIGH)
function LOG (X : in REAL ) return REAL;
-- Purpose:
-- Returns natural logarithm of X
-- Special values:
-- LOG(1.0) = 0.0
-- LOG(MATH_E) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG is approximately given by:
-- LOG(0+) <= LOG(X) <= LOG(REAL'HIGH)
function LOG2 (X : in REAL ) return REAL;
-- Purpose:
-- Returns logarithm base 2 of X
-- Special values:
-- LOG2(1.0) = 0.0
-- LOG2(2.0) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG2(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG2 is approximately given by:
-- LOG2(0+) <= LOG2(X) <= LOG2(REAL'HIGH)
function LOG10 (X : in REAL ) return REAL;
-- Purpose:
-- Returns logarithm base 10 of X
-- Special values:
-- LOG10(1.0) = 0.0
-- LOG10(10.0) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG10(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG10 is approximately given by:
-- LOG10(0+) <= LOG10(X) <= LOG10(REAL'HIGH)
function LOG (X: in REAL; BASE: in REAL) return REAL;
-- Purpose:
-- Returns logarithm base BASE of X
-- Special values:
-- LOG(1.0, BASE) = 0.0
-- LOG(BASE, BASE) = 1.0
-- Domain:
-- X > 0.0
-- BASE > 0.0
-- BASE /= 1.0
-- Error conditions:
-- Error if X <= 0.0
-- Error if BASE <= 0.0
-- Error if BASE = 1.0
-- Range:
-- LOG(X, BASE) is mathematically unbounded
-- Notes:
-- a) When BASE > 1.0, the reachable range of LOG is
-- approximately given by:
-- LOG(0+, BASE) <= LOG(X, BASE) <= LOG(REAL'HIGH, BASE)
-- b) When 0.0 < BASE < 1.0, the reachable range of LOG is
-- approximately given by:
-- LOG(REAL'HIGH, BASE) <= LOG(X, BASE) <= LOG(0+, BASE)
function SIN (X : in REAL ) return REAL;
-- Purpose:
-- Returns sine of X; X in radians
-- Special values:
-- SIN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
-- SIN(X) = 1.0 for X = (4*k+1)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- SIN(X) = -1.0 for X = (4*k+3)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(SIN(X)) <= 1.0
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function COS ( X : in REAL ) return REAL;
-- Purpose:
-- Returns cosine of X; X in radians
-- Special values:
-- COS(X) = 0.0 for X = (2*k+1)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- COS(X) = 1.0 for X = (2*k)*MATH_PI, where k is an INTEGER
-- COS(X) = -1.0 for X = (2*k+1)*MATH_PI, where k is an INTEGER
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(COS(X)) <= 1.0
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function TAN (X : in REAL ) return REAL;
-- Purpose:
-- Returns tangent of X; X in radians
-- Special values:
-- TAN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
-- Domain:
-- X in REAL and
-- X /= (2*k+1)*MATH_PI_OVER_2, where k is an INTEGER
-- Error conditions:
-- Error if X = ((2*k+1) * MATH_PI_OVER_2), where k is an
-- INTEGER
-- Range:
-- TAN(X) is mathematically unbounded
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function ARCSIN (X : in REAL ) return REAL;
-- Purpose:
-- Returns inverse sine of X
-- Special values:
-- ARCSIN(0.0) = 0.0
-- ARCSIN(1.0) = MATH_PI_OVER_2
-- ARCSIN(-1.0) = -MATH_PI_OVER_2
-- Domain:
-- ABS(X) <= 1.0
-- Error conditions:
-- Error if ABS(X) > 1.0
-- Range:
-- ABS(ARCSIN(X) <= MATH_PI_OVER_2
-- Notes:
-- None
function ARCCOS (X : in REAL ) return REAL;
-- Purpose:
-- Returns inverse cosine of X
-- Special values:
-- ARCCOS(1.0) = 0.0
-- ARCCOS(0.0) = MATH_PI_OVER_2
-- ARCCOS(-1.0) = MATH_PI
-- Domain:
-- ABS(X) <= 1.0
-- Error conditions:
-- Error if ABS(X) > 1.0
-- Range:
-- 0.0 <= ARCCOS(X) <= MATH_PI
-- Notes:
-- None
function ARCTAN (Y : in REAL) return REAL;
-- Purpose:
-- Returns the value of the angle in radians of the point
-- (1.0, Y), which is in rectangular coordinates
-- Special values:
-- ARCTAN(0.0) = 0.0
-- Domain:
-- Y in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(ARCTAN(Y)) <= MATH_PI_OVER_2
-- Notes:
-- None
function ARCTAN (Y : in REAL; X : in REAL) return REAL;
-- Purpose:
-- Returns the principal value of the angle in radians of
-- the point (X, Y), which is in rectangular coordinates
-- Special values:
-- ARCTAN(0.0, X) = 0.0 if X > 0.0
-- ARCTAN(0.0, X) = MATH_PI if X < 0.0
-- ARCTAN(Y, 0.0) = MATH_PI_OVER_2 if Y > 0.0
-- ARCTAN(Y, 0.0) = -MATH_PI_OVER_2 if Y < 0.0
-- Domain:
-- Y in REAL
-- X in REAL, X /= 0.0 when Y = 0.0
-- Error conditions:
-- Error if X = 0.0 and Y = 0.0
-- Range:
-- -MATH_PI < ARCTAN(Y,X) <= MATH_PI
-- Notes:
-- None
function SINH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic sine of X
-- Special values:
-- SINH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- SINH(X) is mathematically unbounded
-- Notes:
-- a) The usable domain of SINH is approximately given by:
-- ABS(X) <= LOG(REAL'HIGH)
function COSH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic cosine of X
-- Special values:
-- COSH(0.0) = 1.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- COSH(X) >= 1.0
-- Notes:
-- a) The usable domain of COSH is approximately given by:
-- ABS(X) <= LOG(REAL'HIGH)
function TANH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic tangent of X
-- Special values:
-- TANH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(TANH(X)) <= 1.0
-- Notes:
-- None
function ARCSINH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic sine of X
-- Special values:
-- ARCSINH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ARCSINH(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of ARCSINH is approximately given by:
-- ABS(ARCSINH(X)) <= LOG(REAL'HIGH)
function ARCCOSH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic cosine of X
-- Special values:
-- ARCCOSH(1.0) = 0.0
-- Domain:
-- X >= 1.0
-- Error conditions:
-- Error if X < 1.0
-- Range:
-- ARCCOSH(X) >= 0.0
-- Notes:
-- a) The upper bound of the reachable range of ARCCOSH is
-- approximately given by: ARCCOSH(X) <= LOG(REAL'HIGH)
function ARCTANH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic tangent of X
-- Special values:
-- ARCTANH(0.0) = 0.0
-- Domain:
-- ABS(X) < 1.0
-- Error conditions:
-- Error if ABS(X) >= 1.0
-- Range:
-- ARCTANH(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of ARCTANH is approximately given by:
-- ABS(ARCTANH(X)) < LOG(REAL'HIGH)
end MATH_REAL;
|
gpl-2.0
|
5f34a14fe67060aa496947aad9deca6e
| 0.442277 | 4.245309 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_divider/Shantz/Modular/celda_B.vhd
| 1 | 1,538 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity celda_B is
generic(
NUM_BITS : positive := 163
);
port(
U : in STD_LOGIC_VECTOR(NUM_BITS downto 0);
P : in STD_LOGIC_VECTOR(NUM_BITS downto 0);
Y2 : in STD_LOGIC_VECTOR(NUM_BITS downto 0);
c1 : in STD_LOGIC;
c2 : in STD_LOGIC;
c3 : in STD_LOGIC;
clk : in STD_LOGIC;
RegB : out STD_LOGIC_VECTOR(NUM_BITS downto 0)
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of celda_B is
----------------------------------------------------------------------------------------------------
signal toB : STD_LOGIC_VECTOR(NUM_BITS downto 0);
begin
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
toB <= Y2 when c1 = '0' and c2 = '0' else
P when c1 = '0' and c2 = '1' else
U;
celda_B_process: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if c3 = '1' then
RegB <= toB;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
0e57e8152a5995b079250c72c4903d2b
| 0.353706 | 4.483965 | false | false | false | false |
jakubcabal/pipemania-fpga-game
|
source/comp/game/kurzor_ctrl.vhd
| 1 | 15,564 |
--------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: CELL_GENERATOR
-- AUTHORS: Jakub Cabal <[email protected]>
-- Ondřej Dujiček <[email protected]>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/pipemania-fpga-game
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity KURZOR_CTRL is
Port (
CLK : in std_logic; -- Vychozi hodinovy signal
RST : in std_logic; -- Vychozi synchronni reset
KEY_W : in std_logic; -- Signal znacici zmacknuti tlacitka W
KEY_S : in std_logic; -- Signal znacici zmacknuti tlacitka S
KEY_A : in std_logic; -- Signal znacici zmacknuti tlacitka A
KEY_D : in std_logic; -- Signal znacici zmacknuti tlacitka D
KEY_SPACE : in std_logic; -- Signal znacici zmacknuti tlacitka SPACE
KOMP_GEN : out std_logic; -- Generuj novou nahodnou komponentu
KURZOR_ADDR : out std_logic_vector(7 downto 0); -- Adresa pozice kurzoru
DATAIN : in std_logic_vector(31 downto 0); -- Vstupni data
DATAOUT : out std_logic_vector(31 downto 0); -- Vystupni data
ADDR : out std_logic_vector(7 downto 0); -- Vystupni data
WE : out std_logic; -- Write enable
EN : out std_logic; -- Enable pameti
ACK : in std_logic; -- Potvrzeni zapisoveho nebo cteciho prikazu
KOMP4 : in std_logic_vector (5 downto 0);
CANT_PLACE : out std_logic;
CAN_PLACE : out std_logic;
SCREEN_CODE : in std_logic_vector(2 downto 0); -- game screen code
GAME_ON : in std_logic
);
end KURZOR_CTRL;
architecture FULL of KURZOR_CTRL is
type rom_t is array (15 downto 0) of std_logic_vector(15 downto 0);
constant LEVEL2_MAP : rom_t := (
"1111111111111111",
"1111111111111111",
"1111111111111111",
"1100001000000000",
"1100001000000000",
"1100001000000000",
"1100001000000000",
"1100001000000000",
"1100001000010000",
"1100001000010000",
"1100001000010000",
"1100000000010000",
"1100000000010000",
"1100000000010000",
"1100000000010000",
"1100000000010000"
);
constant LEVEL3_MAP : rom_t := (
"1111111111111111",
"1111111111111111",
"1111111111111111",
"1100000100000000",
"1100000100000000",
"1100000100000000",
"1111000100111000",
"1100000100100000",
"1100000100100000",
"1100000100100000",
"1100000100100000",
"1100000100100000",
"1100011100100011",
"1100000000100000",
"1100000000100000",
"1100000000100000"
);
constant LEVEL4_MAP : rom_t := (
"1111111111111111",
"1111111111111111",
"1111111111111111",
"1100000100000000",
"1100100100111100",
"1100100100000000",
"1100000100100111",
"1100000100100000",
"1100100100100000",
"1100100100100100",
"1100000100100100",
"1100000100100000",
"1111100100100000",
"1100000000100100",
"1100111100100100",
"1100000000100000"
);
signal sig_kurzor_addr : std_logic_vector(7 downto 0);
signal kurzor_x : unsigned(3 downto 0);
signal kurzor_y : unsigned(3 downto 0);
signal uprdownl : std_logic_vector(3 downto 0);
signal reset_en : std_logic;
signal gen_addr : unsigned(7 downto 0);
signal gen_en : std_logic;
signal gen_ok : std_logic;
signal lvl_gen : std_logic;
signal lvl2_row : std_logic_vector(15 downto 0);
signal lvl2_wall : std_logic;
signal lvl2_komp : std_logic_vector(1 downto 0);
signal lvl3_row : std_logic_vector(15 downto 0);
signal lvl3_wall : std_logic;
signal lvl3_komp : std_logic_vector(1 downto 0);
signal lvl4_row : std_logic_vector(15 downto 0);
signal lvl4_wall : std_logic;
signal lvl4_komp : std_logic_vector(1 downto 0);
type state is (wait_on_key, read_cell_data, data_check, pipe_insert,
reset_memory, lvl2_gen, lvl3_gen, lvl4_gen);
signal present_st : state;
signal next_st : state;
constant zeros_22 : std_logic_vector(21 downto 0) := (others => '0');
begin
----------------------------------------------------------------------------
-- RIZENI KURZORU
----------------------------------------------------------------------------
process (CLK)
begin
if (rising_edge(CLK)) then
if (GAME_ON = '1') then
if (KEY_W = '1' AND kurzor_y > 0) then
kurzor_y <= kurzor_y - 1;
elsif (KEY_S = '1' AND kurzor_y < 12) then
kurzor_y <= kurzor_y + 1;
elsif (KEY_A = '1' AND kurzor_x > 0) then
kurzor_x <= kurzor_x - 1;
elsif (KEY_D = '1' AND kurzor_x < 13) then
kurzor_x <= kurzor_x + 1;
end if;
else
kurzor_x <= "0000";
kurzor_y <= "0000";
end if;
end if;
end process;
sig_kurzor_addr <= std_logic_vector(kurzor_y & kurzor_x);
KURZOR_ADDR <= sig_kurzor_addr;
----------------------------------------------------------------------------
-- VKLADANI ROUR - STAVOVY AUTOMAT
----------------------------------------------------------------------------
-- Pametova cast stavoveho automatu
process (CLK, RST)
begin
if (RST = '1') then
present_st <= reset_memory;
elsif (rising_edge(CLK)) then
if (SCREEN_CODE = "000") then
present_st <= reset_memory;
else
present_st <= next_st;
end if;
end if;
end process;
-- Rozhodovaci cast stavoveho automatu
process (present_st, KEY_SPACE, ACK, DATAIN, GAME_ON, SCREEN_CODE, gen_ok)
begin
case present_st is
when wait_on_key => -- cekani na stisk klavesy
if (KEY_SPACE = '1' AND GAME_ON = '1') then
next_st <= read_cell_data;
elsif (SCREEN_CODE = "100") then
next_st <= lvl2_gen;
elsif (SCREEN_CODE = "101") then
next_st <= lvl3_gen;
elsif (SCREEN_CODE = "110") then
next_st <= lvl4_gen;
else
next_st <= wait_on_key;
end if;
when read_cell_data => -- vycteni dat o vybranem policku
if (ACK = '1') then
next_st <= data_check;
elsif (SCREEN_CODE = "100") then
next_st <= lvl2_gen;
elsif (SCREEN_CODE = "101") then
next_st <= lvl3_gen;
elsif (SCREEN_CODE = "110") then
next_st <= lvl4_gen;
else
next_st <= read_cell_data;
end if;
when data_check => -- kontrola vyctenych dat
if (DATAIN(3 downto 0) = "0000") then
next_st <= pipe_insert;
elsif (SCREEN_CODE = "100") then
next_st <= lvl2_gen;
elsif (SCREEN_CODE = "101") then
next_st <= lvl3_gen;
elsif (SCREEN_CODE = "110") then
next_st <= lvl4_gen;
else
next_st <= wait_on_key;
end if;
when pipe_insert => -- vlozeni trubky (zapis dat do pameti)
if (ACK = '1') then
next_st <= wait_on_key;
elsif (SCREEN_CODE = "100") then
next_st <= lvl2_gen;
elsif (SCREEN_CODE = "101") then
next_st <= lvl3_gen;
elsif (SCREEN_CODE = "110") then
next_st <= lvl4_gen;
else
next_st <= pipe_insert;
end if;
when reset_memory => -- resetovani pameti
if (gen_ok = '1') then
next_st <= wait_on_key;
else
next_st <= reset_memory;
end if;
when lvl2_gen => -- generovani lvl2
if (gen_ok = '1') then
next_st <= wait_on_key;
else
next_st <= lvl2_gen;
end if;
when lvl3_gen => -- generovani lvl3
if (gen_ok = '1') then
next_st <= wait_on_key;
else
next_st <= lvl3_gen;
end if;
when lvl4_gen => -- generovani lvl4
if (gen_ok = '1') then
next_st <= wait_on_key;
else
next_st <= lvl4_gen;
end if;
when others =>
next_st <= wait_on_key;
end case;
end process;
-- Vystupni cast stavoveho automatu
process (present_st, KOMP4, sig_kurzor_addr, uprdownl, DATAIN,
gen_addr, lvl2_komp, lvl3_komp, lvl4_komp)
begin
case present_st is
when wait_on_key =>
EN <= '0';
WE <= '0';
ADDR <= sig_kurzor_addr;
DATAOUT <= (others=>'0');
KOMP_GEN <= '0';
reset_en <= '0';
lvl_gen <= '0';
CANT_PLACE <= '0';
CAN_PLACE <= '0';
when read_cell_data =>
EN <= '1';
WE <= '0';
ADDR <= sig_kurzor_addr;
DATAOUT <= (others=>'0');
KOMP_GEN <= '0';
reset_en <= '0';
lvl_gen <= '0';
CANT_PLACE <= '0';
CAN_PLACE <= '0';
when data_check =>
EN <= '0';
WE <= '0';
ADDR <= sig_kurzor_addr;
DATAOUT <= (others=>'0');
KOMP_GEN <= '0';
reset_en <= '0';
lvl_gen <= '0';
CAN_PLACE <= '0';
if (DATAIN(3 downto 0) = "0000") then
CANT_PLACE <= '0';
else
CANT_PLACE <= '1';
end if;
when pipe_insert =>
EN <= '1';
WE <= '1';
ADDR <= sig_kurzor_addr;
DATAOUT <= zeros_22 & uprdownl & KOMP4;
KOMP_GEN <= '1';
reset_en <= '0';
lvl_gen <= '0';
CANT_PLACE <= '0';
CAN_PLACE <= '1';
when reset_memory =>
EN <= '1';
WE <= '1';
ADDR <= std_logic_vector(gen_addr);
DATAOUT <= (others=>'0');
KOMP_GEN <= '0';
reset_en <= '1';
lvl_gen <= '0';
CANT_PLACE <= '0';
CAN_PLACE <= '0';
when lvl2_gen => -- generovani levlu 2
EN <= '1';
WE <= '1';
ADDR <= std_logic_vector(gen_addr);
DATAOUT <= "0000000000000000000000000000" & lvl2_komp & "00";
KOMP_GEN <= '0';
reset_en <= '0';
lvl_gen <= '1';
CANT_PLACE <= '0';
CAN_PLACE <= '0';
when lvl3_gen => -- generovani levlu 3
EN <= '1';
WE <= '1';
ADDR <= std_logic_vector(gen_addr);
DATAOUT <= "0000000000000000000000000000" & lvl3_komp & "00";
KOMP_GEN <= '0';
reset_en <= '0';
lvl_gen <= '1';
CANT_PLACE <= '0';
CAN_PLACE <= '0';
when lvl4_gen => -- generovani levlu 4
EN <= '1';
WE <= '1';
ADDR <= std_logic_vector(gen_addr);
DATAOUT <= "0000000000000000000000000000" & lvl4_komp & "00";
KOMP_GEN <= '0';
reset_en <= '0';
lvl_gen <= '1';
CANT_PLACE <= '0';
CAN_PLACE <= '0';
when others =>
EN <= '0';
WE <= '0';
ADDR <= sig_kurzor_addr;
DATAOUT <= (others=>'0');
KOMP_GEN <= '0';
reset_en <= '0';
lvl_gen <= '0';
CANT_PLACE <= '0';
CAN_PLACE <= '0';
end case;
end process;
with KOMP4 select
uprdownl <= "0011" when "100010", -- zahnuta zprava nahoru
"1100" when "000010", -- zahnuta zleva dolu
"1001" when "010010", -- zahnuta zleva nahoru
"0110" when "110010", -- zahnuta zprava dolu
"1010" when "000001", -- rovna zleva doprava
"0101" when "010001", -- rovna zhora dolu
"1111" when "000011", -- krizova
"0000" when others;
--LDRU
----------------------------------------------------------------------------
-- GENERATE ADDRESS COUNTER AND OK FLAG
----------------------------------------------------------------------------
gen_en <= lvl_gen or reset_en;
process (CLK)
begin
if rising_edge(CLK) then
if (gen_en = '1') then
gen_addr <= gen_addr + 1;
else
gen_addr <= (others=>'0');
end if;
end if;
end process;
gen_ok <= '1' when (gen_addr = "11111111") else '0';
----------------------------------------------------------------------------
-- LEVEL 2 ROM
----------------------------------------------------------------------------
lvl2_row <= LEVEL2_MAP(to_integer(gen_addr(7 downto 4)));
lvl2_wall <= lvl2_row(to_integer(gen_addr(3 downto 0)));
lvl2_komp <= "11" when (lvl2_wall = '1') else "00";
----------------------------------------------------------------------------
-- LEVEL 3 ROM
----------------------------------------------------------------------------
lvl3_row <= LEVEL3_MAP(to_integer(gen_addr(7 downto 4)));
lvl3_wall <= lvl3_row(to_integer(gen_addr(3 downto 0)));
lvl3_komp <= "11" when (lvl3_wall = '1') else "00";
----------------------------------------------------------------------------
-- LEVEL 4 ROM
----------------------------------------------------------------------------
lvl4_row <= LEVEL4_MAP(to_integer(gen_addr(7 downto 4)));
lvl4_wall <= lvl4_row(to_integer(gen_addr(3 downto 0)));
lvl4_komp <= "11" when (lvl4_wall = '1') else "00";
end FULL;
|
mit
|
dcd7d9745475400465c41c5b2d578a80
| 0.413764 | 4.359104 | false | false | false | false |
peteut/ghdl
|
libraries/ieee2008/std_logic_1164.vhdl
| 4 | 15,154 |
-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is sold without written
-- permission from the IEEE Standards Department. This source file may be
-- copied for individual use between licensed users. This source file is
-- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR
-- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE
-- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify
-- and hold IEEE harmless from any damages or liability arising out of the
-- use thereof.
--
-- Title : Standard multivalue logic package
-- : (STD_LOGIC_1164 package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE model standards group (PAR 1164),
-- : Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This packages defines a standard for designers
-- : to use in describing the interconnection data types
-- : used in vhdl modeling.
-- :
-- Limitation: The logic system defined in this package may
-- : be insufficient for modeling switched transistors,
-- : since such a requirement is out of the scope of this
-- : effort. Furthermore, mathematics, primitives,
-- : timing standards, etc. are considered orthogonal
-- : issues as it relates to this package and are therefore
-- : beyond the scope of this effort.
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
use STD.TEXTIO.all;
package std_logic_1164 is
-------------------------------------------------------------------
-- logic state system (unresolved)
-------------------------------------------------------------------
type STD_ULOGIC is ( 'U', -- Uninitialized
'X', -- Forcing Unknown
'0', -- Forcing 0
'1', -- Forcing 1
'Z', -- High Impedance
'W', -- Weak Unknown
'L', -- Weak 0
'H', -- Weak 1
'-' -- Don't care
);
-------------------------------------------------------------------
-- unconstrained array of std_ulogic for use with the resolution function
-- and for use in declaring signal arrays of unresolved elements
-------------------------------------------------------------------
type STD_ULOGIC_VECTOR is array (NATURAL range <>) of STD_ULOGIC;
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
function resolved (s : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-------------------------------------------------------------------
-- logic state system (resolved)
-------------------------------------------------------------------
subtype STD_LOGIC is resolved STD_ULOGIC;
-------------------------------------------------------------------
-- unconstrained array of resolved std_ulogic for use in declaring
-- signal arrays of resolved elements
-------------------------------------------------------------------
subtype STD_LOGIC_VECTOR is (resolved) STD_ULOGIC_VECTOR;
-------------------------------------------------------------------
-- common subtypes
-------------------------------------------------------------------
subtype X01 is resolved STD_ULOGIC range 'X' to '1'; -- ('X','0','1')
subtype X01Z is resolved STD_ULOGIC range 'X' to 'Z'; -- ('X','0','1','Z')
subtype UX01 is resolved STD_ULOGIC range 'U' to '1'; -- ('U','X','0','1')
subtype UX01Z is resolved STD_ULOGIC range 'U' to 'Z'; -- ('U','X','0','1','Z')
-------------------------------------------------------------------
-- overloaded logical operators
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
function "or" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC) return ux01;
function "not" (l : STD_ULOGIC) return UX01;
-------------------------------------------------------------------
-- vectorized overloaded logical operators
-------------------------------------------------------------------
function "and" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nand" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "or" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xnor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "not" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "and" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function "nand" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function "or" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function "nor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function "xor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function "xnor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-------------------------------------------------------------------
-- shift operators
-------------------------------------------------------------------
function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
-------------------------------------------------------------------
-- conversion functions
-------------------------------------------------------------------
function To_bit (s : STD_ULOGIC; xmap : BIT := '0') return BIT;
function To_bitvector (s : STD_ULOGIC_VECTOR; xmap : BIT := '0') return BIT_VECTOR;
function To_StdULogic (b : BIT) return STD_ULOGIC;
function To_StdLogicVector (b : BIT_VECTOR) return STD_LOGIC_VECTOR;
function To_StdLogicVector (s : STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR;
function To_StdULogicVector (b : BIT_VECTOR) return STD_ULOGIC_VECTOR;
function To_StdULogicVector (s : STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR;
alias To_Bit_Vector is
To_bitvector[STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
alias To_BV is
To_bitvector[STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
alias To_Std_Logic_Vector is
To_StdLogicVector[BIT_VECTOR return STD_LOGIC_VECTOR];
alias To_SLV is
To_StdLogicVector[BIT_VECTOR return STD_LOGIC_VECTOR];
alias To_Std_Logic_Vector is
To_StdLogicVector[STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias To_SLV is
To_StdLogicVector[STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias To_Std_ULogic_Vector is
To_StdULogicVector[BIT_VECTOR return STD_ULOGIC_VECTOR];
alias To_SULV is
To_StdULogicVector[BIT_VECTOR return STD_ULOGIC_VECTOR];
alias To_Std_ULogic_Vector is
To_StdULogicVector[STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
alias To_SULV is
To_StdULogicVector[STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
-------------------------------------------------------------------
-- strength strippers and type convertors
-------------------------------------------------------------------
function TO_01 (s : STD_ULOGIC_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR;
function TO_01 (s : STD_ULOGIC; xmap : STD_ULOGIC := '0')
return STD_ULOGIC;
function TO_01 (s : BIT_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR;
function TO_01 (s : BIT; xmap : STD_ULOGIC := '0')
return STD_ULOGIC;
function To_X01 (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function To_X01 (s : STD_ULOGIC) return X01;
function To_X01 (b : BIT_VECTOR) return STD_ULOGIC_VECTOR;
function To_X01 (b : BIT) return X01;
function To_X01Z (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function To_X01Z (s : STD_ULOGIC) return X01Z;
function To_X01Z (b : BIT_VECTOR) return STD_ULOGIC_VECTOR;
function To_X01Z (b : BIT) return X01Z;
function To_UX01 (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function To_UX01 (s : STD_ULOGIC) return UX01;
function To_UX01 (b : BIT_VECTOR) return STD_ULOGIC_VECTOR;
function To_UX01 (b : BIT) return UX01;
function "??" (l : STD_ULOGIC) return BOOLEAN;
-------------------------------------------------------------------
-- edge detection
-------------------------------------------------------------------
function rising_edge (signal s : STD_ULOGIC) return BOOLEAN;
function falling_edge (signal s : STD_ULOGIC) return BOOLEAN;
-------------------------------------------------------------------
-- object contains an unknown
-------------------------------------------------------------------
function Is_X (s : STD_ULOGIC_VECTOR) return BOOLEAN;
function Is_X (s : STD_ULOGIC) return BOOLEAN;
-------------------------------------------------------------------
-- matching relational operators
-------------------------------------------------------------------
-- the following operations are predefined
-- function "?=" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function "?=" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- function "?/=" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function "?/=" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- function "?<" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function "?<=" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function "?>" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function "?>=" (l, r : STD_ULOGIC) return STD_ULOGIC;
-------------------------------------------------------------------
-- string conversion and write operations
-------------------------------------------------------------------
-- the following operations are predefined
-- function to_string (value : STD_ULOGIC) return STRING;
-- function to_string (value : STD_ULOGIC_VECTOR) return STRING;
-- explicitly defined operations
alias TO_BSTRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
function TO_OSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [STD_ULOGIC_VECTOR return STRING];
function TO_HSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [STD_ULOGIC_VECTOR return STRING];
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, STD_ULOGIC_VECTOR];
alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR];
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR];
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR];
alias BWRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
end package std_logic_1164;
|
gpl-2.0
|
22f9c8e23549a7b186df16eec16895fb
| 0.549096 | 4.290487 | false | false | false | false |
herenvarno/dlx
|
dlx_vhd/src/a.b-DataPath.core/a.b.d-FwdMux1.vhd
| 1 | 1,778 |
--------------------------------------------------------------------------------
-- FILE: FwdMux1
-- DESC: Forward Multiplexer with 1 stage forward.
--
-- Author:
-- Create: 2015-06-01
-- Update: 2015-10-03
-- Status: TESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.Consts.all;
use work.Funcs.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity FwdMux1 is
generic (
DATA_SIZE : integer := C_SYS_DATA_SIZE;
REG_ADDR_SIZE : integer := MyLog2Ceil(C_REG_NUM)
);
port(
reg_c : in std_logic_vector(DATA_SIZE-1 downto 0);
reg_f : in std_logic_vector(DATA_SIZE-1 downto 0);
addr_c : in std_logic_vector(REG_ADDR_SIZE-1 downto 0);
addr_f : in std_logic_vector(REG_ADDR_SIZE-1 downto 0);
valid_f : in std_logic;
dirty_f : in std_logic;
output : out std_logic_vector(DATA_SIZE-1 downto 0);
match_dirty_f: out std_logic
);
end FwdMux1;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture fwd_mux_1_arch of FwdMux1 is
begin
P0: process(reg_c, reg_f, addr_c, addr_f, valid_f, dirty_f)
variable dmatchf: std_logic:='0';
begin
dmatchf := '0';
if addr_c=(addr_c'range => '0') then
output <= reg_c;
else
if (addr_c=addr_f) and (valid_f='1') then
if dirty_f='1' then
dmatchf := '1';
else
dmatchf := '0';
end if;
output <= reg_f;
else
match_dirty_f<='0';
output <= reg_c;
end if;
end if;
match_dirty_f <= dmatchf;
end process;
end fwd_mux_1_arch;
|
mit
|
670a5335aafdae2a484a9380e6670faa
| 0.463442 | 3.39313 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc516.vhd
| 4 | 3,934 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc516.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p03n04i00516ent IS
END c03s03b00x00p03n04i00516ent;
ARCHITECTURE c03s03b00x00p03n04i00516arch OF c03s03b00x00p03n04i00516ent IS
BEGIN
TESTING: PROCESS
type color is (red, green, blue);
constant azure : color := blue;
constant first : color := color'low;
type enum_ptr is access color;
variable v_enum_ptr1: enum_ptr := new color'(blue);
variable v_enum_ptr2: enum_ptr;
variable v_enum_ptr3: enum_ptr := v_enum_ptr1;
variable v_enum_ptr4: enum_ptr := new color'(red);
variable v_enum_ptr5: enum_ptr := v_enum_ptr4;
variable OKtest : integer := 0;
BEGIN
assert v_enum_ptr1.all = blue;
if (v_enum_ptr1.all = blue) then
OKtest := OKtest + 1;
end if;
assert v_enum_ptr2 = null;
if (v_enum_ptr2 = null) then
OKtest := OKtest + 1;
end if;
assert v_enum_ptr3.all = blue;
if (v_enum_ptr3.all = blue) then
OKtest := OKtest + 1;
end if;
assert v_enum_ptr4.all = red;
if (v_enum_ptr4.all = red) then
OKtest := OKtest + 1;
end if;
assert v_enum_ptr5.all = red;
if (v_enum_ptr5.all = red) then
OKtest := OKtest + 1;
end if;
v_enum_ptr2 := new color'(green);
assert v_enum_ptr2.all = green;
if (v_enum_ptr2.all = green) then
OKtest := OKtest + 1;
end if;
assert (v_enum_ptr3.all = color'succ(green));
if (v_enum_ptr3.all = color'succ(green)) then
OKtest := OKtest + 1;
end if;
assert (v_enum_ptr5.all = color'pred(v_enum_ptr2.all));
if (v_enum_ptr5.all = color'pred(v_enum_ptr2.all)) then
OKtest := OKtest + 1;
end if;
assert (color'pred(v_enum_ptr3.all) = green);
if (color'pred(v_enum_ptr3.all) = green) then
OKtest := OKtest + 1;
end if;
assert (v_enum_ptr5.all = color'low);
if (v_enum_ptr5.all = color'low) then
OKtest := OKtest + 1;
end if;
assert (v_enum_ptr3.all = color'high);
if (v_enum_ptr3.all = color'high) then
OKtest := OKtest + 1;
end if;
assert (v_enum_ptr5.all = color'left);
if (v_enum_ptr5.all = color'left) then
OKtest := OKtest + 1;
end if;
assert (v_enum_ptr3.all = color'right);
if (v_enum_ptr3.all = color'right) then
OKtest := OKtest + 1;
end if;
assert (v_enum_ptr3.all > v_enum_ptr5.all) = true;
if (v_enum_ptr3.all > v_enum_ptr5.all) then
OKtest := OKtest + 1;
end if;
assert NOT(OKtest = 14)
report "***PASSED TEST: c03s03b00x00p03n04i00516"
severity NOTE;
assert (OKtest = 14)
report "***FAILED TEST: c03s03b00x00p03n04i00516 - Enumeration type using as base for access type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p03n04i00516arch;
|
gpl-2.0
|
5f5faf0367c1b6caf020419fa9a5c6e7
| 0.620234 | 3.190592 | false | true | false | false |
123gmax/Digital-Lab
|
AES128/building_blocks/addRoundKey_tb.vhd
| 1 | 1,807 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/26/2015 04:05:50 PM
-- Design Name:
-- Module Name: addRoundKey_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity addRoundKey_tb is
end addRoundKey_tb;
architecture Behavioral of addRoundKey_tb is
component addRoundKey is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
wordIn : in STD_LOGIC_VECTOR (31 downto 0);
keyIn : in STD_LOGIC_VECTOR (31 downto 0);
wordOut : out STD_LOGIC_VECTOR (31 downto 0));
end component;
constant clk_period : time := 2ns;
signal CLK, RESET : STD_LOGIC := '0';
signal wordIn, keyIn, wordOut : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
begin
uut: addRoundKey port map( CLK => CLK,
RESET => RESET,
wordIn => wordIn,
keyIn => keyIn,
wordOut => wordOut);
clk_process: process
begin
CLK <= '1';
wait for clk_period/2;
CLK <= '0';
wait for clk_period/2;
end process;
--Inputs taken from http://kavaliro.com/wp-content/uploads/2014/03/AES.pdf
stim_process: process
begin
wait for 5*clk_period;
wordIn <= x"54776F20";
keyIn <= x"54686174";
wait for clk_period;
wordIn <= x"4F6E6520";
keyIn <= x"73206D79";
wait for 5*clk_period;
end process;
end Behavioral;
|
gpl-2.0
|
32ffbc818ef5efecd81a68b578647689
| 0.511898 | 4.06982 | false | false | false | false |
herenvarno/dlx
|
dlx_vhd/tb/old_tb/a.a-tbControlUnit.vhd
| 1 | 2,595 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Types.all;
use work.Consts.all;
use work.Funcs.all;
entity tbControlUnit is
end tbControlUnit;
architecture tb_control_unit_arch of tbControlUnit is
constant ISTR_SIZE : integer := C_SYS_ISTR_SIZE;
constant DATA_SIZE : integer := C_SYS_DATA_SIZE;
constant OPCD_SIZE : integer := C_SYS_OPCD_SIZE;
constant FUNC_SIZE : integer := C_SYS_FUNC_SIZE;
constant CWRD_SIZE : integer := C_SYS_CWRD_SIZE;
constant CALU_SIZE : integer := C_CTR_CALU_SIZE;
constant REG_ADDR_SIZE : integer := MyLog2Ceil(C_REG_NUM);
component ControlUnit
generic(
ISTR_SIZE : integer := C_SYS_ISTR_SIZE; -- Instruction Register Size
DATA_SIZE : integer := C_SYS_DATA_SIZE; -- Data Size
OPCD_SIZE : integer := C_SYS_OPCD_SIZE; -- Op Code Size
FUNC_SIZE : integer := C_SYS_FUNC_SIZE; -- Func Field Size for R-Type Ops
CWRD_SIZE : integer := C_SYS_CWRD_SIZE; -- Control Word Size
CALU_SIZE : integer := C_CTR_CALU_SIZE; -- ALU Op Code Word Size
REG_ADDR_SIZE : integer := MyLog2Ceil(C_REG_NUM) -- Control Word Size
);
port(
clk : in std_logic;
rst : in std_logic;
ir : in std_logic_vector(ISTR_SIZE-1 downto 0);
reg_a : in std_logic_vector(DATA_SIZE-1 downto 0);
alu_o : in std_logic_vector(DATA_SIZE-1 downto 0);
wb_o : in std_logic_vector(DATA_SIZE-1 downto 0);
cw : out std_logic_vector(CWRD_SIZE-1 downto 0);
calu : out std_logic_vector(CALU_SIZE-1 downto 0);
reg4_addr_in : in std_logic_vector(REG_ADDR_SIZE downto 0);
reg5_addr_in : in std_logic_vector(REG_ADDR_SIZE downto 0)
);
end component;
signal rst : std_logic;
signal clk : std_logic;
signal ir : std_logic_vector(ISTR_SIZE-1 downto 0);
signal reg_a : std_logic_vector(DATA_SIZE-1 downto 0);
signal alu_o : std_logic_vector(DATA_SIZE-1 downto 0);
signal wb_o : std_logic_vector(DATA_SIZE-1 downto 0);
signal cw : std_logic_vector(CWRD_SIZE-1 downto 0);
signal calu : std_logic_vector(CALU_SIZE-1 downto 0);
signal reg4_addr_in : std_logic_vector(REG_ADDR_SIZE downto 0);
signal reg5_addr_in : std_logic_vector(REG_ADDR_SIZE downto 0)
begin
CU0: ControlUnit
generic map(ISTR_SIZE, DATA_SIZE, OPCD_SIZE, FUNC_SIZE, CWRD_SIZE, CALU_SIZE, REG_ADDR_SIZE)
port map(clk, rst, ir, reg_a, alu_o, wb_o, cw, calu, reg4_addr_in, reg5_addr_in);
CLK0: process(clk)
begin
clk = not (clk);
end process;
rst <= '0', '1' after 1 ns;
end tb_control_unit_arch;
configuration tb_control_unit_cfg of tbControlUnit is
for tb_control_unit_arch
end for;
end tb_control_unit_cfg;
|
mit
|
64042291da780a6c52ecc9678db949ef
| 0.68632 | 2.683557 | false | false | false | false |
dicearr/neuron-vhdl
|
src/sigmoid.vhd
| 1 | 30,205 |
----------------------------------------------------------------------------------
-- Engineer: Diego Ceresuela, Oscar Clemente.
--
-- Create Date: 13.04.2016 08:23:25
-- Module Name: sigmoid - Behavioral
-- Description: Implements a ROM containing the aproximation of the sigmoid function.
--
-- Dependencies:
--
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_arith.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sigmoid is
Port ( Y : in STD_LOGIC_VECTOR (31 downto 0);
O : out STD_LOGIC_VECTOR (31 downto 0);
clk: in STD_LOGIC );
end sigmoid;
architecture Behavioral of sigmoid is
type rom is array (0 to 3410) of STD_LOGIC_VECTOR (15 downto 0);
signal sigmoid_val : rom := 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signal ind, dec, decimal_32, ent_32 : integer := 0;
begin
process (clk) begin
if rising_edge(clk) then
decimal_32 <= conv_integer(x"0000" & Y(15 downto 0));
ent_32 <= conv_integer(Y(31 downto 16));
end if;
end process;
process (clk) begin
if rising_edge(clk) then
if ( Y(31 downto 16) < -10 ) then
dec <= decimal_32/9855;
elsif ( Y(31 downto 16) < -9 ) then
dec <= decimal_32/2815;
elsif ( Y(31 downto 16) < 9 ) then
dec <= decimal_32/351;
elsif ( Y(31 downto 16) < 10 ) then
dec <= decimal_32/2815;
else
dec <= decimal_32/9855;
end if;
end if;
end process;
process (clk) begin
if rising_edge(clk) then
if ( Y(31 downto 16) < -10 ) then
ind <= dec;
elsif ( Y(31 downto 16) < -9 ) then
ind <= 7 + dec;
elsif ( Y(31 downto 16) < 9 ) then
ind <= 1704+(ent_32*186)+dec;
elsif ( Y(31 downto 16) < 10 ) then
ind <= 1705+(ent_32*186)+dec;
else
ind <= 1728+(ent_32*186)+dec;
end if;
end if;
end process;
process (clk) begin
if rising_edge(clk) then
if (Y(31 downto 16) < -11) then O <= x"00000000";
elsif (Y(31 downto 16) > 11) then O <= x"0000FFFF";
else
O <= x"0000" & sigmoid_val(ind);
end if;
end if;
end process;
end Behavioral;
|
mit
|
1739bf61b249e4b91c1163d63d29018e
| 0.612283 | 1.663179 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/bug15966/fail.vhd
| 3 | 2,795 |
package key_pkg is
type key_action is (pressed, released);
type key_status_mat is array (natural range <>, natural range <>) of key_action;
end key_pkg;
library IEEE;
use IEEE.std_logic_1164.all;
use work.key_pkg.all;
entity key is
port(
in_terminal : in std_logic;
out_terminal : out std_logic;
key_status : in key_action);
end key;
architecture key_bhv of key is
begin
bounce_io: process(key_status, in_terminal) is
begin
if key_status = pressed then
out_terminal <= in_terminal;
else
out_terminal <= 'Z';
end if;
end process bounce_io;
end architecture key_bhv;
library IEEE;
use IEEE.std_logic_1164.all;
use work.key_pkg.all;
entity scaleable_matrix_keyboard is
generic(
nr_rows : positive;
nr_cols : positive);
port(
col_inputs : in std_logic_vector(nr_cols-1 downto 0);
row_outputs : out std_logic_vector(nr_rows-1 downto 0);
key_status_all : in key_status_mat(nr_rows-1 downto 0, nr_cols-1 downto 0));
end scaleable_matrix_keyboard;
architecture scaleable_matrix_keyboard_bhv of scaleable_matrix_keyboard is
begin
key_matrix : for row in row_outputs'range generate
begin
key_row: for col in col_inputs'range generate
begin
key_col: entity work.key(key_bhv)
port map(
in_terminal => col_inputs(col),
out_terminal => row_outputs(row),
key_status => key_status_all(row, col));
end generate key_row;
end generate key_matrix;
end architecture scaleable_matrix_keyboard_bhv;
library IEEE;
use IEEE.std_logic_1164.all;
use work.key_pkg.all;
entity mat_key_tb is
end mat_key_tb;
architecture mat_key_tb_bhv of mat_key_tb is
signal key_0 : key_action := released;
signal key_1 : key_action := released;
signal key_2 : key_action := released;
signal key_3 : key_action := released;
signal col1 : std_logic := 'Z';
signal col2 : std_logic := 'Z';
signal row1 : std_logic;
signal row2 : std_logic;
begin
key_DUT: entity work.scaleable_matrix_keyboard(scaleable_matrix_keyboard_bhv)
generic map(
nr_rows => 2,
nr_cols => 2
)
port map(
col_inputs(0) => col1,
col_inputs(1) => col2,
row_outputs(0) => row1,
row_outputs(1) => row2,
key_status_all(0, 0) => key_0,
key_status_all(0, 1) => key_1,
key_status_all(1, 0) => key_1,
key_status_all(1, 1) => key_1
);
end architecture mat_key_tb_bhv;
|
gpl-2.0
|
5f5296543cfbc58b81d14e8401dc651a
| 0.567442 | 3.52459 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_divider/Shantz/Modular/shantz_modular_131.vhd
| 1 | 5,090 |
---------------------------------------------------------------------------------------------------
-- divider_f2m.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Inverter for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: This is an implementation of the division algorithm. Dirent to the other implemented inverter
-- in this, the division is performed directly.
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity f2m_divider_131 is
generic(
NUM_BITS : positive := 131
);
port(
x : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
y : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
done : out STD_LOGIC;
x_div_y : out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of f2m_divider_131 is
----------------------------------------------------------------------------------------------------
-- m = 131, the irreductible polynomial
constant p : std_logic_vector(NUM_BITS downto 0) := "100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100001101";
-- control signals
signal CASO: std_logic_vector(1 downto 0);
signal c0, c1, c2, c3, c4, c5, c6, enA, enB, a_greater_b,a_eq_b: std_logic;
signal A, B, U, V, X2, Y2, toB, toV: STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
type CurrentState_type is (END_STATE, LOAD1, CYCLE);
signal currentState: CurrentState_type;
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
X2 <= x & '0';
Y2 <= y & '0';
caso <= "00" when A(0) = '0' and currentState = CYCLE else
"01" when B(0) = '0' and currentState = CYCLE else
"10" when a_greater_b = '1' and currentState = CYCLE else
"11";
c0 <= '0' when caso = "01" else
'1';
c1 <= '0' when caso = "00" else
'1';
c2 <= '0' when caso = "01" else
'1';
c3 <= '0' when caso = "00" else
'1';
c4 <= '0' when CurrentState = Load1 else
'1';
c5 <= '0' when rst = '1' or currentState = LOAD1 else
'1';
c6 <= '0' when rst = '1' else
'1';
enA <= '1' when currentState = LOAD1 or caso = "00" or caso = "10" else
'0';
enB <= '1' when caso = "01" or caso = "11" or rst = '1' or currentstate = LOAD1 else
'0';
a_greater_b <= '1' when A > B else
'0';
a_eq_b <= '1' when A = B else
'0';
celda_reg_A: entity celda_a(behave)
generic map(NUM_BITS)
port map( A, B, c0, c1, enA, rst, clk, toB, A);
celda_reg_U: entity celda_U(behave)
generic map(NUM_BITS)
port map(U, V, P, c2, c3, c4, enA, rst, clk, toV, U);
celda_reg_B: entity celda_B(behave)
generic map(NUM_BITS)
port map(toB, P , Y2, c5, c6, enB, clk, B);
celda_reg_V: entity celda_v(behave)
generic map(NUM_BITS)
port map(toV, X2, c5, c6, enB, clk, V);
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
EEAL: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if rst = '1' then
x_div_y <= (others => '0');
done <= '0';
currentState <= LOAD1;
else
case currentState is
-----------------------------------------------------------------------------------
when LOAD1 =>
currentState <= Cycle;
when CYCLE =>
if A_eq_B = '1' then
currentState <= END_STATE;
Done <= '1';
x_div_y <= U(NUM_BITS-1 downto 0);
end if;
-----------------------------------------------------------------------------------
when END_STATE => -- Do nothing
currentState <= END_STATE;
--done <= '0'; -- para generar el pulso, quitarlo entity caso contrario
-----------------------------------------------------------------------------------
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
9510b1cdcc79035f09de20ea4a34f73b
| 0.413752 | 4.007874 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_12a.vhd
| 4 | 2,099 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_12a is
end entity inline_12a;
architecture test of inline_12a is
-- code from book
type biases is (forward, reverse);
type regions is (cutoff, saturation, linear);
signal bias : biases;
signal region : regions;
-- end code from book
constant threshold_voltage : voltage := 0.6;
constant k : real := 0.0125;
terminal gate, source, drain : electrical;
quantity vds across ids through drain to source;
quantity vsd across source to drain;
quantity vgs across gate to source;
quantity vgd across gate to drain;
begin
-- code from book
case bias use
when forward =>
case region use
when cutoff =>
ids == 0.0;
when saturation =>
ids == 0.5 * k * (vgs - threshold_voltage)**2;
when linear =>
ids == k * (vgs - threshold_voltage - 0.5*vds) * vds;
end case;
when reverse =>
case region use
when cutoff =>
ids == 0.0;
when saturation =>
ids == -0.5 * k * (vgd - threshold_voltage)**2;
when linear =>
ids == -k * (vgd - threshold_voltage - 0.5*vsd) * vsd;
end case;
end case;
-- end code from book
end architecture test;
|
gpl-2.0
|
3e18f24bcee418846c26f96b06934d0d
| 0.650786 | 4.115686 | false | false | false | false |
stnolting/neo430
|
rtl/core/neo430_exirq.vhd
| 1 | 12,526 |
-- #################################################################################################
-- # << NEO430 - External Interrupts Controller >> #
-- # ********************************************************************************************* #
-- # This unit provides 8 maskable external interrupt lines with according ACK lines. The IRQ #
-- # trigger on a high level (use external edge detectors if required). Each line has a unique #
-- # enable bit. The acknowledge output is set high for one clock cycle to confirm the #
-- # interrupt has been sampled and has also been cpatured by the according handler function. #
-- # All external interrupt requests are forwarded to a *single CPU interrupt*. The according IRQ #
-- # has to check the SRC bits in the unit's control register to determine the actual source and #
-- # start the according handler function. #
-- # If several IRQs occur at the same time, the one with highest priority is executed while the #
-- # others are kept in a buffer. The buffer is reset when the global enable flag of the unit is #
-- # cleared. ext_irq_i(0) has highest priority while ext_irq_i(7) has the lowest priority. #
-- # Each enabled interrupt channel can also be triggered by software using the sw_irq_x bits. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
entity neo430_exirq is
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0); -- data out
-- cpu interrupt --
cpu_irq_o : out std_ulogic;
-- external interrupt lines --
ext_irq_i : in std_ulogic_vector(7 downto 0); -- IRQ, triggering on HIGH level
ext_ack_o : out std_ulogic_vector(7 downto 0) -- acknowledge
);
end neo430_exirq;
architecture neo430_exirq_rtl of neo430_exirq is
-- control register bits --
constant ctrl_irq_sel0_c : natural := 0; -- r/w: IRQ source bit 0 (r); SW IRQ select (w)
constant ctrl_irq_sel1_c : natural := 1; -- r/w: IRQ source bit 1 (r); SW IRQ select (w)
constant ctrl_irq_sel2_c : natural := 2; -- r/w: IRQ source bit 2 (r); SW IRQ select (w)
constant ctrl_en_c : natural := 3; -- r/w: unit enable
constant ctrl_sw_irq_c : natural := 4; -- -/w: use irq_sel as SW IRQ trigger, auto-clears
constant ctrl_ack_irq_c : natural := 5; -- -/w: ACK current IRQ, auto-clears
-- ...
constant ctrl_en_irq0_c : natural := 8; -- r/w: IRQ channel 0 enable
constant ctrl_en_irq1_c : natural := 9; -- r/w: IRQ channel 1 enable
constant ctrl_en_irq2_c : natural := 10; -- r/w: IRQ channel 2 enable
constant ctrl_en_irq3_c : natural := 11; -- r/w: IRQ channel 3 enable
constant ctrl_en_irq4_c : natural := 12; -- r/w: IRQ channel 4 enable
constant ctrl_en_irq5_c : natural := 13; -- r/w: IRQ channel 5 enable
constant ctrl_en_irq6_c : natural := 14; -- r/w: IRQ channel 6 enable
constant ctrl_en_irq7_c : natural := 15; -- r/w: IRQ channel 7 enable
-- IO space: module base address --
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
constant lo_abb_c : natural := index_size_f(exirq_size_c); -- low address boundary bit
-- access control --
signal acc_en : std_ulogic; -- module access enable
signal wren : std_ulogic; -- full word write enable
signal rden : std_ulogic; -- read enable
-- r/w accessible registers --
signal irq_enable : std_ulogic_vector(7 downto 0);
signal enable : std_ulogic; -- global enable
signal irq_sel : std_ulogic_vector(2 downto 0);
signal sw_trig : std_ulogic;
signal ack_trig : std_ulogic;
-- irq input / ack output system --
signal irq_sync, irq_raw, sw_irq, irq_valid, ack_mask : std_ulogic_vector(7 downto 0);
-- controller core --
signal irq_buf : std_ulogic_vector(7 downto 0);
signal irq_src, irq_src_reg : std_ulogic_vector(2 downto 0);
signal irq_fire, state : std_ulogic;
begin
-- Access control -----------------------------------------------------------
-- -----------------------------------------------------------------------------
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = exirq_base_c(hi_abb_c downto lo_abb_c)) else '0';
wren <= acc_en and wren_i;
rden <= acc_en and rden_i;
-- Write access -------------------------------------------------------------
-- -----------------------------------------------------------------------------
wr_access: process(clk_i)
begin
if rising_edge(clk_i) then
sw_trig <= '0';
ack_trig <= '0';
if (wren = '1') then
irq_sel <= data_i(ctrl_irq_sel2_c downto ctrl_irq_sel0_c);
enable <= data_i(ctrl_en_c);
irq_enable <= data_i(ctrl_en_irq7_c downto ctrl_en_irq0_c);
-- irq_sel options --
sw_trig <= data_i(ctrl_sw_irq_c);
ack_trig <= data_i(ctrl_ack_irq_c);
end if;
end if;
end process wr_access;
-- Get external/software interrupt request ----------------------------------
-- -----------------------------------------------------------------------------
ext_irq_source_sync: process(clk_i)
begin
if rising_edge(clk_i) then
irq_sync <= ext_irq_i;
irq_raw <= irq_sync; -- sync to avoid metastability
end if;
end process ext_irq_source_sync;
sw_irq_source: process(sw_trig, irq_sel)
variable sw_irq_v : std_ulogic_vector(3 downto 0);
begin
sw_irq_v := sw_trig & irq_sel;
case sw_irq_v is
when "1000" => sw_irq <= "00000001";
when "1001" => sw_irq <= "00000010";
when "1010" => sw_irq <= "00000100";
when "1011" => sw_irq <= "00001000";
when "1100" => sw_irq <= "00010000";
when "1101" => sw_irq <= "00100000";
when "1110" => sw_irq <= "01000000";
when "1111" => sw_irq <= "10000000";
when others => sw_irq <= "00000000";
end case;
end process sw_irq_source;
-- only pass enabled interrupt sources --
irq_valid <= (irq_raw or sw_irq) and irq_enable;
-- IRQ controller core ------------------------------------------------------
-- -----------------------------------------------------------------------------
irq_core: process(clk_i)
begin
if rising_edge(clk_i) then
-- ack output --
ext_ack_o <= ack_mask;
-- irq buffer --
for i in 0 to 7 loop
-- keep requests until they are acknowledged
-- clear buffer when unit is disabled
irq_buf(i) <= (irq_buf(i) or irq_valid(i)) and enable and (not ack_mask(i));
end loop; -- i
-- mini state FSM --
cpu_irq_o <= '0';
if (state = '0') or (enable = '0') then -- idle or deactivated
state <= '0';
if (irq_fire = '1') and (enable = '1') then -- valid active IRQ
irq_src_reg <= irq_src; -- capture source
cpu_irq_o <= '1'; -- trigger CPU interrupt
state <= '1'; -- go to active IRQ state
end if;
else -- active interrupt request
if (ack_trig = '1') or (enable = '0') then -- ack or disable
state <= '0';
end if;
end if;
end if;
end process irq_core;
-- anybody firing? --
irq_fire <= or_all_f(irq_buf);
-- get interrupt priority --
irq_src <= "000" when (irq_buf(0) = '1') else
"001" when (irq_buf(1) = '1') else
"010" when (irq_buf(2) = '1') else
"011" when (irq_buf(3) = '1') else
"100" when (irq_buf(4) = '1') else
"101" when (irq_buf(5) = '1') else
"110" when (irq_buf(6) = '1') else
"111";-- when (irq_buf(7) = '1') else "---";
-- ACK priority decoder -----------------------------------------------------
-- -----------------------------------------------------------------------------
ack_priority_dec: process(state, ack_trig, irq_src_reg)
variable irq_ack_v : std_ulogic_vector(3 downto 0);
begin
irq_ack_v := (ack_trig and state) & irq_src_reg;
case irq_ack_v is
when "1000" => ack_mask <= "00000001";
when "1001" => ack_mask <= "00000010";
when "1010" => ack_mask <= "00000100";
when "1011" => ack_mask <= "00001000";
when "1100" => ack_mask <= "00010000";
when "1101" => ack_mask <= "00100000";
when "1110" => ack_mask <= "01000000";
when "1111" => ack_mask <= "10000000";
when others => ack_mask <= "00000000";
end case;
end process ack_priority_dec;
-- Read access --------------------------------------------------------------
-- -----------------------------------------------------------------------------
rd_access: process(clk_i)
begin
if rising_edge(clk_i) then
data_o <= (others => '0');
if (rden = '1') then
data_o(ctrl_irq_sel2_c downto ctrl_irq_sel0_c) <= irq_src_reg;
data_o(ctrl_en_irq7_c downto ctrl_en_irq0_c) <= irq_enable;
data_o(ctrl_en_c) <= enable;
end if;
end if;
end process rd_access;
end neo430_exirq_rtl;
|
bsd-3-clause
|
91a04f9fa821fcea0baafa915d941292
| 0.496168 | 4.143566 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc512.vhd
| 4 | 2,266 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc512.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b02x00p07n01i00512ent IS
END c03s02b02x00p07n01i00512ent;
ARCHITECTURE c03s02b02x00p07n01i00512arch OF c03s02b02x00p07n01i00512ent IS
type DATE is
record
DAY,D1,D2 : Integer;
MONTH : Integer;
YEAR : Integer;
end record;
type DAT is
record
DAY : Integer;
D1 : Integer;
D2 : Integer;
MONTH : Integer;
YEAR : Integer;
end record;
BEGIN
TESTING: PROCESS
variable V1 : DATE := (5,5,5,10,15) ;
variable V2 : DAT := (5,5,5,10,15);
BEGIN
assert NOT(V1.D1 = V2.D1 and V1.D2 = V2.D2 and V1.DAY = V2.DAY and V1.Month = V2.Month and V1.Year = V2.Year )
report "***PASSED TEST: c03s02b02x00p07n01i00512"
severity NOTE;
assert (V1.D1 = V2.D1 and V1.D2 = V2.D2 and V1.DAY = V2.DAY and V1.Month = V2.Month and V1.Year = V2.Year )
report "***FAILED TEST: c03s02b02x00p07n01i00512 - An element declaration with several identifiers is equivalent to a sequence of single element declarations."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b02x00p07n01i00512arch;
|
gpl-2.0
|
1a53cb2c814b793db0952de87290745b
| 0.652692 | 3.407519 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/and_or_inv.vhd
| 4 | 1,427 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
entity and_or_inv is
port ( a1, a2, b1, b2 : in bit := '1';
y : out bit );
end entity and_or_inv;
-- end not in book
architecture primitive of and_or_inv is
signal and_a, and_b : bit;
signal or_a_b : bit;
begin
and_gate_a : process (a1, a2) is
begin
and_a <= a1 and a2;
end process and_gate_a;
and_gate_b : process (b1, b2) is
begin
and_b <= b1 and b2;
end process and_gate_b;
or_gate : process (and_a, and_b) is
begin
or_a_b <= and_a or and_b;
end process or_gate;
inv : process (or_a_b) is
begin
y <= not or_a_b;
end process inv;
end architecture primitive;
|
gpl-2.0
|
88e17af201daf24fbbfcaa26ddf204ae
| 0.681149 | 3.318605 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tovec-b.vhd
| 4 | 2,020 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_tovec-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
architecture behavioral of to_vector is
begin
behavior : process (r) is
variable temp : integer range -2**15 to 2**15 - 1;
variable negative : boolean;
variable result : std_ulogic_vector(vec'range);
begin
-- scale to [-2**15, +2**15) and convert to integer
if r * real(2**15) < real(-2**15) then
temp := -2**15;
elsif r * real(2**15) >= real(2**15 - 1) then
temp := 2**15 - 1;
else
temp := integer(r * real(2**15));
end if;
negative := temp < 0;
if negative then
temp := -(temp + 1);
end if;
result := (others => '0');
for index in result'reverse_range loop
result(index) := to_X01(bit'val(temp rem 2));
temp := temp / 2;
exit when temp = 0;
end loop;
if negative then
result := not result;
result(result'left) := '1';
end if;
vec <= result;
end process behavior;
end architecture behavioral;
|
gpl-2.0
|
85a3b3b3972a16c8815253fb4402300a
| 0.575743 | 3.960784 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2420.vhd
| 4 | 1,937 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2420.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x01p01n01i02420ent IS
END c07s03b02x01p01n01i02420ent;
ARCHITECTURE c07s03b02x01p01n01i02420arch OF c07s03b02x01p01n01i02420ent IS
BEGIN
TESTING: PROCESS
type rec is record
ele_1 : integer;
ele_2 : real;
ele_3 : boolean;
ele_4 : integer;
end record;
variable p : rec :=
(ele_3 => true,
ele_1 => 1,
ele_2 => 3.4,
ele_5 => 12); -- Failure_here
-- ele_5 does not belong to the record type.
BEGIN
assert FALSE
report "***FAILED TEST: c07s03b02x01p01n01i02420 - Element names must denote elments of the record type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x01p01n01i02420arch;
|
gpl-2.0
|
a9310649c536adbe20501d2d14eb63a1
| 0.627259 | 3.790607 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/control_processor.vhd
| 4 | 1,897 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
entity control_processor is
generic ( Tpd : delay_length := 3 ns );
end entity control_processor;
-- end not in book
architecture rtl of control_processor is
type func_code is (add, subtract);
signal op1, op2, dest : integer;
signal Z_flag : boolean;
signal func : func_code;
-- . . .
begin
alu : process is
procedure do_arith_op is
variable result : integer;
begin
case func is
when add =>
result := op1 + op2;
when subtract =>
result := op1 - op2;
end case;
dest <= result after Tpd;
Z_flag <= result = 0 after Tpd;
end procedure do_arith_op;
begin
-- . . .
do_arith_op;
-- . . .
-- not in book
wait on op1, op2, func;
-- end not in book
end process alu;
-- . . .
-- not in book
stimulus : process is
begin
op1 <= 0; op2 <= 0; wait for 10 ns;
op1 <= 10; op2 <= 3; wait for 10 ns;
func <= subtract; wait for 10 ns;
op2 <= 10; wait for 10 ns;
wait;
end process stimulus;
-- end not in book
end architecture rtl;
|
gpl-2.0
|
b3d91f9ab0e0e2517081e23cb5301952
| 0.638376 | 3.726916 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_17.vhd
| 4 | 1,914 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_17.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity ch_05_17 is
end entity ch_05_17;
----------------------------------------------------------------
architecture test of ch_05_17 is
signal s, r, q, q_n : bit := '0';
begin
q <= '1' when s = '1' else
'0' when r = '1';
q_n <= '0' when s = '1' else
'1' when r = '1';
-- code from book:
check : process is
begin
assert not (s = '1' and r = '1')
report "Incorrect use of S_R_flip_flop: s and r both '1'";
wait on s, r;
end process check;
-- end of code from book
stimulus : process is
begin
wait for 10 ns;
s <= '1'; wait for 10 ns;
s <= '0'; wait for 10 ns;
r <= '1'; wait for 10 ns;
r <= '0'; wait for 10 ns;
s <= '1'; wait for 10 ns;
r <= '1'; wait for 10 ns;
s <= '0'; wait for 10 ns;
r <= '0'; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
2421c2b30db8557520860d01dbce8bce
| 0.554859 | 3.55102 | false | false | false | false |
stnolting/neo430
|
rtl/core/neo430_boot_rom.vhd
| 1 | 5,946 |
-- #################################################################################################
-- # << NEO430 - Bootloader ROM >> #
-- # ********************************************************************************************* #
-- # This memory includes the in-place executable image of the NEO430 bootloader. See the #
-- # processor's documentary to get more information. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
use neo430.neo430_bootloader_image.all; -- this file is generated by the image generator
entity neo430_boot_rom is
port (
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_o : out std_ulogic_vector(15 downto 0) -- data out
);
end neo430_boot_rom;
architecture neo430_boot_rom_rtl of neo430_boot_rom is
-- local types --
type boot_img_t is array (0 to boot_size_c/2-1) of std_ulogic_vector(15 downto 0);
-- init function --
impure function init_boot_rom(init : bootloader_init_image_t) return boot_img_t is
variable mem_v : boot_img_t;
begin
for i in 0 to boot_size_c/2-1 loop
mem_v(i) := init(i);
end loop; -- i
return mem_v;
end function init_boot_rom;
-- local signals --
signal acc_en : std_ulogic;
signal rden : std_ulogic;
signal rdata : std_ulogic_vector(15 downto 0);
signal addr : natural range 0 to boot_size_c/2-1;
-- bootloader image --
constant boot_img : boot_img_t := init_boot_rom(bootloader_init_image);
begin
-- Access Control -----------------------------------------------------------
-- -----------------------------------------------------------------------------
acc_en <= '1' when (addr_i >= boot_base_c) and (addr_i < std_ulogic_vector(unsigned(boot_base_c) + boot_size_c)) else '0';
addr <= to_integer(unsigned(addr_i(index_size_f(boot_size_c/2) downto 1))); -- word aligned
-- Memory Access ------------------------------------------------------------
-- -----------------------------------------------------------------------------
mem_file_access: process(clk_i)
begin
-- check max size --
if (boot_size_c > boot_max_size_c) then
assert false report "Boot ROM size out of range! Max 2kB!" severity error;
end if;
if rising_edge(clk_i) then
rden <= rden_i and acc_en;
if (acc_en = '1') then -- reduce switching activity when not accessed
rdata <= boot_img(addr);
end if;
end if;
end process mem_file_access;
-- output gate --
data_o <= rdata when (rden = '1') else (others => '0');
end neo430_boot_rom_rtl;
|
bsd-3-clause
|
b31a04150cfae476773a8af05cf4d819
| 0.457787 | 5.077711 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_03.vhd
| 4 | 2,599 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_ch_03_03.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity ch_03_03 is
end entity ch_03_03;
architecture test of ch_03_03 is
begin
process_3_1_c : process is
type mode_type is (immediate, other_mode);
type opcode_type is (load, add, subtract, other_opcode);
variable mode : mode_type;
variable opcode : opcode_type;
constant immed_operand : integer := 1;
constant memory_operand : integer := 2;
constant address_operand : integer := 3;
variable operand : integer;
procedure procedure_3_1_c is
begin
-- code from book:
if mode = immediate then
operand := immed_operand;
elsif opcode = load or opcode = add or opcode = subtract then
operand := memory_operand;
else
operand := address_operand;
end if;
-- end of code from book
end procedure_3_1_c;
begin
mode := immediate;
procedure_3_1_c;
mode := other_mode;
opcode := load;
procedure_3_1_c;
opcode := add;
procedure_3_1_c;
opcode := subtract;
procedure_3_1_c;
opcode := other_opcode;
procedure_3_1_c;
wait;
end process process_3_1_c;
end architecture test;
|
gpl-2.0
|
d42212fc1d1c05185a3fc8e3ae298bc3
| 0.513659 | 4.760073 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc377.vhd
| 4 | 1,912 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc377.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p03n03i00377ent IS
END c03s02b01x01p03n03i00377ent;
ARCHITECTURE c03s02b01x01p03n03i00377arch OF c03s02b01x01p03n03i00377ent IS
type it2 is array (bit range '0' to '1') of bit;
BEGIN
TESTING: PROCESS
variable k : it2;
BEGIN
k('0') := '1';
k('1') := '0';
assert NOT ( k('0') = '1' and
k('1') = '0')
report "***PASSED TEST: c03s02b01x01p03n03i00377"
severity NOTE;
assert ( k('0') = '1' and
k('1') = '0')
report "***FAILED TEST: c03s02b01x01p03n03i00377 - The index constraint must provide a discrete range for each index of the array type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p03n03i00377arch;
|
gpl-2.0
|
8a67474e9c57e51648362a009ceb3b1d
| 0.636506 | 3.560521 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1910.vhd
| 4 | 8,207 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1910.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b00x00p09n01i01910ent IS
END c07s02b00x00p09n01i01910ent;
ARCHITECTURE c07s02b00x00p09n01i01910arch OF c07s02b00x00p09n01i01910ent IS
BEGIN
TESTING: PROCESS
-- Local declarations.
variable ValueB1 : BOOLEAN;
variable ValueB2 : BOOLEAN;
variable ValueB3 : BOOLEAN;
variable ValueB4 : BOOLEAN;
variable ValueI1, SameValueI1, DifferentValueI1 : INTEGER;
variable ValueI2, SameValueI2, DifferentValueI2 : INTEGER;
variable ValueI3, SameValueI3, DifferentValueI3 : INTEGER;
variable ValueI4, SameValueI4, DifferentValueI4 : INTEGER;
variable ValueI5, SameValueI5, DifferentValueI5 : INTEGER;
variable ValueI6, SameValueI6, DifferentValueI6 : INTEGER;
variable ValueI7, SameValueI7, DifferentValueI7 : INTEGER;
BEGIN
-- "+" (addition) operator, and the "-" operator.
-- - NOTE: The following expression would not be able to parse
-- if the precedence used was such that the "=" operator
-- had a higher precedence than the "+" operator. Thus,
-- if this parses you are guaranteed that the precedence
-- relative to these two levels is correctly defined.Same
-- goes for the "-" operator.
ValueB1 := 1 + 3 = 3 + 1;
assert (ValueB1)
report "The expression has not been processed correctly.(5)";
ValueB2 := 3 - 1 = 5 - 3;
assert (ValueB2)
report "The expression has not been processed correctly.(6)";
-- "+" (sign) operator, and the "-" (sign) operator.
-- - NOTE: The following expression would not be able to parse
-- if the precedence used was such that the "=" operator
-- had a higher precedence than the "+" operator. Thus,
-- if this parses you are guaranteed that the precedence
-- relative to these two levels is correctly defined.Same
-- goes for the "-" operator.
ValueB3 := + 1 = + 1;
assert (ValueB3)
report "The expression has not been processed correctly.(7)";
ValueB4 := - 3 = - 3;
assert (ValueB4)
report "The expression has not been processed correctly.(8)";
ValueI1 := -3 + 4;
SameValueI1 := (-3) + 4;
DifferentValueI1:= -(3 + 4);
assert (ValueI1 = SameValueI1)
report "Values of lower precedence associated before those of higher precedence.(9)";
assert (ValueI1 /= DifferentValueI1)
report "Values of lower precedence associated before those of higher precedence.(10)";
-- "*" operator.
ValueI2 := 3 + 4 * 5;
SameValueI2 := 3 + (4 * 5);
DifferentValueI2:= (3 + 4) * 5;
assert (ValueI2 = SameValueI2)
report "Values of lower precedence associated before those of higher precedence.(13)";
assert (ValueI2 /= DifferentValueI2)
report "Values of lower precedence associated before those of higher precedence.(14)";
-- "/" operator.
ValueI3 := 5 + 10 / 5;
SameValueI3 := 5 + (10 / 5);
DifferentValueI3:= (5 + 10) / 5;
assert (ValueI3 = SameValueI3)
report "Values of lower precedence associated before those of higher precedence.(15)";
assert (ValueI3 /= DifferentValueI3)
report "Values of lower precedence associated before those of higher precedence.(16)";
-- "mod" operator.
ValueI4 := 4 + 11 mod 3;
SameValueI4 := 4 + (11 mod 3);
DifferentValueI4:= (4 + 11) mod 3;
assert (ValueI4 = SameValueI4)
report "Values of lower precedence associated before those of higher precedence.(17)";
assert (ValueI4 /= DifferentValueI4)
report "Values of lower precedence associated before those of higher precedence.(18)";
-- "rem" operator.
ValueI5 := 4 + 11 rem 3;
SameValueI5 := 4 + (11 rem 3);
DifferentValueI5:= (4 + 11) rem 3;
assert (ValueI5 = SameValueI5)
report "Values of lower precedence associated before those of higher precedence.(19)";
assert (ValueI5 /= DifferentValueI5)
report "Values of lower precedence associated before those of higher precedence.(20)";
-- "**" operator.
ValueI6 := 3 * 4 ** 2;
SameValueI6 := 3 * (4 ** 2);
DifferentValueI6:= (3 * 4) ** 2;
assert (ValueI6 = SameValueI6)
report "Values of lower precedence associated before those of higher precedence.(21)";
assert (ValueI6 /= DifferentValueI6)
report "Values of lower precedence associated before those of higher precedence.(22)";
-- "abs" operator.
ValueI7 := abs (-5) * (-7);
SameValueI7 := (abs (-5)) * (-7);
DifferentValueI7:= abs((-5) * (-7));
assert (ValueI7 = SameValueI7)
report "Values of lower precedence associated before those of higher precedence.(23)";
assert (ValueI7 /= DifferentValueI7)
report "Values of lower precedence associated before those of higher precedence.(24)";
wait for 5 ns;
assert NOT( (ValueB1) and
(ValueB2) and
(ValueB3) and
(ValueB4) and
(ValueI1 = SameValueI1) and
(ValueI1 /= DifferentValueI1) and
(ValueI2 = SameValueI2) and
(ValueI2 /= DifferentValueI2) and
(ValueI3 = SameValueI3) and
(ValueI3 /= DifferentValueI3) and
(ValueI4 = SameValueI4) and
(ValueI4 /= DifferentValueI4) and
(ValueI5 = SameValueI5) and
(ValueI5 /= DifferentValueI5) and
(ValueI6 = SameValueI6) and
(ValueI6 /= DifferentValueI6) and
(ValueI7 = SameValueI7) and
(ValueI7 /= DifferentValueI7) )
report "***PASSED TEST: c07s02b00x00p09n01i01910"
severity NOTE;
assert ( (ValueB1) and
(ValueB2) and
(ValueB3) and
(ValueB4) and
(ValueI1 = SameValueI1) and
(ValueI1 /= DifferentValueI1) and
(ValueI2 = SameValueI2) and
(ValueI2 /= DifferentValueI2) and
(ValueI3 = SameValueI3) and
(ValueI3 /= DifferentValueI3) and
(ValueI4 = SameValueI4) and
(ValueI4 /= DifferentValueI4) and
(ValueI5 = SameValueI5) and
(ValueI5 /= DifferentValueI5) and
(ValueI6 = SameValueI6) and
(ValueI6 /= DifferentValueI6) and
(ValueI7 = SameValueI7) and
(ValueI7 /= DifferentValueI7) )
report "***FAILED TEST: c07s02b00x00p09n01i01910 - Operators of higher precedence are associated with their operands before operators of lower precedence."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b00x00p09n01i01910arch;
|
gpl-2.0
|
f3ecc1faf447e9b2b5333983d7468b4e
| 0.598879 | 4.38877 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_divider/Gura/Modular/celda_U.vhd
| 1 | 1,350 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity celda_U is
generic(
NUM_BITS : positive := 163
);
port(
U : in STD_LOGIC_VECTOR(NUM_BITS downto 0);
V : in STD_LOGIC_VECTOR(NUM_BITS downto 0);
c0 : in STD_LOGIC;
c1 : in STD_LOGIC;
toU : out STD_LOGIC_VECTOR(NUM_BITS downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of celda_U is
----------------------------------------------------------------------------------------------------
signal U1 : STD_LOGIC_VECTOR(NUM_BITS downto 0);
signal V1 : STD_LOGIC_VECTOR(NUM_BITS downto 0);
begin
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
U1 <= U when c0 = '1' else
(others => '0');
V1 <= V when c1 = '1' else
(others => '0');
toU <= U1 xor V1;
end behave;
|
gpl-3.0
|
e2bd29f8119d7a7f9e9f6ee62c857294
| 0.325926 | 4.80427 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1422.vhd
| 4 | 1,942 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1422.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s06b00x00p04n01i01422ent IS
END c08s06b00x00p04n01i01422ent;
ARCHITECTURE c08s06b00x00p04n01i01422arch OF c08s06b00x00p04n01i01422ent IS
BEGIN
TESTING: PROCESS
procedure proc1(
constant p : in STRING;
variable l : out INTEGER
) is
begin
l := P'LENGTH;
end;
constant C : STRING := "Testing";
variable l : INTEGER := c'LENGTH - 1;
BEGIN
assert l /= c'LENGTH;
proc1(c, l);
assert NOT(l = c'LENGTH)
report "***PASSED TEST: c08s06b00x00p04n01i01422"
severity NOTE;
assert (l = c'LENGTH)
report "***FAILED TEST: c08s06b00x00p04n01i01422 - Sequential procedure call test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s06b00x00p04n01i01422arch;
|
gpl-2.0
|
cf1ce08d88395c7c538df57985cfef41
| 0.651905 | 3.720307 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2233.vhd
| 4 | 2,175 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2233.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02233ent IS
END c07s02b06x00p01n01i02233ent;
ARCHITECTURE c07s02b06x00p01n01i02233arch OF c07s02b06x00p01n01i02233ent IS
BEGIN
TESTING: PROCESS
-- user defined physical types.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
end units;
variable DISTV : DISTANCE;
variable k : integer;
BEGIN
k := DISTV mod 1 A;
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02233 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02233arch;
|
gpl-2.0
|
c646789cc2f79620b59982d2ddb36134
| 0.613793 | 3.947368 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_04.vhd
| 4 | 1,667 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_fg_03_04.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity counter is
port ( clk, reset : in bit; count : out natural );
end entity counter;
architecture behavior of counter is
begin
incrementer : process is
variable count_value : natural := 0;
begin
count <= count_value;
loop
loop
wait until clk = '1' or reset = '1';
exit when reset = '1';
count_value := (count_value + 1) mod 16;
count <= count_value;
end loop;
-- at this point, reset = '1'
count_value := 0;
count <= count_value;
wait until reset = '0';
end loop;
end process incrementer;
end architecture behavior;
|
gpl-2.0
|
9150f7d69a43427adcdb0ab08475439f
| 0.60228 | 4.188442 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_Squarer/squarer_163.vhd
| 1 | 8,434 |
-- Author : Miguel Morales-Sandoval
-- Project : "Reconfigurable ECC
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2007.
--Squarer, solo logica combinacional,
--optimizado para el polinomio de reduccion que se este empleando,
-- funciona solo si el máximo grado del polinomio de reduccion D más 2 es menor a m.
-- Se trata básicamente de un multiplicador de digito combinacional. El tamaño del digito es D+2;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
-----------------------------------------------------------------------------------
entity squarer_163 is
generic(
NUM_BITS : positive := 163 -- 163, 233, 277, 283, 409, 571 -- Orden del campo finito
);
port(
-- clk : in std_logic;
-- en : in std_logic;
Ax : in std_logic_vector(NUM_BITS-1 downto 0);-- 2
C_out : out std_logic_vector(NUM_BITS-1 downto 0)-- A2_x = (A_x) mod Fx
);
end;
---------------------------------------------------------------------------------------------------
architecture behave of squarer_163 is
--constant F_x: std_logic_vector(NUM_BITS-1 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001001";
begin
C_out(162) <= ( Ax(81) xor Ax(159) ) xor Ax(161);
C_out(161) <= Ax(159) xor Ax(162);
C_out(160) <= ( Ax(80) xor Ax(158) ) xor Ax(160);
C_out(159) <= Ax(158) xor Ax(161);
C_out(158) <= ( Ax(79) xor Ax(157) ) xor Ax(159);
C_out(157) <= Ax(157) xor Ax(160);
C_out(156) <= ( Ax(78) xor Ax(156) ) xor Ax(158);
C_out(155) <= Ax(156) xor Ax(159);
C_out(154) <= ( Ax(77) xor Ax(155) ) xor Ax(157);
C_out(153) <= Ax(155) xor Ax(158);
C_out(152) <= ( Ax(76) xor Ax(154) ) xor Ax(156);
C_out(151) <= Ax(154) xor Ax(157);
C_out(150) <= ( Ax(75) xor Ax(153) ) xor Ax(155);
C_out(149) <= Ax(153) xor Ax(156);
C_out(148) <= ( Ax(74) xor Ax(152) ) xor Ax(154);
C_out(147) <= Ax(152) xor Ax(155);
C_out(146) <= ( Ax(73) xor Ax(151) ) xor Ax(153);
C_out(145) <= Ax(151) xor Ax(154);
C_out(144) <= ( Ax(72) xor Ax(150) ) xor Ax(152);
C_out(143) <= Ax(150) xor Ax(153);
C_out(142) <= ( Ax(71) xor Ax(149) ) xor Ax(151);
C_out(141) <= Ax(149) xor Ax(152);
C_out(140) <= ( Ax(70) xor Ax(148) ) xor Ax(150);
C_out(139) <= Ax(148) xor Ax(151);
C_out(138) <= ( Ax(69) xor Ax(147) ) xor Ax(149);
C_out(137) <= Ax(147) xor Ax(150);
C_out(136) <= ( Ax(68) xor Ax(146) ) xor Ax(148);
C_out(135) <= Ax(146) xor Ax(149);
C_out(134) <= ( Ax(67) xor Ax(145) ) xor Ax(147);
C_out(133) <= Ax(145) xor Ax(148);
C_out(132) <= ( Ax(66) xor Ax(144) ) xor Ax(146);
C_out(131) <= Ax(144) xor Ax(147);
C_out(130) <= ( Ax(65) xor Ax(143) ) xor Ax(145);
C_out(129) <= Ax(143) xor Ax(146);
C_out(128) <= ( Ax(64) xor Ax(142) ) xor Ax(144);
C_out(127) <= Ax(142) xor Ax(145);
C_out(126) <= ( Ax(63) xor Ax(141) ) xor Ax(143);
C_out(125) <= Ax(141) xor Ax(144);
C_out(124) <= ( Ax(62) xor Ax(140) ) xor Ax(142);
C_out(123) <= Ax(140) xor Ax(143);
C_out(122) <= ( Ax(61) xor Ax(139) ) xor Ax(141);
C_out(121) <= Ax(139) xor Ax(142);
C_out(120) <= ( Ax(60) xor Ax(138) ) xor Ax(140);
C_out(119) <= Ax(138) xor Ax(141);
C_out(118) <= ( Ax(59) xor Ax(137) ) xor Ax(139);
C_out(117) <= Ax(137) xor Ax(140);
C_out(116) <= ( Ax(58) xor Ax(136) ) xor Ax(138);
C_out(115) <= Ax(136) xor Ax(139);
C_out(114) <= ( Ax(57) xor Ax(135) ) xor Ax(137);
C_out(113) <= Ax(135) xor Ax(138);
C_out(112) <= ( Ax(56) xor Ax(134) ) xor Ax(136);
C_out(111) <= Ax(134) xor Ax(137);
C_out(110) <= ( Ax(55) xor Ax(133) ) xor Ax(135);
C_out(109) <= Ax(133) xor Ax(136);
C_out(108) <= ( Ax(54) xor Ax(132) ) xor Ax(134);
C_out(107) <= Ax(132) xor Ax(135);
C_out(106) <= ( Ax(53) xor Ax(131) ) xor Ax(133);
C_out(105) <= Ax(131) xor Ax(134);
C_out(104) <= ( Ax(52) xor Ax(130) ) xor Ax(132);
C_out(103) <= Ax(130) xor Ax(133);
C_out(102) <= ( Ax(51) xor Ax(129) ) xor Ax(131);
C_out(101) <= Ax(129) xor Ax(132);
C_out(100) <= ( Ax(50) xor Ax(128) ) xor Ax(130);
C_out(99) <= Ax(128) xor Ax(131);
C_out(98) <= ( Ax(49) xor Ax(127) ) xor Ax(129);
C_out(97) <= Ax(127) xor Ax(130);
C_out(96) <= ( Ax(48) xor Ax(126) ) xor Ax(128);
C_out(95) <= Ax(126) xor Ax(129);
C_out(94) <= ( Ax(47) xor Ax(125) ) xor Ax(127);
C_out(93) <= Ax(125) xor Ax(128);
C_out(92) <= ( Ax(46) xor Ax(124) ) xor Ax(126);
C_out(91) <= Ax(124) xor Ax(127);
C_out(90) <= ( Ax(45) xor Ax(123) ) xor Ax(125);
C_out(89) <= Ax(123) xor Ax(126);
C_out(88) <= ( Ax(44) xor Ax(122) ) xor Ax(124);
C_out(87) <= Ax(122) xor Ax(125);
C_out(86) <= ( Ax(43) xor Ax(121) ) xor Ax(123);
C_out(85) <= Ax(121) xor Ax(124);
C_out(84) <= ( Ax(42) xor Ax(120) ) xor Ax(122);
C_out(83) <= Ax(120) xor Ax(123);
C_out(82) <= ( Ax(41) xor Ax(119) ) xor Ax(121);
C_out(81) <= Ax(119) xor Ax(122);
C_out(80) <= ( Ax(40) xor Ax(118) ) xor Ax(120);
C_out(79) <= Ax(118) xor Ax(121);
C_out(78) <= ( Ax(39) xor Ax(117) ) xor Ax(119);
C_out(77) <= Ax(117) xor Ax(120);
C_out(76) <= ( Ax(38) xor Ax(116) ) xor Ax(118);
C_out(75) <= Ax(116) xor Ax(119);
C_out(74) <= ( Ax(37) xor Ax(115) ) xor Ax(117);
C_out(73) <= Ax(115) xor Ax(118);
C_out(72) <= ( Ax(36) xor Ax(114) ) xor Ax(116);
C_out(71) <= Ax(114) xor Ax(117);
C_out(70) <= ( Ax(35) xor Ax(113) ) xor Ax(115);
C_out(69) <= Ax(113) xor Ax(116);
C_out(68) <= ( Ax(34) xor Ax(112) ) xor Ax(114);
C_out(67) <= Ax(112) xor Ax(115);
C_out(66) <= ( Ax(33) xor Ax(111) ) xor Ax(113);
C_out(65) <= Ax(111) xor Ax(114);
C_out(64) <= ( Ax(32) xor Ax(110) ) xor Ax(112);
C_out(63) <= Ax(110) xor Ax(113);
C_out(62) <= ( Ax(31) xor Ax(109) ) xor Ax(111);
C_out(61) <= Ax(109) xor Ax(112);
C_out(60) <= ( Ax(30) xor Ax(108) ) xor Ax(110);
C_out(59) <= Ax(108) xor Ax(111);
C_out(58) <= ( Ax(29) xor Ax(107) ) xor Ax(109);
C_out(57) <= Ax(107) xor Ax(110);
C_out(56) <= ( Ax(28) xor Ax(106) ) xor Ax(108);
C_out(55) <= Ax(106) xor Ax(109);
C_out(54) <= ( Ax(27) xor Ax(105) ) xor Ax(107);
C_out(53) <= Ax(105) xor Ax(108);
C_out(52) <= ( Ax(26) xor Ax(104) ) xor Ax(106);
C_out(51) <= Ax(104) xor Ax(107);
C_out(50) <= ( Ax(25) xor Ax(103) ) xor Ax(105);
C_out(49) <= Ax(103) xor Ax(106);
C_out(48) <= ( Ax(24) xor Ax(102) ) xor Ax(104);
C_out(47) <= Ax(102) xor Ax(105);
C_out(46) <= ( Ax(23) xor Ax(101) ) xor Ax(103);
C_out(45) <= Ax(101) xor Ax(104);
C_out(44) <= ( Ax(22) xor Ax(100) ) xor Ax(102);
C_out(43) <= Ax(100) xor Ax(103);
C_out(42) <= ( Ax(21) xor Ax(99) ) xor Ax(101);
C_out(41) <= Ax(99) xor Ax(102);
C_out(40) <= ( Ax(20) xor Ax(98) ) xor Ax(100);
C_out(39) <= Ax(98) xor Ax(101);
C_out(38) <= ( Ax(19) xor Ax(97) ) xor Ax(99);
C_out(37) <= Ax(97) xor Ax(100);
C_out(36) <= ( Ax(18) xor Ax(96) ) xor Ax(98);
C_out(35) <= Ax(96) xor Ax(99);
C_out(34) <= ( Ax(17) xor Ax(95) ) xor Ax(97);
C_out(33) <= Ax(95) xor Ax(98);
C_out(32) <= ( Ax(16) xor Ax(94) ) xor Ax(96);
C_out(31) <= Ax(94) xor Ax(97);
C_out(30) <= ( Ax(15) xor Ax(93) ) xor Ax(95);
C_out(29) <= Ax(93) xor Ax(96);
C_out(28) <= ( Ax(14) xor Ax(92) ) xor Ax(94);
C_out(27) <= Ax(92) xor Ax(95);
C_out(26) <= ( Ax(13) xor Ax(91) ) xor Ax(93);
C_out(25) <= Ax(91) xor Ax(94);
C_out(24) <= ( Ax(12) xor Ax(90) ) xor Ax(92);
C_out(23) <= Ax(90) xor Ax(93);
C_out(22) <= ( Ax(11) xor Ax(89) ) xor Ax(91);
C_out(21) <= Ax(89) xor Ax(92);
C_out(20) <= ( Ax(10) xor Ax(88) ) xor Ax(90);
C_out(19) <= Ax(88) xor Ax(91);
C_out(18) <= ( Ax(9) xor Ax(87) ) xor Ax(89);
C_out(17) <= Ax(87) xor Ax(90);
C_out(16) <= ( Ax(8) xor Ax(86) ) xor Ax(88);
C_out(15) <= Ax(86) xor Ax(89);
C_out(14) <= ( Ax(7) xor Ax(85) ) xor Ax(87);
C_out(13) <= Ax(85) xor Ax(88);
C_out(12) <= ( Ax(6) xor Ax(84) ) xor (Ax(86) xor Ax(162));
C_out(11) <= Ax(84) xor Ax(87);
C_out(10) <= Ax(5) xor Ax(83) xor Ax(85) xor Ax(161) xor Ax(162);
C_out(9) <= Ax(83) xor Ax(86);
C_out(8) <= Ax(4) xor Ax(82) xor Ax(84) xor Ax(160) xor Ax(161);
C_out(7) <= Ax(82) xor Ax(85);
C_out(6) <= Ax(3) xor Ax(83) xor Ax(160) xor Ax(161);
C_out(5) <= Ax(84) xor Ax(161) xor Ax(162);
C_out(4) <= Ax(2) xor Ax(82) xor Ax(160);
C_out(3) <= Ax(83) xor Ax(160) xor Ax(161);
C_out(2) <= Ax(1) xor Ax(161);
C_out(1) <= Ax(82) xor Ax(160) xor Ax(162);
C_out(0) <= Ax(0) xor Ax(160);
end behave;
|
gpl-3.0
|
7771f57139b1406e6bae7aef4bf12a63
| 0.539483 | 2.165896 | false | false | false | false |
beltagymohamed/FLOATING-POINT-MULTIPLIER-USING-FPGA
|
Multiplier/Project/VHDL/mul_int1.vhd
| 1 | 2,626 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mul_int1 is
port (in1: in std_logic_vector(23 downto 0);
in2: in std_logic_vector(23 downto 0);
clk,rst: in std_logic;
done:out std_logic;
res: out std_logic_vector(47 downto 0):=(others=>'0')
);
end mul_int1;
architecture arch_mul_int_1 of mul_int1 is
component shifter
port (in1: in std_logic_vector(23 downto 0);
in2: in unsigned(4 downto 0);
clk,rst: in std_logic;
res: out std_logic_vector (47 downto 0)
);
end component;
type RAM is array (23 downto 0) of std_logic_vector(47 downto 0);
signal out_shifters: RAM;
signal out_mux: RAM;
signal r:std_logic_vector(47 downto 0 ):=(others=>'0');
signal r1:unsigned(47 downto 0 ):=(others=>'0');
signal r2:unsigned(47 downto 0 ):=(others=>'0');
signal r3:unsigned(47 downto 0 ):=(others=>'0');
signal r4:unsigned(47 downto 0 ):=(others=>'0');
signal r5:unsigned(47 downto 0 ):=(others=>'0');
signal r6:unsigned(47 downto 0 ):=(others=>'0');
signal r7:unsigned(47 downto 0 ):=(others=>'0');
signal r8:unsigned(47 downto 0 ):=(others=>'0');
signal done1:std_logic:='0';
begin
res<=r;
r1<=unsigned(out_mux(0))+unsigned(out_mux(1))+unsigned(out_mux(2))+unsigned(out_mux(3));
r2<=unsigned(out_mux(4))+unsigned(out_mux(5))+unsigned(out_mux(6))+unsigned(out_mux(7));
r3<=unsigned(out_mux(8))+unsigned(out_mux(9))+unsigned(out_mux(10))+unsigned(out_mux(11));
r4<=unsigned(out_mux(12))+unsigned(out_mux(13))+unsigned(out_mux(14))+unsigned(out_mux(15));
r5<=unsigned(out_mux(16))+unsigned(out_mux(17))+unsigned(out_mux(18))+unsigned(out_mux(19));
r6<=unsigned(out_mux(20))+unsigned(out_mux(21))+unsigned(out_mux(22))+unsigned(out_mux(23));
r7<=r1+r2+r3;
r8<=r4+r5+r6;
SH1 : for N in 23 downto 0 generate
shifter_array : shifter
port map (in1=>in2,in2=>to_unsigned(N,5),clk=>clk,rst=>rst,res=>out_shifters(N));
end generate SH1;
MS : for M in 23 downto 0 generate
with in1(M) select
out_mux(M)<=out_shifters(M) when '1',
(others=>'0') when others;
end generate MS;
syncrho:process (clk, rst)
begin
if rst='0' then
r <= (others => '0');
done1<='0';
done<='0';
else
if (rising_edge(clk)) then
done1<='1';
done<=done1;
if (in1="100000000000000000000000" or in2="100000000000000000000000")then
r<=(others => '0');
else
r<=std_logic_vector(r7+r8);
end if;
end if;
end if;
end process;
end arch_mul_int_1;
|
mit
|
8f44b6579dd268797af4d0ff721a8493
| 0.610434 | 2.940649 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1637.vhd
| 4 | 6,844 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1637.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c08s12b00x00p05n01i01637pkg is
-- type declarations
type ENUM is ( E1, E2, E3 );
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
end units;
type ANARRAY is ARRAY( 0 to 1 ) of REAL;
type ARECORD is
RECORD
Field1 : INTEGER;
Field2 : BOOLEAN;
end record;
-- constant declarations
CONSTANT CONSTI : INTEGER := 47;
CONSTANT CONSTR : REAL := 47.0;
CONSTANT CONSTE : ENUM := E1;
CONSTANT CONSTD : DISTANCE := 1 A;
CONSTANT CONSTT : TIME := 1 hr;
CONSTANT CONSTB : BIT := '1';
CONSTANT CONSTS : SEVERITY_LEVEL := WARNING;
CONSTANT CONSTBO : BOOLEAN := FALSE;
CONSTANT CONSTA : ANARRAY := ( 3.1415926, 4.0 );
CONSTANT CONSTRE : ARECORD := ( Field1 => 2, Field2 => TRUE );
-- function declarations.
function funcI return INTEGER;
function funcR return REAL;
function funcE return ENUM;
function funcD return DISTANCE;
function funcT return TIME;
function funcB return BIT;
function funcS return SEVERITY_LEVEL;
function funcBO return BOOLEAN;
function funcA return ANARRAY;
function funcRE return ARECORD;
end c08s12b00x00p05n01i01637pkg;
package body c08s12b00x00p05n01i01637pkg is
function funcI return INTEGER is
begin
return( CONSTI );
end;
function funcR return REAL is
begin
return( CONSTR );
end;
function funcE return ENUM is
begin
return( CONSTE );
end;
function funcD return DISTANCE is
begin
return( CONSTD );
end;
function funcT return TIME is
begin
return( CONSTT );
end;
function funcB return BIT is
begin
return( CONSTB );
end;
function funcS return SEVERITY_LEVEL is
begin
return( CONSTS );
end;
function funcBO return BOOLEAN is
begin
return( CONSTBO );
end;
function funcA return ANARRAY is
begin
return( CONSTA );
end;
function funcRE return ARECORD is
begin
return( CONSTRE );
end;
end c08s12b00x00p05n01i01637pkg;
use work.c08s12b00x00p05n01i01637pkg.all;
ENTITY c08s12b00x00p05n01i01637ent IS
END c08s12b00x00p05n01i01637ent;
ARCHITECTURE c08s12b00x00p05n01i01637arch OF c08s12b00x00p05n01i01637ent IS
BEGIN
TESTING: PROCESS
-- variable declarations.
VARIABLE VARI : INTEGER;
VARIABLE VARR : REAL;
VARIABLE VARE : ENUM;
VARIABLE VARD : DISTANCE;
VARIABLE VART : TIME;
VARIABLE VARB : BIT;
VARIABLE VARS : SEVERITY_LEVEL;
VARIABLE VARBO : BOOLEAN;
VARIABLE VARA : ANARRAY;
VARIABLE VARRE : ARECORD;
BEGIN
-- Call each function, verify that it returns the proper value.
assert (funcI = CONSTI);
assert (funcR = CONSTR);
assert (funcE = CONSTE);
assert (funcD = CONSTD);
assert (funcT = CONSTT);
assert (funcB = CONSTB);
assert (funcS = CONSTS);
assert (funcBO = CONSTBO);
assert (funcA = CONSTA);
assert (funcRE = CONSTRE);
-- Assign function values to variables, make sure they're OK.
VARI := funcI;
VARR := funcR;
VARE := funcE;
VARD := funcD;
VART := funcT;
VARB := funcB;
VARS := funcS;
VARBO := funcBO;
VARA := funcA;
VARRE := funcRE;
assert (VARI = CONSTI);
assert (VARR = CONSTR);
assert (VARE = CONSTE);
assert (VARD = CONSTD);
assert (VART = CONSTT);
assert (VARB = CONSTB);
assert (VARS = CONSTS);
assert (VARBO = CONSTBO);
assert (VARA = CONSTA);
assert (VARRE = CONSTRE);
assert NOT((funcI = CONSTI) and
(funcR = CONSTR) and
(funcE = CONSTE) and
(funcD = CONSTD) and
(funcT = CONSTT) and
(funcB = CONSTB) and
(funcS = CONSTS) and
(funcBO = CONSTBO) and
(funcA = CONSTA) and
(funcRE = CONSTRE) and
(VARI = CONSTI) and
(VARR = CONSTR) and
(VARE = CONSTE) and
(VARD = CONSTD) and
(VART = CONSTT) and
(VARB = CONSTB) and
(VARS = CONSTS) and
(VARBO = CONSTBO) and
(VARA = CONSTA) and
(VARRE = CONSTRE))
report "***PASSED TEST: c08s12b00x00p05n01i01637"
severity NOTE;
assert ((funcI = CONSTI) and
(funcR = CONSTR) and
(funcE = CONSTE) and
(funcD = CONSTD) and
(funcT = CONSTT) and
(funcB = CONSTB) and
(funcS = CONSTS) and
(funcBO = CONSTBO) and
(funcA = CONSTA) and
(funcRE = CONSTRE) and
(VARI = CONSTI) and
(VARR = CONSTR) and
(VARE = CONSTE) and
(VARD = CONSTD) and
(VART = CONSTT) and
(VARB = CONSTB) and
(VARS = CONSTS) and
(VARBO = CONSTBO) and
(VARA = CONSTA) and
(VARRE = CONSTRE))
report "***FAILED TEST: c08s12b00x00p05n01i01637 - The value of the expression defines the result returned by the function."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p05n01i01637arch;
|
gpl-2.0
|
ee01066968512bc5c04ae3e5a079afa9
| 0.574226 | 3.741935 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/gear_rv_r.vhd
| 4 | 1,666 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.mechanical_systems.all;
entity gear_rv_r is
generic ( ratio : real := 1.0 ); -- gear ratio (revs of shaft2 for 1 rev of shaft1)
-- note: can be negative, if shaft polarity changes
port ( terminal rotv1 : rotational_v; -- rotational velocity terminal
terminal rot2 : rotational ); -- rotational angle terminal
end entity gear_rv_r;
----------------------------------------------------------------
architecture ideal of gear_rv_r is
quantity w1 across torq_vel through rotv1 to rotational_v_ref;
quantity theta across torq_ang through rot2 to rotational_ref;
begin
theta == ratio * w1'integ; -- output is angle (integral of w1)
torq_vel == -1.0 * torq_ang * ratio; -- input torque as function of output angle
end architecture ideal;
|
gpl-2.0
|
9fb05589afc1a7c78c214a79e7d2ca3f
| 0.672869 | 4.228426 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2960.vhd
| 4 | 4,579 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2960.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s03b00x00p02n01i02960pkg is
FUNCTION boo ( PARM_VAL : bit) RETURN integer;
FUNCTION boo ( PARM_VAL : bit_vector) RETURN integer;
FUNCTION boo ( PARM_VAL : boolean) RETURN integer;
FUNCTION boo ( PARM_VAL : character) RETURN integer;
FUNCTION boo ( PARM_VAL : integer) RETURN integer;
FUNCTION boo ( PARM_VAL : real) RETURN integer;
FUNCTION boo ( PARM_VAL : string) RETURN integer;
FUNCTION boo ( PARM_VAL : time) RETURN integer;
end c02s03b00x00p02n01i02960pkg;
package body c02s03b00x00p02n01i02960pkg is
FUNCTION boo ( PARM_VAL : bit) RETURN integer IS
BEGIN
assert false report "boo with BIT param" severity note;
RETURN 1;
END;
FUNCTION boo ( PARM_VAL : bit_vector) RETURN integer IS
BEGIN
assert false report "boo with BIT_VECTOR param" severity note;
RETURN 2;
END;
FUNCTION boo ( PARM_VAL : boolean) RETURN integer IS
BEGIN
assert false report "boo with BOOLEAN param" severity note;
RETURN 3;
END;
FUNCTION boo ( PARM_VAL : character) RETURN integer IS
BEGIN
assert false report "boo with CHARACTER param" severity note;
RETURN 4;
END;
FUNCTION boo ( PARM_VAL : integer) RETURN integer IS
BEGIN
assert false report "boo with INTEGER param" severity note;
RETURN 5;
END;
FUNCTION boo ( PARM_VAL : real) RETURN integer IS
BEGIN
assert false report "boo with REAL param" severity note;
RETURN 6;
END;
FUNCTION boo ( PARM_VAL : string) RETURN integer IS
BEGIN
assert false report "boo with STRING param" severity note;
RETURN 7;
END;
FUNCTION boo ( PARM_VAL : time) RETURN integer IS
BEGIN
assert false report "boo with TIME param" severity note;
RETURN 8;
END;
end c02s03b00x00p02n01i02960pkg;
ENTITY c02s03b00x00p02n01i02960ent IS
PORT (bb: INOUT bit;
bv: INOUT bit_vector(0 TO 3);
bo: INOUT boolean;
cc: INOUT character;
ii: INOUT integer;
rr: INOUT real;
ss: INOUT string(1 TO 6);
tt: INOUT time);
SUBTYPE bv_4 IS bit_vector(1 TO 4);
SUBTYPE bv_6 IS bit_vector(1 TO 6);
FUNCTION foo ( PARM_VAL : bv_4) RETURN bit_vector IS
BEGIN
assert false report "function foo in entity e" severity note;
RETURN PARM_VAL;
END;
END c02s03b00x00p02n01i02960ent;
use work.c02s03b00x00p02n01i02960pkg.all;
ARCHITECTURE c02s03b00x00p02n01i02960arch OF c02s03b00x00p02n01i02960ent IS
SIGNAL c1,c2,c3,c4,c5,c6,c7,c8 : INTEGER;
BEGIN
TESTING: PROCESS
BEGIN
WAIT FOR 1 ns;
c1 <= boo(bb);
c2 <= boo(bv);
c3 <= boo(bo);
c4 <= boo(cc);
c5 <= boo(ii);
c6 <= boo(rr);
c7 <= boo(ss);
c8 <= boo(tt);
WAIT FOR 1 ns;
assert NOT( (c1 = 1) AND
(c2 = 2) AND
(c3 = 3) AND
(c4 = 4) AND
(c5 = 5) AND
(c6 = 6) AND
(c7 = 7) AND
(c8 = 8))
report "***PASSED TEST: c02s03b00x00p02n01i02960"
severity NOTE;
assert ( (c1 = 1) AND
(c2 = 2) AND
(c3 = 3) AND
(c4 = 4) AND
(c5 = 5) AND
(c6 = 6) AND
(c7 = 7) AND
(c8 = 8))
report "***FAILED TEST: c02s03b00x00p02n01i02960 - Overloaded functions test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s03b00x00p02n01i02960arch;
|
gpl-2.0
|
2f8afeedaed25f61e1fe38b2b2728829
| 0.624809 | 3.566199 | false | false | false | false |
jakubcabal/pipemania-fpga-game
|
source/comp/control/kb_code.vhd
| 1 | 1,751 |
-- kb_code.vhd - Modul pro dekodovani kodu klavesy
-- Autori: Jakub Cabal
-- Posledni zmena: 14.10.2014
-- Popis: Tato komponenta generuje kod prave zmackle klavesy
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity KB_CODE is
Port (
CLK : in STD_LOGIC; -- Vychozi hodinovy signal
RST : in STD_LOGIC; -- Vychozi synchronni reset
PS2RX_DATA : in STD_LOGIC_VECTOR(7 downto 0); -- Vstupní data z PS2_RX
PS2RX_VALID : in STD_LOGIC; -- Data z PS2_RX jsou pripravena na vycteni
KEY_CODE : out STD_LOGIC_VECTOR(7 downto 0) -- Kod klavesy
);
end KB_CODE;
architecture FULL of KB_CODE is
signal ps2_code : STD_LOGIC_VECTOR(7 downto 0);
signal ps2_code_last : STD_LOGIC_VECTOR(7 downto 0);
begin
----------------------------------------------------------------
-- ZPRACOVANI DAT
----------------------------------------------------------------
-- Vycteni dat z PS2_RX
process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
ps2_code <= (others => '0');
ps2_code_last <= (others => '0');
elsif (PS2RX_VALID = '1') then
ps2_code <= PS2RX_DATA;
ps2_code_last <= ps2_code;
end if;
end if;
end process;
-- Propagace kodu klavesy na vystup, pri uvolneni klavesy
process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
KEY_CODE <= (others => '0');
elsif (ps2_code_last /= X"F0") then
KEY_CODE <= ps2_code;
end if;
end if;
end process;
end FULL;
|
mit
|
d4815fe546c6d633dc44d22915fceae9
| 0.500571 | 3.571429 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_divider/Gura/Modular/celda_V.vhd
| 1 | 1,242 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity celda_V is
generic(
NUM_BITS : positive := 163
);
port(
R : in STD_LOGIC_VECTOR(NUM_BITS downto 0);
X2 : in STD_LOGIC_VECTOR(NUM_BITS downto 0);
c_1 : in STD_LOGIC;
c_2 : in STD_LOGIC;
toV : out STD_LOGIC_VECTOR(NUM_BITS downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of celda_V is
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
toV <= X2 when c_1 = '0' and c_2 = '0' else
(others => '0') when c_1 = '0' and c_2 = '1' else
R;
end behave;
|
gpl-3.0
|
88fc8484534bfef084a6ed466da671b5
| 0.293076 | 5.008065 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1386.vhd
| 4 | 2,758 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1386.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n02i01386ent IS
END c08s05b00x00p03n02i01386ent;
ARCHITECTURE c08s05b00x00p03n02i01386arch OF c08s05b00x00p03n02i01386ent IS
BEGIN
TESTING : PROCESS
variable radix : natural := 10;
variable v1 : natural;
type r_array_index_type is range 1 to 3;
type r_array_type is array (r_array_index_type) of natural;
variable r_array : r_array_type;
procedure set_radix ( constant radix : natural
) is
begin
TESTING.radix := radix; -- test selected name as target
end set_radix;
BEGIN
v1 := 8; --test simple name as target
assert v1 = 8
report "Simple name as target failed."
severity note ;
set_radix (v1);
assert radix = v1
report "Selected name as target failed."
severity note ;
r_array ( 3 to 3 ) := (3 => 10); -- test slice name as target
assert r_array ( 3 ) = 10
report "Slice name as target failed."
severity note ;
r_array ( 2 ) := 8; -- test indexed name as target
assert r_array ( 2 ) = 8
report "Indexed name as target failed."
severity note ;
assert NOT(v1=8 and r_array(3)=10 and r_array(2)=8)
report "***PASSED TEST: c08s05b00x00p03n02i01386"
severity NOTE;
assert (v1=8 and r_array(3)=10 and r_array(2)=8)
report "***FAILED TEST: c08s05b00x00p03n02i01386 - The name of thetarget of the variable assignment statement must denote a variable"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n02i01386arch;
|
gpl-2.0
|
ef501c8861cc85059e3ab60ca97c5a12
| 0.637418 | 3.73207 | false | true | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_Multiplication/Serial_Mul_Paar/multiplier_131_3.vhd
| 1 | 12,429 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--------------------------------------------------------
-- Sin celda y sin maquina de estados
--------------------------------------------------------
-- x^131 + x^8 + x^3 + x^2 + 1
entity serial_multiplier_131 is
generic (
NUM_BITS : positive := 131 -- The order of the finite field
);
port(
ax : in std_logic_vector(NUM_BITS-1 downto 0);
bx : in std_logic_vector(NUM_BITS-1 downto 0);
cx : out std_logic_vector(NUM_BITS-1 downto 0); -- cx = ax*bx mod Fx
reset : in std_logic;
clk : in std_logic;
done : out std_logic
);
end serial_multiplier_131;
-----------------------------------------------------------
architecture behave of serial_multiplier_131 is
-----------------------------------------------------------
signal bx_shift : std_logic_vector(NUM_BITS-1 downto 0); -- B and C shifted one position to the rigth
signal bx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal cx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal counter: std_logic_vector(7 downto 0); -- 8-bit counter, controling the number of iterations: m
signal done_int : std_logic;
--señales para las xor de la reduccion:
signal xor_1 : std_logic;
signal xor_2 : std_logic;
signal xor_3 : std_logic;
-----------------------------------------------------------
-- States for the finite state machine
-----------------------------------------------------------
--type CurrentState_type is (NOTHING, END_STATE, MUL_STATE);
--signal CurrentState: CurrentState_type;
-----------------------------------------------------------
begin
-----------------------------------------------------------
-- Result of the multiplication
xor_1 <= Cx_int(1) xor Cx_int(NUM_BITS-1);
xor_2 <= Cx_int(2) xor Cx_int(NUM_BITS-1);
xor_3 <= Cx_int(7) xor Cx_int(NUM_BITS-1);
--Bx_shift <= bx_int(NUM_BITS-2 downto 0)& '0'; -- Shift Bx to left one position
bx_int <= Bx_shift; -- Shift Bx to left one position
------------------------------------------------------------
-- The finite state machine, it takes m cycles to compute
-- the multiplication, a counter is used to keep this count
------------------------------------------------------------
done <= done_int;
cx <= cx_int;
FSM_MUL: process (CLK)
Begin
if CLK'event and CLK = '1' then
if Reset = '1' then
counter <= "00000000"; -- m-1 value, in this case, it is 112, be sure to set the correct value
cx_int <= (others => '0');
Done_int <= '0';
else
if done_int = '0' then
counter <= counter + 1;
Cx_int(0) <= ( Ax(0) and Bx_int(NUM_BITS-1) ) xor Cx_int(NUM_BITS-1);
Cx_int(1) <= ( Ax(1) and Bx_int(NUM_BITS-1) ) xor Cx_int(0);
Cx_int(2) <= ( Ax(2) and Bx_int(NUM_BITS-1) ) xor xor_1;
Cx_int(3) <= ( Ax(3) and Bx_int(NUM_BITS-1) ) xor xor_2;
Cx_int(4) <= ( Ax(4) and Bx_int(NUM_BITS-1) ) xor Cx_int(3);
Cx_int(5) <= ( Ax(5) and Bx_int(NUM_BITS-1) ) xor Cx_int(4);
Cx_int(6) <= ( Ax(6) and Bx_int(NUM_BITS-1) ) xor Cx_int(5);
Cx_int(7) <= ( Ax(7) and Bx_int(NUM_BITS-1) ) xor Cx_int(6);
Cx_int(8) <= ( Ax(8) and Bx_int(NUM_BITS-1) ) xor xor_3;
Cx_int(9) <= ( Ax(9) and Bx_int(NUM_BITS-1) ) xor Cx_int(8);
Cx_int(10) <= ( Ax(10) and Bx_int(NUM_BITS-1) ) xor Cx_int(9);
Cx_int(11) <= ( Ax(11) and Bx_int(NUM_BITS-1) ) xor Cx_int(10);
Cx_int(12) <= ( Ax(12) and Bx_int(NUM_BITS-1) ) xor Cx_int(11);
Cx_int(13) <= ( Ax(13) and Bx_int(NUM_BITS-1) ) xor Cx_int(12);
Cx_int(14) <= ( Ax(14) and Bx_int(NUM_BITS-1) ) xor Cx_int(13);
Cx_int(15) <= ( Ax(15) and Bx_int(NUM_BITS-1) ) xor Cx_int(14);
Cx_int(16) <= ( Ax(16) and Bx_int(NUM_BITS-1) ) xor Cx_int(15);
Cx_int(17) <= ( Ax(17) and Bx_int(NUM_BITS-1) ) xor Cx_int(16);
Cx_int(18) <= ( Ax(18) and Bx_int(NUM_BITS-1) ) xor Cx_int(17);
Cx_int(19) <= ( Ax(19) and Bx_int(NUM_BITS-1) ) xor Cx_int(18);
Cx_int(20) <= ( Ax(20) and Bx_int(NUM_BITS-1) ) xor Cx_int(19);
Cx_int(21) <= ( Ax(21) and Bx_int(NUM_BITS-1) ) xor Cx_int(20);
Cx_int(22) <= ( Ax(22) and Bx_int(NUM_BITS-1) ) xor Cx_int(21);
Cx_int(23) <= ( Ax(23) and Bx_int(NUM_BITS-1) ) xor Cx_int(22);
Cx_int(24) <= ( Ax(24) and Bx_int(NUM_BITS-1) ) xor Cx_int(23);
Cx_int(25) <= ( Ax(25) and Bx_int(NUM_BITS-1) ) xor Cx_int(24);
Cx_int(26) <= ( Ax(26) and Bx_int(NUM_BITS-1) ) xor Cx_int(25);
Cx_int(27) <= ( Ax(27) and Bx_int(NUM_BITS-1) ) xor Cx_int(26);
Cx_int(28) <= ( Ax(28) and Bx_int(NUM_BITS-1) ) xor Cx_int(27);
Cx_int(29) <= ( Ax(29) and Bx_int(NUM_BITS-1) ) xor Cx_int(28);
Cx_int(30) <= ( Ax(30) and Bx_int(NUM_BITS-1) ) xor Cx_int(29);
Cx_int(31) <= ( Ax(31) and Bx_int(NUM_BITS-1) ) xor Cx_int(30);
Cx_int(32) <= ( Ax(32) and Bx_int(NUM_BITS-1) ) xor Cx_int(31);
Cx_int(33) <= ( Ax(33) and Bx_int(NUM_BITS-1) ) xor Cx_int(32);
Cx_int(34) <= ( Ax(34) and Bx_int(NUM_BITS-1) ) xor Cx_int(33);
Cx_int(35) <= ( Ax(35) and Bx_int(NUM_BITS-1) ) xor Cx_int(34);
Cx_int(36) <= ( Ax(36) and Bx_int(NUM_BITS-1) ) xor Cx_int(35);
Cx_int(37) <= ( Ax(37) and Bx_int(NUM_BITS-1) ) xor Cx_int(36);
Cx_int(38) <= ( Ax(38) and Bx_int(NUM_BITS-1) ) xor Cx_int(37);
Cx_int(39) <= ( Ax(39) and Bx_int(NUM_BITS-1) ) xor Cx_int(38);
Cx_int(40) <= ( Ax(40) and Bx_int(NUM_BITS-1) ) xor Cx_int(39);
Cx_int(41) <= ( Ax(41) and Bx_int(NUM_BITS-1) ) xor Cx_int(40);
Cx_int(42) <= ( Ax(42) and Bx_int(NUM_BITS-1) ) xor Cx_int(41);
Cx_int(43) <= ( Ax(43) and Bx_int(NUM_BITS-1) ) xor Cx_int(42);
Cx_int(44) <= ( Ax(44) and Bx_int(NUM_BITS-1) ) xor Cx_int(43);
Cx_int(45) <= ( Ax(45) and Bx_int(NUM_BITS-1) ) xor Cx_int(44);
Cx_int(46) <= ( Ax(46) and Bx_int(NUM_BITS-1) ) xor Cx_int(45);
Cx_int(47) <= ( Ax(47) and Bx_int(NUM_BITS-1) ) xor Cx_int(46);
Cx_int(48) <= ( Ax(48) and Bx_int(NUM_BITS-1) ) xor Cx_int(47);
Cx_int(49) <= ( Ax(49) and Bx_int(NUM_BITS-1) ) xor Cx_int(48);
Cx_int(50) <= ( Ax(50) and Bx_int(NUM_BITS-1) ) xor Cx_int(49);
Cx_int(51) <= ( Ax(51) and Bx_int(NUM_BITS-1) ) xor Cx_int(50);
Cx_int(52) <= ( Ax(52) and Bx_int(NUM_BITS-1) ) xor Cx_int(51);
Cx_int(53) <= ( Ax(53) and Bx_int(NUM_BITS-1) ) xor Cx_int(52);
Cx_int(54) <= ( Ax(54) and Bx_int(NUM_BITS-1) ) xor Cx_int(53);
Cx_int(55) <= ( Ax(55) and Bx_int(NUM_BITS-1) ) xor Cx_int(54);
Cx_int(56) <= ( Ax(56) and Bx_int(NUM_BITS-1) ) xor Cx_int(55);
Cx_int(57) <= ( Ax(57) and Bx_int(NUM_BITS-1) ) xor Cx_int(56);
Cx_int(58) <= ( Ax(58) and Bx_int(NUM_BITS-1) ) xor Cx_int(57);
Cx_int(59) <= ( Ax(59) and Bx_int(NUM_BITS-1) ) xor Cx_int(58);
Cx_int(60) <= ( Ax(60) and Bx_int(NUM_BITS-1) ) xor Cx_int(59);
Cx_int(61) <= ( Ax(61) and Bx_int(NUM_BITS-1) ) xor Cx_int(60);
Cx_int(62) <= ( Ax(62) and Bx_int(NUM_BITS-1) ) xor Cx_int(61);
Cx_int(63) <= ( Ax(63) and Bx_int(NUM_BITS-1) ) xor Cx_int(62);
Cx_int(64) <= ( Ax(64) and Bx_int(NUM_BITS-1) ) xor Cx_int(63);
Cx_int(65) <= ( Ax(65) and Bx_int(NUM_BITS-1) ) xor Cx_int(64);
Cx_int(66) <= ( Ax(66) and Bx_int(NUM_BITS-1) ) xor Cx_int(65);
Cx_int(67) <= ( Ax(67) and Bx_int(NUM_BITS-1) ) xor Cx_int(66);
Cx_int(68) <= ( Ax(68) and Bx_int(NUM_BITS-1) ) xor Cx_int(67);
Cx_int(69) <= ( Ax(69) and Bx_int(NUM_BITS-1) ) xor Cx_int(68);
Cx_int(70) <= ( Ax(70) and Bx_int(NUM_BITS-1) ) xor Cx_int(69);
Cx_int(71) <= ( Ax(71) and Bx_int(NUM_BITS-1) ) xor Cx_int(70);
Cx_int(72) <= ( Ax(72) and Bx_int(NUM_BITS-1) ) xor Cx_int(71);
Cx_int(73) <= ( Ax(73) and Bx_int(NUM_BITS-1) ) xor Cx_int(72);
Cx_int(74) <= ( Ax(74) and Bx_int(NUM_BITS-1) ) xor Cx_int(73);
Cx_int(75) <= ( Ax(75) and Bx_int(NUM_BITS-1) ) xor Cx_int(74);
Cx_int(76) <= ( Ax(76) and Bx_int(NUM_BITS-1) ) xor Cx_int(75);
Cx_int(77) <= ( Ax(77) and Bx_int(NUM_BITS-1) ) xor Cx_int(76);
Cx_int(78) <= ( Ax(78) and Bx_int(NUM_BITS-1) ) xor Cx_int(77);
Cx_int(79) <= ( Ax(79) and Bx_int(NUM_BITS-1) ) xor Cx_int(78);
Cx_int(80) <= ( Ax(80) and Bx_int(NUM_BITS-1) ) xor Cx_int(79);
Cx_int(81) <= ( Ax(81) and Bx_int(NUM_BITS-1) ) xor Cx_int(80);
Cx_int(82) <= ( Ax(82) and Bx_int(NUM_BITS-1) ) xor Cx_int(81);
Cx_int(83) <= ( Ax(83) and Bx_int(NUM_BITS-1) ) xor Cx_int(82);
Cx_int(84) <= ( Ax(84) and Bx_int(NUM_BITS-1) ) xor Cx_int(83);
Cx_int(85) <= ( Ax(85) and Bx_int(NUM_BITS-1) ) xor Cx_int(84);
Cx_int(86) <= ( Ax(86) and Bx_int(NUM_BITS-1) ) xor Cx_int(85);
Cx_int(87) <= ( Ax(87) and Bx_int(NUM_BITS-1) ) xor Cx_int(86);
Cx_int(88) <= ( Ax(88) and Bx_int(NUM_BITS-1) ) xor Cx_int(87);
Cx_int(89) <= ( Ax(89) and Bx_int(NUM_BITS-1) ) xor Cx_int(88);
Cx_int(90) <= ( Ax(90) and Bx_int(NUM_BITS-1) ) xor Cx_int(89);
Cx_int(91) <= ( Ax(91) and Bx_int(NUM_BITS-1) ) xor Cx_int(90);
Cx_int(92) <= ( Ax(92) and Bx_int(NUM_BITS-1) ) xor Cx_int(91);
Cx_int(93) <= ( Ax(93) and Bx_int(NUM_BITS-1) ) xor Cx_int(92);
Cx_int(94) <= ( Ax(94) and Bx_int(NUM_BITS-1) ) xor Cx_int(93);
Cx_int(95) <= ( Ax(95) and Bx_int(NUM_BITS-1) ) xor Cx_int(94);
Cx_int(96) <= ( Ax(96) and Bx_int(NUM_BITS-1) ) xor Cx_int(95);
Cx_int(97) <= ( Ax(97) and Bx_int(NUM_BITS-1) ) xor Cx_int(96);
Cx_int(98) <= ( Ax(98) and Bx_int(NUM_BITS-1) ) xor Cx_int(97);
Cx_int(99) <= ( Ax(99) and Bx_int(NUM_BITS-1) ) xor Cx_int(98);
Cx_int(100) <= ( Ax(100) and Bx_int(NUM_BITS-1) ) xor Cx_int(99);
Cx_int(101) <= ( Ax(101) and Bx_int(NUM_BITS-1) ) xor Cx_int(100);
Cx_int(102) <= ( Ax(102) and Bx_int(NUM_BITS-1) ) xor Cx_int(101);
Cx_int(103) <= ( Ax(103) and Bx_int(NUM_BITS-1) ) xor Cx_int(102);
Cx_int(104) <= ( Ax(104) and Bx_int(NUM_BITS-1) ) xor Cx_int(103);
Cx_int(105) <= ( Ax(105) and Bx_int(NUM_BITS-1) ) xor Cx_int(104);
Cx_int(106) <= ( Ax(106) and Bx_int(NUM_BITS-1) ) xor Cx_int(105);
Cx_int(107) <= ( Ax(107) and Bx_int(NUM_BITS-1) ) xor Cx_int(106);
Cx_int(108) <= ( Ax(108) and Bx_int(NUM_BITS-1) ) xor Cx_int(107);
Cx_int(109) <= ( Ax(109) and Bx_int(NUM_BITS-1) ) xor Cx_int(108);
Cx_int(110) <= ( Ax(110) and Bx_int(NUM_BITS-1) ) xor Cx_int(109);
Cx_int(111) <= ( Ax(111) and Bx_int(NUM_BITS-1) ) xor Cx_int(110);
Cx_int(112) <= ( Ax(112) and Bx_int(NUM_BITS-1) ) xor Cx_int(111);
Cx_int(113) <= ( Ax(113) and Bx_int(NUM_BITS-1) ) xor Cx_int(112);
Cx_int(114) <= ( Ax(114) and Bx_int(NUM_BITS-1) ) xor Cx_int(113);
Cx_int(115) <= ( Ax(115) and Bx_int(NUM_BITS-1) ) xor Cx_int(114);
Cx_int(116) <= ( Ax(116) and Bx_int(NUM_BITS-1) ) xor Cx_int(115);
Cx_int(117) <= ( Ax(117) and Bx_int(NUM_BITS-1) ) xor Cx_int(116);
Cx_int(118) <= ( Ax(118) and Bx_int(NUM_BITS-1) ) xor Cx_int(117);
Cx_int(119) <= ( Ax(119) and Bx_int(NUM_BITS-1) ) xor Cx_int(118);
Cx_int(120) <= ( Ax(120) and Bx_int(NUM_BITS-1) ) xor Cx_int(119);
Cx_int(121) <= ( Ax(121) and Bx_int(NUM_BITS-1) ) xor Cx_int(120);
Cx_int(122) <= ( Ax(122) and Bx_int(NUM_BITS-1) ) xor Cx_int(121);
Cx_int(123) <= ( Ax(123) and Bx_int(NUM_BITS-1) ) xor Cx_int(122);
Cx_int(124) <= ( Ax(124) and Bx_int(NUM_BITS-1) ) xor Cx_int(123);
Cx_int(125) <= ( Ax(125) and Bx_int(NUM_BITS-1) ) xor Cx_int(124);
Cx_int(126) <= ( Ax(126) and Bx_int(NUM_BITS-1) ) xor Cx_int(125);
Cx_int(127) <= ( Ax(127) and Bx_int(NUM_BITS-1) ) xor Cx_int(126);
Cx_int(128) <= ( Ax(128) and Bx_int(NUM_BITS-1) ) xor Cx_int(127);
Cx_int(129) <= ( Ax(129) and Bx_int(NUM_BITS-1) ) xor Cx_int(128);
Cx_int(130) <= ( Ax(130) and Bx_int(NUM_BITS-1) ) xor Cx_int(129);
end if;
if counter = "10000010" then
done_int <= '1';
end if;
end if;
end if;
end process;
SHIFT_REGISTER: process (CLK)
Begin
if CLK'event and CLK = '1' then
if Reset = '1' then
Bx_shift <= Bx;
else
Bx_shift <= Bx_shift(NUM_BITS-2 downto 0) & '0'; -- carga paralela
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
8dc353b94d1f8717ad4824d5a6da4181
| 0.522085 | 2.386063 | false | false | false | false |
123gmax/Digital-Lab
|
Lab1/Ganesh/FCS/tb_fcs.vhd
| 1 | 1,242 |
library ieee;
use ieee.std_logic_1164.all;
entity tb_fcs is
end tb_fcs;
architecture beh of tb_fcs is
component fc_system_v4
port(
flight_no : in std_logic_vector(2 downto 0);
request: in std_logic;
reset,clk : in std_logic;
clk3_out,clk10_out : out std_logic;--For demo only
grant,denied: out std_logic
);
end component;
signal flight_no_in: std_logic_vector(2 downto 0);
signal request_in,clk_in,reset_in,denied_out,grant_out,clk3_out_out,clk10_out_out: std_logic;
signal clk_period: time :=10 ns;
begin
uut:fc_system_v4
port map(flight_no=>flight_no_in,request=>request_in,reset=>reset_in,clk=>clk_in,clk3_out=>clk3_out_out,clk10_out=>clk10_out_out,grant=>grant_out,denied=>denied_out);
clock_process:process
begin
clk_in <= '0';
wait for clk_period/2;
clk_in <= not clk_in;
wait for clk_period/2;
end process;
teset_bench:process
begin
flight_no_in <= "000";
request_in<='0';
reset_in<='1';
wait for clk_period*5 + 5 ns;
reset_in<='0';
wait for clk_period;
request_in<='1';
wait for clk_period;
request_in<='0';
wait for clk_period*15;
wait;
end process;
end beh;
|
gpl-2.0
|
89e068eac0b2a3080534195a733d11e9
| 0.623188 | 2.992771 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1104.vhd
| 4 | 2,179 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1104.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p03n01i01104ent IS
END c06s05b00x00p03n01i01104ent;
ARCHITECTURE c06s05b00x00p03n01i01104arch OF c06s05b00x00p03n01i01104ent IS
BEGIN
TESTING: PROCESS
type FIVE is range 1 to 5;
type ABASE is array (FIVE range <>) of BOOLEAN;
subtype A1 is ABASE(FIVE);
type R1 is record
RE1: A1;
end record;
type R2 is record
RE2: R1;
end record;
variable V1: A1;
variable V2: R1 ; -- := (RE1=>(others=>TRUE));
variable V3: R2 ; -- := (RE2=>(RE1=>(others=>TRUE)));
BEGIN
V1(2 to 4) := V3.RE2.RE1(2 to 4); -- No_failure_here
assert NOT(V1(2 to 4)=(false,false,false))
report "***PASSED TEST: c06s05b00x00p03n01i01104"
severity NOTE;
assert (V1(2 to 4)=(false,false,false))
report "***FAILED TEST: c06s05b00x00p03n01i01104 - Prefix of a slice can be a selected name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p03n01i01104arch;
|
gpl-2.0
|
a171d0a34c308684bea739a3fea2e3f6
| 0.633777 | 3.566285 | false | true | false | false |
peteut/ghdl
|
testsuite/gna/bug15638/15368.vhd
| 3 | 622 |
entity bug is
end entity;
architecture a of bug is
component cmp is
port(o :out bit_vector);
end component;
signal o:bit_vector(4 downto 0);
begin
i_exp: cmp port map(o);
process(o)
begin
report "o event" severity note;
end process;
end architecture;
entity cmp is
port(o :out bit_vector);
end entity;
architecture a of cmp is
signal big_o:bit_vector(255 downto 0);
signal a:bit_vector(4 downto 0);
begin
o <= big_o(a'range);
big_o <= (others => '1') after 5 ns, (others => '0') after 10 ns;
a <= (others => '1') after 20 ns, (others => '0') after 30 ns;
end architecture;
|
gpl-2.0
|
a30f1766f6a0f7de7e6d360898686476
| 0.639871 | 3.034146 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1468.vhd
| 4 | 1,711 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1468.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p03n01i01468ent IS
END c08s08b00x00p03n01i01468ent;
ARCHITECTURE c08s08b00x00p03n01i01468arch OF c08s08b00x00p03n01i01468ent IS
BEGIN
TESTING: PROCESS
variable x : integer := 0;
BEGIN
case x is
1 => NULL;
when 2 => NULL:
when 3 => NULL;
when others => NULL;
end case;
assert FALSE
report "***FAILED TEST: c08s08b00x00p03n01i01468 - missing reserved word 'when'"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p03n01i01468_arch;
|
gpl-2.0
|
4ff89463568ca30d66fc71d5bc34cf25
| 0.652835 | 3.76044 | false | true | false | false |
peteut/ghdl
|
testsuite/gna/bug11/phonybench.vhdl
| 3 | 1,232 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity phonybench is
generic (
GENSTR : string := "adrien";
GENSTDLV : std_logic_vector(5 downto 0) := "111000";
GENSTDL : std_logic := '1';
GENNAT : natural := 22
);
end phonybench;
architecture bench of phonybench is
type char2std_t is array(character) of std_ulogic;
constant char2std_c : char2std_t := (
'U' => 'U',
'X' => 'X',
'0' => '0',
'1' => '1',
'Z' => 'Z',
'W' => 'W',
'L' => 'L',
'H' => 'H',
'-' => '-',
others => 'X'
);
function str2std(arg : string) return std_logic_vector is
variable result : std_logic_vector(arg'length - 1 downto 0);
variable j : integer;
begin
j := arg'length - 1;
for i in arg'range loop
result(j) := char2std_c(arg(i));
j := j - 1;
end loop;
return result;
end function;
signal sigvec1 : std_logic_vector(5 downto 0) := str2std(GENSTR);
signal sigvec2 : std_logic_vector(5 downto 0) := GENSTDLV;
signal siglog : std_logic := GENSTDL;
signal signat : natural := GENNAT;
signal clk : std_logic := '0';
begin
clk <= not clk after 5 ms;
sigvec1 <= str2std(GENSTR);
sigvec2 <= GENSTDLV;
siglog <= GENSTDL;
signat <= GENNAT;
end architecture;
|
gpl-2.0
|
185f964cfc444a686c3d57e7cebfff2a
| 0.607143 | 2.534979 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_opamp.vhd
| 4 | 2,181 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE; use IEEE.std_logic_1164.all;
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
entity tb_opamp is
end tb_opamp;
architecture TB_opamp of tb_opamp is
-- Component declarations
-- Signal declarations
terminal in_src, op_neg2, out_opamp2 : electrical;
terminal out_opamp1, op_neg1, op_neg3, out_opamp3, out_opamp3_res, op_neg3_res : electrical;
begin
-- Signal assignments
-- Component instances
vio : entity work.v_sine(ideal)
generic map(
freq => 100.0,
amplitude => 5.0e-3
)
port map(
pos => in_src,
neg => ELECTRICAL_REF
);
OP1 : entity work.opamp(slew_limited)
port map(
plus_in => electrical_ref,
minus_in => op_neg1,
output => out_opamp1
);
R1in : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => in_src,
p2 => op_neg1
);
R1F : entity work.resistor(ideal)
generic map(
res => 10.0e9
)
port map(
p1 => op_neg1,
p2 => out_opamp1
);
Rload1 : entity work.resistor(ideal)
generic map(
res => 1.0e3
)
port map(
p1 => out_opamp1,
p2 => electrical_ref
);
end TB_opamp;
|
gpl-2.0
|
556f0faa5e59b3971c7c838c37316942
| 0.602017 | 3.846561 | false | false | false | false |
jakubcabal/pipemania-fpga-game
|
source/comp/memory/mem_hub_tb.vhd
| 1 | 4,418 |
--------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: MEM_HUB_TB
-- AUTHORS: Jakub Cabal <[email protected]>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/pipemania-fpga-game
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MEM_HUB_TB is
end MEM_HUB_TB;
architecture behavior of MEM_HUB_TB is
-- CLK and RST
signal CLK : std_logic := '0';
signal RST : std_logic := '0';
-- Memory signals
signal sig_we_hub : std_logic;
signal sig_addr_hub : std_logic_vector(8 downto 0);
signal sig_dout_hub : std_logic_vector(31 downto 0);
signal sig_din_hub : std_logic_vector(31 downto 0);
-- MEM_HUB signals
signal hub_we_a : std_logic;
signal hub_en_a : std_logic;
signal hub_addr_a : std_logic_vector(8 downto 0);
signal hub_din_a : std_logic_vector(31 downto 0);
signal hub_dout_a : std_logic_vector(31 downto 0);
signal hub_ack_a : std_logic;
signal hub_we_b : std_logic;
signal hub_en_b : std_logic;
signal hub_addr_b : std_logic_vector(8 downto 0);
signal hub_din_b : std_logic_vector(31 downto 0);
signal hub_dout_b : std_logic_vector(31 downto 0);
signal hub_ack_b : std_logic;
-- Clock period definitions
constant CLK_period : time := 10 ns;
begin
uut : entity work.MEM_HUB
port map (
CLK => CLK,
RST => RST,
-- Port A
EN_A => hub_en_a,
WE_A => hub_we_a,
ADDR_A => hub_addr_a,
DIN_A => hub_din_a,
DOUT_A => hub_dout_a,
ACK_A => hub_ack_a,
-- Port B
EN_B => hub_en_b,
WE_B => hub_we_b,
ADDR_B => hub_addr_b,
DIN_B => hub_din_b,
DOUT_B => hub_dout_b,
ACK_B => hub_ack_b,
-- Port to memory
WE => sig_we_hub,
ADDR => sig_addr_hub,
DIN => sig_din_hub,
DOUT => sig_dout_hub
);
mem : entity work.BRAM_SYNC_TDP
port map (
-- Port A
CLK => CLK,
WE_A => sig_we_hub,
ADDR_A => sig_addr_hub,
DATAIN_A => sig_din_hub,
DATAOUT_A => sig_dout_hub,
-- Port B
WE_A => '0',
ADDR_A => (others => '0'),
DATAIN_A => (others => '0'),
DATAOUT_A => open
);
clk_process : process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
sim_proc : process
begin
wait for 100 ns;
wait until rising_edge(CLK);
hub_en_a <= '1';
hub_we_a <= '1';
hub_addr_a <= "000000001";
hub_din_a <= "11111111110000001111111111000000";
wait until rising_edge(CLK);
hub_en_a <= '1';
hub_we_a <= '1';
hub_addr_a <= "000000010";
hub_din_a <= "11111111111111111111111111111111";
wait until rising_edge(CLK);
hub_en_a <= '1';
hub_we_a <= '1';
hub_addr_a <= "000000011";
hub_din_a <= "00000001111111111100000000011111";
wait until rising_edge(CLK);
hub_en_a <= '1';
hub_we_a <= '0';
hub_addr_a <= "000000001";
hub_din_a <= "00000000000000000000000000000000";
wait until rising_edge(CLK);
hub_en_a <= '0';
hub_we_a <= '0';
hub_addr_a <= (others => '0');
wait until rising_edge(CLK);
hub_en_a <= '1';
hub_we_a <= '0';
hub_addr_a <= (others => '0');
wait until rising_edge(CLK);
hub_en_a <= '1';
hub_we_a <= '0';
hub_addr_a <= "000000001";
wait until rising_edge(CLK);
hub_en_a <= '1';
hub_we_a <= '0';
hub_addr_a <= "000000010";
wait until rising_edge(CLK);
hub_en_a <= '1';
hub_we_a <= '0';
hub_addr_a <= "000000011";
wait until rising_edge(CLK);
hub_en_a <= '0';
hub_we_a <= '0';
hub_addr_a <= (others => '0');
wait;
end process;
end;
|
mit
|
c263fa5ef4068bb5ec7fa53612f212c2
| 0.46469 | 3.44081 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc483.vhd
| 4 | 4,220 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc483.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00483ent IS
END c03s02b01x01p19n01i00483ent;
ARCHITECTURE c03s02b01x01p19n01i00483arch OF c03s02b01x01p19n01i00483ent IS
type record_std_package is record
a:boolean;
b:bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
type array_rec_std is array (integer range <>) of record_std_package;
function resolution10(i:in array_rec_std) return record_std_package is
variable temp : record_std_package := C50;
begin
return temp;
end resolution10;
subtype array_rec_std_state is resolution10 record_std_package;
constant C66 : array_rec_std_state := C50;
function complex_scalar(s : array_rec_std_state) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return array_rec_std_state is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : array_rec_std_state;
signal S2 : array_rec_std_state;
signal S3 : array_rec_std_state:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00483"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00483 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00483arch;
|
gpl-2.0
|
9fbfe105854c0bca1bf09fd0e3cda702
| 0.606161 | 3.718062 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/data_logger.vhd
| 4 | 2,503 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity data_logger is
end entity data_logger;
-- code from book
architecture high_level of data_logger is
subtype byte is bit_vector(7 downto 0);
type byte_array is array (integer range <>) of byte;
function resolver ( bytes : byte_array ) return byte is
begin
if bytes'length > 0 then
return bytes( bytes'left );
else
return X"00";
end if;
end function resolver;
subtype resolved_byte is resolver byte;
procedure reg ( signal clock, out_enable : in bit;
signal d : in byte;
signal q : out resolved_byte ) is
variable stored_byte : byte;
begin
loop
if clock = '1' then
stored_byte := d;
end if;
if out_enable = '1' then
q <= stored_byte;
else
q <= null;
end if;
wait on clock, out_enable, d;
end loop;
end procedure reg;
signal data_bus : resolved_byte bus;
-- . . .
-- not in book
signal a_reg_clk, b_reg_clk, a_reg_read, b_reg_read : bit := '0';
signal port_a, port_b : byte := X"00";
-- end not in book
begin
a_reg : reg (a_reg_clk, a_reg_read, port_a, data_bus);
b_reg : reg (b_reg_clk, b_reg_read, port_b, data_bus);
-- . . .
-- not in book
stimulus : process is
begin
port_a <= X"11"; a_reg_clk <= '1', '0' after 5 ns; wait for 10 ns;
a_reg_read <= '1', '0' after 5 ns; wait for 10 ns;
port_b <= X"21"; b_reg_clk <= '1', '0' after 5 ns; wait for 10 ns;
b_reg_read <= '1', '0' after 5 ns; wait for 10 ns;
a_reg_read <= '1', '0' after 5 ns;
b_reg_read <= '1', '0' after 5 ns;
wait;
end process stimulus;
-- end not in book
end architecture high_level;
-- end code from book
|
gpl-2.0
|
1cf428cafa9814bef51524be50221140
| 0.627247 | 3.414734 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/bug21332/twoscomplement.vhdl
| 3 | 1,169 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity twoscompliment is
generic
(
Nbits : positive := 8
);
port
(
--Inputs
A : in std_logic_vector (Nbits-1 downto 0);
--Outputs
Y : out std_logic_vector (Nbits downto 0)
);
end twoscompliment;
architecture twoscompliment_v1 of twoscompliment is
constant ONE: UNSIGNED(Y'RANGE) := (0 => '1', others => '0');
begin
Y <= std_logic_vector(unsigned (not A) + ONE);
end twoscompliment_v1;
architecture twoscompliment_v2 of twoscompliment is
signal temp : std_logic_vector(Nbits-1 downto 0);
begin
temp <= not A;
Y <= std_logic_vector(unsigned(temp) + 1);
end twoscompliment_v2;
library ieee;
use ieee.std_logic_1164.all;
entity test is
end entity;
architecture foo of test is
-- counts on default value for Nbits in DUT = 8)
signal A: std_logic_vector (7 downto 0) := (0=>'1', others => '0'); -- ONE
signal Y: std_logic_vector ( 8 downto 0);
begin
DUT: entity work.twoscompliment(twoscompliment_v2)
port map (
A => A,
Y => Y
);
end architecture;
|
gpl-2.0
|
7c5efac387a479d58eb5b9e744503f7c
| 0.617622 | 3.428152 | false | false | false | false |
peteut/ghdl
|
libraries/ieee2008/numeric_bit-body.vhdl
| 4 | 94,432 |
-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is sold without written
-- permission from the IEEE Standards Department. This source file may be
-- copied for individual use between licensed users. This source file is
-- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR
-- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE
-- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify
-- and hold IEEE harmless from any damages or liability arising out of the
-- use thereof.
--
-- Title : Standard VHDL Synthesis Packages
-- : (NUMERIC_BIT package body)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE DASC Synthesis Working Group,
-- : Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNSIGNED: represents an UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The base element type is type BIT.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array
-- : is returned (exceptions, if any, are noted individually).
--
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
package body NUMERIC_BIT is
-- null range array constants
constant NAU : UNSIGNED(0 downto 1) := (others => '0');
constant NAS : SIGNED(0 downto 1) := (others => '0');
-- implementation controls
constant NO_WARNING : BOOLEAN := false; -- default to emit warnings
-- =========================Local Subprograms =================================
function SIGNED_NUM_BITS (ARG : INTEGER) return NATURAL is
variable NBITS : NATURAL;
variable N : NATURAL;
begin
if ARG >= 0 then
N := ARG;
else
N := -(ARG+1);
end if;
NBITS := 1;
while N > 0 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end function SIGNED_NUM_BITS;
function UNSIGNED_NUM_BITS (ARG : NATURAL) return NATURAL is
variable NBITS : NATURAL;
variable N : NATURAL;
begin
N := ARG;
NBITS := 1;
while N > 1 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end function UNSIGNED_NUM_BITS;
------------------------------------------------------------------------------
-- this internal function computes the addition of two UNSIGNED
-- with input carry
-- * the two arguments are of the same length
function ADD_UNSIGNED (L, R : UNSIGNED; C : BIT) return UNSIGNED is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(L_LEFT downto 0) is R;
variable RESULT : UNSIGNED(L_LEFT downto 0);
variable CBIT : BIT := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end function ADD_UNSIGNED;
-- this internal function computes the addition of two SIGNED
-- with input carry
-- * the two arguments are of the same length
function ADD_SIGNED (L, R : SIGNED; C : BIT) return SIGNED is
constant L_LEFT : INTEGER := L'length-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
alias XR : SIGNED(L_LEFT downto 0) is R;
variable RESULT : SIGNED(L_LEFT downto 0);
variable CBIT : BIT := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end function ADD_SIGNED;
------------------------------------------------------------------------------
-- this internal procedure computes UNSIGNED division
-- giving the quotient and remainder.
procedure DIVMOD (NUM, XDENOM : UNSIGNED; XQUOT, XREMAIN : out UNSIGNED) is
variable TEMP : UNSIGNED(NUM'length downto 0);
variable QUOT : UNSIGNED(MAXIMUM(NUM'length, XDENOM'length)-1 downto 0);
alias DENOM : UNSIGNED(XDENOM'length-1 downto 0) is XDENOM;
variable TOPBIT : INTEGER;
begin
TEMP := "0"&NUM;
QUOT := (others => '0');
TOPBIT := -1;
for J in DENOM'range loop
if DENOM(J) = '1' then
TOPBIT := J;
exit;
end if;
end loop;
assert TOPBIT >= 0 report "NUMERIC_BIT.DIVMOD: DIV, MOD, or REM by zero"
severity error;
for J in NUM'length-(TOPBIT+1) downto 0 loop
if TEMP(TOPBIT+J+1 downto J) >= "0"&DENOM(TOPBIT downto 0) then
TEMP(TOPBIT+J+1 downto J) := (TEMP(TOPBIT+J+1 downto J))
-("0"&DENOM(TOPBIT downto 0));
QUOT(J) := '1';
end if;
assert TEMP(TOPBIT+J+1) = '0'
report "NUMERIC_BIT.DIVMOD: internal error in the division algorithm"
severity error;
end loop;
XQUOT := RESIZE(QUOT, XQUOT'length);
XREMAIN := RESIZE(TEMP, XREMAIN'length);
end procedure DIVMOD;
-----------------Local Subprograms - shift/rotate ops-------------------------
function XSLL (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : BIT_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L downto COUNT) := XARG(ARG_L-COUNT downto 0);
end if;
return RESULT;
end function XSLL;
function XSRL (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : BIT_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L-COUNT downto 0) := XARG(ARG_L downto COUNT);
end if;
return RESULT;
end function XSRL;
function XSRA (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : BIT_VECTOR(ARG_L downto 0);
variable XCOUNT : NATURAL := COUNT;
begin
if ((ARG'length <= 1) or (XCOUNT = 0)) then return ARG;
else
if (XCOUNT > ARG_L) then XCOUNT := ARG_L;
end if;
RESULT(ARG_L-XCOUNT downto 0) := XARG(ARG_L downto XCOUNT);
RESULT(ARG_L downto (ARG_L - XCOUNT + 1)) := (others => XARG(ARG_L));
end if;
return RESULT;
end function XSRA;
function XROL (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : BIT_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM : INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L downto COUNTM) := XARG(ARG_L-COUNTM downto 0);
RESULT(COUNTM-1 downto 0) := XARG(ARG_L downto ARG_L-COUNTM+1);
end if;
return RESULT;
end function XROL;
function XROR (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : BIT_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM : INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L-COUNTM downto 0) := XARG(ARG_L downto COUNTM);
RESULT(ARG_L downto ARG_L-COUNTM+1) := XARG(COUNTM-1 downto 0);
end if;
return RESULT;
end function XROR;
---------------- Local Subprograms - Relational Operators --------------------
--
-- General "=" for UNSIGNED vectors, same length
--
function UNSIGNED_EQUAL (L, R : UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) = BIT_VECTOR(R);
end function UNSIGNED_EQUAL;
--
-- General "=" for SIGNED vectors, same length
--
function SIGNED_EQUAL (L, R : SIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) = BIT_VECTOR(R);
end function SIGNED_EQUAL;
--
-- General "<" for UNSIGNED vectors, same length
--
function UNSIGNED_LESS (L, R : UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) < BIT_VECTOR(R);
end function UNSIGNED_LESS;
--
-- General "<" function for SIGNED vectors, same length
--
function SIGNED_LESS (L, R : SIGNED) return BOOLEAN is
-- Need aliases to assure index direction
variable INTERN_L : SIGNED(0 to L'length-1);
variable INTERN_R : SIGNED(0 to R'length-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return BIT_VECTOR(INTERN_L) < BIT_VECTOR(INTERN_R);
end function SIGNED_LESS;
--
-- General "<=" function for UNSIGNED vectors, same length
--
function UNSIGNED_LESS_OR_EQUAL (L, R : UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) <= BIT_VECTOR(R);
end function UNSIGNED_LESS_OR_EQUAL;
--
-- General "<=" function for SIGNED vectors, same length
--
function SIGNED_LESS_OR_EQUAL (L, R : SIGNED) return BOOLEAN is
-- Need aliases to assure index direction
variable INTERN_L : SIGNED(0 to L'length-1);
variable INTERN_R : SIGNED(0 to R'length-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return BIT_VECTOR(INTERN_L) <= BIT_VECTOR(INTERN_R);
end function SIGNED_LESS_OR_EQUAL;
-- ====================== Exported Functions ==================================
-- Id: A.1
function "abs" (ARG : SIGNED) return SIGNED is
constant ARG_LEFT : INTEGER := ARG'length-1;
variable RESULT : SIGNED(ARG_LEFT downto 0);
begin
if ARG'length < 1 then return NAS;
end if;
RESULT := ARG;
if RESULT(RESULT'left) = '1' then
RESULT := -RESULT;
end if;
return RESULT;
end function "abs";
-- Id: A.2
function "-" (ARG : SIGNED) return SIGNED is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT : SIGNED(ARG_LEFT downto 0);
variable CBIT : BIT := '1';
begin
if ARG'length < 1 then return NAS;
end if;
for I in 0 to RESULT'left loop
RESULT(I) := not(XARG(I)) xor CBIT;
CBIT := CBIT and not(XARG(I));
end loop;
return RESULT;
end function "-";
-- ============================================================================
-- Id: A.3
function "+" (L, R : UNSIGNED) return UNSIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
return ADD_UNSIGNED(RESIZE(L, SIZE), RESIZE(R, SIZE), '0');
end function "+";
-- Id: A.3R
function "+" (L : UNSIGNED; R : BIT) return UNSIGNED is
variable XR : UNSIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L + XR);
end function "+";
-- Id: A.3L
function "+" (L : BIT; R : UNSIGNED) return UNSIGNED is
variable XL : UNSIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL + R);
end function "+";
-- Id: A.4
function "+" (L, R : SIGNED) return SIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
return ADD_SIGNED(RESIZE(L, SIZE), RESIZE(R, SIZE), '0');
end function "+";
-- Id: A.4R
function "+" (L : SIGNED; R : BIT) return SIGNED is
variable XR : SIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L + XR);
end function "+";
-- Id: A.4L
function "+" (L : BIT; R : SIGNED) return SIGNED is
variable XL : SIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL + R);
end function "+";
-- Id: A.5
function "+" (L : UNSIGNED; R : NATURAL) return UNSIGNED is
begin
return L + TO_UNSIGNED(R, L'length);
end function "+";
-- Id: A.6
function "+" (L : NATURAL; R : UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'length) + R;
end function "+";
-- Id: A.7
function "+" (L : SIGNED; R : INTEGER) return SIGNED is
begin
return L + TO_SIGNED(R, L'length);
end function "+";
-- Id: A.8
function "+" (L : INTEGER; R : SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'length) + R;
end function "+";
-- ============================================================================
-- Id: A.9
function "-" (L, R : UNSIGNED) return UNSIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
return ADD_UNSIGNED(RESIZE(L, SIZE),
not(RESIZE(R, SIZE)),
'1');
end function "-";
-- Id: A.9R
function "-" (L : UNSIGNED; R : BIT) return UNSIGNED is
variable XR : UNSIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L - XR);
end function "-";
-- Id: A.9L
function "-" (L : BIT; R : UNSIGNED) return UNSIGNED is
variable XL : UNSIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL - R);
end function "-";
-- Id: A.10
function "-" (L, R : SIGNED) return SIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
return ADD_SIGNED(RESIZE(L, SIZE),
not(RESIZE(R, SIZE)),
'1');
end function "-";
-- Id: A.10R
function "-" (L : SIGNED; R : BIT) return SIGNED is
variable XR : SIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L - XR);
end function "-";
-- Id: A.10L
function "-" (L : BIT; R : SIGNED) return SIGNED is
variable XL : SIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL - R);
end function "-";
-- Id: A.11
function "-" (L : UNSIGNED; R : NATURAL) return UNSIGNED is
begin
return L - TO_UNSIGNED(R, L'length);
end function "-";
-- Id: A.12
function "-" (L : NATURAL; R : UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'length) - R;
end function "-";
-- Id: A.13
function "-" (L : SIGNED; R : INTEGER) return SIGNED is
begin
return L - TO_SIGNED(R, L'length);
end function "-";
-- Id: A.14
function "-" (L : INTEGER; R : SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'length) - R;
end function "-";
-- ============================================================================
-- Id: A.15
function "*" (L, R : UNSIGNED) return UNSIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
variable RESULT : UNSIGNED((L'length+R'length-1) downto 0) := (others => '0');
variable ADVAL : UNSIGNED((L'length+R'length-1) downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
ADVAL := RESIZE(XR, RESULT'length);
for I in 0 to L_LEFT loop
if XL(I) = '1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
return RESULT;
end function "*";
-- Id: A.16
function "*" (L, R : SIGNED) return SIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
variable XL : SIGNED(L_LEFT downto 0);
variable XR : SIGNED(R_LEFT downto 0);
variable RESULT : SIGNED((L_LEFT+R_LEFT+1) downto 0) := (others => '0');
variable ADVAL : SIGNED((L_LEFT+R_LEFT+1) downto 0);
begin
if ((L_LEFT < 0) or (R_LEFT < 0)) then return NAS;
end if;
XL := L;
XR := R;
ADVAL := RESIZE(XR, RESULT'length);
for I in 0 to L_LEFT-1 loop
if XL(I) = '1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
if XL(L_LEFT) = '1' then
RESULT := RESULT - ADVAL;
end if;
return RESULT;
end function "*";
-- Id: A.17
function "*" (L : UNSIGNED; R : NATURAL) return UNSIGNED is
begin
return L * TO_UNSIGNED(R, L'length);
end function "*";
-- Id: A.18
function "*" (L : NATURAL; R : UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'length) * R;
end function "*";
-- Id: A.19
function "*" (L : SIGNED; R : INTEGER) return SIGNED is
begin
return L * TO_SIGNED(R, L'length);
end function "*";
-- Id: A.20
function "*" (L : INTEGER; R : SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'length) * R;
end function "*";
-- ============================================================================
-- Id: A.21
function "/" (L, R : UNSIGNED) return UNSIGNED is
variable FQUOT : UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNSIGNED(R'length-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FQUOT;
end function "/";
-- Id: A.22
function "/" (L, R : SIGNED) return SIGNED is
variable FQUOT : UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNSIGNED(R'length-1 downto 0);
variable XNUM : UNSIGNED(L'length-1 downto 0);
variable XDENOM : UNSIGNED(R'length-1 downto 0);
variable QNEG : BOOLEAN := false;
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
if L(L'left) = '1' then
XNUM := UNSIGNED(-L);
QNEG := true;
else
XNUM := UNSIGNED(L);
end if;
if R(R'left) = '1' then
XDENOM := UNSIGNED(-R);
QNEG := not QNEG;
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if QNEG then FQUOT := "0"-FQUOT;
end if;
return SIGNED(FQUOT);
end function "/";
-- Id: A.23
function "/" (L : UNSIGNED; R : NATURAL) return UNSIGNED is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R));
variable XR, QUOT : UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAU;
end if;
if (R_LENGTH > L'length) then
QUOT := (others => '0');
return RESIZE(QUOT, L'length);
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'length);
return RESIZE(QUOT, L'length);
end function "/";
-- Id: A.24
function "/" (L : NATURAL; R : UNSIGNED) return UNSIGNED is
constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length);
variable XL, QUOT : UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'length);
if L_LENGTH > R'length
and QUOT(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""/"": Quotient Truncated"
severity warning;
end if;
return RESIZE(QUOT, R'length);
end function "/";
-- Id: A.25
function "/" (L : SIGNED; R : INTEGER) return SIGNED is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R));
variable XR, QUOT : SIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAS;
end if;
if (R_LENGTH > L'length) then
QUOT := (others => '0');
return RESIZE(QUOT, L'length);
end if;
XR := TO_SIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'length);
return RESIZE(QUOT, L'length);
end function "/";
-- Id: A.26
function "/" (L : INTEGER; R : SIGNED) return SIGNED is
constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length);
variable XL, QUOT : SIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'length);
if L_LENGTH > R'length and QUOT(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => QUOT(R'length-1))
then
assert NO_WARNING report "NUMERIC_BIT.""/"": Quotient Truncated"
severity warning;
end if;
return RESIZE(QUOT, R'length);
end function "/";
-- ============================================================================
-- Id: A.27
function "rem" (L, R : UNSIGNED) return UNSIGNED is
variable FQUOT : UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNSIGNED(R'length-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FREMAIN;
end function "rem";
-- Id: A.28
function "rem" (L, R : SIGNED) return SIGNED is
variable FQUOT : UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNSIGNED(R'length-1 downto 0);
variable XNUM : UNSIGNED(L'length-1 downto 0);
variable XDENOM : UNSIGNED(R'length-1 downto 0);
variable RNEG : BOOLEAN := false;
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
if L(L'left) = '1' then
XNUM := UNSIGNED(-L);
RNEG := true;
else
XNUM := UNSIGNED(L);
end if;
if R(R'left) = '1' then
XDENOM := UNSIGNED(-R);
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG then
FREMAIN := "0"-FREMAIN;
end if;
return SIGNED(FREMAIN);
end function "rem";
-- Id: A.29
function "rem" (L : UNSIGNED; R : NATURAL) return UNSIGNED is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R));
variable XR, XREM : UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := RESIZE((L rem XR), XREM'length);
if R_LENGTH > L'length and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "rem";
-- Id: A.30
function "rem" (L : NATURAL; R : UNSIGNED) return UNSIGNED is
constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length);
variable XL, XREM : UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := RESIZE((XL rem R), XREM'length);
if L_LENGTH > R'length and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "rem";
-- Id: A.31
function "rem" (L : SIGNED; R : INTEGER) return SIGNED is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R));
variable XR, XREM : SIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L rem XR), XREM'length);
if R_LENGTH > L'length and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => XREM(L'length-1))
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "rem";
-- Id: A.32
function "rem" (L : INTEGER; R : SIGNED) return SIGNED is
constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length);
variable XL, XREM : SIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL rem R), XREM'length);
if L_LENGTH > R'length and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => XREM(R'length-1))
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "rem";
-- ============================================================================
-- Id: A.33
function "mod" (L, R : UNSIGNED) return UNSIGNED is
variable FQUOT : UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNSIGNED(R'length-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FREMAIN;
end function "mod";
-- Id: A.34
function "mod" (L, R : SIGNED) return SIGNED is
variable FQUOT : UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNSIGNED(R'length-1 downto 0);
variable XNUM : UNSIGNED(L'length-1 downto 0);
variable XDENOM : UNSIGNED(R'length-1 downto 0);
variable RNEG : BOOLEAN := false;
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
if L(L'left) = '1' then
XNUM := UNSIGNED(-L);
else
XNUM := UNSIGNED(L);
end if;
if R(R'left) = '1' then
XDENOM := UNSIGNED(-R);
RNEG := true;
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG and L(L'left) = '1' then
FREMAIN := "0"-FREMAIN;
elsif RNEG and FREMAIN /= "0" then
FREMAIN := FREMAIN-XDENOM;
elsif L(L'left) = '1' and FREMAIN /= "0" then
FREMAIN := XDENOM-FREMAIN;
end if;
return SIGNED(FREMAIN);
end function "mod";
-- Id: A.35
function "mod" (L : UNSIGNED; R : NATURAL) return UNSIGNED is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R));
variable XR, XREM : UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'length);
if R_LENGTH > L'length and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "mod";
-- Id: A.36
function "mod" (L : NATURAL; R : UNSIGNED) return UNSIGNED is
constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length);
variable XL, XREM : UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'length);
if L_LENGTH > R'length and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "mod";
-- Id: A.37
function "mod" (L : SIGNED; R : INTEGER) return SIGNED is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R));
variable XR, XREM : SIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'length);
if R_LENGTH > L'length and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => XREM(L'length-1))
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "mod";
-- Id: A.38
function "mod" (L : INTEGER; R : SIGNED) return SIGNED is
constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length);
variable XL, XREM : SIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'length);
if L_LENGTH > R'length and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => XREM(R'length-1))
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "mod";
-- ============================================================================
-- Id: A.39
function find_leftmost (ARG : UNSIGNED; Y : BIT) return INTEGER is
begin
for INDEX in ARG'range loop
if ARG(INDEX) = Y then
return INDEX;
end if;
end loop;
return -1;
end function find_leftmost;
-- Id: A.40
function find_leftmost (ARG : SIGNED; Y : BIT) return INTEGER is
begin
for INDEX in ARG'range loop
if ARG(INDEX) = Y then
return INDEX;
end if;
end loop;
return -1;
end function find_leftmost;
-- Id: A.41
function find_rightmost (ARG : UNSIGNED; Y : BIT) return INTEGER is
begin
for INDEX in ARG'reverse_range loop
if ARG(INDEX) = Y then
return INDEX;
end if;
end loop;
return -1;
end function find_rightmost;
-- Id: A.42
function find_rightmost (ARG : SIGNED; Y : BIT) return INTEGER is
begin
for INDEX in ARG'reverse_range loop
if ARG(INDEX) = Y then
return INDEX;
end if;
end loop;
return -1;
end function find_rightmost;
-- ============================================================================
-- Id: C.1
function ">" (L, R : UNSIGNED) return BOOLEAN is
variable SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return not UNSIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function ">";
-- Id: C.2
function ">" (L, R : SIGNED) return BOOLEAN is
variable SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return not SIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function ">";
-- Id: C.3
function ">" (L : NATURAL; R : UNSIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return true;
end if;
return not UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R'length), R);
end function ">";
-- Id: C.4
function ">" (L : INTEGER; R : SIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L > 0;
end if;
return not SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R'length), R);
end function ">";
-- Id: C.5
function ">" (L : UNSIGNED; R : NATURAL) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return false;
end if;
return not UNSIGNED_LESS_OR_EQUAL(L, TO_UNSIGNED(R, L'length));
end function ">";
-- Id: C.6
function ">" (L : SIGNED; R : INTEGER) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 > R;
end if;
return not SIGNED_LESS_OR_EQUAL(L, TO_SIGNED(R, L'length));
end function ">";
-- ============================================================================
-- Id: C.7
function "<" (L, R : UNSIGNED) return BOOLEAN is
variable SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function "<";
-- Id: C.8
function "<" (L, R : SIGNED) return BOOLEAN is
variable SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function "<";
-- Id: C.9
function "<" (L : NATURAL; R : UNSIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return UNSIGNED_LESS(TO_UNSIGNED(L, R'length), R);
end function "<";
-- Id: C.10
function "<" (L : INTEGER; R : SIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return SIGNED_LESS(TO_SIGNED(L, R'length), R);
end function "<";
-- Id: C.11
function "<" (L : UNSIGNED; R : NATURAL) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return UNSIGNED_LESS(L, TO_UNSIGNED(R, L'length));
end function "<";
-- Id: C.12
function "<" (L : SIGNED; R : INTEGER) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return SIGNED_LESS(L, TO_SIGNED(R, L'length));
end function "<";
-- ============================================================================
-- Id: C.13
function "<=" (L, R : UNSIGNED) return BOOLEAN is
variable SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return UNSIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function "<=";
-- Id: C.14
function "<=" (L, R : SIGNED) return BOOLEAN is
variable SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return SIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function "<=";
-- Id: C.15
function "<=" (L : NATURAL; R : UNSIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R'length), R);
end function "<=";
-- Id: C.16
function "<=" (L : INTEGER; R : SIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R'length), R);
end function "<=";
-- Id: C.17
function "<=" (L : UNSIGNED; R : NATURAL) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return UNSIGNED_LESS_OR_EQUAL(L, TO_UNSIGNED(R, L'length));
end function "<=";
-- Id: C.18
function "<=" (L : SIGNED; R : INTEGER) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return SIGNED_LESS_OR_EQUAL(L, TO_SIGNED(R, L'length));
end function "<=";
-- ============================================================================
-- Id: C.19
function ">=" (L, R : UNSIGNED) return BOOLEAN is
variable SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return not UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function ">=";
-- Id: C.20
function ">=" (L, R : SIGNED) return BOOLEAN is
variable SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return not SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function ">=";
-- Id: C.21
function ">=" (L : NATURAL; R : UNSIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return L > 0;
end if;
return not UNSIGNED_LESS(TO_UNSIGNED(L, R'length), R);
end function ">=";
-- Id: C.22
function ">=" (L : INTEGER; R : SIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L > 0;
end if;
return not SIGNED_LESS(TO_SIGNED(L, R'length), R);
end function ">=";
-- Id: C.23
function ">=" (L : UNSIGNED; R : NATURAL) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return 0 > R;
end if;
return not UNSIGNED_LESS(L, TO_UNSIGNED(R, L'length));
end function ">=";
-- Id: C.24
function ">=" (L : SIGNED; R : INTEGER) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 > R;
end if;
return not SIGNED_LESS(L, TO_SIGNED(R, L'length));
end function ">=";
-- ============================================================================
-- Id: C.25
function "=" (L, R : UNSIGNED) return BOOLEAN is
variable SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return UNSIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function "=";
-- Id: C.26
function "=" (L, R : SIGNED) return BOOLEAN is
variable SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return SIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function "=";
-- Id: C.27
function "=" (L : NATURAL; R : UNSIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return false;
end if;
return UNSIGNED_EQUAL(TO_UNSIGNED(L, R'length), R);
end function "=";
-- Id: C.28
function "=" (L : INTEGER; R : SIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return false;
end if;
return SIGNED_EQUAL(TO_SIGNED(L, R'length), R);
end function "=";
-- Id: C.29
function "=" (L : UNSIGNED; R : NATURAL) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return false;
end if;
return UNSIGNED_EQUAL(L, TO_UNSIGNED(R, L'length));
end function "=";
-- Id: C.30
function "=" (L : SIGNED; R : INTEGER) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return false;
end if;
return SIGNED_EQUAL(L, TO_SIGNED(R, L'length));
end function "=";
-- ============================================================================
-- Id: C.31
function "/=" (L, R : UNSIGNED) return BOOLEAN is
variable SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
return not(UNSIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE)));
end function "/=";
-- Id: C.32
function "/=" (L, R : SIGNED) return BOOLEAN is
variable SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
return not(SIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE)));
end function "/=";
-- Id: C.33
function "/=" (L : NATURAL; R : UNSIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return true;
end if;
return not(UNSIGNED_EQUAL(TO_UNSIGNED(L, R'length), R));
end function "/=";
-- Id: C.34
function "/=" (L : INTEGER; R : SIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
if SIGNED_NUM_BITS(L) > R'length then return true;
end if;
return not(SIGNED_EQUAL(TO_SIGNED(L, R'length), R));
end function "/=";
-- Id: C.35
function "/=" (L : UNSIGNED; R : NATURAL) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return true;
end if;
return not(UNSIGNED_EQUAL(L, TO_UNSIGNED(R, L'length)));
end function "/=";
-- Id: C.36
function "/=" (L : SIGNED; R : INTEGER) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
if SIGNED_NUM_BITS(R) > L'length then return true;
end if;
return not(SIGNED_EQUAL(L, TO_SIGNED(R, L'length)));
end function "/=";
-- ============================================================================
-- Id: C.37
function MINIMUM (L, R : UNSIGNED) return UNSIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
if UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE)) then
return RESIZE(L, SIZE);
else
return RESIZE(R, SIZE);
end if;
end function MINIMUM;
-- Id: C.38
function MINIMUM (L, R : SIGNED) return SIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
if SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE)) then
return RESIZE(L, SIZE);
else
return RESIZE(R, SIZE);
end if;
end function MINIMUM;
-- Id: C.39
function MINIMUM (L : NATURAL; R : UNSIGNED) return UNSIGNED is
begin
return MINIMUM(TO_UNSIGNED(L, R'length), R);
end function MINIMUM;
-- Id: C.40
function MINIMUM (L : INTEGER; R : SIGNED) return SIGNED is
begin
return MINIMUM(TO_SIGNED(L, R'length), R);
end function MINIMUM;
-- Id: C.41
function MINIMUM (L : UNSIGNED; R : NATURAL) return UNSIGNED is
begin
return MINIMUM(L, TO_UNSIGNED(R, L'length));
end function MINIMUM;
-- Id: C.42
function MINIMUM (L : SIGNED; R : INTEGER) return SIGNED is
begin
return MINIMUM(L, TO_SIGNED(R, L'length));
end function MINIMUM;
-- ============================================================================
-- Id: C.43
function MAXIMUM (L, R : UNSIGNED) return UNSIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
if UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE)) then
return RESIZE(R, SIZE);
else
return RESIZE(L, SIZE);
end if;
end function MAXIMUM;
-- Id: C.44
function MAXIMUM (L, R : SIGNED) return SIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
if SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE)) then
return RESIZE(R, SIZE);
else
return RESIZE(L, SIZE);
end if;
end function MAXIMUM;
-- Id: C.45
function MAXIMUM (L : NATURAL; R : UNSIGNED) return UNSIGNED is
begin
return MAXIMUM(TO_UNSIGNED(L, R'length), R);
end function MAXIMUM;
-- Id: C.46
function MAXIMUM (L : INTEGER; R : SIGNED) return SIGNED is
begin
return MAXIMUM(TO_SIGNED(L, R'length), R);
end function MAXIMUM;
-- Id: C.47
function MAXIMUM (L : UNSIGNED; R : NATURAL) return UNSIGNED is
begin
return MAXIMUM(L, TO_UNSIGNED(R, L'length));
end function MAXIMUM;
-- Id: C.48
function MAXIMUM (L : SIGNED; R : INTEGER) return SIGNED is
begin
return MAXIMUM(L, TO_SIGNED(R, L'length));
end function MAXIMUM;
-- ============================================================================
-- Id: C.49
function "?>" (L, R : UNSIGNED) return BIT is
begin
if L > R then
return '1';
else
return '0';
end if;
end function "?>";
-- Id: C.50
function "?>" (L, R : SIGNED) return BIT is
begin
if L > R then
return '1';
else
return '0';
end if;
end function "?>";
-- Id: C.51
function "?>" (L : NATURAL; R : UNSIGNED) return BIT is
begin
if L > R then
return '1';
else
return '0';
end if;
end function "?>";
-- Id: C.52
function "?>" (L : INTEGER; R : SIGNED) return BIT is
begin
if L > R then
return '1';
else
return '0';
end if;
end function "?>";
-- Id: C.53
function "?>" (L : UNSIGNED; R : NATURAL) return BIT is
begin
if L > R then
return '1';
else
return '0';
end if;
end function "?>";
-- Id: C.54
function "?>" (L : SIGNED; R : INTEGER) return BIT is
begin
if L > R then
return '1';
else
return '0';
end if;
end function "?>";
-- ============================================================================
-- Id: C.55
function "?<" (L, R : UNSIGNED) return BIT is
begin
if L < R then
return '1';
else
return '0';
end if;
end function "?<";
-- Id: C.56
function "?<" (L, R : SIGNED) return BIT is
begin
if L < R then
return '1';
else
return '0';
end if;
end function "?<";
-- Id: C.57
function "?<" (L : NATURAL; R : UNSIGNED) return BIT is
begin
if L < R then
return '1';
else
return '0';
end if;
end function "?<";
-- Id: C.58
function "?<" (L : INTEGER; R : SIGNED) return BIT is
begin
if L < R then
return '1';
else
return '0';
end if;
end function "?<";
-- Id: C.59
function "?<" (L : UNSIGNED; R : NATURAL) return BIT is
begin
if L < R then
return '1';
else
return '0';
end if;
end function "?<";
-- Id: C.60
function "?<" (L : SIGNED; R : INTEGER) return BIT is
begin
if L < R then
return '1';
else
return '0';
end if;
end function "?<";
-- ============================================================================
-- Id: C.61
function "?<=" (L, R : UNSIGNED) return BIT is
begin
if L <= R then
return '1';
else
return '0';
end if;
end function "?<=";
-- Id: C.62
function "?<=" (L, R : SIGNED) return BIT is
begin
if L <= R then
return '1';
else
return '0';
end if;
end function "?<=";
-- Id: C.63
function "?<=" (L : NATURAL; R : UNSIGNED) return BIT is
begin
if L <= R then
return '1';
else
return '0';
end if;
end function "?<=";
-- Id: C.64
function "?<=" (L : INTEGER; R : SIGNED) return BIT is
begin
if L <= R then
return '1';
else
return '0';
end if;
end function "?<=";
-- Id: C.65
function "?<=" (L : UNSIGNED; R : NATURAL) return BIT is
begin
if L <= R then
return '1';
else
return '0';
end if;
end function "?<=";
-- Id: C.66
function "?<=" (L : SIGNED; R : INTEGER) return BIT is
begin
if L <= R then
return '1';
else
return '0';
end if;
end function "?<=";
-- ============================================================================
-- Id: C.67
function "?>=" (L, R : UNSIGNED) return BIT is
begin
if L >= R then
return '1';
else
return '0';
end if;
end function "?>=";
-- Id: C.68
function "?>=" (L, R : SIGNED) return BIT is
begin
if L >= R then
return '1';
else
return '0';
end if;
end function "?>=";
-- Id: C.69
function "?>=" (L : NATURAL; R : UNSIGNED) return BIT is
begin
if L >= R then
return '1';
else
return '0';
end if;
end function "?>=";
-- Id: C.70
function "?>=" (L : INTEGER; R : SIGNED) return BIT is
begin
if L >= R then
return '1';
else
return '0';
end if;
end function "?>=";
-- Id: C.71
function "?>=" (L : UNSIGNED; R : NATURAL) return BIT is
begin
if L >= R then
return '1';
else
return '0';
end if;
end function "?>=";
-- Id: C.72
function "?>=" (L : SIGNED; R : INTEGER) return BIT is
begin
if L >= R then
return '1';
else
return '0';
end if;
end function "?>=";
-- ============================================================================
-- Id: C.73
function "?=" (L, R : UNSIGNED) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function "?=";
-- Id: C.74
function "?=" (L, R : SIGNED) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function "?=";
-- Id: C.75
function "?=" (L : NATURAL; R : UNSIGNED) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function "?=";
-- Id: C.76
function "?=" (L : INTEGER; R : SIGNED) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function "?=";
-- Id: C.77
function "?=" (L : UNSIGNED; R : NATURAL) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function "?=";
-- Id: C.78
function "?=" (L : SIGNED; R : INTEGER) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function "?=";
-- ============================================================================
-- Id: C.79
function "?/=" (L, R : UNSIGNED) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function "?/=";
-- Id: C.80
function "?/=" (L, R : SIGNED) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function "?/=";
-- Id: C.81
function "?/=" (L : NATURAL; R : UNSIGNED) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function "?/=";
-- Id: C.82
function "?/=" (L : INTEGER; R : SIGNED) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function "?/=";
-- Id: C.83
function "?/=" (L : UNSIGNED; R : NATURAL) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function "?/=";
-- Id: C.84
function "?/=" (L : SIGNED; R : INTEGER) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function "?/=";
-- ============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : UNSIGNED; COUNT : NATURAL) return UNSIGNED is
begin
if (ARG'length < 1) then return NAU;
end if;
return UNSIGNED(XSLL(BIT_VECTOR(ARG), COUNT));
end function SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG : UNSIGNED; COUNT : NATURAL) return UNSIGNED is
begin
if (ARG'length < 1) then return NAU;
end if;
return UNSIGNED(XSRL(BIT_VECTOR(ARG), COUNT));
end function SHIFT_RIGHT;
-- Id: S.3
function SHIFT_LEFT (ARG : SIGNED; COUNT : NATURAL) return SIGNED is
begin
if (ARG'length < 1) then return NAS;
end if;
return SIGNED(XSLL(BIT_VECTOR(ARG), COUNT));
end function SHIFT_LEFT;
-- Id: S.4
function SHIFT_RIGHT (ARG : SIGNED; COUNT : NATURAL) return SIGNED is
begin
if (ARG'length < 1) then return NAS;
end if;
return SIGNED(XSRA(BIT_VECTOR(ARG), COUNT));
end function SHIFT_RIGHT;
-- ============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : UNSIGNED; COUNT : NATURAL) return UNSIGNED is
begin
if (ARG'length < 1) then return NAU;
end if;
return UNSIGNED(XROL(BIT_VECTOR(ARG), COUNT));
end function ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG : UNSIGNED; COUNT : NATURAL) return UNSIGNED is
begin
if (ARG'length < 1) then return NAU;
end if;
return UNSIGNED(XROR(BIT_VECTOR(ARG), COUNT));
end function ROTATE_RIGHT;
-- Id: S.7
function ROTATE_LEFT (ARG : SIGNED; COUNT : NATURAL) return SIGNED is
begin
if (ARG'length < 1) then return NAS;
end if;
return SIGNED(XROL(BIT_VECTOR(ARG), COUNT));
end function ROTATE_LEFT;
-- Id: S.8
function ROTATE_RIGHT (ARG : SIGNED; COUNT : NATURAL) return SIGNED is
begin
if (ARG'length < 1) then return NAS;
end if;
return SIGNED(XROR(BIT_VECTOR(ARG), COUNT));
end function ROTATE_RIGHT;
-- ============================================================================
------------------------------------------------------------------------------
-- Note: Function S.9 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sll";
------------------------------------------------------------------------------
-- Note: Function S.10 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG : SIGNED; COUNT : INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), -COUNT));
end if;
end function "sll";
------------------------------------------------------------------------------
-- Note: Function S.11 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "srl";
------------------------------------------------------------------------------
-- Note: Function S.12 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG : SIGNED; COUNT : INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT));
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "srl";
------------------------------------------------------------------------------
-- Note: Function S.13 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end function "rol";
------------------------------------------------------------------------------
-- Note: Function S.14 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG : SIGNED; COUNT : INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end function "rol";
------------------------------------------------------------------------------
-- Note: Function S.15 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end function "ror";
------------------------------------------------------------------------------
-- Note: Function S.16 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG : SIGNED; COUNT : INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end function "ror";
------------------------------------------------------------------------------
-- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.17
function "sla" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sla";
------------------------------------------------------------------------------
-- Note: Function S.18 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.18
function "sla" (ARG : SIGNED; COUNT : INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sla";
------------------------------------------------------------------------------
-- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.19
function "sra" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "sra";
------------------------------------------------------------------------------
-- Note: Function S.20 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.20
function "sra" (ARG : SIGNED; COUNT : INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "sra";
-- ============================================================================
-- Id: D.1
function TO_INTEGER (ARG : UNSIGNED) return NATURAL is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT : NATURAL := 0;
begin
if (ARG'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.TO_INTEGER: null detected, returning 0"
severity warning;
return 0;
end if;
for I in XARG'range loop
RESULT := RESULT+RESULT;
if XARG(I) = '1' then
RESULT := RESULT + 1;
end if;
end loop;
return RESULT;
end function TO_INTEGER;
-- Id: D.2
function TO_INTEGER (ARG : SIGNED) return INTEGER is
begin
if (ARG'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.TO_INTEGER: null detected, returning 0"
severity warning;
return 0;
end if;
if ARG(ARG'left) = '0' then
return TO_INTEGER(UNSIGNED(ARG));
else
return (- (TO_INTEGER(UNSIGNED(- (ARG + 1)))) -1);
end if;
end function TO_INTEGER;
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE : NATURAL) return UNSIGNED is
variable RESULT : UNSIGNED(SIZE-1 downto 0);
variable I_VAL : NATURAL := ARG;
begin
if (SIZE < 1) then return NAU;
end if;
for I in 0 to RESULT'left loop
if (I_VAL mod 2) = 0 then
RESULT(I) := '0';
else RESULT(I) := '1';
end if;
I_VAL := I_VAL/2;
end loop;
if not(I_VAL = 0) then
assert NO_WARNING
report "NUMERIC_BIT.TO_UNSIGNED: vector truncated"
severity warning;
end if;
return RESULT;
end function TO_UNSIGNED;
-- Id: D.4
function TO_SIGNED (ARG : INTEGER;
SIZE : NATURAL) return SIGNED is
variable RESULT : SIGNED(SIZE-1 downto 0);
variable B_VAL : BIT := '0';
variable I_VAL : INTEGER := ARG;
begin
if (SIZE < 1) then return NAS;
end if;
if (ARG < 0) then
B_VAL := '1';
I_VAL := -(ARG+1);
end if;
for I in 0 to RESULT'left loop
if (I_VAL mod 2) = 0 then
RESULT(I) := B_VAL;
else
RESULT(I) := not B_VAL;
end if;
I_VAL := I_VAL/2;
end loop;
if ((I_VAL /= 0) or (B_VAL /= RESULT(RESULT'left))) then
assert NO_WARNING
report "NUMERIC_BIT.TO_SIGNED: vector truncated"
severity warning;
end if;
return RESULT;
end function TO_SIGNED;
function TO_UNSIGNED (ARG : NATURAL; SIZE_RES : UNSIGNED)
return UNSIGNED is
begin
return TO_UNSIGNED (ARG => ARG,
SIZE => SIZE_RES'length);
end function TO_UNSIGNED;
function TO_SIGNED (ARG : INTEGER; SIZE_RES : SIGNED)
return SIGNED is
begin
return TO_SIGNED (ARG => ARG,
SIZE => SIZE_RES'length);
end function TO_SIGNED;
-- ============================================================================
-- Id: R.1
function RESIZE (ARG : SIGNED; NEW_SIZE : NATURAL) return SIGNED is
alias INVEC : SIGNED(ARG'length-1 downto 0) is ARG;
variable RESULT : SIGNED(NEW_SIZE-1 downto 0) := (others => '0');
constant BOUND : INTEGER := MINIMUM(ARG'length, RESULT'length)-2;
begin
if (NEW_SIZE < 1) then return NAS;
end if;
if (ARG'length = 0) then return RESULT;
end if;
RESULT := (others => ARG(ARG'left));
if BOUND >= 0 then
RESULT(BOUND downto 0) := INVEC(BOUND downto 0);
end if;
return RESULT;
end function RESIZE;
-- Id: R.2
function RESIZE (ARG : UNSIGNED; NEW_SIZE : NATURAL) return UNSIGNED is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT : UNSIGNED(NEW_SIZE-1 downto 0) := (others => '0');
begin
if (NEW_SIZE < 1) then return NAU;
end if;
if XARG'length = 0 then return RESULT;
end if;
if (RESULT'length < ARG'length) then
RESULT(RESULT'left downto 0) := XARG(RESULT'left downto 0);
else
RESULT(RESULT'left downto XARG'left+1) := (others => '0');
RESULT(XARG'left downto 0) := XARG;
end if;
return RESULT;
end function RESIZE;
function RESIZE (ARG, SIZE_RES : UNSIGNED)
return UNSIGNED is
begin
return RESIZE (ARG => ARG,
NEW_SIZE => SIZE_RES'length);
end function RESIZE;
function RESIZE (ARG, SIZE_RES : SIGNED)
return SIGNED is
begin
return RESIZE (ARG => ARG,
NEW_SIZE => SIZE_RES'length);
end function RESIZE;
-- ============================================================================
-- Id: L.1
function "not" (L : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(not(BIT_VECTOR(L)));
return RESULT;
end function "not";
-- Id: L.2
function "and" (L, R : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) and BIT_VECTOR(R));
return RESULT;
end function "and";
-- Id: L.3
function "or" (L, R : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) or BIT_VECTOR(R));
return RESULT;
end function "or";
-- Id: L.4
function "nand" (L, R : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) nand BIT_VECTOR(R));
return RESULT;
end function "nand";
-- Id: L.5
function "nor" (L, R : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) nor BIT_VECTOR(R));
return RESULT;
end function "nor";
-- Id: L.6
function "xor" (L, R : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) xor BIT_VECTOR(R));
return RESULT;
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.7 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) xnor BIT_VECTOR(R));
return RESULT;
end function "xnor";
-- Id: L.8
function "not" (L : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(not(BIT_VECTOR(L)));
return RESULT;
end function "not";
-- Id: L.9
function "and" (L, R : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) and BIT_VECTOR(R));
return RESULT;
end function "and";
-- Id: L.10
function "or" (L, R : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) or BIT_VECTOR(R));
return RESULT;
end function "or";
-- Id: L.11
function "nand" (L, R : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) nand BIT_VECTOR(R));
return RESULT;
end function "nand";
-- Id: L.12
function "nor" (L, R : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) nor BIT_VECTOR(R));
return RESULT;
end function "nor";
-- Id: L.13
function "xor" (L, R : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) xor BIT_VECTOR(R));
return RESULT;
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.14 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) xnor BIT_VECTOR(R));
return RESULT;
end function "xnor";
-- Id: L.15
function "and" (L : BIT; R : UNSIGNED) return UNSIGNED is
begin
return UNSIGNED (L and BIT_VECTOR(R));
end function "and";
-- Id: L.16
function "and" (L : UNSIGNED; R : BIT) return UNSIGNED is
begin
return UNSIGNED (BIT_VECTOR(L) and R);
end function "and";
-- Id: L.17
function "or" (L : BIT; R : UNSIGNED) return UNSIGNED is
begin
return UNSIGNED (L or BIT_VECTOR(R));
end function "or";
-- Id: L.18
function "or" (L : UNSIGNED; R : BIT) return UNSIGNED is
begin
return UNSIGNED (BIT_VECTOR(L) or R);
end function "or";
-- Id: L.19
function "nand" (L : BIT; R : UNSIGNED) return UNSIGNED is
begin
return UNSIGNED (L nand BIT_VECTOR(R));
end function "nand";
-- Id: L.20
function "nand" (L : UNSIGNED; R : BIT) return UNSIGNED is
begin
return UNSIGNED (BIT_VECTOR(L) nand R);
end function "nand";
-- Id: L.21
function "nor" (L : BIT; R : UNSIGNED) return UNSIGNED is
begin
return UNSIGNED (L nor BIT_VECTOR(R));
end function "nor";
-- Id: L.22
function "nor" (L : UNSIGNED; R : BIT) return UNSIGNED is
begin
return UNSIGNED (BIT_VECTOR(L) nor R);
end function "nor";
-- Id: L.23
function "xor" (L : BIT; R : UNSIGNED) return UNSIGNED is
begin
return UNSIGNED (L xor BIT_VECTOR(R));
end function "xor";
-- Id: L.24
function "xor" (L : UNSIGNED; R : BIT) return UNSIGNED is
begin
return UNSIGNED (BIT_VECTOR(L) xor R);
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.25 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.25
function "xnor" (L : BIT; R : UNSIGNED) return UNSIGNED is
begin
return UNSIGNED (L xnor BIT_VECTOR(R));
end function "xnor";
------------------------------------------------------------------------------
-- Note: Function L.26 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.26
function "xnor" (L : UNSIGNED; R : BIT) return UNSIGNED is
begin
return UNSIGNED (BIT_VECTOR(L) xnor R);
end function "xnor";
-- Id: L.27
function "and" (L : BIT; R : SIGNED) return SIGNED is
begin
return SIGNED (L and BIT_VECTOR(R));
end function "and";
-- Id: L.28
function "and" (L : SIGNED; R : BIT) return SIGNED is
begin
return SIGNED (BIT_VECTOR(L) and R);
end function "and";
-- Id: L.29
function "or" (L : BIT; R : SIGNED) return SIGNED is
begin
return SIGNED (L or BIT_VECTOR(R));
end function "or";
-- Id: L.30
function "or" (L : SIGNED; R : BIT) return SIGNED is
begin
return SIGNED (BIT_VECTOR(L) or R);
end function "or";
-- Id: L.31
function "nand" (L : BIT; R : SIGNED) return SIGNED is
begin
return SIGNED (L nand BIT_VECTOR(R));
end function "nand";
-- Id: L.32
function "nand" (L : SIGNED; R : BIT) return SIGNED is
begin
return SIGNED (BIT_VECTOR(L) nand R);
end function "nand";
-- Id: L.33
function "nor" (L : BIT; R : SIGNED) return SIGNED is
begin
return SIGNED (L nor BIT_VECTOR(R));
end function "nor";
-- Id: L.34
function "nor" (L : SIGNED; R : BIT) return SIGNED is
begin
return SIGNED (BIT_VECTOR(L) nor R);
end function "nor";
-- Id: L.35
function "xor" (L : BIT; R : SIGNED) return SIGNED is
begin
return SIGNED (L xor BIT_VECTOR(R));
end function "xor";
-- Id: L.36
function "xor" (L : SIGNED; R : BIT) return SIGNED is
begin
return SIGNED (BIT_VECTOR(L) xor R);
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.37 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.37
function "xnor" (L : BIT; R : SIGNED) return SIGNED is
begin
return SIGNED (L xnor BIT_VECTOR(R));
end function "xnor";
------------------------------------------------------------------------------
-- Note: Function L.38 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.38
function "xnor" (L : SIGNED; R : BIT) return SIGNED is
begin
return SIGNED (BIT_VECTOR(L) xnor R);
end function "xnor";
------------------------------------------------------------------------------
-- Note: Function L.39 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.39
function "and" (L : SIGNED) return BIT is
begin
return and (BIT_VECTOR (L));
end function "and";
------------------------------------------------------------------------------
-- Note: Function L.40 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.40
function "and" (L : UNSIGNED) return BIT is
begin
return and (BIT_VECTOR (L));
end function "and";
------------------------------------------------------------------------------
-- Note: Function L.41 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.41
function "nand" (L : SIGNED) return BIT is
begin
return nand (BIT_VECTOR (L));
end function "nand";
------------------------------------------------------------------------------
-- Note: Function L.42 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.42
function "nand" (L : UNSIGNED) return BIT is
begin
return nand (BIT_VECTOR (L));
end function "nand";
------------------------------------------------------------------------------
-- Note: Function L.43 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.43
function "or" (L : SIGNED) return BIT is
begin
return or (BIT_VECTOR (L));
end function "or";
------------------------------------------------------------------------------
-- Note: Function L.44 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.44
function "or" (L : UNSIGNED) return BIT is
begin
return or (BIT_VECTOR (L));
end function "or";
------------------------------------------------------------------------------
-- Note: Function L.45 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.45
function "nor" (L : SIGNED) return BIT is
begin
return nor (BIT_VECTOR (L));
end function "nor";
------------------------------------------------------------------------------
-- Note: Function L.46 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.46
function "nor" (L : UNSIGNED) return BIT is
begin
return nor (BIT_VECTOR (L));
end function "nor";
------------------------------------------------------------------------------
-- Note: Function L.47 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.47
function "xor" (L : SIGNED) return BIT is
begin
return xor (BIT_VECTOR (L));
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.48 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.48
function "xor" (L : UNSIGNED) return BIT is
begin
return xor (BIT_VECTOR (L));
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.49 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.49
function "xnor" (L : SIGNED) return BIT is
begin
return xnor (BIT_VECTOR (L));
end function "xnor";
------------------------------------------------------------------------------
-- Note: Function L.50 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.50
function "xnor" (L : UNSIGNED) return BIT is
begin
return xnor (BIT_VECTOR (L));
end function "xnor";
-- ============================================================================
-- string conversion and write operations
-- ============================================================================
function to_ostring (value : UNSIGNED) return STRING is
begin
return to_ostring(BIT_VECTOR (value));
end function to_ostring;
function to_ostring (value : SIGNED) return STRING is
constant result_length : INTEGER := (value'length+2)/3;
constant pad : BIT_VECTOR(1 to (result_length*3 - value'length))
:= (others => value (value'left)); -- Extend sign bit
begin
return to_ostring(pad & BIT_VECTOR (value));
end function to_ostring;
function to_hstring (value : UNSIGNED) return STRING is
begin
return to_hstring(BIT_VECTOR (value));
end function to_hstring;
function to_hstring (value : SIGNED) return STRING is
constant result_length : INTEGER := (value'length+3)/4;
constant pad : BIT_VECTOR(1 to (result_length*4 - value'length))
:= (others => value (value'left)); -- Extend sign bit
begin
return to_hstring(pad & BIT_VECTOR (value));
end function to_hstring;
procedure READ(L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN) is
variable ivalue : BIT_VECTOR(value'range);
begin
READ (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := UNSIGNED(ivalue);
end procedure READ;
procedure READ(L : inout LINE; VALUE : out UNSIGNED) is
variable ivalue : BIT_VECTOR(value'range);
begin
READ (L => L,
VALUE => ivalue);
VALUE := UNSIGNED (ivalue);
end procedure READ;
procedure READ(L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN) is
variable ivalue : BIT_VECTOR(value'range);
begin
READ (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := SIGNED(ivalue);
end procedure READ;
procedure READ(L : inout LINE; VALUE : out SIGNED) is
variable ivalue : BIT_VECTOR(value'range);
begin
READ (L => L,
VALUE => ivalue);
VALUE := SIGNED (ivalue);
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : BIT_VECTOR(value'range);
begin
ivalue := BIT_VECTOR (VALUE);
WRITE (L => L,
VALUE => ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure WRITE;
procedure WRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : BIT_VECTOR(value'range);
begin
ivalue := BIT_VECTOR (VALUE);
WRITE (L => L,
VALUE => ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure WRITE;
procedure OREAD (L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN) is
variable ivalue : BIT_VECTOR(value'range);
begin
OREAD (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := UNSIGNED(ivalue);
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN) is
constant ne : INTEGER := (value'length+2)/3;
constant pad : INTEGER := ne*3 - value'length;
variable ivalue : BIT_VECTOR(0 to ne*3-1);
variable ok : BOOLEAN;
begin
OREAD (L => L,
VALUE => ivalue, -- Read padded STRING
good => ok);
-- Bail out if there was a bad read
if not ok then
good := false;
return;
end if;
if (pad > 0) then
if (ivalue(0) = '0') then -- positive
if ivalue(0) = or (ivalue(0 to pad)) then
VALUE := SIGNED (ivalue (pad to ivalue'high));
good := true;
else
good := false;
end if;
else -- negative
if ivalue(0) = and (ivalue(0 to pad)) then
VALUE := SIGNED (ivalue (pad to ivalue'high));
good := true;
else
good := false;
end if;
end if;
else
good := true;
VALUE := SIGNED (ivalue);
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out UNSIGNED) is
variable ivalue : BIT_VECTOR(value'range);
begin
OREAD (L => L,
VALUE => ivalue);
VALUE := UNSIGNED (ivalue);
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out SIGNED) is
constant ne : INTEGER := (value'length+2)/3;
constant pad : INTEGER := ne*3 - value'length;
variable ivalue : BIT_VECTOR(0 to ne*3-1);
begin
OREAD (L => L,
VALUE => ivalue); -- Read padded string
if (pad > 0) then
if (ivalue(0) = '0') then -- positive
if ivalue(0) = or (ivalue(0 to pad)) then
VALUE := SIGNED (ivalue (pad to ivalue'high));
else
assert false
report "NUMERIC_BIT.OREAD Error: Signed vector truncated"
severity error;
end if;
else -- negative
if ivalue(0) = and (ivalue(0 to pad)) then
VALUE := SIGNED (ivalue (pad to ivalue'high));
else
assert false
report "NUMERIC_BIT.OREAD Error: Signed vector truncated"
severity error;
end if;
end if;
else
VALUE := SIGNED (ivalue);
end if;
end procedure OREAD;
procedure HREAD (L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN) is
variable ivalue : BIT_VECTOR(value'range);
begin
HREAD (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := UNSIGNED(ivalue);
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN) is
constant ne : INTEGER := (value'length+3)/4;
constant pad : INTEGER := ne*4 - value'length;
variable ivalue : BIT_VECTOR(0 to ne*4-1);
variable ok : BOOLEAN;
begin
HREAD (L => L,
VALUE => ivalue, -- Read padded STRING
good => ok);
if not ok then
good := false;
return;
end if;
if (pad > 0) then
if (ivalue(0) = '0') then -- positive
if ivalue(0) = or (ivalue(0 to pad)) then
GOOD := true;
VALUE := SIGNED (ivalue (pad to ivalue'high));
else
GOOD := false;
end if;
else -- negative
if ivalue(0) = and (ivalue(0 to pad)) then
GOOD := true;
VALUE := SIGNED (ivalue (pad to ivalue'high));
else
GOOD := false;
end if;
end if;
else
GOOD := true;
VALUE := SIGNED (ivalue);
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out UNSIGNED) is
variable ivalue : BIT_VECTOR(value'range);
begin
HREAD (L => L,
VALUE => ivalue);
VALUE := UNSIGNED (ivalue);
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out SIGNED) is
constant ne : INTEGER := (value'length+3)/4;
constant pad : INTEGER := ne*4 - value'length;
variable ivalue : BIT_VECTOR(0 to ne*4-1);
begin
HREAD (L => L,
VALUE => ivalue); -- Read padded string
if (pad > 0) then
if (ivalue(0) = '0') then -- positive
if ivalue(0) = or (ivalue(0 to pad)) then
VALUE := SIGNED (ivalue (pad to ivalue'high));
else
assert false
report "NUMERIC_BIT.HREAD Error: Signed vector truncated"
severity error;
end if;
else -- negative
if ivalue(0) = and (ivalue(0 to pad)) then
VALUE := SIGNED (ivalue (pad to ivalue'high));
else
assert false
report "NUMERIC_BIT.HREAD Error: Signed vector truncated"
severity error;
end if;
end if;
else
VALUE := SIGNED (ivalue);
end if;
end procedure HREAD;
procedure OWRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : BIT_VECTOR(value'range);
begin
ivalue := BIT_VECTOR (VALUE);
OWRITE (L => L,
VALUE => ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure OWRITE;
procedure OWRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : BIT_VECTOR(0 to (ne*3 - VALUE'length) - 1)
:= (others => VALUE (VALUE'left));
variable ivalue : BIT_VECTOR(value'range);
begin
ivalue := BIT_VECTOR (VALUE);
OWRITE (L => L,
VALUE => pad & ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure OWRITE;
procedure HWRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : BIT_VECTOR(value'range);
begin
ivalue := BIT_VECTOR (VALUE);
HWRITE (L => L,
VALUE => ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure HWRITE;
procedure HWRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : BIT_VECTOR(value'range);
constant ne : INTEGER := (value'length+3)/4;
constant pad : BIT_VECTOR(0 to (ne*4 - value'length) - 1)
:= (others => VALUE(VALUE'left));
begin
ivalue := BIT_VECTOR (VALUE);
HWRITE (L => L,
VALUE => pad & ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure HWRITE;
end package body NUMERIC_BIT;
|
gpl-2.0
|
06f150084ffc65be1fada3afd233223e
| 0.545662 | 3.954108 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_02.vhd
| 4 | 4,147 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_08_fg_08_02.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity address_decoder is
port ( addr : in work.cpu_types.address;
status : in work.cpu_types.status_value;
mem_sel, int_sel, io_sel : out bit );
end entity address_decoder;
--------------------------------------------------
architecture functional of address_decoder is
constant mem_low : work.cpu_types.address := X"000000";
constant mem_high : work.cpu_types.address := X"EFFFFF";
constant io_low : work.cpu_types.address := X"F00000";
constant io_high : work.cpu_types.address := X"FFFFFF";
begin
mem_decoder :
mem_sel <= '1' when ( work.cpu_types."="(status, work.cpu_types.fetch)
or work.cpu_types."="(status, work.cpu_types.mem_read)
or work.cpu_types."="(status, work.cpu_types.mem_write) )
and addr >= mem_low
and addr <= mem_high else
'0';
int_decoder :
int_sel <= '1' when work.cpu_types."="(status, work.cpu_types.int_ack) else
'0';
io_decoder :
io_sel <= '1' when ( work.cpu_types."="(status, work.cpu_types.io_read)
or work.cpu_types."="(status, work.cpu_types.io_write) )
and addr >= io_low
and addr <= io_high else
'0';
end architecture functional;
-- not in book
entity fg_08_02 is
end entity fg_08_02;
architecture test of fg_08_02 is
use work.cpu_types.all;
signal addr : address := X"000000";
signal status : status_value := idle;
signal mem_sel, int_sel, io_sel : bit;
begin
dut : entity work.address_decoder
port map ( addr => addr, status => status,
mem_sel => mem_sel, int_sel => int_sel, io_sel => io_sel );
stimulus : process is
begin
wait for 10 ns;
status <= fetch; wait for 10 ns;
status <= mem_read; wait for 10 ns;
status <= mem_write; wait for 10 ns;
status <= io_read; wait for 10 ns;
status <= io_write; wait for 10 ns;
status <= int_ack; wait for 10 ns;
status <= idle; wait for 10 ns;
addr <= X"EFFFFF"; wait for 10 ns;
status <= fetch; wait for 10 ns;
status <= mem_read; wait for 10 ns;
status <= mem_write; wait for 10 ns;
status <= io_read; wait for 10 ns;
status <= io_write; wait for 10 ns;
status <= int_ack; wait for 10 ns;
status <= idle; wait for 10 ns;
addr <= X"F00000"; wait for 10 ns;
status <= fetch; wait for 10 ns;
status <= mem_read; wait for 10 ns;
status <= mem_write; wait for 10 ns;
status <= io_read; wait for 10 ns;
status <= io_write; wait for 10 ns;
status <= int_ack; wait for 10 ns;
status <= idle; wait for 10 ns;
addr <= X"FFFFFF"; wait for 10 ns;
status <= fetch; wait for 10 ns;
status <= mem_read; wait for 10 ns;
status <= mem_write; wait for 10 ns;
status <= io_read; wait for 10 ns;
status <= io_write; wait for 10 ns;
status <= int_ack; wait for 10 ns;
status <= idle; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
-- end not in book
|
gpl-2.0
|
ab1f3077195756aa72ca1375acb15993
| 0.579214 | 3.625 | false | false | false | false |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/to_send/ngnp_added_monitor/ngnp/src/tmp/mb_lite/std_Pkg.vhd
| 3 | 9,398 |
----------------------------------------------------------------------------------------------
--
-- Input file : std_Pkg.vhd
-- Design name : std_Pkg
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Package with several standard components.
--
----------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
PACKAGE std_Pkg IS
----------------------------------------------------------------------------------------------
-- STANDARD COMPONENTS IN STD_PKG
----------------------------------------------------------------------------------------------
COMPONENT sram GENERIC
(
WIDTH : positive;
SIZE : positive
);
PORT
(
dat_o : OUT std_ulogic_vector(WIDTH - 1 DOWNTO 0);
dat_i : IN std_ulogic_vector(WIDTH - 1 DOWNTO 0);
adr_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
wre_i : IN std_ulogic;
ena_i : IN std_ulogic;
clk_i : IN std_ulogic
);
END COMPONENT;
COMPONENT sram_4en GENERIC
(
WIDTH : positive;
SIZE : positive
);
PORT
(
dat_o : OUT std_ulogic_vector(WIDTH - 1 DOWNTO 0);
dat_i : IN std_ulogic_vector(WIDTH - 1 DOWNTO 0);
adr_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
wre_i : IN std_ulogic_vector(3 DOWNTO 0);
ena_i : IN std_ulogic;
clk_i : IN std_ulogic
);
END COMPONENT;
COMPONENT dsram GENERIC
(
WIDTH : positive;
SIZE : positive
);
PORT
(
dat_o : OUT std_ulogic_vector(WIDTH - 1 DOWNTO 0);
adr_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
ena_i : IN std_ulogic;
dat_w_i : IN std_ulogic_vector(WIDTH - 1 DOWNTO 0);
adr_w_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
wre_i : IN std_ulogic;
clk_i : IN std_ulogic
);
END COMPONENT;
----------------------------------------------------------------------------------------------
-- FUNCTIONS IN STD_PKG
----------------------------------------------------------------------------------------------
FUNCTION v_or(d : std_ulogic_vector) RETURN std_ulogic;
FUNCTION is_zero(d : std_ulogic_vector) RETURN std_ulogic;
FUNCTION is_not_zero(d : std_ulogic_vector) RETURN std_ulogic;
FUNCTION my_conv_integer(a: std_ulogic_vector) RETURN integer;
FUNCTION notx(d : std_ulogic_vector) RETURN boolean;
FUNCTION compare(a, b : std_ulogic_vector) RETURN std_ulogic;
FUNCTION multiply(a, b : std_ulogic_vector) RETURN std_ulogic_vector;
FUNCTION sign_extend(value: std_ulogic_vector; fill: std_ulogic; size: positive) RETURN std_ulogic_vector;
FUNCTION add(a, b : std_ulogic_vector; ci: std_ulogic) RETURN std_ulogic_vector;
FUNCTION increment(a : std_ulogic_vector) RETURN std_ulogic_vector;
FUNCTION shift(value : std_ulogic_vector(31 DOWNTO 0); shamt: std_ulogic_vector(4 DOWNTO 0); s: std_ulogic; t: std_ulogic) RETURN std_ulogic_vector;
FUNCTION shift_left(value : std_ulogic_vector(31 DOWNTO 0); shamt : std_ulogic_vector(4 DOWNTO 0)) RETURN std_ulogic_vector;
FUNCTION shift_right(value : std_ulogic_vector(31 DOWNTO 0); shamt : std_ulogic_vector(4 DOWNTO 0); padding: std_ulogic) RETURN std_ulogic_vector;
END std_Pkg;
PACKAGE BODY std_Pkg IS
-- Unary OR reduction
FUNCTION v_or(d : std_ulogic_vector) RETURN std_ulogic IS
VARIABLE z : std_ulogic;
BEGIN
z := '0';
IF notx (d) THEN
FOR i IN d'range LOOP
z := z OR d(i);
END LOOP;
END IF;
RETURN z;
END;
-- Check for ones in the vector
FUNCTION is_not_zero(d : std_ulogic_vector) RETURN std_ulogic IS
VARIABLE z : std_ulogic_vector(d'range);
BEGIN
z := (OTHERS => '0');
IF notx(d) THEN
IF d = z THEN
RETURN '0';
ELSE
RETURN '1';
END IF;
ELSE
RETURN '0';
END IF;
END;
-- Check for ones in the vector
FUNCTION is_zero(d : std_ulogic_vector) RETURN std_ulogic IS
BEGIN
RETURN NOT is_not_zero(d);
END;
-- rewrite conv_integer to avoid modelsim warnings
FUNCTION my_conv_integer(a : std_ulogic_vector) RETURN integer IS
VARIABLE res : integer RANGE 0 TO 2**a'length-1;
BEGIN
res := 0;
IF (notx(a)) THEN
res := to_integer(unsigned(a));
END IF;
RETURN res;
END;
FUNCTION compare(a, b : std_ulogic_vector) RETURN std_ulogic IS
VARIABLE z : std_ulogic;
BEGIN
IF notx(a & b) AND a = b THEN
RETURN '1';
ELSE
RETURN '0';
END IF;
END;
-- Unary NOT X test
FUNCTION notx(d : std_ulogic_vector) RETURN boolean IS
VARIABLE res : boolean;
BEGIN
res := true;
-- pragma translate_off
res := NOT is_x(d);
-- pragma translate_on
RETURN (res);
END;
-- -- 32 bit shifter
-- -- SYNOPSIS:
-- -- value: value to be shifted
-- -- shamt: shift amount
-- -- s 0 / 1: shift right / left
-- -- t 0 / 1: shift logical / arithmetic
-- -- PSEUDOCODE (from microblaze reference guide)
-- -- if S = 1 then
-- -- (rD) ← (rA) << (rB)[27:31]
-- -- else
-- -- if T = 1 then
-- -- if ((rB)[27:31]) ≠ 0 then
-- -- (rD)[0:(rB)[27:31]-1] ← (rA)[0]
-- -- (rD)[(rB)[27:31]:31] ← (rA) >> (rB)[27:31]
-- -- else
-- -- (rD) ← (rA)
-- -- else
-- -- (rD) ← (rA) >> (rB)[27:31]
FUNCTION shift(value: std_ulogic_vector(31 DOWNTO 0); shamt: std_ulogic_vector(4 DOWNTO 0); s: std_ulogic; t: std_ulogic) RETURN std_ulogic_vector IS
BEGIN
IF s = '1' THEN
-- left arithmetic or logical shift
RETURN shift_left(value, shamt);
ELSE
IF t = '1' THEN
-- right arithmetic shift
RETURN shift_right(value, shamt, value(31));
ELSE
-- right logical shift
RETURN shift_right(value, shamt, '0');
END IF;
END IF;
END;
FUNCTION shift_left(value: std_ulogic_vector(31 DOWNTO 0); shamt: std_ulogic_vector(4 DOWNTO 0)) RETURN std_ulogic_vector IS
VARIABLE result: std_ulogic_vector(31 DOWNTO 0);
VARIABLE paddings: std_ulogic_vector(15 DOWNTO 0);
BEGIN
paddings := (OTHERS => '0');
result := value;
IF (shamt(4) = '1') THEN result := result(15 DOWNTO 0) & paddings(15 DOWNTO 0); END IF;
IF (shamt(3) = '1') THEN result := result(23 DOWNTO 0) & paddings( 7 DOWNTO 0); END IF;
IF (shamt(2) = '1') THEN result := result(27 DOWNTO 0) & paddings( 3 DOWNTO 0); END IF;
IF (shamt(1) = '1') THEN result := result(29 DOWNTO 0) & paddings( 1 DOWNTO 0); END IF;
IF (shamt(0) = '1') THEN result := result(30 DOWNTO 0) & paddings( 0 ); END IF;
RETURN result;
END;
FUNCTION shift_right(value: std_ulogic_vector(31 DOWNTO 0); shamt: std_ulogic_vector(4 DOWNTO 0); padding: std_ulogic) RETURN std_ulogic_vector IS
VARIABLE result: std_ulogic_vector(31 DOWNTO 0);
VARIABLE paddings: std_ulogic_vector(15 DOWNTO 0);
BEGIN
paddings := (OTHERS => padding);
result := value;
IF (shamt(4) = '1') THEN result := paddings(15 DOWNTO 0) & result(31 DOWNTO 16); END IF;
IF (shamt(3) = '1') THEN result := paddings( 7 DOWNTO 0) & result(31 DOWNTO 8); END IF;
IF (shamt(2) = '1') THEN result := paddings( 3 DOWNTO 0) & result(31 DOWNTO 4); END IF;
IF (shamt(1) = '1') THEN result := paddings( 1 DOWNTO 0) & result(31 DOWNTO 2); END IF;
IF (shamt(0) = '1') THEN result := paddings( 0 ) & result(31 DOWNTO 1); END IF;
RETURN result;
END;
FUNCTION multiply(a, b: std_ulogic_vector) RETURN std_ulogic_vector IS
VARIABLE x: std_ulogic_vector (a'length + b'length - 1 DOWNTO 0);
BEGIN
x := std_ulogic_vector(signed(a) * signed(b));
RETURN x(31 DOWNTO 0);
END;
FUNCTION sign_extend(value: std_ulogic_vector; fill: std_ulogic; size: positive) RETURN std_ulogic_vector IS
VARIABLE a: std_ulogic_vector (size - 1 DOWNTO 0);
BEGIN
a(size - 1 DOWNTO value'length) := (OTHERS => fill);
a(value'length - 1 DOWNTO 0) := value;
return a;
END;
FUNCTION add(a, b : std_ulogic_vector; ci: std_ulogic) RETURN std_ulogic_vector IS
VARIABLE x : std_ulogic_vector(a'length + 1 DOWNTO 0);
BEGIN
x := (OTHERS => '0');
IF notx (a & b & ci) THEN
x := std_ulogic_vector(signed('0' & a & '1') + signed('0' & b & ci));
END IF;
RETURN x(a'length + 1 DOWNTO 1);
END;
FUNCTION increment(a : std_ulogic_vector) RETURN std_ulogic_vector IS
VARIABLE x : std_ulogic_vector(a'length-1 DOWNTO 0);
BEGIN
x := (OTHERS => '0');
IF notx (a) THEN
x := std_ulogic_vector(signed(a) + 1);
END IF;
RETURN x;
END;
END std_Pkg;
|
mit
|
b87bcd59bba84922190bce91b1b9ff40
| 0.527914 | 3.740933 | false | false | false | false |
tristanseifert/68komputer
|
sdr_control_interface.vhd
| 1 | 9,357 |
--###########################################################################
--
-- LOGIC CORE: Control Interface - Top level module
-- MODULE NAME: control_interface()
-- COMPANY: Altera Corporation
-- www.altera.com
--
-- REVISION HISTORY:
--
-- Revision 1.1 06/06/2000 Description: Initial Release.
--
-- FUNCTIONAL DESCRIPTION:
--
-- This module is the command interface module for the SDR SDRAM controller.
--
-- Copyright (C) 1991-2000 Altera Corporation
--
--##########################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity sdr_control_interface is
generic (ASIZE : integer := 32);
port (
CLK : in std_logic; -- System Clock
RESET_N : in std_logic; -- System Reset
CMD : in std_logic_vector(2 downto 0); -- Command input
ADDR : in std_logic_vector(ASIZE-1 downto 0); -- Address
REF_ACK : in std_logic; -- Refresh request acknowledge
CM_ACK : in std_logic; -- Command acknowledge
NOP : out std_logic; -- Decoded NOP command
READA : out std_logic; -- Decoded READA command
WRITEA : out std_logic; -- Decoded WRITEA command
REFRESH : out std_logic; -- Decoded REFRESH command
PRECHARGE : out std_logic; -- Decoded PRECHARGE command
LOAD_MODE : out std_logic; -- Decoded LOAD_MODE command
SADDR : out std_logic_vector(ASIZE-1 downto 0); -- Registered version of ADDR
SC_CL : out std_logic_vector(1 downto 0); -- Programmed CAS latency
SC_RC : out std_logic_vector(1 downto 0); -- Programmed RC delay
SC_RRD : out std_logic_vector(3 downto 0); -- Programmed RRD delay
SC_PM : out std_logic; -- programmed Page Mode
SC_BL : out std_logic_vector(3 downto 0); -- Programmed burst length
REF_REQ : out std_logic; -- Hidden refresh request
CMD_ACK : out std_logic -- Command acknowledge
);
end sdr_control_interface;
architecture RTL of sdr_control_interface is
-- signal declarations
signal LOAD_REG1 : std_logic;
signal LOAD_REG2 : std_logic;
signal REF_PER : std_logic_vector(15 downto 0);
signal timer : signed(15 downto 0);
signal timer_zero : std_logic;
signal SADDR_int : std_logic_vector(ASIZE-1 downto 0);
signal CMD_ACK_int : std_logic;
signal SC_BL_int : std_logic_vector(3 downto 0);
begin
-- This module decodes the commands from the CMD input to individual
-- command lines, NOP, READA, WRITEA, REFRESH, PRECHARGE, LOAD_MODE.
-- ADDR is register in order to keep it aligned with decoded command.
process(CLK, RESET_N)
begin
if (RESET_N = '0') then
NOP <= '0';
READA <= '0';
WRITEA <= '0';
REFRESH <= '0';
PRECHARGE <= '0';
LOAD_MODE <= '0';
load_reg1 <= '0';
load_reg2 <= '0';
SADDR_int <= (others => '0');
elsif rising_edge(CLK) then
SADDR_int <= ADDR; -- register the address to keep proper
-- alignment with the command
if (CMD = "000") then -- NOP command
NOP <= '1';
else
NOP <= '0';
end if;
if (CMD = "001") then -- READA command
READA <= '1';
else
READA <= '0';
end if;
if (CMD = "010") then -- WRITEA command
WRITEA <= '1';
else
WRITEA <= '0';
end if;
if (CMD = "011") then -- REFRESH command
REFRESH <= '1';
else
REFRESH <= '0';
end if;
if (CMD = "100") then -- PRECHARGE command
PRECHARGE <= '1';
else
PRECHARGE <= '0';
end if;
if (CMD = "101") then -- LOAD_MODE command
LOAD_MODE <= '1';
else
LOAD_MODE <= '0';
end if;
if ((CMD = "110") and (LOAD_REG1 = '0')) then --LOAD_REG1 command
LOAD_REG1 <= '1';
else
LOAD_REG1 <= '0';
end if;
if ((CMD = "111") and (LOAD_REG2 = '0')) then --LOAD_REG2 command
LOAD_REG2 <= '1';
else
LOAD_REG2 <= '0';
end if;
end if;
end process;
-- This always block processes the LOAD_REG1 and LOAD_REG2 commands.
-- The register data comes in on SADDR and is distributed to the various
-- registers.
process(CLK, RESET_N)
begin
if (RESET_N = '0') then
SC_CL <= (others => '0');
SC_RC <= (others => '0');
SC_RRD <= (others => '0');
SC_PM <= '0';
SC_BL_int <= (others => '0');
REF_PER <= (others => '0');
elsif rising_edge(CLK) then
if (LOAD_REG1 = '1') then -- LOAD_REG1 command
SC_CL <= SADDR_int(1 downto 0); -- CAS Latency
SC_RC <= SADDR_int(3 downto 2); -- RC delay
SC_RRD <= SADDR_int(7 downto 4); -- RRD delay
SC_PM <= SADDR_int(8); -- Page Mode
SC_BL_int <= SADDR_int(12 downto 9); -- Burst length
end if;
if (LOAD_REG2 = '1') then -- LOAD_REG2 command
REF_PER <= SADDR_int(15 downto 0); -- REFRESH Period
end if;
end if;
end process;
SADDR <= SADDR_int;
SC_BL <= SC_BL_int;
-- This always block generates the command acknowledge, CMD_ACK, for the
-- commands that are handled by this module, LOAD_RE1,2, and it lets
-- the command ack from the lower module pass through when necessary.
process(CLK, RESET_N)
begin
if (RESET_N = '0') then
CMD_ACK_int <= '0';
elsif rising_edge(CLK) then
if (((CM_ACK = '1') or (LOAD_REG1 = '1') or (LOAD_REG2 = '1')) and (CMD_ACK_int = '0')) then
CMD_ACK_int <= '1';
else
CMD_ACK_int <= '0';
end if;
end if;
end process;
CMD_ACK <= CMD_ACK_int;
-- This always block implements the refresh timer. The timer is a 16bit
-- downcounter and a REF_REQ is generated whenever the counter reaches the
-- count of zero. After reaching zero, the counter reloads with the value that
-- was loaded into the refresh period register with the LOAD_REG2 command.
-- Note that the refresh counter is disabled when the controller is in
-- page mode operation.
process(CLK, RESET_N)
begin
if (RESET_N = '0') then
timer <= (others => '0');
timer_zero <= '0';
REF_REQ <= '0';
elsif rising_edge(CLK) then
if (timer_zero = '1') then
timer <= signed(REF_PER);
elsif (not (SC_BL_int = "0000")) then -- only run timer if not in page mode
timer <= timer - 1;
end if;
if (timer=0 and not (SC_BL_int = "0000")) then
timer_zero <= '1'; -- count has reached zero, issue ref_req and reload
REF_REQ <= '1'; -- the timer
else
if (REF_ACK = '1') then -- wait for the ack to come back from the lower
timer_zero <= '0';
REF_REQ <= '0';
end if;
end if;
end if;
end process;
end RTL;
|
bsd-2-clause
|
caac855a957e89e443de018e0ef25f7c
| 0.409105 | 4.632178 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/perf02/tb.vhd
| 1 | 11,144 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity tb is
end tb;
architecture augh of tb is
constant simu_max_cycles : natural := 100000;
constant simu_disp_cycles : std_logic := '1';
constant simu_err_end_in : std_logic := '0';
constant reset_cycles : natural := 4;
component top is
port (
clock : in std_logic;
reset : in std_logic;
start : in std_logic;
stdin_rdy : out std_logic;
stdin_ack : in std_logic;
stdout_data : out std_logic_vector(31 downto 0);
stdout_rdy : out std_logic;
stdout_ack : in std_logic;
stdin_data : in std_logic_vector(31 downto 0)
);
end component;
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal start : std_logic := '0';
signal clock_next : std_logic := '0';
-- Access 'clock' model 'clock'
-- Access 'reset' model 'reset'
-- Access 'start' model 'start'
-- Access 'stdin' model 'fifo_in'
signal stdin_data : std_logic_vector(31 downto 0) := (others => '0');
signal stdin_rdy : std_logic := '0';
signal stdin_ack : std_logic := '0';
signal stdin_vector_idx : natural := 0;
signal stdin_vector : std_logic_vector(31 downto 0) := (others => '0');
-- Test vectors
constant stdin_vectors_nb : natural := 100;
type stdin_vec_type is array (0 to stdin_vectors_nb-1) of std_logic_vector(31 downto 0);
constant stdin_vectors : stdin_vec_type := (
X"00000044", X"00000044", X"00000044", X"00000044", X"00000044", X"00000044", X"00000044", X"00000044",
X"00000044", X"00000044", X"00000044", X"00000044", X"00000044", X"00000044", X"00000044", X"00000044",
X"00000044", X"00000043", X"00000043", X"00000043", X"00000043", X"00000043", X"00000043", X"00000043",
X"00000042", X"00000042", X"00000042", X"00000042", X"00000042", X"00000042", X"00000041", X"00000041",
X"00000041", X"00000041", X"00000041", X"00000040", X"00000040", X"00000040", X"00000040", X"00000040",
X"00000040", X"00000040", X"00000040", X"0000003f", X"0000003f", X"0000003f", X"0000003f", X"0000003f",
X"0000003e", X"0000003e", X"0000003e", X"0000003e", X"0000003e", X"0000003e", X"0000003d", X"0000003d",
X"0000003d", X"0000003d", X"0000003d", X"0000003d", X"0000003c", X"0000003c", X"0000003c", X"0000003c",
X"0000003c", X"0000003c", X"0000003c", X"0000003c", X"0000003c", X"0000003b", X"0000003b", X"0000003b",
X"0000003b", X"0000003b", X"0000003b", X"0000003b", X"0000003b", X"0000003b", X"0000003b", X"0000003b",
X"0000003b", X"0000003b", X"0000003b", X"0000003b", X"0000003b", X"0000003b", X"0000003b", X"0000003b",
X"0000003b", X"0000003b", X"0000003b", X"0000003b", X"0000003c", X"0000003c", X"0000003c", X"0000003c",
X"0000003c", X"0000003c", X"0000003c", X"0000003c"
);
-- Access 'stdout' model 'fifo_out'
signal stdout_data : std_logic_vector(31 downto 0) := (others => '0');
signal stdout_rdy : std_logic := '0';
signal stdout_ack : std_logic := '0';
signal stdout_vector_idx : natural := 0;
signal stdout_vector : std_logic_vector(31 downto 0) := (others => '0');
-- Test vectors
constant stdout_vectors_nb : natural := 150;
type stdout_vec_type is array (0 to stdout_vectors_nb-1) of std_logic_vector(31 downto 0);
constant stdout_vectors : stdout_vec_type := (
X"000000fd", X"000000de", X"00000077", X"000000ba", X"000000f4", X"00000092", X"00000020", X"000000a0",
X"000000ec", X"000000ed", X"000000ee", X"000000f0", X"000000f1", X"000000f1", X"000000f2", X"000000f3",
X"000000f4", X"000000f4", X"000000f3", X"000000f5", X"000000f5", X"000000f5", X"000000f6", X"000000f6",
X"000000f6", X"000000f7", X"000000f8", X"000000f6", X"000000f7", X"000000f8", X"000000f7", X"000000f8",
X"000000f8", X"000000f6", X"000000f8", X"000000f8", X"000000f7", X"000000f9", X"000000f9", X"000000f8",
X"000000f8", X"000000f8", X"000000f7", X"000000fa", X"000000fb", X"000000fb", X"000000fa", X"000000fb",
X"000000fb", X"000000fb", X"00000000", X"00000000", X"00000000", X"00000000", X"ffffffff", X"00000000",
X"00000000", X"ffffffff", X"00000000", X"00000000", X"ffffffff", X"ffffffff", X"00000000", X"00000000",
X"ffffffff", X"fffffffd", X"fffffffe", X"fffffffd", X"ffffffff", X"fffffffc", X"00000000", X"ffffffff",
X"ffffffff", X"fffffffb", X"00000000", X"00000000", X"ffffffff", X"00000004", X"0000000b", X"00000009",
X"0000000b", X"0000000d", X"00000011", X"00000010", X"00000014", X"00000013", X"00000016", X"00000013",
X"00000016", X"00000017", X"0000001a", X"0000001a", X"0000001d", X"0000001e", X"00000021", X"0000001f",
X"0000001e", X"0000001a", X"0000001e", X"00000020", X"00000026", X"00000025", X"00000026", X"00000023",
X"00000025", X"00000024", X"00000027", X"00000025", X"00000028", X"00000028", X"0000002b", X"00000029",
X"0000002d", X"0000002e", X"0000002f", X"00000028", X"00000027", X"00000027", X"0000002d", X"0000002f",
X"00000031", X"0000002d", X"0000002d", X"0000002c", X"00000031", X"00000030", X"0000002f", X"00000028",
X"0000002a", X"0000002d", X"00000033", X"00000030", X"0000002e", X"00000029", X"0000002d", X"00000030",
X"00000037", X"00000035", X"00000035", X"00000030", X"00000030", X"0000002e", X"00000031", X"0000002e",
X"0000002f", X"0000002c", X"00000031", X"00000034", X"0000003a", X"0000003a"
);
signal clock_counter : natural := 0;
signal clock_counter_stop : natural := 0;
signal errors_nb : natural := 0;
-- Defined in VHDL 2008, not handled by GHDL
function to_string(sv: std_logic_vector) return string is
variable bv: bit_vector(sv'range) := to_bitvector(sv);
variable lp: line;
begin
write(lp, bv);
return lp.all;
end;
begin
-- Instantiation of the main component
top_i : top port map (
-- Access 'clock' model 'clock'
clock => clock,
-- Access 'reset' model 'reset'
reset => reset,
-- Access 'start' model 'start'
start => start,
-- Access 'stdin' model 'fifo_in'
stdin_data => stdin_data,
stdin_rdy => stdin_rdy,
stdin_ack => stdin_ack,
-- Access 'stdout' model 'fifo_out'
stdout_data => stdout_data,
stdout_rdy => stdout_rdy,
stdout_ack => stdout_ack
);
-- Functionality for top-level access 'clock' model 'clock'
-- Generation of clock: 100MHz (note: arbitrary value)
clock <= clock_next after 5 ns;
clock_next <= not clock when clock_counter_stop = 0 or clock_counter <= clock_counter_stop else '0';
-- Clock counter and global messages
process (clock)
-- To print simulation messages
variable l : line;
begin
-- Increment clock counter
if rising_edge(clock) then
clock_counter <= clock_counter + 1;
if simu_disp_cycles = '1' then
-- Write simulation message
write(l, string'("INFO clock cycle "));
write(l, clock_counter);
writeline(output, l);
end if;
end if;
-- Messages
if falling_edge(clock) then
if clock_counter > simu_max_cycles then
report "ERROR Too many cycles simulated. Stopping simulation." severity failure;
end if;
if clock_counter < reset_cycles then
report "INFO Reset" severity note;
end if;
if clock_counter = reset_cycles then
report "INFO Start" severity note;
end if;
end if;
end process;
-- Functionality for top-level access 'reset' model 'reset'
-- Generation of reset
reset <= '1' when clock_counter < reset_cycles else '0';
-- Functionality for top-level access 'start' model 'start'
-- Generation of start
start <= '1';
-- Functionality for top-level access 'stdin' model 'fifo_in'
-- FIFO stdin
-- Sending inputs
stdin_vector <= stdin_vectors(stdin_vector_idx) when stdin_vector_idx < stdin_vectors_nb else (others => '0');
stdin_data <= stdin_vector(31 downto 0);
stdin_ack <= '1' when reset = '0' and stdin_vector_idx < stdin_vectors_nb else '0';
process (clock)
-- To print simulation messages
variable l : line;
begin
if rising_edge(clock) then
if stdin_vector_idx < stdin_vectors_nb then
if stdin_rdy = '1' and stdin_ack = '1' and reset = '0' then
-- Write simulation message
write(l, string'("INFO Input vector "));
write(l, stdin_vector_idx);
write(l, string'(" at cycle "));
write(l, clock_counter);
writeline(output, l);
if stdin_vector_idx = 0 then
write(l, string'("INFO First input vector sent at clock cycle "));
write(l, clock_counter);
writeline(output, l);
end if;
if stdin_vector_idx = stdin_vectors_nb - 1 then
write(l, string'("INFO Last input vector sent at clock cycle "));
write(l, clock_counter);
writeline(output, l);
end if;
-- Increase vector index
stdin_vector_idx <= stdin_vector_idx + 1;
end if; -- Handshake
else
if stdin_rdy = '1' and reset = '0' then
if simu_err_end_in = '1' then
report "ERROR Out of input vectors. Stopping simulation." severity failure;
end if;
end if; -- Handshake
end if;
end if;
end process;
-- Functionality for top-level access 'stdout' model 'fifo_out'
-- FIFO stdout
-- Checking outputs
-- Always enable output FIFO
stdout_ack <= '1' when stdout_vector_idx < stdout_vectors_nb and reset = '0' else '0';
stdout_vector <= stdout_vectors(stdout_vector_idx) when stdout_vector_idx < stdout_vectors_nb else (others => '0');
-- Check outputs
process (clock)
variable l : line;
begin
if rising_edge(clock) then
if stdout_vector_idx < stdout_vectors_nb then
if stdout_rdy = '1' and stdout_ack = '1' and reset = '0' then
if stdout_data = stdout_vector(31 downto 0) then
-- The vector is verified
write(l, string'("INFO Output nb "));
write(l, stdout_vector_idx);
write(l, string'(" at cycle "));
write(l, clock_counter);
write(l, string'(" (check OK)"));
write(l, string'(" Obtained "));
write(l, to_string(stdout_data));
writeline(output, l);
else
-- An error is detected
write(l, string'("ERROR Output nb "));
write(l, stdout_vector_idx);
write(l, string'(" at cycle "));
write(l, clock_counter);
writeline(output, l);
write(l, string'(" Obtained "));
write(l, to_string(stdout_data));
writeline(output, l);
write(l, string'(" Expected "));
write(l, to_string(stdout_vector(31 downto 0)));
writeline(output, l);
errors_nb <= errors_nb + 1;
--report "ERROR A simulation error was found." severity failure;
end if;
if stdout_vector_idx = stdout_vectors_nb - 1 then
write(l, string'("INFO Last output vector read at cycle "));
write(l, clock_counter);
writeline(output, l);
report "INFO Stopping simulation." severity note;
clock_counter_stop <= clock_counter + 3;
end if;
-- Increase vector index
stdout_vector_idx <= stdout_vector_idx + 1;
end if; -- FIFO handshake
else
-- All vectors have been read
if errors_nb > 0 then
write(l, string'("ERROR Number of errors found : "));
write(l, errors_nb);
writeline(output, l);
report "ERROR Simulation errors were found." severity failure;
end if;
end if; -- Check all vectors read
end if; -- Clock
end process;
end augh;
|
gpl-2.0
|
4be3389d656d3bb9867d705102b9fbd2
| 0.651651 | 3.034032 | false | false | false | false |
peteut/ghdl
|
libraries/std/textio.vhdl
| 4 | 6,984 |
-- Std.Textio package declaration. This file is part of GHDL.
-- This file was written from the clause 14.3 of the VHDL LRM.
-- Copyright (C) 2002 - 2014 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation; either version 2, or (at your option) any later
-- version.
--
-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with GCC; see the file COPYING3. If not see
-- <http://www.gnu.org/licenses/>.
package Textio is
-- type definitions for text i/o
-- a LINE is a pointer to a string value.
type Line is access String;
-- A file of variable-length ASCII records.
-- Note: in order to work correctly, the TEXT file type must be declared in
-- the Textio package of library Std. Otherwise, a file of string has a
-- non-ASCII format.
type text is file of String;
type side is (right, left); -- For justifying ouput data within fields.
subtype width is natural; -- For specifying widths of output fields.
-- standard text files
--START-V08
function Justify (Value: String;
Justified : Side := Right;
Field: Width := 0 ) return String;
--END-V08
file input: text is in "STD_INPUT"; --V87
file output: text is out "STD_OUTPUT"; --V87
file input : text open read_mode is "STD_INPUT"; --!V87
file output : text open write_mode is "STD_OUTPUT"; --!V87
-- input routines for standard types
procedure readline (variable f: in text; l: inout line); --V87
procedure readline (file f: text; l: inout line); --!V87
-- For READ procedures:
-- In this implementation, any L is accepted (ie, there is no constraints
-- on direction, or left bound). Therefore, even variable of type LINE
-- not initialized by READLINE are accepted. Strictly speaking, this is
-- not required by LRM, nor prevented. However, other implementations may
-- fail at parsing such Strings.
--
-- Also, in case of error (GOOD is false), this implementation do not
-- modify L (as specified by the LRM) nor VALUE.
--
-- For READ procedures without a GOOD argument, an assertion fails in case
-- of error.
--
-- In case of overflow (ie, if the number is out of the bounds of the type),
-- the procedure will fail with an execution error.
-- FIXME: this should not occur for a bad String.
procedure read (l: inout line; value: out bit; good: out boolean);
procedure read (l: inout line; value: out bit);
procedure read (l: inout line; value: out bit_vector; good: out boolean);
procedure read (l: inout line; value: out bit_vector);
procedure read (l: inout line; value: out boolean; good: out boolean);
procedure read (l: inout line; value: out boolean);
procedure read (l: inout line; value: out character; good: out boolean);
procedure read (l: inout line; value: out character);
procedure read (l: inout line; value: out integer; good: out boolean);
procedure read (l: inout line; value: out integer);
procedure read (l: inout line; value: out real; good: out boolean);
procedure read (l: inout line; value: out real);
procedure read (l: inout line; value: out String; good: out boolean);
procedure read (l: inout line; value: out String);
-- This implementation requires no space after the unit identifier,
-- ie "7.5 nsv" is parsed as 7.5 ns.
-- The unit identifier can be in lower case, upper case or mixed case.
procedure read (l: inout line; value: out time; good: out boolean);
procedure read (l: inout line; value: out time);
--START-V08
procedure Sread (L : inout Line; Value : out String; Strlen : out Natural);
alias STRING_READ is SREAD [LINE, STRING, NATURAL];
alias BREAD is READ [LINE, BIT_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, BIT_VECTOR];
alias BINARY_READ is READ [LINE, BIT_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, BIT_VECTOR];
procedure Oread (L : inout Line; Value : out Bit_Vector; Good : out Boolean);
procedure Oread (L : inout Line; Value : out Bit_Vector);
alias OCTAL_READ is OREAD [LINE, BIT_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, BIT_VECTOR];
procedure Hread (L : inout Line; Value : out Bit_Vector; Good : out Boolean);
procedure Hread (L : inout Line; Value : out Bit_Vector);
alias HEX_READ is HREAD [LINE, BIT_VECTOR, BOOLEAN];
alias HEX_READ is HREAD [LINE, BIT_VECTOR];
--END-V08
-- output routines for standard types
procedure writeline (variable f: out text; l: inout line); --V87
procedure writeline (file f: text; l: inout line); --!V87
--START-V08
procedure Tee (file f : Text; L : inout LINE);
--END-V08
-- This implementation accept any value for all the types.
procedure write
(l: inout line; value: in bit;
justified: in side := right; field: in width := 0);
procedure write
(l: inout line; value: in bit_vector;
justified: in side := right; field: in width := 0);
procedure write
(l: inout line; value: in boolean;
justified: in side := right; field: in width := 0);
procedure write
(l: inout line; value: in character;
justified: in side := right; field: in width := 0);
procedure write
(l: inout line; value: in integer;
justified: in side := right; field: in width := 0);
procedure write
(L: inout line; value: in real;
justified: in side := right; field: in width := 0;
digits: in natural := 0);
procedure write
(l: inout line; value: in String;
justified: in side := right; field: in width := 0);
-- UNIT must be a unit name declared in std.standard. Of course, no rules
-- in the core VHDL language prevent you from using a value that is not a
-- unit (eg: 10 ns or even 5 fs).
-- An assertion error message is generated in this case, and question mark
-- (?) is written at the place of the unit name.
procedure write
(l: inout line; value : in time;
justified: in side := right; field: in width := 0; unit : in TIME := ns);
--START-V08
alias Swrite is write [Line, String, Side, Width];
alias String_Write is Write [Line, String, Side, Width];
alias Bwrite is write [Line, Bit_Vector, Side, Width];
alias Binary_Write is write [Line, Bit_Vector, Side, Width];
procedure Owrite (L : inout line; value : in Bit_Vector;
Justified : in Side := Right; Field : in Width := 0);
alias Octal_Write is Owrite [Line, Bit_Vector, Side, Width];
procedure Hwrite (L : inout line; value : in Bit_Vector;
Justified : in Side := Right; Field : in Width := 0);
alias Hex_Write is Hwrite [Line, Bit_Vector, Side, Width];
--END-V08
end textio;
|
gpl-2.0
|
43a4ad214230819c613b983cde16c84b
| 0.676976 | 3.746781 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_09.vhd
| 4 | 2,465 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_09 is
end entity inline_09;
----------------------------------------------------------------
architecture test of inline_09 is
signal clk, reset, trigger, test0, test1 : bit := '0';
begin
process_3_h : process is
begin
-- code from book:
wait until clk = '1';
-- end of code from book
report "clk rising edge detected";
end process process_3_h;
----------------
process_3_i : process is
begin
-- code from book:
wait on clk until reset = '0';
-- end of code from book
report "synchronous reset detected";
end process process_3_i;
----------------
process_3_j : process is
begin
-- code from book:
wait until trigger = '1' for 1 ms;
-- end of code from book
if trigger'event and trigger = '1' then
report "trigger rising edge detected";
else
report "trigger timeout";
end if;
end process process_3_j;
----------------
-- code from book:
test_gen : process is
begin
test0 <= '0' after 10 ns, '1' after 20 ns, '0' after 30 ns, '1' after 40 ns;
test1 <= '0' after 10 ns, '1' after 30 ns;
wait;
end process test_gen;
-- end of code from book
----------------
stimulus_3_h_i_j : process is
begin
clk <= '1' after 10 ns, '0' after 20 ns,
'1' after 30 ns, '0' after 40 ns,
'1' after 50 ns, '0' after 60 ns,
'1' after 70 ns, '0' after 80 ns;
reset <= '1' after 45 ns, '0' after 75 ns;
trigger <= '1' after 10 ns, '0' after 20 ns,
'1' after 30 ns, '0' after 40 ns;
wait;
end process stimulus_3_h_i_j;
end architecture test;
|
gpl-2.0
|
107420a04f32c37da55a8b895012c60a
| 0.597972 | 3.804012 | false | true | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_divider/Gura/Modular/gura_modular.vhd
| 1 | 5,345 |
---------------------------------------------------------------------------------------------------
-- divider_f2m.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Inverter for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: This is an implementation of the division algorithm. Dirent to the other implemented inverter
-- in this, the division is performed directly.
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity f2m_divider_163 is
generic(
NUM_BITS : positive := 163
);
port(
x : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
y : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
done : out STD_LOGIC;
x_div_y : out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of f2m_divider_163 is
----------------------------------------------------------------------------------------------------
-- m = 163, the irreductible polynomial
constant p : std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001001";
-- control signals
signal CASO: std_logic_vector(1 downto 0);
signal c_4, c_5,c_6,a_greater_b,a_eq_b: std_logic;
signal CA, CB : STD_LOGIC_VECTOR(7 downto 0);
signal U, A, V, B,X2, Y2, temp1, toA, toB, toU, toV: STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
type CurrentState_type is (END_STATE, LOAD1, CYCLE);
signal currentState: CurrentState_type;
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
X2 <= x & '0';
Y2 <= y & '0';
caso <= "01" when (A(0) = '1' and B(0) = '0') or CurrentState = LOAD1 else
"10" when A(0) = '0' else
"11";
c_5 <= '0' when rst = '1' or currentState = LOAD1 else
'1';
c_6 <= '1' when CurrentState = LOAD1 else
'0';
a_greater_b <= '1' when CA > CB else
'0';
a_eq_b <= '1' when A = B else
'0';
--a_eq_b <= '1' when CA = "00000000" else
-- '0';
c_4 <= '0' when CurrentState = Load1 or temp1(0) = '0' else
'1';
celda_reg_A: entity celda_a(behave)
port map( A, B,caso(1), caso(0), toA);
celda_reg_U: entity celda_U(behave)
port map(U, V, caso(1), caso(0), temp1);
celda_reg_mod_P: entity mod_P(behave)
port map(temp1, P, c_4, toU);
celda_reg_B: entity celda_B(behave)
port map(toA,P,Y2,c_5,c_6, toB);
celda_reg_V: entity celda_v(behave)
port map(toU,X2,c_5,c_6,toV);
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
EEAL: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if (rst = '1')then
A <= (others => '0');
U <= (others => '0');
B <= toB;
V <= toV;
CA <= "10100010" ;
CB <= "10100011" ;
x_div_y <= (others => '0');
done <= '0';
currentState <= LOAD1;
else
case currentState is
-----------------------------------------------------------------------------------
when LOAD1 =>
A <= toA;
U <= toU;
B <= toB;
V <= toV;
currentState <= Cycle;
when CYCLE =>
if A_eq_B = '1' then
currentState <= END_STATE;
Done <= '1';
x_div_y <= U(NUM_BITS-1 downto 0);
elsif CASO = "10" then
A <= toA;
CA <= CA-1;
U <= toU;
elsif CASO = "01" then
B <= toB;
CB <= CB -1;
V <= toV;
elsif a_greater_b = '1' then
A <= toA;
CA <= CA-1;
U <= toU;
else
B <= toB;
CB <= CB-1;
V <= toV;
end if;
-----------------------------------------------------------------------------------
when END_STATE => -- Do nothing
currentState <= END_STATE;
done <= '0'; -- para generar el pulso, quitarlo entity caso contrario
-----------------------------------------------------------------------------------
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
b1f9ad6b4b1e6c30b7b3587973c07274
| 0.395884 | 4.043116 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1983.vhd
| 4 | 2,607 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1983.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p02n01i01983ent IS
type color is (red, green, blue);
constant azure : color := blue;
constant first : color := color'low;
END c07s02b02x00p02n01i01983ent;
ARCHITECTURE c07s02b02x00p02n01i01983arch OF c07s02b02x00p02n01i01983ent IS
BEGIN
TESTING: PROCESS
variable A1, A2 : color;
variable A3 : color := blue;
alias AA1 :color is A1;
BEGIN
AA1:= first;
A2 := color'succ(A1);
assert NOT( A2 = green and
green = A2 and
A2 > AA1 and
red >= A1 and
A1 >= red and
A3 <= blue and
blue <= A3 and
A1 < green and
green < A3 and
red < azure )
report "***PASSED TEST: c07s02b02x00p02n01i01983"
severity NOTE;
assert ( A2 = green and
green = A2 and
A2 > AA1 and
red >= A1 and
A1 >= red and
A3 <= blue and
blue <= A3 and
A1 < green and
green < A3 and
red < azure )
report "***FAILED TEST: c07s02b02x00p02n01i01983 - Relational operators truth table test for data type of Enumeration failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p02n01i01983arch;
|
gpl-2.0
|
269c8fd1f4044dc736fc0aa988446cb0
| 0.563867 | 3.879464 | false | true | false | false |
beltagymohamed/FLOATING-POINT-MULTIPLIER-USING-FPGA
|
Multiplier/Project/VHDL/reg.vhd
| 1 | 477 |
library ieee;
use ieee.std_logic_1164.all;
entity reg is
port (clk,en,rst: in std_logic;
a:in std_logic_vector((31) downto 0);
r: out std_logic_vector((31) downto 0)
);
end reg;
architecture arch_reg_1 of reg is
begin
process (clk, rst)
begin
if rst='0' then
r <= (others => '0');
else
if (clk'event and clk='1') then
if en='1' then
r <= a;
end if;
end if;
end if;
end process;
end arch_reg_1;
|
mit
|
9c48012e721433f8bb43953a4aa45f6e
| 0.555556 | 2.908537 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_Multiplication/serialMul/serial_multiplier_163_2.vhd
| 1 | 4,150 |
----------------------------------------------------------------------------------------------------
-- serial_multiplier.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Serial multiplier for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: The input buses need to have valid data when Reset signal is asserted
-- FSM are not used.
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--------------------------------------------------------
entity serial_multiplier_163 is
generic (
NUM_BITS : positive := 163 -- The order of the finite field
);
port(
ax : in std_logic_vector(NUM_BITS-1 downto 0);
bx : in std_logic_vector(NUM_BITS-1 downto 0);
cx : out std_logic_vector(NUM_BITS-1 downto 0); -- cx = ax*bx mod Fx
reset : in std_logic;
clk : in std_logic;
done : out std_logic
);
end serial_multiplier_163;
-----------------------------------------------------------
architecture behave of serial_multiplier_163 is
-----------------------------------------------------------
-- m = 163 x163 + x7 + x6 + x3 + 1
constant Fx: std_logic_vector(NUM_BITS-1 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001001";
-----------------------------------------------------------
signal Op1 : std_logic_vector(NUM_BITS-1 downto 0); -- Multiplexers for ax and cx depending upon b_i and c_m
signal Op2 : std_logic_vector(NUM_BITS-1 downto 0);
signal bx_shift : std_logic_vector(NUM_BITS-1 downto 0); -- B and C shifted one position to the rigth
signal cx_shift : std_logic_vector(NUM_BITS-1 downto 0);
signal bx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal cx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal counter: std_logic_vector(7 downto 0); -- 8-bit counter, controling the number of iterations: m
signal done_int : std_logic;
begin
-----------------------------------------------------------
cx <= cx_int; -- Result of the multiplication
Bx_shift <= bx_int(NUM_BITS-2 downto 0)& '0'; -- Shift Bx and Cx to left one position
Cx_shift <= cx_int(NUM_BITS-2 downto 0)& '0';
-- Multiplexer to determine what value is added to C_x in each iteration
Op1 <= ax when bx_int(NUM_BITS-1) = '1' else -- The selector for these multiplexors are the most significant bits of B_x and C_x
(others => '0');
Op2 <= Fx when cx_int(NUM_BITS-1) = '1' else
(others => '0');
done <= done_int;
------------------------------------------------------------
-- The finite state machine, it takes m cycles to compute
-- the multiplication, a counter is used to keep this count
------------------------------------------------------------
FSM_MUL: process (CLK)
Begin
if CLK'event and CLK = '1' then
if Reset = '1' then
counter <= "10100010"; -- m-1 value, in this case, it is 162, be sure to set the correct value
bx_int <= bx;
cx_int <= (others => '0');
Done_int <= '0';
else
if done_int = '0' then
Cx_int <= cx_shift xor Op1 xor Op2;
counter <= counter - 1;
bx_int <= bx_shift;
if counter = "00000000" then -- The done signal is asserted at the same time that the result is computed.
Done_int <= '1';
end if;
end if;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
ff3ae8c4ffb9edcb6246f3cb53c9a700
| 0.495663 | 4.104847 | false | false | false | false |
mmoraless/ecc_vhdl
|
ecc_add/lut3inadd_131.vhd
| 1 | 7,279 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
---------------------------------------------------------------------------------------------
entity lut_3inadd is
generic(
NUM_BITS: positive := 131
);
port (
I: in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
B: in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
C: in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
D: out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0)
);
end;
---------------------------------------------------------------------------------------------
architecture behave of lut_3inadd is
---------------------------------------------------------------------------
---------------------------------------------------------------------------
constant a : std_logic_vector(NUM_BITS-1 downto 0):= "11110100001000110110000100110100111011010110101011000100001010001000100000110001111111100111111111110001100001001010111000010111000";
begin
D(0) <= I(0) xor B(0) xor C(0) xor a(0);
D(1) <= I(1) xor B(1) xor C(1) xor a(1);
D(2) <= I(2) xor B(2) xor C(2) xor a(2);
D(3) <= I(3) xor B(3) xor C(3) xor a(3);
D(4) <= I(4) xor B(4) xor C(4) xor a(4);
D(5) <= I(5) xor B(5) xor C(5) xor a(5);
D(6) <= I(6) xor B(6) xor C(6) xor a(6);
D(7) <= I(7) xor B(7) xor C(7) xor a(7);
D(8) <= I(8) xor B(8) xor C(8) xor a(8);
D(9) <= I(9) xor B(9) xor C(9) xor a(9);
D(10) <= I(10) xor B(10) xor C(10) xor a(10);
D(11) <= I(11) xor B(11) xor C(11) xor a(11);
D(12) <= I(12) xor B(12) xor C(12) xor a(12);
D(13) <= I(13) xor B(13) xor C(13) xor a(13);
D(14) <= I(14) xor B(14) xor C(14) xor a(14);
D(15) <= I(15) xor B(15) xor C(15) xor a(15);
D(16) <= I(16) xor B(16) xor C(16) xor a(16);
D(17) <= I(17) xor B(17) xor C(17) xor a(17);
D(18) <= I(18) xor B(18) xor C(18) xor a(18);
D(19) <= I(19) xor B(19) xor C(19) xor a(19);
D(20) <= I(20) xor B(20) xor C(20) xor a(20);
D(21) <= I(21) xor B(21) xor C(21) xor a(21);
D(22) <= I(22) xor B(22) xor C(22) xor a(22);
D(23) <= I(23) xor B(23) xor C(23) xor a(23);
D(24) <= I(24) xor B(24) xor C(24) xor a(24);
D(25) <= I(25) xor B(25) xor C(25) xor a(25);
D(26) <= I(26) xor B(26) xor C(26) xor a(26);
D(27) <= I(27) xor B(27) xor C(27) xor a(27);
D(28) <= I(28) xor B(28) xor C(28) xor a(28);
D(29) <= I(29) xor B(29) xor C(29) xor a(29);
D(30) <= I(30) xor B(30) xor C(30) xor a(30);
D(31) <= I(31) xor B(31) xor C(31) xor a(31);
D(32) <= I(32) xor B(32) xor C(32) xor a(32);
D(33) <= I(33) xor B(33) xor C(33) xor a(33);
D(34) <= I(34) xor B(34) xor C(34) xor a(34);
D(35) <= I(35) xor B(35) xor C(35) xor a(35);
D(36) <= I(36) xor B(36) xor C(36) xor a(36);
D(37) <= I(37) xor B(37) xor C(37) xor a(37);
D(38) <= I(38) xor B(38) xor C(38) xor a(38);
D(39) <= I(39) xor B(39) xor C(39) xor a(39);
D(40) <= I(40) xor B(40) xor C(40) xor a(40);
D(41) <= I(41) xor B(41) xor C(41) xor a(41);
D(42) <= I(42) xor B(42) xor C(42) xor a(42);
D(43) <= I(43) xor B(43) xor C(43) xor a(43);
D(44) <= I(44) xor B(44) xor C(44) xor a(44);
D(45) <= I(45) xor B(45) xor C(45) xor a(45);
D(46) <= I(46) xor B(46) xor C(46) xor a(46);
D(47) <= I(47) xor B(47) xor C(47) xor a(47);
D(48) <= I(48) xor B(48) xor C(48) xor a(48);
D(49) <= I(49) xor B(49) xor C(49) xor a(49);
D(50) <= I(50) xor B(50) xor C(50) xor a(50);
D(51) <= I(51) xor B(51) xor C(51) xor a(51);
D(52) <= I(52) xor B(52) xor C(52) xor a(52);
D(53) <= I(53) xor B(53) xor C(53) xor a(53);
D(54) <= I(54) xor B(54) xor C(54) xor a(54);
D(55) <= I(55) xor B(55) xor C(55) xor a(55);
D(56) <= I(56) xor B(56) xor C(56) xor a(56);
D(57) <= I(57) xor B(57) xor C(57) xor a(57);
D(58) <= I(58) xor B(58) xor C(58) xor a(58);
D(59) <= I(59) xor B(59) xor C(59) xor a(59);
D(60) <= I(60) xor B(60) xor C(60) xor a(60);
D(61) <= I(61) xor B(61) xor C(61) xor a(61);
D(62) <= I(62) xor B(62) xor C(62) xor a(62);
D(63) <= I(63) xor B(63) xor C(63) xor a(63);
D(64) <= I(64) xor B(64) xor C(64) xor a(64);
D(65) <= I(65) xor B(65) xor C(65) xor a(65);
D(66) <= I(66) xor B(66) xor C(66) xor a(66);
D(67) <= I(67) xor B(67) xor C(67) xor a(67);
D(68) <= I(68) xor B(68) xor C(68) xor a(68);
D(69) <= I(69) xor B(69) xor C(69) xor a(69);
D(70) <= I(70) xor B(70) xor C(70) xor a(70);
D(71) <= I(71) xor B(71) xor C(71) xor a(71);
D(72) <= I(72) xor B(72) xor C(72) xor a(72);
D(73) <= I(73) xor B(73) xor C(73) xor a(73);
D(74) <= I(74) xor B(74) xor C(74) xor a(74);
D(75) <= I(75) xor B(75) xor C(75) xor a(75);
D(76) <= I(76) xor B(76) xor C(76) xor a(76);
D(77) <= I(77) xor B(77) xor C(77) xor a(77);
D(78) <= I(78) xor B(78) xor C(78) xor a(78);
D(79) <= I(79) xor B(79) xor C(79) xor a(79);
D(80) <= I(80) xor B(80) xor C(80) xor a(80);
D(81) <= I(81) xor B(81) xor C(81) xor a(81);
D(82) <= I(82) xor B(82) xor C(82) xor a(82);
D(83) <= I(83) xor B(83) xor C(83) xor a(83);
D(84) <= I(84) xor B(84) xor C(84) xor a(84);
D(85) <= I(85) xor B(85) xor C(85) xor a(85);
D(86) <= I(86) xor B(86) xor C(86) xor a(86);
D(87) <= I(87) xor B(87) xor C(87) xor a(87);
D(88) <= I(88) xor B(88) xor C(88) xor a(88);
D(89) <= I(89) xor B(89) xor C(89) xor a(89);
D(90) <= I(90) xor B(90) xor C(90) xor a(90);
D(91) <= I(91) xor B(91) xor C(91) xor a(91);
D(92) <= I(92) xor B(92) xor C(92) xor a(92);
D(93) <= I(93) xor B(93) xor C(93) xor a(93);
D(94) <= I(94) xor B(94) xor C(94) xor a(94);
D(95) <= I(95) xor B(95) xor C(95) xor a(95);
D(96) <= I(96) xor B(96) xor C(96) xor a(96);
D(97) <= I(97) xor B(97) xor C(97) xor a(97);
D(98) <= I(98) xor B(98) xor C(98) xor a(98);
D(99) <= I(99) xor B(99) xor C(99) xor a(99);
D(100) <= I(100) xor B(100) xor C(100) xor a(100);
D(101) <= I(101) xor B(101) xor C(101) xor a(101);
D(102) <= I(102) xor B(102) xor C(102) xor a(102);
D(103) <= I(103) xor B(103) xor C(103) xor a(103);
D(104) <= I(104) xor B(104) xor C(104) xor a(104);
D(105) <= I(105) xor B(105) xor C(105) xor a(105);
D(106) <= I(106) xor B(106) xor C(106) xor a(106);
D(107) <= I(107) xor B(107) xor C(107) xor a(107);
D(108) <= I(108) xor B(108) xor C(108) xor a(108);
D(109) <= I(109) xor B(109) xor C(109) xor a(109);
D(110) <= I(110) xor B(110) xor C(110) xor a(110);
D(111) <= I(111) xor B(111) xor C(111) xor a(111);
D(112) <= I(112) xor B(112) xor C(112) xor a(112);
D(113) <= I(113) xor B(113) xor C(113) xor a(113);
D(114) <= I(114) xor B(114) xor C(114) xor a(114);
D(115) <= I(115) xor B(115) xor C(115) xor a(115);
D(116) <= I(116) xor B(116) xor C(116) xor a(116);
D(117) <= I(117) xor B(117) xor C(117) xor a(117);
D(118) <= I(118) xor B(118) xor C(118) xor a(118);
D(119) <= I(119) xor B(119) xor C(119) xor a(119);
D(120) <= I(120) xor B(120) xor C(120) xor a(120);
D(121) <= I(121) xor B(121) xor C(121) xor a(121);
D(122) <= I(122) xor B(122) xor C(122) xor a(122);
D(123) <= I(123) xor B(123) xor C(123) xor a(123);
D(124) <= I(124) xor B(124) xor C(124) xor a(124);
D(125) <= I(125) xor B(125) xor C(125) xor a(125);
D(126) <= I(126) xor B(126) xor C(126) xor a(126);
D(127) <= I(127) xor B(127) xor C(127) xor a(127);
D(128) <= I(128) xor B(128) xor C(128) xor a(128);
D(129) <= I(129) xor B(129) xor C(129) xor a(129);
D(130) <= I(130) xor B(130) xor C(130) xor a(130);
end;
|
gpl-3.0
|
adfd4d4c84c209a949850343e501b3c5
| 0.510647 | 2.006893 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/v_source-1.vhd
| 4 | 1,991 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.math_real.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity v_source is
generic ( DC : voltage := 1.0; -- output peak amplitude
min_freq : real := 10.0; -- minimum frequency for spectral source
max_freq : real := 1.0e4; -- maximum frequency for spectral source
ac_mag : voltage := 1.0; -- AC magnitude
ac_phase : real := 0.0 ); -- AC phase [degree]
port ( terminal pos, neg : electrical );
end entity v_source;
----------------------------------------------------------------
architecture behavior of v_source is
function g (freq : real) return real is
begin
if (freq > min_freq and freq < max_freq) then
return 1.0;
else
return 0.0;
end if;
end function g;
quantity vout across iout through pos to neg;
-- declare quantity in frequency domain for AC analysis
quantity ac_spec : real spectrum ac_mag*g(frequency),
math_2_pi*ac_phase/360.0;
begin
if domain = quiescent_domain or domain = time_domain use
vout == DC;
else
vout == ac_spec; -- used for frequency (AC) analysis
end use;
end architecture behavior;
|
gpl-2.0
|
81fe7974ea2b1feeef007cb2624aa777
| 0.65997 | 4.006036 | false | false | false | false |
jakubcabal/pipemania-fpga-game
|
source/comp/video/vga_sync.vhd
| 1 | 3,859 |
--------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: VGA_SYNC
-- AUTHORS: Vojtěch Jeřábek <[email protected]>
-- Jakub Cabal <[email protected]>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/pipemania-fpga-game
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity VGA_SYNC is
Port (
CLK : in std_logic; -- clock, must be 50 MHz
RST : in std_logic; -- reset
PIXEL_X : out std_logic_vector(9 downto 0); -- cislo pixelu na radku
PIXEL_Y : out std_logic_vector(9 downto 0); -- cislo pixelu ve sloupci
HSYNC : out std_logic; -- synchronizacni pulzy pro VGA vystup
VSYNC : out std_logic
);
end VGA_SYNC;
architecture Behavioral of VGA_SYNC is
signal pixel_tick : std_logic; -- doba vykreslovani pixelu - 25 MHz
signal position_x : unsigned(9 downto 0); -- udava cislo pixelu na radku
signal position_y : unsigned(9 downto 0); -- udava cislo pixelu ve sloupci
begin
----------------------------------------------------------------------------
-- pixel_tick o potrebne frekvenci 25MHz, vyzaduje CLK o frekvenci 50MHZ
pixel_tick_p : process (CLK, RST)
begin
if (RST = '1') then
pixel_tick <= '0';
elsif (rising_edge(CLK)) then
pixel_tick <= not pixel_tick;
end if;
end process;
----------------------------------------------------------------------------
-- pocitani na jakem pixelu na radku se nachazime
position_x_p : process (CLK, RST)
begin
if (RST = '1') then
position_x <= (others => '0');
elsif (rising_edge(CLK)) then
if (pixel_tick = '1') then
if (position_x = 799) then
position_x <= (others => '0');
else
position_x <= position_x + 1;
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- pocitani na jakem pixelu ve sloupci se nachazime
position_y_p : process (CLK, RST)
begin
if (RST = '1') then
position_y <= (others => '0');
elsif (rising_edge(CLK)) then
if (pixel_tick = '1' and position_x = 799) then
if (position_y = 524) then
position_y <= (others => '0');
else
position_y <= position_y + 1;
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- synchronizacni pulzy pro VGA
hsync_reg_p : process (CLK, RST)
begin
if (RST = '1') then
HSYNC <= '0';
elsif (rising_edge(CLK)) then
if (position_x > 655 and position_x < 752) then
HSYNC <= '0';
else
HSYNC <= '1';
end if;
end if;
end process;
vsync_reg_p : process (CLK, RST)
begin
if (RST = '1') then
VSYNC <= '0';
elsif (rising_edge(CLK)) then
if (position_y > 489 and position_y < 492) then
VSYNC <= '0';
else
VSYNC <= '1';
end if;
end if;
end process;
----------------------------------------------------------------------------
-- prirazeni vystupnich signalu
PIXEL_X <= std_logic_vector(position_x);
PIXEL_Y <= std_logic_vector(position_y);
end Behavioral;
|
mit
|
241a0cef4ac6ac5f23be554c246d6bcf
| 0.438537 | 4.274945 | false | false | false | false |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/plasma/uart.vhd
| 2 | 6,948 |
---------------------------------------------------------------------
-- TITLE: UART
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 5/29/02
-- FILENAME: uart.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the UART.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
use work.mlite_pack.all;
entity uart is
generic(log_file : string := "UNUSED");
port(clk : in std_logic;
reset : in std_logic;
enable_read : in std_logic;
enable_write : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
uart_read : in std_logic;
uart_write : out std_logic;
busy_write : out std_logic;
data_avail : out std_logic);
end; --entity uart
architecture logic of uart is
signal delay_write_reg : std_logic_vector(9 downto 0);
signal bits_write_reg : std_logic_vector(3 downto 0);
signal data_write_reg : std_logic_vector(8 downto 0);
signal delay_read_reg : std_logic_vector(9 downto 0);
signal bits_read_reg : std_logic_vector(3 downto 0);
signal data_read_reg : std_logic_vector(7 downto 0);
signal data_save_reg : std_logic_vector(17 downto 0);
signal busy_write_sig : std_logic;
signal read_value_reg : std_logic_vector(7 downto 0);
signal uart_read2 : std_logic;
begin
uart_proc: process(clk, reset, enable_read, enable_write, data_in,
data_write_reg, bits_write_reg, delay_write_reg,
data_read_reg, bits_read_reg, delay_read_reg,
data_save_reg, read_value_reg, uart_read2,
busy_write_sig, uart_read)
constant COUNT_VALUE : std_logic_vector(9 downto 0) :=
-- "0100011110"; --33MHz/2/57600Hz = 0x11e
-- "1101100100"; --50MHz/57600Hz = 0x364
"0110110010"; --25MHz/57600Hz = 0x1b2 -- Plasma IF uses div2
-- "0000000100"; --for debug (shorten read_value_reg)
begin
uart_read2 <= read_value_reg(read_value_reg'length - 1);
if reset = '1' then
data_write_reg <= ZERO(8 downto 1) & '1';
bits_write_reg <= "0000";
delay_write_reg <= ZERO(9 downto 0);
read_value_reg <= ONES(7 downto 0);
data_read_reg <= ZERO(7 downto 0);
bits_read_reg <= "0000";
delay_read_reg <= ZERO(9 downto 0);
data_save_reg <= ZERO(17 downto 0);
elsif rising_edge(clk) then
--Write UART
if bits_write_reg = "0000" then --nothing left to write?
if enable_write = '1' then
delay_write_reg <= ZERO(9 downto 0); --delay before next bit
bits_write_reg <= "1010"; --number of bits to write
data_write_reg <= data_in & '0'; --remember data & start bit
end if;
else
if delay_write_reg /= COUNT_VALUE then
delay_write_reg <= delay_write_reg + 1; --delay before next bit
else
delay_write_reg <= ZERO(9 downto 0); --reset delay
bits_write_reg <= bits_write_reg - 1; --bits left to write
data_write_reg <= '1' & data_write_reg(8 downto 1);
end if;
end if;
--Average uart_read signal
if uart_read = '1' then
if read_value_reg /= ONES(read_value_reg'length - 1 downto 0) then
read_value_reg <= read_value_reg + 1;
end if;
else
if read_value_reg /= ZERO(read_value_reg'length - 1 downto 0) then
read_value_reg <= read_value_reg - 1;
end if;
end if;
--Read UART
if delay_read_reg = ZERO(9 downto 0) then --done delay for read?
if bits_read_reg = "0000" then --nothing left to read?
if uart_read2 = '0' then --wait for start bit
delay_read_reg <= '0' & COUNT_VALUE(9 downto 1); --half period
bits_read_reg <= "1001"; --bits left to read
end if;
else
delay_read_reg <= COUNT_VALUE; --initialize delay
bits_read_reg <= bits_read_reg - 1; --bits left to read
data_read_reg <= uart_read2 & data_read_reg(7 downto 1);
end if;
else
delay_read_reg <= delay_read_reg - 1; --delay
end if;
--Control character buffer
if bits_read_reg = "0000" and delay_read_reg = COUNT_VALUE then
if data_save_reg(8) = '0' or
(enable_read = '1' and data_save_reg(17) = '0') then
--Empty buffer
data_save_reg(8 downto 0) <= '1' & data_read_reg;
else
--Second character in buffer
data_save_reg(17 downto 9) <= '1' & data_read_reg;
if enable_read = '1' then
data_save_reg(8 downto 0) <= data_save_reg(17 downto 9);
end if;
end if;
elsif enable_read = '1' then
data_save_reg(17) <= '0'; --data_available
data_save_reg(8 downto 0) <= data_save_reg(17 downto 9);
end if;
end if; --rising_edge(clk)
uart_write <= data_write_reg(0);
if bits_write_reg /= "0000"
-- Comment out the following line for full UART simulation (much slower)
and log_file = "UNUSED"
then
busy_write_sig <= '1';
else
busy_write_sig <= '0';
end if;
busy_write <= busy_write_sig;
data_avail <= data_save_reg(8);
data_out <= data_save_reg(7 downto 0);
end process; --uart_proc
-- synthesis_off
uart_logger:
if log_file /= "UNUSED" generate
uart_proc: process(clk, enable_write, data_in)
file store_file : text open write_mode is log_file;
variable hex_file_line : line;
variable c : character;
variable index : natural;
variable line_length : natural := 0;
begin
if rising_edge(clk) and busy_write_sig = '0' then
if enable_write = '1' then
index := conv_integer(data_in(6 downto 0));
if index /= 10 then
c := character'val(index);
write(hex_file_line, c);
line_length := line_length + 1;
end if;
if index = 10 or line_length >= 72 then
--The following line may have to be commented out for synthesis
writeline(store_file, hex_file_line);
line_length := 0;
end if;
end if; --uart_sel
end if; --rising_edge(clk)
end process; --uart_proc
end generate; --uart_logger
-- synthesis_on
end; --architecture logic
|
mit
|
22653e5e5fe01bed5944791f68090708
| 0.549799 | 3.555783 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc489.vhd
| 4 | 2,843 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc489.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b02x00p01n01i00489ent IS
type small is
record
bt : bit;
bv : bit_vector (11 downto 0);
r : real range 0.0 to real'high;
bb : boolean;
i : integer range 1 to 20;
end record;
END c03s02b02x00p01n01i00489ent;
ARCHITECTURE c03s02b02x00p01n01i00489arch OF c03s02b02x00p01n01i00489ent IS
BEGIN
TESTING: PROCESS
variable A1 : small;
alias A1_bv : bit_vector (11 downto 0) is A1.bv;
alias A1_bt : bit is A1.bt;
alias A1_i : integer is A1.i;
alias A1_r : real is A1.r;
alias A1_bb : boolean is A1.bb;
BEGIN
assert NOT( ( A1.bv = x"000") and
( A1.bt = '0') and
( A1.bb = false) and
( A1.i = 1) and
( A1.r = 0.0) and
( A1_bv = x"000") and
( A1_bt = '0') and
( A1_bb = false) and
( A1_i = 1) and
( A1_r = 0.0) )
report "***PASSED TEST: c03s02b02x00p01n01i00489"
severity NOTE;
assert ( ( A1.bv = x"000") and
( A1.bt = '0') and
( A1.bb = false) and
( A1.i = 1) and
( A1.r = 0.0) and
( A1_bv = x"000") and
( A1_bt = '0') and
( A1_bb = false) and
( A1_i = 1) and
( A1_r = 0.0) )
report "***FAILED TEST: c03s02b02x00p01n01i00489 - Values of a record object consist of the value of its elements."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b02x00p01n01i00489arch;
|
gpl-2.0
|
d06646b3f474c0486e6815936a8e32fd
| 0.539923 | 3.380499 | false | true | false | false |
peteut/ghdl
|
libraries/ieee2008/math_real-body.vhdl
| 4 | 65,284 |
-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is sold without written
-- permission from the IEEE Standards Department. This source file may be
-- copied for individual use between licensed users. This source file is
-- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR
-- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE
-- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify
-- and hold IEEE harmless from any damages or liability arising out of the
-- use thereof.
--
-- Title : Standard VHDL Mathematical Packages
-- : (MATH_REAL package body)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
-- :
-- Purpose : This package defines a standard for designers to use in
-- : describing VHDL models that make use of common REAL
-- : constants and common REAL elementary mathematical
-- : functions.
-- :
-- Limitation: The values generated by the functions in this package
-- : may vary from platform to platform, and the precision
-- : of results is only guaranteed to be the minimum required
-- : by IEEE Std 1076-2008.
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
package body MATH_REAL is
--
-- Local Constants for Use in the Package Body Only
--
constant MATH_E_P2 : REAL := 7.38905_60989_30650; -- e**2
constant MATH_E_P10 : REAL := 22026.46579_48067_17; -- e**10
constant MATH_EIGHT_PI : REAL := 25.13274_12287_18345_90770_115; --8*pi
constant MAX_ITER: INTEGER := 27; -- Maximum precision factor for cordic
constant MAX_COUNT: INTEGER := 150; -- Maximum count for number of tries
constant BASE_EPS: REAL := 0.00001; -- Factor for convergence criteria
constant KC : REAL := 6.0725293500888142e-01; -- Constant for cordic
--
-- Local Type Declarations for Cordic Operations
--
type REAL_VECTOR is array (NATURAL range <>) of REAL;
type NATURAL_VECTOR is array (NATURAL range <>) of NATURAL;
subtype REAL_VECTOR_N is REAL_VECTOR (0 to MAX_ITER);
subtype REAL_ARR_2 is REAL_VECTOR (0 to 1);
subtype REAL_ARR_3 is REAL_VECTOR (0 to 2);
subtype QUADRANT is INTEGER range 0 to 3;
type CORDIC_MODE_TYPE is (ROTATION, VECTORING);
--
-- Auxiliary Functions for Cordic Algorithms
--
function POWER_OF_2_SERIES (D : in NATURAL_VECTOR; INITIAL_VALUE : in REAL;
NUMBER_OF_VALUES : in NATURAL) return REAL_VECTOR is
-- Description:
-- Returns power of two for a vector of values
-- Notes:
-- None
--
variable V : REAL_VECTOR (0 to NUMBER_OF_VALUES);
variable TEMP : REAL := INITIAL_VALUE;
variable FLAG : BOOLEAN := TRUE;
begin
for I in 0 to NUMBER_OF_VALUES loop
V(I) := TEMP;
for P in D'RANGE loop
if I = D(P) then
FLAG := FALSE;
exit;
end if;
end loop;
if FLAG then
TEMP := TEMP/2.0;
end if;
FLAG := TRUE;
end loop;
return V;
end function POWER_OF_2_SERIES;
constant TWO_AT_MINUS : REAL_VECTOR := POWER_OF_2_SERIES(
NATURAL_VECTOR'(100, 90),1.0,
MAX_ITER);
constant EPSILON : REAL_VECTOR_N := (
7.8539816339744827e-01,
4.6364760900080606e-01,
2.4497866312686413e-01,
1.2435499454676144e-01,
6.2418809995957351e-02,
3.1239833430268277e-02,
1.5623728620476830e-02,
7.8123410601011116e-03,
3.9062301319669717e-03,
1.9531225164788189e-03,
9.7656218955931937e-04,
4.8828121119489829e-04,
2.4414062014936175e-04,
1.2207031189367021e-04,
6.1035156174208768e-05,
3.0517578115526093e-05,
1.5258789061315760e-05,
7.6293945311019699e-06,
3.8146972656064960e-06,
1.9073486328101870e-06,
9.5367431640596080e-07,
4.7683715820308876e-07,
2.3841857910155801e-07,
1.1920928955078067e-07,
5.9604644775390553e-08,
2.9802322387695303e-08,
1.4901161193847654e-08,
7.4505805969238281e-09
);
function CORDIC ( X0 : in REAL;
Y0 : in REAL;
Z0 : in REAL;
N : in NATURAL; -- Precision factor
CORDIC_MODE : in CORDIC_MODE_TYPE -- Rotation (Z -> 0)
-- or vectoring (Y -> 0)
) return REAL_ARR_3 is
-- Description:
-- Compute cordic values
-- Notes:
-- None
variable X : REAL := X0;
variable Y : REAL := Y0;
variable Z : REAL := Z0;
variable X_TEMP : REAL;
begin
if CORDIC_MODE = ROTATION then
for K in 0 to N loop
X_TEMP := X;
if ( Z >= 0.0) then
X := X - Y * TWO_AT_MINUS(K);
Y := Y + X_TEMP * TWO_AT_MINUS(K);
Z := Z - EPSILON(K);
else
X := X + Y * TWO_AT_MINUS(K);
Y := Y - X_TEMP * TWO_AT_MINUS(K);
Z := Z + EPSILON(K);
end if;
end loop;
else
for K in 0 to N loop
X_TEMP := X;
if ( Y < 0.0) then
X := X - Y * TWO_AT_MINUS(K);
Y := Y + X_TEMP * TWO_AT_MINUS(K);
Z := Z - EPSILON(K);
else
X := X + Y * TWO_AT_MINUS(K);
Y := Y - X_TEMP * TWO_AT_MINUS(K);
Z := Z + EPSILON(K);
end if;
end loop;
end if;
return REAL_ARR_3'(X, Y, Z);
end function CORDIC;
--
-- Bodies for Global Mathematical Functions Start Here
--
function SIGN (X: in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
if ( X > 0.0 ) then
return 1.0;
elsif ( X < 0.0 ) then
return -1.0;
else
return 0.0;
end if;
end function SIGN;
function CEIL (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) No conversion to an INTEGER type is expected, so truncate
-- cannot overflow for large arguments
-- b) The domain supported by this function is X <= LARGE
-- c) Returns X if ABS(X) >= LARGE
constant LARGE: REAL := REAL(INTEGER'HIGH);
variable RD: REAL;
begin
if ABS(X) >= LARGE then
return X;
end if;
RD := REAL ( INTEGER(X));
if RD = X then
return X;
end if;
if X > 0.0 then
if RD >= X then
return RD;
else
return RD + 1.0;
end if;
elsif X = 0.0 then
return 0.0;
else
if RD <= X then
return RD + 1.0;
else
return RD;
end if;
end if;
end function CEIL;
function FLOOR (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) No conversion to an INTEGER type is expected, so truncate
-- cannot overflow for large arguments
-- b) The domain supported by this function is ABS(X) <= LARGE
-- c) Returns X if ABS(X) >= LARGE
constant LARGE: REAL := REAL(INTEGER'HIGH);
variable RD: REAL;
begin
if ABS( X ) >= LARGE then
return X;
end if;
RD := REAL ( INTEGER(X));
if RD = X then
return X;
end if;
if X > 0.0 then
if RD <= X then
return RD;
else
return RD - 1.0;
end if;
elsif X = 0.0 then
return 0.0;
else
if RD >= X then
return RD - 1.0;
else
return RD;
end if;
end if;
end function FLOOR;
function ROUND (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 if X = 0.0
-- b) Returns FLOOR(X + 0.5) if X > 0
-- c) Returns CEIL(X - 0.5) if X < 0
begin
if X > 0.0 then
return FLOOR(X + 0.5);
elsif X < 0.0 then
return CEIL( X - 0.5);
else
return 0.0;
end if;
end function ROUND;
function TRUNC (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 if X = 0.0
-- b) Returns FLOOR(X) if X > 0
-- c) Returns CEIL(X) if X < 0
begin
if X > 0.0 then
return FLOOR(X);
elsif X < 0.0 then
return CEIL( X);
else
return 0.0;
end if;
end function TRUNC;
function "MOD" (X, Y: in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error
variable XNEGATIVE : BOOLEAN := X < 0.0;
variable YNEGATIVE : BOOLEAN := Y < 0.0;
variable VALUE : REAL;
begin
-- Check validity of input arguments
if (Y = 0.0) then
assert FALSE
report "MOD(X, 0.0) is undefined"
severity ERROR;
return 0.0;
end if;
-- Compute value
if ( XNEGATIVE ) then
if ( YNEGATIVE ) then
VALUE := X + (FLOOR(ABS(X)/ABS(Y)))*ABS(Y);
else
VALUE := X + (CEIL(ABS(X)/ABS(Y)))*ABS(Y);
end if;
else
if ( YNEGATIVE ) then
VALUE := X - (CEIL(ABS(X)/ABS(Y)))*ABS(Y);
else
VALUE := X - (FLOOR(ABS(X)/ABS(Y)))*ABS(Y);
end if;
end if;
return VALUE;
end function "MOD";
function REALMAX (X, Y : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) REALMAX(X,Y) = X when X = Y
--
begin
if X >= Y then
return X;
else
return Y;
end if;
end function REALMAX;
function REALMIN (X, Y : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) REALMIN(X,Y) = X when X = Y
--
begin
if X <= Y then
return X;
else
return Y;
end if;
end function REALMIN;
procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE;variable X:out REAL)
is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error
--
variable Z, K: INTEGER;
variable TSEED1 : INTEGER := INTEGER'(SEED1);
variable TSEED2 : INTEGER := INTEGER'(SEED2);
begin
-- Check validity of arguments
if SEED1 > 2147483562 then
assert FALSE
report "SEED1 > 2147483562 in UNIFORM"
severity ERROR;
X := 0.0;
return;
end if;
if SEED2 > 2147483398 then
assert FALSE
report "SEED2 > 2147483398 in UNIFORM"
severity ERROR;
X := 0.0;
return;
end if;
-- Compute new seed values and pseudo-random number
K := TSEED1/53668;
TSEED1 := 40014 * (TSEED1 - K * 53668) - K * 12211;
if TSEED1 < 0 then
TSEED1 := TSEED1 + 2147483563;
end if;
K := TSEED2/52774;
TSEED2 := 40692 * (TSEED2 - K * 52774) - K * 3791;
if TSEED2 < 0 then
TSEED2 := TSEED2 + 2147483399;
end if;
Z := TSEED1 - TSEED2;
if Z < 1 then
Z := Z + 2147483562;
end if;
-- Get output values
SEED1 := POSITIVE'(TSEED1);
SEED2 := POSITIVE'(TSEED2);
X := REAL(Z)*4.656613e-10;
end procedure UNIFORM;
function SQRT (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Uses the Newton-Raphson approximation:
-- F(n+1) = 0.5*[F(n) + x/F(n)]
-- b) Returns 0.0 on error
--
constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence factor
variable INIVAL: REAL;
variable OLDVAL : REAL ;
variable NEWVAL : REAL ;
variable COUNT : INTEGER := 1;
begin
-- Check validity of argument
if ( X < 0.0 ) then
assert FALSE
report "X < 0.0 in SQRT(X)"
severity ERROR;
return 0.0;
end if;
-- Get the square root for special cases
if X = 0.0 then
return 0.0;
else
if ( X = 1.0 ) then
return 1.0;
end if;
end if;
-- Get the square root for general cases
INIVAL := EXP(LOG(X)*(0.5)); -- Mathematically correct but imprecise
OLDVAL := INIVAL;
NEWVAL := (X/OLDVAL + OLDVAL)*0.5;
-- Check for relative and absolute error and max count
while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS) OR
(ABS(NEWVAL - OLDVAL) > EPS) ) AND
(COUNT < MAX_COUNT) ) loop
OLDVAL := NEWVAL;
NEWVAL := (X/OLDVAL + OLDVAL)*0.5;
COUNT := COUNT + 1;
end loop;
return NEWVAL;
end function SQRT;
function CBRT (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Uses the Newton-Raphson approximation:
-- F(n+1) = (1/3)*[2*F(n) + x/F(n)**2];
--
constant EPS : REAL := BASE_EPS*BASE_EPS;
variable INIVAL: REAL;
variable XLOCAL : REAL := X;
variable NEGATIVE : BOOLEAN := X < 0.0;
variable OLDVAL : REAL ;
variable NEWVAL : REAL ;
variable COUNT : INTEGER := 1;
begin
-- Compute root for special cases
if X = 0.0 then
return 0.0;
elsif ( X = 1.0 ) then
return 1.0;
else
if X = -1.0 then
return -1.0;
end if;
end if;
-- Compute root for general cases
if NEGATIVE then
XLOCAL := -X;
end if;
INIVAL := EXP(LOG(XLOCAL)/(3.0)); -- Mathematically correct but
-- imprecise
OLDVAL := INIVAL;
NEWVAL := (XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0;
-- Check for relative and absolute errors and max count
while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS ) OR
(ABS(NEWVAL - OLDVAL) > EPS ) ) AND
( COUNT < MAX_COUNT ) ) loop
OLDVAL := NEWVAL;
NEWVAL :=(XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0;
COUNT := COUNT + 1;
end loop;
if NEGATIVE then
NEWVAL := -NEWVAL;
end if;
return NEWVAL;
end function CBRT;
function "**" (X : in INTEGER; Y : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error condition
begin
-- Check validity of argument
if ( ( X < 0 ) and ( Y /= 0.0 ) ) then
assert FALSE
report "X < 0 and Y /= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
if ( ( X = 0 ) and ( Y <= 0.0 ) ) then
assert FALSE
report "X = 0 and Y <= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
-- Get value for special cases
if ( X = 0 and Y > 0.0 ) then
return 0.0;
end if;
if ( X = 1 ) then
return 1.0;
end if;
if ( Y = 0.0 and X /= 0 ) then
return 1.0;
end if;
if ( Y = 1.0) then
return (REAL(X));
end if;
-- Get value for general case
return EXP (Y * LOG (REAL(X)));
end function "**";
function "**" (X : in REAL; Y : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error condition
begin
-- Check validity of argument
if ( ( X < 0.0 ) and ( Y /= 0.0 ) ) then
assert FALSE
report "X < 0.0 and Y /= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
if ( ( X = 0.0 ) and ( Y <= 0.0 ) ) then
assert FALSE
report "X = 0.0 and Y <= 0.0 in X**Y"
severity ERROR;
return 0.0;
end if;
-- Get value for special cases
if ( X = 0.0 and Y > 0.0 ) then
return 0.0;
end if;
if ( X = 1.0 ) then
return 1.0;
end if;
if ( Y = 0.0 and X /= 0.0 ) then
return 1.0;
end if;
if ( Y = 1.0) then
return (X);
end if;
-- Get value for general case
return EXP (Y * LOG (X));
end function "**";
function EXP (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) This function computes the exponential using the following
-- series:
-- exp(x) = 1 + x + x**2/2! + x**3/3! + ... ; |x| < 1.0
-- and reduces argument X to take advantage of exp(x+y) =
-- exp(x)*exp(y)
--
-- b) This implementation limits X to be less than LOG(REAL'HIGH)
-- to avoid overflow. Returns REAL'HIGH when X reaches that
-- limit
--
constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;-- Precision criteria
variable RECIPROCAL: BOOLEAN := X < 0.0;-- Check sign of argument
variable XLOCAL : REAL := ABS(X); -- Use positive value
variable OLDVAL: REAL ;
variable COUNT: INTEGER ;
variable NEWVAL: REAL ;
variable LAST_TERM: REAL ;
variable FACTOR : REAL := 1.0;
begin
-- Compute value for special cases
if X = 0.0 then
return 1.0;
end if;
if XLOCAL = 1.0 then
if RECIPROCAL then
return MATH_1_OVER_E;
else
return MATH_E;
end if;
end if;
if XLOCAL = 2.0 then
if RECIPROCAL then
return 1.0/MATH_E_P2;
else
return MATH_E_P2;
end if;
end if;
if XLOCAL = 10.0 then
if RECIPROCAL then
return 1.0/MATH_E_P10;
else
return MATH_E_P10;
end if;
end if;
if XLOCAL > LOG(REAL'HIGH) then
if RECIPROCAL then
return 0.0;
else
assert FALSE
report "X > LOG(REAL'HIGH) in EXP(X)"
severity NOTE;
return REAL'HIGH;
end if;
end if;
-- Reduce argument to ABS(X) < 1.0
while XLOCAL > 10.0 loop
XLOCAL := XLOCAL - 10.0;
FACTOR := FACTOR*MATH_E_P10;
end loop;
while XLOCAL > 1.0 loop
XLOCAL := XLOCAL - 1.0;
FACTOR := FACTOR*MATH_E;
end loop;
-- Compute value for case 0 < XLOCAL < 1
OLDVAL := 1.0;
LAST_TERM := XLOCAL;
NEWVAL:= OLDVAL + LAST_TERM;
COUNT := 2;
-- Check for relative and absolute errors and max count
while ( ( (ABS((NEWVAL - OLDVAL)/NEWVAL) > EPS) OR
(ABS(NEWVAL - OLDVAL) > EPS) ) AND
(COUNT < MAX_COUNT ) ) loop
OLDVAL := NEWVAL;
LAST_TERM := LAST_TERM*(XLOCAL / (REAL(COUNT)));
NEWVAL := OLDVAL + LAST_TERM;
COUNT := COUNT + 1;
end loop;
-- Compute final value using exp(x+y) = exp(x)*exp(y)
NEWVAL := NEWVAL*FACTOR;
if RECIPROCAL then
NEWVAL := 1.0/NEWVAL;
end if;
return NEWVAL;
end function EXP;
--
-- Auxiliary Functions to Compute LOG
--
function ILOGB(X: in REAL) return INTEGER IS
-- Description:
-- Returns n such that -1 <= ABS(X)/2^n < 2
-- Notes:
-- None
variable N: INTEGER := 0;
variable Y: REAL := ABS(X);
begin
if(Y = 1.0 or Y = 0.0) then
return 0;
end if;
if( Y > 1.0) then
while Y >= 2.0 loop
Y := Y/2.0;
N := N+1;
end loop;
return N;
end if;
-- O < Y < 1
while Y < 1.0 loop
Y := Y*2.0;
N := N -1;
end loop;
return N;
end function ILOGB;
function LDEXP(X: in REAL; N: in INTEGER) RETURN REAL IS
-- Description:
-- Returns X*2^n
-- Notes:
-- None
begin
return X*(2.0 ** N);
end function LDEXP;
function LOG (X : in REAL ) return REAL IS
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
--
-- Notes:
-- a) Returns REAL'LOW on error
--
-- Copyright (c) 1992 Regents of the University of California.
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- 3. All advertising materials mentioning features or use of this
-- software must display the following acknowledgement:
-- This product includes software developed by the University of
-- California, Berkeley and its contributors.
-- 4. Neither the name of the University nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS''
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR
-- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-- OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-- DAMAGE.
--
-- NOTE: This VHDL version was generated using the C version of the
-- original function by the IEEE VHDL Mathematical Package
-- Working Group (CS/JT)
constant N: INTEGER := 128;
-- Table of log(Fj) = logF_head[j] + logF_tail[j], for Fj = 1+j/128.
-- Used for generation of extend precision logarithms.
-- The constant 35184372088832 is 2^45, so the divide is exact.
-- It ensures correct reading of logF_head, even for inaccurate
-- decimal-to-binary conversion routines. (Everybody gets the
-- right answer for INTEGERs less than 2^53.)
-- Values for LOG(F) were generated using error < 10^-57 absolute
-- with the bc -l package.
type REAL_VECTOR is array (NATURAL range <>) of REAL;
constant A1:REAL := 0.08333333333333178827;
constant A2:REAL := 0.01250000000377174923;
constant A3:REAL := 0.002232139987919447809;
constant A4:REAL := 0.0004348877777076145742;
constant LOGF_HEAD: REAL_VECTOR(0 TO N) := (
0.0,
0.007782140442060381246,
0.015504186535963526694,
0.023167059281547608406,
0.030771658666765233647,
0.038318864302141264488,
0.045809536031242714670,
0.053244514518837604555,
0.060624621816486978786,
0.067950661908525944454,
0.075223421237524235039,
0.082443669210988446138,
0.089612158689760690322,
0.096729626458454731618,
0.103796793681567578460,
0.110814366340264314203,
0.117783035656430001836,
0.124703478501032805070,
0.131576357788617315236,
0.138402322859292326029,
0.145182009844575077295,
0.151916042025732167530,
0.158605030176659056451,
0.165249572895390883786,
0.171850256926518341060,
0.178407657472689606947,
0.184922338493834104156,
0.191394852999565046047,
0.197825743329758552135,
0.204215541428766300668,
0.210564769107350002741,
0.216873938300523150246,
0.223143551314024080056,
0.229374101064877322642,
0.235566071312860003672,
0.241719936886966024758,
0.247836163904594286577,
0.253915209980732470285,
0.259957524436686071567,
0.265963548496984003577,
0.271933715484010463114,
0.277868451003087102435,
0.283768173130738432519,
0.289633292582948342896,
0.295464212893421063199,
0.301261330578199704177,
0.307025035294827830512,
0.312755710004239517729,
0.318453731118097493890,
0.324119468654316733591,
0.329753286372579168528,
0.335355541920762334484,
0.340926586970454081892,
0.346466767346100823488,
0.351976423156884266063,
0.357455888922231679316,
0.362905493689140712376,
0.368325561158599157352,
0.373716409793814818840,
0.379078352934811846353,
0.384411698910298582632,
0.389716751140440464951,
0.394993808240542421117,
0.400243164127459749579,
0.405465108107819105498,
0.410659924985338875558,
0.415827895143593195825,
0.420969294644237379543,
0.426084395310681429691,
0.431173464818130014464,
0.436236766774527495726,
0.441274560805140936281,
0.446287102628048160113,
0.451274644139630254358,
0.456237433481874177232,
0.461175715122408291790,
0.466089729924533457960,
0.470979715219073113985,
0.475845904869856894947,
0.480688529345570714212,
0.485507815781602403149,
0.490303988045525329653,
0.495077266798034543171,
0.499827869556611403822,
0.504556010751912253908,
0.509261901790523552335,
0.513945751101346104405,
0.518607764208354637958,
0.523248143765158602036,
0.527867089620485785417,
0.532464798869114019908,
0.537041465897345915436,
0.541597282432121573947,
0.546132437597407260909,
0.550647117952394182793,
0.555141507540611200965,
0.559615787935399566777,
0.564070138285387656651,
0.568504735352689749561,
0.572919753562018740922,
0.577315365035246941260,
0.581691739635061821900,
0.586049045003164792433,
0.590387446602107957005,
0.594707107746216934174,
0.599008189645246602594,
0.603290851438941899687,
0.607555250224322662688,
0.611801541106615331955,
0.616029877215623855590,
0.620240409751204424537,
0.624433288012369303032,
0.628608659422752680256,
0.632766669570628437213,
0.636907462236194987781,
0.641031179420679109171,
0.645137961373620782978,
0.649227946625615004450,
0.653301272011958644725,
0.657358072709030238911,
0.661398482245203922502,
0.665422632544505177065,
0.669430653942981734871,
0.673422675212350441142,
0.677398823590920073911,
0.681359224807238206267,
0.685304003098281100392,
0.689233281238557538017,
0.693147180560117703862);
constant LOGF_TAIL: REAL_VECTOR(0 TO N) := (
0.0,
-0.00000000000000543229938420049,
0.00000000000000172745674997061,
-0.00000000000001323017818229233,
-0.00000000000001154527628289872,
-0.00000000000000466529469958300,
0.00000000000005148849572685810,
-0.00000000000002532168943117445,
-0.00000000000005213620639136504,
-0.00000000000001819506003016881,
0.00000000000006329065958724544,
0.00000000000008614512936087814,
-0.00000000000007355770219435028,
0.00000000000009638067658552277,
0.00000000000007598636597194141,
0.00000000000002579999128306990,
-0.00000000000004654729747598444,
-0.00000000000007556920687451336,
0.00000000000010195735223708472,
-0.00000000000017319034406422306,
-0.00000000000007718001336828098,
0.00000000000010980754099855238,
-0.00000000000002047235780046195,
-0.00000000000008372091099235912,
0.00000000000014088127937111135,
0.00000000000012869017157588257,
0.00000000000017788850778198106,
0.00000000000006440856150696891,
0.00000000000016132822667240822,
-0.00000000000007540916511956188,
-0.00000000000000036507188831790,
0.00000000000009120937249914984,
0.00000000000018567570959796010,
-0.00000000000003149265065191483,
-0.00000000000009309459495196889,
0.00000000000017914338601329117,
-0.00000000000001302979717330866,
0.00000000000023097385217586939,
0.00000000000023999540484211737,
0.00000000000015393776174455408,
-0.00000000000036870428315837678,
0.00000000000036920375082080089,
-0.00000000000009383417223663699,
0.00000000000009433398189512690,
0.00000000000041481318704258568,
-0.00000000000003792316480209314,
0.00000000000008403156304792424,
-0.00000000000034262934348285429,
0.00000000000043712191957429145,
-0.00000000000010475750058776541,
-0.00000000000011118671389559323,
0.00000000000037549577257259853,
0.00000000000013912841212197565,
0.00000000000010775743037572640,
0.00000000000029391859187648000,
-0.00000000000042790509060060774,
0.00000000000022774076114039555,
0.00000000000010849569622967912,
-0.00000000000023073801945705758,
0.00000000000015761203773969435,
0.00000000000003345710269544082,
-0.00000000000041525158063436123,
0.00000000000032655698896907146,
-0.00000000000044704265010452446,
0.00000000000034527647952039772,
-0.00000000000007048962392109746,
0.00000000000011776978751369214,
-0.00000000000010774341461609578,
0.00000000000021863343293215910,
0.00000000000024132639491333131,
0.00000000000039057462209830700,
-0.00000000000026570679203560751,
0.00000000000037135141919592021,
-0.00000000000017166921336082431,
-0.00000000000028658285157914353,
-0.00000000000023812542263446809,
0.00000000000006576659768580062,
-0.00000000000028210143846181267,
0.00000000000010701931762114254,
0.00000000000018119346366441110,
0.00000000000009840465278232627,
-0.00000000000033149150282752542,
-0.00000000000018302857356041668,
-0.00000000000016207400156744949,
0.00000000000048303314949553201,
-0.00000000000071560553172382115,
0.00000000000088821239518571855,
-0.00000000000030900580513238244,
-0.00000000000061076551972851496,
0.00000000000035659969663347830,
0.00000000000035782396591276383,
-0.00000000000046226087001544578,
0.00000000000062279762917225156,
0.00000000000072838947272065741,
0.00000000000026809646615211673,
-0.00000000000010960825046059278,
0.00000000000002311949383800537,
-0.00000000000058469058005299247,
-0.00000000000002103748251144494,
-0.00000000000023323182945587408,
-0.00000000000042333694288141916,
-0.00000000000043933937969737844,
0.00000000000041341647073835565,
0.00000000000006841763641591466,
0.00000000000047585534004430641,
0.00000000000083679678674757695,
-0.00000000000085763734646658640,
0.00000000000021913281229340092,
-0.00000000000062242842536431148,
-0.00000000000010983594325438430,
0.00000000000065310431377633651,
-0.00000000000047580199021710769,
-0.00000000000037854251265457040,
0.00000000000040939233218678664,
0.00000000000087424383914858291,
0.00000000000025218188456842882,
-0.00000000000003608131360422557,
-0.00000000000050518555924280902,
0.00000000000078699403323355317,
-0.00000000000067020876961949060,
0.00000000000016108575753932458,
0.00000000000058527188436251509,
-0.00000000000035246757297904791,
-0.00000000000018372084495629058,
0.00000000000088606689813494916,
0.00000000000066486268071468700,
0.00000000000063831615170646519,
0.00000000000025144230728376072,
-0.00000000000017239444525614834);
variable M, J:INTEGER;
variable F1, F2, G, Q, U, U2, V: REAL;
variable ZERO: REAL := 0.0;--Made variable so no constant folding occurs
variable ONE: REAL := 1.0; --Made variable so no constant folding occurs
-- double logb(), ldexp();
variable U1:REAL;
begin
-- Check validity of argument
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG(X)"
severity ERROR;
return(REAL'LOW);
end if;
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
if ( X = MATH_E ) then
return 1.0;
end if;
-- Argument reduction: 1 <= g < 2; x/2^m = g;
-- y = F*(1 + f/F) for |f| <= 2^-8
M := ILOGB(X);
G := LDEXP(X, -M);
J := INTEGER(REAL(N)*(G-1.0)); -- C code adds 0.5 for rounding
F1 := (1.0/REAL(N)) * REAL(J) + 1.0; --F1*128 is an INTEGER in [128,512]
F2 := G - F1;
-- Approximate expansion for log(1+f2/F1) ~= u + q
G := 1.0/(2.0*F1+F2);
U := 2.0*F2*G;
V := U*U;
Q := U*V*(A1 + V*(A2 + V*(A3 + V*A4)));
-- Case 1: u1 = u rounded to 2^-43 absolute. Since u < 2^-8,
-- u1 has at most 35 bits, and F1*u1 is exact, as F1 has < 8 bits.
-- It also adds exactly to |m*log2_hi + log_F_head[j] | < 750.
--
if ( J /= 0 or M /= 0) then
U1 := U + 513.0;
U1 := U1 - 513.0;
-- Case 2: |1-x| < 1/256. The m- and j- dependent terms are zero
-- u1 = u to 24 bits.
--
else
U1 := U;
--TRUNC(U1); --In c this is u1 = (double) (float) (u1)
end if;
U2 := (2.0*(F2 - F1*U1) - U1*F2) * G;
-- u1 + u2 = 2f/(2F+f) to extra precision.
-- log(x) = log(2^m*F1*(1+f2/F1)) =
-- (m*log2_hi+LOGF_HEAD(j)+u1) + (m*log2_lo+LOGF_TAIL(j)+q);
-- (exact) + (tiny)
U1 := U1 + REAL(M)*LOGF_HEAD(N) + LOGF_HEAD(J); -- Exact
U2 := (U2 + LOGF_TAIL(J)) + Q; -- Tiny
U2 := U2 + LOGF_TAIL(N)*REAL(M);
return (U1 + U2);
end function LOG;
function LOG2 (X: in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns REAL'LOW on error
begin
-- Check validity of arguments
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG2(X)"
severity ERROR;
return(REAL'LOW);
end if;
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
if ( X = 2.0 ) then
return 1.0;
end if;
-- Compute value for general case
return ( MATH_LOG2_OF_E*LOG(X) );
end function LOG2;
function LOG10 (X: in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns REAL'LOW on error
begin
-- Check validity of arguments
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG10(X)"
severity ERROR;
return(REAL'LOW);
end if;
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
if ( X = 10.0 ) then
return 1.0;
end if;
-- Compute value for general case
return ( MATH_LOG10_OF_E*LOG(X) );
end function LOG10;
function LOG (X: in REAL; BASE: in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns REAL'LOW on error
begin
-- Check validity of arguments
if ( X <= 0.0 ) then
assert FALSE
report "X <= 0.0 in LOG(X, BASE)"
severity ERROR;
return(REAL'LOW);
end if;
if ( BASE <= 0.0 or BASE = 1.0 ) then
assert FALSE
report "BASE <= 0.0 or BASE = 1.0 in LOG(X, BASE)"
severity ERROR;
return(REAL'LOW);
end if;
-- Compute value for special cases
if ( X = 1.0 ) then
return 0.0;
end if;
if ( X = BASE ) then
return 1.0;
end if;
-- Compute value for general case
return ( LOG(X)/LOG(BASE));
end function LOG;
function SIN (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) SIN(-X) = -SIN(X)
-- b) SIN(X) = X if ABS(X) < EPS
-- c) SIN(X) = X - X**3/3! if EPS < ABS(X) < BASE_EPS
-- d) SIN(MATH_PI_OVER_2 - X) = COS(X)
-- e) COS(X) = 1.0 - 0.5*X**2 if ABS(X) < EPS
-- f) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if
-- EPS< ABS(X) <BASE_EPS
constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence criteria
variable N : INTEGER;
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X) ;
variable VALUE: REAL;
variable TEMP : REAL;
begin
-- Make XLOCAL < MATH_2_PI
if XLOCAL > MATH_2_PI then
TEMP := FLOOR(XLOCAL/MATH_2_PI);
XLOCAL := XLOCAL - TEMP*MATH_2_PI;
end if;
if XLOCAL < 0.0 then
-- adjust for rounding error
XLOCAL := 0.0;
end if;
-- Compute value for special cases
if XLOCAL = 0.0 or XLOCAL = MATH_2_PI or XLOCAL = MATH_PI then
return 0.0;
end if;
if XLOCAL = MATH_PI_OVER_2 then
if NEGATIVE then
return -1.0;
else
return 1.0;
end if;
end if;
if XLOCAL = MATH_3_PI_OVER_2 then
if NEGATIVE then
return 1.0;
else
return -1.0;
end if;
end if;
if XLOCAL < EPS then
if NEGATIVE then
return -XLOCAL;
else
return XLOCAL;
end if;
else
if XLOCAL < BASE_EPS then
TEMP := XLOCAL - (XLOCAL*XLOCAL*XLOCAL)/6.0;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
end if;
end if;
TEMP := MATH_PI - XLOCAL;
if ABS(TEMP) < EPS then
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
else
if ABS(TEMP) < BASE_EPS then
TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
end if;
end if;
TEMP := MATH_2_PI - XLOCAL;
if ABS(TEMP) < EPS then
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
else
if ABS(TEMP) < BASE_EPS then
TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0;
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
end if;
end if;
TEMP := ABS(MATH_PI_OVER_2 - XLOCAL);
if TEMP < EPS then
TEMP := 1.0 - TEMP*TEMP*0.5;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
else
if TEMP < BASE_EPS then
TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0;
if NEGATIVE then
return -TEMP;
else
return TEMP;
end if;
end if;
end if;
TEMP := ABS(MATH_3_PI_OVER_2 - XLOCAL);
if TEMP < EPS then
TEMP := 1.0 - TEMP*TEMP*0.5;
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
else
if TEMP < BASE_EPS then
TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0;
if NEGATIVE then
return TEMP;
else
return -TEMP;
end if;
end if;
end if;
-- Compute value for general cases
if ((XLOCAL < MATH_PI_OVER_2 ) and (XLOCAL > 0.0)) then
VALUE:= CORDIC( KC, 0.0, x, 27, ROTATION)(1);
end if;
N := INTEGER ( FLOOR(XLOCAL/MATH_PI_OVER_2));
case QUADRANT( N mod 4) is
when 0 =>
VALUE := CORDIC( KC, 0.0, XLOCAL, 27, ROTATION)(1);
when 1 =>
VALUE := CORDIC( KC, 0.0, XLOCAL - MATH_PI_OVER_2, 27,
ROTATION)(0);
when 2 =>
VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_PI, 27, ROTATION)(1);
when 3 =>
VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_3_PI_OVER_2, 27,
ROTATION)(0);
end case;
if NEGATIVE then
return -VALUE;
else
return VALUE;
end if;
end function SIN;
function COS (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) COS(-X) = COS(X)
-- b) COS(X) = SIN(MATH_PI_OVER_2 - X)
-- c) COS(MATH_PI + X) = -COS(X)
-- d) COS(X) = 1.0 - X*X/2.0 if ABS(X) < EPS
-- e) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if
-- EPS< ABS(X) <BASE_EPS
--
constant EPS : REAL := BASE_EPS*BASE_EPS;
variable XLOCAL : REAL := ABS(X);
variable VALUE: REAL;
variable TEMP : REAL;
begin
-- Make XLOCAL < MATH_2_PI
if XLOCAL > MATH_2_PI then
TEMP := FLOOR(XLOCAL/MATH_2_PI);
XLOCAL := XLOCAL - TEMP*MATH_2_PI;
end if;
if XLOCAL < 0.0 then
-- adjust for rounding error
XLOCAL := 0.0;
end if;
-- Compute value for special cases
if XLOCAL = 0.0 or XLOCAL = MATH_2_PI then
return 1.0;
end if;
if XLOCAL = MATH_PI then
return -1.0;
end if;
if XLOCAL = MATH_PI_OVER_2 or XLOCAL = MATH_3_PI_OVER_2 then
return 0.0;
end if;
TEMP := ABS(XLOCAL);
if ( TEMP < EPS) then
return (1.0 - 0.5*TEMP*TEMP);
else
if (TEMP < BASE_EPS) then
return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0);
end if;
end if;
TEMP := ABS(XLOCAL -MATH_2_PI);
if ( TEMP < EPS) then
return (1.0 - 0.5*TEMP*TEMP);
else
if (TEMP < BASE_EPS) then
return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0);
end if;
end if;
TEMP := ABS (XLOCAL - MATH_PI);
if TEMP < EPS then
return (-1.0 + 0.5*TEMP*TEMP);
else
if (TEMP < BASE_EPS) then
return (-1.0 +0.5*TEMP*TEMP - TEMP*TEMP*TEMP*TEMP/24.0);
end if;
end if;
-- Compute value for general cases
return SIN(MATH_PI_OVER_2 - XLOCAL);
end function COS;
function TAN (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) TAN(0.0) = 0.0
-- b) TAN(-X) = -TAN(X)
-- c) Returns REAL'LOW on error if X < 0.0
-- d) Returns REAL'HIGH on error if X > 0.0
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X) ;
variable VALUE: REAL;
variable TEMP : REAL;
begin
-- Make 0.0 <= XLOCAL <= MATH_2_PI
if XLOCAL > MATH_2_PI then
TEMP := FLOOR(XLOCAL/MATH_2_PI);
XLOCAL := XLOCAL - TEMP*MATH_2_PI;
end if;
if XLOCAL < 0.0 then
-- adjust for rounding error
XLOCAL := 0.0;
end if;
-- Check validity of argument
if XLOCAL = MATH_PI_OVER_2 then
assert FALSE
report "X is a multiple of MATH_PI_OVER_2 in TAN(X)"
severity ERROR;
if NEGATIVE then
return(REAL'LOW);
else
return(REAL'HIGH);
end if;
end if;
if XLOCAL = MATH_3_PI_OVER_2 then
assert FALSE
report "X is a multiple of MATH_3_PI_OVER_2 in TAN(X)"
severity ERROR;
if NEGATIVE then
return(REAL'HIGH);
else
return(REAL'LOW);
end if;
end if;
-- Compute value for special cases
if XLOCAL = 0.0 or XLOCAL = MATH_PI then
return 0.0;
end if;
-- Compute value for general cases
VALUE := SIN(XLOCAL)/COS(XLOCAL);
if NEGATIVE then
return -VALUE;
else
return VALUE;
end if;
end function TAN;
function ARCSIN (X : in REAL ) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARCSIN(-X) = -ARCSIN(X)
-- b) Returns X on error
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable VALUE : REAL;
begin
-- Check validity of arguments
if XLOCAL > 1.0 then
assert FALSE
report "ABS(X) > 1.0 in ARCSIN(X)"
severity ERROR;
return X;
end if;
-- Compute value for special cases
if XLOCAL = 0.0 then
return 0.0;
elsif XLOCAL = 1.0 then
if NEGATIVE then
return -MATH_PI_OVER_2;
else
return MATH_PI_OVER_2;
end if;
end if;
-- Compute value for general cases
if XLOCAL < 0.9 then
VALUE := ARCTAN(XLOCAL/(SQRT(1.0 - XLOCAL*XLOCAL)));
else
VALUE := MATH_PI_OVER_2 - ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL);
end if;
if NEGATIVE then
VALUE := -VALUE;
end if;
return VALUE;
end function ARCSIN;
function ARCCOS (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARCCOS(-X) = MATH_PI - ARCCOS(X)
-- b) Returns X on error
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable VALUE : REAL;
begin
-- Check validity of argument
if XLOCAL > 1.0 then
assert FALSE
report "ABS(X) > 1.0 in ARCCOS(X)"
severity ERROR;
return X;
end if;
-- Compute value for special cases
if X = 1.0 then
return 0.0;
elsif X = 0.0 then
return MATH_PI_OVER_2;
elsif X = -1.0 then
return MATH_PI;
end if;
-- Compute value for general cases
if XLOCAL > 0.9 then
VALUE := ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL);
else
VALUE := MATH_PI_OVER_2 - ARCTAN(XLOCAL/SQRT(1.0 - XLOCAL*XLOCAL));
end if;
if NEGATIVE then
VALUE := MATH_PI - VALUE;
end if;
return VALUE;
end function ARCCOS;
function ARCTAN (Y : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARCTAN(-Y) = -ARCTAN(Y)
-- b) ARCTAN(Y) = -ARCTAN(1.0/Y) + MATH_PI_OVER_2 for |Y| > 1.0
-- c) ARCTAN(Y) = Y for |Y| < EPS
constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;
variable NEGATIVE : BOOLEAN := Y < 0.0;
variable RECIPROCAL : BOOLEAN;
variable YLOCAL : REAL := ABS(Y);
variable VALUE : REAL;
begin
-- Make argument |Y| <=1.0
if YLOCAL > 1.0 then
YLOCAL := 1.0/YLOCAL;
RECIPROCAL := TRUE;
else
RECIPROCAL := FALSE;
end if;
-- Compute value for special cases
if YLOCAL = 0.0 then
if RECIPROCAL then
if NEGATIVE then
return (-MATH_PI_OVER_2);
else
return (MATH_PI_OVER_2);
end if;
else
return 0.0;
end if;
end if;
if YLOCAL < EPS then
if NEGATIVE then
if RECIPROCAL then
return (-MATH_PI_OVER_2 + YLOCAL);
else
return -YLOCAL;
end if;
else
if RECIPROCAL then
return (MATH_PI_OVER_2 - YLOCAL);
else
return YLOCAL;
end if;
end if;
end if;
-- Compute value for general cases
VALUE := CORDIC( 1.0, YLOCAL, 0.0, 27, VECTORING )(2);
if RECIPROCAL then
VALUE := MATH_PI_OVER_2 - VALUE;
end if;
if NEGATIVE then
VALUE := -VALUE;
end if;
return VALUE;
end function ARCTAN;
function ARCTAN (Y : in REAL; X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns 0.0 on error
variable YLOCAL : REAL;
variable VALUE : REAL;
begin
-- Check validity of arguments
if (Y = 0.0 and X = 0.0 ) then
assert FALSE report
"ARCTAN(0.0, 0.0) is undetermined"
severity ERROR;
return 0.0;
end if;
-- Compute value for special cases
if Y = 0.0 then
if X > 0.0 then
return 0.0;
else
return MATH_PI;
end if;
end if;
if X = 0.0 then
if Y > 0.0 then
return MATH_PI_OVER_2;
else
return -MATH_PI_OVER_2;
end if;
end if;
-- Compute value for general cases
YLOCAL := ABS(Y/X);
VALUE := ARCTAN(YLOCAL);
if X < 0.0 then
VALUE := MATH_PI - VALUE;
end if;
if Y < 0.0 then
VALUE := -VALUE;
end if;
return VALUE;
end function ARCTAN;
function SINH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (EXP(X) - EXP(-X))/2.0
-- b) SINH(-X) = SINH(X)
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable TEMP : REAL;
variable VALUE : REAL;
begin
-- Compute value for special cases
if XLOCAL = 0.0 then
return 0.0;
end if;
-- Compute value for general cases
TEMP := EXP(XLOCAL);
VALUE := (TEMP - 1.0/TEMP)*0.5;
if NEGATIVE then
VALUE := -VALUE;
end if;
return VALUE;
end function SINH;
function COSH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (EXP(X) + EXP(-X))/2.0
-- b) COSH(-X) = COSH(X)
variable XLOCAL : REAL := ABS(X);
variable TEMP : REAL;
variable VALUE : REAL;
begin
-- Compute value for special cases
if XLOCAL = 0.0 then
return 1.0;
end if;
-- Compute value for general cases
TEMP := EXP(XLOCAL);
VALUE := (TEMP + 1.0/TEMP)*0.5;
return VALUE;
end function COSH;
function TANH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (EXP(X) - EXP(-X))/(EXP(X) + EXP(-X))
-- b) TANH(-X) = -TANH(X)
variable NEGATIVE : BOOLEAN := X < 0.0;
variable XLOCAL : REAL := ABS(X);
variable TEMP : REAL;
variable VALUE : REAL;
begin
-- Compute value for special cases
if XLOCAL = 0.0 then
return 0.0;
end if;
-- Compute value for general cases
TEMP := EXP(XLOCAL);
VALUE := (TEMP - 1.0/TEMP)/(TEMP + 1.0/TEMP);
if NEGATIVE then
return -VALUE;
else
return VALUE;
end if;
end function TANH;
function ARCSINH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns LOG( X + SQRT( X*X + 1.0))
begin
-- Compute value for special cases
if X = 0.0 then
return 0.0;
end if;
-- Compute value for general cases
return ( LOG( X + SQRT( X*X + 1.0)) );
end function ARCSINH;
function ARCCOSH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns LOG( X + SQRT( X*X - 1.0)); X >= 1.0
-- b) Returns X on error
begin
-- Check validity of arguments
if X < 1.0 then
assert FALSE
report "X < 1.0 in ARCCOSH(X)"
severity ERROR;
return X;
end if;
-- Compute value for special cases
if X = 1.0 then
return 0.0;
end if;
-- Compute value for general cases
return ( LOG( X + SQRT( X*X - 1.0)));
end function ARCCOSH;
function ARCTANH (X : in REAL) return REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (LOG( (1.0 + X)/(1.0 - X)))/2.0 ; | X | < 1.0
-- b) Returns X on error
begin
-- Check validity of arguments
if ABS(X) >= 1.0 then
assert FALSE
report "ABS(X) >= 1.0 in ARCTANH(X)"
severity ERROR;
return X;
end if;
-- Compute value for special cases
if X = 0.0 then
return 0.0;
end if;
-- Compute value for general cases
return( 0.5*LOG( (1.0+X)/(1.0-X) ) );
end function ARCTANH;
end package body MATH_REAL;
|
gpl-2.0
|
7a48afa453a089f54b49801b4bb11a17
| 0.46817 | 4.333776 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/bv_images_body.vhd
| 4 | 4,536 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: bv_images_body.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
--------------------------------------------------------------------------
--
-- bv_images package body.
--
-- Functions that return the string image of values.
-- Each image is a correctly formed literal according to the
-- rules of VHDL-93.
--
--------------------------------------------------------------------------
package body bv_images is
-- Image of bit vector as binary bit string literal
-- (in the format B"...")
-- Length of result is bv'length + 3
function image (bv : in bit_vector) return string is
alias bv_norm : bit_vector(1 to bv'length) is bv;
variable result : string(1 to bv'length + 3);
begin
result(1) := 'B';
result(2) := '"';
for index in bv_norm'range loop
if bv_norm(index) = '0' then
result(index + 2) := '0';
else
result(index + 2) := '1';
end if;
end loop;
result(bv'length + 3) := '"';
return result;
end image;
----------------------------------------------------------------
-- Image of bit vector as octal bit string literal
-- (in the format O"...")
-- Length of result is (bv'length+2)/3 + 3
function image_octal (bv : in bit_vector) return string is
constant nr_digits : natural := (bv'length + 2) / 3;
variable result : string(1 to nr_digits + 3);
variable bits : bit_vector(0 to 3*nr_digits - 1) := (others => '0');
variable three_bits : bit_vector(0 to 2);
variable digit : character;
begin
result(1) := 'O';
result(2) := '"';
bits(bits'right - bv'length + 1 to bits'right) := bv;
for index in 0 to nr_digits - 1 loop
three_bits := bits(3*index to 3*index + 2);
case three_bits is
when b"000" =>
digit := '0';
when b"001" =>
digit := '1';
when b"010" =>
digit := '2';
when b"011" =>
digit := '3';
when b"100" =>
digit := '4';
when b"101" =>
digit := '5';
when b"110" =>
digit := '6';
when b"111" =>
digit := '7';
end case;
result(index + 3) := digit;
end loop;
result(nr_digits + 3) := '"';
return result;
end image_octal;
----------------------------------------------------------------
-- Image of bit vector as hex bit string literal
-- (in the format X"...")
-- Length of result is (bv'length+3)/4 + 3
function image_hex (bv : in bit_vector) return string is
constant nr_digits : natural := (bv'length + 3) / 4;
variable result : string(1 to nr_digits + 3);
variable bits : bit_vector(0 to 4*nr_digits - 1) := (others => '0');
variable four_bits : bit_vector(0 to 3);
variable digit : character;
begin
result(1) := 'X';
result(2) := '"';
bits(bits'right - bv'length + 1 to bits'right) := bv;
for index in 0 to nr_digits - 1 loop
four_bits := bits(4*index to 4*index + 3);
case four_bits is
when b"0000" =>
digit := '0';
when b"0001" =>
digit := '1';
when b"0010" =>
digit := '2';
when b"0011" =>
digit := '3';
when b"0100" =>
digit := '4';
when b"0101" =>
digit := '5';
when b"0110" =>
digit := '6';
when b"0111" =>
digit := '7';
when b"1000" =>
digit := '8';
when b"1001" =>
digit := '9';
when b"1010" =>
digit := 'A';
when b"1011" =>
digit := 'B';
when b"1100" =>
digit := 'C';
when b"1101" =>
digit := 'D';
when b"1110" =>
digit := 'E';
when b"1111" =>
digit := 'F';
end case;
result(index + 3) := digit;
end loop;
result(nr_digits + 3) := '"';
return result;
end image_hex;
end bv_images;
|
gpl-2.0
|
9b027adfba0fb7f1f4fee0a70fd3b99b
| 0.531966 | 3.491917 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc751.vhd
| 4 | 23,127 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc751.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x01p05n02i00751ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15;
C1 : boolean := true;
C2 : bit := '1';
C3 : character := 's';
C4 : severity_level := note;
C5 : integer := 3;
C6 : real := 3.0;
C7 : time := 3 ns;
C8 : natural := 1;
C9 : positive := 1;
C10 : string := "shishir";
C11 : bit_vector := B"0011"
);
END c01s01b01x01p05n02i00751ent;
ARCHITECTURE c01s01b01x01p05n02i00751arch OF c01s01b01x01p05n02i00751ent IS
subtype hi_to_low_range is integer range zero to seven;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
subtype boolean_vector_st is boolean_vector(zero to fifteen);
subtype severity_level_vector_st is severity_level_vector(zero to fifteen);
subtype integer_vector_st is integer_vector(zero to fifteen);
subtype real_vector_st is real_vector(zero to fifteen);
subtype time_vector_st is time_vector(zero to fifteen);
subtype natural_vector_st is natural_vector(zero to fifteen);
subtype positive_vector_st is positive_vector(zero to fifteen);
type boolean_cons_vector is array (fifteen downto zero) of boolean;
type severity_level_cons_vector is array (fifteen downto zero) of severity_level;
type integer_cons_vector is array (fifteen downto zero) of integer;
type real_cons_vector is array (fifteen downto zero) of real;
type time_cons_vector is array (fifteen downto zero) of time;
type natural_cons_vector is array (fifteen downto zero) of natural;
type positive_cons_vector is array (fifteen downto zero) of positive;
type boolean_cons_vectorofvector is array (zero to fifteen) of boolean_cons_vector;
type severity_level_cons_vectorofvector is array (zero to fifteen) of severity_level_cons_vector;
type integer_cons_vectorofvector is array (zero to fifteen) of integer_cons_vector
;
type real_cons_vectorofvector is array (zero to fifteen) of real_cons_vector;
type time_cons_vectorofvector is array (zero to fifteen) of time_cons_vector;
type natural_cons_vectorofvector is array (zero to fifteen) of natural_cons_vector;
type positive_cons_vectorofvector is array (zero to fifteen) of positive_cons_vector;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
j:string(one to seven);
k:bit_vector(zero to three);
end record;
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type record_cons_arrayofarray is record
a:boolean_cons_vectorofvector;
b:severity_level_cons_vectorofvector;
c:integer_cons_vectorofvector;
d:real_cons_vectorofvector;
e:time_cons_vectorofvector;
f:natural_cons_vectorofvector;
g:positive_cons_vectorofvector;
end record;
type record_array_new is record
a:boolean_vector(zero to fifteen);
b:severity_level_vector(zero to fifteen);
c:integer_vector(zero to fifteen);
d:real_vector(zero to fifteen);
e:time_vector(zero to fifteen);
f:natural_vector(zero to fifteen);
g:positive_vector(zero to fifteen);
end record;
type record_of_records is record
a: record_std_package;
c: record_cons_array;
g: record_cons_arrayofarray;
i: record_array_st;
j: record_array_new;
end record;
subtype boolean_vector_range is boolean_vector(hi_to_low_range);
subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
subtype integer_vector_range is integer_vector(hi_to_low_range);
subtype real_vector_range is real_vector(hi_to_low_range);
subtype time_vector_range is time_vector(hi_to_low_range);
subtype natural_vector_range is natural_vector(hi_to_low_range);
subtype positive_vector_range is positive_vector(hi_to_low_range);
type array_rec_std is array (integer range <>) of record_std_package;
type array_rec_cons is array (integer range <>) of record_cons_array;
type array_rec_rec is array (integer range <>) of record_of_records;
subtype array_rec_std_st is array_rec_std (hi_to_low_range);
subtype array_rec_cons_st is array_rec_cons (hi_to_low_range);
subtype array_rec_rec_st is array_rec_rec (hi_to_low_range);
type record_of_arr_of_record is record
a: array_rec_std(zero to seven);
b: array_rec_cons(zero to seven);
c: array_rec_rec(zero to seven);
end record;
type current is range -2147483647 to +2147483647
units
nA;
uA = 1000 nA;
mA = 1000 uA;
A = 1000 mA;
end units;
type current_vector is array (natural range <>) of current;
subtype current_vector_range is current_vector(hi_to_low_range);
type resistance is range -2147483647 to +2147483647
units
uOhm;
mOhm = 1000 uOhm;
Ohm = 1000 mOhm;
KOhm = 1000 Ohm;
end units;
type resistance_vector is array (natural range <>) of resistance;
subtype resistance_vector_range is resistance_vector(hi_to_low_range);
type byte is array(zero to seven) of bit;
subtype word is bit_vector(zero to fifteen); --constrained array
constant size :integer := seven;
type primary_memory is array(zero to size) of word; --array of an array
type primary_memory_module is --record with field
record --as an array
enable:bit;
memory_number:primary_memory;
end record;
type whole_memory is array(0 to size) of primary_memory_module; --array of a complex record
subtype delay is integer range one to 10;
constant C12 : boolean_vector := (C1,false);
constant C13 : severity_level_vector := (C4,error);
constant C14 : integer_vector := (one,two,three,four);
constant C15 : real_vector := (1.0,2.0,C6,4.0);
constant C16 : time_vector := (1 ns, 2 ns,C7, 4 ns);
constant C17 : natural_vector := (one,2,3,4);
constant C18 : positive_vector := (one,2,3,4);
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
constant C27 : severity_level_cons_vectorofvector := (others => (others => C4));
constant C28 : integer_cons_vectorofvector := (others => (others => C5));
constant C29 : real_cons_vectorofvector := (others => (others => C6));
constant C30 : time_cons_vectorofvector := (others => (others => C7));
constant C31 : natural_cons_vectorofvector := (others => (others => C8));
constant C32 : positive_cons_vectorofvector := (others => (others => C9));
constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st:= (others => C4);
constant C72 : integer_vector_st:=(others => C5);
constant C73 : real_vector_st:=(others => C6);
constant C74 : time_vector_st:=(others => C7);
constant C75 : natural_vector_st:=(others => C8);
constant C76 : positive_vector_st:=(others => C9);
constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54a : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54b: record_array_new:= (C70,C71,C72,C73,C74,C75,C76);
constant C55 : record_of_records := (C50,C51,C53,C77,C54b);
constant C60 : byte := (others => '0');
constant C61 : word := (others =>'0' );
constant C64 : primary_memory := (others => C61);
constant C65 : primary_memory_module := ('1',C64);
constant C66 : whole_memory := (others => C65);
constant C67 : current := 1 A;
constant C68 : resistance := 1 Ohm;
constant C69 : delay := 2;
constant C78: boolean_vector_range := (others => C1);
constant C79: severity_level_vector_range := (others => C4) ;
constant C80: integer_vector_range :=(others => C5) ;
constant C81: real_vector_range :=(others => C6);
constant C82: time_vector_range :=(others => C7);
constant C83: natural_vector_range :=(others => C8);
constant C84: positive_vector_range :=(others => C9);
constant C85: array_rec_std(0 to 7) :=(others => C50) ;
constant C86: array_rec_cons (0 to 7) :=(others => C51);
constant C88: array_rec_rec(0 to 7) :=(others => C55);
constant C102: record_of_arr_of_record:= (C85,C86,C88);
BEGIN
TESTING: PROCESS
variable V1 : boolean_vector(zero to fifteen) ;
variable V2 : severity_level_vector(zero to fifteen);
variable V3 : integer_vector(zero to fifteen) ;
variable V4 : real_vector(zero to fifteen) ;
variable V5 : time_vector (zero to fifteen);
variable V6 : natural_vector(zero to fifteen);
variable V7 : positive_vector(zero to fifteen);
variable V8 : boolean_cons_vector;
variable V9 : severity_level_cons_vector ;
variable V10 : integer_cons_vector;
variable V11 : real_cons_vector;
variable V12 : time_cons_vector ;
variable V13 : natural_cons_vector ;
variable V14 : positive_cons_vector ;
variable V15 : boolean_cons_vectorofvector ;
variable V16 : severity_level_cons_vectorofvector;
variable V17 : integer_cons_vectorofvector;
variable V18 : real_cons_vectorofvector;
variable V19 : time_cons_vectorofvector;
variable V20 : natural_cons_vectorofvector;
variable V21 : positive_cons_vectorofvector;
variable V22 : record_std_package;
variable V23 : record_cons_array ;
variable V24 : record_cons_arrayofarray ;
variable V25 : boolean_vector_st ;
variable V26 : severity_level_vector_st ;
variable V27 : integer_vector_st ;
variable V28 : real_vector_st ;
variable V29 : time_vector_st ;
variable V30 : natural_vector_st ;
variable V31 : positive_vector_st ;
variable V32 : record_array_st ;
variable V33 : record_array_st ;
variable V34 : record_array_new ;
variable V35 : record_of_records ;
variable V36 : byte ;
variable V37 : word ;
variable V41 : boolean_vector_range ;
variable V42 : severity_level_vector_range ;
variable V43 : integer_vector_range ;
variable V44 : real_vector_range ;
variable V45 : time_vector_range ;
variable V46 : natural_vector_range ;
variable V47 : positive_vector_range ;
variable V48 : array_rec_std(zero to seven) ;
variable V49 : array_rec_cons(zero to seven) ;
variable V50 : array_rec_rec(zero to seven) ;
variable V51 : record_of_arr_of_record ;
BEGIN
V1 := (zero to fifteen => C1);
V2 := (zero to fifteen => C4);
V3 := (zero to fifteen => C5);
V4 := (zero to fifteen => C6);
V5 := (zero to fifteen => C7);
V6 := (zero to fifteen => C8);
V7 := (zero to fifteen => C9);
V8 := C19;
V9 := C20;
V10 := C21;
V11 := C22;
V12 := C23;
V13 := C24;
V14 := C25;
V15 := C26;
V16 := C27;
V17 := C28;
V18 := C29;
V19 := C30;
V20 := C31;
V21 := C32;
V22 := C50;
V23 := C51;
V24 := C53;
V25 := C70;
V26 := C71;
V27 := C72;
V28 := C73;
V29 := C74;
V30 := C75;
V31 := C76;
V32 := C54a;
V33 := C54a;
V34 := C54b;
V35 := C55;
V36 := C60;
V37 := C61;
V41 := C78;
V42 := C79;
V43 := C80;
V44 := C81;
V45 := C82;
V46 := C83;
V47 := C84;
V48 := C85;
V49 := C86;
V50 := C88;
V51 := C102;
assert (V1(0) = C1) report " error in initializing S1" severity error;
assert (V2(0) = C4) report " error in initializing S2" severity error;
assert (V3(0) = C5) report " error in initializing S3" severity error;
assert (V4(0) = C6) report " error in initializing S4" severity error;
assert (V5(0) = C7) report " error in initializing S5" severity error;
assert (V6(0) = C8) report " error in initializing S6" severity error;
assert (V7(0) = C9) report " error in initializing S7" severity error;
assert V8 = C19 report " error in initializing S8" severity error;
assert V9 = C20 report " error in initializing S9" severity error;
assert V10 = C21 report " error in initializing S10" severity error;
assert V11 = C22 report " error in initializing S11" severity error;
assert V12 = C23 report " error in initializing S12" severity error;
assert V13 = C24 report " error in initializing S13" severity error;
assert V14 = C25 report " error in initializing S14" severity error;
assert V15 = C26 report " error in initializing S15" severity error;
assert V16 = C27 report " error in initializing S16" severity error;
assert V17 = C28 report " error in initializing S17" severity error;
assert V18 = C29 report " error in initializing S18" severity error;
assert V19 = C30 report " error in initializing S19" severity error;
assert V20 = C31 report " error in initializing S20" severity error;
assert V21 = C32 report " error in initializing S21" severity error;
assert V22 = C50 report " error in initializing S22" severity error;
assert V23 = C51 report " error in initializing S23" severity error;
assert V24 = C53 report " error in initializing S24" severity error;
assert V25 = C70 report " error in initializing S25" severity error;
assert V26 = C71 report " error in initializing S26" severity error;
assert V27 = C72 report " error in initializing S27" severity error;
assert V28 = C73 report " error in initializing S28" severity error;
assert V29 = C74 report " error in initializing S29" severity error;
assert V30 = C75 report " error in initializing S30" severity error;
assert V31 = C76 report " error in initializing S31" severity error;
assert V32 = C54a report " error in initializing S32" severity error;
assert V33 = C54a report " error in initializing S33" severity error;
assert V34= C54b report " error in initializing S34" severity error;
assert V35 = C55 report " error in initializing S35" severity error;
assert V36 = C60 report " error in initializing S36" severity error;
assert V37 = C61 report " error in initializing S37" severity error;
assert V41= C78 report " error in initializing S41" severity error;
assert V42= C79 report " error in initializing S42" severity error;
assert V43= C80 report " error in initializing S43" severity error;
assert V44= C81 report " error in initializing S44" severity error;
assert V45= C82 report " error in initializing S45" severity error;
assert V46= C83 report " error in initializing S46" severity error;
assert V47= C84 report " error in initializing S47" severity error;
assert V48= C85 report " error in initializing S48" severity error;
assert V49= C86 report " error in initializing S49" severity error;
assert V50= C88 report " error in initializing S50" severity error;
assert V51= C102 report " error in initializing S51" severity error;
assert NOT( (V1(0) = C1) and
(V2(0) = C4) and
(V3(0) = C5) and
(V4(0) = C6) and
(V5(0) = C7) and
(V6(0) = C8) and
(V7(0) = C9) and
V8 = C19 and
V9 = C20 and
V10 = C21 and
V11 = C22 and
V12 = C23 and
V13 = C24 and
V14 = C25 and
V15 = C26 and
V16 = C27 and
V17 = C28 and
V18 = C29 and
V19 = C30 and
V20 = C31 and
V21 = C32 and
V22 = C50 and
V23 = C51 and
V24 = C53 and
V25 = C70 and
V26 = C71 and
V27 = C72 and
V28 = C73 and
V29 = C74 and
V30 = C75 and
V31 = C76 and
V32 = C54a and
V33 = C54a and
V34= C54b and
V35 = C55 and
V36 = C60 and
V37 = C61 and
V41= C78 and
V42= C79 and
V43= C80 and
V44= C81 and
V45= C82 and
V46= C83 and
V47= C84 and
V48= C85 and
V49= C86 and
V50= C88 and
V51= C102 )
report "***PASSED TEST: c01s01b01x01p05n02i00751"
severity NOTE;
assert ( (V1(0) = C1) and
(V2(0) = C4) and
(V3(0) = C5) and
(V4(0) = C6) and
(V5(0) = C7) and
(V6(0) = C8) and
(V7(0) = C9) and
V8 = C19 and
V9 = C20 and
V10 = C21 and
V11 = C22 and
V12 = C23 and
V13 = C24 and
V14 = C25 and
V15 = C26 and
V16 = C27 and
V17 = C28 and
V18 = C29 and
V19 = C30 and
V20 = C31 and
V21 = C32 and
V22 = C50 and
V23 = C51 and
V24 = C53 and
V25 = C70 and
V26 = C71 and
V27 = C72 and
V28 = C73 and
V29 = C74 and
V30 = C75 and
V31 = C76 and
V32 = C54a and
V33 = C54a and
V34= C54b and
V35 = C55 and
V36 = C60 and
V37 = C61 and
V41= C78 and
V42= C79 and
V43= C80 and
V44= C81 and
V45= C82 and
V46= C83 and
V47= C84 and
V48= C85 and
V49= C86 and
V50= C88 and
V51= C102 )
report "***FAILED TEST: c01s01b01x01p05n02i00751 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00751arch;
|
gpl-2.0
|
e81fe8ab505ea8a74f910a3c6db7c1b8
| 0.548839 | 3.774604 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_divider/Guerric/Modular/celda_u.vhd
| 1 | 1,472 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity celda_u is
generic(
NUM_BITS : positive := 163
);
port(
V_div_2 : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
U_div_2 : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
c_0 : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
U : out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of celda_u is
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
Celda_u_process: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if (rst = '1')then
U <= (others => '0');
else
if c_0 = '1' then
U <= V_div_2 xor U_div_2;
else
U <= U_div_2;
end if;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
994a30a40e1d70a65f7b5936f1f294a6
| 0.328125 | 4.407186 | false | false | false | false |
peteut/ghdl
|
libraries/ieee/std_logic_1164_body.vhdl
| 4 | 34,617 |
-- --------------------------------------------------------------------
--
-- Title : std_logic_1164 multi-value logic system
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE model standards group (par 1164)
-- Purpose : This packages defines a standard for designers
-- : to use in describing the interconnection data types
-- : used in vhdl modeling.
-- :
-- Limitation: The logic system defined in this package may
-- : be insufficient for modeling switched transistors,
-- : since such a requirement is out of the scope of this
-- : effort. Furthermore, mathematics, primitives,
-- : timing standards, etc. are considered orthogonal
-- : issues as it relates to this package and are therefore
-- : beyond the scope of this effort.
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the types, subtypes and declarations of
-- : std_logic_1164. The std_logic_1164 package body shall be
-- : considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement
-- : the package body in the most efficient manner available
-- : to them.
-- :
-- --------------------------------------------------------------------
-- modification history :
-- --------------------------------------------------------------------
-- version | mod. date:|
-- v4.200 | 01/02/91 |
-- --------------------------------------------------------------------
PACKAGE BODY std_logic_1164 IS
-------------------------------------------------------------------
-- local types
-------------------------------------------------------------------
TYPE stdlogic_1d IS ARRAY (std_ulogic) OF std_ulogic;
TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |
( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - |
);
FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic IS
VARIABLE result : std_ulogic := 'Z'; -- weakest state default
BEGIN
-- the test for a single driver is essential otherwise the
-- loop would return 'X' for a single driver of '-' and that
-- would conflict with the value of a single driver unresolved
-- signal.
IF (s'LENGTH = 1) THEN RETURN s(s'LOW);
ELSE
FOR i IN s'RANGE LOOP
result := resolution_table(result, s(i));
END LOOP;
END IF;
RETURN result;
END resolved;
-------------------------------------------------------------------
-- tables for logical operations
-------------------------------------------------------------------
-- truth table for "and" function
CONSTANT and_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ) -- | - |
);
-- truth table for "or" function
CONSTANT or_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
( 'U', 'U', 'U', '1', 'U', 'U', 'U', '1', 'U' ), -- | U |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | 1 |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | Z |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | H |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ) -- | - |
);
-- truth table for "xor" function
CONSTANT xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - |
);
-- truth table for "not" function
CONSTANT not_table: stdlogic_1d :=
-- -------------------------------------------------
-- | U X 0 1 Z W L H - |
-- -------------------------------------------------
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' );
-------------------------------------------------------------------
-- overloaded logical operators ( with optimizing hints )
-------------------------------------------------------------------
FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (and_table(l, r));
END "and";
FUNCTION "nand" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (not_table ( and_table(l, r)));
END "nand";
FUNCTION "or" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (or_table(l, r));
END "or";
FUNCTION "nor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (not_table ( or_table( l, r )));
END "nor";
FUNCTION "xor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (xor_table(l, r));
END "xor";
--START-!V87
FUNCTION "xnor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN not_table(xor_table(l, r));
END "xnor";
--END-!V87
FUNCTION "not" ( l : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (not_table(l));
END "not";
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
FUNCTION "and" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'and' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := and_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "and";
---------------------------------------------------------------------
FUNCTION "and" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'and' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := and_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "and";
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
FUNCTION "nand" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'nand' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(and_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "nand";
---------------------------------------------------------------------
FUNCTION "nand" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'nand' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(and_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "nand";
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
FUNCTION "or" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'or' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := or_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "or";
---------------------------------------------------------------------
FUNCTION "or" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'or' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := or_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "or";
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
FUNCTION "nor" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'nor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(or_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "nor";
---------------------------------------------------------------------
FUNCTION "nor" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'nor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(or_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "nor";
---------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
FUNCTION "xor" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'xor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := xor_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "xor";
---------------------------------------------------------------------
FUNCTION "xor" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'xor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := xor_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "xor";
-- -------------------------------------------------------------------
-- -- xnor
-- -------------------------------------------------------------------
-- -----------------------------------------------------------------------
-- Note : The declaration and implementation of the "xnor" function is
-- specifically commented until at which time the VHDL language has been
-- officially adopted as containing such a function. At such a point,
-- the following comments may be removed along with this notice without
-- further "official" ballotting of this std_logic_1164 package. It is
-- the intent of this effort to provide such a function once it becomes
-- available in the VHDL standard.
-- -----------------------------------------------------------------------
--START-!V87
FUNCTION "xnor" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'xnor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(xor_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "xnor";
---------------------------------------------------------------------
FUNCTION "xnor" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'xnor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(xor_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "xnor";
--END-!V87
-------------------------------------------------------------------
-- not
-------------------------------------------------------------------
FUNCTION "not" ( l : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH ) := (OTHERS => 'X');
BEGIN
FOR i IN result'RANGE LOOP
result(i) := not_table( lv(i) );
END LOOP;
RETURN result;
END;
---------------------------------------------------------------------
FUNCTION "not" ( l : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH ) := (OTHERS => 'X');
BEGIN
FOR i IN result'RANGE LOOP
result(i) := not_table( lv(i) );
END LOOP;
RETURN result;
END;
-------------------------------------------------------------------
-- conversion tables
-------------------------------------------------------------------
TYPE logic_x01_table IS ARRAY (std_ulogic'LOW TO std_ulogic'HIGH) OF X01;
TYPE logic_x01z_table IS ARRAY (std_ulogic'LOW TO std_ulogic'HIGH) OF X01Z;
TYPE logic_ux01_table IS ARRAY (std_ulogic'LOW TO std_ulogic'HIGH) OF UX01;
----------------------------------------------------------
-- table name : cvt_to_x01
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : x01 -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_x01 (input_signal) = '1' ) then ...
--
----------------------------------------------------------
CONSTANT cvt_to_x01 : logic_x01_table := (
'X', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'X', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
----------------------------------------------------------
-- table name : cvt_to_x01z
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : x01z -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_x01z (input_signal) = '1' ) then ...
--
----------------------------------------------------------
CONSTANT cvt_to_x01z : logic_x01z_table := (
'X', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'Z', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
----------------------------------------------------------
-- table name : cvt_to_ux01
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : ux01 -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_ux01 (input_signal) = '1' ) then ...
--
----------------------------------------------------------
CONSTANT cvt_to_ux01 : logic_ux01_table := (
'U', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'X', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
-------------------------------------------------------------------
-- conversion functions
-------------------------------------------------------------------
FUNCTION To_bit ( s : std_ulogic; xmap : BIT := '0') RETURN BIT IS
BEGIN
CASE s IS
WHEN '0' | 'L' => RETURN ('0');
WHEN '1' | 'H' => RETURN ('1');
WHEN OTHERS => RETURN xmap;
END CASE;
END;
--------------------------------------------------------------------
FUNCTION To_bitvector ( s : std_logic_vector ; xmap : BIT := '0') RETURN BIT_VECTOR IS
ALIAS sv : std_logic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
VARIABLE result : BIT_VECTOR ( s'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
CASE sv(i) IS
WHEN '0' | 'L' => result(i) := '0';
WHEN '1' | 'H' => result(i) := '1';
WHEN OTHERS => result(i) := xmap;
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_bitvector ( s : std_ulogic_vector; xmap : BIT := '0') RETURN BIT_VECTOR IS
ALIAS sv : std_ulogic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
VARIABLE result : BIT_VECTOR ( s'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
CASE sv(i) IS
WHEN '0' | 'L' => result(i) := '0';
WHEN '1' | 'H' => result(i) := '1';
WHEN OTHERS => result(i) := xmap;
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_StdULogic ( b : BIT ) RETURN std_ulogic IS
BEGIN
CASE b IS
WHEN '0' => RETURN '0';
WHEN '1' => RETURN '1';
END CASE;
END;
--------------------------------------------------------------------
FUNCTION To_StdLogicVector ( b : BIT_VECTOR ) RETURN std_logic_vector IS
ALIAS bv : BIT_VECTOR ( b'LENGTH-1 DOWNTO 0 ) IS b;
VARIABLE result : std_logic_vector ( b'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_StdLogicVector ( s : std_ulogic_vector ) RETURN std_logic_vector IS
ALIAS sv : std_ulogic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
VARIABLE result : std_logic_vector ( s'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := sv(i);
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_StdULogicVector ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS
ALIAS bv : BIT_VECTOR ( b'LENGTH-1 DOWNTO 0 ) IS b;
VARIABLE result : std_ulogic_vector ( b'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_StdULogicVector ( s : std_logic_vector ) RETURN std_ulogic_vector IS
ALIAS sv : std_logic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
VARIABLE result : std_ulogic_vector ( s'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := sv(i);
END LOOP;
RETURN result;
END;
-------------------------------------------------------------------
-- strength strippers and type convertors
-------------------------------------------------------------------
-- to_x01
-------------------------------------------------------------------
FUNCTION To_X01 ( s : std_logic_vector ) RETURN std_logic_vector IS
ALIAS sv : std_logic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_logic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_x01 (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS sv : std_ulogic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_ulogic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_x01 (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( s : std_ulogic ) RETURN X01 IS
BEGIN
RETURN (cvt_to_x01(s));
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_logic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_logic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_ulogic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( b : BIT ) RETURN X01 IS
BEGIN
CASE b IS
WHEN '0' => RETURN('0');
WHEN '1' => RETURN('1');
END CASE;
END;
--------------------------------------------------------------------
-- to_x01z
-------------------------------------------------------------------
FUNCTION To_X01Z ( s : std_logic_vector ) RETURN std_logic_vector IS
ALIAS sv : std_logic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_logic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_x01z (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( s : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS sv : std_ulogic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_ulogic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_x01z (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( s : std_ulogic ) RETURN X01Z IS
BEGIN
RETURN (cvt_to_x01z(s));
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_logic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_logic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_ulogic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( b : BIT ) RETURN X01Z IS
BEGIN
CASE b IS
WHEN '0' => RETURN('0');
WHEN '1' => RETURN('1');
END CASE;
END;
--------------------------------------------------------------------
-- to_ux01
-------------------------------------------------------------------
FUNCTION To_UX01 ( s : std_logic_vector ) RETURN std_logic_vector IS
ALIAS sv : std_logic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_logic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_ux01 (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS sv : std_ulogic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_ulogic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_ux01 (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( s : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (cvt_to_ux01(s));
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_logic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_logic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_ulogic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( b : BIT ) RETURN UX01 IS
BEGIN
CASE b IS
WHEN '0' => RETURN('0');
WHEN '1' => RETURN('1');
END CASE;
END;
-------------------------------------------------------------------
-- edge detection
-------------------------------------------------------------------
FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN IS
BEGIN
RETURN (s'EVENT AND (To_X01(s) = '1') AND
(To_X01(s'LAST_VALUE) = '0'));
END;
FUNCTION falling_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN IS
BEGIN
RETURN (s'EVENT AND (To_X01(s) = '0') AND
(To_X01(s'LAST_VALUE) = '1'));
END;
-------------------------------------------------------------------
-- object contains an unknown
-------------------------------------------------------------------
FUNCTION Is_X ( s : std_ulogic_vector ) RETURN BOOLEAN IS
BEGIN
FOR i IN s'RANGE LOOP
CASE s(i) IS
WHEN 'U' | 'X' | 'Z' | 'W' | '-' => RETURN TRUE;
WHEN OTHERS => NULL;
END CASE;
END LOOP;
RETURN FALSE;
END;
--------------------------------------------------------------------
FUNCTION Is_X ( s : std_logic_vector ) RETURN BOOLEAN IS
BEGIN
FOR i IN s'RANGE LOOP
CASE s(i) IS
WHEN 'U' | 'X' | 'Z' | 'W' | '-' => RETURN TRUE;
WHEN OTHERS => NULL;
END CASE;
END LOOP;
RETURN FALSE;
END;
--------------------------------------------------------------------
FUNCTION Is_X ( s : std_ulogic ) RETURN BOOLEAN IS
BEGIN
CASE s IS
WHEN 'U' | 'X' | 'Z' | 'W' | '-' => RETURN TRUE;
WHEN OTHERS => NULL;
END CASE;
RETURN FALSE;
END;
END std_logic_1164;
|
gpl-2.0
|
4fd5705770e18ab21f3d5afdaa26e35c
| 0.387237 | 4.17374 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc90.vhd
| 4 | 7,414 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc90.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x00p01n01i00090ent IS
END c04s03b02x00p01n01i00090ent;
ARCHITECTURE c04s03b02x00p01n01i00090arch OF c04s03b02x00p01n01i00090ent IS
Procedure Variable_params_of_subp (
VARIABLE cp1 : in Boolean := FALSE;
VARIABLE cp2 : in Bit := '0';
VARIABLE cp3 : in Character := '$';
VARIABLE cp4 : in SEVERITY_LEVEL := FAILURE;
VARIABLE cp5 : in Integer := 5 + 6 ;
VARIABLE cp6 : in Real := 2.45 ;
VARIABLE cp7 : in TIME := 0 fs;
VARIABLE cp8 : in Natural := 10;
VARIABLE cp9 : in Positive := 99;
--
VARIABLE cp12 : out Boolean ;
VARIABLE cp13 : out Bit ;
VARIABLE cp14 : out Character ;
VARIABLE cp15 : out SEVERITY_LEVEL ;
VARIABLE cp16 : out Integer ;
VARIABLE cp17 : out Real ;
VARIABLE cp18 : out TIME ;
VARIABLE cp19 : out Natural ;
VARIABLE cp20 : out Positive ;
--
VARIABLE cp23 : inout Boolean ;
VARIABLE cp24 : inout Bit ;
VARIABLE cp25 : inout Character ;
VARIABLE cp26 : inout SEVERITY_LEVEL ;
VARIABLE cp27 : inout Integer ;
VARIABLE cp28 : inout Real ;
VARIABLE cp29 : inout TIME ;
VARIABLE cp30 : inout Natural ;
VARIABLE cp31 : inout Positive
) is
begin
-- assign ins to outs
cp12 := cp1 ;
cp13 := cp2 ;
cp14 := cp3 ;
cp15 := cp4 ;
cp16 := cp5 ;
cp17 := cp6 ;
cp18 := cp7 ;
cp19 := cp8 ;
cp20 := cp9 ;
-- assign ins to inouts
cp23 := cp1 ;
cp24 := cp2 ;
cp25 := cp3 ;
cp26 := cp4 ;
cp27 := cp5 ;
cp28 := cp6 ;
cp29 := cp7 ;
cp30 := cp8 ;
cp31 := cp9 ;
end Variable_params_of_subp;
BEGIN
TESTING: PROCESS
VARIABLE v1 : Boolean := false;
VARIABLE v2 : Bit := '1';
VARIABLE v3 : Character := '%';
VARIABLE v4 : SEVERITY_LEVEL := NOTE;
VARIABLE v5 : Integer := 22121;
VARIABLE v6 : Real := 2.545;
VARIABLE v7 : TIME := 12 ns;
VARIABLE v8 : Natural := 90;
VARIABLE v9 : Positive := 101;
VARIABLE v12 : Boolean ;
VARIABLE v13 : Bit ;
VARIABLE v14 : Character ;
VARIABLE v15 : SEVERITY_LEVEL ;
VARIABLE v16 : Integer ;
VARIABLE v17 : Real ;
VARIABLE v18 : TIME ;
VARIABLE v19 : Natural ;
VARIABLE v20 : Positive ;
VARIABLE v23 : Boolean ;
VARIABLE v24 : Bit ;
VARIABLE v25 : Character ;
VARIABLE v26 : SEVERITY_LEVEL ;
VARIABLE v27 : Integer ;
VARIABLE v28 : Real ;
VARIABLE v29 : TIME ;
VARIABLE v30 : Natural ;
VARIABLE v31 : Positive ;
BEGIN
Variable_params_of_subp ( v1,v2,v3,v4,v5,v6,v7,v8,v9,
v12,v13,v14,v15,v16,v17,v18,v19,v20,
v23,v24,v25,v26,v27,v28,v29,v30,v31
);
assert v12 = v1 report " v12 /= v1" severity failure;
assert v13 = v2 report " v13 /= v2" severity failure;
assert v14 = v3 report " v14 /= v3" severity failure;
assert v15 = v4 report " v15 /= v4" severity failure;
assert v16 = v5 report " v16 /= v5" severity failure;
assert v17 = v6 report " v17 /= v6" severity failure;
assert v18 = v7 report " v18 /= v7" severity failure;
assert v19 = v8 report " v19 /= v8" severity failure;
assert v20 = v9 report " v20 /= v9" severity failure;
assert v23 = v1 report " v23 /= v1" severity failure;
assert v24 = v2 report " v24 /= v2" severity failure;
assert v25 = v3 report " v25 /= v3" severity failure;
assert v26 = v4 report " v26 /= v4" severity failure;
assert v27 = v5 report " v27 /= v5" severity failure;
assert v28 = v6 report " v28 /= v6" severity failure;
assert v29 = v7 report " v29 /= v7" severity failure;
assert v30 = v8 report " v30 /= v8" severity failure;
assert v31 = v9 report " v31 /= v9" severity failure;
WAIT for 1 ns;
assert NOT( v12 = v1 and
v13 = v2 and
v14 = v3 and
v15 = v4 and
v16 = v5 and
v17 = v6 and
v18 = v7 and
v19 = v8 and
v20 = v9 and
v23 = v1 and
v24 = v2 and
v25 = v3 and
v26 = v4 and
v27 = v5 and
v28 = v6 and
v29 = v7 and
v30 = v8 and
v31 = v9 )
report "***PASSED TEST:c04s03b02x00p01n01i00090"
severity NOTE;
assert ( v12 = v1 and
v13 = v2 and
v14 = v3 and
v15 = v4 and
v16 = v5 and
v17 = v6 and
v18 = v7 and
v19 = v8 and
v20 = v9 and
v23 = v1 and
v24 = v2 and
v25 = v3 and
v26 = v4 and
v27 = v5 and
v28 = v6 and
v29 = v7 and
v30 = v8 and
v31 = v9 )
report "***FAILED TEST: c04s03b02x00p01n01i00090 - Variables as the interface objects that appear as variable parameters of subprogram."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x00p01n01i00090arch;
|
gpl-2.0
|
b630229d92c53dcda832705ec04a66dc
| 0.47707 | 3.675756 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc755.vhd
| 4 | 57,757 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc755.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x01p05n02i00755ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15;
C1 : boolean := true;
C2 : bit := '1';
C3 : character := 's';
C4 : severity_level := note;
C5 : integer := 3;
C6 : real := 3.0;
C7 : time := 3 ns;
C8 : natural := 1;
C9 : positive := 1;
C10 : string := "shishir";
C11 : bit_vector := B"0011"
);
END c01s01b01x01p05n02i00755ent;
ARCHITECTURE c01s01b01x01p05n02i00755arch OF c01s01b01x01p05n02i00755ent IS
subtype hi_to_low_range is integer range zero to seven;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
subtype boolean_vector_st is boolean_vector(zero to fifteen);
subtype severity_level_vector_st is severity_level_vector(zero to fifteen);
subtype integer_vector_st is integer_vector(zero to fifteen);
subtype real_vector_st is real_vector(zero to fifteen);
subtype time_vector_st is time_vector(zero to fifteen);
subtype natural_vector_st is natural_vector(zero to fifteen);
subtype positive_vector_st is positive_vector(zero to fifteen);
type boolean_cons_vector is array (fifteen downto zero) of boolean;
type severity_level_cons_vector is array (fifteen downto zero) of severity_level;
type integer_cons_vector is array (fifteen downto zero) of integer;
type real_cons_vector is array (fifteen downto zero) of real;
type time_cons_vector is array (fifteen downto zero) of time;
type natural_cons_vector is array (fifteen downto zero) of natural;
type positive_cons_vector is array (fifteen downto zero) of positive;
type boolean_cons_vectorofvector is array (zero to fifteen) of boolean_cons_vector;
type severity_level_cons_vectorofvector is array (zero to fifteen) of severity_level_cons_vector;
type integer_cons_vectorofvector is array (zero to fifteen) of integer_cons_vector ;
type real_cons_vectorofvector is array (zero to fifteen) of real_cons_vector;
type time_cons_vectorofvector is array (zero to fifteen) of time_cons_vector;
type natural_cons_vectorofvector is array (zero to fifteen) of natural_cons_vector;
type positive_cons_vectorofvector is array (zero to fifteen) of positive_cons_vector;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
j:string(one to seven);
k:bit_vector(zero to three);
end record;
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type record_cons_arrayofarray is record
a:boolean_cons_vectorofvector;
b:severity_level_cons_vectorofvector;
c:integer_cons_vectorofvector;
d:real_cons_vectorofvector;
e:time_cons_vectorofvector;
f:natural_cons_vectorofvector;
g:positive_cons_vectorofvector;
end record;
type record_array_new is record
a:boolean_vector(zero to fifteen);
b:severity_level_vector(zero to fifteen);
c:integer_vector(zero to fifteen);
d:real_vector(zero to fifteen);
e:time_vector(zero to fifteen);
f:natural_vector(zero to fifteen);
g:positive_vector(zero to fifteen);
end record;
type record_of_records is record
a: record_std_package;
c: record_cons_array;
g: record_cons_arrayofarray;
i: record_array_st;
j: record_array_new;
end record;
subtype boolean_vector_range is boolean_vector(hi_to_low_range);
subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
subtype integer_vector_range is integer_vector(hi_to_low_range);
subtype real_vector_range is real_vector(hi_to_low_range);
subtype time_vector_range is time_vector(hi_to_low_range);
subtype natural_vector_range is natural_vector(hi_to_low_range);
subtype positive_vector_range is positive_vector(hi_to_low_range);
type array_rec_std is array (integer range <>) of record_std_package;
type array_rec_cons is array (integer range <>) of record_cons_array;
type array_rec_rec is array (integer range <>) of record_of_records;
subtype array_rec_std_st is array_rec_std (hi_to_low_range);
subtype array_rec_cons_st is array_rec_cons (hi_to_low_range);
subtype array_rec_rec_st is array_rec_rec (hi_to_low_range);
type record_of_arr_of_record is record
a: array_rec_std(zero to seven);
b: array_rec_cons(zero to seven);
c: array_rec_rec(zero to seven);
end record;
type current is range -2147483647 to +2147483647
units
nA;
uA = 1000 nA;
mA = 1000 uA;
A = 1000 mA;
end units;
type current_vector is array (natural range <>) of current;
subtype current_vector_range is current_vector(hi_to_low_range);
type resistance is range -2147483647 to +2147483647
units
uOhm;
mOhm = 1000 uOhm;
Ohm = 1000 mOhm;
KOhm = 1000 Ohm;
end units;
type resistance_vector is array (natural range <>) of resistance;
subtype resistance_vector_range is resistance_vector(hi_to_low_range);
type byte is array(zero to seven) of bit;
subtype word is bit_vector(zero to fifteen); --constrained array
constant size :integer := seven;
type primary_memory is array(zero to size) of word; --array of an array
type primary_memory_module is --record with field
record --as an array
enable:bit;
memory_number:primary_memory;
end record;
type whole_memory is array(0 to size) of primary_memory_module; --array of a complex record
subtype delay is integer range one to 10;
constant C12 : boolean_vector := (C1,false);
constant C13 : severity_level_vector := (C4,error);
constant C14 : integer_vector := (one,two,three,four);
constant C15 : real_vector := (1.0,2.0,C6,4.0);
constant C16 : time_vector := (1 ns, 2 ns,C7, 4 ns);
constant C17 : natural_vector := (one,2,3,4);
constant C18 : positive_vector := (one,2,3,4);
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
constant C27 : severity_level_cons_vectorofvector := (others => (others => C4));
constant C28 : integer_cons_vectorofvector := (others => (others => C5));
constant C29 : real_cons_vectorofvector := (others => (others => C6));
constant C30 : time_cons_vectorofvector := (others => (others => C7));
constant C31 : natural_cons_vectorofvector := (others => (others => C8));
constant C32 : positive_cons_vectorofvector := (others => (others => C9));
constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st:= (others => C4);
constant C72 : integer_vector_st:=(others => C5);
constant C73 : real_vector_st:=(others => C6);
constant C74 : time_vector_st:=(others => C7);
constant C75 : natural_vector_st:=(others => C8);
constant C76 : positive_vector_st:=(others => C9);
constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54a : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54b : record_array_new:= (C70,C71,C72,C73,C74,C75,C76);
constant C55 : record_of_records := (C50,C51,C53,C77,C54b);
constant C60 : byte := (others => '0');
constant C61 : word := (others =>'0' );
constant C64 : primary_memory := (others => C61);
constant C65 : primary_memory_module := ('1',C64);
constant C66 : whole_memory := (others => C65);
constant C67 : current := 1 A;
constant C68 : resistance := 1 Ohm;
constant C69 : delay := 2;
constant C78 : boolean_vector_range := (others => C1);
constant C79 : severity_level_vector_range := (others => C4) ;
constant C80 : integer_vector_range :=(others => C5) ;
constant C81 : real_vector_range :=(others => C6);
constant C82 : time_vector_range :=(others => C7);
constant C83 : natural_vector_range :=(others => C8);
constant C84 : positive_vector_range :=(others => C9);
constant C85 : array_rec_std(0 to 7) :=(others => C50) ;
constant C86 : array_rec_cons (0 to 7) :=(others => C51);
constant C88 : array_rec_rec(0 to 7) :=(others => C55);
constant C102 : record_of_arr_of_record:= (C85,C86,C88);
signal S1 : boolean_vector(zero to fifteen);
signal S2 : severity_level_vector(zero to fifteen);
signal S3 : integer_vector(zero to fifteen);
signal S4 : real_vector(zero to fifteen);
signal S5 : time_vector (zero to fifteen);
signal S6 : natural_vector(zero to fifteen);
signal S7 : positive_vector(zero to fifteen);
signal S8 : boolean_cons_vector;
signal S9 : severity_level_cons_vector ;
signal S10 : integer_cons_vector;
signal S11 : real_cons_vector;
signal S12 : time_cons_vector ;
signal S13 : natural_cons_vector ;
signal S14 : positive_cons_vector ;
signal S15 : boolean_cons_vectorofvector;
signal S16 : severity_level_cons_vectorofvector;
signal S17 : integer_cons_vectorofvector;
signal S18 : real_cons_vectorofvector;
signal S19 : time_cons_vectorofvector;
signal S20 : natural_cons_vectorofvector;
signal S21 : positive_cons_vectorofvector;
signal S22 : record_std_package;
signal S23 : record_cons_array;
signal S24 : record_cons_arrayofarray ;
signal S25 : boolean_vector_st;
signal S26 : severity_level_vector_st;
signal S27 : integer_vector_st;
signal S28 : real_vector_st;
signal S29 : time_vector_st;
signal S30 : natural_vector_st;
signal S31 : positive_vector_st;
signal S32 : record_array_st;
signal S33 : record_array_st;
signal S34 : record_array_new;
signal S35 : record_of_records;
signal S36 : byte;
signal S37 : word;
signal S38 : current_vector(zero to three);
signal S39 : resistance_vector(zero to three);
signal S40 : delay;
signal S41 : boolean_vector_range;
signal S42 : severity_level_vector_range ;
signal S43 : integer_vector_range ;
signal S44 : real_vector_range ;
signal S45 : time_vector_range ;
signal S46 : natural_vector_range ;
signal S47 : positive_vector_range ;
signal S48 : array_rec_std(zero to seven);
signal S49 : array_rec_cons(zero to seven);
signal S50 : array_rec_rec(zero to seven);
signal S51 : record_of_arr_of_record;
BEGIN
assert (S1'left = 0) report " boolean_vector(zero to fifteen) error in the left generic value" severity error;
assert (S2'left = 0) report " severity_level_vector(zero to fifteen) error in the left generic value" severity error;
assert (S3'left = 0) report " integer_vector(zero to fifteen) error in the left generic value" severity error;
assert (S4'left = 0) report " real_vector(zero to fifteen) error in the left generic value" severity error;
assert (S5'left = 0) report " time_vector (zero to fifteen) error in the left generic value" severity error;
assert (S6'left = 0) report " natural_vector(zero to fifteen) error in the left generic value" severity error;
assert (S7'left = 0) report " positive_vector(zero to fifteen) error in the left generic value" severity error;
assert (S8'left = 15) report " boolean_cons_vector error in the left generic value" severity error;
assert (S9'left = 15) report " severity_level_cons_vector error in the left generic value" severity error;
assert (S10'left = 15) report " integer_cons_vector error in the left generic value" severity error;
assert (S11'left = 15) report " real_cons_vector error in the left generic value" severity error;
assert (S12'left = 15) report " time_cons_vector error in the left generic value" severity error;
assert (S13'left = 15) report " natural_cons_vector error in the left generic value" severity error;
assert (S14'left = 15) report " positive_cons_vector error in the left generic value" severity error;
assert (S15'left = 0) report " boolean_cons_vectorofvector error in the left generic value" severity error;
assert (S16'left = 0) report " severity_level_cons_vectorofvector error in the left generic value" severity error;
assert (S17'left = 0) report " integer_cons_vectorofvector error in the left generic value" severity error;
assert (S18'left = 0) report " real_cons_vectorofvector error in the left generic value" severity error;
assert (S19'left = 0) report " time_cons_vectorofvector error in the left generic value" severity error;
assert (S20'left = 0) report " natural_cons_vectorofvector error in the left generic value" severity error;
assert (S21'left = 0) report " positive_cons_vectorofvector error in the left generic value" severity error;
assert (S22.j'left = 1) report " record_std_package error in the left generic value" severity error;
assert (S22.k'left = 0) report " record_std_package error in the left generic value" severity error;
assert (S23.a'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (S23.b'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (S23.c'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (S23.d'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (S23.e'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (S23.f'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (S23.g'left = 15) report " record_cons_array error in the left generic value" severity error;
assert (S24.a'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (S24.b'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (S24.c'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (S24.d'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (S24.e'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (S24.f'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (S24.g'left = 0) report " record_cons_arrayofarray error in the left generic value" severity error;
assert (S25'left = 0) report " boolean_vector_st error in the left generic value" severity error;
assert (S26'left = 0) report " severity_level_vector_st error in the left generic value" severity error;
assert (S27'left = 0) report " integer_vector_st error in the left generic value" severity error;
assert (S28'left = 0) report " real_vector_st error in the left generic value" severity error;
assert (S29'left = 0) report " time_vector_st error in the left generic value" severity error;
assert (S30'left = 0) report " natural_vector_st error in the left generic value" severity error;
assert (S31'left = 0) report " positive_vector_st error in the left generic value" severity error;
assert (S32.a'left = 0) report " record_array_st error in the left generic value" severity error;
assert (S32.b'left = 0) report " record_array_st error in the left generic value" severity error;
assert (S32.c'left = 0) report " record_array_st error in the left generic value" severity error;
assert (S32.d'left = 0) report " record_array_st error in the left generic value" severity error;
assert (S32.e'left = 0) report " record_array_st error in the left generic value" severity error;
assert (S32.f'left = 0) report " record_array_st error in the left generic value" severity error;
assert (S32.g'left = 0) report " record_array_st error in the left generic value" severity error;
assert (S34.a'left = 0) report " record_array_new error in the left generic value" severity error;
assert (S34.b'left = 0) report " record_array_new error in the left generic value" severity error;
assert (S34.c'left = 0) report " record_array_new error in the left generic value" severity error;
assert (S34.d'left = 0) report " record_array_new error in the left generic value" severity error;
assert (S34.e'left = 0) report " record_array_new error in the left generic value" severity error;
assert (S34.f'left = 0) report " record_array_new error in the left generic value" severity error;
assert (S34.g'left = 0) report " record_array_new error in the left generic value" severity error;
assert (S36'left = 0) report " byte error in the left generic value" severity error;
assert (S37'left = 0) report " word error in the left generic value" severity error;
assert (S38'left = 0) report " current_vector(zero to three) error in the left generic value" severity error;
assert (S39'left = 0) report " resistance_vector(zero to three) error in the left generic value" severity error;
--assert (S40'left = 1) report " delay error in the left generic value" severity error;
assert (S41'left = 0) report " boolean_vector_range error in the left generic value" severity error;
assert (S42'left = 0) report " severity_level_vector_range error in the left generic value" severity error;
assert (S43'left = 0) report " integer_vector_range error in the left generic value" severity error;
assert (S44'left = 0) report " real_vector_range error in the left generic value" severity error;
assert (S45'left = 0) report " time_vector_range error in the left generic value" severity error;
assert (S46'left = 0) report " natural_vector_range error in the left generic value" severity error;
assert (S47'left = 0) report " positive_vector_range error in the left generic value" severity error;
assert (S48'left = 0) report " array_rec_std(zero to seven) error in the left generic value" severity error;
assert (S49'left = 0) report " array_rec_cons(zero to seven) error in the left generic value" severity error;
assert (S50'left = 0) report " array_rec_rec(zero to seven) error in the left generic value" severity error;
assert (S51.a'left = 0) report " record_of_arr_of_record error in the left generic value" severity error;
assert (S51.b'left = 0) report " record_of_arr_of_record error in the left generic value" severity error;
assert (S51.c'left = 0) report " record_of_arr_of_record error in the left generic value" severity error;
assert (S1'right = 15) report " boolean_vector(zero to fifteen) error in the right generic value" severity error;
assert (S2'right = 15) report " severity_level_vector(zero to fifteen) error in the right generic value" severity error;
assert (S3'right = 15) report " integer_vector(zero to fifteen) error in the right generic value" severity error;
assert (S4'right = 15) report " real_vector(zero to fifteen) error in the right generic value" severity error;
assert (S5'right = 15) report " time_vector (zero to fifteen) error in the right generic value" severity error;
assert (S6'right = 15) report " natural_vector(zero to fifteen) error in the right generic value" severity error;
assert (S7'right = 15) report " positive_vector(zero to fifteen) error in the right generic value" severity error;
assert (S8'right = 0) report " boolean_cons_vector error in the right generic value" severity error;
assert (S9'right = 0) report " severity_level_cons_vector error in the right generic value" severity error;
assert (S10'right = 0) report " integer_cons_vector error in the right generic value" severity error;
assert (S11'right = 0) report " real_cons_vector error in the right generic value" severity error;
assert (S12'right = 0) report " time_cons_vector error in the right generic value" severity error;
assert (S13'right = 0) report " natural_cons_vector error in the right generic value" severity error;
assert (S14'right = 0) report " positive_cons_vector error in the right generic value" severity error;
assert (S15'right = 15) report " boolean_cons_vectorofvector error in the right generic value" severity error;
assert (S16'right = 15) report " severity_level_cons_vectorofvector error in the right generic value" severity error;
assert (S17'right = 15) report " integer_cons_vectorofvector error in the right generic value" severity error;
assert (S18'right = 15) report " real_cons_vectorofvector error in the right generic value" severity error;
assert (S19'right = 15) report " time_cons_vectorofvector error in the right generic value" severity error;
assert (S20'right = 15) report " natural_cons_vectorofvector error in the right generic value" severity error;
assert (S21'right = 15) report " positive_cons_vectorofvector error in the right generic value" severity error;
assert (S22.j'right = 7) report " record_std_package error in the right generic value" severity error;
assert (S22.k'right = 3) report " record_std_package error in the right generic value" severity error;
assert (S23.a'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (S23.b'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (S23.c'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (S23.d'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (S23.e'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (S23.f'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (S23.g'right = 0) report " record_cons_array error in the right generic value" severity error;
assert (S24.a'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (S24.b'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (S24.c'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (S24.d'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (S24.e'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (S24.f'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (S24.g'right = 15) report " record_cons_arrayofarray error in the right generic value" severity error;
assert (S25'right = 15) report " boolean_vector_st error in the right generic value" severity error;
assert (S26'right = 15) report " severity_level_vector_st error in the right generic value" severity error;
assert (S27'right = 15) report " integer_vector_st error in the right generic value" severity error;
assert (S28'right = 15) report " real_vector_st error in the right generic value" severity error;
assert (S29'right = 15) report " time_vector_st error in the right generic value" severity error;
assert (S30'right = 15) report " natural_vector_st error in the right generic value" severity error;
assert (S31'right = 15) report " positive_vector_st error in the right generic value" severity error;
assert (S32.a'right = 15) report " record_array_st error in the right generic value" severity error;
assert (S32.b'right = 15) report " record_array_st error in the right generic value" severity error;
assert (S32.c'right = 15) report " record_array_st error in the right generic value" severity error;
assert (S32.d'right = 15) report " record_array_st error in the right generic value" severity error;
assert (S32.e'right = 15) report " record_array_st error in the right generic value" severity error;
assert (S32.f'right = 15) report " record_array_st error in the right generic value" severity error;
assert (S32.g'right = 15) report " record_array_st error in the right generic value" severity error;
assert (S34.a'right = 15) report " record_array_new error in the right generic value" severity error;
assert (S34.b'right = 15) report " record_array_new error in the right generic value" severity error;
assert (S34.c'right = 15) report " record_array_new error in the right generic value" severity error;
assert (S34.d'right = 15) report " record_array_new error in the right generic value" severity error;
assert (S34.e'right = 15) report " record_array_new error in the right generic value" severity error;
assert (S34.f'right = 15) report " record_array_new error in the right generic value" severity error;
assert (S34.g'right = 15) report " record_array_new error in the right generic value" severity error;
assert (S36'right = 7) report " byte error in the right generic value" severity error;
assert (S37'right = 15) report " word error in the right generic value" severity error;
assert (S38'right = 3) report " current_vector(zero to three) error in the right generic value" severity error;
assert (S39'right = 3) report " resistance_vector(zero to three) error in the right generic value" severity error;
--assert (S40'right = 1) report " delay error in the right generic value" severity error;
assert (S41'right = 7) report " boolean_vector_range error in the right generic value" severity error;
assert (S42'right = 7) report " severity_level_vector_range error in the right generic value" severity error;
assert (S43'right = 7) report " integer_vector_range error in the right generic value" severity error;
assert (S44'right = 7) report " real_vector_range error in the right generic value" severity error;
assert (S45'right = 7) report " time_vector_range error in the right generic value" severity error;
assert (S46'right = 7) report " natural_vector_range error in the right generic value" severity error;
assert (S47'right = 7) report " positive_vector_range error in the right generic value" severity error;
assert (S48'right = 7) report " array_rec_std(zero to seven) error in the right generic value" severity error;
assert (S49'right = 7) report " array_rec_cons(zero to seven) error in the right generic value" severity error;
assert (S50'right = 7) report " array_rec_rec(zero to seven) error in the right generic value" severity error;
assert (S51.a'right = 7) report " record_of_arr_of_record error in the right generic value" severity error;
assert (S51.b'right = 7) report " record_of_arr_of_record error in the right generic value" severity error;
assert (S51.c'right = 7) report " record_of_arr_of_record error in the right generic value" severity error;
assert (S1'length = 16) report " boolean_vector(zero to fifteen) error in the length generic value" severity error;
assert (S2'length = 16) report " severity_level_vector(zero to fifteen) error in the length generic value" severity error;
assert (S3'length = 16) report " integer_vector(zero to fifteen) error in the length generic value" severity error;
assert (S4'length = 16) report " real_vector(zero to fifteen) error in the length generic value" severity error;
assert (S5'length = 16) report " time_vector (zero to fifteen) error in the length generic value" severity error;
assert (S6'length = 16) report " natural_vector(zero to fifteen) error in the length generic value" severity error;
assert (S7'length = 16) report " positive_vector(zero to fifteen) error in the length generic value" severity error;
assert (S8'length = 16) report " boolean_cons_vector error in the length generic value" severity error;
assert (S9'length = 16) report " severity_level_cons_vector error in the length generic value" severity error;
assert (S10'length = 16) report " integer_cons_vector error in the length generic value" severity error;
assert (S11'length = 16) report " real_cons_vector error in the length generic value" severity error;
assert (S12'length = 16) report " time_cons_vector error in the length generic value" severity error;
assert (S13'length = 16) report " natural_cons_vector error in the length generic value" severity error;
assert (S14'length = 16) report " positive_cons_vector error in the length generic value" severity error;
assert (S15'length = 16) report " boolean_cons_vectorofvector error in the length generic value" severity error;
assert (S16'length = 16) report " severity_level_cons_vectorofvector error in the length generic value" severity error;
assert (S17'length = 16) report " integer_cons_vectorofvector error in the length generic value" severity error;
assert (S18'length = 16) report " real_cons_vectorofvector error in the length generic value" severity error;
assert (S19'length = 16) report " time_cons_vectorofvector error in the length generic value" severity error;
assert (S20'length = 16) report " natural_cons_vectorofvector error in the length generic value" severity error;
assert (S21'length = 16) report " positive_cons_vectorofvector error in the length generic value" severity error;
assert (S22.j'length = 7) report " record_std_package error in the length generic value" severity error;
assert (S22.k'length = 4) report " record_std_package error in the length generic value" severity error;
assert (S23.a'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (S23.b'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (S23.c'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (S23.d'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (S23.e'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (S23.f'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (S23.g'length = 16) report " record_cons_array error in the length generic value" severity error;
assert (S24.a'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (S24.b'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (S24.c'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (S24.d'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (S24.e'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (S24.f'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (S24.g'length = 16) report " record_cons_arrayofarray error in the length generic value" severity error;
assert (S25'length = 16) report " boolean_vector_st error in the length generic value" severity error;
assert (S26'length = 16) report " severity_level_vector_st error in the length generic value" severity error;
assert (S27'length = 16) report " integer_vector_st error in the length generic value" severity error;
assert (S28'length = 16) report " real_vector_st error in the length generic value" severity error;
assert (S29'length = 16) report " time_vector_st error in the length generic value" severity error;
assert (S30'length = 16) report " natural_vector_st error in the length generic value" severity error;
assert (S31'length = 16) report " positive_vector_st error in the length generic value" severity error;
assert (S32.a'length = 16) report " record_array_st error in the length generic value" severity error;
assert (S32.b'length = 16) report " record_array_st error in the length generic value" severity error;
assert (S32.c'length = 16) report " record_array_st error in the length generic value" severity error;
assert (S32.d'length = 16) report " record_array_st error in the length generic value" severity error;
assert (S32.e'length = 16) report " record_array_st error in the length generic value" severity error;
assert (S32.f'length = 16) report " record_array_st error in the length generic value" severity error;
assert (S32.g'length = 16) report " record_array_st error in the length generic value" severity error;
assert (S34.a'length = 16) report " record_array_new error in the length generic value" severity error;
assert (S34.b'length = 16) report " record_array_new error in the length generic value" severity error;
assert (S34.c'length = 16) report " record_array_new error in the length generic value" severity error;
assert (S34.d'length = 16) report " record_array_new error in the length generic value" severity error;
assert (S34.e'length = 16) report " record_array_new error in the length generic value" severity error;
assert (S34.f'length = 16) report " record_array_new error in the length generic value" severity error;
assert (S34.g'length = 16) report " record_array_new error in the length generic value" severity error;
assert (S36'length = 8) report " byte error in the length generic value" severity error;
assert (S37'length = 16) report " word error in the length generic value" severity error;
assert (S38'length = 4) report " current_vector(zero to three) error in the length generic value" severity error;
assert (S39'length = 4) report " resistance_vector(zero to three) error in the length generic value" severity error;
--assert (S40'length = 1) report " delay error in the length generic value" severity error;
assert (S41'length = 8) report " boolean_vector_range error in the length generic value" severity error;
assert (S42'length = 8) report " severity_level_vector_range error in the length generic value" severity error;
assert (S43'length = 8) report " integer_vector_range error in the length generic value" severity error;
assert (S44'length = 8) report " real_vector_range error in the length generic value" severity error;
assert (S45'length = 8) report " time_vector_range error in the length generic value" severity error;
assert (S46'length = 8) report " natural_vector_range error in the length generic value" severity error;
assert (S48'length = 8) report " positive_vector_range error in the length generic value" severity error;
assert (S48'length = 8) report " array_rec_std(zero to seven) error in the length generic value" severity error;
assert (S49'length = 8) report " array_rec_cons(zero to seven) error in the length generic value" severity error;
assert (S50'length = 8) report " array_rec_rec(zero to seven) error in the length generic value" severity error;
assert (S51.a'length = 8) report " record_of_arr_of_record error in the length generic value" severity error;
assert (S51.b'length = 8) report " record_of_arr_of_record error in the length generic value" severity error;
assert (S51.c'length = 8) report " record_of_arr_of_record error in the length generic value" severity error;
TESTING: PROCESS
BEGIN
assert NOT( (S1'left = 0) and
(S2'left = 0) and
(S3'left = 0) and
(S4'left = 0) and
(S5'left = 0) and
(S6'left = 0) and
(S7'left = 0) and
(S8'left = 15) and
(S9'left = 15) and
(S10'left = 15) and
(S11'left = 15) and
(S12'left = 15) and
(S13'left = 15) and
(S14'left = 15) and
(S15'left = 0) and
(S16'left = 0) and
(S17'left = 0) and
(S18'left = 0) and
(S19'left = 0) and
(S20'left = 0) and
(S21'left = 0) and
(S22.j'left = 1) and
(S22.k'left = 0) and
(S23.a'left = 15) and
(S23.b'left = 15) and
(S23.c'left = 15) and
(S23.d'left = 15) and
(S23.e'left = 15) and
(S23.f'left = 15) and
(S23.g'left = 15) and
(S24.a'left = 0) and
(S24.b'left = 0) and
(S24.c'left = 0) and
(S24.d'left = 0) and
(S24.e'left = 0) and
(S24.f'left = 0) and
(S24.g'left = 0) and
(S25'left = 0) and
(S26'left = 0) and
(S27'left = 0) and
(S28'left = 0) and
(S29'left = 0) and
(S30'left = 0) and
(S31'left = 0) and
(S32.a'left = 0) and
(S32.b'left = 0) and
(S32.c'left = 0) and
(S32.d'left = 0) and
(S32.e'left = 0) and
(S32.f'left = 0) and
(S32.g'left = 0) and
(S34.a'left = 0) and
(S34.b'left = 0) and
(S34.c'left = 0) and
(S34.d'left = 0) and
(S34.e'left = 0) and
(S34.f'left = 0) and
(S34.g'left = 0) and
(S36'left = 0) and
(S37'left = 0) and
(S38'left = 0) and
(S39'left = 0) and
-- (S40'left = 1) and
(S42'left = 0) and
(S43'left = 0) and
(S44'left = 0) and
(S45'left = 0) and
(S46'left = 0) and
(S47'left = 0) and
(S48'left = 0) and
(S49'left = 0) and
(S50'left = 0) and
(S51.a'left = 0) and
(S51.b'left = 0) and
(S51.c'left = 0) and
(S1'right = 15) and
(S2'right = 15) and
(S3'right = 15) and
(S4'right = 15) and
(S5'right = 15) and
(S6'right = 15) and
(S7'right = 15) and
(S8'right = 0) and
(S9'right = 0) and
(S10'right = 0)and
(S11'right = 0) and
(S12'right = 0) and
(S13'right = 0) and
(S14'right = 0) and
(S15'right = 15) and
(S16'right = 15) and
(S17'right = 15) and
(S18'right = 15) and
(S19'right = 15) and
(S20'right = 15) and
(S21'right = 15) and
(S22.j'right = 7) and
(S22.k'right = 3) and
(S23.a'right = 0) and
(S23.b'right = 0) and
(S23.c'right = 0) and
(S23.d'right = 0) and
(S23.e'right = 0) and
(S23.f'right = 0) and
(S23.g'right = 0) and
(S24.a'right = 15) and
(S24.b'right = 15) and
(S24.c'right = 15) and
(S24.d'right = 15) and
(S24.e'right = 15) and
(S24.f'right = 15) and
(S24.g'right = 15) and
(S25'right = 15) and
(S26'right = 15) and
(S27'right = 15) and
(S28'right = 15) and
(S29'right = 15) and
(S30'right = 15) and
(S31'right = 15) and
(S32.a'right = 15) and
(S32.b'right = 15) and
(S32.c'right = 15) and
(S32.d'right = 15) and
(S32.e'right = 15) and
(S32.f'right = 15) and
(S32.g'right = 15) and
(S34.a'right = 15) and
(S34.b'right = 15) and
(S34.c'right = 15) and
(S34.d'right = 15) and
(S34.e'right = 15) and
(S34.f'right = 15) and
(S34.g'right = 15) and
(S36'right = 7) and
(S37'right = 15) and
(S38'right = 3) and
(S39'right = 3) and
-- (S40'right = 1) and
(S41'right = 7) and
(S42'right = 7) and
(S43'right = 7) and
(S44'right = 7) and
(S45'right = 7) and
(S46'right = 7) and
(S47'right = 7) and
(S48'right = 7) and
(S49'right = 7) and
(S50'right = 7) and
(S51.a'right = 7) and
(S51.b'right = 7) and
(S51.c'right = 7) and
(S1'length = 16) and
(S2'length = 16) and
(S3'length = 16) and
(S4'length = 16) and
(S5'length = 16) and
(S6'length = 16) and
(S7'length = 16) and
(S8'length = 16) and
(S9'length = 16) and
(S10'length = 16) and
(S11'length = 16) and
(S12'length = 16) and
(S13'length = 16) and
(S14'length = 16) and
(S15'length = 16) and
(S16'length = 16) and
(S17'length = 16) and
(S18'length = 16) and
(S19'length = 16) and
(S20'length = 16) and
(S21'length = 16) and
(S22.j'length = 7)and
(S22.k'length = 4) and
(S23.a'length = 16) and
(S23.b'length = 16) and
(S23.c'length = 16) and
(S23.d'length = 16) and
(S23.e'length = 16) and
(S23.f'length = 16) and
(S23.g'length = 16) and
(S24.a'length = 16) and
(S24.b'length = 16) and
(S24.c'length = 16) and
(S24.d'length = 16) and
(S24.e'length = 16) and
(S24.f'length = 16) and
(S24.g'length = 16) and
(S25'length = 16) and
(S26'length = 16) and
(S27'length = 16) and
(S28'length = 16) and
(S29'length = 16) and
(S30'length = 16) and
(S31'length = 16) and
(S32.a'length = 16) and
(S32.b'length = 16) and
(S32.c'length = 16) and
(S32.d'length = 16) and
(S32.e'length = 16) and
(S32.f'length = 16) and
(S32.g'length = 16) and
(S34.a'length = 16) and
(S34.b'length = 16) and
(S34.c'length = 16) and
(S34.d'length = 16) and
(S34.e'length = 16) and
(S34.f'length = 16) and
(S34.g'length = 16) and
(S36'length = 8) and
(S37'length = 16) and
(S38'length = 4) and
(S39'length = 4) and
-- (S40'length = 1) and
(S41'length = 8) and
(S42'length = 8) and
(S43'length = 8) and
(S44'length = 8) and
(S45'length = 8) and
(S46'length = 8) and
(S48'length = 8) and
(S48'length = 8) and
(S49'length = 8) and
(S50'length = 8) and
(S51.a'length = 8) and
(S51.b'length = 8) and
(S51.c'length = 8) )
report "***PASSED TEST: c01s01b01x01p05n02i00755"
severity NOTE;
assert ((S1'left = 0) and
(S2'left = 0) and
(S3'left = 0) and
(S4'left = 0) and
(S5'left = 0) and
(S6'left = 0) and
(S7'left = 0) and
(S8'left = 15) and
(S9'left = 15) and
(S10'left = 15) and
(S11'left = 15) and
(S12'left = 15) and
(S13'left = 15) and
(S14'left = 15) and
(S15'left = 0) and
(S16'left = 0) and
(S17'left = 0) and
(S18'left = 0) and
(S19'left = 0) and
(S20'left = 0) and
(S21'left = 0) and
(S22.j'left = 1) and
(S22.k'left = 0) and
(S23.a'left = 15) and
(S23.b'left = 15) and
(S23.c'left = 15) and
(S23.d'left = 15) and
(S23.e'left = 15) and
(S23.f'left = 15) and
(S23.g'left = 15) and
(S24.a'left = 0) and
(S24.b'left = 0) and
(S24.c'left = 0) and
(S24.d'left = 0) and
(S24.e'left = 0) and
(S24.f'left = 0) and
(S24.g'left = 0) and
(S25'left = 0) and
(S26'left = 0) and
(S27'left = 0) and
(S28'left = 0) and
(S29'left = 0) and
(S30'left = 0) and
(S31'left = 0) and
(S32.a'left = 0) and
(S32.b'left = 0) and
(S32.c'left = 0) and
(S32.d'left = 0) and
(S32.e'left = 0) and
(S32.f'left = 0) and
(S32.g'left = 0) and
(S34.a'left = 0) and
(S34.b'left = 0) and
(S34.c'left = 0) and
(S34.d'left = 0) and
(S34.e'left = 0) and
(S34.f'left = 0) and
(S34.g'left = 0) and
(S36'left = 0) and
(S37'left = 0) and
(S38'left = 0) and
(S39'left = 0) and
-- (S40'left = 1) and
(S42'left = 0) and
(S43'left = 0) and
(S44'left = 0) and
(S45'left = 0) and
(S46'left = 0) and
(S47'left = 0) and
(S48'left = 0) and
(S49'left = 0) and
(S50'left = 0) and
(S51.a'left = 0) and
(S51.b'left = 0) and
(S51.c'left = 0) and
(S1'right = 15) and
(S2'right = 15) and
(S3'right = 15) and
(S4'right = 15) and
(S5'right = 15) and
(S6'right = 15) and
(S7'right = 15) and
(S8'right = 0) and
(S9'right = 0) and
(S10'right = 0)and
(S11'right = 0) and
(S12'right = 0) and
(S13'right = 0) and
(S14'right = 0) and
(S15'right = 15) and
(S16'right = 15) and
(S17'right = 15) and
(S18'right = 15) and
(S19'right = 15) and
(S20'right = 15) and
(S21'right = 15) and
(S22.j'right = 7) and
(S22.k'right = 3) and
(S23.a'right = 0) and
(S23.b'right = 0) and
(S23.c'right = 0) and
(S23.d'right = 0) and
(S23.e'right = 0) and
(S23.f'right = 0) and
(S23.g'right = 0) and
(S24.a'right = 15) and
(S24.b'right = 15) and
(S24.c'right = 15) and
(S24.d'right = 15) and
(S24.e'right = 15) and
(S24.f'right = 15) and
(S24.g'right = 15) and
(S25'right = 15) and
(S26'right = 15) and
(S27'right = 15) and
(S28'right = 15) and
(S29'right = 15) and
(S30'right = 15) and
(S31'right = 15) and
(S32.a'right = 15) and
(S32.b'right = 15) and
(S32.c'right = 15) and
(S32.d'right = 15) and
(S32.e'right = 15) and
(S32.f'right = 15) and
(S32.g'right = 15) and
(S34.a'right = 15) and
(S34.b'right = 15) and
(S34.c'right = 15) and
(S34.d'right = 15) and
(S34.e'right = 15) and
(S34.f'right = 15) and
(S34.g'right = 15) and
(S36'right = 7) and
(S37'right = 15) and
(S38'right = 3) and
(S39'right = 3) and
-- (S40'right = 1) and
(S41'right = 7) and
(S42'right = 7) and
(S43'right = 7) and
(S44'right = 7) and
(S45'right = 7) and
(S46'right = 7) and
(S47'right = 7) and
(S48'right = 7) and
(S49'right = 7) and
(S50'right = 7) and
(S51.a'right = 7) and
(S51.b'right = 7) and
(S51.c'right = 7) and
(S1'length = 16) and
(S2'length = 16) and
(S3'length = 16) and
(S4'length = 16) and
(S5'length = 16) and
(S6'length = 16) and
(S7'length = 16) and
(S8'length = 16) and
(S9'length = 16) and
(S10'length = 16) and
(S11'length = 16) and
(S12'length = 16) and
(S13'length = 16) and
(S14'length = 16) and
(S15'length = 16) and
(S16'length = 16) and
(S17'length = 16) and
(S18'length = 16) and
(S19'length = 16) and
(S20'length = 16) and
(S21'length = 16) and
(S22.j'length = 7)and
(S22.k'length = 4) and
(S23.a'length = 16) and
(S23.b'length = 16) and
(S23.c'length = 16) and
(S23.d'length = 16) and
(S23.e'length = 16) and
(S23.f'length = 16) and
(S23.g'length = 16) and
(S24.a'length = 16) and
(S24.b'length = 16) and
(S24.c'length = 16) and
(S24.d'length = 16) and
(S24.e'length = 16) and
(S24.f'length = 16) and
(S24.g'length = 16) and
(S25'length = 16) and
(S26'length = 16) and
(S27'length = 16) and
(S28'length = 16) and
(S29'length = 16) and
(S30'length = 16) and
(S31'length = 16) and
(S32.a'length = 16) and
(S32.b'length = 16) and
(S32.c'length = 16) and
(S32.d'length = 16) and
(S32.e'length = 16) and
(S32.f'length = 16) and
(S32.g'length = 16) and
(S34.a'length = 16) and
(S34.b'length = 16) and
(S34.c'length = 16) and
(S34.d'length = 16) and
(S34.e'length = 16) and
(S34.f'length = 16) and
(S34.g'length = 16) and
(S36'length = 8) and
(S37'length = 16) and
(S38'length = 4) and
(S39'length = 4) and
-- (S40'length = 1) and
(S41'length = 8) and
(S42'length = 8) and
(S43'length = 8) and
(S44'length = 8) and
(S45'length = 8) and
(S46'length = 8) and
(S48'length = 8) and
(S48'length = 8) and
(S49'length = 8) and
(S50'length = 8) and
(S51.a'length = 8) and
(S51.b'length = 8) and
(S51.c'length = 8) )
report "***FAILED TEST: c01s01b01x01p05n02i00755 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00755arch;
|
gpl-2.0
|
637a94087153e49140ae29c829f891cf
| 0.5711 | 3.665017 | false | false | false | false |
123gmax/Digital-Lab
|
Lab3/Alex/Assignment3B/substitution_box.vhd
| 1 | 9,681 |
------------------------------------------------------------------------------
-- hw_acc - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: hw_acc
-- Version: 1.00.a
-- Description: Example Axi Streaming core (VHDL).
-- Date: Mon Sep 15 15:41:21 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------------
--
--
-- Definition of Ports
-- ACLK : Synchronous clock
-- ARESETN : System reset, active low
-- S_AXIS_TREADY : Ready to accept data in
-- S_AXIS_TDATA : Data in
-- S_AXIS_TLAST : Optional data in qualifier
-- S_AXIS_TVALID : Data in is valid
-- M_AXIS_TVALID : Data out is valid
-- M_AXIS_TDATA : Data Out
-- M_AXIS_TLAST : Optional data out qualifier
-- M_AXIS_TREADY : Connected slave device is ready to accept data out
--
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity myip_v1_0 is
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
ACLK : in std_logic;
ARESETN : in std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_TDATA : in std_logic_vector(31 downto 0);
S_AXIS_TLAST : in std_logic;
S_AXIS_TVALID : in std_logic;
M_AXIS_TVALID : out std_logic;
M_AXIS_TDATA : out std_logic_vector(31 downto 0);
M_AXIS_TLAST : out std_logic;
M_AXIS_TREADY : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of ACLK : signal is "Clk";
end myip_v1_0;
------------------------------------------------------------------------------
-- Architecture Section
------------------------------------------------------------------------------
-- In this section, we povide an example implementation of ENTITY hw_acc
-- that does the following:
--
-- 1. Read all inputs
-- 2. Add each input to the contents of register 'sum' which
-- acts as an accumulator
-- 3. After all the inputs have been read, write out the
-- content of 'sum' into the output stream NUMBER_OF_OUTPUT_WORDS times
--
-- You will need to modify this example or implement a new architecture for
-- ENTITY hw_acc to implement your coprocessor
architecture EXAMPLE of myip_v1_0 is
-- Total number of input data.
constant NUMBER_OF_INPUT_WORDS : natural := 4;
-- Total number of output data
constant NUMBER_OF_OUTPUT_WORDS : natural := 4;
type STATE_TYPE is (Idle, Read_Inputs, Write_Outputs);
signal state : STATE_TYPE;
-- Accumulator to hold sum of inputs read at any point in time
signal data : std_logic_vector(127 downto 0);
-- Counters to store the number inputs read & outputs written
signal nr_of_reads : natural range 0 to NUMBER_OF_INPUT_WORDS - 1;
signal nr_of_writes : natural range 0 to NUMBER_OF_OUTPUT_WORDS - 1;
begin
-- CAUTION:
-- The sequence in which data are read in and written out should be
-- consistent with the sequence they are written and read in the
-- driver's hw_acc.c file
S_AXIS_TREADY <= '1' when state = Read_Inputs else '0';
M_AXIS_TVALID <= '1' when state = Write_Outputs else '0';
M_AXIS_TLAST <= '1' when (state = Write_Outputs and nr_of_writes = 0) else '0';
M_AXIS_TDATA <= data(127 downto 96); --Most-significant word is always output.
The_SW_accelerator : process (ACLK) is
--These variables are used for indexing purposes during substitution.
variable H : natural range 0 to 127;
variable L : natural range 0 to 127;
begin -- process The_SW_accelerator
if ACLK'event and ACLK = '1' then -- Rising clock edge
if ARESETN = '0' then -- Synchronous reset (active low)
-- CAUTION: make sure your reset polarity is consistent with the
-- system reset polarity
state <= Idle;
nr_of_reads <= 0;
nr_of_writes <= 0;
data <= (others => '0');
else
case state is
when Idle =>
if (S_AXIS_TVALID = '1') then
state <= Read_Inputs;
nr_of_reads <= NUMBER_OF_INPUT_WORDS - 1;
data <= (others => '0');
end if;
when Read_Inputs =>
if (S_AXIS_TVALID = '1') then
data <= std_logic_vector(shift_left(unsigned(data), 32)); --Shift data accumulator 32-bits to the left.
--Begin substitution loop
--Seedbox used is S0 from Lab2 Assignment 2B
--Assign substituted read data to the lower 32-bits.
substitution: for I in 0 to 7
loop
H := I*4 + 3;
L := I*4;
case S_AXIS_TDATA(H downto L) is
when x"0" => data(H downto L) <= x"3";
when x"1" => data(H downto L) <= x"8";
when x"2" => data(H downto L) <= x"F";
when x"3" => data(H downto L) <= x"1";
when x"4" => data(H downto L) <= x"A";
when x"5" => data(H downto L) <= x"6";
when x"6" => data(H downto L) <= x"5";
when x"7" => data(H downto L) <= x"B";
when x"8" => data(H downto L) <= x"E";
when x"9" => data(H downto L) <= x"D";
when x"A" => data(H downto L) <= x"4";
when x"B" => data(H downto L) <= x"2";
when x"C" => data(H downto L) <= x"7";
when x"D" => data(H downto L) <= x"0";
when x"E" => data(H downto L) <= x"9";
when x"F" => data(H downto L) <= x"C";
when others => data(H downto L) <= x"0";
end case;
end loop;
--End substitution loop
if (nr_of_reads = 0) then
state <= Write_Outputs;
nr_of_writes <= NUMBER_OF_OUTPUT_WORDS - 1;
else
nr_of_reads <= nr_of_reads - 1;
end if;
end if;
when Write_Outputs =>
if (M_AXIS_TREADY = '1') then
if (nr_of_writes = 0) then
state <= Idle;
else
nr_of_writes <= nr_of_writes - 1;
data <= std_logic_vector(shift_left(unsigned(data), 32)); --Shift data 32-bits to the left
end if;
end if;
end case;
end if;
end if;
end process The_SW_accelerator;
end architecture EXAMPLE;
|
gpl-2.0
|
9573b28eb1c181d62d9092f4c6277f6f
| 0.465241 | 4.374605 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/increment.vhd
| 4 | 1,647 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity increment is
end entity increment;
architecture test of increment is
subtype word32 is bit_vector(31 downto 0);
-- code from book
procedure increment ( a : inout word32; by : in word32 := X"0000_0001" ) is
variable sum : word32;
variable carry : bit := '0';
begin
for index in a'reverse_range loop
sum(index) := a(index) xor by(index) xor carry;
carry := ( a(index) and by(index) ) or ( carry and ( a(index) xor by(index) ) );
end loop;
a := sum;
end procedure increment;
-- end code from book
begin
stimulus : process is
variable count : word32 := X"0001_1100";
begin
-- code from book (in text)
increment(count, X"0000_0004");
increment(count);
increment(count, by => open);
-- end code from book
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
4035571cb9b1ee188d986b1588cbd560
| 0.685489 | 3.940191 | false | false | false | false |
123gmax/Digital-Lab
|
Lab1/Ganesh/FCS/fcs_v4.vhd
| 1 | 4,531 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fc_system_v4 is
port(
flight_no : in std_logic_vector(2 downto 0);
request: in std_logic;
reset,clk : in std_logic;
clk3_out,clk10_out : out std_logic;--For demo only
grant,denied: out std_logic
);
end fc_system_v4;
architecture beh of fc_system_v4 is
type state_type is (IDLE,WBReq,WBGrant,WBOnly,Deny,Deny_t,NBReq,NBGrant);
signal state_reg,state_next:state_type;
signal clk3_count,clk10_count : unsigned(26 downto 0);
signal pulse3_1sec,pulse10_1sec: std_logic;
signal clk10_reg,clk10_next:unsigned(3 downto 0);
signal clk3_reg,clk3_next:unsigned(1 downto 0);
signal load10_clk,load3_clk:std_logic;
signal clk3_out_reg,clk3_out_next,clk10_out_reg,clk10_out_next:std_logic;--Demo only
signal reset3,reset10:std_logic;
begin
process(clk,reset)
begin
if(reset ='1') then
state_reg<=IDLE;
elsif (clk' event and clk ='1') then
state_reg<=state_next;
end if;
end process;
--Clock process
process(clk,reset3)
begin
if(reset3 ='1') then
clk3_count <= (others => '0');
elsif (clk' event and clk ='1') then
clk3_count <= clk3_count + 1;
end if;
end process;
process(clk,reset10)
begin
if(reset10 ='1') then
clk10_count <= (others => '0');
elsif (clk' event and clk ='1') then
clk10_count <= clk10_count + 1;
end if;
end process;
process(pulse10_1sec,load10_clk)
begin
if(load10_clk ='1') then
clk10_reg<="1010";
clk10_out_reg<='1';
elsif(pulse10_1sec' event and pulse10_1sec ='1') then
clk10_reg <= clk10_next;
clk10_out_reg <= clk10_out_next;--Demo only
end if;
end process;
process(pulse3_1sec,load3_clk)
begin
if(load3_clk ='1') then
clk3_reg<="11";
clk3_out_reg<='1';
elsif(pulse3_1sec' event and pulse3_1sec ='1') then
clk3_reg <= clk3_next;
clk3_out_reg <= clk3_out_next;--Demo only
end if;
end process;
pulse3_1sec <= clk3_count(26);
pulse10_1sec <= clk10_count(26);
reset3 <= load3_clk or reset;
reset10 <= load10_clk or reset;
clk3_out_next <= not clk3_out_reg;
clk10_out_next <= not clk10_out_reg;
clk3_out<=clk3_out_reg;
clk10_out<=clk10_out_reg;
clk10_next <= (others =>'0') when (clk10_reg = "0000") else
(clk10_reg - 1);
clk3_next <= (others => '0') when (clk3_reg ="00" ) else
(clk3_reg - 1);
--Next state logic and output logic
process(state_reg,request,clk10_reg,clk3_reg)
begin
grant <= '0';
denied <='0';
load10_clk <='0';
load3_clk <='0';
case state_reg is
when IDLE =>
if(request ='1') then
if(flight_no="001" or flight_no="011" or flight_no ="111") then
state_next <= WBReq;
else
state_next <= NBReq;
end if;
else
state_next <= IDLE;
end if;
when WBReq=>
load10_clk<='1';
state_next <= WBGrant;
when WBGrant =>
if(clk10_reg = "0111") then --3Sec elapsed
state_next <= WBOnly;
else
state_next <= WBGrant;
end if;
grant <= '1';
when WBOnly =>
if(request = '1') then
if(flight_no="001" or flight_no="011" or flight_no ="111") then
state_next <= WBReq;
else
state_next <= Deny_t;
end if;
elsif(clk10_reg="0000") then
state_next <= IDLE;
else
state_next <= WBOnly;
end if;
when Deny_t =>
load3_clk <='1';
state_next <= Deny;
when Deny =>
if(clk3_reg = "00") then
state_next<=WBOnly;
else
state_next <= Deny;
end if;
denied <='1';
when NBReq =>
load3_clk <='1';
--load10_clk <='1'; --Demo purposr only
state_next <= NBGrant;
when NBGrant =>
if(clk3_reg ="00") then
state_next <= IDLE;
else
state_next <= NBGrant;
end if;
grant <= '1';
end case;
end process;
end beh;
|
gpl-2.0
|
185cbde30e1cd7d5e7f1f52a48cdf56d
| 0.511366 | 3.411898 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_20.vhd
| 4 | 2,156 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_20.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package pk_05_20 is
-- code from book:
type FIFO_status is record
nearly_full, nearly_empty, full, empty : bit;
end record FIFO_status;
-- end of code from book
end package pk_05_20;
----------------------------------------------------------------
use work.pk_05_20.all;
entity FIFO is
port ( status : out FIFO_status;
other_ports : out bit );
end entity FIFO;
----------------------------------------------------------------
entity ch_05_20 is
end entity ch_05_20;
----------------------------------------------------------------
use work.pk_05_20.all;
architecture test of ch_05_20 is
signal start_flush, end_flush, DMA_buffer_full, DMA_buffer_empty : bit;
begin
-- code from book:
DMA_buffer : entity work.FIFO
port map ( -- . . .,
status.nearly_full => start_flush,
status.nearly_empty => end_flush,
status.full => DMA_buffer_full,
status.empty => DMA_buffer_empty, -- . . . );
-- not in book
other_ports => open );
-- end not in book
-- end of code from book
end architecture test;
|
gpl-2.0
|
f7db05a2a8ceeaca5868c0fcfaa76173
| 0.554267 | 4.114504 | false | false | false | false |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/plasma/mem_ctrl.vhd
| 2 | 6,646 |
---------------------------------------------------------------------
-- TITLE: Memory Controller
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 1/31/01
-- FILENAME: mem_ctrl.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Memory controller for the Plasma CPU.
-- Supports Big or Little Endian mode.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity mem_ctrl is
port(clk : in std_logic;
reset_in : in std_logic;
pause_in : in std_logic;
nullify_op : in std_logic;
address_pc : in std_logic_vector(31 downto 2);
opcode_out : out std_logic_vector(31 downto 0);
opcode_test : out std_logic_vector(31 downto 0);
address_in : in std_logic_vector(31 downto 0);
mem_source : in mem_source_type;
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
pause_out : out std_logic;
address_next : out std_logic_vector(31 downto 2);
byte_we_next : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0));
end; --entity mem_ctrl
architecture logic of mem_ctrl is
--"00" = big_endian; "11" = little_endian
constant ENDIAN_MODE : std_logic_vector(1 downto 0) := "00";
signal opcode_reg : std_logic_vector(31 downto 0);
signal next_opcode_reg : std_logic_vector(31 downto 0);
signal address_reg : std_logic_vector(31 downto 2);
signal byte_we_reg : std_logic_vector(3 downto 0);
signal mem_state_reg : std_logic;
constant STATE_ADDR : std_logic := '0';
constant STATE_ACCESS : std_logic := '1';
begin
mem_proc: process(clk, reset_in, pause_in, nullify_op,
address_pc, address_in, mem_source, data_write,
data_r, opcode_reg, next_opcode_reg, mem_state_reg,
address_reg, byte_we_reg)
variable address_var : std_logic_vector(31 downto 2);
variable data_read_var : std_logic_vector(31 downto 0);
variable data_write_var : std_logic_vector(31 downto 0);
variable opcode_next : std_logic_vector(31 downto 0);
variable byte_we_var : std_logic_vector(3 downto 0);
variable mem_state_next : std_logic;
variable pause_var : std_logic;
variable bits : std_logic_vector(1 downto 0);
begin
byte_we_var := "0000";
pause_var := '0';
data_read_var := ZERO;
data_write_var := ZERO;
mem_state_next := mem_state_reg;
opcode_next := opcode_reg;
case mem_source is
when MEM_READ32 =>
data_read_var := data_r;
when MEM_READ16 | MEM_READ16S =>
if address_in(1) = ENDIAN_MODE(1) then
data_read_var(15 downto 0) := data_r(31 downto 16);
else
data_read_var(15 downto 0) := data_r(15 downto 0);
end if;
if mem_source = MEM_READ16 or data_read_var(15) = '0' then
data_read_var(31 downto 16) := ZERO(31 downto 16);
else
data_read_var(31 downto 16) := ONES(31 downto 16);
end if;
when MEM_READ8 | MEM_READ8S =>
bits := address_in(1 downto 0) xor ENDIAN_MODE;
case bits is
when "00" => data_read_var(7 downto 0) := data_r(31 downto 24);
when "01" => data_read_var(7 downto 0) := data_r(23 downto 16);
when "10" => data_read_var(7 downto 0) := data_r(15 downto 8);
when others => data_read_var(7 downto 0) := data_r(7 downto 0);
end case;
if mem_source = MEM_READ8 or data_read_var(7) = '0' then
data_read_var(31 downto 8) := ZERO(31 downto 8);
else
data_read_var(31 downto 8) := ONES(31 downto 8);
end if;
when MEM_WRITE32 =>
data_write_var := data_write;
byte_we_var := "1111";
when MEM_WRITE16 =>
data_write_var := data_write(15 downto 0) & data_write(15 downto 0);
if address_in(1) = ENDIAN_MODE(1) then
byte_we_var := "1100";
else
byte_we_var := "0011";
end if;
when MEM_WRITE8 =>
data_write_var := data_write(7 downto 0) & data_write(7 downto 0) &
data_write(7 downto 0) & data_write(7 downto 0);
bits := address_in(1 downto 0) xor ENDIAN_MODE;
case bits is
when "00" =>
byte_we_var := "1000";
when "01" =>
byte_we_var := "0100";
when "10" =>
byte_we_var := "0010";
when others =>
byte_we_var := "0001";
end case;
when others =>
end case;
if mem_source = MEM_FETCH then --opcode fetch
address_var := address_pc;
opcode_next := data_r;
mem_state_next := STATE_ADDR;
else
if mem_state_reg = STATE_ADDR then
if pause_in = '0' then
address_var := address_in(31 downto 2);
mem_state_next := STATE_ACCESS;
pause_var := '1';
else
address_var := address_pc;
byte_we_var := "0000";
end if;
else --STATE_ACCESS
if pause_in = '0' then
address_var := address_pc;
opcode_next := next_opcode_reg;
mem_state_next := STATE_ADDR;
byte_we_var := "0000";
else
address_var := address_in(31 downto 2);
byte_we_var := "0000";
end if;
end if;
end if;
if nullify_op = '1' and pause_in = '0' then
opcode_next := ZERO; --NOP after beql
end if;
if reset_in = '1' then
mem_state_reg <= STATE_ADDR;
opcode_reg <= ZERO;
next_opcode_reg <= ZERO;
address_reg <= ZERO(31 downto 2);
byte_we_reg <= "0000";
elsif rising_edge(clk) then
if pause_in = '0' then
address_reg <= address_var;
byte_we_reg <= byte_we_var;
mem_state_reg <= mem_state_next;
opcode_reg <= opcode_next;
if mem_state_reg = STATE_ADDR then
next_opcode_reg <= data_r;
end if;
end if;
end if;
opcode_out <= opcode_reg;
opcode_test <= opcode_reg;
data_read <= data_read_var;
pause_out <= pause_var;
address_next <= address_var;
byte_we_next <= byte_we_var;
address <= address_reg;
byte_we <= byte_we_reg;
data_w <= data_write_var;
end process; --data_proc
end; --architecture logic
|
mit
|
b25f088251ff3465760353f92771a60b
| 0.559886 | 3.389087 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_divider/MAIA/inverter_maia_233.vhd
| 1 | 9,681 |
----------------------------------------------------------------------------------------------------
-- inverter_maia_2.vhd ---
----------------------------------------------------------------------------------------------------
-- Inverter for F_2^m
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Coments: This is an implementation of the Modified Almost Inverse Algorithm.
-- Diferent to the first implementation, here the test g(U) < g(V) is
-- performed directly by a m+1 bit comparer.
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
--------------------------------------------------------
entity inverter_maia_233 is
generic(
NUM_BITS : positive := 233 -- The order of the finite field
);
port(
ax : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0); -- input polynomial of grade m-1
clk : in STD_LOGIC;
rst : in STD_LOGIC;
done : out STD_LOGIC;
z : out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0)
);
end ;
---------------------------------------------------------
architecture behave of inverter_maia_233 is
---------------------------------------------------------
signal B,C,U,V : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal processing registers, one bit more
signal Bx_Op1 : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Multiplexer which depends on if B is ever or odd
signal Ux_div_x : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- U and B divided by x
signal Bx_div_x : STD_LOGIC_VECTOR(NUM_BITS downto 0);
--163
--constant UNO : STD_LOGIC_VECTOR(NUM_BITS downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
--233
constant UNO : STD_LOGIC_VECTOR(NUM_BITS downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
--277
-- constant UNO : STD_LOGIC_VECTOR(NUM_BITS downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
--283
-- constant UNO : STD_LOGIC_VECTOR(NUM_BITS downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
--409
-- constant UNO : STD_LOGIC_VECTOR(NUM_BITS downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
--571
-- constant UNO : STD_LOGIC_VECTOR(NUM_BITS downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
--
-- m = 163 x163 + x7 + x6 + x3 + 1
--constant Fx: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001001";
-- m = 233 x233 + x74 + 1
constant Fx: std_logic_vector(NUM_BITS downto 0) := "100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000001";
-- m = 277 x277 + x74 + 1
--constant Fx: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000001001001"; --277 bits
-- m = 283 x283 + x12 + x7 + x5 + 1
--constant Fx: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000010100001";
-- m = 409 x409 + x87 + 1
--constant Fx: std_logic_vector(NUM_BITS1 downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
-- m = 571 x571 + x10 + x5 + x2 + 1
--constant Fx: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000100101";
----------------------------------------------------------------------------------
-- States fot the FSM controlling the execution of the algorithm
----------------------------------------------------------------------------------
type CurrentState_type is (END_STATE, LOOP_U0, NEXT_STEP);
signal State: CurrentState_type;
----------------------------------------------------------------------------------
begin
------------------------------------------------------
Ux_div_x <= '0' & U(NUM_BITS downto 1); -- Dividing U and B by x
Bx_div_x <= '0' & Bx_Op1(NUM_BITS downto 1);
------------------------------------------------------
Bx_Op1 <= B xor Fx when B(0) = '1' else -- Multiplexer for operand B
B;
-------------------------------------------------------
-- The Modified ALmost Inverse Algorithm implementation
-------------------------------------------------------
EEAL: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if (rst = '1')then -- initialize internal registers
State <= LOOP_U0;
B <= UNO;
U <= '0'&Ax;
V <= Fx;
C <= (others => '0');
z <= (others => '0'); -- set to zero the output register
Done <= '0';
else
case State is
-----------------------------------------------------------------------------------
when LOOP_U0 => -- Stay here while U be even
if U(0) = '1' then
if U = UNO then -- The algorithm finishes when U = 1
Z <= B(NUM_BITS-1 downto 0);
Done <= '1';
State <= END_STATE;
else
if U < V then -- Interchange the registers U <-> V and B <-> C
U <= V;
V <= U;
B <= C;
C <= B;
end if;
State <= NEXT_STEP;
end if;
else -- Divide U and B and repeat the process
U <= Ux_div_x;
B <= Bx_div_x;
end if;
-----------------------------------------------------------------------------------
when NEXT_STEP => -- update U and B with the values previously assigned
U <= U xor V;
B <= B xor C;
State <= LOOP_U0;
-----------------------------------------------------------------------------------
when END_STATE => -- Do nothing
State <= END_STATE;
-----------------------------------------------------------------------------------
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
08776998547dd33668cfb3a09fc0bc56
| 0.640946 | 6.736952 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_15.vhd
| 4 | 2,213 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_16_fg_16_15.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity circuit is
generic ( inpad_delay, outpad_delay : delay_length );
port ( in1, in2, in3 : in bit; out1, out2 : out bit );
end entity circuit;
--------------------------------------------------
architecture with_pad_delays of circuit is
component subcircuit is
port ( a, b : in bit; y1, y2 : out bit );
end component subcircuit;
signal delayed_in1, delayed_in2, delayed_in3 : bit;
signal undelayed_out1, undelayed_out2 : bit;
begin
input_delays : block is
begin
delayed_in1 <= in1 after inpad_delay;
delayed_in2 <= in2 after inpad_delay;
delayed_in3 <= in3 after inpad_delay;
end block input_delays;
functionality : block is
signal intermediate : bit;
begin
cell1 : component subcircuit
port map ( delayed_in1, delayed_in2, undelayed_out1, intermediate );
cell2 : component subcircuit
port map ( intermediate, delayed_in3, undelayed_out2, open );
end block functionality;
output_delays : block is
begin
out1 <= undelayed_out1 after outpad_delay;
out2 <= undelayed_out2 after outpad_delay;
end block output_delays;
end architecture with_pad_delays;
|
gpl-2.0
|
4ffca9e650b076aeaee92862fb2b8aec
| 0.63127 | 4.068015 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1960.vhd
| 4 | 1,771 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1960.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p02n02i01960ent IS
END c07s02b01x00p02n02i01960ent;
ARCHITECTURE c07s02b01x00p02n02i01960arch OF c07s02b01x00p02n02i01960ent IS
BEGIN
TESTING: PROCESS
variable a : boolean := TRUE;
variable b : boolean := TRUE;
variable c : boolean;
BEGIN
c := a xor b;
assert NOT(c=FALSE)
report "***PASSED TEST: c07s02b01x00p02n02i01960"
severity NOTE;
assert ( c=FALSE )
report "***FAILED TEST: c07s02b01x00p02n02i01960 - Logical operation of 'XOR'."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p02n02i01960arch;
|
gpl-2.0
|
7f26fa82e6fbb9c7f76fbf79b0b18fa7
| 0.664596 | 3.674274 | false | true | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_Squarer/squarer_131.vhd
| 1 | 6,857 |
-- Author : Miguel Morales-Sandoval
-- Project : "Reconfigurable ECC
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2007.
--Squarer, solo logica combinacional,
--optimizado para el polinomio de reduccion que se este empleando,
-- funciona solo si el máximo grado del polinomio de reduccion D más 2 es menor a m.
-- Se trata básicamente de un multiplicador de digito combinacional. El tamaño del digito es D+2;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
-----------------------------------------------------------------------------------
entity squarer_131 is
generic(
NUM_BITS : positive := 131 --113 163, 233, 277, 283, 409, 571 -- Orden del campo finito
);
port(
-- clk : in std_logic;
-- en : in std_logic;
A_x : in std_logic_vector(NUM_BITS-1 downto 0);-- 2
A2_x : out std_logic_vector(NUM_BITS-1 downto 0)-- A2_x = (A_x) mod Fx
);
end;
---------------------------------------------------------------------------------------------------
architecture behave of squarer_131 is
begin
A2_x(130) <= A_x(65) xor A_x(129);
A2_x(129) <= A_x(130) xor A_x(129) xor A_x(126);
A2_x(128) <= A_x(64) xor A_x(128);
A2_x(127) <= A_x(129) xor A_x(128) xor A_x(125);
A2_x(126) <= A_x(63) xor A_x(127);
A2_x(125) <= A_x(128) xor A_x(127) xor A_x(124);
A2_x(124) <= A_x(62) xor A_x(126);
A2_x(123) <= A_x(127) xor A_x(126) xor A_x(123);
A2_x(122) <= A_x(61) xor A_x(125);
A2_x(121) <= A_x(126) xor A_x(125) xor A_x(122);
A2_x(120) <= A_x(60) xor A_x(124);
A2_x(119) <= A_x(125) xor A_x(124) xor A_x(121);
A2_x(118) <= A_x(59) xor A_x(123);
A2_x(117) <= A_x(124) xor A_x(123) xor A_x(120);
A2_x(116) <= A_x(58) xor A_x(122);
A2_x(115) <= A_x(123) xor A_x(122) xor A_x(119);
A2_x(114) <= A_x(57) xor A_x(121);
A2_x(113) <= A_x(122) xor A_x(121) xor A_x(118);
A2_x(112) <= A_x(56) xor A_x(120);
A2_x(111) <= A_x(121) xor A_x(120) xor A_x(117);
A2_x(110) <= A_x(55) xor A_x(119);
A2_x(109) <= A_x(120) xor A_x(119) xor A_x(116);
A2_x(108) <= A_x(54) xor A_x(118);
A2_x(107) <= A_x(119) xor A_x(118) xor A_x(115);
A2_x(106) <= A_x(53) xor A_x(117);
A2_x(105) <= A_x(118) xor A_x(117) xor A_x(114);
A2_x(104) <= A_x(52) xor A_x(116);
A2_x(103) <= A_x(117) xor A_x(116) xor A_x(113);
A2_x(102) <= A_x(51) xor A_x(115);
A2_x(101) <= A_x(116) xor A_x(115) xor A_x(112);
A2_x(100) <= A_x(50) xor A_x(114);
A2_x(99) <= A_x(115) xor A_x(114) xor A_x(111);
A2_x(98) <= A_x(49) xor A_x(113);
A2_x(97) <= A_x(114) xor A_x(113) xor A_x(110);
A2_x(96) <= A_x(48) xor A_x(112);
A2_x(95) <= A_x(113) xor A_x(112) xor A_x(109);
A2_x(94) <= A_x(47) xor A_x(111);
A2_x(93) <= A_x(112) xor A_x(111) xor A_x(108);
A2_x(92) <= A_x(46) xor A_x(110);
A2_x(91) <= A_x(111) xor A_x(110) xor A_x(107);
A2_x(90) <= A_x(45) xor A_x(109);
A2_x(89) <= A_x(110) xor A_x(109) xor A_x(106);
A2_x(88) <= A_x(44) xor A_x(108);
A2_x(87) <= A_x(109) xor A_x(108) xor A_x(105);
A2_x(86) <= A_x(43) xor A_x(107);
A2_x(85) <= A_x(108) xor A_x(107) xor A_x(104);
A2_x(84) <= A_x(42) xor A_x(106);
A2_x(83) <= A_x(107) xor A_x(106) xor A_x(103);
A2_x(82) <= A_x(41) xor A_x(105);
A2_x(81) <= A_x(106) xor A_x(105) xor A_x(102);
A2_x(80) <= A_x(40) xor A_x(104);
A2_x(79) <= A_x(105) xor A_x(104) xor A_x(101);
A2_x(78) <= A_x(39) xor A_x(103);
A2_x(77) <= A_x(104) xor A_x(103) xor A_x(100);
A2_x(76) <= A_x(38) xor A_x(102);
A2_x(75) <= A_x(103) xor A_x(102) xor A_x(99);
A2_x(74) <= A_x(37) xor A_x(101);
A2_x(73) <= A_x(102) xor A_x(101) xor A_x(98);
A2_x(72) <= A_x(36) xor A_x(100);
A2_x(71) <= A_x(101) xor A_x(100) xor A_x(97);
A2_x(70) <= A_x(35) xor A_x(99);
A2_x(69) <= A_x(100) xor A_x(99) xor A_x(96);
A2_x(68) <= A_x(34) xor A_x(98);
A2_x(67) <= A_x(99) xor A_x(98) xor A_x(95);
A2_x(66) <= A_x(33) xor A_x(97);
A2_x(65) <= A_x(98) xor A_x(97) xor A_x(94);
A2_x(64) <= A_x(32) xor A_x(96);
A2_x(63) <= A_x(97) xor A_x(96) xor A_x(93);
A2_x(62) <= A_x(31) xor A_x(95);
A2_x(61) <= A_x(96) xor A_x(95) xor A_x(92);
A2_x(60) <= A_x(30) xor A_x(94);
A2_x(59) <= A_x(95) xor A_x(94) xor A_x(91);
A2_x(58) <= A_x(29) xor A_x(93);
A2_x(57) <= A_x(94) xor A_x(93) xor A_x(90);
A2_x(56) <= A_x(28) xor A_x(92);
A2_x(55) <= A_x(93) xor A_x(92) xor A_x(89);
A2_x(54) <= A_x(27) xor A_x(91);
A2_x(53) <= A_x(92) xor A_x(91) xor A_x(88);
A2_x(52) <= A_x(26) xor A_x(90);
A2_x(51) <= A_x(91) xor A_x(90) xor A_x(87);
A2_x(50) <= A_x(25) xor A_x(89);
A2_x(49) <= A_x(90) xor A_x(89) xor A_x(86);
A2_x(48) <= A_x(24) xor A_x(88);
A2_x(47) <= A_x(89) xor A_x(88) xor A_x(85);
A2_x(46) <= A_x(23) xor A_x(87);
A2_x(45) <= A_x(88) xor A_x(87) xor A_x(84);
A2_x(44) <= A_x(22) xor A_x(86);
A2_x(43) <= A_x(87) xor A_x(86) xor A_x(83);
A2_x(42) <= A_x(21) xor A_x(85);
A2_x(41) <= A_x(86) xor A_x(85) xor A_x(82);
A2_x(40) <= A_x(20) xor A_x(84);
A2_x(39) <= A_x(85) xor A_x(84) xor A_x(81);
A2_x(38) <= A_x(19) xor A_x(83);
A2_x(37) <= A_x(84) xor A_x(83) xor A_x(80);
A2_x(36) <= A_x(18) xor A_x(82);
A2_x(35) <= A_x(83) xor A_x(82) xor A_x(79);
A2_x(34) <= A_x(17) xor A_x(81);
A2_x(33) <= A_x(82) xor A_x(81) xor A_x(78);
A2_x(32) <= A_x(16) xor A_x(80);
A2_x(31) <= A_x(81) xor A_x(80) xor A_x(77);
A2_x(30) <= A_x(15) xor A_x(79);
A2_x(29) <= A_x(80) xor A_x(79) xor A_x(76);
A2_x(28) <= A_x(14) xor A_x(78);
A2_x(27) <= A_x(79) xor A_x(78) xor A_x(75);
A2_x(26) <= A_x(13) xor A_x(77);
A2_x(25) <= A_x(78) xor A_x(77) xor A_x(74);
A2_x(24) <= A_x(12) xor A_x(76);
A2_x(23) <= A_x(77) xor A_x(76) xor A_x(73);
A2_x(22) <= A_x(11) xor A_x(75);
A2_x(21) <= A_x(76) xor A_x(75) xor A_x(72);
A2_x(20) <= A_x(10) xor A_x(74);
A2_x(19) <= A_x(75) xor A_x(74) xor A_x(71);
A2_x(18) <= A_x(9) xor A_x(73);
A2_x(17) <= A_x(74) xor A_x(73) xor A_x(70);
A2_x(16) <= A_x(8) xor A_x(72);
A2_x(15) <= A_x(73) xor A_x(72) xor A_x(69);
A2_x(14) <= A_x(7) xor A_x(71) xor A_x(130);
A2_x(13) <= A_x(72) xor A_x(71) xor A_x(68);
A2_x(12) <= A_x(6) xor A_x(70) xor A_x(129);
A2_x(11) <= A_x(71) xor A_x(70) xor A_x(67);
A2_x(10) <= A_x(5) xor A_x(69) xor A_x(128);
A2_x(9) <= A_x(70) xor A_x(69) xor A_x(66);
A2_x(8) <= A_x(4) xor A_x(68) xor A_x(127);
A2_x(7) <= A_x(69) xor A_x(68) xor A_x(129);
A2_x(6) <= A_x(3) xor A_x(67) xor A_x(130) xor A_x(129);
A2_x(5) <= A_x(68) xor A_x(67) xor A_x(128);
A2_x(4) <= A_x(2) xor A_x(66) xor A_x(130) xor A_x(129) xor A_x(128);
A2_x(3) <= A_x(67) xor A_x(66) xor A_x(127);
A2_x(2) <= A_x(1) xor A_x(130) xor A_x(128) xor A_x(127);
A2_x(1) <= A_x(66) xor A_x(130);
A2_x(0) <= A_x(0) xor A_x(130) xor A_x(127) ;
end behave;
|
gpl-3.0
|
881cfb970c89942341f8c5fd8350260f
| 0.499781 | 1.765903 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc527.vhd
| 4 | 4,172 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc527.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p03n04i00527ent IS
END c03s03b00x00p03n04i00527ent;
ARCHITECTURE c03s03b00x00p03n04i00527arch OF c03s03b00x00p03n04i00527ent IS
BEGIN
TESTING : PROCESS
-- first index constraint method
type bv_ptr is access bit_vector(0 to 7);
variable v_bv_ptr1: bv_ptr := new bit_vector'("00000001");
variable v_bv_ptr2: bv_ptr;
variable v_bv_ptr3: bv_ptr := v_bv_ptr1;
-- second index constraint method
subtype tbus is bit_vector(1 to 8);
type bus_ptr is access tbus;
variable v_bv_ptr4: bus_ptr := new tbus'("10000000");
-- third index constraint method
type bus_ptr2 is access bit_vector;
variable v_bv_ptr5: bus_ptr2 := new bit_vector'("1111");
variable v_bv_ptr6: bus_ptr2 := new bit_vector(1 to 4);
variable OKtest : integer := 0;
BEGIN
assert v_bv_ptr1.all = "00000001";
if (v_bv_ptr1.all = "00000001") then
OKtest := Oktest + 1;
end if;
assert v_bv_ptr2 = null;
if (v_bv_ptr2 = null) then
OKtest := Oktest + 1;
end if;
assert v_bv_ptr3.all = "00000001";
if (v_bv_ptr3.all = "00000001") then
OKtest := Oktest + 1;
end if;
assert v_bv_ptr4.all = "10000000";
if (v_bv_ptr4.all = "10000000") then
OKtest := Oktest + 1;
end if;
assert v_bv_ptr5.all = "1111";
if (v_bv_ptr5.all = "1111") then
OKtest := Oktest + 1;
end if;
assert v_bv_ptr6.all = "0000";
if (v_bv_ptr6.all = "0000") then
OKtest := Oktest + 1;
end if;
v_bv_ptr2 := new bit_vector'("00110011");
assert v_bv_ptr2.all = "00110011";
if (v_bv_ptr6.all = "0000") then
OKtest := Oktest + 1;
end if;
assert (v_bv_ptr1.all & v_bv_ptr3.all) = "0000000100000001";
if ((v_bv_ptr1.all & v_bv_ptr3.all) = "0000000100000001") then
OKtest := Oktest + 1;
end if;
assert (v_bv_ptr1.all & v_bv_ptr2.all) = "0000000100110011";
if ((v_bv_ptr1.all & v_bv_ptr2.all) = "0000000100110011") then
OKtest := Oktest + 1;
end if;
assert (v_bv_ptr5.all & v_bv_ptr6.all) = "11110000";
if ((v_bv_ptr5.all & v_bv_ptr6.all) = "11110000") then
OKtest := Oktest + 1;
end if;
assert (v_bv_ptr5.all & v_bv_ptr1.all) = "111100000001";
if ((v_bv_ptr5.all & v_bv_ptr1.all) = "111100000001") then
OKtest := Oktest + 1;
end if;
assert (v_bv_ptr6.all /= v_bv_ptr5.all) = true;
if ((v_bv_ptr6.all /= v_bv_ptr5.all) = true) then
OKtest := Oktest + 1;
end if;
deallocate(v_bv_ptr1);
deallocate(v_bv_ptr2);
deallocate(v_bv_ptr4);
deallocate(v_bv_ptr5);
deallocate(v_bv_ptr6);
assert NOT(OKtest = 12)
report "***PASSED TEST: c03s03b00x00p03n04i00527"
severity NOTE;
assert (OKtest = 12)
report "***FAILED TEST: c03s03b00x00p03n04i00527 - Bit Vector type using as base for access type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p03n04i00527arch;
|
gpl-2.0
|
3919cade78577604e9092d72f4e67b56
| 0.611697 | 3.196935 | false | true | false | false |
jakubcabal/pipemania-fpga-game
|
source/comp/game/game_ctrl.vhd
| 1 | 8,261 |
--------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: GAME_CTRL
-- AUTHORS: Tomáš Bannert <[email protected]>
-- Jakub Cabal <[email protected]>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/pipemania-fpga-game
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity GAME_CTRL is
Port (
CLK : in std_logic; -- clock
RST : in std_logic; -- reset
WIN : in std_logic; -- vyhra
LOSE : in std_logic; -- prohra
KEY_W : in std_logic; -- klavesa W
KEY_S : in std_logic; -- klavesa S
KEY_A : in std_logic; -- klavesa A
KEY_D : in std_logic; -- klavesa D
GEN5_EN : out std_logic; -- vygenerovani pocatecnich komponent
SCREEN_CODE : out std_logic_vector(2 downto 0); -- game screen code
GAME_ON : out std_logic; -- in game or in screen
WATER : out std_logic_vector(7 downto 0) -- voda co tece v nadrzi pred zacatkem hry
);
end GAME_CTRL;
architecture Behavioral of GAME_CTRL is
-- Debug mode for skiping levels
constant DEBUG : boolean := False;
type state is (level1_sc, level1, level2_sc, level2, level3_sc, level3, level4_sc, level4, win_sc, lose_sc);
signal present_st : state;
signal next_st : state;
signal water_speed_counter : unsigned(24 downto 0);
signal water_in_progress : unsigned(7 downto 0);
signal game_en : std_logic;
signal next_part_of_water : std_logic;
begin
-- Pametova cast stavoveho automatu
process (CLK, RST)
begin
if (RST = '1') then
present_st <= level1_sc;
elsif (rising_edge(CLK)) then
present_st <= next_st;
end if;
end process;
-- Rozhodovaci cast stavoveho automatu
process (present_st, KEY_W, KEY_S, KEY_A, KEY_D, WIN, LOSE)
begin
case present_st is
when level1_sc => --uvodni obrazovka
if (KEY_S = '1') then
next_st <= level1;
elsif (KEY_A = '1' and DEBUG = True) then
next_st <= level2_sc;
elsif (KEY_W = '1' and DEBUG = True) then
next_st <= level3_sc;
elsif (KEY_D = '1' and DEBUG = True) then
next_st <= level4_sc;
else
next_st <= level1_sc;
end if;
when level1 => --level 1
if (WIN = '1') then
next_st <= level2_sc;
elsif (LOSE = '1') then
next_st <= lose_sc;
else
next_st <= level1;
end if;
when level2_sc => --level 2 obrazovka
if (KEY_S = '1') then
next_st <= level2;
else
next_st <= level2_sc;
end if;
when level2 => --level 2
if (WIN = '1') then
next_st <= level3_sc;
elsif (LOSE = '1') then
next_st <= lose_sc;
else
next_st <= level2;
end if;
when level3_sc => --level 3 obrazovka
if (KEY_S = '1') then
next_st <= level3;
else
next_st <= level3_sc;
end if;
when level3 => --level 3
if (WIN = '1') then
next_st <= level4_sc;
elsif (LOSE = '1') then
next_st <= lose_sc;
else
next_st <= level3;
end if;
when level4_sc => --level 4 obrazovka
if (KEY_S = '1') then
next_st <= level4;
else
next_st <= level4_sc;
end if;
when level4 => --level 4
if (WIN = '1') then
next_st <= win_sc;
elsif (LOSE = '1') then
next_st <= lose_sc;
else
next_st <= level4;
end if;
when win_sc => --win
if (KEY_S = '1') then
next_st <= level1_sc;
else
next_st <= win_sc;
end if;
when lose_sc => --lose
if (KEY_S = '1') then
next_st <= level1_sc;
else
next_st <= lose_sc;
end if;
when others =>
next_st <= level1_sc;
end case;
end process;
-- Vystupni cast stavoveho automatu
process (present_st)
begin
case present_st is
when level1_sc => -- start screen
GEN5_EN <= '1';
SCREEN_CODE <= "000";
game_en <= '0';
when level1 => -- lvl 1
GEN5_EN <= '0';
SCREEN_CODE <= "001";
game_en <= '1';
when level2_sc => -- lvl 2 screen
GEN5_EN <= '1';
SCREEN_CODE <= "100";
game_en <= '0';
when level2 => -- lvl 2
GEN5_EN <= '0';
SCREEN_CODE <= "001";
game_en <= '1';
when level3_sc => -- lvl 3 screen
GEN5_EN <= '1';
SCREEN_CODE <= "101";
game_en <= '0';
when level3 => -- lvl 3
GEN5_EN <= '0';
SCREEN_CODE <= "001";
game_en <= '1';
when level4_sc => -- lvl 4 screen
GEN5_EN <= '1';
SCREEN_CODE <= "110";
game_en <= '0';
when level4 => -- lvl 4
GEN5_EN <= '0';
SCREEN_CODE <= "001";
game_en <= '1';
when win_sc => -- win screen
GEN5_EN <= '0';
SCREEN_CODE <= "010";
game_en <= '0';
when lose_sc => -- game over screen
GEN5_EN <= '0';
SCREEN_CODE <= "011";
game_en <= '0';
when others =>
GEN5_EN <= '0';
SCREEN_CODE <= "000";
game_en <= '0';
end case;
end process;
process (CLK, RST)
begin
if (RST = '1') then
water_speed_counter <= (others=>'0');
next_part_of_water <= '0';
elsif (rising_edge(CLK)) then
if (game_en = '1') then
if (water_speed_counter < 10000000) then -- uprav, pokud chces jinou rychlost. max 1048575
water_speed_counter <= water_speed_counter + 1;
next_part_of_water <= '0';
else
water_speed_counter <= (others=>'0');
next_part_of_water <= '1';
end if;
else
water_speed_counter <= (others=>'0');
next_part_of_water <= '0';
end if;
end if;
end process;
process (CLK, RST)
begin
if (RST = '1') then
water_in_progress <= (others=>'0');
elsif (rising_edge(CLK)) then
if (game_en = '1') then
if (next_part_of_water = '1') then
if (water_in_progress < 255) then
water_in_progress <= water_in_progress + 1;
else
water_in_progress <= to_unsigned(255,8);
end if;
end if;
else
water_in_progress <= (others=>'0');
end if;
end if;
end process;
WATER <= std_logic_vector(water_in_progress);
GAME_ON <= game_en;
end Behavioral;
|
mit
|
8cc7504e38ed780ba10d78b64298d68e
| 0.402107 | 4.070478 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_16.vhd
| 4 | 2,008 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_16.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity and2 is
port ( a, b : in std_ulogic; y : out std_ulogic );
end entity and2;
--------------------------------------------------
architecture detailed_delay of and2 is
signal result : std_ulogic;
begin
gate : process (a, b) is
begin
result <= a and b;
end process gate;
delay : process (result) is
begin
if result = '1' then
y <= reject 400 ps inertial '1' after 1.5 ns;
elsif result = '0' then
y <= reject 300 ps inertial '0' after 1.2 ns;
else
y <= reject 300 ps inertial 'X' after 500 ps;
end if;
end process delay;
end architecture detailed_delay;
|
gpl-2.0
|
6a5e114b1d7c42422e61d8f742b6fc25
| 0.511952 | 4.747045 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_lpf_dot_ltf_ztf.vhd
| 4 | 2,949 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity tb_lpf_dot_ltf_ztf is
end tb_lpf_dot_ltf_ztf;
architecture TB_lpf_dot_ltf_ztf of tb_lpf_dot_ltf_ztf is
-- Component declarations
-- Signal declarations
terminal in_src : electrical;
terminal out_dot, out_ltf, out_ztf1, out_ztf2, out_ztf3, out_ztf4, out_RC : electrical;
begin
-- Signal assignments
-- Component instances
vio : entity work.v_sine(ideal)
generic map(
freq => 100.0,
amplitude => 5.0
)
port map(
pos => in_src,
neg => ELECTRICAL_REF
);
RC1 : entity work.lowpass(RC)
generic map(
gain => 1.0,
fp => 1.0e1,
Fsmp => 10.0e3
)
port map(
input => in_src,
output => out_RC
);
dot1 : entity work.lowpass(dot)
generic map(
gain => 1.0,
fp => 1.0e1,
Fsmp => 10.0e3
)
port map(
input => in_src,
output => out_dot
);
ltf1 : entity work.lowpass(ltf)
generic map(
gain => 1.0,
fp => 1.0e1,
Fsmp => 10.0e3
)
port map(
input => in_src,
output => out_ltf
);
ztf1 : entity work.lowpass(ztf)
generic map(
gain => 1.0,
fp => 1.0e1,
Fsmp => 10.0e3
)
port map(
input => in_src,
output => out_ztf1
);
ztf2 : entity work.lowpass(ztf)
generic map(
gain => 1.0,
fp => 1.0e1,
Fsmp => 1000.0
)
port map(
input => in_src,
output => out_ztf2
);
ztf3 : entity work.lowpass(ztf)
generic map(
gain => 1.0,
fp => 1.0e1,
Fsmp => 100.0
)
port map(
input => in_src,
output => out_ztf3
);
ztf4 : entity work.lowpass(z_minus_1)
generic map(
gain => 1.0,
fp => 1.0e1,
Fsmp => 10.0e3
)
port map(
input => in_src,
output => out_ztf4
);
end TB_lpf_dot_ltf_ztf;
|
gpl-2.0
|
ee9c30fbfd1a1c66a5fa351fb0343d8a
| 0.548661 | 3.514899 | false | false | false | false |
herenvarno/dlx
|
dlx_vhd/tb/old_tb/a.b.a-tbAlu.vhd
| 1 | 2,306 |
library ieee;
use ieee.std_logic_1164.all;
use work.Consts.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
entity tbAlu is
end tbAlu;
architecture tb_alu_arch of tbAlu is
constant N: integer:=32;
signal a, b: std_logic_vector(N-1 downto 0):=x"00000000";
signal o_add, o_and, o_or, o_xor, o_sll, o_srl, o_sra, o_sub, o_sgt, o_sge, o_slt, o_sle, o_sgtu, o_sgeu, o_sltu, o_sleu, o_seq, o_sne: std_logic_vector(N-1 downto 0):=x"00000000";
component Alu is
generic (
DATA_SIZE : integer := C_SYS_DATA_SIZE
);
port (
f : in std_logic_vector(4 downto 0); -- Function
a : in std_logic_vector(DATA_SIZE-1 downto 0); -- Data A
b : in std_logic_vector(DATA_SIZE-1 downto 0); -- Data B
o : out std_logic_vector(DATA_SIZE-1 downto 0) -- Data Out
);
end component;
begin
ALU0 : Alu
generic map(N)
port map(OP_ADD, a, b, o_add);
ALU1 : Alu
generic map(N)
port map(OP_AND, a, b, o_and);
ALU2 : Alu
generic map(N)
port map(OP_OR, a, b, o_or);
ALU3 : Alu
generic map(N)
port map(OP_XOR, a, b, o_xor);
ALU4 : Alu
generic map(N)
port map(OP_SLL, a, b, o_sll);
ALU5 : Alu
generic map(N)
port map(OP_SRL, a, b, o_srl);
ALU6 : Alu
generic map(N)
port map(OP_SRA, a, b, o_sra);
ALU7 : Alu
generic map(N)
port map(OP_SUB, a, b, o_sub);
ALU8 : Alu
generic map(N)
port map(OP_SGT, a, b, o_sgt);
ALU9 : Alu
generic map(N)
port map(OP_SGE, a, b, o_sge);
ALU10 : Alu
generic map(N)
port map(OP_SLT, a, b, o_slt);
ALU11 : Alu
generic map(N)
port map(OP_SLE, a, b, o_sle);
ALU12 : Alu
generic map(N)
port map(OP_SGTU, a, b, o_sgtu);
ALU13 : Alu
generic map(N)
port map(OP_SGEU, a, b, o_sgeu);
ALU14 : Alu
generic map(N)
port map(OP_SLTU, a, b, o_sltu);
ALU15 : Alu
generic map(N)
port map(OP_SLEU, a, b, o_sleu);
ALU16 : Alu
generic map(N)
port map(OP_SEQ, a, b, o_seq);
ALU17 : Alu
generic map(N)
port map(OP_SNE, a, b, o_sne);
a <= x"ffffffff", x"04532434" after 1 ns, x"2234e826" after 2 ns, x"a323f443" after 3 ns, x"8b651a8b" after 4 ns, x"ffffffff" after 5 ns;
b <= x"00000001", x"05335f28" after 1.5 ns, x"2234e826" after 2.5 ns, x"11645030" after 3.5 ns, x"030035a6" after 4.5 ns, x"00000001" after 5.5 ns, x"12334224" after 7 ns;
end tb_alu_arch;
configuration tb_alu_cfg of tbAlu is
for tb_alu_arch
end for;
end tb_alu_cfg;
|
mit
|
96f0fbecfeebed2da788e1d0461fa7a2
| 0.638768 | 2.208812 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1799.vhd
| 4 | 1,848 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1799.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p02n01i01799ent IS
END c07s01b00x00p02n01i01799ent;
ARCHITECTURE c07s01b00x00p02n01i01799arch OF c07s01b00x00p02n01i01799ent IS
BEGIN
TESTING: PROCESS
variable x : integer := 3;
variable y : integer := 5;
variable z : integer := 9;
BEGIN
if ((x <= y) xnor (x <= z) xnor (y <= z)) Then -- Failure_here
-- sequence of nor operators
-- not allowed in an expression
x:= y+z;
end if;
assert FALSE
report "***FAILED TEST: c07s01b00x00p02n01i01799 - Expression with a sequence of nand or nor operators is illegal."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p02n01i01799arch;
|
gpl-2.0
|
73ba7f50ecb2bb5d01c6ec75014645c9
| 0.656926 | 3.740891 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_06.vhd
| 4 | 3,099 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_06 is
end entity inline_06;
----------------------------------------------------------------
architecture test of inline_06 is
type integer_file is file of integer;
begin
process is
-- code from book:
file lookup_table_file, result_file : integer_file;
-- end of code from book
begin
wait;
end process;
process is
type element_type is (t1, t2, t3);
-- code from book:
type file_type is file of element_type;
procedure file_open ( file f : file_type;
external_name : in string;
open_kind : in file_open_kind := read_mode );
-- end of code from book
procedure file_open ( file f : file_type;
external_name : in string;
open_kind : in file_open_kind := read_mode ) is
begin
end;
begin
wait;
end process;
process is
-- code from book:
file lookup_table_file : integer_file open read_mode is "lookup-values";
-- end of code from book
begin
wait;
end process;
process is
-- code from book:
file lookup_table_file : integer_file;
-- . . .
-- end of code from book
begin
-- code from book:
file_open ( lookup_table_file,
external_name => "lookup-values", open_kind => read_mode );
-- end of code from book
wait;
end process;
process is
type element_type is (t1, t2, t3);
type file_type is file of element_type;
-- code from book:
type file_open_status is (open_ok, status_error, name_error, mode_error);
procedure file_open ( status : out file_open_status;
file f : file_type;
external_name : in string;
open_kind : in file_open_kind := read_mode );
procedure file_close ( file f : file_type );
-- end of code from book
procedure file_open ( status : out file_open_status;
file f : file_type;
external_name : in string;
open_kind : in file_open_kind := read_mode ) is
begin
end;
procedure file_close ( file f : file_type ) is
begin
end;
begin
wait;
end process;
end architecture test;
|
gpl-2.0
|
04a30aceb6c5912c05add9fcb4d5baf1
| 0.590513 | 4.159732 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_17a.vhd
| 4 | 2,051 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- code from book
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity adc_with_ref is
port ( quantity v_in : in voltage;
signal d_out : out bit;
quantity v_ref : in voltage := 1.0 );
end entity adc_with_ref;
-- end code from book
architecture signal_flow of adc_with_ref is
begin
end architecture signal_flow;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_17a is
end entity inline_17a;
architecture test of inline_17a is
begin
block_1 : block is
quantity sensor_in : voltage;
signal sensor_data_out : bit;
begin
sensor_in == 5.0;
-- code from book
default_adc : entity work.adc_with_ref(signal_flow)
port map ( sensor_in, sensor_data_out );
-- end code from book
end block block_1;
block_2 : block is
quantity sensor_in : voltage;
signal sensor_data_out : bit;
constant v_supply : voltage := 10.0;
begin
sensor_in == 5.0;
-- code from book
fixed_adc : entity work.adc_with_ref(signal_flow)
port map ( sensor_in, sensor_data_out, v_ref => v_supply / 2.0 );
-- end code from book
end block block_2;
end architecture test;
|
gpl-2.0
|
882d18f9bc7f6f3a567e120509e5f368
| 0.672843 | 3.791128 | false | false | false | false |
123gmax/Digital-Lab
|
Lab1/Alex/AirTrafficControl/air_traffic_control.vhd
| 1 | 5,107 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09/05/2015 06:05:13 PM
-- Design Name:
-- Module Name: air_traffic_control - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity air_traffic_control is
Port ( PLANE_TYPE : in STD_LOGIC_VECTOR (2 downto 0);
REQ : in STD_LOGIC;
CLK : in STD_LOGIC;
GRANTED : out STD_LOGIC;
DENIED : out STD_LOGIC);
end air_traffic_control;
architecture Behavioral of air_traffic_control is
signal clk_1ms : STD_LOGIC := '0';
signal jet_type : STD_LOGIC := '0';
signal clk_count : integer range 0 to 50000 := 0;
signal current_state, next_state : integer range 0 to 4 := 0;
signal timer_3s : integer range 0 to 3000 := 0;
signal timer_heavy : integer range -10000 to 10000 := 0;
constant c_3s : integer := 3000;
constant c_7s : integer := 7000;
begin
--Clock divider process
process(CLK)
begin
if (rising_edge(CLK)) then
if(clk_count > 50000) then
clk_count <= 0;
clk_1ms <= not clk_1ms;
else
clk_count <= clk_count+1;
end if;
end if;
end process;
-- clk_1ms <= CLK; --This should be used for simulation purposes instead of the clock divider process.
--Jet classification process
process(PLANE_TYPE)
begin
case PLANE_TYPE is
when "001" | "011" | "111" => jet_type <= '1'; --Heavy Jet: 1, 3, 7
when others => jet_type <= '0'; --Light Jet
end case;
end process;
--Runway State Process
process(clk_1ms, current_state, timer_3s, timer_heavy)
begin
if(rising_edge(clk_1ms)) then
case current_state is
when 0 => --RUNWAY READY
if(REQ = '1') then
timer_3s <= c_3s;
if(jet_type = '1') then
next_state <= 3;
else
next_state <= 2;
end if;
else
next_state <= 0;
end if;
when 1 => -- HEAVY TURBULENCE DELAY
if(REQ = '1') then
timer_3s <= c_3s;
if(jet_type = '1') then
next_state <= 3;
else
next_state <= 4;
end if;
else
if(timer_heavy > 0) then
timer_heavy <= timer_heavy - 1;
next_state <= 1;
else
next_state <= 0;
end if;
end if;
when 2 => --LIGHT TAKE_OFF
if(timer_3s > 0) then
timer_3s <= timer_3s - 1;
next_state <= 2;
else
next_state <= 0;
end if;
when 3 => --HEAVY TAKE-OFF
if(timer_3s > 0) then
timer_3s <= timer_3s - 1;
next_state <= 3;
else
timer_heavy <= c_7s;
next_state <= 1;
end if;
when 4 => --DENIED
if(timer_3s > 0) then
timer_3s <= timer_3s - 1;
next_state <= 4;
else
timer_heavy <= timer_heavy - c_3s;
if(timer_heavy > 0) then
next_state <= 1;
else
next_state <= 0;
end if;
end if;
end case;
end if;
end process;
--State transition process
process(CLK)
begin
if(rising_edge(CLK)) then
current_state <= next_state;
end if;
end process;
--Output during certain FSM states.
process(current_state)
begin
if(current_state = 4) then
DENIED <= '1';
GRANTED <= '0';
elsif ((current_state = 2) OR (current_state = 3)) then
DENIED <= '0';
GRANTED <= '1';
else
DENIED <= '0';
GRANTED <= '0';
end if;
end process;
end Behavioral;
|
gpl-2.0
|
388710b72e82dbd1976ed66fea985446
| 0.433523 | 4.406385 | false | false | false | false |
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