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jakubcabal/pipemania-fpga-game
|
source/comp/video/cell_ctrl.vhd
| 1 | 15,927 |
--------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: CELL_CTRL
-- AUTHORS: Jakub Cabal <[email protected]>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/pipemania-fpga-game
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity CELL_CTRL is
Port (
CLK : in std_logic;
PIXEL_X : in std_logic_vector(9 downto 0);
PIXEL_Y : in std_logic_vector(9 downto 0);
KURZOR_ADDR : in std_logic_vector(7 downto 0);
KURZOR : out std_logic;
PIXEL_SET_X : out std_logic;
PIXEL_SET_Y : out std_logic;
KOMP_SET_X : out std_logic;
KOMP_SET_Y : out std_logic;
KOMP_ON : out std_logic;
KOMP4_IS : out std_logic;
ADDR : out std_logic_vector(7 downto 0);
KOMP0 : in std_logic_vector(5 downto 0);
KOMP1 : in std_logic_vector(5 downto 0);
KOMP2 : in std_logic_vector(5 downto 0);
KOMP3 : in std_logic_vector(5 downto 0);
KOMP4 : in std_logic_vector(5 downto 0);
KOMP_OUT : out std_logic_vector(5 downto 0);
SCREEN_CODE : in std_logic_vector(2 downto 0) -- game screen code
);
end CELL_CTRL;
architecture FULL of CELL_CTRL is
signal pix_x : std_logic_vector(9 downto 0);
signal pix_y : std_logic_vector(9 downto 0);
signal addr_x : std_logic_vector(3 downto 0);
signal addr_y : std_logic_vector(3 downto 0);
signal addr_x2 : std_logic_vector(3 downto 0);
signal addr_y2 : std_logic_vector(3 downto 0);
signal obj_addr_x : std_logic_vector(4 downto 0);
signal obj_addr_x2 : std_logic_vector(4 downto 0);
signal obj_addr_y : std_logic_vector(3 downto 0);
signal obj_addr_y2 : std_logic_vector(3 downto 0);
signal pix_set_x : std_logic;
signal pix_set_y : std_logic;
signal sig_kurzor_x : std_logic_vector(3 downto 0);
signal sig_kurzor_y : std_logic_vector(3 downto 0);
signal kurzor_set_x : std_logic;
signal kurzor_set_y : std_logic;
signal k_set_x : std_logic;
signal k_set_y : std_logic;
signal sig_kset_x : std_logic;
signal sig_kset_y : std_logic;
signal sig_komp_on : std_logic;
signal pre_komp_out : std_logic_vector(5 downto 0);
signal rom_addr : std_logic_vector(11 downto 0);
signal rom_data : std_logic_vector(8 downto 0);
signal game_screens : std_logic_vector(2 downto 0);
begin
pix_x <= PIXEL_X;
pix_y <= PIXEL_Y;
----------------------------------------------------------------------------
-- ZOBRAZOVANI HERNIHO POLE
----------------------------------------------------------------------------
process (CLK)
begin
if rising_edge(CLK) then
case pix_x is
when "0000000000" => -- 0
pix_set_x <= '0';
k_set_x <= '1';
addr_x <= (others => '0');
obj_addr_x <= std_logic_vector(to_unsigned(0, 5));
when "0000100000" => -- 32
pix_set_x <= '0';
k_set_x <= '1';
addr_x <= (others => '0');
obj_addr_x <= std_logic_vector(to_unsigned(1, 5));
when "0001000000" => -- 64
pix_set_x <= '0';
k_set_x <= '1';
addr_x <= (others => '0');
obj_addr_x <= std_logic_vector(to_unsigned(2, 5));
when "0001100000" => -- 96
pix_set_x <= '1';
k_set_x <= '1';
addr_x <= std_logic_vector(to_unsigned(0, 4));
obj_addr_x <= std_logic_vector(to_unsigned(3, 5));
when "0010000000" => -- 128
pix_set_x <= '1';
k_set_x <= '1';
addr_x <= std_logic_vector(to_unsigned(1, 4));
obj_addr_x <= std_logic_vector(to_unsigned(4, 5));
when "0010100000" => -- 160
pix_set_x <= '1';
k_set_x <= '1';
addr_x <= std_logic_vector(to_unsigned(2, 4));
obj_addr_x <= std_logic_vector(to_unsigned(5, 5));
when "0011000000" => -- 192
pix_set_x <= '1';
k_set_x <= '1';
addr_x <= std_logic_vector(to_unsigned(3, 4));
obj_addr_x <= std_logic_vector(to_unsigned(6, 5));
when "0011100000" => -- 224
pix_set_x <= '1';
k_set_x <= '1';
addr_x <= std_logic_vector(to_unsigned(4, 4));
obj_addr_x <= std_logic_vector(to_unsigned(7, 5));
when "0100000000" => -- 256
pix_set_x <= '1';
k_set_x <= '1';
addr_x <= std_logic_vector(to_unsigned(5, 4));
obj_addr_x <= std_logic_vector(to_unsigned(8, 5));
when "0100100000" => -- 288
pix_set_x <= '1';
k_set_x <= '1';
addr_x <= std_logic_vector(to_unsigned(6, 4));
obj_addr_x <= std_logic_vector(to_unsigned(9, 5));
when "0101000000" => -- 320
pix_set_x <= '1';
k_set_x <= '1';
addr_x <= std_logic_vector(to_unsigned(7, 4));
obj_addr_x <= std_logic_vector(to_unsigned(10, 5));
when "0101100000" => -- 352
pix_set_x <= '1';
k_set_x <= '1';
addr_x <= std_logic_vector(to_unsigned(8, 4));
obj_addr_x <= std_logic_vector(to_unsigned(11, 5));
when "0110000000" => -- 384
pix_set_x <= '1';
k_set_x <= '1';
addr_x <= std_logic_vector(to_unsigned(9, 4));
obj_addr_x <= std_logic_vector(to_unsigned(12, 5));
when "0110100000" => -- 416
pix_set_x <= '1';
k_set_x <= '1';
addr_x <= std_logic_vector(to_unsigned(10, 4));
obj_addr_x <= std_logic_vector(to_unsigned(13, 5));
when "0111000000" => -- 448
pix_set_x <= '1';
k_set_x <= '1';
addr_x <= std_logic_vector(to_unsigned(11, 4));
obj_addr_x <= std_logic_vector(to_unsigned(14, 5));
when "0111100000" => -- 480
pix_set_x <= '1';
k_set_x <= '1';
addr_x <= std_logic_vector(to_unsigned(12, 4));
obj_addr_x <= std_logic_vector(to_unsigned(15, 5));
when "1000000000" => -- 512
pix_set_x <= '1';
k_set_x <= '1';
addr_x <= std_logic_vector(to_unsigned(13, 4));
obj_addr_x <= std_logic_vector(to_unsigned(16, 5));
when "1000100000" => -- 544
pix_set_x <= '0';
k_set_x <= '1';
addr_x <= (others => '0');
obj_addr_x <= std_logic_vector(to_unsigned(17, 5));
when "1001000000" => -- 576
pix_set_x <= '0';
k_set_x <= '1';
addr_x <= (others => '0');
obj_addr_x <= std_logic_vector(to_unsigned(18, 5));
when "1001100000" => -- 608
pix_set_x <= '0';
k_set_x <= '1';
addr_x <= (others => '0');
obj_addr_x <= std_logic_vector(to_unsigned(19, 5));
when others =>
pix_set_x <= '0';
k_set_x <= '0';
addr_x <= (others => '0');
obj_addr_x <= (others => '0');
end case;
end if;
end process;
process (CLK)
begin
if rising_edge(CLK) then
case pix_y is
when "0000000000" => -- 0
pix_set_y <= '0';
k_set_y <= '1';
addr_y <= (others => '0');
obj_addr_y <= std_logic_vector(to_unsigned(0, 4));
when "0000100000" => -- 32
pix_set_y <= '1';
k_set_y <= '1';
addr_y <= std_logic_vector(to_unsigned(0, 4));
obj_addr_y <= std_logic_vector(to_unsigned(1, 4));
when "0001000000" => -- 64
pix_set_y <= '1';
k_set_y <= '1';
addr_y <= std_logic_vector(to_unsigned(1, 4));
obj_addr_y <= std_logic_vector(to_unsigned(2, 4));
when "0001100000" => -- 96
pix_set_y <= '1';
k_set_y <= '1';
addr_y <= std_logic_vector(to_unsigned(2, 4));
obj_addr_y <= std_logic_vector(to_unsigned(3, 4));
when "0010000000" => -- 128
pix_set_y <= '1';
k_set_y <= '1';
addr_y <= std_logic_vector(to_unsigned(3, 4));
obj_addr_y <= std_logic_vector(to_unsigned(4, 4));
when "0010100000" => -- 160
pix_set_y <= '1';
k_set_y <= '1';
addr_y <= std_logic_vector(to_unsigned(4, 4));
obj_addr_y <= std_logic_vector(to_unsigned(5, 4));
when "0011000000" => -- 192
pix_set_y <= '1';
k_set_y <= '1';
addr_y <= std_logic_vector(to_unsigned(5, 4));
obj_addr_y <= std_logic_vector(to_unsigned(6, 4));
when "0011100000" => -- 224
pix_set_y <= '1';
k_set_y <= '1';
addr_y <= std_logic_vector(to_unsigned(6, 4));
obj_addr_y <= std_logic_vector(to_unsigned(7, 4));
when "0100000000" => -- 256
pix_set_y <= '1';
k_set_y <= '1';
addr_y <= std_logic_vector(to_unsigned(7, 4));
obj_addr_y <= std_logic_vector(to_unsigned(8, 4));
when "0100100000" => -- 288
pix_set_y <= '1';
k_set_y <= '1';
addr_y <= std_logic_vector(to_unsigned(8, 4));
obj_addr_y <= std_logic_vector(to_unsigned(9, 4));
when "0101000000" => -- 320
pix_set_y <= '1';
k_set_y <= '1';
addr_y <= std_logic_vector(to_unsigned(9, 4));
obj_addr_y <= std_logic_vector(to_unsigned(10, 4));
when "0101100000" => -- 352
pix_set_y <= '1';
k_set_y <= '1';
addr_y <= std_logic_vector(to_unsigned(10, 4));
obj_addr_y <= std_logic_vector(to_unsigned(11, 4));
when "0110000000" => -- 384
pix_set_y <= '1';
k_set_y <= '1';
addr_y <= std_logic_vector(to_unsigned(11, 4));
obj_addr_y <= std_logic_vector(to_unsigned(12, 4));
when "0110100000" => -- 416
pix_set_y <= '1';
k_set_y <= '1';
addr_y <= std_logic_vector(to_unsigned(12, 4));
obj_addr_y <= std_logic_vector(to_unsigned(13, 4));
when "0111000000" => -- 448
pix_set_y <= '0';
k_set_y <= '1';
addr_y <= (others => '0');
obj_addr_y <= std_logic_vector(to_unsigned(14, 4));
when others =>
pix_set_y <= '0';
k_set_y <= '0';
addr_y <= (others => '0');
obj_addr_y <= (others => '0');
end case;
end if;
end process;
process (CLK)
begin
if rising_edge(CLK) then
if (pix_set_x = '1') then
addr_x2 <= addr_x;
end if;
end if;
end process;
process (CLK)
begin
if rising_edge(CLK) then
if (pix_set_x = '1' AND pix_set_y = '1') then
addr_y2 <= addr_y;
end if;
end if;
end process;
ADDR <= addr_y2 & addr_x2;
process (CLK)
begin
if rising_edge(CLK) then
if (k_set_x = '1') then
obj_addr_x2 <= obj_addr_x;
end if;
end if;
end process;
process (CLK)
begin
if rising_edge(CLK) then
if (k_set_x = '1' AND k_set_y = '1') then
obj_addr_y2 <= obj_addr_y;
end if;
end if;
end process;
process (CLK)
begin
if rising_edge(CLK) then
PIXEL_SET_X <= pix_set_x;
PIXEL_SET_Y <= pix_set_x AND pix_set_y;
sig_kset_x <= k_set_x;
sig_kset_y <= k_set_x AND k_set_y;
KOMP_SET_X <= sig_kset_x;
KOMP_SET_Y <= sig_kset_y;
end if;
end process;
sig_kurzor_x <= KURZOR_ADDR(3 downto 0);
sig_kurzor_y <= KURZOR_ADDR(7 downto 4);
process (CLK)
begin
if rising_edge(CLK) then
if (pix_set_x = '1') then
if (sig_kurzor_x = addr_x) then
kurzor_set_x <= '1';
else
kurzor_set_x <= '0';
end if;
end if;
end if;
end process;
process (CLK)
begin
if rising_edge(CLK) then
if (pix_set_x = '1' AND pix_set_y = '1') then
if (sig_kurzor_y = addr_y) then
kurzor_set_y <= '1';
else
kurzor_set_y <= '0';
end if;
end if;
end if;
end process;
KURZOR <= kurzor_set_x AND kurzor_set_y;
----------------------------------------------------------------------------
-- ZOBRAZOVANI OBJEKTU MIMO HERNI POLE VCETNE MEZI HERNICH OBRAZOVEK
----------------------------------------------------------------------------
-- Nastaveni cteci pameti
rom_addr <= SCREEN_CODE & obj_addr_y2 & obj_addr_x2;
rom_screen_i : entity work.BRAM_ROM_SCREEN
port map (
CLK => CLK,
ROM_ADDR => rom_addr,
ROM_DOUT => rom_data
);
pre_komp_out <= rom_data(8 downto 3);
with rom_data(2 downto 0) select
KOMP_OUT <= pre_komp_out when "100",
KOMP0 when "101",
KOMP1 when "110",
KOMP2 when "111",
KOMP3 when "001",
KOMP4 when "010",
"000000" when others;
-- aktivní, když se vykreslují roury mimo herní plochu
with rom_data(2 downto 0) select
sig_komp_on <= '1' when "100",
'1' when "101",
'1' when "110",
'1' when "111",
'1' when "001",
'1' when "010",
'0' when others;
KOMP_ON <= sig_komp_on;
KOMP4_IS <= '1' when (rom_data(2 downto 0) = "010") else '0';
end FULL;
|
mit
|
bee96edf7a192df3f0b7184ba34b9d92
| 0.403002 | 3.72555 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1031.vhd
| 4 | 2,184 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1031.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p02n01i01031ent IS
END c06s04b00x00p02n01i01031ent;
ARCHITECTURE c06s04b00x00p02n01i01031arch OF c06s04b00x00p02n01i01031ent IS
BEGIN
TESTING: PROCESS
type TEN is range 1 to 10;
type ABASE1 is array (TEN range <>) of BOOLEAN;
subtype A1 is ABASE1(TEN);
type ABASE2 is array (TEN range <>) of A1;
subtype A2 is ABASE2(TEN);
variable Sl_of_sl : A2 ;
variable V2 : A2 ; -- := (others=>(others=>TRUE));
BEGIN
Sl_of_sl(1 to 8)(7) := V2(2 to 9)(2);
assert NOT( Sl_of_sl(1 to 8)(7)=(false,false,false,false,false,false,false,false,false,false))
report "***PASSED TEST: c06s04b00x00p02n01i01031"
severity NOTE;
assert ( Sl_of_sl(1 to 8)(7)=(false,false,false,false,false,false,false,false,false,false))
report "***FAILED TEST: c06s04b00x00p02n01i01031 - The prefix of an indexed name can be a slice name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p02n01i01031arch;
|
gpl-2.0
|
6285ba5e2f75af8983e6fa20dcfa196f
| 0.653388 | 3.477707 | false | true | false | false |
stnolting/neo430
|
rtl/core/neo430_addr_gen.vhd
| 1 | 6,553 |
-- #################################################################################################
-- # << NEO430 - Address Generator Unit >> #
-- # ********************************************************************************************* #
-- # Address computation and memory address register (MAR). #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
entity neo430_addr_gen is
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
-- data input --
reg_i : in std_ulogic_vector(15 downto 0); -- reg file input
mem_i : in std_ulogic_vector(15 downto 0); -- memory input
imm_i : in std_ulogic_vector(15 downto 0); -- branch offset
irq_sel_i : in std_ulogic_vector(01 downto 0); -- IRQ vector
-- control --
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0);
-- data output --
mem_addr_o : out std_ulogic_vector(15 downto 0); -- memory address
dwb_o : out std_ulogic_vector(15 downto 0) -- data write back output
);
end neo430_addr_gen;
architecture neo430_addr_gen_rtl of neo430_addr_gen is
signal mem_addr_reg : std_ulogic_vector(15 downto 0); -- memory address register
signal addr_add : std_ulogic_vector(15 downto 0); -- result from address adder
begin
-- Memory Address Adder -----------------------------------------------------
-- -----------------------------------------------------------------------------
memory_addr_adder: process(ctrl_i, mem_i, imm_i, reg_i)
variable offset_v : std_ulogic_vector(15 downto 0);
begin
case ctrl_i(ctrl_adr_off2_c downto ctrl_adr_off0_c) is
when "000" => offset_v := imm_i;
when "001" => offset_v := x"0001"; -- +1
when "010" => offset_v := x"0002"; -- +2
when "011" => offset_v := x"FFFE"; -- -2
when others => offset_v := mem_i;
end case;
addr_add <= std_ulogic_vector(unsigned(reg_i) + unsigned(offset_v));
end process memory_addr_adder;
-- output for write back --
dwb_o <= addr_add;
-- Memory Address Register --------------------------------------------------
-- -----------------------------------------------------------------------------
memory_addr_reg: process(clk_i)
begin
if rising_edge(clk_i) then
if (ctrl_i(ctrl_adr_mar_wr_c) = '1') then
if (ctrl_i(ctrl_adr_mar_sel_c) = '0') then
mem_addr_reg <= reg_i;
else
mem_addr_reg <= addr_add;
end if;
end if;
end if;
end process memory_addr_reg;
-- Memory Address Output ----------------------------------------------------
-- -----------------------------------------------------------------------------
memory_addr_out: process(ctrl_i, irq_sel_i, reg_i, mem_addr_reg)
begin
if (ctrl_i(ctrl_adr_bp_en_c) = '1') then
if (ctrl_i(ctrl_adr_ivec_oe_c) = '1') then -- interrupt handler call
mem_addr_o <= dmem_base_c; -- IRQ vectors are located at the beginning of DMEM
mem_addr_o(2 downto 0) <= irq_sel_i & '0'; -- select according word-aligned entry
else -- direct output of reg file
mem_addr_o <= reg_i;
end if;
else
mem_addr_o <= mem_addr_reg;
end if;
end process memory_addr_out;
end neo430_addr_gen_rtl;
|
bsd-3-clause
|
1d2c2610ccfd249909881532e668ddec
| 0.448649 | 4.872119 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_10.vhd
| 4 | 1,460 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_10 is
end entity inline_10;
----------------------------------------------------------------
architecture test of inline_10 is
signal data : bit_vector(7 downto 0) := X"FF";
signal s : bit := '0';
begin
process_3_l : process is
begin
wait for 10 ns;
-- code from book:
data <= X"00";
-- end of code from book
wait for 10 ns;
-- code from book:
s <= '1';
-- . . .
if s = '1' then -- . . .
-- not in book
report "s is '1'";
else
report "s is '0'";
end if;
-- end not in boook
-- end of code from book
wait;
end process process_3_l;
end architecture test;
|
gpl-2.0
|
785149d48db313f4807c574e586f54ca
| 0.623973 | 3.924731 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc630.vhd
| 4 | 2,870 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc630.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:47 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:11 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:26 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00630ent IS
END c03s04b01x00p01n01i00630ent;
ARCHITECTURE c03s04b01x00p01n01i00630arch OF c03s04b01x00p01n01i00630ent IS
type four_value is ('Z','0','1','X');
type four_value_map is array (four_value) of boolean;
type four_value_map_file is file of four_value_map;
constant C38 : four_value_map := (true,true,true,true);
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : four_value_map_file open read_mode is "iofile.37";
variable v : four_value_map;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C38) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00630"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00630 - File reading operation (four_value_map file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00630arch;
|
gpl-2.0
|
964a7d152ff67a8f3ca4770d001077e6
| 0.558537 | 3.857527 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1636.vhd
| 4 | 2,047 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1636.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p05n01i01636ent IS
END c08s12b00x00p05n01i01636ent;
ARCHITECTURE c08s12b00x00p05n01i01636arch OF c08s12b00x00p05n01i01636ent IS
BEGIN
TESTING: PROCESS
type PH is range 1 to 24
units
U;
X=3 U;
Y=2 X;
end units;
type AR1 is array (POSITIVE range <>) of PH;
function K return AR1 is
variable V : AR1(49 to 50) ;
begin
V := (5 U,X) ;
return V;
end K;
variable kk : AR1(49 to 50);
BEGIN
kk := K;
assert NOT(kk = (5 U,X))
report "***PASSED TEST: c08s12b00x00p05n01i01636"
severity NOTE;
assert (kk = (5 U,X))
report "***FAILED TEST: c08s12b00x00p05n01i01636 - The return type must be the same base tyep declared in the specification of the function."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p05n01i01636arch;
|
gpl-2.0
|
1e4d7cdb4e0ce6c3d4c208f6397dd97b
| 0.641915 | 3.591228 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc217.vhd
| 4 | 16,010 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc217.vhd,v 1.2 2005-03-21 17:33:22 dmartin Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b01x00p06n02i00217ent IS
END c03s01b01x00p06n02i00217ent;
ARCHITECTURE c03s01b01x00p06n02i00217arch OF c03s01b01x00p06n02i00217ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT ((character'pos(NUL) = 0) and
(character'pos(SOH) = 1) and
(character'pos(STX) = 2) and
(character'pos(ETX) = 3) and
(character'pos(EOT) = 4) and
(character'pos(ENQ) = 5) and
(character'pos(ACK) = 6) and
(character'pos(BEL) = 7) and
(character'pos(BS ) = 8) and
(character'pos(HT ) = 9) and
(character'pos(LF ) = 10) and
(character'pos(VT ) = 11) and
(character'pos(FF ) = 12) and
(character'pos(CR ) = 13) and
(character'pos(SO ) = 14) and
(character'pos(SI ) = 15) and
(character'pos(DLE) = 16) and
(character'pos(DC1) = 17) and
(character'pos(DC2) = 18) and
(character'pos(DC3) = 19) and
(character'pos(DC4) = 20) and
(character'pos(NAK) = 21) and
(character'pos(SYN) = 22) and
(character'pos(ETB) = 23) and
(character'pos(CAN) = 24) and
(character'pos(EM ) = 25) and
(character'pos(SUB) = 26) and
(character'pos(ESC) = 27) and
(character'pos(FSP) = 28) and
(character'pos(GSP) = 29) and
(character'pos(RSP) = 30) and
(character'pos(USP) = 31) and
(character'pos(' ') = 32) and
(character'pos('!') = 33) and
(character'pos('"') = 34) and
(character'pos('#') = 35) and
(character'pos('$') = 36) and
(character'pos('%') = 37) and
(character'pos('&') = 38) and
(character'pos(''') = 39) and
(character'pos('(') = 40) and
(character'pos(')') = 41) and
(character'pos('*') = 42) and
(character'pos('+') = 43) and
(character'pos(',') = 44) and
(character'pos('-') = 45) and
(character'pos('.') = 46) and
(character'pos('/') = 47) and
(character'pos('0') = 48) and
(character'pos('1') = 49) and
(character'pos('2') = 50) and
(character'pos('3') = 51) and
(character'pos('4') = 52) and
(character'pos('5') = 53) and
(character'pos('6') = 54) and
(character'pos('7') = 55) and
(character'pos('8') = 56) and
(character'pos('9') = 57) and
(character'pos(':') = 58) and
(character'pos(';') = 59) and
(character'pos('<') = 60) and
(character'pos('=') = 61) and
(character'pos('>') = 62) and
(character'pos('?') = 63) and
(character'pos('@') = 64) and
(character'pos('A') = 65) and
(character'pos('B') = 66) and
(character'pos('C') = 67) and
(character'pos('D') = 68) and
(character'pos('E') = 69) and
(character'pos('F') = 70) and
(character'pos('G') = 71) and
(character'pos('H') = 72) and
(character'pos('I') = 73) and
(character'pos('J') = 74) and
(character'pos('K') = 75) and
(character'pos('L') = 76) and
(character'pos('M') = 77) and
(character'pos('N') = 78) and
(character'pos('O') = 79) and
(character'pos('P') = 80) and
(character'pos('Q') = 81) and
(character'pos('R') = 82) and
(character'pos('S') = 83) and
(character'pos('T') = 84) and
(character'pos('U') = 85) and
(character'pos('V') = 86) and
(character'pos('W') = 87) and
(character'pos('X') = 88) and
(character'pos('Y') = 89) and
(character'pos('Z') = 90) and
(character'pos('[') = 91) and
(character'pos('\') = 92) and
(character'pos(']') = 93) and
(character'pos('^') = 94) and
(character'pos('_') = 95) and
(character'pos('`') = 96) and
(character'pos('a') = 97) and
(character'pos('b') = 98) and
(character'pos('c') = 99) and
(character'pos('d') = 100) and
(character'pos('e') = 101) and
(character'pos('f') = 102) and
(character'pos('g') = 103) and
(character'pos('h') = 104) and
(character'pos('i') = 105) and
(character'pos('j') = 106) and
(character'pos('k') = 107) and
(character'pos('l') = 108) and
(character'pos('m') = 109) and
(character'pos('n') = 110) and
(character'pos('o') = 111) and
(character'pos('p') = 112) and
(character'pos('q') = 113) and
(character'pos('r') = 114) and
(character'pos('s') = 115) and
(character'pos('t') = 116) and
(character'pos('u') = 117) and
(character'pos('v') = 118) and
(character'pos('w') = 119) and
(character'pos('x') = 120) and
(character'pos('y') = 121) and
(character'pos('z') = 122) and
(character'pos('{') = 123) and
(character'pos('|') = 124) and
(character'pos('}') = 125) and
(character'pos('~') = 126) and
(character'pos(DEL) = 127) and
(character'pos(character'right) = 127) and
(bit'pos('0') = 0) and
(bit'pos('1') = 1) and
(bit'pos(bit'right) = 1) and
(boolean'pos(false) = 0) and
(boolean'pos(true) = 1) and
(boolean'pos(boolean'right) = 1) and
(severity_level'pos(NOTE) = 0) and
(severity_level'pos(WARNING) = 1) and
(severity_level'pos(ERROR) = 2) and
(severity_level'pos(FAILURE) = 3) and
(severity_level'pos(severity_level'right)
= 3))
report "***PASSED TEST: c03s01b01x00p06n02i00217"
severity NOTE;
assert ( (character'pos(NUL) = 0) and
(character'pos(SOH) = 1) and
(character'pos(STX) = 2) and
(character'pos(ETX) = 3) and
(character'pos(EOT) = 4) and
(character'pos(ENQ) = 5) and
(character'pos(ACK) = 6) and
(character'pos(BEL) = 7) and
(character'pos(BS ) = 8) and
(character'pos(HT ) = 9) and
(character'pos(LF ) = 10) and
(character'pos(VT ) = 11) and
(character'pos(FF ) = 12) and
(character'pos(CR ) = 13) and
(character'pos(SO ) = 14) and
(character'pos(SI ) = 15) and
(character'pos(DLE) = 16) and
(character'pos(DC1) = 17) and
(character'pos(DC2) = 18) and
(character'pos(DC3) = 19) and
(character'pos(DC4) = 20) and
(character'pos(NAK) = 21) and
(character'pos(SYN) = 22) and
(character'pos(ETB) = 23) and
(character'pos(CAN) = 24) and
(character'pos(EM ) = 25) and
(character'pos(SUB) = 26) and
(character'pos(ESC) = 27) and
(character'pos(FSP) = 28) and
(character'pos(GSP) = 29) and
(character'pos(RSP) = 30) and
(character'pos(USP) = 31) and
(character'pos(' ') = 32) and
(character'pos('!') = 33) and
(character'pos('"') = 34) and
(character'pos('#') = 35) and
(character'pos('$') = 36) and
(character'pos('%') = 37) and
(character'pos('&') = 38) and
(character'pos(''') = 39) and
(character'pos('(') = 40) and
(character'pos(')') = 41) and
(character'pos('*') = 42) and
(character'pos('+') = 43) and
(character'pos(',') = 44) and
(character'pos('-') = 45) and
(character'pos('.') = 46) and
(character'pos('/') = 47) and
(character'pos('0') = 48) and
(character'pos('1') = 49) and
(character'pos('2') = 50) and
(character'pos('3') = 51) and
(character'pos('4') = 52) and
(character'pos('5') = 53) and
(character'pos('6') = 54) and
(character'pos('7') = 55) and
(character'pos('8') = 56) and
(character'pos('9') = 57) and
(character'pos(':') = 58) and
(character'pos(';') = 59) and
(character'pos('<') = 60) and
(character'pos('=') = 61) and
(character'pos('>') = 62) and
(character'pos('?') = 63) and
(character'pos('@') = 64) and
(character'pos('A') = 65) and
(character'pos('B') = 66) and
(character'pos('C') = 67) and
(character'pos('D') = 68) and
(character'pos('E') = 69) and
(character'pos('F') = 70) and
(character'pos('G') = 71) and
(character'pos('H') = 72) and
(character'pos('I') = 73) and
(character'pos('J') = 74) and
(character'pos('K') = 75) and
(character'pos('L') = 76) and
(character'pos('M') = 77) and
(character'pos('N') = 78) and
(character'pos('O') = 79) and
(character'pos('P') = 80) and
(character'pos('Q') = 81) and
(character'pos('R') = 82) and
(character'pos('S') = 83) and
(character'pos('T') = 84) and
(character'pos('U') = 85) and
(character'pos('V') = 86) and
(character'pos('W') = 87) and
(character'pos('X') = 88) and
(character'pos('Y') = 89) and
(character'pos('Z') = 90) and
(character'pos('[') = 91) and
(character'pos('\') = 92) and
(character'pos(']') = 93) and
(character'pos('^') = 94) and
(character'pos('_') = 95) and
(character'pos('`') = 96) and
(character'pos('a') = 97) and
(character'pos('b') = 98) and
(character'pos('c') = 99) and
(character'pos('d') = 100) and
(character'pos('e') = 101) and
(character'pos('f') = 102) and
(character'pos('g') = 103) and
(character'pos('h') = 104) and
(character'pos('i') = 105) and
(character'pos('j') = 106) and
(character'pos('k') = 107) and
(character'pos('l') = 108) and
(character'pos('m') = 109) and
(character'pos('n') = 110) and
(character'pos('o') = 111) and
(character'pos('p') = 112) and
(character'pos('q') = 113) and
(character'pos('r') = 114) and
(character'pos('s') = 115) and
(character'pos('t') = 116) and
(character'pos('u') = 117) and
(character'pos('v') = 118) and
(character'pos('w') = 119) and
(character'pos('x') = 120) and
(character'pos('y') = 121) and
(character'pos('z') = 122) and
(character'pos('{') = 123) and
(character'pos('|') = 124) and
(character'pos('}') = 125) and
(character'pos('~') = 126) and
(character'pos(DEL) = 127) and
(character'pos(character'right) = 255) and
(bit'pos('0') = 0) and
(bit'pos('1') = 1) and
(bit'pos(bit'right) = 1) and
(boolean'pos(false) = 0) and
(boolean'pos(true) = 1) and
(boolean'pos(boolean'right) = 1) and
(severity_level'pos(NOTE) = 0) and
(severity_level'pos(WARNING) = 1) and
(severity_level'pos(ERROR) = 2) and
(severity_level'pos(FAILURE) = 3) and
(severity_level'pos(severity_level'right)
= 3))
report "***FAILED TEST: c03s01b01x00p06n02i00217 - The predefined order relations between enumeration values follow the order of corresponding position number."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b01x00p06n02i00217arch;
|
gpl-2.0
|
10bbad0c30a48b2c11e9e6268a415d9c
| 0.400812 | 3.959931 | false | false | false | false |
peteut/ghdl
|
libraries/ieee2008/numeric_bit_unsigned-body.vhdl
| 4 | 17,790 |
-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is sold without written
-- permission from the IEEE Standards Department. This source file may be
-- copied for individual use between licensed users. This source file is
-- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR
-- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE
-- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify
-- and hold IEEE harmless from any damages or liability arising out of the
-- use thereof.
--
-- Title : Standard VHDL Synthesis Packages
-- : (NUMERIC_BIT_UNSIGNED package body)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Values of type BIT_VECTOR
-- : are interpreted as unsigned numbers in vector form.
-- : The leftmost bit is treated as the most significant bit.
-- : This package contains overloaded arithmetic operators on
-- : the BIT_VECTOR type. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array
-- : is returned (exceptions, if any, are noted individually).
--
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
library ieee;
use ieee.numeric_bit.all;
package body NUMERIC_BIT_UNSIGNED is
-- Id: A.3
function "+" (L, R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) + UNSIGNED(R));
end function "+";
-- Id: A.3R
function "+"(L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) + R);
end function "+";
-- Id: A.3L
function "+"(L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (L + UNSIGNED(R));
end function "+";
-- Id: A.5
function "+" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) + R);
end function "+";
-- Id: A.6
function "+" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (L + UNSIGNED(R));
end function "+";
--============================================================================
-- Id: A.9
function "-" (L, R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) - UNSIGNED(R));
end function "-";
-- Id: A.9R
function "-"(L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) - R);
end function "-";
-- Id: A.9L
function "-"(L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (L - UNSIGNED(R));
end function "-";
-- Id: A.11
function "-" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) - R);
end function "-";
-- Id: A.12
function "-" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (L - UNSIGNED(R));
end function "-";
--============================================================================
-- Id: A.15
function "*" (L, R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) * UNSIGNED(R));
end function "*";
-- Id: A.17
function "*" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) * R);
end function "*";
-- Id: A.18
function "*" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (L * UNSIGNED(R));
end function "*";
--============================================================================
-- Id: A.21
function "/" (L, R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) / UNSIGNED(R));
end function "/";
-- Id: A.23
function "/" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) / R);
end function "/";
-- Id: A.24
function "/" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (L / UNSIGNED(R));
end function "/";
--============================================================================
-- Id: A.27
function "rem" (L, R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) rem UNSIGNED(R));
end function "rem";
-- Id: A.29
function "rem" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) rem R);
end function "rem";
-- Id: A.30
function "rem" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (L rem UNSIGNED(R));
end function "rem";
--============================================================================
-- Id: A.33
function "mod" (L, R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) mod UNSIGNED(R));
end function "mod";
-- Id: A.35
function "mod" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) mod R);
end function "mod";
-- Id: A.36
function "mod" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (L mod UNSIGNED(R));
end function "mod";
--============================================================================
-- Id: A.39
function find_leftmost (ARG: BIT_VECTOR; Y: BIT) return INTEGER is
begin
return find_leftmost(UNSIGNED(ARG), Y);
end function find_leftmost;
-- Id: A.41
function find_rightmost (ARG: BIT_VECTOR; Y: BIT) return INTEGER is
begin
return find_rightmost(UNSIGNED(ARG), Y);
end function find_rightmost;
--============================================================================
-- Id: C.1
function ">" (L, R : BIT_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) > UNSIGNED(R);
end function ">";
-- Id: C.3
function ">" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN is
begin
return L > UNSIGNED(R);
end function ">";
-- Id: C.5
function ">" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) > R;
end function ">";
--============================================================================
-- Id: C.7
function "<" (L, R : BIT_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) < UNSIGNED(R);
end function "<";
-- Id: C.9
function "<" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN is
begin
return L < UNSIGNED(R);
end function "<";
-- Id: C.11
function "<" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) < R;
end function "<";
--============================================================================
-- Id: C.13
function "<=" (L, R : BIT_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) <= UNSIGNED(R);
end function "<=";
-- Id: C.15
function "<=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN is
begin
return L <= UNSIGNED(R);
end function "<=";
-- Id: C.17
function "<=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) <= R;
end function "<=";
--============================================================================
-- Id: C.19
function ">=" (L, R : BIT_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) >= UNSIGNED(R);
end function ">=";
-- Id: C.21
function ">=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN is
begin
return L >= UNSIGNED(R);
end function ">=";
-- Id: C.23
function ">=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) >= R;
end function ">=";
--============================================================================
-- Id: C.25
function "=" (L, R : BIT_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) = UNSIGNED(R);
end function "=";
-- Id: C.27
function "=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN is
begin
return L = UNSIGNED(R);
end function "=";
-- Id: C.29
function "=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) = R;
end function "=";
--============================================================================
-- Id: C.31
function "/=" (L, R : BIT_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) /= UNSIGNED(R);
end function "/=";
-- Id: C.33
function "/=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN is
begin
return L /= UNSIGNED(R);
end function "/=";
-- Id: C.35
function "/=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) /= R;
end function "/=";
--============================================================================
-- Id: C.37
function MINIMUM (L, R: BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (MINIMUM(UNSIGNED(L), UNSIGNED(R)));
end function MINIMUM;
-- Id: C.39
function MINIMUM (L: NATURAL; R: BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (MINIMUM(L, UNSIGNED(R)));
end function MINIMUM;
-- Id: C.41
function MINIMUM (L: BIT_VECTOR; R: NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (MINIMUM(UNSIGNED(L), R));
end function MINIMUM;
--============================================================================
-- Id: C.43
function MAXIMUM (L, R: BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (MAXIMUM(UNSIGNED(L), UNSIGNED(R)));
end function MAXIMUM;
-- Id: C.45
function MAXIMUM (L: NATURAL; R: BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (MAXIMUM(L, UNSIGNED(R)));
end function MAXIMUM;
-- Id: C.47
function MAXIMUM (L: BIT_VECTOR; R: NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (MAXIMUM(UNSIGNED(L), R));
end function MAXIMUM;
--============================================================================
-- Id: C.49
function "?>" (L, R: BIT_VECTOR) return BIT is
begin
return UNSIGNED(L) ?> UNSIGNED(R);
end function "?>";
-- Id: C.51
function "?>" (L: NATURAL; R: BIT_VECTOR) return BIT is
begin
return L ?> UNSIGNED(R);
end function "?>";
-- Id: C.53
function "?>" (L: BIT_VECTOR; R: NATURAL) return BIT is
begin
return UNSIGNED(L) ?> R;
end function "?>";
--============================================================================
-- Id: C.55
function "?<" (L, R: BIT_VECTOR) return BIT is
begin
return UNSIGNED(L) ?< UNSIGNED(R);
end function "?<";
-- Id: C.57
function "?<" (L: NATURAL; R: BIT_VECTOR) return BIT is
begin
return L ?< UNSIGNED(R);
end function "?<";
-- Id: C.59
function "?<" (L: BIT_VECTOR; R: NATURAL) return BIT is
begin
return UNSIGNED(L) ?< R;
end function "?<";
--============================================================================
-- Id: C.61
function "?<=" (L, R: BIT_VECTOR) return BIT is
begin
return UNSIGNED(L) ?<= UNSIGNED(R);
end function "?<=";
-- Id: C.63
function "?<=" (L: NATURAL; R: BIT_VECTOR) return BIT is
begin
return L ?<= UNSIGNED(R);
end function "?<=";
-- Id: C.65
function "?<=" (L: BIT_VECTOR; R: NATURAL) return BIT is
begin
return UNSIGNED(L) ?<= R;
end function "?<=";
--============================================================================
-- Id: C.67
function "?>=" (L, R: BIT_VECTOR) return BIT is
begin
return UNSIGNED(L) ?>= UNSIGNED(R);
end function "?>=";
-- Id: C.69
function "?>=" (L: NATURAL; R: BIT_VECTOR) return BIT is
begin
return L ?>= UNSIGNED(R);
end function "?>=";
-- Id: C.71
function "?>=" (L: BIT_VECTOR; R: NATURAL) return BIT is
begin
return UNSIGNED(L) ?>= R;
end function "?>=";
--============================================================================
-- Id: C.73
function "?=" (L, R: BIT_VECTOR) return BIT is
begin
return UNSIGNED(L) ?= UNSIGNED(R);
end function "?=";
-- Id: C.75
function "?=" (L: NATURAL; R: BIT_VECTOR) return BIT is
begin
return L ?= UNSIGNED(R);
end function "?=";
-- Id: C.77
function "?=" (L: BIT_VECTOR; R: NATURAL) return BIT is
begin
return UNSIGNED(L) ?= R;
end function "?=";
--============================================================================
-- Id: C.79
function "?/=" (L, R: BIT_VECTOR) return BIT is
begin
return UNSIGNED(L) ?/= UNSIGNED(R);
end function "?/=";
-- Id: C.81
function "?/=" (L: NATURAL; R: BIT_VECTOR) return BIT is
begin
return L ?/= UNSIGNED(R);
end function "?/=";
-- Id: C.83
function "?/=" (L: BIT_VECTOR; R: NATURAL) return BIT is
begin
return UNSIGNED(L) ?/= R;
end function "?/=";
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (shift_left (ARG => UNSIGNED(ARG),
COUNT => COUNT));
end function SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (shift_right (ARG => UNSIGNED(ARG),
COUNT => COUNT));
end function SHIFT_RIGHT;
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (rotate_left (ARG => UNSIGNED(ARG),
COUNT => COUNT));
end function ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (rotate_right (ARG => UNSIGNED(ARG),
COUNT => COUNT));
end function ROTATE_RIGHT;
--============================================================================
-- Id: S.9
function "sll" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(ARG) sll COUNT);
end function "sll";
-- Id: S.11
function "srl" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(ARG) srl COUNT);
end function "srl";
-- Id: S.13
function "rol" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(ARG) rol COUNT);
end function "rol";
-- Id: S.15
function "ror" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(ARG) ror COUNT);
end function "ror";
-- Id: S.17
function "sla" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(ARG) sla COUNT);
end function "sla";
-- Id: S.19
function "sra" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(ARG) sra COUNT);
end function "sra";
--============================================================================
-- Id: R.2
function RESIZE (ARG : BIT_VECTOR; NEW_SIZE : NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (
resize (arg => UNSIGNED(ARG),
NEW_SIZE => NEW_SIZE));
end function RESIZE;
function RESIZE (ARG, SIZE_RES : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (
RESIZE (ARG => UNSIGNED(ARG),
NEW_SIZE => SIZE_RES'length));
end function RESIZE;
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : BIT_VECTOR) return NATURAL is
begin
return TO_INTEGER (UNSIGNED(ARG));
end function TO_INTEGER;
-- Id: D.3
function To_BitVector (ARG, SIZE : NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (TO_UNSIGNED(ARG, SIZE));
end function To_BitVector;
function To_BitVector (ARG : NATURAL; SIZE_RES : BIT_VECTOR)
return BIT_VECTOR is
begin
return BIT_VECTOR (TO_UNSIGNED(ARG, SIZE_RES'length));
end function To_BitVector;
end package body NUMERIC_BIT_UNSIGNED;
|
gpl-2.0
|
5282f798144575147f586b6ddf32d61d
| 0.512929 | 4.192788 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2286.vhd
| 4 | 2,016 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2286.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p14n01i02286ent IS
END c07s02b06x00p14n01i02286ent;
ARCHITECTURE c07s02b06x00p14n01i02286arch OF c07s02b06x00p14n01i02286ent IS
BEGIN
TESTING: PROCESS
type PHYS is range 1 to 100000
units
A;
B = 100 A;
C = 100 B;
end units;
function F_PHYS ( A : PHYS ) return PHYS is
begin
return A;
end F_PHYS;
variable P : PHYS := 1 B;
variable Z : integer := time'(1 min) / time'(27 sec);
BEGIN
Z := P / F_PHYS(1 A);
assert NOT(Z = 100)
report "***PASSED TEST: c07s02b06x00p14n01i02286"
severity NOTE;
assert (Z = 100)
report "***FAILED TEST: c07s02b06x00p14n01i02286 - Incompatible operands: May not be multiplied or divided."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p14n01i02286arch;
|
gpl-2.0
|
8ede18605bc3d23a6e2e4ad1b1e9769f
| 0.640873 | 3.658802 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/opamp.vhd
| 4 | 1,330 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity opamp is
port ( terminal plus_in, minus_in, output : electrical );
end entity opamp;
----------------------------------------------------------------
architecture slew_limited of opamp is
constant gain : real := 50.0;
quantity v_in across plus_in to minus_in;
quantity v_out across i_out through output;
quantity v_amplified : voltage;
begin
v_amplified == gain * v_in;
v_out == v_amplified'slew(1.0e6,-1.0e6);
end architecture slew_limited;
|
gpl-2.0
|
071301217f09a47c64dbf12aa942bfba
| 0.699248 | 4.018127 | false | false | false | false |
tristanseifert/68komputer
|
sdr_sdram.vhd
| 1 | 15,246 |
--#######################################################################
--
-- LOGIC CORE: SDR SDRAM Controller
-- MODULE NAME: sdr_sdram()
-- COMPANY: Altera Corporation
-- www.altera.com
--
-- REVISION HISTORY:
--
-- Revision 1.1 06/06/2000 Description: Initial Release.
--
-- FUNCTIONAL DESCRIPTION:
--
-- This module is the top level module for the SDR SDRAM controller.
--
--
-- Copyright (C) 1991-2000 Altera Corporation
--
--#######################################################################
library ieee;
use ieee.std_logic_1164.all;
entity sdr_sdram is
generic (
ASIZE : integer := 23;
DSIZE : integer := 16;
ROWSIZE : integer := 12;
COLSIZE : integer := 8;
BANKSIZE : integer := 2;
ROWSTART : integer := 8; -- Starting position of the row address within ADDR
COLSTART : integer := 0; -- Starting position of the column address within ADDR
BANKSTART : integer := 20 -- Starting position of the bank address within ADDR
);
port (
CLK : in std_logic; --System Clock
RESET_N : in std_logic; --System Reset
ADDR : in std_logic_vector(ASIZE-1 downto 0); --Address for controller requests
CMD : in std_logic_vector(2 downto 0); --Controller command
CMDACK : out std_logic; --Controller command acknowledgement
DATAIN : in std_logic_vector(DSIZE-1 downto 0); --Data input
DATAOUT : out std_logic_vector(DSIZE-1 downto 0); --Data output
DM : in std_logic_vector(DSIZE/8-1 downto 0); --Data mask input
SA : out std_logic_vector(11 downto 0); --SDRAM address output
BA : out std_logic_vector(1 downto 0); --SDRAM bank address
CS_N : out std_logic_vector(1 downto 0); --SDRAM Chip Selects
CKE : out std_logic; --SDRAM clock enable
RAS_N : out std_logic; --SDRAM Row address Strobe
CAS_N : out std_logic; --SDRAM Column address Strobe
WE_N : out std_logic; --SDRAM write enable
DQ : inout std_logic_vector(DSIZE-1 downto 0); --SDRAM data bus
DQM : out std_logic_vector(DSIZE/8-1 downto 0) --SDRAM data mask lines
);
end sdr_sdram;
architecture RTL of sdr_sdram is
-- component declarations
component sdr_command
generic (
ASIZE : integer := 23;
DSIZE : integer := 32;
ROWSIZE : integer := 12;
COLSIZE : integer := 9;
BANKSIZE : integer := 2;
ROWSTART : integer := 9; -- Starting position of the row address within ADDR
COLSTART : integer := 0; -- Starting position of the column address within ADDR
BANKSTART : integer := 20 -- Starting position of the bank address within ADDR
);
port (
CLK : in std_logic; -- System Clock
RESET_N : in std_logic; -- System Reset
SADDR : in std_logic_vector(ASIZE-1 downto 0); -- Address
NOP : in std_logic; -- Decoded NOP command
READA : in std_logic; -- Decoded READA command
WRITEA : in std_logic; -- Decoded WRITEA command
REFRESH : in std_logic; -- Decoded REFRESH command
PRECHARGE : in std_logic; -- Decoded PRECHARGE command
LOAD_MODE : in std_logic; -- Decoded LOAD_MODE command
SC_CL : in std_logic_vector(1 downto 0); -- Programmed CAS latency
SC_RC : in std_logic_vector(1 downto 0); -- Programmed RC delay
SC_RRD : in std_logic_vector(3 downto 0); -- Programmed RRD delay
SC_PM : in std_logic; -- programmed Page Mode
SC_BL : in std_logic_vector(3 downto 0); -- Programmed burst length
REF_REQ : in std_logic; -- Hidden refresh request
REF_ACK : out std_logic; -- Refresh request acknowledge
CM_ACK : out std_logic; -- Command acknowledge
OE : out std_logic; -- OE signal for data path module
SA : out std_logic_vector(11 downto 0); -- SDRAM address
BA : out std_logic_vector(1 downto 0); -- SDRAM bank address
CS_N : out std_logic_vector(1 downto 0); -- SDRAM chip selects
CKE : out std_logic; -- SDRAM clock enable
RAS_N : out std_logic; -- SDRAM RAS
CAS_N : out std_logic; -- SDRAM CAS
WE_N : out std_logic -- SDRAM WE_N
);
end component;
component sdr_data_path
generic (
DSIZE : integer := 32
);
port (
CLK : in std_logic; -- System Clock
RESET_N : in std_logic; -- System Reset
OE : in std_logic; -- Data output(to the SDRAM) enable
DATAIN : in std_logic_vector(DSIZE-1 downto 0); -- Data input from the host
DM : in std_logic_vector(DSIZE/8-1 downto 0); -- byte data masks
DATAOUT : out std_logic_vector(DSIZE-1 downto 0); -- Read data output to host
DQIN : in std_logic_vector(DSIZE-1 downto 0); -- SDRAM data bus
DQOUT : out std_logic_vector(DSIZE-1 downto 0);
DQM : out std_logic_vector(DSIZE/8-1 downto 0) -- SDRAM data mask ouputs
);
end component;
component sdr_control_interface
generic (
ASIZE : integer := 32
);
port (
CLK : in std_logic; -- System Clock
RESET_N : in std_logic; -- System Reset
CMD : in std_logic_vector(2 downto 0); -- Command input
ADDR : in std_logic_vector(ASIZE-1 downto 0); -- Address
REF_ACK : in std_logic; -- Refresh request acknowledge
CM_ACK : in std_logic; -- Command acknowledge
NOP : out std_logic; -- Decoded NOP command
READA : out std_logic; -- Decoded READA command
WRITEA : out std_logic; -- Decoded WRITEA command
REFRESH : out std_logic; -- Decoded REFRESH command
PRECHARGE : out std_logic; -- Decoded PRECHARGE command
LOAD_MODE : out std_logic; -- Decoded LOAD_MODE command
SADDR : out std_logic_vector(ASIZE-1 downto 0); -- Registered version of ADDR
SC_CL : out std_logic_vector(1 downto 0); -- Programmed CAS latency
SC_RC : out std_logic_vector(1 downto 0); -- Programmed RC delay
SC_RRD : out std_logic_vector(3 downto 0); -- Programmed RRD delay
SC_PM : out std_logic; -- programmed Page Mode
SC_BL : out std_logic_vector(3 downto 0); -- Programmed burst length
REF_REQ : out std_logic; -- Hidden refresh request
CMD_ACK : out std_logic -- Command acknowledge
);
end component;
attribute syn_black_box: boolean;
component pll1
port (
inclock : in std_logic;
clock1 : out std_logic;
locked : out std_logic
);
end component;
attribute syn_black_box of pll1: component is true;
-- signal declarations
signal ISA : std_logic_vector(11 downto 0); --SDRAM address output
signal IBA : std_logic_vector(1 downto 0); --SDRAM bank address
signal ICS_N : std_logic_vector(1 downto 0); --SDRAM Chip Selects
signal ICKE : std_logic; --SDRAM clock enable
signal IRAS_N : std_logic; --SDRAM Row address Strobe
signal ICAS_N : std_logic; --SDRAM Column address Strobe
signal IWE_N : std_logic;
signal DQIN : std_logic_vector(DSIZE-1 downto 0);
signal IDATAOUT : std_logic_vector(DSIZE-1 downto 0);
signal DQOUT : std_logic_vector(DSIZE-1 downto 0); --SDRAM write enable
signal saddr : std_logic_vector(ASIZE-1 downto 0);
signal sc_cl : std_logic_vector(1 downto 0);
signal sc_rc : std_logic_vector(1 downto 0);
signal sc_rrd : std_logic_vector(3 downto 0);
signal sc_pm : std_logic;
signal sc_bl : std_logic_vector(3 downto 0);
signal load_mode : std_logic;
signal nop : std_logic;
signal reada : std_logic;
signal writea : std_logic;
signal refresh : std_logic;
signal precharge : std_logic;
signal oe : std_logic;
signal ref_req : std_logic;
signal ref_ack : std_logic;
signal cm_ack : std_logic;
begin
-- instantiate the control interface module
control1 : sdr_control_interface
generic map (
ASIZE => ASIZE
)
port map (
CLK => CLK,
RESET_N => RESET_N,
CMD => CMD,
ADDR => ADDR,
REF_ACK => ref_ack,
CM_ACK => cm_ack,
NOP => nop,
READA => reada,
WRITEA => writea,
REFRESH => refresh,
PRECHARGE => precharge,
LOAD_MODE => load_mode,
SADDR => saddr,
SC_CL => sc_cl,
SC_RC => sc_rc,
SC_RRD => sc_rrd,
SC_PM => sc_pm,
SC_BL => sc_bl,
REF_REQ => ref_req,
CMD_ACK => CMDACK
);
-- instantiate the command module
command1 : sdr_command
generic map(
ASIZE => ASIZE,
DSIZE => DSIZE,
ROWSIZE => ROWSIZE,
COLSIZE => COLSIZE,
BANKSIZE => BANKSIZE,
ROWSTART => ROWSTART,
COLSTART => COLSTART,
BANKSTART => BANKSTART
)
port map (
CLK => CLK,
RESET_N => RESET_N,
SADDR => saddr,
NOP => nop,
READA => reada,
WRITEA => writea,
REFRESH => refresh,
PRECHARGE => precharge,
LOAD_MODE => load_mode,
SC_CL => sc_cl,
SC_RC => sc_rc,
SC_RRD => sc_rrd,
SC_PM => sc_pm,
SC_BL => sc_bl,
REF_REQ => ref_req,
REF_ACK => ref_ack,
CM_ACK => cm_ack,
OE => oe,
SA => ISA,
BA => IBA,
CS_N => ICS_N,
CKE => ICKE,
RAS_N => IRAS_N,
CAS_N => ICAS_N,
WE_N => IWE_N
);
-- instantiate the data path module
data_path1 : sdr_data_path
generic map (
DSIZE => DSIZE
)
port map (
CLK => CLK,
RESET_N => RESET_N,
OE => oe,
DATAIN => DATAIN,
DM => DM,
DATAOUT => IDATAOUT,
DQM => DQM,
DQIN => DQIN,
DQOUT => DQOUT
);
-- Add a level flops to the sdram i/o that can be place
-- by the router into the I/O cells
process(CLK)
begin
if rising_edge(CLK) then
SA <= ISA;
BA <= IBA;
CS_N <= ICS_N;
CKE <= ICKE;
RAS_N <= IRAS_N;
CAS_N <= ICAS_N;
WE_N <= IWE_N;
DQIN <= DQ;
DATAOUT <= IDATAOUT;
end if;
end process;
-- tri-state the data bus using the OE signal from the main controller.
DQ <= DQOUT when OE = '1' else (others => 'Z');
end RTL;
|
bsd-2-clause
|
5021ac1b9b0c7ba7308c3af5b5c2e5d6
| 0.387446 | 4.897527 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/tb_a2d_d2a.vhd
| 4 | 3,540 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all;
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
entity tb_a2d_d2a is
end tb_a2d_d2a;
architecture TB_a2d_d2a of tb_a2d_d2a is
-- Component declarations
-- Signal declarations
terminal ana_out : electrical;
terminal analog_in : electrical;
signal clock : std_ulogic;
signal start : std_ulogic;
signal eoc : std_ulogic;
signal eoc_logic: std_logic;
signal oe : std_logic;
signal data_bus : std_ulogic_vector(0 to 9);
signal latch : std_ulogic;
signal latch_logic : std_logic;
signal nn_eoc : std_logic;
signal or_out : std_logic;
signal n_eoc : std_logic;
begin
-- Signal assignments
eoc_logic <= To_X01Z(eoc); -- convert std_ulogic to std_logic
latch <= To_X01(latch_logic); -- convert std_logic to std_ulogic
-- Component instances
ad1 : entity work.a2d_nbit(sar)
port map(
dout => data_bus,
ain => analog_in,
clk => clock,
start => start,
eoc => eoc
);
v1 : entity work.v_sine(ideal)
generic map(
freq => 2.5,
amplitude => 2.5,
offset => 2.5,
phase => 0.0
)
port map(
pos => analog_in,
neg => ELECTRICAL_REF
);
inv1 : entity work.inverter(ideal)
generic map(
delay => 2us
)
port map(
input => or_out,
output => oe
);
inv2 : entity work.inverter(ideal)
generic map(
delay => 2us
)
port map(
input => n_eoc,
output => nn_eoc
);
or1 : entity work.or2(ideal)
port map(
in1 => n_eoc,
in2 => nn_eoc,
output => or_out
);
inv3 : entity work.inverter(ideal)
generic map(
delay => 0us
)
port map(
input => eoc_logic,
output => n_eoc
);
U2 : entity work.buff(ideal)
generic map(
delay => 250ns
)
port map(
input => oe,
output => latch_logic
);
da1 : entity work.dac_10_bit(behavioral)
port map(
bus_in => data_bus,
analog_out => ana_out,
clk => latch
);
-- clock
P_clock :
process
begin
clock <= '1';
wait for 50.0 us;
clock <= '0';
wait for 50.0 us;
end process P_clock;
-- start
P_start :
process
begin
start <= '0';
wait for 2.0 ms;
start <= '1';
wait for 0.2 ms;
start <= '0';
wait for 2.0 ms;
end process P_start;
end TB_a2d_d2a;
|
gpl-2.0
|
c3fd015983b71e88fab914959055f447
| 0.55678 | 3.69906 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/resolution/computer_system.vhd
| 4 | 2,541 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
use work.words.all;
entity cpu is
port ( address : out uword; data : inout uword; -- . . . );
-- not in book
other_port : in X01Z := 'Z' );
-- end not in book
end entity cpu;
-- not in book
architecture behavioral of cpu is
begin
end architecture behavioral;
-- end not in book
--------------------------------------------------
use work.words.all;
entity memory is
port ( address : in uword; data : inout uword; -- . . . );
-- not in book
other_port : in X01Z := 'Z' );
-- end not in book
end entity memory;
-- not in book
architecture behavioral of memory is
begin
end architecture behavioral;
-- end not in book
--------------------------------------------------
-- not in book
use work.words.all;
entity ROM is
port ( a : in uword; d : out ubyte; other_port : in X01Z := 'Z' );
end entity ROM;
architecture behavioral of ROM is
begin
end architecture behavioral;
entity computer_system is
end entity computer_system;
-- end not in book
architecture top_level of computer_system is
use work.words.all;
signal address : uword;
signal data : word;
-- . . .
begin
the_cpu : entity work.cpu(behavioral)
port map ( address, data, -- . . . );
-- not in book
open );
-- end not in book
the_memory : entity work.memory(behavioral)
port map ( address, data, -- . . . );
-- not in book
open );
-- end not in book
-- . . .
-- code from book (in text)
-- boot_rom : entity work.ROM(behavioral)
-- port map ( a => address, d => data(24 to 31), -- . . . ); -- illegal
-- -- not in book
-- other_port => open );
-- -- end not in book
-- end code from book
end architecture top_level;
|
gpl-2.0
|
22d42a5131f6c0e121c5d1f237bf9941
| 0.61708 | 3.792537 | false | false | false | false |
herenvarno/dlx
|
dlx_vhd/src/a.c-InstructionRam.vhd
| 1 | 2,767 |
--------------------------------------------------------------------------------
-- FILE: InstructionRam
-- DESC: Instruction Ram, combinational
--
-- Author:
-- Create: 2015-05-24
-- Update: 2015-10-03
-- Status: TESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
--use work.std_logic_textio.all;
use work.Types.all;
use work.Consts.all;
use work.Funcs.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity InstructionRam is
generic (
ADDR_SIZE : integer := C_SYS_ADDR_SIZE;
ISTR_SIZE : integer := C_SYS_ISTR_SIZE
);
port (
rst : in std_logic;
clk : in std_logic;
en : in std_logic;
addr : in std_logic_vector(ADDR_SIZE-1 downto 0):=(others=>'0');
iout : out std_logic_vector(ISTR_SIZE-1 downto 0):=(others=>'0')
);
end InstructionRam;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture instruction_ram_arch of InstructionRam is
constant IRAM_SIZE : integer := C_RAM_IRAM_SIZE;
type IRam_t is array (0 to IRAM_SIZE-1) of std_logic_vector(7 downto 0);
signal data_area : IRam_t:=(others=>"00000000");
begin
-- Fill the memory with text input file while RESET
FILL_MEM_P: process (rst)
file mem_fp: text;
variable file_line : line;
variable index : integer := 0;
variable tmp_data_u : std_logic_vector(ISTR_SIZE-1 downto 0);
variable istr: std_logic_vector(ISTR_SIZE-1 downto 0);
begin -- process FILL_MEM_P
if (rst = '0') then
index := 0;
file_open(mem_fp,"test.asm.mem",READ_MODE);
while (not endfile(mem_fp)) loop
readline(mem_fp,file_line);
hread(file_line,tmp_data_u);
istr := std_logic_vector(unsigned(tmp_data_u));
data_area(index) <= istr(31 downto 24);
index := index + 1;
data_area(index) <= istr(23 downto 16);
index := index + 1;
data_area(index) <= istr(15 downto 8);
index := index + 1;
data_area(index) <= istr(7 downto 0);
index := index + 1;
end loop;
end if;
end process FILL_MEM_P;
READ_MEM_P: process (rst, clk)
variable index : integer := 0;
begin
if rst = '0' then
iout <= (others=>'0');
else
if rising_edge(clk) and en='1' then
index := to_integer(unsigned(addr));
if index >= IRAM_SIZE then
index := IRAM_SIZE-4;
end if;
iout <= data_area(index)&data_area(index+1)&data_area(index+2)&data_area(index+3);
end if;
end if;
end process READ_MEM_P;
end instruction_ram_arch;
|
mit
|
41ff31ac50c1500977cf76cb832f2423
| 0.539212 | 3.395092 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1950.vhd
| 4 | 13,743 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1950.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c07s02b01x00p01n02i01950pkg is
--
-- Index types for array declarations
--
SUBTYPE st_ind1 IS INTEGER RANGE 1 TO 4; -- index from 1 (POSITIVE)
SUBTYPE st_ind2 IS INTEGER RANGE 0 TO 3; -- index from 0 (NATURAL)
SUBTYPE st_ind3 IS CHARACTER RANGE 'a' TO 'd'; -- non-INTEGER index
SUBTYPE st_ind4 IS INTEGER RANGE 0 DOWNTO -3; -- descending range
--
-- Logic types for subelements
--
SUBTYPE st_scl1 IS BIT;
SUBTYPE st_scl2 IS BOOLEAN;
-- -----------------------------------------------------------------------------------------
-- Composite type declarations
-- -----------------------------------------------------------------------------------------
--
-- Unconstrained arrays
--
TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF BIT;
TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF BOOLEAN;
TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF BIT;
TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF BOOLEAN;
--
-- Constrained arrays of scalars (make compatable with unconstrained types
--
SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1);
SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2);
SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3);
SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4);
-- -----------------------------------------------------------------------------------------
--
-- TYPE declarations for resolution function (Constrained types only)
--
TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
end;
use work.c07s02b01x00p01n02i01950pkg.all;
ENTITY c07s02b01x00p01n02i01950ent IS
END c07s02b01x00p01n02i01950ent;
ARCHITECTURE c07s02b01x00p01n02i01950arch OF c07s02b01x00p01n02i01950ent IS
--
-- CONSTANT Declarations
--
CONSTANT ARGA_C_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
CONSTANT ARGA_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
CONSTANT NOT_C_csa1_1 : t_csa1_1 := ( '0', '0', '1', '1' );
CONSTANT NOT_C_usa1_1 : t_usa1_1(st_ind1) := ( '0', '0', '1', '1' );
CONSTANT ARGA_C_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGA_C_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT NOT_C_csa1_2 : t_csa1_2 := ( FALSE, FALSE, TRUE, TRUE );
CONSTANT NOT_C_usa1_2 : t_usa1_2(st_ind2) := ( FALSE, FALSE, TRUE, TRUE );
CONSTANT ARGA_C_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
CONSTANT ARGA_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
CONSTANT NOT_C_csa1_3 : t_csa1_3 := ( '0', '0', '1', '1' );
CONSTANT NOT_C_usa1_3 : t_usa1_3(st_ind3) := ( '0', '0', '1', '1' );
CONSTANT ARGA_C_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT ARGA_C_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
CONSTANT NOT_C_csa1_4 : t_csa1_4 := ( FALSE, FALSE, TRUE, TRUE );
CONSTANT NOT_C_usa1_4 : t_usa1_4(st_ind4) := ( FALSE, FALSE, TRUE, TRUE );
--
-- SIGNAL Declarations
--
SIGNAL ARGA_S_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
SIGNAL ARGA_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
SIGNAL NOT_S_csa1_1 : t_csa1_1 := ( '0', '0', '1', '1' );
SIGNAL NOT_S_usa1_1 : t_usa1_1(st_ind1) := ( '0', '0', '1', '1' );
SIGNAL ARGA_S_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGA_S_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL NOT_S_csa1_2 : t_csa1_2 := ( FALSE, FALSE, TRUE, TRUE );
SIGNAL NOT_S_usa1_2 : t_usa1_2(st_ind2) := ( FALSE, FALSE, TRUE, TRUE );
SIGNAL ARGA_S_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
SIGNAL ARGA_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
SIGNAL NOT_S_csa1_3 : t_csa1_3 := ( '0', '0', '1', '1' );
SIGNAL NOT_S_usa1_3 : t_usa1_3(st_ind3) := ( '0', '0', '1', '1' );
SIGNAL ARGA_S_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL ARGA_S_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
SIGNAL NOT_S_csa1_4 : t_csa1_4 := ( FALSE, FALSE, TRUE, TRUE );
SIGNAL NOT_S_usa1_4 : t_usa1_4(st_ind4) := ( FALSE, FALSE, TRUE, TRUE );
BEGIN
TESTING: PROCESS
--
-- VARIABLE Declarations
--
VARIABLE ARGA_V_csa1_1 : t_csa1_1 := ( '1', '1', '0', '0' );
VARIABLE ARGA_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
VARIABLE NOT_V_csa1_1 : t_csa1_1 := ( '0', '0', '1', '1' );
VARIABLE NOT_V_usa1_1 : t_usa1_1(st_ind1) := ( '0', '0', '1', '1' );
VARIABLE ARGA_V_csa1_2 : t_csa1_2 := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGA_V_usa1_2 : t_usa1_2(st_ind2) := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE NOT_V_csa1_2 : t_csa1_2 := ( FALSE, FALSE, TRUE, TRUE );
VARIABLE NOT_V_usa1_2 : t_usa1_2(st_ind2) := ( FALSE, FALSE, TRUE, TRUE );
VARIABLE ARGA_V_csa1_3 : t_csa1_3 := ( '1', '1', '0', '0' );
VARIABLE ARGA_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
VARIABLE NOT_V_csa1_3 : t_csa1_3 := ( '0', '0', '1', '1' );
VARIABLE NOT_V_usa1_3 : t_usa1_3(st_ind3) := ( '0', '0', '1', '1' );
VARIABLE ARGA_V_csa1_4 : t_csa1_4 := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE ARGA_V_usa1_4 : t_usa1_4(st_ind4) := ( TRUE, TRUE, FALSE, FALSE );
VARIABLE NOT_V_csa1_4 : t_csa1_4 := ( FALSE, FALSE, TRUE, TRUE );
VARIABLE NOT_V_usa1_4 : t_usa1_4(st_ind4) := ( FALSE, FALSE, TRUE, TRUE );
BEGIN
--
-- Test AND operator on: CONSTANTs
--
ASSERT ( NOT ARGA_C_csa1_1 ) = NOT_C_csa1_1
REPORT "ERROR: composite NOT operator failed; CONSTANT; csa1_1"
SEVERITY FAILURE;
ASSERT ( NOT ARGA_C_csa1_2 ) = NOT_C_csa1_2
REPORT "ERROR: composite NOT operator failed; CONSTANT; csa1_2"
SEVERITY FAILURE;
ASSERT ( NOT ARGA_C_csa1_3 ) = NOT_C_csa1_3
REPORT "ERROR: composite NOT operator failed; CONSTANT; csa1_3"
SEVERITY FAILURE;
ASSERT ( NOT ARGA_C_csa1_4 ) = NOT_C_csa1_4
REPORT "ERROR: composite NOT operator failed; CONSTANT; csa1_4"
SEVERITY FAILURE;
ASSERT ( NOT ARGA_C_usa1_1 ) = NOT_C_usa1_1
REPORT "ERROR: composite NOT operator failed; CONSTANT; usa1_1"
SEVERITY FAILURE;
ASSERT ( NOT ARGA_C_usa1_2 ) = NOT_C_usa1_2
REPORT "ERROR: composite NOT operator failed; CONSTANT; usa1_2"
SEVERITY FAILURE;
ASSERT ( NOT ARGA_C_usa1_3 ) = NOT_C_usa1_3
REPORT "ERROR: composite NOT operator failed; CONSTANT; usa1_3"
SEVERITY FAILURE;
ASSERT ( NOT ARGA_C_usa1_4 ) = NOT_C_usa1_4
REPORT "ERROR: composite NOT operator failed; CONSTANT; usa1_4"
SEVERITY FAILURE;
--
-- Test NOT operator on: SIGNALs
--
ASSERT ( NOT ARGA_S_csa1_1 ) = NOT_S_csa1_1
REPORT "ERROR: composite NOT operator failed; SIGNAL; csa1_1"
SEVERITY FAILURE;
ASSERT ( NOT ARGA_S_csa1_2 ) = NOT_S_csa1_2
REPORT "ERROR: composite NOT operator failed; SIGNAL; csa1_2"
SEVERITY FAILURE;
ASSERT ( NOT ARGA_S_csa1_3 ) = NOT_S_csa1_3
REPORT "ERROR: composite NOT operator failed; SIGNAL; csa1_3"
SEVERITY FAILURE;
ASSERT ( NOT ARGA_S_csa1_4 ) = NOT_S_csa1_4
REPORT "ERROR: composite NOT operator failed; SIGNAL; csa1_4"
SEVERITY FAILURE;
ASSERT ( NOT ARGA_S_usa1_1 ) = NOT_S_usa1_1
REPORT "ERROR: composite NOT operator failed; SIGNAL; usa1_1"
SEVERITY FAILURE;
ASSERT ( NOT ARGA_S_usa1_2 ) = NOT_S_usa1_2
REPORT "ERROR: composite NOT operator failed; SIGNAL; usa1_2"
SEVERITY FAILURE;
ASSERT ( NOT ARGA_S_usa1_3 ) = NOT_S_usa1_3
REPORT "ERROR: composite NOT operator failed; SIGNAL; usa1_3"
SEVERITY FAILURE;
ASSERT ( NOT ARGA_S_usa1_4 ) = NOT_S_usa1_4
REPORT "ERROR: composite NOT operator failed; SIGNAL; usa1_4"
SEVERITY FAILURE;
--
-- Test NOT operator on: VARIABLEs
--
ASSERT ( NOT ARGA_V_csa1_1 ) = NOT_V_csa1_1
REPORT "ERROR: composite NOT operator failed; VARIABLE; csa1_1"
SEVERITY FAILURE;
ASSERT ( NOT ARGA_V_csa1_2 ) = NOT_V_csa1_2
REPORT "ERROR: composite NOT operator failed; VARIABLE; csa1_2"
SEVERITY FAILURE;
ASSERT ( NOT ARGA_V_csa1_3 ) = NOT_V_csa1_3
REPORT "ERROR: composite NOT operator failed; VARIABLE; csa1_3"
SEVERITY FAILURE;
ASSERT ( NOT ARGA_V_csa1_4 ) = NOT_V_csa1_4
REPORT "ERROR: composite NOT operator failed; VARIABLE; csa1_4"
SEVERITY FAILURE;
ASSERT ( NOT ARGA_V_usa1_1 ) = NOT_V_usa1_1
REPORT "ERROR: composite NOT operator failed; VARIABLE; usa1_1"
SEVERITY FAILURE;
ASSERT ( NOT ARGA_V_usa1_2 ) = NOT_V_usa1_2
REPORT "ERROR: composite NOT operator failed; VARIABLE; usa1_2"
SEVERITY FAILURE;
ASSERT ( NOT ARGA_V_usa1_3 ) = NOT_V_usa1_3
REPORT "ERROR: composite NOT operator failed; VARIABLE; usa1_3"
SEVERITY FAILURE;
ASSERT ( NOT ARGA_V_usa1_4 ) = NOT_V_usa1_4
REPORT "ERROR: composite NOT operator failed; VARIABLE; usa1_4"
SEVERITY FAILURE;
wait for 5 ns;
assert NOT( ( NOT ARGA_C_csa1_1 ) = NOT_C_csa1_1 and
( NOT ARGA_C_csa1_2 ) = NOT_C_csa1_2 and
( NOT ARGA_C_csa1_3 ) = NOT_C_csa1_3 and
( NOT ARGA_C_csa1_4 ) = NOT_C_csa1_4 and
( NOT ARGA_C_usa1_1 ) = NOT_C_usa1_1 and
( NOT ARGA_C_usa1_2 ) = NOT_C_usa1_2 and
( NOT ARGA_C_usa1_3 ) = NOT_C_usa1_3 and
( NOT ARGA_C_usa1_4 ) = NOT_C_usa1_4 and
( NOT ARGA_S_csa1_1 ) = NOT_S_csa1_1 and
( NOT ARGA_S_csa1_2 ) = NOT_S_csa1_2 and
( NOT ARGA_S_csa1_3 ) = NOT_S_csa1_3 and
( NOT ARGA_S_csa1_4 ) = NOT_S_csa1_4 and
( NOT ARGA_S_usa1_1 ) = NOT_S_usa1_1 and
( NOT ARGA_S_usa1_2 ) = NOT_S_usa1_2 and
( NOT ARGA_S_usa1_3 ) = NOT_S_usa1_3 and
( NOT ARGA_S_usa1_4 ) = NOT_S_usa1_4 and
( NOT ARGA_V_csa1_1 ) = NOT_V_csa1_1 and
( NOT ARGA_V_csa1_2 ) = NOT_V_csa1_2 and
( NOT ARGA_V_csa1_3 ) = NOT_V_csa1_3 and
( NOT ARGA_V_csa1_4 ) = NOT_V_csa1_4 and
( NOT ARGA_V_usa1_1 ) = NOT_V_usa1_1 and
( NOT ARGA_V_usa1_2 ) = NOT_V_usa1_2 and
( NOT ARGA_V_usa1_3 ) = NOT_V_usa1_3 and
( NOT ARGA_V_usa1_4 ) = NOT_V_usa1_4 )
report "***PASSED TEST: c07s02b01x00p01n02i01950"
severity NOTE;
assert ( ( NOT ARGA_C_csa1_1 ) = NOT_C_csa1_1 and
( NOT ARGA_C_csa1_2 ) = NOT_C_csa1_2 and
( NOT ARGA_C_csa1_3 ) = NOT_C_csa1_3 and
( NOT ARGA_C_csa1_4 ) = NOT_C_csa1_4 and
( NOT ARGA_C_usa1_1 ) = NOT_C_usa1_1 and
( NOT ARGA_C_usa1_2 ) = NOT_C_usa1_2 and
( NOT ARGA_C_usa1_3 ) = NOT_C_usa1_3 and
( NOT ARGA_C_usa1_4 ) = NOT_C_usa1_4 and
( NOT ARGA_S_csa1_1 ) = NOT_S_csa1_1 and
( NOT ARGA_S_csa1_2 ) = NOT_S_csa1_2 and
( NOT ARGA_S_csa1_3 ) = NOT_S_csa1_3 and
( NOT ARGA_S_csa1_4 ) = NOT_S_csa1_4 and
( NOT ARGA_S_usa1_1 ) = NOT_S_usa1_1 and
( NOT ARGA_S_usa1_2 ) = NOT_S_usa1_2 and
( NOT ARGA_S_usa1_3 ) = NOT_S_usa1_3 and
( NOT ARGA_S_usa1_4 ) = NOT_S_usa1_4 and
( NOT ARGA_V_csa1_1 ) = NOT_V_csa1_1 and
( NOT ARGA_V_csa1_2 ) = NOT_V_csa1_2 and
( NOT ARGA_V_csa1_3 ) = NOT_V_csa1_3 and
( NOT ARGA_V_csa1_4 ) = NOT_V_csa1_4 and
( NOT ARGA_V_usa1_1 ) = NOT_V_usa1_1 and
( NOT ARGA_V_usa1_2 ) = NOT_V_usa1_2 and
( NOT ARGA_V_usa1_3 ) = NOT_V_usa1_3 and
( NOT ARGA_V_usa1_4 ) = NOT_V_usa1_4 )
report "***FAILED TEST: c07s02b01x00p01n02i01950 - Logical operator NOT for any user-defined one-dimensional array type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n02i01950arch;
|
gpl-2.0
|
11c81c1e4bff31d772b654f0f507ffbe
| 0.539329 | 2.772443 | false | false | false | false |
123gmax/Digital-Lab
|
AES128/Architecture1_Pipeline/controlUnit.vhd
| 1 | 4,041 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/25/2015 07:19:02 PM
-- Design Name:
-- Module Name: controlUnit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity controlUnit is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
ENABLE : in STD_LOGIC;
loadSourceSelector : out STD_LOGIC := '0';
addRoundKeySelector1 : out STD_LOGIC_VECTOR(1 downto 0) := (others => '0');
addRoundKeySelector2 : out STD_LOGIC_VECTOR(1 downto 0) := (others => '0')
);
end controlUnit;
architecture Behavioral of controlUnit is
constant INITIAL_STATE : natural := 6;
constant NUM_STATES : natural := 6;
begin
loadSourceSelectorProcess: process(CLK, RESET, ENABLE)
constant ENABLE_STATE : natural := 3;
variable state : natural range 0 to NUM_STATES := INITIAL_STATE;
begin
if RESET = '1' then
state := INITIAL_STATE;
elsif rising_edge(CLK) then
loadSourceSelector <= '0';
if ENABLE = '1' then
if (state = ENABLE_STATE) then
loadSourceSelector <= '1';
else
loadSourceSelector <= '0';
end if;
if (state < NUM_STATES) then
state := state + 1;
else
state := 0;
end if;
end if;
end if;
end process;
addRoundKeySelectorProcess2 : process(CLK, RESET)
variable state : natural range 0 to NUM_STATES := INITIAL_STATE;
begin
if RESET = '1' then
state := INITIAL_STATE;
elsif rising_edge(CLK) then
addRoundKeySelector2 <= "10"; --NOTE: THIS SHOULD ALWAYS BE THE VALUE OUTPUT BY THE PREVIOUS TO INITIAL STATE. IT SHOULD BE MANUALLY UPDATED
if ENABLE = '1' then
case state is
when 3 => addRoundKeySelector2 <= "00";
when 4 => addRoundKeySelector2 <= "11";
when 5 => addRoundKeySelector2 <= "10";
when 6 => addRoundKeySelector2 <= "01";
when others => addRoundKeySelector2 <= (others => '0');
end case;
if (state < NUM_STATES) then
state := state + 1;
else
state := 0;
end if;
end if;
end if;
end process;
--The initial addRoundKeySelector always has four states instead of six, since it occurs before the pipeline delay.
addRoundKeySelectorProcess1 : process(CLK, RESET, ENABLE)
variable state : natural range 0 to 3 := 2;
begin
if RESET = '1' then
state := 3;
elsif rising_edge(CLK) then
addRoundKeySelector1 <= "11"; --NOTE: THIS SHOULD ALWAYS BE THE VALUE OUTPUT BY THE PREVIOUS TO INITIAL STATE. IT SHOULD BE MANUALLY UPDATED
if ENABLE = '1' then
case state is
when 3 => addRoundKeySelector1 <= "11";
when 2 => addRoundKeySelector1 <= "10";
when 1 => addRoundKeySelector1 <= "01";
when 0 => addRoundKeySelector1 <= "00";
when others => addRoundKeySelector1 <= (others => '0');
end case;
if (state > 0) then
state := state - 1;
else
state := 3;
end if;
end if;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
e0477f26b19ae1cd49cc6cc8a72de567
| 0.487751 | 5.044944 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2093.vhd
| 4 | 2,399 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2093.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02093ent IS
END c07s02b04x00p20n01i02093ent;
ARCHITECTURE c07s02b04x00p20n01i02093arch OF c07s02b04x00p20n01i02093ent IS
TYPE boolean_v is array (integer range <>) of boolean;
SUBTYPE boolean_4_dwn is boolean_v (4 downto 1);
SUBTYPE boolean_4_null is boolean_v (4 downto 5);
SUBTYPE boolean_8_dwn is boolean_v (8 downto 1);
BEGIN
TESTING: PROCESS
variable l_operand : boolean_4_null ;
variable r_operand : boolean_4_dwn := (false, false, true, true);
variable result : boolean_4_dwn;
BEGIN
result := l_operand & r_operand;
assert ( result (4) = false )
report "result (4) /= false" severity FAILURE;
assert ( result (1) = true )
report "result (1) /= true" severity FAILURE;
assert NOT((result(4)=false) and (result=(false,false,true,true)))
report "***PASSED TEST: c07s02b04x00p20n01i02093"
severity NOTE;
assert ((result(4)=false) and (result=(false,false,true,true)))
report "***FAILED TEST: c07s02b04x00p20n01i02093 - The left bound of the concatenated array is that of the second operand."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02093arch;
|
gpl-2.0
|
65995a563466bc978081d0da4249bca8
| 0.661526 | 3.607519 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc3032.vhd
| 4 | 3,023 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3032.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s02b01x00p01n02i03032ent IS
END c12s02b01x00p01n02i03032ent;
ARCHITECTURE c12s02b01x00p01n02i03032arch OF c12s02b01x00p01n02i03032ent IS
subtype subi is integer range 1 to 10;
subtype subr is real range 1.0 to 10.0;
subtype subb is bit range '1' to '1';
type c_a is array(integer range <>) of subi;
signal s1, s2, s3 : c_a(1 to 3);
BEGIN
-- test array generics
bl1: block
generic(gi : c_a(1 to 3));
generic map (gi => (1,1,1));
port (s11 : OUT c_a(1 to 3));
port map (s11 => s1);
begin
assert ((gi(1)=1) and (gi(2)=1) and (gi(3)=1))
report "Generic array GI did not take on the correct low value of 1"
severity failure;
s11 <= gi;
end block;
bl2: block
generic(gi : c_a(1 to 3));
generic map (gi => (5,5,5));
port (s22 : OUT c_a(1 to 3));
port map (s22 => s2);
begin
assert ((gi(1)=5) and (gi(2)=5) and (gi(3)=5))
report "Generic array GI did not take on the correct middle value of 5"
severity failure;
s22 <= gi;
end block;
bl3: block
generic(gi : c_a(1 to 3));
generic map (gi => (10,10,10));
port (s33 : OUT c_a(1 to 3));
port map (s33 => s3);
begin
assert ((gi(1)=10) and (gi(2)=10) and (gi(3)=10))
report "Generic array GI did not take on the correct high value of 10"
severity failure;
s33 <= gi;
end block;
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert NOT( s1 = (1,1,1) and s2 = (5,5,5) and s3 = (10,10,10) )
report "***PASSED TEST: c12s02b01x00p01n02i03032"
severity NOTE;
assert ( s1 = (1,1,1) and s2 = (5,5,5) and s3 = (10,10,10) )
report "***FAILED TEST: c12s02b01x00p01n02i03032 - Generic constants does not conform to their subtype indication."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s02b01x00p01n02i03032arch;
|
gpl-2.0
|
d3ee4ad551de538d746ebdbe1de63074
| 0.622891 | 3.202331 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/average_samples.vhd
| 4 | 1,651 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity average_sample is
end entity average_sample;
architecture test of average_sample is
procedure average_test is
variable average : real := 0.0;
type sample_array is array (positive range <>) of real;
constant samples : sample_array :=
( 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0 );
-- code from book
procedure average_samples is
variable total : real := 0.0;
begin
assert samples'length > 0 severity failure;
for index in samples'range loop
total := total + samples(index);
end loop;
average := total / real(samples'length);
end procedure average_samples;
-- end code from book
begin
-- code from book (in text)
average_samples;
-- end code from book
end procedure average_test;
begin
average_test;
end architecture test;
|
gpl-2.0
|
83a19f5d8113b08c84746dfe61834174
| 0.683828 | 4.036675 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_11.vhd
| 4 | 1,899 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_fg_07_11.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_07_11 is
end entity fg_07_11;
architecture test of fg_07_11 is
subtype word32 is bit_vector(31 downto 0);
-- code from book
procedure increment ( a : inout word32; by : in word32 := X"0000_0001" ) is
variable sum : word32;
variable carry : bit := '0';
begin
for index in a'reverse_range loop
sum(index) := a(index) xor by(index) xor carry;
carry := ( a(index) and by(index) ) or ( carry and ( a(index) xor by(index) ) );
end loop;
a := sum;
end procedure increment;
-- end code from book
begin
stimulus : process is
variable count : word32 := X"0001_1100";
begin
-- code from book (in text)
increment(count, X"0000_0004");
increment(count);
increment(count, by => open);
-- end code from book
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
fa120b97ba5172e8742bbefc23f161dd
| 0.615061 | 3.923554 | false | false | false | false |
beltagymohamed/FLOATING-POINT-MULTIPLIER-USING-FPGA
|
Multiplier/Project/VHDL/add_sub.vhd
| 1 | 680 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity add_sub is
port (
add_sub_in_a:in std_logic_vector(7 downto 0 );
add_sub_in_b:in std_logic_vector(7 downto 0 );
add_sub_out:out std_logic_vector(7 downto 0 );
add_sub_sel:in std_logic
);
end add_sub ;
---// when the sel is ONE = Addition when select zero = subtraction \\---
architecture behaviour of add_sub is
begin
process (add_sub_in_a,add_sub_in_b,add_sub_sel)
begin
if (add_sub_sel='1')then
add_sub_out<=add_sub_in_a+add_sub_in_b;
else
add_sub_out<=add_sub_in_a-add_sub_in_b;
end if ;
end process;
end behaviour;
|
mit
|
6ff52fece247dc06028f9346bfc2c87b
| 0.630882 | 2.764228 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/asym_delay.vhd
| 4 | 1,422 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity asym_delay is
end entity asym_delay;
architecture test of asym_delay is
signal a, z : bit;
begin
-- code from book
asym_delay : process (a) is
constant Tpd_01 : time := 800 ps;
constant Tpd_10 : time := 500 ps;
begin
if a = '1' then
z <= transport a after Tpd_01;
else -- a = '0'
z <= transport a after Tpd_10;
end if;
end process asym_delay;
-- end code from book
stimulus : process is
begin
a <= '1' after 2000 ps,
'0' after 4000 ps,
'1' after 6000 ps,
'0' after 6200 ps;
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
9e6f7dcfdbe01fd83d27b99a092338b2
| 0.673699 | 3.874659 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/reg-1.vhd
| 4 | 1,488 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity reg is
generic ( t_setup, t_hold, t_pd : delay_length;
width : positive );
port ( clock : in std_logic;
reset_n : in std_logic := 'H';
data_in : in std_logic_vector(0 to width - 1);
data_out : out std_logic_vector(0 to width - 1) );
end entity reg;
-- not in book
architecture gate_level of reg is
begin
store : process (clock, reset_n) is
begin
if reset_n = '0' or reset_n = 'L' then
data_out <= (others => '0') after t_pd;
elsif rising_edge(clock) then
data_out <= data_in after t_pd;
end if;
end process store;
end architecture gate_level;
-- end not in book
|
gpl-2.0
|
3597e052c60bd0a4ddd49a8aebab11bb
| 0.678091 | 3.647059 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_divider/Shantz/Modular/shantz_modular.vhd
| 1 | 5,026 |
---------------------------------------------------------------------------------------------------
-- divider_f2m.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Inverter for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: This is an implementation of the division algorithm. Dirent to the other implemented inverter
-- in this, the division is performed directly.
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity f2m_divider_163 is
generic(
NUM_BITS : positive := 163
);
port(
x : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
y : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
done : out STD_LOGIC;
x_div_y : out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of f2m_divider_163 is
----------------------------------------------------------------------------------------------------
-- m = 163, the irreductible polynomial
constant p : std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001001";
-- control signals
signal CASO: std_logic_vector(1 downto 0);
signal c0, c1, c2, c3, c4, c5, c6, enA, enB, a_greater_b,a_eq_b: std_logic;
signal A, B, U, V, X2, Y2, toB, toV: STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
type CurrentState_type is (END_STATE, LOAD1, CYCLE);
signal currentState: CurrentState_type;
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
X2 <= x & '0';
Y2 <= y & '0';
caso <= "00" when A(0) = '0' and currentState = CYCLE else
"01" when B(0) = '0' and currentState = CYCLE else
"10" when a_greater_b = '1' and currentState = CYCLE else
"11";
c0 <= '0' when caso = "01" else
'1';
c1 <= '0' when caso = "00" else
'1';
c2 <= '0' when caso = "01" else
'1';
c3 <= '0' when caso = "00" else
'1';
c4 <= '0' when CurrentState = Load1 else
'1';
c5 <= '0' when rst = '1' or currentState = LOAD1 else
'1';
c6 <= '0' when rst = '1' else
'1';
enA <= '1' when currentState = LOAD1 or caso = "00" or caso = "10" else
'0';
enB <= '1' when caso = "01" or caso = "11" or rst = '1' or currentstate = LOAD1 else
'0';
a_greater_b <= '1' when A > B else
'0';
a_eq_b <= '1' when A = B else
'0';
celda_reg_A: entity celda_a(behave)
port map( A, B, c0, c1, enA, rst, clk, toB, A);
celda_reg_U: entity celda_U(behave)
port map(U, V, P, c2, c3, c4, enA, rst, clk, toV, U);
celda_reg_B: entity celda_B(behave)
port map(toB, P , Y2, c5, c6, enB, clk, B);
celda_reg_V: entity celda_v(behave)
port map(toV, X2, c5, c6, enB, clk, V);
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
EEAL: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if rst = '1' then
x_div_y <= (others => '0');
done <= '0';
currentState <= LOAD1;
else
case currentState is
-----------------------------------------------------------------------------------
when LOAD1 =>
currentState <= Cycle;
when CYCLE =>
if A_eq_B = '1' then
currentState <= END_STATE;
Done <= '1';
x_div_y <= U(NUM_BITS-1 downto 0);
end if;
-----------------------------------------------------------------------------------
when END_STATE => -- Do nothing
currentState <= END_STATE;
--done <= '0'; -- para generar el pulso, quitarlo entity caso contrario
-----------------------------------------------------------------------------------
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
3c9576cfc2bdd5702be0892bef407f2f
| 0.411858 | 4.079545 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2116.vhd
| 4 | 2,216 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2116.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02116ent IS
END c07s02b04x00p20n01i02116ent;
ARCHITECTURE c07s02b04x00p20n01i02116arch OF c07s02b04x00p20n01i02116ent IS
TYPE real_v is array (integer range <>) of real;
SUBTYPE real_8 is real_v (1 to 8);
SUBTYPE real_4 is real_v (1 to 4);
BEGIN
TESTING : PROCESS
variable result : real_8;
variable l_operand : real_4 := (12.345, -67.890,12.345, -67.890);
variable r_operand : real_4 := ( -67.890, -67.890,12.345,12.345);
BEGIN
result := l_operand & r_operand;
wait for 20 ns;
assert NOT((result = (12.345,-67.890,12.345,-67.890,-67.890,-67.890,12.345,12.345)) and (result(1) = 12.345))
report "***PASSED TEST: c07s02b04x00p20n01i02116"
severity NOTE;
assert ((result = (12.345,-67.890,12.345,-67.890,-67.890,-67.890,12.345,12.345)) and (result(1) = 12.345))
report "***FAILED TEST: c07s02b04x00p20n01i02116 - Concatenation of two REAL arrays failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02116arch;
|
gpl-2.0
|
547888245648f67978e34b64034e729b
| 0.655235 | 3.357576 | false | true | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_divider/Guerric/SingleFile/guerric_divider_2.vhd
| 1 | 4,496 |
-- The VHDL code was written by Miguel Morales-Sandoval
--([email protected]) from 2004 to 2008 when he was
--a MSc and PhD student at the Computer Science department in INAOE,
--Mexico.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity f2m_divider_163 is
generic(
NUM_BITS : positive := 163
);
port(
x : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
y : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
done : out STD_LOGIC;
x_div_y: out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of f2m_divider_163 is
----------------------------------------------------------------------------------------------------
signal V : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal U, s, R : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal to_U, to_R, to_V, to_S, op1 : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
----------------------------------------------------------------------------------------------------
constant F : std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001001";
signal c: std_logic_vector(3 downto 0);
signal U_div_2, R_div_2, V_div_2, S_div_2, p_div_2 : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal D, counter :std_logic_vector(8 downto 0);
signal IsPos, en: std_logic;
type CurrentState_type is (END_STATE, INIT, CYCLE);
signal currentState: CurrentState_type;
----------------------------------------------------------------------------------------------------
begin
U_div_2 <= '0' & U(NUM_BITS downto 1);
R_div_2 <= '0' & R(NUM_BITS downto 1);
V_div_2 <= '0' & V(NUM_BITS downto 1);
S_div_2 <= '0' & S(NUM_BITS downto 1);
p_div_2 <= '0' & F(NUM_BITS downto 1);
to_U <= u_div_2 xor v_div_2 when c(0) = '1' else
u_div_2;
op1 <= R_div_2 xor p_div_2 when c(3) = '1' else
R_div_2;
to_R <= op1 xor s_div_2 when c(0) = '1' else
op1;
--to_v <= U when c(1) = '0' and c(2) = '0' else
-- U when c(1) = '0' and c(2) = '1' else
-- Y when c(1) = '1' and c(2) = '0' else
-- F;
--to_s <= R when c(1) = '0' and c(2) = '0' else
-- R when c(1) = '0' and c(2) = '1' else
-- X when c(1) = '1' and c(2) = '0' else
-- (others => '0');
c(0) <= U(0);
c(3) <= '1';
EEAL: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if (rst = '1')then
U <= '0' & Y;
V <= F;
R <= '0' & X;
S <= (others => '0');
done <= '0';
x_div_y <= (others => '0');
counter <= "101000111"; -- 325 2m-1
D <= "000000001";
IsPos <= '0';
currentState <= Cycle;
else
case currentState is
-----------------------------------------------------------------------------------
when CYCLE =>
if counter = "000000000" then
currentState <= END_STATE;
Done <= '1';
x_div_y <= S(NUM_BITS-1 downto 0);
else
counter <= counter - 1;
U <= to_U;
R <= to_R;
if U(0) = '0' then
if IsPos = '0' then
D <= D + 1;
elsif D = "000000000" then
D <= D + 1;
IsPos <= '0';
else
D <= D - 1;
end if;
elsif IsPos = '1' then
if D = "000000000" then
D <= D + 1;
IsPos <= '0';
else
D <= D - 1;
end if;
else
D <= D - 1;
IsPos <= '1';
V <= U;
S <= R;
end if;
end if;
-----------------------------------------------------------------------------------
when END_STATE => -- Do nothing
currentState <= END_STATE;
-- para generar el pulso, quitarlo entity caso contrario
-----------------------------------------------------------------------------------
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
6e6bcdf3ff5c6b364a9778f76454024d
| 0.438835 | 3.377911 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2485.vhd
| 4 | 2,035 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2485.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b03x00p02n01i02485ent IS
END c07s03b03x00p02n01i02485ent;
ARCHITECTURE c07s03b03x00p02n01i02485arch OF c07s03b03x00p02n01i02485ent IS
BEGIN
TESTING: PROCESS
function check (x:integer; y:boolean; z:real) return boolean is
begin
if y then
return true;
end if;
return false;
end;
variable p: integer := 3;
variable q: boolean := true;
variable r: real;
variable q1: boolean;
BEGIN
q1 := check (p,q,r);
assert NOT(q1=true)
report "***PASSED TEST: c07s03b03x00p02n01i02485"
severity NOTE;
assert (q1=true)
report "***FAILED TEST: c07s03b03x00p02n01i02485 - The function call consists of a function name and (optionally) an actual parameter list enclosed with parentheses."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b03x00p02n01i02485arch;
|
gpl-2.0
|
7bfb2b1dffa73951c88dce9613f1a2be
| 0.666339 | 3.693285 | false | true | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_Multiplication/Serial_Mul_Paar/multiplier_113_1.vhd
| 1 | 15,230 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--------------------------------------------------------
-- Con celda y sin maquina de estados
--------------------------------------------------------
-- x ^113 + x ^9 + 1
entity serial_multiplier_113 is
generic (
NUM_BITS : positive := 113 -- The order of the finite field
);
port(
ax : in std_logic_vector(NUM_BITS-1 downto 0);
bx : in std_logic_vector(NUM_BITS-1 downto 0);
cx : out std_logic_vector(NUM_BITS-1 downto 0); -- cx = ax*bx mod Fx
reset : in std_logic;
clk : in std_logic;
done : out std_logic
);
end serial_multiplier_113;
-----------------------------------------------------------
architecture behave of serial_multiplier_113 is
-----------------------------------------------------------
signal bx_shift : std_logic_vector(NUM_BITS-1 downto 0); -- B and C shifted one position to the rigth
signal bx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal cx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal counter: std_logic_vector(7 downto 0); -- 8-bit counter, controling the number of iterations: m
signal done_int : std_logic;
--señales para las xor de la reduccion:
signal xor_1 : std_logic;
-----------------------------------------------------------
-- States for the finite state machine
-----------------------------------------------------------
--type CurrentState_type is (NOTHING, END_STATE, MUL_STATE);
--signal CurrentState: CurrentState_type;
-----------------------------------------------------------
begin
-----------------------------------------------------------
-- Result of the multiplication
xor_1 <= Cx_int(8) xor Cx_int(NUM_BITS-1);
Bx_shift <= bx_int(NUM_BITS-2 downto 0)& '0'; -- Shift Bx to left one position
------------------------------------------------------------
-- The finite state machine, it takes m cycles to compute
-- the multiplication, a counter is used to keep this count
------------------------------------------------------------
CELL_0: ENTITY basic_cell(behave)
PORT MAP(Ax(0),Bx_int(NUM_BITS-1),Cx_int(NUM_BITS-1),clk,reset,Cx_int(0));
CELL_1: ENTITY basic_cell(behave)
PORT MAP(Ax(1),Bx_int(NUM_BITS-1),Cx_int(0),clk,reset,Cx_int(1));
CELL_2: ENTITY basic_cell(behave)
PORT MAP(Ax(2),Bx_int(NUM_BITS-1),Cx_int(1),clk,reset,Cx_int(2));
CELL_3: ENTITY basic_cell(behave)
PORT MAP(Ax(3),Bx_int(NUM_BITS-1),Cx_int(2),clk,reset,Cx_int(3));
CELL_4: ENTITY basic_cell(behave)
PORT MAP(Ax(4),Bx_int(NUM_BITS-1),Cx_int(3),clk,reset,Cx_int(4));
CELL_5: ENTITY basic_cell(behave)
PORT MAP(Ax(5),Bx_int(NUM_BITS-1),Cx_int(4),clk,reset,Cx_int(5));
CELL_6: ENTITY basic_cell(behave)
PORT MAP(Ax(6),Bx_int(NUM_BITS-1),Cx_int(5),clk,reset,Cx_int(6));
CELL_7: ENTITY basic_cell(behave)
PORT MAP(Ax(7),Bx_int(NUM_BITS-1),Cx_int(6),clk,reset,Cx_int(7));
CELL_8: ENTITY basic_cell(behave)
PORT MAP(Ax(8),Bx_int(NUM_BITS-1),Cx_int(7),clk,reset,Cx_int(8));
CELL_9: ENTITY basic_cell(behave)
PORT MAP(Ax(9),Bx_int(NUM_BITS-1),xor_1,clk,reset,Cx_int(9));
CELL_10: ENTITY basic_cell(behave)
PORT MAP(Ax(10),Bx_int(NUM_BITS-1),Cx_int(9),clk,reset,Cx_int(10));
CELL_11: ENTITY basic_cell(behave)
PORT MAP(Ax(11),Bx_int(NUM_BITS-1),Cx_int(10),clk,reset,Cx_int(11));
CELL_12: ENTITY basic_cell(behave)
PORT MAP(Ax(12),Bx_int(NUM_BITS-1),Cx_int(11),clk,reset,Cx_int(12));
CELL_13: ENTITY basic_cell(behave)
PORT MAP(Ax(13),Bx_int(NUM_BITS-1),Cx_int(12),clk,reset,Cx_int(13));
CELL_14: ENTITY basic_cell(behave)
PORT MAP(Ax(14),Bx_int(NUM_BITS-1),Cx_int(13),clk,reset,Cx_int(14));
CELL_15: ENTITY basic_cell(behave)
PORT MAP(Ax(15),Bx_int(NUM_BITS-1),Cx_int(14),clk,reset,Cx_int(15));
CELL_16: ENTITY basic_cell(behave)
PORT MAP(Ax(16),Bx_int(NUM_BITS-1),Cx_int(15),clk,reset,Cx_int(16));
CELL_17: ENTITY basic_cell(behave)
PORT MAP(Ax(17),Bx_int(NUM_BITS-1),Cx_int(16),clk,reset,Cx_int(17));
CELL_18: ENTITY basic_cell(behave)
PORT MAP(Ax(18),Bx_int(NUM_BITS-1),Cx_int(17),clk,reset,Cx_int(18));
CELL_19: ENTITY basic_cell(behave)
PORT MAP(Ax(19),Bx_int(NUM_BITS-1),Cx_int(18),clk,reset,Cx_int(19));
CELL_20: ENTITY basic_cell(behave)
PORT MAP(Ax(20),Bx_int(NUM_BITS-1),Cx_int(19),clk,reset,Cx_int(20));
CELL_21: ENTITY basic_cell(behave)
PORT MAP(Ax(21),Bx_int(NUM_BITS-1),Cx_int(20),clk,reset,Cx_int(21));
CELL_22: ENTITY basic_cell(behave)
PORT MAP(Ax(22),Bx_int(NUM_BITS-1),Cx_int(21),clk,reset,Cx_int(22));
CELL_23: ENTITY basic_cell(behave)
PORT MAP(Ax(23),Bx_int(NUM_BITS-1),Cx_int(22),clk,reset,Cx_int(23));
CELL_24: ENTITY basic_cell(behave)
PORT MAP(Ax(24),Bx_int(NUM_BITS-1),Cx_int(23),clk,reset,Cx_int(24));
CELL_25: ENTITY basic_cell(behave)
PORT MAP(Ax(25),Bx_int(NUM_BITS-1),Cx_int(24),clk,reset,Cx_int(25));
CELL_26: ENTITY basic_cell(behave)
PORT MAP(Ax(26),Bx_int(NUM_BITS-1),Cx_int(25),clk,reset,Cx_int(26));
CELL_27: ENTITY basic_cell(behave)
PORT MAP(Ax(27),Bx_int(NUM_BITS-1),Cx_int(26),clk,reset,Cx_int(27));
CELL_28: ENTITY basic_cell(behave)
PORT MAP(Ax(28),Bx_int(NUM_BITS-1),Cx_int(27),clk,reset,Cx_int(28));
CELL_29: ENTITY basic_cell(behave)
PORT MAP(Ax(29),Bx_int(NUM_BITS-1),Cx_int(28),clk,reset,Cx_int(29));
CELL_30: ENTITY basic_cell(behave)
PORT MAP(Ax(30),Bx_int(NUM_BITS-1),Cx_int(29),clk,reset,Cx_int(30));
CELL_31: ENTITY basic_cell(behave)
PORT MAP(Ax(31),Bx_int(NUM_BITS-1),Cx_int(30),clk,reset,Cx_int(31));
CELL_32: ENTITY basic_cell(behave)
PORT MAP(Ax(32),Bx_int(NUM_BITS-1),Cx_int(31),clk,reset,Cx_int(32));
CELL_33: ENTITY basic_cell(behave)
PORT MAP(Ax(33),Bx_int(NUM_BITS-1),Cx_int(32),clk,reset,Cx_int(33));
CELL_34: ENTITY basic_cell(behave)
PORT MAP(Ax(34),Bx_int(NUM_BITS-1),Cx_int(33),clk,reset,Cx_int(34));
CELL_35: ENTITY basic_cell(behave)
PORT MAP(Ax(35),Bx_int(NUM_BITS-1),Cx_int(34),clk,reset,Cx_int(35));
CELL_36: ENTITY basic_cell(behave)
PORT MAP(Ax(36),Bx_int(NUM_BITS-1),Cx_int(35),clk,reset,Cx_int(36));
CELL_37: ENTITY basic_cell(behave)
PORT MAP(Ax(37),Bx_int(NUM_BITS-1),Cx_int(36),clk,reset,Cx_int(37));
CELL_38: ENTITY basic_cell(behave)
PORT MAP(Ax(38),Bx_int(NUM_BITS-1),Cx_int(37),clk,reset,Cx_int(38));
CELL_39: ENTITY basic_cell(behave)
PORT MAP(Ax(39),Bx_int(NUM_BITS-1),Cx_int(38),clk,reset,Cx_int(39));
CELL_40: ENTITY basic_cell(behave)
PORT MAP(Ax(40),Bx_int(NUM_BITS-1),Cx_int(39),clk,reset,Cx_int(40));
CELL_41: ENTITY basic_cell(behave)
PORT MAP(Ax(41),Bx_int(NUM_BITS-1),Cx_int(40),clk,reset,Cx_int(41));
CELL_42: ENTITY basic_cell(behave)
PORT MAP(Ax(42),Bx_int(NUM_BITS-1),Cx_int(41),clk,reset,Cx_int(42));
CELL_43: ENTITY basic_cell(behave)
PORT MAP(Ax(43),Bx_int(NUM_BITS-1),Cx_int(42),clk,reset,Cx_int(43));
CELL_44: ENTITY basic_cell(behave)
PORT MAP(Ax(44),Bx_int(NUM_BITS-1),Cx_int(43),clk,reset,Cx_int(44));
CELL_45: ENTITY basic_cell(behave)
PORT MAP(Ax(45),Bx_int(NUM_BITS-1),Cx_int(44),clk,reset,Cx_int(45));
CELL_46: ENTITY basic_cell(behave)
PORT MAP(Ax(46),Bx_int(NUM_BITS-1),Cx_int(45),clk,reset,Cx_int(46));
CELL_47: ENTITY basic_cell(behave)
PORT MAP(Ax(47),Bx_int(NUM_BITS-1),Cx_int(46),clk,reset,Cx_int(47));
CELL_48: ENTITY basic_cell(behave)
PORT MAP(Ax(48),Bx_int(NUM_BITS-1),Cx_int(47),clk,reset,Cx_int(48));
CELL_49: ENTITY basic_cell(behave)
PORT MAP(Ax(49),Bx_int(NUM_BITS-1),Cx_int(48),clk,reset,Cx_int(49));
CELL_50: ENTITY basic_cell(behave)
PORT MAP(Ax(50),Bx_int(NUM_BITS-1),Cx_int(49),clk,reset,Cx_int(50));
CELL_51: ENTITY basic_cell(behave)
PORT MAP(Ax(51),Bx_int(NUM_BITS-1),Cx_int(50),clk,reset,Cx_int(51));
CELL_52: ENTITY basic_cell(behave)
PORT MAP(Ax(52),Bx_int(NUM_BITS-1),Cx_int(51),clk,reset,Cx_int(52));
CELL_53: ENTITY basic_cell(behave)
PORT MAP(Ax(53),Bx_int(NUM_BITS-1),Cx_int(52),clk,reset,Cx_int(53));
CELL_54: ENTITY basic_cell(behave)
PORT MAP(Ax(54),Bx_int(NUM_BITS-1),Cx_int(53),clk,reset,Cx_int(54));
CELL_55: ENTITY basic_cell(behave)
PORT MAP(Ax(55),Bx_int(NUM_BITS-1),Cx_int(54),clk,reset,Cx_int(55));
CELL_56: ENTITY basic_cell(behave)
PORT MAP(Ax(56),Bx_int(NUM_BITS-1),Cx_int(55),clk,reset,Cx_int(56));
CELL_57: ENTITY basic_cell(behave)
PORT MAP(Ax(57),Bx_int(NUM_BITS-1),Cx_int(56),clk,reset,Cx_int(57));
CELL_58: ENTITY basic_cell(behave)
PORT MAP(Ax(58),Bx_int(NUM_BITS-1),Cx_int(57),clk,reset,Cx_int(58));
CELL_59: ENTITY basic_cell(behave)
PORT MAP(Ax(59),Bx_int(NUM_BITS-1),Cx_int(58),clk,reset,Cx_int(59));
CELL_60: ENTITY basic_cell(behave)
PORT MAP(Ax(60),Bx_int(NUM_BITS-1),Cx_int(59),clk,reset,Cx_int(60));
CELL_61: ENTITY basic_cell(behave)
PORT MAP(Ax(61),Bx_int(NUM_BITS-1),Cx_int(60),clk,reset,Cx_int(61));
CELL_62: ENTITY basic_cell(behave)
PORT MAP(Ax(62),Bx_int(NUM_BITS-1),Cx_int(61),clk,reset,Cx_int(62));
CELL_63: ENTITY basic_cell(behave)
PORT MAP(Ax(63),Bx_int(NUM_BITS-1),Cx_int(62),clk,reset,Cx_int(63));
CELL_64: ENTITY basic_cell(behave)
PORT MAP(Ax(64),Bx_int(NUM_BITS-1),Cx_int(63),clk,reset,Cx_int(64));
CELL_65: ENTITY basic_cell(behave)
PORT MAP(Ax(65),Bx_int(NUM_BITS-1),Cx_int(64),clk,reset,Cx_int(65));
CELL_66: ENTITY basic_cell(behave)
PORT MAP(Ax(66),Bx_int(NUM_BITS-1),Cx_int(65),clk,reset,Cx_int(66));
CELL_67: ENTITY basic_cell(behave)
PORT MAP(Ax(67),Bx_int(NUM_BITS-1),Cx_int(66),clk,reset,Cx_int(67));
CELL_68: ENTITY basic_cell(behave)
PORT MAP(Ax(68),Bx_int(NUM_BITS-1),Cx_int(67),clk,reset,Cx_int(68));
CELL_69: ENTITY basic_cell(behave)
PORT MAP(Ax(69),Bx_int(NUM_BITS-1),Cx_int(68),clk,reset,Cx_int(69));
CELL_70: ENTITY basic_cell(behave)
PORT MAP(Ax(70),Bx_int(NUM_BITS-1),Cx_int(69),clk,reset,Cx_int(70));
CELL_71: ENTITY basic_cell(behave)
PORT MAP(Ax(71),Bx_int(NUM_BITS-1),Cx_int(70),clk,reset,Cx_int(71));
CELL_72: ENTITY basic_cell(behave)
PORT MAP(Ax(72),Bx_int(NUM_BITS-1),Cx_int(71),clk,reset,Cx_int(72));
CELL_73: ENTITY basic_cell(behave)
PORT MAP(Ax(73),Bx_int(NUM_BITS-1),Cx_int(72),clk,reset,Cx_int(73));
CELL_74: ENTITY basic_cell(behave)
PORT MAP(Ax(74),Bx_int(NUM_BITS-1),Cx_int(73),clk,reset,Cx_int(74));
CELL_75: ENTITY basic_cell(behave)
PORT MAP(Ax(75),Bx_int(NUM_BITS-1),Cx_int(74),clk,reset,Cx_int(75));
CELL_76: ENTITY basic_cell(behave)
PORT MAP(Ax(76),Bx_int(NUM_BITS-1),Cx_int(75),clk,reset,Cx_int(76));
CELL_77: ENTITY basic_cell(behave)
PORT MAP(Ax(77),Bx_int(NUM_BITS-1),Cx_int(76),clk,reset,Cx_int(77));
CELL_78: ENTITY basic_cell(behave)
PORT MAP(Ax(78),Bx_int(NUM_BITS-1),Cx_int(77),clk,reset,Cx_int(78));
CELL_79: ENTITY basic_cell(behave)
PORT MAP(Ax(79),Bx_int(NUM_BITS-1),Cx_int(78),clk,reset,Cx_int(79));
CELL_80: ENTITY basic_cell(behave)
PORT MAP(Ax(80),Bx_int(NUM_BITS-1),Cx_int(79),clk,reset,Cx_int(80));
CELL_81: ENTITY basic_cell(behave)
PORT MAP(Ax(81),Bx_int(NUM_BITS-1),Cx_int(80),clk,reset,Cx_int(81));
CELL_82: ENTITY basic_cell(behave)
PORT MAP(Ax(82),Bx_int(NUM_BITS-1),Cx_int(81),clk,reset,Cx_int(82));
CELL_83: ENTITY basic_cell(behave)
PORT MAP(Ax(83),Bx_int(NUM_BITS-1),Cx_int(82),clk,reset,Cx_int(83));
CELL_84: ENTITY basic_cell(behave)
PORT MAP(Ax(84),Bx_int(NUM_BITS-1),Cx_int(83),clk,reset,Cx_int(84));
CELL_85: ENTITY basic_cell(behave)
PORT MAP(Ax(85),Bx_int(NUM_BITS-1),Cx_int(84),clk,reset,Cx_int(85));
CELL_86: ENTITY basic_cell(behave)
PORT MAP(Ax(86),Bx_int(NUM_BITS-1),Cx_int(85),clk,reset,Cx_int(86));
CELL_87: ENTITY basic_cell(behave)
PORT MAP(Ax(87),Bx_int(NUM_BITS-1),Cx_int(86),clk,reset,Cx_int(87));
CELL_88: ENTITY basic_cell(behave)
PORT MAP(Ax(88),Bx_int(NUM_BITS-1),Cx_int(87),clk,reset,Cx_int(88));
CELL_89: ENTITY basic_cell(behave)
PORT MAP(Ax(89),Bx_int(NUM_BITS-1),Cx_int(88),clk,reset,Cx_int(89));
CELL_90: ENTITY basic_cell(behave)
PORT MAP(Ax(90),Bx_int(NUM_BITS-1),Cx_int(89),clk,reset,Cx_int(90));
CELL_91: ENTITY basic_cell(behave)
PORT MAP(Ax(91),Bx_int(NUM_BITS-1),Cx_int(90),clk,reset,Cx_int(91));
CELL_92: ENTITY basic_cell(behave)
PORT MAP(Ax(92),Bx_int(NUM_BITS-1),Cx_int(91),clk,reset,Cx_int(92));
CELL_93: ENTITY basic_cell(behave)
PORT MAP(Ax(93),Bx_int(NUM_BITS-1),Cx_int(92),clk,reset,Cx_int(93));
CELL_94: ENTITY basic_cell(behave)
PORT MAP(Ax(94),Bx_int(NUM_BITS-1),Cx_int(93),clk,reset,Cx_int(94));
CELL_95: ENTITY basic_cell(behave)
PORT MAP(Ax(95),Bx_int(NUM_BITS-1),Cx_int(94),clk,reset,Cx_int(95));
CELL_96: ENTITY basic_cell(behave)
PORT MAP(Ax(96),Bx_int(NUM_BITS-1),Cx_int(95),clk,reset,Cx_int(96));
CELL_97: ENTITY basic_cell(behave)
PORT MAP(Ax(97),Bx_int(NUM_BITS-1),Cx_int(96),clk,reset,Cx_int(97));
CELL_98: ENTITY basic_cell(behave)
PORT MAP(Ax(98),Bx_int(NUM_BITS-1),Cx_int(97),clk,reset,Cx_int(98));
CELL_99: ENTITY basic_cell(behave)
PORT MAP(Ax(99),Bx_int(NUM_BITS-1),Cx_int(98),clk,reset,Cx_int(99));
CELL_100: ENTITY basic_cell(behave)
PORT MAP(Ax(100),Bx_int(NUM_BITS-1),Cx_int(99),clk,reset,Cx_int(100));
CELL_101: ENTITY basic_cell(behave)
PORT MAP(Ax(101),Bx_int(NUM_BITS-1),Cx_int(100),clk,reset,Cx_int(101));
CELL_102: ENTITY basic_cell(behave)
PORT MAP(Ax(102),Bx_int(NUM_BITS-1),Cx_int(101),clk,reset,Cx_int(102));
CELL_103: ENTITY basic_cell(behave)
PORT MAP(Ax(103),Bx_int(NUM_BITS-1),Cx_int(102),clk,reset,Cx_int(103));
CELL_104: ENTITY basic_cell(behave)
PORT MAP(Ax(104),Bx_int(NUM_BITS-1),Cx_int(103),clk,reset,Cx_int(104));
CELL_105: ENTITY basic_cell(behave)
PORT MAP(Ax(105),Bx_int(NUM_BITS-1),Cx_int(104),clk,reset,Cx_int(105));
CELL_106: ENTITY basic_cell(behave)
PORT MAP(Ax(106),Bx_int(NUM_BITS-1),Cx_int(105),clk,reset,Cx_int(106));
CELL_107: ENTITY basic_cell(behave)
PORT MAP(Ax(107),Bx_int(NUM_BITS-1),Cx_int(106),clk,reset,Cx_int(107));
CELL_108: ENTITY basic_cell(behave)
PORT MAP(Ax(108),Bx_int(NUM_BITS-1),Cx_int(107),clk,reset,Cx_int(108));
CELL_109: ENTITY basic_cell(behave)
PORT MAP(Ax(109),Bx_int(NUM_BITS-1),Cx_int(108),clk,reset,Cx_int(109));
CELL_110: ENTITY basic_cell(behave)
PORT MAP(Ax(110),Bx_int(NUM_BITS-1),Cx_int(109),clk,reset,Cx_int(110));
CELL_111: ENTITY basic_cell(behave)
PORT MAP(Ax(111),Bx_int(NUM_BITS-1),Cx_int(110),clk,reset,Cx_int(111));
CELL_112: ENTITY basic_cell(behave)
PORT MAP(Ax(112),Bx_int(NUM_BITS-1),Cx_int(111),clk,reset,Cx_int(112));
done <= done_int;
FSM_MUL: process (CLK)
Begin
if CLK'event and CLK = '1' then
if Reset = '1' then
counter <= "01110001"; -- m value, in this case, it is 112, be sure to set the correct value
cx <= (others => '0');
Done_int <= '0';
else
if counter = "0000000" then -- The done signal is asserted at the same time that the result is computed.
if (done_int = '0') then
done_int <= '1';
Cx <= Cx_int;
end if;
else
counter <= counter - 1;
end if;
end if;
end if;
end process;
SHIFT_REGISTER: process (CLK)
Begin
if CLK'event and CLK = '1' then
if Reset = '1' then
Bx_shift <= Bx;
else
Bx_shift <= Bx_shift(NUM_BITS-2 downto 0) & '0'; -- carga paralela
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
325114c369ba0ab811d8838cdbdcf73d
| 0.64176 | 2.441879 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/pendulum.vhd
| 4 | 1,855 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.math_real.all;
entity pendulum is
end entity pendulum;
----------------------------------------------------------------
architecture constrained of pendulum is
constant mass : real := 10.0;
constant arm_length : real := 5.0;
constant pin_angle : real := 0.25 * math_pi;
constant pin_distance : real := 2.5;
constant damping : real := 1.0;
constant gravity : real := 9.81;
constant short_length : real := arm_length - pin_distance;
quantity phi : real := -0.5*math_pi;
quantity current_length : real := arm_length;
begin
if phi'above(pin_angle) use
current_length == short_length;
else
current_length == arm_length;
end use;
break phi'dot => phi'dot * arm_length/short_length
when phi'above(pin_angle);
break phi'dot => phi'dot * short_length/arm_length
when not phi'above(pin_angle);
mass * current_length * phi'dot'dot
== - mass * gravity * sin(phi) - damping * current_length * phi'dot;
end architecture constrained;
|
gpl-2.0
|
6bb3b9d7d5ce5f23c032fc249de1b019
| 0.658221 | 3.930085 | false | false | false | false |
stnolting/neo430
|
rtl/core/neo430_trng.vhd
| 1 | 13,168 |
-- #################################################################################################
-- # << NEO430 - True Random Number Generator >> #
-- # ********************************************************************************************* #
-- # This unit implements a true random number generator which uses an inverter chain as entropy #
-- # source. The inverter chain is constructed as GARO (Galois Ring Oscillator) TRNG. The single #
-- # inverters are connected via simple latches that are used to enbale/disable the TRNG. Also, #
-- # these latches are used as additional delay element. By using unique enable signals for each #
-- # latch, the synthesis tool cannot "optimize" one of the inverters out of the design. Further- #
-- # more, the latches prevent the synthesis tool from detecting combinatorial loops. #
-- # The output of the GARO is de-biased by a simple von Neuman random extractor and is further #
-- # post-processed by an 8-bit LFSR for improved whitening. #
-- # #
-- # Sources: #
-- # - GARO: "Experimental Assessment of FIRO- and GARO-based Noise Sources for Digital TRNG #
-- # Designs on FPGAs" by Martin Schramm, Reiner Dojen and Michael Heigly, 2017 #
-- # - Latches for platform independence: "Extended Abstract: The Butterfly PUF Protecting IP #
-- # on every FPGA" by Sandeep S. Kumar, Jorge Guajardo, Roel Maesyz, Geert-Jan Schrijen and #
-- # Pim Tuyls, Philips Research Europe, 2008 #
-- # - Von Neumann De-Biasing: "Iterating Von Neumann's Post-Processing under Hardware #
-- # Constraints" by Vladimir Rozic, Bohan Yang, Wim Dehaene and Ingrid Verbauwhede, 2016 #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
entity neo430_trng is
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0) -- data out
);
end neo430_trng;
architecture neo430_trng_rtl of neo430_trng is
-- advanced configuration ------------------------------------------------------------------------------------
constant num_inv_c : natural := 14; -- length of GARO inverter chain (default=14, max=14)
constant lfsr_taps_c : std_ulogic_vector(11 downto 0) := "100000101001"; -- Fibonacci LFSR feedback taps
-- -------------------------------------------------------------------------------------------------------
-- control register bits --
-- < write-only bits > --
constant ctrl_taps_00_c : natural := 0; -- -/w: TAP 0 enable
-- ...
constant ctrl_taps_13_c : natural := 13; -- -/w: TAP 13 enable
-- < read-only bits > --
constant ctrl_data_00_c : natural := 0; -- r/-: Random data bit 0
-- ...
constant ctrl_data_11_c : natural := 11; -- r/-: Random data bit 11
-- < remaining bits > --
constant ctrl_rnd_en_c : natural := 14; -- r/w: TRNG enable
constant ctrl_rnd_valid_c : natural := 15; -- r/-: Output byte valid
-- IO space: module base address --
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
constant lo_abb_c : natural := index_size_f(trng_size_c); -- low address boundary bit
-- access control --
signal acc_en : std_ulogic; -- module access enable
signal wren : std_ulogic; -- full word write enable
signal rden : std_ulogic; -- read enable
-- random number generator --
signal rnd_inv : std_ulogic_vector(num_inv_c-1 downto 0); -- inverter chain
signal rnd_enable_sreg : std_ulogic_vector(num_inv_c-1 downto 0); -- enable shift register
signal rnd_enable : std_ulogic;
signal tap_config : std_ulogic_vector(13 downto 0);
signal rnd_sync : std_ulogic_vector(2 downto 0); -- metastability filter & de-biasing
signal ready_ff : std_ulogic; -- new random data available
signal rnd_sreg : std_ulogic_vector(11 downto 0); -- sample shift reg
signal rnd_cnt : std_ulogic_vector(3 downto 0);
signal new_sample : std_ulogic; -- new output byte ready
signal rnd_data : std_ulogic_vector(11 downto 0); -- random data register (read-only)
-- Randomness extractor (von Neumann De-Biasing) --
signal db_state : std_ulogic;
signal db_enable : std_ulogic; -- valid data from de-biasing
signal db_data : std_ulogic; -- actual data from de-biasing
begin
-- Access Control -----------------------------------------------------------
-- -----------------------------------------------------------------------------
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = trng_base_c(hi_abb_c downto lo_abb_c)) else '0';
wren <= acc_en and wren_i;
rden <= acc_en and rden_i;
-- Write access -------------------------------------------------------------
-- -----------------------------------------------------------------------------
wr_access: process(clk_i)
begin
if rising_edge(clk_i) then
if (wren = '1') then
rnd_enable <= data_i(ctrl_rnd_en_c);
tap_config(13 downto 0) <= data_i(ctrl_taps_13_c downto ctrl_taps_00_c);
end if;
end if;
end process wr_access;
-- True Random Generator ----------------------------------------------------
-- -----------------------------------------------------------------------------
entropy_source: process(rnd_enable_sreg, rnd_enable, rnd_inv, tap_config)
begin
for i in 0 to num_inv_c-1 loop
if (rnd_enable = '0') then -- start with a defined state (latch reset)
rnd_inv(i) <= '0';
-- uniquely enable latches to prevent synthesis from removing chain elements
elsif (rnd_enable_sreg(i) = '1') then -- latch enable
-- here we have the inverter chain --
if (i = num_inv_c-1) then -- left most inverter?
if (tap_config(i) = '1') then
rnd_inv(i) <= not rnd_inv(0); -- direct input of right most inverter (= output signal)
else
rnd_inv(i) <= '0';
end if;
else
if (tap_config(i) = '1') then
rnd_inv(i) <= not (rnd_inv(i+1) xor rnd_inv(0)); -- use final output as feedback
else
rnd_inv(i) <= not rnd_inv(i+1); -- normal chain: use previous inverter's output as input
end if;
end if;
end if;
end loop; -- i
end process entropy_source;
-- unique enable signals for each inverter latch --
inv_enable: process(clk_i)
begin
if rising_edge(clk_i) then
-- using individual enable signals for each inverter - derived from a shift register - to prevent the synthesis tool
-- from removing all but one inverter (since they implement "logical identical functions")
-- this also allows to make the trng platform independent
rnd_enable_sreg <= rnd_enable_sreg(num_inv_c-2 downto 0) & rnd_enable; -- activate right most inverter first
end if;
end process inv_enable;
-- Processing Core ----------------------------------------------------------
-- -----------------------------------------------------------------------------
processing_core: process(clk_i)
begin
if rising_edge(clk_i) then
-- synchronize output of GARO --
rnd_sync <= rnd_sync(1 downto 0) & rnd_inv(0); -- no more metastability
-- von Neumann De-Biasing state --
db_state <= (not db_state) and rnd_enable; -- just toggle -> process in every second cycle
-- sample random data & post-processing --
if (rnd_enable = '0') then
rnd_cnt <= (others => '0');
rnd_sreg <= (others => '0');
elsif (db_enable = '1') then -- valid de-biased output?
if (rnd_cnt = "1010") then
rnd_cnt <= (others => '0');
else
rnd_cnt <= std_ulogic_vector(unsigned(rnd_cnt) + 1);
end if;
rnd_sreg <= rnd_sreg(10 downto 0) & (xor_all_f(rnd_sreg and lfsr_taps_c) xor db_data); -- LFSR post-processing
end if;
-- data output register --
if (new_sample = '1') then
rnd_data <= rnd_sreg;
end if;
-- data ready flag --
if (rnd_enable = '0') or (rden = '1') then -- clear when deactivated or on data read
ready_ff <= '0';
elsif (new_sample = '1') then
ready_ff <= '1';
end if;
end if;
end process processing_core;
-- John von Neumann De-Biasing --
debiasing: process(db_state, rnd_sync)
variable tmp_v : std_ulogic_vector(2 downto 0);
begin
-- check groups of two non-overlapping bits from the input stream
tmp_v := db_state & rnd_sync(2 downto 1);
case tmp_v is
when "101" => db_enable <= '1'; db_data <= '1'; -- rising edge -> '1'
when "110" => db_enable <= '1'; db_data <= '0'; -- falling edge -> '0'
when others => db_enable <= '0'; db_data <= '-'; -- invalid
end case;
end process debiasing;
-- new valid byte available? --
new_sample <= '1' when (rnd_cnt = "1010") and (rnd_enable = '1') and (db_enable = '1') else '0';
-- Read access --------------------------------------------------------------
-- -----------------------------------------------------------------------------
rd_access: process(clk_i)
begin
if rising_edge(clk_i) then
data_o <= (others => '0');
if (rden = '1') then
data_o(ctrl_data_11_c downto ctrl_data_00_c) <= rnd_data;
data_o(ctrl_rnd_en_c) <= rnd_enable;
data_o(ctrl_rnd_valid_c) <= ready_ff;
end if;
end if;
end process rd_access;
end neo430_trng_rtl;
|
bsd-3-clause
|
9b62237e055ab5ce8e43094aa532030a
| 0.502962 | 4.384948 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_Amp_Lim.vhd
| 3 | 35,269 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity sum2_e is
generic (k1, k2: real := 1.0); -- Gain multipliers
port ( terminal in1, in2: electrical;
terminal output: electrical);
end entity sum2_e;
architecture simple of sum2_e is
QUANTITY vin1 ACROSS in1 TO ELECTRICAL_REF;
QUANTITY vin2 ACROSS in2 TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
begin
vout == k1*vin1 + k2*vin2;
end architecture simple;
--
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
entity gain_e is
generic (
k: REAL := 1.0); -- Gain multiplier
port ( terminal input : electrical;
terminal output: electrical);
end entity gain_e;
architecture simple of gain_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
begin
vout == k*vin;
end architecture simple;
--
-------------------------------------------------------------------------------
-- S-Domain Limiter Model
--
-------------------------------------------------------------------------------
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
entity limiter_2_e is
generic (
limit_high : real := 4.8; -- upper limit
limit_low : real := -4.8); -- lower limit
port (
terminal input: electrical;
terminal output: electrical);
end entity limiter_2_e;
architecture simple of limiter_2_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
constant slope : real := 1.0e-4;
begin
if vin > limit_high use -- Upper limit exceeded, so limit input signal
vout == limit_high + slope*(vin - limit_high);
elsif vin < limit_low use -- Lower limit exceeded, so limit input signal
vout == limit_low + slope*(vin - limit_low);
else -- No limit exceeded, so pass input signal as is
vout == vin;
end use;
break on vin'above(limit_high), vin'above(limit_low);
end architecture simple;
--
-------------------------------------------------------------------------------
-- Lead-Lag Filter
--
-- Transfer Function:
--
-- (s + w1)
-- H(s) = k * ----------
-- (s + w2)
--
-- DC Gain = k*w1/w2
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE;
use ieee.math_real.all;
entity lead_lag_e is
generic (
k: real := 1.0; -- Gain multiplier
f1: real := 10.0; -- First break frequency (zero)
f2: real := 100.0); -- Second break frequency (pole)
port ( terminal input: electrical;
terminal output: electrical);
end entity lead_lag_e;
architecture simple of lead_lag_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
quantity vin_temp : real;
constant w1 : real := f1*math_2_pi;
constant w2 : real := f2*math_2_pi;
constant num : real_vector := (w1, 1.0);
constant den : real_vector := (w2, 1.0);
begin
vin_temp == vin;
vout == k*vin_temp'ltf(num, den);
end architecture simple;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity rudder_servo is
port(
terminal servo_in : electrical;
terminal pos_fb : electrical;
terminal servo_out : electrical
);
end rudder_servo;
architecture rudder_servo of rudder_servo is
-- Component declarations
-- Signal declarations
terminal error : electrical;
terminal ll_in : electrical;
terminal ll_out : electrical;
terminal summer_fb : electrical;
begin
-- Signal assignments
-- Component instances
summer : entity work.sum2_e(simple)
port map(
in1 => servo_in,
in2 => summer_fb,
output => error
);
forward_gain : entity work.gain_e(simple)
generic map(
k => 100.0
)
port map(
input => error,
output => ll_in
);
fb_gain : entity work.gain_e(simple)
generic map(
k => -4.57
)
port map(
input => pos_fb,
output => summer_fb
);
XCMP21 : entity work.limiter_2_e(simple)
generic map(
limit_high => 4.8,
limit_low => -4.8
)
port map(
input => ll_out,
output => servo_out
);
XCMP22 : entity work.lead_lag_e(simple)
generic map(
f2 => 2000.0,
f1 => 5.0,
k => 400.0
)
port map(
input => ll_in,
output => ll_out
);
end rudder_servo;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : gear_rv_r.vhd
-- Author : Mentor Graphics
-- Created : 2001/10/10
-- Last update: 2002/05/21
-------------------------------------------------------------------------------
-- Description: Gear Model (ROTATIONAL_V/ROTATIONAL domains)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/10/10 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity gear_rv_r is
generic(
ratio : real := 1.0); -- Gear ratio (Revs of shaft2 for 1 rev of shaft1)
-- Note: can be negative, if shaft polarity changes
port ( terminal rotv1 : rotational_v;
terminal rot2 : rotational);
end entity gear_rv_r;
-------------------------------------------------------------------------------
-- Ideal Architecture
-------------------------------------------------------------------------------
architecture ideal of gear_rv_r is
quantity w1 across torq_vel through rotv1 to rotational_v_ref;
-- quantity w2 across torq2 through rotv2 to rotational_v_ref;
quantity theta across torq_ang through rot2 to rotational_ref;
begin
-- w2 == w1*ratio;
theta == ratio*w1'integ;
torq_vel == -1.0*torq_ang*ratio;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- Rotational to Electrical Converter
--
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.electrical_systems.all;
entity rot2v is
generic (
k : real := 1.0); -- optional gain
port (
terminal input : rotational; -- input terminal
terminal output : electrical); -- output terminal
end entity rot2v ;
architecture bhv of rot2v is
quantity rot_in across input to rotational_ref; -- Converter's input branch
quantity v_out across out_i through output to electrical_ref;-- Converter's output branch
begin -- bhv
v_out == k*rot_in;
end bhv;
--
-------------------------------------------------------------------------------
-- Control Horn for Rudder Control (mechanical implementation)
--
-- Transfer Function:
--
-- tran = R*sin(rot)
--
-- Where pos = output translational position,
-- R = horn radius,
-- theta = input rotational angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity horn_r2t is
generic (
R : real := 1.0); -- horn radius
port (
terminal theta : ROTATIONAL; -- input angular position port
terminal pos : TRANSLATIONAL); -- output translational position port
end entity horn_r2t;
architecture bhv of horn_r2t is
QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
begin -- bhv
tran == R*sin(rot); -- Convert angle in to translational out
tran_frc == -rot_tq/R; -- Convert torque in to force out
end bhv;
--
-------------------------------------------------------------------------------
-- Control Horn for Rudder Control (mechanical implementation)
--
-- Transfer Function:
--
-- theta = arcsin(pos/R)
--
-- Where pos = input translational position,
-- R = horn radius,
-- theta = output rotational angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity horn_t2r is
generic (
R : real := 1.0); -- Rudder horn radius
port (
terminal pos : translational; -- input translational position port
terminal theta : rotational); -- output angular position port
end entity horn_t2r ;
architecture bhv of horn_t2r is
QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
begin -- bhv
rot == arcsin(tran/R); -- Convert translational to angle
rot_tq == -tran_frc*R; -- Convert force to torque
end bhv;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : DC_Motor.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: Basic DC Motor
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.electrical_systems.all;
entity DC_Motor is
generic (
r_wind : resistance; -- Motor winding resistance [Ohm]
kt : real; -- Torque coefficient [N*m/Amp]
l : inductance; -- Winding inductance [Henrys]
d : real; -- Damping coefficient [N*m/(rad/sec)]
j : mmoment_i); -- Moment of inertia [kg*meter**2]
port (terminal p1, p2 : electrical;
terminal shaft_rotv : rotational_v);
end entity DC_Motor;
-------------------------------------------------------------------------------
-- Basic Architecture
-- Motor equations: V = Kt*W + I*Rwind + L*dI/dt
-- T = -Kt*I + D*W + J*dW/dt
-------------------------------------------------------------------------------
architecture basic of DC_Motor is
quantity v across i through p1 to p2;
quantity w across torq through shaft_rotv to rotational_v_ref;
begin
torq == -1.0*kt*i + d*w + j*w'dot;
v == kt*w + i*r_wind + l*i'dot;
end architecture basic;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : stop_r.vhd
-- Author : Mentor Graphics
-- Created : 2001/10/10
-- Last update: 2001/10/10
-------------------------------------------------------------------------------
-- Description: Mechanical Hard Stop (ROTATIONAL domain)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.MECHANICAL_SYSTEMS.all;
entity stop_r is
generic (
k_stop : real;
-- ang_max : angle;
-- ang_min : angle := 0.0;
ang_max : real;
ang_min : real := 0.0;
damp_stop : real := 0.000000001
);
port ( terminal ang1, ang2 : rotational);
end entity stop_r;
architecture ideal of stop_r is
quantity velocity : velocity;
quantity ang across trq through ang1 to ang2;
begin
velocity == ang'dot;
if ang'above(ang_max) use
trq == k_stop * (ang - ang_max) + (damp_stop * velocity);
elsif ang'above(ang_min) use
trq == 0.0;
else
trq == k_stop * (ang - ang_min) + (damp_stop * velocity);
end use;
break on ang'above(ang_min), ang'above(ang_max);
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity tran_linkage is
port
(
terminal p1, p2 : translational
);
begin
end tran_linkage;
architecture a1 of tran_linkage is
QUANTITY pos_1 across frc_1 through p1 TO translational_ref;
QUANTITY pos_2 across frc_2 through p2 TO translational_ref;
begin
pos_2 == pos_1; -- Pass position
frc_2 == -frc_1; -- Pass force
end;
--
-------------------------------------------------------------------------------
-- Rudder Model (Rotational Spring)
--
-- Transfer Function:
--
-- torq = -k*(theta - theta_0)
--
-- Where theta = input rotational angle,
-- torq = output rotational angle,
-- theta_0 = reference angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity rudder is
generic (
k : real := 1.0; -- Spring constant
theta_0 : real := 0.0);
port (
terminal rot : rotational); -- input rotational angle
end entity rudder;
architecture bhv of rudder is
QUANTITY theta across torq through rot TO ROTATIONAL_REF;
begin -- bhv
torq == k*(theta - theta_0); -- Convert force to torque
end bhv;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Electrical Resistor Model
-- Use proposed IEEE natures and packages
LIBRARY IEEE_proposed;
USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
ENTITY resistor IS
-- Initialize parameters
GENERIC (
res : RESISTANCE); -- resistance (no initial value)
-- Define ports as electrical terminals
PORT (
TERMINAL p1, p2 : ELECTRICAL);
END ENTITY resistor;
-- Ideal Architecture (V = I*R)
ARCHITECTURE ideal OF resistor IS
-- Declare Branch Quantities
QUANTITY v ACROSS i THROUGH p1 TO p2;
BEGIN
-- Characteristic equations
v == i*res;
END ARCHITECTURE ideal;
--
library ieee_proposed;
use ieee_proposed.electrical_systems.all;
entity amp_lim is
port (terminal ps : electrical; -- positive supply terminal
terminal input, output : electrical);
end entity amp_lim;
architecture simple of amp_lim is
quantity v_pwr across i_pwr through ps to electrical_ref;
quantity vin across iin through input to electrical_ref;
quantity vout across iout through output to electrical_ref;
quantity v_amplified : voltage ;
constant gain : real := 1.0;
begin
v_amplified == gain*vin;
if v_amplified > v_pwr use
vout == v_pwr;
else
vout == v_amplified;
end use;
-- ignore loading effects
i_pwr == 0.0;
iin == 0.0;
end architecture simple;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : v_pulse.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/07/09
-------------------------------------------------------------------------------
-- Description: Voltage Pulse Source
-- Includes Frequency Domain settings
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-- 2001/07/09 1.1 Mentor Graphics Changed input parameters to type
-- time. Uses time2real function.
-- Pulsewidth no longer includes
-- rise and fall times.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity v_pulse is
generic (
initial : voltage := 0.0; -- initial value [Volts]
pulse : voltage; -- pulsed value [Volts]
ti2p : time := 1ns; -- initial to pulse [Sec]
tp2i : time := 1ns; -- pulse to initial [Sec]
delay : time := 0ms; -- delay time [Sec]
width : time; -- duration of pulse [Sec]
period : time; -- period [Sec]
ac_mag : voltage := 1.0; -- AC magnitude [Volts]
ac_phase : real := 0.0); -- AC phase [Degrees]
port (
terminal pos, neg : electrical);
end entity v_pulse;
-------------------------------------------------------------------------------
-- Ideal Architecture
-------------------------------------------------------------------------------
architecture ideal of v_pulse is
-- Declare Through and Across Branch Quantities
quantity v across i through pos to neg;
-- Declare quantity in frequency domain for AC analysis
quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
-- Signal used in CreateEvent process below
signal pulse_signal : voltage := initial;
-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
-- Note: these lines gave an error during simulation. Had to use a
-- function call instead.
-- constant ri2p : real := time'pos(ti2p) * 1.0e-15;
-- constant rp2i : real := time'pos(tp2i) * 1.0e-15;
-- Function to convert numbers of type TIME to type REAL
function time2real(tt : time) return real is
begin
return time'pos(tt) * 1.0e-15;
end time2real;
-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
constant ri2p : real := time2real(ti2p);
constant rp2i : real := time2real(tp2i);
begin
if domain = quiescent_domain or domain = time_domain use
v == pulse_signal'ramp(ri2p, rp2i); -- create rise and fall transitions
else
v == ac_spec; -- used for Frequency (AC) analysis
end use;
-- purpose: Create events to define pulse shape
-- type : combinational
-- inputs :
-- outputs: pulse_signal
CreateEvent : process
begin
wait for delay;
loop
pulse_signal <= pulse;
wait for (width + ti2p);
pulse_signal <= initial;
wait for (period - width - ti2p);
end loop;
end process CreateEvent;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
library ieee;
use ieee.math_real.all;
package pwl_full_functions is
function next_increment(x : in real; xdata : in real_vector )
return real;
function interpolate (x,y2,y1,x2,x1 : in real)
return real;
function pwl_dim1_flat (x : in real; xdata, ydata : in real_vector )
return real;
end package pwl_full_functions;
package body pwl_full_functions is
function next_increment(x : in real; xdata : in real_vector)
return real is
variable i : integer;
begin
i := 0;
while i <= xdata'right loop
if x >= xdata(i) - 6.0e-15 then -- The value 6.0e-15 envelopes round-off error
-- of real-to-time conversion in calling model
i := i + 1;
else
return xdata(i) - xdata(i - 1);
end if;
end loop;
return 1.0; -- Returns a "large number" relative to expected High-Speed time scale
end function next_increment;
function interpolate (x,y2,y1,x2,x1 : in real)
return real is
variable m, yvalue : real;
begin
assert (x1 /= x2)
report "interpolate: x1 cannot be equal to x2"
severity error;
assert (x >= x1) and (x <= x2)
report "interpolate: x must be between x1 and x2, inclusively "
severity error;
m := (y2 - y1)/(x2 - x1);
yvalue := y1 + m*(x - x1);
return yvalue;
end function interpolate;
-- Created a new pwl_dim1_flat function that returns a constant
-- value of ydata(0) if x < xdata(0), or ydata(ydata'right) if x > xdata(xdata'right)
function pwl_dim1_flat (x : in real; xdata, ydata : in real_vector )
return real is
variable xvalue, yvalue, m : real;
variable start, fin, mid: integer;
begin
if x >= xdata(xdata'right) then
yvalue := ydata(ydata'right);
return yvalue;
end if;
if x <= xdata(0) then
yvalue := ydata(0);
return yvalue;
end if;
start:=0;
fin:=xdata'right;
-- I assume that the valid elements are from xdata(0) to xdata(fin), inclusive.
-- so fin==n-1 in C terms (where n is the size of the array).
while start <=fin loop
mid:=(start+fin)/2;
if xdata(mid) < x
then start:=mid+1;
else fin:=mid-1;
end if;
end loop;
if xdata(mid) > x
then mid:=mid-1;
end if;
yvalue := interpolate(x,ydata(mid+1),ydata(mid),xdata(mid+1),xdata(mid));
return yvalue;
end function pwl_dim1_flat;
end package body pwl_full_functions;
-- Not sure the sync_tdata process is necessary. Requires the tdata set contain
-- a larger value than the actual simulation time.
-- Piece-wise linear voltage source model
library IEEE;
use IEEE.std_logic_1164.all;
Library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use work.pwl_full_functions.all;
entity v_pwl_full is
generic (
vdata : real_vector; -- v-pulse data
tdata : real_vector -- time-data for v-pulse
);
port (
terminal pos, neg : electrical
);
end entity v_pwl_full;
architecture ideal of v_pwl_full is
QUANTITY v across i through pos TO neg;
signal tick : std_logic := '0'; -- Sync signal for tdata "tracking"
begin
sync_tdata: process is
variable next_tick_delay : real := 0.0; -- Time increment to the next time-point in tdata
begin
wait until domain = time_domain;
loop
next_tick_delay := next_increment(NOW,tdata);
tick <= (not tick) after (integer(next_tick_delay * 1.0e15) * 1 fs);
wait on tick;
end loop;
end process sync_tdata;
break on tick; -- Forces analog solution point at all tdata time-points
v == pwl_dim1_flat(NOW, tdata, vdata);
end architecture ideal;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.fluidic_systems.all;
use IEEE_proposed.thermal_systems.all;
use IEEE_proposed.radiant_systems.all;
entity tb_CS5_Amp_Lim is
end tb_CS5_Amp_Lim;
architecture TB_CS5_Amp_Lim of tb_CS5_Amp_Lim is
-- Component declarations
-- Signal declarations
terminal amp_in : electrical;
terminal gear_out : rotational;
terminal link_in : translational;
terminal link_out : translational;
terminal mot_in : electrical;
terminal mot_out : rotational_v;
terminal pos_fb_v : electrical;
terminal power : electrical;
terminal rudder_in : rotational;
terminal src_in : electrical;
terminal XSIG010068 : electrical;
begin
-- Signal assignments
-- Component instances
rudder_servo1 : entity work.rudder_servo
port map(
servo_out => amp_in,
servo_in => src_in,
pos_fb => pos_fb_v
);
gear3 : entity work.gear_rv_r(ideal)
generic map(
ratio => 0.01
)
port map(
rotv1 => mot_out,
rot2 => gear_out
);
r2v : entity work.rot2v(bhv)
generic map(
k => 1.0
)
port map(
output => pos_fb_v,
input => gear_out
);
r2t : entity work.horn_r2t(bhv)
port map(
theta => gear_out,
pos => link_in
);
t2r : entity work.horn_t2r(bhv)
port map(
theta => rudder_in,
pos => link_out
);
motor1 : entity work.DC_Motor(basic)
generic map(
j => 168.0e-9,
d => 5.63e-6,
l => 2.03e-3,
kt => 3.43e-3,
r_wind => 2.2
)
port map(
p1 => mot_in,
p2 => ELECTRICAL_REF,
shaft_rotv => mot_out
);
stop1 : entity work.stop_r(ideal)
generic map(
ang_min => -1.05,
ang_max => 1.05,
k_stop => 1.0e6,
damp_stop => 1.0e2
)
port map(
ang1 => gear_out,
ang2 => ROTATIONAL_REF
);
XCMP35 : entity work.tran_linkage(a1)
port map(
p2 => link_out,
p1 => link_in
);
XCMP36 : entity work.rudder(bhv)
generic map(
k => 0.2
)
port map(
rot => rudder_in
);
R2w : entity work.resistor(ideal)
generic map(
res => 1000.0
)
port map(
p1 => XSIG010068,
p2 => ELECTRICAL_REF
);
XCMP55 : entity work.amp_lim(simple)
port map(
input => amp_in,
output => mot_in,
ps => power
);
v9 : entity work.v_pulse(ideal)
generic map(
initial => 0.0,
pulse => 4.8,
ti2p => 300ms,
tp2i => 300ms,
delay => 100ms,
width => 5ms,
period => 605ms
)
port map(
pos => src_in,
neg => ELECTRICAL_REF
);
XCMP57 : entity work.v_pwl_full(ideal)
generic map(
tdata => (0.0,100.0e-3,400.0e-3,900.0e-3,1300.0e-3,1800.0e-3,2300.0e-3,2600.0e-3, 2900.0e-3),
vdata => (0.0,0.0,2.4,2.4,4.7,4.7,1.0,1.0,0.0)
)
port map(
pos => XSIG010068,
neg => ELECTRICAL_REF
);
XCMP60 : entity work.v_pwl_full(ideal)
generic map(
vdata => (4.8,4.8,4.4,4.4,4.0,4.0,3.6,3.6,3.2,3.2),
tdata => (0.0,705.0e-3,706.0e-3,1310.0e-3,1320.0e-3,1915.0e-3,1925.0e-3,2520.0e-3,2530.0e-3,3125.0e-3)
)
port map(
pos => power,
neg => ELECTRICAL_REF
);
end TB_CS5_Amp_Lim;
--
|
gpl-2.0
|
01d936165db72200a99039992246b6e9
| 0.576824 | 4.113003 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_10_alu-b.vhd
| 4 | 2,669 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_10_alu-b.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library bv_utilities;
use bv_utilities.bv_arithmetic.all;
architecture behavior of alu is
begin
alu_op: process (s1, s2, func) is
constant Tpd : delay_length := 10 ns;
variable bv_s1 : bit_vector(s1'range) := To_bitvector(s1);
variable bv_s2 : bit_vector(s2'range) := To_bitvector(s2);
variable temp_result : bit_vector(result'range);
constant zero_result : bit_vector(result'range) := (others => '0');
variable temp_overflow : boolean;
type boolean_to_X01_table is array (boolean) of X01;
constant boolean_to_X01 : boolean_to_X01_table
:= ( false => '0', true => '1' );
begin
case func is
when alu_add =>
bv_add(bv_s1, bv_s2, temp_result, temp_overflow);
when alu_addu =>
bv_addu(bv_s1, bv_s2, temp_result, temp_overflow);
when alu_sub =>
bv_sub(bv_s1, bv_s2, temp_result, temp_overflow);
when alu_subu =>
bv_subu(bv_s1, bv_s2, temp_result, temp_overflow);
when others =>
report "alu: illegal function code" severity error;
temp_result := X"0000_0000";
end case;
result <= To_X01(temp_result) after Tpd;
zero <= boolean_to_X01(temp_result = zero_result) after Tpd;
negative <= To_X01(temp_result(temp_result'left)) after Tpd;
overflow <= boolean_to_X01(temp_overflow) after Tpd;
end process alu_op;
end architecture behavior;
|
gpl-2.0
|
399a9469e1c6757ab6aae508d6969da9
| 0.568003 | 3.965825 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/scheduler.vhd
| 4 | 3,435 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity scheduler is
end entity scheduler;
architecture test of scheduler is
constant scheduling_delay : delay_length := 5 ns;
subtype request_type is natural range 0 to 20;
type server_status_type is (ready, busy);
signal first_priority_request,
first_normal_request,
reset_request : request_type := 0;
signal functional_request, equivalent_request : request_type;
signal priority_waiting : boolean := false;
signal server_status : server_status_type := busy;
begin
functional_scheduler : block is
port ( request : out request_type );
port map ( request => functional_request );
begin
-- code from book
scheduler :
request <= first_priority_request after scheduling_delay
when priority_waiting and server_status = ready else
first_normal_request after scheduling_delay
when not priority_waiting and server_status = ready else
unaffected
when server_status = busy else
reset_request after scheduling_delay;
-- end code from book
end block functional_scheduler;
--------------------------------------------------
equivalent_scheduler : block is
port ( request : out request_type );
port map ( request => equivalent_request );
begin
-- code from book
scheduler : process is
begin
if priority_waiting and server_status = ready then
request <= first_priority_request after scheduling_delay;
elsif not priority_waiting and server_status = ready then
request <= first_normal_request after scheduling_delay;
elsif server_status = busy then
null;
else
request <= reset_request after scheduling_delay;
end if;
wait on first_priority_request, priority_waiting, server_status,
first_normal_request, reset_request;
end process scheduler;
-- end code from book
end block equivalent_scheduler;
--------------------------------------------------
stimulus : process is
begin
first_priority_request <= 10; wait for 20 ns;
first_normal_request <= 5; wait for 20 ns;
server_status <= ready; wait for 20 ns;
server_status <= busy; wait for 20 ns;
priority_waiting <= true; wait for 20 ns;
server_status <= ready; wait for 20 ns;
first_normal_request <= 7; wait for 20 ns;
first_priority_request <= 12; wait for 20 ns;
wait;
end process stimulus;
verifier :
assert functional_request = equivalent_request
report "Functional and equivalent models give different results";
end architecture test;
|
gpl-2.0
|
f3cb7eb85573d5b0e569f6e93708bc97
| 0.661718 | 4.549669 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/clifton-labs/compliant/functional/std_logic_1164/test_xor_table.vhdl
| 4 | 1,983 |
entity test is
end test;
library ieee;
use ieee.std_logic_1164.all;
package foo is
TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;
-- truth table for "xor" function
CONSTANT xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - |
);
end foo;
use work.foo.all;
library ieee;
use ieee.std_logic_1164.all;
architecture only of test is
begin -- only
process
begin -- process
assert xor_table( 'U', 'U' ) = 'U' report "TEST FAILED-UxU";
assert xor_table( 'U', 'X' ) = 'U' report "TEST FAILED-UxX";
assert xor_table( 'X', '-' ) = 'X' report "TEST FAILED-Xx-";
assert xor_table( '0', '1' ) = '1' report "TEST FAILED-0x1";
assert xor_table( 'H', 'Z' ) = 'X' report "TEST FAILED-HxZ";
assert xor_table( 'Z', 'W' ) = 'X' report "TEST FAILED-ZxW";
assert xor_table( 'L', '1' ) = '1' report "TEST FAILED-Lx1";
assert xor_table( 'H', '1' ) = '0' report "TEST FAILED-Hx1";
assert xor_table( '0', 'L' ) = '0' report "TEST FAILED-0xL";
assert xor_table( 'Z', 'L' ) = 'X' report "TEST FAILED-ZxL";
assert xor_table( 'Z', 'H' ) = 'X' report "TEST FAILED-ZxH";
wait;
end process;
end only;
|
gpl-2.0
|
4aad04297520ba5f5ab30f1203258028
| 0.396369 | 2.640479 | false | true | false | false |
peteut/ghdl
|
testsuite/gna/perf02/sub_144.vhd
| 3 | 1,782 |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_144 is
port (
output : out std_logic_vector(63 downto 0);
le : out std_logic;
sign : in std_logic;
ge : out std_logic;
in_a : in std_logic_vector(63 downto 0);
in_b : in std_logic_vector(63 downto 0)
);
end sub_144;
architecture augh of sub_144 is
signal carry_inA : std_logic_vector(65 downto 0);
signal carry_inB : std_logic_vector(65 downto 0);
signal carry_res : std_logic_vector(65 downto 0);
-- Signals to generate the comparison outputs
signal msb_abr : std_logic_vector(2 downto 0);
signal tmp_sign : std_logic;
signal tmp_eq : std_logic;
signal tmp_le : std_logic;
signal tmp_ge : std_logic;
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
output <= carry_res(64 downto 1);
-- Other comparison outputs
-- Temporary signals
msb_abr <= in_a(63) & in_b(63) & carry_res(64);
tmp_sign <= sign;
tmp_eq <= '1' when in_a = in_b else '0';
tmp_le <=
tmp_eq when msb_abr = "000" or msb_abr = "110" else
'1' when msb_abr = "001" else
'1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "001" or msb_abr = "111") else
'1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else
'0';
tmp_ge <=
'1' when msb_abr = "000" or msb_abr = "110" else
'1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else
'1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011" or msb_abr = "111") else
'0';
ge <= tmp_ge;
le <= tmp_le;
end architecture;
|
gpl-2.0
|
4c17441b48658db7d747de89bad99b48
| 0.621773 | 2.564029 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc16.vhd
| 4 | 2,000 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc16.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s02b00x00p06n03i00016ent IS
END c04s02b00x00p06n03i00016ent;
ARCHITECTURE c04s02b00x00p06n03i00016arch OF c04s02b00x00p06n03i00016ent IS
BEGIN
TESTING: PROCESS
-- Define a subtype of a subtype.
subtype ZERO is NATURAL;
-- Define variables of these subtypes.
variable ZEROV : ZERO := 0;
variable NATURALV : NATURAL := 0;
BEGIN
-- Verify that these two variables have the same base type.
assert NOT( Naturalv = zerov and zerov = zero'low )
report "***PASSED TEST: c04s02b00x00p06n03i00016"
severity NOTE;
assert ( Naturalv = zerov and zerov = zero'low )
report "***FAILED TEST: c04s02b00x00p06n03i00016 - The base type of a subtype is the base type of the type mark."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s02b00x00p06n03i00016arch;
|
gpl-2.0
|
627ea4a3afed679de967790c01cc984e
| 0.6725 | 3.802281 | false | true | false | false |
stnolting/neo430
|
rtl/top_templates/neo430_test.vhd
| 1 | 8,171 |
-- #################################################################################################
-- # << NEO430 - Processor Test Implementation (neo430_test.vhd) >> #
-- # ********************************************************************************************* #
-- # If you do not have an own design (yet), you can use this unit as top entity to play with #
-- # the NEO430 processor. Take a look at the project's documentary (chapter "Let's Get It #
-- # Started!") to get more information. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
entity neo430_test is
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
rst_i : in std_ulogic; -- global reset, async, LOW-active
-- parallel io --
gpio_o : out std_ulogic_vector(07 downto 0); -- parallel output
-- serial com --
uart_txd_o : out std_ulogic; -- UART send data
uart_rxd_i : in std_ulogic -- UART receive data
);
end neo430_test;
architecture neo430_test_rtl of neo430_test is
-- local signals --
signal gpio_out : std_ulogic_vector(15 downto 0);
signal rst_int : std_ulogic;
begin
-- The Core of the Problem --------------------------------------------------
-- -----------------------------------------------------------------------------
neo430_top_test_inst: neo430_top
generic map (
-- general configuration --
CLOCK_SPEED => 100000000, -- main clock in Hz
IMEM_SIZE => 4*1024, -- internal IMEM size in bytes, max 48kB (default=4kB)
DMEM_SIZE => 2*1024, -- internal DMEM size in bytes, max 12kB (default=2kB)
-- additional configuration --
USER_CODE => x"CAFE", -- custom user code
-- module configuration --
MULDIV_USE => true, -- implement multiplier/divider unit? (default=true)
WB32_USE => true, -- implement WB32 unit? (default=true)
WDT_USE => true, -- implement WDT? (default=true)
GPIO_USE => true, -- implement GPIO unit? (default=true)
TIMER_USE => true, -- implement timer? (default=true)
UART_USE => true, -- implement UART? (default=true)
CRC_USE => true, -- implement CRC unit? (default=true)
CFU_USE => false, -- implement custom functions unit? (default=false)
PWM_USE => true, -- implement PWM controller? (default=true)
TWI_USE => true, -- implement two wire serial interface? (default=true)
SPI_USE => true, -- implement SPI? (default=true)
TRNG_USE => false, -- implement TRNG? (default=false)
EXIRQ_USE => true, -- implement EXIRQ? (default=true)
FREQ_GEN_USE => true, -- implement FREQ_GEN? (default=true)
-- boot configuration --
BOOTLD_USE => true, -- implement and use bootloader? (default=true)
IMEM_AS_ROM => false -- implement IMEM as read-only memory? (default=false)
)
port map (
-- global control --
clk_i => clk_i, -- global clock, rising edge
rst_i => rst_int, -- global reset, async, low-active
-- gpio --
gpio_o => gpio_out, -- parallel output
gpio_i => x"0000", -- parallel input
-- pwm channels --
pwm_o => open, -- pwm channels
-- arbitrary frequency generator --
freq_gen_o => open, -- programmable frequency output
-- serial com --
uart_txd_o => uart_txd_o, -- UART send data
uart_rxd_i => uart_rxd_i, -- UART receive data
spi_sclk_o => open, -- serial clock line
spi_mosi_o => open, -- serial data line out
spi_miso_i => '0', -- serial data line in
spi_cs_o => open, -- SPI CS
twi_sda_io => open, -- twi serial data line
twi_scl_io => open, -- twi serial clock line
-- 32-bit wishbone interface --
wb_adr_o => open, -- address
wb_dat_i => x"00000000", -- read data
wb_dat_o => open, -- write data
wb_we_o => open, -- read/write
wb_sel_o => open, -- byte enable
wb_stb_o => open, -- strobe
wb_cyc_o => open, -- valid cycle
wb_ack_i => '0', -- transfer acknowledge
-- external interrupts --
ext_irq_i => "00000000", -- external interrupt request lines
ext_ack_o => open -- external interrupt request acknowledges
);
-- constrain output signals --
gpio_o <= gpio_out(7 downto 0);
-- internal reset (must be low-active!) --
rst_int <= rst_i; -- invert me?!
end neo430_test_rtl;
|
bsd-3-clause
|
52a836f3681d6c9673f0ca4e02abd5d2
| 0.460898 | 4.881123 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc521.vhd
| 4 | 50,322 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc521.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
PACKAGE c03s03b00x00p03n04i00521pkg IS
--
-- Index types for array declarations
--
SUBTYPE st_ind1 IS INTEGER RANGE 1 TO 8; -- index from 1 (POSITIVE)
SUBTYPE st_ind2 IS INTEGER RANGE 0 TO 3; -- index from 0 (NATURAL)
SUBTYPE st_ind3 IS CHARACTER RANGE 'a' TO 'd'; -- non-INTEGER index
SUBTYPE st_ind4 IS INTEGER RANGE 0 DOWNTO -3; -- descending range
--
-- Scalar type for subelements
--
SUBTYPE st_scl1 IS CHARACTER ;
SUBTYPE st_scl3 IS INTEGER RANGE 1 TO INTEGER'HIGH;
SUBTYPE st_scl4 IS REAL RANGE 0.0 TO 1024.0;
-- -----------------------------------------------------------------------------------------
-- Composite type declarations
-- -----------------------------------------------------------------------------------------
--
-- Records of scalars
--
TYPE t_scre_1 IS RECORD
left : st_scl1;
second : TIME;
third : st_scl3;
right : st_scl4;
END RECORD;
--
-- Unconstrained arrays of scalars
--
TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF st_scl1;
TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF TIME;
TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF st_scl3;
TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF st_scl4;
TYPE t_usa2_1 IS ARRAY (st_ind2 RANGE <>,
st_ind1 RANGE <>) OF st_scl1;
TYPE t_usa3_1 IS ARRAY (st_ind3 RANGE <>,
st_ind2 RANGE <>,
st_ind1 RANGE <>) OF st_scl1;
TYPE t_usa4_1 IS ARRAY (st_ind4 RANGE <>,
st_ind3 RANGE <>,
st_ind2 RANGE <>,
st_ind1 RANGE <>) OF st_scl1;
--
--
-- Constrained arrays of scalars (make compatable with unconstrained types
--
SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1 );
SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2 );
SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3 );
SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4 );
SUBTYPE t_csa2_1 IS t_usa2_1 (st_ind2 , -- ( i2, i1 ) of CHAR
st_ind1 );
SUBTYPE t_csa3_1 IS t_usa3_1 (st_ind3 , -- ( i3, i2, i1) of CHAR
st_ind2 ,
st_ind1 );
SUBTYPE t_csa4_1 IS t_usa4_1 (st_ind4 , -- ( i4, i3, i2, i1 ) of CHAR
st_ind3 ,
st_ind2 ,
st_ind1 );
--
--
-- constrained arrays of composites
--
TYPE t_cca1_1 IS ARRAY (st_ind1) OF t_scre_1; -- ( i1 ) is RECORD of scalar
TYPE t_cca1_2 IS ARRAY (st_ind2) OF t_csa1_1; -- ( i2 )( i1 ) is CHAR
TYPE t_cca1_3 IS ARRAY (st_ind3) OF t_cca1_2; -- ( i3 )( i2 )( i1 ) is CHAR
TYPE t_cca1_4 IS ARRAY (st_ind4) OF t_cca1_3; -- ( i4 )( i3 )( i2 )( i1 ) is CHAR
TYPE t_cca2_1 IS ARRAY (st_ind3) OF t_csa2_1; -- ( i3 )( i2, i1 ) is CHAR
TYPE t_cca2_2 IS ARRAY (st_ind4, -- ( i4, i3 )( i2, i1 ) of CHAR
st_ind3) OF t_csa2_1;
TYPE t_cca3_1 IS ARRAY (st_ind4, -- ( i4, i3, i2 )( i1 ) of CHAR
st_ind3,
st_ind2) OF t_csa1_1;
TYPE t_cca3_2 IS ARRAY (st_ind4) OF t_csa3_1; -- ( i4 )( i3, i2, i1 ) is CHAR
--
-- Records of composites
--
TYPE t_cmre_1 IS RECORD
left : t_csa1_1; -- .fN(i1) is CHAR
second : t_scre_1; -- .fN.fN
END RECORD;
TYPE t_cmre_2 IS RECORD
left ,
second ,
third ,
right : t_csa1_1; -- .fN(i1) is CHAR
END RECORD;
--
-- Mixed Records/arrays
--
TYPE t_cca1_7 IS ARRAY (st_ind3) OF t_cmre_2; -- (i3).fN(i1) is CHAR
TYPE t_cmre_3 IS RECORD
left ,
second ,
third ,
right : t_cca1_7; -- .fN(i3).fN(i1) is CHAR
END RECORD;
--
-- TYPE declarations for resolution function (Constrained types only)
--
TYPE t_scre_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_scre_1;
TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
TYPE t_csa2_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa2_1;
TYPE t_csa3_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa3_1;
TYPE t_csa4_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa4_1;
TYPE t_cca1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_1;
TYPE t_cca1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_2;
TYPE t_cca1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_3;
TYPE t_cca1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_4;
TYPE t_cca2_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca2_1;
TYPE t_cca2_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca2_2;
TYPE t_cca3_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca3_1;
TYPE t_cca3_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca3_2;
TYPE t_cmre_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_1;
TYPE t_cmre_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_2;
TYPE t_cca1_7_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_7;
TYPE t_cmre_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_3;
--
-- Declaration of Resolution Functions
--
FUNCTION rf_scre_1 ( v: t_scre_1_vct ) RETURN t_scre_1;
FUNCTION rf_csa1_1 ( v: t_csa1_1_vct ) RETURN t_csa1_1;
FUNCTION rf_csa1_2 ( v: t_csa1_2_vct ) RETURN t_csa1_2;
FUNCTION rf_csa1_3 ( v: t_csa1_3_vct ) RETURN t_csa1_3;
FUNCTION rf_csa1_4 ( v: t_csa1_4_vct ) RETURN t_csa1_4;
FUNCTION rf_csa2_1 ( v: t_csa2_1_vct ) RETURN t_csa2_1;
FUNCTION rf_csa3_1 ( v: t_csa3_1_vct ) RETURN t_csa3_1;
FUNCTION rf_csa4_1 ( v: t_csa4_1_vct ) RETURN t_csa4_1;
FUNCTION rf_cca1_1 ( v: t_cca1_1_vct ) RETURN t_cca1_1;
FUNCTION rf_cca1_2 ( v: t_cca1_2_vct ) RETURN t_cca1_2;
FUNCTION rf_cca1_3 ( v: t_cca1_3_vct ) RETURN t_cca1_3;
FUNCTION rf_cca1_4 ( v: t_cca1_4_vct ) RETURN t_cca1_4;
FUNCTION rf_cca2_1 ( v: t_cca2_1_vct ) RETURN t_cca2_1;
FUNCTION rf_cca2_2 ( v: t_cca2_2_vct ) RETURN t_cca2_2;
FUNCTION rf_cca3_1 ( v: t_cca3_1_vct ) RETURN t_cca3_1;
FUNCTION rf_cca3_2 ( v: t_cca3_2_vct ) RETURN t_cca3_2;
FUNCTION rf_cmre_1 ( v: t_cmre_1_vct ) RETURN t_cmre_1;
FUNCTION rf_cmre_2 ( v: t_cmre_2_vct ) RETURN t_cmre_2;
FUNCTION rf_cca1_7 ( v: t_cca1_7_vct ) RETURN t_cca1_7;
FUNCTION rf_cmre_3 ( v: t_cmre_3_vct ) RETURN t_cmre_3;
--
-- Resolved SUBTYPE declaration
--
SUBTYPE rst_scre_1 IS rf_scre_1 t_scre_1 ;
SUBTYPE rst_csa1_1 IS rf_csa1_1 t_csa1_1 ;
SUBTYPE rst_csa1_2 IS rf_csa1_2 t_csa1_2 ;
SUBTYPE rst_csa1_3 IS rf_csa1_3 t_csa1_3 ;
SUBTYPE rst_csa1_4 IS rf_csa1_4 t_csa1_4 ;
SUBTYPE rst_csa2_1 IS rf_csa2_1 t_csa2_1 ;
SUBTYPE rst_csa3_1 IS rf_csa3_1 t_csa3_1 ;
SUBTYPE rst_csa4_1 IS rf_csa4_1 t_csa4_1 ;
SUBTYPE rst_cca1_1 IS rf_cca1_1 t_cca1_1 ;
SUBTYPE rst_cca1_2 IS rf_cca1_2 t_cca1_2 ;
SUBTYPE rst_cca1_3 IS rf_cca1_3 t_cca1_3 ;
SUBTYPE rst_cca1_4 IS rf_cca1_4 t_cca1_4 ;
SUBTYPE rst_cca2_1 IS rf_cca2_1 t_cca2_1 ;
SUBTYPE rst_cca2_2 IS rf_cca2_2 t_cca2_2 ;
SUBTYPE rst_cca3_1 IS rf_cca3_1 t_cca3_1 ;
SUBTYPE rst_cca3_2 IS rf_cca3_2 t_cca3_2 ;
SUBTYPE rst_cmre_1 IS rf_cmre_1 t_cmre_1 ;
SUBTYPE rst_cmre_2 IS rf_cmre_2 t_cmre_2 ;
SUBTYPE rst_cca1_7 IS rf_cca1_7 t_cca1_7 ;
SUBTYPE rst_cmre_3 IS rf_cmre_3 t_cmre_3 ;
--
-- Functions declarations for multi-dimensional comosite values
--
FUNCTION F_csa2_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa2_1 ;
FUNCTION F_csa3_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa3_1 ;
FUNCTION F_csa4_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa4_1 ;
FUNCTION F_cca2_2 ( v0,v2 : IN t_csa2_1 ) RETURN t_cca2_2 ;
FUNCTION F_cca3_1 ( v0,v2 : IN t_csa1_1 ) RETURN t_cca3_1 ;
-- -------------------------------------------------------------------------------------------
-- Data values for Composite Types
-- -------------------------------------------------------------------------------------------
CONSTANT CX_scl1 : st_scl1 := 'X' ;
CONSTANT C0_scl1 : st_scl1 := st_scl1'LEFT ;
CONSTANT C1_scl1 : st_scl1 := 'A' ;
CONSTANT C2_scl1 : st_scl1 := 'Z' ;
CONSTANT CX_scl2 : TIME := 99 fs ;
CONSTANT C0_scl2 : TIME := TIME'LEFT ;
CONSTANT C1_scl2 : TIME := 0 fs;
CONSTANT C2_scl2 : TIME := 2 ns;
CONSTANT CX_scl3 : st_scl3 := 15 ;
CONSTANT C0_scl3 : st_scl3 := st_scl3'LEFT ;
CONSTANT C1_scl3 : st_scl3 := 6 ;
CONSTANT C2_scl3 : st_scl3 := 8 ;
CONSTANT CX_scl4 : st_scl4 := 99.9 ;
CONSTANT C0_scl4 : st_scl4 := st_scl4'LEFT ;
CONSTANT C1_scl4 : st_scl4 := 1.0 ;
CONSTANT C2_scl4 : st_scl4 := 2.1 ;
CONSTANT CX_scre_1 : t_scre_1 := ( CX_scl1, CX_scl2, CX_scl3, CX_scl4 );
CONSTANT C0_scre_1 : t_scre_1 := ( C0_scl1, C0_scl2, C0_scl3, C0_scl4 );
CONSTANT C1_scre_1 : t_scre_1 := ( C1_scl1, C1_scl2, C1_scl3, C1_scl4 );
CONSTANT C2_scre_1 : t_scre_1 := ( C2_scl1, C0_scl2, C0_scl3, C2_scl4 );
CONSTANT CX_csa1_1 : t_csa1_1 := ( OTHERS=>CX_scl1);
CONSTANT C0_csa1_1 : t_csa1_1 := ( OTHERS=>C0_scl1);
CONSTANT C1_csa1_1 : t_csa1_1 := ( OTHERS=>C1_scl1);
CONSTANT C2_csa1_1 : t_csa1_1 := ( t_csa1_1'LEFT|t_csa1_1'RIGHT=>C2_scl1,
OTHERS =>C0_scl1);
CONSTANT CX_csa1_2 : t_csa1_2 := ( OTHERS=>CX_scl2);
CONSTANT C0_csa1_2 : t_csa1_2 := ( OTHERS=>C0_scl2);
CONSTANT C1_csa1_2 : t_csa1_2 := ( OTHERS=>C1_scl2);
CONSTANT C2_csa1_2 : t_csa1_2 := ( t_csa1_2'LEFT|t_csa1_2'RIGHT=>C2_scl2,
OTHERS =>C0_scl2);
CONSTANT CX_csa1_3 : t_csa1_3 := ( OTHERS=>CX_scl3);
CONSTANT C0_csa1_3 : t_csa1_3 := ( OTHERS=>C0_scl3);
CONSTANT C1_csa1_3 : t_csa1_3 := ( OTHERS=>C1_scl3);
CONSTANT C2_csa1_3 : t_csa1_3 := ( t_csa1_3'LEFT|t_csa1_3'RIGHT=>C2_scl3,
OTHERS =>C0_scl3);
CONSTANT CX_csa1_4 : t_csa1_4 := ( OTHERS=>CX_scl4);
CONSTANT C0_csa1_4 : t_csa1_4 := ( OTHERS=>C0_scl4);
CONSTANT C1_csa1_4 : t_csa1_4 := ( OTHERS=>C1_scl4);
CONSTANT C2_csa1_4 : t_csa1_4 := ( t_csa1_4'LEFT|t_csa1_4'RIGHT=>C2_scl4,
OTHERS =>C0_scl4);
--
CONSTANT CX_csa2_1 : t_csa2_1 ;
CONSTANT C0_csa2_1 : t_csa2_1 ;
CONSTANT C1_csa2_1 : t_csa2_1 ;
CONSTANT C2_csa2_1 : t_csa2_1 ;
CONSTANT CX_csa3_1 : t_csa3_1 ;
CONSTANT C0_csa3_1 : t_csa3_1 ;
CONSTANT C1_csa3_1 : t_csa3_1 ;
CONSTANT C2_csa3_1 : t_csa3_1 ;
CONSTANT CX_csa4_1 : t_csa4_1 ;
CONSTANT C0_csa4_1 : t_csa4_1 ;
CONSTANT C1_csa4_1 : t_csa4_1 ;
CONSTANT C2_csa4_1 : t_csa4_1 ;
--
CONSTANT CX_cca1_1 : t_cca1_1 := ( OTHERS=>CX_scre_1 );
CONSTANT C0_cca1_1 : t_cca1_1 := ( OTHERS=>C0_scre_1 );
CONSTANT C1_cca1_1 : t_cca1_1 := ( OTHERS=>C1_scre_1 );
CONSTANT C2_cca1_1 : t_cca1_1 := ( C2_scre_1, C0_scre_1, C0_scre_1, C0_scre_1,
C0_scre_1, C0_scre_1, C0_scre_1, C2_scre_1 );
CONSTANT CX_cca1_2 : t_cca1_2 := ( OTHERS=>CX_csa1_1 );
CONSTANT C0_cca1_2 : t_cca1_2 := ( OTHERS=>C0_csa1_1 );
CONSTANT C1_cca1_2 : t_cca1_2 := ( OTHERS=>C1_csa1_1 );
CONSTANT C2_cca1_2 : t_cca1_2 := ( C2_csa1_1, C0_csa1_1, C0_csa1_1, C2_csa1_1 );
CONSTANT CX_cca1_3 : t_cca1_3 := ( OTHERS=>CX_cca1_2 );
CONSTANT C0_cca1_3 : t_cca1_3 := ( OTHERS=>C0_cca1_2 );
CONSTANT C1_cca1_3 : t_cca1_3 := ( OTHERS=>C1_cca1_2 );
CONSTANT C2_cca1_3 : t_cca1_3 := ( C2_cca1_2, C0_cca1_2, C0_cca1_2, C2_cca1_2 );
CONSTANT CX_cca1_4 : t_cca1_4 := ( OTHERS=>CX_cca1_3 );
CONSTANT C0_cca1_4 : t_cca1_4 := ( OTHERS=>C0_cca1_3 );
CONSTANT C1_cca1_4 : t_cca1_4 := ( OTHERS=>C1_cca1_3 );
CONSTANT C2_cca1_4 : t_cca1_4 := ( C2_cca1_3, C0_cca1_3, C0_cca1_3, C2_cca1_3 );
CONSTANT CX_cca2_1 : t_cca2_1 ;
CONSTANT C0_cca2_1 : t_cca2_1 ;
CONSTANT C1_cca2_1 : t_cca2_1 ;
CONSTANT C2_cca2_1 : t_cca2_1 ;
--
CONSTANT CX_cca2_2 : t_cca2_2 ;
CONSTANT C0_cca2_2 : t_cca2_2 ;
CONSTANT C1_cca2_2 : t_cca2_2 ;
CONSTANT C2_cca2_2 : t_cca2_2 ;
CONSTANT CX_cca3_1 : t_cca3_1 ;
CONSTANT C0_cca3_1 : t_cca3_1 ;
CONSTANT C1_cca3_1 : t_cca3_1 ;
CONSTANT C2_cca3_1 : t_cca3_1 ;
--
CONSTANT CX_cca3_2 : t_cca3_2 ;
CONSTANT C0_cca3_2 : t_cca3_2 ;
CONSTANT C1_cca3_2 : t_cca3_2 ;
CONSTANT C2_cca3_2 : t_cca3_2 ;
CONSTANT CX_cmre_1 : t_cmre_1 := ( CX_csa1_1, CX_scre_1 );
CONSTANT C0_cmre_1 : t_cmre_1 := ( C0_csa1_1, C0_scre_1 );
CONSTANT C1_cmre_1 : t_cmre_1 := ( C1_csa1_1, C1_scre_1 );
CONSTANT C2_cmre_1 : t_cmre_1 := ( C2_csa1_1, C0_scre_1 );
CONSTANT CX_cmre_2 : t_cmre_2 := ( OTHERS=>CX_csa1_1 );
CONSTANT C0_cmre_2 : t_cmre_2 := ( OTHERS=>C0_csa1_1 );
CONSTANT C1_cmre_2 : t_cmre_2 := ( OTHERS=>C1_csa1_1 );
CONSTANT C2_cmre_2 : t_cmre_2 := ( left|right=>C2_csa1_1, OTHERS=>C0_csa1_1 );
CONSTANT CX_cca1_7 : t_cca1_7 := ( OTHERS=>CX_cmre_2 );
CONSTANT C0_cca1_7 : t_cca1_7 := ( OTHERS=>C0_cmre_2 );
CONSTANT C1_cca1_7 : t_cca1_7 := ( OTHERS=>C1_cmre_2 );
CONSTANT C2_cca1_7 : t_cca1_7 := ( C2_cmre_2, C0_cmre_2, C0_cmre_2, C2_cmre_2 );
CONSTANT CX_cmre_3 : t_cmre_3 := ( OTHERS=>CX_cca1_7 );
CONSTANT C0_cmre_3 : t_cmre_3 := ( OTHERS=>C0_cca1_7 );
CONSTANT C1_cmre_3 : t_cmre_3 := ( OTHERS=>C1_cca1_7 );
CONSTANT C2_cmre_3 : t_cmre_3 := ( left|right=>C2_cca1_7, OTHERS=>C0_cca1_7 );
-- --------------------------------------------------------------------------------------------
-- Functions for mapping from integer test values to/from values of the Test types
-- --------------------------------------------------------------------------------------------
FUNCTION val_t ( i : INTEGER ) RETURN st_scl1;
FUNCTION val_t ( i : INTEGER ) RETURN TIME;
FUNCTION val_t ( i : INTEGER ) RETURN st_scl3;
FUNCTION val_t ( i : INTEGER ) RETURN st_scl4;
FUNCTION val_t ( i : INTEGER ) RETURN t_scre_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_3;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_4;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa2_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa3_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa4_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_3;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_4;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_7;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_3;
FUNCTION val_i ( i : st_scl1 ) RETURN INTEGER;
FUNCTION val_i ( i : TIME ) RETURN INTEGER;
FUNCTION val_i ( i : st_scl3 ) RETURN INTEGER;
FUNCTION val_i ( i : st_scl4 ) RETURN INTEGER;
FUNCTION val_i ( i : t_scre_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa1_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa1_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa1_3 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa1_4 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa2_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa3_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa4_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_3 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_4 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca2_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca2_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca3_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca3_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cmre_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cmre_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_7 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cmre_3 ) RETURN INTEGER;
FUNCTION val_s ( i : st_scl1 ) RETURN STRING;
FUNCTION val_s ( i : TIME ) RETURN STRING;
FUNCTION val_s ( i : st_scl3 ) RETURN STRING;
FUNCTION val_s ( i : st_scl4 ) RETURN STRING;
FUNCTION val_s ( i : t_scre_1 ) RETURN STRING;
FUNCTION val_s ( i : t_csa1_1 ) RETURN STRING;
FUNCTION val_s ( i : t_csa1_2 ) RETURN STRING;
FUNCTION val_s ( i : t_csa1_3 ) RETURN STRING;
FUNCTION val_s ( i : t_csa1_4 ) RETURN STRING;
FUNCTION val_s ( i : t_csa2_1 ) RETURN STRING;
FUNCTION val_s ( i : t_csa3_1 ) RETURN STRING;
FUNCTION val_s ( i : t_csa4_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_2 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_3 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_4 ) RETURN STRING;
FUNCTION val_s ( i : t_cca2_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cca2_2 ) RETURN STRING;
FUNCTION val_s ( i : t_cca3_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cca3_2 ) RETURN STRING;
FUNCTION val_s ( i : t_cmre_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cmre_2 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_7 ) RETURN STRING;
FUNCTION val_s ( i : t_cmre_3 ) RETURN STRING;
END;
PACKAGE BODY c03s03b00x00p03n04i00521pkg IS
CONSTANT CX_csa2_1 : t_csa2_1 := F_csa2_1 ( CX_scl1, CX_scl1 );
CONSTANT C0_csa2_1 : t_csa2_1 := F_csa2_1 ( C0_scl1, C0_scl1 );
CONSTANT C1_csa2_1 : t_csa2_1 := F_csa2_1 ( C1_scl1, C1_scl1 );
CONSTANT C2_csa2_1 : t_csa2_1 := F_csa2_1 ( C0_scl1, C2_scl1 );
CONSTANT CX_csa3_1 : t_csa3_1 := F_csa3_1 ( CX_scl1, CX_scl1 );
CONSTANT C0_csa3_1 : t_csa3_1 := F_csa3_1 ( C0_scl1, C0_scl1 );
CONSTANT C1_csa3_1 : t_csa3_1 := F_csa3_1 ( C1_scl1, C1_scl1 );
CONSTANT C2_csa3_1 : t_csa3_1 := F_csa3_1 ( C0_scl1, C2_scl1 );
CONSTANT CX_csa4_1 : t_csa4_1 := F_csa4_1 ( CX_scl1, CX_scl1 );
CONSTANT C0_csa4_1 : t_csa4_1 := F_csa4_1 ( C0_scl1, C0_scl1 );
CONSTANT C1_csa4_1 : t_csa4_1 := F_csa4_1 ( C1_scl1, C1_scl1 );
CONSTANT C2_csa4_1 : t_csa4_1 := F_csa4_1 ( C0_scl1, C2_scl1 );
CONSTANT CX_cca2_1 : t_cca2_1 := ( OTHERS=>CX_csa2_1 );
CONSTANT C0_cca2_1 : t_cca2_1 := ( OTHERS=>C0_csa2_1 );
CONSTANT C1_cca2_1 : t_cca2_1 := ( OTHERS=>C1_csa2_1 );
CONSTANT C2_cca2_1 : t_cca2_1 := ( C2_csa2_1, C0_csa2_1, C0_csa2_1, C2_csa2_1 );
CONSTANT CX_cca2_2 : t_cca2_2 := F_cca2_2 ( CX_csa2_1, CX_csa2_1 );
CONSTANT C0_cca2_2 : t_cca2_2 := F_cca2_2 ( C0_csa2_1, C0_csa2_1 );
CONSTANT C1_cca2_2 : t_cca2_2 := F_cca2_2 ( C1_csa2_1, C1_csa2_1 );
CONSTANT C2_cca2_2 : t_cca2_2 := F_cca2_2 ( C0_csa2_1, C2_csa2_1 );
CONSTANT CX_cca3_1 : t_cca3_1 := F_cca3_1 ( CX_csa1_1, CX_csa1_1 );
CONSTANT C0_cca3_1 : t_cca3_1 := F_cca3_1 ( C0_csa1_1, C0_csa1_1 );
CONSTANT C1_cca3_1 : t_cca3_1 := F_cca3_1 ( C1_csa1_1, C1_csa1_1 );
CONSTANT C2_cca3_1 : t_cca3_1 := F_cca3_1 ( C0_csa1_1, C2_csa1_1 );
CONSTANT CX_cca3_2 : t_cca3_2 := ( OTHERS=>CX_csa3_1 );
CONSTANT C0_cca3_2 : t_cca3_2 := ( OTHERS=>C0_csa3_1 );
CONSTANT C1_cca3_2 : t_cca3_2 := ( OTHERS=>C1_csa3_1 );
CONSTANT C2_cca3_2 : t_cca3_2 := ( C2_csa3_1, C0_csa3_1, C0_csa3_1, C2_csa3_1 );
--
-- Functions to provide values for multi-dimensional composites
--
FUNCTION F_csa2_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa2_1 IS
VARIABLE res : t_csa2_1;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
res(i,j) := v0;
END LOOP;
END LOOP;
res(res'left (1),res'left (2)) := v2;
res(res'left (1),res'right(2)) := v2;
res(res'right(1),res'left (2)) := v2;
res(res'right(1),res'right(2)) := v2;
RETURN res;
END;
FUNCTION F_csa3_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa3_1 IS
VARIABLE res : t_csa3_1;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
FOR k IN res'RANGE(3) LOOP
res(i,j,k) := v0;
END LOOP;
END LOOP;
END LOOP;
res(res'left (1),res'left (2),res'left (3)) := v2;
res(res'right(1),res'left (2),res'left (3)) := v2;
res(res'left (1),res'right(2),res'left (3)) := v2;
res(res'right(1),res'right(2),res'left (3)) := v2;
res(res'left (1),res'left (2),res'right(3)) := v2;
res(res'right(1),res'left (2),res'right(3)) := v2;
res(res'left (1),res'right(2),res'right(3)) := v2;
res(res'right(1),res'right(2),res'right(3)) := v2;
RETURN res;
END;
FUNCTION F_csa4_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa4_1 IS
VARIABLE res : t_csa4_1;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
FOR k IN res'RANGE(3) LOOP
FOR l IN res'RANGE(4) LOOP
res(i,j,k,l) := v0;
END LOOP;
END LOOP;
END LOOP;
END LOOP;
res(res'left (1),res'left (2),res'left (3),res'left (4)) := v2;
res(res'right(1),res'left (2),res'left (3),res'left (4)) := v2;
res(res'left (1),res'right(2),res'left (3),res'left (4)) := v2;
res(res'right(1),res'right(2),res'left (3),res'left (4)) := v2;
res(res'left (1),res'left (2),res'right(3),res'left (4)) := v2;
res(res'right(1),res'left (2),res'right(3),res'left (4)) := v2;
res(res'left (1),res'right(2),res'right(3),res'left (4)) := v2;
res(res'right(1),res'right(2),res'right(3),res'left (4)) := v2;
res(res'left (1),res'left (2),res'left (3),res'right(4)) := v2;
res(res'right(1),res'left (2),res'left (3),res'right(4)) := v2;
res(res'left (1),res'right(2),res'left (3),res'right(4)) := v2;
res(res'right(1),res'right(2),res'left (3),res'right(4)) := v2;
res(res'left (1),res'left (2),res'right(3),res'right(4)) := v2;
res(res'right(1),res'left (2),res'right(3),res'right(4)) := v2;
res(res'left (1),res'right(2),res'right(3),res'right(4)) := v2;
res(res'right(1),res'right(2),res'right(3),res'right(4)) := v2;
RETURN res;
END;
FUNCTION F_cca2_2 ( v0,v2 : IN t_csa2_1 ) RETURN t_cca2_2 IS
VARIABLE res : t_cca2_2;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
res(i,j) := v0;
END LOOP;
END LOOP;
res(res'left (1),res'left (2)) := v2;
res(res'left (1),res'right(2)) := v2;
res(res'right(1),res'left (2)) := v2;
res(res'right(1),res'right(2)) := v2;
RETURN res;
END;
FUNCTION F_cca3_1 ( v0,v2 : IN t_csa1_1 ) RETURN t_cca3_1 IS
VARIABLE res : t_cca3_1;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
FOR k IN res'RANGE(3) LOOP
res(i,j,k) := v0;
END LOOP;
END LOOP;
END LOOP;
res(res'left (1),res'left (2),res'left (3)) := v2;
res(res'right(1),res'left (2),res'left (3)) := v2;
res(res'left (1),res'right(2),res'left (3)) := v2;
res(res'right(1),res'right(2),res'left (3)) := v2;
res(res'left (1),res'left (2),res'right(3)) := v2;
res(res'right(1),res'left (2),res'right(3)) := v2;
res(res'left (1),res'right(2),res'right(3)) := v2;
res(res'right(1),res'right(2),res'right(3)) := v2;
RETURN res;
END;
--
-- Resolution Functions
--
FUNCTION rf_scre_1 ( v: t_scre_1_vct ) RETURN t_scre_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_scre_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa1_1 ( v: t_csa1_1_vct ) RETURN t_csa1_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa1_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa1_2 ( v: t_csa1_2_vct ) RETURN t_csa1_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa1_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa1_3 ( v: t_csa1_3_vct ) RETURN t_csa1_3 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa1_3;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa1_4 ( v: t_csa1_4_vct ) RETURN t_csa1_4 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa1_4;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa2_1 ( v: t_csa2_1_vct ) RETURN t_csa2_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa2_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa3_1 ( v: t_csa3_1_vct ) RETURN t_csa3_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa3_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa4_1 ( v: t_csa4_1_vct ) RETURN t_csa4_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa4_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_1 ( v: t_cca1_1_vct ) RETURN t_cca1_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_2 ( v: t_cca1_2_vct ) RETURN t_cca1_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_3 ( v: t_cca1_3_vct ) RETURN t_cca1_3 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_3;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_4 ( v: t_cca1_4_vct ) RETURN t_cca1_4 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_4;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca2_1 ( v: t_cca2_1_vct ) RETURN t_cca2_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca2_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca2_2 ( v: t_cca2_2_vct ) RETURN t_cca2_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca2_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca3_1 ( v: t_cca3_1_vct ) RETURN t_cca3_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca3_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca3_2 ( v: t_cca3_2_vct ) RETURN t_cca3_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca3_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cmre_1 ( v: t_cmre_1_vct ) RETURN t_cmre_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cmre_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cmre_2 ( v: t_cmre_2_vct ) RETURN t_cmre_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cmre_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_7 ( v: t_cca1_7_vct ) RETURN t_cca1_7 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_7;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cmre_3 ( v: t_cmre_3_vct ) RETURN t_cmre_3 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cmre_3;
ELSE RETURN v(1);
END IF;
END;
--
--
FUNCTION val_t ( i : INTEGER ) RETURN st_scl1 IS
BEGIN
IF i = 0 THEN RETURN C0_scl1; END IF;
IF i = 1 THEN RETURN C1_scl1; END IF;
IF i = 2 THEN RETURN C2_scl1; END IF;
RETURN CX_scl1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN TIME IS
BEGIN
IF i = 0 THEN RETURN C0_scl2; END IF;
IF i = 1 THEN RETURN C1_scl2; END IF;
IF i = 2 THEN RETURN C2_scl2; END IF;
RETURN CX_scl2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN st_scl3 IS
BEGIN
IF i = 0 THEN RETURN C0_scl3; END IF;
IF i = 1 THEN RETURN C1_scl3; END IF;
IF i = 2 THEN RETURN C2_scl3; END IF;
RETURN CX_scl3;
END;
FUNCTION val_t ( i : INTEGER ) RETURN st_scl4 IS
BEGIN
IF i = 0 THEN RETURN C0_scl4; END IF;
IF i = 1 THEN RETURN C1_scl4; END IF;
IF i = 2 THEN RETURN C2_scl4; END IF;
RETURN CX_scl4;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_scre_1 IS
BEGIN
IF i = 0 THEN RETURN C0_scre_1; END IF;
IF i = 1 THEN RETURN C1_scre_1; END IF;
IF i = 2 THEN RETURN C2_scre_1; END IF;
RETURN CX_scre_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_1 IS
BEGIN
IF i = 0 THEN RETURN C0_csa1_1; END IF;
IF i = 1 THEN RETURN C1_csa1_1; END IF;
IF i = 2 THEN RETURN C2_csa1_1; END IF;
RETURN CX_csa1_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_2 IS
BEGIN
IF i = 0 THEN RETURN C0_csa1_2; END IF;
IF i = 1 THEN RETURN C1_csa1_2; END IF;
IF i = 2 THEN RETURN C2_csa1_2; END IF;
RETURN CX_csa1_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_3 IS
BEGIN
IF i = 0 THEN RETURN C0_csa1_3; END IF;
IF i = 1 THEN RETURN C1_csa1_3; END IF;
IF i = 2 THEN RETURN C2_csa1_3; END IF;
RETURN CX_csa1_3;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_4 IS
BEGIN
IF i = 0 THEN RETURN C0_csa1_4; END IF;
IF i = 1 THEN RETURN C1_csa1_4; END IF;
IF i = 2 THEN RETURN C2_csa1_4; END IF;
RETURN CX_csa1_4;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa2_1 IS
BEGIN
IF i = 0 THEN RETURN C0_csa2_1; END IF;
IF i = 1 THEN RETURN C1_csa2_1; END IF;
IF i = 2 THEN RETURN C2_csa2_1; END IF;
RETURN CX_csa2_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa3_1 IS
BEGIN
IF i = 0 THEN RETURN C0_csa3_1; END IF;
IF i = 1 THEN RETURN C1_csa3_1; END IF;
IF i = 2 THEN RETURN C2_csa3_1; END IF;
RETURN CX_csa3_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa4_1 IS
BEGIN
IF i = 0 THEN RETURN C0_csa4_1; END IF;
IF i = 1 THEN RETURN C1_csa4_1; END IF;
IF i = 2 THEN RETURN C2_csa4_1; END IF;
RETURN CX_csa4_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_1 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_1; END IF;
IF i = 1 THEN RETURN C1_cca1_1; END IF;
IF i = 2 THEN RETURN C2_cca1_1; END IF;
RETURN CX_cca1_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_2 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_2; END IF;
IF i = 1 THEN RETURN C1_cca1_2; END IF;
IF i = 2 THEN RETURN C2_cca1_2; END IF;
RETURN CX_cca1_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_3 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_3; END IF;
IF i = 1 THEN RETURN C1_cca1_3; END IF;
IF i = 2 THEN RETURN C2_cca1_3; END IF;
RETURN CX_cca1_3;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_4 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_4; END IF;
IF i = 1 THEN RETURN C1_cca1_4; END IF;
IF i = 2 THEN RETURN C2_cca1_4; END IF;
RETURN CX_cca1_4;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_1 IS
BEGIN
IF i = 0 THEN RETURN C0_cca2_1; END IF;
IF i = 1 THEN RETURN C1_cca2_1; END IF;
IF i = 2 THEN RETURN C2_cca2_1; END IF;
RETURN CX_cca2_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_2 IS
BEGIN
IF i = 0 THEN RETURN C0_cca2_2; END IF;
IF i = 1 THEN RETURN C1_cca2_2; END IF;
IF i = 2 THEN RETURN C2_cca2_2; END IF;
RETURN CX_cca2_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_1 IS
BEGIN
IF i = 0 THEN RETURN C0_cca3_1; END IF;
IF i = 1 THEN RETURN C1_cca3_1; END IF;
IF i = 2 THEN RETURN C2_cca3_1; END IF;
RETURN CX_cca3_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_2 IS
BEGIN
IF i = 0 THEN RETURN C0_cca3_2; END IF;
IF i = 1 THEN RETURN C1_cca3_2; END IF;
IF i = 2 THEN RETURN C2_cca3_2; END IF;
RETURN CX_cca3_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_1 IS
BEGIN
IF i = 0 THEN RETURN C0_cmre_1; END IF;
IF i = 1 THEN RETURN C1_cmre_1; END IF;
IF i = 2 THEN RETURN C2_cmre_1; END IF;
RETURN CX_cmre_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_2 IS
BEGIN
IF i = 0 THEN RETURN C0_cmre_2; END IF;
IF i = 1 THEN RETURN C1_cmre_2; END IF;
IF i = 2 THEN RETURN C2_cmre_2; END IF;
RETURN CX_cmre_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_7 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_7; END IF;
IF i = 1 THEN RETURN C1_cca1_7; END IF;
IF i = 2 THEN RETURN C2_cca1_7; END IF;
RETURN CX_cca1_7;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_3 IS
BEGIN
IF i = 0 THEN RETURN C0_cmre_3; END IF;
IF i = 1 THEN RETURN C1_cmre_3; END IF;
IF i = 2 THEN RETURN C2_cmre_3; END IF;
RETURN CX_cmre_3;
END;
--
--
FUNCTION val_i ( i : st_scl1 ) RETURN INTEGER IS
BEGIN
IF i = C0_scl1 THEN RETURN 0; END IF;
IF i = C1_scl1 THEN RETURN 1; END IF;
IF i = C2_scl1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : TIME ) RETURN INTEGER IS
BEGIN
IF i = C0_scl2 THEN RETURN 0; END IF;
IF i = C1_scl2 THEN RETURN 1; END IF;
IF i = C2_scl2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : st_scl3 ) RETURN INTEGER IS
BEGIN
IF i = C0_scl3 THEN RETURN 0; END IF;
IF i = C1_scl3 THEN RETURN 1; END IF;
IF i = C2_scl3 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : st_scl4 ) RETURN INTEGER IS
BEGIN
IF i = C0_scl4 THEN RETURN 0; END IF;
IF i = C1_scl4 THEN RETURN 1; END IF;
IF i = C2_scl4 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_scre_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_scre_1 THEN RETURN 0; END IF;
IF i = C1_scre_1 THEN RETURN 1; END IF;
IF i = C2_scre_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa1_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa1_1 THEN RETURN 0; END IF;
IF i = C1_csa1_1 THEN RETURN 1; END IF;
IF i = C2_csa1_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa1_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa1_2 THEN RETURN 0; END IF;
IF i = C1_csa1_2 THEN RETURN 1; END IF;
IF i = C2_csa1_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa1_3 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa1_3 THEN RETURN 0; END IF;
IF i = C1_csa1_3 THEN RETURN 1; END IF;
IF i = C2_csa1_3 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa1_4 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa1_4 THEN RETURN 0; END IF;
IF i = C1_csa1_4 THEN RETURN 1; END IF;
IF i = C2_csa1_4 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa2_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa2_1 THEN RETURN 0; END IF;
IF i = C1_csa2_1 THEN RETURN 1; END IF;
IF i = C2_csa2_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa3_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa3_1 THEN RETURN 0; END IF;
IF i = C1_csa3_1 THEN RETURN 1; END IF;
IF i = C2_csa3_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa4_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa4_1 THEN RETURN 0; END IF;
IF i = C1_csa4_1 THEN RETURN 1; END IF;
IF i = C2_csa4_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_1 THEN RETURN 0; END IF;
IF i = C1_cca1_1 THEN RETURN 1; END IF;
IF i = C2_cca1_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_2 THEN RETURN 0; END IF;
IF i = C1_cca1_2 THEN RETURN 1; END IF;
IF i = C2_cca1_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_3 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_3 THEN RETURN 0; END IF;
IF i = C1_cca1_3 THEN RETURN 1; END IF;
IF i = C2_cca1_3 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_4 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_4 THEN RETURN 0; END IF;
IF i = C1_cca1_4 THEN RETURN 1; END IF;
IF i = C2_cca1_4 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca2_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca2_1 THEN RETURN 0; END IF;
IF i = C1_cca2_1 THEN RETURN 1; END IF;
IF i = C2_cca2_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca2_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca2_2 THEN RETURN 0; END IF;
IF i = C1_cca2_2 THEN RETURN 1; END IF;
IF i = C2_cca2_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca3_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca3_1 THEN RETURN 0; END IF;
IF i = C1_cca3_1 THEN RETURN 1; END IF;
IF i = C2_cca3_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca3_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca3_2 THEN RETURN 0; END IF;
IF i = C1_cca3_2 THEN RETURN 1; END IF;
IF i = C2_cca3_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cmre_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_cmre_1 THEN RETURN 0; END IF;
IF i = C1_cmre_1 THEN RETURN 1; END IF;
IF i = C2_cmre_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cmre_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_cmre_2 THEN RETURN 0; END IF;
IF i = C1_cmre_2 THEN RETURN 1; END IF;
IF i = C2_cmre_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_7 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_7 THEN RETURN 0; END IF;
IF i = C1_cca1_7 THEN RETURN 1; END IF;
IF i = C2_cca1_7 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cmre_3 ) RETURN INTEGER IS
BEGIN
IF i = C0_cmre_3 THEN RETURN 0; END IF;
IF i = C1_cmre_3 THEN RETURN 1; END IF;
IF i = C2_cmre_3 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_s ( i : st_scl1 ) RETURN STRING IS
BEGIN
IF i = C0_scl1 THEN RETURN "C0_scl1"; END IF;
IF i = C1_scl1 THEN RETURN "C1_scl1"; END IF;
IF i = C2_scl1 THEN RETURN "C2_scl1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : TIME ) RETURN STRING IS
BEGIN
IF i = C0_scl2 THEN RETURN "C0_scl2"; END IF;
IF i = C1_scl2 THEN RETURN "C1_scl2"; END IF;
IF i = C2_scl2 THEN RETURN "C2_scl2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : st_scl3 ) RETURN STRING IS
BEGIN
IF i = C0_scl3 THEN RETURN "C0_scl3"; END IF;
IF i = C1_scl3 THEN RETURN "C1_scl3"; END IF;
IF i = C2_scl3 THEN RETURN "C2_scl3"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : st_scl4 ) RETURN STRING IS
BEGIN
IF i = C0_scl4 THEN RETURN "C0_scl4"; END IF;
IF i = C1_scl4 THEN RETURN "C1_scl4"; END IF;
IF i = C2_scl4 THEN RETURN "C2_scl4"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_scre_1 ) RETURN STRING IS
BEGIN
IF i = C0_scre_1 THEN RETURN "C0_scre_1"; END IF;
IF i = C1_scre_1 THEN RETURN "C1_scre_1"; END IF;
IF i = C2_scre_1 THEN RETURN "C2_scre_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa1_1 ) RETURN STRING IS
BEGIN
IF i = C0_csa1_1 THEN RETURN "C0_csa1_1"; END IF;
IF i = C1_csa1_1 THEN RETURN "C1_csa1_1"; END IF;
IF i = C2_csa1_1 THEN RETURN "C2_csa1_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa1_2 ) RETURN STRING IS
BEGIN
IF i = C0_csa1_2 THEN RETURN "C0_csa1_2"; END IF;
IF i = C1_csa1_2 THEN RETURN "C1_csa1_2"; END IF;
IF i = C2_csa1_2 THEN RETURN "C2_csa1_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa1_3 ) RETURN STRING IS
BEGIN
IF i = C0_csa1_3 THEN RETURN "C0_csa1_3"; END IF;
IF i = C1_csa1_3 THEN RETURN "C1_csa1_3"; END IF;
IF i = C2_csa1_3 THEN RETURN "C2_csa1_3"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa1_4 ) RETURN STRING IS
BEGIN
IF i = C0_csa1_4 THEN RETURN "C0_csa1_4"; END IF;
IF i = C1_csa1_4 THEN RETURN "C1_csa1_4"; END IF;
IF i = C2_csa1_4 THEN RETURN "C2_csa1_4"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa2_1 ) RETURN STRING IS
BEGIN
IF i = C0_csa2_1 THEN RETURN "C0_csa2_1"; END IF;
IF i = C1_csa2_1 THEN RETURN "C1_csa2_1"; END IF;
IF i = C2_csa2_1 THEN RETURN "C2_csa2_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa3_1 ) RETURN STRING IS
BEGIN
IF i = C0_csa3_1 THEN RETURN "C0_csa3_1"; END IF;
IF i = C1_csa3_1 THEN RETURN "C1_csa3_1"; END IF;
IF i = C2_csa3_1 THEN RETURN "C2_csa3_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa4_1 ) RETURN STRING IS
BEGIN
IF i = C0_csa4_1 THEN RETURN "C0_csa4_1"; END IF;
IF i = C1_csa4_1 THEN RETURN "C1_csa4_1"; END IF;
IF i = C2_csa4_1 THEN RETURN "C2_csa4_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_1 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_1 THEN RETURN "C0_cca1_1"; END IF;
IF i = C1_cca1_1 THEN RETURN "C1_cca1_1"; END IF;
IF i = C2_cca1_1 THEN RETURN "C2_cca1_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_2 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_2 THEN RETURN "C0_cca1_2"; END IF;
IF i = C1_cca1_2 THEN RETURN "C1_cca1_2"; END IF;
IF i = C2_cca1_2 THEN RETURN "C2_cca1_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_3 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_3 THEN RETURN "C0_cca1_3"; END IF;
IF i = C1_cca1_3 THEN RETURN "C1_cca1_3"; END IF;
IF i = C2_cca1_3 THEN RETURN "C2_cca1_3"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_4 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_4 THEN RETURN "C0_cca1_4"; END IF;
IF i = C1_cca1_4 THEN RETURN "C1_cca1_4"; END IF;
IF i = C2_cca1_4 THEN RETURN "C2_cca1_4"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca2_1 ) RETURN STRING IS
BEGIN
IF i = C0_cca2_1 THEN RETURN "C0_cca2_1"; END IF;
IF i = C1_cca2_1 THEN RETURN "C1_cca2_1"; END IF;
IF i = C2_cca2_1 THEN RETURN "C2_cca2_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca2_2 ) RETURN STRING IS
BEGIN
IF i = C0_cca2_2 THEN RETURN "C0_cca2_2"; END IF;
IF i = C1_cca2_2 THEN RETURN "C1_cca2_2"; END IF;
IF i = C2_cca2_2 THEN RETURN "C2_cca2_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca3_1 ) RETURN STRING IS
BEGIN
IF i = C0_cca3_1 THEN RETURN "C0_cca3_1"; END IF;
IF i = C1_cca3_1 THEN RETURN "C1_cca3_1"; END IF;
IF i = C2_cca3_1 THEN RETURN "C2_cca3_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca3_2 ) RETURN STRING IS
BEGIN
IF i = C0_cca3_2 THEN RETURN "C0_cca3_2"; END IF;
IF i = C1_cca3_2 THEN RETURN "C1_cca3_2"; END IF;
IF i = C2_cca3_2 THEN RETURN "C2_cca3_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cmre_1 ) RETURN STRING IS
BEGIN
IF i = C0_cmre_1 THEN RETURN "C0_cmre_1"; END IF;
IF i = C1_cmre_1 THEN RETURN "C1_cmre_1"; END IF;
IF i = C2_cmre_1 THEN RETURN "C2_cmre_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cmre_2 ) RETURN STRING IS
BEGIN
IF i = C0_cmre_2 THEN RETURN "C0_cmre_2"; END IF;
IF i = C1_cmre_2 THEN RETURN "C1_cmre_2"; END IF;
IF i = C2_cmre_2 THEN RETURN "C2_cmre_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_7 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_7 THEN RETURN "C0_cca1_7"; END IF;
IF i = C1_cca1_7 THEN RETURN "C1_cca1_7"; END IF;
IF i = C2_cca1_7 THEN RETURN "C2_cca1_7"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cmre_3 ) RETURN STRING IS
BEGIN
IF i = C0_cmre_3 THEN RETURN "C0_cmre_3"; END IF;
IF i = C1_cmre_3 THEN RETURN "C1_cmre_3"; END IF;
IF i = C2_cmre_3 THEN RETURN "C2_cmre_3"; END IF;
RETURN "UNKNOWN";
END;
END c03s03b00x00p03n04i00521pkg;
USE work.c03s03b00x00p03n04i00521pkg.ALL;
ENTITY c03s03b00x00p03n04i00521ent IS
END c03s03b00x00p03n04i00521ent;
ARCHITECTURE c03s03b00x00p03n04i00521arch OF c03s03b00x00p03n04i00521ent IS
--
-- Access type declarations
--
TYPE at_usa2_1 IS ACCESS t_usa2_1 ;
TYPE at_usa3_1 IS ACCESS t_usa3_1 ;
TYPE at_usa4_1 IS ACCESS t_usa4_1 ;
TYPE at_csa2_1 IS ACCESS t_csa2_1 ;
TYPE at_csa3_1 IS ACCESS t_csa3_1 ;
TYPE at_csa4_1 IS ACCESS t_csa4_1 ;
TYPE at_cca2_1 IS ACCESS t_cca2_1 ;
TYPE at_cca2_2 IS ACCESS t_cca2_2 ;
TYPE at_cca3_1 IS ACCESS t_cca3_1 ;
TYPE at_cca3_2 IS ACCESS t_cca3_2 ;
--
--
BEGIN
TESTING: PROCESS
--
-- ACCESS VARIABLE declarations
--
VARIABLE AV0_usa2_1 : at_usa2_1 ;
VARIABLE AV2_usa2_1 : at_usa2_1 ;
VARIABLE AV0_usa3_1 : at_usa3_1 ;
VARIABLE AV2_usa3_1 : at_usa3_1 ;
VARIABLE AV0_usa4_1 : at_usa4_1 ;
VARIABLE AV2_usa4_1 : at_usa4_1 ;
VARIABLE AV0_csa2_1 : at_csa2_1 ;
VARIABLE AV2_csa2_1 : at_csa2_1 ;
VARIABLE AV0_csa3_1 : at_csa3_1 ;
VARIABLE AV2_csa3_1 : at_csa3_1 ;
VARIABLE AV0_csa4_1 : at_csa4_1 ;
VARIABLE AV2_csa4_1 : at_csa4_1 ;
VARIABLE AV0_cca2_1 : at_cca2_1 ;
VARIABLE AV2_cca2_1 : at_cca2_1 ;
VARIABLE AV0_cca2_2 : at_cca2_2 ;
VARIABLE AV2_cca2_2 : at_cca2_2 ;
VARIABLE AV0_cca3_1 : at_cca3_1 ;
VARIABLE AV2_cca3_1 : at_cca3_1 ;
VARIABLE AV0_cca3_2 : at_cca3_2 ;
VARIABLE AV2_cca3_2 : at_cca3_2 ;
--
--
BEGIN
--
-- Allocation of access values
--
AV0_usa2_1 := NEW t_usa2_1 ( st_ind2, st_ind1 ) ;
AV0_usa3_1 := NEW t_usa3_1 ( st_ind3, st_ind2, st_ind1 ) ;
AV0_usa4_1 := NEW t_usa4_1 (st_ind4, st_ind3, st_ind2, st_ind1 ) ;
AV0_csa2_1 := NEW t_csa2_1 ;
AV0_csa3_1 := NEW t_csa3_1 ;
AV0_csa4_1 := NEW t_csa4_1 ;
AV0_cca2_1 := NEW t_cca2_1 ;
AV0_cca2_2 := NEW t_cca2_2 ;
AV0_cca3_1 := NEW t_cca3_1 ;
AV0_cca3_2 := NEW t_cca3_2 ;
---
AV2_usa2_1 := NEW t_usa2_1 ' ( C2_csa2_1 ) ;
AV2_usa3_1 := NEW t_usa3_1 ' ( C2_csa3_1 ) ;
AV2_usa4_1 := NEW t_usa4_1 ' ( C2_csa4_1 ) ;
AV2_csa2_1 := NEW t_csa2_1 ' ( C2_csa2_1 ) ;
AV2_csa3_1 := NEW t_csa3_1 ' ( C2_csa3_1 ) ;
AV2_csa4_1 := NEW t_csa4_1 ' ( C2_csa4_1 ) ;
AV2_cca2_1 := NEW t_cca2_1 ' ( C2_cca2_1 ) ;
AV2_cca2_2 := NEW t_cca2_2 ' ( C2_cca2_2 ) ;
AV2_cca3_1 := NEW t_cca3_1 ' ( C2_cca3_1 ) ;
AV2_cca3_2 := NEW t_cca3_2 ' ( C2_cca3_2 ) ;
--
--
ASSERT AV0_usa2_1.all = C0_csa2_1
REPORT "Improper initialization of AV0_usa2_1" SEVERITY FAILURE;
ASSERT AV2_usa2_1.all = C2_csa2_1
REPORT "Improper initialization of AV2_usa2_1" SEVERITY FAILURE;
ASSERT AV0_usa3_1.all = C0_csa3_1
REPORT "Improper initialization of AV0_usa3_1" SEVERITY FAILURE;
ASSERT AV2_usa3_1.all = C2_csa3_1
REPORT "Improper initialization of AV2_usa3_1" SEVERITY FAILURE;
ASSERT AV0_usa4_1.all = C0_csa4_1
REPORT "Improper initialization of AV0_usa4_1" SEVERITY FAILURE;
ASSERT AV2_usa4_1.all = C2_csa4_1
REPORT "Improper initialization of AV2_usa4_1" SEVERITY FAILURE;
ASSERT AV0_csa2_1.all = C0_csa2_1
REPORT "Improper initialization of AV0_csa2_1" SEVERITY FAILURE;
ASSERT AV2_csa2_1.all = C2_csa2_1
REPORT "Improper initialization of AV2_csa2_1" SEVERITY FAILURE;
ASSERT AV0_csa3_1.all = C0_csa3_1
REPORT "Improper initialization of AV0_csa3_1" SEVERITY FAILURE;
ASSERT AV2_csa3_1.all = C2_csa3_1
REPORT "Improper initialization of AV2_csa3_1" SEVERITY FAILURE;
ASSERT AV0_csa4_1.all = C0_csa4_1
REPORT "Improper initialization of AV0_csa4_1" SEVERITY FAILURE;
ASSERT AV2_csa4_1.all = C2_csa4_1
REPORT "Improper initialization of AV2_csa4_1" SEVERITY FAILURE;
ASSERT AV0_cca2_1.all = C0_cca2_1
REPORT "Improper initialization of AV0_cca2_1" SEVERITY FAILURE;
ASSERT AV2_cca2_1.all = C2_cca2_1
REPORT "Improper initialization of AV2_cca2_1" SEVERITY FAILURE;
ASSERT AV0_cca2_2.all = C0_cca2_2
REPORT "Improper initialization of AV0_cca2_2" SEVERITY FAILURE;
ASSERT AV2_cca2_2.all = C2_cca2_2
REPORT "Improper initialization of AV2_cca2_2" SEVERITY FAILURE;
ASSERT AV0_cca3_1.all = C0_cca3_1
REPORT "Improper initialization of AV0_cca3_1" SEVERITY FAILURE;
ASSERT AV2_cca3_1.all = C2_cca3_1
REPORT "Improper initialization of AV2_cca3_1" SEVERITY FAILURE;
ASSERT AV0_cca3_2.all = C0_cca3_2
REPORT "Improper initialization of AV0_cca3_2" SEVERITY FAILURE;
ASSERT AV2_cca3_2.all = C2_cca3_2
REPORT "Improper initialization of AV2_cca3_2" SEVERITY FAILURE;
--
--
assert NOT( ( AV0_usa2_1.all = C0_csa2_1 )
and ( AV2_usa2_1.all = C2_csa2_1 )
and ( AV0_usa3_1.all = C0_csa3_1 )
and ( AV2_usa3_1.all = C2_csa3_1 )
and ( AV0_usa4_1.all = C0_csa4_1 )
and ( AV2_usa4_1.all = C2_csa4_1 )
and ( AV0_csa2_1.all = C0_csa2_1 )
and ( AV2_csa2_1.all = C2_csa2_1 )
and ( AV0_csa3_1.all = C0_csa3_1 )
and ( AV2_csa3_1.all = C2_csa3_1 ))
report "***PASSED TEST: c03s03b00x00p03n04i00521"
severity NOTE;
assert ( ( AV0_usa2_1.all = C0_csa2_1 )
and ( AV2_usa2_1.all = C2_csa2_1 )
and ( AV0_usa3_1.all = C0_csa3_1 )
and ( AV2_usa3_1.all = C2_csa3_1 )
and ( AV0_usa4_1.all = C0_csa4_1 )
and ( AV2_usa4_1.all = C2_csa4_1 )
and ( AV0_csa2_1.all = C0_csa2_1 )
and ( AV2_csa2_1.all = C2_csa2_1 )
and ( AV0_csa3_1.all = C0_csa3_1 )
and ( AV2_csa3_1.all = C2_csa3_1 ))
report "***FAILED TEST: c03s03b00x00p03n04i00521 - Each access value designates an object of the subtype defined by the subtype indication of the access type definition."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p03n04i00521arch;
|
gpl-2.0
|
0fb96a8a5e9ab28f214689d331361df6
| 0.577282 | 2.584724 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1367.vhd
| 4 | 6,578 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1367.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01367ent IS
END c08s05b00x00p03n01i01367ent;
ARCHITECTURE c08s05b00x00p03n01i01367arch OF c08s05b00x00p03n01i01367ent IS
BEGIN
TESTING: PROCESS
--
-- Define constants for package
--
constant lowb : integer := 1 ;
constant highb : integer := 5 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0 ;
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
variable v_st_rec3 : st_rec3 := c_st_rec3_1 ;
--
BEGIN
v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) :=
c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2)) ;
assert NOT(v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2)
report "***PASSED TEST: c08s05b00x00p03n01i01367"
severity NOTE;
assert (v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2)
report "***FAILED TEST: c08s05b00x00p03n01i01367 - The types of the variable and the assigned variable must match."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01367arch;
|
gpl-2.0
|
8405ae9bc140f917f0ffc9ad57ad4fd1
| 0.583612 | 2.923556 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_05.vhd
| 4 | 2,634 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_21_fg_21_05.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity SR_flipflop is
port ( s_n, r_n : in bit; q, q_n : inout bit );
begin
postponed process (q, q_n) is
begin
assert now = 0 fs or q = not q_n
report "implementation error: q /= not q_n";
end postponed process;
end entity SR_flipflop;
--------------------------------------------------
architecture dataflow of SR_flipflop is
begin
gate_1 : q <= s_n nand q_n;
gate_2 : q_n <= r_n nand q;
end architecture dataflow;
-- not in book
entity fg_21_05 is
end entity fg_21_05;
architecture test of fg_21_05 is
signal s_n, r_n, q, q_n : bit;
begin
dut : entity work.SR_flipflop
port map ( s_n, r_n, q, q_n );
s_n <= '1',
'0' after 10 ns, '1' after 15 ns,
'0' after 30 ns, '1' after 40 ns;
r_n <= '0', '1' after 5 ns,
'0' after 20 ns, '1' after 25 ns,
'0' after 30 ns, '1' after 35 ns;
end architecture test;
-- end not in book
|
gpl-2.0
|
ced99608417048433d7646bcffbb7a12
| 0.432422 | 4.806569 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_and2.vhd
| 4 | 1,917 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_and2 is
end entity tb_and2;
library ieee; use ieee.std_logic_1164.all;
architecture test of tb_and2 is
signal a, b : std_ulogic := '0';
signal y : std_ulogic;
begin
dut : entity work.and2(detailed_delay)
port map ( a => a, b => b, y => y );
stimulus : process is
begin
wait for 10 ns;
a <= '1'; wait for 10 ns;
b <= '1'; wait for 10 ns;
b <= '0'; wait for 10 ns;
b <= '1', '0' after 250 ps; wait for 10 ns;
b <= '1', '0' after 350 ps; wait for 10 ns;
b <= '1', '0' after 450 ps; wait for 10 ns;
b <= '1', '0' after 550 ps; wait for 10 ns;
b <= '1', '0' after 650 ps; wait for 10 ns;
b <= '1', '0' after 750 ps; wait for 10 ns;
b <= '1', '0' after 850 ps; wait for 10 ns;
b <= '1'; wait for 10 ns;
b <= '0', '1' after 250 ps; wait for 10 ns;
b <= '0', '1' after 350 ps; wait for 10 ns;
b <= '0', '1' after 450 ps; wait for 10 ns;
b <= 'X'; wait for 10 ns;
b <= '0'; wait for 10 ns;
b <= 'X', '0' after 250 ps; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
7e34641d5f53b53349d6b92a7c82a157
| 0.61398 | 3.195 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1957.vhd
| 4 | 1,768 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1957.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p02n02i01957ent IS
END c07s02b01x00p02n02i01957ent;
ARCHITECTURE c07s02b01x00p02n02i01957arch OF c07s02b01x00p02n02i01957ent IS
BEGIN
TESTING: PROCESS
variable a : boolean := TRUE;
variable b : boolean := FALSE;
variable c : boolean;
BEGIN
c := a or b;
assert NOT(c=TRUE)
report "***PASSED TEST: c07s02b01x00p02n02i01957"
severity NOTE;
assert ( c=TRUE )
report "***FAILED TEST: c07s02b01x00p02n02i01957 - Logical operation of 'OR'."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p02n02i01957arch;
|
gpl-2.0
|
720ea5b9a9fc904aeb8c2c1cecb2fb41
| 0.664027 | 3.66805 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_09.vhd
| 4 | 1,701 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_09 is
end entity inline_09;
----------------------------------------------------------------
architecture test of inline_09 is
begin
process is
use std.textio.all;
variable L : line;
begin
write(L, 42, justified => left, field => 5);
writeline(output, L);
write(L, 42, justified => right, field => 5);
writeline(output, L);
write(L, 123, field => 2);
writeline(output, L);
-- code from book:
write ( L, string'( "fred" ) );
write ( L, ' ' );
write ( L, bit_vector'( X"3A" ) );
-- end of code from book
writeline(output, L);
write(L, 3.14159, digits => 2);
writeline(output, L);
write(L, 123.4567, digits => 0);
writeline(output, L);
write(L, 40 ns, unit => ps);
writeline(output, L);
write(L, 23 us, unit => ms);
writeline(output, L);
wait;
end process;
end architecture test;
|
gpl-2.0
|
d2e2f5627e972197f2684413e49ce521
| 0.629042 | 3.839729 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_Multiplication/Serial_Mul_Paar/multiplier_131_1.vhd
| 1 | 17,351 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--------------------------------------------------------
-- Con celda y sin maquina de estados
--------------------------------------------------------
-- x^131 + x^8 + x^3 + x^2 + 1
entity serial_multiplier_131 is
generic (
NUM_BITS : positive := 131 -- The order of the finite field
);
port(
ax : in std_logic_vector(NUM_BITS-1 downto 0);
bx : in std_logic_vector(NUM_BITS-1 downto 0);
cx : out std_logic_vector(NUM_BITS-1 downto 0); -- cx = ax*bx mod Fx
reset : in std_logic;
clk : in std_logic;
done : out std_logic
);
end serial_multiplier_131;
-----------------------------------------------------------
architecture behave of serial_multiplier_131 is
-----------------------------------------------------------
signal bx_shift : std_logic_vector(NUM_BITS-1 downto 0); -- B and C shifted one position to the rigth
signal bx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal cx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal counter: std_logic_vector(7 downto 0); -- 8-bit counter, controling the number of iterations: m
signal done_int : std_logic;
--señales para las xor de la reduccion:
signal xor_1 : std_logic;
signal xor_2 : std_logic;
signal xor_3 : std_logic;
-----------------------------------------------------------
-- States for the finite state machine
-----------------------------------------------------------
--type CurrentState_type is (NOTHING, END_STATE, MUL_STATE);
--signal CurrentState: CurrentState_type;
-----------------------------------------------------------
begin
-----------------------------------------------------------
xor_1 <= Cx_int(1) xor Cx_int(NUM_BITS-1);
xor_2 <= Cx_int(2) xor Cx_int(NUM_BITS-1);
xor_3 <= Cx_int(7) xor Cx_int(NUM_BITS-1);
--Bx_shift <= bx_int(NUM_BITS-2 downto 0)& '0'; -- Shift Bx to left one position
bx_int <= Bx_shift;
------------------------------------------------------------
-- The finite state machine, it takes m cycles to compute
-- the multiplication, a counter is used to keep this count
------------------------------------------------------------
CELL_0: ENTITY basic_cell(behave)
PORT MAP(Ax(0),Bx_int(NUM_BITS-1),Cx_int(NUM_BITS-1),clk,reset,Cx_int(0));
CELL_1: ENTITY basic_cell(behave)
PORT MAP(Ax(1),Bx_int(NUM_BITS-1),Cx_int(0),clk,reset,Cx_int(1));
CELL_2: ENTITY basic_cell(behave)
PORT MAP(Ax(2),Bx_int(NUM_BITS-1),xor_1,clk,reset,Cx_int(2));
CELL_3: ENTITY basic_cell(behave)
PORT MAP(Ax(3),Bx_int(NUM_BITS-1),xor_2,clk,reset,Cx_int(3));
CELL_4: ENTITY basic_cell(behave)
PORT MAP(Ax(4),Bx_int(NUM_BITS-1),Cx_int(3),clk,reset,Cx_int(4));
CELL_5: ENTITY basic_cell(behave)
PORT MAP(Ax(5),Bx_int(NUM_BITS-1),Cx_int(4),clk,reset,Cx_int(5));
CELL_6: ENTITY basic_cell(behave)
PORT MAP(Ax(6),Bx_int(NUM_BITS-1),Cx_int(5),clk,reset,Cx_int(6));
CELL_7: ENTITY basic_cell(behave)
PORT MAP(Ax(7),Bx_int(NUM_BITS-1),Cx_int(6),clk,reset,Cx_int(7));
CELL_8: ENTITY basic_cell(behave)
PORT MAP(Ax(8),Bx_int(NUM_BITS-1),xor_3,clk,reset,Cx_int(8));
CELL_9: ENTITY basic_cell(behave)
PORT MAP(Ax(9),Bx_int(NUM_BITS-1),Cx_int(8),clk,reset,Cx_int(9));
CELL_10: ENTITY basic_cell(behave)
PORT MAP(Ax(10),Bx_int(NUM_BITS-1),Cx_int(9),clk,reset,Cx_int(10));
CELL_11: ENTITY basic_cell(behave)
PORT MAP(Ax(11),Bx_int(NUM_BITS-1),Cx_int(10),clk,reset,Cx_int(11));
CELL_12: ENTITY basic_cell(behave)
PORT MAP(Ax(12),Bx_int(NUM_BITS-1),Cx_int(11),clk,reset,Cx_int(12));
CELL_13: ENTITY basic_cell(behave)
PORT MAP(Ax(13),Bx_int(NUM_BITS-1),Cx_int(12),clk,reset,Cx_int(13));
CELL_14: ENTITY basic_cell(behave)
PORT MAP(Ax(14),Bx_int(NUM_BITS-1),Cx_int(13),clk,reset,Cx_int(14));
CELL_15: ENTITY basic_cell(behave)
PORT MAP(Ax(15),Bx_int(NUM_BITS-1),Cx_int(14),clk,reset,Cx_int(15));
CELL_16: ENTITY basic_cell(behave)
PORT MAP(Ax(16),Bx_int(NUM_BITS-1),Cx_int(15),clk,reset,Cx_int(16));
CELL_17: ENTITY basic_cell(behave)
PORT MAP(Ax(17),Bx_int(NUM_BITS-1),Cx_int(16),clk,reset,Cx_int(17));
CELL_18: ENTITY basic_cell(behave)
PORT MAP(Ax(18),Bx_int(NUM_BITS-1),Cx_int(17),clk,reset,Cx_int(18));
CELL_19: ENTITY basic_cell(behave)
PORT MAP(Ax(19),Bx_int(NUM_BITS-1),Cx_int(18),clk,reset,Cx_int(19));
CELL_20: ENTITY basic_cell(behave)
PORT MAP(Ax(20),Bx_int(NUM_BITS-1),Cx_int(19),clk,reset,Cx_int(20));
CELL_21: ENTITY basic_cell(behave)
PORT MAP(Ax(21),Bx_int(NUM_BITS-1),Cx_int(20),clk,reset,Cx_int(21));
CELL_22: ENTITY basic_cell(behave)
PORT MAP(Ax(22),Bx_int(NUM_BITS-1),Cx_int(21),clk,reset,Cx_int(22));
CELL_23: ENTITY basic_cell(behave)
PORT MAP(Ax(23),Bx_int(NUM_BITS-1),Cx_int(22),clk,reset,Cx_int(23));
CELL_24: ENTITY basic_cell(behave)
PORT MAP(Ax(24),Bx_int(NUM_BITS-1),Cx_int(23),clk,reset,Cx_int(24));
CELL_25: ENTITY basic_cell(behave)
PORT MAP(Ax(25),Bx_int(NUM_BITS-1),Cx_int(24),clk,reset,Cx_int(25));
CELL_26: ENTITY basic_cell(behave)
PORT MAP(Ax(26),Bx_int(NUM_BITS-1),Cx_int(25),clk,reset,Cx_int(26));
CELL_27: ENTITY basic_cell(behave)
PORT MAP(Ax(27),Bx_int(NUM_BITS-1),Cx_int(26),clk,reset,Cx_int(27));
CELL_28: ENTITY basic_cell(behave)
PORT MAP(Ax(28),Bx_int(NUM_BITS-1),Cx_int(27),clk,reset,Cx_int(28));
CELL_29: ENTITY basic_cell(behave)
PORT MAP(Ax(29),Bx_int(NUM_BITS-1),Cx_int(28),clk,reset,Cx_int(29));
CELL_30: ENTITY basic_cell(behave)
PORT MAP(Ax(30),Bx_int(NUM_BITS-1),Cx_int(29),clk,reset,Cx_int(30));
CELL_31: ENTITY basic_cell(behave)
PORT MAP(Ax(31),Bx_int(NUM_BITS-1),Cx_int(30),clk,reset,Cx_int(31));
CELL_32: ENTITY basic_cell(behave)
PORT MAP(Ax(32),Bx_int(NUM_BITS-1),Cx_int(31),clk,reset,Cx_int(32));
CELL_33: ENTITY basic_cell(behave)
PORT MAP(Ax(33),Bx_int(NUM_BITS-1),Cx_int(32),clk,reset,Cx_int(33));
CELL_34: ENTITY basic_cell(behave)
PORT MAP(Ax(34),Bx_int(NUM_BITS-1),Cx_int(33),clk,reset,Cx_int(34));
CELL_35: ENTITY basic_cell(behave)
PORT MAP(Ax(35),Bx_int(NUM_BITS-1),Cx_int(34),clk,reset,Cx_int(35));
CELL_36: ENTITY basic_cell(behave)
PORT MAP(Ax(36),Bx_int(NUM_BITS-1),Cx_int(35),clk,reset,Cx_int(36));
CELL_37: ENTITY basic_cell(behave)
PORT MAP(Ax(37),Bx_int(NUM_BITS-1),Cx_int(36),clk,reset,Cx_int(37));
CELL_38: ENTITY basic_cell(behave)
PORT MAP(Ax(38),Bx_int(NUM_BITS-1),Cx_int(37),clk,reset,Cx_int(38));
CELL_39: ENTITY basic_cell(behave)
PORT MAP(Ax(39),Bx_int(NUM_BITS-1),Cx_int(38),clk,reset,Cx_int(39));
CELL_40: ENTITY basic_cell(behave)
PORT MAP(Ax(40),Bx_int(NUM_BITS-1),Cx_int(39),clk,reset,Cx_int(40));
CELL_41: ENTITY basic_cell(behave)
PORT MAP(Ax(41),Bx_int(NUM_BITS-1),Cx_int(40),clk,reset,Cx_int(41));
CELL_42: ENTITY basic_cell(behave)
PORT MAP(Ax(42),Bx_int(NUM_BITS-1),Cx_int(41),clk,reset,Cx_int(42));
CELL_43: ENTITY basic_cell(behave)
PORT MAP(Ax(43),Bx_int(NUM_BITS-1),Cx_int(42),clk,reset,Cx_int(43));
CELL_44: ENTITY basic_cell(behave)
PORT MAP(Ax(44),Bx_int(NUM_BITS-1),Cx_int(43),clk,reset,Cx_int(44));
CELL_45: ENTITY basic_cell(behave)
PORT MAP(Ax(45),Bx_int(NUM_BITS-1),Cx_int(44),clk,reset,Cx_int(45));
CELL_46: ENTITY basic_cell(behave)
PORT MAP(Ax(46),Bx_int(NUM_BITS-1),Cx_int(45),clk,reset,Cx_int(46));
CELL_47: ENTITY basic_cell(behave)
PORT MAP(Ax(47),Bx_int(NUM_BITS-1),Cx_int(46),clk,reset,Cx_int(47));
CELL_48: ENTITY basic_cell(behave)
PORT MAP(Ax(48),Bx_int(NUM_BITS-1),Cx_int(47),clk,reset,Cx_int(48));
CELL_49: ENTITY basic_cell(behave)
PORT MAP(Ax(49),Bx_int(NUM_BITS-1),Cx_int(48),clk,reset,Cx_int(49));
CELL_50: ENTITY basic_cell(behave)
PORT MAP(Ax(50),Bx_int(NUM_BITS-1),Cx_int(49),clk,reset,Cx_int(50));
CELL_51: ENTITY basic_cell(behave)
PORT MAP(Ax(51),Bx_int(NUM_BITS-1),Cx_int(50),clk,reset,Cx_int(51));
CELL_52: ENTITY basic_cell(behave)
PORT MAP(Ax(52),Bx_int(NUM_BITS-1),Cx_int(51),clk,reset,Cx_int(52));
CELL_53: ENTITY basic_cell(behave)
PORT MAP(Ax(53),Bx_int(NUM_BITS-1),Cx_int(52),clk,reset,Cx_int(53));
CELL_54: ENTITY basic_cell(behave)
PORT MAP(Ax(54),Bx_int(NUM_BITS-1),Cx_int(53),clk,reset,Cx_int(54));
CELL_55: ENTITY basic_cell(behave)
PORT MAP(Ax(55),Bx_int(NUM_BITS-1),Cx_int(54),clk,reset,Cx_int(55));
CELL_56: ENTITY basic_cell(behave)
PORT MAP(Ax(56),Bx_int(NUM_BITS-1),Cx_int(55),clk,reset,Cx_int(56));
CELL_57: ENTITY basic_cell(behave)
PORT MAP(Ax(57),Bx_int(NUM_BITS-1),Cx_int(56),clk,reset,Cx_int(57));
CELL_58: ENTITY basic_cell(behave)
PORT MAP(Ax(58),Bx_int(NUM_BITS-1),Cx_int(57),clk,reset,Cx_int(58));
CELL_59: ENTITY basic_cell(behave)
PORT MAP(Ax(59),Bx_int(NUM_BITS-1),Cx_int(58),clk,reset,Cx_int(59));
CELL_60: ENTITY basic_cell(behave)
PORT MAP(Ax(60),Bx_int(NUM_BITS-1),Cx_int(59),clk,reset,Cx_int(60));
CELL_61: ENTITY basic_cell(behave)
PORT MAP(Ax(61),Bx_int(NUM_BITS-1),Cx_int(60),clk,reset,Cx_int(61));
CELL_62: ENTITY basic_cell(behave)
PORT MAP(Ax(62),Bx_int(NUM_BITS-1),Cx_int(61),clk,reset,Cx_int(62));
CELL_63: ENTITY basic_cell(behave)
PORT MAP(Ax(63),Bx_int(NUM_BITS-1),Cx_int(62),clk,reset,Cx_int(63));
CELL_64: ENTITY basic_cell(behave)
PORT MAP(Ax(64),Bx_int(NUM_BITS-1),Cx_int(63),clk,reset,Cx_int(64));
CELL_65: ENTITY basic_cell(behave)
PORT MAP(Ax(65),Bx_int(NUM_BITS-1),Cx_int(64),clk,reset,Cx_int(65));
CELL_66: ENTITY basic_cell(behave)
PORT MAP(Ax(66),Bx_int(NUM_BITS-1),Cx_int(65),clk,reset,Cx_int(66));
CELL_67: ENTITY basic_cell(behave)
PORT MAP(Ax(67),Bx_int(NUM_BITS-1),Cx_int(66),clk,reset,Cx_int(67));
CELL_68: ENTITY basic_cell(behave)
PORT MAP(Ax(68),Bx_int(NUM_BITS-1),Cx_int(67),clk,reset,Cx_int(68));
CELL_69: ENTITY basic_cell(behave)
PORT MAP(Ax(69),Bx_int(NUM_BITS-1),Cx_int(68),clk,reset,Cx_int(69));
CELL_70: ENTITY basic_cell(behave)
PORT MAP(Ax(70),Bx_int(NUM_BITS-1),Cx_int(69),clk,reset,Cx_int(70));
CELL_71: ENTITY basic_cell(behave)
PORT MAP(Ax(71),Bx_int(NUM_BITS-1),Cx_int(70),clk,reset,Cx_int(71));
CELL_72: ENTITY basic_cell(behave)
PORT MAP(Ax(72),Bx_int(NUM_BITS-1),Cx_int(71),clk,reset,Cx_int(72));
CELL_73: ENTITY basic_cell(behave)
PORT MAP(Ax(73),Bx_int(NUM_BITS-1),Cx_int(72),clk,reset,Cx_int(73));
CELL_74: ENTITY basic_cell(behave)
PORT MAP(Ax(74),Bx_int(NUM_BITS-1),Cx_int(73),clk,reset,Cx_int(74));
CELL_75: ENTITY basic_cell(behave)
PORT MAP(Ax(75),Bx_int(NUM_BITS-1),Cx_int(74),clk,reset,Cx_int(75));
CELL_76: ENTITY basic_cell(behave)
PORT MAP(Ax(76),Bx_int(NUM_BITS-1),Cx_int(75),clk,reset,Cx_int(76));
CELL_77: ENTITY basic_cell(behave)
PORT MAP(Ax(77),Bx_int(NUM_BITS-1),Cx_int(76),clk,reset,Cx_int(77));
CELL_78: ENTITY basic_cell(behave)
PORT MAP(Ax(78),Bx_int(NUM_BITS-1),Cx_int(77),clk,reset,Cx_int(78));
CELL_79: ENTITY basic_cell(behave)
PORT MAP(Ax(79),Bx_int(NUM_BITS-1),Cx_int(78),clk,reset,Cx_int(79));
CELL_80: ENTITY basic_cell(behave)
PORT MAP(Ax(80),Bx_int(NUM_BITS-1),Cx_int(79),clk,reset,Cx_int(80));
CELL_81: ENTITY basic_cell(behave)
PORT MAP(Ax(81),Bx_int(NUM_BITS-1),Cx_int(80),clk,reset,Cx_int(81));
CELL_82: ENTITY basic_cell(behave)
PORT MAP(Ax(82),Bx_int(NUM_BITS-1),Cx_int(81),clk,reset,Cx_int(82));
CELL_83: ENTITY basic_cell(behave)
PORT MAP(Ax(83),Bx_int(NUM_BITS-1),Cx_int(82),clk,reset,Cx_int(83));
CELL_84: ENTITY basic_cell(behave)
PORT MAP(Ax(84),Bx_int(NUM_BITS-1),Cx_int(83),clk,reset,Cx_int(84));
CELL_85: ENTITY basic_cell(behave)
PORT MAP(Ax(85),Bx_int(NUM_BITS-1),Cx_int(84),clk,reset,Cx_int(85));
CELL_86: ENTITY basic_cell(behave)
PORT MAP(Ax(86),Bx_int(NUM_BITS-1),Cx_int(85),clk,reset,Cx_int(86));
CELL_87: ENTITY basic_cell(behave)
PORT MAP(Ax(87),Bx_int(NUM_BITS-1),Cx_int(86),clk,reset,Cx_int(87));
CELL_88: ENTITY basic_cell(behave)
PORT MAP(Ax(88),Bx_int(NUM_BITS-1),Cx_int(87),clk,reset,Cx_int(88));
CELL_89: ENTITY basic_cell(behave)
PORT MAP(Ax(89),Bx_int(NUM_BITS-1),Cx_int(88),clk,reset,Cx_int(89));
CELL_90: ENTITY basic_cell(behave)
PORT MAP(Ax(90),Bx_int(NUM_BITS-1),Cx_int(89),clk,reset,Cx_int(90));
CELL_91: ENTITY basic_cell(behave)
PORT MAP(Ax(91),Bx_int(NUM_BITS-1),Cx_int(90),clk,reset,Cx_int(91));
CELL_92: ENTITY basic_cell(behave)
PORT MAP(Ax(92),Bx_int(NUM_BITS-1),Cx_int(91),clk,reset,Cx_int(92));
CELL_93: ENTITY basic_cell(behave)
PORT MAP(Ax(93),Bx_int(NUM_BITS-1),Cx_int(92),clk,reset,Cx_int(93));
CELL_94: ENTITY basic_cell(behave)
PORT MAP(Ax(94),Bx_int(NUM_BITS-1),Cx_int(93),clk,reset,Cx_int(94));
CELL_95: ENTITY basic_cell(behave)
PORT MAP(Ax(95),Bx_int(NUM_BITS-1),Cx_int(94),clk,reset,Cx_int(95));
CELL_96: ENTITY basic_cell(behave)
PORT MAP(Ax(96),Bx_int(NUM_BITS-1),Cx_int(95),clk,reset,Cx_int(96));
CELL_97: ENTITY basic_cell(behave)
PORT MAP(Ax(97),Bx_int(NUM_BITS-1),Cx_int(96),clk,reset,Cx_int(97));
CELL_98: ENTITY basic_cell(behave)
PORT MAP(Ax(98),Bx_int(NUM_BITS-1),Cx_int(97),clk,reset,Cx_int(98));
CELL_99: ENTITY basic_cell(behave)
PORT MAP(Ax(99),Bx_int(NUM_BITS-1),Cx_int(98),clk,reset,Cx_int(99));
CELL_100: ENTITY basic_cell(behave)
PORT MAP(Ax(100),Bx_int(NUM_BITS-1),Cx_int(99),clk,reset,Cx_int(100));
CELL_101: ENTITY basic_cell(behave)
PORT MAP(Ax(101),Bx_int(NUM_BITS-1),Cx_int(100),clk,reset,Cx_int(101));
CELL_102: ENTITY basic_cell(behave)
PORT MAP(Ax(102),Bx_int(NUM_BITS-1),Cx_int(101),clk,reset,Cx_int(102));
CELL_103: ENTITY basic_cell(behave)
PORT MAP(Ax(103),Bx_int(NUM_BITS-1),Cx_int(102),clk,reset,Cx_int(103));
CELL_104: ENTITY basic_cell(behave)
PORT MAP(Ax(104),Bx_int(NUM_BITS-1),Cx_int(103),clk,reset,Cx_int(104));
CELL_105: ENTITY basic_cell(behave)
PORT MAP(Ax(105),Bx_int(NUM_BITS-1),Cx_int(104),clk,reset,Cx_int(105));
CELL_106: ENTITY basic_cell(behave)
PORT MAP(Ax(106),Bx_int(NUM_BITS-1),Cx_int(105),clk,reset,Cx_int(106));
CELL_107: ENTITY basic_cell(behave)
PORT MAP(Ax(107),Bx_int(NUM_BITS-1),Cx_int(106),clk,reset,Cx_int(107));
CELL_108: ENTITY basic_cell(behave)
PORT MAP(Ax(108),Bx_int(NUM_BITS-1),Cx_int(107),clk,reset,Cx_int(108));
CELL_109: ENTITY basic_cell(behave)
PORT MAP(Ax(109),Bx_int(NUM_BITS-1),Cx_int(108),clk,reset,Cx_int(109));
CELL_110: ENTITY basic_cell(behave)
PORT MAP(Ax(110),Bx_int(NUM_BITS-1),Cx_int(109),clk,reset,Cx_int(110));
CELL_111: ENTITY basic_cell(behave)
PORT MAP(Ax(111),Bx_int(NUM_BITS-1),Cx_int(110),clk,reset,Cx_int(111));
CELL_112: ENTITY basic_cell(behave)
PORT MAP(Ax(112),Bx_int(NUM_BITS-1),Cx_int(111),clk,reset,Cx_int(112));
CELL_113: ENTITY basic_cell(behave)
PORT MAP(Ax(113),Bx_int(NUM_BITS-1),Cx_int(112),clk,reset,Cx_int(113));
CELL_114: ENTITY basic_cell(behave)
PORT MAP(Ax(114),Bx_int(NUM_BITS-1),Cx_int(113),clk,reset,Cx_int(114));
CELL_115: ENTITY basic_cell(behave)
PORT MAP(Ax(115),Bx_int(NUM_BITS-1),Cx_int(114),clk,reset,Cx_int(115));
CELL_116: ENTITY basic_cell(behave)
PORT MAP(Ax(116),Bx_int(NUM_BITS-1),Cx_int(115),clk,reset,Cx_int(116));
CELL_117: ENTITY basic_cell(behave)
PORT MAP(Ax(117),Bx_int(NUM_BITS-1),Cx_int(116),clk,reset,Cx_int(117));
CELL_118: ENTITY basic_cell(behave)
PORT MAP(Ax(118),Bx_int(NUM_BITS-1),Cx_int(117),clk,reset,Cx_int(118));
CELL_119: ENTITY basic_cell(behave)
PORT MAP(Ax(119),Bx_int(NUM_BITS-1),Cx_int(118),clk,reset,Cx_int(119));
CELL_120: ENTITY basic_cell(behave)
PORT MAP(Ax(120),Bx_int(NUM_BITS-1),Cx_int(119),clk,reset,Cx_int(120));
CELL_121: ENTITY basic_cell(behave)
PORT MAP(Ax(121),Bx_int(NUM_BITS-1),Cx_int(120),clk,reset,Cx_int(121));
CELL_122: ENTITY basic_cell(behave)
PORT MAP(Ax(122),Bx_int(NUM_BITS-1),Cx_int(121),clk,reset,Cx_int(122));
CELL_123: ENTITY basic_cell(behave)
PORT MAP(Ax(123),Bx_int(NUM_BITS-1),Cx_int(122),clk,reset,Cx_int(123));
CELL_124: ENTITY basic_cell(behave)
PORT MAP(Ax(124),Bx_int(NUM_BITS-1),Cx_int(123),clk,reset,Cx_int(124));
CELL_125: ENTITY basic_cell(behave)
PORT MAP(Ax(125),Bx_int(NUM_BITS-1),Cx_int(124),clk,reset,Cx_int(125));
CELL_126: ENTITY basic_cell(behave)
PORT MAP(Ax(126),Bx_int(NUM_BITS-1),Cx_int(125),clk,reset,Cx_int(126));
CELL_127: ENTITY basic_cell(behave)
PORT MAP(Ax(127),Bx_int(NUM_BITS-1),Cx_int(126),clk,reset,Cx_int(127));
CELL_128: ENTITY basic_cell(behave)
PORT MAP(Ax(128),Bx_int(NUM_BITS-1),Cx_int(127),clk,reset,Cx_int(128));
CELL_129: ENTITY basic_cell(behave)
PORT MAP(Ax(129),Bx_int(NUM_BITS-1),Cx_int(128),clk,reset,Cx_int(129));
CELL_130: ENTITY basic_cell(behave)
PORT MAP(Ax(130),Bx_int(NUM_BITS-1),Cx_int(129),clk,reset,Cx_int(130));
done <= done_int;
FSM_MUL: process (CLK)
Begin
if CLK'event and CLK = '1' then
if Reset = '1' then
counter <= "10000011"; -- m value, in this case, it is 112, be sure to set the correct value
cx <= (others => '0');
Done_int <= '0';
else
if counter = "0000000" then -- The done signal is asserted at the same time that the result is computed.
if (done_int = '0') then
done_int <= '1';
Cx <= Cx_int;
end if;
else
counter <= counter - 1;
end if;
end if;
end if;
end process;
SHIFT_REGISTER: process (CLK)
Begin
if CLK'event and CLK = '1' then
if Reset = '1' then
Bx_shift <= Bx;
else
Bx_shift <= Bx_shift(NUM_BITS-2 downto 0) & '0'; -- carga paralela
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
520f52b5e7c2fcde320af8731a396038
| 0.647513 | 2.417247 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/perf02/compressed.vhd
| 3 | 1,406 |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity compressed is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
wa0_en : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
wa0_data : in std_logic_vector(31 downto 0)
);
end compressed;
architecture augh of compressed is
-- Embedded RAM
type ram_type is array (0 to 127) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
gpl-2.0
|
d813ffb58dc1bbee6b0cb646cd45c6c8
| 0.674964 | 2.935282 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_divider/Shantz/SingleFile/f2m_divider_409.vhd
| 1 | 8,920 |
---------------------------------------------------------------------------------------------------
-- divider_f2m.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Inverter for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: This is an implementation of the division algorithm. Dirent to the other implemented inverter
-- in this, the division is performed directly.
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity f2m_divider_409 is
generic(
NUM_BITS : positive := 409
);
port(
x : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
y : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
done : out STD_LOGIC;
Ux : out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of f2m_divider_409 is
----------------------------------------------------------------------------------------------------
-- Signal for up-date regsiters A and B
signal A,B : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal U, V : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
----------------------------------------------------------------------------------------------------
-- m = 163, the irreductible polynomial
--constant F : std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001001";
-- m = 233 x233 + x74 + 1
--constant F: std_logic_vector(NUM_BITS downto 0) := "100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000001";
-- m = 277 x277 + x74 + 1
--constant F: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000001001001"; --277 bits
-- m = 283 x283 + x12 + x7 + x5 + 1
--constant F: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000010100001";
-- m = 409 x409 + x87 + 1
constant F: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
-- m = 571 x571 + x10 + x5 + x2 + 1
--constant F: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000100101";
----------------------------------------------------------------------------------------------------
-- control signals
signal a_greater_b, a_eq_b, A_par, B_par, U_par, V_par, u_mas_v_par: std_logic;
signal A_div_t, B_div_t, U_div_t, V_div_t : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal u_mas_M, v_mas_M, u_mas_v, u_mas_v_mas_M, a_mas_b : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal u_mas_M_div_t, v_mas_M_div_t, u_mas_v_div_t, u_mas_v_mas_M_div_t, a_mas_b_div_t: STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
----------------------------------------------------------------------------------------------------------------------------------------------------------
type CurrentState_type is (END_STATE, INIT, CYCLE);
signal currentState: CurrentState_type;
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- Control signals
A_par <= '1' when A(0) = '0' else
'0';
B_par <= '1' when B(0) = '0' else
'0';
U_par <= '1' when U(0) = '0' else
'0';
V_par <= '1' when V(0) = '0' else
'0';
a_greater_b <= '1' when A > B else
'0';
a_eq_b <= '1' when A = B else
'0';
----------------------------------------------------------------------------------------------------
-- Mux definitions
----------------------------------------------------------------------------------------------------
u_mas_M <= U xor F;
v_mas_M <= V xor F;
u_mas_v <= U xor V;
u_mas_v_mas_M <= u_mas_v xor F;
a_mas_b <= A xor B;
-- Muxes for A and B
a_div_t <= '0'& A(NUM_BITS downto 1);
b_div_t <= '0'& B(NUM_BITS downto 1);
u_div_t <= '0'& U(NUM_BITS downto 1);
v_div_t <= '0'& V(NUM_BITS downto 1);
u_mas_M_div_t <= '0' & u_mas_M(NUM_BITS downto 1);
v_mas_M_div_t <= '0' & v_mas_M(NUM_BITS downto 1);
u_mas_v_div_t <= '0' & u_mas_v(NUM_BITS downto 1);
u_mas_v_mas_M_div_t <= '0' & u_mas_v_mas_M(NUM_BITS downto 1);
a_mas_b_div_t <= '0' & a_mas_b(NUM_BITS downto 1);
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
EEAL: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if (rst = '1')then
A <= '0' & y;
B <= F;
U <= '0' & x;
v <= (others => '0');
Ux <= (others => '0');
done <= '0';
currentState <= CYCLE;
else
case currentState is
-----------------------------------------------------------------------------------
when CYCLE =>
if A_eq_B = '1' then
currentState <= END_STATE;
Done <= '1';
Ux <= U(NUM_BITS-1 downto 0);
elsif A_par = '1' then
A <= A_div_t;
if U_par = '1' then
U <= U_div_t;
else
U <= u_mas_M_div_t;
end if;
elsif B_par = '1' then
B <= B_div_t;
if V_par = '1' then
V <= V_div_t;
else
V <= V_mas_M_div_t;
end if;
elsif a_greater_b = '1' then
A <= a_mas_b_div_t;
if u_mas_v(0) = '0' then
U <= u_mas_v_div_t;
else
U <= u_mas_v_mas_M_div_t;
end if;
else
B <= a_mas_b_div_t;
if u_mas_v(0) = '0' then
V <= u_mas_v_div_t;
else
V <= u_mas_v_mas_M_div_t;
end if;
end if;
-----------------------------------------------------------------------------------
when END_STATE => -- Do nothing
currentState <= END_STATE;
done <= '0'; -- para generar el pulso, quitarlo entity caso contrario
-----------------------------------------------------------------------------------
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
51cbeff440b50ba3b88dc0cf4ae398f0
| 0.499103 | 4.772606 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc3123.vhd
| 4 | 6,633 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3123.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b01x02p01n01i03123ent_a IS
generic ( socket_g1 : Boolean;
socket_g2 : Bit;
socket_g3 : character;
socket_g4 : severity_level;
socket_g5 : integer;
socket_g6 : real;
socket_g7 : time;
socket_g8 : natural;
socket_g9 : positive
);
port ( socket_p1 : inout Boolean;
socket_p2 : inout Bit;
socket_p3 : inout character;
socket_p4 : inout severity_level;
socket_p5 : inout integer;
socket_p6 : inout real;
socket_p7 : inout time;
socket_p8 : inout natural;
socket_p9 : inout positive
);
END c05s02b01x02p01n01i03123ent_a;
ARCHITECTURE c05s02b01x02p01n01i03123arch_a OF c05s02b01x02p01n01i03123ent_a IS
BEGIN
socket_p1 <= socket_g1 after 22 ns;
socket_p2 <= socket_g2 after 22 ns;
socket_p3 <= socket_g3 after 22 ns;
socket_p4 <= socket_g4 after 22 ns;
socket_p5 <= socket_g5 after 22 ns;
socket_p6 <= socket_g6 after 22 ns;
socket_p7 <= socket_g7 after 22 ns;
socket_p8 <= socket_g8 after 22 ns;
socket_p9 <= socket_g9 after 22 ns;
END c05s02b01x02p01n01i03123arch_a;
ENTITY c05s02b01x02p01n01i03123ent IS
END c05s02b01x02p01n01i03123ent;
ARCHITECTURE c05s02b01x02p01n01i03123arch OF c05s02b01x02p01n01i03123ent IS
component ic_socket
generic ( socket_g1 : Boolean;
socket_g2 : Bit;
socket_g3 : character;
socket_g4 : severity_level;
socket_g5 : integer;
socket_g6 : real;
socket_g7 : time;
socket_g8 : natural;
socket_g9 : positive
);
port ( socket_p1 : inout Boolean;
socket_p2 : inout Bit;
socket_p3 : inout character;
socket_p4 : inout severity_level;
socket_p5 : inout integer;
socket_p6 : inout real;
socket_p7 : inout time;
socket_p8 : inout natural;
socket_p9 : inout positive
);
end component;
signal socket_p1 : Boolean;
signal socket_p2 : Bit;
signal socket_p3 : character;
signal socket_p4 : severity_level;
signal socket_p5 : integer;
signal socket_p6 : real;
signal socket_p7 : time;
signal socket_p8 : natural;
signal socket_p9 : positive;
BEGIN
instance : ic_socket
generic map ( true,
'1',
'$',
warning,
-100002,
-9.999,
20 ns,
23423,
4564576
)
port map ( socket_p1,
socket_p2,
socket_p3,
socket_p4,
socket_p5,
socket_p6,
socket_p7,
socket_p8,
socket_p9
);
TESTING: PROCESS
BEGIN
wait for 30 ns;
assert NOT( socket_p1 = true and
socket_p2 = '1' and
socket_p3 = '$' and
socket_p4 = warning and
socket_p5 = -100002 and
socket_p6 = -9.999 and
socket_p7 = 20 ns and
socket_p8 = 23423 and
socket_p9 = 4564576 )
report "***PASSED TEST: c05s02b01x02p01n01i03123"
severity NOTE;
assert ( socket_p1 = true and
socket_p2 = '1' and
socket_p3 = '$' and
socket_p4 = warning and
socket_p5 = -100002 and
socket_p6 = -9.999 and
socket_p7 = 20 ns and
socket_p8 = 23423 and
socket_p9 = 4564576 )
report "***FAILED TEST: c05s02b01x02p01n01i03123 - Positional association generic and port list test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b01x02p01n01i03123arch;
configuration c05s02b01x02p01n01i03123cfg of c05s02b01x02p01n01i03123ent is
for c05s02b01x02p01n01i03123arch
for instance : ic_socket use entity work.c05s02b01x02p01n01i03123ent_a (c05s02b01x02p01n01i03123arch_a)
generic map ( socket_g1,
socket_g2,
socket_g3,
socket_g4,
socket_g5,
socket_g6,
socket_g7,
socket_g8,
socket_g9
)
port map ( socket_p1,
socket_p2,
socket_p3,
socket_p4,
socket_p5,
socket_p6,
socket_p7,
socket_p8,
socket_p9
);
end for;
end for;
end c05s02b01x02p01n01i03123cfg;
|
gpl-2.0
|
7ff525a61ea87669b31fe76b912ade02
| 0.484547 | 4.076829 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_08.vhd
| 4 | 1,782 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_tb_05_08.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
architecture do_nothing of ROM is
begin
end architecture do_nothing;
entity tb_05_08 is
end entity tb_05_08;
architecture test of tb_05_08 is
signal address : natural := 0;
signal data : bit_vector(0 to 7);
signal enable : bit := '0';
begin
dut : entity work.ROM(do_nothing)
port map ( address => address, data => data, enable => enable );
stimulus : process is
begin
wait for 100 ns;
address <= 1000; wait for 10 ns;
enable <= '1', '0' after 10 ns; wait for 90 ns;
address <= 1004; wait for 10 ns;
enable <= '1', '0' after 10 ns; wait for 90 ns;
address <= 1008; wait for 10 ns;
enable <= '1', '0' after 10 ns; wait for 90 ns;
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
7921a9bce9f9c3b6c1ebaa862bf729cd
| 0.623457 | 3.783439 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/hold_time_checker.vhd
| 4 | 1,565 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity hold_time_checker is
end entity hold_time_checker;
architecture test of hold_time_checker is
constant Thold_d_clk : delay_length := 3 ns;
signal clk, d : bit := '0';
begin
-- code from book
hold_time_checker : process ( clk, d ) is
variable last_clk_edge_time : time := 0 fs;
begin
if clk'event and clk = '1' then
last_clk_edge_time := now;
end if;
if d'event then
assert now - last_clk_edge_time >= Thold_d_clk
report "hold time violation";
end if;
end process hold_time_checker;
-- end code from book
clk_gen : clk <= '1' after 10 ns, '0' after 20 ns when clk = '0';
stimulus : d <= '1' after 15 ns,
'0' after 53 ns,
'1' after 72 ns;
end architecture test;
|
gpl-2.0
|
ecd2189ee1b6a0155d91f328e377a142
| 0.670927 | 3.771084 | false | true | false | false |
jakubcabal/pipemania-fpga-game
|
source/comp/base/debouncer.vhd
| 1 | 1,342 |
--------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: DEBOUNCER
-- AUTHORS: Jakub Cabal <[email protected]>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/pipemania-fpga-game
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DEBOUNCER is
Port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- High active asynchronous reset
DIN : in std_logic; -- Data input
DOUT : out std_logic -- Debounced data output
);
end DEBOUNCER;
architecture FULL of DEBOUNCER is
signal data_shreg : std_logic_vector(3 downto 0);
signal data_deb_reg : std_logic;
begin
DOUT <= data_deb_reg;
process (CLK, RST)
begin
if (RST = '1') then
data_shreg <= (others => '0');
data_deb_reg <= '0';
elsif (rising_edge(CLK)) then
data_shreg <= data_shreg(2 downto 0) & DIN;
data_deb_reg <= data_shreg(0) AND data_shreg(1) AND
data_shreg(2) AND data_shreg(3);
end if;
end process;
end FULL;
|
mit
|
ee142ff9b61450e7cd0ef7b8f6817225
| 0.480626 | 4.19375 | false | false | false | false |
stnolting/neo430
|
rtl/core/neo430_top.vhd
| 1 | 34,906 |
-- #################################################################################################
-- # << NEO430 - Processor Top Entity >> #
-- # ********************************************************************************************* #
-- # This is the top entity of the NEO430 processor. Instantiate this unit in your own project and #
-- # define all the configuration generics according to your needs. Alternatively, you can use one #
-- # of the other top entities provided in rtl\top_templates #
-- # Check the processor's documentary for more information: doc\NEO430.pdf #
-- # ********************************************************************************************* #
-- # The NEO430 processor: #
-- # - Reset and clock generators #
-- # - External IRQ synchronizer #
-- # - NEO430 CPU (MSP430(TM)-ISA-compatible) (CPU) #
-- # - Internal RAM or ROM (configurable size) for code (IMEM) #
-- # - Internal RAM (configurable size) for data (and code) (DMEM) #
-- # - Sysconfig (infomem for various system information) (SYSCONFIG) #
-- # - Optional 16-bit multiplier/divider unit (MULDIV) #
-- # - Optional 16-bit IN and 16-bit OUT GPIO port with pin-change interrupt (GPIO) #
-- # - Optional 32-bit Wishbone interface (WB32) #
-- # - Optional High precision timer (TIMER) #
-- # - Optional Universal Asynchronous Receiver and Transmitter (UART) #
-- # - Optional Serial Peripheral Interface (SPI) #
-- # - Optional Internal ROM for bootloader (BOOTLD) #
-- # - Optional Watchdog Timer (WDT) #
-- # - Optional CRC16/32 Module (CRC16/32) #
-- # - Optional Custom Functions Unit to implement user-defined processor extension (CFU) #
-- # - Optional Pulse Width Modulation controller (PWM) #
-- # - Optional Two Wire Serial Interface (TWI) #
-- # - Optional True Random Number Generator (TRNG) #
-- # - Optional External Interrupts Controller (EXIRQ) #
-- # - Optional Arbitrary Frequency Generator (FREQ_GEN) #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
entity neo430_top is
generic (
-- general configuration --
CLOCK_SPEED : natural := 100000000; -- main clock in Hz
IMEM_SIZE : natural := 4*1024; -- internal IMEM size in bytes, max 48kB (default=4kB)
DMEM_SIZE : natural := 2*1024; -- internal DMEM size in bytes, max 12kB (default=2kB)
-- additional configuration --
USER_CODE : std_ulogic_vector(15 downto 0) := x"0000"; -- custom user code
-- module configuration --
MULDIV_USE : boolean := true; -- implement multiplier/divider unit? (default=true)
WB32_USE : boolean := true; -- implement WB32 unit? (default=true)
WDT_USE : boolean := true; -- implement WDT? (default=true)
GPIO_USE : boolean := true; -- implement GPIO unit? (default=true)
TIMER_USE : boolean := true; -- implement timer? (default=true)
UART_USE : boolean := true; -- implement UART? (default=true)
CRC_USE : boolean := true; -- implement CRC unit? (default=true)
CFU_USE : boolean := false; -- implement custom functions unit? (default=false)
PWM_USE : boolean := true; -- implement PWM controller? (default=true)
TWI_USE : boolean := true; -- implement two wire serial interface? (default=true)
SPI_USE : boolean := true; -- implement SPI? (default=true)
TRNG_USE : boolean := false; -- implement TRNG? (default=false)
EXIRQ_USE : boolean := true; -- implement EXIRQ? (default=true)
FREQ_GEN_USE : boolean := true; -- implement FREQ_GEN? (default=true)
-- boot configuration --
BOOTLD_USE : boolean := true; -- implement and use bootloader? (default=true)
IMEM_AS_ROM : boolean := false -- implement IMEM as read-only memory? (default=false)
);
port (
-- global control --
clk_i : in std_ulogic; -- global clock, rising edge
rst_i : in std_ulogic; -- global reset, async, LOW-active
-- parallel io --
gpio_o : out std_ulogic_vector(15 downto 0); -- parallel output
gpio_i : in std_ulogic_vector(15 downto 0); -- parallel input
-- pwm channels --
pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels
-- arbitrary frequency generator --
freq_gen_o : out std_ulogic_vector(02 downto 0); -- programmable frequency output
-- serial com --
uart_txd_o : out std_ulogic; -- UART send data
uart_rxd_i : in std_ulogic; -- UART receive data
spi_sclk_o : out std_ulogic; -- serial clock line
spi_mosi_o : out std_ulogic; -- serial data line out
spi_miso_i : in std_ulogic; -- serial data line in
spi_cs_o : out std_ulogic_vector(05 downto 0); -- SPI CS
twi_sda_io : inout std_logic; -- twi serial data line
twi_scl_io : inout std_logic; -- twi serial clock line
-- 32-bit wishbone interface --
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
wb_we_o : out std_ulogic; -- read/write
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
wb_stb_o : out std_ulogic; -- strobe
wb_cyc_o : out std_ulogic; -- valid cycle
wb_ack_i : in std_ulogic; -- transfer acknowledge
-- external interrupts --
ext_irq_i : in std_ulogic_vector(07 downto 0); -- external interrupt request lines (active HI)
ext_ack_o : out std_ulogic_vector(07 downto 0) -- external interrupt request acknowledges
);
end neo430_top;
architecture neo430_top_rtl of neo430_top is
-- generators --
signal rst_i_sync0 : std_ulogic;
signal rst_i_sync1 : std_ulogic;
signal rst_gen : std_ulogic_vector(03 downto 0) := (others => '0'); -- reset on bitstream upload
signal ext_rst : std_ulogic;
signal sys_rst : std_ulogic;
signal wdt_rst : std_ulogic;
signal clk_div : std_ulogic_vector(11 downto 0);
signal clk_div_ff : std_ulogic_vector(11 downto 0);
signal clk_gen : std_ulogic_vector(07 downto 0);
signal timer_cg_en : std_ulogic;
signal uart_cg_en : std_ulogic;
signal spi_cg_en : std_ulogic;
signal wdt_cg_en : std_ulogic;
signal pwm_cg_en : std_ulogic;
signal twi_cg_en : std_ulogic;
signal cfu_cg_en : std_ulogic;
signal freq_gen_cg_en : std_ulogic;
type cpu_bus_t is record
rd_en : std_ulogic;
wr_en : std_ulogic_vector(01 downto 0);
addr : std_ulogic_vector(15 downto 0);
rdata : std_ulogic_vector(15 downto 0);
wdata : std_ulogic_vector(15 downto 0);
end record;
-- main CPU communication bus --
signal cpu_bus : cpu_bus_t;
signal io_acc : std_ulogic;
signal io_wr_en : std_ulogic;
signal io_rd_en : std_ulogic;
-- read-back data buses --
signal rom_rdata : std_ulogic_vector(15 downto 0);
signal ram_rdata : std_ulogic_vector(15 downto 0);
signal muldiv_rdata : std_ulogic_vector(15 downto 0);
signal wb_rdata : std_ulogic_vector(15 downto 0);
signal boot_rdata : std_ulogic_vector(15 downto 0);
signal wdt_rdata : std_ulogic_vector(15 downto 0);
signal timer_rdata : std_ulogic_vector(15 downto 0);
signal uart_rdata : std_ulogic_vector(15 downto 0);
signal spi_rdata : std_ulogic_vector(15 downto 0);
signal gpio_rdata : std_ulogic_vector(15 downto 0);
signal crc_rdata : std_ulogic_vector(15 downto 0);
signal cfu_rdata : std_ulogic_vector(15 downto 0);
signal pwm_rdata : std_ulogic_vector(15 downto 0);
signal twi_rdata : std_ulogic_vector(15 downto 0);
signal trng_rdata : std_ulogic_vector(15 downto 0);
signal exirq_rdata : std_ulogic_vector(15 downto 0);
signal freq_gen_rdata : std_ulogic_vector(15 downto 0);
signal sysconfig_rdata : std_ulogic_vector(15 downto 0);
-- interrupt system --
signal irq : std_ulogic_vector(03 downto 0);
signal timer_irq : std_ulogic;
signal uart_irq : std_ulogic;
signal spi_irq : std_ulogic;
signal twi_irq : std_ulogic;
signal gpio_irq : std_ulogic;
signal ext_irq : std_ulogic;
-- misc --
signal imem_up_en : std_ulogic;
signal gpio_pwm : std_ulogic;
begin
-- Reset Generator ----------------------------------------------------------
-- -----------------------------------------------------------------------------
-- make sure the external reset is free of metastability and has a minimal duration of 1 clock cycle
reset_generator_filter: process(clk_i)
begin
if rising_edge(clk_i) then
rst_i_sync0 <= rst_i;
rst_i_sync1 <= rst_i_sync0; -- no metastability, thanks
end if;
end process reset_generator_filter;
-- keep internal reset active for at least 4 clock cycles
reset_generator: process(rst_i_sync1, clk_i)
begin
if rising_edge(clk_i) then
if (rst_i_sync1 = '0') then
rst_gen <= (others => '0');
else
rst_gen <= rst_gen(rst_gen'left-1 downto 0) & '1';
end if;
end if;
end process reset_generator;
ext_rst <= rst_gen(rst_gen'left); -- the beautified external reset signal
sys_rst <= ext_rst and wdt_rst;
-- Clock Generator ----------------------------------------------------------
-- -----------------------------------------------------------------------------
clock_generator: process(sys_rst, clk_i)
begin
if (sys_rst = '0') then
clk_div <= (others => '0');
elsif rising_edge(clk_i) then
-- anybody needing fresh clocks?
if ((timer_cg_en or uart_cg_en or spi_cg_en or wdt_cg_en or pwm_cg_en or twi_cg_en or cfu_cg_en or freq_gen_cg_en) = '1') then
clk_div <= std_ulogic_vector(unsigned(clk_div) + 1);
end if;
end if;
end process clock_generator;
clock_generator_buf: process(clk_i)
begin
if rising_edge(clk_i) then
clk_div_ff <= clk_div;
end if;
end process clock_generator_buf;
-- clock enable select: rising edge detectors --
clk_gen(clk_div2_c) <= clk_div(0) and (not clk_div_ff(0)); -- CLK/2
clk_gen(clk_div4_c) <= clk_div(1) and (not clk_div_ff(1)); -- CLK/4
clk_gen(clk_div8_c) <= clk_div(2) and (not clk_div_ff(2)); -- CLK/8
clk_gen(clk_div64_c) <= clk_div(5) and (not clk_div_ff(5)); -- CLK/64
clk_gen(clk_div128_c) <= clk_div(6) and (not clk_div_ff(6)); -- CLK/128
clk_gen(clk_div1024_c) <= clk_div(9) and (not clk_div_ff(9)); -- CLK/1024
clk_gen(clk_div2048_c) <= clk_div(10) and (not clk_div_ff(10)); -- CLK/2048
clk_gen(clk_div4096_c) <= clk_div(11) and (not clk_div_ff(11)); -- CLK/4096
-- The core of the problem: The CPU -----------------------------------------
-- -----------------------------------------------------------------------------
neo430_cpu_inst: neo430_cpu
generic map (
BOOTLD_USE => BOOTLD_USE, -- implement and use bootloader? (default=true)
IMEM_AS_ROM => IMEM_AS_ROM -- implement IMEM as read-only memory?
)
port map (
-- global control --
clk_i => clk_i, -- global clock, rising edge
rst_i => sys_rst, -- global reset, low-active, async
-- memory interface --
mem_rd_o => cpu_bus.rd_en, -- memory read
mem_imwe_o => imem_up_en, -- allow writing to IMEM
mem_wr_o => cpu_bus.wr_en, -- memory write
mem_addr_o => cpu_bus.addr, -- address
mem_data_o => cpu_bus.wdata, -- write data
mem_data_i => cpu_bus.rdata, -- read data
-- interrupt system --
irq_i => irq -- interrupt request lines
);
-- final CPU read data --
cpu_bus.rdata <= rom_rdata or ram_rdata or boot_rdata or muldiv_rdata or
wb_rdata or uart_rdata or spi_rdata or gpio_rdata or freq_gen_rdata or
timer_rdata or wdt_rdata or sysconfig_rdata or crc_rdata or
cfu_rdata or pwm_rdata or twi_rdata or trng_rdata or exirq_rdata;
-- interrupts: priority assignment --
irq(0) <= timer_irq; -- timer match (highest priority)
irq(1) <= uart_irq or spi_irq or twi_irq; -- serial IRQ
irq(2) <= gpio_irq; -- GPIO input pin change
irq(3) <= ext_irq; -- external interrupt request (lowest priority)
-- Main Memory (ROM/IMEM & RAM/DMEM) ----------------------------------------
-- -----------------------------------------------------------------------------
neo430_imem_inst: neo430_imem
generic map (
IMEM_SIZE => IMEM_SIZE, -- internal IMEM size in bytes, max 32kB (default=4kB)
IMEM_AS_ROM => IMEM_AS_ROM, -- implement IMEM as read-only memory?
BOOTLD_USE => BOOTLD_USE -- implement and use bootloader? (default=true)
)
port map (
clk_i => clk_i, -- global clock line
rden_i => cpu_bus.rd_en, -- read enable
wren_i => cpu_bus.wr_en, -- write enable
upen_i => imem_up_en, -- update enable
addr_i => cpu_bus.addr, -- address
data_i => cpu_bus.wdata, -- data in
data_o => rom_rdata -- data out
);
neo430_dmem_inst: neo430_dmem
generic map (
DMEM_SIZE => DMEM_SIZE -- internal DMEM size in bytes, max 28kB (default=2kB)
)
port map (
clk_i => clk_i, -- global clock line
rden_i => cpu_bus.rd_en, -- read enable
wren_i => cpu_bus.wr_en, -- write enable
addr_i => cpu_bus.addr, -- address
data_i => cpu_bus.wdata, -- data in
data_o => ram_rdata -- data out
);
-- Boot ROM -----------------------------------------------------------------
-- -----------------------------------------------------------------------------
neo430_boot_rom_inst_true:
if (BOOTLD_USE = true) generate
neo430_boot_rom_inst: neo430_boot_rom
port map (
clk_i => clk_i, -- global clock line
rden_i => cpu_bus.rd_en, -- read enable
addr_i => cpu_bus.addr, -- address
data_o => boot_rdata -- data out
);
end generate;
neo430_boot_rom_inst_false:
if (BOOTLD_USE = false) generate
boot_rdata <= (others => '0');
end generate;
-- IO Access? ---------------------------------------------------------------
-- -----------------------------------------------------------------------------
io_acc <= '1' when (cpu_bus.addr(15 downto index_size_f(io_size_c)) = io_base_c(15 downto index_size_f(io_size_c))) else '0';
io_rd_en <= cpu_bus.rd_en and io_acc;
io_wr_en <= (cpu_bus.wr_en(0) or cpu_bus.wr_en(1)) and io_acc; -- use all accesses as full-word accesses
-- Multiplier/Divider Unit (MULDIV) -----------------------------------------
-- -----------------------------------------------------------------------------
neo430_muldiv_inst_true:
if (MULDIV_USE = true) generate
neo430_muldiv_inst: neo430_muldiv
port map (
-- host access --
clk_i => clk_i, -- global clock line
rden_i => io_rd_en, -- read enable
wren_i => io_wr_en, -- write enable
addr_i => cpu_bus.addr, -- address
data_i => cpu_bus.wdata, -- data in
data_o => muldiv_rdata -- data out
);
end generate;
neo430_muldiv_inst_false:
if (MULDIV_USE = false) generate
muldiv_rdata <= (others => '0');
end generate;
-- Wishbone Adapter (WB32) --------------------------------------------------
-- -----------------------------------------------------------------------------
neo430_wb32_if_inst_true:
if (WB32_USE = true) generate
neo430_wb32_inst: neo430_wb_interface
port map (
-- host access --
clk_i => clk_i, -- global clock line
rden_i => io_rd_en, -- read enable
wren_i => io_wr_en, -- write enable
addr_i => cpu_bus.addr, -- address
data_i => cpu_bus.wdata, -- data in
data_o => wb_rdata, -- data out
-- wishbone interface --
wb_adr_o => wb_adr_o, -- address
wb_dat_i => wb_dat_i, -- read data
wb_dat_o => wb_dat_o, -- write data
wb_we_o => wb_we_o, -- read/write
wb_sel_o => wb_sel_o, -- byte enable
wb_stb_o => wb_stb_o, -- strobe
wb_cyc_o => wb_cyc_o, -- valid cycle
wb_ack_i => wb_ack_i -- transfer acknowledge
);
end generate;
neo430_wb32_if_inst_false:
if (WB32_USE = false) generate
wb_rdata <= (others => '0');
wb_adr_o <= (others => '0');
wb_dat_o <= (others => '0');
wb_we_o <= '0';
wb_sel_o <= (others => '0');
wb_stb_o <= '0';
wb_cyc_o <= '0';
end generate;
-- Universal Asynchronous Receiver & Transmitter (UART) ---------------------
-- -----------------------------------------------------------------------------
neo430_uart_inst_true:
if (UART_USE = true) generate
neo430_uart_inst: neo430_uart
port map (
-- host access --
clk_i => clk_i, -- global clock line
rden_i => io_rd_en, -- read enable
wren_i => io_wr_en, -- write enable
addr_i => cpu_bus.addr, -- address
data_i => cpu_bus.wdata, -- data in
data_o => uart_rdata, -- data out
-- clock generator --
clkgen_en_o => uart_cg_en, -- enable clock generator
clkgen_i => clk_gen,
-- com lines --
uart_txd_o => uart_txd_o,
uart_rxd_i => uart_rxd_i,
-- interrupts --
uart_irq_o => uart_irq -- uart rx/tx interrupt
);
end generate;
neo430_uart_inst_false:
if (UART_USE = false) generate
uart_rdata <= (others => '0');
uart_irq <= '0';
uart_cg_en <= '0';
uart_txd_o <= '1';
end generate;
-- Serial Peripheral Interface (SPI) ----------------------------------------
-- -----------------------------------------------------------------------------
neo430_spi_inst_true:
if (SPI_USE = true) generate
neo430_spi_inst: neo430_spi
port map (
-- host access --
clk_i => clk_i, -- global clock line
rden_i => io_rd_en, -- read enable
wren_i => io_wr_en, -- write enable
addr_i => cpu_bus.addr, -- address
data_i => cpu_bus.wdata, -- data in
data_o => spi_rdata, -- data out
-- clock generator --
clkgen_en_o => spi_cg_en, -- enable clock generator
clkgen_i => clk_gen,
-- com lines --
spi_sclk_o => spi_sclk_o, -- SPI serial clock
spi_mosi_o => spi_mosi_o, -- SPI master out, slave in
spi_miso_i => spi_miso_i, -- SPI master in, slave out
spi_cs_o => spi_cs_o, -- SPI CS 0..5
-- interrupt --
spi_irq_o => spi_irq -- transmission done interrupt
);
end generate;
neo430_spi_inst_false:
if (SPI_USE = false) generate
spi_rdata <= (others => '0');
spi_cg_en <= '0';
spi_sclk_o <= '0';
spi_mosi_o <= '0';
spi_cs_o <= (others => '1');
spi_irq <= '0';
end generate;
-- General Purpose Parallel IO (GPIO) ---------------------------------------
-- -----------------------------------------------------------------------------
neo430_gpio_inst_true:
if (GPIO_USE = true) generate
neo430_gpio_inst: neo430_gpio
port map (
-- host access --
clk_i => clk_i, -- global clock line
rden_i => io_rd_en, -- read enable
wren_i => io_wr_en, -- write enable
addr_i => cpu_bus.addr, -- address
data_i => cpu_bus.wdata, -- data in
data_o => gpio_rdata, -- data out
-- parallel io --
gpio_o => gpio_o,
gpio_i => gpio_i,
-- GPIO PWM --
gpio_pwm_i => gpio_pwm,
-- interrupt --
irq_o => gpio_irq -- pin-change interrupt
);
end generate;
neo430_gpio_inst_false:
if (GPIO_USE = false) generate
gpio_rdata <= (others => '0');
gpio_o <= (others => '0');
gpio_irq <= '0';
end generate;
-- High Precision Timer (TIMER) ---------------------------------------------
-- -----------------------------------------------------------------------------
neo430_timer_inst_true:
if (TIMER_USE = true) generate
neo430_timer_inst: neo430_timer
port map (
-- host access --
clk_i => clk_i, -- global clock line
rden_i => io_rd_en, -- read enable
wren_i => io_wr_en, -- write enable
addr_i => cpu_bus.addr, -- address
data_i => cpu_bus.wdata, -- data in
data_o => timer_rdata, -- data out
-- clock generator --
clkgen_en_o => timer_cg_en, -- enable clock generator
clkgen_i => clk_gen,
-- interrupt --
irq_o => timer_irq -- interrupt request
);
end generate;
neo430_timer_inst_false:
if (TIMER_USE = false) generate
timer_rdata <= (others => '0');
timer_irq <= '0';
timer_cg_en <= '0';
end generate;
-- Watchdog Timer (WDT) -----------------------------------------------------
-- -----------------------------------------------------------------------------
neo430_wdt_inst_true:
if (WDT_USE = true) generate
neo430_wdt_inst: neo430_wdt
port map(
-- host access --
clk_i => clk_i, -- global clock line
rst_i => ext_rst, -- external reset, low-active, use as async
rden_i => io_rd_en, -- read enable
wren_i => io_wr_en, -- write enable
addr_i => cpu_bus.addr, -- address
data_i => cpu_bus.wdata, -- data in
data_o => wdt_rdata, -- data out
-- clock generator --
clkgen_en_o => wdt_cg_en, -- enable clock generator
clkgen_i => clk_gen, -- clock generator
-- system reset --
rst_o => wdt_rst -- timeout reset, low-active, use as async
);
end generate;
neo430_wdt_inst_false:
if (WDT_USE = false) generate
wdt_rdata <= (others => '0');
wdt_rst <= '1';
wdt_cg_en <= '0';
end generate;
-- Checksum Module (CRC) ----------------------------------------------------
-- -----------------------------------------------------------------------------
neo430_crc_inst_true:
if (CRC_USE = true) generate
neo430_crc_inst: neo430_crc
port map(
-- host access --
clk_i => clk_i, -- global clock line
rden_i => io_rd_en, -- read enable
wren_i => io_wr_en, -- write enable
addr_i => cpu_bus.addr, -- address
data_i => cpu_bus.wdata, -- data in
data_o => crc_rdata -- data out
);
end generate;
neo430_crc_inst_false:
if (CRC_USE = false) generate
crc_rdata <= (others => '0');
end generate;
-- Custom Functions Unit (CFU) ----------------------------------------------
-- -----------------------------------------------------------------------------
neo430_cfu_inst_true:
if (CFU_USE = true) generate
neo430_cfu_inst: neo430_cfu
port map(
-- host access --
clk_i => clk_i, -- global clock line
rden_i => io_rd_en, -- read enable
wren_i => io_wr_en, -- write enable
addr_i => cpu_bus.addr, -- address
data_i => cpu_bus.wdata, -- data in
data_o => cfu_rdata, -- data out
-- clock generator --
clkgen_en_o => cfu_cg_en, -- enable clock generator
clkgen_i => clk_gen
-- add custom IOs below --
);
end generate;
neo430_cfu_inst_false:
if (CFU_USE = false) generate
cfu_cg_en <= '0';
cfu_rdata <= (others => '0');
end generate;
-- PWM Controller (PWM) -----------------------------------------------------
-- -----------------------------------------------------------------------------
neo430_pwm_inst_true:
if (PWM_USE = true) generate
neo430_pwm_inst: neo430_pwm
port map(
-- host access --
clk_i => clk_i, -- global clock line
rden_i => io_rd_en, -- read enable
wren_i => io_wr_en, -- write enable
addr_i => cpu_bus.addr, -- address
data_i => cpu_bus.wdata, -- data in
data_o => pwm_rdata, -- data out
-- clock generator --
clkgen_en_o => pwm_cg_en, -- enable clock generator
clkgen_i => clk_gen,
-- GPIO output PWM --
gpio_pwm_o => gpio_pwm,
-- pwm output channels --
pwm_o => pwm_o
);
end generate;
neo430_pwm_inst_false:
if (PWM_USE = false) generate
pwm_cg_en <= '0';
gpio_pwm <= '1';
pwm_rdata <= (others => '0');
pwm_o <= (others => '0');
end generate;
-- Two Wire Serial Interface (SPI) ------------------------------------------
-- -----------------------------------------------------------------------------
neo430_twi_inst_true:
if (TWI_USE = true) generate
neo430_twi_inst: neo430_twi
port map (
-- host access --
clk_i => clk_i, -- global clock line
rden_i => io_rd_en, -- read enable
wren_i => io_wr_en, -- write enable
addr_i => cpu_bus.addr, -- address
data_i => cpu_bus.wdata, -- data in
data_o => twi_rdata, -- data out
-- clock generator --
clkgen_en_o => twi_cg_en, -- enable clock generator
clkgen_i => clk_gen,
-- com lines --
twi_sda_io => twi_sda_io, -- serial data line
twi_scl_io => twi_scl_io, -- serial clock line
-- interrupt --
twi_irq_o => twi_irq -- transfer done IRQ
);
end generate;
neo430_twi_inst_false:
if (TWI_USE = false) generate
twi_cg_en <= '0';
twi_rdata <= (others => '0');
twi_irq <= '0';
end generate;
-- True Random Number Generator (TRNG) --------------------------------------
-- -----------------------------------------------------------------------------
neo430_trng_inst_true:
if (TRNG_USE = true) generate
neo430_trng_inst: neo430_trng
port map (
-- host access --
clk_i => clk_i, -- global clock line
rden_i => io_rd_en, -- read enable
wren_i => io_wr_en, -- write enable
addr_i => cpu_bus.addr, -- address
data_i => cpu_bus.wdata, -- data in
data_o => trng_rdata -- data out
);
end generate;
neo430_trng_inst_false:
if (TRNG_USE = false) generate
trng_rdata <= (others => '0');
end generate;
-- External Interrupts Controller (EXIRQ) -----------------------------------
-- -----------------------------------------------------------------------------
neo430_exirq_inst_true:
if (EXIRQ_USE = true) generate
neo430_exirq_inst: neo430_exirq
port map (
-- host access --
clk_i => clk_i, -- global clock line
rden_i => io_rd_en, -- read enable
wren_i => io_wr_en, -- write enable
addr_i => cpu_bus.addr, -- address
data_i => cpu_bus.wdata, -- data in
data_o => exirq_rdata, -- data out
-- cpu interrupt --
cpu_irq_o => ext_irq,
-- external interrupt lines --
ext_irq_i => ext_irq_i, -- IRQ
ext_ack_o => ext_ack_o -- acknowledge
);
end generate;
neo430_exirq_inst_false:
if (EXIRQ_USE = false) generate
exirq_rdata <= (others => '0');
ext_ack_o <= (others => '0');
ext_irq <= '0';
end generate;
-- Arbitrary Frequency Generator (FREW_GEN)) --------------------------------
-- -----------------------------------------------------------------------------
neo430_freq_gen_inst_true:
if (FREQ_GEN_USE = true) generate
neo430_freq_gen_inst: neo430_freq_gen
port map (
-- host access --
clk_i => clk_i, -- global clock line
rden_i => io_rd_en, -- read enable
wren_i => io_wr_en, -- write enable
addr_i => cpu_bus.addr, -- address
data_i => cpu_bus.wdata, -- data in
data_o => freq_gen_rdata, -- data out
-- clock generator --
clkgen_en_o => freq_gen_cg_en, -- enable clock generator
clkgen_i => clk_gen,
-- frequency generator --
freq_gen_o => freq_gen_o -- programmable frequency output
);
end generate;
neo430_freq_gen_inst_false:
if (FREQ_GEN_USE = false) generate
freq_gen_cg_en <= '0';
freq_gen_rdata <= (others => '0');
freq_gen_o <= (others => '0');
end generate;
-- System Configuration -----------------------------------------------------
-- -----------------------------------------------------------------------------
neo430_sysconfig_inst: neo430_sysconfig
generic map (
-- general configuration --
CLOCK_SPEED => CLOCK_SPEED, -- main clock in Hz
IMEM_SIZE => IMEM_SIZE, -- internal IMEM size in bytes
DMEM_SIZE => DMEM_SIZE, -- internal DMEM size in bytes
-- additional configuration --
USER_CODE => USER_CODE, -- custom user code
-- module configuration --
MULDIV_USE => MULDIV_USE, -- implement multiplier/divider unit?
WB32_USE => WB32_USE, -- implement WB32 unit?
WDT_USE => WDT_USE, -- implement WDT?
GPIO_USE => GPIO_USE, -- implement GPIO unit?
TIMER_USE => TIMER_USE, -- implement timer?
UART_USE => UART_USE, -- implement UART?
CRC_USE => CRC_USE, -- implement CRC unit?
CFU_USE => CFU_USE, -- implement CFU?
PWM_USE => PWM_USE, -- implement PWM?
TWI_USE => TWI_USE, -- implement TWI?
SPI_USE => SPI_USE, -- implement SPI?
TRNG_USE => TRNG_USE, -- implement TRNG?
EXIRQ_USE => EXIRQ_USE, -- implement EXIRQ?
FREQ_GEN_USE => FREQ_GEN_USE, -- implement FREQ_GEN?
-- boot configuration --
BOOTLD_USE => BOOTLD_USE, -- implement and use bootloader?
IMEM_AS_ROM => IMEM_AS_ROM -- implement IMEM as read-only memory?
)
port map (
clk_i => clk_i, -- global clock line
rden_i => io_rd_en, -- read enable
wren_i => io_wr_en, -- write enable
addr_i => cpu_bus.addr, -- address
data_i => cpu_bus.wdata, -- data in
data_o => sysconfig_rdata -- data out
);
end neo430_top_rtl;
|
bsd-3-clause
|
c541e2e8938339245bc0542dc502630d
| 0.481722 | 3.916302 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/PLL.vhd
| 4 | 2,460 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
library ieee; use ieee.math_real.all;
entity PLL is
generic ( Fp : real := 20.0e3; -- loop filter pole freq [Hz]
Fz : real := 1.0e6; -- loop filter zero freq [Hz]
Kv : real := 100.0e3; -- VCO gain [Hz/V]
Fc : real := 1.0e6 ); -- VCO center freq [Hz]
port ( terminal input, lf_out, vco_out : electrical );
end entity PLL;
----------------------------------------------------------------
architecture behavioral of PLL is
quantity v_in across input to electrical_ref;
quantity v_lf across i_lf through lf_out to electrical_ref;
quantity v_vco across i_vco through vco_out to electrical_ref;
-- internal quantities and constants
-- multiplier
quantity mult : real;
-- loop filter (Lag)
constant wp : real := math_2_pi * fp; -- pole freq in rad/s
constant wz : real := math_2_pi * fz; -- zero freq in rad/s
constant num : real_vector := (1.0, 1.0 / wz); -- numerator array
constant den : real_vector := (1.0, 1.0 / wp); -- denominator array
-- VCO
quantity phi : real; -- used in VCO equation
constant Kv_w : real := math_2_pi * Kv; -- change gain to (rad/s)/V
constant wc : real := math_2_pi * Fc; -- change freq to rad/s
begin
if domain = quiescent_domain use
phi == 0.0; -- initialize phi
else
phi'dot == wc + Kv_w * (v_lf); -- calculate VCO frequency
end use;
mult == v_in * v_vco; -- multiplier output
v_lf == mult'ltf(num, den); -- loop filter output
v_vco == cos(phi); -- VCO output
end architecture behavioral;
|
gpl-2.0
|
df887865ba70a84fbca7b2ff17e34e2b
| 0.630894 | 3.693694 | false | false | false | false |
bmikaili/TUM-ERA-Praktikum-SS17-Gruppe-45
|
Projekt2/Implementierung/stp.vhdl
| 1 | 4,620 |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
-----------------------------------
--------------ENTITY---------------
-----------------------------------
entity audiostp is
port (
sclk, fsync, sdata : in std_logic; -- Eingänge definieren
left, right : out signed (17 downto 0); -- 18 Bit Ausgabewerte
flag : out std_logic -- 1 Bit Ausgabeflag
);
end audiostp;
-------------ENTITY END------------
-----------------------------------
-----------ARCHITECTURE------------
-----------------------------------
architecture converter of audiostp is
-----------------------------------
---------SIGNAL DEFINITION---------
-----------------------------------
signal ileft, iright : signed (17 downto 0) := "000000000000000000"; -- interne Zwischenspeicherung der seriellen Daten
signal iflag : unsigned (0 downto 0) := "0"; -- internes Flag um zu speichern, ob sowohl left, als auch
-- right eingelesen wurden und zur Ausgabe bereit sind
signal hflag : unsigned (0 downto 0) := "0"; -- internes Hilfsflag
signal counter : unsigned(4 downto 0) := "10001"; -- Zähler um serielle Daten in Vektor einzufügen
signal rightold : signed ( 17 downto 0 ) := "000000000000000000"; -- Hilfsvariable weil right output nicht gelesen werden kann
signal leftold : signed ( 17 downto 0 ) := "000000000000000000"; -- Hilfsvariable weil left output nicht gelesen werden kann
--------SIGNAL DEFINITION END------
begin -- Architecture begin
-----------------------------------
--------------SPLIT----------------
-----------------------------------
process (fsync, sclk) -- nur wenn sclk sich ändert, wird process betreten
begin
if falling_edge(fsync) or rising_edge(fsync) then -- Wenn fsync sich ändert wird counter zurückgesetzt
counter <= "10001";
elsif falling_edge (sclk) then -- wenn es sich um eine fallende Kante von sclk handelt
case fsync is -- Je nach aktuellem Wert von fsync wird ...
when '1' => ileft (to_integer(unsigned(counter))) <= sdata; -- ... sdata in den 'linken' Vektor an Stelle 'counter' eingefügt
when others => iright (to_integer(unsigned(counter))) <= sdata; -- ... oder in den 'rechten' Vektor eingefügt
end case;
if counter > 0 then
counter <= counter - 1 ; -- nach dem Einfügen wird counter um 1 dekrementiert
end if;
if counter = 0 then -- wenn counter = 0,
iflag <= iflag + 1; -- wird i_flag invertiert (markiert, dass left bzw.
-- right nun vollständig ist)
end if;
end if;
end process;
-------------SPLIT END-------------
-----------------------------------
--------------OUTPUT---------------
-----------------------------------
hflag <= "1" when iflag = "0" -- Wenn i_flag auf 0 gesetzt ist, wird h_flag auf 1 gesetzt.
-- Da dies in einem Concurrent Statement geschieht, wird die
-- Aenderung des h_flags erst beim nächsten Durchlauf für
-- die anderen Statements sichtbar, was ermöglich, dass
-- das Ausgabeflag im nächsten Takt wieder auf 0 gesetzt wird.
-- wenn i_flag auf 1 gesetzt ist, wird h_flag auf wieder auf 0 gesetzt
else "0";
rightold <= iright when iflag = "0" and hflag = "0" -- erst wenn i_flag wieder auf 0 gesetzt wurde (also nach
-- einem kompletten left-right Zyklus) und das Hilfsflag
-- auf 0 steht (siehe h_flag), wird dem Ausgang 'right' der
-- neue Wert von i_right zugewiesen
else rightold; -- ansonsten bleibt der Wert von right beibehalten.
leftold <= ileft when iflag = "0" and hflag = "0" -- analog zur Zuweisung von right
else leftold;
left <= leftold;
right <= rightold;
flag <= '1' when iflag = "0" and hflag = "0" -- Ausgabeflag wird für einen Takt auf 1 gesetzt wenn i_flag
-- auf 0 steht (also nach einem kompletten left-right Zyklus)
-- und h_flag auch auf 0 steht.
else '0'; -- Da h_flag im nächsten Durchlauf bereits auf 1 steht (siehe h_flag)
-- wird Ausgabeflag im nächsten Durchlauf wieder auf 0 gesetzt.
-------------OUTPUT END------------
end converter;
----------ARCHITECTURE END---------
|
gpl-3.0
|
46078d753926c36f47248f353a5f4e79
| 0.521399 | 4.041264 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc987.vhd
| 4 | 46,990 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc987.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s03b00x00p06n01i00987pkg is
------------------------------------USING ONLY WHITE MATTER---------------------------------
--------------------------------------------------------------------------------------------
---ACCESS TYPE FROM STANDARD PACKAGE
type boolean_ptr is access boolean ; --simple boolean type
type bit_ptr is access bit ; --simple bit type
type char_ptr is access character; --simple character type
type severity_level_ptr is access severity_level; --simple severity type
type integer_ptr is access integer; --simple integer type
type real_ptr is access real; --simple real type
type time_ptr is access time; --simple time type
type natural_ptr is access natural; --simple natural type
type positive_ptr is access positive; --simple positive type
type string_ptr is access string; --simple string type
type bit_vector_ptr is access bit_vector; --simple bit_vector type
--------------------------------------------------------------------------------------------
--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
---------------------------------------------------------------------------------------------
--CONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
subtype boolean_vector_st is boolean_vector(0 to 15);
subtype severity_level_vector_st is severity_level_vector(0 to 15);
subtype integer_vector_st is integer_vector(0 to 15);
subtype real_vector_st is real_vector(0 to 15);
subtype time_vector_st is time_vector(0 to 15);
subtype natural_vector_st is natural_vector(0 to 15);
subtype positive_vector_st is positive_vector(0 to 15);
---------------------------------------------------------------------------------------------
--CONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type boolean_cons_vector is array (15 downto 0) of boolean;
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type integer_cons_vector is array (15 downto 0) of integer;
type real_cons_vector is array (15 downto 0) of real;
type time_cons_vector is array (15 downto 0) of time;
type natural_cons_vector is array (15 downto 0) of natural;
type positive_cons_vector is array (15 downto 0) of positive;
---------------------------------------------------------------------------------------------
--CONSTRAINED ARRAY OF ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type boolean_cons_vectorofvector is array (0 to 15) of boolean_cons_vector;
type severity_level_cons_vectorofvector is array (0 to 15) of severity_level_cons_vector;
type integer_cons_vectorofvector is array (0 to 15) of integer_cons_vector ;
type real_cons_vectorofvector is array (0 to 15) of real_cons_vector;
type time_cons_vectorofvector is array (0 to 15) of time_cons_vector;
type natural_cons_vectorofvector is array (0 to 15) of natural_cons_vector;
type positive_cons_vectorofvector is array (0 to 15) of positive_cons_vector;
---------------------------------------------------------------------------------------------
--UNCONSTRAINED 2-DIMENSIONAL ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type s2boolean_vector is array (natural range <>,natural range <>) of boolean;
type s2bit_vector is array (natural range<>,natural range <>) of bit;
type s2char_vector is array (natural range<>,natural range <>) of character;
type s2severity_level_vector is array (natural range <>,natural range <>) of severity_level;
type s2integer_vector is array (natural range <>,natural range <>) of integer;
type s2real_vector is array (natural range <>,natural range <>) of real;
type s2time_vector is array (natural range <>,natural range <>) of time;
type s2natural_vector is array (natural range <>,natural range <>) of natural;
type s2positive_vector is array (natural range <>,natural range <>) of positive;
----------------------------------------------------------------------------------------------
--CONSTRAINED 2-DIMENSIONAL ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type column is range 1 to 64;
type row is range 1 to 1024;
type s2boolean_cons_vector is array (row,column) of boolean;
type s2bit_cons_vector is array (row,column) of bit;
type s2char_cons_vector is array (row,column) of character;
type s2severity_level_cons_vector is array (row,column) of severity_level;
type s2integer_cons_vector is array (row,column) of integer;
type s2real_cons_vector is array (row,column) of real;
type s2time_cons_vector is array (row,column) of time;
type s2natural_cons_vector is array (row,column) of natural;
type s2positive_cons_vector is array (row,column) of positive;
-----------------------------------------------------------------------------------------------
--RECORD WITH FIELDS FROM STANDARD PACKAGE
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
-----------------------------------------------------------------------------------------------
--RECORD WITH FIELDS AS UNCONSTRAINT ARRAYS
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
-----------------------------------------------------------------------------------------------
--RECORD WITH FIELDS AS CONSTRAINT ARRAYS
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
-----------------------------------------------------------------------------------------------
--RECORD WITH FIELDS AS 2-DIMENSIONAL CONSTRAINED ARRAYS
type record_2cons_array is record
a:s2boolean_cons_vector;
b:s2bit_cons_vector;
c:s2char_cons_vector;
d:s2severity_level_cons_vector;
e:s2integer_cons_vector;
f:s2real_cons_vector;
g:s2time_cons_vector;
h:s2natural_cons_vector;
i:s2positive_cons_vector;
end record;
-----------------------------------------------------------------------------------------------
--RECORD WITH FIELDS AS 2-DIMENSIONAL CONSTRAINED ARRAYS OF ARRAY
type record_cons_arrayofarray is record
a:boolean_cons_vectorofvector;
b:severity_level_cons_vectorofvector;
c:integer_cons_vectorofvector;
d:real_cons_vectorofvector;
e:time_cons_vectorofvector;
f:natural_cons_vectorofvector;
g:positive_cons_vectorofvector;
end record;
-----------------------------------------------------------------------------------------------
type record_of_ptr is record
a:boolean_ptr ; --simple boolean type
b:bit_ptr; --simple bit type
c:char_ptr; --simple character type
e:severity_level_ptr; --simple severity type
f:integer_ptr; --simple integer type
g: real_ptr ; --simple real type
h:time_ptr; --simple time type
i: natural_ptr; --simple natural type
j:positive_ptr; --simple positive type
k: string_ptr; --simple string type
l: bit_vector_ptr; --simple bit_vector type
end record;
-----------------------------------------------------------------------------------------------
type record_of_records is record
a: record_std_package;
c: record_cons_array;
e: record_2cons_array;
g: record_cons_arrayofarray;
h: record_of_ptr;
i: record_array_st;
end record;
-----------------------------------------------------------------------------------------------
--ACCESS TYPES FOR ABOVE
-----------------------------------------------------------------------------------------------
type boolean_vector_ptr is access boolean_vector;
type severity_level_vector_ptr is access severity_level_vector;
type integer_vector_ptr is access integer_vector;
type real_vector_ptr is access real_vector;
type time_vector_ptr is access time_vector;
type natural_vector_ptr is access natural_vector;
type positive_vector_ptr is access positive_vector;
-----------------------------------------------------------------------------------------------
type boolean_vector_st_ptr is access boolean_vector_st;--(0 to 15);
type severity_level_vector_st_ptr is access severity_level_vector_st;--(0 to 15);
type integer_vector_st_ptr is access integer_vector_st;--(0 to 15);
type real_vector_st_ptr is access real_vector_st;--(0 to 15);
type time_vector_st_ptr is access time_vector_st;--(0 to 15);
type natural_vector_st_ptr is access natural_vector_st;--(0 to 15);
type positive_vector_st_ptr is access positive_vector_st;--(0 to 15);
-----------------------------------------------------------------------------------------------
type boolean_cons_vector_ptr is access boolean_cons_vector;
type severity_level_cons_vector_ptr is access severity_level_cons_vector;
type integer_cons_vector_ptr is access integer_cons_vector;
type real_cons_vector_ptr is access real_cons_vector;
type time_cons_vector_ptr is access time_cons_vector;
type natural_cons_vector_ptr is access natural_cons_vector;
type positive_cons_vector_ptr is access positive_cons_vector;
-----------------------------------------------------------------------------------------------
type boolean_cons_vectorofvector_ptr is access boolean_cons_vectorofvector;
type sev_lvl_cons_vecofvec_ptr is access severity_level_cons_vectorofvector;
type integer_cons_vectorofvector_ptr is access integer_cons_vectorofvector;
type real_cons_vectorofvector_ptr is access real_cons_vectorofvector;
type time_cons_vectorofvector_ptr is access time_cons_vectorofvector;
type natural_cons_vectorofvector_ptr is access natural_cons_vectorofvector;
type posi_cons_vecofvec_ptr is access positive_cons_vectorofvector;
-----------------------------------------------------------------------------------------------
type s2boolean_vector_ptr is access s2boolean_vector;
type s2bit_vector_ptr is access s2bit_vector;
type s2char_vector_ptr is access s2char_vector;
type s2severity_level_vector_ptr is access s2severity_level_vector;
type s2integer_vector_ptr is access s2integer_vector;
type s2real_vector_ptr is access s2real_vector;
type s2time_vector_ptr is access s2time_vector;
type s2positive_vector_ptr is access s2positive_vector;
-----------------------------------------------------------------------------------------------
type s2boolean_cons_vector_ptr is access s2boolean_cons_vector;
type s2bit_cons_vector_ptr is access s2bit_cons_vector;
type s2char_cons_vector_ptr is access s2char_cons_vector;
type s2sev_lvl_cons_vec_ptr is access s2severity_level_cons_vector;
type s2integer_cons_vector_ptr is access s2integer_cons_vector;
type s2real_cons_vector_ptr is access s2real_cons_vector;
type s2time_cons_vector_ptr is access s2time_cons_vector;
type s2natural_cons_vector_ptr is access s2natural_cons_vector;
type s2positive_cons_vector_ptr is access s2positive_cons_vector;
----------------------------------------------------------------------------------------------
type record_std_package_ptr is access record_std_package;
type record_cons_array_ptr is access record_cons_array;
type record_2cons_array_ptr is access record_2cons_array;
type record_cons_arrayofarray_ptr is access record_cons_arrayofarray;
type record_of_ptr_ptr is access record_of_ptr;
type record_of_records_ptr is access record_of_records;
type record_array_st_ptr is access record_array_st;
-----------------------------------------------------------------------------------------------
-------------------------USING PARTIAL GRAY & PARTIAL WHITE MATTER-----------------------------
type four_value is ('Z','0','1','X'); --enumerated type
type four_value_map is array(four_value) of boolean;
subtype binary is four_value range '0' to '1';
type four_value_vector is array (natural range <>) of four_value; --unconstraint array of
type byte is array(0 to 7) of bit;
subtype word is bit_vector(0 to 15); --constrained array
function resolution(i:in four_value_vector) return four_value; --bus resolution
subtype four_value_state is resolution four_value; --function type
type state_vector is array (natural range <>) of four_value_state; --unconstraint array of
constant size :integer := 63;
type primary_memory is array(0 to size) of word; --array of an array
type primary_memory_module is --record with field
record --as an array
enable:binary;
memory_number:primary_memory;
end record;
type whole_memory is array(0 to size) of primary_memory_module; --array of a complex record
type current is range -2147483647 to +2147483647
units
nA;
uA = 1000 nA;
mA = 1000 uA;
A = 1000 mA;
end units;
type resistance is range -2147483647 to +2147483647
units
uOhm;
mOhm = 1000 uOhm;
Ohm = 1000 mOhm;
KOhm = 1000 Ohm;
end units;
subtype delay is integer range 1 to 10;
type four_value_ptr is access four_value;
type four_value_map_ptr is access four_value_map;
type binary_ptr is access binary;
type four_value_vector_ptr is access four_value_vector; --ennumerated type
type byte_ptr is access byte;
type word_ptr is access word;
type four_value_state_ptr is access four_value_state;
type state_vector_ptr is access state_vector; --type returned by resolu.
type primary_memory_ptr is access primary_memory;
type primary_memory_module_ptr is access primary_memory_module;
type whole_memory_ptr is access whole_memory;
type current_ptr is access current;
type resistance_ptr is access resistance;
type delay_ptr is access delay;
-------------------------------------------------------------------------------------------
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C10 : string := "shishir";
constant C11 : bit_vector := B"0011";
constant C12 : boolean_vector := (true,false);
constant C13 : severity_level_vector := (note,error);
constant C14 : integer_vector := (1,2,3,4);
constant C15 : real_vector := (1.0,2.0,3.0,4.0);
constant C16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
constant C17 : natural_vector := (1,2,3,4);
constant C18 : positive_vector := (1,2,3,4);
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st:= (others => C4);
constant C72 : integer_vector_st:=(others => C5);
constant C73 : real_vector_st:=(others => C6);
constant C74 : time_vector_st:=(others => C7);
constant C75 : natural_vector_st:=(others => C8);
constant C76 : positive_vector_st:=(others => C9);
constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
constant C27 : severity_level_cons_vectorofvector := (others => (others => C4));
constant C28 : integer_cons_vectorofvector := (others => (others => C5));
constant C29 : real_cons_vectorofvector := (others => (others => C6));
constant C30 : time_cons_vectorofvector := (others => (others => C7));
constant C31 : natural_cons_vectorofvector := (others => (others => C8));
constant C32 : positive_cons_vectorofvector := (others => (others => C9));
--constant C33 : s2boolean_vector := ((true,true),(false,false));
--constant C34 : s2bit_vector := ((B"0011"),(B"1100"));
--constant C35 : s2char_vector := (('s','h'),('i','s'));
--constant C36 : s2severity_level_vector := ((note,error),(error,note));
--constant C37 : s2integer_vector := ((1,2,3,4),(4,3,2,1));
--constant C38 : s2real_vector := ((1.0,2.0,3.0,4.0),(4.0,3.0,2.0,1.0));
--constant C39 : s2time_vector := ((1 ns, 2 ns, 3 ns, 4 ns),(1 ns, 2 ns, 3 ns, 4 ns));
--constant C40 : s2positive_vector := ((1,2,3,4),(4,3,2,1));
constant C41 : s2boolean_cons_vector := (others =>(others => C1));
constant C42 : s2bit_cons_vector := (others => (others => C2));
constant C43 : s2char_cons_vector := (others =>(others => C3));
constant C44 : s2severity_level_cons_vector := (others => (others => C4));
constant C45 : s2integer_cons_vector := (others => (others => C5));
constant C46 : s2real_cons_vector := (others =>(others => C6));
constant C47 : s2time_cons_vector := (others =>(others => C7));
constant C48 : s2natural_cons_vector := (others =>(others => C8));
constant C49 : s2positive_cons_vector := (others => (others => C9));
constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C52 : record_2cons_array := (C41,C42,C43,C44,C45,C46,C47,C48,C49);
constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
--constant C54 : record_of_ptr := (NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL);
--constant C54a : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
--constant C55 : record_of_records := (C50,C51,C52,C53,C54,C54a);
constant C56 : four_value := 'Z';
constant C57 : four_value_map := (true,true,true,true);
constant C58 : binary := '0';
constant C59 : four_value_vector := ('1','0','1','0');
constant C60 : byte := (others => '0');
constant C61 : word := (others =>'0' );
constant C62 : four_value_state := 'Z';
constant C63 : state_vector := ('Z','Z','Z','Z');
constant C64 : primary_memory := (others => C61);
constant C65 : primary_memory_module := ('1',C64);
constant C66 : whole_memory := (others => C65);
constant C67 : current := 1 A;
constant C68 : resistance := 1 Ohm;
constant C69 : delay := 2;
end c06s03b00x00p06n01i00987pkg;
package body c06s03b00x00p06n01i00987pkg is
function resolution(i:in four_value_vector) return four_value is
variable temp :four_value := 'Z';
begin
return temp;
end;
end c06s03b00x00p06n01i00987pkg;
use work.c06s03b00x00p06n01i00987pkg.all;
ENTITY c06s03b00x00p06n01i00987ent IS
END c06s03b00x00p06n01i00987ent;
ARCHITECTURE c06s03b00x00p06n01i00987arch OF c06s03b00x00p06n01i00987ent IS
BEGIN
TESTING: PROCESS
variable var1 : boolean_ptr ;
variable var2 : bit_ptr ;
variable var3 : char_ptr ;
variable var4 : severity_level_ptr ;
variable var5 : integer_ptr ;
variable var6 : real_ptr ;
variable var7 : time_ptr ;
variable var8 : natural_ptr ;
variable var9 : positive_ptr ;
variable var10 : string_ptr ;
variable var11 : bit_vector_ptr ;
variable var12 : boolean_vector_ptr ;
variable var13 : severity_level_vector_ptr ;
variable var14 : integer_vector_ptr ;
variable var15 : real_vector_ptr ;
variable var16 : time_vector_ptr ;
variable var17 : natural_vector_ptr ;
variable var18 : positive_vector_ptr ;
variable var19 : boolean_cons_vector_ptr ;
variable var20 : severity_level_cons_vector_ptr ;
variable var21 : integer_cons_vector_ptr ;
variable var22 : real_cons_vector_ptr ;
variable var23 : time_cons_vector_ptr ;
variable var24 : natural_cons_vector_ptr ;
variable var25 : positive_cons_vector_ptr ;
variable var26 : boolean_cons_vectorofvector_ptr ;
variable var27 : sev_lvl_cons_vecofvec_ptr ;
variable var28 : integer_cons_vectorofvector_ptr ;
variable var29 : real_cons_vectorofvector_ptr ;
variable var30 : time_cons_vectorofvector_ptr ;
variable var31 : natural_cons_vectorofvector_ptr ;
variable var32 : posi_cons_vecofvec_ptr ;
-- variable var33 : s2boolean_vector_ptr ;
-- variable var34 : s2bit_vector_ptr ;
-- variable var35 : s2char_vector_ptr ;
-- variable var36 : s2severity_level_vector_ptr ;
-- variable var37 : s2integer_vector_ptr ;
-- variable var38 : s2real_vector_ptr ;
-- variable var39 : s2time_vector_ptr ;
-- variable var40 : s2positive_vector_ptr ;
variable var41 : s2boolean_cons_vector_ptr ;
variable var42 : s2bit_cons_vector_ptr ;
variable var43 : s2char_cons_vector_ptr ;
variable var44 : s2sev_lvl_cons_vec_ptr ;
variable var45 : s2integer_cons_vector_ptr ;
variable var46 : s2real_cons_vector_ptr ;
variable var47 : s2time_cons_vector_ptr ;
variable var48 : s2natural_cons_vector_ptr ;
variable var49 : s2positive_cons_vector_ptr ;
variable var50 : record_std_package_ptr ;
variable var51 : record_cons_array_ptr ;
variable var52 : record_2cons_array_ptr ;
variable var53 : record_cons_arrayofarray_ptr ;
variable var54 : record_of_ptr_ptr ;
variable var54a : record_array_st_ptr;
variable var55 : record_of_records_ptr ;
variable var56 : four_value_ptr ;
variable var57 : four_value_map_ptr ;
variable var58 : binary_ptr ;
variable var59 : four_value_vector_ptr ;
variable var60 : byte_ptr ;
variable var61 : word_ptr ;
variable var62 : four_value_state_ptr ;
variable var63 : state_vector_ptr ;
variable var64 : primary_memory_ptr ;
variable var65 : primary_memory_module_ptr;
variable var66 : whole_memory_ptr ;
variable var67 : current_ptr ;
variable var68 : resistance_ptr ;
variable var69 : delay_ptr ;
variable var70 : boolean_vector_st_ptr;
variable var71 : severity_level_vector_st_ptr;
variable var72 : integer_vector_st_ptr;
variable var73 : real_vector_st_ptr;
variable var74 : time_vector_st_ptr;
variable var75 : natural_vector_st_ptr;
variable var76 : positive_vector_st_ptr;
variable vari1 : boolean;
variable vari2 : bit;
variable vari3 : character;
variable vari4 : severity_level;
variable vari5 : integer;
variable vari6 : real;
variable vari7 : time;
variable vari8 : natural;
variable vari9 : positive;
variable vari10 : string(1 to 7);
variable vari11 : bit_vector(0 to 3);
variable vari12 : boolean_vector(0 to 1);
variable vari13 : severity_level_vector(0 to 1);
variable vari14 : integer_vector(0 to 3);
variable vari15 : real_vector(0 to 3);
variable vari16 : time_vector(0 to 3);
variable vari17 : natural_vector(0 to 3);
variable vari18 : positive_vector(0 to 3);
variable vari19 : boolean_cons_vector;
variable vari20 : severity_level_cons_vector;
variable vari21 : integer_cons_vector;
variable vari22 : real_cons_vector;
variable vari23 : time_cons_vector;
variable vari24 : natural_cons_vector;
variable vari25 : positive_cons_vector;
variable vari26 : boolean_cons_vectorofvector;
variable vari27 : severity_level_cons_vectorofvector;
variable vari28 : integer_cons_vectorofvector;
variable vari29 : real_cons_vectorofvector;
variable vari30 : time_cons_vectorofvector;
variable vari31 : natural_cons_vectorofvector;
variable vari32 : positive_cons_vectorofvector;
--variable vari33 : s2boolean_vector;
--variable vari34 : s2bit_vector;
--variable vari35 : s2char_vector;
--variable vari36 : s2severity_level_vector;
--variable vari37 : s2integer_vector;
--variable vari38 : s2real_vector;
--variable vari39 : s2time_vector;
--variable vari40 : s2positive_vector;
variable vari41 : s2boolean_cons_vector;
variable vari42 : s2bit_cons_vector;
variable vari43 : s2char_cons_vector;
variable vari44 : s2severity_level_cons_vector;
variable vari45 : s2integer_cons_vector;
variable vari46 : s2real_cons_vector;
variable vari47 : s2time_cons_vector;
variable vari48 : s2natural_cons_vector;
variable vari49 : s2positive_cons_vector;
variable vari50 : record_std_package;
variable vari51 : record_cons_array;
variable vari52 : record_2cons_array;
variable vari53 : record_cons_arrayofarray;
variable vari54 : record_of_ptr;
variable vari55 : record_of_records;
variable vari56 : four_value;
variable vari57 : four_value_map;
variable vari58 : binary;
variable vari59 : four_value_vector(0 to 3);
variable vari60 : byte;
variable vari61 : word;
variable vari62 : four_value_state;
variable vari63 : state_vector(0 to 3);
variable vari64 : primary_memory;
variable vari65 : primary_memory_module;
variable vari66 : whole_memory;
variable vari67 : current;
variable vari68 : resistance;
variable vari69 : delay;
variable vari70 : boolean_vector_st;
variable vari71 : severity_level_vector_st;
variable vari72 : integer_vector_st;
variable vari73 : real_vector_st;
variable vari74 : time_vector_st;
variable vari75 : natural_vector_st;
variable vari76 : positive_vector_st;
variable vari54a : record_array_st;
BEGIN
var1 := NEW boolean '(C1);
var2 := NEW bit '(C2);
var3 := NEW character '(C3);
var4 := NEW severity_level '(C4);
var5 := NEW integer '(C5);
var6 := NEW real '(C6);
var7 := NEW time '(C7);
var8 := NEW natural '(C8);
var9 := NEW positive '(C9);
var10 := NEW string '(C10);
var11 := NEW bit_vector '(C11);
var12 := NEW boolean_vector '(C12);
var13 := NEW severity_level_vector '(C13);
var14 := NEW integer_vector '(C14);
var15 := NEW real_vector '(C15);
var16 := NEW time_vector '(C16);
var17 := NEW natural_vector '(C17);
var18 := NEW positive_vector '(C18);
var19 := NEW boolean_cons_vector '(C19);
var20 := NEW severity_level_cons_vector '(C20);
var21 := NEW integer_cons_vector '(C21);
var22 := NEW real_cons_vector '(C22);
var23 := NEW time_cons_vector '(C23);
var24 := NEW natural_cons_vector '(C24);
var25 := NEW positive_cons_vector '(C25);
var26 := NEW boolean_cons_vectorofvector '(C26);
var27 := NEW severity_level_cons_vectorofvector '(C27);
var28 := NEW integer_cons_vectorofvector '(C28);
var29 := NEW real_cons_vectorofvector '(C29);
var30 := NEW time_cons_vectorofvector '(C30);
var31 := NEW natural_cons_vectorofvector '(C31);
var32 := NEW positive_cons_vectorofvector '(C32);
--var33 := NEW s2boolean_vector '(C33);
--var34 := NEW s2bit_vector '(C34);
--var35 := NEW s2char_vector '(C35);
--var36 := NEW s2severity_level_vector '(C36);
--var37 := NEW s2integer_vector '(C37);
--var38 := NEW s2real_vector '(C38);
--var39 := NEW s2time_vector '(C39);
--var40 := NEW s2positive_vector '(C40);
var41 := NEW s2boolean_cons_vector '(C41);
var42 := NEW s2bit_cons_vector '(C42);
var43 := NEW s2char_cons_vector '(C43);
var44 := NEW s2severity_level_cons_vector '(C44);
var45 := NEW s2integer_cons_vector '(C45);
var46 := NEW s2real_cons_vector '(C46);
var47 := NEW s2time_cons_vector '(C47);
var48 := NEW s2natural_cons_vector '(C48);
var49 := NEW s2positive_cons_vector '(C49);
var50 := NEW record_std_package '(C50);
var51 := NEW record_cons_array '(C51);
var52 := NEW record_2cons_array '(C52);
var53 := NEW record_cons_arrayofarray '(C53);
--var54 := NEW record_of_ptr '(C54);
--var54a := NEW record_array_st '(C54a);
--var55 := NEW record_of_records '(C55);
var56 := NEW four_value '(C56);
var57 := NEW four_value_map '(C57);
var58 := NEW binary '(C58);
var59 := NEW four_value_vector '(C59);
var60 := NEW byte '(C60);
var61 := NEW word '(C61);
var62 := NEW four_value_state '(C62);
var63 := NEW state_vector '(C63);
var64 := NEW primary_memory '(C64);
var65 := NEW primary_memory_module '(C65);
var66 := NEW whole_memory '(C66);
var67 := NEW current '(C67);
var68 := NEW resistance '(C68);
var69 := NEW delay '(C69);
var70 := NEW boolean_vector_st '(C70);
var71 := NEW severity_level_vector_st '(C71);
var72 := NEW integer_vector_st '(C72);
var73 := NEW real_vector_st '(C73);
var74 := NEW time_vector_st '(C74);
var75 := NEW natural_vector_st '(C75);
var76 := NEW positive_vector_st '(C76);
vari1 := var1.all;
vari2 := var2.all;
vari3 := var3.all;
vari4 := var4.all;
vari5 := var5.all;
vari6 := var6.all;
vari7 := var7.all;
vari8 := var8.all;
vari9 := var9.all;
vari10 := var10.all;
vari11 := var11.all;
vari12 := var12.all;
vari13 := var13.all;
vari14 := var14.all;
vari15 := var15.all;
vari16 := var16.all;
vari17 := var17.all;
vari18 := var18.all;
vari19 := var19.all;
vari20 := var20.all;
vari21 := var21.all;
vari22 := var22.all;
vari23 := var23.all;
vari24 := var24.all;
vari25 := var25.all;
vari26 := var26.all;
vari27 := var27.all;
vari28 := var28.all;
vari29 := var29.all;
vari30 := var30.all;
vari31 := var31.all;
vari32 := var32.all;
--vari33 := var33.all;
--vari34 := var34.all;
--vari35 := var35.all;
--vari36 := var36.all;
--vari37 := var37.all;
--vari38 := var38.all;
--vari39 := var39.all;
--vari40 := var40.all;
vari41 := var41.all;
vari42 := var42.all;
vari43 := var43.all;
vari44 := var44.all;
vari45 := var45.all;
vari46 := var46.all;
vari47 := var47.all;
vari48 := var48.all;
vari49 := var49.all;
vari50 := var50.all;
vari51 := var51.all;
vari52 := var52.all;
vari53 := var53.all;
--vari54 := var54.all;
--vari55 := var55.all;
vari56 := var56.all;
vari57 := var57.all;
vari58 := var58.all;
vari59 := var59.all;
vari60 := var60.all;
vari61 := var61.all;
vari62 := var62.all;
vari63 := var63.all;
vari64 := var64.all;
vari65 := var65.all;
vari66 := var66.all;
vari67 := var67.all;
vari68 := var68.all;
vari69 := var69.all;
vari70 := var70.all;
vari71 := var71.all;
vari72 := var72.all;
vari73 := var73.all;
vari74 := var74.all;
vari75 := var75.all;
vari76 := var76.all;
--vari54a := var54a.all;
ASSERT vari1= C1 report "Improper Assignment of vari1" SEVERITY FAILURE;
ASSERT vari2 = C2 report "Improper Assignment of vari2" SEVERITY FAILURE;
ASSERT vari3 = C3 report "Improper Assignment of vari3" SEVERITY FAILURE;
ASSERT vari4 = C4 report "Improper Assignment of vari4" SEVERITY FAILURE;
ASSERT vari5 = C5 report "Improper Assignment of vari5" SEVERITY FAILURE;
ASSERT vari6 = C6 report "Improper Assignment of vari6" SEVERITY FAILURE;
ASSERT vari7 = C7 report "Improper Assignment of vari7" SEVERITY FAILURE;
ASSERT vari8 = C8 report "Improper Assignment of vari8" SEVERITY FAILURE;
ASSERT vari9 = C9 report "Improper Assignment of vari9" SEVERITY FAILURE;
ASSERT vari10 = C10 report "Improper Assignment of vari10" SEVERITY FAILURE;
ASSERT vari11 = C11 report "Improper Assignment of vari11" SEVERITY FAILURE;
ASSERT vari12 = C12 report "Improper Assignment of vari12" SEVERITY FAILURE;
ASSERT vari13 = C13 report "Improper Assignment of vari13" SEVERITY FAILURE;
ASSERT vari14 = C14 report "Improper Assignment of vari14" SEVERITY FAILURE;
ASSERT vari15 = C15 report "Improper Assignment of vari15" SEVERITY FAILURE;
ASSERT vari16 = C16 report "Improper Assignment of vari16" SEVERITY FAILURE;
ASSERT vari17 = C17 report "Improper Assignment of vari17" SEVERITY FAILURE;
ASSERT vari18 = C18 report "Improper Assignment of vari18" SEVERITY FAILURE;
ASSERT vari19 = C19 report "Improper Assignment of vari19" SEVERITY FAILURE;
ASSERT vari20 = C20 report "Improper Assignment of vari20" SEVERITY FAILURE;
ASSERT vari21 = C21 report "Improper Assignment of vari21" SEVERITY FAILURE;
ASSERT vari22 = C22 report "Improper Assignment of vari22" SEVERITY FAILURE;
ASSERT vari23 = C23 report "Improper Assignment of vari23" SEVERITY FAILURE;
ASSERT vari24 = C24 report "Improper Assignment of vari24" SEVERITY FAILURE;
ASSERT vari25 = C25 report "Improper Assignment of vari25" SEVERITY FAILURE;
ASSERT vari26 = C26 report "Improper Assignment of vari26" SEVERITY FAILURE;
ASSERT vari27 = C27 report "Improper Assignment of vari27" SEVERITY FAILURE;
ASSERT vari28 = C28 report "Improper Assignment of vari28" SEVERITY FAILURE;
ASSERT vari29 = C29 report "Improper Assignment of vari29" SEVERITY FAILURE;
ASSERT vari30 = C30 report "Improper Assignment of vari30" SEVERITY FAILURE;
ASSERT vari31 = C31 report "Improper Assignment of vari31" SEVERITY FAILURE;
ASSERT vari32 = C32 report "Improper Assignment of vari32" SEVERITY FAILURE;
--ASSERT vari33 = C33 report "Improper Assignment of vari33" SEVERITY FAILURE;
--ASSERT vari34 = C34 report "Improper Assignment of vari34" SEVERITY FAILURE;
--ASSERT vari35 = C35 report "Improper Assignment of vari35" SEVERITY FAILURE;
--ASSERT vari36 = C36 report "Improper Assignment of vari36" SEVERITY FAILURE;
--ASSERT vari37 = C37 report "Improper Assignment of vari37" SEVERITY FAILURE;
--ASSERT vari38 = C38 report "Improper Assignment of vari38" SEVERITY FAILURE;
--ASSERT vari39 = C39 report "Improper Assignment of vari39" SEVERITY FAILURE;
--ASSERT vari40 = C40 report "Improper Assignment of vari40" SEVERITY FAILURE;
ASSERT vari41 = C41 report "Improper Assignment of vari41" SEVERITY FAILURE;
ASSERT vari42 = C42 report "Improper Assignment of vari42" SEVERITY FAILURE;
ASSERT vari43 = C43 report "Improper Assignment of vari43" SEVERITY FAILURE;
ASSERT vari44 = C44 report "Improper Assignment of vari44" SEVERITY FAILURE;
ASSERT vari45 = C45 report "Improper Assignment of vari45" SEVERITY FAILURE;
ASSERT vari46 = C46 report "Improper Assignment of vari46" SEVERITY FAILURE;
ASSERT vari47 = C47 report "Improper Assignment of vari47" SEVERITY FAILURE;
ASSERT vari48 = C48 report "Improper Assignment of vari48" SEVERITY FAILURE;
ASSERT vari49 = C49 report "Improper Assignment of vari49" SEVERITY FAILURE;
ASSERT vari50 = C50 report "Improper Assignment of vari50" SEVERITY FAILURE;
ASSERT vari51 = C51 report "Improper Assignment of vari51" SEVERITY FAILURE;
ASSERT vari52 = C52 report "Improper Assignment of vari52" SEVERITY FAILURE;
ASSERT vari53 = C53 report "Improper Assignment of vari53" SEVERITY FAILURE;
--ASSERT vari54 = C54 report "Improper Assignment of vari54" SEVERITY FAILURE;
--ASSERT vari54a = C54a report "Improper Assignment of vari54a" SEVERITY FAILURE;
--ASSERT vari55 = C55 report "Improper Assignment of vari55" SEVERITY FAILURE;
ASSERT vari56 = C56 report "Improper Assignment of vari56" SEVERITY FAILURE;
ASSERT vari57 = C57 report "Improper Assignment of vari57" SEVERITY FAILURE;
ASSERT vari58 = C58 report "Improper Assignment of vari58" SEVERITY FAILURE;
ASSERT vari59 = C59 report "Improper Assignment of vari59" SEVERITY FAILURE;
ASSERT vari60 = C60 report "Improper Assignment of vari60" SEVERITY FAILURE;
ASSERT vari61 = C61 report "Improper Assignment of vari61" SEVERITY FAILURE;
ASSERT vari62 = C62 report "Improper Assignment of vari62" SEVERITY FAILURE;
ASSERT vari63 = C63 report "Improper Assignment of vari63" SEVERITY FAILURE;
ASSERT vari64 = C64 report "Improper Assignment of vari64" SEVERITY FAILURE;
ASSERT vari65 = C65 report "Improper Assignment of vari65" SEVERITY FAILURE;
ASSERT vari66 = C66 report "Improper Assignment of vari66" SEVERITY FAILURE;
ASSERT vari67 = C67 report "Improper Assignment of vari67" SEVERITY FAILURE;
ASSERT vari68 = C68 report "Improper Assignment of vari68" SEVERITY FAILURE;
ASSERT vari69 = C69 report "Improper Assignment of vari69" SEVERITY FAILURE;
ASSERT vari70 = C70 report "Improper Assignment of vari70" SEVERITY FAILURE;
ASSERT vari71 = C71 report "Improper Assignment of vari71" SEVERITY FAILURE;
ASSERT vari72 = C72 report "Improper Assignment of vari72" SEVERITY FAILURE;
ASSERT vari73 = C73 report "Improper Assignment of vari73" SEVERITY FAILURE;
ASSERT vari74 = C74 report "Improper Assignment of vari74" SEVERITY FAILURE;
ASSERT vari74 = C74 report "Improper Assignment of vari74" SEVERITY FAILURE;
ASSERT vari75 = C75 report "Improper Assignment of vari75" SEVERITY FAILURE;
ASSERT vari76 = C76 report "Improper Assignment of vari76" SEVERITY FAILURE;
assert NOT( vari1 = C1 and
vari2 = C2 and
vari3 = C3 and
vari4 = C4 and
vari5 = C5 and
vari6 = C6 and
vari7 = C7 and
vari8 = C8 and
vari9 = C9 and
vari10 = C10 and
vari11 = C11 and
vari12 = C12 and
vari13 = C13 and
vari14 = C14 and
vari15 = C15 and
vari16 = C16 and
vari17 = C17 and
vari18 = C18 and
vari19 = C19 and
vari20 = C20 and
vari21 = C21 and
vari22 = C22 and
vari23 = C23 and
vari24 = C24 and
vari25 = C25 and
vari26 = C26 and
vari27 = C27 and
vari28 = C28 and
vari29 = C29 and
vari30 = C30 and
vari31 = C31 and
vari32 = C32 and
-- vari33 = C33 and
-- vari34 = C34 and
-- vari35 = C35 and
-- vari36 = C36 and
-- vari37 = C37 and
-- vari38 = C38 and
-- vari39 = C39 and
-- vari40 = C40 and
vari41 = C41 and
vari42 = C42 and
vari43 = C43 and
vari44 = C44 and
vari45 = C45 and
vari46 = C46 and
vari47 = C47 and
vari48 = C48 and
vari49 = C49 and
vari50 = C50 and
vari51 = C51 and
vari52 = C52 and
vari53 = C53 and
-- vari54 = C54 and
-- vari54a = C54a and
-- vari55 = C55 and
vari56 = C56 and
vari57 = C57 and
vari58 = C58 and
vari59 = C59 and
vari60 = C60 and
vari61 = C61 and
vari62 = C62 and
vari63 = C63 and
vari64 = C64 and
vari65 = C65 and
vari66 = C66 and
vari67 = C67 and
vari68 = C68 and
vari69 = C69 and
vari70 = C70 and
vari71 = C71 and
vari72 = C72 and
vari73 = C73 and
vari74 = C74 and
vari75 = C75 and
vari76 = C76 )
report "***PASSED TEST: c06s03b00x00p06n01i00987"
severity NOTE;
assert ( vari1 = C1 and
vari2 = C2 and
vari3 = C3 and
vari4 = C4 and
vari5 = C5 and
vari6 = C6 and
vari7 = C7 and
vari8 = C8 and
vari9 = C9 and
vari10 = C10 and
vari11 = C11 and
vari12 = C12 and
vari13 = C13 and
vari14 = C14 and
vari15 = C15 and
vari16 = C16 and
vari17 = C17 and
vari18 = C18 and
vari19 = C19 and
vari20 = C20 and
vari21 = C21 and
vari22 = C22 and
vari23 = C23 and
vari24 = C24 and
vari25 = C25 and
vari26 = C26 and
vari27 = C27 and
vari28 = C28 and
vari29 = C29 and
vari30 = C30 and
vari31 = C31 and
vari32 = C32 and
-- vari33 = C33 and
-- vari34 = C34 and
-- vari35 = C35 and
-- vari36 = C36 and
-- vari37 = C37 and
-- vari38 = C38 and
-- vari39 = C39 and
-- vari40 = C40 and
vari41 = C41 and
vari42 = C42 and
vari43 = C43 and
vari44 = C44 and
vari45 = C45 and
vari46 = C46 and
vari47 = C47 and
vari48 = C48 and
vari49 = C49 and
vari50 = C50 and
vari51 = C51 and
vari52 = C52 and
vari53 = C53 and
-- vari54 = C54 and
-- vari54a = C54a and
-- vari55 = C55 and
vari56 = C56 and
vari57 = C57 and
vari58 = C58 and
vari59 = C59 and
vari60 = C60 and
vari61 = C61 and
vari62 = C62 and
vari63 = C63 and
vari64 = C64 and
vari65 = C65 and
vari66 = C66 and
vari67 = C67 and
vari68 = C68 and
vari69 = C69 and
vari70 = C70 and
vari71 = C71 and
vari72 = C72 and
vari73 = C73 and
vari74 = C74 and
vari75 = C75 and
vari76 = C76 )
report "***FAILED TEST: c06s03b00x00p06n01i00987 - Prefix of a selected name used to denote an object designated by an access value should be an access type."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p06n01i00987arch;
|
gpl-2.0
|
f168bf91b50c898a354df5effe92db1d
| 0.575803 | 3.967075 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/perf02/shr_141.vhd
| 3 | 1,108 |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity shr_141 is
port (
output : out std_logic_vector(31 downto 0);
input : in std_logic_vector(31 downto 0);
shift : in std_logic_vector(5 downto 0);
padding : in std_logic
);
end shr_141;
architecture augh of shr_141 is
signal tmp_padding : std_logic;
signal tmp_result : std_logic_vector(32 downto 0);
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Temporary signals
tmp_padding <= padding;
tmp_result <= std_logic_vector(shift_right( unsigned(padding & input), to_integer(shift) ));
-- The output
output <= tmp_result(31 downto 0);
end architecture;
|
gpl-2.0
|
bcf3b1269e39db98a0c7fc15a1d4c33e
| 0.704874 | 3.086351 | false | false | false | false |
mmoraless/ecc_vhdl
|
ecc_add/Lut_3in_163.vhd
| 1 | 6,793 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
---------------------------------------------------------------------------------------------
entity lut_3in is
generic(
NUM_BITS: positive := 163
);
port (
A: in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
s0: in STD_LOGIC;
B: in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
D: out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0)
);
end;
---------------------------------------------------------------------------------------------
architecture behave of lut_3in is
---------------------------------------------------------------------------
---------------------------------------------------------------------------
begin
D(0) <= (A(0) and s0) xor B(0);
D(1) <= (A(1) and s0) xor B(1);
D(2) <= (A(2) and s0) xor B(2);
D(3) <= (A(3) and s0) xor B(3);
D(4) <= (A(4) and s0) xor B(4);
D(5) <= (A(5) and s0) xor B(5);
D(6) <= (A(6) and s0) xor B(6);
D(7) <= (A(7) and s0) xor B(7);
D(8) <= (A(8) and s0) xor B(8);
D(9) <= (A(9) and s0) xor B(9);
D(10) <= (A(10) and s0) xor B(10);
D(11) <= (A(11) and s0) xor B(11);
D(12) <= (A(12) and s0) xor B(12);
D(13) <= (A(13) and s0) xor B(13);
D(14) <= (A(14) and s0) xor B(14);
D(15) <= (A(15) and s0) xor B(15);
D(16) <= (A(16) and s0) xor B(16);
D(17) <= (A(17) and s0) xor B(17);
D(18) <= (A(18) and s0) xor B(18);
D(19) <= (A(19) and s0) xor B(19);
D(20) <= (A(20) and s0) xor B(20);
D(21) <= (A(21) and s0) xor B(21);
D(22) <= (A(22) and s0) xor B(22);
D(23) <= (A(23) and s0) xor B(23);
D(24) <= (A(24) and s0) xor B(24);
D(25) <= (A(25) and s0) xor B(25);
D(26) <= (A(26) and s0) xor B(26);
D(27) <= (A(27) and s0) xor B(27);
D(28) <= (A(28) and s0) xor B(28);
D(29) <= (A(29) and s0) xor B(29);
D(30) <= (A(30) and s0) xor B(30);
D(31) <= (A(31) and s0) xor B(31);
D(32) <= (A(32) and s0) xor B(32);
D(33) <= (A(33) and s0) xor B(33);
D(34) <= (A(34) and s0) xor B(34);
D(35) <= (A(35) and s0) xor B(35);
D(36) <= (A(36) and s0) xor B(36);
D(37) <= (A(37) and s0) xor B(37);
D(38) <= (A(38) and s0) xor B(38);
D(39) <= (A(39) and s0) xor B(39);
D(40) <= (A(40) and s0) xor B(40);
D(41) <= (A(41) and s0) xor B(41);
D(42) <= (A(42) and s0) xor B(42);
D(43) <= (A(43) and s0) xor B(43);
D(44) <= (A(44) and s0) xor B(44);
D(45) <= (A(45) and s0) xor B(45);
D(46) <= (A(46) and s0) xor B(46);
D(47) <= (A(47) and s0) xor B(47);
D(48) <= (A(48) and s0) xor B(48);
D(49) <= (A(49) and s0) xor B(49);
D(50) <= (A(50) and s0) xor B(50);
D(51) <= (A(51) and s0) xor B(51);
D(52) <= (A(52) and s0) xor B(52);
D(53) <= (A(53) and s0) xor B(53);
D(54) <= (A(54) and s0) xor B(54);
D(55) <= (A(55) and s0) xor B(55);
D(56) <= (A(56) and s0) xor B(56);
D(57) <= (A(57) and s0) xor B(57);
D(58) <= (A(58) and s0) xor B(58);
D(59) <= (A(59) and s0) xor B(59);
D(60) <= (A(60) and s0) xor B(60);
D(61) <= (A(61) and s0) xor B(61);
D(62) <= (A(62) and s0) xor B(62);
D(63) <= (A(63) and s0) xor B(63);
D(64) <= (A(64) and s0) xor B(64);
D(65) <= (A(65) and s0) xor B(65);
D(66) <= (A(66) and s0) xor B(66);
D(67) <= (A(67) and s0) xor B(67);
D(68) <= (A(68) and s0) xor B(68);
D(69) <= (A(69) and s0) xor B(69);
D(70) <= (A(70) and s0) xor B(70);
D(71) <= (A(71) and s0) xor B(71);
D(72) <= (A(72) and s0) xor B(72);
D(73) <= (A(73) and s0) xor B(73);
D(74) <= (A(74) and s0) xor B(74);
D(75) <= (A(75) and s0) xor B(75);
D(76) <= (A(76) and s0) xor B(76);
D(77) <= (A(77) and s0) xor B(77);
D(78) <= (A(78) and s0) xor B(78);
D(79) <= (A(79) and s0) xor B(79);
D(80) <= (A(80) and s0) xor B(80);
D(81) <= (A(81) and s0) xor B(81);
D(82) <= (A(82) and s0) xor B(82);
D(83) <= (A(83) and s0) xor B(83);
D(84) <= (A(84) and s0) xor B(84);
D(85) <= (A(85) and s0) xor B(85);
D(86) <= (A(86) and s0) xor B(86);
D(87) <= (A(87) and s0) xor B(87);
D(88) <= (A(88) and s0) xor B(88);
D(89) <= (A(89) and s0) xor B(89);
D(90) <= (A(90) and s0) xor B(90);
D(91) <= (A(91) and s0) xor B(91);
D(92) <= (A(92) and s0) xor B(92);
D(93) <= (A(93) and s0) xor B(93);
D(94) <= (A(94) and s0) xor B(94);
D(95) <= (A(95) and s0) xor B(95);
D(96) <= (A(96) and s0) xor B(96);
D(97) <= (A(97) and s0) xor B(97);
D(98) <= (A(98) and s0) xor B(98);
D(99) <= (A(99) and s0) xor B(99);
D(100) <= (A(100) and s0) xor B(100);
D(101) <= (A(101) and s0) xor B(101);
D(102) <= (A(102) and s0) xor B(102);
D(103) <= (A(103) and s0) xor B(103);
D(104) <= (A(104) and s0) xor B(104);
D(105) <= (A(105) and s0) xor B(105);
D(106) <= (A(106) and s0) xor B(106);
D(107) <= (A(107) and s0) xor B(107);
D(108) <= (A(108) and s0) xor B(108);
D(109) <= (A(109) and s0) xor B(109);
D(110) <= (A(110) and s0) xor B(110);
D(111) <= (A(111) and s0) xor B(111);
D(112) <= (A(112) and s0) xor B(112);
D(113) <= (A(113) and s0) xor B(113);
D(114) <= (A(114) and s0) xor B(114);
D(115) <= (A(115) and s0) xor B(115);
D(116) <= (A(116) and s0) xor B(116);
D(117) <= (A(117) and s0) xor B(117);
D(118) <= (A(118) and s0) xor B(118);
D(119) <= (A(119) and s0) xor B(119);
D(120) <= (A(120) and s0) xor B(120);
D(121) <= (A(121) and s0) xor B(121);
D(122) <= (A(122) and s0) xor B(122);
D(123) <= (A(123) and s0) xor B(123);
D(124) <= (A(124) and s0) xor B(124);
D(125) <= (A(125) and s0) xor B(125);
D(126) <= (A(126) and s0) xor B(126);
D(127) <= (A(127) and s0) xor B(127);
D(128) <= (A(128) and s0) xor B(128);
D(129) <= (A(129) and s0) xor B(129);
D(130) <= (A(130) and s0) xor B(130);
D(131) <= (A(131) and s0) xor B(131);
D(132) <= (A(132) and s0) xor B(132);
D(133) <= (A(133) and s0) xor B(133);
D(134) <= (A(134) and s0) xor B(134);
D(135) <= (A(135) and s0) xor B(135);
D(136) <= (A(136) and s0) xor B(136);
D(137) <= (A(137) and s0) xor B(137);
D(138) <= (A(138) and s0) xor B(138);
D(139) <= (A(139) and s0) xor B(139);
D(140) <= (A(140) and s0) xor B(140);
D(141) <= (A(141) and s0) xor B(141);
D(142) <= (A(142) and s0) xor B(142);
D(143) <= (A(143) and s0) xor B(143);
D(144) <= (A(144) and s0) xor B(144);
D(145) <= (A(145) and s0) xor B(145);
D(146) <= (A(146) and s0) xor B(146);
D(147) <= (A(147) and s0) xor B(147);
D(148) <= (A(148) and s0) xor B(148);
D(149) <= (A(149) and s0) xor B(149);
D(150) <= (A(150) and s0) xor B(150);
D(151) <= (A(151) and s0) xor B(151);
D(152) <= (A(152) and s0) xor B(152);
D(153) <= (A(153) and s0) xor B(153);
D(154) <= (A(154) and s0) xor B(154);
D(155) <= (A(155) and s0) xor B(155);
D(156) <= (A(156) and s0) xor B(156);
D(157) <= (A(157) and s0) xor B(157);
D(158) <= (A(158) and s0) xor B(158);
D(159) <= (A(159) and s0) xor B(159);
D(160) <= (A(160) and s0) xor B(160);
D(161) <= (A(161) and s0) xor B(161);
D(162) <= (A(162) and s0) xor B(162);
end;
|
gpl-3.0
|
48e0568a4ef3c81f4f16a1426da24e6d
| 0.471515 | 1.892728 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_22.vhd
| 4 | 2,203 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- code from book:
entity mux4 is
port ( i0, i1, i2, i3, sel0, sel1 : in bit;
z : out bit );
end entity mux4;
-- end of code from book
----------------------------------------------------------------
architecture functional of mux4 is
begin
out_select : process (sel0, sel1, i0, i1, i2, i3) is
subtype bits_2 is bit_vector(1 downto 0);
begin
case bits_2'(sel1, sel0) is
when "00" => z <= i0;
when "01" => z <= i1;
when "10" => z <= i2;
when "11" => z <= i3;
end case;
end process out_select;
end architecture functional;
----------------------------------------------------------------
entity inline_22 is
end entity inline_22;
----------------------------------------------------------------
architecture test of inline_22 is
signal select_line, line0, line1, result_line : bit;
begin
-- code from book:
a_mux : entity work.mux4
port map ( sel0 => select_line, i0 => line0, i1 => line1,
z => result_line,
sel1 => '0', i2 => '1', i3 => '1' );
-- end of code from book
----------------
stimulus : process is
begin
wait for 5 ns;
line0 <= '1'; wait for 5 ns;
line1 <= '1'; wait for 5 ns;
select_line <= '1'; wait for 5 ns;
line1 <= '0'; wait for 5 ns;
line0 <= '0'; wait for 5 ns;
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
b341b90527d5760951564318421037f9
| 0.569678 | 3.677796 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/interlock_control.vhd
| 4 | 3,051 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity nor_gate is
generic ( width : positive;
Tpd01, Tpd10 : delay_length );
port ( input : in std_logic_vector(0 to width - 1);
output : out std_logic );
end entity nor_gate;
architecture primitive of nor_gate is
function max ( a, b : delay_length ) return delay_length is
begin
if a > b then
return a;
else
return b;
end if;
end function max;
begin
reducer : process (input) is
variable result : std_logic;
begin
result := '0';
for index in input'range loop
result := result or input(index);
end loop;
if not result = '1' then
output <= not result after Tpd01;
elsif not result = '0' then
output <= not result after Tpd10;
else
output <= not result after max(Tpd01, Tpd10);
end if;
end process reducer;
end architecture primitive;
library ieee; use ieee.std_logic_1164.all;
library cell_lib;
entity interlock_control is
end entity interlock_control;
-- code from book
architecture detailed_timing of interlock_control is
component nor_gate is
generic ( input_width : positive );
port ( input : in std_logic_vector(0 to input_width - 1);
output : out std_logic );
end component nor_gate;
for ex_interlock_gate : nor_gate
use entity cell_lib.nor_gate(primitive)
generic map ( width => input_width,
Tpd01 => 250 ps, Tpd10 => 200 ps ); -- estimates
-- . . .
-- not in book
signal reg_access_hazard, load_hazard, stall_ex_n : std_logic;
-- end not in book
begin
ex_interlock_gate : component nor_gate
generic map ( input_width => 2 )
port map ( input(0) => reg_access_hazard,
input(1) => load_hazard,
output => stall_ex_n);
-- . . .
-- not in book
reg_access_hazard <= '0' after 10 ns, '1' after 20 ns, 'X' after 30 ns;
load_hazard <= '0' after 2 ns, '1' after 4 ns, 'X' after 6 ns,
'0' after 12 ns, '1' after 14 ns, 'X' after 16 ns,
'0' after 22 ns, '1' after 24 ns, 'X' after 26 ns,
'0' after 32 ns, '1' after 34 ns, 'X' after 36 ns;
-- end not in book
end architecture detailed_timing;
-- end code from book
|
gpl-2.0
|
591ebf25fb6a092a1f823dcbbdc1b918
| 0.641757 | 3.675904 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/bug10/TestFIFO.vhdl
| 3 | 4,821 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- equal speed writer and reader
-- faster writer
-- faster reader
entity TestFIFO is
end TestFIFO;
architecture behaviour of TestFIFO is
component FIFO is
generic(Depth : integer := 3);
port(
iClk : in std_logic;
iReset : in std_logic;
-- write port
iWrEn : in std_logic;
iData : in std_logic_vector(7 downto 0);
oHasSpace : out std_logic;
-- read port
iRdEn : in std_logic;
oData : out std_logic_vector(7 downto 0);
oHasData : out std_logic
);
end component;
type ramType is array(0 to 255) of std_logic_vector(7 downto 0);
signal clk, reset : std_logic;
signal wrEn, rdEn : std_logic;
signal inData, outData : std_logic_vector(7 downto 0);
signal hasSpace, hasData : std_logic;
signal rawInData : std_logic_vector(7 downto 0);
signal rawWrEn, rawRdEn : std_logic;
signal dstRAM : ramType;
signal writerData : unsigned(8 downto 0) := (others => '0');
signal writerWrEn : std_logic;
signal writeDone : std_logic;
signal writerClkCntInit, readerClkCntInit : unsigned(1 downto 0) := "00";
signal writerClkCnt, readerClkCnt : unsigned(1 downto 0) := "00";
signal readerCnt : unsigned(8 downto 0) := (others => '0');
signal readerRdEn : std_logic;
signal readDone : std_logic;
signal rawMode : std_logic;
begin
FIFO0: FIFO port map(
iClk => clk, iReset => reset,
iWrEn => wrEn, iData => inData, oHasSpace => hasSpace,
iRdEn => rdEn, oData => outData, oHasData => hasData
);
wrEn <= rawWrEn when rawMode = '1' else writerWrEn;
rdEn <= rawRdEn when rawMode = '1' else readerRdEn;
inData <= rawInData when rawMode = '1' else std_logic_vector(writerData(7 downto 0));
writeDone <= writerData(7); -- done when writerData == 0x100
writerWrEn <= '1' when (writerClkCnt = "00") and (hasSpace = '1') and (writeDone = '0') else '0';
fifoWriter: process(clk)
begin
if clk'event and clk = '1' and reset = '0' then
if writerClkCnt = "00" then
if hasSpace = '1' and writeDone = '0' then
writerData <= writerData + 1;
end if;
report "writerClkCnt <= writerClkCntInit;";
writerClkCnt <= writerClkCntInit;
else
report "writerClkCnt <= writerClkCnt - 1;";
writerClkCnt <= writerClkCnt - 1;
end if;
end if;
end process;
readDone <= readerCnt(7); -- done when readerCnt == 0x100
readerRdEn <= '1' when readerClkCnt = "00" and hasData = '1' and readDone = '0' else '0';
fifoReader: process(clk)
begin
if clk'event and clk = '1' and reset = '0' then
if readerClkCnt = "00" then
if hasData = '1' and readDone = '0' then
dstRAM(to_integer(readerCnt)) <= outData;
readerCnt <= readerCnt + 1;
end if;
readerClkCnt <= readerClkCntInit;
else
readerClkCnt <= readerClkCnt - 1;
end if;
end if;
end process;
main: process
procedure nextCycle is begin
wait for 500 ns;
report "rise";
clk <= '1';
wait for 500 ns;
clk <= '0';
end procedure;
procedure doReset is begin
reset <= '1';
clk <= '0';
nextCycle;
reset <= '0';
end procedure;
procedure testSimple is
procedure write(data : std_logic_vector(7 downto 0); expHasData, expHasSpace: std_logic) is begin
rawWrEn <= '1';
rawInData <= data;
nextCycle;
assert hasData = expHasData and hasSpace = expHasSpace;
end procedure;
begin
rawMode <= '1';
rawWrEn <= '0';
rawRdEn <= '0';
doReset;
assert hasData = '0' and hasSpace = '1';
write(X"70", '1', '1');
write(X"61", '1', '1');
write(X"52", '1', '1');
write(X"43", '1', '1');
write(X"34", '1', '1');
write(X"25", '1', '1');
write(X"16", '1', '1');
write(X"07", '1', '0');
write(X"5a", '1', '0'); -- attempt to write to the full FIFO, should be ignored
end procedure;
procedure clearDst is
variable i : integer;
begin
for i in 0 to 255 loop
dstRAM(i) <= X"00";
end loop;
end procedure;
procedure checkDst is
variable i : integer;
begin
for i in 0 to 255 loop
assert dstRAM(i) = std_logic_vector(to_unsigned(i, 8));
end loop;
end procedure;
-- 0 means fastest
procedure setWriterSpeed(div: integer) is begin
writerClkCntInit <= to_unsigned(div, 2);
writerClkCnt <= to_unsigned(div, 2);
writerData <= (others => '0');
end procedure;
procedure setReaderSpeed(div: integer) is begin
readerClkCntInit <= to_unsigned(div, 2);
readerClkCnt <= to_unsigned(div, 2);
end procedure;
procedure testEqualFastSpeed is begin
setWriterSpeed(0);
setReaderSpeed(0);
clearDst;
doReset;
while readDone = '0' loop
nextCycle;
end loop;
checkDst;
end procedure;
begin
testSimple;
-- testEqualFastSpeed;
wait; -- wait forever, end simulation
end process;
end behaviour;
|
gpl-2.0
|
7910f1350ec52e09709b26c570f387e8
| 0.639286 | 2.990695 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc992.vhd
| 4 | 10,328 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc992.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
PACKAGE c06s03b00x00p08n01i00992pkg IS
--
-- This packages contains declarations of User attributes
--
-- ----------------------------------------------------------------------
--
TYPE RESISTANCE IS RANGE 0 TO 1E9
UNITS
pf;
nf = 1000 pf;
mf = 1000 nf;
END UNITS;
TYPE t_logic IS (
U, D,
Z0, Z1, ZDX, DZX, ZX,
W0, W1, WZ0, WZ1, WDX, DWX, WZX, ZWX, WX,
R0, R1, RW0, RW1, RZ0, RZ1, RDX, DRX, RZX, ZRX, RWX, WRX, RX,
F0, F1, FR0, FR1, FW0, FW1, FZ0, FZ1, FDX, DFX, FZX, ZFX, FWX, WFX, FRX, RFX, FX
);
--
-- Scalar types Declarations
--
SUBTYPE st_scl1 IS BOOLEAN;
SUBTYPE st_scl2 IS BIT;
SUBTYPE st_scl3 IS CHARACTER;
SUBTYPE st_scl4 IS INTEGER;
SUBTYPE st_scl5 IS REAL;
SUBTYPE st_scl6 IS TIME;
SUBTYPE st_scl7 IS RESISTANCE;
SUBTYPE st_scl8 IS t_logic;
--
-- character string types
--
SUBTYPE st_str1 IS STRING;
SUBTYPE st_str2 IS STRING (1 TO 4);
--
-- Scalar types with a range constraint
--
SUBTYPE cst_scl1 IS BOOLEAN RANGE TRUE TO TRUE;
SUBTYPE cst_scl2 IS BIT RANGE '0' TO '0';
SUBTYPE cst_scl3 IS CHARACTER RANGE 'a' TO 'z';
SUBTYPE cst_scl4 IS INTEGER RANGE 10 DOWNTO 0;
SUBTYPE cst_scl5 IS REAL RANGE 0.0 TO 10.0;
SUBTYPE cst_scl6 IS TIME RANGE 0 fs TO 10 ns;
SUBTYPE cst_scl7 IS RESISTANCE RANGE 0 pf TO 10000 pf;
SUBTYPE cst_scl8 IS t_logic RANGE F0 TO FX;
-- -----------------------------------------------------------------------------------------
-- Attribute Declarations
-- -----------------------------------------------------------------------------------------
--
ATTRIBUTE atr_scl1 : st_scl1;
ATTRIBUTE atr_scl2 : st_scl2;
ATTRIBUTE atr_scl3 : st_scl3;
ATTRIBUTE atr_scl4 : st_scl4;
ATTRIBUTE atr_scl5 : st_scl5;
ATTRIBUTE atr_scl6 : st_scl6;
ATTRIBUTE atr_scl7 : st_scl7;
ATTRIBUTE atr_scl8 : st_scl8;
ATTRIBUTE atr_str1 : st_str1;
ATTRIBUTE atr_str2 : st_str2;
ATTRIBUTE cat_scl1 : cst_scl1;
ATTRIBUTE cat_scl2 : cst_scl2;
ATTRIBUTE cat_scl3 : cst_scl3;
ATTRIBUTE cat_scl4 : cst_scl4;
ATTRIBUTE cat_scl5 : cst_scl5;
ATTRIBUTE cat_scl6 : cst_scl6;
ATTRIBUTE cat_scl7 : cst_scl7;
ATTRIBUTE cat_scl8 : cst_scl8;
-- =========================================================================================
--
-- Apply attributes to the package
--
ATTRIBUTE atr_scl1 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS TRUE;
ATTRIBUTE atr_scl2 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS '0';
ATTRIBUTE atr_scl3 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS 'z';
ATTRIBUTE atr_scl4 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS 0;
ATTRIBUTE atr_scl5 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS 10.0;
ATTRIBUTE atr_scl6 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS 10 ns;
ATTRIBUTE atr_scl7 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS 10000 pf;
ATTRIBUTE atr_scl8 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS FX;
ATTRIBUTE atr_str1 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS "packit";
ATTRIBUTE atr_str2 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS "pack";
ATTRIBUTE cat_scl1 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS TRUE;
ATTRIBUTE cat_scl2 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS '0';
ATTRIBUTE cat_scl3 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS 'z';
ATTRIBUTE cat_scl4 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS 0;
ATTRIBUTE cat_scl5 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS 10.0;
ATTRIBUTE cat_scl6 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS 10 ns;
ATTRIBUTE cat_scl7 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS 10000 pf;
ATTRIBUTE cat_scl8 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS FX;
--
END;
use work.all;
use c06s03b00x00p08n01i00992pkg.all;
ENTITY c06s03b00x00p08n01i00992ent IS
END c06s03b00x00p08n01i00992ent;
ARCHITECTURE c06s03b00x00p08n01i00992arch OF c06s03b00x00p08n01i00992ent IS
BEGIN
TESTING: PROCESS
BEGIN
ASSERT c06s03b00x00p08n01i00992pkg'atr_scl1 = TRUE
REPORT "ERROR: Wrong value for 'atr_scl1" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00992pkg'atr_scl2 = '0'
REPORT "ERROR: Wrong value for 'atr_scl2" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00992pkg'atr_scl3 = 'z'
REPORT "ERROR: Wrong value for 'atr_scl3" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00992pkg'atr_scl4 = 0
REPORT "ERROR: Wrong value for 'atr_scl4" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00992pkg'atr_scl5 = 10.0
REPORT "ERROR: Wrong value for 'atr_scl5" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00992pkg'atr_scl6 = 10 ns
REPORT "ERROR: Wrong value for 'atr_scl6" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00992pkg'atr_scl7 = 10000 pf
REPORT "ERROR: Wrong value for 'atr_scl7" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00992pkg'atr_scl8 = FX
REPORT "ERROR: Wrong value for 'atr_scl8" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00992pkg'atr_str1 = "packit"
REPORT "ERROR: Wrong value for 'atr_str1" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00992pkg'atr_str2 = "pack"
REPORT "ERROR: Wrong value for 'atr_str2" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00992pkg'cat_scl1 = TRUE
REPORT "ERROR: Wrong value for 'cat_scl1" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00992pkg'cat_scl2 = '0'
REPORT "ERROR: Wrong value for 'cat_scl2" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00992pkg'cat_scl3 = 'z'
REPORT "ERROR: Wrong value for 'cat_scl3" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00992pkg'cat_scl4 = 0
REPORT "ERROR: Wrong value for 'cat_scl4" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00992pkg'cat_scl5 = 10.0
REPORT "ERROR: Wrong value for 'cat_scl5" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00992pkg'cat_scl6 = 10 ns
REPORT "ERROR: Wrong value for 'cat_scl6" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00992pkg'cat_scl7 = 10000 pf
REPORT "ERROR: Wrong value for 'cat_scl7" SEVERITY FAILURE;
ASSERT c06s03b00x00p08n01i00992pkg'cat_scl8 = FX
REPORT "ERROR: Wrong value for 'cat_scl8" SEVERITY FAILURE;
assert NOT( c06s03b00x00p08n01i00992pkg'atr_scl1 = TRUE
and c06s03b00x00p08n01i00992pkg'atr_scl2 = '0'
and c06s03b00x00p08n01i00992pkg'atr_scl3 = 'z'
and c06s03b00x00p08n01i00992pkg'atr_scl4 = 0
and c06s03b00x00p08n01i00992pkg'atr_scl5 = 10.0
and c06s03b00x00p08n01i00992pkg'atr_scl6 = 10 ns
and c06s03b00x00p08n01i00992pkg'atr_scl7 = 10000 pf
and c06s03b00x00p08n01i00992pkg'atr_scl8 = FX
and c06s03b00x00p08n01i00992pkg'atr_str1 = "packit"
and c06s03b00x00p08n01i00992pkg'atr_str2 = "pack"
and c06s03b00x00p08n01i00992pkg'cat_scl1 = TRUE
and c06s03b00x00p08n01i00992pkg'cat_scl2 = '0'
and c06s03b00x00p08n01i00992pkg'cat_scl3 = 'z'
and c06s03b00x00p08n01i00992pkg'cat_scl4 = 0
and c06s03b00x00p08n01i00992pkg'cat_scl5 = 10.0
and c06s03b00x00p08n01i00992pkg'cat_scl6 = 10 ns
and c06s03b00x00p08n01i00992pkg'cat_scl7 = 10000 pf
and c06s03b00x00p08n01i00992pkg'cat_scl8 = FX)
report "***PASSED TEST: c06s03b00x00p08n01i00992"
severity NOTE;
assert ( c06s03b00x00p08n01i00992pkg'atr_scl1 = TRUE
and c06s03b00x00p08n01i00992pkg'atr_scl2 = '0'
and c06s03b00x00p08n01i00992pkg'atr_scl3 = 'z'
and c06s03b00x00p08n01i00992pkg'atr_scl4 = 0
and c06s03b00x00p08n01i00992pkg'atr_scl5 = 10.0
and c06s03b00x00p08n01i00992pkg'atr_scl6 = 10 ns
and c06s03b00x00p08n01i00992pkg'atr_scl7 = 10000 pf
and c06s03b00x00p08n01i00992pkg'atr_scl8 = FX
and c06s03b00x00p08n01i00992pkg'atr_str1 = "packit"
and c06s03b00x00p08n01i00992pkg'atr_str2 = "pack"
and c06s03b00x00p08n01i00992pkg'cat_scl1 = TRUE
and c06s03b00x00p08n01i00992pkg'cat_scl2 = '0'
and c06s03b00x00p08n01i00992pkg'cat_scl3 = 'z'
and c06s03b00x00p08n01i00992pkg'cat_scl4 = 0
and c06s03b00x00p08n01i00992pkg'cat_scl5 = 10.0
and c06s03b00x00p08n01i00992pkg'cat_scl6 = 10 ns
and c06s03b00x00p08n01i00992pkg'cat_scl7 = 10000 pf
and c06s03b00x00p08n01i00992pkg'cat_scl8 = FX)
report "***FAILED TEST: c06s03b00x00p08n01i00992 - Expanded name denotes a primary unit contained in design library test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p08n01i00992arch;
|
gpl-2.0
|
313375890b24bf0407006c3b512efb2f
| 0.63507 | 2.992756 | false | false | false | false |
nkkav/bstest-s3esk
|
bstest_tb.vhd
| 1 | 1,913 |
library IEEE, STD;
use STD.textio.all;
use WORK.std_logic_textio.all;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity bstest_tb is
end bstest_tb;
architecture tb_arch of bstest_tb is
-- UUT component
component bstest
port (
sldsw : in std_logic_vector(3 downto 0);
button : in std_logic_vector(3 downto 0); -- N-E-W-S
led : out std_logic_vector(7 downto 0)
);
end component;
-- I/O signals
signal clk : std_logic := '0';
signal sldsw : std_logic_vector(3 downto 0);
signal button : std_logic_vector(3 downto 0);
signal led : std_logic_vector(7 downto 0);
-- Constant declarations
constant CLK_PERIOD : time := 20 ns;
-- Declare results file
file ResultsFile: text open write_mode is "bstest_results.txt";
begin
uut : bstest
port map (
sldsw => sldsw,
button => button,
led => led
);
DATA_STIM: process
variable count_hi : integer range 0 to 15 := 0;
variable count_lo : integer range 0 to 15 := 0;
variable line_el: line;
begin
for i in 0 to 255 loop
count_hi := i / 16;
count_lo := i mod 16;
sldsw <= std_logic_vector(to_unsigned(count_hi, 4));
button <= std_logic_vector(to_unsigned(count_lo, 4));
-- Write the time
write(line_el, now); -- write the line
write(line_el, ':'); -- write the line
-- Write the sldsw signal
write(line_el, ' ');
write(line_el, sldsw); -- write the line
-- Write the button signal
write(line_el, ' ');
write(line_el, button); -- write the line
wait for CLK_PERIOD;
-- Write the led signal
write(line_el, ' ');
write(line_el, led); -- write the line
writeline(ResultsFile, line_el); -- write the contents into the file
wait for 9*CLK_PERIOD;
end loop;
wait for CLK_PERIOD;
end process DATA_STIM;
end tb_arch;
|
bsd-3-clause
|
553b251991092c043073b3d8ff085485
| 0.606377 | 3.43447 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2529.vhd
| 4 | 1,843 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2529.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p06n04i02529ent IS
END c07s03b05x00p06n04i02529ent;
ARCHITECTURE c07s03b05x00p06n04i02529arch OF c07s03b05x00p06n04i02529ent IS
BEGIN
TESTING: PROCESS
variable V1 : Integer;
BEGIN
V1 := Integer (10.5);
assert NOT((V1 = 10) or ( V1 = 11 ))
report "***PASSED TEST: c07s03b05x00p06n04i02529"
severity NOTE;
assert ((V1 = 10) or ( V1 = 11 ))
report "***FAILED TEST: c07s03b05x00p06n04i02529 - The conversion of a floating point to an integer point, if the value is halfway between two integers, rounding may be up or down."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p06n04i02529arch;
|
gpl-2.0
|
c95d88b3a92da92ef1905b2e675b604e
| 0.66956 | 3.635108 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/signal_generator.vhd
| 4 | 1,880 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
entity signal_generator is
generic ( period : delay_length := 20 ns;
pulse_count : natural := 5 );
end entity signal_generator;
-- end not in book
library ieee; use ieee.std_logic_1164.all;
architecture top_level of signal_generator is
signal raw_signal : std_ulogic;
-- . . .
procedure generate_pulse_train ( width, separation : in delay_length;
number : in natural;
signal s : out std_ulogic ) is
begin
for count in 1 to number loop
s <= '1', '0' after width;
wait for width + separation;
end loop;
end procedure generate_pulse_train;
begin
raw_signal_generator : process is
begin
-- . . .
generate_pulse_train ( width => period / 2,
separation => period - period / 2,
number => pulse_count,
s => raw_signal );
-- . . .
-- not in book
wait;
-- end not in book
end process raw_signal_generator;
-- . . .
end architecture top_level;
|
gpl-2.0
|
c891f9280068ec6337f4c29f839bfd06
| 0.629787 | 4.205817 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc143.vhd
| 4 | 2,593 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc143.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c04s03b02x02p12n01i00143pkg is
type fourstate is ('0','1','x','z');
function fourstate_to_bit(x : fourstate) return bit;
procedure simple ( crude : in bit;
signal refined : out bit);
end c04s03b02x02p12n01i00143pkg;
package body c04s03b02x02p12n01i00143pkg is
procedure simple ( crude : in bit;
signal refined : out bit) is
begin
refined <= crude after 5 ns;
end simple;
function fourstate_to_bit(x : fourstate) return bit is
variable newval: bit := '0';
begin
case x is
when '0' => newval := '0';
when '1' => newval := '1';
when 'z' => newval := '0';
when 'x' => newval := '0';
end case;
return newval;
end fourstate_to_bit;
end c04s03b02x02p12n01i00143pkg;
use work.c04s03b02x02p12n01i00143pkg.all;
ENTITY c04s03b02x02p12n01i00143ent IS
port( x, y: in fourstate);
END c04s03b02x02p12n01i00143ent;
ARCHITECTURE c04s03b02x02p12n01i00143arch OF c04s03b02x02p12n01i00143ent IS
signal yint : bit;
BEGIN
simple ( fourstate_to_bit(y) , yint);
TESTING: PROCESS
BEGIN
wait for 10 ns;
assert NOT( yint = '0' )
report "***PASSED TEST: c04s03b02x02p12n01i00143"
severity NOTE;
assert ( yint = '0' )
report "***FAILED TEST: c04s03b02x02p12n01i00143 - Type conversion test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p12n01i00143arch;
|
gpl-2.0
|
1bcdbc3ca816235f363f674a2d4a9b59
| 0.653683 | 3.429894 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_and_or_inv.vhd
| 4 | 1,772 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_and_or_inv is
end entity tb_and_or_inv;
architecture test of tb_and_or_inv is
signal a1, a2, b1, b2, y : bit;
begin
dut : entity work.and_or_inv(primitive)
port map ( a1 => a1, a2 => a2, b1 => b1, b2 => b2,
y => y );
stimulus : process is
subtype stim_vector_type is bit_vector(0 to 3);
type stim_vector_array is array ( natural range <> ) of stim_vector_type;
constant stim_vector : stim_vector_array
:= ( "0000",
"0001",
"0010",
"0011",
"0100",
"0101",
"0110",
"0111",
"1000",
"1001",
"1010",
"1011",
"1100",
"1101",
"1110",
"1111" );
begin
for i in stim_vector'range loop
(a1, a2, b1, b2) <= stim_vector(i);
wait for 10 ns;
assert y = not ( (stim_vector(i)(0) and stim_vector(i)(1))
or (stim_vector(i)(2) and stim_vector(i)(3)) );
end loop;
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
1fba2ad68de683818ffcbb177cfdd8c8
| 0.628668 | 3.47451 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/ticket89/repro2.vhdl
| 3 | 354 |
entity repro2 is
end repro2;
architecture behav of repro2 is
signal s : natural;
begin -- behav
process (s) is
variable v : natural;
begin
v := s'delayed (10 ns);
end process;
process
begin
s <= 3;
wait for 0 ns;
s <= 4;
wait for 0 ns;
s <= 5;
wait for 0 ns;
s <= 5;
wait;
end process;
end behav;
|
gpl-2.0
|
10df084253c1960c6f6bca95074dd7b8
| 0.564972 | 3.218182 | false | false | false | false |
herenvarno/dlx
|
dlx_vhd/src/a.b-DataPath.core/a.b.f-Mul.core/a.b.f.0-BoothEncoder.vhd
| 1 | 1,285 |
--------------------------------------------------------------------------------
-- FILE: BoothEncoder
-- DESC: Encoder of Booth's Multiplier
--
-- Author:
-- Create: 2015-08-14
-- Update: 2015-08-14
-- Status: TESED
-- NOTE 1:
-- Encoder:
-- 0xx -- 0
-- x0x -- positive x1x -- negative
-- xx0 -- a xx1 -- 2a
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Consts.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity BoothEncoder is
port(
din: in std_logic_vector(2 downto 0);
sel: out std_logic_vector(2 downto 0)
);
end BoothEncoder;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture booth_encoder_arch of BoothEncoder is
begin
sel <= "000" when (din="000" or din="111") else -- 0
"100" when (din="001" or din="010") else -- +a
"110" when (din="101" or din="110") else -- -a
"101" when (din="011") else -- +2a
"111" when (din="100"); -- -2a
end booth_encoder_arch;
|
mit
|
9155c7f1221b07907bb0591e65d20c7f
| 0.389883 | 4.003115 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_25.vhd
| 4 | 2,096 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_25.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity nand3 is
generic ( Tpd : delay_length );
port ( a, b, c : in bit; y : out bit );
end entity nand3;
architecture basic of nand3 is
begin
y <= not (a and b and c) after Tpd;
end architecture basic;
library project_lib;
library stimulus;
use stimulus.stimulus_generators.all;
entity misc_logic is
end entity misc_logic;
-- code from book
architecture gate_level of misc_logic is
component nand3 is
generic ( Tpd : delay_length );
port ( a, b, c : in bit; y : out bit );
end component nand3;
for all : nand3
use entity project_lib.nand3(basic);
-- . . .
-- not in book
signal sig1, sig2, sig3, out_sig : bit;
signal test_vector : bit_vector(1 to 3);
-- end not in book
begin
gate1 : component nand3
generic map ( Tpd => 2 ns )
port map ( a => sig1, b => sig2, c => sig3, y => out_sig );
-- . . .
-- not in book
all_possible_values(test_vector, 10 ns);
(sig1, sig2, sig3) <= test_vector;
-- end not in book
end architecture gate_level;
-- end code from book
|
gpl-2.0
|
ee469884363ded06b411edaaa8802f06
| 0.617844 | 3.690141 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_Prop.vhd
| 4 | 35,957 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : DC_Motor.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2002/05/21
-------------------------------------------------------------------------------
-- Description: Basic DC Motor
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.electrical_systems.all;
entity DC_Motor is
generic (
r_wind : resistance; -- Motor winding resistance [Ohm]
kt : real; -- Torque coefficient [N*m/Amp]
l : inductance; -- Winding inductance [Henrys]
d : real; -- Damping coefficient [N*m/(rad/sec)]
j : mmoment_i); -- Moment of inertia [kg*meter**2]
port (terminal p1, p2 : electrical;
terminal shaft_rotv : rotational_v);
end entity DC_Motor;
-------------------------------------------------------------------------------
-- Basic Architecture
-- Motor equations: V = Kt*W + I*Rwind + L*dI/dt
-- T = -Kt*I + D*W + J*dW/dt
-------------------------------------------------------------------------------
architecture basic of DC_Motor is
quantity v across i through p1 to p2;
quantity w across torq through shaft_rotv to rotational_v_ref;
begin
torq == -1.0*kt*i + d*w + j*w'dot;
v == kt*w + i*r_wind + l*i'dot;
end architecture basic;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Constant Voltage Source (Includes Frequency Domain settings)
LIBRARY IEEE;
USE IEEE.MATH_REAL.ALL;
-- Use proposed IEEE natures and packages
LIBRARY IEEE_proposed;
USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
ENTITY v_constant IS
-- Initialize parameters
GENERIC (
level : VOLTAGE; -- Constant voltage value (V)
ac_mag : VOLTAGE := 1.0; -- AC magnitude (V)
ac_phase : real := 0.0); -- AC phase (degrees)
-- Define ports as electrical terminals
PORT (
TERMINAL pos, neg : ELECTRICAL);
END ENTITY v_constant;
-- Ideal Architecture (I = constant)
ARCHITECTURE ideal OF v_constant IS
-- Declare Branch Quantities
QUANTITY v ACROSS i THROUGH pos TO neg;
-- Declare quantity in frequency domain for AC analysis
QUANTITY ac_spec : real SPECTRUM ac_mag, math_2_pi*ac_phase/360.0;
BEGIN
IF DOMAIN = QUIESCENT_DOMAIN or DOMAIN = TIME_DOMAIN USE
v == level;
ELSE
v == ac_spec; -- used for Frequency (AC) analysis
END USE;
END ARCHITECTURE ideal;
--
-- C:\Rehan\Cs5\design_definition\hdl\vhdl\switch_dig_log.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.math_real.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity switch_dig_log is
generic
(
trans_time : real := 1.0e-9;
r_closed : resistance := 1.0e-3;
r_open : resistance := 1.0e6
);
port
(
terminal p1 : electrical ;
sw_state : in std_logic ;
terminal p2 : electrical
);
begin
end switch_dig_log ;
-----------------------------------------------------------------------------------------
architecture linear of switch_dig_log is
signal r_sig : resistance := r_open; -- create internal signal for CreateState process
quantity v across i through p1 to p2;
quantity r : resistance;
begin
-- purpose: Detect Switch state and assign resistance value to r_sig
-- type : combinational
-- inputs : sw_state
-- outputs: r_sig
DetectState: process (sw_state)
begin -- process DetectState
if (sw_state'event and sw_state = '0') then
r_sig <= r_open;
elsif (sw_state'event and sw_state = '1') then
r_sig <= r_closed;
end if;
end process DetectState;
-- Characteristic equations
r == r_sig'ramp(trans_time, trans_time);
v == r*i;
end architecture linear;
-------------------------------------------------------------------------------------------
architecture log of switch_dig_log is
constant log10_r_open : real := log10(r_open);
constant log10_r_closed : real := log10(r_closed);
signal log10_r_sig : resistance := log10_r_open; -- create internal signal for CreateState process
quantity v across i through p1 to p2;
quantity r : resistance;
quantity log10_r : real;
begin
-- purpose: Detect Switch state and assign resistance value to r_sig
-- type : combinational
-- inputs : sw_state
-- outputs: r_sig
DetectState: process (sw_state)
begin -- process DetectState
if (sw_state'event and sw_state = '0') then
log10_r_sig <= log10_r_open;
elsif (sw_state'event and sw_state = '1') then
log10_r_sig <= log10_r_closed;
end if;
end process DetectState;
-- Characteristic equations
log10_r == log10_r_sig'ramp(trans_time, trans_time);
r == 10**log10_r;
v == r*i;
end architecture log;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : opamp.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: 3-pin OpAmp model with behavioral architecture
-- Uses Q'LTF function to define open-loop response
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.math_real.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity opamp is
-- Initialize parameters
generic (rin : resistance := 1.0e6; -- Input resistance [Ohms]
rout : resistance := 100.0; -- Output resistance (Ohms]
avol : real := 100.0e3; -- Open loop gain
f_0dB : real := 1.0e6 -- Unity Gain Frequency [Hz]
);
-- Define ports as electrical terminals
port (
terminal in_pos, in_neg, output : electrical);
end entity opamp;
-------------------------------------------------------------------------------
-- Basic Architecture
-- Characteristics modeled:
-- 1. Open loop gain
-- 2. Frequency characteristics (single pole response)
-- 3. Input and output resistance
-- Uses Q'Ltf function to create open loop gain and roll off
-------------------------------------------------------------------------------
architecture basic of opamp is
-- Declare constants
constant f_3db : real := f_0db / avol; -- -3dB frequency
constant w_3dB : real := math_2_pi*f_3dB; -- -3dB freq in radians
-- Numerator and denominator for Q'LTF function
constant num : real_vector := (0 => avol);
constant den : real_vector := (1.0, 1.0/w_3dB);
-- Declare input and output quantities
quantity v_in across i_in through in_pos to in_neg;
quantity v_out across i_out through output;
begin -- ARCHITECTURE basic
i_in == v_in / rin; -- input current
v_out == v_in'ltf(num, den) + i_out*rout; -- output voltage
end architecture basic;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Electrical Resistor Model
-- Use proposed IEEE natures and packages
LIBRARY IEEE_proposed;
USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
ENTITY resistor IS
-- Initialize parameters
GENERIC (
res : RESISTANCE); -- resistance (no initial value)
-- Define ports as electrical terminals
PORT (
TERMINAL p1, p2 : ELECTRICAL);
END ENTITY resistor;
-- Ideal Architecture (V = I*R)
ARCHITECTURE ideal OF resistor IS
-- Declare Branch Quantities
QUANTITY v ACROSS i THROUGH p1 TO p2;
BEGIN
-- Characteristic equations
v == i*res;
END ARCHITECTURE ideal;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : comparator_d.vhd
-- Author : Mentor Graphics
-- Created : 2001/08/03
-- Last update: 2001/08/03
-------------------------------------------------------------------------------
-- Description: Voltage comparator with digital output
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/08/03 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- Use IEEE natures and packages
library IEEE;
use ieee.std_logic_1164.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
use IEEE_proposed.ENERGY_SYSTEMS.all;
entity comparator_d is
port (
terminal in_pos : electrical;
terminal in_neg : electrical;
signal output : out std_logic := '1' -- Digital output
);
end comparator_d;
-------------------------------------------------------------------------------
-- Behavioral architecture
-------------------------------------------------------------------------------
architecture behavioral of comparator_d is
quantity Vin across in_pos;
quantity Vref across in_neg;
begin -- behavioral
-- purpose: Detect threshold crossing and assign event on output
-- type : combinational
-- inputs : vin'above(thres)
-- outputs: pulse_signal
process (Vin'above(Vref)) is
begin -- PROCESS
if Vin'above(Vref) then
output <= '1' after 1us;
else
output <= '0' after 1us;
end if;
end process;
end behavioral;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : v_pulse.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/07/09
-------------------------------------------------------------------------------
-- Description: Voltage Pulse Source
-- Includes Frequency Domain settings
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-- 2001/07/09 1.1 Mentor Graphics Changed input parameters to type
-- time. Uses time2real function.
-- Pulsewidth no longer includes
-- rise and fall times.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity v_pulse is
generic (
initial : voltage := 0.0; -- initial value [Volts]
pulse : voltage; -- pulsed value [Volts]
ti2p : time := 1ns; -- initial to pulse [Sec]
tp2i : time := 1ns; -- pulse to initial [Sec]
delay : time := 0ms; -- delay time [Sec]
width : time; -- duration of pulse [Sec]
period : time; -- period [Sec]
ac_mag : voltage := 1.0; -- AC magnitude [Volts]
ac_phase : real := 0.0); -- AC phase [Degrees]
port (
terminal pos, neg : electrical);
end entity v_pulse;
-------------------------------------------------------------------------------
-- Ideal Architecture
-------------------------------------------------------------------------------
architecture ideal of v_pulse is
-- Declare Through and Across Branch Quantities
quantity v across i through pos to neg;
-- Declare quantity in frequency domain for AC analysis
quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
-- Signal used in CreateEvent process below
signal pulse_signal : voltage := initial;
-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
-- Note: these lines gave an error during simulation. Had to use a
-- function call instead.
-- constant ri2p : real := time'pos(ti2p) * 1.0e-15;
-- constant rp2i : real := time'pos(tp2i) * 1.0e-15;
-- Function to convert numbers of type TIME to type REAL
function time2real(tt : time) return real is
begin
return time'pos(tt) * 1.0e-15;
end time2real;
-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
constant ri2p : real := time2real(ti2p);
constant rp2i : real := time2real(tp2i);
begin
if domain = quiescent_domain or domain = time_domain use
v == pulse_signal'ramp(ri2p, rp2i); -- create rise and fall transitions
else
v == ac_spec; -- used for Frequency (AC) analysis
end use;
-- purpose: Create events to define pulse shape
-- type : combinational
-- inputs :
-- outputs: pulse_signal
CreateEvent : process
begin
wait for delay;
loop
pulse_signal <= pulse;
wait for (width + ti2p);
pulse_signal <= initial;
wait for (period - width - ti2p);
end loop;
end process CreateEvent;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity pwm_mac is
port(
terminal inp : electrical;
terminal inm : electrical;
dig_out : out std_logic
);
end pwm_mac;
architecture pwm_mac of pwm_mac is
-- Component declarations
-- Signal declarations
terminal cmp_in : electrical;
terminal plse_in : electrical;
terminal XSIG010002 : electrical;
terminal XSIG010003 : electrical;
begin
-- Signal assignments
-- Component instances
U1 : entity work.opamp(basic)
port map(
in_neg => XSIG010002,
in_pos => inm,
output => cmp_in
);
R1 : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => XSIG010002,
p2 => cmp_in
);
v2 : entity work.v_constant(ideal)
generic map(
level => 0.0
)
port map(
pos => XSIG010003,
neg => ELECTRICAL_REF
);
R2 : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => plse_in,
p2 => XSIG010002
);
R3 : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => inp,
p2 => XSIG010002
);
XCMP4 : entity work.comparator_d(behavioral)
port map(
output => dig_out,
in_pos => XSIG010003,
in_neg => cmp_in
);
v9 : entity work.v_pulse(ideal)
generic map(
initial => -4.7,
pulse => 4.7,
ti2p => 200 us,
tp2i => 200 us,
delay => 1 us,
width => 1 us,
period => 405 us
)
port map(
pos => plse_in,
neg => ELECTRICAL_REF
);
end pwm_mac;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : prop_pwl.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: Propeller Load (Rotational_V domain)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library ieee;
use ieee.math_real.all;
package pwl_functions is
function pwl_dim1_extrap (x : in real; xdata, ydata : in real_vector )
return real;
function interpolate (x,y2,y1,x2,x1 : in real)
return real;
function extrapolate (x,y2,y1,x2,x1 : in real)
return real;
end package pwl_functions;
package body pwl_functions is
function interpolate (x,y2,y1,x2,x1 : in real)
return real is
variable m, yvalue : real;
begin
assert (x1 /= x2)
report "interpolate: x1 cannot be equal to x2"
severity error;
assert (x >= x1) and (x <= x2)
report "interpolate: x must be between x1 and x2, inclusively "
severity error;
m := (y2 - y1)/(x2 - x1);
yvalue := y1 + m*(x - x1);
return yvalue;
end function interpolate;
function extrapolate (x,y2,y1,x2,x1 : in real)
return real is
variable m, yvalue : real;
begin
assert (x1 /= x2)
report "extrapolate: x1 cannot be equal to x2"
severity error;
assert (x <= x1) or (x >= x2)
report "extrapolate: x is within x1, x2 bounds; interpolation will be performed"
severity warning;
m := (y2 - y1)/(x2 - x1);
yvalue := y1 + m*(x - x1);
return yvalue;
end function extrapolate;
-- Created a new pwl_dim1_extrap function that returns extrapolated yvalue for "out-of-range" x value.
function pwl_dim1_extrap (x : in real; xdata, ydata : in real_vector )
return real is
variable xvalue, yvalue, m : real;
variable start, fin, mid: integer;
begin
if x <= xdata(0) then
yvalue := extrapolate(x,ydata(1),ydata(0),xdata(1),xdata(0));
return yvalue;
end if;
if x >= xdata(xdata'right) then
yvalue := extrapolate(x,ydata(ydata'right),ydata(ydata'right-1),xdata(xdata'right),xdata(xdata'right-1));
return yvalue;
end if;
start:=0;
fin:=xdata'right;
-- I assume that the valid elements are from xdata(0) to xdata(fin), inclusive.
-- so fin==n-1 in C terms (where n is the size of the array).
while start <=fin loop
mid:=(start+fin)/2;
if xdata(mid) < x
then start:=mid+1;
else fin:=mid-1;
end if;
end loop;
if xdata(mid) > x
then mid:=mid-1;
end if;
yvalue := interpolate(x,ydata(mid+1),ydata(mid),xdata(mid+1),xdata(mid));
return yvalue;
end function pwl_dim1_extrap;
end package body pwl_functions;
library IEEE_proposed; use IEEE_proposed.mechanical_systems.all;
library ieee; use ieee.math_real.all;
use work.pwl_functions.all;
entity prop_pwl is
generic (
ydata : real_vector; -- torque data
xdata : real_vector -- velocity data
);
port (terminal shaft1 : rotational_v);
end entity prop_pwl;
architecture ideal of prop_pwl is
quantity w across torq through shaft1 to rotational_v_ref;
begin
torq == pwl_dim1_extrap(w, xdata, ydata);
end architecture ideal;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : diode_pwl.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: Diode model with ideal architecture
-- Currently no Generics due to bug in DV
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.math_real.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
-- energy_systems package needed for Boltzmann constant (K = Joules/Kelvin)
use IEEE_proposed.energy_systems.all;
ENTITY diode_pwl IS
GENERIC (
ron : real; -- equivalent series resistance
roff : real); -- leakage resistance
PORT (
TERMINAL p, -- positive pin
m : electrical); -- minus pin
END ENTITY diode_pwl;
ARCHITECTURE simple OF diode_pwl IS
QUANTITY v across i through p TO m;
BEGIN -- simple ARCHITECTURE
if v'Above(0.0) use
i == v/ron;
elsif not v'Above(0.0) use
i == v/roff;
else
i == 0.0;
end use;
break on v'Above(0.0);
END ARCHITECTURE simple;
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Electrical sinusoidal voltage source (v_sine.vhd)
LIBRARY IEEE;
USE IEEE.MATH_REAL.ALL;
-- Use proposed IEEE natures and packages
LIBRARY IEEE_proposed;
USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
ENTITY v_sine IS
-- Initialize parameters
GENERIC (
freq : real; -- frequency, [Hertz]
amplitude : real; -- amplitude, [Volt]
phase : real := 0.0; -- initial phase, [Degree]
offset : real := 0.0; -- DC value, [Volt]
df : real := 0.0; -- damping factor, [1/second]
ac_mag : real := 1.0; -- AC magnitude, [Volt]
ac_phase : real := 0.0); -- AC phase, [Degree]
-- Define ports as electrical terminals
PORT (
TERMINAL pos, neg : ELECTRICAL);
END ENTITY v_sine;
-- Ideal Architecture
ARCHITECTURE ideal OF v_sine IS
-- Declare Branch Quantities
QUANTITY v ACROSS i THROUGH pos TO neg;
-- Declare Quantity for Phase in radians (calculated below)
QUANTITY phase_rad : real;
-- Declare Quantity in frequency domain for AC analysis
QUANTITY ac_spec : real SPECTRUM ac_mag, math_2_pi*ac_phase/360.0;
BEGIN
-- Convert phase to radians
phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
IF DOMAIN = QUIESCENT_DOMAIN OR DOMAIN = TIME_DOMAIN USE
v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df);
ELSE
v == ac_spec; -- used for Frequency (AC) analysis
END USE;
END ARCHITECTURE ideal;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity tb_CS5_Prop is
end tb_CS5_Prop;
architecture TB_CS5_Prop of tb_CS5_Prop is
-- Component declarations
-- Signal declarations
terminal prop : rotational_v;
terminal prop_amp_in : electrical;
terminal prop_mtr_in : electrical;
terminal prop_pwr : electrical;
signal pwm_out : std_logic;
begin
-- Signal assignments
-- Component instances
motor2 : entity work.DC_Motor(basic)
generic map(
kt => 30.1e-3,
l => 40.0e-6,
d => 5.63e-12,
j => 315.0e-6,
r_wind => 0.16
)
port map(
p1 => prop_mtr_in,
p2 => ELECTRICAL_REF,
shaft_rotv => prop
);
v4 : entity work.v_constant(ideal)
generic map(
level => 42.0
)
port map(
pos => prop_pwr,
neg => ELECTRICAL_REF
);
sw2 : entity work.switch_dig_log
port map(
sw_state => pwm_out,
p2 => prop_mtr_in,
p1 => prop_pwr
);
pwm1 : entity work.pwm_mac
port map(
inp => prop_amp_in,
dig_out => pwm_out,
inm => ELECTRICAL_REF
);
XCMP37 : entity work.prop_pwl(ideal)
generic map(
ydata => (0.233, 0.2865, 0.347, 0.4138, 0.485, 0.563, 0.645, 0.735, 0.830, 0.93, 1.08),
xdata => (471.2, 523.6, 576.0, 628.3, 680.7, 733.0, 785.4, 837.7, 890.0, 942.5, 994.8)
)
port map(
shaft1 => prop
);
D4 : entity work.diode_pwl(simple)
generic map(
ron => 0.001,
roff => 100.0e3
)
port map(
p => ELECTRICAL_REF,
m => prop_mtr_in
);
v8 : entity work.v_sine(ideal)
generic map(
freq => 1.0,
amplitude => 2.3,
phase => 0.0,
offset => 2.3
)
port map(
pos => prop_amp_in,
neg => ELECTRICAL_REF
);
end TB_CS5_Prop;
--
|
gpl-2.0
|
1f22434c77a22291c57e4acc2e253fa2
| 0.588036 | 4.304681 | false | false | false | false |
stnolting/neo430
|
rtl/core/neo430_twi.vhd
| 1 | 14,344 |
-- #################################################################################################
-- # << NEO430 - Two Wire Serial Interface Master (I2C) >> #
-- # ********************************************************************************************* #
-- # Supports START and STOP conditions, 8 bit data + ACK/NACK transfers and clock stretching. #
-- # Supports ACKs by the master. No multi-master support and no slave mode support yet! #
-- # Interrupt: TWI_transfer_done #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
entity neo430_twi is
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0); -- data out
-- clock generator --
clkgen_en_o : out std_ulogic; -- enable clock generator
clkgen_i : in std_ulogic_vector(07 downto 0);
-- com lines --
twi_sda_io : inout std_logic; -- serial data line
twi_scl_io : inout std_logic; -- serial clock line
-- interrupt --
twi_irq_o : out std_ulogic -- transfer done IRQ
);
end neo430_twi;
architecture neo430_twi_rtl of neo430_twi is
-- IO space: module base address --
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
constant lo_abb_c : natural := index_size_f(twi_size_c); -- low address boundary bit
-- control reg bits --
constant ctrl_twi_en_c : natural := 0; -- r/w: TWI enable
constant ctrl_twi_start_c : natural := 1; -- -/w: Generate START condition
constant ctrl_twi_stop_c : natural := 2; -- -/w: Generate STOP condition
constant ctrl_twi_busy_c : natural := 3; -- r/-: Set if TWI unit is busy
constant ctrl_twi_prsc0_c : natural := 4; -- r/w: CLK prsc bit 0
constant ctrl_twi_prsc1_c : natural := 5; -- r/w: CLK prsc bit 1
constant ctrl_twi_prsc2_c : natural := 6; -- r/w: CLK prsc bit 2
constant ctrl_twi_irq_en_c : natural := 7; -- r/w: transmission done interrupt
constant ctrl_twi_mack_c : natural := 8; -- r/w: generate ACK by master for transmission
-- data register flags --
constant data_twi_ack_c : natural := 15; -- r/-: Set if ACK received
-- access control --
signal acc_en : std_ulogic; -- module access enable
signal addr : std_ulogic_vector(15 downto 0); -- access address
signal wr_en : std_ulogic; -- word write enable
signal rd_en : std_ulogic; -- read enable
-- twi clocking --
signal twi_clk : std_ulogic;
signal twi_phase_gen : std_ulogic_vector(3 downto 0);
signal twi_clk_phase : std_ulogic_vector(3 downto 0);
-- twi clock stretching --
signal twi_clk_halt : std_ulogic;
-- twi transceiver core --
signal ctrl : std_ulogic_vector(8 downto 0); -- unit's control register
signal arbiter : std_ulogic_vector(2 downto 0);
signal twi_bitcnt : std_ulogic_vector(3 downto 0);
signal twi_rtx_sreg : std_ulogic_vector(8 downto 0); -- main rx/tx shift reg
-- tri-state I/O --
signal twi_sda_i_ff0, twi_sda_i_ff1 : std_ulogic; -- sda input sync
signal twi_scl_i_ff0, twi_scl_i_ff1 : std_ulogic; -- sda input sync
signal twi_sda_i, twi_sda_o : std_ulogic;
signal twi_scl_i, twi_scl_o : std_ulogic;
begin
-- Access Control -----------------------------------------------------------
-- -----------------------------------------------------------------------------
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = twi_base_c(hi_abb_c downto lo_abb_c)) else '0';
addr <= twi_base_c(15 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 1) & '0'; -- word aligned
wr_en <= acc_en and wren_i;
rd_en <= acc_en and rden_i;
-- Write access -------------------------------------------------------------
-- -----------------------------------------------------------------------------
wr_access: process(clk_i)
begin
if rising_edge(clk_i) then
if (wr_en = '1') then
if (addr = twi_ctrl_addr_c) then
ctrl <= data_i(ctrl'left downto 0);
end if;
end if;
end if;
end process wr_access;
-- Clock Generation ---------------------------------------------------------
-- -----------------------------------------------------------------------------
-- clock generator enable --
clkgen_en_o <= ctrl(ctrl_twi_en_c);
-- main twi clock select --
twi_clk <= clkgen_i(to_integer(unsigned(ctrl(ctrl_twi_prsc2_c downto ctrl_twi_prsc0_c))));
-- generate four non-overlapping clock ticks at twi_clk/4 --
clock_phase_gen: process(clk_i)
begin
if rising_edge(clk_i) then
if (arbiter(2) = '0') or (arbiter = "100") then -- offline or idle
twi_phase_gen <= "0001"; -- make sure to start with a new phase, 0,1,2,3 stepping
elsif (twi_clk = '1') and (twi_clk_halt = '0') then -- enabled and no clock stretching detected
twi_phase_gen <= twi_phase_gen(2 downto 0) & twi_phase_gen(3); -- shift left
end if;
end if;
end process clock_phase_gen;
twi_clk_phase(0) <= twi_phase_gen(0) and twi_clk; -- first step
twi_clk_phase(1) <= twi_phase_gen(1) and twi_clk;
twi_clk_phase(2) <= twi_phase_gen(2) and twi_clk;
twi_clk_phase(3) <= twi_phase_gen(3) and twi_clk; -- last step
-- TWI transceiver ----------------------------------------------------------
-- -----------------------------------------------------------------------------
twi_rtx_unit: process(clk_i)
begin
if rising_edge(clk_i) then
-- input synchronizer & sampler --
twi_sda_i_ff0 <= twi_sda_i;
twi_sda_i_ff1 <= twi_sda_i_ff0;
twi_scl_i_ff0 <= twi_scl_i;
twi_scl_i_ff1 <= twi_scl_i_ff0;
-- defaults --
twi_irq_o <= '0';
arbiter(2) <= ctrl(ctrl_twi_en_c); -- still activated?
-- arbiter FSM --
-- TWI bus signals are set/sampled using 4 clock phases
case arbiter is
when "100" => -- IDLE: waiting for requests, bus might be still claimed by this master if no STOP condition was generated
twi_bitcnt <= (others => '0');
if (wr_en = '1') then
if (addr = twi_ctrl_addr_c) then
if (data_i(ctrl_twi_start_c) = '1') then -- issue START condition
arbiter(1 downto 0) <= "01";
elsif (data_i(ctrl_twi_stop_c) = '1') then -- issue STOP condition
arbiter(1 downto 0) <= "10";
end if;
elsif (addr = twi_rtx_addr_c) then -- start a data transmission
-- one bit extra for ack, issued by master if ctrl_twi_mack_c is set,
-- sampled from slave if ctrl_twi_mack_c is cleared
twi_rtx_sreg <= data_i(7 downto 0) & (not ctrl(ctrl_twi_mack_c));
arbiter(1 downto 0) <= "11";
end if;
end if;
when "101" => -- START: generate START condition
if (twi_clk_phase(0) = '1') then
twi_sda_o <= '1';
elsif (twi_clk_phase(1) = '1') then
twi_sda_o <= '0';
end if;
if (twi_clk_phase(0) = '1') then
twi_scl_o <= '1';
elsif (twi_clk_phase(3) = '1') then
twi_scl_o <= '0';
arbiter(1 downto 0) <= "00"; -- go back to IDLE
end if;
when "110" => -- STOP: generate STOP condition
if (twi_clk_phase(0) = '1') then
twi_sda_o <= '0';
elsif (twi_clk_phase(3) = '1') then
twi_sda_o <= '1';
arbiter(1 downto 0) <= "00"; -- go back to IDLE
end if;
if (twi_clk_phase(0) = '1') then
twi_scl_o <= '0';
elsif (twi_clk_phase(1) = '1') then
twi_scl_o <= '1';
end if;
when "111" => -- TRANSMISSION: transmission in progress
if (twi_clk_phase(0) = '1') then
twi_bitcnt <= std_ulogic_vector(unsigned(twi_bitcnt) + 1);
twi_scl_o <= '0';
twi_sda_o <= twi_rtx_sreg(8); -- MSB first
elsif (twi_clk_phase(1) = '1') then -- first half + second half of valid data strobe
twi_scl_o <= '1';
elsif (twi_clk_phase(3) = '1') then
twi_rtx_sreg <= twi_rtx_sreg(7 downto 0) & twi_sda_i_ff1; -- sample and shift left
twi_scl_o <= '0';
end if;
if (twi_bitcnt = "1010") then -- 8 data bits + 1 bit for ACK + 1 tick delay
arbiter(1 downto 0) <= "00"; -- go back to IDLE
twi_irq_o <= ctrl(ctrl_twi_irq_en_c); -- fire IRQ if enabled
end if;
when others => -- "0--" OFFLINE: TWI deactivated
twi_sda_o <= '1';
twi_scl_o <= '1';
arbiter <= ctrl(ctrl_twi_en_c) & "00"; -- stay here, go to idle when activated
end case;
end if;
end process twi_rtx_unit;
-- Clock Stretching Detector ------------------------------------------------
-- -----------------------------------------------------------------------------
clock_stretching: process(arbiter, twi_scl_o, twi_scl_i_ff1)
begin
-- clock stretching by the slave can happen at "any time"
if (arbiter(2) = '1') and -- module enabled
(twi_scl_o = '1') and -- master wants to pull scl high
(twi_scl_i_ff1 = '0') then -- but scl is pulled low by slave
twi_clk_halt <= '1';
else
twi_clk_halt <= '0';
end if;
end process clock_stretching;
-- Read access --------------------------------------------------------------
-- -----------------------------------------------------------------------------
rd_access: process(clk_i)
begin
if rising_edge(clk_i) then
data_o <= (others => '0');
if (rd_en = '1') then
if (addr = twi_ctrl_addr_c) then
data_o(ctrl_twi_en_c) <= ctrl(ctrl_twi_en_c);
data_o(ctrl_twi_prsc0_c) <= ctrl(ctrl_twi_prsc0_c);
data_o(ctrl_twi_prsc1_c) <= ctrl(ctrl_twi_prsc1_c);
data_o(ctrl_twi_prsc2_c) <= ctrl(ctrl_twi_prsc2_c);
data_o(ctrl_twi_irq_en_c) <= ctrl(ctrl_twi_irq_en_c);
data_o(ctrl_twi_busy_c) <= arbiter(1) or arbiter(0);
data_o(ctrl_twi_mack_c) <= ctrl(ctrl_twi_mack_c);
else -- twi_rtx_addr_c =>
data_o(7 downto 0) <= twi_rtx_sreg(8 downto 1);
data_o(data_twi_ack_c) <= not twi_rtx_sreg(0);
end if;
end if;
end if;
end process rd_access;
-- Tri-State Driver ---------------------------------------------------------
-- -----------------------------------------------------------------------------
-- SDA and SCL need to be of type std_logic to be correctly resolved in simulation
twi_sda_io <= '0' when (twi_sda_o = '0') else 'Z';
twi_scl_io <= '0' when (twi_scl_o = '0') else 'Z';
-- read-back --
twi_sda_i <= std_ulogic(twi_sda_io);
twi_scl_i <= std_ulogic(twi_scl_io);
end neo430_twi_rtl;
|
bsd-3-clause
|
6bfd0f8c3dbee8c280d502729191d551
| 0.482641 | 3.947166 | false | false | false | false |
stnolting/neo430
|
rtl/core/neo430_wb_interface.vhd
| 1 | 9,138 |
-- #################################################################################################
-- # << NEO430 - 32-bit Wishbone Bus Interface Adapter >> #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
entity neo430_wb_interface is
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0); -- data out
-- wishbone interface --
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
wb_we_o : out std_ulogic; -- read/write
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
wb_stb_o : out std_ulogic; -- strobe
wb_cyc_o : out std_ulogic; -- valid cycle
wb_ack_i : in std_ulogic -- transfer acknowledge
);
end neo430_wb_interface;
architecture neo430_wb_interface_rtl of neo430_wb_interface is
-- IO space: module base address --
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
constant lo_abb_c : natural := index_size_f(wb32_size_c); -- low address boundary bit
-- control reg bits --
constant ctrl_byte_en0_c : natural := 0; -- -/w: wishbone data byte enable bit 0
constant ctrl_byte_en1_c : natural := 1; -- -/w: wishbone data byte enable bit 1
constant ctrl_byte_en2_c : natural := 2; -- -/w: wishbone data byte enable bit 2
constant ctrl_byte_en3_c : natural := 3; -- -/w: wishbone data byte enable bit 3
constant ctrl_pending_c : natural := 15; -- r/-: pending wb transfer
-- access control --
signal acc_en : std_ulogic; -- module access enable
signal addr : std_ulogic_vector(15 downto 0); -- access address
signal wr_en : std_ulogic;
-- accessible regs --
signal wb_addr : std_ulogic_vector(31 downto 0);
signal wb_rdata : std_ulogic_vector(31 downto 0);
signal wb_wdata : std_ulogic_vector(31 downto 0);
signal pending : std_ulogic; -- pending transfer?
signal byte_en : std_ulogic_vector(03 downto 0);
-- misc --
signal enable : std_ulogic;
begin
-- Access control -----------------------------------------------------------
-- -----------------------------------------------------------------------------
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = wb32_base_c(hi_abb_c downto lo_abb_c)) else '0';
addr <= wb32_base_c(15 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 1) & '0'; -- word aligned
wr_en <= acc_en and wren_i;
-- Write access -------------------------------------------------------------
-- -----------------------------------------------------------------------------
wr_access: process(clk_i)
begin
if rising_edge(clk_i) then
if (wr_en = '1') then -- valid word write
if (addr = wb32_rd_adr_lo_addr_c) then
wb_addr(15 downto 0) <= data_i;
wb_we_o <= '0';
end if;
if (addr = wb32_rd_adr_hi_addr_c) then
wb_addr(31 downto 16) <= data_i;
wb_we_o <= '0';
end if;
if (addr = wb32_wr_adr_lo_addr_c) then
wb_addr(15 downto 0) <= data_i;
wb_we_o <= '1';
end if;
if (addr = wb32_wr_adr_hi_addr_c) then
wb_addr(31 downto 16) <= data_i;
wb_we_o <= '1';
end if;
if (addr = wb32_data_lo_addr_c) then
wb_wdata(15 downto 0) <= data_i;
end if;
if (addr = wb32_data_hi_addr_c) then
wb_wdata(31 downto 16) <= data_i;
end if;
if (addr = wb32_ctrl_addr_c) then
byte_en(0) <= data_i(ctrl_byte_en0_c);
byte_en(1) <= data_i(ctrl_byte_en1_c);
byte_en(2) <= data_i(ctrl_byte_en2_c);
byte_en(3) <= data_i(ctrl_byte_en3_c);
end if;
end if;
end if;
end process wr_access;
-- direct output --
wb_adr_o <= wb_addr; -- address
wb_dat_o <= wb_wdata; -- write data
wb_sel_o <= byte_en; -- byte enable
-- Access arbiter -------------------------------------------------------------
-- -----------------------------------------------------------------------------
arbiter: process(clk_i)
begin
if rising_edge(clk_i) then
-- trigger transfer --
if (pending = '0') or (enable = '0') then
wb_stb_o <= '0';
pending <= '0';
if (wr_en = '1') and (enable = '1') and ((addr_i = wb32_rd_adr_hi_addr_c) or (addr_i = wb32_wr_adr_hi_addr_c)) then
wb_stb_o <= '1';
pending <= '1';
end if;
else -- transfer in progress
wb_stb_o <= '0'; -- use ONLY standard/classic cycle with single-cycle STB assertion!!
-- waiting for ACK
if (wb_ack_i = '1') then
wb_rdata <= wb_dat_i; -- sample input data
wb_stb_o <= '0';
pending <= '0';
end if;
end if;
end if;
end process arbiter;
-- device actually in use? --
enable <= or_all_f(byte_en);
-- valid cycle signal --
wb_cyc_o <= pending;
-- Read access --------------------------------------------------------------
-- -----------------------------------------------------------------------------
rd_access: process(clk_i)
begin
if rising_edge(clk_i) then
data_o <= (others => '0');
if (rden_i = '1') and (acc_en = '1') then
if (addr = wb32_data_lo_addr_c) then
data_o <= wb_rdata(15 downto 00);
elsif (addr = wb32_data_hi_addr_c) then
data_o <= wb_rdata(31 downto 16);
else -- when wb32_ctrl_addr_c =>
data_o(ctrl_pending_c) <= pending;
end if;
end if;
end if;
end process rd_access;
end neo430_wb_interface_rtl;
|
bsd-3-clause
|
6ae8245253cf6eabdf5770749051a724
| 0.471547 | 4.151749 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_16.vhd
| 4 | 1,652 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_16.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_05_16 is
end entity ch_05_16;
----------------------------------------------------------------
architecture test of ch_05_16 is
constant Tpd_01 : time := 800 ps;
constant Tpd_10 : time := 500 ps;
signal a, z : bit;
begin
-- code from book:
asym_delay : z <= transport a after Tpd_01 when a = '1' else
a after Tpd_10;
-- end of code from book
----------------
stimulus : process is
begin
a <= '1' after 2000 ps,
'0' after 4000 ps,
'1' after 6000 ps,
'0' after 6200 ps;
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
cd7d320f25de5ca9da94374c57b65630
| 0.572639 | 4.109453 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/bug17127/bug2.vhdl
| 3 | 809 |
library ieee;
use ieee.std_logic_1164.all;
entity bug2 is
end;
architecture this of bug2 is
function f return integer is
constant cc1: std_logic_vector := "1100";
constant cc2: std_logic_vector := cc1;
variable r: std_logic_vector(3 downto 0);
begin
assert false report "case2-a: "&integer'image(cc1'length) severity note;
assert false report "case2-b: "&integer'image(cc2'length) severity note;--This reports "0". Correct one would be "4"!
return 0;
end;
constant c1: std_logic_vector := "1010";
constant c2: std_logic_vector := c1;
signal i: integer;
begin
process
begin
assert false report "case1-a: "&integer'image(c1'length) severity note;
assert false report "case1-b: "&integer'image(c2'length) severity note;
i <= f;
wait;
end process;
end;
|
gpl-2.0
|
dd55195483211402f152fd0a406f76bd
| 0.686032 | 3.236 | false | false | false | false |
velentr/foundry.vhdl
|
uart-tb.vhd
| 1 | 9,350 |
--
-- uart-tb.vhd
--
-- Test Bench for UART transmitter and receiver.
--
-- This is not an exhaustive testbench; it simply puts data into the UART
-- transmitter, and checks that the same data comes out the other side from the
-- receiver.
--
-- Revision History:
-- 24 Apr 2015 Brian Kubisiak Initial revision.
--
library ieee;
use ieee.std_logic_1164.all;
-- Our testbench entity has no ports; it is completely self-contained.
entity uart_tb is
end uart_tb;
architecture TB_ARCHITECTURE of uart_tb is
--
-- uarttx
--
-- This component is one of the units-under-test. It is an asynchronous
-- transmitter for the UART design. It takes in data on the parallel input
-- (along with a signal telling it to start transmitting), and outputs the data
-- serially.
--
-- Parameters:
-- N (integer) Number of bits per character.
--
-- Inputs:
-- reset (std_logic) Active-low line to reset the UART transmitter.
-- clk (std_logic) Baud rate clock. The UART will transmit one bit
-- on every rising edge of the clock.
-- data (std_logic_vector) Next character to send over the UART.
-- rdy (std_logic) Active-low line indicating that data is ready to
-- transmit. It should be sent low for at least one
-- baud.
--
-- Outputs:
-- tx (std_logic) Transmit line for transmitting the serial data.
-- ack (std_logic) Active-low signal acknowledging the ready data,
-- indicating that the new data will now be
-- transmitted.
--
component uarttx is
generic ( N : integer := 8 );
port
(
reset : in std_logic; -- Reset the UART
clk : in std_logic; -- Baud clock
data : in std_logic_vector(N-1 downto 0); -- Parallel data out
rdy : in std_logic; -- New data ready
ack : out std_logic; -- Ack data ready
tx : out std_logic -- Serial data input
);
end component;
--
-- uartrx
--
-- This component is the unit-under-test. It is an asynchronous receiver for
-- the UART design. It takes in serial data at the baud rate determined by the
-- clock, and outputs the data in parallel.
--
-- Parameters:
-- N (integer) Number of bits per character.
--
-- Inputs:
-- reset (std_logic) Active-low line to reset the UART receiver.
-- clk (std_logic) Baud rate clock. The UART will sample the input
-- signal on every rising edge of the clock.
-- rx (std_logic) Receive line carrying the serial data.
--
-- Outputs:
-- data (std_logic_vector) Last character received over the UART.
-- rdy (std_logic) Active-low line indicating when the data is
-- ready. Once a character is received, this will
-- pulse low for one clock.
-- err (std_logic) Active-low signal indicating an error occurred.
-- Currently, this means that the stop bit was not
-- high.
component uartrx is
generic ( N : integer := 8 );
port (
reset : in std_logic; -- Reset the UART
clk : in std_logic; -- Baud clock
rx : in std_logic; -- Serial data in
data : out std_logic_vector(N-1 downto 0); -- Parallel data out
rdy : out std_logic; -- New data ready
err : out std_logic -- Error occurred
);
end component;
-- Stimulus signals - signals mapped to the input ports of tested entity
signal clk : std_logic; -- System clock
signal reset : std_logic; -- Reset UART
signal data_tx : std_logic_vector(7 downto 0); -- Data to send
signal rdy_tx : std_logic; -- Data input should be sent
-- Outputs - signals that are checked against the expected outputs of the
-- test bench.
signal ack : std_logic; -- New data is being transmitted
signal data_rx : std_logic_vector(7 downto 0); -- Received data
signal rdy_rx : std_logic; -- New data has been received
signal err : std_logic; -- Error ocurred during transmission
-- Line for transferring data between the transmitter and receiver.
signal transmit : std_logic;
-- Indicates that the simulation has finished
signal END_SIM : boolean := FALSE;
-- Type for holding the test vectors. We need this because VHDL doesn't like
-- declaring an array of std_logic_vector without a new type.
type DataVec is array (0 to 5) of std_logic_vector(7 downto 0);
-- We should see the following data output from the UART:
constant test_vec: DataVec := ("11010111", "11111111", "00000000",
"10101010", "00001111", "11110000");
begin
-- Declare the units-under-test and wire up all its inputs to stimulus
-- signals and outputs to tested signals.
UUT_rx: uartrx
generic map ( N => 8 )
port map (
-- Map inputs to stimulus signals:
clk => clk,
reset => reset,
-- Line for transferring the data:
rx => transmit,
-- Map outputs to tested signals:
data => data_rx,
rdy => rdy_rx,
err => err
);
UUT_tx: uarttx
generic map ( N => 8 )
port map (
-- Map inputs to stimulus signals:
reset => reset,
clk => clk,
data => data_tx,
rdy => rdy_tx,
-- Line for transferring the data:
tx => transmit,
-- Map outputs to tested signals:
ack => ack
);
-- Send data into the transmitter. This will test transmitting a burst as
-- well as transmitting isolated characters.
TxData: process
begin
-- Reset the UART
reset <= '0';
-- Start without transmitting data
rdy_tx <= '1';
-- Wait a clock for it to completely reset
wait until clk = '1';
wait until clk = '0';
-- Transmitter should be transmitting stop bits now, we can stop
-- resetting
reset <= '1';
-- Transmit the first 4 characters in quick succession
for i in 0 to 3 loop
-- Start transmitting data.
data_tx <= test_vec(i);
rdy_tx <= '0';
-- Once the transfer is acknowledged, go on to the next vector
wait until ack = '0';
end loop;
-- Done transmitting for a little bit.
rdy_tx <= '1';
for i in 4 to 5 loop
-- Wait for a long time for a break between transmissions
wait for 500 ns;
-- Start the next transmission.
data_tx <= test_vec(i);
rdy_tx <= '0';
-- Wait for acknowledgement before continuing
wait until ack = '0';
rdy_tx <= '1';
end loop;
-- Finished transmitting all data; just wait here.
wait;
end process;
-- Check the data on the receiver, making sure that it is the same as the
-- transmitted data.
RxData: process
begin
for i in 0 to 5 loop
-- Wait until a new character is received.
wait until rdy_rx = '0';
-- Check data on the next rising edge of the clock.
wait until (clk'event and clk = '1');
assert (data_rx = test_vec(i))
report "Incorrect data received."
severity ERROR;
-- Now wait for the ready signal to clear.
wait until rdy_rx = '1';
end loop;
-- Notify once all tests have passed.
assert (FALSE) report "All tests completed." severity NOTE;
-- Simulation is over once all the outputs have been tested.
END_SIM <= TRUE;
wait;
end process;
-- Check to make sure that the error signal is never asserted.
CheckErr: process(err)
begin
-- Make sure that the error signal isn't asserted.
assert (err = '1')
report "Error found on receiver."
severity ERROR;
end process;
-- This process will generate a clock with a 20 ns period and a 50% duty
-- cycle. Once the end of the simulation has been reached (END_SIM = TRUE),
-- then the clock will stop oscillating.
GenClock: process
begin
-- this process generates a 20 ns 50% duty cycle clock
-- stop the clock when the end of the simulation is reached
if END_SIM = FALSE then
clk <= '0';
wait for 10 ns;
else
wait;
end if;
if END_SIM = FALSE then
clk <= '1';
wait for 10 ns;
else
wait;
end if;
end process;
end TB_ARCHITECTURE;
|
mit
|
dbe9a2083561e3d0929656487b2e4fb2
| 0.542567 | 4.497354 | false | true | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_Multiplication/serialMul/serial_multiplier_113_2.vhd
| 1 | 4,090 |
----------------------------------------------------------------------------------------------------
-- serial_multiplier.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Serial multiplier for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: The input buses need to have valid data when Reset signal is asserted
-- FSM are not used.
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--------------------------------------------------------
entity serial_multiplier_113 is
generic (
NUM_BITS : positive := 113 -- The order of the finite field
);
port(
ax : in std_logic_vector(NUM_BITS-1 downto 0);
bx : in std_logic_vector(NUM_BITS-1 downto 0);
cx : out std_logic_vector(NUM_BITS-1 downto 0); -- cx = ax*bx mod Fx
reset : in std_logic;
clk : in std_logic;
done : out std_logic
);
end serial_multiplier_113;
-----------------------------------------------------------
architecture behave of serial_multiplier_113 is
-----------------------------------------------------------
-- m = 113 x113 + x9 + 1
constant Fx: std_logic_vector(NUM_BITS-1 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000001";
-----------------------------------------------------------
signal Op1 : std_logic_vector(NUM_BITS-1 downto 0); -- Multiplexers for ax and cx depending upon b_i and c_m
signal Op2 : std_logic_vector(NUM_BITS-1 downto 0);
signal bx_shift : std_logic_vector(NUM_BITS-1 downto 0); -- B and C shifted one position to the rigth
signal cx_shift : std_logic_vector(NUM_BITS-1 downto 0);
signal bx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal cx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal counter: std_logic_vector(7 downto 0); -- 8-bit counter, controling the number of iterations: m
signal done_int : std_logic;
begin
-----------------------------------------------------------
cx <= cx_int; -- Result of the multiplication
Bx_shift <= bx_int(NUM_BITS-2 downto 0)& '0'; -- Shift Bx and Cx to left one position
Cx_shift <= cx_int(NUM_BITS-2 downto 0)& '0';
-- Multiplexer to determine what value is added to C_x in each iteration
Op1 <= ax when bx_int(NUM_BITS-1) = '1' else -- The selector for these multiplexors are the most significant bits of B_x and C_x
(others => '0');
Op2 <= Fx when cx_int(NUM_BITS-1) = '1' else
(others => '0');
done <= done_int;
------------------------------------------------------------
-- The finite state machine, it takes m cycles to compute
-- the multiplication, a counter is used to keep this count
------------------------------------------------------------
FSM_MUL: process (CLK)
Begin
if CLK'event and CLK = '1' then
if Reset = '1' then
counter <= "01110000"; -- m-1 value, in this case, it is 162, be sure to set the correct value
bx_int <= bx;
cx_int <= (others => '0');
Done_int <= '0';
else
if done_int = '0' then
Cx_int <= cx_shift xor Op1 xor Op2;
counter <= counter - 1;
bx_int <= bx_shift;
if counter = "00000000" then -- The done signal is asserted at the same time that the result is computed.
Done_int <= '1';
end if;
end if;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
83671216a568457a840a4d40d5a65d3a
| 0.489731 | 4.065606 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_08.vhd
| 4 | 3,648 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ap_a_ap_a_08.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity entname is
end entity entname;
architecture rtl of entname is
-- code from book
subtype state_type is std_ulogic_vector(3 downto 0);
constant s0 : state_type := "0001";
constant s1 : state_type := "0010";
constant s2 : state_type := "0100";
constant s3 : state_type := "1000";
-- end code from book
signal state, next_state : state_type;
signal con1, con2, con3 : std_ulogic;
signal out1, out2 : std_ulogic;
signal clk, reset : std_ulogic;
begin
state_logic : process (state, con1, con2, con3) is
begin
case state is
when s0 =>
out1 <= '0';
out2 <= '0';
next_state <= s1;
when s1 =>
out1 <= '1';
if con1 = '1' then
next_state <= s2;
else
next_state <= s1;
end if;
when s2 =>
out2 <= '1';
next_state <= s3;
when s3 =>
if con2 = '0' then
next_state <= s3;
elsif con3 = '0' then
out1 <= '0';
next_state <= s2;
else
next_state <= s1;
end if;
when others =>
null;
end case;
end process state_logic;
state_register : process (clk, reset) is
begin
if reset = '0' then
state <= s0;
elsif rising_edge(clk) then
state <= next_state;
end if;
end process state_register;
clk_gen : process is
begin
clk <= '0', '1' after 10 ns;
wait for 20 ns;
end process clk_gen;
reset <= '0', '1' after 40 ns;
con1 <= '0', '1' after 100 ns, '0' after 120 ns;
con2 <= '0', '1' after 160 ns;
con3 <= '0', '1' after 220 ns;
end architecture rtl;
|
gpl-2.0
|
a34e02d19975f9cc5fd9c153a1424dcd
| 0.421875 | 4.857523 | false | false | false | false |
bmikaili/TUM-ERA-Praktikum-SS17-Gruppe-45
|
Projekt2/Implementierung/stp_tb.vhdl
| 1 | 12,597 |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
-----------------------------------
--------------ENTITY---------------
-----------------------------------
entity audiostp_tb is
end audiostp_tb;
architecture test of audiostp_tb is
component audiostp
port (
sclk, fsync, sdata : in std_logic; -- Eingänge definieren
left, right : out signed (17 downto 0); -- 18 Bit Ausgabewerte
flag : out std_logic -- 1 Bit Ausgabeflag
);
end component;
signal sclk, fsync, sdata, flag: std_logic;
signal left, right: signed (17 downto 0);
begin
audioconverter: audiostp port map (sclk => sclk, fsync => fsync, sdata => sdata, flag => flag, left => left, right => right);
process begin
sclk <= 'X';
fsync <= 'X';
sdata <= 'X';
wait for 1 ns;
sclk <= '1';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '1';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '1';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '1';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '1';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '1';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '1';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '1';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '1';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '1';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '1';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '1';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '1';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '1';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '1';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '1';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '1';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '1';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '1';
fsync <= '1';
sdata <= '1';
wait for 1 ns;
sclk <= '0';
fsync <= '1';
sdata <= '1';
wait for 1 ns;
sclk <= '1';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '1';
sdata <= '1';
wait for 1 ns;
sclk <= '1';
fsync <= '1';
sdata <= '1';
wait for 1 ns;
sclk <= '0';
fsync <= '1';
sdata <= '1';
wait for 1 ns;
sclk <= '1';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '1';
fsync <= '1';
sdata <= '1';
wait for 1 ns;
sclk <= '0';
fsync <= '1';
sdata <= '1';
wait for 1 ns;
sclk <= '1';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '1';
fsync <= '1';
sdata <= '1';
wait for 1 ns;
sclk <= '0';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '1';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '1';
fsync <= '1';
sdata <= '1';
wait for 1 ns;
sclk <= '0';
fsync <= '1';
sdata <= '1';
wait for 1 ns;
sclk <= '1';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '1';
fsync <= '1';
sdata <= '1';
wait for 1 ns;
sclk <= '0';
fsync <= '1';
sdata <= '1';
wait for 1 ns;
sclk <= '1';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '1';
fsync <= '1';
sdata <= '1';
wait for 1 ns;
sclk <= '0';
fsync <= '1';
sdata <= '1';
wait for 1 ns;
sclk <= '1';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '1';
fsync <= '1';
sdata <= '1';
wait for 1 ns;
sclk <= '0';
fsync <= '1';
sdata <= '1';
wait for 1 ns;
sclk <= '1';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '1';
fsync <= '1';
sdata <= '1';
wait for 1 ns;
sclk <= '0';
fsync <= '1';
sdata <= '1';
wait for 1 ns;
sclk <= '1';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
------------------------
sclk <= '1';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '1';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '1';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '1';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '1';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '1';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '1';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '1';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '1';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '1';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '1';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '1';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '1';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '1';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '1';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '1';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '1';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '1';
wait for 1 ns;
sclk <= '1';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '0';
sdata <= '0';
wait for 1 ns;
sclk <= '1';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '1';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '1';
sdata <= '1';
wait for 1 ns;
sclk <= '1';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '1';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '1';
fsync <= '1';
sdata <= '1';
wait for 1 ns;
sclk <= '0';
fsync <= '1';
sdata <= '1';
wait for 1 ns;
sclk <= '1';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '1';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '1';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '1';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '1';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '1';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '1';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '1';
fsync <= '1';
sdata <= '1';
wait for 1 ns;
sclk <= '0';
fsync <= '1';
sdata <= '1';
wait for 1 ns;
sclk <= '1';
fsync <= '1';
sdata <= '1';
wait for 1 ns;
sclk <= '0';
fsync <= '1';
sdata <= '1';
wait for 1 ns;
sclk <= '1';
fsync <= '1';
sdata <= '1';
wait for 1 ns;
sclk <= '0';
fsync <= '1';
sdata <= '1';
wait for 1 ns;
sclk <= '1';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '1';
fsync <= '1';
sdata <= '1';
wait for 1 ns;
sclk <= '0';
fsync <= '1';
sdata <= '1';
wait for 1 ns;
sclk <= '1';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
sclk <= '0';
fsync <= '1';
sdata <= '0';
wait for 1 ns;
wait;
end process;
end test;
|
gpl-3.0
|
d00345ecb352b45341850ce22db2da26
| 0.391712 | 2.583795 | false | false | false | false |
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_divider/Shantz/SingleFile/f2m_divider_283.vhd
| 1 | 8,901 |
---------------------------------------------------------------------------------------------------
-- divider_f2m.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Inverter for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: This is an implementation of the division algorithm. Dirent to the other implemented inverter
-- in this, the division is performed directly.
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity f2m_divider_283 is
generic(
NUM_BITS : positive := 283
);
port(
x : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
y : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
done : out STD_LOGIC;
Ux : out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of f2m_divider_283 is
----------------------------------------------------------------------------------------------------
-- Signal for up-date regsiters A and B
signal A,B : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal U, V : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
----------------------------------------------------------------------------------------------------
-- m = 163, the irreductible polynomial
--constant F : std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001001";
-- m = 233 x233 + x74 + 1
--constant F: std_logic_vector(NUM_BITS downto 0) := "100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000001";
-- m = 277 x277 + x74 + 1
--constant F: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000001001001"; --277 bits
-- m = 283 x283 + x12 + x7 + x5 + 1
constant F: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000010100001";
-- m = 409 x409 + x87 + 1
--constant F: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
-- m = 571 x571 + x10 + x5 + x2 + 1
--constant F: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000100101";
----------------------------------------------------------------------------------------------------
-- control signals
signal a_greater_b, a_eq_b, A_par, B_par, U_par, V_par: std_logic;
signal A_div_t, B_div_t, U_div_t, V_div_t : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal u_mas_M, v_mas_M, u_mas_v, u_mas_v_mas_M, a_mas_b : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal u_mas_M_div_t, v_mas_M_div_t, u_mas_v_div_t, u_mas_v_mas_M_div_t, a_mas_b_div_t: STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
----------------------------------------------------------------------------------------------------------------------------------------------------------
type CurrentState_type is (END_STATE, CYCLE);
signal currentState: CurrentState_type;
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- Control signals
A_par <= '1' when A(0) = '0' else
'0';
B_par <= '1' when B(0) = '0' else
'0';
U_par <= '1' when U(0) = '0' else
'0';
V_par <= '1' when V(0) = '0' else
'0';
a_greater_b <= '1' when A > B else
'0';
a_eq_b <= '1' when A = B else
'0';
----------------------------------------------------------------------------------------------------
-- Mux definitions
----------------------------------------------------------------------------------------------------
u_mas_M <= U xor F;
v_mas_M <= V xor F;
u_mas_v <= U xor V;
u_mas_v_mas_M <= u_mas_v xor F;
a_mas_b <= A xor B;
-- Muxes for A and B
a_div_t <= '0'& A(NUM_BITS downto 1);
b_div_t <= '0'& B(NUM_BITS downto 1);
u_div_t <= '0'& U(NUM_BITS downto 1);
v_div_t <= '0'& V(NUM_BITS downto 1);
u_mas_M_div_t <= '0' & u_mas_M(NUM_BITS downto 1);
v_mas_M_div_t <= '0' & v_mas_M(NUM_BITS downto 1);
u_mas_v_div_t <= '0' & u_mas_v(NUM_BITS downto 1);
u_mas_v_mas_M_div_t <= '0' & u_mas_v_mas_M(NUM_BITS downto 1);
a_mas_b_div_t <= '0' & a_mas_b(NUM_BITS downto 1);
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
EEAL: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if (rst = '1')then
A <= '0' & y;
B <= F;
U <= '0' & x;
v <= (others => '0');
Ux <= (others => '0');
done <= '0';
currentState <= CYCLE;
else
case currentState is
-----------------------------------------------------------------------------------
when CYCLE =>
if A_eq_B = '1' then
currentState <= END_STATE;
Done <= '1';
Ux <= U(NUM_BITS-1 downto 0);
elsif A_par = '1' then
A <= A_div_t;
if U_par = '1' then
U <= U_div_t;
else
U <= u_mas_M_div_t;
end if;
elsif B_par = '1' then
B <= B_div_t;
if V_par = '1' then
V <= V_div_t;
else
V <= V_mas_M_div_t;
end if;
elsif a_greater_b = '1' then
A <= a_mas_b_div_t;
if u_mas_v(0) = '0' then
U <= u_mas_v_div_t;
else
U <= u_mas_v_mas_M_div_t;
end if;
else
B <= a_mas_b_div_t;
if u_mas_v(0) = '0' then
V <= u_mas_v_div_t;
else
V <= u_mas_v_mas_M_div_t;
end if;
end if;
-----------------------------------------------------------------------------------
when END_STATE => -- Do nothing
currentState <= END_STATE;
done <= '0'; -- para generar el pulso, quitarlo entity caso contrario
-----------------------------------------------------------------------------------
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
f2ba36f815ae5eab3ef0d3503b60faae
| 0.49882 | 4.788058 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/network_driver.vhd
| 4 | 2,117 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity network_driver is
end entity network_driver;
architecture test of network_driver is
constant target_host_id : natural := 10;
constant my_host_id : natural := 5;
type pkt_types is (control_pkt, other_pkt);
type pkt_header is record
dest, src : natural;
pkt_type : pkt_types;
seq : natural;
end record;
begin
-- code from book
network_driver : process is
constant seq_modulo : natural := 2**5;
subtype seq_number is natural range 0 to seq_modulo-1;
variable next_seq_number : seq_number := 0;
-- . . .
-- not in book
variable new_header : pkt_header;
-- end not in book
impure function generate_seq_number return seq_number is
variable number : seq_number;
begin
number := next_seq_number;
next_seq_number := (next_seq_number + 1) mod seq_modulo;
return number;
end function generate_seq_number;
begin -- network_driver
-- not in book
wait for 10 ns;
-- end not in book
-- . . .
new_header := pkt_header'( dest => target_host_id,
src => my_host_id,
pkt_type => control_pkt,
seq => generate_seq_number );
-- . . .
end process network_driver;
-- end code from book
end architecture test;
|
gpl-2.0
|
ccc641eac9882bd97f977c376150fc05
| 0.647142 | 4.032381 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc876.vhd
| 4 | 2,272 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc876.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c01s03b02x00p02n01i00876ent_a is
port ( ia, ib : bit;
oc, od : out bit) ;
end c01s03b02x00p02n01i00876ent_a;
architecture c01s03b02x00p02n01i00876arch_a of c01s03b02x00p02n01i00876ent_a is
begin
A1_BLK : block
signal S : INTEGER;
begin
S <= 1;
end block;
end c01s03b02x00p02n01i00876arch_a;
ENTITY c01s03b02x00p02n01i00876ent IS
port ( P3 : out bit;
P4 : out bit) ;
END c01s03b02x00p02n01i00876ent;
ARCHITECTURE c01s03b02x00p02n01i00876arch OF c01s03b02x00p02n01i00876ent IS
BEGIN
BB : block
signal S1 : bit;
signal S2 : bit;
component LOCAL port( CI, I2 : in BIT;
CO, RES :out BIT);
end component ;
for all : LOCAL
use entity work.c01s03b02x00p02n01i00876ent_a (c01s03b02x00p02n01i00876arch_a)
port map (ia => CI, ib => I2, oc => CO, od => RES);
begin
L : LOCAL
port map (CI =>S1 , I2 =>S2 , CO=>P3 , RES =>P4 );
assert FALSE
report "***PASSED TEST: c01s03b02x00p02n01i00876"
severity NOTE;
end block BB;
END c01s03b02x00p02n01i00876arch;
|
gpl-2.0
|
fbc03ec8c3beeec220c6712264337bea
| 0.647007 | 3.241084 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/CPU.vhd
| 4 | 1,636 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package cell_attributes is
type length is range 0 to integer'high
units nm;
um = 1000 nm;
mm = 1000 um;
mil = 25400 nm;
end units length;
type coordinate is record
x, y : length;
end record coordinate;
attribute cell_position : coordinate;
end package cell_attributes;
entity CPU is
end entity CPU;
-- code from book
architecture cell_based of CPU is
component fpu is
port ( -- . . . );
-- not in book
port_name : bit := '0' );
-- end not in book
end component;
use work.cell_attributes.all;
attribute cell_position of the_fpu : label is ( 540 um, 1200 um );
-- . . .
begin
the_fpu : component fpu
port map ( -- . . . );
-- not in book
port_name => open );
-- end not in book
-- . . .
end architecture cell_based;
-- end code from book
|
gpl-2.0
|
e69cceac172db8dcc864ce35f66a83e9
| 0.669315 | 3.932692 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc2903.vhd
| 4 | 2,258 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2903.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x01p02n02i02903ent IS
END c02s01b01x01p02n02i02903ent;
ARCHITECTURE c02s01b01x01p02n02i02903arch OF c02s01b01x01p02n02i02903ent IS
type t1 is (one,two,three);
signal s1 : t1;
constant c1 : integer:=65;
procedure proc1(variable vv1:inout real; signal ss1:inout t1) is
begin
assert (vv1=43.1)
report "Variables of mode inout for procedures are not copied properly"
severity failure;
assert (ss1=two)
report "Signals of mode inout for procedures are not copied properly"
severity failure;
assert NOT( vv1=43.1 and ss1=two )
report "***PASSED TEST: c02s01b01x01p02n02i02903"
severity NOTE;
assert ( vv1=43.1 and ss1=two )
report "***FAILED TEST: c02s01b01x01p02n02i02903 - Values of actual parameters of mode inout are not copied into their associated formal parameter."
severity ERROR;
end proc1;
BEGIN
TESTING: PROCESS
variable v1:real;
BEGIN
s1<=two;
v1:=43.1;
wait for 5 ns;
proc1(v1,s1);
wait;
END PROCESS TESTING;
END c02s01b01x01p02n02i02903arch;
|
gpl-2.0
|
1de200a01a5639b30dd8a03748fca7b7
| 0.672719 | 3.630225 | false | true | false | false |
peteut/ghdl
|
testsuite/gna/bug16782/bug.vhd
| 3 | 1,277 |
entity bug is end entity;
architecture arch of bug is
component comp is port(a :in bit_vector); end component;
constant DATAPATH :natural := 16;
signal a :bit_vector(DATAPATH-1 downto 0);
begin
i_comp: comp port map(a);
end architecture;
entity comp is port(a :in bit_vector); end entity;
architecture arch of comp is
constant DATAPATH :natural := a'length;
signal state :natural;
signal tmp :bit_vector(31 downto 0);
begin
process(a) begin
case DATAPATH is
when 8=>
case state is
when 0=> tmp(1*DATAPATH-1 downto 0*DATAPATH)<=a;
when 1=> tmp(2*DATAPATH-1 downto 1*DATAPATH)<=a;
-- When DATAPATH>10 this range violates bounds, but this code should not be reached because "case DATAPATH is when 8=>"
when 2=> tmp(3*DATAPATH-1 downto 2*DATAPATH)<=a;
when 3=> tmp(4*DATAPATH-1 downto 3*DATAPATH)<=a;
when others=>
end case;
when 16=>
case state is
when 0=> tmp(1*DATAPATH-1 downto 0*DATAPATH)<=a;
when 1=> tmp(2*DATAPATH-1 downto 1*DATAPATH)<=a;
when others=>
end case;
when others=>
end case;
end process;
end architecture;
|
gpl-2.0
|
2306ee21a44cf415f4953ae0f10ebe4e
| 0.589663 | 4.053968 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc140.vhd
| 4 | 2,170 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc140.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x02p09n01i00140ent IS
PORT ( SIGNAL a : IN bit;
SIGNAL b : IN integer;
SIGNAL c : IN boolean;
SIGNAL d : IN time;
SIGNAL e : IN real;
SIGNAL oint : INOUT integer);
END c04s03b02x02p09n01i00140ent;
ARCHITECTURE c04s03b02x02p09n01i00140arch OF c04s03b02x02p09n01i00140ent IS
function funct1( fpar1:bit :='1';
fpar2:integer :=455;
fpar3:boolean :=true;
fpar4:time :=55.77 ns;
fpar5:real :=34.558) return integer is
begin
return 1;
end funct1;
BEGIN
TESTING: PROCESS
BEGIN
wait for 1 ns;
oint <= funct1(fpar3=>c,fpar2=>b,fpar1=>a,fpar4=>d,nosuch=>e);
assert FALSE
report "***FAILED TEST: c04s03b02x02p09n01i00140 - Named association parameter where name is not in formal parameter list."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p09n01i00140arch;
|
gpl-2.0
|
34536d7785c047a6c34c00c1aabe2536
| 0.622581 | 3.80035 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1100.vhd
| 4 | 2,071 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1100.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p03n01i01100ent IS
END c06s05b00x00p03n01i01100ent;
ARCHITECTURE c06s05b00x00p03n01i01100arch OF c06s05b00x00p03n01i01100ent IS
BEGIN
TESTING: PROCESS
subtype FIVE is INTEGER range 1 to 5;
subtype THREE is INTEGER range 1 to 3;
subtype ONE is INTEGER range 1 to 1;
type A0 is array (INTEGER range <>) of BOOLEAN;
subtype A1 is A0 (FIVE);
subtype A2 is A0 (ONE);
subtype A3 is A0 (THREE);
subtype A5 is A0 (FIVE);
variable V2: A2;
variable V3: A3;
BEGIN
V3 := A5'(1=>TRUE, 2=>TRUE, 3=>TRUE, 4=>TRUE, 5=>TRUE) (2 to 4);
-- PREFIX OF SLICE NAME CANNOT BE AN AGGREGATE
assert FALSE
report "***FAILED TEST: c06s05b00x00p03n01i01100 - Prefix of a slice must be appropraite for a one-dimensional array object."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p03n01i01100arch;
|
gpl-2.0
|
84143329831e16ec519076b2e8361e97
| 0.66055 | 3.678508 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc692.vhd
| 4 | 3,120 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc692.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:04 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:38 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:43 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00692ent IS
END c03s04b01x00p23n01i00692ent;
ARCHITECTURE c03s04b01x00p23n01i00692arch OF c03s04b01x00p23n01i00692ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type FT is file of BIT;
-- Declare the actual file to read.
file FILEV : FT open read_mode is "iofile.08";
-- Declare a variable into which we will read.
constant CON : BIT := '1';
variable VAR : BIT;
variable k : integer := 0;
BEGIN
-- Read in the file.
for I in 1 to 100 loop
if (ENDFILE( FILEV ) /= FALSE) then
k := 1;
end if;
assert( (ENDFILE( FILEV ) = FALSE) )
report "Hit the end of file too soon.";
READ( FILEV,VAR );
if (VAR /= CON) then
k := 1;
end if;
end loop;
-- Verify that we are at the end.
if (ENDFILE( FILEV ) /= TRUE) then
k := 1;
end if;
assert( ENDFILE( FILEV ) = TRUE )
report "Have not reached end of file yet."
severity ERROR;
assert NOT( k = 0 )
report "***PASSED TEST: c03s04b01x00p23n01i00692"
severity NOTE;
assert( k = 0 )
report "***FAILED TEST: c03s04b01x00p23n01i00692 - The variables don't equal the constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00692arch;
|
gpl-2.0
|
dc1f854e2ad46926ed23bf29c87e48fe
| 0.542949 | 4.015444 | false | true | false | false |
herenvarno/dlx
|
dlx_vhd/src/a.b-DataPath.core/a.b.c-RegisterFile.vhd
| 1 | 3,138 |
--------------------------------------------------------------------------------
-- FILE: RegisterFile
-- DESC: Register File with 2 read port and 1 write port.
--
-- Author:
-- Create: 2015-05-27
-- Update: 2015-05-27
-- Status: TESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Consts.all;
use work.Funcs.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity RegisterFile is
generic(
DATA_SIZE : integer := C_SYS_DATA_SIZE;
REG_NUM : integer := C_REG_NUM
);
port(
clk : in std_logic; -- clock
rst : in std_logic; -- reset
en : in std_logic; -- enable
rd1_en : in std_logic; -- read port 1
rd2_en : in std_logic; -- read port 2
wr_en : in std_logic; -- write port
link_en : in std_logic; -- save link reg
rd1_addr: in std_logic_vector(MyLog2Ceil(REG_NUM)-1 downto 0):=(others=>'0'); -- address of read port 1
rd2_addr: in std_logic_vector(MyLog2Ceil(REG_NUM)-1 downto 0):=(others=>'0'); -- address of read port 2
wr_addr : in std_logic_vector(MyLog2Ceil(REG_NUM)-1 downto 0):=(others=>'0'); -- address of write port
d_out1 : out std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); -- data out 1 bus
d_out2 : out std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); -- data out 2 bus
d_in : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); -- data in bus
d_link : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0') -- link register input bus
);
end RegisterFile;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture register_file_arch of RegisterFile is
type RegArray_t is array(natural range 0 to REG_NUM-1) of std_logic_vector(DATA_SIZE-1 downto 0);
signal registers : RegArray_t;
constant ADDR_SIZE: integer:= MyLog2Ceil(REG_NUM);
signal zeros5 : std_logic_vector(MyLog2Ceil(REG_NUM)-1 downto 0):=(others=>'0');
begin
PROC: process(clk)
begin
if rst = '0' then
LO0: for i in 0 to REG_NUM-1 loop
registers(i) <= (others=>'0');
end loop;
else
if falling_edge(clk) then
if en = '1' then
if rd1_en= '1' then
if wr_en = '1' and wr_addr=rd1_addr then
d_out1 <= d_in;
else
d_out1 <= registers(to_integer(unsigned(rd1_addr)));
end if;
end if;
if rd2_en='1' then
if wr_en = '1' and wr_addr=rd2_addr then
d_out2 <= d_in;
else
d_out2 <= registers(to_integer(unsigned(rd2_addr)));
end if;
end if;
if wr_en = '1' then
if wr_addr /= zeros5 then -- Keep R0 always 0.
registers(to_integer(unsigned(wr_addr))) <= d_in;
end if;
end if;
if link_en = '1' then
registers(REG_NUM-1) <= d_link;
end if;
end if;
end if;
end if;
end process;
end register_file_arch;
|
mit
|
6ff93819b27fa55753386eb5bd944d23
| 0.514022 | 3.245088 | false | false | false | false |
siavooshpayandehazad/high_level_test_pattern_gen
|
Testbench/AP_tb - Random Pattern Generation.vhd
| 1 | 5,921 |
-- TestBench Template
LIBRARY ieee;
library std;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.all;
USE ieee.math_real.ALL;
USE std.textio.ALL;
USE work.my_package.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
-- Component Declaration
COMPONENT AP_Alu IS
PORT(
clock : IN std_logic;
rst : IN std_logic;
OP_A : IN std_logic_vector(7 downto 0);
OP_B : IN std_logic_vector(7 downto 0);
RESULT : OUT std_logic_vector(7 downto 0);
ALU_OP : IN std_logic_vector(3 downto 0)
);
END COMPONENT;
SIGNAL clock : std_logic:= '0';
SIGNAL rst : std_logic := '1';
SIGNAL OP_A : std_logic_vector(7 downto 0) := "00000000";
SIGNAL OP_B : std_logic_vector(7 downto 0) := "00000000";
SIGNAL RESULT : std_logic_vector(7 downto 0) := "00000000";
SIGNAL ALU_OP : std_logic_vector(3 downto 0) := "0000";
--SIGNAL ALU_OP1 : std_logic_vector(3 downto 0) := "0000";
--SIGNAL num_bin1 : std_logic_vector (7 downto 0);
--SIGNAL num_bin2 : std_logic_vector (7 downto 0);
--variable num_1 : std_logic_vector (7 downto 0);
--variable num_2 : std_logic_vector (7 downto 0);
--SIGNAL Header1 : string(1 to 3) := "OPC";
SIGNAL Header2 : string(1 to 4) := "OP_A";
SIGNAL Header3 : string(1 to 4) := "OP_B";
SIGNAL Header4 : string(1 to 6) := "RESULT";
CONSTANT clk_period : time := 10 ns;
-- procedure my_proc is trying to create procedure for header
--begin
--end procedure my_proc;
BEGIN
-- Component Instantiation
uut: AP_Alu PORT MAP(
clock => clock,
rst=> rst,
OP_A=> OP_A,
OP_B=> OP_B,
ALU_OP=> ALU_OP,
RESULT=> RESULT
);
-- Test Bench Statements
--clock <= not clock after 50 ns;
rst <= '0' after 1 ns;
clk_process:
process
begin
clock <= '0';
wait for clk_period/2; --for 0.5 ns signal is '0'.
clock <= '1';
wait for clk_period/2; --for next 0.5 ns signal is '1'.
end process;
--NOLABEL:
-- process
--
-- variable Header1 : string(1 to 3) := "OPC";
-- variable seed1 :positive ; -- seed of value for random generator
-- variable seed2 :positive ; -- seed of value for random generator
-- variable rand_num : integer;
-- variable rand_num1 : integer;
-- variable rand : real ; -- random real number value in range of 0 to 1
-- variable rand1 : real ; -- random real number value in range of 0 to 1
-- variable range_of_random : real := 1000.0; -- range of random value to be created
--
---- begin
---- uniform (seed1,seed2,rand); -- generate random number
---- uniform (seed1,seed2,rand1);
---- rand_num := integer (rand * range_of_random); -- rescale to 0 to 1000 and convert to integer
---- rand_num1 := integer (rand1 * range_of_random); -- rescale to 0 to 1000 and convert to integer
---- num_bin1 <= std_logic_vector ( to_unsigned (rand_num,8));
---- num_bin2 <= std_logic_vector ( to_unsigned (rand_num1,8));
-- wait for 2 ns;
-- wait;
-- end process;
MONITOR:
--process (num_bin1, num_bin2)
process
variable line_v : line;
variable line_num : line;
file input_file : text; -- open read_mode is "input.txt"; --declare input file
file out_file : text open write_mode is "sim_generated_file/out.txt";
variable a, b : string(1 to 8);
variable char : character:='0';
variable num_1 : std_logic_vector (7 downto 0); -- num_1 and num_2 are declared as variable
variable num_2 : std_logic_vector (7 downto 0);
variable I : integer range 0 to 4;
variable count_value : integer := 0;
begin
--wait for 10 ns;
while (count_value < 16) loop
--file out_file : text open write_mode is "out.txt";
file_open(input_file, "sim_input/input.txt", read_mode);
--while not endfile(input_file) loop
f: loop
readline(input_file, line_num);
read(line_num, a);
read(line_num, b);
for idx in 1 to 8 loop
char := a(idx);
if(char = '0') then
num_1(8-idx) := '0';
else
num_1(8-idx) := '1';
end if;
end loop;
for id in 1 to 8 loop
char := b(id);
if(char = '0') then
num_2(8-id) := '0';
else
num_2(8-id) := '1';
end if;
end loop;
OP_A <= num_1;
OP_B <= num_2;
ALU_OP <= std_logic_vector(to_unsigned(count_value, 4));
wait for 1 ns;
--OP_A1 := num_1;
--OP_B1 := num_2;
write(line_v, to_bstring(ALU_OP)& " " & to_bstring(OP_A)& " " & to_bstring(OP_B)& " " & to_bstring(RESULT));
writeline(out_file, line_v);
wait for 4 ns;
--wait;
exit f when endfile(input_file);
end loop; -- end inner while loop
write(line_v, string'(""));
writeline(out_file, line_v);
wait for 1 ns;
file_close(input_file);
count_value := count_value + 1;
--report "The value of count_value is " & integer'image(count_value);
--wait;
--wait for 1 ns;
--file_close(out_file);
end loop ; -- end outer while loop
--wait;
file_close(out_file);
wait;
end process;
END;
|
gpl-3.0
|
ad78db01c1d8ff04d7e0f8cd121699b7
| 0.515453 | 3.537037 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_12.vhd
| 4 | 2,142 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_12 is
end entity inline_12;
----------------------------------------------------------------
architecture test of inline_12 is
begin
process_3_a : process is
-- code from book:
subtype pixel_row is bit_vector (0 to 15);
variable current_row, mask : pixel_row;
-- end of code from book
begin
current_row := "0000000011111111";
mask := "0000111111110000";
-- code from book:
current_row := current_row and not mask;
current_row := current_row xor X"FFFF";
-- end of code from book
-- code from book (conditions only):
assert B"10001010" sll 3 = B"01010000";
assert B"10001010" sll -2 = B"00100010";
assert B"10010111" srl 2 = B"00100101";
assert B"10010111" srl -6 = B"11000000";
assert B"01001011" sra 3 = B"00001001";
assert B"10010111" sra 3 = B"11110010";
assert B"00001100" sla 2 = B"00110000";
assert B"00010001" sla 2 = B"01000111";
assert B"00010001" sra -2 = B"01000111";
assert B"00110000" sla -2 = B"00001100";
assert B"10010011" rol 1 = B"00100111";
assert B"10010011" ror 1 = B"11001001";
assert "abc" & 'd' = "abcd";
assert 'w' & "xyz" = "wxyz";
assert 'a' & 'b' = "ab";
-- end of code from book
wait;
end process process_3_a;
end architecture test;
|
gpl-2.0
|
eb2f61c6f4da72cfab5d38895fe33d8c
| 0.635854 | 3.693103 | false | false | false | false |
nczempin/NICNAC16
|
ipcore_dir/ROM01/simulation/ROM01_synth.vhd
| 1 | 7,051 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ROM01_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY ROM01_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE ROM01_synth_ARCH OF ROM01_synth IS
COMPONENT ROM01_exdes
PORT (
--Inputs - Port A
ENA : IN STD_LOGIC; --opt port
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ENA: STD_LOGIC := '0';
SIGNAL ENA_R: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
ENA => ENA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ENA_R <= '0' AFTER 50 ns;
ELSE
ENA_R <= ENA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: ROM01_exdes PORT MAP (
--Port A
ENA => ENA_R,
ADDRA => ADDRA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
mit
|
79a8ba2890e8060b721a065a5869fa35
| 0.573961 | 3.782725 | false | false | false | false |
tristanseifert/68komputer
|
BusMonitor.vhd
| 1 | 4,382 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--
-- This hooks up to the bus, LED display, LEDs, switches and buttons and allows
-- control of the processor. It allows single-stepping of the processor, and
-- when not in debug mode, functions as a memory-mapped peripheral that can
-- control the seven-segments, buttons and LEDs.
--
-- To single-step the CPU, put SW0 into the up position. The LED above it will
-- begin blinking, indicating you are in single-stepping mode. KEY0 can then be
-- used to single-step. Note that all other debugger functions are dependant
-- on this.
--
-- To change what is displayed on the LED display, use SW8 and SW9. With both off,
-- the contents of the data bus is displayed. With SW8 on and SW9 off, the low 16
-- bits of the address bus are displayed. With SW9 on and SW8 off, the IPL and high
-- 8 bits of the address bus are displayed. With both SW8 and SW9 on, the contents
-- of the memory-mapped register is displayed.
--
entity BusMonitor is
PORT(
-- CPU clock
clk_cpu: IN std_logic;
sys_reset: INOUT std_logic;
-- Blinking clock
blink_clk: IN std_logic;
-- 68k bus: system control
bus_reset: IN std_logic;
bus_clk: INOUT std_logic; -- CPU clock
bus_halt: INOUT std_logic;
bus_error: IN std_logic;
-- 68k bus: data
bus_data: INOUT std_logic_vector(15 downto 0);
bus_addr: INOUT std_logic_vector(23 downto 0);
-- 68k bus: bus control
bus_as: INOUT std_logic;
bus_rw: INOUT std_logic; -- read = 1, write = 0
bus_uds: INOUT std_logic; -- upper and lower byte strobes
bus_lds: INOUT std_logic;
bus_dtack: IN std_logic; -- data acknowledge, driven by peripheral
-- 68k bus: bus arbitration
bus_br: INOUT std_logic; -- assert to request bus
bus_bg: IN std_logic; -- asserted when bus is free
bus_bgack: INOUT std_logic; -- assert to acknowledge bus request
-- 68k bus: interrupt control
bus_irq: IN std_logic_vector(2 downto 0);
-- peripherals
HEX0: OUT std_logic_vector(6 downto 0);
HEX1: OUT std_logic_vector(6 downto 0);
HEX2: OUT std_logic_vector(6 downto 0);
HEX3: OUT std_logic_vector(6 downto 0);
SW: IN std_logic_vector(9 downto 0);
KEY: IN std_logic_vector(3 downto 0);
LEDR: OUT std_logic_vector(9 downto 0);
LEDG: OUT std_logic_vector(7 downto 0)
);
end BusMonitor;
architecture behavioral of BusMonitor is
signal hexValue: std_logic_vector(15 downto 0);
begin
-- hex displays
u_hex0: entity work.HexDisplay(behavioral)
port map(
clk => clk_cpu,
reset => sys_reset,
Display => HEX3,
InVal => hexValue(15 downto 12)
);
u_hex1: entity work.HexDisplay(behavioral)
port map(
clk => clk_cpu,
reset => sys_reset,
Display => HEX2,
InVal => hexValue(11 downto 8)
);
u_hex2: entity work.HexDisplay(behavioral)
port map(
clk => clk_cpu,
reset => sys_reset,
Display => HEX1,
InVal => hexValue(7 downto 4)
);
u_hex3: entity work.HexDisplay(behavioral)
port map(
clk => clk_cpu,
reset => sys_reset,
Display => HEX0,
InVal => hexValue(3 downto 0)
);
-- Green LEDs indicate the bus state:
-- BERR | AS | RW | UDS | LDS | DTACK | BR | BG
process(bus_clk, sys_reset, bus_error, bus_as, bus_rw, bus_uds, bus_lds, bus_dtack, bus_br, bus_bg)
begin
if sys_reset='1' then
elsif rising_edge(bus_clk) then
LEDG(7) <= bus_error;
LEDG(6) <= bus_as;
LEDG(5) <= bus_rw;
LEDG(4) <= bus_uds;
LEDG(3) <= bus_lds;
LEDG(2) <= bus_dtack;
LEDG(1) <= bus_br;
LEDG(0) <= bus_bg;
end if;
end process;
-- reset button
sys_reset <= NOT KEY(3);
-- Single-stepping
process(SW(0), KEY(0), blink_clk)
begin
if SW(0)='1' then
bus_clk <= KEY(0);
LEDR(0) <= blink_clk;
else
bus_clk <= clk_cpu;
LEDR(0) <= '0';
end if;
end process;
-- Display
process (SW(9 downto 8))
begin
case SW(9 downto 8) is
when "00" =>
hexValue <= bus_data;
when "01" =>
hexValue <= bus_addr(15 downto 0);
when "10" =>
hexValue <= "0" & bus_irq & "0000" & bus_addr(23 downto 16);
when "11" =>
hexValue <= x"ABCD";
end case;
end process;
end behavioral;
|
bsd-2-clause
|
118c18b1d3aca29dcb8d1dafb1ee03b0
| 0.628708 | 2.89432 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1365.vhd
| 4 | 6,566 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1365.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01365ent IS
END c08s05b00x00p03n01i01365ent;
ARCHITECTURE c08s05b00x00p03n01i01365arch OF c08s05b00x00p03n01i01365ent IS
BEGIN
TESTING: PROCESS
--
-- Define constants for package
--
constant lowb : integer := 1 ;
constant highb : integer := 5 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0 ;
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
variable v_st_arr2 : st_arr2 := c_st_arr2_1 ;
--
BEGIN
v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) :=
c_st_arr2_2(st_arr2'Right(1),st_arr2'Right(2)) ;
assert NOT(v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2)
report "***PASSED TEST: c08s05b00x00p03n01i01365"
severity NOTE;
assert (v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2)
report "***FAILED TEST: c08s05b00x00p03n01i01365 - The types of the variable and the assigned variable must match."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01365arch;
|
gpl-2.0
|
dc2f8357682f0e14462750ba0110e111
| 0.58346 | 2.943075 | false | false | false | false |
stnolting/neo430
|
rtl/core/neo430_cfu.vhd
| 1 | 11,127 |
-- #################################################################################################
-- # << NEO430 - Custom Functions Unit >> #
-- # ********************************************************************************************* #
-- # This unit is a template for implementing custom functions, which are directly memory-mapped #
-- # into the CPU's IO address space. The address space of this unit is 16 bytes large. This unit #
-- # can only be accessed using full word (16-bit) accesses. #
-- # In the original state, this unit only provides 8 16-bit register, that do not perform any #
-- # kind of data manipulation. #
-- # Exemplary applications: Cryptography, complex arithmetic, rocket science, ... #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
entity neo430_cfu is
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0); -- data out
-- clock generator --
clkgen_en_o : out std_ulogic; -- enable clock generator
clkgen_i : in std_ulogic_vector(07 downto 0)
-- custom IOs --
-- ...
);
end neo430_cfu;
architecture neo430_cfu_rtl of neo430_cfu is
-- IO space: module base address --
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
constant lo_abb_c : natural := index_size_f(cfu_size_c); -- low address boundary bit
-- access control --
signal acc_en : std_ulogic; -- module access enable
signal addr : std_ulogic_vector(15 downto 0); -- access address
signal wren : std_ulogic; -- full word write enable
signal rden : std_ulogic; -- read enable
-- accessible regs (8x16-bit) --
signal cfu_ctrl_reg : std_ulogic_vector(15 downto 0);
signal user_reg1 : std_ulogic_vector(15 downto 0);
signal user_reg2 : std_ulogic_vector(15 downto 0);
signal user_reg3 : std_ulogic_vector(15 downto 0);
signal user_reg4 : std_ulogic_vector(15 downto 0);
signal user_reg5 : std_ulogic_vector(15 downto 0);
signal user_reg6 : std_ulogic_vector(15 downto 0);
signal user_reg7 : std_ulogic_vector(15 downto 0);
begin
-- Access Control -----------------------------------------------------------
-- -----------------------------------------------------------------------------
-- These assignments are required to check if this unit is accessed at all.
-- Do NOT modify this for your custom application (unless you really know what you are doing)!
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = cfu_base_c(hi_abb_c downto lo_abb_c)) else '0';
addr <= cfu_base_c(15 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 1) & '0'; -- word aligned
wren <= acc_en and wren_i;
rden <= acc_en and rden_i;
-- Clock System -------------------------------------------------------------
-- -----------------------------------------------------------------------------
-- The top unit implements a clock generator providing 8 "derived clocks"
-- Actually, these signals must not be used as direct clock signals, but as clock enable signals.
-- If wou want to drive a system at MAIN_CLK/8 use the following construct:
-- if rising_edge(clk_i) then -- Always use the main clock for all clock processes!
-- if (clkgen_i(clk_div8_c) = '1') then -- the div8 "clock" is actually a clock enable
-- ...
-- end if;
-- end if;
-- The following clock divider rates are available:
-- clkgen_i(clk_div2_c) -> MAIN_CLK/2
-- clkgen_i(clk_div4_c) -> MAIN_CLK/4
-- clkgen_i(clk_div8_c) -> MAIN_CLK/8
-- clkgen_i(clk_div64_c) -> MAIN_CLK/64
-- clkgen_i(clk_div128_c) -> MAIN_CLK/128
-- clkgen_i(clk_div1024_c) -> MAIN_CLK/1024
-- clkgen_i(clk_div2048_c) -> MAIN_CLK/2048
-- clkgen_i(clk_div4096_c) -> MAIN_CLK/4096
-- this signal enabled the generator driving the clkgen_i
-- set this signal to '0' when you do not need the clkgen_i signal or when your CFU is disabled
-- to reduce dynamic power consumption
clkgen_en_o <= '0';
-- Write access -------------------------------------------------------------
-- -----------------------------------------------------------------------------
-- Here we are writing to the interface registers of the module. This unit can only be accessed
-- in full 16-bit word mode!
-- Please note, that all register of every unit are cleared during the processor boot sequence.
-- Make cfu_reg0_addr_c the CFU's control register. This register is cleared first during booting.
-- If the control register is cleared no actions should be taken when writing to other CFU registers.
wr_access: process(clk_i)
begin
if rising_edge(clk_i) then
-- write access to user registers --
if (wren = '1') then -- valid write access
-- use full-parallel IFs instead of a CASE to prevent some EDA tools from complaining (GHDL)
if (addr = cfu_reg0_addr_c) then
cfu_ctrl_reg <= data_i;
end if;
if (addr = cfu_reg1_addr_c) then
user_reg1 <= data_i;
end if;
if (addr = cfu_reg2_addr_c) then
user_reg2 <= data_i;
end if;
if (addr = cfu_reg3_addr_c) then
user_reg3 <= data_i;
end if;
if (addr = cfu_reg4_addr_c) then
user_reg4 <= data_i;
end if;
if (addr = cfu_reg5_addr_c) then
user_reg5 <= data_i;
end if;
if (addr = cfu_reg6_addr_c) then
user_reg6 <= data_i;
end if;
if (addr = cfu_reg7_addr_c) then
user_reg7 <= data_i;
end if;
end if;
end if;
end process wr_access;
-- >>> UNIT HARDWARE RESET <<< --
-- The IO devices DO NOT feature a dedicated reset signal, so make sure your CFU does not require a defined initial state.
-- If you really require a defined initial state, implement a software reset by implementing a control register with an
-- enable bit, which resets all internal states when cleared.
-- Read access --------------------------------------------------------------
-- -----------------------------------------------------------------------------
-- This is the read access process. Data must be asserted synchronously to the output data bus
-- and thus, with exactly 1 cycle delay. The units always output a full 16-bit word, no matter if we want to
-- read 8- or 16-bit. For actual 8-bit read accesses the corresponding byte is selected in the
-- hardware of the CPU core.
rd_access: process(clk_i)
begin
if rising_edge(clk_i) then
data_o <= (others => '0'); -- this is crucial for the final OR-ing of all IO device's outputs
if (rden = '1') then -- valid read access
-- use IFs instead of a CASE to prevent some EDA tools from complaining (GHDL)
if (addr = cfu_reg0_addr_c) then
data_o <= cfu_ctrl_reg;
elsif (addr = cfu_reg1_addr_c) then
data_o <= user_reg1;
elsif (addr = cfu_reg2_addr_c) then
data_o <= user_reg2;
elsif (addr = cfu_reg3_addr_c) then
data_o <= user_reg3;
elsif (addr = cfu_reg4_addr_c) then
data_o <= user_reg4;
elsif (addr = cfu_reg5_addr_c) then
data_o <= user_reg5;
elsif (addr = cfu_reg6_addr_c) then
data_o <= user_reg6;
elsif (addr = cfu_reg7_addr_c) then
data_o <= user_reg7;
else
data_o <= (others => '0');
end if;
end if;
end if;
end process rd_access;
end neo430_cfu_rtl;
|
bsd-3-clause
|
68d10d6b5c741868f11fb08c1f82ccd5
| 0.514784 | 4.382434 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc781.vhd
| 4 | 2,484 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc781.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x02p12n04i00781ent_a IS
port (
C1 : in Bit;
C2 : inout Bit;
C3 : linkage Bit;
C4 : out Bit;
C5 : Buffer Bit
);
END c01s01b01x02p12n04i00781ent_a;
ARCHITECTURE c01s01b01x02p12n04i00781arch_a OF c01s01b01x02p12n04i00781ent_a IS
BEGIN
END c01s01b01x02p12n04i00781arch_a;
ENTITY c01s01b01x02p12n04i00781ent IS
port (
A1 : in Bit;
A2 : inout Bit;
A3 : linkage Bit;
A4 : out Bit;
A5 : Buffer Bit
) ;
END c01s01b01x02p12n04i00781ent;
ARCHITECTURE c01s01b01x02p12n04i00781arch OF c01s01b01x02p12n04i00781ent IS
component c01s01b01x02p12n04i00781ent_b
port (
C1 : in Bit;
C2 : inout Bit;
C3 : linkage Bit;
C4 : out Bit;
C5 : Buffer Bit
);
end component;
for L : c01s01b01x02p12n04i00781ent_b use entity work.c01s01b01x02p12n04i00781ent_a(c01s01b01x02p12n04i00781arch_a);
BEGIN
L : c01s01b01x02p12n04i00781ent_b port map ( C1 => open, C2 => open, C3 => open, C4 => open, C5 => open );
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b01x02p12n04i00781 - A port of mode in may not be unconnected."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x02p12n04i00781arch;
|
gpl-2.0
|
d6cc797e028ac7bbb1dcaf56978de298
| 0.64694 | 3.188703 | false | true | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc621.vhd
| 4 | 4,783 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc621.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:45 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:07 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:24 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00621ent IS
END c03s04b01x00p01n01i00621ent;
ARCHITECTURE c03s04b01x00p01n01i00621arch OF c03s04b01x00p01n01i00621ent IS
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
subtype boolean_vector_st is boolean_vector(0 to 15);
subtype severity_level_vector_st is severity_level_vector(0 to 15);
subtype integer_vector_st is integer_vector(0 to 15);
subtype real_vector_st is real_vector(0 to 15);
subtype time_vector_st is time_vector(0 to 15);
subtype natural_vector_st is natural_vector(0 to 15);
subtype positive_vector_st is positive_vector(0 to 15);
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
type record_array_st_file is file of record_array_st;
constant C1 : boolean := true;
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 3;
constant C9 : positive := 3;
constant C28 : boolean_vector_st :=(others => C1);
constant C29 : severity_level_vector_st :=(others => C4);
constant C30 : integer_vector_st :=(others => C5);
constant C31 : real_vector_st :=(others => C6);
constant C32 : time_vector_st :=(others => C7);
constant C33 : natural_vector_st :=(others => C8);
constant C34 : positive_vector_st :=(others => C9);
constant C35 : record_array_st := (C28,C29,C30,C31,C32,C33,C34);
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : record_array_st_file open read_mode is "iofile.34";
variable v : record_array_st;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C35) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00621"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00621 - File reading operation (record_array_st file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00621arch;
|
gpl-2.0
|
08ea538f3f0166f5ea5798b13c620768
| 0.562199 | 3.863489 | false | false | false | false |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/to_send/ngnp_added_monitor/ngnp/src/tmp/tg86/TG68_fast.vhd
| 3 | 100,640 |
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- This is the 68000 software compatible Kernal of TG68 --
-- --
-- Copyright (c) 2007 Tobias Gubener <[email protected]> --
-- --
-- This source file is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published --
-- by the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This source file is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--
-- Revision 1.06 2009/02/10
-- Bugfix shift and rotations opcodes when the bitcount and the data are in the same register:
-- Example lsr.l D2,D2
-- Thanks to Peter Graf for report
--
-- Revision 1.05 2009/01/26
-- Implement missing RTR
-- Thanks to Peter Graf for report
--
-- Revision 1.04 2007/12/29
-- size improvement
-- change signal "microaddr" to one hot state machine
--
-- Revision 1.03 2007/12/21
-- Thanks to Andreas Ehliar
-- Split regfile to use blockram for registers
-- insert "WHEN OTHERS => null;" on END CASE;
--
-- Revision 1.02 2007/12/17
-- Bugfix jsr nn.w
--
-- Revision 1.01 2007/11/28
-- add MOVEP
-- Bugfix Interrupt in MOVEQ
--
-- Revision 1.0 2007/11/05
-- Clean up code and first release
--
-- known bugs/todo:
-- Add CHK INSTRUCTION
-- full decode ILLEGAL INSTRUCTIONS
-- Add FC Output
-- add odd Address test
-- add TRACE
-- Movem with regmask==x0000
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity TG68_fast is
port(clk : in std_logic;
reset : in std_logic; --low active
clkena_in : in std_logic:='1';
data_in : in std_logic_vector(15 downto 0);
IPL : in std_logic_vector(2 downto 0):="111";
test_IPL : in std_logic:='0'; --only for debugging
address : out std_logic_vector(31 downto 0);
data_write : out std_logic_vector(15 downto 0);
state_out : out std_logic_vector(1 downto 0);
LDS, UDS : out std_logic;
decodeOPC : buffer std_logic;
wr : out std_logic
);
end TG68_fast;
architecture logic of TG68_fast is
signal state : std_logic_vector(1 downto 0);
signal clkena : std_logic;
signal TG68_PC : std_logic_vector(31 downto 0);
signal TG68_PC_add : std_logic_vector(31 downto 0);
signal memaddr : std_logic_vector(31 downto 0);
signal memaddr_in : std_logic_vector(31 downto 0);
signal ea_data : std_logic_vector(31 downto 0);
signal ea_data_OP1 : std_logic;
signal setaddrlong : std_logic;
signal OP1out, OP2out : std_logic_vector(31 downto 0);
signal OP1outbrief : std_logic_vector(15 downto 0);
signal OP1in : std_logic_vector(31 downto 0);
signal data_write_tmp : std_logic_vector(31 downto 0);
signal Xtmp : std_logic_vector(31 downto 0);
signal PC_dataa, PC_datab, PC_result : std_logic_vector(31 downto 0);
signal setregstore : std_logic;
signal datatype : std_logic_vector(1 downto 0);
signal longread : std_logic;
signal longreaddirect : std_logic;
signal long_done : std_logic;
signal nextpass : std_logic;
signal setnextpass : std_logic;
signal setdispbyte : std_logic;
signal setdisp : std_logic;
signal setdispbrief : std_logic;
signal regdirectsource : std_logic;
signal endOPC : std_logic;
signal postadd : std_logic;
signal presub : std_logic;
signal addsub_a : std_logic_vector(31 downto 0);
signal addsub_b : std_logic_vector(31 downto 0);
signal addsub_q : std_logic_vector(31 downto 0);
signal briefext : std_logic_vector(31 downto 0);
signal setbriefext : std_logic;
signal addsub : std_logic;
signal c_in : std_logic_vector(3 downto 0);
signal c_out : std_logic_vector(2 downto 0);
signal add_result : std_logic_vector(33 downto 0);
signal addsub_ofl : std_logic_vector(2 downto 0);
signal flag_z : std_logic_vector(2 downto 0);
signal last_data_read : std_logic_vector(15 downto 0);
signal data_read : std_logic_vector(31 downto 0);
signal registerin : std_logic_vector(31 downto 0);
signal reg_QA : std_logic_vector(31 downto 0);
signal reg_QB : std_logic_vector(31 downto 0);
signal Hwrena,Lwrena : std_logic;
signal Regwrena : std_logic;
signal rf_dest_addr : std_logic_vector(6 downto 0);
signal rf_source_addr : std_logic_vector(6 downto 0);
signal rf_dest_addr_tmp : std_logic_vector(6 downto 0);
signal rf_source_addr_tmp : std_logic_vector(6 downto 0);
signal opcode : std_logic_vector(15 downto 0);
signal laststate : std_logic_vector(1 downto 0);
signal setstate : std_logic_vector(1 downto 0);
signal mem_address : std_logic_vector(31 downto 0);
signal memaddr_a : std_logic_vector(31 downto 0);
signal mem_data_read : std_logic_vector(31 downto 0);
signal mem_data_write : std_logic_vector(31 downto 0);
signal set_mem_rega : std_logic;
signal data_read_ram : std_logic_vector(31 downto 0);
signal data_read_uart : std_logic_vector(7 downto 0);
signal counter_reg : std_logic_vector(31 downto 0);
signal TG68_PC_br8 : std_logic;
signal TG68_PC_brw : std_logic;
signal TG68_PC_nop : std_logic;
signal setgetbrief : std_logic;
signal getbrief : std_logic;
signal brief : std_logic_vector(15 downto 0);
signal dest_areg : std_logic;
signal source_areg : std_logic;
signal data_is_source : std_logic;
signal set_store_in_tmp : std_logic;
signal store_in_tmp : std_logic;
signal write_back : std_logic;
signal setaddsub : std_logic;
signal setstackaddr : std_logic;
signal writePC : std_logic;
signal writePC_add : std_logic;
signal set_TG68_PC_dec: std_logic;
signal TG68_PC_dec : std_logic_vector(1 downto 0);
signal directPC : std_logic;
signal set_directPC : std_logic;
signal execOPC : std_logic;
signal fetchOPC : std_logic;
signal Flags : std_logic_vector(15 downto 0); --T.S..III ...XNZVC
signal set_Flags : std_logic_vector(3 downto 0); --NZVC
signal exec_ADD : std_logic;
signal exec_OR : std_logic;
signal exec_AND : std_logic;
signal exec_EOR : std_logic;
signal exec_MOVE : std_logic;
signal exec_MOVEQ : std_logic;
signal exec_MOVESR : std_logic;
signal exec_DIRECT : std_logic;
signal exec_ADDQ : std_logic;
signal exec_CMP : std_logic;
signal exec_ROT : std_logic;
signal exec_exg : std_logic;
signal exec_swap : std_logic;
signal exec_write_back: std_logic;
signal exec_tas : std_logic;
signal exec_EXT : std_logic;
signal exec_ABCD : std_logic;
signal exec_SBCD : std_logic;
signal exec_MULU : std_logic;
signal exec_DIVU : std_logic;
signal exec_Scc : std_logic;
signal exec_CPMAW : std_logic;
signal set_exec_ADD : std_logic;
signal set_exec_OR : std_logic;
signal set_exec_AND : std_logic;
signal set_exec_EOR : std_logic;
signal set_exec_MOVE : std_logic;
signal set_exec_MOVEQ : std_logic;
signal set_exec_MOVESR: std_logic;
signal set_exec_ADDQ : std_logic;
signal set_exec_CMP : std_logic;
signal set_exec_ROT : std_logic;
signal set_exec_tas : std_logic;
signal set_exec_EXT : std_logic;
signal set_exec_ABCD : std_logic;
signal set_exec_SBCD : std_logic;
signal set_exec_MULU : std_logic;
signal set_exec_DIVU : std_logic;
signal set_exec_Scc : std_logic;
signal set_exec_CPMAW : std_logic;
signal condition : std_logic;
signal OP2out_one : std_logic;
signal OP1out_zero : std_logic;
signal ea_to_pc : std_logic;
signal ea_build : std_logic;
signal ea_only : std_logic;
signal get_ea_now : std_logic;
signal source_lowbits : std_logic;
signal dest_hbits : std_logic;
signal rot_rot : std_logic;
signal rot_lsb : std_logic;
signal rot_msb : std_logic;
signal rot_XC : std_logic;
signal set_rot_nop : std_logic;
signal rot_nop : std_logic;
signal rot_out : std_logic_vector(31 downto 0);
signal rot_bits : std_logic_vector(1 downto 0);
signal rot_cnt : std_logic_vector(5 downto 0);
signal set_rot_cnt : std_logic_vector(5 downto 0);
signal movem_busy : std_logic;
signal set_movem_busy : std_logic;
signal movem_addr : std_logic;
signal movem_regaddr : std_logic_vector(3 downto 0);
signal movem_mask : std_logic_vector(15 downto 0);
signal set_get_movem_mask : std_logic;
signal get_movem_mask : std_logic;
signal movem_muxa : std_logic_vector(7 downto 0);
signal movem_muxb : std_logic_vector(3 downto 0);
signal movem_muxc : std_logic_vector(1 downto 0);
signal movem_presub : std_logic;
signal save_memaddr : std_logic;
signal movem_bits : std_logic_vector(4 downto 0);
signal ea_calc_b : std_logic_vector(31 downto 0);
signal set_mem_addsub : std_logic;
signal bit_bits : std_logic_vector(1 downto 0);
signal bit_number_reg : std_logic_vector(4 downto 0);
signal bit_number : std_logic_vector(4 downto 0);
signal exec_Bits : std_logic;
signal bits_out : std_logic_vector(31 downto 0);
signal one_bit_in : std_logic;
signal one_bit_out : std_logic;
signal set_get_bitnumber : std_logic;
signal get_bitnumber : std_logic;
signal mem_byte : std_logic;
signal wait_mem_byte : std_logic;
signal movepl : std_logic;
signal movepw : std_logic;
signal set_movepl : std_logic;
signal set_movepw : std_logic;
signal set_direct_data: std_logic;
signal use_direct_data: std_logic;
signal direct_data : std_logic;
signal set_get_extendedOPC : std_logic;
signal get_extendedOPC: std_logic;
signal setstate_delay : std_logic_vector(1 downto 0);
signal setstate_mux : std_logic_vector(1 downto 0);
signal use_XZFlag : std_logic;
signal use_XFlag : std_logic;
signal dummy_a : std_logic_vector(8 downto 0);
signal niba_l : std_logic_vector(5 downto 0);
signal niba_h : std_logic_vector(5 downto 0);
signal niba_lc : std_logic;
signal niba_hc : std_logic;
signal bcda_lc : std_logic;
signal bcda_hc : std_logic;
signal dummy_s : std_logic_vector(8 downto 0);
signal nibs_l : std_logic_vector(5 downto 0);
signal nibs_h : std_logic_vector(5 downto 0);
signal nibs_lc : std_logic;
signal nibs_hc : std_logic;
signal dummy_mulu : std_logic_vector(31 downto 0);
signal dummy_div : std_logic_vector(31 downto 0);
signal dummy_div_sub : std_logic_vector(16 downto 0);
signal dummy_div_over : std_logic_vector(16 downto 0);
signal set_V_Flag : std_logic;
signal OP1sign : std_logic;
signal set_sign : std_logic;
signal sign : std_logic;
signal sign2 : std_logic;
signal muls_msb : std_logic;
signal mulu_reg : std_logic_vector(31 downto 0);
signal div_reg : std_logic_vector(31 downto 0);
signal div_sign : std_logic;
signal div_quot : std_logic_vector(31 downto 0);
signal div_ovl : std_logic;
signal pre_V_Flag : std_logic;
signal set_vectoraddr : std_logic;
signal writeSR : std_logic;
signal trap_illegal : std_logic;
signal trap_priv : std_logic;
signal trap_1010 : std_logic;
signal trap_1111 : std_logic;
signal trap_trap : std_logic;
signal trap_trapv : std_logic;
signal trap_interrupt : std_logic;
signal trapmake : std_logic;
signal trapd : std_logic;
-- signal trap_PC : std_logic_vector(31 downto 0);
signal trap_SR : std_logic_vector(15 downto 0);
signal set_directSR : std_logic;
signal directSR : std_logic;
signal set_directCCR : std_logic;
signal directCCR : std_logic;
signal set_stop : std_logic;
signal stop : std_logic;
signal trap_vector : std_logic_vector(31 downto 0);
signal to_USP : std_logic;
signal from_USP : std_logic;
signal to_SR : std_logic;
signal from_SR : std_logic;
signal illegal_write_mode : std_logic;
signal illegal_read_mode : std_logic;
signal illegal_byteaddr : std_logic;
signal use_SP : std_logic;
signal no_Flags : std_logic;
signal IPL_nr : std_logic_vector(2 downto 0);
signal rIPL_nr : std_logic_vector(2 downto 0);
signal interrupt : std_logic;
signal SVmode : std_logic;
signal trap_chk : std_logic;
signal test_delay : std_logic_vector(2 downto 0);
signal set_PCmarker : std_logic;
signal PCmarker : std_logic;
signal set_Z_error : std_logic;
signal Z_error : std_logic;
type micro_states is (idle, nop, ld_nn, st_nn, ld_dAn1, ld_dAn2, ld_AnXn1, ld_AnXn2, ld_AnXn3, st_dAn1, st_dAn2,
st_AnXn1, st_AnXn2, st_AnXn3, bra1, bra2, bsr1, bsr2, dbcc1, dbcc2,
movem, andi, op_AxAy, cmpm, link, int1, int2, int3, int4, rte, trap1, trap2, trap3,
movep1, movep2, movep3, movep4, movep5, init1, init2,
mul1, mul2, mul3, mul4, mul5, mul6, mul7, mul8, mul9, mul10, mul11, mul12, mul13, mul14, mul15,
div1, div2, div3, div4, div5, div6, div7, div8, div9, div10, div11, div12, div13, div14, div15 );
signal micro_state : micro_states;
signal next_micro_state : micro_states;
type regfile_t is array(0 to 16) of std_logic_vector(15 downto 0);
signal regfile_low : regfile_t;
signal regfile_high : regfile_t;
signal RWindex_A : integer range 0 to 16;
signal RWindex_B : integer range 0 to 16;
BEGIN
-----------------------------------------------------------------------------
-- Registerfile
-----------------------------------------------------------------------------
RWindex_A <= conv_integer(rf_dest_addr(4)&(rf_dest_addr(3 downto 0) XOR "1111"));
RWindex_B <= conv_integer(rf_source_addr(4)&(rf_source_addr(3 downto 0) XOR "1111"));
PROCESS (clk)
BEGIN
IF falling_edge(clk) THEN
IF clkena='1' THEN
reg_QA <= regfile_high(RWindex_A) & regfile_low(RWindex_A);
reg_QB <= regfile_high(RWindex_B) & regfile_low(RWindex_B);
END IF;
END IF;
IF rising_edge(clk) THEN
IF clkena='1' THEN
IF Lwrena='1' THEN
regfile_low(RWindex_A) <= registerin(15 downto 0);
END IF;
IF Hwrena='1' THEN
regfile_high(RWindex_A) <= registerin(31 downto 16);
END IF;
END IF;
END IF;
END PROCESS;
address <= TG68_PC when state="00" else X"ffffffff" when state="01" else memaddr;
LDS <= '0' WHEN (datatype/="00" OR state="00" OR memaddr(0)='1') AND state/="01" ELSE '1';
UDS <= '0' WHEN (datatype/="00" OR state="00" OR memaddr(0)='0') AND state/="01" ELSE '1';
state_out <= state;
wr <= '0' WHEN state="11" ELSE '1';
IPL_nr <= NOT IPL;
-----------------------------------------------------------------------------
-- "ALU"
-----------------------------------------------------------------------------
PROCESS (addsub_a, addsub_b, addsub, add_result, c_in)
BEGIN
IF addsub='1' THEN --ADD
add_result <= (('0'&addsub_a&c_in(0))+('0'&addsub_b&c_in(0)));
ELSE --SUB
add_result <= (('0'&addsub_a&'0')-('0'&addsub_b&c_in(0)));
END IF;
addsub_q <= add_result(32 downto 1);
c_in(1) <= add_result(9) XOR addsub_a(8) XOR addsub_b(8);
c_in(2) <= add_result(17) XOR addsub_a(16) XOR addsub_b(16);
c_in(3) <= add_result(33);
addsub_ofl(0) <= (c_in(1) XOR add_result(8) XOR addsub_a(7) XOR addsub_b(7)); --V Byte
addsub_ofl(1) <= (c_in(2) XOR add_result(16) XOR addsub_a(15) XOR addsub_b(15)); --V Word
addsub_ofl(2) <= (c_in(3) XOR add_result(32) XOR addsub_a(31) XOR addsub_b(31)); --V Long
c_out <= c_in(3 downto 1);
END PROCESS;
-----------------------------------------------------------------------------
-- MEM_IO
-----------------------------------------------------------------------------
PROCESS (clk, reset, clkena_in, opcode, rIPL_nr, longread, get_extendedOPC, memaddr, memaddr_a, set_mem_addsub, movem_presub,
movem_busy, state, PCmarker, execOPC, datatype, setdisp, setdispbrief, briefext, setdispbyte, brief,
set_mem_rega, reg_QA, setaddrlong, data_read, decodeOPC, TG68_PC, data_in, long_done, last_data_read, mem_byte,
data_write_tmp, addsub_q, set_vectoraddr, trap_vector, interrupt)
BEGIN
clkena <= clkena_in AND NOT longread AND NOT get_extendedOPC;
IF rising_edge(clk) THEN
IF clkena='1' THEN
trap_vector(31 downto 8) <= (others => '0');
-- IF trap_addr_fault='1' THEN
-- trap_vector(7 downto 0) <= X"08";
-- END IF;
-- IF trap_addr_error='1' THEN
-- trap_vector(7 downto 0) <= X"0C";
-- END IF;
IF trap_illegal='1' THEN
trap_vector(7 downto 0) <= X"10";
END IF;
IF z_error='1' THEN
trap_vector(7 downto 0) <= X"14";
END IF;
-- IF trap_chk='1' THEN
-- trap_vector(7 downto 0) <= X"18";
-- END IF;
IF trap_trapv='1' THEN
trap_vector(7 downto 0) <= X"1C";
END IF;
IF trap_priv='1' THEN
trap_vector(7 downto 0) <= X"20";
END IF;
-- IF trap_trace='1' THEN
-- trap_vector(7 downto 0) <= X"24";
-- END IF;
IF trap_1010='1' THEN
trap_vector(7 downto 0) <= X"28";
END IF;
IF trap_1111='1' THEN
trap_vector(7 downto 0) <= X"2C";
END IF;
IF trap_trap='1' THEN
trap_vector(7 downto 2) <= "10"&opcode(3 downto 0);
END IF;
IF interrupt='1' THEN
trap_vector(7 downto 2) <= "011"&rIPL_nr;
END IF;
END IF;
END IF;
memaddr_a(3 downto 0) <= "0000";
memaddr_a(7 downto 4) <= (OTHERS=>memaddr_a(3));
memaddr_a(15 downto 8) <= (OTHERS=>memaddr_a(7));
memaddr_a(31 downto 16) <= (OTHERS=>memaddr_a(15));
IF movem_presub='1' THEN
IF movem_busy='1' OR longread='1' THEN
memaddr_a(3 downto 0) <= "1110";
END IF;
ELSIF state(1)='1' OR (get_extendedOPC='1' AND PCmarker='1') THEN
memaddr_a(1) <= '1';
ELSIF execOPC='1' THEN
IF datatype="10" THEN
memaddr_a(3 downto 0) <= "1100";
ELSE
memaddr_a(3 downto 0) <= "1110";
END IF;
ELSIF setdisp='1' THEN
IF setdispbrief='1' THEN
memaddr_a <= briefext;
ELSIF setdispbyte='1' THEN
memaddr_a(7 downto 0) <= brief(7 downto 0);
ELSE
memaddr_a(15 downto 0) <= brief;
END IF;
END IF;
memaddr_in <= memaddr+memaddr_a;
IF longread='0' THEN
IF set_mem_addsub='1' THEN
memaddr_in <= addsub_q;
ELSIF set_vectoraddr='1' THEN
memaddr_in <= trap_vector;
ELSIF interrupt='1' THEN
memaddr_in <= "1111111111111111111111111111"&rIPL_nr&'0';
ELSIF set_mem_rega='1' THEN
memaddr_in <= reg_QA;
ELSIF setaddrlong='1' AND longread='0' THEN
memaddr_in <= data_read;
ELSIF decodeOPC='1' THEN
memaddr_in <= TG68_PC;
END IF;
END IF;
data_read(15 downto 0) <= data_in;
data_read(31 downto 16) <= (OTHERS=>data_in(15));
IF long_done='1' THEN
data_read(31 downto 16) <= last_data_read;
END IF;
IF mem_byte='1' AND memaddr(0)='0' THEN
data_read(7 downto 0) <= data_in(15 downto 8);
END IF;
IF longread='1' THEN
data_write <= data_write_tmp(31 downto 16);
ELSE
data_write(7 downto 0) <= data_write_tmp(7 downto 0);
IF mem_byte='1' THEN
data_write(15 downto 8) <= data_write_tmp(7 downto 0);
ELSE
data_write(15 downto 8) <= data_write_tmp(15 downto 8);
IF datatype="00" THEN
data_write(7 downto 0) <= data_write_tmp(15 downto 8);
END IF;
END IF;
END IF;
IF reset='0' THEN
longread <= '0';
long_done <= '0';
ELSIF rising_edge(clk) THEN
IF clkena_in='1' THEN
last_data_read <= data_in;
long_done <= longread;
IF get_extendedOPC='0' OR (get_extendedOPC='1' AND PCmarker='1') THEN
memaddr <= memaddr_in;
END IF;
IF get_extendedOPC='0' THEN
IF ((setstate_mux(1)='1' AND datatype="10") OR longreaddirect='1') AND longread='0' AND interrupt='0' THEN
longread <= '1';
ELSE
longread <= '0';
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- brief
-----------------------------------------------------------------------------
process (clk, brief, OP1out)
begin
IF brief(11)='1' THEN
OP1outbrief <= OP1out(31 downto 16);
ELSE
OP1outbrief <= (OTHERS=>OP1out(15));
END IF;
IF rising_edge(clk) THEN
IF clkena='1' THEN
briefext <= OP1outbrief&OP1out(15 downto 0);
-- CASE brief(10 downto 9) IS
-- WHEN "00" => briefext <= OP1outbrief&OP1out(15 downto 0);
-- WHEN "01" => briefext <= OP1outbrief(14 downto 0)&OP1out(15 downto 0)&'0';
-- WHEN "10" => briefext <= OP1outbrief(13 downto 0)&OP1out(15 downto 0)&"00";
-- WHEN "11" => briefext <= OP1outbrief(12 downto 0)&OP1out(15 downto 0)&"000";
-- END CASE;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- PC Calc + fetch opcode
-----------------------------------------------------------------------------
process (clk, reset, opcode, TG68_PC, TG68_PC_dec, TG68_PC_br8, TG68_PC_brw, PC_dataa, PC_datab, execOPC, last_data_read, get_extendedOPC,
setstate_delay, setstate)
begin
PC_dataa <= TG68_PC;
PC_datab(2 downto 0) <= "010";
PC_datab(7 downto 3) <= (others => PC_datab(2));
PC_datab(15 downto 8) <= (others => PC_datab(7));
PC_datab(31 downto 16) <= (others => PC_datab(15));
IF execOPC='0' THEN
IF TG68_PC_br8='1' THEN
PC_datab(7 downto 0) <= opcode(7 downto 0);
END IF;
IF TG68_PC_dec(1)='1' THEN
PC_datab(2) <= '1';
END IF;
IF TG68_PC_brw = '1' THEN
PC_datab(15 downto 0) <= last_data_read(15 downto 0);
END IF;
END IF;
TG68_PC_add <= PC_dataa+PC_datab;
IF get_extendedOPC='1' THEN
setstate_mux <= setstate_delay;
ELSE
setstate_mux <= setstate;
END IF;
IF reset = '0' THEN
opcode(15 downto 12) <= X"7"; --moveq
opcode(8 downto 6) <= "010"; --long
TG68_PC <= (others =>'0');
state <= "01";
decodeOPC <= '0';
fetchOPC <= '0';
endOPC <= '0';
interrupt <= '0';
trap_interrupt <= '1';
execOPC <= '0';
getbrief <= '0';
TG68_PC_dec <= "00";
directPC <= '0';
directSR <= '0';
directCCR <= '0';
stop <= '0';
exec_ADD <= '0';
exec_OR <= '0';
exec_AND <= '0';
exec_EOR <= '0';
exec_MOVE <= '0';
exec_MOVEQ <= '0';
exec_MOVESR <= '0';
exec_ADDQ <= '0';
exec_CMP <= '0';
exec_ROT <= '0';
exec_EXT <= '0';
exec_ABCD <= '0';
exec_SBCD <= '0';
exec_MULU <= '0';
exec_DIVU <= '0';
exec_Scc <= '0';
exec_CPMAW <= '0';
mem_byte <= '0';
rot_cnt <="000001";
rot_nop <= '0';
get_extendedOPC <= '0';
get_bitnumber <= '0';
get_movem_mask <= '0';
movepl <= '0';
movepw <= '0';
test_delay <= "000";
PCmarker <= '0';
ELSIF rising_edge(clk) THEN
IF clkena_in='1' THEN
get_extendedOPC <= set_get_extendedOPC;
get_bitnumber <= set_get_bitnumber;
get_movem_mask <= set_get_movem_mask;
setstate_delay <= setstate;
TG68_PC_dec <= TG68_PC_dec(0)&set_TG68_PC_dec;
IF directPC='1' AND clkena='1' THEN
TG68_PC <= data_read;
ELSIF ea_to_pc='1' AND longread='0' THEN
TG68_PC <= memaddr_in;
ELSIF (state ="00" AND TG68_PC_nop='0') OR TG68_PC_br8='1' OR TG68_PC_brw='1' OR TG68_PC_dec(1)='1' THEN
TG68_PC <= TG68_PC_add;
END IF;
IF get_bitnumber='1' THEN
bit_number_reg <= data_read(4 downto 0);
END IF;
IF clkena='1' OR get_extendedOPC='1' THEN
IF set_get_extendedOPC='1' THEN
state <= "00";
ELSIF get_extendedOPC='1' THEN
state <= setstate_mux;
ELSIF fetchOPC='1' OR (state="10" AND write_back='1' AND setstate/="10") OR set_rot_cnt/="000001" OR stop='1' THEN
state <= "01"; --decode cycle, execute cycle
ELSE
state <= setstate_mux;
END IF;
IF setstate_mux(1)='1' AND datatype="00" AND set_get_extendedOPC='0' AND wait_mem_byte='0' THEN
mem_byte <= '1';
ELSE
mem_byte <= '0';
END IF;
END IF;
END IF;
IF clkena='1' THEN
exec_ADD <= '0';
exec_OR <= '0';
exec_AND <= '0';
exec_EOR <= '0';
exec_MOVE <= '0';
exec_MOVEQ <= '0';
exec_MOVESR <= '0';
exec_ADDQ <= '0';
exec_CMP <= '0';
exec_ROT <= '0';
exec_ABCD <= '0';
exec_SBCD <= '0';
fetchOPC <= '0';
exec_CPMAW <= '0';
endOPC <= '0';
interrupt <= '0';
execOPC <= '0';
exec_EXT <= '0';
exec_Scc <= '0';
rot_nop <= '0';
decodeOPC <= fetchOPC;
directPC <= set_directPC;
directSR <= set_directSR;
directCCR <= set_directCCR;
exec_MULU <= set_exec_MULU;
exec_DIVU <= set_exec_DIVU;
movepl <= '0';
movepw <= '0';
stop <= set_stop OR (stop AND NOT interrupt);
IF set_PCmarker='1' THEN
PCmarker <= '1';
ELSIF (state="10" AND longread='0') OR (ea_only='1' AND get_ea_now='1') THEN
PCmarker <= '0';
END IF;
IF (decodeOPC OR execOPC)='1' THEN
rot_cnt <= set_rot_cnt;
END IF;
IF next_micro_state=idle AND setstate_mux="00" AND (setnextpass='0' OR ea_only='1') AND endOPC='0' AND movem_busy='0' AND set_movem_busy='0' AND set_get_bitnumber='0' THEN
nextpass <= '0';
IF (exec_write_back='0' OR state="11") AND set_rot_cnt="000001" THEN
endOPC <= '1';
IF Flags(10 downto 8)<IPL_nr OR IPL_nr="111" THEN
interrupt <= '1';
rIPL_nr <= IPL_nr;
ELSE
IF stop='0' THEN
fetchOPC <= '1';
END IF;
END IF;
END IF;
IF exec_write_back='0' OR state/="11" THEN
IF stop='0' THEN
execOPC <= '1';
END IF;
exec_ADD <= set_exec_ADD;
exec_OR <= set_exec_OR;
exec_AND <= set_exec_AND;
exec_EOR <= set_exec_EOR;
exec_MOVE <= set_exec_MOVE;
exec_MOVEQ <= set_exec_MOVEQ;
exec_MOVESR <= set_exec_MOVESR;
exec_ADDQ <= set_exec_ADDQ;
exec_CMP <= set_exec_CMP;
exec_ROT <= set_exec_ROT;
exec_tas <= set_exec_tas;
exec_EXT <= set_exec_EXT;
exec_ABCD <= set_exec_ABCD;
exec_SBCD <= set_exec_SBCD;
exec_Scc <= set_exec_Scc;
exec_CPMAW <= set_exec_CPMAW;
rot_nop <= set_rot_nop;
END IF;
ELSE
IF endOPC='0' AND (setnextpass='1' OR (regdirectsource='1' AND decodeOPC='1')) THEN
nextpass <= '1';
END IF;
END IF;
IF interrupt='1' THEN
opcode(15 downto 12) <= X"7"; --moveq
opcode(8 downto 6) <= "010"; --long
-- trap_PC <= TG68_PC;
trap_interrupt <= '1';
END IF;
IF fetchOPC='1' THEN
trap_interrupt <= '0';
IF (test_IPL='1' AND (Flags(10 downto 8)<IPL_nr OR IPL_nr="111")) OR to_SR='1' THEN
-- IF (test_IPL='1' AND (Flags(10 downto 8)<IPL_nr OR IPL_nr="111")) OR to_SR='1' OR opcode(15 downto 6)="0100111011" THEN --nur für Validator
opcode <= X"60FE";
IF to_SR='0' THEN
test_delay <= "001";
END IF;
ELSE
opcode <= data_read(15 downto 0);
END IF;
getbrief <= '0';
-- trap_PC <= TG68_PC;
ELSE
test_delay <= test_delay(1 downto 0)&'0';
getbrief <= setgetbrief;
movepl <= set_movepl;
movepw <= set_movepw;
END IF;
IF decodeOPC='1' OR interrupt='1' THEN
trap_SR <= Flags;
END IF;
IF getbrief='1' THEN
brief <= data_read(15 downto 0);
END IF;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- handle EA_data, data_write_tmp
-----------------------------------------------------------------------------
PROCESS (clk, reset, opcode)
BEGIN
IF reset = '0' THEN
set_store_in_tmp <='0';
exec_DIRECT <= '0';
exec_write_back <= '0';
direct_data <= '0';
use_direct_data <= '0';
Z_error <= '0';
ELSIF rising_edge(clk) THEN
IF clkena='1' THEN
direct_data <= '0';
IF endOPC='1' THEN
set_store_in_tmp <='0';
exec_DIRECT <= '0';
exec_write_back <= '0';
use_direct_data <= '0';
Z_error <= '0';
ELSE
IF set_Z_error='1' THEN
Z_error <= '1';
END IF;
exec_DIRECT <= set_exec_MOVE;
IF setstate_mux="10" AND write_back='1' THEN
exec_write_back <= '1';
END IF;
END IF;
IF set_direct_data='1' THEN
direct_data <= '1';
use_direct_data <= '1';
END IF;
IF set_exec_MOVE='1' AND state="11" THEN
use_direct_data <= '1';
END IF;
IF (exec_DIRECT='1' AND state="00" AND getbrief='0' AND endOPC='0') OR state="10" THEN
set_store_in_tmp <= '1';
ea_data <= data_read;
END IF;
IF writePC_add='1' THEN
data_write_tmp <= TG68_PC_add;
ELSIF writePC='1' OR fetchOPC='1' OR interrupt='1' OR (trap_trap='1' AND decodeOPC='1') THEN --fetchOPC für Trap
data_write_tmp <= TG68_PC;
ELSIF execOPC='1' OR (get_ea_now='1' AND ea_only='1') THEN --get_ea_now='1' AND ea_only='1' ist für pea
data_write_tmp <= registerin(31 downto 8)&(registerin(7)OR exec_tas)®isterin(6 downto 0);
ELSIF (exec_DIRECT='1' AND state="10") OR direct_data='1' THEN
data_write_tmp <= data_read;
IF movepl='1' THEN
data_write_tmp(31 downto 8) <= data_write_tmp(23 downto 0);
END IF;
ELSIF (movem_busy='1' AND datatype="10" AND movem_presub='1') OR movepl='1' THEN
data_write_tmp <= OP2out(15 downto 0)&OP2out(31 downto 16);
ELSIF (NOT trapmake AND decodeOPC)='1' OR movem_busy='1' OR movepw='1' THEN
data_write_tmp <= OP2out;
ELSIF writeSR='1'THEN
data_write_tmp(15 downto 0) <= trap_SR(15 downto 8)& Flags(7 downto 0);
END IF;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set dest regaddr
-----------------------------------------------------------------------------
PROCESS (opcode, rf_dest_addr_tmp, to_USP, Flags, trapmake, movem_addr, movem_presub, movem_regaddr, setbriefext, brief, setstackaddr, dest_hbits, dest_areg, data_is_source)
BEGIN
rf_dest_addr <= rf_dest_addr_tmp;
IF rf_dest_addr_tmp(3 downto 0)="1111" AND to_USP='0' THEN
rf_dest_addr(4) <= Flags(13) OR trapmake;
END IF;
IF movem_addr='1' THEN
IF movem_presub='1' THEN
rf_dest_addr_tmp <= "000"&(movem_regaddr XOR "1111");
ELSE
rf_dest_addr_tmp <= "000"&movem_regaddr;
END IF;
ELSIF setbriefext='1' THEN
rf_dest_addr_tmp <= ("000"&brief(15 downto 12));
ELSIF setstackaddr='1' THEN
rf_dest_addr_tmp <= "0001111";
ELSIF dest_hbits='1' THEN
rf_dest_addr_tmp <= "000"&dest_areg&opcode(11 downto 9);
ELSE
IF opcode(5 downto 3)="000" OR data_is_source='1' THEN
rf_dest_addr_tmp <= "000"&dest_areg&opcode(2 downto 0);
ELSE
rf_dest_addr_tmp <= "0001"&opcode(2 downto 0);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set OP1
-----------------------------------------------------------------------------
PROCESS (reg_QA, OP1out_zero, from_SR, Flags, ea_data_OP1, set_store_in_tmp, ea_data)
BEGIN
OP1out <= reg_QA;
IF OP1out_zero='1' THEN
OP1out <= (OTHERS => '0');
ELSIF from_SR='1' THEN
OP1out(15 downto 0) <= Flags;
ELSIF ea_data_OP1='1' AND set_store_in_tmp='1' THEN
OP1out <= ea_data;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set source regaddr
-----------------------------------------------------------------------------
PROCESS (opcode, Flags, movem_addr, movem_presub, movem_regaddr, source_lowbits, source_areg, from_USP, rf_source_addr_tmp)
BEGIN
rf_source_addr <= rf_source_addr_tmp;
IF rf_source_addr_tmp(3 downto 0)="1111" AND from_USP='0' THEN
rf_source_addr(4) <= Flags(13);
END IF;
IF movem_addr='1' THEN
IF movem_presub='1' THEN
rf_source_addr_tmp <= "000"&(movem_regaddr XOR "1111");
ELSE
rf_source_addr_tmp <= "000"&movem_regaddr;
END IF;
ELSIF from_USP='1' THEN
rf_source_addr_tmp <= "0001111";
ELSIF source_lowbits='1' THEN
rf_source_addr_tmp <= "000"&source_areg&opcode(2 downto 0);
ELSE
rf_source_addr_tmp <= "000"&source_areg&opcode(11 downto 9);
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set OP2
-----------------------------------------------------------------------------
PROCESS (OP2out, reg_QB, opcode, datatype, OP2out_one, exec_EXT, exec_MOVEQ, EXEC_ADDQ, use_direct_data, data_write_tmp,
ea_data_OP1, set_store_in_tmp, ea_data, movepl)
BEGIN
OP2out(15 downto 0) <= reg_QB(15 downto 0);
OP2out(31 downto 16) <= (OTHERS => OP2out(15));
IF OP2out_one='1' THEN
OP2out(15 downto 0) <= "1111111111111111";
ELSIF exec_EXT='1' THEN
IF opcode(6)='0' THEN --ext.w
OP2out(15 downto 8) <= (OTHERS => OP2out(7));
END IF;
ELSIF use_direct_data='1' THEN
OP2out <= data_write_tmp;
ELSIF ea_data_OP1='0' AND set_store_in_tmp='1' THEN
OP2out <= ea_data;
ELSIF exec_MOVEQ='1' THEN
OP2out(7 downto 0) <= opcode(7 downto 0);
OP2out(15 downto 8) <= (OTHERS => opcode(7));
ELSIF exec_ADDQ='1' THEN
OP2out(2 downto 0) <= opcode(11 downto 9);
IF opcode(11 downto 9)="000" THEN
OP2out(3) <='1';
ELSE
OP2out(3) <='0';
END IF;
OP2out(15 downto 4) <= (OTHERS => '0');
ELSIF datatype="10" OR movepl='1' THEN
OP2out(31 downto 16) <= reg_QB(31 downto 16);
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- addsub
-----------------------------------------------------------------------------
PROCESS (OP1out, OP2out, presub, postadd, execOPC, OP2out_one, datatype, use_SP, use_XZFlag, use_XFlag, Flags, setaddsub)
BEGIN
addsub_a <= OP1out;
addsub_b <= OP2out;
addsub <= NOT presub;
c_in(0) <='0';
IF execOPC='0' AND OP2out_one='0' THEN
IF datatype="00" AND use_SP='0' THEN
addsub_b <= "00000000000000000000000000000001";
ELSIF datatype="10" AND (presub OR postadd)='1' THEN
addsub_b <= "00000000000000000000000000000100";
ELSE
addsub_b <= "00000000000000000000000000000010";
END IF;
ELSE
IF (use_XZFlag='1' OR use_XFlag='1') AND Flags(4)='1' THEN
c_in(0) <= '1';
END IF;
addsub <= setaddsub;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- Write Reg
-----------------------------------------------------------------------------
PROCESS (clkena, OP1in, datatype, presub, postadd, endOPC, regwrena, state, execOPC, last_data_read, movem_addr, rf_dest_addr, reg_QA)
BEGIN
Lwrena <= '0';
Hwrena <= '0';
registerin <= OP1in;
IF (presub='1' OR postadd='1') AND endOPC='0' THEN -- -(An)+
Hwrena <= '1';
Lwrena <= '1';
ELSIF Regwrena='1' THEN --read (mem)
Lwrena <= '1';
CASE datatype IS
WHEN "00" => --BYTE
registerin(15 downto 8) <= reg_QA(15 downto 8);
WHEN "01" => --WORD
IF rf_dest_addr(3)='1' OR movem_addr='1' THEN
Hwrena <='1';
END IF;
WHEN OTHERS => --LONG
Hwrena <= '1';
END CASE;
END IF;
END PROCESS;
------------------------------------------------------------------------------
--ALU
------------------------------------------------------------------------------
PROCESS (opcode, OP1in, OP1out, OP2out, datatype, c_out, exec_ABCD, exec_SBCD, exec_CPMAW, exec_MOVESR, bits_out, Flags, flag_z, use_XZFlag, addsub_ofl,
dummy_s, dummy_a, niba_hc, niba_h, niba_l, niba_lc, nibs_hc, nibs_h, nibs_l, nibs_lc, addsub_q, movem_addr, data_read, exec_MULU, exec_DIVU, exec_OR,
exec_AND, exec_Scc, exec_EOR, exec_MOVE, exec_exg, exec_ROT, execOPC, exec_swap, exec_Bits, rot_out, dummy_mulu, dummy_div, save_memaddr, memaddr,
memaddr_in, ea_only, get_ea_now)
BEGIN
--BCD_ARITH-------------------------------------------------------------------
--ADC
dummy_a <= niba_hc&(niba_h(4 downto 1)+('0',niba_hc,niba_hc,'0'))&(niba_l(4 downto 1)+('0',niba_lc,niba_lc,'0'));
niba_l <= ('0'&OP1out(3 downto 0)&'1') + ('0'&OP2out(3 downto 0)&Flags(4));
niba_lc <= niba_l(5) OR (niba_l(4) AND niba_l(3)) OR (niba_l(4) AND niba_l(2));
niba_h <= ('0'&OP1out(7 downto 4)&'1') + ('0'&OP2out(7 downto 4)&niba_lc);
niba_hc <= niba_h(5) OR (niba_h(4) AND niba_h(3)) OR (niba_h(4) AND niba_h(2));
--SBC
dummy_s <= nibs_hc&(nibs_h(4 downto 1)-('0',nibs_hc,nibs_hc,'0'))&(nibs_l(4 downto 1)-('0',nibs_lc,nibs_lc,'0'));
nibs_l <= ('0'&OP1out(3 downto 0)&'0') - ('0'&OP2out(3 downto 0)&Flags(4));
nibs_lc <= nibs_l(5);
nibs_h <= ('0'&OP1out(7 downto 4)&'0') - ('0'&OP2out(7 downto 4)&nibs_lc);
nibs_hc <= nibs_h(5);
------------------------------------------------------------------------------
flag_z <= "000";
OP1in <= addsub_q;
IF movem_addr='1' THEN
OP1in <= data_read;
ELSIF exec_ABCD='1' THEN
OP1in(7 downto 0) <= dummy_a(7 downto 0);
ELSIF exec_SBCD='1' THEN
OP1in(7 downto 0) <= dummy_s(7 downto 0);
ELSIF exec_MULU='1' THEN
OP1in <= dummy_mulu;
ELSIF exec_DIVU='1' AND execOPC='1' THEN
OP1in <= dummy_div;
ELSIF exec_OR='1' THEN
OP1in <= OP2out OR OP1out;
ELSIF exec_AND='1' OR exec_Scc='1' THEN
OP1in <= OP2out AND OP1out;
ELSIF exec_EOR='1' THEN
OP1in <= OP2out XOR OP1out;
ELSIF exec_MOVE='1' OR exec_exg='1' THEN
OP1in <= OP2out;
ELSIF exec_ROT='1' THEN
OP1in <= rot_out;
ELSIF save_memaddr='1' THEN
OP1in <= memaddr;
ELSIF get_ea_now='1' AND ea_only='1' THEN
OP1in <= memaddr_in;
ELSIF exec_swap='1' THEN
OP1in <= OP1out(15 downto 0)& OP1out(31 downto 16);
ELSIF exec_bits='1' THEN
OP1in <= bits_out;
ELSIF exec_MOVESR='1' THEN
OP1in(15 downto 0) <= Flags;
END IF;
IF use_XZFlag='1' AND flags(2)='0' THEN
flag_z <= "000";
ELSIF OP1in(7 downto 0)="00000000" THEN
flag_z(0) <= '1';
IF OP1in(15 downto 8)="00000000" THEN
flag_z(1) <= '1';
IF OP1in(31 downto 16)="0000000000000000" THEN
flag_z(2) <= '1';
END IF;
END IF;
END IF;
-- --Flags NZVC
IF datatype="00" THEN --Byte
set_flags <= OP1IN(7)&flag_z(0)&addsub_ofl(0)&c_out(0);
IF exec_ABCD='1' THEN
set_flags(0) <= dummy_a(8);
ELSIF exec_SBCD='1' THEN
set_flags(0) <= dummy_s(8);
END IF;
ELSIF datatype="10" OR exec_CPMAW='1' THEN --Long
set_flags <= OP1IN(31)&flag_z(2)&addsub_ofl(2)&c_out(2);
ELSE --Word
set_flags <= OP1IN(15)&flag_z(1)&addsub_ofl(1)&c_out(1);
END IF;
END PROCESS;
------------------------------------------------------------------------------
--Flags
------------------------------------------------------------------------------
PROCESS (clk, reset, opcode)
BEGIN
IF reset='0' THEN
Flags(13) <= '1';
SVmode <= '1';
Flags(10 downto 8) <= "111";
ELSIF rising_edge(clk) THEN
IF clkena = '1' THEN
IF directSR='1' THEN
Flags <= data_read(15 downto 0);
END IF;
IF directCCR='1' THEN
Flags(7 downto 0) <= data_read(7 downto 0);
END IF;
IF interrupt='1' THEN
Flags(10 downto 8) <=rIPL_nr;
SVmode <= '1';
END IF;
IF writeSR='1' OR interrupt='1' THEN
Flags(13) <='1';
END IF;
IF endOPC='1' AND to_SR='0' THEN
SVmode <= Flags(13);
END IF;
IF execOPC='1' AND to_SR='1' THEN
Flags(7 downto 0) <= OP1in(7 downto 0); --CCR
IF datatype="01" AND (opcode(14)='0' OR opcode(9)='1') THEN --move to CCR wird als word gespeichert
Flags(15 downto 8) <= OP1in(15 downto 8); --SR
SVmode <= OP1in(13);
END IF;
ELSIF Z_error='1' THEN
IF opcode(8)='0' THEN
Flags(3 downto 0) <= "1000";
ELSE
Flags(3 downto 0) <= "0100";
END IF;
ELSIF no_Flags='0' AND trapmake='0' THEN
IF exec_ADD='1' THEN
Flags(4) <= set_flags(0);
ELSIF exec_ROT='1' AND rot_bits/="11" AND rot_nop='0' THEN
Flags(4) <= rot_XC;
END IF;
IF (exec_ADD OR exec_CMP)='1' THEN
Flags(3 downto 0) <= set_flags;
ELSIF decodeOPC='1' and set_exec_ROT='1' THEN
Flags(1) <= '0';
ELSIF exec_DIVU='1' THEN
IF set_V_Flag='1' THEN
Flags(3 downto 0) <= "1010";
ELSE
Flags(3 downto 0) <= OP1IN(15)&flag_z(1)&"00";
END IF;
ELSIF exec_OR='1' OR exec_AND='1' OR exec_EOR='1' OR exec_MOVE='1' OR exec_swap='1' OR exec_MULU='1' THEN
Flags(3 downto 0) <= set_flags(3 downto 2)&"00";
ELSIF exec_ROT='1' THEN
Flags(3 downto 2) <= set_flags(3 downto 2);
Flags(0) <= rot_XC;
IF rot_bits="00" THEN --ASL/ASR
Flags(1) <= ((set_flags(3) XOR rot_rot) OR Flags(1));
END IF;
ELSIF exec_bits='1' THEN
Flags(2) <= NOT one_bit_in;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- execute opcode
-----------------------------------------------------------------------------
PROCESS (clk, reset, OP2out, opcode, fetchOPC, decodeOPC, execOPC, endOPC, nextpass, condition, set_V_flag, trapmake, trapd, interrupt, trap_interrupt,
Z_error, c_in, rot_cnt, one_bit_in, bit_number_reg, bit_number, ea_only, get_ea_now, ea_build, datatype, exec_write_back, get_extendedOPC,
Flags, SVmode, movem_addr, movem_busy, getbrief, set_exec_AND, set_exec_OR, set_exec_EOR, TG68_PC_dec, c_out, OP1out, micro_state)
BEGIN
TG68_PC_br8 <= '0';
TG68_PC_brw <= '0';
TG68_PC_nop <= '0';
setstate <= "00";
Regwrena <= '0';
postadd <= '0';
presub <= '0';
movem_presub <= '0';
setaddsub <= '1';
setaddrlong <= '0';
setnextpass <= '0';
regdirectsource <= '0';
setdisp <= '0';
setdispbyte <= '0';
setdispbrief <= '0';
setbriefext <= '0';
setgetbrief <= '0';
longreaddirect <= '0';
dest_areg <= '0';
source_areg <= '0';
data_is_source <= '0';
write_back <= '0';
setstackaddr <= '0';
writePC <= '0';
writePC_add <= '0';
set_TG68_PC_dec <= '0';
set_directPC <= '0';
set_exec_ADD <= '0';
set_exec_OR <= '0';
set_exec_AND <= '0';
set_exec_EOR <= '0';
set_exec_MOVE <= '0';
set_exec_MOVEQ <= '0';
set_exec_MOVESR <= '0';
set_exec_ADDQ <= '0';
set_exec_CMP <= '0';
set_exec_ROT <= '0';
set_exec_EXT <= '0';
set_exec_CPMAW <= '0';
OP2out_one <= '0';
ea_to_pc <= '0';
ea_build <= '0';
get_ea_now <= '0';
rot_bits <= "XX";
set_rot_nop <= '0';
set_rot_cnt <= "000001";
set_movem_busy <= '0';
set_get_movem_mask <= '0';
save_memaddr <= '0';
set_mem_addsub <= '0';
exec_exg <= '0';
exec_swap <= '0';
exec_Bits <= '0';
set_get_bitnumber <= '0';
dest_hbits <= '0';
source_lowbits <= '0';
set_mem_rega <= '0';
ea_data_OP1 <= '0';
ea_only <= '0';
set_direct_data <= '0';
set_get_extendedOPC <= '0';
set_exec_tas <= '0';
OP1out_zero <= '0';
use_XZFlag <= '0';
use_XFlag <= '0';
set_exec_ABCD <= '0';
set_exec_SBCD <= '0';
set_exec_MULU <= '0';
set_exec_DIVU <= '0';
set_exec_Scc <= '0';
trap_illegal <='0';
trap_priv <='0';
trap_1010 <='0';
trap_1111 <='0';
trap_trap <='0';
trap_trapv <= '0';
trapmake <='0';
set_vectoraddr <='0';
writeSR <= '0';
set_directSR <= '0';
set_directCCR <= '0';
set_stop <= '0';
from_SR <= '0';
to_SR <= '0';
from_USP <= '0';
to_USP <= '0';
illegal_write_mode <= '0';
illegal_read_mode <= '0';
illegal_byteaddr <= '0';
no_Flags <= '0';
set_PCmarker <= '0';
use_SP <= '0';
set_Z_error <= '0';
wait_mem_byte <= '0';
set_movepl <= '0';
set_movepw <= '0';
trap_chk <= '0';
next_micro_state <= idle;
------------------------------------------------------------------------------
--Sourcepass
------------------------------------------------------------------------------
IF ea_only='0' AND get_ea_now='1' THEN
setstate <= "10";
END IF;
IF ea_build='1' THEN
CASE opcode(5 downto 3) IS --source
WHEN "010"|"011"|"100" => -- -(An)+
get_ea_now <='1';
setnextpass <= '1';
IF opcode(4)='1' THEN
set_mem_rega <= '1';
ELSE
set_mem_addsub <= '1';
END IF;
IF opcode(3)='1' THEN --(An)+
postadd <= '1';
IF opcode(2 downto 0)="111" THEN
use_SP <= '1';
END IF;
END IF;
IF opcode(5)='1' THEN -- -(An)
presub <= '1';
IF opcode(2 downto 0)="111" THEN
use_SP <= '1';
END IF;
END IF;
IF opcode(4 downto 3)/="10" THEN
regwrena <= '1';
END IF;
WHEN "101" => --(d16,An)
next_micro_state <= ld_dAn1;
setgetbrief <='1';
set_mem_regA <= '1';
WHEN "110" => --(d8,An,Xn)
next_micro_state <= ld_AnXn1;
setgetbrief <='1';
set_mem_regA <= '1';
WHEN "111" =>
CASE opcode(2 downto 0) IS
WHEN "000" => --(xxxx).w
next_micro_state <= ld_nn;
WHEN "001" => --(xxxx).l
longreaddirect <= '1';
next_micro_state <= ld_nn;
WHEN "010" => --(d16,PC)
next_micro_state <= ld_dAn1;
setgetbrief <= '1';
set_PCmarker <= '1';
WHEN "011" => --(d8,PC,Xn)
next_micro_state <= ld_AnXn1;
setgetbrief <= '1';
set_PCmarker <= '1';
WHEN "100" => --#data
setnextpass <= '1';
set_direct_data <= '1';
IF datatype="10" THEN
longreaddirect <= '1';
END IF;
WHEN OTHERS =>
END CASE;
WHEN OTHERS =>
END CASE;
END IF;
------------------------------------------------------------------------------
--prepere opcode
------------------------------------------------------------------------------
CASE opcode(7 downto 6) IS
WHEN "00" => datatype <= "00"; --Byte
WHEN "01" => datatype <= "01"; --Word
WHEN OTHERS => datatype <= "10"; --Long
END CASE;
IF execOPC='1' AND endOPC='0' AND exec_write_back='1' THEN
setstate <="11";
END IF;
------------------------------------------------------------------------------
--test illegal mode
------------------------------------------------------------------------------
IF (opcode(5 downto 3)="111" AND opcode(2 downto 1)/="00") OR (opcode(5 downto 3)="001" AND datatype="00") THEN
illegal_write_mode <= '1';
END IF;
IF (opcode(5 downto 2)="1111" AND opcode(1 downto 0)/="00") OR (opcode(5 downto 3)="001" AND datatype="00") THEN
illegal_read_mode <= '1';
END IF;
IF opcode(5 downto 3)="001" AND datatype="00" THEN
illegal_byteaddr <= '1';
END IF;
CASE opcode(15 downto 12) IS
-- 0000 ----------------------------------------------------------------------------
WHEN "0000" =>
IF opcode(8)='1' AND opcode(5 downto 3)="001" THEN --movep
datatype <= "00"; --Byte
use_SP <= '1';
no_Flags <='1';
IF opcode(7)='0' THEN
set_exec_move <= '1';
set_movepl <= '1';
END IF;
IF decodeOPC='1' THEN
IF opcode(7)='0' THEN
set_direct_data <= '1';
END IF;
next_micro_state <= movep1;
setgetbrief <='1';
set_mem_regA <= '1';
END IF;
IF opcode(7)='0' AND endOPC='1' THEN
IF opcode(6)='1' THEN
datatype <= "10"; --Long
ELSE
datatype <= "01"; --Word
END IF;
dest_hbits <='1';
regwrena <= '1';
END IF;
ELSE
IF opcode(8)='1' OR opcode(11 downto 8)="1000" THEN --Bits
IF execOPC='1' AND get_extendedOPC='0' THEN
IF opcode(7 downto 6)/="00" AND endOPC='1' THEN
regwrena <= '1';
END IF;
exec_Bits <= '1';
ea_data_OP1 <= '1';
END IF;
-- IF get_extendedOPC='1' THEN
-- datatype <= "01"; --Word
-- ELS
IF opcode(5 downto 4)="00" THEN
datatype <= "10"; --Long
ELSE
datatype <= "00"; --Byte
IF opcode(7 downto 6)/="00" THEN
write_back <= '1';
END IF;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
IF opcode(8)='0' THEN
IF opcode(5 downto 4)/="00" THEN --Dn, An
set_get_extendedOPC <= '1';
END IF;
set_get_bitnumber <= '1';
END IF;
END IF;
ELSE --andi, ...xxxi
IF opcode(11 downto 8)="0000" THEN --ORI
set_exec_OR <= '1';
END IF;
IF opcode(11 downto 8)="0010" THEN --ANDI
set_exec_AND <= '1';
END IF;
IF opcode(11 downto 8)="0100" OR opcode(11 downto 8)="0110" THEN --SUBI, ADDI
set_exec_ADD <= '1';
END IF;
IF opcode(11 downto 8)="1010" THEN --EORI
set_exec_EOR <= '1';
END IF;
IF opcode(11 downto 8)="1100" THEN --CMPI
set_exec_CMP <= '1';
ELSIF trapmake='0' THEN
write_back <= '1';
END IF;
IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (set_exec_AND OR set_exec_OR OR set_exec_EOR)='1' THEN --SR
-- IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (opcode(11 downto 8)="0010" OR opcode(11 downto 8)="0000" OR opcode(11 downto 8)="1010") THEN --SR
IF SVmode='0' AND opcode(6)='1' THEN --SR
trap_priv <= '1';
trapmake <= '1';
ELSE
from_SR <= '1';
to_SR <= '1';
IF decodeOPC='1' THEN
setnextpass <= '1';
set_direct_data <= '1';
END IF;
END IF;
ELSE
IF decodeOPC='1' THEN
IF opcode(11 downto 8)="0010" OR opcode(11 downto 8)="0000" OR opcode(11 downto 8)="0100" --ANDI, ORI, SUBI
OR opcode(11 downto 8)="0110" OR opcode(11 downto 8)="1010" OR opcode(11 downto 8)="1100" THEN --ADDI, EORI, CMPI
-- IF (set_exec_AND OR set_exec_OR OR set_exec_ADD --ANDI, ORI, SUBI
-- OR set_exec_EOR OR set_exec_CMP)='1' THEN --ADDI, EORI, CMPI
next_micro_state <= andi;
set_direct_data <= '1';
IF datatype="10" THEN
longreaddirect <= '1';
END IF;
END IF;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
IF opcode(11 downto 8)/="1100" THEN --CMPI
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
IF opcode(11 downto 8)="1100" OR opcode(11 downto 8)="0100" THEN --CMPI, SUBI
setaddsub <= '0';
END IF;
END IF;
END IF;
END IF;
END IF;
-- 0001, 0010, 0011 -----------------------------------------------------------------
WHEN "0001"|"0010"|"0011" => --move.b, move.l, move.w
set_exec_MOVE <= '1';
IF opcode(8 downto 6)="001" THEN
no_Flags <= '1';
END IF;
IF opcode(5 downto 4)="00" THEN --Dn, An
regdirectsource <= '1';
END IF;
CASE opcode(13 downto 12) IS
WHEN "01" => datatype <= "00"; --Byte
WHEN "10" => datatype <= "10"; --Long
WHEN OTHERS => datatype <= "01"; --Word
END CASE;
source_lowbits <= '1'; -- Dn=> An=>
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
IF getbrief='1' AND nextpass='1' THEN -- =>(d16,An) =>(d8,An,Xn)
set_mem_rega <= '1';
END IF;
IF execOPC='1' AND opcode(8 downto 7)="00" THEN
Regwrena <= '1';
END IF;
IF nextpass='1' OR execOPC='1' OR opcode(5 downto 4)="00" THEN
dest_hbits <= '1';
IF opcode(8 downto 6)/="000" THEN
dest_areg <= '1';
END IF;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF micro_state=idle AND (nextpass='1' OR (opcode(5 downto 4)="00" AND decodeOPC='1')) THEN
CASE opcode(8 downto 6) IS --destination
-- WHEN "000" => --Dn
-- WHEN "001" => --An
WHEN "010"|"011"|"100" => --destination -(an)+
IF opcode(7)='1' THEN
set_mem_rega <= '1';
ELSE
set_mem_addsub <= '1';
END IF;
IF opcode(6)='1' THEN --(An)+
postadd <= '1';
IF opcode(11 downto 9)="111" THEN
use_SP <= '1';
END IF;
END IF;
IF opcode(8)='1' THEN -- -(An)
presub <= '1';
IF opcode(11 downto 9)="111" THEN
use_SP <= '1';
END IF;
END IF;
IF opcode(7 downto 6)/="10" THEN
regwrena <= '1';
END IF;
setstate <= "11";
next_micro_state <= nop;
WHEN "101" => --(d16,An)
next_micro_state <= st_dAn1;
set_mem_regA <= '1';
setgetbrief <= '1';
WHEN "110" => --(d8,An,Xn)
next_micro_state <= st_AnXn1;
set_mem_regA <= '1';
setgetbrief <= '1';
WHEN "111" =>
CASE opcode(11 downto 9) IS
WHEN "000" => --(xxxx).w
next_micro_state <= st_nn;
WHEN "001" => --(xxxx).l
longreaddirect <= '1';
next_micro_state <= st_nn;
WHEN OTHERS =>
END CASE;
WHEN OTHERS =>
END CASE;
END IF;
-- 0100 ----------------------------------------------------------------------------
WHEN "0100" => --rts_group
IF opcode(8)='1' THEN --lea
IF opcode(6)='1' THEN --lea
IF opcode(7)='1' THEN
ea_only <= '1';
IF opcode(5 downto 3)="010" THEN --lea (Am),An
set_exec_move <='1';
no_Flags <='1';
dest_areg <= '1';
dest_hbits <= '1';
source_lowbits <= '1';
source_areg <= '1';
IF execOPC='1' THEN
Regwrena <= '1';
END IF;
ELSE
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
END IF;
IF get_ea_now='1' THEN
dest_areg <= '1';
dest_hbits <= '1';
regwrena <= '1';
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSE --chk
IF opcode(7)='1' THEN
set_exec_ADD <= '1';
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
datatype <= "01"; --Word
IF execOPC='1' THEN
setaddsub <= '0';
--first alternative
ea_data_OP1 <= '1';
IF c_out(1)='1' OR OP1out(15)='1' OR OP2out(15)='1' THEN
-- trap_chk <= '1'; --first I must change the Trap System
-- trapmake <= '1';
END IF;
--second alternative
-- IF (c_out(1)='0' AND flag_z(1)='0') OR OP1out(15)='1' OR OP2out(15)='1' THEN
-- -- trap_chk <= '1'; --first I must change the Trap System
-- -- trapmake <= '1';
-- END IF;
-- dest_hbits <= '1';
-- source_lowbits <='1';
END IF;
ELSE
trap_illegal <= '1'; -- chk long for 68020
trapmake <= '1';
END IF;
END IF;
ELSE
CASE opcode(11 downto 9) IS
WHEN "000"=>
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(7 downto 6)="11" THEN --move from SR
set_exec_MOVESR <= '1';
datatype <= "01";
write_back <='1'; -- im 68000 wird auch erst gelesen
IF execOPC='1' THEN
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
ELSE --negx
use_XFlag <= '1';
write_back <='1';
set_exec_ADD <= '1';
setaddsub <='0';
IF execOPC='1' THEN
source_lowbits <= '1';
OP1out_zero <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
WHEN "001"=>
IF opcode(7 downto 6)="11" THEN --move from CCR 68010
trap_illegal <= '1';
trapmake <= '1';
ELSE --clr
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
write_back <='1';
set_exec_AND <= '1';
IF execOPC='1' THEN
OP1out_zero <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
WHEN "010"=>
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(7 downto 6)="11" THEN --move to CCR
set_exec_MOVE <= '1';
datatype <= "01";
IF execOPC='1' THEN
source_lowbits <= '1';
to_SR <= '1';
END IF;
ELSE --neg
write_back <='1';
set_exec_ADD <= '1';
setaddsub <='0';
IF execOPC='1' THEN
source_lowbits <= '1';
OP1out_zero <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
WHEN "011"=> --not, move toSR
IF opcode(7 downto 6)="11" THEN --move to SR
IF SVmode='1' THEN
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
set_exec_MOVE <= '1';
datatype <= "01";
IF execOPC='1' THEN
source_lowbits <= '1';
to_SR <= '1';
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
ELSE --not
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
write_back <='1';
set_exec_EOR <= '1';
IF execOPC='1' THEN
OP2out_one <= '1';
ea_data_OP1 <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
WHEN "100"|"110"=>
IF opcode(7)='1' THEN --movem, ext
IF opcode(5 downto 3)="000" AND opcode(10)='0' THEN --ext
source_lowbits <= '1';
IF decodeOPC='1' THEN
set_exec_EXT <= '1';
set_exec_move <= '1';
END IF;
IF opcode(6)='0' THEN
datatype <= "01"; --WORD
END IF;
IF execOPC='1' THEN
regwrena <= '1';
END IF;
ELSE --movem
-- IF opcode(11 downto 7)="10001" OR opcode(11 downto 7)="11001" THEN --MOVEM
ea_only <= '1';
IF decodeOPC='1' THEN
datatype <= "01"; --Word
set_get_movem_mask <='1';
set_get_extendedOPC <='1';
IF opcode(5 downto 3)="010" OR opcode(5 downto 3)="011" OR opcode(5 downto 3)="100" THEN
set_mem_rega <= '1';
setstate <= "01";
IF opcode(10)='0' THEN
set_movem_busy <='1';
ELSE
next_micro_state <= movem;
END IF;
ELSE
ea_build <= '1';
END IF;
ELSE
IF opcode(6)='0' THEN
datatype <= "01"; --Word
END IF;
END IF;
IF execOPC='1' THEN
IF opcode(5 downto 3)="100" OR opcode(5 downto 3)="011" THEN
regwrena <= '1';
save_memaddr <= '1';
END IF;
END IF;
IF get_ea_now='1' THEN
set_movem_busy <= '1';
IF opcode(10)='0' THEN
setstate <="01";
ELSE
setstate <="10";
END IF;
END IF;
IF opcode(5 downto 3)="100" THEN
movem_presub <= '1';
END IF;
IF movem_addr='1' THEN
IF opcode(10)='1' THEN
regwrena <= '1';
END IF;
END IF;
IF movem_busy='1' THEN
IF opcode(10)='0' THEN
setstate <="11";
ELSE
setstate <="10";
END IF;
END IF;
END IF;
ELSE
IF opcode(10)='1' THEN --MUL, DIV 68020
trap_illegal <= '1';
trapmake <= '1';
ELSE --pea, swap
IF opcode(6)='1' THEN
datatype <= "10";
IF opcode(5 downto 3)="000" THEN --swap
IF execOPC='1' THEN
exec_swap <= '1';
regwrena <= '1';
END IF;
ELSIF opcode(5 downto 3)="001" THEN --bkpt
ELSE --pea
ea_only <= '1';
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF nextpass='1' AND micro_state=idle THEN
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <="11";
next_micro_state <= nop;
END IF;
IF get_ea_now='1' THEN
setstate <="01";
END IF;
END IF;
ELSE --nbcd
IF decodeOPC='1' THEN --nbcd
ea_build <= '1';
END IF;
use_XFlag <= '1';
write_back <='1';
set_exec_ADD <= '1';
set_exec_SBCD <= '1';
IF execOPC='1' THEN
source_lowbits <= '1';
OP1out_zero <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
END IF;
END IF;
WHEN "101"=> --tst, tas
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' THEN
dest_hbits <= '1'; --for Flags
source_lowbits <= '1';
-- IF opcode(3)='1' THEN --MC68020...
-- source_areg <= '1';
-- END IF;
END IF;
set_exec_MOVE <= '1';
IF opcode(7 downto 6)="11" THEN --tas
set_exec_tas <= '1';
write_back <= '1';
datatype <= "00"; --Byte
IF execOPC='1' AND endOPC='1' THEN
regwrena <= '1';
END IF;
END IF;
-- WHEN "110"=>
WHEN "111"=> --4EXX
IF opcode(7)='1' THEN --jsr, jmp
datatype <= "10";
ea_only <= '1';
IF nextpass='1' AND micro_state=idle THEN
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <="11";
next_micro_state <= nop;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF get_ea_now='1' THEN --jsr
IF opcode(6)='0' THEN
setstate <="01";
END IF;
ea_to_pc <= '1';
IF opcode(5 downto 1)="11100" THEN
writePC_add <= '1';
ELSE
writePC <= '1';
END IF;
END IF;
ELSE --
CASE opcode(6 downto 0) IS
WHEN "1000000"|"1000001"|"1000010"|"1000011"|"1000100"|"1000101"|"1000110"|"1000111"| --trap
"1001000"|"1001001"|"1001010"|"1001011"|"1001100"|"1001101"|"1001110"|"1001111" => --trap
trap_trap <='1';
trapmake <= '1';
WHEN "1010000"|"1010001"|"1010010"|"1010011"|"1010100"|"1010101"|"1010110"|"1010111" => --link
datatype <= "10";
IF decodeOPC='1' THEN
next_micro_state <= link;
set_exec_MOVE <= '1'; --für displacement
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
source_lowbits <= '1';
source_areg <= '1';
END IF;
IF execOPC='1' THEN
setstackaddr <='1';
regwrena <= '1';
END IF;
WHEN "1011000"|"1011001"|"1011010"|"1011011"|"1011100"|"1011101"|"1011110"|"1011111" => --unlink
datatype <= "10";
IF decodeOPC='1' THEN
setstate <= "10";
set_mem_rega <= '1';
ELSIF execOPC='1' THEN
regwrena <= '1';
exec_exg <= '1';
ELSE
setstackaddr <='1';
regwrena <= '1';
get_ea_now <= '1';
ea_only <= '1';
END IF;
WHEN "1100000"|"1100001"|"1100010"|"1100011"|"1100100"|"1100101"|"1100110"|"1100111" => --move An,USP
IF SVmode='1' THEN
no_Flags <= '1';
to_USP <= '1';
setstackaddr <= '1';
source_lowbits <= '1';
source_areg <= '1';
set_exec_MOVE <= '1';
datatype <= "10";
IF execOPC='1' THEN
regwrena <= '1';
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1101000"|"1101001"|"1101010"|"1101011"|"1101100"|"1101101"|"1101110"|"1101111" => --move USP,An
IF SVmode='1' THEN
no_Flags <= '1';
from_USP <= '1';
set_exec_MOVE <= '1';
datatype <= "10";
IF execOPC='1' THEN
regwrena <= '1';
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1110000" => --reset
IF SVmode='0' THEN
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1110001" => --nop
WHEN "1110010" => --stop
IF SVmode='0' THEN
trap_priv <= '1';
trapmake <= '1';
ELSE
IF decodeOPC='1' THEN
setnextpass <= '1';
set_directSR <= '1';
set_stop <= '1';
END IF;
END IF;
WHEN "1110011" => --rte
IF SVmode='1' THEN
IF decodeOPC='1' THEN
datatype <= "01";
setstate <= "10";
postadd <= '1';
setstackaddr <= '1';
set_mem_rega <= '1';
set_directSR <= '1';
next_micro_state <= rte;
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1110101" => --rts
IF decodeOPC='1' THEN
datatype <= "10";
setstate <= "10";
postadd <= '1';
setstackaddr <= '1';
set_mem_rega <= '1';
set_directPC <= '1';
next_micro_state <= nop;
END IF;
WHEN "1110110" => --trapv
IF Flags(1)='1' THEN
trap_trapv <= '1';
trapmake <= '1';
END IF;
WHEN "1110111" => --rtr
IF decodeOPC='1' THEN
datatype <= "01";
setstate <= "10";
postadd <= '1';
setstackaddr <= '1';
set_mem_rega <= '1';
set_directCCR <= '1';
next_micro_state <= rte;
END IF;
WHEN OTHERS =>
trap_illegal <= '1';
trapmake <= '1';
END CASE;
END IF;
WHEN OTHERS => null;
END CASE;
END IF;
-- 0101 ----------------------------------------------------------------------------
WHEN "0101" => --subq, addq
IF opcode(7 downto 6)="11" THEN --dbcc
IF opcode(5 downto 3)="001" THEN --dbcc
datatype <= "01"; --Word
IF decodeOPC='1' THEN
next_micro_state <= nop;
OP2out_one <= '1';
IF condition='0' THEN
Regwrena <= '1';
IF c_in(2)='1' THEN
next_micro_state <= dbcc1;
END IF;
END IF;
data_is_source <= '1';
END IF;
ELSE --Scc
datatype <= "00"; --Byte
write_back <= '1';
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF condition='0' THEN
set_exec_Scc <= '1';
END IF;
IF execOPC='1' THEN
IF condition='1' THEN
OP2out_one <= '1';
exec_EXG <= '1';
ELSE
OP1out_zero <= '1';
END IF;
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
ELSE --addq, subq
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(5 downto 3)="001" THEN
no_Flags <= '1';
END IF;
write_back <= '1';
set_exec_ADDQ <= '1';
set_exec_ADD <= '1';
IF execOPC='1' THEN
ea_data_OP1 <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
IF opcode(8)='1' THEN
setaddsub <= '0';
END IF;
END IF;
END IF;
-- 0110 ----------------------------------------------------------------------------
WHEN "0110" => --bra,bsr,bcc
datatype <= "10";
IF micro_state=idle THEN
IF opcode(11 downto 8)="0001" THEN --bsr
IF opcode(7 downto 0)="00000000" THEN
next_micro_state <= bsr1;
ELSE
next_micro_state <= bsr2;
setstate <= "01";
END IF;
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
ELSE --bra
IF opcode(7 downto 0)="00000000" THEN
next_micro_state <= bra1;
END IF;
IF condition='1' THEN
TG68_PC_br8 <= '1';
END IF;
END IF;
END IF;
-- 0111 ----------------------------------------------------------------------------
WHEN "0111" => --moveq
IF opcode(8)='0' THEN
IF trap_interrupt='0' THEN
datatype <= "10"; --Long
Regwrena <= '1';
set_exec_MOVEQ <= '1';
set_exec_MOVE <= '1';
dest_hbits <= '1';
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
-- 1000 ----------------------------------------------------------------------------
WHEN "1000" => --or
IF opcode(7 downto 6)="11" THEN --divu, divs
IF opcode(5 downto 4)="00" THEN --Dn, An
regdirectsource <= '1';
END IF;
IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div1;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' AND z_error='0' AND set_V_Flag='0' THEN
regwrena <= '1';
END IF;
IF (micro_state/=idle AND nextpass='1') OR execOPC='1' THEN
dest_hbits <= '1';
source_lowbits <='1';
ELSE
datatype <= "01";
END IF;
ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN --sbcd, pack , unpack
IF opcode(7 downto 6)="00" THEN --sbcd
use_XZFlag <= '1';
set_exec_ADD <= '1';
set_exec_SBCD <= '1';
IF opcode(3)='1' THEN
write_back <= '1';
IF decodeOPC='1' THEN
set_direct_data <= '1';
setstate <= "10";
set_mem_addsub <= '1';
presub <= '1';
next_micro_state <= op_AxAy;
END IF;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
dest_hbits <= '1';
source_lowbits <='1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
ELSE --pack, unpack
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSE --or
set_exec_OR <= '1';
IF opcode(8)='1' THEN
write_back <= '1';
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' THEN
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
IF opcode(8)='1' THEN
ea_data_OP1 <= '1';
ELSE
dest_hbits <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
END IF;
END IF;
END IF;
-- 1001, 1101 -----------------------------------------------------------------------
WHEN "1001"|"1101" => --sub, add
set_exec_ADD <= '1';
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(8 downto 6)="011" THEN --adda.w, suba.w
datatype <= "01"; --Word
END IF;
IF execOPC='1' THEN
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
IF opcode(14)='0' THEN
setaddsub <= '0';
END IF;
END IF;
IF opcode(8)='1' AND opcode(5 downto 4)="00" AND opcode(7 downto 6)/="11" THEN --addx, subx
use_XZFlag <= '1';
IF opcode(3)='1' THEN
write_back <= '1';
IF decodeOPC='1' THEN
set_direct_data <= '1';
setstate <= "10";
set_mem_addsub <= '1';
presub <= '1';
next_micro_state <= op_AxAy;
END IF;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
dest_hbits <= '1';
source_lowbits <='1';
END IF;
ELSE --sub, add
IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN
write_back <= '1';
END IF;
IF execOPC='1' THEN
IF opcode(7 downto 6)="11" THEN --adda, suba
no_Flags <= '1';
dest_areg <='1';
dest_hbits <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
ELSE
IF opcode(8)='1' THEN
ea_data_OP1 <= '1';
ELSE
dest_hbits <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
END IF;
END IF;
END IF;
END IF;
-- 1010 ----------------------------------------------------------------------------
WHEN "1010" => --Trap 1010
trap_1010 <= '1';
trapmake <= '1';
-- 1011 ----------------------------------------------------------------------------
WHEN "1011" => --eor, cmp
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(8 downto 6)="011" THEN --cmpa.w
datatype <= "01"; --Word
set_exec_CPMAW <= '1';
END IF;
IF opcode(8)='1' AND opcode(5 downto 3)="001" AND opcode(7 downto 6)/="11" THEN --cmpm
set_exec_CMP <= '1';
IF decodeOPC='1' THEN
set_direct_data <= '1';
setstate <= "10";
set_mem_rega <= '1';
postadd <= '1';
next_micro_state <= cmpm;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
setaddsub <= '0';
END IF;
ELSE --sub, add
IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN --eor
set_exec_EOR <= '1';
write_back <= '1';
ELSE --cmp
set_exec_CMP <= '1';
END IF;
IF execOPC='1' THEN
IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN --eor
ea_data_OP1 <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
ELSE --cmp
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
IF opcode(7 downto 6)="11" THEN --cmpa
dest_areg <='1';
END IF;
dest_hbits <= '1';
setaddsub <= '0';
END IF;
END IF;
END IF;
-- 1100 ----------------------------------------------------------------------------
WHEN "1100" => --and, exg
IF opcode(7 downto 6)="11" THEN --mulu, muls
IF opcode(5 downto 4)="00" THEN --Dn, An
regdirectsource <= '1';
END IF;
IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul1;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' THEN
regwrena <= '1';
END IF;
IF (micro_state/=idle AND nextpass='1') OR execOPC='1' THEN
dest_hbits <= '1';
source_lowbits <='1';
ELSE
datatype <= "01";
END IF;
ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN --exg, abcd
IF opcode(7 downto 6)="00" THEN --abcd
use_XZFlag <= '1';
-- datatype <= "00"; --ist schon default
set_exec_ADD <= '1';
set_exec_ABCD <= '1';
IF opcode(3)='1' THEN
write_back <= '1';
IF decodeOPC='1' THEN
set_direct_data <= '1';
setstate <= "10";
set_mem_addsub <= '1';
presub <= '1';
next_micro_state <= op_AxAy;
END IF;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
dest_hbits <= '1';
source_lowbits <='1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
ELSE --exg
datatype <= "10";
regwrena <= '1';
IF opcode(6)='1' AND opcode(3)='1' THEN
dest_areg <= '1';
source_areg <= '1';
END IF;
IF decodeOPC='1' THEN
set_mem_rega <= '1';
exec_exg <= '1';
ELSE
save_memaddr <= '1';
dest_hbits <= '1';
END IF;
END IF;
ELSE --and
set_exec_AND <= '1';
IF opcode(8)='1' THEN
write_back <= '1';
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' THEN
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
IF opcode(8)='1' THEN
ea_data_OP1 <= '1';
ELSE
dest_hbits <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
END IF;
END IF;
END IF;
-- 1110 ----------------------------------------------------------------------------
WHEN "1110" => --rotation
set_exec_ROT <= '1';
IF opcode(7 downto 6)="11" THEN
datatype <= "01";
rot_bits <= opcode(10 downto 9);
ea_data_OP1 <= '1';
write_back <= '1';
ELSE
rot_bits <= opcode(4 downto 3);
data_is_source <= '1';
END IF;
IF decodeOPC='1' THEN
IF opcode(7 downto 6)="11" THEN
ea_build <= '1';
ELSE
IF opcode(5)='1' THEN
IF OP2out(5 downto 0)/="000000" THEN
set_rot_cnt <= OP2out(5 downto 0);
ELSE
set_rot_nop <= '1';
END IF;
ELSE
set_rot_cnt(2 downto 0) <= opcode(11 downto 9);
IF opcode(11 downto 9)="000" THEN
set_rot_cnt(3) <='1';
ELSE
set_rot_cnt(3) <='0';
END IF;
END IF;
END IF;
END IF;
IF opcode(7 downto 6)/="11" THEN
IF execOPC='1' AND rot_nop='0' THEN
Regwrena <= '1';
set_rot_cnt <= rot_cnt-1;
END IF;
END IF;
-- ----------------------------------------------------------------------------
WHEN OTHERS =>
trap_1111 <= '1';
trapmake <= '1';
END CASE;
-- END PROCESS;
-----------------------------------------------------------------------------
-- execute microcode
-----------------------------------------------------------------------------
--PROCESS (micro_state)
-- BEGIN
IF Z_error='1' THEN -- divu by zero
trapmake <= '1'; --wichtig für USP
IF trapd='0' THEN
writePC <= '1';
END IF;
END IF;
IF trapmake='1' AND trapd='0' THEN
next_micro_state <= trap1;
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <= "11";
datatype <= "10";
END IF;
IF interrupt='1' THEN
next_micro_state <= int1;
setstate <= "10";
-- datatype <= "01"; --wirkt sich auf Flags aus
END IF;
IF reset='0' THEN
micro_state <= init1;
ELSIF rising_edge(clk) THEN
IF clkena='1' THEN
trapd <= trapmake;
IF fetchOPC='1' THEN
micro_state <= idle;
ELSE
micro_state <= next_micro_state;
END IF;
END IF;
END IF;
CASE micro_state IS
WHEN ld_nn => -- (nnnn).w/l=>
get_ea_now <='1';
setnextpass <= '1';
setaddrlong <= '1';
WHEN st_nn => -- =>(nnnn).w/l
setstate <= "11";
setaddrlong <= '1';
next_micro_state <= nop;
WHEN ld_dAn1 => -- d(An)=>, --d(PC)=>
setstate <= "01";
next_micro_state <= ld_dAn2;
WHEN ld_dAn2 => -- d(An)=>, --d(PC)=>
get_ea_now <='1';
setdisp <= '1'; --word
setnextpass <= '1';
WHEN ld_AnXn1 => -- d(An,Xn)=>, --d(PC,Xn)=>
setstate <= "01";
next_micro_state <= ld_AnXn2;
WHEN ld_AnXn2 => -- d(An,Xn)=>, --d(PC,Xn)=>
setdisp <= '1'; --byte
setdispbyte <= '1';
setstate <= "01";
setbriefext <= '1';
next_micro_state <= ld_AnXn3;
WHEN ld_AnXn3 =>
get_ea_now <='1';
setdisp <= '1'; --brief
setdispbrief <= '1';
setnextpass <= '1';
WHEN st_dAn1 => -- =>d(An)
setstate <= "01";
next_micro_state <= st_dAn2;
WHEN st_dAn2 => -- =>d(An)
setstate <= "11";
setdisp <= '1'; --word
next_micro_state <= nop;
WHEN st_AnXn1 => -- =>d(An,Xn)
setstate <= "01";
next_micro_state <= st_AnXn2;
WHEN st_AnXn2 => -- =>d(An,Xn)
setdisp <= '1'; --byte
setdispbyte <= '1';
setstate <= "01";
setbriefext <= '1';
next_micro_state <= st_AnXn3;
WHEN st_AnXn3 =>
setstate <= "11";
setdisp <= '1'; --brief
setdispbrief <= '1';
next_micro_state <= nop;
WHEN bra1 => --bra
IF condition='1' THEN
TG68_PC_br8 <= '1'; --pc+0000
setstate <= "01";
next_micro_state <= bra2;
END IF;
WHEN bra2 => --bra
TG68_PC_brw <= '1';
WHEN bsr1 => --bsr
set_TG68_PC_dec <= '1'; --in 2 Takten -2
setstate <= "01";
next_micro_state <= bsr2;
WHEN bsr2 => --bsr
IF TG68_PC_dec(0)='1' THEN
TG68_PC_brw <= '1';
ELSE
TG68_PC_br8 <= '1';
END IF;
writePC <= '1';
setstate <= "11";
next_micro_state <= nop;
WHEN dbcc1 => --dbcc
TG68_PC_nop <= '1';
setstate <= "01";
next_micro_state <= dbcc2;
WHEN dbcc2 => --dbcc
TG68_PC_brw <= '1';
WHEN movem => --movem
set_movem_busy <='1';
setstate <= "10";
WHEN andi => --andi
IF opcode(5 downto 4)/="00" THEN
ea_build <= '1';
setnextpass <= '1';
END IF;
WHEN op_AxAy => -- op -(Ax),-(Ay)
presub <= '1';
dest_hbits <= '1';
dest_areg <= '1';
set_mem_addsub <= '1';
setstate <= "10";
WHEN cmpm => -- cmpm (Ay)+,(Ax)+
postadd <= '1';
dest_hbits <= '1';
dest_areg <= '1';
set_mem_rega <= '1';
setstate <= "10";
WHEN link => -- link
setstate <="11";
save_memaddr <= '1';
regwrena <= '1';
WHEN int1 => -- interrupt
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <= "11";
datatype <= "10";
next_micro_state <= int2;
WHEN int2 => -- interrupt
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <= "11";
datatype <= "01";
writeSR <= '1';
next_micro_state <= int3;
WHEN int3 => -- interrupt
set_vectoraddr <= '1';
datatype <= "10";
set_directPC <= '1';
setstate <= "10";
next_micro_state <= int4;
WHEN int4 => -- interrupt
datatype <= "10";
WHEN rte => -- RTE
datatype <= "10";
setstate <= "10";
postadd <= '1';
setstackaddr <= '1';
set_mem_rega <= '1';
set_directPC <= '1';
next_micro_state <= nop;
WHEN trap1 => -- TRAP
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <= "11";
datatype <= "01";
writeSR <= '1';
next_micro_state <= trap2;
WHEN trap2 => -- TRAP
set_vectoraddr <= '1';
datatype <= "10";
set_directPC <= '1';
-- longreaddirect <= '1';
setstate <= "10";
next_micro_state <= trap3;
WHEN trap3 => -- TRAP
datatype <= "10";
WHEN movep1 => -- MOVEP d(An)
setstate <= "01";
IF opcode(6)='1' THEN
set_movepl <= '1';
END IF;
next_micro_state <= movep2;
WHEN movep2 =>
setdisp <= '1';
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
setstate <= "11";
wait_mem_byte <= '1';
END IF;
next_micro_state <= movep3;
WHEN movep3 =>
IF opcode(6)='1' THEN
set_movepw <= '1';
next_micro_state <= movep4;
END IF;
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
setstate <= "11";
END IF;
WHEN movep4 =>
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
wait_mem_byte <= '1';
setstate <= "11";
END IF;
next_micro_state <= movep5;
WHEN movep5 =>
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
setstate <= "11";
END IF;
WHEN init1 => -- init SP
longreaddirect <= '1';
next_micro_state <= init2;
WHEN init2 => -- init PC
get_ea_now <='1'; --\
ea_only <= '1'; --- OP1in <= memaddr_in
setaddrlong <= '1'; -- memaddr_in <= data_read
regwrena <= '1';
setstackaddr <='1'; -- dest_addr <= SP
set_directPC <= '1';
longreaddirect <= '1';
next_micro_state <= nop;
WHEN mul1 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul2;
WHEN mul2 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul3;
WHEN mul3 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul4;
WHEN mul4 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul5;
WHEN mul5 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul6;
WHEN mul6 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul7;
WHEN mul7 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul8;
WHEN mul8 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul9;
WHEN mul9 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul10;
WHEN mul10 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul11;
WHEN mul11 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul12;
WHEN mul12 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul13;
WHEN mul13 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul14;
WHEN mul14 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul15;
WHEN mul15 => -- mulu
set_exec_MULU <= '1';
WHEN div1 => -- divu
IF OP2out(15 downto 0)=x"0000" THEN --div zero
set_Z_error <= '1';
ELSE
set_exec_DIVU <= '1';
next_micro_state <= div2;
END IF;
setstate <="01";
WHEN div2 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div3;
WHEN div3 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div4;
WHEN div4 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div5;
WHEN div5 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div6;
WHEN div6 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div7;
WHEN div7 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div8;
WHEN div8 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div9;
WHEN div9 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div10;
WHEN div10 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div11;
WHEN div11 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div12;
WHEN div12 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div13;
WHEN div13 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div14;
WHEN div14 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div15;
WHEN div15 => -- divu
set_exec_DIVU <= '1';
WHEN OTHERS => null;
END CASE;
END PROCESS;
-----------------------------------------------------------------------------
-- Conditions
-----------------------------------------------------------------------------
PROCESS (opcode, Flags)
BEGIN
CASE opcode(11 downto 8) IS
WHEN X"0" => condition <= '1';
WHEN X"1" => condition <= '0';
WHEN X"2" => condition <= NOT Flags(0) AND NOT Flags(2);
WHEN X"3" => condition <= Flags(0) OR Flags(2);
WHEN X"4" => condition <= NOT Flags(0);
WHEN X"5" => condition <= Flags(0);
WHEN X"6" => condition <= NOT Flags(2);
WHEN X"7" => condition <= Flags(2);
WHEN X"8" => condition <= NOT Flags(1);
WHEN X"9" => condition <= Flags(1);
WHEN X"a" => condition <= NOT Flags(3);
WHEN X"b" => condition <= Flags(3);
WHEN X"c" => condition <= (Flags(3) AND Flags(1)) OR (NOT Flags(3) AND NOT Flags(1));
WHEN X"d" => condition <= (Flags(3) AND NOT Flags(1)) OR (NOT Flags(3) AND Flags(1));
WHEN X"e" => condition <= (Flags(3) AND Flags(1) AND NOT Flags(2)) OR (NOT Flags(3) AND NOT Flags(1) AND NOT Flags(2));
WHEN X"f" => condition <= (Flags(3) AND NOT Flags(1)) OR (NOT Flags(3) AND Flags(1)) OR Flags(2);
WHEN OTHERS => null;
END CASE;
END PROCESS;
-----------------------------------------------------------------------------
-- Bits
-----------------------------------------------------------------------------
PROCESS (opcode, OP1out, OP2out, one_bit_in, one_bit_out, bit_Number, bit_number_reg)
BEGIN
CASE opcode(7 downto 6) IS
WHEN "00" => --btst
one_bit_out <= one_bit_in;
WHEN "01" => --bchg
one_bit_out <= NOT one_bit_in;
WHEN "10" => --bclr
one_bit_out <= '0';
WHEN "11" => --bset
one_bit_out <= '1';
WHEN OTHERS => null;
END CASE;
IF opcode(8)='0' THEN
IF opcode(5 downto 4)="00" THEN
bit_number <= bit_number_reg(4 downto 0);
ELSE
bit_number <= "00"&bit_number_reg(2 downto 0);
END IF;
ELSE
IF opcode(5 downto 4)="00" THEN
bit_number <= OP2out(4 downto 0);
ELSE
bit_number <= "00"&OP2out(2 downto 0);
END IF;
END IF;
bits_out <= OP1out;
CASE bit_Number IS
WHEN "00000" => one_bit_in <= OP1out(0);
bits_out(0) <= one_bit_out;
WHEN "00001" => one_bit_in <= OP1out(1);
bits_out(1) <= one_bit_out;
WHEN "00010" => one_bit_in <= OP1out(2);
bits_out(2) <= one_bit_out;
WHEN "00011" => one_bit_in <= OP1out(3);
bits_out(3) <= one_bit_out;
WHEN "00100" => one_bit_in <= OP1out(4);
bits_out(4) <= one_bit_out;
WHEN "00101" => one_bit_in <= OP1out(5);
bits_out(5) <= one_bit_out;
WHEN "00110" => one_bit_in <= OP1out(6);
bits_out(6) <= one_bit_out;
WHEN "00111" => one_bit_in <= OP1out(7);
bits_out(7) <= one_bit_out;
WHEN "01000" => one_bit_in <= OP1out(8);
bits_out(8) <= one_bit_out;
WHEN "01001" => one_bit_in <= OP1out(9);
bits_out(9) <= one_bit_out;
WHEN "01010" => one_bit_in <= OP1out(10);
bits_out(10) <= one_bit_out;
WHEN "01011" => one_bit_in <= OP1out(11);
bits_out(11) <= one_bit_out;
WHEN "01100" => one_bit_in <= OP1out(12);
bits_out(12) <= one_bit_out;
WHEN "01101" => one_bit_in <= OP1out(13);
bits_out(13) <= one_bit_out;
WHEN "01110" => one_bit_in <= OP1out(14);
bits_out(14) <= one_bit_out;
WHEN "01111" => one_bit_in <= OP1out(15);
bits_out(15) <= one_bit_out;
WHEN "10000" => one_bit_in <= OP1out(16);
bits_out(16) <= one_bit_out;
WHEN "10001" => one_bit_in <= OP1out(17);
bits_out(17) <= one_bit_out;
WHEN "10010" => one_bit_in <= OP1out(18);
bits_out(18) <= one_bit_out;
WHEN "10011" => one_bit_in <= OP1out(19);
bits_out(19) <= one_bit_out;
WHEN "10100" => one_bit_in <= OP1out(20);
bits_out(20) <= one_bit_out;
WHEN "10101" => one_bit_in <= OP1out(21);
bits_out(21) <= one_bit_out;
WHEN "10110" => one_bit_in <= OP1out(22);
bits_out(22) <= one_bit_out;
WHEN "10111" => one_bit_in <= OP1out(23);
bits_out(23) <= one_bit_out;
WHEN "11000" => one_bit_in <= OP1out(24);
bits_out(24) <= one_bit_out;
WHEN "11001" => one_bit_in <= OP1out(25);
bits_out(25) <= one_bit_out;
WHEN "11010" => one_bit_in <= OP1out(26);
bits_out(26) <= one_bit_out;
WHEN "11011" => one_bit_in <= OP1out(27);
bits_out(27) <= one_bit_out;
WHEN "11100" => one_bit_in <= OP1out(28);
bits_out(28) <= one_bit_out;
WHEN "11101" => one_bit_in <= OP1out(29);
bits_out(29) <= one_bit_out;
WHEN "11110" => one_bit_in <= OP1out(30);
bits_out(30) <= one_bit_out;
WHEN "11111" => one_bit_in <= OP1out(31);
bits_out(31) <= one_bit_out;
WHEN OTHERS => null;
END CASE;
END PROCESS;
-----------------------------------------------------------------------------
-- Rotation
-----------------------------------------------------------------------------
PROCESS (opcode, OP1out, Flags, rot_bits, rot_msb, rot_lsb, rot_rot, rot_nop)
BEGIN
CASE opcode(7 downto 6) IS
WHEN "00" => --Byte
rot_rot <= OP1out(7);
WHEN "01"|"11" => --Word
rot_rot <= OP1out(15);
WHEN "10" => --Long
rot_rot <= OP1out(31);
WHEN OTHERS => null;
END CASE;
CASE rot_bits IS
WHEN "00" => --ASL, ASR
rot_lsb <= '0';
rot_msb <= rot_rot;
WHEN "01" => --LSL, LSR
rot_lsb <= '0';
rot_msb <= '0';
WHEN "10" => --ROXL, ROXR
rot_lsb <= Flags(4);
rot_msb <= Flags(4);
WHEN "11" => --ROL, ROR
rot_lsb <= rot_rot;
rot_msb <= OP1out(0);
WHEN OTHERS => null;
END CASE;
IF rot_nop='1' THEN
rot_out <= OP1out;
rot_XC <= Flags(0);
ELSE
IF opcode(8)='1' THEN --left
rot_out <= OP1out(30 downto 0)&rot_lsb;
rot_XC <= rot_rot;
ELSE --right
rot_XC <= OP1out(0);
rot_out <= rot_msb&OP1out(31 downto 1);
CASE opcode(7 downto 6) IS
WHEN "00" => --Byte
rot_out(7) <= rot_msb;
WHEN "01"|"11" => --Word
rot_out(15) <= rot_msb;
WHEN OTHERS =>
END CASE;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- MULU/MULS
-----------------------------------------------------------------------------
PROCESS (clk, opcode, OP2out, muls_msb, mulu_reg, OP1sign, sign2)
BEGIN
IF rising_edge(clk) THEN
IF clkena='1' THEN
IF decodeOPC='1' THEN
IF opcode(8)='1' AND reg_QB(15)='1' THEN --MULS Neg faktor
OP1sign <= '1';
mulu_reg <= "0000000000000000"&(0-reg_QB(15 downto 0));
ELSE
OP1sign <= '0';
mulu_reg <= "0000000000000000"®_QB(15 downto 0);
END IF;
ELSIF exec_MULU='1' THEN
mulu_reg <= dummy_mulu;
END IF;
END IF;
END IF;
IF (opcode(8)='1' AND OP2out(15)='1') OR OP1sign='1' THEN
muls_msb <= mulu_reg(31);
ELSE
muls_msb <= '0';
END IF;
IF opcode(8)='1' AND OP2out(15)='1' THEN
sign2 <= '1';
ELSE
sign2 <= '0';
END IF;
IF mulu_reg(0)='1' THEN
IF OP1sign='1' THEN
dummy_mulu <= (muls_msb&mulu_reg(31 downto 16))-(sign2&OP2out(15 downto 0))& mulu_reg(15 downto 1);
ELSE
dummy_mulu <= (muls_msb&mulu_reg(31 downto 16))+(sign2&OP2out(15 downto 0))& mulu_reg(15 downto 1);
END IF;
ELSE
dummy_mulu <= muls_msb&mulu_reg(31 downto 1);
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- DIVU
-----------------------------------------------------------------------------
PROCESS (clk, execOPC, opcode, OP1out, OP2out, div_reg, dummy_div_sub, div_quot, div_sign, dummy_div_over, dummy_div)
BEGIN
set_V_Flag <= '0';
IF rising_edge(clk) THEN
IF clkena='1' THEN
IF decodeOPC='1' THEN
IF opcode(8)='1' AND reg_QB(31)='1' THEN -- Neg divisor
div_sign <= '1';
div_reg <= 0-reg_QB;
ELSE
div_sign <= '0';
div_reg <= reg_QB;
END IF;
ELSIF exec_DIVU='1' THEN
div_reg <= div_quot;
END IF;
END IF;
END IF;
dummy_div_over <= ('0'&OP1out(31 downto 16))-('0'&OP2out(15 downto 0));
IF opcode(8)='1' AND OP2out(15) ='1' THEN
dummy_div_sub <= (div_reg(31 downto 15))+('1'&OP2out(15 downto 0));
ELSE
dummy_div_sub <= (div_reg(31 downto 15))-('0'&OP2out(15 downto 0));
END IF;
IF (dummy_div_sub(16))='1' THEN
div_quot(31 downto 16) <= div_reg(30 downto 15);
ELSE
div_quot(31 downto 16) <= dummy_div_sub(15 downto 0);
END IF;
div_quot(15 downto 0) <= div_reg(14 downto 0)&NOT dummy_div_sub(16);
IF execOPC='1' AND opcode(8)='1' AND (OP2out(15) XOR div_sign)='1' THEN
dummy_div(15 downto 0) <= 0-div_quot(15 downto 0);
ELSE
dummy_div(15 downto 0) <= div_quot(15 downto 0);
END IF;
IF div_sign='1' THEN
dummy_div(31 downto 16) <= 0-div_quot(31 downto 16);
ELSE
dummy_div(31 downto 16) <= div_quot(31 downto 16);
END IF;
IF (opcode(8)='1' AND (OP2out(15) XOR div_sign XOR dummy_div(15))='1' AND dummy_div(15 downto 0)/=X"0000") --Overflow DIVS
OR (opcode(8)='0' AND dummy_div_over(16)='0') THEN --Overflow DIVU
set_V_Flag <= '1';
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- Movem
-----------------------------------------------------------------------------
PROCESS (reset, clk, movem_mask, movem_muxa ,movem_muxb, movem_muxc)
BEGIN
IF movem_mask(7 downto 0)="00000000" THEN
movem_muxa <= movem_mask(15 downto 8);
movem_regaddr(3) <= '1';
ELSE
movem_muxa <= movem_mask(7 downto 0);
movem_regaddr(3) <= '0';
END IF;
IF movem_muxa(3 downto 0)="0000" THEN
movem_muxb <= movem_muxa(7 downto 4);
movem_regaddr(2) <= '1';
ELSE
movem_muxb <= movem_muxa(3 downto 0);
movem_regaddr(2) <= '0';
END IF;
IF movem_muxb(1 downto 0)="00" THEN
movem_muxc <= movem_muxb(3 downto 2);
movem_regaddr(1) <= '1';
ELSE
movem_muxc <= movem_muxb(1 downto 0);
movem_regaddr(1) <= '0';
END IF;
IF movem_muxc(0)='0' THEN
movem_regaddr(0) <= '1';
ELSE
movem_regaddr(0) <= '0';
END IF;
movem_bits <= ("0000"&movem_mask(0))+("0000"&movem_mask(1))+("0000"&movem_mask(2))+("0000"&movem_mask(3))+
("0000"&movem_mask(4))+("0000"&movem_mask(5))+("0000"&movem_mask(6))+("0000"&movem_mask(7))+
("0000"&movem_mask(8))+("0000"&movem_mask(9))+("0000"&movem_mask(10))+("0000"&movem_mask(11))+
("0000"&movem_mask(12))+("0000"&movem_mask(13))+("0000"&movem_mask(14))+("0000"&movem_mask(15));
IF reset = '0' THEN
movem_busy <= '0';
movem_addr <= '0';
ELSIF rising_edge(clk) THEN
IF clkena_in='1' AND get_movem_mask='1' THEN
movem_mask <= data_read(15 downto 0);
END IF;
IF clkena='1' THEN
IF set_movem_busy='1' THEN
IF movem_bits(3 downto 1) /= "000" OR opcode(10)='0' THEN
movem_busy <= '1';
END IF;
movem_addr <= '1';
END IF;
IF movem_addr='1' THEN
CASE movem_regaddr IS
WHEN "0000" => movem_mask(0) <= '0';
WHEN "0001" => movem_mask(1) <= '0';
WHEN "0010" => movem_mask(2) <= '0';
WHEN "0011" => movem_mask(3) <= '0';
WHEN "0100" => movem_mask(4) <= '0';
WHEN "0101" => movem_mask(5) <= '0';
WHEN "0110" => movem_mask(6) <= '0';
WHEN "0111" => movem_mask(7) <= '0';
WHEN "1000" => movem_mask(8) <= '0';
WHEN "1001" => movem_mask(9) <= '0';
WHEN "1010" => movem_mask(10) <= '0';
WHEN "1011" => movem_mask(11) <= '0';
WHEN "1100" => movem_mask(12) <= '0';
WHEN "1101" => movem_mask(13) <= '0';
WHEN "1110" => movem_mask(14) <= '0';
WHEN "1111" => movem_mask(15) <= '0';
WHEN OTHERS => null;
END CASE;
IF opcode(10)='1' THEN
IF movem_bits="00010" OR movem_bits="00001" OR movem_bits="00000" THEN
movem_busy <= '0';
END IF;
END IF;
IF movem_bits="00001" OR movem_bits="00000" THEN
movem_busy <= '0';
movem_addr <= '0';
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END;
|
mit
|
27ed5c17bcf0fde3d406e3cc9ce115ca
| 0.495638 | 3.049789 | false | false | false | false |
peteut/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_08.vhd
| 4 | 1,647 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_fg_03_08.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity max3 is
port ( a, b, c : in integer; z : out integer );
end entity max3;
architecture check_error of max3 is
begin
maximizer : process (a, b, c)
variable result : integer;
begin
if a > b then
if a > c then
result := a;
else
result := a; -- Oops! Should be: result := c;
end if;
elsif b > c then
result := b;
else
result := c;
end if;
assert result >= a and result >= b and result >= c
report "inconsistent result for maximum"
severity failure;
z <= result;
end process maximizer;
end architecture check_error;
|
gpl-2.0
|
ab32670494156153d6bf7df495911f68
| 0.604736 | 4.017073 | false | false | false | false |
peteut/ghdl
|
testsuite/gna/ticket20/morten2.vhdl
| 3 | 2,262 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- library std;
use std.textio.all;
entity morten2 is
end entity;
architecture foo of morten2 is
signal clk: std_logic := '0';
signal rst: std_logic := '1';
signal cnt_1: unsigned (7 downto 0);
signal cnt_3: unsigned (7 downto 0);
function to_bstring(sl : std_logic) return string is
alias bstring: string is std_logic'image(sl);
begin
--return "" & string'(std_logic'image(sl))(2); -- "" & character to get string
return "" & bstring(2);
end function;
function to_bstring(slv : std_logic_vector) return string is
alias slv_norm : std_logic_vector(1 to slv'length) is slv;
begin
if slv_norm'length = 0 then
return "";
elsif slv_norm'length = 1 then
return to_bstring(slv_norm(1));
else -- slv_norm'length > 0
return to_bstring(slv_norm(1)) & to_bstring(slv_norm(2 to slv_norm'length));
end if;
end function;
begin
PRINT:
process (clk) is
variable line_v : line;
file out_file : text open write_mode is "out.txt";
begin
if rising_edge(clk) then
write(line_v, to_bstring(rst) & " " &
to_bstring(std_logic_vector(cnt_1)) & " " &
to_bstring(std_logic_vector(cnt_3))
);
writeline(out_file, line_v);
end if;
end process;
COUNTER1:
process (clk,rst)
begin
if rst = '1' then
cnt_1 <= (others => '0');
elsif rising_edge(clk) then
cnt_1 <= cnt_1 + 1;
end if;
end process;
COUNTER3:
process (clk,rst)
begin
if rst = '1' then
cnt_3 <= (others => '0');
elsif rising_edge(clk) then
cnt_3 <= cnt_3 + 3;
end if;
end process;
RESET:
process
begin
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
rst <= '0';
wait;
end process;
CLOCK:
process
begin
wait for 10 ns;
clk <= not clk;
if Now > 210 ns then
wait;
end if;
end process;
end architecture;
|
gpl-2.0
|
7c608cb73e9f9ef68a6b2fe6ac24f23c
| 0.534925 | 3.579114 | false | false | false | false |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/to_send/ngnp_added_monitor/ngnp/src/tmp/mb_lite/core_Pkg.vhd
| 3 | 20,511 |
----------------------------------------------------------------------------------------------
--
-- Input file : core_Pkg.vhd
-- Design name : core_Pkg
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Package with components and type definitions for the interface
-- of the components
--
--
----------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
LIBRARY work;
USE work.config_Pkg.ALL;
USE work.std_Pkg.ALL;
PACKAGE core_Pkg IS
----------------------------------------------------------------------------------------------
-- TYPES USED IN MB-LITE
----------------------------------------------------------------------------------------------
TYPE alu_operation IS (ALU_ADD, ALU_OR, ALU_AND, ALU_XOR, ALU_SHIFT, ALU_SEXT8, ALU_SEXT16, ALU_MUL, ALU_BS);
TYPE src_type_a IS (ALU_SRC_REGA, ALU_SRC_NOT_REGA, ALU_SRC_PC, ALU_SRC_ZERO);
TYPE src_type_b IS (ALU_SRC_REGB, ALU_SRC_NOT_REGB, ALU_SRC_IMM, ALU_SRC_NOT_IMM);
TYPE carry_type IS (CARRY_ZERO, CARRY_ONE, CARRY_ALU, CARRY_ARITH);
TYPE carry_keep_type IS (CARRY_NOT_KEEP, CARRY_KEEP);
TYPE branch_condition IS (NOP, BNC, BEQ, BNE, BLT, BLE, BGT, BGE);
TYPE transfer_size IS (WORD, HALFWORD, BYTE);
TYPE ctrl_execution IS RECORD
alu_op : alu_operation;
alu_src_a : src_type_a;
alu_src_b : src_type_b;
operation : std_ulogic;
carry : carry_type;
carry_keep : carry_keep_type;
branch_cond : branch_condition;
delay : std_ulogic;
END RECORD;
TYPE ctrl_memory IS RECORD
mem_write : std_ulogic;
mem_read : std_ulogic;
transfer_size : transfer_size;
END RECORD;
TYPE ctrl_memory_writeback_type IS RECORD
mem_read : std_ulogic;
transfer_size : transfer_size;
END RECORD;
TYPE forward_type IS RECORD
reg_d : std_ulogic_vector(CFG_GPRF_SIZE - 1 DOWNTO 0);
reg_write : std_ulogic;
END RECORD;
TYPE imem_in_type IS RECORD
dat_i : std_ulogic_vector(CFG_IMEM_WIDTH - 1 DOWNTO 0);
END RECORD;
TYPE imem_out_type IS RECORD
adr_o : std_ulogic_vector(CFG_IMEM_SIZE - 1 DOWNTO 0);
ena_o : std_ulogic;
END RECORD;
TYPE fetch_in_type IS RECORD
hazard : std_ulogic;
branch : std_ulogic;
branch_target : std_ulogic_vector(CFG_IMEM_SIZE - 1 DOWNTO 0);
END RECORD;
TYPE fetch_out_type IS RECORD
program_counter : std_ulogic_vector(CFG_IMEM_SIZE - 1 DOWNTO 0);
END RECORD;
TYPE gprf_out_type IS RECORD
dat_a_o : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
dat_b_o : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
dat_d_o : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
END RECORD;
TYPE decode_in_type IS RECORD
program_counter : std_ulogic_vector(CFG_IMEM_SIZE - 1 DOWNTO 0);
instruction : std_ulogic_vector(CFG_IMEM_WIDTH - 1 DOWNTO 0);
ctrl_wb : forward_type;
ctrl_mem_wb : ctrl_memory_writeback_type;
mem_result : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
alu_result : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
interrupt : std_ulogic;
flush_id : std_ulogic;
END RECORD;
TYPE decode_out_type IS RECORD
reg_a : std_ulogic_vector(CFG_GPRF_SIZE - 1 DOWNTO 0);
reg_b : std_ulogic_vector(CFG_GPRF_SIZE - 1 DOWNTO 0);
imm : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
program_counter : std_ulogic_vector(CFG_IMEM_SIZE - 1 DOWNTO 0);
hazard : std_ulogic;
ctrl_ex : ctrl_execution;
ctrl_mem : ctrl_memory;
ctrl_wb : forward_type;
fwd_dec_result : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
fwd_dec : forward_type;
END RECORD;
TYPE gprf_in_type IS RECORD
adr_a_i : std_ulogic_vector(CFG_GPRF_SIZE - 1 DOWNTO 0);
adr_b_i : std_ulogic_vector(CFG_GPRF_SIZE - 1 DOWNTO 0);
adr_d_i : std_ulogic_vector(CFG_GPRF_SIZE - 1 DOWNTO 0);
dat_w_i : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
adr_w_i : std_ulogic_vector(CFG_GPRF_SIZE - 1 DOWNTO 0);
wre_i : std_ulogic;
END RECORD;
TYPE execute_out_type IS RECORD
alu_result : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
dat_d : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
branch : std_ulogic;
program_counter : std_ulogic_vector(CFG_IMEM_SIZE - 1 DOWNTO 0);
flush_id : std_ulogic;
ctrl_mem : ctrl_memory;
ctrl_wb : forward_type;
END RECORD;
TYPE execute_in_type IS RECORD
reg_a : std_ulogic_vector(CFG_GPRF_SIZE - 1 DOWNTO 0);
dat_a : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
reg_b : std_ulogic_vector(CFG_GPRF_SIZE - 1 DOWNTO 0);
dat_b : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
dat_d : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
imm : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
program_counter : std_ulogic_vector(CFG_IMEM_SIZE - 1 DOWNTO 0);
fwd_dec : forward_type;
fwd_dec_result : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
fwd_mem : forward_type;
ctrl_ex : ctrl_execution;
ctrl_mem : ctrl_memory;
ctrl_wb : forward_type;
ctrl_mem_wb : ctrl_memory_writeback_type;
mem_result : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
alu_result : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
END RECORD;
TYPE mem_in_type IS RECORD
dat_d : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
alu_result : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
mem_result : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
program_counter : std_ulogic_vector(CFG_IMEM_SIZE - 1 DOWNTO 0);
branch : std_ulogic;
ctrl_mem : ctrl_memory;
ctrl_wb : forward_type;
END RECORD;
TYPE mem_out_type IS RECORD
alu_result : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
ctrl_wb : forward_type;
ctrl_mem_wb : ctrl_memory_writeback_type;
END RECORD;
TYPE dmem_in_type IS RECORD
dat_i : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
ena_i : std_ulogic;
END RECORD;
TYPE dmem_out_type IS RECORD
dat_o : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
adr_o : std_ulogic_vector(CFG_DMEM_SIZE - 1 DOWNTO 0);
sel_o : std_ulogic_vector(3 DOWNTO 0);
we_o : std_ulogic;
ena_o : std_ulogic;
END RECORD;
TYPE dmem_in_array_type IS ARRAY(NATURAL RANGE <>) OF dmem_in_type;
TYPE dmem_out_array_type IS ARRAY(NATURAL RANGE <>) OF dmem_out_type;
-- WB-master inputs from the wb-slaves
TYPE wb_mst_in_type IS RECORD
clk_i : std_ulogic; -- master clock input
rst_i : std_ulogic; -- synchronous active high reset
dat_i : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0); -- databus input
ack_i : std_ulogic; -- buscycle acknowledge input
int_i : std_ulogic; -- interrupt request input
END RECORD;
-- WB-master outputs to the wb-slaves
TYPE wb_mst_out_type IS RECORD
adr_o : std_ulogic_vector(CFG_DMEM_SIZE - 1 DOWNTO 0); -- address bits
dat_o : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0); -- databus output
we_o : std_ulogic; -- write enable output
stb_o : std_ulogic; -- strobe signals
sel_o : std_ulogic_vector(3 DOWNTO 0); -- select output array
cyc_o : std_ulogic; -- valid BUS cycle output
END RECORD;
-- WB-slave inputs, from the WB-master
TYPE wb_slv_in_type IS RECORD
clk_i : std_ulogic; -- master clock input
rst_i : std_ulogic; -- synchronous active high reset
adr_i : std_ulogic_vector(CFG_DMEM_SIZE - 1 DOWNTO 0); -- address bits
dat_i : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0); -- Databus input
we_i : std_ulogic; -- Write enable input
stb_i : std_ulogic; -- strobe signals / core select signal
sel_i : std_ulogic_vector(3 DOWNTO 0); -- select output array
cyc_i : std_ulogic; -- valid BUS cycle input
END RECORD;
-- WB-slave outputs to the WB-master
TYPE wb_slv_out_type IS RECORD
dat_o : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0); -- Databus output
ack_o : std_ulogic; -- Bus cycle acknowledge output
int_o : std_ulogic; -- interrupt request output
END RECORD;
----------------------------------------------------------------------------------------------
-- COMPONENTS USED IN MB-LITE
----------------------------------------------------------------------------------------------
COMPONENT core
PORT
(
imem_adr_o : OUT std_ulogic_vector(CFG_IMEM_SIZE - 1 DOWNTO 0);
imem_ena_o : OUT std_ulogic;
dmem_dat_o : OUT std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
dmem_adr_o : OUT std_ulogic_vector(CFG_DMEM_SIZE - 1 DOWNTO 0);
dmem_sel_o : OUT std_ulogic_vector(3 DOWNTO 0);
dmem_we_o : OUT std_ulogic;
dmem_ena_o : OUT std_ulogic;
imem_dat_i : IN std_ulogic_vector(CFG_IMEM_WIDTH - 1 DOWNTO 0);
dmem_dat_i : IN std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
dmem_ena_i : IN std_ulogic;
int_i : IN std_ulogic;
rst_i : IN std_ulogic;
clk_i : IN std_ulogic
);
END COMPONENT;
COMPONENT core_wb GENERIC
(
G_INTERRUPT : boolean := CFG_INTERRUPT;
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL;
G_DEBUG : boolean := CFG_DEBUG
);
PORT
(
imem_o : OUT imem_out_type;
wb_o : OUT wb_mst_out_type;
imem_i : IN imem_in_type;
wb_i : IN wb_mst_in_type
);
END COMPONENT;
COMPONENT core_wb_adapter PORT
(
dmem_i : OUT dmem_in_type;
wb_o : OUT wb_mst_out_type;
dmem_o : IN dmem_out_type;
wb_i : IN wb_mst_in_type
);
END COMPONENT;
COMPONENT core_wb_async_adapter PORT
(
dmem_i : OUT dmem_in_type;
wb_o : OUT wb_mst_out_type;
dmem_o : IN dmem_out_type;
wb_i : IN wb_mst_in_type
);
END COMPONENT;
COMPONENT fetch PORT
(
fetch_o : OUT fetch_out_type;
imem_adr_o : OUT std_ulogic_vector(CFG_IMEM_SIZE - 1 DOWNTO 0);
imem_ena_o : OUT std_ulogic;
fetch_i : IN fetch_in_type;
rst_i : IN std_ulogic;
ena_i : IN std_ulogic;
clk_i : IN std_ulogic
);
END COMPONENT;
COMPONENT decode GENERIC
(
G_INTERRUPT : boolean := CFG_INTERRUPT;
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL;
G_DEBUG : boolean := CFG_DEBUG
);
PORT
(
decode_o : OUT decode_out_type;
gprf_o : OUT gprf_out_type;
decode_i : IN decode_in_type;
ena_i : IN std_ulogic;
rst_i : IN std_ulogic;
clk_i : IN std_ulogic
);
END COMPONENT;
COMPONENT gprf PORT
(
gprf_o : OUT gprf_out_type;
gprf_i : IN gprf_in_type;
ena_i : IN std_ulogic;
clk_i : IN std_ulogic
);
END COMPONENT;
COMPONENT execute GENERIC
(
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL
);
PORT
(
exec_o : OUT execute_out_type;
exec_i : IN execute_in_type;
ena_i : IN std_ulogic;
rst_i : IN std_ulogic;
clk_i : IN std_ulogic
);
END COMPONENT;
COMPONENT mem PORT
(
mem_o : OUT mem_out_type;
dmem_dat_o : OUT std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
dmem_adr_o : OUT std_ulogic_vector(CFG_DMEM_SIZE - 1 DOWNTO 0);
dmem_sel_o : OUT std_ulogic_vector(3 DOWNTO 0);
dmem_we_o : OUT std_ulogic;
dmem_ena_o : OUT std_ulogic;
mem_i : IN mem_in_type;
ena_i : IN std_ulogic;
rst_i : IN std_ulogic;
clk_i : IN std_ulogic
);
END COMPONENT;
COMPONENT core_address_decoder GENERIC
(
G_NUM_SLAVES : positive := CFG_NUM_SLAVES
);
PORT
(
m_dmem_i : OUT dmem_in_type;
s_dmem_o : OUT dmem_out_array_type;
m_dmem_o : IN dmem_out_type;
s_dmem_i : IN dmem_in_array_type;
clk_i : IN std_ulogic
);
END COMPONENT;
----------------------------------------------------------------------------------------------
-- FUNCTIONS USED IN MB-LITE
----------------------------------------------------------------------------------------------
FUNCTION select_register_data(reg_dat, reg, wb_dat : std_ulogic_vector; write : std_ulogic) RETURN std_ulogic_vector;
FUNCTION forward_condition(reg_write : std_ulogic; reg_a, reg_d : std_ulogic_vector) RETURN std_ulogic;
FUNCTION align_mem_load(data : std_ulogic_vector; size : transfer_size; address : std_ulogic_vector) RETURN std_ulogic_vector;
FUNCTION align_mem_store(data : std_ulogic_vector; size : transfer_size) RETURN std_ulogic_vector;
FUNCTION decode_mem_store(address : std_ulogic_vector(1 DOWNTO 0); size : transfer_size) RETURN std_ulogic_vector;
END core_Pkg;
PACKAGE BODY core_Pkg IS
-- This function select the register value:
-- A) zero
-- B) bypass value read from register file
-- C) value from register file
FUNCTION select_register_data(reg_dat, reg, wb_dat : std_ulogic_vector; write : std_ulogic) RETURN std_ulogic_vector IS
VARIABLE tmp : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
BEGIN
IF CFG_REG_FORCE_ZERO = true AND is_zero(reg) = '1' THEN
tmp := (OTHERS => '0');
ELSIF CFG_REG_FWD_WB = true AND write = '1' THEN
tmp := wb_dat;
ELSE
tmp := reg_dat;
END IF;
RETURN tmp;
END select_register_data;
-- This function checks if a forwarding condition is met. The condition is met of register A and D match
-- and the signal needs to be written back to the register file.
FUNCTION forward_condition(reg_write : std_ulogic; reg_a, reg_d : std_ulogic_vector ) RETURN std_ulogic IS
BEGIN
RETURN reg_write AND compare(reg_a, reg_d);
END forward_condition;
-- This function aligns the memory load operation. The load byte-order is defined here.
FUNCTION align_mem_load(data : std_ulogic_vector; size : transfer_size; address : std_ulogic_vector ) RETURN std_ulogic_vector IS
BEGIN
IF CFG_BYTE_ORDER = false THEN
-- Little endian decoding
CASE size IS
WHEN byte =>
CASE address(1 DOWNTO 0) IS
WHEN "00" => RETURN "000000000000000000000000" & data(CFG_DMEM_WIDTH/4 - 1 DOWNTO 0);
WHEN "01" => RETURN "000000000000000000000000" & data(CFG_DMEM_WIDTH/2 - 1 DOWNTO CFG_DMEM_WIDTH/4);
WHEN "10" => RETURN "000000000000000000000000" & data(3*CFG_DMEM_WIDTH/4 - 1 DOWNTO CFG_DMEM_WIDTH/2);
WHEN "11" => RETURN "000000000000000000000000" & data(CFG_DMEM_WIDTH - 1 DOWNTO 3*CFG_DMEM_WIDTH/4);
WHEN OTHERS => RETURN "00000000000000000000000000000000";
END CASE;
WHEN halfword =>
CASE address(1 DOWNTO 0) IS
WHEN "00" => RETURN "0000000000000000" & data(CFG_DMEM_WIDTH/2 - 1 DOWNTO 0);
WHEN "10" => RETURN "0000000000000000" & data(CFG_DMEM_WIDTH - 1 DOWNTO CFG_DMEM_WIDTH/2);
WHEN OTHERS => RETURN "00000000000000000000000000000000";
END CASE;
WHEN OTHERS =>
RETURN data;
END CASE;
ELSE
-- Big endian decoding
CASE size IS
WHEN byte =>
CASE address(1 DOWNTO 0) IS
WHEN "00" => RETURN "000000000000000000000000" & data(CFG_DMEM_WIDTH - 1 DOWNTO 3*CFG_DMEM_WIDTH/4);
WHEN "01" => RETURN "000000000000000000000000" & data(3*CFG_DMEM_WIDTH/4 - 1 DOWNTO CFG_DMEM_WIDTH/2);
WHEN "10" => RETURN "000000000000000000000000" & data(CFG_DMEM_WIDTH/2 - 1 DOWNTO CFG_DMEM_WIDTH/4);
WHEN "11" => RETURN "000000000000000000000000" & data(CFG_DMEM_WIDTH/4 - 1 DOWNTO 0);
WHEN OTHERS => RETURN "00000000000000000000000000000000";
END CASE;
WHEN halfword =>
CASE address(1 DOWNTO 0) IS
WHEN "00" => RETURN "0000000000000000" & data(CFG_DMEM_WIDTH - 1 DOWNTO CFG_DMEM_WIDTH/2);
WHEN "10" => RETURN "0000000000000000" & data(CFG_DMEM_WIDTH/2 - 1 DOWNTO 0);
WHEN OTHERS => RETURN "00000000000000000000000000000000";
END CASE;
WHEN OTHERS =>
RETURN data;
END CASE;
END IF;
END align_mem_load;
-- This function repeats the operand to all positions memory store operation.
FUNCTION align_mem_store(data : std_ulogic_vector; size : transfer_size) RETURN std_ulogic_vector IS
BEGIN
CASE size IS
WHEN byte => RETURN data( 7 DOWNTO 0) & data( 7 DOWNTO 0) & data(7 DOWNTO 0) & data(7 DOWNTO 0);
WHEN halfword => RETURN data(15 DOWNTO 0) & data(15 DOWNTO 0);
WHEN OTHERS => RETURN data;
END CASE;
END align_mem_store;
-- This function selects the correct bytes for memory writes. The store byte-order (MSB / LSB) can be defined here.
FUNCTION decode_mem_store(address : std_ulogic_vector(1 DOWNTO 0); size : transfer_size) RETURN std_ulogic_vector IS
BEGIN
IF CFG_BYTE_ORDER = false THEN
-- Little endian encoding
CASE size IS
WHEN BYTE =>
CASE address IS
WHEN "00" => RETURN "0001";
WHEN "01" => RETURN "0010";
WHEN "10" => RETURN "0100";
WHEN "11" => RETURN "1000";
WHEN OTHERS => RETURN "0000";
END CASE;
WHEN HALFWORD =>
CASE address IS
WHEN "00" => RETURN "0011";
WHEN "10" => RETURN "1100";
WHEN OTHERS => RETURN "0000";
END CASE;
WHEN OTHERS =>
RETURN "1111";
END CASE;
ELSE
-- Big endian encoding
CASE size IS
WHEN BYTE =>
CASE address IS
WHEN "00" => RETURN "1000";
WHEN "01" => RETURN "0100";
WHEN "10" => RETURN "0010";
WHEN "11" => RETURN "0001";
WHEN OTHERS => RETURN "0000";
END CASE;
WHEN HALFWORD =>
CASE address IS
-- Big endian encoding
WHEN "10" => RETURN "0011";
WHEN "00" => RETURN "1100";
WHEN OTHERS => RETURN "0000";
END CASE;
WHEN OTHERS =>
RETURN "1111";
END CASE;
END IF;
END decode_mem_store;
END core_Pkg;
|
mit
|
7f1c615ec0df6c0e36a40e262a6a06ab
| 0.527912 | 3.895726 | false | false | false | false |
stnolting/neo430
|
rtl/core/neo430_timer.vhd
| 1 | 9,531 |
-- #################################################################################################
-- # << NEO430 - High-Precision Timer >> #
-- # ********************************************************************************************* #
-- # This timer uses a configurable prescaler to increment an internal 16-bit counter. When the #
-- # counter value reaches the programmable threshold an interrupt can be triggered. Optionally, #
-- # the counter can be automatically reset when reaching the threshold value to restart counting. #
-- # Configure THRES before enabling the timer to prevent false interrupt requests. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
entity neo430_timer is
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0); -- data out
-- clock generator --
clkgen_en_o : out std_ulogic; -- enable clock generator
clkgen_i : in std_ulogic_vector(07 downto 0);
-- interrupt --
irq_o : out std_ulogic -- interrupt request
);
end neo430_timer;
architecture neo430_timer_rtl of neo430_timer is
-- IO space: module base address --
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
constant lo_abb_c : natural := index_size_f(timer_size_c); -- low address boundary bit
-- control reg bits --
constant ctrl_en_c : natural := 0; -- r/w: timer enable
constant ctrl_arst_c : natural := 1; -- r/w: auto reset on match
constant ctrl_irq_en_c : natural := 2; -- r/w: interrupt enable
constant ctrl_run_c : natural := 3; -- r/w: start/stop timer
constant ctrl_prsc0_c : natural := 4; -- r/w: prescaler select bit 0
constant ctrl_prsc1_c : natural := 5; -- r/w: prescaler select bit 1
constant ctrl_prsc2_c : natural := 6; -- r/w: prescaler select bit 2
-- access control --
signal acc_en : std_ulogic; -- module access enable
signal addr : std_ulogic_vector(15 downto 0); -- access address
signal wr_en : std_ulogic; -- word write enable
-- timer regs --
signal ctrl : std_ulogic_vector(06 downto 0); -- r/w: control register
signal thres : std_ulogic_vector(15 downto 0); -- -/w: threshold register
signal cnt : std_ulogic_vector(15 downto 0); -- r/-: counter register
-- prescaler clock generator --
signal prsc_tick : std_ulogic;
-- timer control --
signal match : std_ulogic; -- set if thres == cnt
signal irq_fire : std_ulogic;
signal irq_fire_ff : std_ulogic;
begin
-- Access Control -----------------------------------------------------------
-- -----------------------------------------------------------------------------
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = timer_base_c(hi_abb_c downto lo_abb_c)) else '0';
addr <= timer_base_c(15 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 1) & '0'; -- word aligned
wr_en <= acc_en and wren_i;
-- Write access -------------------------------------------------------------
-- -----------------------------------------------------------------------------
wr_access: process(clk_i)
begin
if rising_edge(clk_i) then
if (wr_en = '1') then
if (addr = timer_thres_addr_c) then
thres <= data_i;
end if;
if (addr = timer_ctrl_addr_c) then
ctrl(ctrl_en_c) <= data_i(ctrl_en_c);
ctrl(ctrl_arst_c) <= data_i(ctrl_arst_c);
ctrl(ctrl_irq_en_c) <= data_i(ctrl_irq_en_c);
ctrl(ctrl_run_c) <= data_i(ctrl_run_c);
ctrl(ctrl_prsc0_c) <= data_i(ctrl_prsc0_c);
ctrl(ctrl_prsc1_c) <= data_i(ctrl_prsc1_c);
ctrl(ctrl_prsc2_c) <= data_i(ctrl_prsc2_c);
end if;
end if;
end if;
end process wr_access;
-- enable external clock generator --
clkgen_en_o <= ctrl(ctrl_en_c);
-- Counter update -----------------------------------------------------------
-- -----------------------------------------------------------------------------
timer_cnt_core: process(clk_i)
begin
if rising_edge(clk_i) then
-- clock_enable buffer --
prsc_tick <= clkgen_i(to_integer(unsigned(ctrl(ctrl_prsc2_c downto ctrl_prsc0_c))));
-- irq edge detector --
irq_fire_ff <= irq_fire;
-- counter update --
if (ctrl(ctrl_en_c) = '0') then -- timer disabled
cnt <= (others => '0');
elsif (ctrl(ctrl_run_c) = '1') then -- timer enabled, but is it started?
if (match = '1') and (ctrl(ctrl_arst_c) = '1') then -- threshold match and auto reset?
cnt <= (others => '0');
elsif (match = '0') and (prsc_tick = '1') then -- count++
cnt <= std_ulogic_vector(unsigned(cnt) + 1);
end if;
end if;
end if;
end process timer_cnt_core;
-- match --
match <= '1' when (cnt = thres) else '0';
-- interrupt line --
irq_fire <= match and ctrl(ctrl_en_c) and ctrl(ctrl_irq_en_c); -- and ctrl(ctrl_run_c);
-- edge detector --
irq_o <= irq_fire and (not irq_fire_ff);
-- Read access --------------------------------------------------------------
-- -----------------------------------------------------------------------------
rd_access: process(clk_i)
begin
if rising_edge(clk_i) then
data_o <= (others => '0');
if (rden_i = '1') and (acc_en = '1') then
if (addr = timer_ctrl_addr_c) then
data_o(ctrl_en_c) <= ctrl(ctrl_en_c);
data_o(ctrl_arst_c) <= ctrl(ctrl_arst_c);
data_o(ctrl_irq_en_c) <= ctrl(ctrl_irq_en_c);
data_o(ctrl_run_c) <= ctrl(ctrl_run_c);
data_o(ctrl_prsc0_c) <= ctrl(ctrl_prsc0_c);
data_o(ctrl_prsc1_c) <= ctrl(ctrl_prsc1_c);
data_o(ctrl_prsc2_c) <= ctrl(ctrl_prsc2_c);
else--if (addr = timer_cnt_addr_c) then
data_o <= cnt;
-- else -- (addr = timer_thres_addr_c) then
-- data_o <= thres;
end if;
end if;
end if;
end process rd_access;
end neo430_timer_rtl;
|
bsd-3-clause
|
c69c4c30f57d7ebdd370d3fcab7d84b1
| 0.478649 | 4.258713 | false | false | false | false |
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