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VladisM/MARK_II
|
VHDL/src/uart/baudgen.vhd
| 1 | 1,124 |
-- Baudrate generator.
--
-- Part of MARK II project. For informations about license, please
-- see file /LICENSE .
--
-- author: Vladislav Mlejnecký
-- email: [email protected]
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity baudgen is
port(
clk: in std_logic;
res: in std_logic;
n: in unsigned(15 downto 0);
baud16_clk_en: out std_logic
);
end entity baudgen;
architecture baudgen_arch of baudgen is
begin
baud_div:
process(clk, res) is
variable count: unsigned(15 downto 0);
variable clkenvar: std_logic;
begin
if rising_edge(clk) then
if res = '1' then
count := (others => '0');
clkenvar := '0';
elsif count = n then
count := (others => '0');
clkenvar := '1';
else
count := count + 1;
clkenvar := '0';
end if;
end if;
baud16_clk_en <= clkenvar;
end process;
end architecture baudgen_arch;
|
mit
|
7191f4f64c582051106a80976d689d59
| 0.517364 | 3.954225 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/clk_gen.vhd
| 1 | 1,594 |
library UNISIM;
use UNISIM.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic;
sys_clk_bufg_o : out std_logic
);
end clk_gen;
architecture syn of clk_gen is
-- Internal clock signal
signal s_sys_clk : std_logic;
begin
-- IBUFGDS: Differential Global Clock Input Buffer
-- Virtex-6
-- Xilinx HDL Language Template, version 13.4
cpm_ibufgds_clk_gen : IBUFGDS
generic map (
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => FALSE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT"
)
port map (
O => s_sys_clk, -- Clock buffer output
I => sys_clk_p_i, -- Diff_p clock buffer input (connect directly to top-level port)
IB => sys_clk_n_i -- Diff_n clock buffer input (connect directly to top-level port)
);
sys_clk_o <= s_sys_clk;
-- BUFG: Global Clock Buffer
-- Virtex-6
-- Xilinx HDL Language Template, version 13.4
cmp_bufg_clk_gen : BUFG
port map (
O => sys_clk_bufg_o, -- 1-bit output: Clock buffer output
I => s_sys_clk -- 1-bit input: Clock buffer input
);
end syn;
|
lgpl-3.0
|
e25e43612b923d2e737d3293bca40e10
| 0.51192 | 4.025253 | false | false | false | false |
tec499-20142/t01-warmup
|
sim/interface_control-tb.vhd
| 1 | 3,744 |
-- +UEFSHDR----------------------------------------------------------------------
-- 2014 UEFS Universidade Estadual de Feira de Santana
-- TEC499-Sistemas Digitais
-- ------------------------------------------------------------------------------
-- TEAM: 01
-- ------------------------------------------------------------------------------
-- PROJECT: Warm up
-- ------------------------------------------------------------------------------
-- FILE NAME : interface_tb
-- KEYWORDS test, interface, control
-- -----------------------------------------------------------------------------
-- PURPOSE: Testa o módulo internet control
-- -UEFSHDR----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity interface_tb is
end interface_tb;
architecture Behavioral of interface_tb is
----------------------------------------------
-- Constants
----------------------------------------------
constant MAIN_CLK_PER : time := 20 ns; -- 50 MHz
constant MAIN_CLK : integer := 50;
constant BAUD_RATE : integer := 9600; -- Bits per Second
constant RST_LVL : std_logic := '1'; -- Active Level of Reset
----------------------------------------------
-- Signal Declaration
----------------------------------------------
-- Clock and reset Signals
signal clk_50m : std_logic := '0';
signal rst : std_logic;
signal rx_ready_in : std_logic;
signal rx_data_in : std_logic_vector(7 downto 0);
-- componente descrito como manda o documento de arquitetura,
-- segundo fontes, caso o mapeamento das portas seja esse, funciona
-- independentemente da linguagem.
component interfaceControl is
port (
clk: in std_logic;
reset: in std_logic;
rx_data_ready: in std_logic;
rx_data: in std_logic_vector(7 downto 0);
data_a: out std_logic_vector(7 downto 0);
data_b: out std_logic_vector(7 downto 0);
operation: out std_logic_vector(7 downto 0)
);
end component;
begin
----------------------------------------------
-- Components Instantiation
----------------------------------------------
uut: component interfaceControl port map(
-- Controle
clk => clk_50m, -- seta clock para o gerado por este rtl
reset => rst, -- seta o reset para o gerado por este rtl
-- interface de entrada
rx_data_ready => rx_ready_in, -- seta o pino que anuncia a transmissão
rx_data => rx_data_in, -- seta o pino que tem os dados da transmissão
-- Saídas
data_a => open,
data_b => open,
operation => open
);
----------------------------------------------
-- Main Signals Generation
----------------------------------------------
-- gera clocl que é enviado para o modulo de interface_control
main_clock_generation : process
begin
wait for MAIN_CLK_PER / 2;
clk_50m <= not clk_50m;
end process;
envia_dados : process
variable temp : integer := 1;
begin
--verifica qual o valor de temp, pois temp define qual dado será enviado
if temp = 1 then
rx_data_in <= "00000001";
temp:= temp +1;
elsif temp = 2 then
rx_data_in <= "01000010";
temp:= temp+1;
else
rx_data_in <= "11111111";
end if;
-- atraso
wait for 100ns;
-- rx_ready_in fica com valor '1' durante tempo de um pulso de clock
rx_ready_in <= '1';
wait for MAIN_CLK_PER / 2;
rx_ready_in <= '0';
-- reinicia a variavel temp e envia um reset caso 3 dados já forem enviados
if temp = 3 then
temp := 1;
wait for 200ns;
rst <= '0';
wait for MAIN_CLK_PER /2;
rst <= '1';
end if;
end process envia_dados;
end Behavioral;
|
gpl-2.0
|
a2bd0142c3fb59cc65a31a95ea623be3
| 0.498261 | 3.872539 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/modules/wb_position_calc/xwb_position_calc_core.vhd
| 1 | 25,686 |
------------------------------------------------------------------------------
-- Title : Wishbone Position Calculation Core
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-07-02
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Core Module for position calculation with de-cross, amplitude compensation
-- and delay tuning.
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-07-02 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- DSP Cores
use work.dsp_cores_pkg.all;
-- BPM cores
use work.bpm_cores_pkg.all;
-- Position Calc
use work.position_calc_core_pkg.all;
entity xwb_position_calc_core is
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_with_extra_wb_reg : boolean := false;
g_rffe_version : string := "V2";
-- selection of position_calc stages
g_with_downconv : boolean := true;
-- input sizes
g_input_width : natural := 16;
g_mixed_width : natural := 16;
g_adc_ratio : natural := 1;
-- mixer
g_dds_width : natural := 16;
g_dds_points : natural := 35;
g_sin_file : string := "../../../dsp-cores/hdl/modules/position_nosysgen/dds_sin.nif";
g_cos_file : string := "../../../dsp-cores/hdl/modules/position_nosysgen/dds_cos.nif";
-- CIC setup
g_tbt_cic_delay : natural := 1;
g_tbt_cic_stages : natural := 2;
g_tbt_ratio : natural := 35; -- ratio between
g_tbt_decim_width : natural := 32;
g_fofb_cic_delay : natural := 1;
g_fofb_cic_stages : natural := 2;
g_fofb_ratio : natural := 980; -- ratio between adc and fofb rates
g_fofb_decim_width : natural := 32;
g_monit1_cic_delay : natural := 1;
g_monit1_cic_stages : natural := 1;
g_monit1_ratio : natural := 100; --ratio between fofb and monit 1
g_monit1_cic_ratio : positive := 8;
g_monit2_cic_delay : natural := 1;
g_monit2_cic_stages : natural := 1;
g_monit2_ratio : natural := 100; -- ratio between monit 1 and 2
g_monit2_cic_ratio : positive := 8;
g_monit_decim_width : natural := 32;
-- Cordic setup
g_tbt_cordic_stages : positive := 12;
g_tbt_cordic_iter_per_clk : positive := 3;
g_tbt_cordic_ratio : positive := 4;
g_fofb_cordic_stages : positive := 15;
g_fofb_cordic_iter_per_clk : positive := 3;
g_fofb_cordic_ratio : positive := 4;
-- width of K constants
g_k_width : natural := 25;
-- width of offset constants
g_offset_width : natural := 32;
--width for IQ output
g_IQ_width : natural := 32;
-- Swap/de-swap setup
g_delay_vec_width : natural := 8;
g_swap_div_freq_vec_width : natural := 16
);
port
(
rst_n_i : in std_logic;
clk_i : in std_logic; -- Wishbone clock
fs_rst_n_i : in std_logic; -- FS reset
fs_rst2x_n_i : in std_logic; -- FS 2x reset
fs_clk_i : in std_logic; -- clock period = 8.8823218389287 ns (112.583175675676 Mhz)
fs_clk2x_i : in std_logic; -- clock period = 4.4411609194644 ns (225.166351351351 Mhz)
-----------------------------
-- Wishbone signals
-----------------------------
wb_slv_i : in t_wishbone_slave_in;
wb_slv_o : out t_wishbone_slave_out;
-----------------------------
-- Raw ADC signals
-----------------------------
adc_ch0_i : in std_logic_vector(g_input_width-1 downto 0);
adc_ch1_i : in std_logic_vector(g_input_width-1 downto 0);
adc_ch2_i : in std_logic_vector(g_input_width-1 downto 0);
adc_ch3_i : in std_logic_vector(g_input_width-1 downto 0);
adc_valid_i : in std_logic;
-----------------------------
-- Position calculation at various rates
-----------------------------
adc_ch0_swap_o : out std_logic_vector(g_input_width-1 downto 0);
adc_ch1_swap_o : out std_logic_vector(g_input_width-1 downto 0);
adc_ch2_swap_o : out std_logic_vector(g_input_width-1 downto 0);
adc_ch3_swap_o : out std_logic_vector(g_input_width-1 downto 0);
adc_tag_o : out std_logic_vector(0 downto 0);
adc_swap_valid_o : out std_logic;
-----------------------------
-- MIX Data
-----------------------------
mix_ch0_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch0_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch1_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch1_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch2_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch2_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch3_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_ch3_q_o : out std_logic_vector(g_IQ_width-1 downto 0);
mix_valid_o : out std_logic;
-----------------------------
-- TBT Data
-----------------------------
tbt_decim_ch0_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch0_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch1_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch1_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch2_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch2_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch3_i_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_ch3_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_decim_valid_o : out std_logic;
tbt_amp_ch0_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_ch1_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_ch2_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_ch3_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_amp_valid_o : out std_logic;
tbt_pha_ch0_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_ch1_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_ch2_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_ch3_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pha_valid_o : out std_logic;
-----------------------------
-- FOFB Data
-----------------------------
fofb_decim_ch0_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch0_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch1_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch1_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch2_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch2_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch3_i_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_ch3_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_decim_valid_o : out std_logic;
fofb_amp_ch0_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_ch1_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_ch2_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_ch3_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_amp_valid_o : out std_logic;
fofb_pha_ch0_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_ch1_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_ch2_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_ch3_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pha_valid_o : out std_logic;
-----------------------------
-- Monit. Data
-----------------------------
monit1_amp_ch0_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_ch1_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_ch2_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_ch3_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_amp_valid_o : out std_logic;
monit_amp_ch0_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_ch1_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_ch2_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_ch3_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_amp_valid_o : out std_logic;
-----------------------------
-- Position Data
-----------------------------
tbt_pos_x_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_y_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_q_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_sum_o : out std_logic_vector(g_tbt_decim_width-1 downto 0);
tbt_pos_valid_o : out std_logic;
fofb_pos_x_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_y_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_q_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_sum_o : out std_logic_vector(g_fofb_decim_width-1 downto 0);
fofb_pos_valid_o : out std_logic;
monit1_pos_x_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_y_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_q_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_sum_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit1_pos_valid_o : out std_logic;
monit_pos_x_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_y_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_q_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_sum_o : out std_logic_vector(g_monit_decim_width-1 downto 0);
monit_pos_valid_o : out std_logic;
-----------------------------
-- Output to RFFE board
-----------------------------
rffe_swclk_o : out std_logic;
-----------------------------
-- Synchronization trigger for all rates. Slow clock
-----------------------------
sync_trig_slow_i : in std_logic;
-----------------------------
-- Debug signals
-----------------------------
dbg_cur_address_o : out std_logic_vector(31 downto 0);
dbg_adc_ch0_cond_o : out std_logic_vector(g_input_width-1 downto 0);
dbg_adc_ch1_cond_o : out std_logic_vector(g_input_width-1 downto 0);
dbg_adc_ch2_cond_o : out std_logic_vector(g_input_width-1 downto 0);
dbg_adc_ch3_cond_o : out std_logic_vector(g_input_width-1 downto 0)
);
end xwb_position_calc_core;
architecture rtl of xwb_position_calc_core is
begin
cmp_wb_position_calc_core : wb_position_calc_core
generic map
(
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
g_with_extra_wb_reg => g_with_extra_wb_reg,
g_rffe_version => g_rffe_version,
-- selection of position_calc stages
g_with_downconv => g_with_downconv,
-- input sizes
g_input_width => g_input_width,
g_mixed_width => g_mixed_width,
g_adc_ratio => g_adc_ratio,
-- mixer
g_dds_width => g_dds_width,
g_dds_points => g_dds_points,
g_sin_file => g_sin_file,
g_cos_file => g_cos_file,
-- CIC setup
g_tbt_cic_delay => g_tbt_cic_delay,
g_tbt_cic_stages => g_tbt_cic_stages,
g_tbt_ratio => g_tbt_ratio,
g_tbt_decim_width => g_tbt_decim_width,
g_fofb_cic_delay => g_fofb_cic_delay,
g_fofb_cic_stages => g_fofb_cic_stages,
g_fofb_ratio => g_fofb_ratio,
g_fofb_decim_width => g_fofb_decim_width,
g_monit1_cic_delay => g_monit1_cic_delay,
g_monit1_cic_stages => g_monit1_cic_stages,
g_monit1_ratio => g_monit1_ratio,
g_monit1_cic_ratio => g_monit1_cic_ratio,
g_monit2_cic_delay => g_monit2_cic_delay,
g_monit2_cic_stages => g_monit2_cic_stages,
g_monit2_ratio => g_monit2_ratio,
g_monit2_cic_ratio => g_monit2_cic_ratio,
g_monit_decim_width => g_monit_decim_width,
-- Cordic setup
g_tbt_cordic_stages => g_tbt_cordic_stages,
g_tbt_cordic_iter_per_clk => g_tbt_cordic_iter_per_clk,
g_tbt_cordic_ratio => g_tbt_cordic_ratio,
g_fofb_cordic_stages => g_fofb_cordic_stages,
g_fofb_cordic_iter_per_clk => g_fofb_cordic_iter_per_clk,
g_fofb_cordic_ratio => g_fofb_cordic_ratio,
-- width of K constants
g_k_width => g_k_width,
--width for IQ output
g_IQ_width => g_IQ_width,
-- Swap/de-swap setup
g_delay_vec_width => g_delay_vec_width,
g_swap_div_freq_vec_width => g_swap_div_freq_vec_width
)
port map
(
rst_n_i => rst_n_i,
clk_i => clk_i,
fs_rst_n_i => fs_rst_n_i,
fs_rst2x_n_i => fs_rst2x_n_i,
fs_clk_i => fs_clk_i, -- clock period = 8.8823218389287 ns (112.583175675676 Mhz)
fs_clk2x_i => fs_clk2x_i, -- clock period = 4.44116091946435 ns (225.16635135135124 Mhz)
-----------------------------
-- Wishbone signals
-----------------------------
wb_adr_i => wb_slv_i.adr,
wb_dat_i => wb_slv_i.dat,
wb_dat_o => wb_slv_o.dat,
wb_sel_i => wb_slv_i.sel,
wb_we_i => wb_slv_i.we,
wb_cyc_i => wb_slv_i.cyc,
wb_stb_i => wb_slv_i.stb,
wb_ack_o => wb_slv_o.ack,
wb_stall_o => wb_slv_o.stall,
-----------------------------
-- Raw ADC signals
-----------------------------
adc_ch0_i => adc_ch0_i,
adc_ch1_i => adc_ch1_i,
adc_ch2_i => adc_ch2_i,
adc_ch3_i => adc_ch3_i,
adc_valid_i => adc_valid_i,
-----------------------------
-- Position calculation at various rates
-----------------------------
adc_ch0_swap_o => adc_ch0_swap_o,
adc_ch1_swap_o => adc_ch1_swap_o,
adc_ch2_swap_o => adc_ch2_swap_o,
adc_ch3_swap_o => adc_ch3_swap_o,
adc_tag_o => adc_tag_o,
adc_swap_valid_o => adc_swap_valid_o,
-----------------------------
-- MIX Data
-----------------------------
mix_ch0_i_o => mix_ch0_i_o,
mix_ch0_q_o => mix_ch0_q_o,
mix_ch1_i_o => mix_ch1_i_o,
mix_ch1_q_o => mix_ch1_q_o,
mix_ch2_i_o => mix_ch2_i_o,
mix_ch2_q_o => mix_ch2_q_o,
mix_ch3_i_o => mix_ch3_i_o,
mix_ch3_q_o => mix_ch3_q_o,
mix_valid_o => mix_valid_o,
-----------------------------
-- TBT Data
-----------------------------
tbt_decim_ch0_i_o => tbt_decim_ch0_i_o,
tbt_decim_ch0_q_o => tbt_decim_ch0_q_o,
tbt_decim_ch1_i_o => tbt_decim_ch1_i_o,
tbt_decim_ch1_q_o => tbt_decim_ch1_q_o,
tbt_decim_ch2_i_o => tbt_decim_ch2_i_o,
tbt_decim_ch2_q_o => tbt_decim_ch2_q_o,
tbt_decim_ch3_i_o => tbt_decim_ch3_i_o,
tbt_decim_ch3_q_o => tbt_decim_ch3_q_o,
tbt_decim_valid_o => tbt_decim_valid_o,
tbt_amp_ch0_o => tbt_amp_ch0_o,
tbt_amp_ch1_o => tbt_amp_ch1_o,
tbt_amp_ch2_o => tbt_amp_ch2_o,
tbt_amp_ch3_o => tbt_amp_ch3_o,
tbt_amp_valid_o => tbt_amp_valid_o,
tbt_pha_ch0_o => tbt_pha_ch0_o,
tbt_pha_ch1_o => tbt_pha_ch1_o,
tbt_pha_ch2_o => tbt_pha_ch2_o,
tbt_pha_ch3_o => tbt_pha_ch3_o,
tbt_pha_valid_o => tbt_pha_valid_o,
-----------------------------
-- FOFB Data
-----------------------------
fofb_decim_ch0_i_o => fofb_decim_ch0_i_o,
fofb_decim_ch0_q_o => fofb_decim_ch0_q_o,
fofb_decim_ch1_i_o => fofb_decim_ch1_i_o,
fofb_decim_ch1_q_o => fofb_decim_ch1_q_o,
fofb_decim_ch2_i_o => fofb_decim_ch2_i_o,
fofb_decim_ch2_q_o => fofb_decim_ch2_q_o,
fofb_decim_ch3_i_o => fofb_decim_ch3_i_o,
fofb_decim_ch3_q_o => fofb_decim_ch3_q_o,
fofb_decim_valid_o => fofb_decim_valid_o,
fofb_amp_ch0_o => fofb_amp_ch0_o,
fofb_amp_ch1_o => fofb_amp_ch1_o,
fofb_amp_ch2_o => fofb_amp_ch2_o,
fofb_amp_ch3_o => fofb_amp_ch3_o,
fofb_amp_valid_o => fofb_amp_valid_o,
fofb_pha_ch0_o => fofb_pha_ch0_o,
fofb_pha_ch1_o => fofb_pha_ch1_o,
fofb_pha_ch2_o => fofb_pha_ch2_o,
fofb_pha_ch3_o => fofb_pha_ch3_o,
fofb_pha_valid_o => fofb_pha_valid_o,
-----------------------------
-- Monit. Data
-----------------------------
monit1_amp_ch0_o => monit1_amp_ch0_o,
monit1_amp_ch1_o => monit1_amp_ch1_o,
monit1_amp_ch2_o => monit1_amp_ch2_o,
monit1_amp_ch3_o => monit1_amp_ch3_o,
monit1_amp_valid_o => monit1_amp_valid_o,
monit_amp_ch0_o => monit_amp_ch0_o,
monit_amp_ch1_o => monit_amp_ch1_o,
monit_amp_ch2_o => monit_amp_ch2_o,
monit_amp_ch3_o => monit_amp_ch3_o,
monit_amp_valid_o => monit_amp_valid_o,
-----------------------------
-- Position Data
-----------------------------
tbt_pos_x_o => tbt_pos_x_o,
tbt_pos_y_o => tbt_pos_y_o,
tbt_pos_q_o => tbt_pos_q_o,
tbt_pos_sum_o => tbt_pos_sum_o,
tbt_pos_valid_o => tbt_pos_valid_o,
fofb_pos_x_o => fofb_pos_x_o,
fofb_pos_y_o => fofb_pos_y_o,
fofb_pos_q_o => fofb_pos_q_o,
fofb_pos_sum_o => fofb_pos_sum_o,
fofb_pos_valid_o => fofb_pos_valid_o,
monit1_pos_x_o => monit1_pos_x_o,
monit1_pos_y_o => monit1_pos_y_o,
monit1_pos_q_o => monit1_pos_q_o,
monit1_pos_sum_o => monit1_pos_sum_o,
monit1_pos_valid_o => monit1_pos_valid_o,
monit_pos_x_o => monit_pos_x_o,
monit_pos_y_o => monit_pos_y_o,
monit_pos_q_o => monit_pos_q_o,
monit_pos_sum_o => monit_pos_sum_o,
monit_pos_valid_o => monit_pos_valid_o,
-----------------------------
-- Output to RFFE board
-----------------------------
rffe_swclk_o => rffe_swclk_o,
-----------------------------
-- Synchronization trigger for all rates. Slow clock
-----------------------------
sync_trig_slow_i => sync_trig_slow_i,
-----------------------------
-- Debug signals
-----------------------------
dbg_cur_address_o => dbg_cur_address_o,
dbg_adc_ch0_cond_o => dbg_adc_ch0_cond_o,
dbg_adc_ch1_cond_o => dbg_adc_ch1_cond_o,
dbg_adc_ch2_cond_o => dbg_adc_ch2_cond_o,
dbg_adc_ch3_cond_o => dbg_adc_ch3_cond_o
);
end rtl;
|
lgpl-3.0
|
71a3eba81d0d3b9b7858e2326944a51b
| 0.405357 | 3.771806 | false | false | false | false |
nanomolina/MIPS
|
prueba/ID_EX.vhd
| 1 | 1,869 |
library ieee;
use ieee.std_logic_1164.all;
entity ID_EX is
port (
RtD_in : in std_logic_vector(4 downto 0);
RdD_in : in std_logic_vector(4 downto 0);
SignImm_in : in std_logic_vector(31 downto 0);
RD1_in : in std_logic_vector(31 downto 0);
RD2_in : in std_logic_vector(31 downto 0);
PCPlus4_in: in std_logic_vector(31 downto 0);
MemToReg_in: in std_logic;
MemWrite_in: in std_logic;
Branch_in: in std_logic;
AluSrc_in: in std_logic;
RegDst_in: in std_logic;
RegWrite_in: in std_logic;
Jump_in: in std_logic;
alucontrol_in: in std_logic_vector (2 downto 0);
clk : in std_logic;
PCPlus4_out: out std_logic_vector(31 downto 0);
MemToReg_out: out std_logic;
MemWrite_out: out std_logic;
Branch_out: out std_logic;
AluSrc_out: out std_logic;
RegDst_out: out std_logic;
RegWrite_out: out std_logic;
Jump_out: out std_logic;
alucontrol_out: out std_logic_vector (2 downto 0);
RtD_out : out std_logic_vector(4 downto 0);
RdD_out : out std_logic_vector(4 downto 0);
SignImm_out : out std_logic_vector(31 downto 0);
RD1_out : out std_logic_vector(31 downto 0);
RD2_out : out std_logic_vector(31 downto 0)
);
end entity;
architecture BH of ID_EX is
begin
process (clk) begin
if (clk'event and clk = '1') then
MemToReg_out <= MemToReg_in;
MemWrite_out <= MemWrite_in;
Branch_out <= Branch_in;
AluSrc_out <= AluSrc_in;
RegDst_out <= RegDst_in;
RegWrite_out <= RegWrite_in;
Jump_out <= Jump_in;
alucontrol_out <= alucontrol_in;
RtD_out <= RtD_in;
RdD_out <= RdD_in;
SignImm_out <= SignImm_in;
RD1_out <= RD1_in;
RD2_out <= RD2_in;
end if;
end process;
end BH;
|
gpl-3.0
|
5b76df1ed63ee249f97c22e482aa8c11
| 0.589085 | 3.053922 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/modules/input_gen/input_gen.vhd
| 1 | 4,746 |
-------------------------------------------------------------------------------
-- Title : Input generator
-- Project :
-------------------------------------------------------------------------------
-- File : input_gen.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-06-26
-- Last update: 2015-10-15
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Simulates an input signal using hardware.
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-06-26 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.dsp_cores_pkg.all;
use work.bpm_cores_pkg.all;
-------------------------------------------------------------------------------
entity input_gen is
generic (
g_input_width : natural := 16;
g_output_width : natural := 16;
g_ksum : integer := 1
);
port (
x_i : in std_logic_vector(g_input_width-1 downto 0);
y_i : in std_logic_vector(g_input_width-1 downto 0);
clk_i : in std_logic;
ce_i : in std_logic;
a_o : out std_logic_vector(g_output_width-1 downto 0);
b_o : out std_logic_vector(g_output_width-1 downto 0);
c_o : out std_logic_vector(g_output_width-1 downto 0);
d_o : out std_logic_vector(g_output_width-1 downto 0)
);
end entity input_gen;
-------------------------------------------------------------------------------
architecture str of input_gen is
signal a_bb, b_bb, c_bb, d_bb : std_logic_vector(g_input_width-1 downto 0) := (others => '0');
signal sin, cos : std_logic_vector(23 downto 0);
constant c_ksum : signed(g_input_width-1 downto 0) := to_signed(g_ksum,g_input_width);
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
begin -- architecture str
calculate : process(clk_i)
variable x, y : signed(g_input_width-1 downto 0);
begin
if rising_edge(clk_i) then
if ce_i = '1' then
x := signed(x_i);
y := signed(y_i);
a_bb <= std_logic_vector(c_ksum - x + y);
b_bb <= std_logic_vector(c_ksum + x + y);
c_bb <= std_logic_vector(c_ksum + x - y);
d_bb <= std_logic_vector(c_ksum - x - y);
end if; --clk
end if; -- ce
end process calculate;
cmp_dds : fixed_dds
generic map (
g_number_of_points => 6,
g_output_width => 24,
g_sin_file => "./dds_sin.nif",
g_cos_file => "./dds_cos.nif")
port map (
clk_i => clk_i,
ce_i => ce_i,
rst_i => '0',
valid_i => '1',
sin_o => sin,
cos_o => cos);
cmp_mod_a : generic_multiplier
generic map (
g_a_width => 16,
g_b_width => 24,
g_signed => true,
g_p_width => g_output_width,
g_levels => 6)
port map (
a_i => a_bb,
b_i => sin,
valid_i => '1',
p_o => a_o,
ce_i => ce_i,
clk_i => clk_i,
rst_i => '0');
cmp_mod_b : generic_multiplier
generic map (
g_a_width => g_input_width,
g_b_width => 24,
g_signed => true,
g_p_width => g_output_width,
g_levels => 6)
port map (
a_i => b_bb,
b_i => sin,
valid_i => '1',
p_o => b_o,
ce_i => ce_i,
clk_i => clk_i,
rst_i => '0');
cmp_mod_c : generic_multiplier
generic map (
g_a_width => g_input_width,
g_b_width => 24,
g_signed => true,
g_p_width => g_output_width,
g_levels => 6)
port map (
a_i => c_bb,
b_i => cos,
valid_i => '1',
p_o => c_o,
ce_i => ce_i,
clk_i => clk_i,
rst_i => '0');
cmp_mod_d : generic_multiplier
generic map (
g_a_width => g_input_width,
g_b_width => 24,
g_signed => true,
g_p_width => g_output_width,
g_levels => 6)
port map (
a_i => d_bb,
b_i => cos,
valid_i => '1',
p_o => d_o,
ce_i => ce_i,
clk_i => clk_i,
rst_i => '0');
end architecture str;
-------------------------------------------------------------------------------
|
lgpl-3.0
|
a909a8d3643a6beec35fc72690d2b1d2
| 0.405183 | 3.466764 | false | false | false | false |
mithro/soft-utmi
|
hdl/third_party/XAPP1064-serdes-macros/VHDL_Source/Top level examples/BUFIO2 DDR/top_nto1_ddr_se_rx.vhd
| 1 | 7,746 |
------------------------------------------------------------------------------/
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------/
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: top_nto1_ddr_se_rx.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: June 1 2009
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: Example single ended input receiver for DDR clock and data using 2 x BUFIO2
-- Serdes factor and number of data lines are set by constants in the code
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
--
------------------------------------------------------------------------------/
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and signalulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity top_nto1_ddr_se_rx is port (
reset : in std_logic ; -- reset (active high)
datain : in std_logic_vector(7 downto 0) ; -- single ended data inputs
clkin1, clkin2 : in std_logic ; -- TWO single ended clock input
dummy_out : out std_logic_vector(63 downto 0) ) ; -- dummy outputs
end top_nto1_ddr_se_rx ;
architecture arch_top_nto1_ddr_se_rx of top_nto1_ddr_se_rx is
component serdes_1_to_n_clk_ddr_s8_se is generic (
S : integer := 8) ; -- Parameter to set the serdes factor 1..8
port (
clkin1 : in std_logic ; -- Input from se receiver pin
clkin2 : in std_logic ; -- Input from se receiver pin
rxioclkp : out std_logic ; -- IO Clock network
rxioclkn : out std_logic ; -- IO Clock network
rx_serdesstrobe : out std_logic ; -- Parallel data capture strobe
rx_bufg_x1 : out std_logic) ; -- Global clock
end component ;
component serdes_1_to_n_data_ddr_s8_se is generic (
USE_PD : boolean := FALSE ; -- Parameter to set generation of phase detector logic
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
D : integer := 16) ; -- Set the number of inputs and outputs
port (
use_phase_detector : in std_logic ; -- '1' enables the phase detector logic if USE_PD = TRUE
datain : in std_logic_vector(D-1 downto 0) ; -- Input from LVDS receiver pin
rxioclkp : in std_logic ; -- IO Clock network
rxioclkn : in std_logic ; -- IO Clock network
rxserdesstrobe : in std_logic ; -- Parallel data capture strobe
reset : in std_logic ; -- Reset line
gclk : in std_logic ; -- Global clock
bitslip : in std_logic ; -- Bitslip control line
data_out : out std_logic_vector((D*S)-1 downto 0) ; -- Output data
debug_in : in std_logic_vector(1 downto 0) ; -- Debug Inputs, set to '0' if not required
debug : out std_logic_vector((2*D)+6 downto 0)) ; -- Debug output bus, 2D+6 = 2 lines per input (from mux and ce) + 7, leave nc if debug not required
end component ;
-- constants for serdes factor and number of IO pins
constant S : integer := 8 ; -- Set the serdes factor to 8
constant D : integer := 8 ; -- Set the number of inputs and outputs
constant DS : integer := (D*S)-1 ; -- Used for bus widths = serdes factor * number of inputs - 1
signal rst : std_logic ;
signal rxd : std_logic_vector(DS downto 0) ; -- Data from serdeses
signal rxr : std_logic_vector(DS downto 0); -- signalistered Data from serdeses
signal state : std_logic ;
signal bslip : std_logic ;
signal count : std_logic_vector(3 downto 0);
signal rxioclkp : std_logic ;
signal rxioclkn : std_logic ;
signal rx_serdesstrobe : std_logic ;
signal rx_bufg_x1 : std_logic ;
begin
rst <= reset ; -- active high reset pin
dummy_out <= rxr ;
-- Clock Input. Generate ioclocks via BUFIO2
inst_clkin : serdes_1_to_n_clk_ddr_s8_se generic map(
S => S)
port map (
clkin1 => clkin1,
clkin2 => clkin2,
rxioclkp => rxioclkp,
rxioclkn => rxioclkn,
rx_serdesstrobe => rx_serdesstrobe,
rx_bufg_x1 => rx_bufg_x1);
-- Data Inputs
inst_datain : serdes_1_to_n_data_ddr_s8_se generic map(
S => S,
D => D,
USE_PD => TRUE) -- Enables use of the phase detector - will require 2 input serdes whatever the serdes ratio required
port map (
use_phase_detector => '1', -- '1' enables the phase detector logic
datain => datain,
rxioclkp => rxioclkp,
rxioclkn => rxioclkn,
rxserdesstrobe => rx_serdesstrobe,
gclk => rx_bufg_x1,
bitslip => bslip,
reset => rst,
data_out => rxd,
debug_in => "00",
debug => open);
process (rx_bufg_x1, rst) -- example bitslip logic, if required
begin
if rst = '1' then
state <= '0' ;
bslip <= '1' ;
count <= "0000" ;
elsif rx_bufg_x1'event and rx_bufg_x1 = '1' then
if state = '0' then
if rxd(63 downto 60) /= "0011" then
bslip <= '1' ; -- bitslip needed
state <= '1' ;
count <= "0000" ;
end if ;
elsif state = '1' then
bslip <= '0' ; -- bitslip low
count <= count + 1 ;
if count = "1111" then
state <= '0' ;
end if ;
end if ;
end if ;
end process ;
process (rx_bufg_x1) -- process received data
begin
if rx_bufg_x1'event and rx_bufg_x1 = '1' then
rxr <= rxd ;
end if ;
end process ;
end arch_top_nto1_ddr_se_rx ;
|
apache-2.0
|
92c843fc73e9e9b0b068cfaa335c32ec
| 0.606507 | 3.42289 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/tests/serialization/AssignToASliceOfReg2a.vhd
| 1 | 2,899 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- Register where an overlapping slices of next signal are set conditionally
--
ENTITY AssignToASliceOfReg2a IS
PORT(
clk : IN STD_LOGIC;
data_in_addr : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
data_in_data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
data_in_mask : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
data_in_rd : OUT STD_LOGIC;
data_in_vld : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
rst_n : IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF AssignToASliceOfReg2a IS
SIGNAL r : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL r_next : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL r_next_11downto8 : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL r_next_15downto12 : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL r_next_3downto0 : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL r_next_7downto4 : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
data_in_rd <= '1';
data_out <= r;
assig_process_r: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst_n = '0' THEN
r <= X"0000";
ELSE
r <= r_next;
END IF;
END IF;
END PROCESS;
r_next <= r_next_15downto12 & r_next_11downto8 & r_next_7downto4 & r_next_3downto0;
assig_process_r_next_11downto8: PROCESS(data_in_addr, data_in_data, data_in_mask, data_in_vld, r)
BEGIN
IF data_in_vld = '1' AND data_in_addr = "1" THEN
IF data_in_mask = X"FF" THEN
r_next_11downto8 <= data_in_data(3 DOWNTO 0);
r_next_15downto12 <= data_in_data(7 DOWNTO 4);
ELSIF data_in_mask = X"0F" THEN
r_next_11downto8 <= data_in_data(3 DOWNTO 0);
r_next_15downto12 <= r(15 DOWNTO 12);
ELSE
r_next_11downto8 <= r(11 DOWNTO 8);
r_next_15downto12 <= r(15 DOWNTO 12);
END IF;
ELSE
r_next_11downto8 <= r(11 DOWNTO 8);
r_next_15downto12 <= r(15 DOWNTO 12);
END IF;
END PROCESS;
assig_process_r_next_3downto0: PROCESS(data_in_addr, data_in_data, data_in_mask, data_in_vld, r)
BEGIN
IF data_in_vld = '1' AND data_in_addr = "0" THEN
IF data_in_mask = X"FF" THEN
r_next_3downto0 <= data_in_data(3 DOWNTO 0);
r_next_7downto4 <= data_in_data(7 DOWNTO 4);
ELSIF data_in_mask = X"0F" THEN
r_next_3downto0 <= data_in_data(3 DOWNTO 0);
r_next_7downto4 <= r(7 DOWNTO 4);
ELSE
r_next_3downto0 <= r(3 DOWNTO 0);
r_next_7downto4 <= r(7 DOWNTO 4);
END IF;
ELSE
r_next_3downto0 <= r(3 DOWNTO 0);
r_next_7downto4 <= r(7 DOWNTO 4);
END IF;
END PROCESS;
END ARCHITECTURE;
|
mit
|
8e1191f536f34f0b85c47017232cdc55
| 0.553294 | 3.235491 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/modules/machine/sirius_bo_250M/dds_sin_lut.vhd
| 1 | 2,440 |
-------------------------------------------------------------------------------
-- Title : Vivadi DDS sin lut for SIRIUS 130M
-- Project :
-------------------------------------------------------------------------------
-- File : dds_sin_lut.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2015-04-15
-- Last update: 2016-04-06
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Temporary sine lut for SIRIUS machine with 130M ADC generated
-- through Vivado.
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-04-15 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genram_pkg.all;
-------------------------------------------------------------------------------
entity dds_sin_lut is
port (
clka : in std_logic;
addra : in std_logic_vector(7 downto 0);
douta : out std_logic_vector(15 downto 0)
);
end entity dds_sin_lut;
architecture str of dds_sin_lut is
component generic_rom
generic (
g_data_width : natural := 32;
g_size : natural := 16384;
g_init_file : string := "";
g_fail_if_file_not_found : boolean := true
);
port (
rst_n_i : in std_logic; -- synchronous reset, active LO
clk_i : in std_logic; -- clock input
-- address input
a_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
-- data output
q_o : out std_logic_vector(g_data_width-1 downto 0)
);
end component;
begin
cmp_sin_lut_sirius_52_181_1 : generic_rom
generic map (
g_data_width => 16,
g_size => 181,
g_init_file => "sin_lut_sirius_52_181.mif",
g_fail_if_file_not_found => true
)
port map (
rst_n_i => '1',
clk_i => clka,
a_i => addra,
q_o => douta
);
end architecture str;
|
lgpl-3.0
|
e4251eda6c5f63e2fd5b9eeb46924639
| 0.391393 | 4.428312 | false | false | false | false |
mithro/soft-utmi
|
hdl/third_party/XAPP1064-serdes-macros/VHDL_Source/Macros/serdes_1_to_n_data_ddr_s8_se.vhd
| 1 | 19,136 |
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: serdes_1_to_n_data_ddr_s8_se.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: August 1 2008
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: D-bit generic 1:n data receiver module with differential inputs for DDR systems
-- Takes in 1 bit of differential data and deserialises this to n bits
-- data is received LSB first
-- Serial input words
-- Line0 : 0, ...... DS-(S+1)
-- Line1 : 1, ...... DS-(S+2)
-- Line(D-1) : . .
-- Line(D) : D-1, ...... DS
-- Parallel output word
-- DS, DS-1 ..... 1, 0
--
-- Includes state machine to control CAL and the phase detector if required
-- Note for serdes factors of 4 and less, only one input delay and serdes is needed, this
-- makes use of the phase detector impossible unless USE_PD is set TRUE.
-- Data inversion can be accomplished via the RX_SWAP_MASK parameter if required
--
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity serdes_1_to_n_data_ddr_s8_se is generic (
USE_PD : boolean := FALSE ; -- Parameter to set generation of phase detector logic
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
D : integer := 16) ; -- Set the number of inputs and outputs
port (
use_phase_detector : in std_logic ; -- '1' enables the phase detector logic if USE_PD = TRUE
datain : in std_logic_vector(D-1 downto 0) ; -- Input from se receiver pin
rxioclkp : in std_logic ; -- IO Clock network
rxioclkn : in std_logic ; -- IO Clock network
rxserdesstrobe : in std_logic ; -- Parallel data capture strobe
reset : in std_logic ; -- Reset line
gclk : in std_logic ; -- Global clock
bitslip : in std_logic ; -- Bitslip control line
data_out : out std_logic_vector((D*S)-1 downto 0) ; -- Output data
debug_in : in std_logic_vector(1 downto 0) ; -- Debug Inputs, set to '0' if not required
debug : out std_logic_vector((2*D)+6 downto 0)) ; -- Debug output bus, 2D+6 = 2 lines per input (from mux and ce) + 7, leave nc if debug not required
end serdes_1_to_n_data_ddr_s8_se ;
architecture arch_serdes_1_to_n_data_ddr_s8_se of serdes_1_to_n_data_ddr_s8_se is
signal ddly_m : std_logic_vector(D-1 downto 0) ; -- Master output from IODELAY1
signal ddly_s : std_logic_vector(D-1 downto 0) ; -- Slave output from IODELAY1
signal mdataout : std_logic_vector((8*D)-1 downto 0) ;
signal cascade : std_logic_vector(D-1 downto 0) ;
signal pd_edge : std_logic_vector(D-1 downto 0) ;
signal busys : std_logic_vector(D-1 downto 0) ;
signal busym : std_logic_vector(D-1 downto 0) ;
signal rx_data_in : std_logic_vector(D-1 downto 0) ;
signal rx_data_in_fix : std_logic_vector(D-1 downto 0) ;
signal state : integer range 0 to 8 ;
signal busy_data_d : std_logic ;
signal busy_data : std_logic_vector(D-1 downto 0) ;
signal inc_data : std_logic ;
signal ce_data : std_logic_vector(D-1 downto 0) ;
signal incdec_data_d : std_logic ;
signal valid_data_d : std_logic ;
signal counter : std_logic_vector(8 downto 0) ;
signal enable : std_logic ;
signal cal_data_master : std_logic ;
signal rst_data : std_logic ;
signal pdcounter : std_logic_vector(4 downto 0) ;
signal ce_data_int : std_logic_vector(D-1 downto 0) ;
signal inc_data_int : std_logic ;
signal incdec_data : std_logic_vector(D-1 downto 0) ;
signal cal_data_slave : std_logic ;
signal valid_data : std_logic_vector(D-1 downto 0) ;
signal mux : std_logic_vector(D-1 downto 0) ;
signal ce_data_inta : std_logic ;
signal flag : std_logic ;
signal cal_data_sint : std_logic ;
signal incdec_data_or : std_logic_vector(D downto 0) ;
signal incdec_data_im : std_logic_vector(D-1 downto 0) ;
signal valid_data_or : std_logic_vector(D downto 0) ;
signal valid_data_im : std_logic_vector(D-1 downto 0) ;
signal busy_data_or : std_logic_vector(D downto 0) ;
signal all_ce : std_logic_vector(D-1 downto 0) ;
constant RX_SWAP_MASK : std_logic_vector(D-1 downto 0) := (others => '0') ; -- pinswap mask for input bits (0 = no swap (default), 1 = swap). Allows inputs to be connected the wrong way round to ease PCB routing.
begin
cal_data_slave <= cal_data_sint ;
debug <= mux & cal_data_master & rst_data & cal_data_slave & busy_data_d & inc_data & ce_data & valid_data_d & incdec_data_d ;
process (gclk, reset)
begin
if reset = '1' then
state <= 0 ;
cal_data_master <= '0' ;
cal_data_sint <= '0' ;
counter <= (others => '0') ;
enable <= '0' ;
counter <= (others => '0') ;
mux <= (0 => '1', others => '0') ;
elsif gclk'event and gclk = '1' then
counter <= counter + 1 ;
if counter(8) = '1' then
counter <= "000000000" ;
end if ;
if counter(5) = '1' then
enable <= '1' ;
end if ;
if state = 0 and enable = '1' then -- Wait for all IODELAYs to be available
cal_data_master <= '0' ;
cal_data_sint <= '0' ;
rst_data <= '0' ;
if busy_data_d = '0' then
state <= 1 ;
end if ;
elsif state = 1 then -- Issue calibrate command to both master and slave
cal_data_master <= '1' ;
cal_data_sint <= '1' ;
if busy_data_d = '1' then -- and wait for command to be accepted
state <= 2 ;
end if ;
elsif state = 2 then -- Now RST all master and slave IODELAYs
cal_data_master <= '0' ;
cal_data_sint <= '0' ;
if busy_data_d = '0' then
rst_data <= '1' ;
state <= 3 ;
end if ;
elsif state = 3 then -- Wait for all IODELAYs to be available
rst_data <= '0' ;
if busy_data_d = '0' then
state <= 4 ;
end if ;
elsif state = 4 then -- Hang around
if counter(8) = '1' then
state <= 5 ;
end if ;
elsif state = 5 then -- Calibrate slave only
if busy_data_d = '0' then
cal_data_sint <= '1' ;
state <= 6 ;
if D /= 1 then
mux <= mux(D-2 downto 0) & mux(D-1) ;
end if ;
end if ;
elsif state = 6 then -- Wait for command to be accepted
if busy_data_d = '1' then
cal_data_sint <= '0' ;
state <= 7 ;
end if ;
elsif state = 7 then -- Wait for all IODELAYs to be available, ie CAL command finished
cal_data_sint <= '0' ;
if busy_data_d = '0' then
state <= 4 ;
end if ;
end if ;
end if ;
end process ;
process (gclk, reset)
begin
if reset = '1' then
pdcounter <= "10000" ;
ce_data_inta <= '0' ;
flag <= '0' ;
elsif gclk'event and gclk = '1' then
busy_data_d <= busy_data_or(D) ;
if use_phase_detector = '1' and USE_PD = TRUE then -- decide whther pd is used
incdec_data_d <= incdec_data_or(D) ;
valid_data_d <= valid_data_or(D) ;
if ce_data_inta = '1' then
ce_data <= mux ;
else
ce_data <= (others => '0') ;
end if ;
if state = 7 then
flag <= '0' ;
elsif state /= 4 or busy_data_d = '1' then -- Reset filter if state machine issues a cal command or unit is busy
pdcounter <= "10000" ;
ce_data_inta <= '0' ;
elsif pdcounter = "11111" and flag = '0' then -- Filter has reached positive max - increment the tap count
ce_data_inta <= '1' ;
inc_data_int <= '1' ;
pdcounter <= "10000" ;
flag <= '0' ;
elsif pdcounter = "00000" and flag = '0' then -- Filter has reached negative max - decrement the tap count
ce_data_inta <= '1' ;
inc_data_int <= '0' ;
pdcounter <= "10000" ;
flag <= '0' ;
elsif valid_data_d = '1' then -- increment filter
ce_data_inta <= '0' ;
if incdec_data_d = '1' and pdcounter /= "11111" then
pdcounter <= pdcounter + 1 ;
elsif incdec_data_d = '0' and pdcounter /= "00000" then -- decrement filter
pdcounter <= pdcounter - 1 ;
end if ;
else
ce_data_inta <= '0' ;
end if ;
else
ce_data <= all_ce ;
inc_data_int <= debug_in(1) ;
end if ;
end if ;
end process ;
inc_data <= inc_data_int ;
incdec_data_or(0) <= '0' ; -- Input Mux - Initialise generate loop OR gates
valid_data_or(0) <= '0' ;
busy_data_or(0) <= '0' ;
loop0 : for i in 0 to (D - 1) generate
incdec_data_im(i) <= incdec_data(i) and mux(i) ; -- Input muxes
incdec_data_or(i+1) <= incdec_data_im(i) or incdec_data_or(i) ; -- AND gates to allow just one signal through at a tome
valid_data_im(i) <= valid_data(i) and mux(i) ; -- followed by an OR
valid_data_or(i+1) <= valid_data_im(i) or valid_data_or(i) ; -- for the three inputs from each PD
busy_data_or(i+1) <= busy_data(i) or busy_data_or(i) ; -- The busy signals just need an OR gate
all_ce(i) <= debug_in(0) ;
rx_data_in_fix(i) <= rx_data_in(i) xor RX_SWAP_MASK(i) ; -- Invert signals as required
iob_clk_in : IBUF port map (
I => datain(i),
O => rx_data_in(i));
loop2 : if (USE_PD = TRUE or S > 4) generate --Two oserdes are needed
busy_data(i) <= busys(i) ;
iodelay_m : IODELAY2 generic map(
DATA_RATE => "DDR", -- <SDR>, DDR
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL" , -- NORMAL, PCI
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_TYPE => "DIFF_PHASE_DETECTOR",-- "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
COUNTER_WRAPAROUND => "WRAPAROUND", -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN", -- "IO", "IDATAIN", "ODATAIN"
SERDES_MODE => "MASTER", -- <NONE>, MASTER, SLAVE
SIM_TAPDELAY_VALUE => 49) --
port map (
IDATAIN => rx_data_in_fix(i), -- data from primary IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_m(i), -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => rxioclkp, -- High speed clock for calibration
IOCLK1 => rxioclkn, -- High speed clock for calibration
CLK => gclk, -- Fabric clock (GCLK) for control signals
CAL => cal_data_master, -- Calibrate control signal
INC => inc_data, -- Increment counter
CE => ce_data(i), -- Clock Enable
RST => rst_data, -- Reset delay line
BUSY => open) ; -- output signal indicating sync circuit has finished / calibration has finished
iodelay_s : IODELAY2 generic map(
DATA_RATE => "DDR", -- <SDR>, DDR
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL" , -- NORMAL, PCI
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_TYPE => "DIFF_PHASE_DETECTOR",-- "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
COUNTER_WRAPAROUND => "WRAPAROUND", -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN", -- "IO", "IDATAIN", "ODATAIN"
SERDES_MODE => "SLAVE", -- <NONE>, MASTER, SLAVE
SIM_TAPDELAY_VALUE => 49) --
port map (
IDATAIN => rx_data_in_fix(i), -- data from primary IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_s(i), -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => rxioclkp, -- High speed clock for calibration
IOCLK1 => rxioclkn, -- High speed clock for calibration
CLK => gclk, -- Fabric clock (GCLK) for control signals
CAL => cal_data_slave, -- Calibrate control signal
INC => inc_data, -- Increment counter
CE => ce_data(i), -- Clock Enable
RST => rst_data, -- Reset delay line
BUSY => busys(i)) ; -- output signal indicating sync circuit has finished / calibration has finished
iserdes_m : ISERDES2 generic map (
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE => "DDR", -- <SDR>, DDR
BITSLIP_ENABLE => TRUE, -- <FALSE>, TRUE
SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE
INTERFACE_TYPE => "RETIMED") -- NETWORKING, NETWORKING_PIPELINED, <RETIMED>
port map (
D => ddly_m(i),
CE0 => '1',
CLK0 => rxioclkp,
CLK1 => rxioclkn,
IOCE => rxserdesstrobe,
RST => reset,
CLKDIV => gclk,
SHIFTIN => pd_edge(i),
BITSLIP => bitslip,
FABRICOUT => open,
Q4 => mdataout((8*i)+7),
Q3 => mdataout((8*i)+6),
Q2 => mdataout((8*i)+5),
Q1 => mdataout((8*i)+4),
DFB => open, -- are these the same as above? These were in Johns design
CFB0 => open,
CFB1 => open,
VALID => open,
INCDEC => open,
SHIFTOUT => cascade(i));
iserdes_s : ISERDES2 generic map(
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE => "DDR", -- <SDR>, DDR
BITSLIP_ENABLE => TRUE, -- <FALSE>, TRUE
SERDES_MODE => "SLAVE", -- <DEFAULT>, MASTER, SLAVE
INTERFACE_TYPE => "RETIMED") -- NETWORKING, NETWORKING_PIPELINED, <RETIMED>
port map (
D => ddly_s(i),
CE0 => '1',
CLK0 => rxioclkp,
CLK1 => rxioclkn,
IOCE => rxserdesstrobe,
RST => reset,
CLKDIV => gclk,
SHIFTIN => cascade(i),
BITSLIP => bitslip,
FABRICOUT => open,
Q4 => mdataout((8*i)+3),
Q3 => mdataout((8*i)+2),
Q2 => mdataout((8*i)+1),
Q1 => mdataout((8*i)+0),
DFB => open, -- are these the same as above? These were in Johns design
CFB0 => open,
CFB1 => open,
VALID => open,
INCDEC => open,
SHIFTOUT => pd_edge(i));
end generate ;
loop3 : if (USE_PD /= TRUE and S < 5) generate -- Only one oserdes is needed
busy_data(i) <= busym(i) ;
iodelay_m : IODELAY2 generic map(
DATA_RATE => "DDR", -- <SDR>, DDR
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL" , -- NORMAL, PCI
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_TYPE => "VARIABLE_FROM_HALF_MAX",-- "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
COUNTER_WRAPAROUND => "WRAPAROUND", -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN", -- "IO", "IDATAIN", "ODATAIN"
-- SERDES_MODE => "MASTER", -- <NONE>, MASTER, SLAVE
SIM_TAPDELAY_VALUE => 49) --
port map (
IDATAIN => rx_data_in_fix(i), -- data from primary IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_m(i), -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => rxioclkp, -- High speed clock for calibration
IOCLK1 => rxioclkn, -- High speed clock for calibration
CLK => gclk, -- Fabric clock (GCLK) for control signals
CAL => cal_data_master, -- Calibrate control signal
INC => inc_data, -- Increment counter
CE => ce_data(i), -- Clock Enable
RST => rst_data, -- Reset delay line
BUSY => busym(i)) ; -- output signal indicating sync circuit has finished / calibration has finished
iserdes_m : ISERDES2 generic map (
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE => "DDR", -- <SDR>, DDR
BITSLIP_ENABLE => TRUE, -- <FALSE>, TRUE
-- SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE
INTERFACE_TYPE => "RETIMED") -- NETWORKING, NETWORKING_PIPELINED, <RETIMED>
port map (
D => ddly_m(i),
CE0 => '1',
CLK0 => rxioclkp,
CLK1 => rxioclkn,
IOCE => rxserdesstrobe,
RST => reset,
CLKDIV => gclk,
SHIFTIN => '0',
BITSLIP => bitslip,
FABRICOUT => open,
Q4 => mdataout((8*i)+7),
Q3 => mdataout((8*i)+6),
Q2 => mdataout((8*i)+5),
Q1 => mdataout((8*i)+4),
DFB => open,
CFB0 => open,
CFB1 => open,
VALID => open,
INCDEC => open,
SHIFTOUT => open);
end generate ;
loop1 : for j in 7 downto (8-S) generate
data_out(((D*(j+S-8))+i)) <= mdataout((8*i)+j) ;
end generate ;
end generate ;
end arch_serdes_1_to_n_data_ddr_s8_se ;
|
apache-2.0
|
74bc2434c754441d43192562ecee6e00
| 0.589883 | 2.980221 | false | false | false | false |
VladisM/MARK_II
|
VHDL/src/cpu/qip/fp_cmp_lt/fp_cmp_lt.vhd
| 1 | 5,883 |
-- megafunction wizard: %ALTERA_FP_FUNCTIONS v17.0%
-- GENERATION: XML
-- fp_cmp_lt.vhd
-- Generated using ACDS version 17.0 595
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fp_cmp_lt is
port (
clk : in std_logic := '0'; -- clk.clk
areset : in std_logic := '0'; -- areset.reset
a : in std_logic_vector(31 downto 0) := (others => '0'); -- a.a
b : in std_logic_vector(31 downto 0) := (others => '0'); -- b.b
q : out std_logic_vector(0 downto 0) -- q.q
);
end entity fp_cmp_lt;
architecture rtl of fp_cmp_lt is
component fp_cmp_lt_0002 is
port (
clk : in std_logic := 'X'; -- clk
areset : in std_logic := 'X'; -- reset
a : in std_logic_vector(31 downto 0) := (others => 'X'); -- a
b : in std_logic_vector(31 downto 0) := (others => 'X'); -- b
q : out std_logic_vector(0 downto 0) -- q
);
end component fp_cmp_lt_0002;
begin
fp_cmp_lt_inst : component fp_cmp_lt_0002
port map (
clk => clk, -- clk.clk
areset => areset, -- areset.reset
a => a, -- a.a
b => b, -- b.b
q => q -- q.q
);
end architecture rtl; -- of fp_cmp_lt
-- Retrieval info: <?xml version="1.0"?>
--<!--
-- Generated by Altera MegaWizard Launcher Utility version 1.0
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2018 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
---->
-- Retrieval info: <instance entity-name="altera_fp_functions" version="17.0" >
-- Retrieval info: <generic name="FUNCTION_FAMILY" value="COMPARE" />
-- Retrieval info: <generic name="ARITH_function" value="ADD" />
-- Retrieval info: <generic name="CONVERT_function" value="FXP_FP" />
-- Retrieval info: <generic name="ALL_function" value="ADD" />
-- Retrieval info: <generic name="EXP_LOG_function" value="EXPE" />
-- Retrieval info: <generic name="TRIG_function" value="SIN" />
-- Retrieval info: <generic name="COMPARE_function" value="LT" />
-- Retrieval info: <generic name="ROOTS_function" value="SQRT" />
-- Retrieval info: <generic name="fp_format" value="single" />
-- Retrieval info: <generic name="fp_exp" value="8" />
-- Retrieval info: <generic name="fp_man" value="23" />
-- Retrieval info: <generic name="exponent_width" value="23" />
-- Retrieval info: <generic name="frequency_target" value="25" />
-- Retrieval info: <generic name="latency_target" value="2" />
-- Retrieval info: <generic name="performance_goal" value="frequency" />
-- Retrieval info: <generic name="rounding_mode" value="nearest with tie breaking away from zero" />
-- Retrieval info: <generic name="faithful_rounding" value="false" />
-- Retrieval info: <generic name="gen_enable" value="false" />
-- Retrieval info: <generic name="divide_type" value="0" />
-- Retrieval info: <generic name="select_signal_enable" value="false" />
-- Retrieval info: <generic name="scale_by_pi" value="false" />
-- Retrieval info: <generic name="number_of_inputs" value="2" />
-- Retrieval info: <generic name="trig_no_range_reduction" value="false" />
-- Retrieval info: <generic name="report_resources_to_xml" value="false" />
-- Retrieval info: <generic name="fxpt_width" value="32" />
-- Retrieval info: <generic name="fxpt_fraction" value="0" />
-- Retrieval info: <generic name="fxpt_sign" value="1" />
-- Retrieval info: <generic name="fp_out_format" value="single" />
-- Retrieval info: <generic name="fp_out_exp" value="8" />
-- Retrieval info: <generic name="fp_out_man" value="23" />
-- Retrieval info: <generic name="fp_in_format" value="single" />
-- Retrieval info: <generic name="fp_in_exp" value="8" />
-- Retrieval info: <generic name="fp_in_man" value="23" />
-- Retrieval info: <generic name="enable_hard_fp" value="true" />
-- Retrieval info: <generic name="manual_dsp_planning" value="true" />
-- Retrieval info: <generic name="forceRegisters" value="1111" />
-- Retrieval info: <generic name="selected_device_family" value="MAX 10" />
-- Retrieval info: <generic name="selected_device_speedgrade" value="6" />
-- Retrieval info: </instance>
-- IPFS_FILES : fp_cmp_lt.vho
-- RELATED_FILES: fp_cmp_lt.vhd, dspba_library_package.vhd, dspba_library.vhd, fp_cmp_lt_0002.vhd
|
mit
|
6bfc480c698d6e9bccdec2a7f632f7e4
| 0.642359 | 3.464664 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/modules/machine/sirius_sr_250M/machine_pkg.vhd
| 1 | 4,436 |
-------------------------------------------------------------------------------
-- Title : Machine parameters for Sirius with 250MSps ADC
-- Project :
-------------------------------------------------------------------------------
-- File : machine_pkg.vhd<sirius_250M>
-- Author : <aylons@dig-jobs>
-- Company :
-- Created : 2016-04-04
-- Last update: 2016-04-06
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Machine parameters for Sirius with 250MSps ADC
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public License
-- as published by the Free Software Foundation, either version 3 of
-- the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-04-04 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package machine_pkg is
constant c_pos_calc_with_downconv : boolean := true;
constant c_pos_calc_adc_freq : real := 221.644e6;
constant c_pos_calc_input_width : natural := 16;
constant c_pos_calc_mixed_width : natural := 16;
constant c_pos_calc_adc_ratio : natural := 1;
constant c_pos_calc_dds_width : natural := 16;
constant c_pos_calc_dds_points : natural := 191;
constant c_pos_calc_sin_file : string := "../../../dsp-cores/hdl/modules/position_calc/dds_sin.nif";
constant c_pos_calc_cos_file : string := "../../../dsp-cores/hdl/modules/position_calc/dds_cos.nif";
constant c_pos_calc_tbt_cic_delay : natural := 1;
constant c_pos_calc_tbt_cic_stages : natural := 1;
constant c_pos_calc_tbt_ratio : natural := 382;
constant c_pos_calc_tbt_decim_width : natural := 32;
constant c_pos_calc_fofb_cic_delay : natural := 1;
constant c_pos_calc_fofb_cic_stages : natural := 1;
constant c_pos_calc_fofb_ratio : natural := 8786;
constant c_pos_calc_fofb_decim_width : natural := 32;
constant c_pos_calc_monit1_cic_delay : natural := 1;
constant c_pos_calc_monit1_cic_stages : natural := 1;
constant c_pos_calc_monit1_ratio : natural := 25; --ratio between fofb and monit 1
constant c_pos_calc_monit1_cic_ratio : natural := 8;
constant c_pos_calc_monit2_cic_delay : natural := 1;
constant c_pos_calc_monit2_cic_stages : natural := 1;
constant c_pos_calc_monit2_ratio : natural := 40; -- ratio between monit 1 and 2
constant c_pos_calc_monit2_cic_ratio : natural := 8;
constant c_pos_calc_monit_decim_width : natural := 32;
constant c_pos_calc_tbt_cordic_stages : positive := 12;
constant c_pos_calc_tbt_cordic_iter_per_clk : positive := 3;
constant c_pos_calc_tbt_cordic_ratio : positive := 8;
constant c_pos_calc_fofb_cordic_stages : positive := 15;
constant c_pos_calc_fofb_cordic_iter_per_clk : positive := 3;
constant c_pos_calc_fofb_cordic_ratio : positive := 8;
constant c_pos_calc_k_width : natural := 25;
constant c_pos_calc_offset_width : natural := 32;
constant c_pos_calc_IQ_width : natural := c_pos_calc_mixed_width;
constant c_pos_calc_k_sum : natural := 85e5;
constant c_pos_calc_k_x : natural := 85e5;
constant c_pos_calc_k_y : natural := 85e5;
end machine_pkg;
|
lgpl-3.0
|
2c1e55dc75678b264d290a354bcfd4b0
| 0.543057 | 3.936114 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/testbench/position/position_tb.vhd
| 1 | 14,147 |
-------------------------------------------------------------------------------
-- Title : Position calc testbench
-- Project :
-------------------------------------------------------------------------------
-- File : position_tb.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-05-28
-- Last update: 2015-11-25
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Testes the position calc module
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-05-28 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library std;
use std.textio.all;
library work;
use work.dsp_cores_pkg.all;
use work.bpm_cores_pkg.all;
use work.machine_pkg;
entity position_tb is
end entity position_tb;
architecture test of position_tb is
constant c_input_freq : real := 2.0*machine_pkg.c_pos_calc_adc_freq; -- double the ADC freq
constant clock_period : time := 1.0 sec / (c_input_freq);
constant c_input_width : natural := machine_pkg.c_pos_calc_input_width;
constant c_mixed_width : natural := machine_pkg.c_pos_calc_mixed_width;
constant c_output_width : natural := machine_pkg.c_pos_calc_fofb_decim_width;
constant c_k_width : natural := machine_pkg.c_pos_calc_k_width;
--width for IQ output
constant c_IQ_width : natural := machine_pkg.c_pos_calc_mixed_width;
constant c_adc_ratio : natural := machine_pkg.c_pos_calc_adc_ratio;
-- mixer
constant c_dds_width : natural := machine_pkg.c_pos_calc_dds_width;
constant c_dds_points : natural := machine_pkg.c_pos_calc_dds_points;
constant c_sin_file : string := machine_pkg.c_pos_calc_sin_file;
constant c_cos_file : string := machine_pkg.c_pos_calc_cos_file;
-- CIC setup
constant c_tbt_cic_delay : natural := machine_pkg.c_pos_calc_tbt_cic_delay;
constant c_tbt_cic_stages : natural := machine_pkg.c_pos_calc_tbt_cic_stages;
constant c_tbt_ratio : natural := machine_pkg.c_pos_calc_tbt_ratio;
constant c_tbt_decim_width : natural := machine_pkg.c_pos_calc_tbt_decim_width;
constant c_fofb_cic_delay : natural := machine_pkg.c_pos_calc_fofb_cic_delay;
constant c_fofb_cic_stages : natural := machine_pkg.c_pos_calc_fofb_cic_stages;
constant c_fofb_ratio : natural := machine_pkg.c_pos_calc_fofb_ratio; -- ratio between adc and fofb rates
constant c_fofb_decim_width : natural := machine_pkg.c_pos_calc_fofb_decim_width;
constant c_monit1_cic_delay : natural := 1;
constant c_monit1_cic_stages : natural := 1;
constant c_monit1_ratio : natural := natural(floor(sqrt(real(machine_pkg.c_pos_calc_monit1_ratio)))); --ratio between fofb and monit 1
constant c_monit1_cic_ratio : positive := machine_pkg.c_pos_calc_monit1_cic_ratio;
constant c_monit2_cic_delay : natural := 1;
constant c_monit2_cic_stages : natural := 1;
constant c_monit2_ratio : natural := natural(floor(sqrt(real(machine_pkg.c_pos_calc_monit2_ratio)))); -- ratio between monit 1 and 2
constant c_monit2_cic_ratio : positive := machine_pkg.c_pos_calc_monit2_cic_ratio;
constant c_ksum : std_logic_vector(23 downto 0) :=
std_logic_vector(to_unsigned(1e7, 24));
constant c_kx : std_logic_vector(23 downto 0) :=
std_logic_vector(to_unsigned(1e7, 24));
constant c_ky : std_logic_vector(23 downto 0) :=
std_logic_vector(to_unsigned(1e7, 24));
signal clock : std_logic := '0';
signal ce_adc : std_logic;
signal ce_tbt : std_logic;
signal ce_fofb : std_logic;
signal adc_data : std_logic_vector(c_input_width-1 downto 0);
signal endoffile : bit := '0';
signal reset : std_logic := '1';
signal rst : std_logic := '0';
signal a, b, c, d : std_logic_vector(c_input_width-1 downto 0);
-- Debug signals
signal mix_ch0_i, mix_ch0_q : std_logic_vector(c_mixed_width-1 downto 0);
-- tbt debug
signal tbt_ch0_i, tbt_ch0_q : std_logic_vector(c_output_width-1 downto 0);
signal tbt_pos_x_out, tbt_pos_y_out, tbt_pos_q_out, tbt_pos_sum_out :
std_logic_vector(c_output_width-1 downto 0);
signal a_tbt_out, b_tbt_out, c_tbt_out, d_tbt_out :
std_logic_vector(c_output_width-1 downto 0);
--fofb debug
signal fofb_ch0_i, fofb_ch0_q : std_logic_vector(c_output_width-1 downto 0);
signal x_fofb_out, y_fofb_out, q_fofb_out, sum_fofb_out :
std_logic_vector(c_output_width-1 downto 0);
signal a_fofb_out, b_fofb_out, c_fofb_out, d_fofb_out :
std_logic_vector(c_output_width-1 downto 0);
--function for writing 4 signals to file
procedure p_out_file(file out_file : text;
a_i : in signed;
b_i : in signed;
c_i : in signed;
d_i : in signed) is
variable a, b, c, d : integer;
variable cur_line : line;
begin
a := to_integer(a_i);
write(cur_line, a);
write(cur_line, string'(" "));
b := to_integer(b_i);
write(cur_line, b);
write(cur_line, string'(" "));
c := to_integer(c_i);
write(cur_line, c);
write(cur_line, string'(" "));
d := to_integer(d_i);
write(cur_line, d);
write(cur_line, string'(" "));
writeline(out_file, cur_line);
end procedure p_out_file;
begin
clk_gen : process
begin
clock <= '0';
wait for clock_period/2.0;
clock <= '1';
wait for clock_period/2.0;
end process;
rst_gen : process(clock)
variable clock_count : natural := 4;
begin
if rising_edge(clock) then
if clock_count > 0 then
clock_count := clock_count - 1;
else
reset <= '0';
end if;
end if;
end process;
adc_read : process(clock)
file adc_file : text open read_mode is "position_in.samples";
variable cur_line : line;
variable a_in, b_in, c_in, d_in : integer;
variable count : integer := 0;
begin
if rising_edge(clock) then
if ce_adc = '1' then
if not(endfile(adc_file)) then
readline(adc_file, cur_line);
read(cur_line, a_in);
a <= std_logic_vector(to_signed(a_in, c_input_width));
read(cur_line, b_in);
b <= std_logic_vector(to_signed(b_in, c_input_width));
read(cur_line, c_in);
c <= std_logic_vector(to_signed(c_in, c_input_width));
read(cur_line, d_in);
d <= std_logic_vector(to_signed(d_in, c_input_width));
else
endoffile <= '1';
a <= (others => '0');
b <= (others => '0');
c <= (others => '0');
d <= (others => '0');
end if;
end if;
end if;
end process adc_read;
uut : position_calc
generic map(
g_input_width => c_input_width,
g_mixed_width => c_mixed_width,
g_adc_ratio => c_adc_ratio,
g_dds_width => c_dds_width,
g_dds_points => c_dds_points,
g_tbt_cic_delay => c_tbt_cic_delay,
g_tbt_cic_stages => c_tbt_cic_stages,
g_tbt_ratio => c_tbt_ratio,
g_tbt_decim_width => c_tbt_decim_width,
g_fofb_cic_delay => c_fofb_cic_delay,
g_fofb_cic_stages => c_fofb_cic_stages,
g_fofb_ratio => c_fofb_ratio,
g_fofb_decim_width => c_fofb_decim_width,
g_monit1_cic_delay => c_monit1_cic_delay,
g_monit1_cic_stages => c_monit1_cic_stages,
g_monit1_ratio => c_monit1_ratio,
g_monit1_cic_ratio => c_monit1_cic_ratio,
g_monit2_cic_delay => c_monit2_cic_delay,
g_monit2_cic_stages => c_monit2_cic_stages,
g_monit2_ratio => c_monit2_ratio,
g_monit2_cic_ratio => c_monit2_cic_ratio,
g_monit_decim_width => 32,
g_tbt_cordic_stages => 12,
g_tbt_cordic_iter_per_clk => 3,
g_tbt_cordic_ratio => 4,
g_fofb_cordic_stages => 15,
g_fofb_cordic_iter_per_clk => 3,
g_fofb_cordic_ratio => 4,
g_k_width => c_k_width,
g_IQ_width => c_IQ_width
)
port map (
adc_ch0_i => a,
adc_ch1_i => b,
adc_ch2_i => c,
adc_ch3_i => d,
adc_valid_i => '1',
adc_tag_i => (others => '0'),
clk_i => clock,
rst_i => reset,
ksum_i => c_ksum,
kx_i => c_kx,
ky_i => c_ky,
mix_ch0_i_o => mix_ch0_i,
mix_ch0_q_o => mix_ch0_q,
mix_ch1_i_o => open,
mix_ch1_q_o => open,
mix_ch2_i_o => open,
mix_ch2_q_o => open,
mix_ch3_i_o => open,
mix_ch3_q_o => open,
mix_valid_o => open,
mix_ce_o => ce_adc,
tbt_decim_ch0_i_o => tbt_ch0_i,
tbt_decim_ch0_q_o => tbt_ch0_q,
tbt_decim_ch1_i_o => open,
tbt_decim_ch1_q_o => open,
tbt_decim_ch2_i_o => open,
tbt_decim_ch2_q_o => open,
tbt_decim_ch3_i_o => open,
tbt_decim_ch3_q_o => open,
tbt_decim_valid_o => open,
tbt_decim_ce_o => open,
tbt_tag_i => (others => '0'),
tbt_amp_ch0_o => a_tbt_out,
tbt_amp_ch1_o => b_tbt_out,
tbt_amp_ch2_o => c_tbt_out,
tbt_amp_ch3_o => d_tbt_out,
tbt_pha_ch0_o => open,
tbt_pha_ch1_o => open,
tbt_pha_ch2_o => open,
tbt_pha_ch3_o => open,
tbt_pha_valid_o => open,
tbt_pha_ce_o => ce_tbt,
fofb_decim_ch0_i_o => fofb_ch0_i,
fofb_decim_ch0_q_o => fofb_ch0_q,
fofb_decim_ch1_i_o => open,
fofb_decim_ch1_q_o => open,
fofb_decim_ch2_i_o => open,
fofb_decim_ch2_q_o => open,
fofb_decim_ch3_i_o => open,
fofb_decim_ch3_q_o => open,
fofb_decim_valid_o => open,
fofb_decim_ce_o => ce_fofb,
fofb_amp_ch0_o => a_fofb_out,
fofb_amp_ch1_o => b_fofb_out,
fofb_amp_ch2_o => c_fofb_out,
fofb_amp_ch3_o => d_fofb_out,
fofb_pha_ch0_o => open,
fofb_pha_ch1_o => open,
fofb_pha_ch2_o => open,
fofb_pha_ch3_o => open,
fofb_pha_valid_o => open,
fofb_pha_ce_o => open,
monit_amp_ch0_o => open,
monit_amp_ch1_o => open,
monit_amp_ch2_o => open,
monit_amp_ch3_o => open,
monit_amp_valid_o => open,
monit_amp_ce_o => open,
monit_tag_i => (others => '0'),
monit1_tag_i => (others => '0'),
tbt_pos_x_o => tbt_pos_x_out,
tbt_pos_y_o => tbt_pos_y_out,
tbt_pos_q_o => tbt_pos_q_out,
tbt_pos_sum_o => tbt_pos_sum_out,
tbt_pos_valid_o => open,
tbt_pos_ce_o => open,
fofb_pos_x_o => x_fofb_out,
fofb_pos_y_o => y_fofb_out,
fofb_pos_q_o => q_fofb_out,
fofb_pos_sum_o => sum_fofb_out,
fofb_pos_valid_o => open,
fofb_pos_ce_o => open,
monit_pos_x_o => open,
monit_pos_y_o => open,
monit_pos_q_o => open,
monit_pos_sum_o => open,
monit_pos_valid_o => open,
monit_pos_ce_o => open);
signal_write : process(clock)
file mixed_file : text open write_mode is "mixed_out.samples";
file tbt_file : text open write_mode is "tbt_out.samples";
file tbt_position_file : text open write_mode is "tbt_position_out.samples";
file tbt_amp_file : text open write_mode is "tbt_amp_out.samples";
file fofb_file : text open write_mode is "fofb_out.samples";
file fofb_position_file : text open write_mode is "position_out.samples";
file fofb_amp_file : text open write_mode is "fofb_amp_out.samples";
variable cur_line : line;
variable x, y, q, sum : integer;
variable mix_i, mix_q : signed(c_mixed_width-1 downto 0);
variable fofb_i, fofb_q : integer;
begin
if rising_edge(clock) then
-- fofb
if ce_fofb = '1' then
if(endoffile = '0') then
p_out_file(fofb_position_file,
signed(x_fofb_out),
signed(y_fofb_out),
signed(q_fofb_out),
signed(sum_fofb_out));
p_out_file(fofb_file,
signed(fofb_ch0_i),
signed(fofb_ch0_q),
(c_mixed_width-1 downto 0 => '0'),
(c_mixed_width-1 downto 0 => '0'));
p_out_file(fofb_amp_file,
signed(a_fofb_out),
signed(b_fofb_out),
signed(c_fofb_out),
signed(d_fofb_out));
else
assert (false) report "Input file finished." severity failure;
end if;
end if;
-- undecimated mixed
if ce_adc = '1' then
p_out_file(mixed_file, signed(mix_ch0_i), signed(mix_ch0_q),
(c_mixed_width-1 downto 0 => '0'),
(c_mixed_width-1 downto 0 => '0'));
end if;
-- turn by turn
if ce_tbt = '1' then
p_out_file(tbt_file, signed(tbt_ch0_i), signed(tbt_ch0_q),
(c_mixed_width-1 downto 0 => '0'),
(c_mixed_width-1 downto 0 => '0'));
p_out_file(tbt_amp_file, signed(a_tbt_out), signed(b_tbt_out),
signed(c_tbt_out), signed(d_tbt_out));
p_out_file(tbt_position_file, signed(tbt_pos_x_out), signed(tbt_pos_y_out),
(c_mixed_width-1 downto 0 => '0'),
(c_mixed_width-1 downto 0 => '0'));
end if;
end if;
end process signal_write;
end architecture test;
|
lgpl-3.0
|
3ccac634930c8130cbaa3231236df596
| 0.523008 | 3.084823 | false | false | false | false |
markert/vhdl-pci-arbiter
|
Arbiter.vhd
| 1 | 6,126 |
library ieee;
use ieee.std_logic_1164.all;
use work.PROTOCOL.all;
use work.FUNCTIONS.all;
use work.ARBITER_CONFIG.all;
use work.GLOBAL_PCI_CONFIG.all;
entity PCI_ARB is
port (
RESET_i, CLOCK : in bit;
FRAME_i, IRDY_i : in std_ulogic;
REQ_i : in std_ulogic_vector
(c_Agents - 1 downto 0);
GNT_o : out std_ulogic_vector
(c_Agents - 1 downto 0)
);
end entity PCI_ARB;
architecture TIME_SLOTS of PCI_ARB is
-- c_Agents is the number of Agents attached to the bus
-- c_AckTimer is the number of clocks a master gets maximal priority
-- Indicate master with maximal priority
signal s_Token : integer range 0 to c_Agents := 0;
-- signal to increment token
signal s_Ack : std_ulogic := '0';
-- timer for token shifting
signal s_AckTimer : integer range 0 to c_AckTimer := 0;
-- counter for master timeout
signal s_MasterTimeout : integer range 0 to 8 := 0;
-- equal to GNT_o
signal s_GntSet : std_ulogic_vector (c_Agents - 1 downto 0) :=
SetBitVector(0, c_Agents-1, '0');
signal s_GntSet_prev : std_ulogic_vector (c_Agents - 1 downto 0);
-- 0 shows that master got problem and will not be granted
signal s_ReqValid : std_ulogic_vector (c_Agents - 1 downto 0) :=
(others => '1');
begin
------------------------------------------------------------------------------------------
---------------------------- Ring Counter ------------------------------------------
------------------------------------------------------------------------------------------
RING_COUNTER : process (CLOCK, RESET_i)
begin -- process RING_COUNTER
if (RESET_i = '0') then
s_Token <= 0;
elsif (s_Ack = '1' and CLOCK'event and CLOCK = '1') then
s_Token <= (s_Token + 1) mod c_Agents;
end if;
end process RING_COUNTER;
------------------------------------------------------------------------------------------
---------------------------- Priority Logic ----------------------------------------
------------------------------------------------------------------------------------------
PRIORITY_LOGIC : process (REQ_i, RESET_i, CLOCK)
variable v_Req : std_ulogic_vector (c_Agents - 1 downto 0);
variable v_Gnt : std_ulogic_vector (c_Agents - 1 downto 0);
begin -- process PRIORITY_LOGIC
if RESET_i = '0' then
GNT_o <= (others => '1');
s_GntSet <= (others => '0');
s_GntSet_prev <= (others => '0');
elsif (CLOCK = '1' and CLOCK'event) then
s_GntSet_prev <= s_GntSet;
-- multiplex request inputs with respect to token position
for j in 0 to c_Agents - 1 loop
v_Req(j) := REQ_i((j + s_Token) mod c_Agents);
if s_ReqValid((j + s_Token) mod c_Agents) = '0' then
v_Req(j) := '1';
end if;
end loop; -- j
-- set v_gnt
for i in 0 to c_Agents - 1 loop
if v_Req(i) = '0' then
v_Gnt(i) := '0';
for j in i+1 to c_Agents - 1 loop
v_Gnt(j) := '1';
end loop; -- j
exit;
else
v_Gnt(i) := '1';
end if;
end loop; -- i
-- Arbitration parking of primary master, if no request is set
for i in 0 to c_Agents -1 loop
if IsEven(v_Gnt) = '1' then
if s_ReqValid((i + s_Token) mod c_Agents) = '1' then
v_Gnt(i) := '0';
exit;
end if;
else
exit;
end if;
end loop; -- i
-- attach v_gnt of Priority Logic to correct GNT_o of the PCI Bus
for i in 0 to c_Agents - 1 loop
--GNT_o((i + s_Token) mod c_Agents) <= v_Gnt(i);
s_GntSet((i + s_Token) mod c_Agents) <= v_Gnt(i);
end loop; -- i
if (FRAME_i /= '0' and IRDY_i /= '0' and
s_GntSet /= s_GntSet_prev) then
GNT_o <= (others => '1');
else
GNT_o <= s_GntSet;
end if;
end if;
end process PRIORITY_LOGIC;
------------------------------------------------------------------------------------------
---------------------------- Ring Counter Timer ------------------------------------
------------------------------------------------------------------------------------------
ACK_TIMER : process(CLOCK, RESET_i, s_AckTimer)
begin
if (RESET_i = '0') then
s_Ack <= '0';
s_AckTimer <= 0;
else
if (CLOCK = '1' and CLOCK'event) then
s_AckTimer <= (s_AckTimer + 1) mod c_AckTimer;
end if;
if (s_AckTimer = c_AckTimer - 1) then
s_Ack <= '1';
else
s_Ack <= '0';
end if;
end if;
end process ACK_TIMER;
------------------------------------------------------------------------------------------
---------------------------- Timeout Detection -------------------------------------
------------------------------------------------------------------------------------------
MASTER_TIMEOUT_DETECTION : process (RESET_i, CLOCK)
begin -- process MASTER_TIMEOUT_DETECTION
if (CLOCK = '1' and CLOCK'event) then
if RESET_i = '0' then
s_MasterTimeout <= 0;
s_ReqValid <= (others => '1');
-- set masters s_ReqValid 0 when master violates time constraints
elsif (s_MasterTimeout = c_MasterTimeOut) then
s_MasterTimeout <= 0;
for i in 0 to c_Agents - 1 loop
if s_GntSet(i) = '0' then
s_ReqValid(i) <= '0';
end if;
end loop; -- i
-- increment and reset Time Out timer
elsif (s_MasterTimeout /= c_MasterTimeOut) then
if (FRAME_i = '0' and IRDY_i = '1') then
s_MasterTimeout <= s_MasterTimeout + 1;
elsif IRDY_i = '0' then
s_MasterTimeout <= 0;
end if;
end if;
-- Reset s_ReqValid to 1 if master removes REQ_i
for j in 0 to c_Agents - 1 loop
if REQ_i(j) = '1' and s_ReqValid(j) = '0' then
s_ReqValid(j) <= '1';
end if;
end loop; -- j
end if;
end process MASTER_TIMEOUT_DETECTION;
end architecture TIME_SLOTS;
|
mit
|
5df71d2d4918fc05822d37ee2d5566f8
| 0.454456 | 3.911877 | false | false | false | false |
nanomolina/MIPS
|
prueba/datapath.vhd
| 1 | 13,001 |
library ieee;
use ieee.std_logic_1164.all;
entity datapath is
port (
MemToReg : in std_logic;
MemWrite : in std_logic;
Branch : in std_logic;
AluSrc : in std_logic;
RegDst : in std_logic;
RegWrite : in std_logic;
Jump : in std_logic;
AluControl : in std_logic_vector(2 downto 0);
dump : in std_logic;
pc : out std_logic_vector(31 downto 0);
instr : out std_logic_vector(31 downto 0);
reset : in std_logic;
clk : in std_logic);
end entity;
architecture arq_datapath of datapath is
component fetch
port(
jumpM, PcSrcM, clk, reset: in std_logic;
PcBranchM: in std_logic_vector(31 downto 0);
InstrF, PCF, PCPlus4F: out std_logic_vector(31 downto 0));
end component;
component decode
port(
A3: in std_logic_vector(4 downto 0);
InstrD, Wd3: in std_logic_vector(31 downto 0);
RegWrite, clk: in std_logic;
RtD, RdD: out std_logic_vector(4 downto 0);
SignImmD, RD1D, RD2D: out std_logic_vector(31 downto 0));
end component;
component execute
port(
RD1E, RD2E, PCPlus4E, SignImmE: in std_logic_vector(31 downto 0);
RtE, RdE: in std_logic_vector(4 downto 0);
RegDst, AluSrc : in std_logic;
AluControl: in std_logic_vector(2 downto 0);
WriteRegE: out std_logic_vector(4 downto 0);
ZeroE: out std_logic;
AluOutE, WriteDataE, PCBranchE: out std_logic_vector(31 downto 0));
end component;
component memory
port(
AluOutM, WriteDataM: in std_logic_vector(31 downto 0);
ZeroM, MemWrite, Branch, clk, dump: in std_logic;
ReadDataM: out std_logic_vector(31 downto 0);
PCSrcM: out std_logic);
end component;
component writeback
port(
AluOutW, ReadDataW: in std_logic_vector(31 downto 0);
MemToReg: in std_logic;
ResultW: out std_logic_vector(31 downto 0));
end component;
component IF_ID
port(
clk : in std_logic;
instr_in : in std_logic_vector(31 downto 0);
pcplus4_in : in std_logic_vector(31 downto 0);
instr_out : out std_logic_vector(31 downto 0);
pcplus4_out : out std_logic_vector(31 downto 0)
);
end component;
component ID_EX
port(
RtD_in : in std_logic_vector(4 downto 0);
RdD_in : in std_logic_vector(4 downto 0);
SignImm_in : in std_logic_vector(31 downto 0);
RD1_in : in std_logic_vector(31 downto 0);
RD2_in : in std_logic_vector(31 downto 0);
PCPlus4_in : in std_logic_vector(31 downto 0);
MemToReg_in:in std_logic;
MemWrite_in:in std_logic;
Branch_in:in std_logic;
AluSrc_in:in std_logic;
RegDst_in:in std_logic;
RegWrite_in:in std_logic;
Jump_in:in std_logic;
alucontrol_in: in std_logic_vector (2 downto 0);
clk : in std_logic;
PCPlus4_out : out std_logic_vector(31 downto 0);
MemToReg_out:out std_logic;
MemWrite_out:out std_logic;
Branch_out:out std_logic;
AluSrc_out:out std_logic;
RegDst_out:out std_logic;
RegWrite_out:out std_logic;
Jump_out:out std_logic;
alucontrol_out: out std_logic_vector (2 downto 0);
RtD_out : out std_logic_vector(4 downto 0);
RdD_out : out std_logic_vector(4 downto 0);
SignImm_out : out std_logic_vector(31 downto 0);
RD1_out : out std_logic_vector(31 downto 0);
RD2_out : out std_logic_vector(31 downto 0)
);
end component;
component EX_MEM
port(
Zero_in : in std_logic;
AluOut_in : in std_logic_vector(31 downto 0);
WriteData_in : in std_logic_vector(31 downto 0);
WriteReg_in : in std_logic_vector(4 downto 0);
PCBranch_in : in std_logic_vector(31 downto 0);
RegWrite_in: in std_logic;
MemToReg_in: in std_logic;
MemWrite_in: in std_logic;
Jump_in: in std_logic;
Branch_in: in std_logic;
clk : in std_logic;
RegWrite_out: out std_logic;
MemToReg_out: out std_logic;
MemWrite_out: out std_logic;
Jump_out: out std_logic;
Branch_out: out std_logic;
Zero_out : out std_logic;
AluOut_out : out std_logic_vector(31 downto 0);
WriteData_out : out std_logic_vector(31 downto 0);
WriteReg_out : out std_logic_vector(4 downto 0);
PCBranch_out : out std_logic_vector(31 downto 0)
);
end component;
component MEM_WB
port(
AluOut_in : in std_logic_vector(31 downto 0);
ReadData_in : in std_logic_vector(31 downto 0);
WriteReg_in : in std_logic_vector(4 downto 0);
RegWrite_in: in std_logic;
MemToReg_in: in std_logic;
clk : in std_logic;
RegWrite_out: out std_logic;
MemToReg_out: out std_logic;
AluOut_out : out std_logic_vector(31 downto 0);
ReadData_out : out std_logic_vector(31 downto 0);
WriteReg_out : out std_logic_vector(4 downto 0)
);
end component;
signal PCBranchE_out_s, InstrF_out_s, InstrIFID_out_s , PCF_s, PCPlus4F_out_s,
PCPlus4IFID_out_s, RD2D_out_s,RD2IDEX_out_s, RD1D_out_s,RD1IDEX_out_s,
SignImmD_out_s,SignImmIDEX_out_s,
AluOutE_out_s,AluOutEXMEM_out_s, WriteDataE_out_s,WriteDataEXMEM_out_s, ReadDataM_out_s,
ReadDataMEMWB_out_s,PCPlus4IDEX_out_s,
ResultW_s, PCBranchEXMEM_out_s, AluOutMEMWB_out_s: std_logic_vector(31 downto 0);
signal ZeroE_out_s,ZeroEXMEM_out_s, PcSrcM_s,MemToRegIDEX_out_s, MemToRegEXMEM_out_s,
MemToRegMEMWB_out_s,MemWriteIDEX_out_s,BranchIDEX_out_s,BranchEXMEM_out_s,
AluSrcIDEX_out_s,RegDstIDEX_out_s,RegWriteIDEX_out_s,RegWriteEXMEM_out_s,
RegWriteMEMEB_out_s,JumpIDEX_out_s, JumpEXMEM_out_s,MemWriteEXMEM_out_s: std_logic;
signal A3E_out_s,A3EXMEM_out_s,A3MEMWB_out_s, RtD_out_s, RtIDEX_out_s, RdD_out_s, RdIDEX_out_s: std_logic_vector(4 downto 0);
signal AluControlIDEX_out_s: std_logic_vector(2 downto 0);
begin
Fetch1: fetch port map(
jumpM => JumpEXMEM_out_s,
PcSrcM => PcSrcM_s,
clk => clk,
reset => reset,
PcBranchM => PCBranchEXMEM_out_s,
InstrF => InstrF_out_s,
PCF => pc,
PCPlus4F => PCPlus4F_out_s
);
IF_ID1: IF_ID port map(
clk => clk,
instr_in => InstrF_out_s,
pcplus4_in => PCPlus4F_out_s,
instr_out => InstrIFID_out_s,
pcplus4_out => PCPlus4IFID_out_s
);
Decode1: decode port map(
A3 => A3MEMWB_out_s,
InstrD => InstrIFID_out_s,
Wd3 => ResultW_s,
RegWrite => RegWriteMEMEB_out_s,
clk => clk,
RtD => RtD_out_s,
RdD => RdD_out_s,
SignImmD => SignImmD_out_s,
RD1D => RD1D_out_s,
RD2D => RD2D_out_s
);
ID_EX1: ID_EX port map(
RtD_in => RtD_out_s,
RdD_in => RdD_out_s,
SignImm_in => SignImmD_out_s,
RD1_in => RD1D_out_s,
RD2_in => RD2D_out_s,
PCPlus4_in => PCPlus4IFID_out_s,
MemToReg_in => MemToReg,
MemWrite_in => MemWrite,
Branch_in => Branch,
AluSrc_in => AluSrc,
RegDst_in => RegDst,
RegWrite_in => RegWrite,
Jump_in => Jump,
alucontrol_in => AluControl,
clk => clk,
PCPlus4_out => PCPlus4IDEX_out_s,
MemToReg_out => MemToRegIDEX_out_s,
MemWrite_out => MemWriteIDEX_out_s,
Branch_out => BranchIDEX_out_s,
AluSrc_out => AluSrcIDEX_out_s,
RegDst_out => RegDstIDEX_out_s,
RegWrite_out => RegWriteIDEX_out_s,
Jump_out => JumpIDEX_out_s,
alucontrol_out => AluControlIDEX_out_s,
RtD_out => RtIDEX_out_s,
RdD_out => RdIDEX_out_s,
SignImm_out => SignImmIDEX_out_s,
RD1_out => RD1IDEX_out_s,
RD2_out => RD2IDEX_out_s
);
Execute1: execute port map(
RD1E => RD1IDEX_out_s,
RD2E => RD2IDEX_out_s,
PCPlus4E => PCPlus4IDEX_out_s,
SignImmE => SignImmIDEX_out_s,
RtE => RtIDEX_out_s,
RdE => RdIDEX_out_s,
RegDst => RegDstIDEX_out_s,
AluSrc => AluSrcIDEX_out_s,
AluControl => AluControlIDEX_out_s,
WriteRegE => A3E_out_s,
ZeroE => ZeroE_out_s,
AluOutE => AluOutE_out_s,
WriteDataE => WriteDataE_out_s,
PCBranchE => PCBranchE_out_s
);
EX_MEM1: EX_MEM port map(
Zero_in => ZeroE_out_s,
AluOut_in => AluOutE_out_s,
WriteData_in => WriteDataE_out_s,
WriteReg_in => A3E_out_s,
PCBranch_in => PCBranchE_out_s,
RegWrite_in => RegWriteIDEX_out_s,
MemToReg_in => MemToRegIDEX_out_s,
MemWrite_in => MemWriteIDEX_out_s,
Jump_in => JumpIDEX_out_s,
Branch_in => BranchIDEX_out_s,
clk => clk,
RegWrite_out => RegWriteEXMEM_out_s,
MemToReg_out => MemToRegEXMEM_out_s,
MemWrite_out => MemWriteEXMEM_out_s,
Jump_out => JumpEXMEM_out_s,
Branch_out => BranchEXMEM_out_s,
Zero_out => ZeroEXMEM_out_s,
AluOut_out => AluOutEXMEM_out_s,
WriteData_out => WriteDataEXMEM_out_s,
WriteReg_out => A3EXMEM_out_s,
PCBranch_out => PCBranchEXMEM_out_s
);
Memory1: memory port map(
AluOutM => AluOutEXMEM_out_s,
WriteDataM => WriteDataEXMEM_out_s,
ZeroM => ZeroEXMEM_out_s,
MemWrite => MemWriteEXMEM_out_s,
Branch => BranchEXMEM_out_s,
clk => clk,
dump => dump,
ReadDataM => ReadDataM_out_s,
PCSrcM => PCSrcM_s
);
MEM_WB1: MEM_WB port map(
AluOut_in => AluOutEXMEM_out_s,
ReadData_in => ReadDataM_out_s,
WriteReg_in => A3EXMEM_out_s,
RegWrite_in => RegWriteEXMEM_out_s,
MemToReg_in => MemToRegEXMEM_out_s,
clk => clk,
RegWrite_out => RegWriteMEMEB_out_s,
MemToReg_out => MemToRegMEMWB_out_s,
AluOut_out => AluOutMEMWB_out_s,
ReadData_out => ReadDataMEMWB_out_s,
WriteReg_out => A3MEMWB_out_s
);
WriteBack1: writeback port map(
AluOutW => AluOutEXMEM_out_s,
ReadDataW => ReadDataMEMWB_out_s,
MemToReg => MemToRegMEMWB_out_s,
ResultW => ResultW_s
);
instr <= InstrF_out_s;
end architecture;
|
gpl-3.0
|
dc51f59848abd122b8d8f2d6b216dfbd
| 0.470348 | 4.076827 | false | false | false | false |
nanomolina/MIPS
|
prueba/decode.vhd
| 2 | 1,374 |
library ieee;
use ieee.std_logic_1164.all;
entity decode is
port(
A3: in std_logic_vector(4 downto 0);
InstrD, Wd3: in std_logic_vector(31 downto 0);
RegWrite, clk: in std_logic;
RtD, RdD: out std_logic_vector(4 downto 0);
SignImmD, RD1D, RD2D: out std_logic_vector(31 downto 0));
end entity;
architecture d_arq of decode is
component regfile
port (
ra1, ra2, wa3: in std_logic_vector(4 downto 0);
wd3: in std_logic_vector(31 downto 0);
we3, clk: in std_logic;
rd1, rd2: out std_logic_vector(31 downto 0));
end component;
component sign
port (
a: in std_logic_vector(15 downto 0);
y: out std_logic_vector(31 downto 0));
end component;
begin
regfile1: regfile port map(
ra1 => InstrD(25 downto 21),
ra2 => InstrD(20 downto 16),
wa3 => A3,
wd3 => Wd3,
we3 => RegWrite,
clk => clk,
rd1 => RD1D, --salida
rd2 => RD2D); --salida
sign1: sign port map(
a => InstrD(15 downto 0),
y => SignImmD); --salida
RtD <= InstrD(20 downto 16); --salida
RdD <= InstrD(15 downto 11); --salida
end architecture;
|
gpl-3.0
|
fe26f734823afaf530dba7b47bea4357
| 0.505095 | 3.837989 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/top/afc_v3/dbe_pbpm_with_dcc/dbe_pbpm_with_dcc.vhd
| 1 | 19,219 |
------------------------------------------------------------------------------
-- Title : Top FMC250M design
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2016-02-19
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Top design for testing the integration/control of the DSP with
-- FMC250M_4ch board
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-02-19 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- FMC516 definitions
use work.fmc_adc_pkg.all;
-- IP cores constants
use work.ipcores_pkg.all;
-- AFC definitions
use work.afc_base_pkg.all;
entity dbe_pbpm_with_dcc is
generic (
-- Number of P2P GTs
g_NUM_P2P_GTS : integer := 8;
-- Start index of the P2P GTs
g_P2P_GT_START_ID : integer := 0
);
port(
---------------------------------------------------------------------------
-- Clocking pins
---------------------------------------------------------------------------
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
aux_clk_p_i : in std_logic;
aux_clk_n_i : in std_logic;
afc_fp2_clk1_p_i : in std_logic;
afc_fp2_clk1_n_i : in std_logic;
---------------------------------------------------------------------------
-- Reset Button
---------------------------------------------------------------------------
sys_rst_button_n_i : in std_logic := '1';
---------------------------------------------------------------------------
-- UART pins
---------------------------------------------------------------------------
uart_rxd_i : in std_logic := '1';
uart_txd_o : out std_logic;
---------------------------------------------------------------------------
-- Trigger pins
---------------------------------------------------------------------------
trig_dir_o : out std_logic_vector(c_NUM_TRIG-1 downto 0);
trig_b : inout std_logic_vector(c_NUM_TRIG-1 downto 0);
---------------------------------------------------------------------------
-- AFC Diagnostics
---------------------------------------------------------------------------
diag_spi_cs_i : in std_logic := '0';
diag_spi_si_i : in std_logic := '0';
diag_spi_so_o : out std_logic;
diag_spi_clk_i : in std_logic := '0';
---------------------------------------------------------------------------
-- ADN4604ASVZ
---------------------------------------------------------------------------
adn4604_vadj2_clk_updt_n_o : out std_logic;
---------------------------------------------------------------------------
-- AFC I2C.
---------------------------------------------------------------------------
-- Si57x oscillator
afc_si57x_scl_b : inout std_logic;
afc_si57x_sda_b : inout std_logic;
-- Si57x oscillator output enable
afc_si57x_oe_o : out std_logic;
---------------------------------------------------------------------------
-- PCIe pins
---------------------------------------------------------------------------
-- DDR3 memory pins
ddr3_dq_b : inout std_logic_vector(c_DDR_DQ_WIDTH-1 downto 0);
ddr3_dqs_p_b : inout std_logic_vector(c_DDR_DQS_WIDTH-1 downto 0);
ddr3_dqs_n_b : inout std_logic_vector(c_DDR_DQS_WIDTH-1 downto 0);
ddr3_addr_o : out std_logic_vector(c_DDR_ROW_WIDTH-1 downto 0);
ddr3_ba_o : out std_logic_vector(c_DDR_BANK_WIDTH-1 downto 0);
ddr3_cs_n_o : out std_logic_vector(0 downto 0);
ddr3_ras_n_o : out std_logic;
ddr3_cas_n_o : out std_logic;
ddr3_we_n_o : out std_logic;
ddr3_reset_n_o : out std_logic;
ddr3_ck_p_o : out std_logic_vector(c_DDR_CK_WIDTH-1 downto 0);
ddr3_ck_n_o : out std_logic_vector(c_DDR_CK_WIDTH-1 downto 0);
ddr3_cke_o : out std_logic_vector(c_DDR_CKE_WIDTH-1 downto 0);
ddr3_dm_o : out std_logic_vector(c_DDR_DM_WIDTH-1 downto 0);
ddr3_odt_o : out std_logic_vector(c_DDR_ODT_WIDTH-1 downto 0);
-- PCIe transceivers
pci_exp_rxp_i : in std_logic_vector(c_PCIELANES - 1 downto 0);
pci_exp_rxn_i : in std_logic_vector(c_PCIELANES - 1 downto 0);
pci_exp_txp_o : out std_logic_vector(c_PCIELANES - 1 downto 0);
pci_exp_txn_o : out std_logic_vector(c_PCIELANES - 1 downto 0);
-- PCI clock and reset signals
pcie_clk_p_i : in std_logic;
pcie_clk_n_i : in std_logic;
---------------------------------------------------------------------------
-- User LEDs
---------------------------------------------------------------------------
leds_o : out std_logic_vector(2 downto 0);
---------------------------------------------------------------------------
-- FMC interface
---------------------------------------------------------------------------
board_i2c_scl_b : inout std_logic;
board_i2c_sda_b : inout std_logic;
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
--
-- spi_sclk_o : out std_logic;
-- spi_cs_n_o : out std_logic;
-- spi_mosi_o : out std_logic;
-- spi_miso_i : in std_logic := '0';
---------------------------------------------------------------------------
-- P2P GT pins
---------------------------------------------------------------------------
-- P2P
p2p_gt_rx_p_i : in std_logic_vector(g_NUM_P2P_GTS+g_P2P_GT_START_ID-1 downto g_P2P_GT_START_ID) := (others => '0');
p2p_gt_rx_n_i : in std_logic_vector(g_NUM_P2P_GTS+g_P2P_GT_START_ID-1 downto g_P2P_GT_START_ID) := (others => '1');
p2p_gt_tx_p_o : out std_logic_vector(g_NUM_P2P_GTS+g_P2P_GT_START_ID-1 downto g_P2P_GT_START_ID);
p2p_gt_tx_n_o : out std_logic_vector(g_NUM_P2P_GTS+g_P2P_GT_START_ID-1 downto g_P2P_GT_START_ID);
-----------------------------------------
-- FMC PICO 1M_4CH Ports
-----------------------------------------
fmc1_adc_cnv_o : out std_logic;
fmc1_adc_sck_o : out std_logic;
fmc1_adc_sck_rtrn_i : in std_logic;
fmc1_adc_sdo1_i : in std_logic;
fmc1_adc_sdo2_i : in std_logic;
fmc1_adc_sdo3_i : in std_logic;
fmc1_adc_sdo4_i : in std_logic;
fmc1_adc_busy_cmn_i : in std_logic;
fmc1_rng_r1_o : out std_logic;
fmc1_rng_r2_o : out std_logic;
fmc1_rng_r3_o : out std_logic;
fmc1_rng_r4_o : out std_logic;
fmc1_led1_o : out std_logic;
fmc1_led2_o : out std_logic;
-- EEPROM (Connected to the CPU). Use board I2C pins if needed as they are
-- behind a I2C switch that can access FMC I2C bus
-- fmc1_sm_scl_o : out std_logic;
-- fmc1_sm_sda_b : inout std_logic;
fmc1_a_scl_o : out std_logic;
fmc1_a_sda_b : inout std_logic;
-----------------------------------------
-- FMC PICO 1M_4CH Ports
-----------------------------------------
fmc2_adc_cnv_o : out std_logic;
fmc2_adc_sck_o : out std_logic;
fmc2_adc_sck_rtrn_i : in std_logic;
fmc2_adc_sdo1_i : in std_logic;
fmc2_adc_sdo2_i : in std_logic;
fmc2_adc_sdo3_i : in std_logic;
fmc2_adc_sdo4_i : in std_logic;
fmc2_adc_busy_cmn_i : in std_logic;
fmc2_rng_r1_o : out std_logic;
fmc2_rng_r2_o : out std_logic;
fmc2_rng_r3_o : out std_logic;
fmc2_rng_r4_o : out std_logic;
fmc2_led1_o : out std_logic;
fmc2_led2_o : out std_logic;
-- Connected through FPGA MUX. Use board I2C pins if needed as they are
-- behind a I2C switch that can access FMC I2C bus
--fmc2_sm_scl_o : out std_logic;
--fmc2_sm_sda_b : inout std_logic;
fmc2_a_scl_o : out std_logic;
fmc2_a_sda_b : inout std_logic
);
end dbe_pbpm_with_dcc;
architecture rtl of dbe_pbpm_with_dcc is
begin
cmp_dbe_bpm_gen : entity work.dbe_bpm_gen
generic map (
g_fmc_adc_type => "FMCPICO_1M",
g_NUM_P2P_GTS => g_NUM_P2P_GTS,
g_P2P_GT_START_ID => g_P2P_GT_START_ID,
g_WITH_P2P_FOFB_DCC => true
)
port map (
---------------------------------------------------------------------------
-- Clocking pins
---------------------------------------------------------------------------
sys_clk_p_i => sys_clk_p_i,
sys_clk_n_i => sys_clk_n_i,
aux_clk_p_i => aux_clk_p_i,
aux_clk_n_i => aux_clk_n_i,
afc_fp2_clk1_p_i => afc_fp2_clk1_p_i,
afc_fp2_clk1_n_i => afc_fp2_clk1_n_i,
---------------------------------------------------------------------------
-- Reset Button
---------------------------------------------------------------------------
sys_rst_button_n_i => sys_rst_button_n_i,
---------------------------------------------------------------------------
-- UART pins
---------------------------------------------------------------------------
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
---------------------------------------------------------------------------
-- Trigger pins
---------------------------------------------------------------------------
trig_dir_o => trig_dir_o,
trig_b => trig_b,
---------------------------------------------------------------------------
-- AFC Diagnostics
---------------------------------------------------------------------------
diag_spi_cs_i => diag_spi_cs_i,
diag_spi_si_i => diag_spi_si_i,
diag_spi_so_o => diag_spi_so_o,
diag_spi_clk_i => diag_spi_clk_i,
---------------------------------------------------------------------------
-- ADN4604ASVZ
---------------------------------------------------------------------------
adn4604_vadj2_clk_updt_n_o => adn4604_vadj2_clk_updt_n_o,
---------------------------------------------------------------------------
-- AFC I2C.
---------------------------------------------------------------------------
-- Si57x oscillator
afc_si57x_scl_b => afc_si57x_scl_b,
afc_si57x_sda_b => afc_si57x_sda_b,
-- Si57x oscillator output enable
afc_si57x_oe_o => afc_si57x_oe_o,
---------------------------------------------------------------------------
-- PCIe pins
---------------------------------------------------------------------------
-- DDR3 memory pins
ddr3_dq_b => ddr3_dq_b,
ddr3_dqs_p_b => ddr3_dqs_p_b,
ddr3_dqs_n_b => ddr3_dqs_n_b,
ddr3_addr_o => ddr3_addr_o,
ddr3_ba_o => ddr3_ba_o,
ddr3_cs_n_o => ddr3_cs_n_o,
ddr3_ras_n_o => ddr3_ras_n_o,
ddr3_cas_n_o => ddr3_cas_n_o,
ddr3_we_n_o => ddr3_we_n_o,
ddr3_reset_n_o => ddr3_reset_n_o,
ddr3_ck_p_o => ddr3_ck_p_o,
ddr3_ck_n_o => ddr3_ck_n_o,
ddr3_cke_o => ddr3_cke_o,
ddr3_dm_o => ddr3_dm_o,
ddr3_odt_o => ddr3_odt_o,
-- PCIe transceivers
pci_exp_rxp_i => pci_exp_rxp_i,
pci_exp_rxn_i => pci_exp_rxn_i,
pci_exp_txp_o => pci_exp_txp_o,
pci_exp_txn_o => pci_exp_txn_o,
-- PCI clock and reset signals
pcie_clk_p_i => pcie_clk_p_i,
pcie_clk_n_i => pcie_clk_n_i,
---------------------------------------------------------------------------
-- User LEDs
---------------------------------------------------------------------------
leds_o => leds_o,
---------------------------------------------------------------------------
-- FMC interface
---------------------------------------------------------------------------
board_i2c_scl_b => board_i2c_scl_b,
board_i2c_sda_b => board_i2c_sda_b,
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
--
-- spi_sclk_o => spi_sclk_o,
-- spi_cs_n_o => spi_cs_n_o,
-- spi_mosi_o => spi_mosi_o,
-- spi_miso_i => spi_miso_i,
---------------------------------------------------------------------------
-- P2P GT pins
---------------------------------------------------------------------------
-- P2P
p2p_gt_rx_p_i => p2p_gt_rx_p_i,
p2p_gt_rx_n_i => p2p_gt_rx_n_i,
p2p_gt_tx_p_o => p2p_gt_tx_p_o,
p2p_gt_tx_n_o => p2p_gt_tx_n_o,
-----------------------------------------
-- FMC PICO 1M_4CH Ports
-----------------------------------------
fmcpico_1_adc_cnv_o => fmc1_adc_cnv_o,
fmcpico_1_adc_sck_o => fmc1_adc_sck_o,
fmcpico_1_adc_sck_rtrn_i => fmc1_adc_sck_rtrn_i,
fmcpico_1_adc_sdo1_i => fmc1_adc_sdo1_i,
fmcpico_1_adc_sdo2_i => fmc1_adc_sdo2_i,
fmcpico_1_adc_sdo3_i => fmc1_adc_sdo3_i,
fmcpico_1_adc_sdo4_i => fmc1_adc_sdo4_i,
fmcpico_1_adc_busy_cmn_i => fmc1_adc_busy_cmn_i,
fmcpico_1_rng_r1_o => fmc1_rng_r1_o,
fmcpico_1_rng_r2_o => fmc1_rng_r2_o,
fmcpico_1_rng_r3_o => fmc1_rng_r3_o,
fmcpico_1_rng_r4_o => fmc1_rng_r4_o,
fmcpico_1_led1_o => fmc1_led1_o,
fmcpico_1_led2_o => fmc1_led2_o,
---- Connected through FPGA MUX. Use board I2C, if needed
--fmcpico_1_sm_scl_o => fmc1_sm_scl_o,
--fmcpico_1_sm_sda_b => fmc1_sm_sda_b,
fmcpico_1_a_scl_o => fmc1_a_scl_o,
fmcpico_1_a_sda_b => fmc1_a_sda_b,
-----------------------------------------
-- FMC PICO 1M_4CH Ports
-----------------------------------------
fmcpico_2_adc_cnv_o => fmc2_adc_cnv_o,
fmcpico_2_adc_sck_o => fmc2_adc_sck_o,
fmcpico_2_adc_sck_rtrn_i => fmc2_adc_sck_rtrn_i,
fmcpico_2_adc_sdo1_i => fmc2_adc_sdo1_i,
fmcpico_2_adc_sdo2_i => fmc2_adc_sdo2_i,
fmcpico_2_adc_sdo3_i => fmc2_adc_sdo3_i,
fmcpico_2_adc_sdo4_i => fmc2_adc_sdo4_i,
fmcpico_2_adc_busy_cmn_i => fmc2_adc_busy_cmn_i,
fmcpico_2_rng_r1_o => fmc2_rng_r1_o,
fmcpico_2_rng_r2_o => fmc2_rng_r2_o,
fmcpico_2_rng_r3_o => fmc2_rng_r3_o,
fmcpico_2_rng_r4_o => fmc2_rng_r4_o,
fmcpico_2_led1_o => fmc2_led1_o,
fmcpico_2_led2_o => fmc2_led2_o,
-- Connected through FPGA MUX. Use board I2C, if needed
--fmcpico_2_sm_scl_o => fmc2_sm_scl_o,
--fmcpico_2_sm_sda_b => fmc2_sm_sda_b,
fmcpico_2_a_scl_o => fmc2_a_scl_o,
fmcpico_2_a_sda_b => fmc2_a_sda_b
);
end rtl;
|
lgpl-3.0
|
890562912acccb5bad5418b7682af790
| 0.307768 | 4.310159 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/modules/wb_bpm_swap/xwb_bpm_swap.vhd
| 1 | 4,838 |
------------------------------------------------------------------------------
-- Title : Wishbone BPM SWAP interface
------------------------------------------------------------------------------
-- Author : Jose Alvim Berkenbrock
-- Company : CNPEM LNLS-DIG
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Wishbone interface with BPM Swap core.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-04-11 1.0 jose.berkenbrock Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- DSP Cores
use work.dsp_cores_pkg.all;
-- BPM Cores
use work.bpm_cores_pkg.all;
-- Register Bank
use work.bpm_swap_wbgen2_pkg.all;
entity xwb_bpm_swap is
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_delay_vec_width : natural := 8;
g_swap_div_freq_vec_width : natural := 16;
g_ch_width : natural := 16
);
port
(
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
fs_rst_n_i : in std_logic;
fs_clk_i : in std_logic;
-----------------------------
-- Wishbone signals
-----------------------------
wb_slv_i : in t_wishbone_slave_in;
wb_slv_o : out t_wishbone_slave_out;
-----------------------------
-- External ports
-----------------------------
-- Input data from ADCs
cha_i : in std_logic_vector(g_ch_width-1 downto 0);
chb_i : in std_logic_vector(g_ch_width-1 downto 0);
chc_i : in std_logic_vector(g_ch_width-1 downto 0);
chd_i : in std_logic_vector(g_ch_width-1 downto 0);
ch_valid_i : in std_logic;
-- Output data to BPM DSP chain
cha_o : out std_logic_vector(g_ch_width-1 downto 0);
chb_o : out std_logic_vector(g_ch_width-1 downto 0);
chc_o : out std_logic_vector(g_ch_width-1 downto 0);
chd_o : out std_logic_vector(g_ch_width-1 downto 0);
ch_tag_o : out std_logic_vector(0 downto 0);
ch_valid_o : out std_logic;
-- RFFE swap clock (or switchwing clock)
rffe_swclk_o : out std_logic;
sync_trig_i : in std_logic
);
end xwb_bpm_swap;
architecture rtl of xwb_bpm_swap is
begin
cmp_wb_bpm_swap : wb_bpm_swap
generic map
(
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
g_delay_vec_width => g_delay_vec_width,
g_swap_div_freq_vec_width => g_swap_div_freq_vec_width,
g_ch_width => g_ch_width
)
port map
(
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
fs_rst_n_i => fs_rst_n_i,
fs_clk_i => fs_clk_i,
wb_adr_i => wb_slv_i.adr,
wb_dat_i => wb_slv_i.dat,
wb_dat_o => wb_slv_o.dat,
wb_sel_i => wb_slv_i.sel,
wb_we_i => wb_slv_i.we,
wb_cyc_i => wb_slv_i.cyc,
wb_stb_i => wb_slv_i.stb,
wb_ack_o => wb_slv_o.ack,
wb_stall_o => wb_slv_o.stall,
cha_i => cha_i,
chb_i => chb_i,
chc_i => chc_i,
chd_i => chd_i,
ch_valid_i => ch_valid_i,
cha_o => cha_o,
chb_o => chb_o,
chc_o => chc_o,
chd_o => chd_o,
ch_tag_o => ch_tag_o,
ch_valid_o => ch_valid_o,
rffe_swclk_o => rffe_swclk_o,
sync_trig_i => sync_trig_i
);
end rtl;
|
lgpl-3.0
|
15cc3c78dd22b1578e12bea8d0479795
| 0.383216 | 4.065546 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/top/pcie/top_kc705.vhd
| 1 | 7,226 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library work;
use work.abb64Package.all;
use work.ipcores_pkg.all;
library UNISIM;
use UNISIM.VComponents.all;
entity top is
generic (
SIMULATION : string := "FALSE"
);
port (
--DDR3 memory pins
ddr3_dq : inout std_logic_vector(C_DDR_DQ_WIDTH-1 downto 0);
ddr3_dqs_p : inout std_logic_vector(C_DDR_DQS_WIDTH-1 downto 0);
ddr3_dqs_n : inout std_logic_vector(C_DDR_DQS_WIDTH-1 downto 0);
ddr3_addr : out std_logic_vector(C_DDR_ROW_WIDTH-1 downto 0);
ddr3_ba : out std_logic_vector(C_DDR_BANK_WIDTH-1 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(C_DDR_CK_WIDTH-1 downto 0);
ddr3_ck_n : out std_logic_vector(C_DDR_CK_WIDTH-1 downto 0);
ddr3_cke : out std_logic_vector(C_DDR_CKE_WIDTH-1 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(C_DDR_DM_WIDTH-1 downto 0);
ddr3_odt : out std_logic_vector(C_DDR_ODT_WIDTH-1 downto 0);
-- PCIe transceivers
pci_exp_rxp : in std_logic_vector(c_pcielanes-1 downto 0);
pci_exp_rxn : in std_logic_vector(c_pcielanes-1 downto 0);
pci_exp_txp : out std_logic_vector(c_pcielanes-1 downto 0);
pci_exp_txn : out std_logic_vector(c_pcielanes-1 downto 0);
-- Necessity signals
ddr_sys_clk_p : in std_logic;
ddr_sys_clk_n : in std_logic;
pci_sys_clk_p : in std_logic; --100 MHz PCIe Clock (connect directly to input pin)
pci_sys_clk_n : in std_logic; --100 MHz PCIe Clock
sys_rst_n : in std_logic --Reset to PCIe core
);
end entity top;
architecture arch of top is
signal ddr_sys_clk_i : std_logic;
signal ddr_sys_rst_i : std_logic;
signal ddr_axi_aclk_o : std_logic;
signal sys_rst_n_c : std_logic;
signal wbone_clk : std_logic;
signal wbone_addr : std_logic_vector(31 downto 0);
signal wbone_mdin : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wbone_mdout : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wbone_we : std_logic;
signal wbone_sel : std_logic_vector(0 downto 0);
signal wbone_stb : std_logic;
signal wbone_ack : std_logic;
signal wbone_cyc : std_logic;
signal wbone_rst : std_logic;
begin
bpm_pcie_i : entity work.bpm_pcie
generic map(
SIMULATION => SIMULATION
)
port map(
--DDR3 memory pins
ddr3_dq => ddr3_dq,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_cs_n => ddr3_cs_n,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
ddr3_cke => ddr3_cke,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
-- PCIe transceivers
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
-- Necessity signals
ddr_sys_clk => ddr_sys_clk_i,
ddr_sys_rst => ddr_sys_rst_i,
pci_sys_clk_p => pci_sys_clk_p,
pci_sys_clk_n => pci_sys_clk_n,
pci_sys_rst_n => sys_rst_n_c,
-- DDR memory controller AXI4 interface --
-- Slave interface clock
ddr_axi_aclk_o => ddr_axi_aclk_o,
ddr_axi_aresetn_o => open,
-- Slave Interface Write Address Ports
ddr_axi_awid => (others => '0'),
ddr_axi_awaddr => (others => '0'),
ddr_axi_awlen => (others => '0'),
ddr_axi_awsize => (others => '0'),
ddr_axi_awburst => (others => '0'),
ddr_axi_awlock => '0',
ddr_axi_awcache => (others => '0'),
ddr_axi_awprot => (others => '0'),
ddr_axi_awqos => (others => '0'),
ddr_axi_awvalid => '0',
ddr_axi_awready => open,
-- Slave Interface Write Data Ports
ddr_axi_wdata => (others => '0'),
ddr_axi_wstrb => (others => '0'),
ddr_axi_wlast => '0',
ddr_axi_wvalid => '0',
ddr_axi_wready => open,
-- Slave Interface Write Response Ports
ddr_axi_bid => open,
ddr_axi_bresp => open,
ddr_axi_bvalid => open,
ddr_axi_bready => '1',
-- Slave Interface Read Address Ports
ddr_axi_arid => (others => '0'),
ddr_axi_araddr => (others => '0'),
ddr_axi_arlen => (others => '0'),
ddr_axi_arsize => (others => '0'),
ddr_axi_arburst => (others => '0'),
ddr_axi_arlock => '0',
ddr_axi_arcache => (others => '0'),
ddr_axi_arprot => (others => '0'),
ddr_axi_arqos => (others => '0'),
ddr_axi_arvalid => '0',
ddr_axi_arready => open,
-- Slave Interface Read Data Ports
ddr_axi_rid => open,
ddr_axi_rdata => open,
ddr_axi_rresp => open,
ddr_axi_rlast => open,
ddr_axi_rvalid => open,
ddr_axi_rready => '1',
--/ DDR memory controller interface
-- Wishbone interface --
-- uncomment when instantiating in another project
CLK_I => wbone_clk,
RST_I => wbone_rst,
ACK_I => wbone_ack,
DAT_I => wbone_mdin,
ADDR_O => wbone_addr(28 downto 0),
DAT_O => wbone_mdout,
WE_O => wbone_we,
STB_O => wbone_stb,
SEL_O => wbone_sel(0),
CYC_O => wbone_cyc,
--/ Wishbone interface
-- Additional exported signals for instantiation
ext_rst_o => wbone_rst
);
Wishbone_mem_large: if (SIMULATION = "TRUE") generate
wb_mem_sim :
entity work.wb_mem
generic map(
AWIDTH => 16,
DWIDTH => 64
)
port map(
CLK_I => wbone_clk, --in std_logic;
ACK_O => wbone_ack, --out std_logic;
ADR_I => wbone_addr(16-1 downto 0), --in std_logic_vector(AWIDTH-1 downto 0);
DAT_I => wbone_mdout, --in std_logic_vector(DWIDTH-1 downto 0);
DAT_O => wbone_mdin, --out std_logic_vector(DWIDTH-1 downto 0);
STB_I => wbone_stb, --in std_logic;
WE_I => wbone_we --in std_logic
);
end generate;
Wishbone_mem_sample: if (SIMULATION = "FALSE") generate
wb_mem_syn :
entity work.wb_mem
generic map(
AWIDTH => 7,
DWIDTH => 64
)
port map(
CLK_I => wbone_clk, --in std_logic;
ACK_O => wbone_ack, --out std_logic;
ADR_I => wbone_addr(7-1 downto 0), --in std_logic_vector(AWIDTH-1 downto 0);
DAT_I => wbone_mdout, --in std_logic_vector(DWIDTH-1 downto 0);
DAT_O => wbone_mdin, --out std_logic_vector(DWIDTH-1 downto 0);
STB_I => wbone_stb, --in std_logic;
WE_I => wbone_we --in std_logic
);
end generate;
--temporary clock assignment
wbone_clk <= ddr_axi_aclk_o;
sys_reset_n_ibuf: IBUF
port map (
O => sys_rst_n_c,
I => sys_rst_n
);
ddr_sys_rst_i <= not sys_rst_n_c;
ddr_inclk_buf: IBUFGDS
port map(
o => ddr_sys_clk_i,
i => ddr_sys_clk_p,
ib => ddr_sys_clk_n
);
end architecture;
|
lgpl-3.0
|
0313a06026247ecb588abcc26b9989a8
| 0.557016 | 3.034859 | false | false | false | false |
Given-Jiang/Gray_Binarization
|
tb_Gray_Binarization/hdl/alt_dspbuilder_delay_GND2PGZRBZ.vhd
| 3 | 1,088 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GND2PGZRBZ is
generic ( ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 1;
BitPattern : string := "1";
width : positive := 1);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector((width)-1 downto 0);
output : out std_logic_vector((width)-1 downto 0);
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_delay_GND2PGZRBZ is
Begin
-- Delay Element, with reset value
DelayWithInit : alt_dspbuilder_SInitDelay generic map (
LPM_WIDTH => 1,
LPM_DELAY => 1,
SequenceLength => 1,
SequenceValue => "1",
ResetValue => "1")
port map (
dataa => input,
clock => clock,
ena => ena,
sclr => sclr,
aclr => aclr,
user_aclr => '0',
result => output);
end architecture;
|
mit
|
39fb275f959e41af93cc9eb24bb0fd10
| 0.629596 | 2.989011 | false | false | false | false |
Given-Jiang/Gray_Binarization
|
Gray_Binarization_dspbuilder/hdl/tb_Gray_Binarization.vhd
| 2 | 16,021 |
-- tb_Gray_Binarization.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.11:20:48
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tb_Gray_Binarization is
end entity tb_Gray_Binarization;
architecture rtl of tb_Gray_Binarization is
component Gray_Binarization_GN is
port (
Clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset_n
Avalon_ST_Sink_data : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
Avalon_ST_Sink_endofpacket : in std_logic := 'X'; -- wire
Avalon_MM_Slave_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire
Avalon_MM_Slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
Avalon_ST_Source_valid : out std_logic; -- wire
Avalon_ST_Sink_valid : in std_logic := 'X'; -- wire
Avalon_ST_Source_endofpacket : out std_logic; -- wire
Avalon_ST_Source_startofpacket : out std_logic; -- wire
Avalon_ST_Source_ready : in std_logic := 'X'; -- wire
Avalon_MM_Slave_write : in std_logic := 'X'; -- wire
Avalon_ST_Sink_ready : out std_logic; -- wire
Avalon_ST_Sink_startofpacket : in std_logic := 'X'; -- wire
Avalon_ST_Source_data : out std_logic_vector(23 downto 0) -- wire
);
end component Gray_Binarization_GN;
component alt_dspbuilder_testbench_clock_GNXGQJH2DS is
generic (
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
aclr_out : out std_logic; -- reset
clock_out : out std_logic; -- clk
reg_aclr_out : out std_logic; -- reset
tb_aclr : out std_logic -- reset
);
end component alt_dspbuilder_testbench_clock_GNXGQJH2DS;
component alt_dspbuilder_testbench_salt_GNOXVOQUET is
generic (
XFILE : string := "default"
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_testbench_salt_GNOXVOQUET;
component alt_dspbuilder_testbench_salt_GNDBMPYDND is
generic (
XFILE : string := "default"
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
output : out std_logic -- wire
);
end component alt_dspbuilder_testbench_salt_GNDBMPYDND;
component alt_dspbuilder_testbench_salt_GN6DKNTQ5M is
generic (
XFILE : string := "default"
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
output : out std_logic_vector(1 downto 0) -- wire
);
end component alt_dspbuilder_testbench_salt_GN6DKNTQ5M;
component alt_dspbuilder_testbench_salt_GN7Z4SHGOK is
generic (
XFILE : string := "default"
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
output : out std_logic_vector(31 downto 0) -- wire
);
end component alt_dspbuilder_testbench_salt_GN7Z4SHGOK;
component alt_dspbuilder_testbench_capture_GNQX2JTRTZ is
generic (
XFILE : string := "default";
DSPBTYPE : string := ""
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
input : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_testbench_capture_GNQX2JTRTZ;
component alt_dspbuilder_testbench_capture_GNHCRI5YMO is
generic (
XFILE : string := "default";
DSPBTYPE : string := ""
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
input : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_testbench_capture_GNHCRI5YMO;
signal salt_avalon_st_sink_data_output_wire : std_logic_vector(23 downto 0); -- salt_Avalon_ST_Sink_data:output -> dut:Avalon_ST_Sink_data
signal clock_clock_tb_reset : std_logic; -- Clock:tb_aclr -> [salt_Avalon_MM_Slave_address:aclr, salt_Avalon_MM_Slave_write:aclr, salt_Avalon_MM_Slave_writedata:aclr, salt_Avalon_ST_Sink_data:aclr, salt_Avalon_ST_Sink_endofpacket:aclr, salt_Avalon_ST_Sink_startofpacket:aclr, salt_Avalon_ST_Sink_valid:aclr, salt_Avalon_ST_Source_ready:aclr]
signal clock_clock_tb_clk : std_logic; -- Clock:clock_out -> [capture_Avalon_ST_Sink_ready:clock, capture_Avalon_ST_Source_data:clock, capture_Avalon_ST_Source_endofpacket:clock, capture_Avalon_ST_Source_startofpacket:clock, capture_Avalon_ST_Source_valid:clock, dut:Clock, salt_Avalon_MM_Slave_address:clock, salt_Avalon_MM_Slave_write:clock, salt_Avalon_MM_Slave_writedata:clock, salt_Avalon_ST_Sink_data:clock, salt_Avalon_ST_Sink_endofpacket:clock, salt_Avalon_ST_Sink_startofpacket:clock, salt_Avalon_ST_Sink_valid:clock, salt_Avalon_ST_Source_ready:clock]
signal salt_avalon_st_sink_endofpacket_output_wire : std_logic; -- salt_Avalon_ST_Sink_endofpacket:output -> dut:Avalon_ST_Sink_endofpacket
signal salt_avalon_mm_slave_address_output_wire : std_logic_vector(1 downto 0); -- salt_Avalon_MM_Slave_address:output -> dut:Avalon_MM_Slave_address
signal salt_avalon_mm_slave_writedata_output_wire : std_logic_vector(31 downto 0); -- salt_Avalon_MM_Slave_writedata:output -> dut:Avalon_MM_Slave_writedata
signal salt_avalon_st_sink_valid_output_wire : std_logic; -- salt_Avalon_ST_Sink_valid:output -> dut:Avalon_ST_Sink_valid
signal salt_avalon_st_source_ready_output_wire : std_logic; -- salt_Avalon_ST_Source_ready:output -> dut:Avalon_ST_Source_ready
signal salt_avalon_mm_slave_write_output_wire : std_logic; -- salt_Avalon_MM_Slave_write:output -> dut:Avalon_MM_Slave_write
signal salt_avalon_st_sink_startofpacket_output_wire : std_logic; -- salt_Avalon_ST_Sink_startofpacket:output -> dut:Avalon_ST_Sink_startofpacket
signal dut_avalon_st_source_valid_wire : std_logic; -- dut:Avalon_ST_Source_valid -> capture_Avalon_ST_Source_valid:input
signal clock_clock_reg_reset_reset : std_logic; -- Clock:reg_aclr_out -> [capture_Avalon_ST_Sink_ready:aclr, capture_Avalon_ST_Source_data:aclr, capture_Avalon_ST_Source_endofpacket:aclr, capture_Avalon_ST_Source_startofpacket:aclr, capture_Avalon_ST_Source_valid:aclr]
signal dut_avalon_st_source_endofpacket_wire : std_logic; -- dut:Avalon_ST_Source_endofpacket -> capture_Avalon_ST_Source_endofpacket:input
signal dut_avalon_st_source_startofpacket_wire : std_logic; -- dut:Avalon_ST_Source_startofpacket -> capture_Avalon_ST_Source_startofpacket:input
signal dut_avalon_st_sink_ready_wire : std_logic; -- dut:Avalon_ST_Sink_ready -> capture_Avalon_ST_Sink_ready:input
signal dut_avalon_st_source_data_wire : std_logic_vector(23 downto 0); -- dut:Avalon_ST_Source_data -> capture_Avalon_ST_Source_data:input
signal clock_clock_output_reset : std_logic; -- Clock:aclr_out -> clock_clock_output_reset:in
signal clock_clock_output_reset_ports_inv : std_logic; -- clock_clock_output_reset:inv -> dut:aclr
begin
dut : component Gray_Binarization_GN
port map (
Clock => clock_clock_tb_clk, -- Clock.clk
aclr => clock_clock_output_reset_ports_inv, -- .reset_n
Avalon_ST_Sink_data => salt_avalon_st_sink_data_output_wire, -- Avalon_ST_Sink_data.wire
Avalon_ST_Sink_endofpacket => salt_avalon_st_sink_endofpacket_output_wire, -- Avalon_ST_Sink_endofpacket.wire
Avalon_MM_Slave_address => salt_avalon_mm_slave_address_output_wire, -- Avalon_MM_Slave_address.wire
Avalon_MM_Slave_writedata => salt_avalon_mm_slave_writedata_output_wire, -- Avalon_MM_Slave_writedata.wire
Avalon_ST_Source_valid => dut_avalon_st_source_valid_wire, -- Avalon_ST_Source_valid.wire
Avalon_ST_Sink_valid => salt_avalon_st_sink_valid_output_wire, -- Avalon_ST_Sink_valid.wire
Avalon_ST_Source_endofpacket => dut_avalon_st_source_endofpacket_wire, -- Avalon_ST_Source_endofpacket.wire
Avalon_ST_Source_startofpacket => dut_avalon_st_source_startofpacket_wire, -- Avalon_ST_Source_startofpacket.wire
Avalon_ST_Source_ready => salt_avalon_st_source_ready_output_wire, -- Avalon_ST_Source_ready.wire
Avalon_MM_Slave_write => salt_avalon_mm_slave_write_output_wire, -- Avalon_MM_Slave_write.wire
Avalon_ST_Sink_ready => dut_avalon_st_sink_ready_wire, -- Avalon_ST_Sink_ready.wire
Avalon_ST_Sink_startofpacket => salt_avalon_st_sink_startofpacket_output_wire, -- Avalon_ST_Sink_startofpacket.wire
Avalon_ST_Source_data => dut_avalon_st_source_data_wire -- Avalon_ST_Source_data.wire
);
clock : component alt_dspbuilder_testbench_clock_GNXGQJH2DS
generic map (
SIMULATION_START_CYCLE => 5,
RESET_LATENCY => 0,
RESET_REGISTER_CASCADE_DEPTH => 0
)
port map (
clock_out => clock_clock_tb_clk, -- clock_tb.clk
tb_aclr => clock_clock_tb_reset, -- .reset
aclr_out => clock_clock_output_reset, -- clock_output.reset
reg_aclr_out => clock_clock_reg_reset_reset -- clock_reg_reset.reset
);
salt_avalon_st_sink_data : component alt_dspbuilder_testbench_salt_GNOXVOQUET
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Sink_data.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_st_sink_data_output_wire -- output.wire
);
salt_avalon_st_sink_endofpacket : component alt_dspbuilder_testbench_salt_GNDBMPYDND
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Sink_endofpacket.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_st_sink_endofpacket_output_wire -- output.wire
);
salt_avalon_mm_slave_address : component alt_dspbuilder_testbench_salt_GN6DKNTQ5M
generic map (
XFILE => "Gray%5FBinarization_Avalon-MM+Slave_address.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_mm_slave_address_output_wire -- output.wire
);
salt_avalon_mm_slave_writedata : component alt_dspbuilder_testbench_salt_GN7Z4SHGOK
generic map (
XFILE => "Gray%5FBinarization_Avalon-MM+Slave_writedata.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_mm_slave_writedata_output_wire -- output.wire
);
salt_avalon_st_sink_valid : component alt_dspbuilder_testbench_salt_GNDBMPYDND
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Sink_valid.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_st_sink_valid_output_wire -- output.wire
);
salt_avalon_st_source_ready : component alt_dspbuilder_testbench_salt_GNDBMPYDND
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Source_ready.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_st_source_ready_output_wire -- output.wire
);
salt_avalon_mm_slave_write : component alt_dspbuilder_testbench_salt_GNDBMPYDND
generic map (
XFILE => "Gray%5FBinarization_Avalon-MM+Slave_write.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_mm_slave_write_output_wire -- output.wire
);
salt_avalon_st_sink_startofpacket : component alt_dspbuilder_testbench_salt_GNDBMPYDND
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Sink_startofpacket.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_st_sink_startofpacket_output_wire -- output.wire
);
capture_avalon_st_source_valid : component alt_dspbuilder_testbench_capture_GNQX2JTRTZ
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Source_valid.capture.msim",
DSPBTYPE => "BIT [1, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_avalon_st_source_valid_wire -- input.wire
);
capture_avalon_st_source_endofpacket : component alt_dspbuilder_testbench_capture_GNQX2JTRTZ
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Source_endofpacket.capture.msim",
DSPBTYPE => "BIT [1, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_avalon_st_source_endofpacket_wire -- input.wire
);
capture_avalon_st_source_startofpacket : component alt_dspbuilder_testbench_capture_GNQX2JTRTZ
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Source_startofpacket.capture.msim",
DSPBTYPE => "BIT [1, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_avalon_st_source_startofpacket_wire -- input.wire
);
capture_avalon_st_sink_ready : component alt_dspbuilder_testbench_capture_GNQX2JTRTZ
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Sink_ready.capture.msim",
DSPBTYPE => "BIT [1, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_avalon_st_sink_ready_wire -- input.wire
);
capture_avalon_st_source_data : component alt_dspbuilder_testbench_capture_GNHCRI5YMO
generic map (
XFILE => "Gray%5FBinarization_Avalon-ST+Source_data.capture.msim",
DSPBTYPE => "UINT [24, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_avalon_st_source_data_wire -- input.wire
);
clock_clock_output_reset_ports_inv <= not clock_clock_output_reset;
end architecture rtl; -- of tb_Gray_Binarization
|
mit
|
8b99ac5741d7ddec4f0c5626f12a9406
| 0.594595 | 3.436508 | false | true | false | false |
nanomolina/MIPS
|
prueba/flopr.vhd
| 3 | 439 |
library ieee;
use ieee.std_logic_1164.all;
entity flopr is
port (
d: in std_logic_vector(31 downto 0);
rst, clk: in std_logic;
q: out std_logic_vector(31 downto 0));
end entity;
architecture behavior of flopr is
begin
process (clk, rst) begin
if (rst = '1') then
q <= (others => '0');
elsif (clk'event and clk = '1') then
q <= d;
end if;
end process;
end architecture;
|
gpl-3.0
|
27eb4ae42d164ccc138a178722dfb143
| 0.578588 | 3.325758 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/top/afc_v3/wb_trigger/wb_trigger_top.vhd
| 1 | 19,993 |
-------------------------------------------------------------------------------
-- Title : Wishbone trigger component toplevel
-- Project :
-------------------------------------------------------------------------------
-- File : wb_trigger_top.vhd
-- Author : Vitor Finotti Ferreira <vfinotti@finotti-Inspiron-7520>
-- Company : Brazilian Synchrotron Light Laboratory, LNLS/CNPEM
-- Created : 2016-02-02
-- Last update: 2016-05-10
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2016 Brazilian Synchrotron Light Laboratory, LNLS/CNPEM
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public License
-- as published by the Free Software Foundation, either version 3 of
-- the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-02-02 1.0 vfinotti Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Memory core generator
use work.gencores_pkg.all;
-- Custom Wishbone Modules
use work.ifc_wishbone_pkg.all;
-- Custom common cores
use work.ifc_common_pkg.all;
-- Trigger definitons
use work.trigger_pkg.all;
-- Positicon Calc constants
use work.machine_pkg.all;
-- Genrams
use work.genram_pkg.all;
-- Meta Package
--use work.synthesis_descriptor_pkg.all;
-- AXI cores
--use work.pcie_cntr_axi_pkg.all;
use work.bpm_pcie_a7_const_pkg.all;
-- PCIe Core
use work.bpm_pcie_a7_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity wb_trigger_top is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
-----------------------------------------
-- PCIe pins
-----------------------------------------
-- DDR3 memory pins
ddr3_dq_b : inout std_logic_vector(c_ddr_dq_width-1 downto 0);
ddr3_dqs_p_b : inout std_logic_vector(c_ddr_dqs_width-1 downto 0);
ddr3_dqs_n_b : inout std_logic_vector(c_ddr_dqs_width-1 downto 0);
ddr3_addr_o : out std_logic_vector(c_ddr_row_width-1 downto 0);
ddr3_ba_o : out std_logic_vector(c_ddr_bank_width-1 downto 0);
ddr3_cs_n_o : out std_logic_vector(0 downto 0);
ddr3_ras_n_o : out std_logic;
ddr3_cas_n_o : out std_logic;
ddr3_we_n_o : out std_logic;
ddr3_reset_n_o : out std_logic;
ddr3_ck_p_o : out std_logic_vector(c_ddr_ck_width-1 downto 0);
ddr3_ck_n_o : out std_logic_vector(c_ddr_ck_width-1 downto 0);
ddr3_cke_o : out std_logic_vector(c_ddr_cke_width-1 downto 0);
ddr3_dm_o : out std_logic_vector(c_ddr_dm_width-1 downto 0);
ddr3_odt_o : out std_logic_vector(c_ddr_odt_width-1 downto 0);
-- PCIe transceivers
pci_exp_rxp_i : in std_logic_vector(c_pcie_lanes - 1 downto 0);
pci_exp_rxn_i : in std_logic_vector(c_pcie_lanes - 1 downto 0);
pci_exp_txp_o : out std_logic_vector(c_pcie_lanes - 1 downto 0);
pci_exp_txn_o : out std_logic_vector(c_pcie_lanes - 1 downto 0);
-- PCI clock and reset signals
pcie_clk_p_i : in std_logic;
pcie_clk_n_i : in std_logic;
-- Trigger signals
trig_dir_o : out std_logic_vector(7 downto 0);
trig_b : inout std_logic_vector(7 downto 0)
);
end wb_trigger_top;
architecture structural of wb_trigger_top is
-------------------------------------------------------------------------------
-- Chipscope
-------------------------------------------------------------------------------
component chipscope_icon_1_port is
port (
CONTROL0 : inout std_logic_vector(35 downto 0));
end component chipscope_icon_1_port;
component chipscope_ila is
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0));
end component chipscope_ila;
component chipscope_vio_16 is
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
SYNC_OUT : out std_logic_vector(15 downto 0));
end component chipscope_vio_16;
-----------------------------------------------------------------------------
-- Clock and system
-----------------------------------------------------------------------------
component clk_gen is
port (
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic;
sys_clk_bufg_o : out std_logic);
end component clk_gen;
component sys_pll is
generic(
-- 200 MHz input clock
g_clkin_period : real := 5.000;
g_divclk_divide : integer := 1;
g_clkbout_mult_f : integer := 5;
-- Reference jitter
g_ref_jitter : real := 0.010;
-- 100 MHz output clock
g_clk0_divide_f : integer := 10;
-- 200 MHz output clock
g_clk1_divide : integer := 5;
g_clk2_divide : integer := 6
);
port (
rst_i : in std_logic := '0';
clk_i : in std_logic := '0';
clk0_o : out std_logic;
clk1_o : out std_logic;
clk2_o : out std_logic;
locked_o : out std_logic);
end component sys_pll;
-- Constants
constant c_width_bus_size : positive := 8;
constant c_rcv_len_bus_width : positive := 8;
constant c_transm_len_bus_width : positive := 8;
constant c_sync_edge : string := "positive";
constant c_trig_num : positive := 8;
constant c_intern_num : positive := 8;
constant c_rcv_intern_num : positive := 2;
constant c_counter_wid : positive := 16;
constant c_num_tlvl_clks : natural := 3;
constant c_masters : natural := 1;
constant c_slaves : natural := 3;
constant c_slv_trigger_iface_id : natural := 0;
constant c_slv_trigger_mux0_id : natural := 1;
constant c_slv_trigger_mux1_id : natural := 2;
constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) :=
(
c_slv_trigger_iface_id => f_sdb_embed_device(c_xwb_trigger_iface_sdb, x"10000000"),
c_slv_trigger_mux0_id => f_sdb_embed_device(c_xwb_trigger_mux_sdb, x"20000000"),
c_slv_trigger_mux1_id => f_sdb_embed_device(c_xwb_trigger_mux_sdb, x"30000000")
);
constant c_button_rst_width : natural := 255;
constant c_sdb_address : t_wishbone_address := x"00000000";
constant c_ma_pcie_id : natural := 0;
constant c_num_mux_interfaces : natural := 2;
signal c_clk_sys_id : natural := 0;
signal c_clk_200mhz_id : natural := 1;
signal c_clk_133mhz_id : natural := 2;
signal CONTROL0 : std_logic_vector(35 downto 0);
-- Global Clock Single ended
signal clk_sys, clk_200mhz, clk_133mhz : std_logic;
signal sys_clk_gen_bufg : std_logic;
signal sys_clk_gen : std_logic;
signal reset_rstn : std_logic_vector(c_num_tlvl_clks-1 downto 0);
signal reset_clks : std_logic_vector(c_num_tlvl_clks-1 downto 0);
-- Clocks and resets signals
signal locked : std_logic;
signal clk_sys_pcie_rstn : std_logic;
signal clk_sys_pcie_rst : std_logic;
signal clk_sys_rstn : std_logic;
signal clk_sys_rst : std_logic;
signal clk_200mhz_rst : std_logic;
signal clk_200mhz_rstn : std_logic;
signal clk_133mhz_rst : std_logic;
signal clk_133mhz_rstn : std_logic;
signal rst_button_sys_pp : std_logic;
signal rst_button_sys : std_logic;
signal rst_button_sys_n : std_logic;
-- Crossbar master/slave arrays
signal cbar_slave_i : t_wishbone_slave_in_array (c_masters-1 downto 0);
signal cbar_slave_o : t_wishbone_slave_out_array(c_masters-1 downto 0);
signal cbar_master_i : t_wishbone_master_in_array(c_slaves-1 downto 0);
signal cbar_master_o : t_wishbone_master_out_array(c_slaves-1 downto 0);
signal wb_ma_pcie_rst : std_logic;
signal wb_ma_pcie_rstn : std_logic;
signal wb_ma_pcie_rstn_sync : std_logic;
signal wb_slv_in : t_wishbone_slave_in;
signal wb_slv_out : t_wishbone_slave_out;
signal trig_rcv_intern : t_trig_channel_array2d(1 downto 0, 1 downto 0);
signal trig_pulse_transm : t_trig_channel_array2d(1 downto 0, 7 downto 0);
signal trig_pulse_rcv : t_trig_channel_array2d(1 downto 0, 7 downto 0);
signal trig_dir_int : std_logic_vector(7 downto 0);
begin
cmp_chipscope_icon_1 : chipscope_icon_1_port
port map (
CONTROL0 => CONTROL0);
cmp_chipscope_ila_0 : chipscope_ila
port map (
CONTROL => CONTROL0,
CLK => clk_133mhz,
TRIG0(31 downto 24) => trig_dir_int,
TRIG0(23) => trig_pulse_rcv(0, 7).pulse,
TRIG0(22) => trig_pulse_rcv(0, 6).pulse,
TRIG0(21) => trig_pulse_rcv(0, 5).pulse,
TRIG0(20) => trig_pulse_rcv(0, 4).pulse,
TRIG0(19) => trig_pulse_rcv(0, 3).pulse,
TRIG0(18) => trig_pulse_rcv(0, 2).pulse,
TRIG0(17) => trig_pulse_rcv(0, 1).pulse,
TRIG0(16) => trig_pulse_rcv(0, 0).pulse,
TRIG0(15) => trig_pulse_transm(0, 7).pulse,
TRIG0(14) => trig_pulse_transm(0, 6).pulse,
TRIG0(13) => trig_pulse_transm(0, 5).pulse,
TRIG0(12) => trig_pulse_transm(0, 4).pulse,
TRIG0(11) => trig_pulse_transm(0, 3).pulse,
TRIG0(10) => trig_pulse_transm(0, 2).pulse,
TRIG0(9) => trig_pulse_transm(0, 1).pulse,
TRIG0(8) => trig_pulse_transm(0, 0).pulse,
TRIG0(7 downto 2) => (others => '0'),
TRIG0(1) => trig_rcv_intern(0, 1).pulse,
TRIG0(0) => trig_rcv_intern(0, 0).pulse,
TRIG1 => (others => '0'),
TRIG2 => (others => '0'),
TRIG3 => (others => '0'));
trig_dir_o <= trig_dir_int;
-- Clock generation
cmp_clk_gen : clk_gen
port map (
sys_clk_p_i => sys_clk_p_i,
sys_clk_n_i => sys_clk_n_i,
sys_clk_o => sys_clk_gen,
sys_clk_bufg_o => sys_clk_gen_bufg
);
-- Obtain core locking and generate necessary clocks
cmp_sys_pll_inst : sys_pll
generic map (
-- 125 MHz input clock
g_clkin_period => 8.000,
g_divclk_divide => 5,
g_clkbout_mult_f => 32,
-- 100 MHz output clock
g_clk0_divide_f => 8,
-- 200 MHz output clock
g_clk1_divide => 4,
-- 133 MHz output clock
g_clk2_divide => 6
)
port map (
rst_i => '0',
clk_i => sys_clk_gen_bufg,
--clk_i => sys_clk_gen,
clk0_o => clk_sys, -- 100MHz locked clock
clk1_o => clk_200mhz, -- 200MHz locked clock
clk2_o => clk_133mhz, -- 133MHz locked clock
locked_o => locked -- '1' when the PLL has locked
);
-- Reset synchronization. Hold reset line until few locked cycles have passed.
cmp_reset : gc_reset
generic map(
g_clocks => c_num_tlvl_clks -- CLK_SYS & CLK_200
)
port map(
--free_clk_i => sys_clk_gen,
free_clk_i => sys_clk_gen_bufg,
locked_i => locked,
clks_i => reset_clks,
rstn_o => reset_rstn
);
reset_clks(c_clk_sys_id) <= clk_sys;
reset_clks(c_clk_200mhz_id) <= clk_200mhz;
reset_clks(c_clk_133mhz_id) <= clk_133mhz;
-- Reset for PCIe core. Caution when resetting the PCIe core after the
-- initialization. The PCIe core needs to retrain the link and the PCIe
-- host (linux OS, likely) will not be able to do that automatically,
-- probably.
clk_sys_pcie_rstn <= reset_rstn(c_clk_sys_id) and rst_button_sys_n;
clk_sys_pcie_rst <= not clk_sys_pcie_rstn;
-- Reset for all other modules
clk_sys_rstn <= reset_rstn(c_clk_sys_id) and rst_button_sys_n and
wb_ma_pcie_rstn_sync;
clk_sys_rst <= not clk_sys_rstn;
-- Reset synchronous to clk200mhz
clk_200mhz_rstn <= reset_rstn(c_clk_200mhz_id);
clk_200mhz_rst <= not(reset_rstn(c_clk_200mhz_id));
-- Reset synchronous to clk133mhz
clk_133mhz_rstn <= reset_rstn(c_clk_133mhz_id);
clk_133mhz_rst <= not(reset_rstn(c_clk_133mhz_id));
-- Generate button reset synchronous to each clock domain
-- Detect button positive edge of clk_sys
cmp_button_sys_ffs : gc_sync_ffs
port map (
clk_i => clk_sys,
rst_n_i => '1',
data_i => '0', --sys_rst_button_n_i,
npulse_o => rst_button_sys_pp
);
-- Generate the reset signal based on positive edge
-- of synched gc
cmp_button_sys_rst : gc_extend_pulse
generic map (
g_width => c_button_rst_width
)
port map(
clk_i => clk_sys,
rst_n_i => '1',
pulse_i => rst_button_sys_pp,
extended_o => rst_button_sys
);
rst_button_sys_n <= not rst_button_sys;
-- The top-most Wishbone B.4 crossbar
cmp_interconnect : xwb_sdb_crossbar
generic map(
g_num_masters => c_masters,
g_num_slaves => c_slaves,
g_registered => true,
g_wraparound => true, -- Should be true for nested buses
g_layout => c_layout,
g_sdb_addr => c_sdb_address
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- Master connections (INTERCON is a slave)
slave_i => cbar_slave_i,
slave_o => cbar_slave_o,
-- Slave connections (INTERCON is a master)
master_i => cbar_master_i,
master_o => cbar_master_o
);
-- The LM32 is master 0+1
--lm32_rstn <= clk_sys_rstn;
--cmp_lm32 : xwb_lm32
--generic map(
-- g_profile => "medium_icache_debug"
--) -- Including JTAG and I-cache (no divide)
--port map(
-- clk_sys_i => clk_sys,
-- rst_n_i => lm32_rstn,
-- irq_i => lm32_interrupt,
-- dwb_o => cbar_slave_i(0), -- Data bus
-- dwb_i => cbar_slave_o(0),
-- iwb_o => cbar_slave_i(1), -- Instruction bus
-- iwb_i => cbar_slave_o(1)
--);
-- Interrupt '0' is Button(0).
-- Interrupts 31 downto 1 are disabled
--lm32_interrupt <= (0 => not buttons_i(0), others => '0');
----------------------------------
-- PCIe Core --
----------------------------------
cmp_xwb_bpm_pcie_a7 : xwb_bpm_pcie_a7
generic map (
g_ma_interface_mode => PIPELINED,
g_ma_address_granularity => BYTE,
g_ext_rst_pin => false,
g_sim_bypass_init_cal => "OFF"
)
port map (
-- DDR3 memory pins
ddr3_dq_b => ddr3_dq_b,
ddr3_dqs_p_b => ddr3_dqs_p_b,
ddr3_dqs_n_b => ddr3_dqs_n_b,
ddr3_addr_o => ddr3_addr_o,
ddr3_ba_o => ddr3_ba_o,
ddr3_cs_n_o => ddr3_cs_n_o,
ddr3_ras_n_o => ddr3_ras_n_o,
ddr3_cas_n_o => ddr3_cas_n_o,
ddr3_we_n_o => ddr3_we_n_o,
ddr3_reset_n_o => ddr3_reset_n_o,
ddr3_ck_p_o => ddr3_ck_p_o,
ddr3_ck_n_o => ddr3_ck_n_o,
ddr3_cke_o => ddr3_cke_o,
ddr3_dm_o => ddr3_dm_o,
ddr3_odt_o => ddr3_odt_o,
-- PCIe transceivers
pci_exp_rxp_i => pci_exp_rxp_i,
pci_exp_rxn_i => pci_exp_rxn_i,
pci_exp_txp_o => pci_exp_txp_o,
pci_exp_txn_o => pci_exp_txn_o,
-- Necessity signals
ddr_clk_p_i => clk_200mhz, --200 MHz DDR core clock (connect through BUFG or PLL)
ddr_clk_n_i => '0', --200 MHz DDR core clock (connect through BUFG or PLL)
pcie_clk_p_i => pcie_clk_p_i, --100 MHz PCIe Clock (connect directly to input pin)
pcie_clk_n_i => pcie_clk_n_i, --100 MHz PCIe Clock
pcie_rst_n_i => clk_sys_pcie_rstn, -- PCIe core reset
-- DDR memory controller interface --
ddr_core_rst_i => clk_sys_pcie_rst,
memc_ui_clk_o => open,
memc_ui_rst_o => open,
memc_cmd_rdy_o => open,
memc_cmd_en_i => '0',
memc_cmd_instr_i => (others => '0'),
memc_cmd_addr_i => (others => '0'),
memc_wr_en_i => '0',
memc_wr_end_i => '0',
memc_wr_mask_i => (others => '0'),
memc_wr_data_i => (others => '0'),
memc_wr_rdy_o => open,
memc_rd_data_o => open,
memc_rd_valid_o => open,
---- memory arbiter interface
memarb_acc_req_i => '0',
memarb_acc_gnt_o => open,
-- Wishbone interface --
wb_clk_i => clk_sys,
-- Reset wishbone interface with the same reset as the other
-- modules, including a reset coming from the PCIe itself.
wb_rst_i => clk_sys_rst,
wb_ma_i => cbar_slave_o(c_ma_pcie_id),
wb_ma_o => cbar_slave_i(c_ma_pcie_id),
-- Additional exported signals for instantiation
wb_ma_pcie_rst_o => wb_ma_pcie_rst,
-- Debug signals
dbg_app_addr_o => open,
dbg_app_cmd_o => open,
dbg_app_en_o => open,
dbg_app_wdf_data_o => open,
dbg_app_wdf_end_o => open,
dbg_app_wdf_wren_o => open,
dbg_app_wdf_mask_o => open,
dbg_app_rd_data_o => open,
dbg_app_rd_data_end_o => open,
dbg_app_rd_data_valid_o => open,
dbg_app_rdy_o => open,
dbg_app_wdf_rdy_o => open,
dbg_ddr_ui_clk_o => open,
dbg_ddr_ui_reset_o => open,
dbg_arb_req_o => open,
dbg_arb_gnt_o => open
);
wb_ma_pcie_rstn <= not wb_ma_pcie_rst;
cmp_pcie_reset_synch : reset_synch
port map
(
clk_i => clk_sys,
arst_n_i => wb_ma_pcie_rstn,
rst_n_o => wb_ma_pcie_rstn_sync
);
cmp_xwb_trigger : xwb_trigger
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_sync_edge => c_sync_edge,
g_trig_num => c_trig_num,
g_intern_num => c_intern_num,
g_rcv_intern_num => c_rcv_intern_num,
g_num_mux_interfaces => c_num_mux_interfaces,
g_out_resolver => "fanout",
g_in_resolver => "or"
)
port map (
rst_n_i => clk_sys_rstn,
clk_i => clk_sys,
ref_clk_i => clk_133mhz,
ref_rst_n_i => clk_133mhz_rstn,
fs_clk_array_i => (clk_133mhz, clk_133mhz),
fs_rst_n_array_i => (clk_133mhz_rstn, clk_133mhz_rstn),
wb_slv_trigger_iface_i => cc_dummy_slave_in,
wb_slv_trigger_iface_o => open,
wb_slv_trigger_mux_i => (cc_dummy_slave_in, cc_dummy_slave_in),
wb_slv_trigger_mux_o => open,
trig_dir_o => trig_dir_int,
trig_rcv_intern_i => trig_rcv_intern,
trig_pulse_transm_i => trig_pulse_transm,
trig_pulse_rcv_o => trig_pulse_rcv,
trig_b => trig_b);
end architecture structural;
|
lgpl-3.0
|
02619d2c4f3659834fe22bb6f6ee874b
| 0.537938 | 3.213275 | false | false | false | false |
Given-Jiang/Gray_Binarization
|
tb_Gray_Binarization/db/alt_dspbuilder_delay.vhd
| 1 | 4,983 |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_delay is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 0;
BITPATTERN : string := "00000001";
WIDTH : positive := 8
);
port (
input : in std_logic_vector(width-1 downto 0) := (others=>'0');
clock : in std_logic := '0';
sclr : in std_logic := '0';
aclr : in std_logic := '0';
output : out std_logic_vector(width-1 downto 0);
ena : in std_logic := '0'
);
end entity alt_dspbuilder_delay;
architecture rtl of alt_dspbuilder_delay is
component alt_dspbuilder_delay_GNUECIBFDH is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 1;
BITPATTERN : string := "0";
WIDTH : positive := 1
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
ena : in std_logic := '0';
input : in std_logic_vector(1-1 downto 0) := (others=>'0');
output : out std_logic_vector(1-1 downto 0);
sclr : in std_logic := '0'
);
end component alt_dspbuilder_delay_GNUECIBFDH;
component alt_dspbuilder_delay_GND2PGZRBZ is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 1;
BITPATTERN : string := "1";
WIDTH : positive := 1
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
ena : in std_logic := '0';
input : in std_logic_vector(1-1 downto 0) := (others=>'0');
output : out std_logic_vector(1-1 downto 0);
sclr : in std_logic := '0'
);
end component alt_dspbuilder_delay_GND2PGZRBZ;
component alt_dspbuilder_delay_GNHYCSAEGT is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 0;
BITPATTERN : string := "0";
WIDTH : positive := 1
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
ena : in std_logic := '0';
input : in std_logic_vector(1-1 downto 0) := (others=>'0');
output : out std_logic_vector(1-1 downto 0);
sclr : in std_logic := '0'
);
end component alt_dspbuilder_delay_GNHYCSAEGT;
component alt_dspbuilder_delay_GNVTJPHWYT is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 1;
BITPATTERN : string := "01111111";
WIDTH : positive := 8
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
ena : in std_logic := '0';
input : in std_logic_vector(8-1 downto 0) := (others=>'0');
output : out std_logic_vector(8-1 downto 0);
sclr : in std_logic := '0'
);
end component alt_dspbuilder_delay_GNVTJPHWYT;
begin
alt_dspbuilder_delay_GNUECIBFDH_0: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "0") and (WIDTH = 1)) generate
inst_alt_dspbuilder_delay_GNUECIBFDH_0: alt_dspbuilder_delay_GNUECIBFDH
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 1, BITPATTERN => "0", WIDTH => 1)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
alt_dspbuilder_delay_GND2PGZRBZ_1: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "1") and (WIDTH = 1)) generate
inst_alt_dspbuilder_delay_GND2PGZRBZ_1: alt_dspbuilder_delay_GND2PGZRBZ
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 1, BITPATTERN => "1", WIDTH => 1)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
alt_dspbuilder_delay_GNHYCSAEGT_2: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 0) and (BITPATTERN = "0") and (WIDTH = 1)) generate
inst_alt_dspbuilder_delay_GNHYCSAEGT_2: alt_dspbuilder_delay_GNHYCSAEGT
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 0, BITPATTERN => "0", WIDTH => 1)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
alt_dspbuilder_delay_GNVTJPHWYT_3: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "01111111") and (WIDTH = 8)) generate
inst_alt_dspbuilder_delay_GNVTJPHWYT_3: alt_dspbuilder_delay_GNVTJPHWYT
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 1, BITPATTERN => "01111111", WIDTH => 8)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
assert not (((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "0") and (WIDTH = 1)) or ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "1") and (WIDTH = 1)) or ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 0) and (BITPATTERN = "0") and (WIDTH = 1)) or ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "01111111") and (WIDTH = 8)))
report "Please run generate again" severity error;
end architecture rtl;
|
mit
|
e6c1c19ecf716cc5c476d8ff245e4ba8
| 0.640177 | 3.087361 | false | false | false | false |
mithro/soft-utmi
|
hdl/third_party/XAPP1064-serdes-macros/VHDL_Source/Top level examples/BUFIO2 DDR/top_nto1_ddr_diff_rx.vhd
| 1 | 7,684 |
------------------------------------------------------------------------------/
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------/
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: top_nto1_ddr_diff_rx.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: June 1 2009
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: Example differential input receiver for DDR clock and data using 2 x BUFIO2
-- Serdes factor and number of data lines are set by constants in the code
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
--
------------------------------------------------------------------------------/
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and signalulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity top_nto1_ddr_diff_rx is port (
reset : in std_logic ; -- reset (active high)
datain_p, datain_n : in std_logic_vector(7 downto 0) ; -- differential data inputs
clkin_p, clkin_n : in std_logic ; -- differential clock input
dummy_out : out std_logic_vector(63 downto 0) ) ; -- dummy outputs
end top_nto1_ddr_diff_rx ;
architecture arch_top_nto1_ddr_diff_rx of top_nto1_ddr_diff_rx is
component serdes_1_to_n_clk_ddr_s8_diff is generic (
S : integer := 8) ; -- Parameter to set the serdes factor 1..8
port (
clkin_p : in std_logic ; -- Input from LVDS receiver pin
clkin_n : in std_logic ; -- Input from LVDS receiver pin
rxioclkp : out std_logic ; -- IO Clock network
rxioclkn : out std_logic ; -- IO Clock network
rx_serdesstrobe : out std_logic ; -- Parallel data capture strobe
rx_bufg_x1 : out std_logic) ; -- Global clock
end component ;
component serdes_1_to_n_data_ddr_s8_diff is generic (
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
D : integer := 16) ; -- Set the number of inputs and outputs
port (
use_phase_detector : in std_logic ; -- '1' enables the phase detector logic if USE_PD = TRUE
datain_p : in std_logic_vector(D-1 downto 0) ; -- Input from LVDS receiver pin
datain_n : in std_logic_vector(D-1 downto 0) ; -- Input from LVDS receiver pin
rxioclkp : in std_logic ; -- IO Clock network
rxioclkn : in std_logic ; -- IO Clock network
rxserdesstrobe : in std_logic ; -- Parallel data capture strobe
reset : in std_logic ; -- Reset line
gclk : in std_logic ; -- Global clock
bitslip : in std_logic ; -- Bitslip control line
data_out : out std_logic_vector((D*S)-1 downto 0) ; -- Output data
debug_in : in std_logic_vector(1 downto 0) ; -- Debug Inputs, set to '0' if not required
debug : out std_logic_vector((2*D)+6 downto 0)) ; -- Debug output bus, 2D+6 = 2 lines per input (from mux and ce) + 7, leave nc if debug not required
end component ;
-- constants for serdes factor and number of IO pins
constant S : integer := 8 ; -- Set the serdes factor to 8
constant D : integer := 8 ; -- Set the number of inputs and outputs
constant DS : integer := (D*S)-1 ; -- Used for bus widths = serdes factor * number of inputs - 1
signal rst : std_logic ;
signal rxd : std_logic_vector(DS downto 0) ; -- Data from serdeses
signal rxr : std_logic_vector(DS downto 0); -- signalistered Data from serdeses
signal state : std_logic ;
signal bslip : std_logic ;
signal count : std_logic_vector(3 downto 0);
signal rxioclkp : std_logic ;
signal rxioclkn : std_logic ;
signal rx_serdesstrobe : std_logic ;
signal rx_bufg_x1 : std_logic ;
begin
rst <= reset ; -- active high reset pin
dummy_out <= rxr ;
-- Clock Input. Generate ioclocks via BUFIO2
inst_clkin : serdes_1_to_n_clk_ddr_s8_diff generic map(
S => S)
port map (
clkin_p => clkin_p,
clkin_n => clkin_n,
rxioclkp => rxioclkp,
rxioclkn => rxioclkn,
rx_serdesstrobe => rx_serdesstrobe,
rx_bufg_x1 => rx_bufg_x1);
-- Data Inputs
inst_datain : serdes_1_to_n_data_ddr_s8_diff generic map(
S => S,
D => D)
port map (
use_phase_detector => '1', -- '1' enables the phase detector logic
datain_p => datain_p,
datain_n => datain_n,
rxioclkp => rxioclkp,
rxioclkn => rxioclkn,
rxserdesstrobe => rx_serdesstrobe,
gclk => rx_bufg_x1,
bitslip => bslip,
reset => rst,
data_out => rxd,
debug_in => "00",
debug => open);
process (rx_bufg_x1, rst) -- example bitslip logic, if required
begin
if rst = '1' then
state <= '0' ;
bslip <= '1' ;
count <= "0000" ;
elsif rx_bufg_x1'event and rx_bufg_x1 = '1' then
if state = '0' then
if rxd(63 downto 60) /= "0011" then
bslip <= '1' ; -- bitslip needed
state <= '1' ;
count <= "0000" ;
end if ;
elsif state = '1' then
bslip <= '0' ; -- bitslip low
count <= count + 1 ;
if count = "1111" then
state <= '0' ;
end if ;
end if ;
end if ;
end process ;
process (rx_bufg_x1) -- process received data
begin
if rx_bufg_x1'event and rx_bufg_x1 = '1' then
rxr <= rxd ;
end if ;
end process ;
end arch_top_nto1_ddr_diff_rx ;
|
apache-2.0
|
5687ed4a6e983eacab2279f06be79514
| 0.605414 | 3.389502 | false | false | false | false |
Given-Jiang/Gray_Binarization
|
Gray_Binarization_dspbuilder/hdl/Gray_Binarization_GN.vhd
| 2 | 10,796 |
-- Gray_Binarization_GN.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.11:20:48
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Gray_Binarization_GN is
port (
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset_n
Avalon_ST_Sink_valid : in std_logic := '0'; -- Avalon_ST_Sink_valid.wire
Avalon_ST_Source_data : out std_logic_vector(23 downto 0); -- Avalon_ST_Source_data.wire
Avalon_MM_Slave_address : in std_logic_vector(1 downto 0) := (others => '0'); -- Avalon_MM_Slave_address.wire
Avalon_ST_Source_valid : out std_logic; -- Avalon_ST_Source_valid.wire
Avalon_ST_Sink_startofpacket : in std_logic := '0'; -- Avalon_ST_Sink_startofpacket.wire
Avalon_ST_Source_endofpacket : out std_logic; -- Avalon_ST_Source_endofpacket.wire
Avalon_ST_Sink_ready : out std_logic; -- Avalon_ST_Sink_ready.wire
Avalon_ST_Source_startofpacket : out std_logic; -- Avalon_ST_Source_startofpacket.wire
Avalon_MM_Slave_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- Avalon_MM_Slave_writedata.wire
Avalon_MM_Slave_write : in std_logic := '0'; -- Avalon_MM_Slave_write.wire
Avalon_ST_Sink_endofpacket : in std_logic := '0'; -- Avalon_ST_Sink_endofpacket.wire
Avalon_ST_Source_ready : in std_logic := '0'; -- Avalon_ST_Source_ready.wire
Avalon_ST_Sink_data : in std_logic_vector(23 downto 0) := (others => '0') -- Avalon_ST_Sink_data.wire
);
end entity Gray_Binarization_GN;
architecture rtl of Gray_Binarization_GN is
component alt_dspbuilder_clock_GNF343OQUJ is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNF343OQUJ;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component alt_dspbuilder_port_GN6TDLHAW6 is
port (
input : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(1 downto 0) -- wire
);
end component alt_dspbuilder_port_GN6TDLHAW6;
component alt_dspbuilder_port_GNEPKLLZKY is
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(31 downto 0) -- wire
);
end component alt_dspbuilder_port_GNEPKLLZKY;
component Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module is
port (
data_out : out std_logic_vector(23 downto 0); -- wire
write : in std_logic := 'X'; -- wire
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
data_in : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
sop : in std_logic := 'X'; -- wire
addr : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire
eop : in std_logic := 'X'; -- wire
Clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X' -- reset
);
end component Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module;
signal avalon_st_sink_valid_0_output_wire : std_logic; -- Avalon_ST_Sink_valid_0:output -> Avalon_ST_Source_valid_0:input
signal avalon_st_sink_startofpacket_0_output_wire : std_logic; -- Avalon_ST_Sink_startofpacket_0:output -> [Avalon_ST_Source_startofpacket_0:input, Gray_Binarization_Gray_Binarization_Module_0:sop]
signal avalon_st_sink_endofpacket_0_output_wire : std_logic; -- Avalon_ST_Sink_endofpacket_0:output -> [Avalon_ST_Source_endofpacket_0:input, Gray_Binarization_Gray_Binarization_Module_0:eop]
signal avalon_st_source_ready_0_output_wire : std_logic; -- Avalon_ST_Source_ready_0:output -> Avalon_ST_Sink_ready_0:input
signal avalon_mm_slave_address_0_output_wire : std_logic_vector(1 downto 0); -- Avalon_MM_Slave_address_0:output -> Gray_Binarization_Gray_Binarization_Module_0:addr
signal avalon_mm_slave_write_0_output_wire : std_logic; -- Avalon_MM_Slave_write_0:output -> Gray_Binarization_Gray_Binarization_Module_0:write
signal avalon_mm_slave_writedata_0_output_wire : std_logic_vector(31 downto 0); -- Avalon_MM_Slave_writedata_0:output -> Gray_Binarization_Gray_Binarization_Module_0:writedata
signal avalon_st_sink_data_0_output_wire : std_logic_vector(23 downto 0); -- Avalon_ST_Sink_data_0:output -> Gray_Binarization_Gray_Binarization_Module_0:data_in
signal gray_binarization_gray_binarization_module_0_data_out_wire : std_logic_vector(23 downto 0); -- Gray_Binarization_Gray_Binarization_Module_0:data_out -> Avalon_ST_Source_data_0:input
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> Gray_Binarization_Gray_Binarization_Module_0:aclr
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> Gray_Binarization_Gray_Binarization_Module_0:Clock
begin
clock_0 : component alt_dspbuilder_clock_GNF343OQUJ
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr_n => aclr -- .reset_n
);
avalon_st_sink_data_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => Avalon_ST_Sink_data, -- input.wire
output => avalon_st_sink_data_0_output_wire -- output.wire
);
avalon_st_sink_endofpacket_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => Avalon_ST_Sink_endofpacket, -- input.wire
output => avalon_st_sink_endofpacket_0_output_wire -- output.wire
);
avalon_mm_slave_address_0 : component alt_dspbuilder_port_GN6TDLHAW6
port map (
input => Avalon_MM_Slave_address, -- input.wire
output => avalon_mm_slave_address_0_output_wire -- output.wire
);
avalon_mm_slave_writedata_0 : component alt_dspbuilder_port_GNEPKLLZKY
port map (
input => Avalon_MM_Slave_writedata, -- input.wire
output => avalon_mm_slave_writedata_0_output_wire -- output.wire
);
avalon_st_source_valid_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => avalon_st_sink_valid_0_output_wire, -- input.wire
output => Avalon_ST_Source_valid -- output.wire
);
avalon_st_sink_valid_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => Avalon_ST_Sink_valid, -- input.wire
output => avalon_st_sink_valid_0_output_wire -- output.wire
);
avalon_st_source_endofpacket_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => avalon_st_sink_endofpacket_0_output_wire, -- input.wire
output => Avalon_ST_Source_endofpacket -- output.wire
);
avalon_st_source_startofpacket_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => avalon_st_sink_startofpacket_0_output_wire, -- input.wire
output => Avalon_ST_Source_startofpacket -- output.wire
);
gray_binarization_gray_binarization_module_0 : component Gray_Binarization_GN_Gray_Binarization_Gray_Binarization_Module
port map (
data_out => gray_binarization_gray_binarization_module_0_data_out_wire, -- data_out.wire
write => avalon_mm_slave_write_0_output_wire, -- write.wire
writedata => avalon_mm_slave_writedata_0_output_wire, -- writedata.wire
data_in => avalon_st_sink_data_0_output_wire, -- data_in.wire
sop => avalon_st_sink_startofpacket_0_output_wire, -- sop.wire
addr => avalon_mm_slave_address_0_output_wire, -- addr.wire
eop => avalon_st_sink_endofpacket_0_output_wire, -- eop.wire
Clock => clock_0_clock_output_clk, -- Clock.clk
aclr => clock_0_clock_output_reset -- .reset
);
avalon_st_source_ready_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => Avalon_ST_Source_ready, -- input.wire
output => avalon_st_source_ready_0_output_wire -- output.wire
);
avalon_mm_slave_write_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => Avalon_MM_Slave_write, -- input.wire
output => avalon_mm_slave_write_0_output_wire -- output.wire
);
avalon_st_sink_ready_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => avalon_st_source_ready_0_output_wire, -- input.wire
output => Avalon_ST_Sink_ready -- output.wire
);
avalon_st_sink_startofpacket_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => Avalon_ST_Sink_startofpacket, -- input.wire
output => avalon_st_sink_startofpacket_0_output_wire -- output.wire
);
avalon_st_source_data_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => gray_binarization_gray_binarization_module_0_data_out_wire, -- input.wire
output => Avalon_ST_Source_data -- output.wire
);
end architecture rtl; -- of Gray_Binarization_GN
|
mit
|
2b014e8224b1761430904e9fe3aba81d
| 0.575398 | 3.485954 | false | false | false | false |
VladisM/MARK_II
|
VHDL/src/timer/timer.vhd
| 1 | 4,324 |
-- Simple 16bit Timer with prescaler
--
-- Part of MARK II project. For informations about license, please
-- see file /LICENSE .
--
-- author: Vladislav Mlejnecký
-- email: [email protected]
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity timer is
generic(
BASE_ADDRESS: unsigned(23 downto 0) := x"000000" --base address
);
port(
--bus
clk: in std_logic;
res: in std_logic;
address: in std_logic_vector(23 downto 0);
data_mosi: in std_logic_vector(31 downto 0);
data_miso: out std_logic_vector(31 downto 0);
WR: in std_logic;
RD: in std_logic;
ack: out std_logic;
--device
intrq: out std_logic
);
end entity timer;
architecture timer_arch of timer is
signal compare_match, clear_from_write: std_logic;
signal counter: std_logic_vector(15 downto 0);
--control_reg
signal timeren, intrqen: std_logic;
signal prescaler_sel: std_logic_vector(2 downto 0);
signal set_val: std_logic_vector(15 downto 0);
signal control_reg: std_logic_vector(31 downto 0) := (others => '0');
-- signals for prescaler
signal enclk2, enclk4, enclk8, enclk16, clk_en: std_logic := '0';
-- bus interface signals
signal reg_sel: std_logic_vector(1 downto 0);
begin
--internal counter
process (clk) is
variable cnt: unsigned(15 downto 0) := (others => '0');
begin
if(rising_edge(clk)) then
if (res = '1' or clear_from_write = '1' or compare_match = '1') then
cnt := (others => '0');
elsif(timeren = '1' and clk_en = '1') then
cnt := cnt + 1;
end if;
end if;
counter <= std_logic_vector(cnt);
end process;
--comparator
process(counter, set_val) is
begin
if counter = set_val then
compare_match <= '1';
else
compare_match <= '0';
end if;
end process;
intrq <= intrqen and compare_match;
set_val <= control_reg(15 downto 0);
timeren <= control_reg(16);
intrqen <= control_reg(17);
prescaler_sel <= control_reg(20 downto 18);
--clk divider/prescaler
process(clk) is
variable var: unsigned(3 downto 0);
begin
if falling_edge(clk) then
if res = '1' then
var := "0000";
else
var := var + 1;
end if;
end if;
enclk2 <= var(0);
enclk4 <= var(0) and var(1);
enclk8 <= var(0) and var(1) and var(2);
enclk16 <= var(0) and var(1) and var(2) and var(3);
end process;
process(prescaler_sel, enclk2, enclk4, enclk8, enclk16) is
begin
case prescaler_sel is
when "000" => clk_en <= '1';
when "001" => clk_en <= enclk2;
when "010" => clk_en <= enclk4;
when "011" => clk_en <= enclk8;
when others => clk_en <= enclk16;
end case;
end process;
-----------------
--bus interface
--chip select
process(address) is begin
if (unsigned(address) = BASE_ADDRESS) then
reg_sel <= "01"; -- control register
elsif (unsigned(address) = (BASE_ADDRESS + 1)) then
reg_sel <= "10"; -- counter
else
reg_sel <= "00";
end if;
end process;
--registers
process(clk, res, WR, data_mosi, reg_sel) is begin
if rising_edge(clk) then
if res = '1' then
control_reg <= (others => '0');
elsif (reg_sel = "01" and WR = '1') then
control_reg <= data_mosi(31 downto 0);
end if;
end if;
end process;
--output from registers
data_miso <= control_reg when (RD = '1' and reg_sel = "01") else
x"0000" & counter when (RD = '1' and reg_sel = "10") else (others => 'Z');
--generate signal when there is write acces to counter
process(WR, reg_sel) is begin
if(WR = '1' and reg_sel = "10") then
clear_from_write <= '1';
else
clear_from_write <= '0';
end if;
end process;
ack <= '1' when ((WR = '1' and reg_sel /= "00") or (RD = '1' and reg_sel /= "00")) else '0';
end architecture timer_arch;
|
mit
|
55766ec6a79a0d78bf1c82d6dbef11ba
| 0.536664 | 3.626678 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/dbe_bpm_fmc130m_4ch_pcie.vhd
| 1 | 83,910 |
------------------------------------------------------------------------------
-- Title : Top FMC516 design
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-09-26
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Top design for testing the integration/control between pcie and
-- the crossbar
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-09-26 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Memory core generator
use work.gencores_pkg.all;
-- Custom Wishbone Modules
use work.ifc_wishbone_pkg.all;
-- Wishbone stream modules and interface
use work.wb_stream_generic_pkg.all;
-- Ethernet MAC Modules and SDB structure
use work.ethmac_pkg.all;
-- Wishbone Fabric interface
use work.wr_fabric_pkg.all;
-- Etherbone slave core
use work.etherbone_pkg.all;
-- FMC516 definitions
use work.fmc_adc_pkg.all;
-- Data Acquisition core
use work.acq_core_pkg.all;
-- PCIe Core
use work.bpm_pcie_ml605_pkg.all;
use work.bpm_pcie_ml605_priv_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity dbe_bpm_fmc130m_4ch_pcie is
generic(
-- PCIe Lanes
g_pcieLanes : integer := 4;
-- PCIE Constants. TEMPORARY!
constant pcieLanes : integer := 4;
constant DDR_DQ_WIDTH : integer := 64;
constant DDR_PAYLOAD_WIDTH : integer := 256;
constant DDR_DQS_WIDTH : integer := 8;
constant DDR_DM_WIDTH : integer := 8;
constant DDR_ROW_WIDTH : integer := 14;
constant DDR_BANK_WIDTH : integer := 3;
constant DDR_CK_WIDTH : integer := 1;
constant DDR_CKE_WIDTH : integer := 1;
constant DDR_ODT_WIDTH : integer := 1
);
port(
-----------------------------------------
-- Clocking pins
-----------------------------------------
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
-----------------------------------------
-- Reset Button
-----------------------------------------
sys_rst_button_i : in std_logic;
-----------------------------------------
-- UART pins
-----------------------------------------
rs232_txd_o : out std_logic;
rs232_rxd_i : in std_logic;
-----------------------------------------
-- PHY pins
-----------------------------------------
-- Clock and resets to PHY (GMII). Not used in MII mode (10/100)
mgtx_clk_o : out std_logic;
mrstn_o : out std_logic;
-- PHY TX
mtx_clk_pad_i : in std_logic;
mtxd_pad_o : out std_logic_vector(3 downto 0);
mtxen_pad_o : out std_logic;
mtxerr_pad_o : out std_logic;
-- PHY RX
mrx_clk_pad_i : in std_logic;
mrxd_pad_i : in std_logic_vector(3 downto 0);
mrxdv_pad_i : in std_logic;
mrxerr_pad_i : in std_logic;
mcoll_pad_i : in std_logic;
mcrs_pad_i : in std_logic;
-- MII
mdc_pad_o : out std_logic;
md_pad_b : inout std_logic;
-----------------------------
-- FMC130m_4ch ports
-----------------------------
-- ADC LTC2208 interface
fmc_adc_pga_o : out std_logic;
fmc_adc_shdn_o : out std_logic;
fmc_adc_dith_o : out std_logic;
fmc_adc_rand_o : out std_logic;
-- ADC0 LTC2208
fmc_adc0_clk_i : in std_logic;
fmc_adc0_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0);
fmc_adc0_of_i : in std_logic; -- Unused
-- ADC1 LTC2208
fmc_adc1_clk_i : in std_logic;
fmc_adc1_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0);
fmc_adc1_of_i : in std_logic; -- Unused
-- ADC2 LTC2208
fmc_adc2_clk_i : in std_logic;
fmc_adc2_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0);
fmc_adc2_of_i : in std_logic; -- Unused
-- ADC3 LTC2208
fmc_adc3_clk_i : in std_logic;
fmc_adc3_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0);
fmc_adc3_of_i : in std_logic; -- Unused
-- FMC General Status
fmc_prsnt_i : in std_logic;
fmc_pg_m2c_i : in std_logic;
--fmc_clk_dir_i : in std_logic;, -- not supported on Kintex7 KC705 board
-- Trigger
fmc_trig_dir_o : out std_logic;
fmc_trig_term_o : out std_logic;
fmc_trig_val_p_b : inout std_logic;
fmc_trig_val_n_b : inout std_logic;
-- Si571 clock gen
si571_scl_pad_b : inout std_logic;
si571_sda_pad_b : inout std_logic;
fmc_si571_oe_o : out std_logic;
-- AD9510 clock distribution PLL
spi_ad9510_cs_o : out std_logic;
spi_ad9510_sclk_o : out std_logic;
spi_ad9510_mosi_o : out std_logic;
spi_ad9510_miso_i : in std_logic;
fmc_pll_function_o : out std_logic;
fmc_pll_status_i : in std_logic;
-- AD9510 clock copy
fmc_fpga_clk_p_i : in std_logic;
fmc_fpga_clk_n_i : in std_logic;
-- Clock reference selection (TS3USB221)
fmc_clk_sel_o : out std_logic;
-- EEPROM
eeprom_scl_pad_b : inout std_logic;
eeprom_sda_pad_b : inout std_logic;
-- Temperature monitor
-- LM75AIMM
lm75_scl_pad_b : inout std_logic;
lm75_sda_pad_b : inout std_logic;
fmc_lm75_temp_alarm_i : in std_logic;
-- FMC LEDs
fmc_led1_o : out std_logic;
fmc_led2_o : out std_logic;
fmc_led3_o : out std_logic;
-----------------------------------------
-- General board status
-----------------------------------------
fmc_mmcm_lock_led_o : out std_logic;
fmc_pll_status_led_o : out std_logic;
-----------------------------------------
-- PCIe pins
-----------------------------------------
-- DDR3 memory pins
ddr3_dq_b : inout std_logic_vector(DDR_DQ_WIDTH-1 downto 0);
ddr3_dqs_p_b : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0);
ddr3_dqs_n_b : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0);
ddr3_addr_o : out std_logic_vector(DDR_ROW_WIDTH-1 downto 0);
ddr3_ba_o : out std_logic_vector(DDR_BANK_WIDTH-1 downto 0);
ddr3_cs_n_o : out std_logic_vector(0 downto 0);
ddr3_ras_n_o : out std_logic;
ddr3_cas_n_o : out std_logic;
ddr3_we_n_o : out std_logic;
ddr3_reset_n_o : out std_logic;
ddr3_ck_p_o : out std_logic_vector(DDR_CK_WIDTH-1 downto 0);
ddr3_ck_n_o : out std_logic_vector(DDR_CK_WIDTH-1 downto 0);
ddr3_cke_o : out std_logic_vector(DDR_CKE_WIDTH-1 downto 0);
ddr3_dm_o : out std_logic_vector(DDR_DM_WIDTH-1 downto 0);
ddr3_odt_o : out std_logic_vector(DDR_ODT_WIDTH-1 downto 0);
-- PCIe transceivers
pci_exp_rxp_i : in std_logic_vector(g_pcieLanes - 1 downto 0);
pci_exp_rxn_i : in std_logic_vector(g_pcieLanes - 1 downto 0);
pci_exp_txp_o : out std_logic_vector(g_pcieLanes - 1 downto 0);
pci_exp_txn_o : out std_logic_vector(g_pcieLanes - 1 downto 0);
-- PCI clock and reset signals
pcie_rst_n_i : in std_logic;
pcie_clk_p_i : in std_logic;
pcie_clk_n_i : in std_logic;
-----------------------------------------
-- Button pins
-----------------------------------------
--buttons_i : in std_logic_vector(7 downto 0);
-----------------------------------------
-- User LEDs
-----------------------------------------
-- Directional leds
--led_south_o : out std_logic;
--led_east_o : out std_logic;
--led_north_o : out std_logic;
-- GPIO leds
leds_o : out std_logic_vector(7 downto 0)
);
end dbe_bpm_fmc130m_4ch_pcie;
architecture rtl of dbe_bpm_fmc130m_4ch_pcie is
-- Top crossbar layout
-- Number of slaves
constant c_slaves : natural := 10;
-- General Dual-port memory, Buffer Single-port memory, DMA control port, MAC,
--Etherbone, FMC516, Peripherals
-- Number of masters
--constant c_masters : natural := 9; -- LM32 master, Data + Instruction,
--DMA read+write master, Ethernet MAC, Ethernet MAC adapter read+write master, Etherbone, RS232-Syscon
constant c_masters : natural := 8; -- RS232-Syscon,
--DMA read+write master, Ethernet MAC, Ethernet MAC adapter read+write master, Etherbone, PCIe
--constant c_dpram_size : natural := 131072/4; -- in 32-bit words (128KB)
constant c_dpram_size : natural := 90112/4; -- in 32-bit words (90KB)
--constant c_dpram_ethbuf_size : natural := 32768/4; -- in 32-bit words (32KB)
constant c_dpram_ethbuf_size : natural := 65536/4; -- in 32-bit words (64KB)
constant c_acq_fifo_size : natural := 256;
-- TEMPORARY! DON'T TOUCH!
--constant c_acq_data_width : natural := 64;
constant c_acq_addr_width : natural := 28;
constant c_acq_ddr_payload_width : natural := DDR_PAYLOAD_WIDTH; -- DDR3 UI (256 bits)
constant c_acq_ddr_addr_width : natural := 28;
constant c_acq_ddr_addr_res_width : natural := 32;
constant c_acq_ddr_addr_diff : natural := c_acq_ddr_addr_res_width-c_acq_ddr_addr_width;
constant c_acq_adc_id : natural := 0;
constant c_acq_tbt_id : natural := 1;
constant c_acq_fofb_id : natural := 2;
constant c_acq_monit_id : natural := 3;
constant c_acq_monit_1_id : natural := 4;
constant c_acq_num_channels : natural := 5; -- ADC + TBT + FOFB + MONIT + MONIT_1
constant c_acq_channels : t_acq_chan_param_array(c_acq_num_channels-1 downto 0) :=
( c_acq_adc_id => (width => to_unsigned(64, c_acq_chan_max_w_log2)),
c_acq_tbt_id => (width => to_unsigned(128, c_acq_chan_max_w_log2)),
c_acq_fofb_id => (width => to_unsigned(128, c_acq_chan_max_w_log2)),
c_acq_monit_id => (width => to_unsigned(128, c_acq_chan_max_w_log2)),
c_acq_monit_1_id => (width => to_unsigned(128, c_acq_chan_max_w_log2))
);
-- DDR3 constants
constant c_ddr_dq_width : natural := 64;
-- GPIO num pinscalc
constant c_leds_num_pins : natural := 8;
constant c_buttons_num_pins : natural := 8;
-- Counter width. It willl count up to 2^32 clock cycles
constant c_counter_width : natural := 32;
-- TICs counter period. 100MHz clock -> msec granularity
constant c_tics_cntr_period : natural := 100000;
-- Number of reset clock cycles (FF)
constant c_button_rst_width : natural := 255;
-- number of the ADC reference clock used for all downstream
-- FPGA logic
constant c_adc_ref_clk : natural := 1;
-- Number of top level clocks
constant c_num_tlvl_clks : natural := 2; -- CLK_SYS and CLK_200 MHz
constant c_clk_sys_id : natural := 0; -- CLK_SYS and CLK_200 MHz
constant c_clk_200mhz_id : natural := 1; -- CLK_SYS and CLK_200 MHz
constant c_xwb_etherbone_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", --32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"0000000000000651", -- GSI
device_id => x"68202b22",
version => x"00000001",
date => x"20120912",
name => "GSI_ETHERBONE_CFG ")));
constant c_xwb_ethmac_adapter_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", --32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"1000000000001215", -- LNLS
device_id => x"2ff9a28e",
version => x"00000001",
date => x"20130701",
name => "ETHMAC_ADAPTER ")));
-- FMC130m_4ch layout. Size (0x00000FFF) is larger than needed. Just to be sure
-- no address overlaps will occur
--constant c_fmc516_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000800");
-- FMC130m_4ch
constant c_fmc130m_4ch_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000800");
-- General peripherals layout. UART, LEDs (GPIO), Buttons (GPIO) and Tics counter
constant c_periph_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000400");
-- WB SDB (Self describing bus) layout
--constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) :=
-- ( 0 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"00000000"), -- 90KB RAM
-- 1 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"10000000"), -- Second port to the same memory
-- 2 => f_sdb_embed_device(f_xwb_dpram(c_dpram_ethbuf_size),
-- x"20000000"), -- 64KB RAM
-- 3 => f_sdb_embed_device(c_xwb_dma_sdb, x"30004000"), -- DMA control port
-- 4 => f_sdb_embed_device(c_xwb_ethmac_sdb, x"30005000"), -- Ethernet MAC control port
-- 5 => f_sdb_embed_device(c_xwb_ethmac_adapter_sdb, x"30006000"), -- Ethernet Adapter control port
-- 6 => f_sdb_embed_device(c_xwb_etherbone_sdb, x"30007000"), -- Etherbone control port
-- 7 => f_sdb_embed_bridge(c_fmc130m_4ch_bridge_sdb, x"30010000"), -- FMC130m_4ch control port
-- 8 => f_sdb_embed_bridge(c_periph_bridge_sdb, x"30020000"), -- General peripherals control port
-- 9 => f_sdb_embed_device(c_xwb_acq_core_sdb, x"30030000") -- Data Acquisition control port
-- );
-- Changed due to the limitation in PCIe addressing. Only up to 29 bits
constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) :=
( 0 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"00000000"), -- 90KB RAM
1 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"00100000"), -- Second port to the same memory
2 => f_sdb_embed_device(f_xwb_dpram(c_dpram_ethbuf_size),
x"00200000"), -- 64KB RAM
3 => f_sdb_embed_device(c_xwb_dma_sdb, x"00304000"), -- DMA control port
4 => f_sdb_embed_device(c_xwb_ethmac_sdb, x"00305000"), -- Ethernet MAC control port
5 => f_sdb_embed_device(c_xwb_ethmac_adapter_sdb, x"00306000"), -- Ethernet Adapter control port
6 => f_sdb_embed_device(c_xwb_etherbone_sdb, x"00307000"), -- Etherbone control port
7 => f_sdb_embed_bridge(c_fmc130m_4ch_bridge_sdb, x"00310000"), -- FMC130m_4ch control port
8 => f_sdb_embed_bridge(c_periph_bridge_sdb, x"00320000"), -- General peripherals control port
9 => f_sdb_embed_device(c_xwb_acq_core_sdb, x"00330000") -- Data Acquisition control port
);
-- Self Describing Bus ROM Address. It will be an addressed slave as well
constant c_sdb_address : t_wishbone_address := x"00300000";
-- Crossbar master/slave arrays
signal cbar_slave_i : t_wishbone_slave_in_array (c_masters-1 downto 0);
signal cbar_slave_o : t_wishbone_slave_out_array(c_masters-1 downto 0);
signal cbar_master_i : t_wishbone_master_in_array(c_slaves-1 downto 0);
signal cbar_master_o : t_wishbone_master_out_array(c_slaves-1 downto 0);
-- LM32 signals
signal clk_sys : std_logic;
signal lm32_interrupt : std_logic_vector(31 downto 0);
signal lm32_rstn : std_logic;
-- PCIe signals
signal wb_ma_pcie_ack_in : std_logic;
signal wb_ma_pcie_dat_in : std_logic_vector(63 downto 0);
signal wb_ma_pcie_addr_out : std_logic_vector(28 downto 0);
signal wb_ma_pcie_dat_out : std_logic_vector(63 downto 0);
signal wb_ma_pcie_we_out : std_logic;
signal wb_ma_pcie_stb_out : std_logic;
signal wb_ma_pcie_sel_out : std_logic;
signal wb_ma_pcie_cyc_out : std_logic;
signal wb_ma_pcie_rst : std_logic;
signal wb_ma_pcie_rstn : std_logic;
signal wb_ma_sladp_pcie_ack_in : std_logic;
signal wb_ma_sladp_pcie_dat_in : std_logic_vector(31 downto 0);
signal wb_ma_sladp_pcie_addr_out : std_logic_vector(31 downto 0);
signal wb_ma_sladp_pcie_dat_out : std_logic_vector(31 downto 0);
signal wb_ma_sladp_pcie_we_out : std_logic;
signal wb_ma_sladp_pcie_stb_out : std_logic;
signal wb_ma_sladp_pcie_sel_out : std_logic_vector(3 downto 0);
signal wb_ma_sladp_pcie_cyc_out : std_logic;
-- PCIe Debug signals
signal dbg_app_addr : std_logic_vector(31 downto 0);
signal dbg_app_cmd : std_logic_vector(2 downto 0);
signal dbg_app_en : std_logic;
signal dbg_app_wdf_data : std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
signal dbg_app_wdf_end : std_logic;
signal dbg_app_wdf_wren : std_logic;
signal dbg_app_wdf_mask : std_logic_vector(DDR_PAYLOAD_WIDTH/8-1 downto 0);
signal dbg_app_rd_data : std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
signal dbg_app_rd_data_end : std_logic;
signal dbg_app_rd_data_valid : std_logic;
signal dbg_app_rdy : std_logic;
signal dbg_app_wdf_rdy : std_logic;
signal dbg_ddr_ui_clk : std_logic;
signal dbg_ddr_ui_reset : std_logic;
signal dbg_arb_req : std_logic_vector(1 downto 0);
signal dbg_arb_gnt : std_logic_vector(1 downto 0);
-- To/From Acquisition Core
signal acq_chan_array : t_acq_chan_array(c_acq_num_channels-1 downto 0);
signal bpm_acq_dpram_dout : std_logic_vector(f_acq_chan_find_widest(c_acq_channels)-1 downto 0);
signal bpm_acq_dpram_valid : std_logic;
signal bpm_acq_ext_dout : std_logic_vector(f_acq_chan_find_widest(c_acq_channels)-1 downto 0);
signal bpm_acq_ext_valid : std_logic;
signal bpm_acq_ext_addr : std_logic_vector(c_acq_addr_width-1 downto 0);
signal bpm_acq_ext_sof : std_logic;
signal bpm_acq_ext_eof : std_logic;
signal bpm_acq_ext_dreq : std_logic;
signal bpm_acq_ext_stall : std_logic;
signal memc_ui_clk : std_logic;
signal memc_ui_rst : std_logic;
signal memc_ui_rstn : std_logic;
signal memc_cmd_rdy : std_logic;
signal memc_cmd_en : std_logic;
signal memc_cmd_instr : std_logic_vector(2 downto 0);
signal memc_cmd_addr_resized : std_logic_vector(c_acq_ddr_addr_res_width-1 downto 0);
signal memc_cmd_addr : std_logic_vector(c_acq_ddr_addr_width-1 downto 0);
signal memc_wr_en : std_logic;
signal memc_wr_end : std_logic;
signal memc_wr_mask : std_logic_vector(DDR_PAYLOAD_WIDTH/8-1 downto 0);
signal memc_wr_data : std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
signal memc_wr_rdy : std_logic;
signal memc_rd_data : std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
signal memc_rd_valid : std_logic;
signal dbg_ddr_rb_data : std_logic_vector(f_acq_chan_find_widest(c_acq_channels)-1 downto 0);
signal dbg_ddr_rb_addr : std_logic_vector(c_acq_addr_width-1 downto 0);
signal dbg_ddr_rb_valid : std_logic;
-- memory arbiter interface
signal memarb_acc_req : std_logic;
signal memarb_acc_gnt : std_logic;
-- Clocks and resets signals
signal locked : std_logic;
signal clk_sys_rstn : std_logic;
signal clk_sys_rst : std_logic;
signal clk_200mhz_rst : std_logic;
signal clk_200mhz_rstn : std_logic;
signal rst_button_sys_pp : std_logic;
signal rst_button_sys : std_logic;
signal rst_button_sys_n : std_logic;
signal rs232_rstn : std_logic;
-- Only one clock domain
signal reset_clks : std_logic_vector(c_num_tlvl_clks-1 downto 0);
signal reset_rstn : std_logic_vector(c_num_tlvl_clks-1 downto 0);
-- 200 Mhz clocck for iodelay_ctrl
signal clk_200mhz : std_logic;
-- Global Clock Single ended
signal sys_clk_gen : std_logic;
signal sys_clk_gen_bufg : std_logic;
-- Ethernet MAC signals
signal ethmac_int : std_logic;
signal ethmac_md_in : std_logic;
signal ethmac_md_out : std_logic;
signal ethmac_md_oe : std_logic;
signal mtxd_pad_int : std_logic_vector(3 downto 0);
signal mtxen_pad_int : std_logic;
signal mtxerr_pad_int : std_logic;
signal mdc_pad_int : std_logic;
-- Ethrnet MAC adapter signals
signal irq_rx_done : std_logic;
signal irq_tx_done : std_logic;
-- Etherbone signals
signal wb_ebone_out : t_wishbone_master_out;
signal wb_ebone_in : t_wishbone_master_in;
signal eb_src_i : t_wrf_source_in;
signal eb_src_o : t_wrf_source_out;
signal eb_snk_i : t_wrf_sink_in;
signal eb_snk_o : t_wrf_sink_out;
-- DMA signals
signal dma_int : std_logic;
-- FMC130m_4ch Signals
signal wbs_fmc130m_4ch_in_array : t_wbs_source_in16_array(c_num_adc_channels-1 downto 0);
signal wbs_fmc130m_4ch_out_array : t_wbs_source_out16_array(c_num_adc_channels-1 downto 0);
signal fmc_mmcm_lock_int : std_logic;
signal fmc_pll_status_int : std_logic;
signal fmc_led1_int : std_logic;
signal fmc_led2_int : std_logic;
signal fmc_led3_int : std_logic;
signal fmc_130m_4ch_clk : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc_130m_4ch_clk2x : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc_130m_4ch_data : std_logic_vector(c_num_adc_channels*c_num_adc_bits-1 downto 0);
signal fmc_130m_4ch_data_valid : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc_debug : std_logic;
signal reset_adc_counter : unsigned(6 downto 0) := (others => '0');
signal fmc_130m_4ch_rst_n : std_logic_vector(c_num_adc_channels-1 downto 0);
-- fmc130m_4ch Debug
signal fmc130m_4ch_debug_valid_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc130m_4ch_debug_full_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc130m_4ch_debug_empty_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal adc_dly_debug_int : t_adc_fn_dly_array(c_num_adc_channels-1 downto 0);
signal sys_spi_clk_int : std_logic;
--signal sys_spi_data_int : std_logic;
signal sys_spi_dout_int : std_logic;
signal sys_spi_din_int : std_logic;
signal sys_spi_miosio_oe_n_int : std_logic;
signal sys_spi_cs_adc0_n_int : std_logic;
signal sys_spi_cs_adc1_n_int : std_logic;
signal sys_spi_cs_adc2_n_int : std_logic;
signal sys_spi_cs_adc3_n_int : std_logic;
signal lmk_lock_int : std_logic;
signal lmk_sync_int : std_logic;
signal lmk_uwire_latch_en_int : std_logic;
signal lmk_uwire_data_int : std_logic;
signal lmk_uwire_clock_int : std_logic;
signal fmc_reset_adcs_n_int : std_logic;
signal fmc_reset_adcs_n_out : std_logic;
-- GPIO LED signals
signal gpio_slave_led_o : t_wishbone_slave_out;
signal gpio_slave_led_i : t_wishbone_slave_in;
signal gpio_leds_int : std_logic_vector(c_leds_num_pins-1 downto 0);
-- signal leds_gpio_dummy_in : std_logic_vector(c_leds_num_pins-1 downto 0);
-- GPIO Button signals
signal gpio_slave_button_o : t_wishbone_slave_out;
signal gpio_slave_button_i : t_wishbone_slave_in;
signal buttons_dummy : std_logic_vector(7 downto 0);
-- Counter signal
--signal s_counter : unsigned(c_counter_width-1 downto 0);
-- 100MHz period or 1 second
--constant s_counter_full : integer := 100000000;
-- Chipscope control signals
signal CONTROL0 : std_logic_vector(35 downto 0);
signal CONTROL1 : std_logic_vector(35 downto 0);
signal CONTROL2 : std_logic_vector(35 downto 0);
signal CONTROL3 : std_logic_vector(35 downto 0);
signal CONTROL4 : std_logic_vector(35 downto 0);
signal CONTROL5 : std_logic_vector(35 downto 0);
-- Chipscope ILA 0 signals
signal TRIG_ILA0_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_3 : std_logic_vector(31 downto 0);
-- Chipscope ILA 1 signals
signal TRIG_ILA1_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_3 : std_logic_vector(31 downto 0);
-- Chipscope ILA 2 signals
signal TRIG_ILA2_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA2_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA2_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA2_3 : std_logic_vector(31 downto 0);
-- Chipscope ILA 3 signals
signal TRIG_ILA3_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA3_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA3_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA3_3 : std_logic_vector(31 downto 0);
-- Chipscope ILA 4 signals
signal TRIG_ILA4_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA4_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA4_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA4_3 : std_logic_vector(31 downto 0);
-- Chipscope ILA 5 signals
signal TRIG_ILA5_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA5_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA5_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA5_3 : std_logic_vector(31 downto 0);
---------------------------
-- Components --
---------------------------
-- Clock generation
component clk_gen
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic;
sys_clk_bufg_o : out std_logic
);
end component;
-- Xilinx Megafunction
component sys_pll is
port(
rst_i : in std_logic := '0';
clk_i : in std_logic := '0';
clk0_o : out std_logic;
clk1_o : out std_logic;
locked_o : out std_logic
);
end component;
-- Xilinx Chipscope Controller
component chipscope_icon_1_port
port (
CONTROL0 : inout std_logic_vector(35 downto 0)
);
end component;
-- Xilinx Chipscope Controller 2 port
--component chipscope_icon_2_port
--port (
-- CONTROL0 : inout std_logic_vector(35 downto 0);
-- CONTROL1 : inout std_logic_vector(35 downto 0)
--);
--end component;
--component chipscope_icon_4_port
--port (
-- CONTROL0 : inout std_logic_vector(35 downto 0);
-- CONTROL1 : inout std_logic_vector(35 downto 0);
-- CONTROL2 : inout std_logic_vector(35 downto 0);
-- CONTROL3 : inout std_logic_vector(35 downto 0)
--);
--end component;
component chipscope_icon_6_port
port (
CONTROL0 : inout std_logic_vector(35 downto 0);
CONTROL1 : inout std_logic_vector(35 downto 0);
CONTROL2 : inout std_logic_vector(35 downto 0);
CONTROL3 : inout std_logic_vector(35 downto 0);
CONTROL4 : inout std_logic_vector(35 downto 0);
CONTROL5 : inout std_logic_vector(35 downto 0)
);
end component;
-- Xilinx Chipscope Logic Analyser
component chipscope_ila
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0)
);
end component;
-- Functions
-- Generate dummy (0) values
function f_zeros(size : integer)
return std_logic_vector is
begin
return std_logic_vector(to_unsigned(0, size));
end f_zeros;
begin
-- Clock generation
cmp_clk_gen : clk_gen
port map (
sys_clk_p_i => sys_clk_p_i,
sys_clk_n_i => sys_clk_n_i,
sys_clk_o => sys_clk_gen,
sys_clk_bufg_o => sys_clk_gen_bufg
);
-- Obtain core locking and generate necessary clocks
cmp_sys_pll_inst : sys_pll
port map (
rst_i => '0',
--clk_i => sys_clk_gen,
clk_i => sys_clk_gen_bufg,
clk0_o => clk_sys, -- 100MHz locked clock
clk1_o => clk_200mhz, -- 200MHz locked clock
locked_o => locked -- '1' when the PLL has locked
);
-- Reset synchronization. Hold reset line until few locked cycles have passed.
cmp_reset : gc_reset
generic map(
g_clocks => c_num_tlvl_clks -- CLK_SYS & CLK_200
)
port map(
--free_clk_i => sys_clk_gen,
free_clk_i => sys_clk_gen_bufg,
locked_i => locked,
clks_i => reset_clks,
rstn_o => reset_rstn
);
reset_clks(c_clk_sys_id) <= clk_sys;
reset_clks(c_clk_200mhz_id) <= clk_200mhz;
clk_sys_rstn <= reset_rstn(c_clk_sys_id) and rst_button_sys_n and
rs232_rstn and wb_ma_pcie_rstn;
clk_sys_rst <= not clk_sys_rstn;
mrstn_o <= clk_sys_rstn;
clk_200mhz_rstn <= reset_rstn(c_clk_200mhz_id);
clk_200mhz_rst <= not(reset_rstn(c_clk_200mhz_id));
-- Generate button reset synchronous to each clock domain
-- Detect button positive edge of clk_sys
cmp_button_sys_ffs : gc_sync_ffs
port map (
clk_i => clk_sys,
rst_n_i => '1',
data_i => sys_rst_button_i,
ppulse_o => rst_button_sys_pp
);
-- Generate the reset signal based on positive edge
-- of synched sys_rst_button_i
cmp_button_sys_rst : gc_extend_pulse
generic map (
g_width => c_button_rst_width
)
port map(
clk_i => clk_sys,
rst_n_i => '1',
pulse_i => rst_button_sys_pp,
extended_o => rst_button_sys
);
rst_button_sys_n <= not rst_button_sys;
-- The top-most Wishbone B.4 crossbar
cmp_interconnect : xwb_sdb_crossbar
generic map(
g_num_masters => c_masters,
g_num_slaves => c_slaves,
g_registered => true,
g_wraparound => true, -- Should be true for nested buses
g_layout => c_layout,
g_sdb_addr => c_sdb_address
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- Master connections (INTERCON is a slave)
slave_i => cbar_slave_i,
slave_o => cbar_slave_o,
-- Slave connections (INTERCON is a master)
master_i => cbar_master_i,
master_o => cbar_master_o
);
-- The LM32 is master 0+1
--lm32_rstn <= clk_sys_rstn;
--cmp_lm32 : xwb_lm32
--generic map(
-- g_profile => "medium_icache_debug"
--) -- Including JTAG and I-cache (no divide)
--port map(
-- clk_sys_i => clk_sys,
-- rst_n_i => lm32_rstn,
-- irq_i => lm32_interrupt,
-- dwb_o => cbar_slave_i(0), -- Data bus
-- dwb_i => cbar_slave_o(0),
-- iwb_o => cbar_slave_i(1), -- Instruction bus
-- iwb_i => cbar_slave_o(1)
--);
-- Interrupt '0' is Ethmac.
-- Interrupt '1' is DMA completion.
-- Interrupt '2' is Button(0).
-- Interrupt '3' is Ethernet Adapter RX completion.
-- Interrupt '4' is Ethernet Adapter TX completion.
-- Interrupts 31 downto 5 are disabled
--lm32_interrupt <= (0 => ethmac_int, 1 => dma_int, 2 => not buttons_i(0), 3 => irq_rx_done,
-- 4 => irq_tx_done, others => '0');
----------------------------------
-- PCIe Core --
----------------------------------
cmp_bpm_pcie_ml605 : bpm_pcie_ml605
generic map (
SIM_BYPASS_INIT_CAL => "OFF" -- Full calibration sequence
)
port map (
--DDR3 memory pins
ddr3_dq => ddr3_dq_b,
ddr3_dqs_p => ddr3_dqs_p_b,
ddr3_dqs_n => ddr3_dqs_n_b,
ddr3_addr => ddr3_addr_o,
ddr3_ba => ddr3_ba_o,
ddr3_cs_n => ddr3_cs_n_o,
ddr3_ras_n => ddr3_ras_n_o,
ddr3_cas_n => ddr3_cas_n_o,
ddr3_we_n => ddr3_we_n_o,
ddr3_reset_n => ddr3_reset_n_o,
ddr3_ck_p => ddr3_ck_p_o,
ddr3_ck_n => ddr3_ck_n_o,
ddr3_cke => ddr3_cke_o,
ddr3_dm => ddr3_dm_o,
ddr3_odt => ddr3_odt_o,
-- PCIe transceivers
pci_exp_rxp => pci_exp_rxp_i,
pci_exp_rxn => pci_exp_rxn_i,
pci_exp_txp => pci_exp_txp_o,
pci_exp_txn => pci_exp_txn_o,
-- Necessity signals
ddr_sys_clk_p => clk_200mhz, --200 MHz DDR core clock (connect through BUFG or PLL)
--ddr_sys_clk_p => sys_clk_gen_bufg, --200 MHz DDR core clock (connect through BUFG or PLL)
sys_clk_p => pcie_clk_p_i, --100 MHz PCIe Clock (connect directly to input pin)
sys_clk_n => pcie_clk_n_i, --100 MHz PCIe Clock
sys_rst_n => pcie_rst_n_i, -- PCIe core reset
-- DDR memory controller interface --
ddr_core_rst => wb_ma_pcie_rst,
memc_ui_clk => memc_ui_clk,
memc_ui_rst => memc_ui_rst,
memc_cmd_rdy => memc_cmd_rdy,
memc_cmd_en => memc_cmd_en,
memc_cmd_instr => memc_cmd_instr,
--memc_cmd_addr => memc_cmd_addr,
memc_cmd_addr => memc_cmd_addr_resized,
memc_wr_en => memc_wr_en,
memc_wr_end => memc_wr_end,
memc_wr_mask => memc_wr_mask,
memc_wr_data => memc_wr_data,
memc_wr_rdy => memc_wr_rdy,
memc_rd_data => memc_rd_data,
memc_rd_valid => memc_rd_valid,
-- memory arbiter interface
memarb_acc_req => memarb_acc_req,
memarb_acc_gnt => memarb_acc_gnt,
--/ DDR memory controller interface
-- Wishbone interface --
-- uncomment when instantiating in another project
clk_i => clk_sys,
rst_i => clk_sys_rst,
ack_i => wb_ma_pcie_ack_in,
dat_i => wb_ma_pcie_dat_in,
addr_o => wb_ma_pcie_addr_out,
dat_o => wb_ma_pcie_dat_out,
we_o => wb_ma_pcie_we_out,
stb_o => wb_ma_pcie_stb_out,
sel_o => wb_ma_pcie_sel_out,
cyc_o => wb_ma_pcie_cyc_out,
--/ Wishbone interface
-- Additional exported signals for instantiation
ext_rst_o => wb_ma_pcie_rst,
-- Debug signals
dbg_app_addr_o => dbg_app_addr,
dbg_app_cmd_o => dbg_app_cmd,
dbg_app_en_o => dbg_app_en,
dbg_app_wdf_data_o => dbg_app_wdf_data,
dbg_app_wdf_end_o => dbg_app_wdf_end,
dbg_app_wdf_wren_o => dbg_app_wdf_wren,
dbg_app_wdf_mask_o => dbg_app_wdf_mask,
dbg_app_rd_data_o => dbg_app_rd_data,
dbg_app_rd_data_end_o => dbg_app_rd_data_end,
dbg_app_rd_data_valid_o => dbg_app_rd_data_valid,
dbg_app_rdy_o => dbg_app_rdy,
dbg_app_wdf_rdy_o => dbg_app_wdf_rdy,
dbg_ddr_ui_clk_o => dbg_ddr_ui_clk,
dbg_ddr_ui_reset_o => dbg_ddr_ui_reset,
dbg_arb_req_o => dbg_arb_req,
dbg_arb_gnt_o => dbg_arb_gnt
);
wb_ma_pcie_rstn <= not(wb_ma_pcie_rst);
cmp_pcie_ma_iface_slave_adapter : wb_slave_adapter
generic map (
g_master_use_struct => true,
g_master_mode => PIPELINED,
g_master_granularity => WORD,
g_slave_use_struct => false,
g_slave_mode => CLASSIC,
g_slave_granularity => WORD
)
port map (
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
sl_adr_i => wb_ma_sladp_pcie_addr_out,
sl_dat_i => wb_ma_sladp_pcie_dat_out,
sl_sel_i => wb_ma_sladp_pcie_sel_out,
sl_cyc_i => wb_ma_sladp_pcie_cyc_out,
sl_stb_i => wb_ma_sladp_pcie_stb_out,
sl_we_i => wb_ma_sladp_pcie_we_out,
sl_dat_o => wb_ma_sladp_pcie_dat_in,
sl_ack_o => wb_ma_sladp_pcie_ack_in,
sl_stall_o => open,
sl_int_o => open,
sl_rty_o => open,
sl_err_o => open,
master_i => cbar_slave_o(0),
master_o => cbar_slave_i(0)
);
-- Connect PCIe to the Wishbone Crossbar
wb_ma_sladp_pcie_addr_out(wb_ma_sladp_pcie_addr_out'left downto wb_ma_pcie_addr_out'left+1)
<= (others => '0');
wb_ma_sladp_pcie_addr_out(wb_ma_pcie_addr_out'left downto 0)
<= wb_ma_pcie_addr_out;
wb_ma_sladp_pcie_dat_out <= wb_ma_pcie_dat_out(wb_ma_sladp_pcie_dat_out'left downto 0);
wb_ma_sladp_pcie_sel_out <= wb_ma_pcie_sel_out & wb_ma_pcie_sel_out &
wb_ma_pcie_sel_out & wb_ma_pcie_sel_out;
wb_ma_sladp_pcie_cyc_out <= wb_ma_pcie_cyc_out;
wb_ma_sladp_pcie_stb_out <= wb_ma_pcie_stb_out;
wb_ma_sladp_pcie_we_out <= wb_ma_pcie_we_out;
wb_ma_pcie_dat_in(wb_ma_pcie_dat_in'left downto wb_ma_sladp_pcie_dat_in'left+1)
<= (others => '0');
wb_ma_pcie_dat_in(wb_ma_sladp_pcie_dat_in'left downto 0)
<= wb_ma_sladp_pcie_dat_in;
wb_ma_pcie_ack_in <= wb_ma_sladp_pcie_ack_in;
cmp_xwb_rs232_syscon : xwb_rs232_syscon
generic map (
g_ma_interface_mode => PIPELINED,
g_ma_address_granularity => BYTE
)
port map(
-- WISHBONE common
wb_clk_i => clk_sys,
wb_rstn_i => '1', -- No need for resetting the controller
-- External ports
rs232_rxd_i => rs232_rxd_i,
rs232_txd_o => rs232_txd_o,
-- Reset to FPGA logic
rstn_o => rs232_rstn,
-- WISHBONE master
wb_master_i => cbar_slave_o(1),
wb_master_o => cbar_slave_i(1)
);
-- A DMA controller is master 2+3, slave 3, and interrupt 1
cmp_dma : xwb_dma
port map(
clk_i => clk_sys,
rst_n_i => clk_sys_rstn,
slave_i => cbar_master_o(3),
slave_o => cbar_master_i(3),
r_master_i => cbar_slave_o(2),
r_master_o => cbar_slave_i(2),
w_master_i => cbar_slave_o(3),
w_master_o => cbar_slave_i(3),
interrupt_o => dma_int
);
-- Slave 0+1 is the RAM. Load a input file containing the embedded software
cmp_ram : xwb_dpram
generic map(
g_size => c_dpram_size, -- must agree with sw/target/lm32/ram.ld:LENGTH / 4
--g_init_file => "../../../../embedded-sw/rampdata.ram", -- Ramp Data for testing PCIe
g_init_file => "",
--g_must_have_init_file => true,
g_must_have_init_file => false,
--g_slave1_interface_mode => PIPELINED,
--g_slave2_interface_mode => PIPELINED,
--g_slave1_granularity => BYTE,
--g_slave2_granularity => BYTE
g_slave1_interface_mode => CLASSIC,
g_slave2_interface_mode => CLASSIC,
g_slave1_granularity => WORD,
g_slave2_granularity => WORD
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- First port connected to the crossbar
slave1_i => cbar_master_o(0),
slave1_o => cbar_master_i(0),
-- Second port connected to the crossbar
slave2_i => cbar_master_o(1),
slave2_o => cbar_master_i(1)
);
-- Slave 2 is the RAM Buffer for Ethernet MAC.
cmp_ethmac_buf_ram : xwb_dpram
generic map(
g_size => c_dpram_ethbuf_size,
g_init_file => "",
g_must_have_init_file => false,
g_slave1_interface_mode => CLASSIC,
--g_slave2_interface_mode => PIPELINED,
g_slave1_granularity => BYTE
--g_slave2_granularity => BYTE
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- First port connected to the crossbar
slave1_i => cbar_master_o(2),
slave1_o => cbar_master_i(2),
-- Second port connected to the crossbar
slave2_i => cc_dummy_slave_in, -- CYC always low
slave2_o => open
);
-- The Ethernet MAC is master 4, slave 4
cmp_xwb_ethmac : xwb_ethmac
generic map (
--g_ma_interface_mode => PIPELINED,
g_ma_interface_mode => CLASSIC, -- NOT used for now
--g_ma_address_granularity => WORD,
g_ma_address_granularity => BYTE, -- NOT used for now
g_sl_interface_mode => PIPELINED,
--g_sl_interface_mode => CLASSIC,
--g_sl_address_granularity => WORD
g_sl_address_granularity => BYTE
)
port map(
-- WISHBONE common
wb_clk_i => clk_sys,
wb_rst_i => clk_sys_rst,
-- WISHBONE slave
wb_slave_in => cbar_master_o(4),
wb_slave_out => cbar_master_i(4),
-- WISHBONE master
wb_master_in => cbar_slave_o(4),
wb_master_out => cbar_slave_i(4),
-- PHY TX
mtx_clk_pad_i => mtx_clk_pad_i,
--mtxd_pad_o => mtxd_pad_o,
mtxd_pad_o => mtxd_pad_int,
--mtxen_pad_o => mtxen_pad_o,
mtxen_pad_o => mtxen_pad_int,
--mtxerr_pad_o => mtxerr_pad_o,
mtxerr_pad_o => mtxerr_pad_int,
-- PHY RX
mrx_clk_pad_i => mrx_clk_pad_i,
mrxd_pad_i => mrxd_pad_i,
mrxdv_pad_i => mrxdv_pad_i,
mrxerr_pad_i => mrxerr_pad_i,
mcoll_pad_i => mcoll_pad_i,
mcrs_pad_i => mcrs_pad_i,
-- MII
--mdc_pad_o => mdc_pad_o,
mdc_pad_o => mdc_pad_int,
md_pad_i => ethmac_md_in,
md_pad_o => ethmac_md_out,
md_padoe_o => ethmac_md_oe,
-- Interrupt
int_o => ethmac_int
);
-- Tri-state buffer for MII config
md_pad_b <= ethmac_md_out when ethmac_md_oe = '1' else 'Z';
ethmac_md_in <= md_pad_b;
mtxd_pad_o <= mtxd_pad_int;
mtxen_pad_o <= mtxen_pad_int;
mtxerr_pad_o <= mtxerr_pad_int;
mdc_pad_o <= mdc_pad_int;
-- The Ethernet MAC Adapter is master 5+6, slave 5
cmp_xwb_ethmac_adapter : xwb_ethmac_adapter
port map(
clk_i => clk_sys,
rstn_i => clk_sys_rstn,
wb_slave_o => cbar_master_i(5),
wb_slave_i => cbar_master_o(5),
tx_ram_o => cbar_slave_i(5),
tx_ram_i => cbar_slave_o(5),
rx_ram_o => cbar_slave_i(6),
rx_ram_i => cbar_slave_o(6),
rx_eb_o => eb_snk_i,
rx_eb_i => eb_snk_o,
tx_eb_o => eb_src_i,
tx_eb_i => eb_src_o,
irq_tx_done_o => irq_tx_done,
irq_rx_done_o => irq_rx_done
);
-- The Etherbone is slave 6
cmp_eb_slave_core : eb_slave_core
generic map(
g_sdb_address => x"00000000" & c_sdb_address
)
port map
(
clk_i => clk_sys,
nRst_i => clk_sys_rstn,
-- EB streaming sink
snk_i => eb_snk_i,
snk_o => eb_snk_o,
-- EB streaming source
src_i => eb_src_i,
src_o => eb_src_o,
-- WB slave - Cfg IF
cfg_slave_o => cbar_master_i(6),
cfg_slave_i => cbar_master_o(6),
-- WB master - Bus IF
master_o => wb_ebone_out,
master_i => wb_ebone_in
);
cbar_slave_i(7) <= wb_ebone_out;
wb_ebone_in <= cbar_slave_o(7);
-- The FMC130M_4CH is slave 7
cmp_xwb_fmc130m_4ch : xwb_fmc130m_4ch
generic map(
g_fpga_device => "VIRTEX6",
g_interface_mode => PIPELINED,
--g_address_granularity => WORD,
g_address_granularity => BYTE,
--g_adc_clk_period_values => default_adc_clk_period_values,
g_adc_clk_period_values => (8.88, 8.88, 8.88, 8.88),
--g_use_clk_chains => default_clk_use_chain,
-- using clock1 from fmc130m_4ch (CLK2_ M2C_P, CLK2_ M2C_M pair)
-- using clock0 from fmc130m_4ch.
-- BUFIO can drive half-bank only, not the full IO bank
g_use_clk_chains => "1111",
g_with_bufio_clk_chains => "0000",
g_with_bufr_clk_chains => "1111",
g_use_data_chains => "1111",
--g_map_clk_data_chains => (-1,-1,-1,-1),
-- Clock 1 is the adc reference clock
g_ref_clk => c_adc_ref_clk,
g_packet_size => 32,
g_sim => 0
)
port map(
sys_clk_i => clk_sys,
sys_rst_n_i => clk_sys_rstn,
sys_clk_200Mhz_i => clk_200mhz,
-----------------------------
-- Wishbone Control Interface signals
-----------------------------
wb_slv_i => cbar_master_o(7),
wb_slv_o => cbar_master_i(7),
-----------------------------
-- External ports
-----------------------------
-- ADC LTC2208 interface
fmc_adc_pga_o => fmc_adc_pga_o,
fmc_adc_shdn_o => fmc_adc_shdn_o,
fmc_adc_dith_o => fmc_adc_dith_o,
fmc_adc_rand_o => fmc_adc_rand_o,
-- ADC0 LTC2208
fmc_adc0_clk_i => fmc_adc0_clk_i,
fmc_adc0_data_i => fmc_adc0_data_i,
fmc_adc0_of_i => fmc_adc0_of_i,
-- ADC1 LTC2208
fmc_adc1_clk_i => fmc_adc1_clk_i,
fmc_adc1_data_i => fmc_adc1_data_i,
fmc_adc1_of_i => fmc_adc1_of_i,
-- ADC2 LTC2208
fmc_adc2_clk_i => fmc_adc2_clk_i,
fmc_adc2_data_i => fmc_adc2_data_i,
fmc_adc2_of_i => fmc_adc2_of_i,
-- ADC3 LTC2208
fmc_adc3_clk_i => fmc_adc3_clk_i,
fmc_adc3_data_i => fmc_adc3_data_i,
fmc_adc3_of_i => fmc_adc3_of_i,
-- FMC General Status
fmc_prsnt_i => fmc_prsnt_i,
fmc_pg_m2c_i => fmc_pg_m2c_i,
-- Trigger
fmc_trig_dir_o => fmc_trig_dir_o,
fmc_trig_term_o => fmc_trig_term_o,
fmc_trig_val_p_b => fmc_trig_val_p_b,
fmc_trig_val_n_b => fmc_trig_val_n_b,
-- Si571 clock gen
si571_scl_pad_b => si571_scl_pad_b,
si571_sda_pad_b => si571_sda_pad_b,
fmc_si571_oe_o => fmc_si571_oe_o,
-- AD9510 clock distribution PLL
spi_ad9510_cs_o => spi_ad9510_cs_o,
spi_ad9510_sclk_o => spi_ad9510_sclk_o,
spi_ad9510_mosi_o => spi_ad9510_mosi_o,
spi_ad9510_miso_i => spi_ad9510_miso_i,
fmc_pll_function_o => fmc_pll_function_o,
fmc_pll_status_i => fmc_pll_status_i,
-- AD9510 clock copy
fmc_fpga_clk_p_i => fmc_fpga_clk_p_i,
fmc_fpga_clk_n_i => fmc_fpga_clk_n_i,
-- Clock reference selection (TS3USB221)
fmc_clk_sel_o => fmc_clk_sel_o,
-- EEPROM
eeprom_scl_pad_b => eeprom_scl_pad_b,
eeprom_sda_pad_b => eeprom_sda_pad_b,
-- Temperature monitor
-- LM75AIMM
lm75_scl_pad_b => lm75_scl_pad_b,
lm75_sda_pad_b => lm75_sda_pad_b,
fmc_lm75_temp_alarm_i => fmc_lm75_temp_alarm_i,
-- FMC LEDs
fmc_led1_o => fmc_led1_int,
fmc_led2_o => fmc_led2_int,
fmc_led3_o => fmc_led3_int,
-----------------------------
-- Optional external reference clock ports
-----------------------------
fmc_ext_ref_clk_i => '0', -- Unused
fmc_ext_ref_clk2x_i => '0', -- Unused
fmc_ext_ref_mmcm_locked_i => '0', -- Unused
-----------------------------
-- ADC output signals. Continuous flow
-----------------------------
adc_clk_o => fmc_130m_4ch_clk,
adc_clk2x_o => fmc_130m_4ch_clk2x,
adc_rst_n_o => fmc_130m_4ch_rst_n,
adc_data_o => fmc_130m_4ch_data,
adc_data_valid_o => fmc_130m_4ch_data_valid,
-----------------------------
-- General ADC output signals and status
-----------------------------
-- Trigger to other FPGA logic
trig_hw_o => open,
trig_hw_i => '0',
-- General board status
fmc_mmcm_lock_o => fmc_mmcm_lock_int,
fmc_pll_status_o => fmc_pll_status_int,
-----------------------------
-- Wishbone Streaming Interface Source
-----------------------------
wbs_source_i => wbs_fmc130m_4ch_in_array,
wbs_source_o => wbs_fmc130m_4ch_out_array,
adc_dly_debug_o => adc_dly_debug_int,
fifo_debug_valid_o => fmc130m_4ch_debug_valid_int,
fifo_debug_full_o => fmc130m_4ch_debug_full_int,
fifo_debug_empty_o => fmc130m_4ch_debug_empty_int
);
gen_wbs_dummy_signals : for i in 0 to c_num_adc_channels-1 generate
wbs_fmc130m_4ch_in_array(i) <= cc_dummy_src_com_in;
end generate;
fmc_mmcm_lock_led_o <= fmc_mmcm_lock_int;
fmc_pll_status_led_o <= fmc_pll_status_int;
fmc_led1_o <= fmc_led1_int;
fmc_led2_o <= fmc_led2_int;
fmc_led3_o <= fmc_led3_int;
--led_south_o <= fmc_led1_int;
--led_east_o <= fmc_led2_int;
--led_north_o <= fmc_led3_int;
-- The board peripherals components is slave 8
cmp_xwb_dbe_periph : xwb_dbe_periph
generic map(
-- NOT used!
--g_interface_mode : t_wishbone_interface_mode := CLASSIC;
-- NOT used!
--g_address_granularity : t_wishbone_address_granularity := WORD;
g_cntr_period => c_tics_cntr_period,
g_num_leds => c_leds_num_pins,
g_num_buttons => c_buttons_num_pins
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- UART
uart_rxd_i => '0',
uart_txd_o => open,
-- LEDs
led_out_o => gpio_leds_int,
led_in_i => gpio_leds_int,
led_oen_o => open,
-- Buttons
button_out_o => open,
--button_in_i => buttons_i,
button_in_i => buttons_dummy,
button_oen_o => open,
-- Wishbone
slave_i => cbar_master_o(8),
slave_o => cbar_master_i(8)
);
leds_o <= gpio_leds_int;
acq_chan_array(c_acq_adc_id).val_low <= fmc_130m_4ch_data(63 downto 48) &
fmc_130m_4ch_data(47 downto 32) &
fmc_130m_4ch_data(31 downto 16) &
fmc_130m_4ch_data(15 downto 0);
acq_chan_array(c_acq_adc_id).val_high <= (others => '0');
acq_chan_array(c_acq_adc_id).dvalid <= fmc_130m_4ch_data_valid(c_adc_ref_clk);
acq_chan_array(c_acq_adc_id).trig <= '0';
acq_chan_array(c_acq_tbt_id).val_low <= fmc_130m_4ch_data(63 downto 48) &
fmc_130m_4ch_data(47 downto 32) &
fmc_130m_4ch_data(31 downto 16) &
fmc_130m_4ch_data(15 downto 0);
acq_chan_array(c_acq_tbt_id).val_high <= std_logic_vector(unsigned(fmc_130m_4ch_data(63 downto 48)) + 100) &
std_logic_vector(unsigned(fmc_130m_4ch_data(47 downto 32)) + 100) &
std_logic_vector(unsigned(fmc_130m_4ch_data(31 downto 16)) + 100) &
std_logic_vector(unsigned(fmc_130m_4ch_data(15 downto 0)) + 100);
acq_chan_array(c_acq_tbt_id).dvalid <= fmc_130m_4ch_data_valid(c_adc_ref_clk);
acq_chan_array(c_acq_tbt_id).trig <= '0';
acq_chan_array(c_acq_fofb_id).val_low <= fmc_130m_4ch_data(63 downto 48) &
fmc_130m_4ch_data(47 downto 32) &
fmc_130m_4ch_data(31 downto 16) &
fmc_130m_4ch_data(15 downto 0);
acq_chan_array(c_acq_fofb_id).val_high <= std_logic_vector(unsigned(fmc_130m_4ch_data(63 downto 48)) + 200) &
std_logic_vector(unsigned(fmc_130m_4ch_data(47 downto 32)) + 200) &
std_logic_vector(unsigned(fmc_130m_4ch_data(31 downto 16)) + 200) &
std_logic_vector(unsigned(fmc_130m_4ch_data(15 downto 0)) + 200) ;
acq_chan_array(c_acq_fofb_id).dvalid <= fmc_130m_4ch_data_valid(c_adc_ref_clk);
acq_chan_array(c_acq_fofb_id).trig <= '0';
acq_chan_array(c_acq_monit_id).val_low <= fmc_130m_4ch_data(63 downto 48) &
fmc_130m_4ch_data(47 downto 32) &
fmc_130m_4ch_data(31 downto 16) &
fmc_130m_4ch_data(15 downto 0);
acq_chan_array(c_acq_monit_id).val_high <= std_logic_vector(unsigned(fmc_130m_4ch_data(63 downto 48)) + 300) &
std_logic_vector(unsigned(fmc_130m_4ch_data(47 downto 32)) + 300) &
std_logic_vector(unsigned(fmc_130m_4ch_data(31 downto 16)) + 300) &
std_logic_vector(unsigned(fmc_130m_4ch_data(15 downto 0)) + 300) ;
acq_chan_array(c_acq_monit_id).dvalid <= fmc_130m_4ch_data_valid(c_adc_ref_clk);
acq_chan_array(c_acq_monit_id).trig <= '0';
acq_chan_array(c_acq_monit_1_id).val_low <= fmc_130m_4ch_data(63 downto 48) &
fmc_130m_4ch_data(47 downto 32) &
fmc_130m_4ch_data(31 downto 16) &
fmc_130m_4ch_data(15 downto 0);
acq_chan_array(c_acq_monit_1_id).val_high <= std_logic_vector(unsigned(fmc_130m_4ch_data(63 downto 48)) + 400) &
std_logic_vector(unsigned(fmc_130m_4ch_data(47 downto 32)) + 400) &
std_logic_vector(unsigned(fmc_130m_4ch_data(31 downto 16)) + 400) &
std_logic_vector(unsigned(fmc_130m_4ch_data(15 downto 0)) + 400) ;
acq_chan_array(c_acq_monit_1_id).dvalid <= fmc_130m_4ch_data_valid(c_adc_ref_clk);
acq_chan_array(c_acq_monit_1_id).trig <= '0';
-- The xwb_acq_core is slave 9
cmp_xwb_acq_core : xwb_acq_core
generic map
(
g_interface_mode => PIPELINED,
g_address_granularity => WORD,
g_acq_addr_width => c_acq_addr_width,
g_acq_num_channels => c_acq_num_channels,
g_acq_channels => c_acq_channels,
g_ddr_payload_width => c_acq_ddr_payload_width,
g_ddr_dq_width => c_ddr_dq_width,
g_ddr_addr_width => c_acq_ddr_addr_width,
--g_multishot_ram_size => 2048,
g_fifo_fc_size => c_acq_fifo_size -- avoid fifo overflow
--g_sim_readback => false
)
port map
(
-- assign to a better and shorter name
fs_clk_i => fmc_130m_4ch_clk(c_adc_ref_clk),
fs_ce_i => '1',
-- assign to a better and shorter name
fs_rst_n_i => fmc_130m_4ch_rst_n(c_adc_ref_clk),
sys_clk_i => clk_sys,
sys_rst_n_i => clk_sys_rstn,
-- From DDR3 Controller
ext_clk_i => memc_ui_clk,
ext_rst_n_i => memc_ui_rstn,
-----------------------------
-- Wishbone Control Interface signals
-----------------------------
wb_slv_i => cbar_master_o(9),
wb_slv_o => cbar_master_i(9),
-----------------------------
-- External Interface
-----------------------------
--data_i => fmc_130m_4ch_data, -- ch4 ch3 ch2 ch1
--dvalid_i => fmc_130m_4ch_data_valid(c_adc_ref_clk), -- Change this!!
--ext_trig_i => '0',
acq_chan_array_i => acq_chan_array,
-----------------------------
-- DRRAM Interface
-----------------------------
dpram_dout_o => bpm_acq_dpram_dout , -- to chipscope
dpram_valid_o => bpm_acq_dpram_valid, -- to chipscope
-----------------------------
-- External Interface (w/ FLow Control)
-----------------------------
ext_dout_o => bpm_acq_ext_dout, -- to chipscope
ext_valid_o => bpm_acq_ext_valid, -- to chipscope
ext_addr_o => bpm_acq_ext_addr, -- to chipscope
ext_sof_o => bpm_acq_ext_sof, -- to chipscope
ext_eof_o => bpm_acq_ext_eof, -- to chipscope
ext_dreq_o => bpm_acq_ext_dreq, -- to chipscope
ext_stall_o => bpm_acq_ext_stall, -- to chipscope
-----------------------------
-- DDR3 SDRAM Interface
-----------------------------
ui_app_addr_o => memc_cmd_addr,
ui_app_cmd_o => memc_cmd_instr,
ui_app_en_o => memc_cmd_en,
ui_app_rdy_i => memc_cmd_rdy,
ui_app_wdf_data_o => memc_wr_data,
ui_app_wdf_end_o => memc_wr_end,
ui_app_wdf_mask_o => memc_wr_mask,
ui_app_wdf_wren_o => memc_wr_en,
ui_app_wdf_rdy_i => memc_wr_rdy,
ui_app_rd_data_i => memc_rd_data, -- not used!
ui_app_rd_data_end_i => '0', -- not used!
ui_app_rd_data_valid_i => memc_rd_valid, -- not used!
-- DDR3 arbitrer for multiple accesses
ui_app_req_o => memarb_acc_req,
ui_app_gnt_i => memarb_acc_gnt,
-----------------------------
-- Debug Interface
-----------------------------
dbg_ddr_rb_data_o => dbg_ddr_rb_data,
dbg_ddr_rb_addr_o => dbg_ddr_rb_addr,
dbg_ddr_rb_valid_o => dbg_ddr_rb_valid
);
memc_ui_rstn <= not(memc_ui_rst);
memc_cmd_addr_resized <= f_gen_std_logic_vector(c_acq_ddr_addr_diff, '0') &
memc_cmd_addr;
-- Xilinx Chipscope
cmp_chipscope_icon_0 : chipscope_icon_6_port
port map (
CONTROL0 => CONTROL0,
CONTROL1 => CONTROL1,
CONTROL2 => CONTROL2,
CONTROL3 => CONTROL3,
CONTROL4 => CONTROL4,
CONTROL5 => CONTROL5
);
cmp_chipscope_ila_0_fmc130m_4ch_clk0 : chipscope_ila
port map (
CONTROL => CONTROL0,
CLK => fmc_130m_4ch_clk(c_adc_ref_clk),
TRIG0 => TRIG_ILA0_0,
TRIG1 => TRIG_ILA0_1,
TRIG2 => TRIG_ILA0_2,
TRIG3 => TRIG_ILA0_3
);
-- fmc130m_4ch WBS master output data
--TRIG_ILA0_0 <= wbs_fmc130m_4ch_out_array(3).dat &
-- wbs_fmc130m_4ch_out_array(2).dat;
TRIG_ILA0_0 <= fmc_130m_4ch_data(31 downto 16) &
fmc_130m_4ch_data(47 downto 32);
-- fmc130m_4ch WBS master output data
TRIG_ILA0_1(11 downto 0) <= adc_dly_debug_int(1).clk_chain.idelay.pulse &
adc_dly_debug_int(1).data_chain.idelay.pulse &
adc_dly_debug_int(1).clk_chain.idelay.val &
adc_dly_debug_int(1).data_chain.idelay.val;
TRIG_ILA0_1(31 downto 12) <= (others => '0');
-- fmc130m_4ch WBS master output control signals
TRIG_ILA0_2(17 downto 0) <= wbs_fmc130m_4ch_out_array(1).cyc &
wbs_fmc130m_4ch_out_array(1).stb &
wbs_fmc130m_4ch_out_array(1).adr &
wbs_fmc130m_4ch_out_array(1).sel &
wbs_fmc130m_4ch_out_array(1).we &
wbs_fmc130m_4ch_out_array(2).cyc &
wbs_fmc130m_4ch_out_array(2).stb &
wbs_fmc130m_4ch_out_array(2).adr &
wbs_fmc130m_4ch_out_array(2).sel &
wbs_fmc130m_4ch_out_array(2).we;
TRIG_ILA0_2(18) <= '0';
TRIG_ILA0_2(22 downto 19) <= fmc_130m_4ch_data_valid;
TRIG_ILA0_2(23) <= fmc_mmcm_lock_int;
TRIG_ILA0_2(24) <= fmc_pll_status_int;
TRIG_ILA0_2(25) <= fmc130m_4ch_debug_valid_int(1);
TRIG_ILA0_2(26) <= fmc130m_4ch_debug_full_int(1);
TRIG_ILA0_2(27) <= fmc130m_4ch_debug_empty_int(1);
TRIG_ILA0_2(31 downto 28) <= (others => '0');
TRIG_ILA0_3 <= (others => '0');
cmp_chipscope_ila_1_fmc130m_4ch_clk1 : chipscope_ila
port map (
CONTROL => CONTROL1,
--CLK => fmc_130m_4ch_clk(1),
CLK => fmc_130m_4ch_clk(c_adc_ref_clk),
TRIG0 => TRIG_ILA1_0,
TRIG1 => TRIG_ILA1_1,
TRIG2 => TRIG_ILA1_2,
TRIG3 => TRIG_ILA1_3
);
-- fmc130m_4ch WBS master output data
TRIG_ILA1_0 <= fmc_130m_4ch_data(15 downto 0) &
fmc_130m_4ch_data(63 downto 48);
-- fmc130m_4ch WBS master output data
TRIG_ILA1_1 <= (others => '0');
-- fmc130m_4ch WBS master output control signals
TRIG_ILA1_2(17 downto 0) <= wbs_fmc130m_4ch_out_array(0).cyc &
wbs_fmc130m_4ch_out_array(0).stb &
wbs_fmc130m_4ch_out_array(0).adr &
wbs_fmc130m_4ch_out_array(0).sel &
wbs_fmc130m_4ch_out_array(0).we &
wbs_fmc130m_4ch_out_array(3).cyc &
wbs_fmc130m_4ch_out_array(3).stb &
wbs_fmc130m_4ch_out_array(3).adr &
wbs_fmc130m_4ch_out_array(3).sel &
wbs_fmc130m_4ch_out_array(3).we;
TRIG_ILA1_2(18) <= '0';
TRIG_ILA1_2(22 downto 19) <= fmc_130m_4ch_data_valid;
TRIG_ILA1_2(23) <= fmc_mmcm_lock_int;
TRIG_ILA1_2(24) <= fmc_pll_status_int;
TRIG_ILA1_2(25) <= fmc130m_4ch_debug_valid_int(0);
TRIG_ILA1_2(26) <= fmc130m_4ch_debug_full_int(0);
TRIG_ILA1_2(27) <= fmc130m_4ch_debug_empty_int(0);
TRIG_ILA1_2(31 downto 28) <= (others => '0');
TRIG_ILA1_3 <= (others => '0');
cmp_chipscope_ila_2_ethmac_tx : chipscope_ila
port map (
CONTROL => CONTROL2,
CLK => mtx_clk_pad_i,
TRIG0 => TRIG_ILA2_0,
TRIG1 => TRIG_ILA2_1,
TRIG2 => TRIG_ILA2_2,
TRIG3 => TRIG_ILA2_3
);
TRIG_ILA2_0(5 downto 0) <= mtxd_pad_int &
mtxen_pad_int &
mtxerr_pad_int;
TRIG_ILA2_0(31 downto 6) <= (others => '0');
TRIG_ILA2_1 <= (others => '0');
TRIG_ILA2_2 <= (others => '0');
TRIG_ILA2_3 <= (others => '0');
-- The clocks to/from peripherals are derived from the bus clock.
-- Therefore we don't have to worry about synchronization here, just
-- keep in mind that the data/ss lines will appear longer than normal
cmp_chipscope_ila_3_fmc130m_4ch_periph : chipscope_ila
port map (
CONTROL => CONTROL3,
CLK => clk_sys, -- Wishbone clock
TRIG0 => TRIG_ILA3_0,
TRIG1 => TRIG_ILA3_1,
TRIG2 => TRIG_ILA3_2,
TRIG3 => TRIG_ILA3_3
);
TRIG_ILA3_0 <= wb_ma_pcie_dat_in(31 downto 0);
TRIG_ILA3_1 <= wb_ma_pcie_dat_out(31 downto 0);
TRIG_ILA3_2(31 downto wb_ma_pcie_addr_out'left + 1) <= (others => '0');
TRIG_ILA3_2(wb_ma_pcie_addr_out'left downto 0)
<= wb_ma_pcie_addr_out(wb_ma_pcie_addr_out'left downto 0);
TRIG_ILA3_3(31 downto 5) <= (others => '0');
TRIG_ILA3_3(4 downto 0) <= wb_ma_pcie_ack_in &
wb_ma_pcie_we_out &
wb_ma_pcie_stb_out &
wb_ma_pcie_sel_out &
wb_ma_pcie_cyc_out;
cmp_chipscope_ila_4_bpm_acq : chipscope_ila
port map (
CONTROL => CONTROL4,
CLK => memc_ui_clk, -- DDR3 controller clk
TRIG0 => TRIG_ILA4_0,
TRIG1 => TRIG_ILA4_1,
TRIG2 => TRIG_ILA4_2,
TRIG3 => TRIG_ILA4_3
);
TRIG_ILA4_0 <= dbg_app_rd_data(207 downto 192) &
dbg_app_rd_data(143 downto 128);
TRIG_ILA4_1 <= dbg_app_rd_data(79 downto 64) &
dbg_app_rd_data(15 downto 0);
TRIG_ILA4_2 <= dbg_app_addr;
TRIG_ILA4_3(31 downto 11) <= (others => '0');
TRIG_ILA4_3(10 downto 0) <= dbg_app_rd_data_end &
dbg_app_rd_data_valid &
dbg_app_cmd & -- std_logic_vector(2 downto 0);
dbg_app_en &
dbg_app_rdy &
dbg_arb_req &
dbg_arb_gnt;
cmp_chipscope_ila_5_bpm_acq : chipscope_ila
port map (
CONTROL => CONTROL5,
CLK => memc_ui_clk, -- DDR3 controller clk
TRIG0 => TRIG_ILA5_0,
TRIG1 => TRIG_ILA5_1,
TRIG2 => TRIG_ILA5_2,
TRIG3 => TRIG_ILA5_3
);
TRIG_ILA5_0 <= dbg_app_wdf_data(207 downto 192) &
dbg_app_wdf_data(143 downto 128);
TRIG_ILA5_1 <= dbg_app_wdf_data(79 downto 64) &
dbg_app_wdf_data(15 downto 0);
TRIG_ILA5_2 <= dbg_app_addr;
TRIG_ILA5_3(31 downto 30) <= (others => '0');
TRIG_ILA5_3(29 downto 0) <= memc_ui_rst &
clk_200mhz_rstn &
dbg_app_cmd & -- std_logic_vector(2 downto 0);
dbg_app_en &
dbg_app_rdy &
dbg_app_wdf_end &
dbg_app_wdf_mask(15 downto 0) & -- std_logic_vector(31 downto 0);
dbg_app_wdf_wren &
dbg_app_wdf_rdy &
dbg_arb_req &
dbg_arb_gnt;
end rtl;
|
lgpl-3.0
|
1c82a40c610396d55b9f0f47af8136b7
| 0.421761 | 3.963441 | false | false | false | false |
mithro/soft-utmi
|
hdl/third_party/XAPP1064-serdes-macros/VHDL_Source/Macros/serdes_n_to_1_s16_diff.vhd
| 1 | 11,337 |
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: serdes_n_to_1_s16_diff.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: August 1 2008
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: D-bit generic n:1 transmitter module
-- Takes in n bits of data and serialises this to 1 bit
-- data is transmitted LSB first
-- Parallel input word
-- DS, DS-1 ..... 1, 0
-- Serial output words
-- Line0 : 0, ...... DS-(S+1)
-- Line1 : 1, ...... DS-(S+2)
-- Line(D-1) : . .
-- Line0(D) : D-1, ...... DS
-- Data inversion can be accomplished via the TX_SWAP_MASK parameter if required
--
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity serdes_n_to_1_s16_diff is generic (
S : integer := 10 ; -- Parameter to set the serdes factor 1..8
D : integer := 16) ; -- Set the number of inputs and outputs
port (
txioclk : in std_logic ; -- IO Clock network
txserdesstrobe : in std_logic ; -- Parallel data capture strobe
reset : in std_logic ; -- Reset
tx_bufg_pll_x2 : in std_logic ; -- Global clock
tx_bufg_pll_x1 : in std_logic ; -- Global clock
datain : in std_logic_vector((D*S)-1 downto 0) ; -- Data for output
clkin : in std_logic_vector(S-1 downto 0) ; -- Data for clock
dataout_p : out std_logic_vector(D-1 downto 0) ; -- output
dataout_n : out std_logic_vector(D-1 downto 0) ; -- output
clkout_p : out std_logic ; -- output
clkout_n : out std_logic) ; -- output
end serdes_n_to_1_s16_diff ;
architecture arch_serdes_n_to_1_s16_diff of serdes_n_to_1_s16_diff is
signal cascade_di : std_logic_vector(D-1 downto 0) ;
signal cascade_do : std_logic_vector(D-1 downto 0) ;
signal cascade_ti : std_logic_vector(D-1 downto 0) ;
signal cascade_to : std_logic_vector(D-1 downto 0) ;
signal mdatain : std_logic_vector(D*8 downto 0) ;
signal tx_data_out : std_logic_vector((D*S/2)-1 downto 0) ;
signal txd_int : std_logic_vector(D*S/2-1 downto 0) ;
signal tx_clk_int : std_logic_vector(7 downto 0) ;
signal old_tx_toggle : std_logic ;
signal tx_toggle : std_logic ;
signal tx_clk_out : std_logic ;
signal cascade_tci : std_logic ;
signal cascade_dci : std_logic ;
signal cascade_tco : std_logic ;
signal cascade_dco : std_logic ;
constant TX_SWAP_MASK : std_logic_vector(D-1 downto 0) := (others => '0') ; -- pinswap mask for input bits (0 = no swap (default), 1 = swap). Allows inputs to be connected the wrong way round to ease PCB routing.
begin
process (tx_bufg_pll_x1, reset)
begin
if reset = '1' then
tx_toggle <= '0' ;
elsif tx_bufg_pll_x1'event and tx_bufg_pll_x1 = '1' then
tx_toggle <= not tx_toggle after 1 pS; -- The 1 pS solves a simulation timing issue
end if ;
end process ;
process (tx_bufg_pll_x2)
begin
if tx_bufg_pll_x2'event and tx_bufg_pll_x2 = '1' then
old_tx_toggle <= tx_toggle ;
if tx_toggle /= old_tx_toggle then
txd_int <= datain((D*S/2)-1 downto 0) ;
tx_clk_int((S/2)-1 downto 0) <= clkin((S/2)-1 downto 0) ;
else
txd_int <= datain((D*S)-1 downto D*S/2) ;
tx_clk_int((S/2)-1 downto 0) <= clkin(S-1 downto S/2) ;
end if ;
end if ;
end process ;
io_clk_out : obufds port map (
O => clkout_p,
OB => clkout_n,
I => tx_clk_out);
loop0 : for i in 0 to (D - 1) generate
io_data_out : obufds port map (
O => dataout_p(i),
OB => dataout_n(i),
I => tx_data_out(i));
loop2 : for j in 0 to (S/2 - 1) generate
-- re-arrange data bits for transmission and invert lines as given by the mask
-- NOTE If pin inversion is required (non-zero SWAP MASK) then inverters will occur in fabric, as there are no inverters in the ISERDES2
-- This can be avoided by doing the inversion (if necessary) in the user logic
mdatain((8*i)+j) <= txd_int((i)+(D*j)) xor TX_SWAP_MASK(i) ;
end generate ;
oserdes_m : OSERDES2 generic map (
DATA_WIDTH => S/2, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE_OQ => "SDR", -- <SDR>, DDR
DATA_RATE_OT => "SDR", -- <SDR>, DDR
SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE
OUTPUT_MODE => "DIFFERENTIAL")
port map (
OQ => tx_data_out(i),
OCE => '1',
CLK0 => txioclk,
CLK1 => '0',
IOCE => txserdesstrobe,
RST => reset,
CLKDIV => tx_bufg_pll_x2,
D4 => mdatain((8*i)+7),
D3 => mdatain((8*i)+6),
D2 => mdatain((8*i)+5),
D1 => mdatain((8*i)+4),
TQ => open,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TRAIN => '0',
TCE => '1',
SHIFTIN1 => '1', -- Dummy input in Master
SHIFTIN2 => '1', -- Dummy input in Master
SHIFTIN3 => cascade_do(i), -- Cascade output D data from slave
SHIFTIN4 => cascade_to(i), -- Cascade output T data from slave
SHIFTOUT1 => cascade_di(i), -- Cascade input D data to slave
SHIFTOUT2 => cascade_ti(i), -- Cascade input T data to slave
SHIFTOUT3 => open, -- Dummy output in Master
SHIFTOUT4 => open) ; -- Dummy output in Master
oserdes_s : OSERDES2 generic map(
DATA_WIDTH => S/2, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE_OQ => "SDR", -- <SDR>, DDR
DATA_RATE_OT => "SDR", -- <SDR>, DDR
SERDES_MODE => "SLAVE", -- <DEFAULT>, MASTER, SLAVE
OUTPUT_MODE => "DIFFERENTIAL")
port map (
OQ => open,
OCE => '1',
CLK0 => txioclk,
CLK1 => '0',
IOCE => txserdesstrobe,
RST => reset,
CLKDIV => tx_bufg_pll_x2,
D4 => mdatain((8*i)+3),
D3 => mdatain((8*i)+2),
D2 => mdatain((8*i)+1),
D1 => mdatain((8*i)+0),
TQ => open,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TRAIN => '0',
TCE => '1',
SHIFTIN1 => cascade_di(i), -- Cascade input D from Master
SHIFTIN2 => cascade_ti(i), -- Cascade input T from Master
SHIFTIN3 => '1', -- Dummy input in Slave
SHIFTIN4 => '1', -- Dummy input in Slave
SHIFTOUT1 => open, -- Dummy output in Slave
SHIFTOUT2 => open, -- Dummy output in Slave
SHIFTOUT3 => cascade_do(i), -- Cascade output D data to Master
SHIFTOUT4 => cascade_to(i)) ; -- Cascade output T data to Master
end generate ;
oserdes_cm : OSERDES2 generic map (
DATA_WIDTH => S/2, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE_OQ => "SDR", -- <SDR>, DDR
DATA_RATE_OT => "SDR", -- <SDR>, DDR
SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE
OUTPUT_MODE => "DIFFERENTIAL")
port map (
OQ => tx_clk_out,
OCE => '1',
CLK0 => txioclk,
CLK1 => '0',
IOCE => txserdesstrobe,
RST => reset,
CLKDIV => tx_bufg_pll_x2,
D4 => tx_clk_int(7),
D3 => tx_clk_int(6),
D2 => tx_clk_int(5),
D1 => tx_clk_int(4),
TQ => open,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TRAIN => '0',
TCE => '1',
SHIFTIN1 => '1', -- Dummy input in Master
SHIFTIN2 => '1', -- Dummy input in Master
SHIFTIN3 => cascade_dco, -- Cascade output D data from slave
SHIFTIN4 => cascade_tco, -- Cascade output T data from slave
SHIFTOUT1 => cascade_dci, -- Cascade input D data to slave
SHIFTOUT2 => cascade_tci, -- Cascade input T data to slave
SHIFTOUT3 => open, -- Dummy output in Master
SHIFTOUT4 => open) ; -- Dummy output in Master
oserdes_cs : OSERDES2 generic map(
DATA_WIDTH => S/2, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE_OQ => "SDR", -- <SDR>, DDR
DATA_RATE_OT => "SDR", -- <SDR>, DDR
SERDES_MODE => "SLAVE", -- <DEFAULT>, MASTER, SLAVE
OUTPUT_MODE => "DIFFERENTIAL")
port map (
OQ => open,
OCE => '1',
CLK0 => txioclk,
CLK1 => '0',
IOCE => txserdesstrobe,
RST => reset,
CLKDIV => tx_bufg_pll_x2,
D4 => tx_clk_int(3),
D3 => tx_clk_int(2),
D2 => tx_clk_int(1),
D1 => tx_clk_int(0),
TQ => open,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TRAIN => '0',
TCE => '1',
SHIFTIN1 => cascade_dci, -- Cascade input D from Master
SHIFTIN2 => cascade_tci, -- Cascade input T from Master
SHIFTIN3 => '1', -- Dummy input in Slave
SHIFTIN4 => '1', -- Dummy input in Slave
SHIFTOUT1 => open, -- Dummy output in Slave
SHIFTOUT2 => open, -- Dummy output in Slave
SHIFTOUT3 => cascade_dco, -- Cascade output D data to Master
SHIFTOUT4 => cascade_tco) ; -- Cascade output T data to Master
end arch_serdes_n_to_1_s16_diff ;
|
apache-2.0
|
375af68b76c4a51e551429562d9034da
| 0.584811 | 2.923414 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/examples/mem/AsyncResetReg.vhd
| 1 | 606 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- .. hwt-autodoc::
--
ENTITY AsyncResetReg IS
PORT(
clk : IN STD_LOGIC;
din : IN STD_LOGIC;
dout : OUT STD_LOGIC;
rst : IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF AsyncResetReg IS
SIGNAL internReg : STD_LOGIC := '0';
BEGIN
dout <= internReg;
assig_process_internReg: PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
internReg <= '0';
ELSIF RISING_EDGE(clk) THEN
internReg <= din;
END IF;
END PROCESS;
END ARCHITECTURE;
|
mit
|
79a452cbb805f4f554494cfd4a53db14
| 0.574257 | 3.607143 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/examples/rtlLvl/SimpleWhile.vhd
| 1 | 1,227 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY SimpleWhile IS
PORT(
clk : IN STD_LOGIC;
en : IN STD_LOGIC;
rst : IN STD_LOGIC;
s_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
start : IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF SimpleWhile IS
CONSTANT boundary : STD_LOGIC_VECTOR(7 DOWNTO 0) := X"08";
SIGNAL counter : STD_LOGIC_VECTOR(7 DOWNTO 0) := X"00";
SIGNAL counter_next : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
assig_process_counter: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst = '1' THEN
counter <= X"00";
ELSE
counter <= counter_next;
END IF;
END IF;
END PROCESS;
assig_process_counter_next: PROCESS(counter, en, start)
VARIABLE tmpCastExpr_0 : UNSIGNED(7 DOWNTO 0);
BEGIN
tmpCastExpr_0 := UNSIGNED(counter) - UNSIGNED'(X"01");
IF start = '1' THEN
counter_next <= boundary;
ELSIF en = '1' THEN
counter_next <= STD_LOGIC_VECTOR(tmpCastExpr_0);
ELSE
counter_next <= counter;
END IF;
END PROCESS;
s_out <= counter;
END ARCHITECTURE;
|
mit
|
a21d455b3e390a599fc3c72bfdbb47fb
| 0.571312 | 3.810559 | false | false | false | false |
Jawanga/ece385final
|
finalproject/finalproject_inst.vhd
| 1 | 3,585 |
component finalproject is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
sdram_wire_addr : out std_logic_vector(12 downto 0); -- addr
sdram_wire_ba : out std_logic_vector(1 downto 0); -- ba
sdram_wire_cas_n : out std_logic; -- cas_n
sdram_wire_cke : out std_logic; -- cke
sdram_wire_cs_n : out std_logic; -- cs_n
sdram_wire_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- dq
sdram_wire_dqm : out std_logic_vector(3 downto 0); -- dqm
sdram_wire_ras_n : out std_logic; -- ras_n
sdram_wire_we_n : out std_logic; -- we_n
keycode_export : out std_logic_vector(7 downto 0); -- export
usb_DATA : inout std_logic_vector(15 downto 0) := (others => 'X'); -- DATA
usb_ADDR : out std_logic_vector(1 downto 0); -- ADDR
usb_RD_N : out std_logic; -- RD_N
usb_WR_N : out std_logic; -- WR_N
usb_CS_N : out std_logic; -- CS_N
usb_RST_N : out std_logic; -- RST_N
usb_INT : in std_logic := 'X'; -- INT
sdram_out_clk_clk : out std_logic; -- clk
usb_out_clk_clk : out std_logic -- clk
);
end component finalproject;
u0 : component finalproject
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
sdram_wire_addr => CONNECTED_TO_sdram_wire_addr, -- sdram_wire.addr
sdram_wire_ba => CONNECTED_TO_sdram_wire_ba, -- .ba
sdram_wire_cas_n => CONNECTED_TO_sdram_wire_cas_n, -- .cas_n
sdram_wire_cke => CONNECTED_TO_sdram_wire_cke, -- .cke
sdram_wire_cs_n => CONNECTED_TO_sdram_wire_cs_n, -- .cs_n
sdram_wire_dq => CONNECTED_TO_sdram_wire_dq, -- .dq
sdram_wire_dqm => CONNECTED_TO_sdram_wire_dqm, -- .dqm
sdram_wire_ras_n => CONNECTED_TO_sdram_wire_ras_n, -- .ras_n
sdram_wire_we_n => CONNECTED_TO_sdram_wire_we_n, -- .we_n
keycode_export => CONNECTED_TO_keycode_export, -- keycode.export
usb_DATA => CONNECTED_TO_usb_DATA, -- usb.DATA
usb_ADDR => CONNECTED_TO_usb_ADDR, -- .ADDR
usb_RD_N => CONNECTED_TO_usb_RD_N, -- .RD_N
usb_WR_N => CONNECTED_TO_usb_WR_N, -- .WR_N
usb_CS_N => CONNECTED_TO_usb_CS_N, -- .CS_N
usb_RST_N => CONNECTED_TO_usb_RST_N, -- .RST_N
usb_INT => CONNECTED_TO_usb_INT, -- .INT
sdram_out_clk_clk => CONNECTED_TO_sdram_out_clk_clk, -- sdram_out_clk.clk
usb_out_clk_clk => CONNECTED_TO_usb_out_clk_clk -- usb_out_clk.clk
);
|
apache-2.0
|
7083a2ac76dbc6263b34eee2922953a9
| 0.414226 | 3.473837 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/tests/serialization/AssignToASliceOfReg3d.vhd
| 1 | 1,763 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- Only a small fragment assigned and then whole signal assigned.
--
ENTITY AssignToASliceOfReg3d IS
PORT(
clk : IN STD_LOGIC;
data_in_addr : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
data_in_data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
data_in_mask : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
data_in_rd : OUT STD_LOGIC;
data_in_vld : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
rst_n : IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF AssignToASliceOfReg3d IS
SIGNAL r : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000000";
SIGNAL r_next : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL r_next_15downto8 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL r_next_31downto16 : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL r_next_7downto0 : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
data_in_rd <= '1';
data_out <= r;
assig_process_r: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst_n = '0' THEN
r <= X"00000000";
ELSE
r <= r_next;
END IF;
END IF;
END PROCESS;
r_next <= r_next_31downto16 & r_next_15downto8 & r_next_7downto0;
assig_process_r_next_15downto8: PROCESS(data_in_addr, data_in_data, r)
BEGIN
CASE data_in_addr IS
WHEN "01" =>
r_next_15downto8 <= data_in_data;
r_next_31downto16 <= r(31 DOWNTO 16);
r_next_7downto0 <= r(7 DOWNTO 0);
WHEN OTHERS =>
r_next_7downto0 <= X"7B";
r_next_15downto8 <= X"00";
r_next_31downto16 <= X"0000";
END CASE;
END PROCESS;
END ARCHITECTURE;
|
mit
|
14d0ebb25d87ea1ed7454e18afb2db3b
| 0.568349 | 3.332703 | false | false | false | false |
nanomolina/MIPS
|
prueba/alu.vhd
| 2 | 1,184 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity alu is
port( a,b : in std_logic_vector(31 downto 0);
alucontrol : in std_logic_vector(2 downto 0);
result : out std_logic_vector(31 downto 0);
zero: out std_logic
);
end alu;
architecture Behavioral of alu is
signal Reg : std_logic_vector(31 downto 0);
begin
process(alucontrol, a, b, Reg)
begin
case alucontrol is
when "000" => Reg <= a and b; --AND gate
when "001" => Reg <= a or b; --OR gate
when "010" => Reg <= a + b; --addition
when "100" => Reg <= a nand b; --NAND gate
when "101" => Reg <= a nor b; --NOR gate
when "110" => Reg <= a - b; --substraction
when "111" => if a < b then Reg <= (others => '1');
else Reg <= (others => '0'); --SLT
end if;
when others => Reg <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU";
end case;
result <= Reg;
if (Reg = x"00000000") then
zero <= '1';
elsif (Reg = x"FFFFFFFF") then
zero <= '0';
end if;
end process;
end Behavioral;
|
gpl-3.0
|
078dc7fb1a1c27244d66390e3ac2b721
| 0.535473 | 3.534328 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/modules/wb_position_calc/trigger2tag.vhd
| 1 | 3,930 |
------------------------------------------------------------------------------
-- Title : Trigger to Tag generator
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2019-04-01
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Generates a tag given a trigger
-------------------------------------------------------------------------------
-- Copyright (c) 2019 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2019-03-01 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity trigger2tag is
generic (
g_delay_width : natural := 9;
g_tag_size : natural := 1
);
port (
fs_clk_i : in std_logic;
fs_rst_n_i : in std_logic;
-- Pulse programmable delay
pulse_dly_i : in std_logic_vector(g_delay_width-1 downto 0);
-- Pulse input
pulse_i : in std_logic;
-- Output counter
tag_o : out std_logic
);
end trigger2tag;
architecture rtl of trigger2tag is
signal square : std_logic;
signal tag_dly : std_logic;
signal tag_out : std_logic;
attribute shreg_extract : string;
attribute shreg_extract of tag_out : signal is "no";
attribute keep : string;
attribute keep of tag_out : signal is "true";
component gc_shiftreg
generic (
g_size : integer
);
port (
clk_i : in std_logic;
en_i : in std_logic;
d_i : in std_logic;
q_o : out std_logic;
a_i : in std_logic_vector
);
end component;
component pulse2square
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Pulse input
pulse_i : in std_logic;
-- Clear square
clr_i : in std_logic;
-- square output
square_o : out std_logic
);
end component;
begin
cmp_tbt_tag_generate : pulse2square
port map
(
clk_i => fs_clk_i,
rst_n_i => fs_rst_n_i,
-- Pulse input
pulse_i => pulse_i,
-- Clear square
clr_i => '0',
-- square output
square_o => square
);
cmp_gc_shiftreg: gc_shiftreg
generic map (
g_size => 2**g_delay_width
)
port map (
clk_i => fs_clk_i,
en_i => '1',
d_i => square,
q_o => tag_dly,
a_i => pulse_dly_i
);
-- Additional ff for timing
p_output_reg : process(fs_clk_i)
begin
if rising_edge(fs_clk_i) then
if fs_rst_n_i = '0' then
tag_out <= '0';
else
tag_out <= tag_dly;
end if;
end if;
end process;
tag_o <= tag_out;
end rtl;
|
lgpl-3.0
|
ffff70703f084d965ba7b104d2c79a7c
| 0.356997 | 4.851852 | false | false | false | false |
mithro/soft-utmi
|
hdl/third_party/XAPP1064-serdes-macros/VHDL_Source/Top level examples/PLL/top_nto1_pll_diff_tx.vhd
| 1 | 7,413 |
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: top_nto1_pll_diff_tx
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: June 1 2009
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: Example differential output transmitter for clock and data using PLL
-- Serdes factor and number of data lines are set by constants in the code
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
--
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity top_nto1_pll_diff_tx is port (
refclkin_p, refclkin_n : in std_logic ; -- reference clock input
reset : in std_logic ; -- reset (active high)
clkout_p, clkout_n : out std_logic ; -- lvds clock output
dataout_p, dataout_n : out std_logic_vector(5 downto 0)) ; -- lvds data outputs
end top_nto1_pll_diff_tx ;
architecture arch_top_nto1_pll_diff_tx of top_nto1_pll_diff_tx is
component serdes_n_to_1_s8_diff is generic (
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
D : integer := 16) ; -- Set the number of inputs and outputs
port (
txioclk : in std_logic ; -- IO Clock network
txserdesstrobe : in std_logic ; -- Parallel data capture strobe
reset : in std_logic ; -- Reset
gclk : in std_logic ; -- Global clock
datain : in std_logic_vector((D*S)-1 downto 0) ; -- Data for output
dataout_p : out std_logic_vector(D-1 downto 0) ; -- output
dataout_n : out std_logic_vector(D-1 downto 0)) ; -- output
end component ;
component clock_generator_pll_s8_diff is generic (
PLLD : integer := 1 ; -- Parameter to set the division factor in the PLL
PLLX : integer := 8 ; -- Parameter to set the multiplication factor in the PLL
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
CLKIN_PERIOD : real := 6.000) ; -- clock period (ns) of input clock on clkin_p
port (
reset : in std_logic ; -- reset (active high)
clkin_p, clkin_n : in std_logic ; -- differential clock input
ioclk : out std_logic ; -- ioclock from BUFPLL
serdesstrobe : out std_logic ; -- serdes strobe from BUFPLL
gclk : out std_logic ; -- global clock output from BUFG x1
bufpll_lckd : out std_logic) ; -- Locked output from BUFPLL
end component ;
-- Parameters for serdes factor and number of IO pins
constant S : integer := 7 ; -- Set the serdes factor to be 7
constant D : integer := 6 ; -- Set the number of inputs and outputs to be 6
constant DS : integer := (D*S)-1 ; -- Used for bus widths = serdes factor * number of inputs - 1
signal tx_bufpll_lckd : std_logic ;
signal txd : std_logic_vector(DS downto 0) ;
signal tx_bufg_x1 : std_logic ;
signal rst : std_logic ;
signal tx_bufpll_clk_xn : std_logic ;
signal temp1p : std_logic_vector(0 downto 0) ;
signal temp1n : std_logic_vector(0 downto 0) ;
signal tx_serdesstrobe : std_logic ;
-- Parameters for pin swapping and clock generation
constant TX_CLK_GEN : std_logic_vector(S-1 downto 0) := "1100001" ; -- Transmit a constant to make a clock
begin
rst <= reset ; -- active high reset pin
-- Frequency Generator Clock Input
clkgen : clock_generator_pll_s8_diff generic map(
S => S,
PLLX => 7,
PLLD => 1,
CLKIN_PERIOD => 7.000)
port map (
reset => rst,
clkin_p => refclkin_p,
clkin_n => refclkin_n,
ioclk => tx_bufpll_clk_xn,
serdesstrobe => tx_serdesstrobe,
gclk => tx_bufg_x1,
bufpll_lckd => tx_bufpll_lckd) ;
process (tx_bufg_x1, rst) -- Generate some data to transmit
begin
if rst = '1' then
txd <= (0 => '1', others => '0') ;
elsif tx_bufg_x1'event and tx_bufg_x1 = '1' then
txd <= txd(40 downto 0) & txd(41) ;
end if ;
end process ;
-- Transmitter Logic - Instantiate serialiser to generate forwarded clock
clkout : serdes_n_to_1_s8_diff generic map (
S => S,
D => 1)
port map (
dataout_p => temp1p,
dataout_n => temp1n,
txioclk => tx_bufpll_clk_xn,
txserdesstrobe => tx_serdesstrobe,
gclk => tx_bufg_x1,
reset => rst,
datain => TX_CLK_GEN); -- Transmit a constant to make the clock
clkout_p <= temp1p(0) ;
clkout_n <= temp1n(0) ;
-- Instantiate Outputs and output serialisers for output data lines
dataout : serdes_n_to_1_s8_diff generic map(
S => S,
D => D)
port map (
dataout_p => dataout_p,
dataout_n => dataout_n,
txioclk => tx_bufpll_clk_xn,
txserdesstrobe => tx_serdesstrobe,
gclk => tx_bufg_x1,
reset => rst,
datain => txd);
end arch_top_nto1_pll_diff_tx ;
|
apache-2.0
|
aac3bdeebc5923d778010742341c2a1d
| 0.612168 | 3.438312 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/top/afc_v3/dbe_bpm2/dbe_bpm2.vhd
| 1 | 56,633 |
------------------------------------------------------------------------------
-- Title : Top FMC250M design
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2016-02-19
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Top design for testing the integration/control of the DSP with
-- FMC250M_4ch board
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-02-19 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- FMC516 definitions
use work.fmc_adc_pkg.all;
-- IP cores constants
use work.ipcores_pkg.all;
-- AFC definitions
use work.afc_base_pkg.all;
entity dbe_bpm2 is
port(
---------------------------------------------------------------------------
-- Clocking pins
---------------------------------------------------------------------------
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
aux_clk_p_i : in std_logic;
aux_clk_n_i : in std_logic;
afc_fp2_clk1_p_i : in std_logic;
afc_fp2_clk1_n_i : in std_logic;
---------------------------------------------------------------------------
-- Reset Button
---------------------------------------------------------------------------
sys_rst_button_n_i : in std_logic := '1';
---------------------------------------------------------------------------
-- UART pins
---------------------------------------------------------------------------
uart_rxd_i : in std_logic := '1';
uart_txd_o : out std_logic;
---------------------------------------------------------------------------
-- Trigger pins
---------------------------------------------------------------------------
trig_dir_o : out std_logic_vector(c_NUM_TRIG-1 downto 0);
trig_b : inout std_logic_vector(c_NUM_TRIG-1 downto 0);
---------------------------------------------------------------------------
-- AFC Diagnostics
---------------------------------------------------------------------------
diag_spi_cs_i : in std_logic := '0';
diag_spi_si_i : in std_logic := '0';
diag_spi_so_o : out std_logic;
diag_spi_clk_i : in std_logic := '0';
---------------------------------------------------------------------------
-- ADN4604ASVZ
---------------------------------------------------------------------------
adn4604_vadj2_clk_updt_n_o : out std_logic;
---------------------------------------------------------------------------
-- AFC I2C.
---------------------------------------------------------------------------
-- Si57x oscillator
afc_si57x_scl_b : inout std_logic;
afc_si57x_sda_b : inout std_logic;
-- Si57x oscillator output enable
afc_si57x_oe_o : out std_logic;
---------------------------------------------------------------------------
-- PCIe pins
---------------------------------------------------------------------------
-- DDR3 memory pins
ddr3_dq_b : inout std_logic_vector(c_DDR_DQ_WIDTH-1 downto 0);
ddr3_dqs_p_b : inout std_logic_vector(c_DDR_DQS_WIDTH-1 downto 0);
ddr3_dqs_n_b : inout std_logic_vector(c_DDR_DQS_WIDTH-1 downto 0);
ddr3_addr_o : out std_logic_vector(c_DDR_ROW_WIDTH-1 downto 0);
ddr3_ba_o : out std_logic_vector(c_DDR_BANK_WIDTH-1 downto 0);
ddr3_cs_n_o : out std_logic_vector(0 downto 0);
ddr3_ras_n_o : out std_logic;
ddr3_cas_n_o : out std_logic;
ddr3_we_n_o : out std_logic;
ddr3_reset_n_o : out std_logic;
ddr3_ck_p_o : out std_logic_vector(c_DDR_CK_WIDTH-1 downto 0);
ddr3_ck_n_o : out std_logic_vector(c_DDR_CK_WIDTH-1 downto 0);
ddr3_cke_o : out std_logic_vector(c_DDR_CKE_WIDTH-1 downto 0);
ddr3_dm_o : out std_logic_vector(c_DDR_DM_WIDTH-1 downto 0);
ddr3_odt_o : out std_logic_vector(c_DDR_ODT_WIDTH-1 downto 0);
-- PCIe transceivers
pci_exp_rxp_i : in std_logic_vector(c_PCIELANES - 1 downto 0);
pci_exp_rxn_i : in std_logic_vector(c_PCIELANES - 1 downto 0);
pci_exp_txp_o : out std_logic_vector(c_PCIELANES - 1 downto 0);
pci_exp_txn_o : out std_logic_vector(c_PCIELANES - 1 downto 0);
-- PCI clock and reset signals
pcie_clk_p_i : in std_logic;
pcie_clk_n_i : in std_logic;
---------------------------------------------------------------------------
-- User LEDs
---------------------------------------------------------------------------
leds_o : out std_logic_vector(2 downto 0);
---------------------------------------------------------------------------
-- FMC interface
---------------------------------------------------------------------------
board_i2c_scl_b : inout std_logic;
board_i2c_sda_b : inout std_logic;
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
--
-- spi_sclk_o : out std_logic;
-- spi_cs_n_o : out std_logic;
-- spi_mosi_o : out std_logic;
-- spi_miso_i : in std_logic := '0';
-----------------------------
-- FMC1_250m_4ch ports
-----------------------------
-- ADC clock (half of the sampling frequency) divider reset
fmc1_adc_clk_div_rst_p_o : out std_logic;
fmc1_adc_clk_div_rst_n_o : out std_logic;
fmc1_adc_ext_rst_n_o : out std_logic;
fmc1_adc_sleep_o : out std_logic;
-- ADC clocks. One clock per ADC channel.
-- Only ch1 clock is used as all data chains
-- are sampled at the same frequency
fmc1_adc_clk0_p_i : in std_logic := '0';
fmc1_adc_clk0_n_i : in std_logic := '0';
fmc1_adc_clk1_p_i : in std_logic := '0';
fmc1_adc_clk1_n_i : in std_logic := '0';
fmc1_adc_clk2_p_i : in std_logic := '0';
fmc1_adc_clk2_n_i : in std_logic := '0';
fmc1_adc_clk3_p_i : in std_logic := '0';
fmc1_adc_clk3_n_i : in std_logic := '0';
-- DDR ADC data channels.
fmc1_adc_data_ch0_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc1_adc_data_ch0_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc1_adc_data_ch1_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc1_adc_data_ch1_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc1_adc_data_ch2_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc1_adc_data_ch2_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc1_adc_data_ch3_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc1_adc_data_ch3_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
---- FMC General Status
--fmc1_prsnt_i : in std_logic;
--fmc1_pg_m2c_i : in std_logic;
--fmc1_clk_dir_i : in std_logic;
-- Trigger
fmc1_trig_dir_o : out std_logic;
fmc1_trig_term_o : out std_logic;
fmc1_trig_val_p_b : inout std_logic;
fmc1_trig_val_n_b : inout std_logic;
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
fmc1_adc_spi_clk_o : out std_logic;
fmc1_adc_spi_mosi_o : out std_logic;
fmc1_adc_spi_miso_i : in std_logic;
fmc1_adc_spi_cs_adc0_n_o : out std_logic; -- SPI ADC CS channel 0
fmc1_adc_spi_cs_adc1_n_o : out std_logic; -- SPI ADC CS channel 1
fmc1_adc_spi_cs_adc2_n_o : out std_logic; -- SPI ADC CS channel 2
fmc1_adc_spi_cs_adc3_n_o : out std_logic; -- SPI ADC CS channel 3
-- Si571 clock gen
fmc1_si571_scl_pad_b : inout std_logic;
fmc1_si571_sda_pad_b : inout std_logic;
fmc1_si571_oe_o : out std_logic;
-- AD9510 clock distribution PLL
fmc1_spi_ad9510_cs_o : out std_logic;
fmc1_spi_ad9510_sclk_o : out std_logic;
fmc1_spi_ad9510_mosi_o : out std_logic;
fmc1_spi_ad9510_miso_i : in std_logic;
fmc1_pll_function_o : out std_logic;
fmc1_pll_status_i : in std_logic;
-- AD9510 clock copy
fmc1_fpga_clk_p_i : in std_logic;
fmc1_fpga_clk_n_i : in std_logic;
-- Clock reference selection (TS3USB221)
fmc1_clk_sel_o : out std_logic;
-- EEPROM (Connected to the CPU). Use board I2C pins if needed as they are
-- behind a I2C switch that can access FMC I2C bus
--eeprom_scl_pad_b : inout std_logic;
--eeprom_sda_pad_b : inout std_logic;
-- AMC7823 temperature monitor
fmc1_amc7823_spi_cs_o : out std_logic;
fmc1_amc7823_spi_sclk_o : out std_logic;
fmc1_amc7823_spi_mosi_o : out std_logic;
fmc1_amc7823_spi_miso_i : in std_logic;
fmc1_amc7823_davn_i : in std_logic;
-- FMC LEDs
fmc1_led1_o : out std_logic;
fmc1_led2_o : out std_logic;
fmc1_led3_o : out std_logic;
-----------------------------
-- FMC2_250m_4ch ports
-----------------------------
-- ADC clock (half of the sampling frequency) divider reset
fmc2_adc_clk_div_rst_p_o : out std_logic;
fmc2_adc_clk_div_rst_n_o : out std_logic;
fmc2_adc_ext_rst_n_o : out std_logic;
fmc2_adc_sleep_o : out std_logic;
-- ADC clocks. One clock per ADC channel.
-- Only ch1 clock is used as all data chains
-- are sampled at the same frequency
fmc2_adc_clk0_p_i : in std_logic := '0';
fmc2_adc_clk0_n_i : in std_logic := '0';
fmc2_adc_clk1_p_i : in std_logic := '0';
fmc2_adc_clk1_n_i : in std_logic := '0';
fmc2_adc_clk2_p_i : in std_logic := '0';
fmc2_adc_clk2_n_i : in std_logic := '0';
fmc2_adc_clk3_p_i : in std_logic := '0';
fmc2_adc_clk3_n_i : in std_logic := '0';
-- DDR ADC data channels.
fmc2_adc_data_ch0_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc2_adc_data_ch0_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc2_adc_data_ch1_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc2_adc_data_ch1_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc2_adc_data_ch2_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc2_adc_data_ch2_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc2_adc_data_ch3_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
fmc2_adc_data_ch3_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0) := (others => '0');
---- FMC General Status
--fmc2_prsnt_i : in std_logic;
--fmc2_pg_m2c_i : in std_logic;
--fmc2_clk_dir_i : in std_logic;
-- Trigger
fmc2_trig_dir_o : out std_logic;
fmc2_trig_term_o : out std_logic;
fmc2_trig_val_p_b : inout std_logic;
fmc2_trig_val_n_b : inout std_logic;
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
fmc2_adc_spi_clk_o : out std_logic;
fmc2_adc_spi_mosi_o : out std_logic;
fmc2_adc_spi_miso_i : in std_logic;
fmc2_adc_spi_cs_adc0_n_o : out std_logic; -- SPI ADC CS channel 0
fmc2_adc_spi_cs_adc1_n_o : out std_logic; -- SPI ADC CS channel 1
fmc2_adc_spi_cs_adc2_n_o : out std_logic; -- SPI ADC CS channel 2
fmc2_adc_spi_cs_adc3_n_o : out std_logic; -- SPI ADC CS channel 3
-- Si571 clock gen
fmc2_si571_scl_pad_b : inout std_logic;
fmc2_si571_sda_pad_b : inout std_logic;
fmc2_si571_oe_o : out std_logic;
-- AD9510 clock distribution PLL
fmc2_spi_ad9510_cs_o : out std_logic;
fmc2_spi_ad9510_sclk_o : out std_logic;
fmc2_spi_ad9510_mosi_o : out std_logic;
fmc2_spi_ad9510_miso_i : in std_logic;
fmc2_pll_function_o : out std_logic;
fmc2_pll_status_i : in std_logic;
-- AD9510 clock copy
fmc2_fpga_clk_p_i : in std_logic;
fmc2_fpga_clk_n_i : in std_logic;
-- Clock reference selection (TS3USB221)
fmc2_clk_sel_o : out std_logic;
-- EEPROM (Connected to the CPU)
--eeprom_scl_pad_b : inout std_logic;
--eeprom_sda_pad_b : inout std_logic;
-- AMC7823 temperature monitor
fmc2_amc7823_spi_cs_o : out std_logic;
fmc2_amc7823_spi_sclk_o : out std_logic;
fmc2_amc7823_spi_mosi_o : out std_logic;
fmc2_amc7823_spi_miso_i : in std_logic;
fmc2_amc7823_davn_i : in std_logic;
-- FMC LEDs
fmc2_led1_o : out std_logic;
fmc2_led2_o : out std_logic;
fmc2_led3_o : out std_logic
);
end dbe_bpm2;
architecture rtl of dbe_bpm2 is
---------------------------
-- Components --
---------------------------
component dbe_bpm_gen
generic(
g_fmc_adc_type : string := "FMC250M"
);
port(
---------------------------------------------------------------------------
-- Clocking pins
---------------------------------------------------------------------------
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
aux_clk_p_i : in std_logic;
aux_clk_n_i : in std_logic;
afc_fp2_clk1_p_i : in std_logic;
afc_fp2_clk1_n_i : in std_logic;
---------------------------------------------------------------------------
-- Reset Button
---------------------------------------------------------------------------
sys_rst_button_n_i : in std_logic := '1';
---------------------------------------------------------------------------
-- UART pins
---------------------------------------------------------------------------
uart_rxd_i : in std_logic := '1';
uart_txd_o : out std_logic;
---------------------------------------------------------------------------
-- Trigger pins
---------------------------------------------------------------------------
trig_dir_o : out std_logic_vector(c_NUM_TRIG-1 downto 0);
trig_b : inout std_logic_vector(c_NUM_TRIG-1 downto 0);
---------------------------------------------------------------------------
-- AFC Diagnostics
---------------------------------------------------------------------------
diag_spi_cs_i : in std_logic := '0';
diag_spi_si_i : in std_logic := '0';
diag_spi_so_o : out std_logic;
diag_spi_clk_i : in std_logic := '0';
---------------------------------------------------------------------------
-- ADN4604ASVZ
---------------------------------------------------------------------------
adn4604_vadj2_clk_updt_n_o : out std_logic;
---------------------------------------------------------------------------
-- AFC I2C.
---------------------------------------------------------------------------
-- Si57x oscillator
afc_si57x_scl_b : inout std_logic;
afc_si57x_sda_b : inout std_logic;
-- Si57x oscillator output enable
afc_si57x_oe_o : out std_logic;
---------------------------------------------------------------------------
-- PCIe pins
---------------------------------------------------------------------------
-- DDR3 memory pins
ddr3_dq_b : inout std_logic_vector(c_DDR_DQ_WIDTH-1 downto 0);
ddr3_dqs_p_b : inout std_logic_vector(c_DDR_DQS_WIDTH-1 downto 0);
ddr3_dqs_n_b : inout std_logic_vector(c_DDR_DQS_WIDTH-1 downto 0);
ddr3_addr_o : out std_logic_vector(c_DDR_ROW_WIDTH-1 downto 0);
ddr3_ba_o : out std_logic_vector(c_DDR_BANK_WIDTH-1 downto 0);
ddr3_cs_n_o : out std_logic_vector(0 downto 0);
ddr3_ras_n_o : out std_logic;
ddr3_cas_n_o : out std_logic;
ddr3_we_n_o : out std_logic;
ddr3_reset_n_o : out std_logic;
ddr3_ck_p_o : out std_logic_vector(c_DDR_CK_WIDTH-1 downto 0);
ddr3_ck_n_o : out std_logic_vector(c_DDR_CK_WIDTH-1 downto 0);
ddr3_cke_o : out std_logic_vector(c_DDR_CKE_WIDTH-1 downto 0);
ddr3_dm_o : out std_logic_vector(c_DDR_DM_WIDTH-1 downto 0);
ddr3_odt_o : out std_logic_vector(c_DDR_ODT_WIDTH-1 downto 0);
-- PCIe transceivers
pci_exp_rxp_i : in std_logic_vector(c_PCIELANES - 1 downto 0);
pci_exp_rxn_i : in std_logic_vector(c_PCIELANES - 1 downto 0);
pci_exp_txp_o : out std_logic_vector(c_PCIELANES - 1 downto 0);
pci_exp_txn_o : out std_logic_vector(c_PCIELANES - 1 downto 0);
-- PCI clock and reset signals
pcie_clk_p_i : in std_logic;
pcie_clk_n_i : in std_logic;
---------------------------------------------------------------------------
-- User LEDs
---------------------------------------------------------------------------
leds_o : out std_logic_vector(2 downto 0);
---------------------------------------------------------------------------
-- FMC interface
---------------------------------------------------------------------------
board_i2c_scl_b : inout std_logic;
board_i2c_sda_b : inout std_logic;
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
--
-- spi_sclk_o : out std_logic;
-- spi_cs_n_o : out std_logic;
-- spi_mosi_o : out std_logic;
-- spi_miso_i : in std_logic := '0';
-----------------------------
-- FMC1_130m_4ch ports
-----------------------------
-- ADC LTC2208 interface
fmc130_1_adc_pga_o : out std_logic;
fmc130_1_adc_shdn_o : out std_logic;
fmc130_1_adc_dith_o : out std_logic;
fmc130_1_adc_rand_o : out std_logic;
-- ADC0 LTC2208
fmc130_1_adc0_clk_i : in std_logic := '0';
fmc130_1_adc0_data_i : in std_logic_vector(16-1 downto 0) := (others => '0');
fmc130_1_adc0_of_i : in std_logic := '0'; -- Unused
-- ADC1 LTC2208
fmc130_1_adc1_clk_i : in std_logic := '0';
fmc130_1_adc1_data_i : in std_logic_vector(16-1 downto 0) := (others => '0');
fmc130_1_adc1_of_i : in std_logic := '0'; -- Unused
-- ADC2 LTC2208
fmc130_1_adc2_clk_i : in std_logic := '0';
fmc130_1_adc2_data_i : in std_logic_vector(16-1 downto 0) := (others => '0');
fmc130_1_adc2_of_i : in std_logic := '0'; -- Unused
-- ADC3 LTC2208
fmc130_1_adc3_clk_i : in std_logic := '0';
fmc130_1_adc3_data_i : in std_logic_vector(16-1 downto 0) := (others => '0');
fmc130_1_adc3_of_i : in std_logic := '0'; -- Unused
---- FMC General Status
--fmc130_1_prsnt_i : in std_logic := '0';
--fmc130_1_pg_m2c_i : in std_logic := '0';
--fmc130_1_clk_dir_i : in std_logic := '0';
-- Trigger
fmc130_1_trig_dir_o : out std_logic;
fmc130_1_trig_term_o : out std_logic;
fmc130_1_trig_val_p_b : inout std_logic;
fmc130_1_trig_val_n_b : inout std_logic;
-- Si571 clock gen
fmc130_1_si571_scl_pad_b : inout std_logic;
fmc130_1_si571_sda_pad_b : inout std_logic;
fmc130_1_si571_oe_o : out std_logic;
-- AD9510 clock distribution PLL
fmc130_1_spi_ad9510_cs_o : out std_logic;
fmc130_1_spi_ad9510_sclk_o : out std_logic;
fmc130_1_spi_ad9510_mosi_o : out std_logic;
fmc130_1_spi_ad9510_miso_i : in std_logic := '0';
fmc130_1_pll_function_o : out std_logic;
fmc130_1_pll_status_i : in std_logic := '0';
-- AD9510 clock copy
fmc130_1_fpga_clk_p_i : in std_logic := '0';
fmc130_1_fpga_clk_n_i : in std_logic := '0';
-- Clock reference selection (TS3USB221)
fmc130_1_clk_sel_o : out std_logic;
-- EEPROM (Connected to the CPU)
--eeprom_scl_pad_b : inout std_logic;
--eeprom_sda_pad_b : inout std_logic;
fmc130_1_eeprom_scl_pad_b : inout std_logic;
fmc130_1_eeprom_sda_pad_b : inout std_logic;
-- Temperature monitor (LM75AIMM)
fmc130_1_lm75_scl_pad_b : inout std_logic;
fmc130_1_lm75_sda_pad_b : inout std_logic;
fmc130_1_lm75_temp_alarm_i : in std_logic := '0';
-- FMC LEDs
fmc130_1_led1_o : out std_logic;
fmc130_1_led2_o : out std_logic;
fmc130_1_led3_o : out std_logic;
-----------------------------
-- FMC2_130m_4ch ports
-----------------------------
-- ADC LTC2208 interface
fmc130_2_adc_pga_o : out std_logic;
fmc130_2_adc_shdn_o : out std_logic;
fmc130_2_adc_dith_o : out std_logic;
fmc130_2_adc_rand_o : out std_logic;
-- ADC0 LTC2208
fmc130_2_adc0_clk_i : in std_logic := '0';
fmc130_2_adc0_data_i : in std_logic_vector(16-1 downto 0) := (others => '0');
fmc130_2_adc0_of_i : in std_logic := '0'; -- Unused
-- ADC1 LTC2208
fmc130_2_adc1_clk_i : in std_logic := '0';
fmc130_2_adc1_data_i : in std_logic_vector(16-1 downto 0) := (others => '0');
fmc130_2_adc1_of_i : in std_logic := '0'; -- Unused
-- ADC2 LTC2208
fmc130_2_adc2_clk_i : in std_logic := '0';
fmc130_2_adc2_data_i : in std_logic_vector(16-1 downto 0) := (others => '0');
fmc130_2_adc2_of_i : in std_logic := '0'; -- Unused
-- ADC3 LTC2208
fmc130_2_adc3_clk_i : in std_logic := '0';
fmc130_2_adc3_data_i : in std_logic_vector(16-1 downto 0) := (others => '0');
fmc130_2_adc3_of_i : in std_logic := '0'; -- Unused
---- FMC General Status
--fmc130_2_prsnt_i : in std_logic := '0';
--fmc130_2_pg_m2c_i : in std_logic := '0';
--fmc130_2_clk_dir_i : in std_logic := '0';
-- Trigger
fmc130_2_trig_dir_o : out std_logic;
fmc130_2_trig_term_o : out std_logic;
fmc130_2_trig_val_p_b : inout std_logic;
fmc130_2_trig_val_n_b : inout std_logic;
-- Si571 clock gen
fmc130_2_si571_scl_pad_b : inout std_logic;
fmc130_2_si571_sda_pad_b : inout std_logic;
fmc130_2_si571_oe_o : out std_logic;
-- AD9510 clock distribution PLL
fmc130_2_spi_ad9510_cs_o : out std_logic;
fmc130_2_spi_ad9510_sclk_o : out std_logic;
fmc130_2_spi_ad9510_mosi_o : out std_logic;
fmc130_2_spi_ad9510_miso_i : in std_logic := '0';
fmc130_2_pll_function_o : out std_logic;
fmc130_2_pll_status_i : in std_logic := '0';
-- AD9510 clock copy
fmc130_2_fpga_clk_p_i : in std_logic := '0';
fmc130_2_fpga_clk_n_i : in std_logic := '0';
-- Clock reference selection (TS3USB221)
fmc130_2_clk_sel_o : out std_logic;
-- EEPROM (Connected to the CPU)
--eeprom_scl_pad_b : inout std_logic;
--eeprom_sda_pad_b : inout std_logic;
-- Temperature monitor (LM75AIMM)
fmc130_2_lm75_scl_pad_b : inout std_logic;
fmc130_2_lm75_sda_pad_b : inout std_logic;
fmc130_2_lm75_temp_alarm_i : in std_logic := '0';
-- FMC LEDs
fmc130_2_led1_o : out std_logic;
fmc130_2_led2_o : out std_logic;
fmc130_2_led3_o : out std_logic;
-----------------------------
-- FMC1_250m_4ch ports
-----------------------------
-- ADC clock (half of the sampling frequency) divider reset
fmc250_1_adc_clk_div_rst_p_o : out std_logic;
fmc250_1_adc_clk_div_rst_n_o : out std_logic;
fmc250_1_adc_ext_rst_n_o : out std_logic;
fmc250_1_adc_sleep_o : out std_logic;
-- ADC clocks. One clock per ADC channel.
-- Only ch1 clock is used as all data chains
-- are sampled at the same frequency
fmc250_1_adc_clk0_p_i : in std_logic := '0';
fmc250_1_adc_clk0_n_i : in std_logic := '0';
fmc250_1_adc_clk1_p_i : in std_logic := '0';
fmc250_1_adc_clk1_n_i : in std_logic := '0';
fmc250_1_adc_clk2_p_i : in std_logic := '0';
fmc250_1_adc_clk2_n_i : in std_logic := '0';
fmc250_1_adc_clk3_p_i : in std_logic := '0';
fmc250_1_adc_clk3_n_i : in std_logic := '0';
-- DDR ADC data channels.
fmc250_1_adc_data_ch0_p_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_1_adc_data_ch0_n_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_1_adc_data_ch1_p_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_1_adc_data_ch1_n_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_1_adc_data_ch2_p_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_1_adc_data_ch2_n_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_1_adc_data_ch3_p_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_1_adc_data_ch3_n_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
---- FMC General Status
--fmc250_1_prsnt_i : in std_logic := '0';
--fmc250_1_pg_m2c_i : in std_logic := '0';
--fmc250_1_clk_dir_i : in std_logic := '0';
-- Trigger
fmc250_1_trig_dir_o : out std_logic;
fmc250_1_trig_term_o : out std_logic;
fmc250_1_trig_val_p_b : inout std_logic;
fmc250_1_trig_val_n_b : inout std_logic;
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
fmc250_1_adc_spi_clk_o : out std_logic;
fmc250_1_adc_spi_mosi_o : out std_logic;
fmc250_1_adc_spi_miso_i : in std_logic := '0';
fmc250_1_adc_spi_cs_adc0_n_o : out std_logic; -- SPI ADC CS channel 0
fmc250_1_adc_spi_cs_adc1_n_o : out std_logic; -- SPI ADC CS channel 1
fmc250_1_adc_spi_cs_adc2_n_o : out std_logic; -- SPI ADC CS channel 2
fmc250_1_adc_spi_cs_adc3_n_o : out std_logic; -- SPI ADC CS channel 3
-- Si571 clock gen
fmc250_1_si571_scl_pad_b : inout std_logic;
fmc250_1_si571_sda_pad_b : inout std_logic;
fmc250_1_si571_oe_o : out std_logic;
-- AD9510 clock distribution PLL
fmc250_1_spi_ad9510_cs_o : out std_logic;
fmc250_1_spi_ad9510_sclk_o : out std_logic;
fmc250_1_spi_ad9510_mosi_o : out std_logic;
fmc250_1_spi_ad9510_miso_i : in std_logic := '0';
fmc250_1_pll_function_o : out std_logic;
fmc250_1_pll_status_i : in std_logic := '0';
-- AD9510 clock copy
fmc250_1_fpga_clk_p_i : in std_logic := '0';
fmc250_1_fpga_clk_n_i : in std_logic := '0';
-- Clock reference selection (TS3USB221)
fmc250_1_clk_sel_o : out std_logic;
-- EEPROM (Connected to the CPU)
--eeprom_scl_pad_b : inout std_logic;
--eeprom_sda_pad_b : inout std_logic;
fmc250_1_eeprom_scl_pad_b : inout std_logic;
fmc250_1_eeprom_sda_pad_b : inout std_logic;
-- AMC7823 temperature monitor
fmc250_1_amc7823_spi_cs_o : out std_logic;
fmc250_1_amc7823_spi_sclk_o : out std_logic;
fmc250_1_amc7823_spi_mosi_o : out std_logic;
fmc250_1_amc7823_spi_miso_i : in std_logic := '0';
fmc250_1_amc7823_davn_i : in std_logic := '0';
-- FMC LEDs
fmc250_1_led1_o : out std_logic;
fmc250_1_led2_o : out std_logic;
fmc250_1_led3_o : out std_logic;
-----------------------------
-- FMC2_250m_4ch ports
-----------------------------
-- ADC clock (half of the sampling frequency) divider reset
fmc250_2_adc_clk_div_rst_p_o : out std_logic;
fmc250_2_adc_clk_div_rst_n_o : out std_logic;
fmc250_2_adc_ext_rst_n_o : out std_logic;
fmc250_2_adc_sleep_o : out std_logic;
-- ADC clocks. One clock per ADC channel.
-- Only ch1 clock is used as all data chains
-- are sampled at the same frequency
fmc250_2_adc_clk0_p_i : in std_logic := '0';
fmc250_2_adc_clk0_n_i : in std_logic := '0';
fmc250_2_adc_clk1_p_i : in std_logic := '0';
fmc250_2_adc_clk1_n_i : in std_logic := '0';
fmc250_2_adc_clk2_p_i : in std_logic := '0';
fmc250_2_adc_clk2_n_i : in std_logic := '0';
fmc250_2_adc_clk3_p_i : in std_logic := '0';
fmc250_2_adc_clk3_n_i : in std_logic := '0';
-- DDR ADC data channels.
fmc250_2_adc_data_ch0_p_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_2_adc_data_ch0_n_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_2_adc_data_ch1_p_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_2_adc_data_ch1_n_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_2_adc_data_ch2_p_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_2_adc_data_ch2_n_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_2_adc_data_ch3_p_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
fmc250_2_adc_data_ch3_n_i : in std_logic_vector(16/2-1 downto 0) := (others => '0');
---- FMC General Status
--fmc250_2_prsnt_i : in std_logic := '0';
--fmc250_2_pg_m2c_i : in std_logic := '0';
--fmc250_2_clk_dir_i : in std_logic := '0';
-- Trigger
fmc250_2_trig_dir_o : out std_logic;
fmc250_2_trig_term_o : out std_logic;
fmc250_2_trig_val_p_b : inout std_logic;
fmc250_2_trig_val_n_b : inout std_logic;
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
fmc250_2_adc_spi_clk_o : out std_logic;
fmc250_2_adc_spi_mosi_o : out std_logic;
fmc250_2_adc_spi_miso_i : in std_logic := '0';
fmc250_2_adc_spi_cs_adc0_n_o : out std_logic; -- SPI ADC CS channel 0
fmc250_2_adc_spi_cs_adc1_n_o : out std_logic; -- SPI ADC CS channel 1
fmc250_2_adc_spi_cs_adc2_n_o : out std_logic; -- SPI ADC CS channel 2
fmc250_2_adc_spi_cs_adc3_n_o : out std_logic; -- SPI ADC CS channel 3
-- Si571 clock gen
fmc250_2_si571_scl_pad_b : inout std_logic;
fmc250_2_si571_sda_pad_b : inout std_logic;
fmc250_2_si571_oe_o : out std_logic;
-- AD9510 clock distribution PLL
fmc250_2_spi_ad9510_cs_o : out std_logic;
fmc250_2_spi_ad9510_sclk_o : out std_logic;
fmc250_2_spi_ad9510_mosi_o : out std_logic;
fmc250_2_spi_ad9510_miso_i : in std_logic := '0';
fmc250_2_pll_function_o : out std_logic;
fmc250_2_pll_status_i : in std_logic := '0';
-- AD9510 clock copy
fmc250_2_fpga_clk_p_i : in std_logic := '0';
fmc250_2_fpga_clk_n_i : in std_logic := '0';
-- Clock reference selection (TS3USB221)
fmc250_2_clk_sel_o : out std_logic;
-- EEPROM (Connected to the CPU)
--eeprom_scl_pad_b : inout std_logic;
--eeprom_sda_pad_b : inout std_logic;
-- AMC7823 temperature monitor
fmc250_2_amc7823_spi_cs_o : out std_logic;
fmc250_2_amc7823_spi_sclk_o : out std_logic;
fmc250_2_amc7823_spi_mosi_o : out std_logic;
fmc250_2_amc7823_spi_miso_i : in std_logic := '0';
fmc250_2_amc7823_davn_i : in std_logic := '0';
-- FMC LEDs
fmc250_2_led1_o : out std_logic;
fmc250_2_led2_o : out std_logic;
fmc250_2_led3_o : out std_logic;
-----------------------------------------
-- FMC PICO 1M_4CH Ports
-----------------------------------------
fmcpico_1_adc_cnv_o : out std_logic;
fmcpico_1_adc_sck_o : out std_logic;
fmcpico_1_adc_sck_rtrn_i : in std_logic := '0';
fmcpico_1_adc_sdo1_i : in std_logic := '0';
fmcpico_1_adc_sdo2_i : in std_logic := '0';
fmcpico_1_adc_sdo3_i : in std_logic := '0';
fmcpico_1_adc_sdo4_i : in std_logic := '0';
fmcpico_1_adc_busy_cmn_i : in std_logic := '0';
fmcpico_1_rng_r1_o : out std_logic;
fmcpico_1_rng_r2_o : out std_logic;
fmcpico_1_rng_r3_o : out std_logic;
fmcpico_1_rng_r4_o : out std_logic;
fmcpico_1_led1_o : out std_logic;
fmcpico_1_led2_o : out std_logic;
fmcpico_1_sm_scl_o : out std_logic;
fmcpico_1_sm_sda_b : inout std_logic;
fmcpico_1_a_scl_o : out std_logic;
fmcpico_1_a_sda_b : inout std_logic;
-----------------------------------------
-- FMC PICO 1M_4CH Ports
-----------------------------------------
fmcpico_2_adc_cnv_o : out std_logic;
fmcpico_2_adc_sck_o : out std_logic;
fmcpico_2_adc_sck_rtrn_i : in std_logic := '0';
fmcpico_2_adc_sdo1_i : in std_logic := '0';
fmcpico_2_adc_sdo2_i : in std_logic := '0';
fmcpico_2_adc_sdo3_i : in std_logic := '0';
fmcpico_2_adc_sdo4_i : in std_logic := '0';
fmcpico_2_adc_busy_cmn_i : in std_logic := '0';
fmcpico_2_rng_r1_o : out std_logic;
fmcpico_2_rng_r2_o : out std_logic;
fmcpico_2_rng_r3_o : out std_logic;
fmcpico_2_rng_r4_o : out std_logic;
fmcpico_2_led1_o : out std_logic;
fmcpico_2_led2_o : out std_logic;
---- Connected through FPGA MUX
--fmcpico_2_sm_scl_o : out std_logic;
--fmcpico_2_sm_sda_b : inout std_logic;
fmcpico_2_a_scl_o : out std_logic;
fmcpico_2_a_sda_b : inout std_logic
);
end component;
begin
cmp_dbe_bpm_gen : dbe_bpm_gen
generic map (
g_fmc_adc_type => "FMC250M"
)
port map (
---------------------------------------------------------------------------
-- Clocking pins
---------------------------------------------------------------------------
sys_clk_p_i => sys_clk_p_i,
sys_clk_n_i => sys_clk_n_i,
aux_clk_p_i => aux_clk_p_i,
aux_clk_n_i => aux_clk_n_i,
afc_fp2_clk1_p_i => afc_fp2_clk1_p_i,
afc_fp2_clk1_n_i => afc_fp2_clk1_n_i,
---------------------------------------------------------------------------
-- Reset Button
---------------------------------------------------------------------------
sys_rst_button_n_i => sys_rst_button_n_i,
---------------------------------------------------------------------------
-- UART pins
---------------------------------------------------------------------------
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
---------------------------------------------------------------------------
-- Trigger pins
---------------------------------------------------------------------------
trig_dir_o => trig_dir_o,
trig_b => trig_b,
---------------------------------------------------------------------------
-- AFC Diagnostics
---------------------------------------------------------------------------
diag_spi_cs_i => diag_spi_cs_i,
diag_spi_si_i => diag_spi_si_i,
diag_spi_so_o => diag_spi_so_o,
diag_spi_clk_i => diag_spi_clk_i,
---------------------------------------------------------------------------
-- ADN4604ASVZ
---------------------------------------------------------------------------
adn4604_vadj2_clk_updt_n_o => adn4604_vadj2_clk_updt_n_o,
---------------------------------------------------------------------------
-- AFC I2C.
---------------------------------------------------------------------------
-- Si57x oscillator
afc_si57x_scl_b => afc_si57x_scl_b,
afc_si57x_sda_b => afc_si57x_sda_b,
-- Si57x oscillator output enable
afc_si57x_oe_o => afc_si57x_oe_o,
---------------------------------------------------------------------------
-- PCIe pins
---------------------------------------------------------------------------
-- DDR3 memory pins
ddr3_dq_b => ddr3_dq_b,
ddr3_dqs_p_b => ddr3_dqs_p_b,
ddr3_dqs_n_b => ddr3_dqs_n_b,
ddr3_addr_o => ddr3_addr_o,
ddr3_ba_o => ddr3_ba_o,
ddr3_cs_n_o => ddr3_cs_n_o,
ddr3_ras_n_o => ddr3_ras_n_o,
ddr3_cas_n_o => ddr3_cas_n_o,
ddr3_we_n_o => ddr3_we_n_o,
ddr3_reset_n_o => ddr3_reset_n_o,
ddr3_ck_p_o => ddr3_ck_p_o,
ddr3_ck_n_o => ddr3_ck_n_o,
ddr3_cke_o => ddr3_cke_o,
ddr3_dm_o => ddr3_dm_o,
ddr3_odt_o => ddr3_odt_o,
-- PCIe transceivers
pci_exp_rxp_i => pci_exp_rxp_i,
pci_exp_rxn_i => pci_exp_rxn_i,
pci_exp_txp_o => pci_exp_txp_o,
pci_exp_txn_o => pci_exp_txn_o,
-- PCI clock and reset signals
pcie_clk_p_i => pcie_clk_p_i,
pcie_clk_n_i => pcie_clk_n_i,
---------------------------------------------------------------------------
-- User LEDs
---------------------------------------------------------------------------
leds_o => leds_o,
---------------------------------------------------------------------------
-- FMC interface
---------------------------------------------------------------------------
board_i2c_scl_b => board_i2c_scl_b,
board_i2c_sda_b => board_i2c_sda_b,
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
--
-- spi_sclk_o => spi_sclk_o,
-- spi_cs_n_o => spi_cs_n_o,
-- spi_mosi_o => spi_mosi_o,
-- spi_miso_i => spi_miso_i,
-----------------------------
-- FMC1_250m_4ch ports
-----------------------------
-- ADC clock (half of the sampling frequency) divider reset
fmc250_1_adc_clk_div_rst_p_o => fmc1_adc_clk_div_rst_p_o,
fmc250_1_adc_clk_div_rst_n_o => fmc1_adc_clk_div_rst_n_o,
fmc250_1_adc_ext_rst_n_o => fmc1_adc_ext_rst_n_o,
fmc250_1_adc_sleep_o => fmc1_adc_sleep_o,
-- ADC clocks. One clock per ADC channel.
-- Only ch1 clock is used as all data chains
-- are sampled at the same frequency
fmc250_1_adc_clk0_p_i => fmc1_adc_clk0_p_i,
fmc250_1_adc_clk0_n_i => fmc1_adc_clk0_n_i,
fmc250_1_adc_clk1_p_i => fmc1_adc_clk1_p_i,
fmc250_1_adc_clk1_n_i => fmc1_adc_clk1_n_i,
fmc250_1_adc_clk2_p_i => fmc1_adc_clk2_p_i,
fmc250_1_adc_clk2_n_i => fmc1_adc_clk2_n_i,
fmc250_1_adc_clk3_p_i => fmc1_adc_clk3_p_i,
fmc250_1_adc_clk3_n_i => fmc1_adc_clk3_n_i,
-- DDR ADC data channels.
fmc250_1_adc_data_ch0_p_i => fmc1_adc_data_ch0_p_i,
fmc250_1_adc_data_ch0_n_i => fmc1_adc_data_ch0_n_i,
fmc250_1_adc_data_ch1_p_i => fmc1_adc_data_ch1_p_i,
fmc250_1_adc_data_ch1_n_i => fmc1_adc_data_ch1_n_i,
fmc250_1_adc_data_ch2_p_i => fmc1_adc_data_ch2_p_i,
fmc250_1_adc_data_ch2_n_i => fmc1_adc_data_ch2_n_i,
fmc250_1_adc_data_ch3_p_i => fmc1_adc_data_ch3_p_i,
fmc250_1_adc_data_ch3_n_i => fmc1_adc_data_ch3_n_i,
---- FMC General Status
--fmc250_1_prsnt_i : in std_logic := '0';
--fmc250_1_pg_m2c_i : in std_logic := '0';
--fmc250_1_clk_dir_i : in std_logic := '0';
-- Trigger
fmc250_1_trig_dir_o => fmc1_trig_dir_o,
fmc250_1_trig_term_o => fmc1_trig_term_o,
fmc250_1_trig_val_p_b => fmc1_trig_val_p_b,
fmc250_1_trig_val_n_b => fmc1_trig_val_n_b,
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
fmc250_1_adc_spi_clk_o => fmc1_adc_spi_clk_o,
fmc250_1_adc_spi_mosi_o => fmc1_adc_spi_mosi_o,
fmc250_1_adc_spi_miso_i => fmc1_adc_spi_miso_i,
fmc250_1_adc_spi_cs_adc0_n_o => fmc1_adc_spi_cs_adc0_n_o,
fmc250_1_adc_spi_cs_adc1_n_o => fmc1_adc_spi_cs_adc1_n_o,
fmc250_1_adc_spi_cs_adc2_n_o => fmc1_adc_spi_cs_adc2_n_o,
fmc250_1_adc_spi_cs_adc3_n_o => fmc1_adc_spi_cs_adc3_n_o,
-- Si571 clock gen
fmc250_1_si571_scl_pad_b => fmc1_si571_scl_pad_b,
fmc250_1_si571_sda_pad_b => fmc1_si571_sda_pad_b,
fmc250_1_si571_oe_o => fmc1_si571_oe_o,
-- AD9510 clock distribution PLL
fmc250_1_spi_ad9510_cs_o => fmc1_spi_ad9510_cs_o,
fmc250_1_spi_ad9510_sclk_o => fmc1_spi_ad9510_sclk_o,
fmc250_1_spi_ad9510_mosi_o => fmc1_spi_ad9510_mosi_o,
fmc250_1_spi_ad9510_miso_i => fmc1_spi_ad9510_miso_i,
fmc250_1_pll_function_o => fmc1_pll_function_o,
fmc250_1_pll_status_i => fmc1_pll_status_i,
-- AD9510 clock copy
fmc250_1_fpga_clk_p_i => fmc1_fpga_clk_p_i,
fmc250_1_fpga_clk_n_i => fmc1_fpga_clk_n_i,
-- Clock reference selection (TS3USB221)
fmc250_1_clk_sel_o => fmc1_clk_sel_o,
-- EEPROM (Connected to the CPU). Use board I2C pins if needed as they are
-- behind a I2C switch that can access FMC I2C bus
--eeprom_scl_pad_b : inout std_logic;
--eeprom_sda_pad_b : inout std_logic;
-- AMC7823 temperature monitor
fmc250_1_amc7823_spi_cs_o => fmc1_amc7823_spi_cs_o,
fmc250_1_amc7823_spi_sclk_o => fmc1_amc7823_spi_sclk_o,
fmc250_1_amc7823_spi_mosi_o => fmc1_amc7823_spi_mosi_o,
fmc250_1_amc7823_spi_miso_i => fmc1_amc7823_spi_miso_i,
fmc250_1_amc7823_davn_i => fmc1_amc7823_davn_i,
-- FMC LEDs
fmc250_1_led1_o => fmc1_led1_o,
fmc250_1_led2_o => fmc1_led2_o,
fmc250_1_led3_o => fmc1_led3_o,
-----------------------------
-- FMC2_250m_4ch ports
-----------------------------
-- ADC clock (half of the sampling frequency) divider reset
fmc250_2_adc_clk_div_rst_p_o => fmc2_adc_clk_div_rst_p_o,
fmc250_2_adc_clk_div_rst_n_o => fmc2_adc_clk_div_rst_n_o,
fmc250_2_adc_ext_rst_n_o => fmc2_adc_ext_rst_n_o,
fmc250_2_adc_sleep_o => fmc2_adc_sleep_o,
-- ADC clocks. One clock per ADC channel.
-- Only ch1 clock is used as all data chains
-- are sampled at the same frequency
fmc250_2_adc_clk0_p_i => fmc2_adc_clk0_p_i,
fmc250_2_adc_clk0_n_i => fmc2_adc_clk0_n_i,
fmc250_2_adc_clk1_p_i => fmc2_adc_clk1_p_i,
fmc250_2_adc_clk1_n_i => fmc2_adc_clk1_n_i,
fmc250_2_adc_clk2_p_i => fmc2_adc_clk2_p_i,
fmc250_2_adc_clk2_n_i => fmc2_adc_clk2_n_i,
fmc250_2_adc_clk3_p_i => fmc2_adc_clk3_p_i,
fmc250_2_adc_clk3_n_i => fmc2_adc_clk3_n_i,
-- DDR ADC data channels.
fmc250_2_adc_data_ch0_p_i => fmc2_adc_data_ch0_p_i,
fmc250_2_adc_data_ch0_n_i => fmc2_adc_data_ch0_n_i,
fmc250_2_adc_data_ch1_p_i => fmc2_adc_data_ch1_p_i,
fmc250_2_adc_data_ch1_n_i => fmc2_adc_data_ch1_n_i,
fmc250_2_adc_data_ch2_p_i => fmc2_adc_data_ch2_p_i,
fmc250_2_adc_data_ch2_n_i => fmc2_adc_data_ch2_n_i,
fmc250_2_adc_data_ch3_p_i => fmc2_adc_data_ch3_p_i,
fmc250_2_adc_data_ch3_n_i => fmc2_adc_data_ch3_n_i,
---- FMC General Status
--fmc250_2_prsnt_i : in std_logic := '0';
--fmc250_2_pg_m2c_i : in std_logic := '0';
--fmc250_2_clk_dir_i : in std_logic := '0';
-- Trigger
fmc250_2_trig_dir_o => fmc2_trig_dir_o,
fmc250_2_trig_term_o => fmc2_trig_term_o,
fmc250_2_trig_val_p_b => fmc2_trig_val_p_b,
fmc250_2_trig_val_n_b => fmc2_trig_val_n_b,
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
fmc250_2_adc_spi_clk_o => fmc2_adc_spi_clk_o,
fmc250_2_adc_spi_mosi_o => fmc2_adc_spi_mosi_o,
fmc250_2_adc_spi_miso_i => fmc2_adc_spi_miso_i,
fmc250_2_adc_spi_cs_adc0_n_o => fmc2_adc_spi_cs_adc0_n_o,
fmc250_2_adc_spi_cs_adc1_n_o => fmc2_adc_spi_cs_adc1_n_o,
fmc250_2_adc_spi_cs_adc2_n_o => fmc2_adc_spi_cs_adc2_n_o,
fmc250_2_adc_spi_cs_adc3_n_o => fmc2_adc_spi_cs_adc3_n_o,
-- Si571 clock gen
fmc250_2_si571_scl_pad_b => fmc2_si571_scl_pad_b,
fmc250_2_si571_sda_pad_b => fmc2_si571_sda_pad_b,
fmc250_2_si571_oe_o => fmc2_si571_oe_o,
-- AD9510 clock distribution PLL
fmc250_2_spi_ad9510_cs_o => fmc2_spi_ad9510_cs_o,
fmc250_2_spi_ad9510_sclk_o => fmc2_spi_ad9510_sclk_o,
fmc250_2_spi_ad9510_mosi_o => fmc2_spi_ad9510_mosi_o,
fmc250_2_spi_ad9510_miso_i => fmc2_spi_ad9510_miso_i,
fmc250_2_pll_function_o => fmc2_pll_function_o,
fmc250_2_pll_status_i => fmc2_pll_status_i,
-- AD9510 clock copy
fmc250_2_fpga_clk_p_i => fmc2_fpga_clk_p_i,
fmc250_2_fpga_clk_n_i => fmc2_fpga_clk_n_i,
-- Clock reference selection (TS3USB221)
fmc250_2_clk_sel_o => fmc2_clk_sel_o,
-- EEPROM (Connected to the CPU)
--eeprom_scl_pad_b : inout std_logic;
--eeprom_sda_pad_b : inout std_logic;
-- AMC7823 temperature monitor
fmc250_2_amc7823_spi_cs_o => fmc2_amc7823_spi_cs_o,
fmc250_2_amc7823_spi_sclk_o => fmc2_amc7823_spi_sclk_o,
fmc250_2_amc7823_spi_mosi_o => fmc2_amc7823_spi_mosi_o,
fmc250_2_amc7823_spi_miso_i => fmc2_amc7823_spi_miso_i,
fmc250_2_amc7823_davn_i => fmc2_amc7823_davn_i,
-- FMC LEDs
fmc250_2_led1_o => fmc2_led1_o,
fmc250_2_led2_o => fmc2_led2_o,
fmc250_2_led3_o => fmc2_led3_o
);
end rtl;
|
lgpl-3.0
|
7300af1efb6f769bdd58a13b2a953462
| 0.3962 | 3.617797 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/examples/statements/SimpleIfStatementMergable.vhd
| 1 | 545 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- .. hwt-autodoc::
--
ENTITY SimpleIfStatementMergable IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
c : OUT STD_LOGIC;
d : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF SimpleIfStatementMergable IS
BEGIN
assig_process_d: PROCESS(a, b)
BEGIN
IF a = '1' THEN
d <= b;
c <= b;
ELSE
d <= '0';
c <= '0';
END IF;
END PROCESS;
END ARCHITECTURE;
|
mit
|
fa67cc1ed4de9c4db622558e0c175ee8
| 0.515596 | 3.471338 | false | false | false | false |
mithro/soft-utmi
|
hdl/third_party/XAPP1064-serdes-macros/VHDL_Source/Macros/serdes_1_to_n_clk_pll_s16_diff.vhd
| 1 | 20,774 |
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: serdes_1_to_n_clk_pll_s16_diff.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: August 1 2008
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: 1-bit generic 1:n clock receiver module where n is 10, 12, 14 or 16
-- Instantiates necessary clock buffers and PLL
-- Contains state machine to calibrate clock input delay line, and perform bitslip if required.
-- The required search pattern for bitslip to function should be modified around line 142
-- Takes in 1 bit of differential data and deserialises this to n bits for where this data is required
-- data is received LSB first
-- 0, 1, 2 ......
--
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity serdes_1_to_n_clk_pll_s16_diff is generic (
PLLD : integer := 1 ; -- Parameter to set division for PLL
PLLX : integer := 2 ; -- Parameter to set multiplier for PLL
CLKIN_PERIOD : real := 6.000 ; -- clock period (ns) of input clock on clkin_p
S : integer := 16 ; -- Parameter to set the serdes factor 1..8
BS : boolean := FALSE ; -- Parameter to enable bitslip TRUE or FALSE
DIFF_TERM : boolean := FALSE) ; -- Enable or disable internal differential termination
port (
clkin_p : in std_logic ; -- Input from LVDS receiver pin
clkin_n : in std_logic ; -- Input from LVDS receiver pin
rxioclk : out std_logic ; -- IO Clock network
rx_serdesstrobe : out std_logic ; -- Parallel data capture strobe
reset : in std_logic ; -- Reset line
pattern1 : in std_logic_vector(S-1 downto 0) ; -- Data to define pattern that bitslip should search for
rx_bufg_pll_x1 : out std_logic ; -- Global clock
rx_bufg_pll_x2 : out std_logic ; -- Global clock x2
bitslip : out std_logic ; -- Bitslip control line
rx_toggle : out std_logic ; -- Control line to data receiver
datain : out std_logic_vector(S-1 downto 0) ; -- Output data
rx_bufpll_lckd : out std_logic); -- BUFPLL locked
end serdes_1_to_n_clk_pll_s16_diff ;
architecture arch_serdes_1_to_n_clk_pll_s16_diff of serdes_1_to_n_clk_pll_s16_diff is
signal P_clk : std_logic; -- P clock out to BUFIO2
signal buf_pll_fb_clk : std_logic; -- PLL feedback clock into BUFIOFB
signal ddly_m : std_logic; -- Master output from IODELAY1
signal ddly_s : std_logic; -- Slave output from IODELAY1
signal mdataout : std_logic_vector(7 downto 0) ; --
signal cascade : std_logic ; --
signal pd_edge : std_logic ; --
signal busys : std_logic ; --
signal busym : std_logic ; --
signal rx_clk_in : std_logic ; --
signal feedback : std_logic ; --
signal buf_P_clk : std_logic ; --
signal iob_data_in : std_logic ; --
signal rx_bufg_pll_x1_int : std_logic ;
signal rx_bufg_pll_x2_int : std_logic ;
signal rxioclk_int : std_logic ;
signal rx_serdesstrobe_int : std_logic ;
signal rx_pllout_x1 : std_logic ;
signal rx_pll_lckd : std_logic ;
signal rx_toggle_int : std_logic ;
signal state : integer range 0 to 9 ;
signal bslip : std_logic ;
signal count : std_logic_vector(2 downto 0) ;
signal busyd : std_logic ;
signal counter : std_logic_vector(11 downto 0) ;
signal clk_iserdes_data : std_logic_vector(S-1 downto 0) ;
signal clk_iserdes_data_int : std_logic_vector(S/2-1 downto 0) ;
signal clkh : std_logic_vector(S/2-1 downto 0) ;
signal cal_clk : std_logic ;
signal rst_clk : std_logic ;
signal rx_bufplllckd : std_logic ;
signal not_rx_bufpll_lckd : std_logic ;
signal busy_clk : std_logic ;
signal rx_pllout_xs : std_logic ;
signal rx_pllout_x2 : std_logic ;
signal enable : std_logic ;
constant RX_SWAP_CLK : std_logic := '0' ; -- pinswap mask for input clock (0 = no swap (default), 1 = swap). Allows input to be connected the wrong way round to ease PCB routing.
begin
rx_bufg_pll_x1 <= rx_bufg_pll_x1_int ;
rx_bufg_pll_x2 <= rx_bufg_pll_x2_int ;
rxioclk <= rxioclk_int ;
rx_serdesstrobe <= rx_serdesstrobe_int ;
rx_toggle <= rx_toggle_int ;
bitslip <= bslip ;
iob_clk_in : IBUFGDS generic map(
DIFF_TERM => DIFF_TERM)
port map (
I => clkin_p,
IB => clkin_n,
O => rx_clk_in);
iob_data_in <= rx_clk_in xor RX_SWAP_CLK ; -- Invert clock as required
busy_clk <= busym ;
datain <= clk_iserdes_data ;
-- Bitslip and CAL state machine
process (rx_bufg_pll_x1_int)
begin
if rx_bufg_pll_x1_int'event and rx_bufg_pll_x1_int = '1' then
clk_iserdes_data <= clk_iserdes_data_int & clkh ;
end if ;
end process ;
process (rx_bufg_pll_x2_int, not_rx_bufpll_lckd)
begin
if not_rx_bufpll_lckd = '1' then
rx_toggle_int <= '0' ;
elsif rx_bufg_pll_x2_int'event and rx_bufg_pll_x2_int = '1' then
if rx_toggle_int = '1' then -- check gearbox is in the right phase
clkh <= clk_iserdes_data_int ;
if clk_iserdes_data_int = pattern1(S-1 downto S/2) and count = "111" then
rx_toggle_int <= rx_toggle_int ;
else
rx_toggle_int <= not rx_toggle_int ;
end if ;
else
rx_toggle_int <= not rx_toggle_int ;
end if ;
end if ;
end process ;
process (rx_bufg_pll_x2_int, not_rx_bufpll_lckd)
begin
if not_rx_bufpll_lckd = '1' then
state <= 0 ;
enable <= '0' ;
cal_clk <= '0' ;
rst_clk <= '0' ;
bslip <= '0' ;
busyd <= '1' ;
counter <= "000000000000" ;
elsif rx_bufg_pll_x1_int'event and rx_bufg_pll_x1_int = '1' then
busyd <= busy_clk ;
if counter(5) = '1' then
enable <= '1' ;
end if ;
if counter(11) = '1' then
state <= 0 ;
cal_clk <= '0' ;
rst_clk <= '0' ;
bslip <= '0' ;
busyd <= '1' ;
counter <= "000000000000" ;
else
counter <= counter + 1 ;
if state = 0 and enable = '1' and busyd = '0' then
state <= 1 ;
elsif state = 1 then -- cal high
cal_clk <= '1' ; state <= 2 ;
elsif state = 2 and busyd = '1' then -- wait for busy high
cal_clk <= '0' ; state <= 3 ; -- cal low
elsif state = 3 and busyd = '0' then -- wait for busy low
rst_clk <= '1' ; state <= 4 ; -- rst high
elsif state = 4 then -- rst low
rst_clk <= '0' ; state <= 5 ;
elsif state = 5 and busyd = '0' then -- wait for busy low
state <= 6 ;
count <= "000" ;
elsif state = 6 then -- hang around
count <= count + 1 ;
if count = "111" then
state <= 7 ;
end if ;
elsif state = 7 then
if BS = TRUE and clk_iserdes_data /= pattern1 then
bslip <= '1' ; -- bitslip needed
state <= 8 ;
count <= "000" ;
else
state <= 9 ;
end if ;
elsif state = 8 then
bslip <= '0' ; -- bitslip low
count <= count + 1 ;
if count = "111" then
state <= 7 ;
end if ;
elsif state = 9 then -- repeat after a delay
state <= 9 ;
end if ;
end if ;
end if ;
end process ;
loop0 : for i in 0 to (S/2 - 1) generate -- Limit the output data bus to the most significant 'S' number of bits
clk_iserdes_data_int(i) <= mdataout(8+i-S/2) ;
end generate ;
iodelay_m : IODELAY2 generic map(
DATA_RATE => "SDR", -- <SDR>, DDR
SIM_TAPDELAY_VALUE => 50, -- nominal tap delay (sim parameter only)
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL", -- "NORMAL", "PCI"
SERDES_MODE => "MASTER", -- <NONE>, MASTER, SLAVE
IDELAY_TYPE => "VARIABLE_FROM_HALF_MAX", -- "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
COUNTER_WRAPAROUND => "STAY_AT_LIMIT", -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN" ) -- "IO", "IDATAIN", "ODATAIN"
port map (
IDATAIN => iob_data_in, -- data from master IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_m, -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => rxioclk_int, -- High speed clock for calibration
IOCLK1 => '0', -- High speed clock for calibration
CLK => rx_bufg_pll_x2_int, -- Fabric clock (GCLK) for control signals
CAL => cal_clk, -- Calibrate enable signal
INC => '0', -- Increment counter
CE => '0', -- Clock Enable
RST => rst_clk, -- Reset delay line to 1/2 max in this case
BUSY => busym) ; -- output signal indicating sync circuit has finished / calibration has finished
iodelay_s : IODELAY2 generic map(
DATA_RATE => "SDR", -- <SDR>, DDR
SIM_TAPDELAY_VALUE => 50, -- nominal tap delay (sim parameter only)
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL", -- "NORMAL", "PCI"
SERDES_MODE => "SLAVE", -- <NONE>, MASTER, SLAVE
IDELAY_TYPE => "FIXED", -- <DEFAULT>, FIXED, VARIABLE
COUNTER_WRAPAROUND => "STAY_AT_LIMIT", -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN") -- "IO", "IDATAIN", "ODATAIN"
port map (
IDATAIN => iob_data_in, -- data from slave IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_s, -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => '0', -- High speed clock for calibration
IOCLK1 => '0', -- High speed clock for calibration
CLK => '0', -- Fabric clock (GCLK) for control signals
CAL => '0', -- Calibrate control signal, never needed as the slave supplies the clock input to the PLL
INC => '0', -- Increment counter
CE => '0', -- Clock Enable
RST => '0', -- Reset delay line
BUSY => open) ; -- output signal indicating sync circuit has finished / calibration has finished
P_clk_bufio2_inst : BUFIO2 generic map(
DIVIDE => 1, -- The DIVCLK divider divide-by value; default 1
DIVIDE_BYPASS => TRUE) -- DIVCLK output sourced from Divider (FALSE) or from I input, by-passing Divider (TRUE); default TRUE
port map (
I => P_clk, -- P_clk input from IDELAY
IOCLK => open, -- Output Clock
DIVCLK => buf_P_clk, -- Output Divided Clock
SERDESSTROBE => open) ; -- Output SERDES strobe (Clock Enable)
P_clk_bufio2fb_inst : BUFIO2FB generic map(
DIVIDE_BYPASS => TRUE) -- DIVCLK output sourced from Divider (FALSE) or from I input, by-passing Divider (TRUE); default TRUE
port map (
I => feedback, -- PLL generated Clock
O => buf_pll_fb_clk) ; -- PLL Output Feedback Clock
iserdes_m : ISERDES2 generic map(
DATA_WIDTH => S/2, -- SERDES word width. This should match the setting in BUFPLL
DATA_RATE => "SDR", -- <SDR>, DDR
BITSLIP_ENABLE => TRUE, -- <FALSE>, TRUE
SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE
INTERFACE_TYPE => "RETIMED") -- NETWORKING, NETWORKING_PIPELINED, <RETIMED>
port map (
D => ddly_m,
CE0 => '1',
CLK0 => rxioclk_int,
CLK1 => '0',
IOCE => rx_serdesstrobe_int,
RST => reset,
CLKDIV => rx_bufg_pll_x2_int,
SHIFTIN => pd_edge,
BITSLIP => bslip,
FABRICOUT => open,
DFB => open,
CFB0 => open,
CFB1 => open,
Q4 => mdataout(7),
Q3 => mdataout(6),
Q2 => mdataout(5),
Q1 => mdataout(4),
VALID => open,
INCDEC => open,
SHIFTOUT => cascade);
iserdes_s : ISERDES2 generic map(
DATA_WIDTH => S/2, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE => "SDR", -- <SDR>, DDR
BITSLIP_ENABLE => TRUE, -- <FALSE>, TRUE
SERDES_MODE => "SLAVE", -- <DEFAULT>, MASTER, SLAVE
INTERFACE_TYPE => "RETIMED") -- NETWORKING, NETWORKING_PIPELINED, <RETIMED>
port map (
D => ddly_s,
CE0 => '1',
CLK0 => rxioclk_int,
CLK1 => '0',
IOCE => rx_serdesstrobe_int,
RST => reset,
CLKDIV => rx_bufg_pll_x2_int,
SHIFTIN => cascade,
BITSLIP => bslip,
FABRICOUT => open,
DFB => P_clk,
CFB0 => feedback,
CFB1 => open,
Q4 => mdataout(3),
Q3 => mdataout(2),
Q2 => mdataout(1),
Q1 => mdataout(0),
VALID => open,
INCDEC => open,
SHIFTOUT => pd_edge);
rx_pll_adv_inst : PLL_ADV generic map(
BANDWIDTH => "OPTIMIZED", -- "high", "low" or "optimized"
CLKFBOUT_MULT => PLLX, -- multiplication factor for all output clocks
CLKFBOUT_PHASE => 0.0, -- phase shift (degrees) of all output clocks
CLKIN1_PERIOD => CLKIN_PERIOD, -- clock period (ns) of input clock on clkin1
CLKIN2_PERIOD => CLKIN_PERIOD, -- clock period (ns) of input clock on clkin2
CLKOUT0_DIVIDE => 1, -- division factor for clkout0 (1 to 128)
CLKOUT0_DUTY_CYCLE => 0.5, -- duty cycle for clkout0 (0.01 to 0.99)
CLKOUT0_PHASE => 0.0, -- phase shift (degrees) for clkout0 (0.0 to 360.0)
CLKOUT1_DIVIDE => S/2, -- division factor for clkout1 (1 to 128)
CLKOUT1_DUTY_CYCLE => 0.5, -- duty cycle for clkout1 (0.01 to 0.99)
CLKOUT1_PHASE => 0.0, -- phase shift (degrees) for clkout1 (0.0 to 360.0)
CLKOUT2_DIVIDE => S, -- division factor for clkout2 (1 to 128)
CLKOUT2_DUTY_CYCLE => 0.5, -- duty cycle for clkout2 (0.01 to 0.99)
CLKOUT2_PHASE => 0.0, -- phase shift (degrees) for clkout2 (0.0 to 360.0)
CLKOUT3_DIVIDE => 7, -- division factor for clkout3 (1 to 128)
CLKOUT3_DUTY_CYCLE => 0.5, -- duty cycle for clkout3 (0.01 to 0.99)
CLKOUT3_PHASE => 0.0, -- phase shift (degrees) for clkout3 (0.0 to 360.0)
CLKOUT4_DIVIDE => 7, -- division factor for clkout4 (1 to 128)
CLKOUT4_DUTY_CYCLE => 0.5, -- duty cycle for clkout4 (0.01 to 0.99)
CLKOUT4_PHASE => 0.0, -- phase shift (degrees) for clkout4 (0.0 to 360.0)
CLKOUT5_DIVIDE => 7, -- division factor for clkout5 (1 to 128)
CLKOUT5_DUTY_CYCLE => 0.5, -- duty cycle for clkout5 (0.01 to 0.99)
CLKOUT5_PHASE => 0.0, -- phase shift (degrees) for clkout5 (0.0 to 360.0)
COMPENSATION => "SOURCE_SYNCHRONOUS", -- "SYSTEM_SYNCHRONOUS", "SOURCE_SYNCHRONOUS", "INTERNAL", "EXTERNAL", "DCM2PLL", "PLL2DCM"
DIVCLK_DIVIDE => PLLD, -- division factor for all clocks (1 to 52)
CLK_FEEDBACK => "CLKOUT0",
REF_JITTER => 0.100) -- input reference jitter (0.000 to 0.999 ui%)
port map (
CLKFBDCM => open, -- output feedback signal used when pll feeds a dcm
CLKFBOUT => open, -- general output feedback signal
CLKOUT0 => rx_pllout_xs, -- x7 clock for transmitter
CLKOUT1 => rx_pllout_x2, -- x2 clock for BUFG
CLKOUT2 => rx_pllout_x1, -- x1 clock for BUFG
CLKOUT3 => open,
CLKOUT4 => open, -- one of six general clock output signals
CLKOUT5 => open, -- one of six general clock output signals
CLKOUTDCM0 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM1 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM2 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM3 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM4 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM5 => open, -- one of six clock outputs to connect to the dcm
DO => open, -- dynamic reconfig data output (16-bits)
DRDY => open, -- dynamic reconfig ready output
LOCKED => rx_pll_lckd, -- active high pll lock signal
CLKFBIN => buf_pll_fb_clk, -- clock feedback input
CLKIN1 => buf_P_clk, -- primary clock input
CLKIN2 => '0', -- secondary clock input
CLKINSEL => '1', -- selects '1' = clkin1, '0' = clkin2
DADDR => "00000", -- dynamic reconfig address input (5-bits)
DCLK => '0', -- dynamic reconfig clock input
DEN => '0', -- dynamic reconfig enable input
DI => "0000000000000000", -- dynamic reconfig data input (16-bits)
DWE => '0', -- dynamic reconfig write enable input
RST => reset, -- asynchronous pll reset
REL => '0') ; -- used to force the state of the PFD outputs (test only)
bufg_pll_x1 : BUFG port map (I => rx_pllout_x1, O => rx_bufg_pll_x1_int) ;
bufg_pll_x2 : BUFG port map (I => rx_pllout_x2, O => rx_bufg_pll_x2_int) ;
rx_bufpll_inst : BUFPLL generic map(
DIVIDE => S/2) -- PLLIN0 divide-by value to produce rx_serdesstrobe (1 to 8); default 1
port map (
PLLIN => rx_pllout_xs, -- PLL Clock input
GCLK => rx_bufg_pll_x2_int, -- Global Clock input
LOCKED => rx_pll_lckd, -- Clock0 locked input
IOCLK => rxioclk_int, -- Output PLL Clock
LOCK => rx_bufplllckd, -- BUFPLL Clock and strobe locked
serdesstrobe => rx_serdesstrobe_int) ; -- Output SERDES strobe
rx_bufpll_lckd <= rx_pll_lckd and rx_bufplllckd ;
not_rx_bufpll_lckd <= not (rx_pll_lckd and rx_bufplllckd) ;
end arch_serdes_1_to_n_clk_pll_s16_diff ;
|
apache-2.0
|
d08a5984cb1b4dba7119502705a3a6e5
| 0.579859 | 3.135225 | false | false | false | false |
Jawanga/ece385final
|
simulation/modelsim/rtl_work/block/_primary.vhd
| 1 | 1,554 |
library verilog;
use verilog.vl_types.all;
entity \block\ is
generic(
Block_X_Min : vl_logic_vector(9 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
Block_X_Max : vl_logic_vector(9 downto 0) := (Hi1, Hi0, Hi0, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1);
Block_Y_Min : vl_logic_vector(9 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
Block_Y_Max : vl_logic_vector(9 downto 0) := (Hi0, Hi1, Hi1, Hi1, Hi0, Hi1, Hi1, Hi1, Hi1, Hi1);
Block_X_Step : vl_logic_vector(9 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi1);
Block_Y_Step : vl_logic_vector(9 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi1)
);
port(
Reset : in vl_logic;
frame_clk : in vl_logic;
Block_X_Center : in vl_logic_vector(9 downto 0);
BlockX : out vl_logic_vector(9 downto 0);
BlockY : out vl_logic_vector(9 downto 0);
BlockS : out vl_logic_vector(9 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of Block_X_Min : constant is 2;
attribute mti_svvh_generic_type of Block_X_Max : constant is 2;
attribute mti_svvh_generic_type of Block_Y_Min : constant is 2;
attribute mti_svvh_generic_type of Block_Y_Max : constant is 2;
attribute mti_svvh_generic_type of Block_X_Step : constant is 2;
attribute mti_svvh_generic_type of Block_Y_Step : constant is 2;
end \block\;
|
apache-2.0
|
6696d26e597a8c1cfb646b2c47f9b322
| 0.58816 | 2.775 | false | false | false | false |
Given-Jiang/Gray_Binarization
|
Gray_Binarization_dspbuilder/reports/Gray_Binarization/Gray_Binarization_example.vhd
| 1 | 2,480 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity Gray_Binarization_example is
port(
Avalon_ST_Sink_data : in STD_LOGIC_VECTOR(23 downto 0);
Avalon_ST_Sink_endofpacket : in STD_LOGIC;
Avalon_MM_Slave_address : in STD_LOGIC_VECTOR(1 downto 0);
Avalon_ST_Source_valid : out STD_LOGIC;
Avalon_MM_Slave_writedata : in STD_LOGIC_VECTOR(31 downto 0);
Avalon_ST_Sink_valid : in STD_LOGIC;
Clock : in STD_LOGIC;
Avalon_ST_Source_endofpacket : out STD_LOGIC;
Avalon_ST_Source_startofpacket : out STD_LOGIC;
Avalon_ST_Source_ready : in STD_LOGIC;
aclr : in STD_LOGIC;
Avalon_MM_Slave_write : in STD_LOGIC;
Avalon_ST_Sink_ready : out STD_LOGIC;
Avalon_ST_Sink_startofpacket : in STD_LOGIC;
Avalon_ST_Source_data : out STD_LOGIC_VECTOR(23 downto 0));
end entity;
architecture rtl of Gray_Binarization_example is
component Gray_Binarization
port(
Avalon_ST_Sink_data : in STD_LOGIC_VECTOR(23 downto 0);
Avalon_ST_Sink_endofpacket : in STD_LOGIC;
Avalon_MM_Slave_address : in STD_LOGIC_VECTOR(1 downto 0);
Avalon_ST_Source_valid : out STD_LOGIC;
Avalon_MM_Slave_writedata : in STD_LOGIC_VECTOR(31 downto 0);
Avalon_ST_Sink_valid : in STD_LOGIC;
Clock : in STD_LOGIC;
Avalon_ST_Source_endofpacket : out STD_LOGIC;
Avalon_ST_Source_startofpacket : out STD_LOGIC;
Avalon_ST_Source_ready : in STD_LOGIC;
aclr : in STD_LOGIC;
Avalon_MM_Slave_write : in STD_LOGIC;
Avalon_ST_Sink_ready : out STD_LOGIC;
Avalon_ST_Sink_startofpacket : in STD_LOGIC;
Avalon_ST_Source_data : out STD_LOGIC_VECTOR(23 downto 0));
end component;
begin
Gray_Binarization_instance :
component Gray_Binarization
port map(
Avalon_ST_Sink_data => Avalon_ST_Sink_data,
Avalon_ST_Sink_endofpacket => Avalon_ST_Sink_endofpacket,
Avalon_MM_Slave_address => Avalon_MM_Slave_address,
Avalon_ST_Source_valid => Avalon_ST_Source_valid,
Avalon_MM_Slave_writedata => Avalon_MM_Slave_writedata,
Avalon_ST_Sink_valid => Avalon_ST_Sink_valid,
Clock => Clock,
Avalon_ST_Source_endofpacket => Avalon_ST_Source_endofpacket,
Avalon_ST_Source_startofpacket => Avalon_ST_Source_startofpacket,
Avalon_ST_Source_ready => Avalon_ST_Source_ready,
aclr => aclr,
Avalon_MM_Slave_write => Avalon_MM_Slave_write,
Avalon_ST_Sink_ready => Avalon_ST_Sink_ready,
Avalon_ST_Sink_startofpacket => Avalon_ST_Sink_startofpacket,
Avalon_ST_Source_data => Avalon_ST_Source_data);
end architecture rtl;
|
mit
|
4afe4adb34c35a87cabda319e3e8545b
| 0.720565 | 3.050431 | false | false | false | false |
nanomolina/MIPS
|
prueba/memory.vhd
| 2 | 1,083 |
library ieee;
use ieee.std_logic_1164.all;
entity memory is
port(
AluOutM, WriteDataM: in std_logic_vector(31 downto 0);
ZeroM, MemWrite, Branch, clk, dump: in std_logic;
ReadDataM: out std_logic_vector(31 downto 0);
PCSrcM: out std_logic);
end entity;
architecture e_arq of memory is
component dmem
port (
a, wd: in std_logic_vector (31 downto 0);
clk,we: in std_logic;
rd: out std_logic_vector (31 downto 0);
dump: in std_logic);
end component;
signal temp1: std_logic_vector(31 downto 0);
signal temp2: std_logic_vector(31 downto 0);
begin
temp1 <= "0000000000000000" & AluOutM(31 downto 16);
temp2 <= "0000000000000000" & WriteDataM(31 downto 16);
dmem1: dmem port map(
a => temp1,
wd => temp2,
clk => clk,
we => MemWrite,
rd => ReadDataM, --salida
dump => dump);
PCSrcM <= ZeroM and Branch; --salida
end architecture;
|
gpl-3.0
|
9b12932241bc7429b8a58d13d8711f26
| 0.547553 | 3.909747 | false | false | false | false |
Jawanga/ece385final
|
simulation/modelsim/usb_system/altera_avalon_mm_clock_crossing_bridge/_primary.vhd
| 2 | 2,332 |
library verilog;
use verilog.vl_types.all;
entity altera_avalon_mm_clock_crossing_bridge is
generic(
DATA_WIDTH : integer := 32;
SYMBOL_WIDTH : integer := 8;
HDL_ADDR_WIDTH : integer := 10;
BURSTCOUNT_WIDTH: integer := 1;
COMMAND_FIFO_DEPTH: integer := 4;
RESPONSE_FIFO_DEPTH: integer := 4;
MASTER_SYNC_DEPTH: integer := 2;
SLAVE_SYNC_DEPTH: integer := 2;
BYTEEN_WIDTH : vl_notype
);
port(
s0_clk : in vl_logic;
s0_reset : in vl_logic;
m0_clk : in vl_logic;
m0_reset : in vl_logic;
s0_waitrequest : out vl_logic;
s0_readdata : out vl_logic_vector;
s0_readdatavalid: out vl_logic;
s0_burstcount : in vl_logic_vector;
s0_writedata : in vl_logic_vector;
s0_address : in vl_logic_vector;
s0_write : in vl_logic;
s0_read : in vl_logic;
s0_byteenable : in vl_logic_vector;
s0_debugaccess : in vl_logic;
m0_waitrequest : in vl_logic;
m0_readdata : in vl_logic_vector;
m0_readdatavalid: in vl_logic;
m0_burstcount : out vl_logic_vector;
m0_writedata : out vl_logic_vector;
m0_address : out vl_logic_vector;
m0_write : out vl_logic;
m0_read : out vl_logic;
m0_byteenable : out vl_logic_vector;
m0_debugaccess : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of DATA_WIDTH : constant is 1;
attribute mti_svvh_generic_type of SYMBOL_WIDTH : constant is 1;
attribute mti_svvh_generic_type of HDL_ADDR_WIDTH : constant is 1;
attribute mti_svvh_generic_type of BURSTCOUNT_WIDTH : constant is 1;
attribute mti_svvh_generic_type of COMMAND_FIFO_DEPTH : constant is 1;
attribute mti_svvh_generic_type of RESPONSE_FIFO_DEPTH : constant is 1;
attribute mti_svvh_generic_type of MASTER_SYNC_DEPTH : constant is 1;
attribute mti_svvh_generic_type of SLAVE_SYNC_DEPTH : constant is 1;
attribute mti_svvh_generic_type of BYTEEN_WIDTH : constant is 3;
end altera_avalon_mm_clock_crossing_bridge;
|
apache-2.0
|
b8a0b159acefc37543bee7d12f10384d
| 0.581475 | 3.517345 | false | false | false | false |
mithro/soft-utmi
|
hdl/third_party/XAPP1064-serdes-macros/VHDL_Source/Macros/serdes_1_to_n_clk_ddr_s8_diff.vhd
| 1 | 6,785 |
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: serdes_1_to_n_clk_ddr_s8_diff.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: August 1 2008
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: 1-bit generic 1:n DDR clock receiver module for serdes factors from 2 to 8 with differential inputs
-- Instantiates necessary BUFIO2 clock buffers
--
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity serdes_1_to_n_clk_ddr_s8_diff is generic (
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
DIFF_TERM : boolean := FALSE) ; -- Enable or disable internal differential termination
port (
clkin_p : in std_logic ; -- Input from LVDS receiver pin
clkin_n : in std_logic ; -- Input from LVDS receiver pin
rxioclkp : out std_logic ; -- IO Clock network
rxioclkn : out std_logic ; -- IO Clock network
rx_serdesstrobe : out std_logic ; -- Parallel data capture strobe
rx_bufg_x1 : out std_logic) ; -- Global clock
end serdes_1_to_n_clk_ddr_s8_diff ;
architecture arch_serdes_1_to_n_clk_ddr_s8_diff of serdes_1_to_n_clk_ddr_s8_diff is
signal ddly_m : std_logic; -- Master output from IODELAY1
signal ddly_s : std_logic; -- Slave output from IODELAY1
signal rx_clk_in : std_logic; --
signal iob_data_in_p : std_logic; --
signal iob_data_in_n : std_logic; --
signal rx_clk_in_p : std_logic; --
signal rx_clk_in_n : std_logic; --
signal rx_bufio2_x1 : std_logic; --
constant RX_SWAP_CLK : std_logic := '0' ; -- pinswap mask for input clock (0 = no swap (default), 1 = swap). Allows input to be connected the wrong way round to ease PCB routing.
begin
iob_clk_in : IBUFDS_DIFF_OUT generic map(
DIFF_TERM => DIFF_TERM)
port map (
I => clkin_p,
IB => clkin_n,
O => rx_clk_in_p,
OB => rx_clk_in_n) ;
iob_data_in_p <= rx_clk_in_p xor RX_SWAP_CLK ; -- Invert clock as required
iob_data_in_n <= rx_clk_in_n xor RX_SWAP_CLK ; -- Invert clock as required
iodelay_m : IODELAY2 generic map(
DATA_RATE => "SDR", -- <SDR>, DDR
SIM_TAPDELAY_VALUE => 49, -- nominal tap delay (sim parameter only)
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL", -- "NORMAL", "PCI"
SERDES_MODE => "MASTER", -- <NONE>, MASTER, SLAVE
IDELAY_TYPE => "FIXED", -- "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
COUNTER_WRAPAROUND => "STAY_AT_LIMIT", -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN") -- "IO", "IDATAIN", "ODATAIN"
port map (
IDATAIN => iob_data_in_p, -- data from master IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_m, -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => '0', -- High speed clock for calibration
IOCLK1 => '0', -- High speed clock for calibration
CLK => '0', -- Fabric clock (GCLK) for control signals
CAL => '0', -- Calibrate enable signal
INC => '0', -- Increment counter
CE => '0', -- Clock Enable
RST => '0', -- Reset delay line to 1/2 max in this case
BUSY => open) ; -- output signal indicating sync circuit has finished / calibration has finished
iodelay_s : IODELAY2 generic map(
DATA_RATE => "SDR", -- <SDR>, DDR
SIM_TAPDELAY_VALUE => 49, -- nominal tap delay (sim parameter only)
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL", -- "NORMAL", "PCI"
SERDES_MODE => "SLAVE", -- <NONE>, MASTER, SLAVE
IDELAY_TYPE => "FIXED", -- "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
COUNTER_WRAPAROUND => "STAY_AT_LIMIT", -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN") -- "IO", "IDATAIN", "ODATAIN"
port map (
IDATAIN => iob_data_in_n, -- data from slave IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_s, -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => '0', -- High speed clock for calibration
IOCLK1 => '0', -- High speed clock for calibration
CLK => '0', -- Fabric clock (GCLK) for control signals
CAL => '0', -- Calibrate control signal, never needed as the slave supplies the clock input to the PLL
INC => '0', -- Increment counter
CE => '0', -- Clock Enable
RST => '0', -- Reset delay line
BUSY => open) ; -- output signal indicating sync circuit has finished / calibration has finished
bufg_pll_x1 : BUFG port map (I => rx_bufio2_x1, O => rx_bufg_x1) ;
bufio2_2clk_inst : BUFIO2_2CLK generic map(
DIVIDE => S) -- The DIVCLK divider divide-by value; default 1
port map (
I => ddly_m, -- Input source clock 0 degrees
IB => ddly_s, -- Input source clock 0 degrees
IOCLK => rxioclkp, -- Output Clock for IO
DIVCLK => rx_bufio2_x1, -- Output Divided Clock
SERDESSTROBE => rx_serdesstrobe) ; -- Output SERDES strobe (Clock Enable)
bufio2_inst : BUFIO2 generic map(
I_INVERT => FALSE, --
DIVIDE_BYPASS => FALSE, --
USE_DOUBLER => FALSE) --
port map (
I => ddly_s, -- N_clk input from IDELAY
IOCLK => rxioclkn, -- Output Clock
DIVCLK => open, -- Output Divided Clock
SERDESSTROBE => open) ; -- Output SERDES strobe (Clock Enable)
end arch_serdes_1_to_n_clk_ddr_s8_diff ;
|
apache-2.0
|
7928293bd3881caccec9ffdecc93d94d
| 0.55549 | 3.08129 | false | false | false | false |
Given-Jiang/Gray_Binarization
|
Gray_Binarization_dspbuilder/db/alt_dspbuilder_decoder.vhd
| 1 | 3,360 |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_decoder is
generic (
DECODE : string := "00000000";
PIPELINE : natural := 0;
WIDTH : natural := 8
);
port (
dec : out std_logic;
clock : in std_logic := '0';
sclr : in std_logic := '0';
data : in std_logic_vector(width-1 downto 0) := (others=>'0');
aclr : in std_logic := '0';
ena : in std_logic := '0'
);
end entity alt_dspbuilder_decoder;
architecture rtl of alt_dspbuilder_decoder is
component alt_dspbuilder_decoder_GNM4LOIHXZ is
generic (
DECODE : string := "01";
PIPELINE : natural := 1;
WIDTH : natural := 2
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
data : in std_logic_vector(2-1 downto 0) := (others=>'0');
dec : out std_logic;
ena : in std_logic := '0';
sclr : in std_logic := '0'
);
end component alt_dspbuilder_decoder_GNM4LOIHXZ;
component alt_dspbuilder_decoder_GNSCEXJCJK is
generic (
DECODE : string := "000000000000000000001111";
PIPELINE : natural := 0;
WIDTH : natural := 24
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
data : in std_logic_vector(24-1 downto 0) := (others=>'0');
dec : out std_logic;
ena : in std_logic := '0';
sclr : in std_logic := '0'
);
end component alt_dspbuilder_decoder_GNSCEXJCJK;
component alt_dspbuilder_decoder_GNEQGKKPXW is
generic (
DECODE : string := "10";
PIPELINE : natural := 1;
WIDTH : natural := 2
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
data : in std_logic_vector(2-1 downto 0) := (others=>'0');
dec : out std_logic;
ena : in std_logic := '0';
sclr : in std_logic := '0'
);
end component alt_dspbuilder_decoder_GNEQGKKPXW;
begin
alt_dspbuilder_decoder_GNM4LOIHXZ_0: if ((DECODE = "01") and (PIPELINE = 1) and (WIDTH = 2)) generate
inst_alt_dspbuilder_decoder_GNM4LOIHXZ_0: alt_dspbuilder_decoder_GNM4LOIHXZ
generic map(DECODE => "01", PIPELINE => 1, WIDTH => 2)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
alt_dspbuilder_decoder_GNSCEXJCJK_1: if ((DECODE = "000000000000000000001111") and (PIPELINE = 0) and (WIDTH = 24)) generate
inst_alt_dspbuilder_decoder_GNSCEXJCJK_1: alt_dspbuilder_decoder_GNSCEXJCJK
generic map(DECODE => "000000000000000000001111", PIPELINE => 0, WIDTH => 24)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
alt_dspbuilder_decoder_GNEQGKKPXW_2: if ((DECODE = "10") and (PIPELINE = 1) and (WIDTH = 2)) generate
inst_alt_dspbuilder_decoder_GNEQGKKPXW_2: alt_dspbuilder_decoder_GNEQGKKPXW
generic map(DECODE => "10", PIPELINE => 1, WIDTH => 2)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
assert not (((DECODE = "01") and (PIPELINE = 1) and (WIDTH = 2)) or ((DECODE = "000000000000000000001111") and (PIPELINE = 0) and (WIDTH = 24)) or ((DECODE = "10") and (PIPELINE = 1) and (WIDTH = 2)))
report "Please run generate again" severity error;
end architecture rtl;
|
mit
|
a4ea3ff5d39645249a909d356a0ffc10
| 0.658631 | 3.193916 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/tests/serialization/TmpVarExampleTernary.vhd
| 1 | 1,431 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY TmpVarExampleTernary IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
c : IN STD_LOGIC;
d : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
e : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
f : OUT STD_LOGIC;
g : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF TmpVarExampleTernary IS
BEGIN
assig_process_d: PROCESS(a, b, c)
VARIABLE tmpTernaryAutoCast_0 : STD_LOGIC;
BEGIN
tmpTernaryAutoCast_0 := b(0);
d(0) <= a WHEN (c = '1') ELSE tmpTernaryAutoCast_0;
END PROCESS;
assig_process_e: PROCESS(a, b, c)
VARIABLE tmpTernaryAutoCast_0 : STD_LOGIC_VECTOR(0 DOWNTO 0);
BEGIN
tmpTernaryAutoCast_0(0) := a;
e <= b WHEN (c = '1') ELSE tmpTernaryAutoCast_0;
END PROCESS;
assig_process_f: PROCESS(a, b, c)
VARIABLE tmpTernaryAutoCast_0 : STD_LOGIC;
BEGIN
tmpTernaryAutoCast_0 := b(0);
f <= a WHEN (c = '1') ELSE tmpTernaryAutoCast_0;
END PROCESS;
assig_process_g: PROCESS(a, b, c)
VARIABLE tmpTernaryAutoCast_0 : STD_LOGIC_VECTOR(0 DOWNTO 0);
VARIABLE tmpTypeConv_0 : STD_LOGIC_VECTOR(0 DOWNTO 0);
BEGIN
tmpTernaryAutoCast_0(0) := a;
tmpTypeConv_0 := b WHEN (c = '1') ELSE tmpTernaryAutoCast_0;
g <= tmpTypeConv_0(0);
END PROCESS;
END ARCHITECTURE;
|
mit
|
cff450d42190ed7a14b099c665c863e3
| 0.609364 | 3.604534 | false | false | false | false |
lnls-dig/bpm-gw
|
hdl/top/ml_605/dbe_bpm_fmc130m_4ch/dbe_bpm_fmc130m_4ch.vhd
| 1 | 55,716 |
------------------------------------------------------------------------------
-- Title : Top FMC516 design
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-02-25
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Top design for testing the integration/control of the FMC516
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-02-25 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Memory core generator
use work.gencores_pkg.all;
-- Custom Wishbone Modules
use work.ifc_wishbone_pkg.all;
-- Wishbone stream modules and interface
use work.wb_stream_generic_pkg.all;
-- Ethernet MAC Modules and SDB structure
use work.ethmac_pkg.all;
-- Wishbone Fabric interface
use work.wr_fabric_pkg.all;
-- Etherbone slave core
use work.etherbone_pkg.all;
-- FMC516 definitions
use work.fmc_adc_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity dbe_bpm_fmc130m_4ch is
port(
-----------------------------------------
-- Clocking pins
-----------------------------------------
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
-----------------------------------------
-- Reset Button
-----------------------------------------
sys_rst_button_i : in std_logic;
-----------------------------------------
-- UART pins
-----------------------------------------
rs232_txd_o : out std_logic;
rs232_rxd_i : in std_logic;
-----------------------------------------
-- PHY pins
-----------------------------------------
-- Clock and resets to PHY (GMII). Not used in MII mode (10/100)
mgtx_clk_o : out std_logic;
mrstn_o : out std_logic;
-- PHY TX
mtx_clk_pad_i : in std_logic;
mtxd_pad_o : out std_logic_vector(3 downto 0);
mtxen_pad_o : out std_logic;
mtxerr_pad_o : out std_logic;
-- PHY RX
mrx_clk_pad_i : in std_logic;
mrxd_pad_i : in std_logic_vector(3 downto 0);
mrxdv_pad_i : in std_logic;
mrxerr_pad_i : in std_logic;
mcoll_pad_i : in std_logic;
mcrs_pad_i : in std_logic;
-- MII
mdc_pad_o : out std_logic;
md_pad_b : inout std_logic;
-----------------------------
-- FMC130m_4ch ports
-----------------------------
-- ADC LTC2208 interface
fmc_adc_pga_o : out std_logic;
fmc_adc_shdn_o : out std_logic;
fmc_adc_dith_o : out std_logic;
fmc_adc_rand_o : out std_logic;
-- ADC0 LTC2208
fmc_adc0_clk_i : in std_logic;
fmc_adc0_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0);
fmc_adc0_of_i : in std_logic; -- Unused
-- ADC1 LTC2208
fmc_adc1_clk_i : in std_logic;
fmc_adc1_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0);
fmc_adc1_of_i : in std_logic; -- Unused
-- ADC2 LTC2208
fmc_adc2_clk_i : in std_logic;
fmc_adc2_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0);
fmc_adc2_of_i : in std_logic; -- Unused
-- ADC3 LTC2208
fmc_adc3_clk_i : in std_logic;
fmc_adc3_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0);
fmc_adc3_of_i : in std_logic; -- Unused
-- FMC General Status
fmc_prsnt_i : in std_logic;
fmc_pg_m2c_i : in std_logic;
--fmc_clk_dir_i : in std_logic;, -- not supported on Kintex7 KC705 board
-- Trigger
fmc_trig_dir_o : out std_logic;
fmc_trig_term_o : out std_logic;
fmc_trig_val_p_b : inout std_logic;
fmc_trig_val_n_b : inout std_logic;
-- Si571 clock gen
si571_scl_pad_b : inout std_logic;
si571_sda_pad_b : inout std_logic;
fmc_si571_oe_o : out std_logic;
-- AD9510 clock distribution PLL
spi_ad9510_cs_o : out std_logic;
spi_ad9510_sclk_o : out std_logic;
spi_ad9510_mosi_o : out std_logic;
spi_ad9510_miso_i : in std_logic;
fmc_pll_function_o : out std_logic;
fmc_pll_status_i : in std_logic;
-- AD9510 clock copy
fmc_fpga_clk_p_i : in std_logic;
fmc_fpga_clk_n_i : in std_logic;
-- Clock reference selection (TS3USB221)
fmc_clk_sel_o : out std_logic;
-- EEPROM
eeprom_scl_pad_b : inout std_logic;
eeprom_sda_pad_b : inout std_logic;
-- Temperature monitor
-- LM75AIMM
lm75_scl_pad_b : inout std_logic;
lm75_sda_pad_b : inout std_logic;
fmc_lm75_temp_alarm_i : in std_logic;
-- FMC LEDs
fmc_led1_o : out std_logic;
fmc_led2_o : out std_logic;
fmc_led3_o : out std_logic;
-----------------------------------------
-- General board status
-----------------------------------------
fmc_mmcm_lock_led_o : out std_logic;
fmc_pll_status_led_o : out std_logic;
-----------------------------------------
-- Button pins
-----------------------------------------
buttons_i : in std_logic_vector(7 downto 0);
-----------------------------------------
-- User LEDs
-----------------------------------------
-- Directional leds
--led_south_o : out std_logic;
--led_east_o : out std_logic;
--led_north_o : out std_logic;
-- GPIO leds
leds_o : out std_logic_vector(7 downto 0)
);
end dbe_bpm_fmc130m_4ch;
architecture rtl of dbe_bpm_fmc130m_4ch is
-- Top crossbar layout
-- Number of slaves
constant c_slaves : natural := 9;
-- General Dual-port memory, Buffer Single-port memory, DMA control port, MAC,
--Etherbone, FMC516, Peripherals
-- Number of masters
--constant c_masters : natural := 9; -- LM32 master, Data + Instruction,
--DMA read+write master, Ethernet MAC, Ethernet MAC adapter read+write master, Etherbone, RS232-Syscon
constant c_masters : natural := 7; -- RS232-Syscon,
--DMA read+write master, Ethernet MAC, Ethernet MAC adapter read+write master, Etherbone
constant c_dpram_size : natural := 131072/4; -- in 32-bit words (128KB)
--constant c_dpram_ethbuf_size : natural := 32768/4; -- in 32-bit words (32KB)
constant c_dpram_ethbuf_size : natural := 65536/4; -- in 32-bit words (64KB)
-- GPIO num pinscalc
constant c_leds_num_pins : natural := 8;
constant c_buttons_num_pins : natural := 8;
-- Counter width. It willl count up to 2^32 clock cycles
constant c_counter_width : natural := 32;
-- TICs counter period. 100MHz clock -> msec granularity
constant c_tics_cntr_period : natural := 100000;
-- Number of reset clock cycles (FF)
constant c_button_rst_width : natural := 255;
-- number of the ADC reference clock used for all downstream
-- FPGA logic
constant c_adc_ref_clk : natural := 1;
constant c_xwb_etherbone_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", --32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"0000000000000651", -- GSI
device_id => x"68202b22",
version => x"00000001",
date => x"20120912",
name => "GSI_ETHERBONE_CFG ")));
constant c_xwb_ethmac_adapter_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", --32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"1000000000001215", -- LNLS
device_id => x"2ff9a28e",
version => x"00000001",
date => x"20130701",
name => "ETHMAC_ADAPTER ")));
-- FMC130m_4ch layout. Size (0x00000FFF) is larger than needed. Just to be sure
-- no address overlaps will occur
--constant c_fmc516_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000800");
-- FMC130m_4ch
constant c_fmc130m_4ch_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000800");
-- General peripherals layout. UART, LEDs (GPIO), Buttons (GPIO) and Tics counter
constant c_periph_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000400");
-- WB SDB (Self describing bus) layout
constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) :=
( 0 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"00000000"), -- 128KB RAM
1 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"10000000"), -- Second port to the same memory
2 => f_sdb_embed_device(f_xwb_dpram(c_dpram_ethbuf_size),
x"20000000"), -- 64KB RAM
3 => f_sdb_embed_device(c_xwb_dma_sdb, x"30004000"), -- DMA control port
4 => f_sdb_embed_device(c_xwb_ethmac_sdb, x"30005000"), -- Ethernet MAC control port
5 => f_sdb_embed_device(c_xwb_ethmac_adapter_sdb, x"30006000"), -- Ethernet Adapter control port
6 => f_sdb_embed_device(c_xwb_etherbone_sdb, x"30007000"), -- Etherbone control port
7 => f_sdb_embed_bridge(c_fmc130m_4ch_bridge_sdb, x"30010000"), -- FMC130m_4ch control port
8 => f_sdb_embed_bridge(c_periph_bridge_sdb, x"30020000") -- General peripherals control port
);
-- Self Describing Bus ROM Address. It will be an addressed slave as well
constant c_sdb_address : t_wishbone_address := x"30000000";
-- Crossbar master/slave arrays
signal cbar_slave_i : t_wishbone_slave_in_array (c_masters-1 downto 0);
signal cbar_slave_o : t_wishbone_slave_out_array(c_masters-1 downto 0);
signal cbar_master_i : t_wishbone_master_in_array(c_slaves-1 downto 0);
signal cbar_master_o : t_wishbone_master_out_array(c_slaves-1 downto 0);
-- LM32 signals
signal clk_sys : std_logic;
signal lm32_interrupt : std_logic_vector(31 downto 0);
signal lm32_rstn : std_logic;
-- Clocks and resets signals
signal locked : std_logic;
signal clk_sys_rstn : std_logic;
signal clk_sys_rst : std_logic;
signal rst_button_sys_pp : std_logic;
signal rst_button_sys : std_logic;
signal rst_button_sys_n : std_logic;
signal rs232_rstn : std_logic;
-- Only one clock domain
signal reset_clks : std_logic_vector(0 downto 0);
signal reset_rstn : std_logic_vector(0 downto 0);
-- 200 Mhz clocck for iodelay_ctrl
signal clk_200mhz : std_logic;
-- Global Clock Single ended
signal sys_clk_gen : std_logic;
-- Ethernet MAC signals
signal ethmac_int : std_logic;
signal ethmac_md_in : std_logic;
signal ethmac_md_out : std_logic;
signal ethmac_md_oe : std_logic;
signal mtxd_pad_int : std_logic_vector(3 downto 0);
signal mtxen_pad_int : std_logic;
signal mtxerr_pad_int : std_logic;
signal mdc_pad_int : std_logic;
-- Ethrnet MAC adapter signals
signal irq_rx_done : std_logic;
signal irq_tx_done : std_logic;
-- Etherbone signals
signal wb_ebone_out : t_wishbone_master_out;
signal wb_ebone_in : t_wishbone_master_in;
signal eb_src_i : t_wrf_source_in;
signal eb_src_o : t_wrf_source_out;
signal eb_snk_i : t_wrf_sink_in;
signal eb_snk_o : t_wrf_sink_out;
-- DMA signals
signal dma_int : std_logic;
-- FMC130m_4ch Signals
signal wbs_fmc130m_4ch_in_array : t_wbs_source_in16_array(c_num_adc_channels-1 downto 0);
signal wbs_fmc130m_4ch_out_array : t_wbs_source_out16_array(c_num_adc_channels-1 downto 0);
signal fmc_mmcm_lock_int : std_logic;
signal fmc_pll_status_int : std_logic;
signal fmc_led1_int : std_logic;
signal fmc_led2_int : std_logic;
signal fmc_led3_int : std_logic;
signal fmc_130m_4ch_clk : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc_130m_4ch_clk2x : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc_130m_4ch_data : std_logic_vector(c_num_adc_channels*c_num_adc_bits-1 downto 0);
signal fmc_130m_4ch_data_valid : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc_debug : std_logic;
signal reset_adc_counter : unsigned(6 downto 0) := (others => '0');
signal fmc_130m_4ch_rst_n : std_logic_vector(c_num_adc_channels-1 downto 0);
-- fmc130m_4ch Debug
signal fmc130m_4ch_debug_valid_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc130m_4ch_debug_full_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc130m_4ch_debug_empty_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal adc_dly_debug_int : t_adc_fn_dly_array(c_num_adc_channels-1 downto 0);
signal sys_spi_clk_int : std_logic;
--signal sys_spi_data_int : std_logic;
signal sys_spi_dout_int : std_logic;
signal sys_spi_din_int : std_logic;
signal sys_spi_miosio_oe_n_int : std_logic;
signal sys_spi_cs_adc0_n_int : std_logic;
signal sys_spi_cs_adc1_n_int : std_logic;
signal sys_spi_cs_adc2_n_int : std_logic;
signal sys_spi_cs_adc3_n_int : std_logic;
signal lmk_lock_int : std_logic;
signal lmk_sync_int : std_logic;
signal lmk_uwire_latch_en_int : std_logic;
signal lmk_uwire_data_int : std_logic;
signal lmk_uwire_clock_int : std_logic;
signal fmc_reset_adcs_n_int : std_logic;
signal fmc_reset_adcs_n_out : std_logic;
-- GPIO LED signals
signal gpio_slave_led_o : t_wishbone_slave_out;
signal gpio_slave_led_i : t_wishbone_slave_in;
signal gpio_leds_int : std_logic_vector(c_leds_num_pins-1 downto 0);
-- signal leds_gpio_dummy_in : std_logic_vector(c_leds_num_pins-1 downto 0);
-- GPIO Button signals
signal gpio_slave_button_o : t_wishbone_slave_out;
signal gpio_slave_button_i : t_wishbone_slave_in;
-- Counter signal
--signal s_counter : unsigned(c_counter_width-1 downto 0);
-- 100MHz period or 1 second
--constant s_counter_full : integer := 100000000;
-- Chipscope control signals
signal CONTROL0 : std_logic_vector(35 downto 0);
signal CONTROL1 : std_logic_vector(35 downto 0);
signal CONTROL2 : std_logic_vector(35 downto 0);
signal CONTROL3 : std_logic_vector(35 downto 0);
-- Chipscope ILA 0 signals
signal TRIG_ILA0_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_3 : std_logic_vector(31 downto 0);
-- Chipscope ILA 1 signals
signal TRIG_ILA1_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_3 : std_logic_vector(31 downto 0);
-- Chipscope ILA 2 signals
signal TRIG_ILA2_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA2_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA2_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA2_3 : std_logic_vector(31 downto 0);
-- Chipscope ILA 3 signals
signal TRIG_ILA3_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA3_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA3_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA3_3 : std_logic_vector(31 downto 0);
---------------------------
-- Components --
---------------------------
-- Clock generation
component clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic
);
end component;
-- Xilinx Megafunction
component sys_pll is
port(
rst_i : in std_logic := '0';
clk_i : in std_logic := '0';
clk0_o : out std_logic;
clk1_o : out std_logic;
locked_o : out std_logic
);
end component;
-- Xilinx Chipscope Controller
component chipscope_icon_1_port
port (
CONTROL0 : inout std_logic_vector(35 downto 0)
);
end component;
-- Xilinx Chipscope Controller 2 port
--component chipscope_icon_2_port
--port (
-- CONTROL0 : inout std_logic_vector(35 downto 0);
-- CONTROL1 : inout std_logic_vector(35 downto 0)
--);
--end component;
component chipscope_icon_4_port
port (
CONTROL0 : inout std_logic_vector(35 downto 0);
CONTROL1 : inout std_logic_vector(35 downto 0);
CONTROL2 : inout std_logic_vector(35 downto 0);
CONTROL3 : inout std_logic_vector(35 downto 0)
);
end component;
-- Xilinx Chipscope Logic Analyser
component chipscope_ila
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0)
);
end component;
-- Functions
-- Generate dummy (0) values
function f_zeros(size : integer)
return std_logic_vector is
begin
return std_logic_vector(to_unsigned(0, size));
end f_zeros;
begin
-- Clock generation
cmp_clk_gen : clk_gen
port map (
sys_clk_p_i => sys_clk_p_i,
sys_clk_n_i => sys_clk_n_i,
sys_clk_o => sys_clk_gen
);
-- Obtain core locking and generate necessary clocks
cmp_sys_pll_inst : sys_pll
port map (
rst_i => '0',
clk_i => sys_clk_gen,
clk0_o => clk_sys, -- 100MHz locked clock
clk1_o => clk_200mhz, -- 200MHz locked clock
locked_o => locked -- '1' when the PLL has locked
);
-- Reset synchronization. Hold reset line until few locked cycles have passed.
cmp_reset : gc_reset
generic map(
g_clocks => 1 -- CLK_SYS
)
port map(
free_clk_i => sys_clk_gen,
locked_i => locked,
clks_i => reset_clks,
rstn_o => reset_rstn
);
reset_clks(0) <= clk_sys;
--clk_sys_rstn <= reset_rstn(0) and rst_button_sys_n;
clk_sys_rstn <= reset_rstn(0) and rst_button_sys_n and rs232_rstn;
clk_sys_rst <= not clk_sys_rstn;
mrstn_o <= clk_sys_rstn;
-- Generate button reset synchronous to each clock domain
-- Detect button positive edge of clk_sys
cmp_button_sys_ffs : gc_sync_ffs
port map (
clk_i => clk_sys,
rst_n_i => '1',
data_i => sys_rst_button_i,
ppulse_o => rst_button_sys_pp
);
-- Generate the reset signal based on positive edge
-- of synched sys_rst_button_i
cmp_button_sys_rst : gc_extend_pulse
generic map (
g_width => c_button_rst_width
)
port map(
clk_i => clk_sys,
rst_n_i => '1',
pulse_i => rst_button_sys_pp,
extended_o => rst_button_sys
);
rst_button_sys_n <= not rst_button_sys;
-- The top-most Wishbone B.4 crossbar
cmp_interconnect : xwb_sdb_crossbar
generic map(
g_num_masters => c_masters,
g_num_slaves => c_slaves,
g_registered => true,
g_wraparound => true, -- Should be true for nested buses
g_layout => c_layout,
g_sdb_addr => c_sdb_address
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- Master connections (INTERCON is a slave)
slave_i => cbar_slave_i,
slave_o => cbar_slave_o,
-- Slave connections (INTERCON is a master)
master_i => cbar_master_i,
master_o => cbar_master_o
);
-- The LM32 is master 0+1
lm32_rstn <= clk_sys_rstn;
--cmp_lm32 : xwb_lm32
--generic map(
-- g_profile => "medium_icache_debug"
--) -- Including JTAG and I-cache (no divide)
--port map(
-- clk_sys_i => clk_sys,
-- rst_n_i => lm32_rstn,
-- irq_i => lm32_interrupt,
-- dwb_o => cbar_slave_i(0), -- Data bus
-- dwb_i => cbar_slave_o(0),
-- iwb_o => cbar_slave_i(1), -- Instruction bus
-- iwb_i => cbar_slave_o(1)
--);
-- Interrupt '0' is Ethmac.
-- Interrupt '1' is DMA completion.
-- Interrupt '2' is Button(0).
-- Interrupt '3' is Ethernet Adapter RX completion.
-- Interrupt '4' is Ethernet Adapter TX completion.
-- Interrupts 31 downto 5 are disabled
lm32_interrupt <= (0 => ethmac_int, 1 => dma_int, 2 => not buttons_i(0), 3 => irq_rx_done,
4 => irq_tx_done, others => '0');
cmp_xwb_rs232_syscon : xwb_rs232_syscon
generic map (
g_ma_interface_mode => PIPELINED,
g_ma_address_granularity => BYTE
)
port map(
-- WISHBONE common
wb_clk_i => clk_sys,
wb_rstn_i => '1', -- No need for resetting the controller
-- External ports
rs232_rxd_i => rs232_rxd_i,
rs232_txd_o => rs232_txd_o,
-- Reset to FPGA logic
rstn_o => rs232_rstn,
-- WISHBONE master
wb_master_i => cbar_slave_o(0),
wb_master_o => cbar_slave_i(0)
);
-- A DMA controller is master 2+3, slave 3, and interrupt 1
cmp_dma : xwb_dma
port map(
clk_i => clk_sys,
rst_n_i => clk_sys_rstn,
slave_i => cbar_master_o(3),
slave_o => cbar_master_i(3),
r_master_i => cbar_slave_o(1),
r_master_o => cbar_slave_i(1),
w_master_i => cbar_slave_o(2),
w_master_o => cbar_slave_i(2),
interrupt_o => dma_int
);
-- Slave 0+1 is the RAM. Load a input file containing the embedded software
cmp_ram : xwb_dpram
generic map(
g_size => c_dpram_size, -- must agree with sw/target/lm32/ram.ld:LENGTH / 4
--g_init_file => "../../../embedded-sw/dbe.ram",
--"../../top/ml_605/dbe_bpm_simple/sw/main.ram",
--g_must_have_init_file => true,
g_must_have_init_file => false,
g_slave1_interface_mode => PIPELINED,
g_slave2_interface_mode => PIPELINED,
g_slave1_granularity => BYTE,
g_slave2_granularity => BYTE
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- First port connected to the crossbar
slave1_i => cbar_master_o(0),
slave1_o => cbar_master_i(0),
-- Second port connected to the crossbar
slave2_i => cbar_master_o(1),
slave2_o => cbar_master_i(1)
);
-- Slave 2 is the RAM Buffer for Ethernet MAC.
cmp_ethmac_buf_ram : xwb_dpram
generic map(
g_size => c_dpram_ethbuf_size,
g_init_file => "",
g_must_have_init_file => false,
g_slave1_interface_mode => CLASSIC,
--g_slave2_interface_mode => PIPELINED,
g_slave1_granularity => BYTE
--g_slave2_granularity => BYTE
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- First port connected to the crossbar
slave1_i => cbar_master_o(2),
slave1_o => cbar_master_i(2),
-- Second port connected to the crossbar
slave2_i => cc_dummy_slave_in, -- CYC always low
slave2_o => open
);
-- The Ethernet MAC is master 4, slave 4
cmp_xwb_ethmac : xwb_ethmac
generic map (
--g_ma_interface_mode => PIPELINED,
g_ma_interface_mode => CLASSIC, -- NOT used for now
--g_ma_address_granularity => WORD,
g_ma_address_granularity => BYTE, -- NOT used for now
g_sl_interface_mode => PIPELINED,
--g_sl_interface_mode => CLASSIC,
--g_sl_address_granularity => WORD
g_sl_address_granularity => BYTE
)
port map(
-- WISHBONE common
wb_clk_i => clk_sys,
wb_rst_i => clk_sys_rst,
-- WISHBONE slave
wb_slave_in => cbar_master_o(4),
wb_slave_out => cbar_master_i(4),
-- WISHBONE master
wb_master_in => cbar_slave_o(3),
wb_master_out => cbar_slave_i(3),
-- PHY TX
mtx_clk_pad_i => mtx_clk_pad_i,
--mtxd_pad_o => mtxd_pad_o,
mtxd_pad_o => mtxd_pad_int,
--mtxen_pad_o => mtxen_pad_o,
mtxen_pad_o => mtxen_pad_int,
--mtxerr_pad_o => mtxerr_pad_o,
mtxerr_pad_o => mtxerr_pad_int,
-- PHY RX
mrx_clk_pad_i => mrx_clk_pad_i,
mrxd_pad_i => mrxd_pad_i,
mrxdv_pad_i => mrxdv_pad_i,
mrxerr_pad_i => mrxerr_pad_i,
mcoll_pad_i => mcoll_pad_i,
mcrs_pad_i => mcrs_pad_i,
-- MII
--mdc_pad_o => mdc_pad_o,
mdc_pad_o => mdc_pad_int,
md_pad_i => ethmac_md_in,
md_pad_o => ethmac_md_out,
md_padoe_o => ethmac_md_oe,
-- Interrupt
int_o => ethmac_int
);
-- Tri-state buffer for MII config
md_pad_b <= ethmac_md_out when ethmac_md_oe = '1' else 'Z';
ethmac_md_in <= md_pad_b;
mtxd_pad_o <= mtxd_pad_int;
mtxen_pad_o <= mtxen_pad_int;
mtxerr_pad_o <= mtxerr_pad_int;
mdc_pad_o <= mdc_pad_int;
-- The Ethernet MAC Adapter is master 5+6, slave 5
cmp_xwb_ethmac_adapter : xwb_ethmac_adapter
port map(
clk_i => clk_sys,
rstn_i => clk_sys_rstn,
wb_slave_o => cbar_master_i(5),
wb_slave_i => cbar_master_o(5),
tx_ram_o => cbar_slave_i(4),
tx_ram_i => cbar_slave_o(4),
rx_ram_o => cbar_slave_i(5),
rx_ram_i => cbar_slave_o(5),
rx_eb_o => eb_snk_i,
rx_eb_i => eb_snk_o,
tx_eb_o => eb_src_i,
tx_eb_i => eb_src_o,
irq_tx_done_o => irq_tx_done,
irq_rx_done_o => irq_rx_done
);
-- The Etherbone is slave 6
cmp_eb_slave_core : eb_slave_core
generic map(
g_sdb_address => x"00000000" & c_sdb_address
)
port map
(
clk_i => clk_sys,
nRst_i => clk_sys_rstn,
-- EB streaming sink
snk_i => eb_snk_i,
snk_o => eb_snk_o,
-- EB streaming source
src_i => eb_src_i,
src_o => eb_src_o,
-- WB slave - Cfg IF
cfg_slave_o => cbar_master_i(6),
cfg_slave_i => cbar_master_o(6),
-- WB master - Bus IF
master_o => wb_ebone_out,
master_i => wb_ebone_in
);
cbar_slave_i(6) <= wb_ebone_out;
wb_ebone_in <= cbar_slave_o(6);
-- The FMC130M_4CH is slave 7
cmp_xwb_fmc130m_4ch : xwb_fmc130m_4ch
generic map(
g_fpga_device => "VIRTEX6",
g_interface_mode => PIPELINED,
--g_address_granularity => WORD,
g_address_granularity => BYTE,
--g_adc_clk_period_values => default_adc_clk_period_values,
g_adc_clk_period_values => (8.88, 8.88, 8.88, 8.88),
--g_use_clk_chains => default_clk_use_chain,
-- using clock1 from fmc130m_4ch (CLK2_ M2C_P, CLK2_ M2C_M pair)
-- using clock0 from fmc130m_4ch.
-- BUFIO can drive half-bank only, not the full IO bank
g_use_clk_chains => "1111",
g_with_bufio_clk_chains => "0000",
g_with_bufr_clk_chains => "1111",
g_use_data_chains => "1111",
--g_map_clk_data_chains => (-1,-1,-1,-1),
-- Clock 1 is the adc reference clock
g_ref_clk => c_adc_ref_clk,
g_packet_size => 32,
g_sim => 0
)
port map(
sys_clk_i => clk_sys,
sys_rst_n_i => clk_sys_rstn,
sys_clk_200Mhz_i => clk_200mhz,
-----------------------------
-- Wishbone Control Interface signals
-----------------------------
wb_slv_i => cbar_master_o(7),
wb_slv_o => cbar_master_i(7),
-----------------------------
-- External ports
-----------------------------
-- ADC LTC2208 interface
fmc_adc_pga_o => fmc_adc_pga_o,
fmc_adc_shdn_o => fmc_adc_shdn_o,
fmc_adc_dith_o => fmc_adc_dith_o,
fmc_adc_rand_o => fmc_adc_rand_o,
-- ADC0 LTC2208
fmc_adc0_clk_i => fmc_adc0_clk_i,
fmc_adc0_data_i => fmc_adc0_data_i,
fmc_adc0_of_i => fmc_adc0_of_i,
-- ADC1 LTC2208
fmc_adc1_clk_i => fmc_adc1_clk_i,
fmc_adc1_data_i => fmc_adc1_data_i,
fmc_adc1_of_i => fmc_adc1_of_i,
-- ADC2 LTC2208
fmc_adc2_clk_i => fmc_adc2_clk_i,
fmc_adc2_data_i => fmc_adc2_data_i,
fmc_adc2_of_i => fmc_adc2_of_i,
-- ADC3 LTC2208
fmc_adc3_clk_i => fmc_adc3_clk_i,
fmc_adc3_data_i => fmc_adc3_data_i,
fmc_adc3_of_i => fmc_adc3_of_i,
-- FMC General Status
fmc_prsnt_i => fmc_prsnt_i,
fmc_pg_m2c_i => fmc_pg_m2c_i,
-- Trigger
fmc_trig_dir_o => fmc_trig_dir_o,
fmc_trig_term_o => fmc_trig_term_o,
fmc_trig_val_p_b => fmc_trig_val_p_b,
fmc_trig_val_n_b => fmc_trig_val_n_b,
-- Si571 clock gen
si571_scl_pad_b => si571_scl_pad_b,
si571_sda_pad_b => si571_sda_pad_b,
fmc_si571_oe_o => fmc_si571_oe_o,
-- AD9510 clock distribution PLL
spi_ad9510_cs_o => spi_ad9510_cs_o,
spi_ad9510_sclk_o => spi_ad9510_sclk_o,
spi_ad9510_mosi_o => spi_ad9510_mosi_o,
spi_ad9510_miso_i => spi_ad9510_miso_i,
fmc_pll_function_o => fmc_pll_function_o,
fmc_pll_status_i => fmc_pll_status_i,
-- AD9510 clock copy
fmc_fpga_clk_p_i => fmc_fpga_clk_p_i,
fmc_fpga_clk_n_i => fmc_fpga_clk_n_i,
-- Clock reference selection (TS3USB221)
fmc_clk_sel_o => fmc_clk_sel_o,
-- EEPROM
eeprom_scl_pad_b => eeprom_scl_pad_b,
eeprom_sda_pad_b => eeprom_sda_pad_b,
-- Temperature monitor
-- LM75AIMM
lm75_scl_pad_b => lm75_scl_pad_b,
lm75_sda_pad_b => lm75_sda_pad_b,
fmc_lm75_temp_alarm_i => fmc_lm75_temp_alarm_i,
-- FMC LEDs
fmc_led1_o => fmc_led1_int,
fmc_led2_o => fmc_led2_int,
fmc_led3_o => fmc_led3_int,
-----------------------------
-- Optional external reference clock ports
-----------------------------
fmc_ext_ref_clk_i => '0', -- Unused
fmc_ext_ref_clk2x_i => '0', -- Unused
fmc_ext_ref_mmcm_locked_i => '0', -- Unused
-----------------------------
-- ADC output signals. Continuous flow
-----------------------------
adc_clk_o => fmc_130m_4ch_clk,
adc_clk2x_o => fmc_130m_4ch_clk2x,
adc_rst_n_o => fmc_130m_4ch_rst_n,
adc_data_o => fmc_130m_4ch_data,
adc_data_valid_o => fmc_130m_4ch_data_valid,
-----------------------------
-- General ADC output signals and status
-----------------------------
-- Trigger to other FPGA logic
trig_hw_o => open,
trig_hw_i => '0',
-- General board status
fmc_mmcm_lock_o => fmc_mmcm_lock_int,
fmc_pll_status_o => fmc_pll_status_int,
-----------------------------
-- Wishbone Streaming Interface Source
-----------------------------
wbs_source_i => wbs_fmc130m_4ch_in_array,
wbs_source_o => wbs_fmc130m_4ch_out_array,
adc_dly_debug_o => adc_dly_debug_int,
fifo_debug_valid_o => fmc130m_4ch_debug_valid_int,
fifo_debug_full_o => fmc130m_4ch_debug_full_int,
fifo_debug_empty_o => fmc130m_4ch_debug_empty_int
);
gen_wbs_dummy_signals : for i in 0 to c_num_adc_channels-1 generate
wbs_fmc130m_4ch_in_array(i) <= cc_dummy_src_com_in;
end generate;
fmc_mmcm_lock_led_o <= fmc_mmcm_lock_int;
fmc_pll_status_led_o <= fmc_pll_status_int;
fmc_led1_o <= fmc_led1_int;
fmc_led2_o <= fmc_led2_int;
fmc_led3_o <= fmc_led3_int;
--led_south_o <= fmc_led1_int;
--led_east_o <= fmc_led2_int;
--led_north_o <= fmc_led3_int;
-- The board peripherals components is slave 8
cmp_xwb_dbe_periph : xwb_dbe_periph
generic map(
-- NOT used!
--g_interface_mode : t_wishbone_interface_mode := CLASSIC;
-- NOT used!
--g_address_granularity : t_wishbone_address_granularity := WORD;
g_cntr_period => c_tics_cntr_period,
g_num_leds => c_leds_num_pins,
g_num_buttons => c_buttons_num_pins
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- UART
uart_rxd_i => '0',
uart_txd_o => open,
-- LEDs
led_out_o => gpio_leds_int,
led_in_i => gpio_leds_int,
led_oen_o => open,
-- Buttons
button_out_o => open,
button_in_i => buttons_i,
button_oen_o => open,
-- Wishbone
slave_i => cbar_master_o(8),
slave_o => cbar_master_i(8)
);
leds_o <= gpio_leds_int;
---- Xilinx Chipscope
cmp_chipscope_icon_0 : chipscope_icon_4_port
port map (
CONTROL0 => CONTROL0,
CONTROL1 => CONTROL1,
CONTROL2 => CONTROL2,
CONTROL3 => CONTROL3
);
cmp_chipscope_ila_0_fmc130m_4ch_clk0 : chipscope_ila
port map (
CONTROL => CONTROL0,
--CLK => clk_sys,
CLK => fmc_130m_4ch_clk(c_adc_ref_clk),
TRIG0 => TRIG_ILA0_0,
TRIG1 => TRIG_ILA0_1,
TRIG2 => TRIG_ILA0_2,
TRIG3 => TRIG_ILA0_3
);
-- fmc130m_4ch WBS master output data
--TRIG_ILA0_0 <= wbs_fmc130m_4ch_out_array(3).dat &
-- wbs_fmc130m_4ch_out_array(2).dat;
TRIG_ILA0_0 <= fmc_130m_4ch_data(31 downto 16) &
fmc_130m_4ch_data(47 downto 32);
-- fmc130m_4ch WBS master output data
--TRIG_ILA0_1 <= wbs_fmc130m_4ch_out_array(1).dat &
-- wbs_fmc130m_4ch_out_array(0).dat;
--TRIG_ILA0_1 <= fmc130m_4ch_adc_data(15 downto 0) &
-- fmc130m_4ch_adc_data(47 downto 32);
TRIG_ILA0_1(11 downto 0) <= adc_dly_debug_int(1).clk_chain.idelay.pulse &
adc_dly_debug_int(1).data_chain.idelay.pulse &
adc_dly_debug_int(1).clk_chain.idelay.val &
adc_dly_debug_int(1).data_chain.idelay.val;
TRIG_ILA0_1(31 downto 12) <= (others => '0');
-- fmc130m_4ch WBS master output control signals
TRIG_ILA0_2(17 downto 0) <= wbs_fmc130m_4ch_out_array(1).cyc &
wbs_fmc130m_4ch_out_array(1).stb &
wbs_fmc130m_4ch_out_array(1).adr &
wbs_fmc130m_4ch_out_array(1).sel &
wbs_fmc130m_4ch_out_array(1).we &
wbs_fmc130m_4ch_out_array(2).cyc &
wbs_fmc130m_4ch_out_array(2).stb &
wbs_fmc130m_4ch_out_array(2).adr &
wbs_fmc130m_4ch_out_array(2).sel &
wbs_fmc130m_4ch_out_array(2).we;
TRIG_ILA0_2(18) <= '0';
TRIG_ILA0_2(22 downto 19) <= fmc_130m_4ch_data_valid;
TRIG_ILA0_2(23) <= fmc_mmcm_lock_int;
TRIG_ILA0_2(24) <= fmc_pll_status_int;
TRIG_ILA0_2(25) <= fmc130m_4ch_debug_valid_int(1);
TRIG_ILA0_2(26) <= fmc130m_4ch_debug_full_int(1);
TRIG_ILA0_2(27) <= fmc130m_4ch_debug_empty_int(1);
TRIG_ILA0_2(31 downto 28) <= (others => '0');
-- fmc130m_4ch WBS master output control signals
--TRIG_ILA0_3(17 downto 0) <= wbs_fmc130m_4ch_out_array(1).cyc &
-- wbs_fmc130m_4ch_out_array(1).stb &
-- wbs_fmc130m_4ch_out_array(1).adr &
-- wbs_fmc130m_4ch_out_array(1).sel &
-- wbs_fmc130m_4ch_out_array(1).we &
-- wbs_fmc130m_4ch_out_array(0).cyc &
-- wbs_fmc130m_4ch_out_array(0).stb &
-- wbs_fmc130m_4ch_out_array(0).adr &
-- wbs_fmc130m_4ch_out_array(0).sel &
-- wbs_fmc130m_4ch_out_array(0).we;
--TRIG_ILA0_3(18) <= fmc_reset_adcs_n_out;
--TRIG_ILA0_3(22 downto 19) <= fmc130m_4ch_adc_valid;
--TRIG_ILA0_3(23) <= fmc130m_4ch_mmcm_lock_int;
--TRIG_ILA0_3(24) <= fmc130m_4ch_lmk_lock_int;
--TRIG_ILA0_3(25) <= fmc130m_4ch_debug_valid_int(1);
--TRIG_ILA0_3(26) <= fmc130m_4ch_debug_full_int(1);
--TRIG_ILA0_3(27) <= fmc130m_4ch_debug_empty_int(1);
--TRIG_ILA0_3(31 downto 28) <= (others => '0');
TRIG_ILA0_3 <= (others => '0');
-- Etherbone debuging signals
--cmp_chipscope_ila_1_etherbone : chipscope_ila
--port map (
-- CONTROL => CONTROL1,
-- CLK => clk_sys,
-- TRIG0 => TRIG_ILA1_0,
-- TRIG1 => TRIG_ILA1_1,
-- TRIG2 => TRIG_ILA1_2,
-- TRIG3 => TRIG_ILA1_3
--);
--TRIG_ILA1_0 <= wb_ebone_out.dat;
--TRIG_ILA1_1 <= wb_ebone_in.dat;
--TRIG_ILA1_2 <= wb_ebone_out.adr;
--TRIG_ILA1_3(6 downto 0) <= wb_ebone_out.cyc &
-- wb_ebone_out.stb &
-- wb_ebone_out.sel &
-- wb_ebone_out.we;
--TRIG_ILA1_3(11 downto 7) <= wb_ebone_in.ack &
-- wb_ebone_in.err &
-- wb_ebone_in.rty &
-- wb_ebone_in.stall &
-- wb_ebone_in.int;
--TRIG_ILA1_3(31 downto 12) <= (others => '0');
--cmp_chipscope_ila_1_ethmac_rx : chipscope_ila
--port map (
-- CONTROL => CONTROL1,
-- CLK => mrx_clk_pad_i,
-- TRIG0 => TRIG_ILA1_0,
-- TRIG1 => TRIG_ILA1_1,
-- TRIG2 => TRIG_ILA1_2,
-- TRIG3 => TRIG_ILA1_3
--);
--
--TRIG_ILA1_0(7 downto 0) <= mrxd_pad_i &
-- mrxdv_pad_i &
-- mrxerr_pad_i &
-- mcoll_pad_i &
-- mcrs_pad_i;
--
--TRIG_ILA1_0(31 downto 8) <= (others => '0');
--TRIG_ILA1_1 <= (others => '0');
--TRIG_ILA1_2 <= (others => '0');
--TRIG_ILA1_3 <= (others => '0');
cmp_chipscope_ila_1_fmc130m_4ch_clk1 : chipscope_ila
port map (
CONTROL => CONTROL1,
--CLK => fmc_130m_4ch_clk(1),
CLK => fmc_130m_4ch_clk(c_adc_ref_clk),
TRIG0 => TRIG_ILA1_0,
TRIG1 => TRIG_ILA1_1,
TRIG2 => TRIG_ILA1_2,
TRIG3 => TRIG_ILA1_3
);
-- fmc130m_4ch WBS master output data
TRIG_ILA1_0 <= fmc_130m_4ch_data(15 downto 0) &
fmc_130m_4ch_data(63 downto 48);
-- fmc130m_4ch WBS master output data
TRIG_ILA1_1 <= (others => '0');
-- fmc130m_4ch WBS master output control signals
TRIG_ILA1_2(17 downto 0) <= wbs_fmc130m_4ch_out_array(0).cyc &
wbs_fmc130m_4ch_out_array(0).stb &
wbs_fmc130m_4ch_out_array(0).adr &
wbs_fmc130m_4ch_out_array(0).sel &
wbs_fmc130m_4ch_out_array(0).we &
wbs_fmc130m_4ch_out_array(3).cyc &
wbs_fmc130m_4ch_out_array(3).stb &
wbs_fmc130m_4ch_out_array(3).adr &
wbs_fmc130m_4ch_out_array(3).sel &
wbs_fmc130m_4ch_out_array(3).we;
TRIG_ILA1_2(18) <= '0';
TRIG_ILA1_2(22 downto 19) <= fmc_130m_4ch_data_valid;
TRIG_ILA1_2(23) <= fmc_mmcm_lock_int;
TRIG_ILA1_2(24) <= fmc_pll_status_int;
TRIG_ILA1_2(25) <= fmc130m_4ch_debug_valid_int(0);
TRIG_ILA1_2(26) <= fmc130m_4ch_debug_full_int(0);
TRIG_ILA1_2(27) <= fmc130m_4ch_debug_empty_int(0);
TRIG_ILA1_2(31 downto 28) <= (others => '0');
TRIG_ILA1_3 <= (others => '0');
cmp_chipscope_ila_2_ethmac_tx : chipscope_ila
port map (
CONTROL => CONTROL2,
CLK => mtx_clk_pad_i,
TRIG0 => TRIG_ILA2_0,
TRIG1 => TRIG_ILA2_1,
TRIG2 => TRIG_ILA2_2,
TRIG3 => TRIG_ILA2_3
);
TRIG_ILA2_0(5 downto 0) <= mtxd_pad_int &
mtxen_pad_int &
mtxerr_pad_int;
TRIG_ILA2_0(31 downto 6) <= (others => '0');
TRIG_ILA2_1 <= (others => '0');
TRIG_ILA2_2 <= (others => '0');
TRIG_ILA2_3 <= (others => '0');
--cmp_chipscope_ila_3_ethmac_miim : chipscope_ila
--port map (
-- CONTROL => CONTROL3,
-- CLK => clk_sys,
-- TRIG0 => TRIG_ILA3_0,
-- TRIG1 => TRIG_ILA3_1,
-- TRIG2 => TRIG_ILA3_2,
-- TRIG3 => TRIG_ILA3_3
--);
--
--TRIG_ILA3_0(4 downto 0) <= mdc_pad_int &
-- ethmac_md_in &
-- ethmac_md_out &
-- ethmac_md_oe &
-- ethmac_int;
--
--TRIG_ILA3_0(31 downto 6) <= (others => '0');
--TRIG_ILA3_1 <= (others => '0');
--TRIG_ILA3_2 <= (others => '0');
--TRIG_ILA3_3 <= (others => '0');
-- The clocks to/from peripherals are derived from the bus clock.
-- Therefore we don't have to worry about synchronization here, just
-- keep in mind that the data/ss lines will appear longer than normal
cmp_chipscope_ila_3_fmc130m_4ch_periph : chipscope_ila
port map (
CONTROL => CONTROL3,
CLK => clk_sys,
TRIG0 => TRIG_ILA3_0,
TRIG1 => TRIG_ILA3_1,
TRIG2 => TRIG_ILA3_2,
TRIG3 => TRIG_ILA3_3
);
TRIG_ILA3_0(7 downto 0) <= (others => '0');
TRIG_ILA3_0(31 downto 8) <= (others => '0');
TRIG_ILA3_1(4 downto 0) <= (others => '0');
TRIG_ILA3_1(31 downto 5) <= (others => '0');
TRIG_ILA3_2 <= (others => '0');
TRIG_ILA3_3 <= (others => '0');
end rtl;
|
lgpl-3.0
|
8cbf187f5a8eda6fbb2aa2153d47a01b
| 0.40798 | 4.059454 | false | false | false | false |
mithro/soft-utmi
|
hdl/third_party/XAPP1064-serdes-macros/VHDL_Source/Macros/serdes_1_to_n_data_s8_se.vhd
| 1 | 15,943 |
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: serdes_1_to_n_data_s8_se.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: August 1 2008
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: D-bit generic 1:n data receiver module with se inputs
-- Takes in 1 bit of se data and deserialises this to n bits
-- data is received LSB first
-- Serial input words
-- Line0 : 0, ...... DS-(S+1)
-- Line1 : 1, ...... DS-(S+2)
-- Line(D-1) : . .
-- Line0(D) : D-1, ...... DS
-- Parallel output word
-- DS, DS-1 ..... 1, 0
--
-- Includes state machine to control CAL and the phase detector
-- Data inversion can be accomplished via the RX_RX_SWAP_MASK
-- parameter if required
--
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity serdes_1_to_n_data_s8_se is generic (
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
D : integer := 16) ; -- Set the number of inputs and outputs
port (
use_phase_detector : in std_logic ; -- Set generation of phase detector logic
datain : in std_logic_vector(D-1 downto 0) ; -- Input from se receiver pin
rxioclk : in std_logic ; -- IO Clock network
rxserdesstrobe : in std_logic ; -- Parallel data capture strobe
reset : in std_logic ; -- Reset line
gclk : in std_logic ; -- Global clock
bitslip : in std_logic ; -- Bitslip control line
debug_in : in std_logic_vector(1 downto 0) ; -- input debug data
data_out : out std_logic_vector((D*S)-1 downto 0) ; -- Output data
debug : out std_logic_vector((2*D)+6 downto 0)) ; -- Debug bus, 2D+6 = 2 lines per input (from mux and ce) + 7, leave nc if debug not required
end serdes_1_to_n_data_s8_se ;
architecture arch_serdes_1_to_n_data_s8_se of serdes_1_to_n_data_s8_se is
signal ddly_m : std_logic_vector(D-1 downto 0) ; -- Master output from IODELAY1
signal ddly_s : std_logic_vector(D-1 downto 0) ; -- Slave output from IODELAY1
signal cascade : std_logic_vector(D-1 downto 0) ;
signal busys : std_logic_vector(D-1 downto 0) ;
signal rx_data_in : std_logic_vector(D-1 downto 0) ;
signal rx_data_in_fix : std_logic_vector(D-1 downto 0) ;
signal state : integer range 0 to 8 ;
signal busyd : std_logic_vector(D-1 downto 0) ;
signal cal_data_sint : std_logic ;
signal ce_data_inta : std_logic ;
signal busy_data : std_logic_vector(D-1 downto 0) ;
signal busy_data_d : std_logic ;
signal counter : std_logic_vector(8 downto 0) ;
signal enable : std_logic ;
signal pd_edge : std_logic_vector(D-1 downto 0) ;
signal cal_data_slave : std_logic ;
signal cal_data_master : std_logic ;
signal valid_data : std_logic_vector(D-1 downto 0) ;
signal valid_data_d : std_logic ;
signal rst_data : std_logic ;
signal mdataout : std_logic_vector((8*D)-1 downto 0) ;
signal pdcounter : std_logic_vector(4 downto 0) ;
signal inc_data : std_logic ;
signal ce_data : std_logic_vector(D-1 downto 0) ;
signal inc_data_int : std_logic ;
signal incdec_data : std_logic_vector(D-1 downto 0) ;
signal incdec_data_d : std_logic ;
signal flag : std_logic ;
signal mux : std_logic_vector(D-1 downto 0) ;
signal incdec_data_or : std_logic_vector(D downto 0) ;
signal valid_data_or : std_logic_vector(D downto 0) ;
signal busy_data_or : std_logic_vector(D downto 0) ;
signal incdec_data_im : std_logic_vector(D-1 downto 0) ;
signal valid_data_im : std_logic_vector(D-1 downto 0) ;
signal all_ce : std_logic_vector(D-1 downto 0) ;
constant RX_SWAP_MASK : std_logic_vector(D-1 downto 0) := (others => '0') ; -- pinswap mask for input bits (0 = no swap (default), 1 = swap). Allows inputs to be connected the wrong way round to ease PCB routing.
begin
busy_data <= busys ;
debug <= mux & cal_data_master & rst_data & cal_data_slave & busy_data_d & inc_data & ce_data & valid_data_d & incdec_data_d ;
cal_data_slave <= cal_data_sint ;
process (gclk, reset)
begin
if reset = '1' then
state <= 0 ;
cal_data_master <= '0' ;
cal_data_sint <= '0' ;
counter <= (others => '0') ;
enable <= '0' ;
counter <= (others => '0') ;
mux <= (0 => '1', others => '0') ;
elsif gclk'event and gclk = '1' then
counter <= counter + 1 ;
if counter(8) = '1' then
counter <= "000000000" ;
end if ;
if counter(5) = '1' then
enable <= '1' ;
end if ;
if state = 0 and enable = '1' then -- Wait for all IODELAYs to be available
cal_data_master <= '0' ;
cal_data_sint <= '0' ;
rst_data <= '0' ;
if busy_data_d = '0' then
state <= 1 ;
end if ;
elsif state = 1 then -- Issue calibrate command to both master and slave
cal_data_master <= '1' ;
cal_data_sint <= '1' ;
if busy_data_d = '1' then -- and wait for command to be accepted
state <= 2 ;
end if ;
elsif state = 2 then -- Now RST all master and slave IODELAYs
cal_data_master <= '0' ;
cal_data_sint <= '0' ;
if busy_data_d = '0' then
rst_data <= '1' ;
state <= 3 ;
end if ;
elsif state = 3 then -- Wait for all IODELAYs to be available
rst_data <= '0' ;
if busy_data_d = '0' then
state <= 4 ;
end if ;
elsif state = 4 then -- Hang around
if counter(8) = '1' then
state <= 5 ;
end if ;
elsif state = 5 then -- Calibrate slave only
if busy_data_d = '0' then
cal_data_sint <= '1' ;
state <= 6 ;
if D /= 1 then
mux <= mux(D-2 downto 0) & mux(D-1) ;
end if ;
end if ;
elsif state = 6 then -- Wait for command to be accepted
if busy_data_d = '1' then
cal_data_sint <= '0' ;
state <= 7 ;
end if ;
elsif state = 7 then -- Wait for all IODELAYs to be available, ie CAL command finished
cal_data_sint <= '0' ;
if busy_data_d = '0' then
state <= 4 ;
end if ;
end if ;
end if ;
end process ;
process (gclk, reset)
begin
if reset = '1' then
pdcounter <= "10000" ;
ce_data_inta <= '0' ;
flag <= '0' ;
elsif gclk'event and gclk = '1' then
busy_data_d <= busy_data_or(D) ;
if use_phase_detector = '1' then -- decide whther pd is used
incdec_data_d <= incdec_data_or(D) ;
valid_data_d <= valid_data_or(D) ;
if ce_data_inta = '1' then
ce_data <= mux ;
else
ce_data <= (others => '0') ;
end if ;
if state = 7 then
flag <= '0' ;
elsif state /= 4 or busy_data_d = '1' then -- Reset filter if state machine issues a cal command or unit is busy
pdcounter <= "10000" ;
ce_data_inta <= '0' ;
elsif pdcounter = "11111" and flag = '0' then -- Filter has reached positive max - increment the tap count
ce_data_inta <= '1' ;
inc_data_int <= '1' ;
pdcounter <= "10000" ;
flag <= '0' ;
elsif pdcounter = "00000" and flag = '0' then -- Filter has reached negative max - decrement the tap count
ce_data_inta <= '1' ;
inc_data_int <= '0' ;
pdcounter <= "10000" ;
flag <= '0' ;
elsif valid_data_d = '1' then -- increment filter
ce_data_inta <= '0' ;
if incdec_data_d = '1' and pdcounter /= "11111" then
pdcounter <= pdcounter + 1 ;
elsif incdec_data_d = '0' and pdcounter /= "00000" then -- decrement filter
pdcounter <= pdcounter - 1 ;
end if ;
else
ce_data_inta <= '0' ;
end if ;
else
ce_data <= all_ce ;
inc_data_int <= debug_in(1) ;
end if ;
end if ;
end process ;
inc_data <= inc_data_int ;
incdec_data_or(0) <= '0' ; -- Input Mux - Initialise generate loop OR gates
valid_data_or(0) <= '0' ;
busy_data_or(0) <= '0' ;
loop0 : for i in 0 to (D - 1) generate
incdec_data_im(i) <= incdec_data(i) and mux(i) ; -- Input muxes
incdec_data_or(i+1) <= incdec_data_im(i) or incdec_data_or(i) ; -- AND gates to allow just one signal through at a tome
valid_data_im(i) <= valid_data(i) and mux(i) ; -- followed by an OR
valid_data_or(i+1) <= valid_data_im(i) or valid_data_or(i) ; -- for the three inputs from each PD
busy_data_or(i+1) <= busy_data(i) or busy_data_or(i) ; -- The busy signals just need an OR gate
all_ce(i) <= debug_in(0) ;
rx_data_in_fix(i) <= rx_data_in(i) xor RX_SWAP_MASK(i) ; -- Invert signals as required
iob_clk_in : IBUF port map (
I => datain(i),
O => rx_data_in(i));
iodelay_m : IODELAY2 generic map(
DATA_RATE => "SDR", -- <SDR>, DDR
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL" , -- NORMAL, PCI
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_TYPE => "DIFF_PHASE_DETECTOR",-- "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
COUNTER_WRAPAROUND => "WRAPAROUND", -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN", -- "IO", "IDATAIN", "ODATAIN"
SERDES_MODE => "MASTER", -- <NONE>, MASTER, SLAVE
SIM_TAPDELAY_VALUE => 49) --
port map (
IDATAIN => rx_data_in_fix(i), -- data from primary IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_m(i), -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => rxioclk, -- High speed clock for calibration
IOCLK1 => '0', -- High speed clock for calibration
CLK => gclk, -- Fabric clock (GCLK) for control signals
CAL => cal_data_master, -- Calibrate control signal
INC => inc_data, -- Increment counter
CE => ce_data(i), -- Clock Enable
RST => rst_data, -- Reset delay line
BUSY => open) ; -- output signal indicating sync circuit has finished / calibration has finished
iodelay_s : IODELAY2 generic map(
DATA_RATE => "SDR", -- <SDR>, DDR
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL", -- NORMAL, PCI
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_TYPE => "DIFF_PHASE_DETECTOR",-- "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
COUNTER_WRAPAROUND => "WRAPAROUND" , -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN" , -- "IO", "IDATAIN", "ODATAIN"
SERDES_MODE => "SLAVE", -- <NONE>, MASTER, SLAVE
SIM_TAPDELAY_VALUE => 49) --
port map (
IDATAIN => rx_data_in_fix(i), -- data from primary IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_s(i), -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => rxioclk, -- High speed clock for calibration
IOCLK1 => '0', -- High speed clock for calibration
CLK => gclk, -- Fabric clock (GCLK) for control signals
CAL => cal_data_slave, -- Calibrate control signal
INC => inc_data, -- Increment counter
CE => ce_data(i) , -- Clock Enable
RST => rst_data, -- Reset delay line
BUSY => busys(i)) ; -- output signal indicating sync circuit has finished / calibration has finished
iserdes_m : ISERDES2 generic map (
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE => "SDR", -- <SDR>, DDR
BITSLIP_ENABLE => TRUE, -- <FALSE>, TRUE
SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE
INTERFACE_TYPE => "RETIMED") -- NETWORKING, NETWORKING_PIPELINED, <RETIMED>
port map (
D => ddly_m(i),
CE0 => '1',
CLK0 => rxioclk,
CLK1 => '0',
IOCE => rxserdesstrobe,
RST => reset,
CLKDIV => gclk,
SHIFTIN => pd_edge(i),
BITSLIP => bitslip,
FABRICOUT => open,
Q4 => mdataout((8*i)+7),
Q3 => mdataout((8*i)+6),
Q2 => mdataout((8*i)+5),
Q1 => mdataout((8*i)+4),
DFB => open,
CFB0 => open,
CFB1 => open,
VALID => valid_data(i),
INCDEC => incdec_data(i),
SHIFTOUT => cascade(i));
iserdes_s : ISERDES2 generic map(
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE => "SDR", -- <SDR>, DDR
BITSLIP_ENABLE => TRUE, -- <FALSE>, TRUE
SERDES_MODE => "SLAVE", -- <DEFAULT>, MASTER, SLAVE
INTERFACE_TYPE => "RETIMED") -- NETWORKING, NETWORKING_PIPELINED, <RETIMED>
port map (
D => ddly_s(i),
CE0 => '1',
CLK0 => rxioclk,
CLK1 => '0',
IOCE => rxserdesstrobe,
RST => reset,
CLKDIV => gclk,
SHIFTIN => cascade(i),
BITSLIP => bitslip,
FABRICOUT => open,
Q4 => mdataout((8*i)+3),
Q3 => mdataout((8*i)+2),
Q2 => mdataout((8*i)+1),
Q1 => mdataout((8*i)+0),
DFB => open,
CFB0 => open,
CFB1 => open,
VALID => open,
INCDEC => open,
SHIFTOUT => pd_edge(i));
loop1 : for j in 7 downto (8-S) generate
data_out(((D*(j+S-8))+i)) <= mdataout((8*i)+j) ;
end generate ;
end generate ;
end arch_serdes_1_to_n_data_s8_se ;
|
apache-2.0
|
2ae5782707975a95b000222767f47e03
| 0.587719 | 2.978886 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/examples/specialIntfTypes/InterfaceWithVHDLUnconstrainedArrayImportedType.vhd
| 1 | 617 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY InterfaceWithVHDLUnconstrainedArrayImportedType IS
GENERIC(
SIZE_X : INTEGER := 3
);
PORT(
din : IN mem(0 TO 3)(7 DOWNTO 0);
dout_0 : OUT UNSIGNED(7 DOWNTO 0);
dout_1 : OUT UNSIGNED(7 DOWNTO 0);
dout_2 : OUT UNSIGNED(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE rtl OF InterfaceWithVHDLUnconstrainedArrayImportedType IS
BEGIN
dout_0 <= din(0);
dout_1 <= din(1);
dout_2 <= din(2);
ASSERT SIZE_X = 3 REPORT "Generated only for this value" SEVERITY failure;
END ARCHITECTURE;
|
mit
|
b61b7beeb06badbf5b3f42c82f52e512
| 0.654781 | 3.505682 | false | false | false | false |
missatisfaction/fpu
|
VHDL/finv.vhd
| 1 | 2,544 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity finv is
Port (
clk: in STD_LOGIC;
f1 : in STD_LOGIC_VECTOR (31 downto 0);
ans: out STD_LOGIC_VECTOR (31 downto 0));
end finv;
architecture finv of finv is
component table_finv is
port ( clk: in std_logic;
addrb: in std_logic_vector(9 downto 0);
doutb: out std_logic_vector(34 downto 0));
end component;
signal s : std_logic;
signal exp : std_logic_vector(7 downto 0);
signal fr : std_logic_vector(22 downto 0);
signal key : std_logic_vector(9 downto 0);
signal tb : std_logic_vector(34 downto 0);
signal s1 : std_logic;
signal e1 : std_logic_vector(7 downto 0);
signal e2 : std_logic_vector(8 downto 0);
signal low : std_logic_vector(12 downto 0);
signal flag1 : std_logic;
signal val : std_logic_vector(22 downto 0);
signal comp,comp1 : std_logic_vector(13 downto 0);
signal comp2 : std_logic_vector(12 downto 0);
signal comp_low : std_logic_vector(9 downto 0);
signal flag2,flag3 : std_logic;
signal comp_t : std_logic_vector(24 downto 0); --step2
signal comp_l : std_logic_vector(13 downto 0); --step3
begin
tb_ram : table_finv
PORT MAP (
clk => clk,
addrb => key,
doutb => tb);
ans <= s&exp&fr;
key <= f1(22 downto 13);
step1 : process(clk,f1)
begin
if rising_edge(clk) then
s1 <= f1(31);
e1 <= f1(30 downto 23);
low <= f1(12 downto 0);
if (f1(12 downto 8) > 14 and f1(12 downto 8) < 22) then
flag1 <= '1';
else
flag1 <= '0';
end if;
end if;
end process;
step2 : process(clk,s1,e1,low,tb,comp_t)
begin
comp_t <= low * tb(11 downto 0);
if rising_edge(clk) then
s <= s1;
e2 <= 253 - ('0'&e1);
val <= tb(34 downto 12);
comp <= comp_t(24 downto 11);
flag2 <= flag1;
comp_low <= comp_t(9 downto 0);
end if;
end process;
step3 : process(e2,val,comp,comp1,comp2,comp_low,flag2,flag3,comp_l)
begin
comp1 <= comp + 1;
comp2 <= comp(13 downto 1) + 1;
if (comp_low = "00"&x"00") then
flag3 <= '0';
else
flag3 <= '1';
end if;
if ((flag2 or flag3) = '1') then
if ((flag2 and flag3) = '1') then
comp_l <= comp2&comp(0);
else
comp_l <= comp1;
end if;
else
comp_l <= comp;
end if;
if e2(8) = '1' then
exp <= x"00";
fr <= "000"&x"00000";
else
exp <= e2(7 downto 0);
fr <= val - comp_l;
end if;
end process;
end finv;
|
apache-2.0
|
ea36ab502bba3895002b7fab08dbaece
| 0.575079 | 2.968495 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/examples/rtlLvl/SimpleEnum.vhd
| 1 | 995 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY SimpleEnum IS
PORT(
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
s_in0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_in1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE rtl OF SimpleEnum IS
TYPE fsmT IS (send0, send1);
SIGNAL fsmSt : fsmt := send0;
SIGNAL fsmSt_next : fsmt;
BEGIN
assig_process_fsmSt: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst = '1' THEN
fsmSt <= send0;
ELSE
fsmSt <= fsmSt_next;
END IF;
END IF;
END PROCESS;
assig_process_fsmSt_next: PROCESS(fsmSt, s_in0, s_in1)
BEGIN
IF fsmSt = send0 THEN
s_out <= s_in0;
fsmSt_next <= send1;
ELSE
s_out <= s_in1;
fsmSt_next <= send0;
END IF;
END PROCESS;
END ARCHITECTURE;
|
mit
|
7910e9c1da98fa8f62ab685ad038377d
| 0.539698 | 3.442907 | false | false | false | false |
zeruniverse/pipelined_CPU
|
ISE project/ipcore_dir/data_mem.vhd
| 1 | 6,674 |
--------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file data_mem.vhd when simulating
-- the core, data_mem. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY data_mem IS
port (
clka: in std_logic;
wea: in std_logic_vector(0 downto 0);
addra: in std_logic_vector(5 downto 0);
dina: in std_logic_vector(31 downto 0);
douta: out std_logic_vector(31 downto 0));
END data_mem;
ARCHITECTURE data_mem_a OF data_mem IS
-- synthesis translate_off
component wrapped_data_mem
port (
clka: in std_logic;
wea: in std_logic_vector(0 downto 0);
addra: in std_logic_vector(5 downto 0);
dina: in std_logic_vector(31 downto 0);
douta: out std_logic_vector(31 downto 0));
end component;
-- Configuration specification
for all : wrapped_data_mem use entity XilinxCoreLib.blk_mem_gen_v4_3(behavioral)
generic map(
c_has_regceb => 0,
c_has_regcea => 0,
c_mem_type => 0,
c_rstram_b => 0,
c_rstram_a => 0,
c_has_injecterr => 0,
c_rst_type => "SYNC",
c_prim_type => 1,
c_read_width_b => 32,
c_initb_val => "0",
c_family => "spartan3",
c_read_width_a => 32,
c_disable_warn_bhv_coll => 0,
c_use_softecc => 0,
c_write_mode_b => "WRITE_FIRST",
c_init_file_name => "data_mem.mif",
c_write_mode_a => "WRITE_FIRST",
c_mux_pipeline_stages => 0,
c_has_softecc_output_regs_b => 0,
c_has_mem_output_regs_b => 0,
c_has_mem_output_regs_a => 0,
c_load_init_file => 1,
c_xdevicefamily => "spartan3",
c_write_depth_b => 64,
c_write_depth_a => 64,
c_has_rstb => 0,
c_has_rsta => 0,
c_has_mux_output_regs_b => 0,
c_inita_val => "0",
c_has_mux_output_regs_a => 0,
c_addra_width => 6,
c_has_softecc_input_regs_a => 0,
c_addrb_width => 6,
c_default_data => "0",
c_use_ecc => 0,
c_algorithm => 1,
c_disable_warn_bhv_range => 0,
c_write_width_b => 32,
c_write_width_a => 32,
c_read_depth_b => 64,
c_read_depth_a => 64,
c_byte_size => 9,
c_sim_collision_check => "ALL",
c_common_clk => 0,
c_wea_width => 1,
c_has_enb => 0,
c_web_width => 1,
c_has_ena => 0,
c_use_byte_web => 0,
c_use_byte_wea => 0,
c_rst_priority_b => "CE",
c_rst_priority_a => "CE",
c_use_default_data => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_data_mem
port map (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta);
-- synthesis translate_on
END data_mem_a;
|
gpl-3.0
|
b2f591e855006977d77213c3bb68f3ab
| 0.52682 | 3.991627 | false | false | false | false |
Nic30/hwtLib
|
hwtLib/tests/serialization/AssignToASliceOfReg3a.vhd
| 1 | 2,417 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- Something not assigned by index at the end and then whole signal assigned.
--
ENTITY AssignToASliceOfReg3a IS
PORT(
clk : IN STD_LOGIC;
data_in_addr : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
data_in_data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
data_in_mask : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
data_in_rd : OUT STD_LOGIC;
data_in_vld : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
rst_n : IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF AssignToASliceOfReg3a IS
SIGNAL r : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000000";
SIGNAL r_next : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL r_next_15downto8 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL r_next_23downto16 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL r_next_31downto24 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL r_next_7downto0 : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
data_in_rd <= '1';
data_out <= r;
assig_process_r: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst_n = '0' THEN
r <= X"00000000";
ELSE
r <= r_next;
END IF;
END IF;
END PROCESS;
r_next <= r_next_31downto24 & r_next_23downto16 & r_next_15downto8 & r_next_7downto0;
assig_process_r_next_15downto8: PROCESS(data_in_addr, data_in_data, r)
BEGIN
CASE data_in_addr IS
WHEN "00" =>
r_next_7downto0 <= data_in_data;
r_next_15downto8 <= r(15 DOWNTO 8);
r_next_23downto16 <= r(23 DOWNTO 16);
r_next_31downto24 <= r(31 DOWNTO 24);
WHEN "01" =>
r_next_15downto8 <= data_in_data;
r_next_23downto16 <= r(23 DOWNTO 16);
r_next_31downto24 <= r(31 DOWNTO 24);
r_next_7downto0 <= r(7 DOWNTO 0);
WHEN "10" =>
r_next_23downto16 <= data_in_data;
r_next_15downto8 <= r(15 DOWNTO 8);
r_next_31downto24 <= r(31 DOWNTO 24);
r_next_7downto0 <= r(7 DOWNTO 0);
WHEN OTHERS =>
r_next_7downto0 <= X"7B";
r_next_15downto8 <= X"00";
r_next_23downto16 <= X"00";
r_next_31downto24 <= X"00";
END CASE;
END PROCESS;
END ARCHITECTURE;
|
mit
|
4c5a68307d6e4c4fa8d83b9000bdddef
| 0.545304 | 3.356944 | false | false | false | false |
sorgelig/ZX_Spectrum-128K_MIST
|
tzxplayer.vhd
| 1 | 18,263 |
---------------------------------------------------------------------------------
-- TZX player
-- by György Szombathelyi
-- basic idea for the structure based on c1530 tap player by darfpga
--
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity tzxplayer is
generic (
TZX_MS : integer := 64000; -- CE periods for one milliseconds
-- Default: ZX Spectrum
NORMAL_PILOT_LEN : integer := 2168;
NORMAL_SYNC1_LEN : integer := 667;
NORMAL_SYNC2_LEN : integer := 735;
NORMAL_ZERO_LEN : integer := 855;
NORMAL_ONE_LEN : integer := 1710;
NORMAL_PILOT_PULSES : integer := 4031
-- Amstrad CPC
--NORMAL_PILOT_LEN : integer := 2000;
--NORMAL_SYNC1_LEN : integer := 855;
--NORMAL_SYNC2_LEN : integer := 855;
--NORMAL_ZERO_LEN : integer := 855;
--NORMAL_ONE_LEN : integer := 1710;
--NORMAL_PILOT_PULSES : integer := 4096;
);
port(
clk : in std_logic;
ce : in std_logic;
restart_tape : in std_logic;
host_tap_in : in std_logic_vector(7 downto 0); -- 8bits fifo input
tzx_req : buffer std_logic; -- request for new byte (edge trigger)
tzx_ack : in std_logic; -- new data available
loop_start : out std_logic; -- active for one clock if a loop starts
loop_next : out std_logic; -- active for one clock at the next iteration
stop : out std_logic; -- tape should be stopped
stop48k : out std_logic; -- tape should be stopped in 48k mode
cass_read : buffer std_logic; -- tape read signal
cass_motor : in std_logic -- 1 = tape motor is powered
);
end tzxplayer;
architecture struct of tzxplayer is
signal tap_fifo_do : std_logic_vector(7 downto 0);
signal tick_cnt : std_logic_vector(16 downto 0);
signal wave_cnt : std_logic_vector(15 downto 0);
signal wave_period : std_logic;
signal skip_bytes : std_logic;
signal playing : std_logic; -- 1 = tap or wav file is playing
signal bit_cnt : std_logic_vector(2 downto 0);
type tzx_state_t is (
TZX_HEADER,
TZX_NEWBLOCK,
TZX_LOOP_START,
TZX_LOOP_END,
TZX_PAUSE,
TZX_PAUSE2,
TZX_STOP48K,
TZX_HWTYPE,
TZX_TEXT,
TZX_MESSAGE,
TZX_ARCHIVE_INFO,
TZX_CUSTOM_INFO,
TZX_GLUE,
TZX_TONE,
TZX_PULSES,
TZX_DATA,
TZX_NORMAL,
TZX_TURBO,
TZX_PLAY_TONE,
TZX_PLAY_SYNC1,
TZX_PLAY_SYNC2,
TZX_PLAY_TAPBLOCK,
TZX_PLAY_TAPBLOCK2,
TZX_PLAY_TAPBLOCK3,
TZX_PLAY_TAPBLOCK4,
TZX_DIRECT,
TZX_DIRECT2,
TZX_DIRECT3);
signal tzx_state: tzx_state_t;
signal tzx_offset : std_logic_vector( 7 downto 0);
signal pause_len : std_logic_vector(15 downto 0);
signal ms_counter : std_logic_vector(15 downto 0);
signal pilot_l : std_logic_vector(15 downto 0);
signal sync1_l : std_logic_vector(15 downto 0);
signal sync2_l : std_logic_vector(15 downto 0);
signal zero_l : std_logic_vector(15 downto 0);
signal one_l : std_logic_vector(15 downto 0);
signal pilot_pulses : std_logic_vector(15 downto 0);
signal last_byte_bits : std_logic_vector( 3 downto 0);
signal data_len : std_logic_vector(23 downto 0);
signal pulse_len : std_logic_vector(15 downto 0);
signal end_period : std_logic;
signal cass_motor_D : std_logic;
signal motor_counter : std_logic_vector(21 downto 0);
signal loop_iter : std_logic_vector(15 downto 0);
signal data_len_dword : std_logic_vector(31 downto 0);
begin
tap_fifo_do <= host_tap_in;
process(clk)
begin
if rising_edge(clk) then
if restart_tape = '1' then
tzx_offset <= (others => '0');
tzx_state <= TZX_HEADER;
pulse_len <= (others => '0');
motor_counter <= (others => '0');
wave_period <= '0';
playing <= '0';
tzx_req <= tzx_ack;
loop_start <= '0';
loop_next <= '0';
loop_iter <= (others => '0');
else
-- simulate tape motor momentum
-- don't change the playing state if the motor is switched in 50 ms
-- Opera Soft K17 protection needs this!
cass_motor_D <= cass_motor;
if cass_motor_D /= cass_motor then
motor_counter <= CONV_STD_LOGIC_VECTOR(50*TZX_MS, motor_counter'length);
elsif motor_counter /= 0 then
if ce = '1' then motor_counter <= motor_counter - 1; end if;
else
playing <= cass_motor;
end if;
if playing = '0' then
--cass_read <= '1';
end if;
if pulse_len /= 0 then
if ce = '1' then
tick_cnt <= tick_cnt + 3500;
if tick_cnt >= (TZX_MS - 3500) then
tick_cnt <= tick_cnt - (TZX_MS - 3500);
wave_cnt <= wave_cnt + 1;
if wave_cnt = pulse_len then
wave_cnt <= (others => '0');
cass_read <= wave_period;
wave_period <= not wave_period;
if wave_period = end_period then
pulse_len <= (others => '0');
end if;
end if;
end if;
end if;
else
tick_cnt <= (others => '0');
wave_cnt <= (others => '0');
end if;
loop_start <= '0';
loop_next <= '0';
stop <= '0';
stop48k <= '0';
if playing = '1' and pulse_len = 0 and tzx_req = tzx_ack then
tzx_req <= not tzx_ack; -- default request for new data
case tzx_state is
when TZX_HEADER =>
cass_read <= '1';
tzx_offset <= tzx_offset + 1;
if tzx_offset = x"0A" then -- skip 9 bytes, offset lags 1
tzx_state <= TZX_NEWBLOCK;
end if;
when TZX_NEWBLOCK =>
tzx_offset <= (others=>'0');
ms_counter <= (others=>'0');
case tap_fifo_do is
when x"10" => tzx_state <= TZX_NORMAL;
when x"11" => tzx_state <= TZX_TURBO;
when x"12" => tzx_state <= TZX_TONE;
when x"13" => tzx_state <= TZX_PULSES;
when x"14" => tzx_state <= TZX_DATA;
when x"15" => tzx_state <= TZX_DIRECT;
when x"18" => null; -- CSW recording (not implemented)
when x"19" => null; -- Generalized data block (not implemented)
when x"20" => tzx_state <= TZX_PAUSE;
when x"21" => tzx_state <= TZX_TEXT; -- Group start
when x"22" => null; -- Group end
when x"23" => null; -- Jump to block (not implemented)
when x"24" => tzx_state <= TZX_LOOP_START;
when x"25" => tzx_state <= TZX_LOOP_END;
when x"26" => null; -- Call sequence (not implemented)
when x"27" => null; -- Return from sequence (not implemented)
when x"28" => null; -- Select block (not implemented)
when x"2A" => tzx_state <= TZX_STOP48K;
when x"2B" => null; -- Set signal level (not implemented)
when x"30" => tzx_state <= TZX_TEXT;
when x"31" => tzx_state <= TZX_MESSAGE;
when x"32" => tzx_state <= TZX_ARCHIVE_INFO;
when x"33" => tzx_state <= TZX_HWTYPE;
when x"35" => tzx_state <= TZX_CUSTOM_INFO;
when x"5A" => tzx_state <= TZX_GLUE;
when others => null;
end case;
when TZX_LOOP_START =>
tzx_offset <= tzx_offset + 1;
if tzx_offset = x"00" then loop_iter( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"01" then
loop_iter(15 downto 8) <= tap_fifo_do;
tzx_state <= TZX_NEWBLOCK;
loop_start <= '1';
end if;
when TZX_LOOP_END =>
if loop_iter > 1 then
loop_iter <= loop_iter - 1;
loop_next <= '1';
else
tzx_req <= tzx_ack; -- don't request new byte
end if;
tzx_state <= TZX_NEWBLOCK;
when TZX_PAUSE =>
tzx_offset <= tzx_offset + 1;
if tzx_offset = x"00" then
pause_len(7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"01" then
pause_len(15 downto 8) <= tap_fifo_do;
tzx_state <= TZX_PAUSE2;
if pause_len(7 downto 0) = 0 and tap_fifo_do = 0 then
stop <= '1';
end if;
end if;
when TZX_PAUSE2 =>
tzx_req <= tzx_ack; -- don't request new byte
if ms_counter /= 0 then
if ce = '1' then
ms_counter <= ms_counter - 1;
-- Set pulse level to low after 1 ms
if ms_counter = 1 then
wave_period <= '0';
end_period <= '0';
cass_read <= '0';
end if;
end if;
elsif pause_len /= 0 then
pause_len <= pause_len - 1;
ms_counter <= conv_std_logic_vector(TZX_MS, 16);
else
tzx_state <= TZX_NEWBLOCK;
end if;
when TZX_STOP48K =>
tzx_offset <= tzx_offset + 1;
if tzx_offset = x"03" then
stop48k <= '1';
tzx_state <= TZX_NEWBLOCK;
end if;
when TZX_HWTYPE =>
tzx_offset <= tzx_offset + 1;
-- 0, 1-3, 1-3, ...
if tzx_offset = x"00" then data_len( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"03" then
if data_len(7 downto 0) = x"01" then
tzx_state <= TZX_NEWBLOCK;
else
data_len(7 downto 0) <= data_len(7 downto 0) - 1;
tzx_offset <= x"01";
end if;
end if;
when TZX_MESSAGE =>
-- skip display time, then then same as TEXT DESRCRIPTION
tzx_state <= TZX_TEXT;
when TZX_TEXT =>
tzx_offset <= tzx_offset + 1;
if tzx_offset = x"00" then data_len( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = data_len(7 downto 0) then
tzx_state <= TZX_NEWBLOCK;
end if;
when TZX_ARCHIVE_INFO =>
tzx_offset <= tzx_offset + 1;
if tzx_offset = x"00" then data_len( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"01" then data_len(15 downto 8) <= tap_fifo_do;
else
tzx_offset <= x"02";
data_len <= data_len - 1;
if data_len = 1 then
tzx_state <= TZX_NEWBLOCK;
end if;
end if;
when TZX_CUSTOM_INFO =>
tzx_offset <= tzx_offset + 1;
if tzx_offset = x"10" then data_len_dword( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"11" then data_len_dword(15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"12" then data_len_dword(23 downto 16) <= tap_fifo_do;
elsif tzx_offset = x"13" then data_len_dword(31 downto 24) <= tap_fifo_do;
elsif tzx_offset = x"14" then
tzx_offset <= x"14";
if data_len_dword = 1 then
tzx_state <= TZX_NEWBLOCK;
else
data_len_dword <= data_len_dword - 1;
end if;
end if;
when TZX_GLUE =>
tzx_offset <= tzx_offset + 1;
if tzx_offset = x"08" then
tzx_state <= TZX_NEWBLOCK;
end if;
when TZX_TONE =>
tzx_offset <= tzx_offset + 1;
-- 0, 1, 2, 3, 4, 4, 4, ...
if tzx_offset = x"00" then pilot_l( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"01" then pilot_l(15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"02" then pilot_pulses( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"03" then
tzx_req <= tzx_ack; -- don't request new byte
pilot_pulses(15 downto 8) <= tap_fifo_do;
else
tzx_offset <= x"04";
tzx_req <= tzx_ack; -- don't request new byte
if pilot_pulses = 0 then
tzx_req <= not tzx_ack; -- default request for new data
tzx_state <= TZX_NEWBLOCK;
else
pilot_pulses <= pilot_pulses - 1;
end_period <= wave_period;
pulse_len <= pilot_l;
end if;
end if;
when TZX_PULSES =>
tzx_offset <= tzx_offset + 1;
-- 0, 1-2+3, 1-2+3, ...
if tzx_offset = x"00" then data_len( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"01" then one_l( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"02" then
tzx_req <= tzx_ack; -- don't request new byte
end_period <= wave_period;
pulse_len <= tap_fifo_do & one_l( 7 downto 0);
elsif tzx_offset = x"03" then
if data_len(7 downto 0) = x"01" then
tzx_state <= TZX_NEWBLOCK;
else
data_len(7 downto 0) <= data_len(7 downto 0) - 1;
tzx_offset <= x"01";
end if;
end if;
when TZX_DATA =>
tzx_offset <= tzx_offset + 1;
if tzx_offset = x"00" then zero_l ( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"01" then zero_l (15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"02" then one_l ( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"03" then one_l (15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"04" then last_byte_bits <= tap_fifo_do(3 downto 0);
elsif tzx_offset = x"05" then pause_len( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"06" then pause_len(15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"07" then data_len ( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"08" then data_len (15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"09" then
tzx_req <= tzx_ack; -- don't request new byte
data_len (23 downto 16) <= tap_fifo_do;
tzx_state <= TZX_PLAY_TAPBLOCK;
end if;
when TZX_NORMAL =>
tzx_offset <= tzx_offset + 1;
if tzx_offset = x"00" then pause_len( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"01" then pause_len(15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"02" then data_len ( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"03" then
tzx_req <= tzx_ack; -- don't request new byte
data_len(15 downto 8) <= tap_fifo_do;
data_len(23 downto 16) <= (others => '0');
pilot_l <= conv_std_logic_vector(NORMAL_PILOT_LEN, 16);
sync1_l <= conv_std_logic_vector(NORMAL_SYNC1_LEN, 16);
sync2_l <= conv_std_logic_vector(NORMAL_SYNC2_LEN, 16);
zero_l <= conv_std_logic_vector(NORMAL_ZERO_LEN, 16);
one_l <= conv_std_logic_vector(NORMAL_ONE_LEN, 16);
pilot_pulses <= conv_std_logic_vector(NORMAL_PILOT_PULSES, 16);
last_byte_bits <= "1000";
tzx_state <= TZX_PLAY_TONE;
end if;
when TZX_TURBO =>
tzx_offset <= tzx_offset + 1;
if tzx_offset = x"00" then pilot_l( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"01" then pilot_l(15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"02" then sync1_l( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"03" then sync1_l(15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"04" then sync2_l( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"05" then sync2_l(15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"06" then zero_l ( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"07" then zero_l (15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"08" then one_l ( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"09" then one_l (15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"0A" then pilot_pulses( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"0B" then pilot_pulses(15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"0C" then last_byte_bits <= tap_fifo_do(3 downto 0);
elsif tzx_offset = x"0D" then pause_len( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"0E" then pause_len(15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"0F" then data_len ( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"10" then data_len (15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"11" then
tzx_req <= tzx_ack; -- don't request new byte
data_len (23 downto 16) <= tap_fifo_do;
tzx_state <= TZX_PLAY_TONE;
end if;
when TZX_PLAY_TONE =>
tzx_req <= tzx_ack; -- don't request new byte
end_period <= not wave_period;
pulse_len <= pilot_l;
if pilot_pulses /= 0 then
pilot_pulses <= pilot_pulses - 1;
else
tzx_state <= TZX_PLAY_SYNC1;
end if;
when TZX_PLAY_SYNC1 =>
tzx_req <= tzx_ack; -- don't request new byte
end_period <= wave_period;
pulse_len <= sync1_l;
tzx_state <= TZX_PLAY_SYNC2;
when TZX_PLAY_SYNC2 =>
tzx_req <= tzx_ack; -- don't request new byte
end_period <= wave_period;
pulse_len <= sync2_l;
tzx_state <= TZX_PLAY_TAPBLOCK;
when TZX_PLAY_TAPBLOCK =>
bit_cnt <= "111";
tzx_state <= TZX_PLAY_TAPBLOCK2;
when TZX_PLAY_TAPBLOCK2 =>
tzx_req <= tzx_ack; -- don't request new byte
bit_cnt <= bit_cnt - 1;
if bit_cnt = "000" or (data_len = 1 and ((bit_cnt = (8 - last_byte_bits)) or (last_byte_bits = 0))) then
data_len <= data_len - 1;
tzx_state <= TZX_PLAY_TAPBLOCK3;
end if;
end_period <= not wave_period;
if tap_fifo_do(CONV_INTEGER(bit_cnt)) = '0' then
pulse_len <= zero_l;
else
pulse_len <= one_l;
end if;
when TZX_PLAY_TAPBLOCK3 =>
if data_len = 0 then
tzx_state <= TZX_PAUSE2;
else
tzx_state <= TZX_PLAY_TAPBLOCK4;
end if;
when TZX_PLAY_TAPBLOCK4 =>
tzx_req <= tzx_ack; -- don't request new byte
tzx_state <= TZX_PLAY_TAPBLOCK2;
when TZX_DIRECT =>
tzx_offset <= tzx_offset + 1;
if tzx_offset = x"00" then zero_l ( 7 downto 0) <= tap_fifo_do; -- here this is used for one bit, too
elsif tzx_offset = x"01" then zero_l (15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"02" then pause_len ( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"03" then pause_len (15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"04" then last_byte_bits <= tap_fifo_do(3 downto 0);
elsif tzx_offset = x"05" then data_len( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"06" then data_len(15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"07" then
data_len(23 downto 16) <= tap_fifo_do;
tzx_state <= TZX_DIRECT2;
bit_cnt <= "111";
end if;
when TZX_DIRECT2 =>
tzx_req <= tzx_ack; -- don't request new byte
bit_cnt <= bit_cnt - 1;
if bit_cnt = "000" or (data_len = 1 and ((bit_cnt = (8 - last_byte_bits)) or (last_byte_bits = 0))) then
data_len <= data_len - 1;
tzx_state <= TZX_DIRECT3;
end if;
pulse_len <= zero_l;
cass_read <= tap_fifo_do(CONV_INTEGER(bit_cnt));
wave_period <= tap_fifo_do(CONV_INTEGER(bit_cnt));
end_period <= tap_fifo_do(CONV_INTEGER(bit_cnt));
when TZX_DIRECT3 =>
if data_len = 0 then
tzx_state <= TZX_PAUSE2;
else
tzx_state <= TZX_DIRECT2;
end if;
when others => null;
end case;
end if; -- play tzx
end if;
end if; -- clk
end process;
end struct;
|
gpl-2.0
|
bcef74c37712921105f9a8bab7da019d
| 0.566641 | 2.900111 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
gxb_pll.vhd
| 1 | 16,869 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: gxb_pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY gxb_pll IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END gxb_pll;
ARCHITECTURE SYN OF gxb_pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire6_bv(0 DOWNTO 0) <= "0";
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
sub_wire4 <= inclk0;
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 27,
clk0_duty_cycle => 50,
clk0_multiply_by => 125,
clk0_phase_shift => "0",
clk1_divide_by => 18,
clk1_duty_cycle => 50,
clk1_multiply_by => 25,
clk1_phase_shift => "0",
inclk0_input_frequency => 37037,
intended_device_family => "Cyclone IV GX",
lpm_hint => "CBX_MODULE_PREFIX=gxb_pll",
lpm_type => "altpll",
operation_mode => "NO_COMPENSATION",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
areset => areset,
inclk => sub_wire5,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "90"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "125.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "37.500000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "125"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "125.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "37.50000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "gxb_pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "125"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "18"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "25"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL gxb_pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gxb_pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gxb_pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gxb_pll.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gxb_pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gxb_pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
gpl-3.0
|
46ed98e725cfc32609418880fb4f8603
| 0.698559 | 3.310893 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
testbench/dvb_dma_tb.vhd
| 1 | 5,451 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.avblabs_common_pkg.all;
entity dvb_dma_tb is
end;
architecture sym of dvb_dma_tb is
signal rst : std_logic := '1';
signal clk : std_logic := '0';
signal dvb0_clk : std_logic;
signal dvb0_strt : std_logic;
signal dvb0_dval : std_logic;
signal dvb0_data : std_logic_vector(7 downto 0);
signal dvb1_clk : std_logic;
signal dvb1_strt : std_logic;
signal dvb1_dval : std_logic;
signal dvb1_data : std_logic_vector(7 downto 0);
signal tsa_sop : std_logic;
signal tsa_data : std_logic_vector(7 downto 0);
signal tsa_dval : std_logic;
signal tsb_sop : std_logic;
signal tsb_data : std_logic_vector(7 downto 0);
signal tsb_dval : std_logic;
signal address : std_logic_vector(3 downto 0) := (others => '0');
signal byteenable : std_logic_vector(3 downto 0) := (others => '0');
signal writedata : std_logic_vector(31 downto 0) := (others => '0');
signal write : std_logic := '0';
signal readdata_0 : std_logic_vector(31 downto 0);
signal readdata_1 : std_logic_vector(31 downto 0);
signal interrupt_0 : std_logic;
signal interrupt_1 : std_logic;
signal mem0_addr : std_logic_vector(63 downto 3);
signal mem0_byteen : std_logic_vector(7 downto 0);
signal mem0_size : std_logic_vector(6 downto 0);
signal mem0_wrdata : std_logic_vector(63 downto 0);
signal mem0_write : std_logic;
signal mem0_waitreq : std_logic;
signal mem1_addr : std_logic_vector(63 downto 3);
signal mem1_byteen : std_logic_vector(7 downto 0);
signal mem1_size : std_logic_vector(6 downto 0);
signal mem1_wrdata : std_logic_vector(63 downto 0);
signal mem1_write : std_logic;
signal mem1_waitreq : std_logic;
signal mem_addr : std_logic_vector(30 downto 0);
signal mem_byteen : std_logic_vector(7 downto 0);
signal mem_size : std_logic_vector(6 downto 0);
signal mem_wrdata : std_logic_vector(63 downto 0);
signal mem_write : std_logic;
signal mem_waitreq : std_logic := '0';
begin
DVB_SRC_0 : entity work.dvb_source
generic map (
CLOCK_RATE_MHZ => 15,
INTERPACKET_GAP => 5,
INTEROCTET_GAP => 2
)
port map (
ts_clk => dvb0_clk,
ts_strt => dvb0_strt,
ts_dval => dvb0_dval,
ts_data => dvb0_data
);
DVB_SRC_1 : entity work.dvb_source
port map (
ts_clk => dvb1_clk,
ts_strt => dvb1_strt,
ts_dval => dvb1_dval,
ts_data => dvb1_data
);
DVB_TSIN_0 : entity work.dvb_ts_sync
port map (
ts_clk => dvb0_clk,
ts_strt => dvb0_strt,
ts_dval => dvb0_dval,
ts_data => dvb0_data,
--
rst => rst,
clk => clk,
--
strt => tsa_sop,
data => tsa_data,
dval => tsa_dval
);
DVB_TSIN_1 : entity work.dvb_ts_sync
port map (
ts_clk => dvb1_clk,
ts_strt => dvb1_strt,
ts_dval => dvb1_dval,
ts_data => dvb1_data,
--
rst => rst,
clk => clk,
--
strt => tsb_sop,
data => tsb_data,
dval => tsb_dval
);
DVB_DMA_0 : entity work.dvb_dma
port map (
rst => rst,
clk => clk,
address => address,
byteenable => byteenable,
writedata => writedata,
write => write,
readdata => readdata_0,
interrupt => interrupt_0,
dvb_sop => tsa_sop,
dvb_data => tsa_data,
dvb_dval => tsa_dval,
mem_addr => mem0_addr,
mem_byteen => mem0_byteen,
mem_size => mem0_size,
mem_wrdata => mem0_wrdata,
mem_write => mem0_write,
mem_waitreq => mem0_waitreq
);
DVB_DMA_1 : entity work.dvb_dma
port map (
rst => rst,
clk => clk,
address => address,
byteenable => byteenable,
writedata => writedata,
write => write,
readdata => readdata_1,
interrupt => interrupt_1,
dvb_sop => tsb_sop,
dvb_data => tsb_data,
dvb_dval => tsb_dval,
mem_addr => mem1_addr,
mem_byteen => mem1_byteen,
mem_size => mem1_size,
mem_wrdata => mem1_wrdata,
mem_write => mem1_write,
mem_waitreq => mem1_waitreq
);
ARB_0 : entity work.dma_arbiter
port map (
rst => rst,
clk => clk,
dma0_addr => mem0_addr,
dma0_byteen => mem0_byteen,
dma0_size => mem0_size,
dma0_wrdata => mem0_wrdata,
dma0_write => mem0_write,
dma0_wait => mem0_waitreq,
dma1_addr => mem1_addr,
dma1_byteen => mem1_byteen,
dma1_size => mem1_size,
dma1_wrdata => mem1_wrdata,
dma1_write => mem1_write,
dma1_wait => mem1_waitreq,
mem_addr => mem_addr,
mem_byteen => mem_byteen,
mem_size => mem_size,
mem_wrdata => mem_wrdata,
mem_write => mem_write,
mem_waitreq => mem_waitreq
);
process
begin
wait for 8 ns;
clk <= not clk;
end process;
process
begin
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
rst <= '0';
wait until rising_edge(clk);
wait until rising_edge(clk);
byteenable <= "1111";
write <= '1';
address <= X"4";
writedata <= X"040008BC";
wait until rising_edge(clk);
address <= X"0";
writedata <= X"00000001";
wait until rising_edge(clk);
write <= '0';
loop
wait until interrupt_0 = '1';
-- wait for 225 us;
wait until rising_edge(clk);
address <= X"1";
write <= '1';
writedata <= X"00000200";
wait until rising_edge(clk);
write <= '0';
end loop;
--
wait;
end process;
process
begin
wait until rising_edge(clk);
mem_waitreq <= mem_waitreq xor mem_write;
end process;
end;
|
gpl-3.0
|
3914c614777ebcc46665e1ceec191964
| 0.625206 | 2.53417 | false | false | false | false |
Krabby127/ADC
|
adclb/tb.vhd
| 1 | 1,474 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.all;
library std;
USE std.textio.all;
entity tb is
end entity;
architecture behav of tb is
component adclb
port (
reset :in std_logic;
clk :in std_logic;
clrb :in std_logic;
scl :out std_logic;
sdai :in std_logic;
sdao :out std_logic;
sda_oe :out std_logic;
diff_flag :out std_logic;
max :inout std_logic_vector (7 downto 0);
min :inout std_logic_vector (7 downto 0)
);
end component;
signal clk : std_logic;
signal reset : std_logic;
signal sdai : std_logic;
signal upd : std_logic;
signal scl : std_logic;
signal sdao : std_logic;
signal sda_oe : std_logic;
signal diff_i : std_logic;
signal diff: std_logic_vector(7 downto 0);
--signal val : std_logic_vector(7 downto 0);
begin
adc: adclb
port map (
reset => reset,
clk => clk,
clrb => reset,
scl => scl,
sdai => sdai,
sdao => sdao,
sda_oe => sda_oe,
diff_flag => diff_i,
max => open,
min => open
);
clk_p:process
begin
clk<='1';
wait for 5 ns;
clk <= '0';
wait for 5 ns;
end process;
testb:process
begin
reset <= '1';
sdai <= '0';
upd <= '0';
wait for 200ns;
reset <= '0';
wait for 6103us;
sdai<='1';
wait for 2us;
sdai<='0';
wait;
end process;
end;
|
apache-2.0
|
42b838eada56f6053825810b52f5b2c4
| 0.555631 | 3.083682 | false | false | false | false |
antlr/grammars-v4
|
vhdl/examples/standard.vhd
| 5 | 2,026 |
-- This is Package STANDARD as defined in the VHDL 1992 Language Reference Manual.
package standard is
type boolean is (false,true);
type bit is ('0', '1');
type character is (
nul, soh, stx, etx, eot, enq, ack, bel,
bs, ht, lf, vt, ff, cr, so, si,
dle, dc1, dc2, dc3, dc4, nak, syn, etb,
can, em, sub, esc, fsp, gsp, rsp, usp,
' ', '!', '"', '#', '$', '%', '&', ''',
'(', ')', '*', '+', ',', '-', '.', '/',
'0', '1', '2', '3', '4', '5', '6', '7',
'8', '9', ':', ';', '<', '=', '>', '?',
'@', 'A', 'B', 'C', 'D', 'E', 'F', 'G',
'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O',
'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W',
'X', 'Y', 'Z', '[', '\', ']', '^', '_',
'`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '{', '|', '}', '~', del,
c128, c129, c130, c131, c132, c133, c134, c135,
c136, c137, c138, c139, c140, c141, c142, c143,
c144, c145, c146, c147, c148, c149, c150, c151,
c152, c153, c154, c155, c156, c157, c158, c159
-- the character code for 160 is there (NBSP),
-- but prints as no char
);
type severity_level is (note, warning, error, failure);
type integer is range -2147483647 to 2147483647;
type real is range -1.0E308 to 1.0E308;
type time is range -2147483647 to 2147483647
units
fs;
ps = 1000 fs;
ns = 1000 ps;
us = 1000 ns;
ms = 1000 us;
sec = 1000 ms;
min = 60 sec;
hr = 60 min;
end units;
subtype delay_length is time range 0 fs to time'high;
impure function now return delay_length;
subtype natural is integer range 0 to integer'high;
subtype positive is integer range 1 to integer'high;
type string is array (positive range <>) of character;
type bit_vector is array (natural range <>) of bit;
type file_open_kind is (
read_mode,
write_mode,
append_mode);
type file_open_status is (
open_ok,
status_error,
name_error,
mode_error);
attribute foreign : string;
end standard;
|
mit
|
279ba2a3a6a37a5bc895675afc7393e8
| 0.51925 | 2.564557 | false | false | false | false |
andrewandrepowell/kernel-on-chip
|
hdl/projects/Nexys4/plasoc_cpu_2_crossbar_wrap.vhd
| 1 | 45,569 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.plasoc_crossbar_pack.plasoc_crossbar;
use work.plasoc_cpu_2_crossbar_wrap_pack.all;
entity plasoc_cpu_2_crossbar_wrap is
generic
(
axi_address_width : integer := 32;
axi_data_width : integer := 32;
axi_slave_id_width : integer := 0;
axi_master_amount : integer := 5;
axi_slave_amount : integer := 1;
axi_master_base_address : std_logic_vector := X"f0030000f0020000f0010000f000000000000000";
axi_master_high_address : std_logic_vector := X"f003fffff002fffff001fffff000ffffefffffff"
);
port
(
cpu_s_axi_awid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
cpu_s_axi_awlen : in std_logic_vector(7 downto 0);
cpu_s_axi_awsize : in std_logic_vector(2 downto 0);
cpu_s_axi_awburst : in std_logic_vector(1 downto 0);
cpu_s_axi_awlock : in std_logic;
cpu_s_axi_awcache : in std_logic_vector(3 downto 0);
cpu_s_axi_awprot : in std_logic_vector(2 downto 0);
cpu_s_axi_awqos : in std_logic_vector(3 downto 0);
cpu_s_axi_awregion : in std_logic_vector(3 downto 0);
cpu_s_axi_awvalid : in std_logic;
cpu_s_axi_awready : out std_logic;
cpu_s_axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
cpu_s_axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
cpu_s_axi_wlast : in std_logic;
cpu_s_axi_wvalid : in std_logic;
cpu_s_axi_wready : out std_logic;
cpu_s_axi_bid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_bresp : out std_logic_vector(1 downto 0);
cpu_s_axi_bvalid : out std_logic;
cpu_s_axi_bready : in std_logic;
cpu_s_axi_arid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
cpu_s_axi_arlen : in std_logic_vector(7 downto 0);
cpu_s_axi_arsize : in std_logic_vector(2 downto 0);
cpu_s_axi_arburst : in std_logic_vector(1 downto 0);
cpu_s_axi_arlock : in std_logic;
cpu_s_axi_arcache : in std_logic_vector(3 downto 0);
cpu_s_axi_arprot : in std_logic_vector(2 downto 0);
cpu_s_axi_arqos : in std_logic_vector(3 downto 0);
cpu_s_axi_arregion : in std_logic_vector(3 downto 0);
cpu_s_axi_arvalid : in std_logic;
cpu_s_axi_arready : out std_logic;
cpu_s_axi_rid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_rdata : out std_logic_vector(axi_data_width-1 downto 0);
cpu_s_axi_rresp : out std_logic_vector(1 downto 0);
cpu_s_axi_rlast : out std_logic;
cpu_s_axi_rvalid : out std_logic;
cpu_s_axi_rready : in std_logic;
ip_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ip_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
ip_m_axi_awlen : out std_logic_vector(7 downto 0);
ip_m_axi_awsize : out std_logic_vector(2 downto 0);
ip_m_axi_awburst : out std_logic_vector(1 downto 0);
ip_m_axi_awlock : out std_logic;
ip_m_axi_awcache : out std_logic_vector(3 downto 0);
ip_m_axi_awprot : out std_logic_vector(2 downto 0);
ip_m_axi_awqos : out std_logic_vector(3 downto 0);
ip_m_axi_awregion : out std_logic_vector(3 downto 0);
ip_m_axi_awvalid : out std_logic;
ip_m_axi_awready : in std_logic;
ip_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
ip_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
ip_m_axi_wlast : out std_logic;
ip_m_axi_wvalid : out std_logic;
ip_m_axi_wready : in std_logic;
ip_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ip_m_axi_bresp : in std_logic_vector(1 downto 0);
ip_m_axi_bvalid : in std_logic;
ip_m_axi_bready : out std_logic;
ip_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ip_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
ip_m_axi_arlen : out std_logic_vector(7 downto 0);
ip_m_axi_arsize : out std_logic_vector(2 downto 0);
ip_m_axi_arburst : out std_logic_vector(1 downto 0);
ip_m_axi_arlock : out std_logic;
ip_m_axi_arcache : out std_logic_vector(3 downto 0);
ip_m_axi_arprot : out std_logic_vector(2 downto 0);
ip_m_axi_arqos : out std_logic_vector(3 downto 0);
ip_m_axi_arregion : out std_logic_vector(3 downto 0);
ip_m_axi_arvalid : out std_logic;
ip_m_axi_arready : in std_logic;
ip_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ip_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
ip_m_axi_rresp : in std_logic_vector(1 downto 0);
ip_m_axi_rlast : in std_logic;
ip_m_axi_rvalid : in std_logic;
ip_m_axi_rready : out std_logic;
cpuid_gpio_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cpuid_gpio_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
cpuid_gpio_m_axi_awlen : out std_logic_vector(7 downto 0);
cpuid_gpio_m_axi_awsize : out std_logic_vector(2 downto 0);
cpuid_gpio_m_axi_awburst : out std_logic_vector(1 downto 0);
cpuid_gpio_m_axi_awlock : out std_logic;
cpuid_gpio_m_axi_awcache : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_awprot : out std_logic_vector(2 downto 0);
cpuid_gpio_m_axi_awqos : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_awregion : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_awvalid : out std_logic;
cpuid_gpio_m_axi_awready : in std_logic;
cpuid_gpio_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
cpuid_gpio_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
cpuid_gpio_m_axi_wlast : out std_logic;
cpuid_gpio_m_axi_wvalid : out std_logic;
cpuid_gpio_m_axi_wready : in std_logic;
cpuid_gpio_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cpuid_gpio_m_axi_bresp : in std_logic_vector(1 downto 0);
cpuid_gpio_m_axi_bvalid : in std_logic;
cpuid_gpio_m_axi_bready : out std_logic;
cpuid_gpio_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cpuid_gpio_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
cpuid_gpio_m_axi_arlen : out std_logic_vector(7 downto 0);
cpuid_gpio_m_axi_arsize : out std_logic_vector(2 downto 0);
cpuid_gpio_m_axi_arburst : out std_logic_vector(1 downto 0);
cpuid_gpio_m_axi_arlock : out std_logic;
cpuid_gpio_m_axi_arcache : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_arprot : out std_logic_vector(2 downto 0);
cpuid_gpio_m_axi_arqos : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_arregion : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_arvalid : out std_logic;
cpuid_gpio_m_axi_arready : in std_logic;
cpuid_gpio_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cpuid_gpio_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
cpuid_gpio_m_axi_rresp : in std_logic_vector(1 downto 0);
cpuid_gpio_m_axi_rlast : in std_logic;
cpuid_gpio_m_axi_rvalid : in std_logic;
cpuid_gpio_m_axi_rready : out std_logic;
int_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
int_m_axi_awlen : out std_logic_vector(7 downto 0);
int_m_axi_awsize : out std_logic_vector(2 downto 0);
int_m_axi_awburst : out std_logic_vector(1 downto 0);
int_m_axi_awlock : out std_logic;
int_m_axi_awcache : out std_logic_vector(3 downto 0);
int_m_axi_awprot : out std_logic_vector(2 downto 0);
int_m_axi_awqos : out std_logic_vector(3 downto 0);
int_m_axi_awregion : out std_logic_vector(3 downto 0);
int_m_axi_awvalid : out std_logic;
int_m_axi_awready : in std_logic;
int_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
int_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
int_m_axi_wlast : out std_logic;
int_m_axi_wvalid : out std_logic;
int_m_axi_wready : in std_logic;
int_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_bresp : in std_logic_vector(1 downto 0);
int_m_axi_bvalid : in std_logic;
int_m_axi_bready : out std_logic;
int_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
int_m_axi_arlen : out std_logic_vector(7 downto 0);
int_m_axi_arsize : out std_logic_vector(2 downto 0);
int_m_axi_arburst : out std_logic_vector(1 downto 0);
int_m_axi_arlock : out std_logic;
int_m_axi_arcache : out std_logic_vector(3 downto 0);
int_m_axi_arprot : out std_logic_vector(2 downto 0);
int_m_axi_arqos : out std_logic_vector(3 downto 0);
int_m_axi_arregion : out std_logic_vector(3 downto 0);
int_m_axi_arvalid : out std_logic;
int_m_axi_arready : in std_logic;
int_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
int_m_axi_rresp : in std_logic_vector(1 downto 0);
int_m_axi_rlast : in std_logic;
int_m_axi_rvalid : in std_logic;
int_m_axi_rready : out std_logic;
signal_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
signal_m_axi_awlen : out std_logic_vector(7 downto 0);
signal_m_axi_awsize : out std_logic_vector(2 downto 0);
signal_m_axi_awburst : out std_logic_vector(1 downto 0);
signal_m_axi_awlock : out std_logic;
signal_m_axi_awcache : out std_logic_vector(3 downto 0);
signal_m_axi_awprot : out std_logic_vector(2 downto 0);
signal_m_axi_awqos : out std_logic_vector(3 downto 0);
signal_m_axi_awregion : out std_logic_vector(3 downto 0);
signal_m_axi_awvalid : out std_logic;
signal_m_axi_awready : in std_logic;
signal_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
signal_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
signal_m_axi_wlast : out std_logic;
signal_m_axi_wvalid : out std_logic;
signal_m_axi_wready : in std_logic;
signal_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal_m_axi_bresp : in std_logic_vector(1 downto 0);
signal_m_axi_bvalid : in std_logic;
signal_m_axi_bready : out std_logic;
signal_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
signal_m_axi_arlen : out std_logic_vector(7 downto 0);
signal_m_axi_arsize : out std_logic_vector(2 downto 0);
signal_m_axi_arburst : out std_logic_vector(1 downto 0);
signal_m_axi_arlock : out std_logic;
signal_m_axi_arcache : out std_logic_vector(3 downto 0);
signal_m_axi_arprot : out std_logic_vector(2 downto 0);
signal_m_axi_arqos : out std_logic_vector(3 downto 0);
signal_m_axi_arregion : out std_logic_vector(3 downto 0);
signal_m_axi_arvalid : out std_logic;
signal_m_axi_arready : in std_logic;
signal_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
signal_m_axi_rresp : in std_logic_vector(1 downto 0);
signal_m_axi_rlast : in std_logic;
signal_m_axi_rvalid : in std_logic;
signal_m_axi_rready : out std_logic;
timer_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
timer_m_axi_awlen : out std_logic_vector(7 downto 0);
timer_m_axi_awsize : out std_logic_vector(2 downto 0);
timer_m_axi_awburst : out std_logic_vector(1 downto 0);
timer_m_axi_awlock : out std_logic;
timer_m_axi_awcache : out std_logic_vector(3 downto 0);
timer_m_axi_awprot : out std_logic_vector(2 downto 0);
timer_m_axi_awqos : out std_logic_vector(3 downto 0);
timer_m_axi_awregion : out std_logic_vector(3 downto 0);
timer_m_axi_awvalid : out std_logic;
timer_m_axi_awready : in std_logic;
timer_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
timer_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
timer_m_axi_wlast : out std_logic;
timer_m_axi_wvalid : out std_logic;
timer_m_axi_wready : in std_logic;
timer_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_bresp : in std_logic_vector(1 downto 0);
timer_m_axi_bvalid : in std_logic;
timer_m_axi_bready : out std_logic;
timer_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
timer_m_axi_arlen : out std_logic_vector(7 downto 0);
timer_m_axi_arsize : out std_logic_vector(2 downto 0);
timer_m_axi_arburst : out std_logic_vector(1 downto 0);
timer_m_axi_arlock : out std_logic;
timer_m_axi_arcache : out std_logic_vector(3 downto 0);
timer_m_axi_arprot : out std_logic_vector(2 downto 0);
timer_m_axi_arqos : out std_logic_vector(3 downto 0);
timer_m_axi_arregion : out std_logic_vector(3 downto 0);
timer_m_axi_arvalid : out std_logic;
timer_m_axi_arready : in std_logic;
timer_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
timer_m_axi_rresp : in std_logic_vector(1 downto 0);
timer_m_axi_rlast : in std_logic;
timer_m_axi_rvalid : in std_logic;
timer_m_axi_rready : out std_logic;
aclk : in std_logic;
aresetn : in std_logic
);
end plasoc_cpu_2_crossbar_wrap;
architecture Behavioral of plasoc_cpu_2_crossbar_wrap is
constant axi_master_id_width : integer := clogb2(axi_slave_amount)+axi_slave_id_width;
signal s_axi_awid : std_logic_vector(axi_slave_amount*axi_slave_id_width-1 downto 0);
signal s_axi_awaddr : std_logic_vector(axi_slave_amount*axi_address_width-1 downto 0);
signal s_axi_awlen : std_logic_vector(axi_slave_amount*8-1 downto 0);
signal s_axi_awsize : std_logic_vector(axi_slave_amount*3-1 downto 0);
signal s_axi_awburst : std_logic_vector(axi_slave_amount*2-1 downto 0);
signal s_axi_awlock : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_awcache : std_logic_vector(axi_slave_amount*4-1 downto 0);
signal s_axi_awprot : std_logic_vector(axi_slave_amount*3-1 downto 0);
signal s_axi_awqos : std_logic_vector(axi_slave_amount*4-1 downto 0);
signal s_axi_awregion : std_logic_vector(axi_slave_amount*4-1 downto 0);
signal s_axi_awvalid : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_awready : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_wdata : std_logic_vector(axi_slave_amount*axi_data_width-1 downto 0);
signal s_axi_wstrb : std_logic_vector(axi_slave_amount*axi_data_width/8-1 downto 0);
signal s_axi_wlast : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_wvalid : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_wready : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_bid : std_logic_vector(axi_slave_amount*axi_slave_id_width-1 downto 0);
signal s_axi_bresp : std_logic_vector(axi_slave_amount*2-1 downto 0);
signal s_axi_bvalid : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_bready : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_arid : std_logic_vector(axi_slave_amount*axi_slave_id_width-1 downto 0);
signal s_axi_araddr : std_logic_vector(axi_slave_amount*axi_address_width-1 downto 0);
signal s_axi_arlen : std_logic_vector(axi_slave_amount*8-1 downto 0);
signal s_axi_arsize : std_logic_vector(axi_slave_amount*3-1 downto 0);
signal s_axi_arburst : std_logic_vector(axi_slave_amount*2-1 downto 0);
signal s_axi_arlock : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_arcache : std_logic_vector(axi_slave_amount*4-1 downto 0);
signal s_axi_arprot : std_logic_vector(axi_slave_amount*3-1 downto 0);
signal s_axi_arqos : std_logic_vector(axi_slave_amount*4-1 downto 0);
signal s_axi_arregion : std_logic_vector(axi_slave_amount*4-1 downto 0);
signal s_axi_arvalid : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_arready : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_rid : std_logic_vector(axi_slave_amount*axi_slave_id_width-1 downto 0);
signal s_axi_rdata : std_logic_vector(axi_slave_amount*axi_data_width-1 downto 0);
signal s_axi_rresp : std_logic_vector(axi_slave_amount*2-1 downto 0);
signal s_axi_rlast : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_rvalid : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_rready : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal m_axi_awid : std_logic_vector(axi_master_amount*(clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal m_axi_awaddr : std_logic_vector(axi_master_amount*axi_address_width-1 downto 0);
signal m_axi_awlen : std_logic_vector(axi_master_amount*8-1 downto 0);
signal m_axi_awsize : std_logic_vector(axi_master_amount*3-1 downto 0);
signal m_axi_awburst : std_logic_vector(axi_master_amount*2-1 downto 0);
signal m_axi_awlock : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_awcache : std_logic_vector(axi_master_amount*4-1 downto 0);
signal m_axi_awprot : std_logic_vector(axi_master_amount*3-1 downto 0);
signal m_axi_awqos : std_logic_vector(axi_master_amount*4-1 downto 0);
signal m_axi_awregion : std_logic_vector(axi_master_amount*4-1 downto 0);
signal m_axi_awvalid : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_awready : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_wdata : std_logic_vector(axi_master_amount*axi_data_width-1 downto 0);
signal m_axi_wstrb : std_logic_vector(axi_master_amount*axi_data_width/8-1 downto 0);
signal m_axi_wlast : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_wvalid : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_wready : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_bid : std_logic_vector(axi_master_amount*(clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal m_axi_bresp : std_logic_vector(axi_master_amount*2-1 downto 0);
signal m_axi_bvalid : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_bready : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_arid : std_logic_vector(axi_master_amount*(clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal m_axi_araddr : std_logic_vector(axi_master_amount*axi_address_width-1 downto 0);
signal m_axi_arlen : std_logic_vector(axi_master_amount*8-1 downto 0);
signal m_axi_arsize : std_logic_vector(axi_master_amount*3-1 downto 0);
signal m_axi_arburst : std_logic_vector(axi_master_amount*2-1 downto 0);
signal m_axi_arlock : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_arcache : std_logic_vector(axi_master_amount*4-1 downto 0);
signal m_axi_arprot : std_logic_vector(axi_master_amount*3-1 downto 0);
signal m_axi_arqos : std_logic_vector(axi_master_amount*4-1 downto 0);
signal m_axi_arregion : std_logic_vector(axi_master_amount*4-1 downto 0);
signal m_axi_arvalid : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_arready : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_rid : std_logic_vector(axi_master_amount*(clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal m_axi_rdata : std_logic_vector(axi_master_amount*axi_data_width-1 downto 0);
signal m_axi_rresp : std_logic_vector(axi_master_amount*2-1 downto 0);
signal m_axi_rlast : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_rvalid : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_rready : std_logic_vector(axi_master_amount*1-1 downto 0);
signal s_address_write_connected : std_logic_vector(axi_slave_amount-1 downto 0);
signal s_data_write_connected : std_logic_vector(axi_slave_amount-1 downto 0);
signal s_response_write_connected : std_logic_vector(axi_slave_amount-1 downto 0);
signal s_address_read_connected : std_logic_vector(axi_slave_amount-1 downto 0);
signal s_data_read_connected : std_logic_vector(axi_slave_amount-1 downto 0);
signal m_address_write_connected : std_logic_vector(axi_master_amount-1 downto 0);
signal m_data_write_connected : std_logic_vector(axi_master_amount-1 downto 0);
signal m_response_write_connected : std_logic_vector(axi_master_amount-1 downto 0);
signal m_address_read_connected : std_logic_vector(axi_master_amount-1 downto 0);
signal m_data_read_connected : std_logic_vector(axi_master_amount-1 downto 0);
begin
s_axi_awid <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awid;
s_axi_awaddr <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awaddr;
s_axi_awlen <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awlen;
s_axi_awsize <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awsize;
s_axi_awburst <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awburst;
s_axi_awlock <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awlock;
s_axi_awcache <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awcache;
s_axi_awprot <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awprot;
s_axi_awqos <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awqos;
s_axi_awregion <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awregion;
s_axi_awvalid <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awvalid;
s_axi_wdata <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_wdata;
s_axi_wstrb <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_wstrb;
s_axi_wlast <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_wlast;
s_axi_wvalid <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_wvalid;
s_axi_bready <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_bready;
s_axi_arid <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arid;
s_axi_araddr <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_araddr;
s_axi_arlen <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arlen;
s_axi_arsize <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arsize;
s_axi_arburst <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arburst;
s_axi_arlock <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arlock;
s_axi_arcache <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arcache;
s_axi_arprot <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arprot;
s_axi_arqos <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arqos;
s_axi_arregion <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arregion;
s_axi_arvalid <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arvalid;
s_axi_rready <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_rready;
m_axi_awready <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_awready & signal_m_axi_awready & int_m_axi_awready & cpuid_gpio_m_axi_awready & ip_m_axi_awready;
m_axi_wready <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_wready & signal_m_axi_wready & int_m_axi_wready & cpuid_gpio_m_axi_wready & ip_m_axi_wready;
m_axi_bid <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_bid & signal_m_axi_bid & int_m_axi_bid & cpuid_gpio_m_axi_bid & ip_m_axi_bid;
m_axi_bresp <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_bresp & signal_m_axi_bresp & int_m_axi_bresp & cpuid_gpio_m_axi_bresp & ip_m_axi_bresp;
m_axi_bvalid <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_bvalid & signal_m_axi_bvalid & int_m_axi_bvalid & cpuid_gpio_m_axi_bvalid & ip_m_axi_bvalid;
m_axi_arready <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_arready & signal_m_axi_arready & int_m_axi_arready & cpuid_gpio_m_axi_arready & ip_m_axi_arready;
m_axi_rid <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_rid & signal_m_axi_rid & int_m_axi_rid & cpuid_gpio_m_axi_rid & ip_m_axi_rid;
m_axi_rdata <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_rdata & signal_m_axi_rdata & int_m_axi_rdata & cpuid_gpio_m_axi_rdata & ip_m_axi_rdata;
m_axi_rresp <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_rresp & signal_m_axi_rresp & int_m_axi_rresp & cpuid_gpio_m_axi_rresp & ip_m_axi_rresp;
m_axi_rlast <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_rlast & signal_m_axi_rlast & int_m_axi_rlast & cpuid_gpio_m_axi_rlast & ip_m_axi_rlast;
m_axi_rvalid <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_rvalid & signal_m_axi_rvalid & int_m_axi_rvalid & cpuid_gpio_m_axi_rvalid & ip_m_axi_rvalid;
cpu_s_axi_awready <= '0' when s_address_write_connected(0)='0' else s_axi_awready(0);
cpu_s_axi_wready <= '0' when s_data_write_connected(0)='0' else s_axi_wready(0);
cpu_s_axi_bid <= (others=>'0') when s_response_write_connected(0)='0' else s_axi_bid((1+0)*axi_slave_id_width-1 downto 0*axi_slave_id_width);
cpu_s_axi_bresp <= (others=>'0') when s_response_write_connected(0)='0' else s_axi_bresp((1+0)*2-1 downto 0*2);
cpu_s_axi_bvalid <= '0' when s_response_write_connected(0)='0' else s_axi_bvalid(0);
cpu_s_axi_arready <= '0' when s_address_read_connected(0)='0' else s_axi_arready(0);
cpu_s_axi_rid <= (others=>'0') when s_data_read_connected(0)='0' else s_axi_rid((1+0)*axi_slave_id_width-1 downto 0*axi_slave_id_width);
cpu_s_axi_rdata <= (others=>'0') when s_data_read_connected(0)='0' else s_axi_rdata((1+0)*axi_data_width-1 downto 0*axi_data_width);
cpu_s_axi_rresp <= (others=>'0') when s_data_read_connected(0)='0' else s_axi_rresp((1+0)*2-1 downto 0*2);
cpu_s_axi_rlast <= '0' when s_data_read_connected(0)='0' else s_axi_rlast(0);
cpu_s_axi_rvalid <= '0' when s_data_read_connected(0)='0' else s_axi_rvalid(0);
ip_m_axi_awid <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awid((1+0)*axi_master_id_width-1 downto 0*axi_master_id_width);
cpuid_gpio_m_axi_awid <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awid((1+1)*axi_master_id_width-1 downto 1*axi_master_id_width);
int_m_axi_awid <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awid((1+2)*axi_master_id_width-1 downto 2*axi_master_id_width);
signal_m_axi_awid <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awid((1+3)*axi_master_id_width-1 downto 3*axi_master_id_width);
timer_m_axi_awid <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awid((1+4)*axi_master_id_width-1 downto 4*axi_master_id_width);
ip_m_axi_awaddr <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awaddr((1+0)*axi_address_width-1 downto 0*axi_address_width);
cpuid_gpio_m_axi_awaddr <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awaddr((1+1)*axi_address_width-1 downto 1*axi_address_width);
int_m_axi_awaddr <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awaddr((1+2)*axi_address_width-1 downto 2*axi_address_width);
signal_m_axi_awaddr <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awaddr((1+3)*axi_address_width-1 downto 3*axi_address_width);
timer_m_axi_awaddr <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awaddr((1+4)*axi_address_width-1 downto 4*axi_address_width);
ip_m_axi_awlen <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awlen((1+0)*8-1 downto 0*8);
cpuid_gpio_m_axi_awlen <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awlen((1+1)*8-1 downto 1*8);
int_m_axi_awlen <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awlen((1+2)*8-1 downto 2*8);
signal_m_axi_awlen <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awlen((1+3)*8-1 downto 3*8);
timer_m_axi_awlen <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awlen((1+4)*8-1 downto 4*8);
ip_m_axi_awsize <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awsize((1+0)*3-1 downto 0*3);
cpuid_gpio_m_axi_awsize <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awsize((1+1)*3-1 downto 1*3);
int_m_axi_awsize <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awsize((1+2)*3-1 downto 2*3);
signal_m_axi_awsize <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awsize((1+3)*3-1 downto 3*3);
timer_m_axi_awsize <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awsize((1+4)*3-1 downto 4*3);
ip_m_axi_awburst <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awburst((1+0)*2-1 downto 0*2);
cpuid_gpio_m_axi_awburst <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awburst((1+1)*2-1 downto 1*2);
int_m_axi_awburst <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awburst((1+2)*2-1 downto 2*2);
signal_m_axi_awburst <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awburst((1+3)*2-1 downto 3*2);
timer_m_axi_awburst <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awburst((1+4)*2-1 downto 4*2);
ip_m_axi_awlock <= '0' when m_address_write_connected(0)='0' else m_axi_awlock(0);
cpuid_gpio_m_axi_awlock <= '0' when m_address_write_connected(1)='0' else m_axi_awlock(1);
int_m_axi_awlock <= '0' when m_address_write_connected(2)='0' else m_axi_awlock(2);
signal_m_axi_awlock <= '0' when m_address_write_connected(3)='0' else m_axi_awlock(3);
timer_m_axi_awlock <= '0' when m_address_write_connected(4)='0' else m_axi_awlock(4);
ip_m_axi_awcache <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awcache((1+0)*4-1 downto 0*4);
cpuid_gpio_m_axi_awcache <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awcache((1+1)*4-1 downto 1*4);
int_m_axi_awcache <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awcache((1+2)*4-1 downto 2*4);
signal_m_axi_awcache <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awcache((1+3)*4-1 downto 3*4);
timer_m_axi_awcache <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awcache((1+4)*4-1 downto 4*4);
ip_m_axi_awprot <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awprot((1+0)*3-1 downto 0*3);
cpuid_gpio_m_axi_awprot <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awprot((1+1)*3-1 downto 1*3);
int_m_axi_awprot <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awprot((1+2)*3-1 downto 2*3);
signal_m_axi_awprot <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awprot((1+3)*3-1 downto 3*3);
timer_m_axi_awprot <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awprot((1+4)*3-1 downto 4*3);
ip_m_axi_awqos <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awqos((1+0)*4-1 downto 0*4);
cpuid_gpio_m_axi_awqos <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awqos((1+1)*4-1 downto 1*4);
int_m_axi_awqos <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awqos((1+2)*4-1 downto 2*4);
signal_m_axi_awqos <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awqos((1+3)*4-1 downto 3*4);
timer_m_axi_awqos <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awqos((1+4)*4-1 downto 4*4);
ip_m_axi_awregion <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awregion((1+0)*4-1 downto 0*4);
cpuid_gpio_m_axi_awregion <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awregion((1+1)*4-1 downto 1*4);
int_m_axi_awregion <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awregion((1+2)*4-1 downto 2*4);
signal_m_axi_awregion <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awregion((1+3)*4-1 downto 3*4);
timer_m_axi_awregion <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awregion((1+4)*4-1 downto 4*4);
ip_m_axi_awvalid <= '0' when m_address_write_connected(0)='0' else m_axi_awvalid(0);
cpuid_gpio_m_axi_awvalid <= '0' when m_address_write_connected(1)='0' else m_axi_awvalid(1);
int_m_axi_awvalid <= '0' when m_address_write_connected(2)='0' else m_axi_awvalid(2);
signal_m_axi_awvalid <= '0' when m_address_write_connected(3)='0' else m_axi_awvalid(3);
timer_m_axi_awvalid <= '0' when m_address_write_connected(4)='0' else m_axi_awvalid(4);
ip_m_axi_wdata <= (others=>'0') when m_data_write_connected(0)='0' else m_axi_wdata((1+0)*axi_data_width-1 downto 0*axi_data_width);
cpuid_gpio_m_axi_wdata <= (others=>'0') when m_data_write_connected(1)='0' else m_axi_wdata((1+1)*axi_data_width-1 downto 1*axi_data_width);
int_m_axi_wdata <= (others=>'0') when m_data_write_connected(2)='0' else m_axi_wdata((1+2)*axi_data_width-1 downto 2*axi_data_width);
signal_m_axi_wdata <= (others=>'0') when m_data_write_connected(3)='0' else m_axi_wdata((1+3)*axi_data_width-1 downto 3*axi_data_width);
timer_m_axi_wdata <= (others=>'0') when m_data_write_connected(4)='0' else m_axi_wdata((1+4)*axi_data_width-1 downto 4*axi_data_width);
ip_m_axi_wstrb <= (others=>'0') when m_data_write_connected(0)='0' else m_axi_wstrb((1+0)*axi_data_width/8-1 downto 0*axi_data_width/8);
cpuid_gpio_m_axi_wstrb <= (others=>'0') when m_data_write_connected(1)='0' else m_axi_wstrb((1+1)*axi_data_width/8-1 downto 1*axi_data_width/8);
int_m_axi_wstrb <= (others=>'0') when m_data_write_connected(2)='0' else m_axi_wstrb((1+2)*axi_data_width/8-1 downto 2*axi_data_width/8);
signal_m_axi_wstrb <= (others=>'0') when m_data_write_connected(3)='0' else m_axi_wstrb((1+3)*axi_data_width/8-1 downto 3*axi_data_width/8);
timer_m_axi_wstrb <= (others=>'0') when m_data_write_connected(4)='0' else m_axi_wstrb((1+4)*axi_data_width/8-1 downto 4*axi_data_width/8);
ip_m_axi_wlast <= '0' when m_data_write_connected(0)='0' else m_axi_wlast(0);
cpuid_gpio_m_axi_wlast <= '0' when m_data_write_connected(1)='0' else m_axi_wlast(1);
int_m_axi_wlast <= '0' when m_data_write_connected(2)='0' else m_axi_wlast(2);
signal_m_axi_wlast <= '0' when m_data_write_connected(3)='0' else m_axi_wlast(3);
timer_m_axi_wlast <= '0' when m_data_write_connected(4)='0' else m_axi_wlast(4);
ip_m_axi_wvalid <= '0' when m_data_write_connected(0)='0' else m_axi_wvalid(0);
cpuid_gpio_m_axi_wvalid <= '0' when m_data_write_connected(1)='0' else m_axi_wvalid(1);
int_m_axi_wvalid <= '0' when m_data_write_connected(2)='0' else m_axi_wvalid(2);
signal_m_axi_wvalid <= '0' when m_data_write_connected(3)='0' else m_axi_wvalid(3);
timer_m_axi_wvalid <= '0' when m_data_write_connected(4)='0' else m_axi_wvalid(4);
ip_m_axi_bready <= '0' when m_response_write_connected(0)='0' else m_axi_bready(0);
cpuid_gpio_m_axi_bready <= '0' when m_response_write_connected(1)='0' else m_axi_bready(1);
int_m_axi_bready <= '0' when m_response_write_connected(2)='0' else m_axi_bready(2);
signal_m_axi_bready <= '0' when m_response_write_connected(3)='0' else m_axi_bready(3);
timer_m_axi_bready <= '0' when m_response_write_connected(4)='0' else m_axi_bready(4);
ip_m_axi_arid <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arid((1+0)*axi_master_id_width-1 downto 0*axi_master_id_width);
cpuid_gpio_m_axi_arid <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arid((1+1)*axi_master_id_width-1 downto 1*axi_master_id_width);
int_m_axi_arid <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arid((1+2)*axi_master_id_width-1 downto 2*axi_master_id_width);
signal_m_axi_arid <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arid((1+3)*axi_master_id_width-1 downto 3*axi_master_id_width);
timer_m_axi_arid <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arid((1+4)*axi_master_id_width-1 downto 4*axi_master_id_width);
ip_m_axi_araddr <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_araddr((1+0)*axi_address_width-1 downto 0*axi_address_width);
cpuid_gpio_m_axi_araddr <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_araddr((1+1)*axi_address_width-1 downto 1*axi_address_width);
int_m_axi_araddr <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_araddr((1+2)*axi_address_width-1 downto 2*axi_address_width);
signal_m_axi_araddr <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_araddr((1+3)*axi_address_width-1 downto 3*axi_address_width);
timer_m_axi_araddr <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_araddr((1+4)*axi_address_width-1 downto 4*axi_address_width);
ip_m_axi_arlen <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arlen((1+0)*8-1 downto 0*8);
cpuid_gpio_m_axi_arlen <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arlen((1+1)*8-1 downto 1*8);
int_m_axi_arlen <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arlen((1+2)*8-1 downto 2*8);
signal_m_axi_arlen <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arlen((1+3)*8-1 downto 3*8);
timer_m_axi_arlen <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arlen((1+4)*8-1 downto 4*8);
ip_m_axi_arsize <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arsize((1+0)*3-1 downto 0*3);
cpuid_gpio_m_axi_arsize <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arsize((1+1)*3-1 downto 1*3);
int_m_axi_arsize <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arsize((1+2)*3-1 downto 2*3);
signal_m_axi_arsize <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arsize((1+3)*3-1 downto 3*3);
timer_m_axi_arsize <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arsize((1+4)*3-1 downto 4*3);
ip_m_axi_arburst <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arburst((1+0)*2-1 downto 0*2);
cpuid_gpio_m_axi_arburst <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arburst((1+1)*2-1 downto 1*2);
int_m_axi_arburst <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arburst((1+2)*2-1 downto 2*2);
signal_m_axi_arburst <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arburst((1+3)*2-1 downto 3*2);
timer_m_axi_arburst <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arburst((1+4)*2-1 downto 4*2);
ip_m_axi_arlock <= '0' when m_address_read_connected(0)='0' else m_axi_arlock(0);
cpuid_gpio_m_axi_arlock <= '0' when m_address_read_connected(1)='0' else m_axi_arlock(1);
int_m_axi_arlock <= '0' when m_address_read_connected(2)='0' else m_axi_arlock(2);
signal_m_axi_arlock <= '0' when m_address_read_connected(3)='0' else m_axi_arlock(3);
timer_m_axi_arlock <= '0' when m_address_read_connected(4)='0' else m_axi_arlock(4);
ip_m_axi_arcache <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arcache((1+0)*4-1 downto 0*4);
cpuid_gpio_m_axi_arcache <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arcache((1+1)*4-1 downto 1*4);
int_m_axi_arcache <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arcache((1+2)*4-1 downto 2*4);
signal_m_axi_arcache <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arcache((1+3)*4-1 downto 3*4);
timer_m_axi_arcache <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arcache((1+4)*4-1 downto 4*4);
ip_m_axi_arprot <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arprot((1+0)*3-1 downto 0*3);
cpuid_gpio_m_axi_arprot <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arprot((1+1)*3-1 downto 1*3);
int_m_axi_arprot <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arprot((1+2)*3-1 downto 2*3);
signal_m_axi_arprot <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arprot((1+3)*3-1 downto 3*3);
timer_m_axi_arprot <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arprot((1+4)*3-1 downto 4*3);
ip_m_axi_arqos <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arqos((1+0)*4-1 downto 0*4);
cpuid_gpio_m_axi_arqos <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arqos((1+1)*4-1 downto 1*4);
int_m_axi_arqos <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arqos((1+2)*4-1 downto 2*4);
signal_m_axi_arqos <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arqos((1+3)*4-1 downto 3*4);
timer_m_axi_arqos <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arqos((1+4)*4-1 downto 4*4);
ip_m_axi_arregion <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arregion((1+0)*4-1 downto 0*4);
cpuid_gpio_m_axi_arregion <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arregion((1+1)*4-1 downto 1*4);
int_m_axi_arregion <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arregion((1+2)*4-1 downto 2*4);
signal_m_axi_arregion <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arregion((1+3)*4-1 downto 3*4);
timer_m_axi_arregion <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arregion((1+4)*4-1 downto 4*4);
ip_m_axi_arvalid <= '0' when m_address_read_connected(0)='0' else m_axi_arvalid(0);
cpuid_gpio_m_axi_arvalid <= '0' when m_address_read_connected(1)='0' else m_axi_arvalid(1);
int_m_axi_arvalid <= '0' when m_address_read_connected(2)='0' else m_axi_arvalid(2);
signal_m_axi_arvalid <= '0' when m_address_read_connected(3)='0' else m_axi_arvalid(3);
timer_m_axi_arvalid <= '0' when m_address_read_connected(4)='0' else m_axi_arvalid(4);
ip_m_axi_rready <= '0' when m_data_read_connected(0)='0' else m_axi_rready(0);
cpuid_gpio_m_axi_rready <= '0' when m_data_read_connected(1)='0' else m_axi_rready(1);
int_m_axi_rready <= '0' when m_data_read_connected(2)='0' else m_axi_rready(2);
signal_m_axi_rready <= '0' when m_data_read_connected(3)='0' else m_axi_rready(3);
timer_m_axi_rready <= '0' when m_data_read_connected(4)='0' else m_axi_rready(4);
plasoc_crossbar_inst : plasoc_crossbar
generic map
(
axi_address_width => axi_address_width,
axi_data_width => axi_data_width,
axi_master_amount => axi_master_amount,
axi_slave_id_width => axi_slave_id_width,
axi_slave_amount => axi_slave_amount,
axi_master_base_address => axi_master_base_address,
axi_master_high_address => axi_master_high_address
)
port map
(
aclk => aclk,
aresetn => aresetn,
s_address_write_connected => s_address_write_connected,
s_data_write_connected => s_data_write_connected,
s_response_write_connected => s_response_write_connected,
s_address_read_connected => s_address_read_connected,
s_data_read_connected => s_data_read_connected,
m_address_write_connected => m_address_write_connected,
m_data_write_connected => m_data_write_connected,
m_response_write_connected => m_response_write_connected,
m_address_read_connected => m_address_read_connected,
m_data_read_connected => m_data_read_connected,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awqos => s_axi_awqos,
s_axi_awregion => s_axi_awregion,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arqos => s_axi_arqos,
s_axi_arregion => s_axi_arregion,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
m_axi_awid => m_axi_awid,
m_axi_awaddr => m_axi_awaddr,
m_axi_awlen => m_axi_awlen,
m_axi_awsize => m_axi_awsize,
m_axi_awburst => m_axi_awburst,
m_axi_awlock => m_axi_awlock,
m_axi_awcache => m_axi_awcache,
m_axi_awprot => m_axi_awprot,
m_axi_awqos => m_axi_awqos,
m_axi_awregion => m_axi_awregion,
m_axi_awvalid => m_axi_awvalid,
m_axi_awready => m_axi_awready,
m_axi_wdata => m_axi_wdata,
m_axi_wstrb => m_axi_wstrb,
m_axi_wlast => m_axi_wlast,
m_axi_wvalid => m_axi_wvalid,
m_axi_wready => m_axi_wready,
m_axi_bid => m_axi_bid,
m_axi_bresp => m_axi_bresp,
m_axi_bvalid => m_axi_bvalid,
m_axi_bready => m_axi_bready,
m_axi_arid => m_axi_arid,
m_axi_araddr => m_axi_araddr,
m_axi_arlen => m_axi_arlen,
m_axi_arsize => m_axi_arsize,
m_axi_arburst => m_axi_arburst,
m_axi_arlock => m_axi_arlock,
m_axi_arcache => m_axi_arcache,
m_axi_arprot => m_axi_arprot,
m_axi_arqos => m_axi_arqos,
m_axi_arregion => m_axi_arregion,
m_axi_arvalid => m_axi_arvalid,
m_axi_arready => m_axi_arready,
m_axi_rid => m_axi_rid,
m_axi_rdata => m_axi_rdata,
m_axi_rresp => m_axi_rresp,
m_axi_rlast => m_axi_rlast,
m_axi_rvalid => m_axi_rvalid,
m_axi_rready => m_axi_rready
);
end Behavioral;
|
mit
|
3d062deca6814ae69bbe0967a092a135
| 0.681033 | 2.494881 | false | false | false | false |
JosiCoder/CtLab
|
FPGA/SPI Interface/Testbenches/SPI_SlaveAddressDecoderTester.vhd
| 1 | 3,807 |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Tests the SPI slave address decoder.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.TestTools.all;
entity SPI_SlaveAddressDecoder_Tester is
end entity;
architecture stdarch of SPI_SlaveAddressDecoder_Tester is
-- Constants
constant test_delay: time := 1ps;
constant address_width: positive := 3;
constant no_of_addresses: positive := 2**address_width;
-- Inputs
signal buffer_enable: std_logic := '1';
signal address: unsigned(address_width-1 downto 0) := (others => '0');
-- Outputs
signal buffer_enable_x: std_logic_vector(no_of_addresses-1 downto 0);
begin
--------------------------------------------------------------------------------
-- Instantiate the UUT(s).
--------------------------------------------------------------------------------
uut: entity work.SPI_SlaveAddressDecoder
generic map
(
address_width => address_width
)
port map
(
buffer_enable => buffer_enable,
address => address,
buffer_enable_x => buffer_enable_x
);
--------------------------------------------------------------------------------
-- Stimulate the UUT.
--------------------------------------------------------------------------------
stimulus: process is
variable expected_ss_x: std_logic_vector(buffer_enable_x'range);
begin
-- Wait for the UUT's initial output values to settle down and check them.
wait for test_delay;
assert (buffer_enable_x = (buffer_enable_x'range => '1'))
report "At least one buffer_enable_x unintentionally active."
severity error;
-- Enable the slave select.
buffer_enable <= '0';
-- Now provide consecutive addresses and check whether the buffer_enable_x signals
-- match them.
for i in 0 to no_of_addresses-1 loop
address <= to_unsigned(i, address_width);
wait for test_delay;
expected_ss_x := (buffer_enable_x'range => '1');
expected_ss_x(to_integer(address)) := '0';
assert (buffer_enable_x = expected_ss_x)
report "One or more buffer_enable_x not set correctly."
severity error;
end loop;
-- Disable the slave select again and check whether all buffer_enable_x signals
-- are deactivated.
buffer_enable <= '1';
wait for test_delay;
assert (buffer_enable_x = (buffer_enable_x'range => '1'))
report "At least one buffer_enable_x not deactivated."
severity error;
wait;
end process;
end architecture;
|
gpl-3.0
|
dddb633a292aaa03b31c2796b0800466
| 0.510113 | 4.950585 | false | true | false | false |
maijohnson/comp3601_blue_15s2
|
AudioController/CompSel.vhd
| 1 | 1,552 |
------------------------------------------------------------------------
-- CompSel.vhd -- Component Selector
------------------------------------------------------------------------
-- Author : Mircea Dabacan
-- Copyright 2004 Digilent, Inc.
------------------------------------------------------------------------
-- Software version: Xilinx ISE 6.2.03i
-- WebPack
------------------------------------------------------------------------
-- This file decodes the upper 5 bits of regEppAdrIn
-- to generate a "SELECT" signal named CS0_7.
-- CS0_7 is active (HIGH) whenever regEppAdrIn = "00000".
-- The selected component is assigned to the address range 0 to 7.
-- CompSel.vhd can be enhanced to select multiple components,
-- with various address ranges assigned.
------------------------------------------------------------------------
-- Revision History:
-- 10/21/2004(MirceaD): created
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CompSel is
Port (regEppAdrIn : in std_logic_vector(7 downto 0);
CS80_9F : out std_logic;
CS0_7 : out std_logic;
CS8_F : out std_logic);
end CompSel;
architecture Behavioral of CompSel is
begin
CS0_7 <= '1' when regEppAdrIn(7 downto 3) = "00000" else '0';
CS8_F <= '1' when regEppAdrIn(7 downto 3) = "00001" else '0';
CS80_9F <= '1' when regEppAdrIn(7 downto 5) = "100" else '0';
end Behavioral;
|
mit
|
02f579f4f5afcd178d2d10155729ee72
| 0.48067 | 4.409091 | false | false | false | false |
maijohnson/comp3601_blue_15s2
|
AudioController/PhoenixOnBoardMemCtrl.vhd
| 1 | 38,730 |
------------------------------------------------------------------------
-- PhoenixOnBoardMemCtrl.vhd -- Digilent C1 Memory Module programming controller
------------------------------------------------------------------------
-- Author : Mircea Dabacan
-- Copyright 2005 Digilent, Inc.
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1.03i
-- WebPack
------------------------------------------------------------------------
-- This is the source file for the PhoenixOnBoardMemCtrl component,
-- provided by the Digilent Component Library.
-- This file contains the design for a programming controller.
-- This component, in conjunction with a communication module
-- (Phoenix OnBoard USB controller),
-- a PC application program (a Digilent utility or user generated)
-- and the EppCtrl Digilent Library component allows the user to
-- read or write the RAM and Flash memory chips on the
-- Digilent Phoenix board.
------------------------------------------------------------------------
-- Behavioral description
------------------------------------------------------------------------
-- PhoenixOnBoardMemCtrl acts as a "client" for EppCtrl.
-- It implements the following Epp data registers:
------------------------------------------------------------------------
-- EPP Register Interface
-- Register Function
-- -------- --------
-- 0 Memory control register (read/write)
-- 1 Memory address bits 0-7 (read/write)
-- 2 Memory address bits 8-15 (read/write)
-- 3 Memory address bits 16-18 (read/write)
-- 4 Memory data write holding register (read/write) -see Note 1
-- 5 Memory data read register (read) - see Note 2
-- Registers 6 and 7 are used for block transfers
-- 6 RAM auto read/write register (read/write) - see Note 3
-- 7 Flash auto read/write register (read/write) - see Note 4
--
-- Reading from or writing to registers 0...5 generates a simple
-- Register Transfer (see the EppCtrl.vhd header):
-- the HandShakeReqOut is inactive when regEppAdrInDummy(2:0) = 0...5.
-- (see the EppCtrl.vhd Component Header)
-- Registers 6 and 7 belong to the "Process Launch" type,
-- both for read and write operations (see the EppCtrl.vhd header):
-- the HandShakeReqOut activates when regEppAdrInDummy(2:0) = 6...7.
-- Consequently, at each Epp Data Register read or write cycle for this
-- address, the EppCtrl component activates the ctlEppStart signal.
-- As response, the PhoenixOnBoardMemCtrl:
-- - performs the actions explained by Note 3 or 4.
-- - activates the ctlMsmDoneOut signal
-- - waits for the ctlEppStart signal to go inactive.
-- - inactivates the ctlMsmDoneOut signal
-- - returns to the idle state (stMsmReady)
--
-- Note 1: Writing to "registers" 6 or 7 updates register 4.
-- Note 2: This is not a physical register. The memory data bus content
-- is read at this address.
-- Note 3: Writing to "register" 6, when in byte mode:
-- - updates the register 4 content AND
-- - launches an automatic RAM write cycle (asynchronous mode):
-- - generates the appropriate control signal sequence
-- - increments the Memory address register by 1.
-- Reading from address 7, when in byte mode:
-- - launches an automatic RAM read cycle (asynchronous mode):
-- - generates the appropriate control signal sequence
-- - loads the AutoReadData register with the content of the
-- addressed Flash location
-- - increments the Memory address register by 1.
-- Writing to "register" 6, when in word mode and even address:
-- - launches a blind cycle to update the auxiliary register.
-- No RAM cycle is launched.
-- - increments the Memory address register by 1.
-- Writing to "register" 6, when in word mode and odd address:
-- - updates the register 4 content AND
-- - launches an automatic RAM write cycle (asynchronous mode):
-- - generates the appropriate control signal sequence
-- (a word is written to RAM:
-- - memory address bus is set to the word address (A0 = 0)
-- - memory data bus is set with the previous stored value
-- of auxiliary register as lower byte and curent value of
-- register 4 as higher byte)
-- - increments the Memory address register to the next even.
-- Reading from address 6, when in word mode and even address:
-- - launches an automatic RAM read cycle (asynchronous mode):
-- - generates the appropriate control signal sequence
-- - loads the AutoReadData register with the lower byte of
-- the addressed RAM location (sent over the Epp)
-- - loads the auxiliary register with the upper byte of
-- the addressed RAM location (not yet sent over the Epp)
-- - increments the Memory address register by 1.
-- Reading from address 6, when in word mode and odd address:
-- - launches a blind cycle to send the previous stored value
-- of the auxiliary register. No RAM cycle is performed.
-- - increments the Memory address register by 1.
--
-- Note 4: Writing to "register" 7, when in byte mode:
-- - updates the register 4 content AND
-- - launches an automatic Flash write cycle:
-- - generates the appropriate control signal sequence
-- - waits for the internal Flash write procedure to complete
-- - increments the Memory address register by 1.
-- Reading from address 7, when in byte mode:
-- - launches an automatic Flash read cycle:
-- - generates the appropriate control signal sequence
-- - loads the AutoReadData register with the content of the
-- addressed Flash location
-- - increments the Memory address register by 1.
-- Writing to "register" 7, when in word mode and even address:
-- - launches a blind cycle to update the auxiliary register.
-- No Flash cycle is launched.
-- - increments the Memory address register by 1.
-- Writing to "register" 7, when in word mode and odd address:
-- - updates the register 4 content AND
-- - launches an automatic Flash write cycle:
-- - generates the appropriate control signal sequence
-- (a word is written to Flash:
-- - memory address bus is set to the word address (A0 = 0)
-- - memory data bus is set with the previous stored value
-- of auxiliary register as lower byte and curent value of
-- register 4 as higher byte)
-- - waits for the internal Flash write procedure to complete
-- - increments the Memory address register to the next even.
-- Reading from address 7, when in word mode and even address:
-- - launches an automatic Flash read cycle:
-- - generates the appropriate control signal sequence
-- - loads the AutoReadData register with the lower byte of
-- the addressed Flash location (sent over the Epp)
-- - loads the auxiliary register with the upper byte of
-- the addressed Flash location (not yet sent over the Epp)
-- - increments the Memory address register by 1.
-- Reading from address 7, when in word mode and odd address:
-- - launches a blind cycle to send the previous stored value
-- of the auxiliary register. No Flash cycle is performed.
-- - increments the Memory address register by 1.
--
-- Memory control register
-- Bit Function
-- -------- --------
-- 0 (0x01) Output enable (read strobe) |
-- 1 (0x02) Write enable (write strobe) | active LOW signals
-- 2 (0x04) RAM chip select (not used) |
-- 3 (0x08) Flash chip select |
-- 4 (0x10) Memory module during programming
-- (memory is not available for a user application)
-- (not yet implemented)
-- 5 (0x20) Byte enable ('0') or word enable ('1')
-- The Epp interfaces can only handle 8 bit data.
-- Word mode (16 bit) is only available for Automatic Read/Write,
-- both RAM (using register 6) and Flash (using register 7).
-- A "Word write" operation consists in two Epp (byte) cycles:
-- the first one, at even address, launces a "blind cycle",
-- which only stores the lower data byte in an auxiliary register.
-- the second one, at odd address, combines the two data bytes to a
-- data word on the memory data bus, and writes it to memory.
-- A "Word read" operation consists in two Epp (byte) cycles:
-- the first one, at even address, reads the data word from memory,
-- sends the lower data byte over the Epp bus and stores the upper
-- byte in an auxiliary register.
-- the second one, at odd address, launces a "blind cycle",
-- which only sends the upper data byte over the Epp bus.
-- Manual mode is only allowed for Flash
-- (Celullar RAM would hold CS active to long, blocking refresh cycles)
-- Manual "Word" mode for flash reads the upper data bus byte for odd
-- addresses and the lower data bus byte for even addresses.
-- Manual "Byte" mode for flash reads the lower data bus byte
-- for both odd and even addresses:
-- These features are completely transparent to the Epp host, which only
-- needs to set the appropriate value in the Memory Control and
-- memory address registers and read/write the data registers (4...7).
------------------------------------------------------------------------
-- Revision History:
-- 10/21/2004(MirceaD): created
-- 12/19/2005(MirceaD): modified for PhoenixOnBoard Memory
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity PhoenixOnBoardMemCtrl is
Port(
clk : in std_logic; -- system clock (50MHz)
-- Epp interface signals
HandShakeReqOut: out std_logic; -- User Handshake Request
ctlMsmStartIn: in std_logic; -- Automatic process Start
ctlMsmDoneOut: out std_logic; -- Automatic process Done
ctlMsmDwrIn: in std_logic; -- Data Write pulse
ctlEppRdCycleIn: in std_logic; -- Indicates a READ Epp cycle
EppRdDataOut: inout std_logic_vector(7 downto 0);-- Data Input bus
EppWrDataIn: in std_logic_vector(7 downto 0); -- Data Output bus
regEppAdrIn: in std_logic_vector(7 downto 0) := "00000000";
-- Epp Address Register content (bits 7:3 ignored)
ComponentSelect : in std_logic;
-- active HIGH, selects the current MemCtrl instance
-- If a single "client" component (CxMemCfg or other) is connected
-- to a "host" component (EppCtrl or other), ComponentSelect signal
-- can be held permanently active (connected to Vcc).
-- When more "client" components (CxMemCfg or other) are connected
-- to a "host" component (EppCtrl or other), the ComponentSelect
-- input of each client must be synthesized by decoding the higher
-- bits of regEppAdrOut bus, such a way to provide a distinct
-- address range for each.
-- C1MemCfg component requires 8 Epp data registers
-- (address range xxxxx000...xxxxx111)
-- Memory bus signals
MemDB: inout std_logic_vector(15 downto 0);-- Memory data bus
MemAdr: out std_logic_vector(23 downto 1);-- Memory Address bus
FlashByte: out std_logic; -- Byte enable('0') or word enable('1')
RamCS: out std_logic; -- RAM CS
FlashCS: out std_logic; -- Flash CS
MemWR: out std_logic; -- memory write
MemOE: out std_logic; -- memory read (Output Enable),
-- also controls the MemDB direction
RamUB: out std_logic; -- RAM Upper byte enable
RamLB: out std_logic; -- RAM Lower byte enable
RamCre: out std_logic; -- Cfg Register enable
RamAdv: out std_logic; -- RAM Address Valid pin
RamClk: out std_logic; -- RAM Clock
RamWait: in std_logic; -- RAM Wait pin
FlashRp: out std_logic; -- Flash RP pin
FlashStSts: in std_logic; -- Flash ST-STS pin
MemCtrlEnabled: out std_logic; -- MemCtrl takes bus control
ReadReq: in std_logic;
DataRdy: out std_logic;
DataOut :out std_logic_vector(7 downto 0);
DataAck: in std_logic;
Reset: in std_logic
);
end PhoenixOnBoardMemCtrl;
architecture Behavioral of PhoenixOnBoardMemCtrl is
component debounce
PORT( clk : IN STD_LOGIC;
input : IN STD_LOGIC;
output : OUT STD_LOGIC);
end component;
------------------------------------------------------------------------
-- Constant and Signal Declarations
------------------------------------------------------------------------
-- The following constants define the state codes for the Memory
-- control state machine. This state machine controls the sequence
-- of operations needed to perform a write sequence or a read sequence
-- on either flash or RAM memory.
-- The states are such a way assigned that each transition
-- changes a single state register bit (Grey code - like)
constant stMsmReady: std_logic_vector(3 downto 0) := "0000";
constant stMsmFwr01: std_logic_vector(3 downto 0) := "0001";
constant stMsmFwr02: std_logic_vector(3 downto 0) := "0101";
constant stMsmFwr03: std_logic_vector(3 downto 0) := "0111";
constant stMsmFwr04: std_logic_vector(3 downto 0) := "1111";
constant stMsmFwr05: std_logic_vector(3 downto 0) := "1011";
constant stMsmFwr06: std_logic_vector(3 downto 0) := "1001";
constant stMsmFwr07: std_logic_vector(3 downto 0) := "1101";
constant stMsmAdInc: std_logic_vector(3 downto 0) := "1100";
constant stMsmDone : std_logic_vector(3 downto 0) := "1000";
constant stMsmBlind: std_logic_vector(3 downto 0) := "0100";
constant stMsmDir01: std_logic_vector(3 downto 0) := "0010";
constant stMsmDWr02: std_logic_vector(3 downto 0) := "0110";
constant stMsmDir03: std_logic_vector(3 downto 0) := "1110";
constant stMsmDRd02: std_logic_vector(3 downto 0) := "1010";
-- Epp Data register addresses
constant MemCtrlReg: std_logic_vector(2 downto 0) := "000";
-- 0 Memory control register (read/write)
constant MemAdrL: std_logic_vector(2 downto 0) := "001";
-- 1 Memory address bits 0-7 (read/write)
constant MemAdrM: std_logic_vector(2 downto 0) := "010";
-- 2 Memory address bits 8-15 (read/write)
constant MemAdrH: std_logic_vector(2 downto 0) := "011";
-- 3 Memory address bits 16-21 (read/write)
constant MemDataWr: std_logic_vector(2 downto 0) := "100";
-- 4 Memory data write holding register (read/write) - see Note 1
constant MemDataRd: std_logic_vector(2 downto 0) := "101";
-- 5 Memory data read register (read) - see Note 2
-- Register 7 is used for block transfers
constant RamAutoRW: std_logic_vector(2 downto 0) := "110";
-- 6 RAM auto write register (read/write) - see Note 4
constant FlashAutoRW: std_logic_vector(2 downto 0) := "111";
-- 7 Flash auto write register (read/write) - see Note 4
-- State register and next state for the FSMs
signal stMsmCur : std_logic_vector(3 downto 0) := stMsmReady;
signal stMsmNext : std_logic_vector(3 downto 0);
-- Counter used to generate delays
signal DelayCnt : std_logic_vector(4 downto 0);
-- The attribute lines below prevent the ISE compiler to extract and
-- optimize the state machines.
-- WebPack 5.1 doesn't need them (the default value is NO)
-- WebPack 6.2 has the default value YES, so without these lines,
-- it would "optimize" the state machines.
-- Although the overall circuit would be optimized, the particular goal
-- of "glitch free output signals" may not be reached.
-- That is the reason of implementing the state machine as described in
-- the constant declarations above.
attribute fsm_extract : string;
attribute fsm_extract of stMsmCur: signal is "no";
attribute fsm_extract of stMsmNext: signal is "no";
attribute fsm_encoding : string;
attribute fsm_encoding of stMsmCur: signal is "user";
attribute fsm_encoding of stMsmNext: signal is "user";
attribute signal_encoding : string;
attribute signal_encoding of stMsmCur: signal is "user";
attribute signal_encoding of stMsmNext: signal is "user";
-- Signals dealing with memory chips
signal regMemCtl: std_logic_vector(7 downto 0):= x"0f";
-- Memory Control register ( MemCtrl disabled )
signal regMemAdr: std_logic_vector(23 downto 0):= x"000000";
-- Memory Address register
signal carryoutL:std_logic:='0';
-- Carry out for memory address low byte
signal carryoutM:std_logic:='0';
-- Carry out for memory address middle byte
signal regMemWrData: std_logic_vector(15 downto 0) := x"0000";
-- Memory Write Data register
signal regMemRdData: std_logic_vector(7 downto 0) := x"00";
-- Memory Read Data register
signal regMemRdDataAux: std_logic_vector(7 downto 0) := x"00";
-- Auxiliary Memory Read Data register
signal busMemIn: std_logic_vector(15 downto 0);
--signal busMemInHigh: std_logic_vector(7 downto 0);
signal busMemOut: std_logic_vector(15 downto 0);
-- Signals in the memory control register
signal ctlMcrOe: std_logic; -- Output enable (read strobe)
signal ctlMcrWr: std_logic; -- Write enable (write strobe)
signal ctlMcrRAMCs: std_logic; -- RAM chip select
signal ctlMcrFlashCs: std_logic; -- Flash chip select
signal ctlMcrEnable: std_logic; -- '1' => Enables the MemCtrl
signal ctlMcrWord: std_logic; -- PC enerated Word signal
-- Byte enable ('0') or word enable ('1')
signal ctlMcrDir: std_logic; -- composed out of previous ones
-- Signals used by Memory control state machine
signal ctlMsmOe : std_logic;
signal ctlMsmWr : std_logic;
signal ctlMsmRAMCs : std_logic;
signal ctlMsmFlashCs : std_logic;
signal ctlMsmDir : std_logic;
signal ctlMsmAdrInc : std_logic;
signal ctlMsmWrCmd : std_logic;
signal ctlEppRdCycleInDummy : std_logic;
signal ctlMsmStartInDummy : std_logic;
signal regEppAdrInDummy : std_logic_vector(7 downto 0);
signal ctlMsmDwrInDummy :std_logic;
signal EppWrDataInDummy : std_logic_vector(7 downto 0);
signal MemReadSig : std_logic;
signal counter : integer range 0 to 10 := 0;
signal redir : std_logic;
signal DataFromMem : std_logic_vector(7 downto 0);
signal Rst : std_logic := '0';
signal stage : integer range 0 to 10 := 0;
signal counter2 : integer range 0 to 91 := 0;
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
-- Data Retrieval Section
ctlEppRdCycleInDummy <= ctlEppRdCycleIn or MemReadSig;
ctlMsmStartInDummy <= ctlMsmStartIn or MemReadSig;
ctlMsmDwrInDummy <= ctlMsmDwrIn or Rst;
DataOut <= DataFromMem;
process (ReadReq, DataAck, clk)
BEGIN
if (ReadReq = '1') then
MemReadSig <= '1';
redir <= '1';
end if;
if (MemReadSig = '1' and (clk'event and clk = '1')) then
counter <= counter + 1;
end if;
if (counter = 8) then
DataFromMem <= EppRdDataOut;
MemReadSig <= '0';
counter <= 0;
DataRdy <= '1';
end if;
if (DataAck = '1') then
DataRdy <= '0';
redir <= '0';
end if;
end process;
process (redir, stage)
Begin
if stage = 2 then
regEppAdrInDummy <= "00000001";
elsif stage = 4 then
regEppAdrInDummy <= "00000010";
elsif stage = 6 then
regEppAdrInDummy <= "00000011";
elsif redir = '0' then
regEppAdrInDummy <= regEppAdrIn;
else
regEppAdrInDummy <= "00000110";
end if;
end process;
-------------------------------
process (reset, counter2)
Begin
if (Reset = '1') then
stage <= 1;
elsif (counter2 = 15) then
stage <= 2;
elsif (counter2 = 30) then
stage <= 3;
elsif (counter2 = 45) then
stage <= 4;
elsif (counter2 = 60) then
stage <= 5;
elsif (counter2 = 75) then
stage <= 6;
elsif (counter2 = 90) then
stage <= 0;
end if;
end process;
process (clk)
begin
if stage = 1 then
counter2 <= 1;
elsif (clk'event and clk = '1' and stage /= 0 and reset = '0') then
counter2 <= counter2 + 1;
end if;
end process;
process (stage)
Begin
EppWrDataInDummy <= EppWrDataIn;
rst <= '0';
if stage = 2 or stage = 4 or stage = 6 then
EppWrDataInDummy <= "00000000";
rst <= '1';
else
rst <= '0';
EppWrDataInDummy <= EppWrDataIn;
end if;
end process;
------------------------------------------------------------------------
-- Map basic status and control signals
------------------------------------------------------------------------
MemCtrlEnabled <= ctlMcrEnable;
-- Epp signals
-- Port signals
EppRdDataOut <=
regMemCtl when regEppAdrInDummy(2 downto 0) = MemCtrlReg
and ComponentSelect = '1' else
regMemAdr(7 downto 0) when regEppAdrInDummy(2 downto 0) = MemAdrL
and ComponentSelect = '1' else
regMemAdr(15 downto 8) when regEppAdrInDummy(2 downto 0) = MemAdrM
and ComponentSelect = '1' else
regMemAdr(23 downto 16)
when regEppAdrInDummy(2 downto 0) = MemAdrH
and ComponentSelect = '1' else
regMemWrData(7 downto 0) when regEppAdrInDummy(2 downto 0) = MemDataWr
and regMemAdr(0) ='0' -- even address
and ComponentSelect = '1' else
regMemWrData(15 downto 8) when regEppAdrInDummy(2 downto 0) = MemDataWr
and regMemAdr(0) ='1' -- odd address
and ComponentSelect = '1' else
regMemRdData when regEppAdrInDummy(2 downto 0) = RamAutoRW
and ComponentSelect = '1' else
regMemRdData when regEppAdrInDummy(2 downto 0) = FlashAutoRW
and ComponentSelect = '1' else
-- Manual mode is only allowed for Flash
-- (Celullar RAM would hold CS active to long, blocking refresh cycles)
-- Manual "Word" mode for flash reads the upper data bus byte
-- when address odd:
busMemIn(15 downto 8) when ctlMcrWord = '1' -- Word Mode
and regMemAdr(0) = '1' -- odd address
and ComponentSelect = '1' else
-- Manual "Byte" mode for flash reads the lower data bus byte
-- for both odd and even addresses:
busMemIn(7 downto 0) when ComponentSelect = '1' else
"00000000"; -- prepared to "OR" EppRdDataOut to some other busses
-- Memory signals
-- Memory control register
ctlMcrOe <= regMemCtl(0); -- Output enable (read strobe)
ctlMcrWr <= regMemCtl(1); -- Write enable (write strobe)
ctlMcrRAMCs <= regMemCtl(2); -- RAM chip select
ctlMcrFlashCs <= regMemCtl(3); -- Flash chip select
ctlMcrEnable <= regMemCtl(4); -- MemCtrl enable ('1') or disable ('0')
ctlMcrWord <= regMemCtl(5); -- Byte enable ('0') or word enable ('1')
-- Memory control bus driven either by automatic state machine or by
-- memory control register
RamCS <= 'Z' when ctlMcrEnable = '0' else -- MemCtrl Disabled
ctlMcrRAMCs when stMsmCur = stMsmReady else -- MemCtrl Idle
ctlMsmRAMCs; -- MemCtrl generated RAM CS;
FlashCS <= 'Z' when ctlMcrEnable = '0' else -- MemCtrl Disabled
ctlMcrFlashCs when stMsmCur = stMsmReady and -- MemCtrl Idle
ctlMcrRamCs = '1' else -- RAM priority
ctlMsmFlashCs; -- MemCtrl generated Flash CS;
MemOE <= 'Z' when ctlMcrEnable = '0' else -- MemCtrl Disabled
ctlMcrOe when stMsmCur = stMsmReady else -- MemCtrl Idle
ctlMsmOe; -- MemCtrl generated RAM CS;
MemWR <= 'Z' when ctlMcrEnable = '0' else -- MemCtrl Disabled
ctlMcrWr when stMsmCur = stMsmReady and -- MemCtrl Idle
ctlMcrOe = '1' else -- OE priority
ctlMsmWr; -- MemCtrl generated RAM CS;
FlashByte <= 'Z' when ctlMcrEnable = '0' else -- MemCtrl Disabled
ctlMcrWord; -- PC generated Word signal;
-- Byte enable ('0') or word enable ('1')
RamLB <= 'Z' when ctlMcrEnable = '0' else -- MemCtrl Disabled
'0' when ctlMcrWord = '1' or -- word mode
regMemAdr(0) ='0' else -- even address
'1';
RamUB <= 'Z' when ctlMcrEnable = '0' else -- MemCtrl Disabled
'0' when ctlMcrWord = '1' or -- word mode
regMemAdr(0) ='1' else -- odd address
'1';
-- Memory control signals not yet used
RamClk <= 'Z' when ctlMcrEnable = '0' else -- MemCtrl Disabled
'0'; -- inactive for asinchronous mode
RamCre <= 'Z' when ctlMcrEnable = '0' else -- MemCtrl Disabled
'0'; -- inactive for asinchronous default mode
RamAdv <= 'Z' when ctlMcrEnable = '0' else -- MemCtrl Disabled
'0'; -- inactive for asinchronous mode
FlashRp <= 'Z' when ctlMcrEnable = '0' else -- MemCtrl Disabled
'1'; -- no reset, no power down
busMemIn <= MemDB;
busMemOut <= "00000000" & "01000000" when ctlMsmWrCmd = '1' else -- WrC
"00000000" & regMemWrData(15 downto 8)
when ctlMcrWord = '0' and -- byte mode
regMemAdr(0) = '1'and -- odd addr
regEppAdrInDummy(2 downto 0) = FlashAutoRW
-- Flash accessed
else -- any other: -- all RAM
-- Flash word
-- Flash byte even
regMemWrData;-- when ctlMcrWord = '1';
MemAdr <= "ZZZZZZZ" & "ZZZZZZZZ" & "ZZZZZZZZ"
when ctlMcrEnable = '0' else -- MemCtrl Disabled
regMemAdr(23 downto 1);
ctlMcrDir <= ctlMcrOe and -- ctlMcrOe inactive
((not ctlMcrFlashCs) or -- ctlMcrFlashCs active
(not ctlMcrRAMCs)); -- ctlMcrRAMCs active
MemDB <= busMemOut when ctlMcrEnable = '1' and -- MemCtrl Enabled
(ctlMsmDir = '1' or -- Msm controlled
ctlMcrDir = '1') else -- Mcr controlled
"ZZZZZZZZ" & "ZZZZZZZZ";
-- Handshake signal
HandShakeReqOut <= '1' when (regEppAdrInDummy(2 downto 0) = RamAutoRW or
regEppAdrInDummy(2 downto 0) = FlashAutoRW)
and ComponentSelect = '1' else
'0';
-- Memory state machine related signals
-- Control commands generated by the memory state machine.
with stMsmCur select
ctlMsmOe <= '0' when stMsmDRd02|stMsmFwr05|stMsmFwr07,
'1' when others; -- Output enable (read strobe)
with stMsmCur select
ctlMsmWr <= '0' when stMsmDWr02|stMsmFwr01|stMsmFwr03,
'1' when others; -- Write enable (write strobe)
-- with stMsmCur select
-- ctlMsmFlashCs <= '0' when "---1"|"010-", -- FlashCS
-- '1' when others; -- Flash chip select
ctlMsmFlashCs <= '0'
when (stMsmCur = stMsmFwr01 or
stMsmCur = stMsmFwr02 or
stMsmCur = stMsmFwr03 or
stMsmCur = stMsmFwr04 or
stMsmCur = stMsmFwr05 or
stMsmCur = stMsmFwr06 or
stMsmCur = stMsmFwr07) or
((stMsmCur = stMsmDir01 or
stMsmCur = stMsmDWr02 or
stMsmCur = stMsmDRd02 or
stMsmCur = stMsmDir03) and
regEppAdrInDummy(2 downto 0) = FlashAutoRW) else
'1';
-- with stMsmCur select
-- ctlMsmRamCs <= '0' when "--10", -- RamCS
-- '1' when others; -- Flash chip select
ctlMsmRamCs <= '0'
when ((stMsmCur = stMsmDir01 or
stMsmCur = stMsmDWr02 or
stMsmCur = stMsmDRd02 or
stMsmCur = stMsmDir03) and
regEppAdrInDummy(2 downto 0) = RamAutoRW) else
'1';
with stMsmCur select
ctlMsmDir <= '1' when "0--1"|"011-", -- stMsmFwr01-03, stMsmDWr02
'0' when others;-- Memory bus direction: 1=toward memory
with stMsmCur select
ctlMsmAdrInc <= '1' when stMsmAdInc,
'0' when others; -- Flag to automatically increment
-- the address after a step of automatic memory access.
with stMsmCur select
ctlMsmWrCmd <= '1' when stMsmFwr01|stMsmFwr02,
'0' when others;
-- Flag to place write command on the BusMemOut
with stMsmCur select
ctlMsmDoneOut <= '1' when stMsmDone,
'0' when others;
-- Flag to tell the Epp state machine the current access cycle ended
-- Memory Control Register
process (clk, ctlMsmDwrInDummy)
begin
if clk = '1' and clk'Event then
if ctlMsmDwrInDummy = '1' and -- write cycle
regEppAdrInDummy(2 downto 0) = MemCtrlReg and -- MemCtrlReg addressed
ComponentSelect = '1' then -- PhoenixOnBoardMemCtrl component selected
regMemCtl <= EppWrDataInDummy;
end if;
end if;
end process;
-- Memory Address Register/Counter
MsmAdrL: process (clk, ctlMsmDwrInDummy, ctlMsmAdrInc)
begin
if clk = '1' and clk'Event then
if ctlMsmAdrInc = '1' then -- automatic memory cycle
regMemAdr(7 downto 0) <= regMemAdr(7 downto 0) + 1; -- inc. address
elsif ctlMsmDwrInDummy = '1' and -- Epp write cycle
regEppAdrInDummy(2 downto 0) = MemAdrL and-- MemAdrL reg. addressed
ComponentSelect = '1' then -- PhoenixOnBoardMemCtrl comp. selected
regMemAdr(7 downto 0) <= EppWrDataInDummy; -- update MemAdrL content
end if;
end if;
end process;
carryoutL <= '1' when regMemAdr(7 downto 0) = x"ff" else
'0'; -- Lower byte carry out
MsmAdrM: process (clk, ctlMsmDwrInDummy, ctlMsmAdrInc)
begin
if clk = '1' and clk'Event then
if ctlMsmAdrInc = '1' and -- automatic memory cycle
carryoutL = '1' then -- lower byte rollover
regMemAdr(15 downto 8) <= regMemAdr(15 downto 8) + 1;--inc. address
elsif ctlMsmDwrInDummy = '1' and -- Epp write cycle
regEppAdrInDummy(2 downto 0) = MemAdrM and-- MemAdrM reg. addressed
ComponentSelect = '1' then -- PhoenixOnBoardMemCtrl comp. selected
regMemAdr(15 downto 8) <= EppWrDataInDummy; -- update MemAdrM content
end if;
end if;
end process;
carryoutM <= '1' when regMemAdr(15 downto 8) = x"ff" else
'0'; -- Middle byte carry out
MsmAdrH: process (clk, ctlMsmDwrInDummy, ctlMsmAdrInc)
begin
if clk = '1' and clk'Event then
if ctlMsmAdrInc = '1' and -- automatic memory cycle
carryoutL = '1' and -- lower byte rollover
carryoutM = '1' then -- middle byte rollover
regMemAdr(23 downto 16) <= regMemAdr(23 downto 16) + 1;--inc. addr.
elsif ctlMsmDwrInDummy = '1' and -- Epp write cycle
regEppAdrInDummy(2 downto 0) = MemAdrH and-- MemAdrM reg. addressed
ComponentSelect = '1' then -- PhoenixOnBoardMemCtrl comp. selected
regMemAdr(23 downto 16) <= EppWrDataInDummy;-- update MemAdrH
end if;
end if;
end process;
-- Memory write data holding register
process (clk, ctlMsmDwrInDummy)
begin
if clk = '1' and clk'Event then
if ctlMsmDwrInDummy = '1' and -- Epp write cycle
(regEppAdrInDummy(2 downto 0) = RamAutoRW or -- | Any register holding
regEppAdrInDummy(2 downto 0) = FlashAutoRW or-- | data to be written
regEppAdrInDummy(2 downto 0) = MemDataWr) and-- | to memory
ComponentSelect = '1' then
if regMemAdr(0) = '0' then -- even address
regMemWrData(7 downto 0) <= EppWrDataInDummy; -- update lower regMemWrData
else -- odd address
regMemWrData(15 downto 8) <= EppWrDataInDummy; -- update upper regMemWrData
end if;
end if;
end if;
end process;
-- Memory read register: - holds data after an automatic read
process (clk)
begin
if clk = '1' and clk'Event then
if stMsmCur = stMsmDRd02 then -- direct read state
if ctlMcrWord = '1' and -- word mode
regMemAdr(0) = '1' then -- odd address
null; -- should never happen
elsif ctlMcrWord = '1' and -- word mode
regMemAdr(0) = '0' then -- even address
regMemRdData <= busMemIn(7 downto 0); -- update regMemRdData
regMemRdDataAux <= busMemIn(15 downto 8); -- update auxiliary regMemRdData
elsif ctlMcrWord = '0' and -- byte mode
regMemAdr(0) = '0' then -- even address
regMemRdData <= busMemIn(7 downto 0); -- update regMemRdData
elsif ctlMcrWord = '0' and -- byte mode
regMemAdr(0) = '1' and -- odd address
regEppAdrInDummy(2 downto 0) = RamAutoRW then
regMemRdData <= busMemIn(15 downto 8); -- update regMemRdData
elsif ctlMcrWord = '0' and -- byte mode
regMemAdr(0) = '1' and -- odd address
regEppAdrInDummy(2 downto 0) = FlashAutoRW then
regMemRdData <= busMemIn(7 downto 0); -- update regMemRdData
end if;
elsif stMsmCur = stMsmBlind then
if ctlMcrWord = '1' and -- word mode
regMemAdr(0) = '1' then -- odd address
regMemRdData <= regMemRdDataAux; -- update regMemRdData
end if;
end if;
end if;
end process;
------------------------------------------------------------------------
-- Memory Control State Machine
------------------------------------------------------------------------
process (clk)
begin
if clk = '1' and clk'Event then
stMsmCur <= stMsmNext;
end if;
end process;
process (stMsmCur)
variable flagMsmCycle: std_logic; -- 1 => Msm cycle requested
variable flagBlindCycle: std_logic; -- 1 => Blind Msm cycle requested:
-- no memory cycle, but either:
-- store the low regMemWrData byte in preparation for a 16 bit write or
-- send the high regMemWrData byte after a 16 bit read cycle
variable flagFlashAutoWr: std_logic;
-- 1 => Flash Auto Write Cycle cycle requested:
begin
if ctlMsmStartInDummy = '1' and -- process launch
ComponentSelect = '1' and -- comp. selected
((regEppAdrInDummy(2 downto 0) = FlashAutoRW) or
(regEppAdrInDummy(2 downto 0) = RamAutoRW)) then
flagMsmCycle := '1';
else
flagMsmCycle := '0';
end if;
if ctlMcrWord = '1' and -- 16 bit mode
((ctlEppRdCycleInDummy = '0' and -- write cycle
regMemAdr(0) = '0') or -- even address
(ctlEppRdCycleInDummy = '1' and -- read cycle
regMemAdr(0) = '1')) then -- odd address
flagBlindCycle := '1';
else
flagBlindCycle := '0';
end if;
if regEppAdrInDummy = FlashAutoRW and -- auto flash cycle requested
ctlEppRdCycleInDummy = '0' then -- write cycle
flagFlashAutoWr := '1';
else
flagFlashAutoWr := '0';
end if;
case stMsmCur is
-- Idle state waiting for the beginning of an EPP cycle
when stMsmReady =>
if flagMsmCycle = '1' then
if flagBlindCycle = '1' then
stMsmNext <= stMsmBlind; -- Blind state
elsif flagFlashAutoWr = '1' then
stMsmNext <= stMsmFwr01; -- Flash auto write (with write cmd)
else
stMsmNext <= stMsmDir01; -- Direct access (without cmds)
end if;
else
stMsmNext <= stMsmReady;
end if;
-- Automatic flash write cont.
when stMsmFwr01 =>
if DelayCnt = "00101" then
stMsmNext <= stMsmFwr02;
else
stMsmNext <= stMsmFwr01;
end if;
when stMsmFwr02 =>
if DelayCnt = "00111" then
stMsmNext <= stMsmFwr03;
else
stMsmNext <= stMsmFwr02;
end if;
when stMsmFwr03 =>
if DelayCnt = "01101" then
stMsmNext <= stMsmFwr04;
else
stMsmNext <= stMsmFwr03;
end if;
when stMsmFwr04 =>
if DelayCnt = "01101" then
stMsmNext <= stMsmFwr05;
else
stMsmNext <= stMsmFwr04;
end if;
when stMsmFwr05 =>
if DelayCnt = "--101" then
if busMemIn(7) = '0' then
stMsmNext <= stMsmFwr06;
else
stMsmNext <= stMsmFwr04;
end if;
else
stMsmNext <= stMsmFwr05;
end if;
when stMsmFwr06 =>
if DelayCnt = "--111" then
stMsmNext <= stMsmFwr07;
else
stMsmNext <= stMsmFwr06;
end if;
when stMsmFwr07 =>
if DelayCnt = "--101" then
if busMemIn(7) = '1' then
stMsmNext <= stMsmAdInc;
else
stMsmNext <= stMsmFwr06;
end if;
else
stMsmNext <= stMsmFwr07;
end if;
-- Direct access cont.
when stMsmDir01 =>
-- if DelayCnt = "---11" then
if ctlEppRdCycleInDummy = '1' then
stMsmNext <= stMsmDRd02; -- Direct write
else
stMsmNext <= stMsmDWr02; -- Direct read
end if;
-- else
-- stMsmNext <= stMsmDir01; -- keep state
-- end if;
-- Direct write
when stMsmDWr02 =>
if DelayCnt = "--000" then
stMsmNext <= stMsmDir03;
else
stMsmNext <= stMsmDWr02; -- keep state
end if;
-- Direct read cont.
when stMsmDRd02 =>
if DelayCnt = "--000" then
stMsmNext <= stMsmDir03;
else
stMsmNext <= stMsmDRd02; -- keep state
end if;
when stMsmDir03 =>
-- if DelayCnt = "---11" then
stMsmNext <= stMsmAdInc;
-- else
-- stMsmNext <= stMsmDir03; -- keep state
-- end if;
when stMsmAdInc =>
stMsmNext <= stMsmDone;
when stMsmDone =>
if ctlMsmStartInDummy = '1' then
stMsmNext <= stMsmDone;
else
stMsmNext <= stMsmReady;
end if;
-- Automatic flash read cont.
when stMsmBlind =>
stMsmNext <= stMsmAdInc;
-- Unknown states
when others =>
stMsmNext <= stMsmReady;
end case;
end process;
------------------------------------------------------------------------
-- Delay Counter
------------------------------------------------------------------------
process (clk)
begin
if clk'event and clk = '1' then
if stMsmCur = stMsmReady then
DelayCnt <= "00000";
else
DelayCnt <= DelayCnt + 1;
end if;
end if;
end process;
end Behavioral;
|
mit
|
c0eefcc9ceddf4216129118355a4e9f2
| 0.604777 | 4.305247 | false | false | false | false |
andrewandrepowell/kernel-on-chip
|
hdl/koc/koc_lock_pack.vhd
| 1 | 3,447 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
package koc_lock_pack is
constant default_axi_address_width : integer := 32;
constant default_axi_data_width : integer := 32;
constant default_axi_control_offset : integer := 0;
constant default_control_default : integer := 1;
constant axi_resp_okay : std_logic_vector := "00";
component koc_lock is
generic (
axi_address_width : integer := default_axi_address_width; --! Defines the AXI4-Lite Address Width.
axi_data_width : integer := default_axi_data_width; --! Defines the AXI4-Lite Data Width.
axi_control_offset : integer := default_axi_control_offset; --! Defines the offset for the Control register.
control_default : integer := default_control_default
);
port (
aclk : in std_logic; --! Clock. Tested with 50 MHz.
aresetn : in std_logic;
axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Write signal.
axi_awprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Write signal.
axi_awvalid : in std_logic; --! AXI4-Lite Address Write signal.
axi_awready : out std_logic; --! AXI4-Lite Address Write signal.
axi_wvalid : in std_logic; --! AXI4-Lite Write Data signal.
axi_wready : out std_logic; --! AXI4-Lite Write Data signal.
axi_wdata : in std_logic_vector(axi_data_width-1 downto 0); --! AXI4-Lite Write Data signal.
axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0); --! AXI4-Lite Write Data signal.
axi_bvalid : out std_logic; --! AXI4-Lite Write Response signal.
axi_bready : in std_logic; --! AXI4-Lite Write Response signal.
axi_bresp : out std_logic_vector(1 downto 0); --! AXI4-Lite Write Response signal.
axi_araddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Read signal.
axi_arprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Read signal.
axi_arvalid : in std_logic; --! AXI4-Lite Address Read signal.
axi_arready : out std_logic; --! AXI4-Lite Address Read signal.
axi_rdata : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0'); --! AXI4-Lite Read Data signal.
axi_rvalid : out std_logic; --! AXI4-Lite Read Data signal.
axi_rready : in std_logic; --! AXI4-Lite Read Data signal.
axi_rresp : out std_logic_vector(1 downto 0)
);
end component;
end package;
|
mit
|
339f9f6d941a7733e1ae0a95d07847a2
| 0.482158 | 4.767635 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
fifo_out_8b_sync_0.vhd
| 1 | 3,681 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- fifo_out_8b_sync_0.vhd
-- This file was auto-generated as part of a generation operation.
-- If you edit it your changes will probably be lost.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fifo_out_8b_sync_0 is
port (
addr : in std_logic_vector(1 downto 0) := (others => '0'); -- avalon_slave_0.address
in_data : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
wr_en : in std_logic := '0'; -- .write
out_data : out std_logic_vector(31 downto 0); -- .readdata
wait_req : out std_logic; -- .waitrequest
byte_en : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
clk : in std_logic := '0'; -- clock.clk
rst : in std_logic := '0'; -- reset_sink.reset
st_data : out std_logic_vector(7 downto 0); -- avalon_streaming_source.data
st_ready : in std_logic := '0'; -- .ready
st_valid : out std_logic; -- .valid
irq : out std_logic -- conduit_end.export
);
end entity fifo_out_8b_sync_0;
architecture rtl of fifo_out_8b_sync_0 is
component fifo_out_8b_sync is
generic (
FIFO_DEPTH : integer := 16;
BUS_WIDTH : integer := 32
);
port (
addr : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
in_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
wr_en : in std_logic := 'X'; -- write
out_data : out std_logic_vector(31 downto 0); -- readdata
wait_req : out std_logic; -- waitrequest
byte_en : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
clk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
st_data : out std_logic_vector(7 downto 0); -- data
st_ready : in std_logic := 'X'; -- ready
st_valid : out std_logic; -- valid
irq : out std_logic -- export
);
end component fifo_out_8b_sync;
begin
fifo_out_8b_sync_0 : component fifo_out_8b_sync
generic map (
FIFO_DEPTH => 16,
BUS_WIDTH => 32
)
port map (
addr => addr, -- avalon_slave_0.address
in_data => in_data, -- .writedata
wr_en => wr_en, -- .write
out_data => out_data, -- .readdata
wait_req => wait_req, -- .waitrequest
byte_en => byte_en, -- .byteenable
clk => clk, -- clock.clk
rst => rst, -- reset_sink.reset
st_data => st_data, -- avalon_streaming_source.data
st_ready => st_ready, -- .ready
st_valid => st_valid, -- .valid
irq => irq -- conduit_end.export
);
end architecture rtl; -- of fifo_out_8b_sync_0
|
gpl-3.0
|
18be6f8445bb789a3ca781a26acd65e5
| 0.430861 | 3.684685 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
spi_master.vhd
| 1 | 6,340 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- altera vhdl_input_version vhdl_2008
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity spi_master_16 is
port (
rst : in std_logic;
clk : in std_logic;
--
addr : in std_logic_vector(9 downto 0);
byte_en : in std_logic_vector(1 downto 0) := (others => '1');
in_data : in std_logic_vector(15 downto 0);
wr_en : in std_logic;
out_data : out std_logic_vector(15 downto 0);
wait_req : out std_logic;
irq : out std_logic;
--
sclk : out std_logic;
mosi : out std_logic;
miso : in std_logic;
cs_n : out std_logic
);
end entity;
architecture rtl of spi_master_16 is
constant BIT_IRQ : natural := 12;
constant BIT_IMASK : natural := 13;
constant BIT_LAST_BLOCK : natural := 14;
constant BIT_START : natural := 15;
signal ctrlstat_reg : std_logic_vector(15 downto 10);
signal length_reg : unsigned(9 downto 0);
signal clkdiv_reg : unsigned(15 downto 0);
signal ctrlstat_reg_wren : std_logic;
signal clkdiv_reg_wren : std_logic;
signal spi_run : std_logic;
signal spi_last_block : std_logic;
signal spi_irq : std_logic;
signal spi_imask : std_logic;
signal bus_ram_addr : std_logic_vector(8 downto 0);
signal bus_ram_data : std_logic_vector(15 downto 0);
signal bus_ram_we : std_logic;
signal spi_ram_addr : unsigned(9 downto 0);
signal spi_ram_data : std_logic_vector(7 downto 0);
signal spi_ram_we : std_logic;
signal spi_ram_rdy_n : std_logic;
signal clk_cnt : unsigned(16 downto 0);
signal bit_cnt : unsigned(2 downto 0);
signal spi_shift_reg : std_logic_vector(8 downto 0);
signal clk_cnt_rst : std_logic;
signal clk_tick_en : std_logic;
signal clk_tick : std_logic;
signal spi_shift_en : std_logic;
signal spi_load_en : std_logic;
signal spi_sample_en : std_logic;
signal spi_complete : std_logic;
signal cs_i : std_logic;
signal cs_ext_i : std_logic;
signal sclk_i : std_logic;
begin
-- system bus interface
bus_ram_we <= wr_en and not addr(addr'left);
wait_req <= wr_en nor addr(addr'left) when bus_ram_addr /= addr(bus_ram_addr'range) else '0';
RAM_BUFFER_0 : entity work.spi_ram_buffer
port map (
clock => clk,
--
address_a => addr(bus_ram_addr'range),
byteena_a => byte_en,
data_a => in_data,
wren_a => bus_ram_we,
q_a => bus_ram_data,
--
address_b => std_logic_vector(spi_ram_addr),
data_b => spi_shift_reg(7 downto 0),
wren_b => spi_ram_we,
q_b => spi_ram_data
);
ctrlstat_reg_wren <= wr_en when addr(addr'left) and not addr(0) else '0';
clkdiv_reg_wren <= wr_en when addr(addr'left) and addr(0) else '0';
ctrlstat_reg <= (
BIT_START => spi_run,
BIT_LAST_BLOCK => spi_last_block,
BIT_IRQ => spi_irq,
BIT_IMASK => spi_imask,
--
others => '0'
);
process (rst, clk)
begin
if rising_edge(clk) then
bus_ram_addr <= addr(bus_ram_addr'range);
if ctrlstat_reg_wren and byte_en(0) then
length_reg(7 downto 0) <= unsigned(in_data(7 downto 0));
end if;
if ctrlstat_reg_wren and byte_en(1) then
spi_imask <= in_data(BIT_IMASK);
spi_last_block <= in_data(BIT_LAST_BLOCK);
length_reg(9 downto 8) <= unsigned(in_data(9 downto 8));
end if;
if spi_complete then
spi_run <= '0';
elsif ctrlstat_reg_wren and byte_en(1) then
spi_run <= in_data(BIT_START);
end if;
if spi_complete then
spi_irq <= '1';
elsif ctrlstat_reg_wren and byte_en(1) and in_data(BIT_IRQ) then
spi_irq <= '0';
end if;
if clkdiv_reg_wren and byte_en(0) then
clkdiv_reg(7 downto 0) <= unsigned(in_data(7 downto 0));
end if;
if clkdiv_reg_wren and byte_en(1) then
clkdiv_reg(15 downto 8) <= unsigned(in_data(15 downto 8));
end if;
end if;
if rst = '1' then
bus_ram_addr <= (others => '0');
spi_imask <= '0';
spi_irq <= '0';
spi_last_block <= '0';
spi_run <= '0';
length_reg <= (others => '0');
clkdiv_reg <= (others => '0');
end if;
end process;
out_data <= bus_ram_data when addr(addr'left) = '0' else
ctrlstat_reg & std_logic_vector(length_reg) when addr(0) = '0' else
std_logic_vector(clkdiv_reg);
irq <= spi_irq and spi_imask;
-- SPI part
clk_cnt_rst <= '1' when clkdiv_reg = clk_cnt else '0';
clk_tick <= clk_tick_en and not spi_ram_rdy_n;
spi_shift_en <= clk_tick and (sclk_i or not cs_i);
spi_load_en <= spi_shift_en when bit_cnt = 0 else '0';
spi_sample_en <= clk_tick and not sclk_i and cs_i;
spi_complete <= spi_ram_we when spi_ram_addr = length_reg - 1 else '0';
process (rst, spi_run, clk)
begin
if rising_edge(clk) then
-- main clock divider
if clk_cnt_rst or clkdiv_reg_wren then
clk_cnt <= (others => '0');
else
clk_cnt <= clk_cnt + 1;
end if;
clk_tick_en <= clk_cnt_rst;
-- chip select
if clk_tick then
cs_i <= '1';
end if;
-- external clock
if cs_i and clk_tick then
sclk_i <= not sclk_i;
end if;
-- shift register processing
if spi_load_en then
spi_shift_reg(8 downto 1) <= spi_ram_data;
elsif spi_shift_en then
spi_shift_reg(8 downto 1) <= spi_shift_reg(7 downto 0);
end if;
if spi_shift_en then
bit_cnt <= bit_cnt + 1;
end if;
-- sample input data on rising edge os sclk
if spi_sample_en then
spi_shift_reg(0) <= miso;
end if;
-- increment bufer address after store byte
if spi_sample_en = '1' and bit_cnt = 0 then
spi_ram_we <= '1';
spi_ram_rdy_n <= '1';
else
spi_ram_we <= '0';
spi_ram_rdy_n <= spi_ram_we;
end if;
if spi_ram_we then
spi_ram_addr <= spi_ram_addr + 1;
end if;
-- external chip select control
if clk_tick then
cs_ext_i <= '1';
elsif spi_last_block and (spi_complete or (ctrlstat_reg_wren and byte_en(1) and not in_data(BIT_LAST_BLOCK))) then
cs_ext_i <= '0';
end if;
end if;
if not spi_run then
clk_cnt <= (others => '0');
clk_tick_en <= '0';
bit_cnt <= (others => '0');
sclk_i <= '0';
cs_i <= '0';
spi_shift_reg <= (others => '0');
spi_ram_addr <= (others => '0');
spi_ram_we <= '0';
spi_ram_rdy_n <= '0';
end if;
if rst then
cs_ext_i <= '0';
end if;
end process;
cs_n <= not cs_ext_i;
sclk <= sclk_i;
mosi <= spi_shift_reg(8);
end architecture;
|
gpl-3.0
|
a015750c5c6f90c62d4ec670285a1f7b
| 0.614984 | 2.542101 | false | false | false | false |
JosiCoder/CtLab
|
FPGA/SPI Interface/Source/Main.vhd
| 1 | 7,881 |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Provides a loopback test application that simply connects SPI receivers to
-- transmitters. Thus data received on a specific address are retransmitted on
-- the same address.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.globals.all;
entity Main is
port
(
-- The system clock.
sysclk: in std_logic;
-- The internal SPI interface.
f_sck: in std_logic; --
f_rs: in std_logic; -- low during transmission
f_ds: in std_logic; -- low during transmission
f_mosi: in std_logic;
f_miso: out std_logic;
-- The external SPI interface.
ext_sck: in std_logic; --
ext_rs: in std_logic; -- low during transmission
ext_ds: in std_logic; -- low during transmission
ext_mosi: in std_logic;
ext_miso: out std_logic;
-- The test LED output.
test_led: out std_logic
);
end entity;
architecture stdarch of Main is
-- Constants
constant address_width: positive := 4; -- max. 8 (for addresses 0..255)
constant number_of_data_buffers: positive := 2**address_width;
constant use_internal_spi: boolean := true;
constant use_external_spi: boolean := false;
-- SPI interfaces
type spi_in_type is record
mosi: std_logic;
sclk: std_logic;
ss_address: std_logic;
ss_data: std_logic;
end record;
signal selected_spi_in, internal_spi_in, external_spi_in, inactive_spi_in: spi_in_type :=
(
-- Initialize to proper idle values.
mosi => '0',
sclk => '1',
ss_address => '1',
ss_data => '1'
);
signal miso: std_logic;
-- Internals
signal transmit_data_x: data_buffer_vector(number_of_data_buffers-1 downto 0);
signal received_data_x: data_buffer_vector(number_of_data_buffers-1 downto 0);
signal ready_x: std_logic_vector(number_of_data_buffers-1 downto 0);
begin
--------------------------------------------------------------------------------
-- Connections to and from internal signals.
--------------------------------------------------------------------------------
-- NOTE: Reading to and writing from an SPI address always happen together. Each time
-- the SPI master reads a value from the slave's transmit register, it also writes a value
-- to the slave's receive register of the same address, overwriting any previous value.
--
-- If the internal SPI connection is used, the microcontroller of the c'Lab FPGA board
-- acts as the SPI master. It accesses a particular SPI adress as follows:
-- 1) If one of the Param or Value screens is selected on the panel, the microcontroller
-- accesses the SPI bus periodically to read the value from and write the parameter to
-- the according SPI address.
-- 2) When processing a c't Lab protocol set command, the microcontroller writes the
-- according parameter to the SPI slave and ignores the value read from the SPI slave.
-- 3) When processing a c't Lab protocol query command, the microcontroller writes an
-- arbitrary parameter to the SPI slave and returns the value read from the SPI slave.
-- It happens to be that the parameter sent most recently to the same or any other SPI
-- address is reused as this arbitrary parameter.
--
-- If the external SPI connection is used, it's up to the external SPI master how to handle
-- values read from the SPI slave and how to generate parameters written to the SPI slave.
-- Test loop back
transmit_data_x <= received_data_x;
--------------------------------------------------------------------------------
-- SPI input selection logic.
--------------------------------------------------------------------------------
-- The internal SPI bus (i.e. the one connected to the microcontroller of the
-- c'Lab FPGA board).
internal_spi_in.mosi <= f_mosi;
internal_spi_in.sclk <= f_sck;
internal_spi_in.ss_address <= f_rs;
internal_spi_in.ss_data <= f_ds;
-- The external SPI bus (i.e. the one connected to the expansion ports of the
-- c'Lab FPGA board).
external_spi_in.mosi <= ext_mosi;
external_spi_in.sclk <= ext_sck;
external_spi_in.ss_address <= ext_rs;
external_spi_in.ss_data <= ext_ds;
-- Select the SPI connection to use.
-- NOTE: If one of the Param or Value screens is selected on the panel, the microcontroller
-- of the c'Lab FPGA board accesses the SPI bus periodically to read the value from and write
-- the parameter to the according SPI address (SPI reading and writing always happen together).
-- Thus, when both connections are activated, while using the *external* connection, set the
-- panel to the file selection screen to avoid this interference.
-- Also, when both connections are activated, while using the *internal* connection, ensure
-- that the selection pins of the external connection (ext_rs and ext_ds) are pulled up properly.
-- If they are e.g. connected to the SPI interface of a Raspberry Pi, ensure that the latter is
-- switched on. Don't leave the pins unconnected, pull them up instead.
selected_spi_in <=
internal_spi_in when use_internal_spi and
(internal_spi_in.ss_address = '0' or internal_spi_in.ss_data = '0') else
external_spi_in when use_external_spi and
(external_spi_in.ss_address = '0' or external_spi_in.ss_data = '0') else
inactive_spi_in;
--------------------------------------------------------------------------------
-- Component instantiation.
--------------------------------------------------------------------------------
-- The SPI slave.
slave: entity work.SPI_Slave
generic map
(
address_width => address_width,
synchronize_data_to_clk => true
)
port map
(
clk => sysclk,
sclk => selected_spi_in.sclk,
ss_address => selected_spi_in.ss_address,
ss_data => selected_spi_in.ss_data,
transmit_data_x => transmit_data_x,
mosi => selected_spi_in.mosi,
miso => miso,
received_data_x => received_data_x,
ready_x => ready_x
);
--------------------------------------------------------------------------------
-- Output logic.
--------------------------------------------------------------------------------
-- SPI & test LED.
f_miso <= miso when f_ds = '0' else 'Z';
ext_miso <= miso when ext_ds = '0' else 'Z';
test_led <= received_data_x(0)(0); -- LED is active low
end architecture;
|
gpl-3.0
|
1880e200685fb91ecfab6c8c372cca74
| 0.559447 | 4.539747 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
dvb_dma_1.vhd
| 1 | 4,546 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- dvb_dma_1.vhd
-- This file was auto-generated as part of a generation operation.
-- If you edit it your changes will probably be lost.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity dvb_dma_1 is
port (
address : in std_logic_vector(3 downto 0) := (others => '0'); -- avalon_slave_0.address
byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
write : in std_logic := '0'; -- .write
readdata : out std_logic_vector(31 downto 0); -- .readdata
clk : in std_logic := '0'; -- clock.clk
dvb_sop : in std_logic := '0'; -- conduit_end.export
dvb_data : in std_logic_vector(7 downto 0) := (others => '0'); -- .export
dvb_dval : in std_logic := '0'; -- .export
mem_size : out std_logic_vector(6 downto 0); -- .export
mem_addr : out std_logic_vector(60 downto 0); -- .export
mem_byteen : out std_logic_vector(7 downto 0); -- .export
mem_wrdata : out std_logic_vector(63 downto 0); -- .export
mem_write : out std_logic; -- .export
mem_waitreq : in std_logic := '0'; -- .export
interrupt : out std_logic; -- .export
rst : in std_logic := '0' -- reset_sink.reset
);
end entity dvb_dma_1;
architecture rtl of dvb_dma_1 is
component dvb_dma is
port (
address : in std_logic_vector(3 downto 0) := (others => 'X'); -- address
byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
write : in std_logic := 'X'; -- write
readdata : out std_logic_vector(31 downto 0); -- readdata
clk : in std_logic := 'X'; -- clk
dvb_sop : in std_logic := 'X'; -- export
dvb_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
dvb_dval : in std_logic := 'X'; -- export
mem_size : out std_logic_vector(6 downto 0); -- export
mem_addr : out std_logic_vector(60 downto 0); -- export
mem_byteen : out std_logic_vector(7 downto 0); -- export
mem_wrdata : out std_logic_vector(63 downto 0); -- export
mem_write : out std_logic; -- export
mem_waitreq : in std_logic := 'X'; -- export
interrupt : out std_logic; -- export
rst : in std_logic := 'X' -- reset
);
end component dvb_dma;
begin
dvb_dma_1 : component dvb_dma
port map (
address => address, -- avalon_slave_0.address
byteenable => byteenable, -- .byteenable
writedata => writedata, -- .writedata
write => write, -- .write
readdata => readdata, -- .readdata
clk => clk, -- clock.clk
dvb_sop => dvb_sop, -- conduit_end.export
dvb_data => dvb_data, -- .export
dvb_dval => dvb_dval, -- .export
mem_size => mem_size, -- .export
mem_addr => mem_addr, -- .export
mem_byteen => mem_byteen, -- .export
mem_wrdata => mem_wrdata, -- .export
mem_write => mem_write, -- .export
mem_waitreq => mem_waitreq, -- .export
interrupt => interrupt, -- .export
rst => rst -- reset_sink.reset
);
end architecture rtl; -- of dvb_dma_1
|
gpl-3.0
|
b37124f4a2f4a56984359de0ee366c72
| 0.434888 | 3.791493 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/DCM_clock/tb_7seg.vhd
| 2 | 1,513 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_7seg IS
END tb_7seg;
ARCHITECTURE behavior OF tb_7seg IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT seven_seg
PORT(
display1 : IN std_logic_vector(3 downto 0);
display2 : IN std_logic_vector(3 downto 0);
display3 : IN std_logic_vector(3 downto 0);
display4 : IN std_logic_vector(3 downto 0);
clk : IN std_logic;
anodes : INOUT std_logic_vector(4 downto 0);
sevenseg : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
--BiDirs
signal anodes : std_logic_vector(4 downto 0);
--Outputs
signal sevenseg : std_logic_vector(7 downto 0);
-- Clock period definitions
constant clk_period : time := 31.25 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: seven_seg PORT MAP (
display1 => x"1",
display2 => x"2",
display3 => x"3",
display4 => x"4",
clk => clk,
anodes => anodes,
sevenseg => sevenseg
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
gpl-3.0
|
4ba945c91fe905be7a59b3eb334c128d
| 0.575017 | 3.67233 | false | false | false | false |
wyvernSemi/vproc
|
f_vproc.vhd
| 1 | 5,872 |
-- =============================================================
--
-- Copyright (c) 2021 Simon Southwell. All rights reserved.
--
-- Date: 4th May 2021
--
-- This file is part of the VProc package.
--
-- VProc is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- VProc is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with VProc. If not, see <http://www.gnu.org/licenses/>.
--
-- $Id: f_vproc.vhd,v 1.2 2021/05/05 08:07:40 simon Exp $
-- $Source: /home/simon/CVS/src/HDL/VProc/f_vproc.vhd,v $
--
-- =============================================================
-- altera vhdl_input_version vhdl_2008
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vproc_pkg.all;
entity VProc is
port (
Clk : in std_logic;
Addr : out std_logic_vector(31 downto 0) := 32x"0";
WE : out std_logic := '0';
RD : out std_logic := '0';
DataOut : out std_logic_vector(31 downto 0);
DataIn : in std_logic_vector(31 downto 0);
WRAck : in std_logic;
RDAck : in std_logic;
Interrupt : in std_logic_vector(2 downto 0);
Update : out std_logic := '0';
UpdateResponse : in std_logic;
Node : in std_logic_vector(3 downto 0)
);
end;
architecture model of VProc is
constant WEbit : integer := 0;
constant RDbit : integer := 1;
constant DeltaCycle : integer := -1;
signal Initialised : integer := 0;
begin
-- Initial
pINIT : process
begin
-- Don't remove delay! Needed to allow Node to be assigned
wait for 1 ns;
VInit(to_integer(unsigned(Node)));
Initialised <= 1;
wait;
end process;
-- Update process
pUPDATE : process
variable VPDataOut : integer;
variable VPAddr : integer;
variable VPRW : integer;
variable VPTicks : integer;
variable TickVal : integer := 1;
variable DataInSamp : integer;
variable IntSamp : integer;
variable RdAckSamp : std_logic;
variable WRAckSamp : std_logic;
begin
while true loop
-- Can't have a sensitivity list for the process and process delta cyclies in VHDL,
-- so emulate the clock edge with a wait here.
wait until Clk'event and Clk = '1';
-- Cleanly sample the inputs
DataInSamp := to_integer(signed(DataIn));
IntSamp := to_integer(signed("0" & Interrupt));
RdAckSamp := RDAck;
WRAckSamp := WRAck;
if Initialised = 1 then
if IntSamp > 0 then
VSched(to_integer(unsigned(Node)),
IntSamp,
DataInSamp,
VPDataOut,
VPAddr,
VPRW,
VPTicks);
-- If interrupt routine returns non-zero tick, then override
-- current tick value. Otherwise, leave at present value.
if VPTicks > 0 then
TickVal := VPTicks;
end if;
end if;
-- If tick, write or a read has completed...
if (RD = '0' and WE = '0' and TickVal = 0) or
(RD = '1' and RdAckSamp = '1') or
(WE = '1' and WRAckSamp = '1') then
-- Host process message scheduler called
VSched(to_integer(unsigned(Node)),
0,
DataInSamp,
VPDataOut,
VPAddr,
VPRW,
VPTicks);
--wait for 0 ns;
WE <= to_unsigned(VPRW, 2)(WEbit);
RD <= to_unsigned(VPRW, 2)(RDbit);
DataOut <= std_logic_vector(to_signed(VPDataOut, 32));
Addr <= std_logic_vector(to_signed(VPAddr, 32));
Update <= not Update;
wait on UpdateResponse;
-- Update current tick value with returned number (if not zero)
if VPTicks > 0 then
TickVal := VPTicks;
elsif VPTicks < 0 then
while VPTicks = DeltaCycle loop
-- Resample delta input data
DataInSamp := to_integer(signed(DataIn));
VSched(to_integer(unsigned(Node)),
0,
DataInSamp,
VPDataOut,
VPAddr,
VPRW,
VPTicks);
WE <= to_unsigned(VPRW, 2)(WEbit);
RD <= to_unsigned(VPRW, 2)(RDbit);
DataOut <= std_logic_vector(to_signed(VPDataOut, 32));
Addr <= std_logic_vector(to_signed(VPAddr, 32));
Update <= not Update;
if VPTicks >= 0 then
TickVal := VPTicks;
end if;
wait on UpdateResponse;
end loop;
end if;
else
-- Count down to zero and stop
if TickVal > 0 then
TickVal := TickVal - 1;
else
TickVal := 0;
end if;
end if;
end if;
end loop;
end process;
end architecture;
|
gpl-3.0
|
c01faa4b96d59f17dd5f5b35c0cdd6e2
| 0.493869 | 4.304985 | false | false | false | false |
arthurTemporim/SD_SS
|
rel/2/rel2/Mux4.vhd
| 1 | 556 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Mux4 is
Port ( seletora : in STD_LOGIC_VECTOR (1 downto 0);
entrada : in STD_LOGIC_VECTOR (3 downto 0);
saida : out STD_LOGIC);
end Mux4;
architecture Behavioral of Mux4 is
signal s1 : STD_LOGIC;
begin
mux: process (seletora,entrada)
begin
if (seletora = "00") then
saida <= entrada(0);
elsif (seletora = "01") then
saida <= entrada(1);
elsif (seletora = "10") then
saida <= entrada(2);
else
saida <= entrada(3);
end if;
end process;
end Behavioral;
|
mit
|
c2b99fc3073864d700f0430d1ccfdbed
| 0.636691 | 2.989247 | false | false | false | false |
JosiCoder/CtLab
|
FPGA/SPI Interface/Testbenches/TestTools.vhd
| 1 | 6,322 |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Provides some tools for the test benches.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
package TestTools is
-- Functions and Procedures
procedure serialize_byte (sclk_period: time;
parallel_in: std_logic_vector(7 downto 0);
signal sclk: out std_logic;
signal serial_out: out std_logic);
procedure serialize_longword (sclk_period: time;
parallel_in: std_logic_vector(31 downto 0);
signal sclk: out std_logic;
signal serial_out: out std_logic);
procedure deserialize_longword (sclk_period: time;
signal serial_in: std_logic;
signal sclk: out std_logic;
signal parallel_out: out std_logic_vector(31 downto 0));
procedure serialize_and_deserialize_longword (
sclk_period: time;
parallel_in: std_logic_vector(7 downto 0);
signal serial_in: std_logic;
signal sclk: out std_logic;
signal serial_out: out std_logic;
signal parallel_out: out std_logic_vector(31 downto 0));
end;
package body TestTools is
-----------------------------------------------------------------
-- Serializes a single byte and writes it to a serial signal.
-- Also controls the according SCLK signal.
-----------------------------------------------------------------
procedure serialize_byte (sclk_period: time;
parallel_in: std_logic_vector(7 downto 0);
signal sclk: out std_logic;
signal serial_out: out std_logic)
is
begin
for i in parallel_in'high downto 0 loop
sclk <= '0';
serial_out <= parallel_in(i);
wait for sclk_period/2;
sclk <= '1';
wait for sclk_period/2;
end loop;
end procedure;
-----------------------------------------------------------------
-- Serializes a single longword and writes it to a serial signal.
-- Also controls the according SCLK signal.
-----------------------------------------------------------------
procedure serialize_longword (sclk_period: time;
parallel_in: std_logic_vector(31 downto 0);
signal sclk: out std_logic;
signal serial_out: out std_logic)
is
begin
serialize_byte(sclk_period, parallel_in(31 downto 24), sclk, serial_out);
serialize_byte(sclk_period, parallel_in(23 downto 16), sclk, serial_out);
serialize_byte(sclk_period, parallel_in(15 downto 8), sclk, serial_out);
serialize_byte(sclk_period, parallel_in(7 downto 0), sclk, serial_out);
end procedure;
-----------------------------------------------------------------
-- Deserializes a single longword by reading from a serial signal.
-- Writes the deserialized data to the specified parallel signal
-- continuously. Also controls the according SCLK signal.
-----------------------------------------------------------------
procedure deserialize_longword (sclk_period: time;
signal serial_in: std_logic;
signal sclk: out std_logic;
signal parallel_out: out std_logic_vector(31 downto 0))
is
begin
parallel_out <= (others => '0');
for i in parallel_out'high downto 0 loop
sclk <= '0';
wait for sclk_period/2;
parallel_out(i) <= serial_in;
sclk <= '1';
wait for sclk_period/2;
end loop;
end procedure;
-----------------------------------------------------------------
-- Serializes a single longword and writes it to a serial signal,
-- simultaneously deserializes a single longword by reading from
-- a serial signal. Writes the deserialized data to the specified
-- parallel signal continuously.
-- Also controls the according SCLK signal.
-----------------------------------------------------------------
procedure serialize_and_deserialize_longword (
sclk_period: time;
parallel_in: std_logic_vector(31 downto 0);
signal serial_in: std_logic;
signal sclk: out std_logic;
signal serial_out: out std_logic;
signal parallel_out: out std_logic_vector(31 downto 0))
is
begin
parallel_out <= (others => '0');
for i in parallel_in'high downto 0 loop
sclk <= '0';
serial_out <= parallel_in(i);
wait for sclk_period/2;
parallel_out(i) <= serial_in;
sclk <= '1';
wait for sclk_period/2;
end loop;
end procedure;
end;
|
gpl-3.0
|
cfce2311274a1a7bf005bc205d1510b2
| 0.472635 | 5.385009 | false | false | false | false |
arthurbenemann/fpga-bits
|
mandelbrot/color_palette.vhd
| 1 | 1,268 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity color_generator is Port (
clk : in std_logic;
overflow_bits : in STD_LOGIC_VECTOR (19 downto 0);
color_rgb : out STD_LOGIC_VECTOR (11 downto 0));
end color_generator;
architecture Behavioral of color_generator is
signal count : unsigned (3 downto 0) :=(others=>'0');
signal overflow_bits_buffer : STD_LOGIC_VECTOR (19 downto 0);
signal color_rgb_buffer,douta : STD_LOGIC_VECTOR (11 downto 0);
function count_ones(s : std_logic_vector) return integer is
variable temp : natural := 0;
begin
for i in s'range loop
if s(i) = '1' then temp := temp + 1;
end if;
end loop;
return temp;
end function count_ones;
COMPONENT color_palette PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END COMPONENT;
begin
color_rgb <= color_rgb_buffer;
rom: color_palette PORT MAP (
clka => clk,
addra => std_logic_vector(count),
douta => douta
);
process (clk) begin
if rising_edge(clk) then
overflow_bits_buffer <= overflow_bits;
count <= to_unsigned(count_ones(overflow_bits_buffer),4);
color_rgb_buffer <= douta;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
b4156e4b334da5f6c42d216b06f22618
| 0.671924 | 3.177945 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
dvb_ts_filter.vhd
| 1 | 8,004 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- altera vhdl_input_version vhdl_2008
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library altera_mf;
use altera_mf.all;
use work.avblabs_common_pkg.all;
entity dvb_ts_filter is
port (
rst : in std_logic;
clk : in std_logic;
--
pid_tbl_addr : in std_logic_vector(7 downto 0);
pid_tbl_be : in std_logic_vector(3 downto 0);
pid_tbl_wrdata : in std_logic_vector(31 downto 0);
pid_tbl_write : in std_logic;
pid_tbl_rddata : out std_logic_vector(31 downto 0);
pid_tbl_read : in std_logic;
pid_tbl_waitreq : out std_logic;
--
dvb_in_dsop : in std_logic;
dvb_in_data : in std_logic_vector(7 downto 0);
dvb_in_dval : in std_logic;
--
dvb_out_dsop : out std_logic;
dvb_out_data : out std_logic_vector(7 downto 0);
dvb_out_dval : out std_logic
);
end entity;
architecture rtl of dvb_ts_filter is
-- type mem_t is array(0 to 255) of std_logic_vector(7 downto 0);
-- shared variable pid_tbl_ram_0 : mem_t;
-- shared variable pid_tbl_ram_1 : mem_t;
-- shared variable pid_tbl_ram_2 : mem_t;
-- shared variable pid_tbl_ram_3 : mem_t;
-- signal pid_tbl_ram_addr_a : unsigned(12 downto 5);
-- signal pid_tbl_ram_be_a : std_logic_vector(3 downto 0);
-- signal pid_tbl_ram_we_a : std_logic;
-- signal pid_tbl_ram_d_a : std_logic_vector(7 downto 0);
signal pid_tbl_ram_q_a_0 : std_logic_vector(7 downto 0);
signal pid_tbl_ram_q_a_1 : std_logic_vector(7 downto 0);
signal pid_tbl_ram_q_a_2 : std_logic_vector(7 downto 0);
signal pid_tbl_ram_q_a_3 : std_logic_vector(7 downto 0);
-- signal pid_tbl_ram_addr_b : unsigned(12 downto 1);
signal pid_tbl_ram_q_b_0 : std_logic_vector(0 downto 0);
signal pid_tbl_ram_q_b_1 : std_logic_vector(0 downto 0);
signal pid_tbl_ram_q_b_2 : std_logic_vector(0 downto 0);
signal pid_tbl_ram_q_b_3 : std_logic_vector(0 downto 0);
signal pid_tbl_value : std_logic_vector(3 downto 0);
signal pid_tbl_rddata_latch : std_logic_vector(31 downto 0);
signal latch_valid : std_logic;
signal rddata_valid : std_logic;
signal header : std_logic;
signal pkten : std_logic;
signal dvb_word_0 : std_logic_vector(9 downto 0);
signal dvb_word_1 : std_logic_vector(9 downto 0);
signal dvb_word_2 : std_logic_vector(9 downto 0);
signal dvb_word_3 : std_logic_vector(9 downto 0);
signal dvb_word_4 : std_logic_vector(9 downto 0);
-- attribute ramstyle : string;
-- attribute ramstyle of pid_tbl_ram_0 : variable is "M9K, no_rw_check";
-- attribute ramstyle of pid_tbl_ram_1 : variable is "M9K, no_rw_check";
-- attribute ramstyle of pid_tbl_ram_2 : variable is "M9K, no_rw_check";
-- attribute ramstyle of pid_tbl_ram_3 : variable is "M9K, no_rw_check";
begin
/*
-- RAM port A (read/write)
process (clk)
variable addr_a : integer range 0 to 255;
begin
if rising_edge(clk) then
addr_a := to_integer(unsigned(pid_tbl_addr));
--
if pid_tbl_write and pid_tbl_be(0) then
pid_tbl_ram_0(addr_a) := pid_tbl_wrdata(7 downto 0);
end if;
if pid_tbl_write and pid_tbl_be(1) then
pid_tbl_ram_1(addr_a) := pid_tbl_wrdata(15 downto 8);
end if;
if pid_tbl_write and pid_tbl_be(2) then
pid_tbl_ram_2(addr_a) := pid_tbl_wrdata(23 downto 16);
end if;
if pid_tbl_write and pid_tbl_be(3) then
pid_tbl_ram_3(addr_a) := pid_tbl_wrdata(31 downto 24);
end if;
--
pid_tbl_ram_q_a_0 <= pid_tbl_ram_0(addr_a);
pid_tbl_ram_q_a_1 <= pid_tbl_ram_1(addr_a);
pid_tbl_ram_q_a_2 <= pid_tbl_ram_2(addr_a);
pid_tbl_ram_q_a_3 <= pid_tbl_ram_3(addr_a);
end if;
end process;
-- RAM port B (read only)
process (clk)
variable addr_b : integer range 0 to 255;
begin
if rising_edge(clk) then
addr_b := to_integer(unsigned(dvb_word_1(4 downto 0)) & unsigned(dvb_word_0(7 downto 5)) & unsigned(dvb_word_0(2 downto 0)));
--
pid_tbl_ram_q_b_0 <= pid_tbl_ram_0(addr_b / 8)(addr_b rem 8);
pid_tbl_ram_q_b_1 <= pid_tbl_ram_1(addr_b / 8)(addr_b rem 8);
pid_tbl_ram_q_b_2 <= pid_tbl_ram_2(addr_b / 8)(addr_b rem 8);
pid_tbl_ram_q_b_3 <= pid_tbl_ram_3(addr_b / 8)(addr_b rem 8);
end if;
end process;
*/
RAM_0 : entity work.pid_table_ram
port map (
clock => clk,
--
address_a => pid_tbl_addr,
data_a => pid_tbl_wrdata(7 downto 0),
wren_a => pid_tbl_write and pid_tbl_be(0),
q_a => pid_tbl_ram_q_a_0,
--
address_b => dvb_word_1(4 downto 0) & dvb_word_0(7 downto 5) & dvb_word_0(2 downto 0),
data_b => (others => '0'),
wren_b => '0',
q_b => pid_tbl_ram_q_b_0
);
RAM_1 : entity work.pid_table_ram
port map (
clock => clk,
--
address_a => pid_tbl_addr,
data_a => pid_tbl_wrdata(15 downto 8),
wren_a => pid_tbl_write and pid_tbl_be(1),
q_a => pid_tbl_ram_q_a_1,
--
address_b => dvb_word_1(4 downto 0) & dvb_word_0(7 downto 5) & dvb_word_0(2 downto 0),
data_b => (others => '0'),
wren_b => '0',
q_b => pid_tbl_ram_q_b_1
);
RAM_2 : entity work.pid_table_ram
port map (
clock => clk,
--
address_a => pid_tbl_addr,
data_a => pid_tbl_wrdata(23 downto 16),
wren_a => pid_tbl_write and pid_tbl_be(2),
q_a => pid_tbl_ram_q_a_2,
--
address_b => dvb_word_1(4 downto 0) & dvb_word_0(7 downto 5) & dvb_word_0(2 downto 0),
data_b => (others => '0'),
wren_b => '0',
q_b => pid_tbl_ram_q_b_2
);
RAM_3 : entity work.pid_table_ram
port map (
clock => clk,
--
address_a => pid_tbl_addr,
data_a => pid_tbl_wrdata(31 downto 24),
wren_a => pid_tbl_write and pid_tbl_be(3),
q_a => pid_tbl_ram_q_a_3,
--
address_b => dvb_word_1(4 downto 0) & dvb_word_0(7 downto 5) & dvb_word_0(2 downto 0),
data_b => (others => '0'),
wren_b => '0',
q_b => pid_tbl_ram_q_b_3
);
-- other logic
-- pid_tbl_ram_addr_a <= unsigned(pid_tbl_addr);
-- pid_tbl_ram_be_a <= pid_tbl_be;
-- pid_tbl_ram_we_a <= pid_tbl_write;
-- REORG_0 : for i in 0 to 3 generate
-- pid_tbl_rddata_latch(i * 8 + 7 downto i * 8) <= pid_tbl_ram_q_a(i);
-- pid_tbl_ram_d_a(i) <= pid_tbl_wrdata(i * 8 + 7 downto i * 8);
-- end generate;
pid_tbl_rddata_latch <= pid_tbl_ram_q_a_3 & pid_tbl_ram_q_a_2 & pid_tbl_ram_q_a_1 & pid_tbl_ram_q_a_0;
pid_tbl_value <= pid_tbl_ram_q_b_3 & pid_tbl_ram_q_b_2 & pid_tbl_ram_q_b_1 & pid_tbl_ram_q_b_0;
-- pid_tbl_ram_addr_b <= unsigned(dvb_word_1(4 downto 0)) & unsigned(dvb_word_0(7 downto 5));
pid_tbl_waitreq <= pid_tbl_read and not rddata_valid;
process (rst, clk)
begin
if rising_edge(clk) then
pid_tbl_rddata <= pid_tbl_rddata_latch;
latch_valid <= pid_tbl_read and (latch_valid nor rddata_valid);
rddata_valid <= latch_valid;
--
if dvb_in_dval then
if dvb_in_dsop then
header <= '1';
elsif dvb_word_1(8) then
header <= '0';
end if;
end if;
if dvb_word_3(8) then
pkten <= not pid_tbl_value(to_integer(unsigned(dvb_word_1(4 downto 3))));--(to_integer(unsigned(dvb_word_1(4 downto 3))))(to_integer(unsigned(dvb_word_1(2 downto 0))));
end if;
if not header or dvb_in_dval then
dvb_word_0 <= dvb_in_dval & dvb_in_dsop & dvb_in_data;
dvb_word_1 <= dvb_word_0;
dvb_word_2 <= dvb_word_1;
dvb_word_3 <= dvb_word_2;
dvb_word_4 <= dvb_word_3;
-- output stage
if not pkten then
dvb_out_dval <= '0';
dvb_out_dsop <= '0';
dvb_out_data <= (others => '0');
else
dvb_out_dval <= dvb_word_4(9);
dvb_out_dsop <= dvb_word_4(8);
dvb_out_data <= dvb_word_4(7 downto 0);
end if;
end if;
end if;
if rst then
pid_tbl_rddata <= (others => '0');
latch_valid <= '0';
rddata_valid <= '0';
--
header <= '0';
pkten <= '0';
--
dvb_word_0 <= (others => '0');
dvb_word_1 <= (others => '0');
dvb_word_2 <= (others => '0');
dvb_word_3 <= (others => '0');
dvb_word_4 <= (others => '0');
--
dvb_out_dval <= '0';
dvb_out_dsop <= '0';
dvb_out_data <= (others => '0');
end if;
end process;
end architecture;
|
gpl-3.0
|
99050753aaf56a9769cb581dbbb56766
| 0.607321 | 2.336252 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
avblabs_common_pkg.vhd
| 1 | 4,701 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- altera vhdl_input_version vhdl_2008
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package avblabs_common_pkg is
procedure write_sr_flag (
signal flag : out std_logic;
constant baseaddr : natural;
constant bitpos : natural;
signal addr : in std_logic_vector;
signal data : in std_logic_vector;
signal be : in std_logic_vector
);
procedure write_reg (
signal reg : out std_logic_vector;
constant baseaddr : natural;
signal addr : in std_logic_vector;
signal data : in std_logic_vector;
signal be : in std_logic_vector
);
function ulen (arg : natural) return natural;
function slen (arg : integer) return natural;
function bin_to_gray (inputs: unsigned) return std_logic_vector;
function gray_to_bin (inputs: std_logic_vector) return unsigned;
function fifo_not_full (
wrptr : std_logic_vector;
rdptr : std_logic_vector
) return std_logic;
function fifo_not_empty (
wrptr : std_logic_vector;
rdptr : std_logic_vector
) return std_logic;
function fifo_water_level (
wrptr : std_logic_vector;
rdptr : std_logic_vector
) return unsigned;
end package;
package body avblabs_common_pkg is
procedure write_sr_flag (
signal flag : out std_logic;
constant baseaddr : natural;
constant bitpos : natural;
signal addr : in std_logic_vector;
signal data : in std_logic_vector;
signal be : in std_logic_vector
) is
begin
if unsigned(addr(addr'left downto addr'right + 1)) = baseaddr / 2 then
if be(bitpos / 8) and data(bitpos) then
flag <= not addr(addr'right);
end if;
end if;
end procedure;
procedure write_reg (
signal reg : out std_logic_vector;
constant baseaddr : natural;
signal addr : in std_logic_vector;
signal data : in std_logic_vector;
signal be : in std_logic_vector
) is
begin
if unsigned(addr) = baseaddr then
for i in reg'range loop
if be(i / 8) then
reg(i) <= data(i);
end if;
end loop;
end if;
end procedure;
function ulen (arg : natural) return natural is
begin
if arg < 2 then
return 1;
else
return ulen(arg / 2) + 1;
end if;
end function;
function slen (arg : integer) return natural is
begin
if arg < 0 then
return ulen(abs(arg) - 1) + 1;
else
return ulen(arg) + 1;
end if;
end function;
function bin_to_gray (inputs: unsigned) return std_logic_vector is
begin
return std_logic_vector(inputs xor ('0' & inputs(inputs'left downto inputs'right + 1)));
end function;
function gray_to_bin_i (inputs: std_logic_vector) return std_logic_vector is
variable u_result : std_logic_vector(inputs'left downto inputs'length / 2 + inputs'right);
variable l_result : std_logic_vector(inputs'length / 2 + inputs'right - 1 downto inputs'right);
begin
u_result := inputs(u_result'range);
l_result := inputs(l_result'range);
if u_result'length > 1 then
u_result := gray_to_bin_i(u_result);
end if;
if l_result'length > 1 then
l_result := gray_to_bin_i(l_result);
end if;
l_result := l_result xor (l_result'range => u_result(u_result'right));
return u_result & l_result;
end function;
function gray_to_bin (inputs: std_logic_vector) return unsigned is
-- variable result : unsigned(inputs'range);
begin
-- result(result'left) := inputs(inputs'left);
-- for i in inputs'left - 1 downto inputs'right loop
-- result(i) := inputs(i) xor result(i + 1);
-- end loop;
-- return result;
return unsigned(gray_to_bin_i(inputs));
end function;
function fifo_not_full (
wrptr : std_logic_vector;
rdptr : std_logic_vector
) return std_logic is
begin
if wrptr(wrptr'left - 2 downto 0) = rdptr(rdptr'left - 2 downto 0) then
return (wrptr(wrptr'left) xor rdptr(rdptr'left)) nand (wrptr(wrptr'left - 1) xor rdptr(rdptr'left - 1));
else
return '1';
end if;
end function;
function fifo_not_empty (
wrptr : std_logic_vector;
rdptr : std_logic_vector
) return std_logic is
begin
if wrptr = rdptr then
return '0';
else
return '1';
end if;
end function;
function fifo_water_level (
wrptr : std_logic_vector;
rdptr : std_logic_vector
) return unsigned is
variable wraddr : std_logic_vector(wrptr'left - 1 downto wrptr'right);
variable rdaddr : std_logic_vector(rdptr'left - 1 downto rdptr'right);
begin
wraddr := (wrptr(wrptr'left) xor wrptr(wrptr'left - 1)) & wrptr(wrptr'left - 2 downto 0);
rdaddr := (rdptr(rdptr'left) xor rdptr(rdptr'left - 1)) & rdptr(rdptr'left - 2 downto 0);
return gray_to_bin(wraddr) - gray_to_bin(rdaddr);
end function;
end package body;
|
gpl-3.0
|
edbe31ff1cbc8cdc56c0d888e68ffcf4
| 0.679855 | 2.938125 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
avalon64_to_avalon8_0.vhd
| 1 | 4,534 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- avalon64_to_avalon8_0.vhd
-- This file was auto-generated as part of a generation operation.
-- If you edit it your changes will probably be lost.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity avalon64_to_avalon8_0 is
port (
address : in std_logic_vector(14 downto 0) := (others => '0'); -- avalon_slave_0.address
byteenable : in std_logic_vector(7 downto 0) := (others => '0'); -- .byteenable
writedata : in std_logic_vector(63 downto 0) := (others => '0'); -- .writedata
write : in std_logic := '0'; -- .write
readdata : out std_logic_vector(63 downto 0); -- .readdata
read : in std_logic := '0'; -- .read
waitrequest : out std_logic; -- .waitrequest
clk : in std_logic := '0'; -- clock.clk
rst : in std_logic := '0'; -- reset_sink.reset
out_address : out std_logic_vector(17 downto 0); -- conduit_end.export
out_writedata : out std_logic_vector(7 downto 0); -- .export
out_write : out std_logic; -- .export
out_readdata : in std_logic_vector(7 downto 0) := (others => '0'); -- .export
out_read : out std_logic; -- .export
out_waitrequest : in std_logic := '0' -- .export
);
end entity avalon64_to_avalon8_0;
architecture rtl of avalon64_to_avalon8_0 is
component avalon64_to_avalon8 is
generic (
OUT_ADDR_WIDTH : integer := 15
);
port (
address : in std_logic_vector(14 downto 0) := (others => 'X'); -- address
byteenable : in std_logic_vector(7 downto 0) := (others => 'X'); -- byteenable
writedata : in std_logic_vector(63 downto 0) := (others => 'X'); -- writedata
write : in std_logic := 'X'; -- write
readdata : out std_logic_vector(63 downto 0); -- readdata
read : in std_logic := 'X'; -- read
waitrequest : out std_logic; -- waitrequest
clk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
out_address : out std_logic_vector(17 downto 0); -- export
out_writedata : out std_logic_vector(7 downto 0); -- export
out_write : out std_logic; -- export
out_readdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
out_read : out std_logic; -- export
out_waitrequest : in std_logic := 'X' -- export
);
end component avalon64_to_avalon8;
begin
avalon64_to_avalon8_0 : component avalon64_to_avalon8
generic map (
OUT_ADDR_WIDTH => 18
)
port map (
address => address, -- avalon_slave_0.address
byteenable => byteenable, -- .byteenable
writedata => writedata, -- .writedata
write => write, -- .write
readdata => readdata, -- .readdata
read => read, -- .read
waitrequest => waitrequest, -- .waitrequest
clk => clk, -- clock.clk
rst => rst, -- reset_sink.reset
out_address => out_address, -- conduit_end.export
out_writedata => out_writedata, -- .export
out_write => out_write, -- .export
out_readdata => out_readdata, -- .export
out_read => out_read, -- .export
out_waitrequest => out_waitrequest -- .export
);
end architecture rtl; -- of avalon64_to_avalon8_0
|
gpl-3.0
|
b2ce1eff6db5e2897d2d1cfb963db6ab
| 0.439568 | 4.008842 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
dma_arbiter_0.vhd
| 1 | 5,354 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- dma_arbiter_0.vhd
-- This file was auto-generated as part of a generation operation.
-- If you edit it your changes will probably be lost.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity dma_arbiter_0 is
port (
clk : in std_logic := '0'; -- clock.clk
rst : in std_logic := '0'; -- reset_sink.reset
dma0_addr : in std_logic_vector(60 downto 0) := (others => '0'); -- conduit_end.export
dma0_wrdata : in std_logic_vector(63 downto 0) := (others => '0'); -- .export
dma0_size : in std_logic_vector(6 downto 0) := (others => '0'); -- .export
dma0_write : in std_logic := '0'; -- .export
dma0_wait : out std_logic; -- .export
dma1_addr : in std_logic_vector(60 downto 0) := (others => '0'); -- .export
dma1_size : in std_logic_vector(6 downto 0) := (others => '0'); -- .export
dma1_wrdata : in std_logic_vector(63 downto 0) := (others => '0'); -- .export
dma1_write : in std_logic := '0'; -- .export
dma1_wait : out std_logic; -- .export
dma0_byteen : in std_logic_vector(7 downto 0) := (others => '0'); -- .export
dma1_byteen : in std_logic_vector(7 downto 0) := (others => '0'); -- .export
mem_addr : out std_logic_vector(30 downto 0); -- avalon_master.address
mem_size : out std_logic_vector(6 downto 0); -- .burstcount
mem_wrdata : out std_logic_vector(63 downto 0); -- .writedata
mem_write : out std_logic; -- .write
mem_waitreq : in std_logic := '0'; -- .waitrequest
mem_byteen : out std_logic_vector(7 downto 0) -- .byteenable
);
end entity dma_arbiter_0;
architecture rtl of dma_arbiter_0 is
component dma_arbiter is
generic (
MEM_ADDR_WIDTH : natural := 31
);
port (
clk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
dma0_addr : in std_logic_vector(60 downto 0) := (others => 'X'); -- export
dma0_wrdata : in std_logic_vector(63 downto 0) := (others => 'X'); -- export
dma0_size : in std_logic_vector(6 downto 0) := (others => 'X'); -- export
dma0_write : in std_logic := 'X'; -- export
dma0_wait : out std_logic; -- export
dma1_addr : in std_logic_vector(60 downto 0) := (others => 'X'); -- export
dma1_size : in std_logic_vector(6 downto 0) := (others => 'X'); -- export
dma1_wrdata : in std_logic_vector(63 downto 0) := (others => 'X'); -- export
dma1_write : in std_logic := 'X'; -- export
dma1_wait : out std_logic; -- export
dma0_byteen : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
dma1_byteen : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
mem_addr : out std_logic_vector(30 downto 0); -- address
mem_size : out std_logic_vector(6 downto 0); -- burstcount
mem_wrdata : out std_logic_vector(63 downto 0); -- writedata
mem_write : out std_logic; -- write
mem_waitreq : in std_logic := 'X'; -- waitrequest
mem_byteen : out std_logic_vector(7 downto 0) -- byteenable
);
end component dma_arbiter;
begin
dma_arbiter_0 : component dma_arbiter
generic map (
MEM_ADDR_WIDTH => 31
)
port map (
clk => clk, -- clock.clk
rst => rst, -- reset_sink.reset
dma0_addr => dma0_addr, -- conduit_end.export
dma0_wrdata => dma0_wrdata, -- .export
dma0_size => dma0_size, -- .export
dma0_write => dma0_write, -- .export
dma0_wait => dma0_wait, -- .export
dma1_addr => dma1_addr, -- .export
dma1_size => dma1_size, -- .export
dma1_wrdata => dma1_wrdata, -- .export
dma1_write => dma1_write, -- .export
dma1_wait => dma1_wait, -- .export
dma0_byteen => dma0_byteen, -- .export
dma1_byteen => dma1_byteen, -- .export
mem_addr => mem_addr, -- avalon_master.address
mem_size => mem_size, -- .burstcount
mem_wrdata => mem_wrdata, -- .writedata
mem_write => mem_write, -- .write
mem_waitreq => mem_waitreq, -- .waitrequest
mem_byteen => mem_byteen -- .byteenable
);
end architecture rtl; -- of dma_arbiter_0
|
gpl-3.0
|
f3b6e99e12de97a8eea0556193d716ed
| 0.46582 | 3.481144 | false | false | false | false |
arthurTemporim/SD_SS
|
pre/5/projetos/projeto1/projeto1.vhd
| 1 | 774 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity projeto1 is
port (
d : in std_logic := '0'; -- Entrada 'D'
sel : in std_logic_vector (2 downto 0) := "000"; -- Entradas "ABC"
s_m : out std_logic
);
end projeto1;
architecture Behavioral of projeto1 is
signal saida_mux : std_logic;
begin
-- Multiplexador 8 para 1.
process (sel, d)
begin
if(sel = "000") then
saida_mux <= (not d);
elsif(sel = "001") then
saida_mux <= (not d);
elsif(sel = "010") then
saida_mux <= sel(0);
elsif(sel = "011") then
saida_mux <= d;
elsif(sel = "100") then
saida_mux <= d;
elsif(sel = "101") then
saida_mux <= '0';
elsif(sel = "110") then
saida_mux <= '0';
else
saida_mux <= '0';
end if;
end process;
s_m <= saida_mux;
end Behavioral;
|
mit
|
a4ca56c8c142122347a083b5abce81e4
| 0.593023 | 2.571429 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
dvb_ts_1.vhd
| 1 | 8,154 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- dvb_ts_1.vhd
-- This file was auto-generated as part of a generation operation.
-- If you edit it your changes will probably be lost.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity dvb_ts_1 is
port (
address : in std_logic_vector(8 downto 0) := (others => '0'); -- avalon_slave_0.address
byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
write : in std_logic := '0'; -- .write
readdata : out std_logic_vector(31 downto 0); -- .readdata
read : in std_logic := '0'; -- .read
waitrequest : out std_logic; -- .waitrequest
clk : in std_logic := '0'; -- clock.clk
rst : in std_logic := '0'; -- reset_sink.reset
interrupt : out std_logic; -- conduit_end.export
cam_bypass : in std_logic := '0'; -- .export
dvb_in0_dsop : in std_logic := '0'; -- .export
dvb_in0_data : in std_logic_vector(7 downto 0) := (others => '0'); -- .export
dvb_in0_dval : in std_logic := '0'; -- .export
dvb_in1_dsop : in std_logic := '0'; -- .export
dvb_in1_data : in std_logic_vector(7 downto 0) := (others => '0'); -- .export
dvb_in1_dval : in std_logic := '0'; -- .export
dvb_in2_dsop : in std_logic := '0'; -- .export
dvb_in2_data : in std_logic_vector(7 downto 0) := (others => '0'); -- .export
dvb_in2_dval : in std_logic := '0'; -- .export
cam_baseclk : in std_logic := '0'; -- .export
cam_mclki : out std_logic; -- .export
cam_mdi : out std_logic_vector(7 downto 0); -- .export
cam_mival : out std_logic; -- .export
cam_mistrt : out std_logic; -- .export
cam_mclko : in std_logic := '0'; -- .export
cam_mdo : in std_logic_vector(7 downto 0) := (others => '0'); -- .export
cam_mostrt : in std_logic := '0'; -- .export
cam_moval : in std_logic := '0'; -- .export
dvb_out_dsop : out std_logic; -- .export
dvb_out_dval : out std_logic; -- .export
dvb_out_data : out std_logic_vector(7 downto 0) -- .export
);
end entity dvb_ts_1;
architecture rtl of dvb_ts_1 is
component dvb_ts is
port (
address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
write : in std_logic := 'X'; -- write
readdata : out std_logic_vector(31 downto 0); -- readdata
read : in std_logic := 'X'; -- read
waitrequest : out std_logic; -- waitrequest
clk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
interrupt : out std_logic; -- export
cam_bypass : in std_logic := 'X'; -- export
dvb_in0_dsop : in std_logic := 'X'; -- export
dvb_in0_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
dvb_in0_dval : in std_logic := 'X'; -- export
dvb_in1_dsop : in std_logic := 'X'; -- export
dvb_in1_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
dvb_in1_dval : in std_logic := 'X'; -- export
dvb_in2_dsop : in std_logic := 'X'; -- export
dvb_in2_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
dvb_in2_dval : in std_logic := 'X'; -- export
cam_baseclk : in std_logic := 'X'; -- export
cam_mclki : out std_logic; -- export
cam_mdi : out std_logic_vector(7 downto 0); -- export
cam_mival : out std_logic; -- export
cam_mistrt : out std_logic; -- export
cam_mclko : in std_logic := 'X'; -- export
cam_mdo : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
cam_mostrt : in std_logic := 'X'; -- export
cam_moval : in std_logic := 'X'; -- export
dvb_out_dsop : out std_logic; -- export
dvb_out_dval : out std_logic; -- export
dvb_out_data : out std_logic_vector(7 downto 0) -- export
);
end component dvb_ts;
begin
dvb_ts_1 : component dvb_ts
port map (
address => address, -- avalon_slave_0.address
byteenable => byteenable, -- .byteenable
writedata => writedata, -- .writedata
write => write, -- .write
readdata => readdata, -- .readdata
read => read, -- .read
waitrequest => waitrequest, -- .waitrequest
clk => clk, -- clock.clk
rst => rst, -- reset_sink.reset
interrupt => interrupt, -- conduit_end.export
cam_bypass => cam_bypass, -- .export
dvb_in0_dsop => dvb_in0_dsop, -- .export
dvb_in0_data => dvb_in0_data, -- .export
dvb_in0_dval => dvb_in0_dval, -- .export
dvb_in1_dsop => dvb_in1_dsop, -- .export
dvb_in1_data => dvb_in1_data, -- .export
dvb_in1_dval => dvb_in1_dval, -- .export
dvb_in2_dsop => dvb_in2_dsop, -- .export
dvb_in2_data => dvb_in2_data, -- .export
dvb_in2_dval => dvb_in2_dval, -- .export
cam_baseclk => cam_baseclk, -- .export
cam_mclki => cam_mclki, -- .export
cam_mdi => cam_mdi, -- .export
cam_mival => cam_mival, -- .export
cam_mistrt => cam_mistrt, -- .export
cam_mclko => cam_mclko, -- .export
cam_mdo => cam_mdo, -- .export
cam_mostrt => cam_mostrt, -- .export
cam_moval => cam_moval, -- .export
dvb_out_dsop => dvb_out_dsop, -- .export
dvb_out_dval => dvb_out_dval, -- .export
dvb_out_data => dvb_out_data -- .export
);
end architecture rtl; -- of dvb_ts_1
|
gpl-3.0
|
22ad2e86d123788c7ba5cdf556421d09
| 0.395021 | 3.806723 | false | false | false | false |
sundw2014/hackrf
|
firmware/cpld/sgpio_if_passthrough/top.vhd
| 14 | 1,910 |
--
-- Copyright 2012 Jared Boone
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.vcomponents.all;
entity top is
Port(
SGPIO : inout std_logic_vector(15 downto 0);
DA : in std_logic_vector(7 downto 0);
DD : out std_logic_vector(9 downto 0);
CODEC_CLK : in std_logic;
CODEC_X2_CLK : in std_logic;
B1AUX : in std_logic_vector(16 downto 9);
B2AUX : inout std_logic_vector(16 downto 1)
);
end top;
architecture Behavioral of top is
type transfer_direction is (to_sgpio, from_sgpio);
signal transfer_direction_i : transfer_direction;
begin
transfer_direction_i <= to_sgpio when B1AUX(9) = '0'
else from_sgpio;
DD <= (DD'high => '1', others => '0');
B2AUX <= SGPIO when transfer_direction_i = from_sgpio
else (others => 'Z');
SGPIO <= B2AUX when transfer_direction_i = to_sgpio
else (others => 'Z');
end Behavioral;
|
gpl-2.0
|
9a87609c3c35c3138e6450b5d3628806
| 0.604188 | 3.930041 | false | false | false | false |
arthurbenemann/fpga-bits
|
fm_transmitter/seven_seg.vhd
| 1 | 2,094 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity seven_seg is
Port ( display_hex : in STD_LOGIC_VECTOR (15 downto 0);
clk : in STD_LOGIC;
double_dot : IN STD_LOGIC;
anodes : out STD_LOGIC_VECTOR (4 downto 0);
sevenseg : out STD_LOGIC_VECTOR (7 downto 0));
end seven_seg;
architecture Behavioral of seven_seg is
signal value : STD_LOGIC_VECTOR(4 downto 0) := (OTHERS =>'0');
signal anodes_buf : STD_LOGIC_VECTOR(4 downto 0);
begin
anodes <= anodes_buf;
display_update:process(clk) begin
if rising_edge(clk) then
CASE anodes_buf IS
WHEN "01111" =>
anodes_buf <= "10111";
value <= "0" & display_hex(3 downto 0);
WHEN "10111" =>
anodes_buf <= "11011";
value <= "0" & display_hex(7 downto 4);
WHEN "11011" =>
anodes_buf <= "11101";
value <= "0" & display_hex(11 downto 8);
WHEN "11101" =>
anodes_buf <= "11110";
value <= "0" & display_hex(15 downto 12);
WHEN OTHERS =>
anodes_buf <= "01111";
value <= "10000";
END CASE;
end if;
end process;
display_mapping:process(value, double_dot) begin
CASE value IS
WHEN "0" & x"0" => sevenseg <= NOT x"3F"; -- 0
WHEN "0" & x"1" => sevenseg <= NOT x"06"; -- 1
WHEN "0" & x"2" => sevenseg <= NOT x"5B"; -- 2
WHEN "0" & x"3" => sevenseg <= NOT x"4F"; -- 3
WHEN "0" & x"4" => sevenseg <= NOT (x"66"or x"80"); -- 4
WHEN "0" & x"5" => sevenseg <= NOT x"6D"; -- 5
WHEN "0" & x"6" => sevenseg <= NOT x"7D"; -- 6
WHEN "0" & x"7" => sevenseg <= NOT x"07"; -- 7
WHEN "0" & x"8" => sevenseg <= NOT x"7F"; -- 8
WHEN "0" & x"9" => sevenseg <= NOT x"6F"; -- 9
WHEN "0" & x"a" => sevenseg <= NOT x"77"; -- A
WHEN "0" & x"b" => sevenseg <= NOT x"7C"; -- b
WHEN "0" & x"c" => sevenseg <= NOT x"39"; -- C
WHEN "0" & x"d" => sevenseg <= NOT x"5E"; -- d
WHEN "0" & x"e" => sevenseg <= NOT x"79"; -- E
WHEN "0" & x"f" => sevenseg <= NOT x"71"; -- F
WHEN OTHERS => sevenseg <= "1111111" & ( NOT double_dot);
END CASE;
end process;
end Behavioral;
|
gpl-3.0
|
3e440b6ffaec3c33e7b7ef40e95a2f8c
| 0.542502 | 2.82973 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
ci_bridge.vhd
| 1 | 13,092 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- altera vhdl_input_version vhdl_2008
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ci_bridge is
port (
clk : in std_logic;
rst : in std_logic;
-- CI control port (avalon-MM slave)
address : in std_logic_vector(1 downto 0);
byteenable : in std_logic_vector(1 downto 0);
writedata : in std_logic_vector(15 downto 0);
write : in std_logic;
readdata : out std_logic_vector(15 downto 0);
interrupt : out std_logic;
-- CI data port (avalon-MM slave)
cam_address : in std_logic_vector(17 downto 0);
cam_writedata : in std_logic_vector(7 downto 0);
cam_write : in std_logic;
cam_readdata : out std_logic_vector(7 downto 0);
cam_read : in std_logic;
cam_waitreq : out std_logic;
cam_interrupts : out std_logic_vector(1 downto 0);
-- conduit (CI bus)
cia_reset : out std_logic;
cib_reset : out std_logic;
cia_ce_n : out std_logic;
cib_ce_n : out std_logic;
ci_reg_n : out std_logic;
ci_a : out std_logic_vector(14 downto 0);
ci_d_out : out std_logic_vector(7 downto 0);
ci_d_in : in std_logic_vector(7 downto 0);
ci_d_en : out std_logic;
ci_we_n : out std_logic;
ci_oe_n : out std_logic;
ci_iowr_n : out std_logic;
ci_iord_n : out std_logic;
cia_wait_n : in std_logic;
cib_wait_n : in std_logic;
cia_ireq_n : in std_logic;
cib_ireq_n : in std_logic;
cia_cd_n : in std_logic_vector(1 downto 0);
cib_cd_n : in std_logic_vector(1 downto 0);
-- conduit (CI bus helpers)
cia_overcurrent_n : in std_logic;
cib_overcurrent_n : in std_logic;
cia_reset_buf_oe_n : out std_logic;
cib_reset_buf_oe_n : out std_logic;
cia_data_buf_oe_n : out std_logic;
cib_data_buf_oe_n : out std_logic;
ci_bus_dir : out std_logic;
-- conduit (CAM status)
cam0_ready : out std_logic;
cam0_fail : out std_logic;
cam0_bypass : out std_logic;
cam1_ready : out std_logic;
cam1_fail : out std_logic;
cam1_bypass : out std_logic
);
end entity;
architecture rtl of ci_bridge is
constant BIT_CAM0_STCHG : natural := 0;
constant BIT_CAM0_PRESENT : natural := 1;
constant BIT_CAM0_RESET : natural := 2;
constant BIT_CAM0_BYPASS : natural := 3;
constant BIT_CAM0_READY : natural := 4;
constant BIT_CAM0_ERROR : natural := 5;
constant BIT_CAM0_OVERCURR : natural := 6;
constant BIT_CAM0_BUSY : natural := 7;
constant BIT_CAM1_STCHG : natural := 8;
constant BIT_CAM1_PRESENT : natural := 9;
constant BIT_CAM1_RESET : natural := 10;
constant BIT_CAM1_BYPASS : natural := 11;
constant BIT_CAM1_READY : natural := 12;
constant BIT_CAM1_ERROR : natural := 13;
constant BIT_CAM1_OVERCURR : natural := 14;
constant BIT_CAM1_BUSY : natural := 15;
signal scratchpad_reg : std_logic_vector(15 downto 0);
signal status_reg : std_logic_vector(15 downto 0);
signal ci_timeout_cnt : unsigned(9 downto 0);
alias ci_access_cnt is ci_timeout_cnt(4 downto 0);
signal cia_ce_i : std_logic;
signal cib_ce_i : std_logic;
signal ci_iord_i : std_logic;
signal ci_iowr_i : std_logic;
signal ci_oe_i : std_logic;
signal ci_we_i : std_logic;
signal ci_d_latch : std_logic_vector(7 downto 0);
signal cia_data_buf_oe_i : std_logic;
signal cib_data_buf_oe_i : std_logic;
signal cam_ready : std_logic;
signal cia_wait_meta : std_logic;
signal cia_wait : std_logic;
signal cib_wait_meta : std_logic;
signal cib_wait : std_logic;
signal ci_access_io : std_logic;
signal ci_access_read : std_logic;
signal ci_state_idle_n : std_logic;
signal ci_state_access : std_logic;
signal ci_state_wait : std_logic;
signal ci_state_ack : std_logic;
signal ci_state_hold : std_logic;
signal ci_evt_error : std_logic;
signal ci_oe_start : std_logic;
signal ci_oe_end : std_logic;
signal ci_we_start : std_logic;
signal ci_we_end : std_logic;
signal ci_iord_start : std_logic;
signal ci_iord_end : std_logic;
signal ci_iowr_start : std_logic;
signal ci_iowr_end : std_logic;
signal bus_oe_start : std_logic;
signal cam0_soft_rst : std_logic;
signal cam0_stschg_ack : std_logic;
signal cia_timeout : std_logic;
signal cam1_soft_rst : std_logic;
signal cam1_stschg_ack : std_logic;
signal cib_timeout : std_logic;
signal cam0_stschg : std_logic;
signal cam0_present : std_logic;
signal cam0_reset : std_logic;
signal cam0_bypass_n : std_logic;
signal cam0_ready_i : std_logic;
signal cam0_error : std_logic;
signal cam0_ovcp : std_logic;
signal cam0_busy : std_logic;
signal cam1_stschg : std_logic;
signal cam1_present : std_logic;
signal cam1_reset : std_logic;
signal cam1_bypass_n : std_logic;
signal cam1_ready_i : std_logic;
signal cam1_error : std_logic;
signal cam1_ovcp : std_logic;
signal cam1_busy : std_logic;
begin
status_reg <= (
BIT_CAM0_STCHG => cam0_stschg,
BIT_CAM0_PRESENT => cam0_present,
BIT_CAM0_RESET => cam0_reset,
BIT_CAM0_BYPASS => not cam0_bypass_n,
BIT_CAM0_READY => cam0_ready_i,
BIT_CAM0_ERROR => cam0_error,
BIT_CAM0_OVERCURR => cam0_ovcp,
BIT_CAM0_BUSY => cam0_busy,
--
BIT_CAM1_STCHG => cam1_stschg,
BIT_CAM1_PRESENT => cam1_present,
BIT_CAM1_RESET => cam1_reset,
BIT_CAM1_BYPASS => not cam1_bypass_n,
BIT_CAM1_READY => cam1_ready_i,
BIT_CAM1_ERROR => cam1_error,
BIT_CAM1_OVERCURR => cam1_ovcp,
BIT_CAM1_BUSY => cam1_busy
);
readdata <= scratchpad_reg when address(1) else status_reg;
interrupt <= cam0_stschg or cam1_stschg;
cam_waitreq <= not cam_ready;
cam0_soft_rst <= write and byteenable(BIT_CAM0_RESET / 8) and writedata(BIT_CAM0_RESET) and (address(0) nor address(1));
cam0_stschg_ack <= write and byteenable(BIT_CAM0_STCHG / 8) and writedata(BIT_CAM0_STCHG) and address(0) and not address(1);
cia_timeout <= ci_evt_error and cia_ce_i;
cam1_soft_rst <= write and byteenable(BIT_CAM1_RESET / 8) and writedata(BIT_CAM1_RESET) and (address(0) nor address(1));
cam1_stschg_ack <= write and byteenable(BIT_CAM1_STCHG / 8) and writedata(BIT_CAM1_STCHG) and address(0) and not address(1);
cib_timeout <= ci_evt_error and cib_ce_i;
cam0_fail <= cam0_error or cam0_ovcp;
cam0_ready <= cam0_ready_i;
cam0_bypass <= not cam0_bypass_n;
cam1_fail <= cam1_error or cam1_ovcp;
cam1_ready <= cam1_ready_i;
cam1_bypass <= not cam1_bypass_n;
CI_CTRL_0 : entity work.ci_control
port map (
rst => rst,
clk => clk,
--
soft_reset => cam0_soft_rst,
stschg_ack => cam0_stschg_ack,
ci_timeout => cia_timeout,
--
ci_cd_n => cia_cd_n,
ci_reset => cia_reset,
ci_reset_oe_n => cia_reset_buf_oe_n,
ci_overcurrent_n => cia_overcurrent_n,
ci_ireq_n => cia_ireq_n,
--
cam_stschg => cam0_stschg,
cam_present => cam0_present,
cam_reset => cam0_reset,
cam_ready => cam0_ready_i,
cam_error => cam0_error,
cam_ovcp => cam0_ovcp,
cam_busy => cam0_busy,
cam_interrupt => cam_interrupts(0)
);
CI_CTRL_1 : entity work.ci_control
port map (
rst => rst,
clk => clk,
--
soft_reset => cam1_soft_rst,
stschg_ack => cam1_stschg_ack,
ci_timeout => cib_timeout,
--
ci_cd_n => cib_cd_n,
ci_reset => cib_reset,
ci_reset_oe_n => cib_reset_buf_oe_n,
ci_overcurrent_n => cib_overcurrent_n,
ci_ireq_n => cib_ireq_n,
--
cam_stschg => cam1_stschg,
cam_present => cam1_present,
cam_reset => cam1_reset,
cam_ready => cam1_ready_i,
cam_error => cam1_error,
cam_ovcp => cam1_ovcp,
cam_busy => cam1_busy,
cam_interrupt => cam_interrupts(1)
);
ci_oe_start <= not ci_state_access and not ci_access_io and ci_access_read when ci_access_cnt = 1 else '0';
ci_oe_end <= not ci_state_wait and ci_oe_i when ci_access_cnt = 16 else '0';
ci_we_start <= not ci_state_access and not ci_access_io and not ci_access_read when ci_access_cnt = 1 else '0';
ci_we_end <= not ci_state_wait and ci_we_i when ci_access_cnt = 11 else '0';
ci_iord_start <= not ci_state_access and ci_access_io and ci_access_read when ci_access_cnt = 4 else '0';
ci_iord_end <= not ci_state_wait and ci_iord_i when ci_access_cnt = 13 else '0';
ci_iowr_start <= not ci_state_access and ci_access_io and not ci_access_read when ci_access_cnt = 7 else '0';
ci_iowr_end <= not ci_state_wait and ci_iowr_i when ci_access_cnt = 16 else '0';
bus_oe_start <= ci_access_read when ci_access_cnt = 1 else not ci_access_read when ci_access_cnt = 3 else '0';
process (rst, clk)
begin
if rising_edge(clk) then
if write and address(1) then
if byteenable(0) then
scratchpad_reg(7 downto 0) <= writedata(7 downto 0);
end if;
if byteenable(1) then
scratchpad_reg(15 downto 8) <= writedata(15 downto 8);
end if;
end if;
if not cam0_present then
cam0_bypass_n <= '0';
elsif write and byteenable(BIT_CAM0_BYPASS / 8) and writedata(BIT_CAM0_BYPASS) and not address(1) then
cam0_bypass_n <= address(0);
end if;
if not cam1_present then
cam1_bypass_n <= '0';
elsif write and byteenable(BIT_CAM1_BYPASS / 8) and writedata(BIT_CAM1_BYPASS) and not address(1) then
cam1_bypass_n <= address(0);
end if;
--
ci_d_latch <= ci_d_in;
--
cia_wait_meta <= not cia_wait_n;
cia_wait <= cia_wait_meta;
cib_wait_meta <= not cib_wait_n;
cib_wait <= cib_wait_meta;
-- CI main timer
if not ci_state_idle_n then
ci_timeout_cnt <= (others => '0');
else
ci_timeout_cnt <= ci_timeout_cnt + 1;
end if;
-- CI events
if ci_timeout_cnt = 750 then
ci_evt_error <= '1';
else
ci_evt_error <= '0';
end if;
cam_ready <= (ci_state_ack or ci_evt_error) and not ci_state_hold;
-- state machine
if cam_ready then
ci_state_idle_n <= '0';
elsif not ci_state_idle_n then
ci_state_idle_n <= cam_read or cam_write;
end if;
if not ci_state_idle_n then
ci_state_access <= '0';
elsif ci_oe_start or ci_we_start or ci_iord_start or ci_iowr_start then
ci_state_access <= '1';
end if;
if not ci_state_idle_n then
ci_state_wait <= '0';
elsif ci_oe_end or ci_we_end or ci_iord_end or ci_iowr_end then
ci_state_wait <= '1';
end if;
if not ci_state_idle_n then
ci_state_ack <= '0';
elsif not ci_state_ack then
ci_state_ack <= ci_state_wait and ((cia_wait and cia_ce_i) nor (cib_wait and cib_ce_i));
end if;
if not ci_state_idle_n then
ci_state_hold <= '0';
elsif not ci_state_hold then
ci_state_hold <= ci_evt_error or ci_state_ack;
end if;
--
if not ci_state_idle_n then
cia_ce_i <= (cam_read or cam_write) and not cam_address(17);
cib_ce_i <= (cam_read or cam_write) and cam_address(17);
end if;
if not ci_state_idle_n and (cam_read or cam_write) then
ci_reg_n <= cam_address(16);
ci_a <= cam_address(14 downto 0);
ci_d_out <= cam_writedata;
ci_access_io <= cam_address(15) and not cam_address(16);
ci_access_read <= cam_read;
end if;
if not ci_state_idle_n then
cam_readdata <= (others => '1');
elsif ci_state_ack and not ci_state_hold then
cam_readdata <= ci_d_latch;
end if;
-- Data direction control
ci_d_en <= ci_state_idle_n and not ci_access_read;
ci_bus_dir <= ci_access_read;
cia_data_buf_oe_i <= ci_state_idle_n and cia_ce_i and (cia_data_buf_oe_i or bus_oe_start);
cib_data_buf_oe_i <= ci_state_idle_n and cib_ce_i and (cib_data_buf_oe_i or bus_oe_start);
--
if ci_oe_start then
ci_oe_i <= '1';
elsif ci_state_ack or ci_evt_error then
ci_oe_i <= '0';
end if;
if ci_we_start then
ci_we_i <= '1';
elsif ci_state_ack or ci_evt_error then
ci_we_i <= '0';
end if;
if ci_iord_start then
ci_iord_i <= '1';
elsif ci_state_ack or ci_evt_error then
ci_iord_i <= '0';
end if;
if ci_iowr_start then
ci_iowr_i <= '1';
elsif ci_state_ack or ci_evt_error then
ci_iowr_i <= '0';
end if;
end if;
if rst then
scratchpad_reg <= (others => '0');
cam0_bypass_n <= '0';
cam1_bypass_n <= '0';
--
ci_d_latch <= (others => '0');
cia_wait_meta <= '0';
cia_wait <= '0';
cib_wait_meta <= '0';
cib_wait <= '0';
--
ci_timeout_cnt <= (others => '0');
ci_access_io <= '0';
ci_access_read <= '0';
ci_evt_error <= '0';
--
ci_state_idle_n <= '0';
ci_state_access <= '0';
ci_state_wait <= '0';
ci_state_ack <= '0';
ci_state_hold <= '0';
--
cam_ready <= '0';
cam_readdata <= (others => '0');
--
cia_ce_i <= '0';
cib_ce_i <= '0';
ci_reg_n <= '0';
ci_a <= (others => '0');
ci_d_out <= (others => '0');
ci_d_en <= '0';
ci_bus_dir <= '0';
cia_data_buf_oe_i <= '0';
cib_data_buf_oe_i <= '0';
ci_oe_i <= '0';
ci_we_i <= '0';
ci_iord_i <= '0';
ci_iowr_i <= '0';
end if;
end process;
cia_ce_n <= not cia_ce_i;
cib_ce_n <= not cib_ce_i;
ci_oe_n <= not ci_oe_i;
ci_we_n <= not ci_we_i;
ci_iord_n <= not ci_iord_i;
ci_iowr_n <= not ci_iowr_i;
cia_data_buf_oe_n <= not cia_data_buf_oe_i;
cib_data_buf_oe_n <= not cib_data_buf_oe_i;
end architecture;
|
gpl-3.0
|
c81484c8c7b02cff77b7869a63687889
| 0.629774 | 2.446188 | false | false | false | false |
andrewandrepowell/kernel-on-chip
|
hdl/projects/Nexys4/plasoc_cpu_0_crossbar_wrap.vhd
| 1 | 45,569 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.plasoc_crossbar_pack.plasoc_crossbar;
use work.plasoc_cpu_0_crossbar_wrap_pack.all;
entity plasoc_cpu_0_crossbar_wrap is
generic
(
axi_address_width : integer := 32;
axi_data_width : integer := 32;
axi_slave_id_width : integer := 0;
axi_master_amount : integer := 5;
axi_slave_amount : integer := 1;
axi_master_base_address : std_logic_vector := X"f0030000f0020000f0010000f000000000000000";
axi_master_high_address : std_logic_vector := X"f003fffff002fffff001fffff000ffffefffffff"
);
port
(
cpu_s_axi_awid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
cpu_s_axi_awlen : in std_logic_vector(7 downto 0);
cpu_s_axi_awsize : in std_logic_vector(2 downto 0);
cpu_s_axi_awburst : in std_logic_vector(1 downto 0);
cpu_s_axi_awlock : in std_logic;
cpu_s_axi_awcache : in std_logic_vector(3 downto 0);
cpu_s_axi_awprot : in std_logic_vector(2 downto 0);
cpu_s_axi_awqos : in std_logic_vector(3 downto 0);
cpu_s_axi_awregion : in std_logic_vector(3 downto 0);
cpu_s_axi_awvalid : in std_logic;
cpu_s_axi_awready : out std_logic;
cpu_s_axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
cpu_s_axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
cpu_s_axi_wlast : in std_logic;
cpu_s_axi_wvalid : in std_logic;
cpu_s_axi_wready : out std_logic;
cpu_s_axi_bid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_bresp : out std_logic_vector(1 downto 0);
cpu_s_axi_bvalid : out std_logic;
cpu_s_axi_bready : in std_logic;
cpu_s_axi_arid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
cpu_s_axi_arlen : in std_logic_vector(7 downto 0);
cpu_s_axi_arsize : in std_logic_vector(2 downto 0);
cpu_s_axi_arburst : in std_logic_vector(1 downto 0);
cpu_s_axi_arlock : in std_logic;
cpu_s_axi_arcache : in std_logic_vector(3 downto 0);
cpu_s_axi_arprot : in std_logic_vector(2 downto 0);
cpu_s_axi_arqos : in std_logic_vector(3 downto 0);
cpu_s_axi_arregion : in std_logic_vector(3 downto 0);
cpu_s_axi_arvalid : in std_logic;
cpu_s_axi_arready : out std_logic;
cpu_s_axi_rid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_rdata : out std_logic_vector(axi_data_width-1 downto 0);
cpu_s_axi_rresp : out std_logic_vector(1 downto 0);
cpu_s_axi_rlast : out std_logic;
cpu_s_axi_rvalid : out std_logic;
cpu_s_axi_rready : in std_logic;
ip_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ip_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
ip_m_axi_awlen : out std_logic_vector(7 downto 0);
ip_m_axi_awsize : out std_logic_vector(2 downto 0);
ip_m_axi_awburst : out std_logic_vector(1 downto 0);
ip_m_axi_awlock : out std_logic;
ip_m_axi_awcache : out std_logic_vector(3 downto 0);
ip_m_axi_awprot : out std_logic_vector(2 downto 0);
ip_m_axi_awqos : out std_logic_vector(3 downto 0);
ip_m_axi_awregion : out std_logic_vector(3 downto 0);
ip_m_axi_awvalid : out std_logic;
ip_m_axi_awready : in std_logic;
ip_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
ip_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
ip_m_axi_wlast : out std_logic;
ip_m_axi_wvalid : out std_logic;
ip_m_axi_wready : in std_logic;
ip_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ip_m_axi_bresp : in std_logic_vector(1 downto 0);
ip_m_axi_bvalid : in std_logic;
ip_m_axi_bready : out std_logic;
ip_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ip_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
ip_m_axi_arlen : out std_logic_vector(7 downto 0);
ip_m_axi_arsize : out std_logic_vector(2 downto 0);
ip_m_axi_arburst : out std_logic_vector(1 downto 0);
ip_m_axi_arlock : out std_logic;
ip_m_axi_arcache : out std_logic_vector(3 downto 0);
ip_m_axi_arprot : out std_logic_vector(2 downto 0);
ip_m_axi_arqos : out std_logic_vector(3 downto 0);
ip_m_axi_arregion : out std_logic_vector(3 downto 0);
ip_m_axi_arvalid : out std_logic;
ip_m_axi_arready : in std_logic;
ip_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ip_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
ip_m_axi_rresp : in std_logic_vector(1 downto 0);
ip_m_axi_rlast : in std_logic;
ip_m_axi_rvalid : in std_logic;
ip_m_axi_rready : out std_logic;
cpuid_gpio_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cpuid_gpio_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
cpuid_gpio_m_axi_awlen : out std_logic_vector(7 downto 0);
cpuid_gpio_m_axi_awsize : out std_logic_vector(2 downto 0);
cpuid_gpio_m_axi_awburst : out std_logic_vector(1 downto 0);
cpuid_gpio_m_axi_awlock : out std_logic;
cpuid_gpio_m_axi_awcache : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_awprot : out std_logic_vector(2 downto 0);
cpuid_gpio_m_axi_awqos : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_awregion : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_awvalid : out std_logic;
cpuid_gpio_m_axi_awready : in std_logic;
cpuid_gpio_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
cpuid_gpio_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
cpuid_gpio_m_axi_wlast : out std_logic;
cpuid_gpio_m_axi_wvalid : out std_logic;
cpuid_gpio_m_axi_wready : in std_logic;
cpuid_gpio_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cpuid_gpio_m_axi_bresp : in std_logic_vector(1 downto 0);
cpuid_gpio_m_axi_bvalid : in std_logic;
cpuid_gpio_m_axi_bready : out std_logic;
cpuid_gpio_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cpuid_gpio_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
cpuid_gpio_m_axi_arlen : out std_logic_vector(7 downto 0);
cpuid_gpio_m_axi_arsize : out std_logic_vector(2 downto 0);
cpuid_gpio_m_axi_arburst : out std_logic_vector(1 downto 0);
cpuid_gpio_m_axi_arlock : out std_logic;
cpuid_gpio_m_axi_arcache : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_arprot : out std_logic_vector(2 downto 0);
cpuid_gpio_m_axi_arqos : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_arregion : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_arvalid : out std_logic;
cpuid_gpio_m_axi_arready : in std_logic;
cpuid_gpio_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cpuid_gpio_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
cpuid_gpio_m_axi_rresp : in std_logic_vector(1 downto 0);
cpuid_gpio_m_axi_rlast : in std_logic;
cpuid_gpio_m_axi_rvalid : in std_logic;
cpuid_gpio_m_axi_rready : out std_logic;
int_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
int_m_axi_awlen : out std_logic_vector(7 downto 0);
int_m_axi_awsize : out std_logic_vector(2 downto 0);
int_m_axi_awburst : out std_logic_vector(1 downto 0);
int_m_axi_awlock : out std_logic;
int_m_axi_awcache : out std_logic_vector(3 downto 0);
int_m_axi_awprot : out std_logic_vector(2 downto 0);
int_m_axi_awqos : out std_logic_vector(3 downto 0);
int_m_axi_awregion : out std_logic_vector(3 downto 0);
int_m_axi_awvalid : out std_logic;
int_m_axi_awready : in std_logic;
int_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
int_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
int_m_axi_wlast : out std_logic;
int_m_axi_wvalid : out std_logic;
int_m_axi_wready : in std_logic;
int_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_bresp : in std_logic_vector(1 downto 0);
int_m_axi_bvalid : in std_logic;
int_m_axi_bready : out std_logic;
int_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
int_m_axi_arlen : out std_logic_vector(7 downto 0);
int_m_axi_arsize : out std_logic_vector(2 downto 0);
int_m_axi_arburst : out std_logic_vector(1 downto 0);
int_m_axi_arlock : out std_logic;
int_m_axi_arcache : out std_logic_vector(3 downto 0);
int_m_axi_arprot : out std_logic_vector(2 downto 0);
int_m_axi_arqos : out std_logic_vector(3 downto 0);
int_m_axi_arregion : out std_logic_vector(3 downto 0);
int_m_axi_arvalid : out std_logic;
int_m_axi_arready : in std_logic;
int_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
int_m_axi_rresp : in std_logic_vector(1 downto 0);
int_m_axi_rlast : in std_logic;
int_m_axi_rvalid : in std_logic;
int_m_axi_rready : out std_logic;
signal_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
signal_m_axi_awlen : out std_logic_vector(7 downto 0);
signal_m_axi_awsize : out std_logic_vector(2 downto 0);
signal_m_axi_awburst : out std_logic_vector(1 downto 0);
signal_m_axi_awlock : out std_logic;
signal_m_axi_awcache : out std_logic_vector(3 downto 0);
signal_m_axi_awprot : out std_logic_vector(2 downto 0);
signal_m_axi_awqos : out std_logic_vector(3 downto 0);
signal_m_axi_awregion : out std_logic_vector(3 downto 0);
signal_m_axi_awvalid : out std_logic;
signal_m_axi_awready : in std_logic;
signal_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
signal_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
signal_m_axi_wlast : out std_logic;
signal_m_axi_wvalid : out std_logic;
signal_m_axi_wready : in std_logic;
signal_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal_m_axi_bresp : in std_logic_vector(1 downto 0);
signal_m_axi_bvalid : in std_logic;
signal_m_axi_bready : out std_logic;
signal_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
signal_m_axi_arlen : out std_logic_vector(7 downto 0);
signal_m_axi_arsize : out std_logic_vector(2 downto 0);
signal_m_axi_arburst : out std_logic_vector(1 downto 0);
signal_m_axi_arlock : out std_logic;
signal_m_axi_arcache : out std_logic_vector(3 downto 0);
signal_m_axi_arprot : out std_logic_vector(2 downto 0);
signal_m_axi_arqos : out std_logic_vector(3 downto 0);
signal_m_axi_arregion : out std_logic_vector(3 downto 0);
signal_m_axi_arvalid : out std_logic;
signal_m_axi_arready : in std_logic;
signal_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
signal_m_axi_rresp : in std_logic_vector(1 downto 0);
signal_m_axi_rlast : in std_logic;
signal_m_axi_rvalid : in std_logic;
signal_m_axi_rready : out std_logic;
timer_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
timer_m_axi_awlen : out std_logic_vector(7 downto 0);
timer_m_axi_awsize : out std_logic_vector(2 downto 0);
timer_m_axi_awburst : out std_logic_vector(1 downto 0);
timer_m_axi_awlock : out std_logic;
timer_m_axi_awcache : out std_logic_vector(3 downto 0);
timer_m_axi_awprot : out std_logic_vector(2 downto 0);
timer_m_axi_awqos : out std_logic_vector(3 downto 0);
timer_m_axi_awregion : out std_logic_vector(3 downto 0);
timer_m_axi_awvalid : out std_logic;
timer_m_axi_awready : in std_logic;
timer_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
timer_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
timer_m_axi_wlast : out std_logic;
timer_m_axi_wvalid : out std_logic;
timer_m_axi_wready : in std_logic;
timer_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_bresp : in std_logic_vector(1 downto 0);
timer_m_axi_bvalid : in std_logic;
timer_m_axi_bready : out std_logic;
timer_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
timer_m_axi_arlen : out std_logic_vector(7 downto 0);
timer_m_axi_arsize : out std_logic_vector(2 downto 0);
timer_m_axi_arburst : out std_logic_vector(1 downto 0);
timer_m_axi_arlock : out std_logic;
timer_m_axi_arcache : out std_logic_vector(3 downto 0);
timer_m_axi_arprot : out std_logic_vector(2 downto 0);
timer_m_axi_arqos : out std_logic_vector(3 downto 0);
timer_m_axi_arregion : out std_logic_vector(3 downto 0);
timer_m_axi_arvalid : out std_logic;
timer_m_axi_arready : in std_logic;
timer_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
timer_m_axi_rresp : in std_logic_vector(1 downto 0);
timer_m_axi_rlast : in std_logic;
timer_m_axi_rvalid : in std_logic;
timer_m_axi_rready : out std_logic;
aclk : in std_logic;
aresetn : in std_logic
);
end plasoc_cpu_0_crossbar_wrap;
architecture Behavioral of plasoc_cpu_0_crossbar_wrap is
constant axi_master_id_width : integer := clogb2(axi_slave_amount)+axi_slave_id_width;
signal s_axi_awid : std_logic_vector(axi_slave_amount*axi_slave_id_width-1 downto 0);
signal s_axi_awaddr : std_logic_vector(axi_slave_amount*axi_address_width-1 downto 0);
signal s_axi_awlen : std_logic_vector(axi_slave_amount*8-1 downto 0);
signal s_axi_awsize : std_logic_vector(axi_slave_amount*3-1 downto 0);
signal s_axi_awburst : std_logic_vector(axi_slave_amount*2-1 downto 0);
signal s_axi_awlock : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_awcache : std_logic_vector(axi_slave_amount*4-1 downto 0);
signal s_axi_awprot : std_logic_vector(axi_slave_amount*3-1 downto 0);
signal s_axi_awqos : std_logic_vector(axi_slave_amount*4-1 downto 0);
signal s_axi_awregion : std_logic_vector(axi_slave_amount*4-1 downto 0);
signal s_axi_awvalid : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_awready : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_wdata : std_logic_vector(axi_slave_amount*axi_data_width-1 downto 0);
signal s_axi_wstrb : std_logic_vector(axi_slave_amount*axi_data_width/8-1 downto 0);
signal s_axi_wlast : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_wvalid : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_wready : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_bid : std_logic_vector(axi_slave_amount*axi_slave_id_width-1 downto 0);
signal s_axi_bresp : std_logic_vector(axi_slave_amount*2-1 downto 0);
signal s_axi_bvalid : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_bready : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_arid : std_logic_vector(axi_slave_amount*axi_slave_id_width-1 downto 0);
signal s_axi_araddr : std_logic_vector(axi_slave_amount*axi_address_width-1 downto 0);
signal s_axi_arlen : std_logic_vector(axi_slave_amount*8-1 downto 0);
signal s_axi_arsize : std_logic_vector(axi_slave_amount*3-1 downto 0);
signal s_axi_arburst : std_logic_vector(axi_slave_amount*2-1 downto 0);
signal s_axi_arlock : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_arcache : std_logic_vector(axi_slave_amount*4-1 downto 0);
signal s_axi_arprot : std_logic_vector(axi_slave_amount*3-1 downto 0);
signal s_axi_arqos : std_logic_vector(axi_slave_amount*4-1 downto 0);
signal s_axi_arregion : std_logic_vector(axi_slave_amount*4-1 downto 0);
signal s_axi_arvalid : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_arready : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_rid : std_logic_vector(axi_slave_amount*axi_slave_id_width-1 downto 0);
signal s_axi_rdata : std_logic_vector(axi_slave_amount*axi_data_width-1 downto 0);
signal s_axi_rresp : std_logic_vector(axi_slave_amount*2-1 downto 0);
signal s_axi_rlast : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_rvalid : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal s_axi_rready : std_logic_vector(axi_slave_amount*1-1 downto 0);
signal m_axi_awid : std_logic_vector(axi_master_amount*(clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal m_axi_awaddr : std_logic_vector(axi_master_amount*axi_address_width-1 downto 0);
signal m_axi_awlen : std_logic_vector(axi_master_amount*8-1 downto 0);
signal m_axi_awsize : std_logic_vector(axi_master_amount*3-1 downto 0);
signal m_axi_awburst : std_logic_vector(axi_master_amount*2-1 downto 0);
signal m_axi_awlock : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_awcache : std_logic_vector(axi_master_amount*4-1 downto 0);
signal m_axi_awprot : std_logic_vector(axi_master_amount*3-1 downto 0);
signal m_axi_awqos : std_logic_vector(axi_master_amount*4-1 downto 0);
signal m_axi_awregion : std_logic_vector(axi_master_amount*4-1 downto 0);
signal m_axi_awvalid : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_awready : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_wdata : std_logic_vector(axi_master_amount*axi_data_width-1 downto 0);
signal m_axi_wstrb : std_logic_vector(axi_master_amount*axi_data_width/8-1 downto 0);
signal m_axi_wlast : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_wvalid : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_wready : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_bid : std_logic_vector(axi_master_amount*(clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal m_axi_bresp : std_logic_vector(axi_master_amount*2-1 downto 0);
signal m_axi_bvalid : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_bready : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_arid : std_logic_vector(axi_master_amount*(clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal m_axi_araddr : std_logic_vector(axi_master_amount*axi_address_width-1 downto 0);
signal m_axi_arlen : std_logic_vector(axi_master_amount*8-1 downto 0);
signal m_axi_arsize : std_logic_vector(axi_master_amount*3-1 downto 0);
signal m_axi_arburst : std_logic_vector(axi_master_amount*2-1 downto 0);
signal m_axi_arlock : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_arcache : std_logic_vector(axi_master_amount*4-1 downto 0);
signal m_axi_arprot : std_logic_vector(axi_master_amount*3-1 downto 0);
signal m_axi_arqos : std_logic_vector(axi_master_amount*4-1 downto 0);
signal m_axi_arregion : std_logic_vector(axi_master_amount*4-1 downto 0);
signal m_axi_arvalid : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_arready : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_rid : std_logic_vector(axi_master_amount*(clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal m_axi_rdata : std_logic_vector(axi_master_amount*axi_data_width-1 downto 0);
signal m_axi_rresp : std_logic_vector(axi_master_amount*2-1 downto 0);
signal m_axi_rlast : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_rvalid : std_logic_vector(axi_master_amount*1-1 downto 0);
signal m_axi_rready : std_logic_vector(axi_master_amount*1-1 downto 0);
signal s_address_write_connected : std_logic_vector(axi_slave_amount-1 downto 0);
signal s_data_write_connected : std_logic_vector(axi_slave_amount-1 downto 0);
signal s_response_write_connected : std_logic_vector(axi_slave_amount-1 downto 0);
signal s_address_read_connected : std_logic_vector(axi_slave_amount-1 downto 0);
signal s_data_read_connected : std_logic_vector(axi_slave_amount-1 downto 0);
signal m_address_write_connected : std_logic_vector(axi_master_amount-1 downto 0);
signal m_data_write_connected : std_logic_vector(axi_master_amount-1 downto 0);
signal m_response_write_connected : std_logic_vector(axi_master_amount-1 downto 0);
signal m_address_read_connected : std_logic_vector(axi_master_amount-1 downto 0);
signal m_data_read_connected : std_logic_vector(axi_master_amount-1 downto 0);
begin
s_axi_awid <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awid;
s_axi_awaddr <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awaddr;
s_axi_awlen <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awlen;
s_axi_awsize <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awsize;
s_axi_awburst <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awburst;
s_axi_awlock <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awlock;
s_axi_awcache <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awcache;
s_axi_awprot <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awprot;
s_axi_awqos <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awqos;
s_axi_awregion <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awregion;
s_axi_awvalid <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_awvalid;
s_axi_wdata <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_wdata;
s_axi_wstrb <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_wstrb;
s_axi_wlast <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_wlast;
s_axi_wvalid <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_wvalid;
s_axi_bready <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_bready;
s_axi_arid <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arid;
s_axi_araddr <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_araddr;
s_axi_arlen <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arlen;
s_axi_arsize <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arsize;
s_axi_arburst <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arburst;
s_axi_arlock <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arlock;
s_axi_arcache <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arcache;
s_axi_arprot <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arprot;
s_axi_arqos <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arqos;
s_axi_arregion <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arregion;
s_axi_arvalid <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_arvalid;
s_axi_rready <= std_logic_vector(to_unsigned(0,0)) & cpu_s_axi_rready;
m_axi_awready <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_awready & signal_m_axi_awready & int_m_axi_awready & cpuid_gpio_m_axi_awready & ip_m_axi_awready;
m_axi_wready <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_wready & signal_m_axi_wready & int_m_axi_wready & cpuid_gpio_m_axi_wready & ip_m_axi_wready;
m_axi_bid <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_bid & signal_m_axi_bid & int_m_axi_bid & cpuid_gpio_m_axi_bid & ip_m_axi_bid;
m_axi_bresp <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_bresp & signal_m_axi_bresp & int_m_axi_bresp & cpuid_gpio_m_axi_bresp & ip_m_axi_bresp;
m_axi_bvalid <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_bvalid & signal_m_axi_bvalid & int_m_axi_bvalid & cpuid_gpio_m_axi_bvalid & ip_m_axi_bvalid;
m_axi_arready <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_arready & signal_m_axi_arready & int_m_axi_arready & cpuid_gpio_m_axi_arready & ip_m_axi_arready;
m_axi_rid <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_rid & signal_m_axi_rid & int_m_axi_rid & cpuid_gpio_m_axi_rid & ip_m_axi_rid;
m_axi_rdata <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_rdata & signal_m_axi_rdata & int_m_axi_rdata & cpuid_gpio_m_axi_rdata & ip_m_axi_rdata;
m_axi_rresp <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_rresp & signal_m_axi_rresp & int_m_axi_rresp & cpuid_gpio_m_axi_rresp & ip_m_axi_rresp;
m_axi_rlast <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_rlast & signal_m_axi_rlast & int_m_axi_rlast & cpuid_gpio_m_axi_rlast & ip_m_axi_rlast;
m_axi_rvalid <= std_logic_vector(to_unsigned(0,0)) & timer_m_axi_rvalid & signal_m_axi_rvalid & int_m_axi_rvalid & cpuid_gpio_m_axi_rvalid & ip_m_axi_rvalid;
cpu_s_axi_awready <= '0' when s_address_write_connected(0)='0' else s_axi_awready(0);
cpu_s_axi_wready <= '0' when s_data_write_connected(0)='0' else s_axi_wready(0);
cpu_s_axi_bid <= (others=>'0') when s_response_write_connected(0)='0' else s_axi_bid((1+0)*axi_slave_id_width-1 downto 0*axi_slave_id_width);
cpu_s_axi_bresp <= (others=>'0') when s_response_write_connected(0)='0' else s_axi_bresp((1+0)*2-1 downto 0*2);
cpu_s_axi_bvalid <= '0' when s_response_write_connected(0)='0' else s_axi_bvalid(0);
cpu_s_axi_arready <= '0' when s_address_read_connected(0)='0' else s_axi_arready(0);
cpu_s_axi_rid <= (others=>'0') when s_data_read_connected(0)='0' else s_axi_rid((1+0)*axi_slave_id_width-1 downto 0*axi_slave_id_width);
cpu_s_axi_rdata <= (others=>'0') when s_data_read_connected(0)='0' else s_axi_rdata((1+0)*axi_data_width-1 downto 0*axi_data_width);
cpu_s_axi_rresp <= (others=>'0') when s_data_read_connected(0)='0' else s_axi_rresp((1+0)*2-1 downto 0*2);
cpu_s_axi_rlast <= '0' when s_data_read_connected(0)='0' else s_axi_rlast(0);
cpu_s_axi_rvalid <= '0' when s_data_read_connected(0)='0' else s_axi_rvalid(0);
ip_m_axi_awid <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awid((1+0)*axi_master_id_width-1 downto 0*axi_master_id_width);
cpuid_gpio_m_axi_awid <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awid((1+1)*axi_master_id_width-1 downto 1*axi_master_id_width);
int_m_axi_awid <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awid((1+2)*axi_master_id_width-1 downto 2*axi_master_id_width);
signal_m_axi_awid <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awid((1+3)*axi_master_id_width-1 downto 3*axi_master_id_width);
timer_m_axi_awid <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awid((1+4)*axi_master_id_width-1 downto 4*axi_master_id_width);
ip_m_axi_awaddr <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awaddr((1+0)*axi_address_width-1 downto 0*axi_address_width);
cpuid_gpio_m_axi_awaddr <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awaddr((1+1)*axi_address_width-1 downto 1*axi_address_width);
int_m_axi_awaddr <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awaddr((1+2)*axi_address_width-1 downto 2*axi_address_width);
signal_m_axi_awaddr <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awaddr((1+3)*axi_address_width-1 downto 3*axi_address_width);
timer_m_axi_awaddr <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awaddr((1+4)*axi_address_width-1 downto 4*axi_address_width);
ip_m_axi_awlen <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awlen((1+0)*8-1 downto 0*8);
cpuid_gpio_m_axi_awlen <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awlen((1+1)*8-1 downto 1*8);
int_m_axi_awlen <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awlen((1+2)*8-1 downto 2*8);
signal_m_axi_awlen <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awlen((1+3)*8-1 downto 3*8);
timer_m_axi_awlen <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awlen((1+4)*8-1 downto 4*8);
ip_m_axi_awsize <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awsize((1+0)*3-1 downto 0*3);
cpuid_gpio_m_axi_awsize <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awsize((1+1)*3-1 downto 1*3);
int_m_axi_awsize <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awsize((1+2)*3-1 downto 2*3);
signal_m_axi_awsize <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awsize((1+3)*3-1 downto 3*3);
timer_m_axi_awsize <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awsize((1+4)*3-1 downto 4*3);
ip_m_axi_awburst <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awburst((1+0)*2-1 downto 0*2);
cpuid_gpio_m_axi_awburst <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awburst((1+1)*2-1 downto 1*2);
int_m_axi_awburst <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awburst((1+2)*2-1 downto 2*2);
signal_m_axi_awburst <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awburst((1+3)*2-1 downto 3*2);
timer_m_axi_awburst <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awburst((1+4)*2-1 downto 4*2);
ip_m_axi_awlock <= '0' when m_address_write_connected(0)='0' else m_axi_awlock(0);
cpuid_gpio_m_axi_awlock <= '0' when m_address_write_connected(1)='0' else m_axi_awlock(1);
int_m_axi_awlock <= '0' when m_address_write_connected(2)='0' else m_axi_awlock(2);
signal_m_axi_awlock <= '0' when m_address_write_connected(3)='0' else m_axi_awlock(3);
timer_m_axi_awlock <= '0' when m_address_write_connected(4)='0' else m_axi_awlock(4);
ip_m_axi_awcache <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awcache((1+0)*4-1 downto 0*4);
cpuid_gpio_m_axi_awcache <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awcache((1+1)*4-1 downto 1*4);
int_m_axi_awcache <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awcache((1+2)*4-1 downto 2*4);
signal_m_axi_awcache <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awcache((1+3)*4-1 downto 3*4);
timer_m_axi_awcache <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awcache((1+4)*4-1 downto 4*4);
ip_m_axi_awprot <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awprot((1+0)*3-1 downto 0*3);
cpuid_gpio_m_axi_awprot <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awprot((1+1)*3-1 downto 1*3);
int_m_axi_awprot <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awprot((1+2)*3-1 downto 2*3);
signal_m_axi_awprot <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awprot((1+3)*3-1 downto 3*3);
timer_m_axi_awprot <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awprot((1+4)*3-1 downto 4*3);
ip_m_axi_awqos <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awqos((1+0)*4-1 downto 0*4);
cpuid_gpio_m_axi_awqos <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awqos((1+1)*4-1 downto 1*4);
int_m_axi_awqos <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awqos((1+2)*4-1 downto 2*4);
signal_m_axi_awqos <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awqos((1+3)*4-1 downto 3*4);
timer_m_axi_awqos <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awqos((1+4)*4-1 downto 4*4);
ip_m_axi_awregion <= (others=>'0') when m_address_write_connected(0)='0' else m_axi_awregion((1+0)*4-1 downto 0*4);
cpuid_gpio_m_axi_awregion <= (others=>'0') when m_address_write_connected(1)='0' else m_axi_awregion((1+1)*4-1 downto 1*4);
int_m_axi_awregion <= (others=>'0') when m_address_write_connected(2)='0' else m_axi_awregion((1+2)*4-1 downto 2*4);
signal_m_axi_awregion <= (others=>'0') when m_address_write_connected(3)='0' else m_axi_awregion((1+3)*4-1 downto 3*4);
timer_m_axi_awregion <= (others=>'0') when m_address_write_connected(4)='0' else m_axi_awregion((1+4)*4-1 downto 4*4);
ip_m_axi_awvalid <= '0' when m_address_write_connected(0)='0' else m_axi_awvalid(0);
cpuid_gpio_m_axi_awvalid <= '0' when m_address_write_connected(1)='0' else m_axi_awvalid(1);
int_m_axi_awvalid <= '0' when m_address_write_connected(2)='0' else m_axi_awvalid(2);
signal_m_axi_awvalid <= '0' when m_address_write_connected(3)='0' else m_axi_awvalid(3);
timer_m_axi_awvalid <= '0' when m_address_write_connected(4)='0' else m_axi_awvalid(4);
ip_m_axi_wdata <= (others=>'0') when m_data_write_connected(0)='0' else m_axi_wdata((1+0)*axi_data_width-1 downto 0*axi_data_width);
cpuid_gpio_m_axi_wdata <= (others=>'0') when m_data_write_connected(1)='0' else m_axi_wdata((1+1)*axi_data_width-1 downto 1*axi_data_width);
int_m_axi_wdata <= (others=>'0') when m_data_write_connected(2)='0' else m_axi_wdata((1+2)*axi_data_width-1 downto 2*axi_data_width);
signal_m_axi_wdata <= (others=>'0') when m_data_write_connected(3)='0' else m_axi_wdata((1+3)*axi_data_width-1 downto 3*axi_data_width);
timer_m_axi_wdata <= (others=>'0') when m_data_write_connected(4)='0' else m_axi_wdata((1+4)*axi_data_width-1 downto 4*axi_data_width);
ip_m_axi_wstrb <= (others=>'0') when m_data_write_connected(0)='0' else m_axi_wstrb((1+0)*axi_data_width/8-1 downto 0*axi_data_width/8);
cpuid_gpio_m_axi_wstrb <= (others=>'0') when m_data_write_connected(1)='0' else m_axi_wstrb((1+1)*axi_data_width/8-1 downto 1*axi_data_width/8);
int_m_axi_wstrb <= (others=>'0') when m_data_write_connected(2)='0' else m_axi_wstrb((1+2)*axi_data_width/8-1 downto 2*axi_data_width/8);
signal_m_axi_wstrb <= (others=>'0') when m_data_write_connected(3)='0' else m_axi_wstrb((1+3)*axi_data_width/8-1 downto 3*axi_data_width/8);
timer_m_axi_wstrb <= (others=>'0') when m_data_write_connected(4)='0' else m_axi_wstrb((1+4)*axi_data_width/8-1 downto 4*axi_data_width/8);
ip_m_axi_wlast <= '0' when m_data_write_connected(0)='0' else m_axi_wlast(0);
cpuid_gpio_m_axi_wlast <= '0' when m_data_write_connected(1)='0' else m_axi_wlast(1);
int_m_axi_wlast <= '0' when m_data_write_connected(2)='0' else m_axi_wlast(2);
signal_m_axi_wlast <= '0' when m_data_write_connected(3)='0' else m_axi_wlast(3);
timer_m_axi_wlast <= '0' when m_data_write_connected(4)='0' else m_axi_wlast(4);
ip_m_axi_wvalid <= '0' when m_data_write_connected(0)='0' else m_axi_wvalid(0);
cpuid_gpio_m_axi_wvalid <= '0' when m_data_write_connected(1)='0' else m_axi_wvalid(1);
int_m_axi_wvalid <= '0' when m_data_write_connected(2)='0' else m_axi_wvalid(2);
signal_m_axi_wvalid <= '0' when m_data_write_connected(3)='0' else m_axi_wvalid(3);
timer_m_axi_wvalid <= '0' when m_data_write_connected(4)='0' else m_axi_wvalid(4);
ip_m_axi_bready <= '0' when m_response_write_connected(0)='0' else m_axi_bready(0);
cpuid_gpio_m_axi_bready <= '0' when m_response_write_connected(1)='0' else m_axi_bready(1);
int_m_axi_bready <= '0' when m_response_write_connected(2)='0' else m_axi_bready(2);
signal_m_axi_bready <= '0' when m_response_write_connected(3)='0' else m_axi_bready(3);
timer_m_axi_bready <= '0' when m_response_write_connected(4)='0' else m_axi_bready(4);
ip_m_axi_arid <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arid((1+0)*axi_master_id_width-1 downto 0*axi_master_id_width);
cpuid_gpio_m_axi_arid <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arid((1+1)*axi_master_id_width-1 downto 1*axi_master_id_width);
int_m_axi_arid <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arid((1+2)*axi_master_id_width-1 downto 2*axi_master_id_width);
signal_m_axi_arid <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arid((1+3)*axi_master_id_width-1 downto 3*axi_master_id_width);
timer_m_axi_arid <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arid((1+4)*axi_master_id_width-1 downto 4*axi_master_id_width);
ip_m_axi_araddr <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_araddr((1+0)*axi_address_width-1 downto 0*axi_address_width);
cpuid_gpio_m_axi_araddr <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_araddr((1+1)*axi_address_width-1 downto 1*axi_address_width);
int_m_axi_araddr <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_araddr((1+2)*axi_address_width-1 downto 2*axi_address_width);
signal_m_axi_araddr <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_araddr((1+3)*axi_address_width-1 downto 3*axi_address_width);
timer_m_axi_araddr <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_araddr((1+4)*axi_address_width-1 downto 4*axi_address_width);
ip_m_axi_arlen <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arlen((1+0)*8-1 downto 0*8);
cpuid_gpio_m_axi_arlen <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arlen((1+1)*8-1 downto 1*8);
int_m_axi_arlen <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arlen((1+2)*8-1 downto 2*8);
signal_m_axi_arlen <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arlen((1+3)*8-1 downto 3*8);
timer_m_axi_arlen <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arlen((1+4)*8-1 downto 4*8);
ip_m_axi_arsize <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arsize((1+0)*3-1 downto 0*3);
cpuid_gpio_m_axi_arsize <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arsize((1+1)*3-1 downto 1*3);
int_m_axi_arsize <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arsize((1+2)*3-1 downto 2*3);
signal_m_axi_arsize <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arsize((1+3)*3-1 downto 3*3);
timer_m_axi_arsize <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arsize((1+4)*3-1 downto 4*3);
ip_m_axi_arburst <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arburst((1+0)*2-1 downto 0*2);
cpuid_gpio_m_axi_arburst <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arburst((1+1)*2-1 downto 1*2);
int_m_axi_arburst <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arburst((1+2)*2-1 downto 2*2);
signal_m_axi_arburst <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arburst((1+3)*2-1 downto 3*2);
timer_m_axi_arburst <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arburst((1+4)*2-1 downto 4*2);
ip_m_axi_arlock <= '0' when m_address_read_connected(0)='0' else m_axi_arlock(0);
cpuid_gpio_m_axi_arlock <= '0' when m_address_read_connected(1)='0' else m_axi_arlock(1);
int_m_axi_arlock <= '0' when m_address_read_connected(2)='0' else m_axi_arlock(2);
signal_m_axi_arlock <= '0' when m_address_read_connected(3)='0' else m_axi_arlock(3);
timer_m_axi_arlock <= '0' when m_address_read_connected(4)='0' else m_axi_arlock(4);
ip_m_axi_arcache <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arcache((1+0)*4-1 downto 0*4);
cpuid_gpio_m_axi_arcache <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arcache((1+1)*4-1 downto 1*4);
int_m_axi_arcache <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arcache((1+2)*4-1 downto 2*4);
signal_m_axi_arcache <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arcache((1+3)*4-1 downto 3*4);
timer_m_axi_arcache <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arcache((1+4)*4-1 downto 4*4);
ip_m_axi_arprot <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arprot((1+0)*3-1 downto 0*3);
cpuid_gpio_m_axi_arprot <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arprot((1+1)*3-1 downto 1*3);
int_m_axi_arprot <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arprot((1+2)*3-1 downto 2*3);
signal_m_axi_arprot <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arprot((1+3)*3-1 downto 3*3);
timer_m_axi_arprot <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arprot((1+4)*3-1 downto 4*3);
ip_m_axi_arqos <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arqos((1+0)*4-1 downto 0*4);
cpuid_gpio_m_axi_arqos <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arqos((1+1)*4-1 downto 1*4);
int_m_axi_arqos <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arqos((1+2)*4-1 downto 2*4);
signal_m_axi_arqos <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arqos((1+3)*4-1 downto 3*4);
timer_m_axi_arqos <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arqos((1+4)*4-1 downto 4*4);
ip_m_axi_arregion <= (others=>'0') when m_address_read_connected(0)='0' else m_axi_arregion((1+0)*4-1 downto 0*4);
cpuid_gpio_m_axi_arregion <= (others=>'0') when m_address_read_connected(1)='0' else m_axi_arregion((1+1)*4-1 downto 1*4);
int_m_axi_arregion <= (others=>'0') when m_address_read_connected(2)='0' else m_axi_arregion((1+2)*4-1 downto 2*4);
signal_m_axi_arregion <= (others=>'0') when m_address_read_connected(3)='0' else m_axi_arregion((1+3)*4-1 downto 3*4);
timer_m_axi_arregion <= (others=>'0') when m_address_read_connected(4)='0' else m_axi_arregion((1+4)*4-1 downto 4*4);
ip_m_axi_arvalid <= '0' when m_address_read_connected(0)='0' else m_axi_arvalid(0);
cpuid_gpio_m_axi_arvalid <= '0' when m_address_read_connected(1)='0' else m_axi_arvalid(1);
int_m_axi_arvalid <= '0' when m_address_read_connected(2)='0' else m_axi_arvalid(2);
signal_m_axi_arvalid <= '0' when m_address_read_connected(3)='0' else m_axi_arvalid(3);
timer_m_axi_arvalid <= '0' when m_address_read_connected(4)='0' else m_axi_arvalid(4);
ip_m_axi_rready <= '0' when m_data_read_connected(0)='0' else m_axi_rready(0);
cpuid_gpio_m_axi_rready <= '0' when m_data_read_connected(1)='0' else m_axi_rready(1);
int_m_axi_rready <= '0' when m_data_read_connected(2)='0' else m_axi_rready(2);
signal_m_axi_rready <= '0' when m_data_read_connected(3)='0' else m_axi_rready(3);
timer_m_axi_rready <= '0' when m_data_read_connected(4)='0' else m_axi_rready(4);
plasoc_crossbar_inst : plasoc_crossbar
generic map
(
axi_address_width => axi_address_width,
axi_data_width => axi_data_width,
axi_master_amount => axi_master_amount,
axi_slave_id_width => axi_slave_id_width,
axi_slave_amount => axi_slave_amount,
axi_master_base_address => axi_master_base_address,
axi_master_high_address => axi_master_high_address
)
port map
(
aclk => aclk,
aresetn => aresetn,
s_address_write_connected => s_address_write_connected,
s_data_write_connected => s_data_write_connected,
s_response_write_connected => s_response_write_connected,
s_address_read_connected => s_address_read_connected,
s_data_read_connected => s_data_read_connected,
m_address_write_connected => m_address_write_connected,
m_data_write_connected => m_data_write_connected,
m_response_write_connected => m_response_write_connected,
m_address_read_connected => m_address_read_connected,
m_data_read_connected => m_data_read_connected,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awqos => s_axi_awqos,
s_axi_awregion => s_axi_awregion,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arqos => s_axi_arqos,
s_axi_arregion => s_axi_arregion,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
m_axi_awid => m_axi_awid,
m_axi_awaddr => m_axi_awaddr,
m_axi_awlen => m_axi_awlen,
m_axi_awsize => m_axi_awsize,
m_axi_awburst => m_axi_awburst,
m_axi_awlock => m_axi_awlock,
m_axi_awcache => m_axi_awcache,
m_axi_awprot => m_axi_awprot,
m_axi_awqos => m_axi_awqos,
m_axi_awregion => m_axi_awregion,
m_axi_awvalid => m_axi_awvalid,
m_axi_awready => m_axi_awready,
m_axi_wdata => m_axi_wdata,
m_axi_wstrb => m_axi_wstrb,
m_axi_wlast => m_axi_wlast,
m_axi_wvalid => m_axi_wvalid,
m_axi_wready => m_axi_wready,
m_axi_bid => m_axi_bid,
m_axi_bresp => m_axi_bresp,
m_axi_bvalid => m_axi_bvalid,
m_axi_bready => m_axi_bready,
m_axi_arid => m_axi_arid,
m_axi_araddr => m_axi_araddr,
m_axi_arlen => m_axi_arlen,
m_axi_arsize => m_axi_arsize,
m_axi_arburst => m_axi_arburst,
m_axi_arlock => m_axi_arlock,
m_axi_arcache => m_axi_arcache,
m_axi_arprot => m_axi_arprot,
m_axi_arqos => m_axi_arqos,
m_axi_arregion => m_axi_arregion,
m_axi_arvalid => m_axi_arvalid,
m_axi_arready => m_axi_arready,
m_axi_rid => m_axi_rid,
m_axi_rdata => m_axi_rdata,
m_axi_rresp => m_axi_rresp,
m_axi_rlast => m_axi_rlast,
m_axi_rvalid => m_axi_rvalid,
m_axi_rready => m_axi_rready
);
end Behavioral;
|
mit
|
a868c06264eddc2dfc999655988e7daf
| 0.681033 | 2.494881 | false | false | false | false |
arthurTemporim/SD_SS
|
pre/7/projetos/projeto1/projeto1.vhd
| 1 | 706 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity projeto1 is
port(
clock : in std_logic;
direction, reset : in std_logic := '0';
enable : in std_logic := '1';
q : out std_logic_vector (3 downto 0)
);
end projeto1;
architecture Behavioral of projeto1 is
begin
process (clock, reset)
variable contagem : integer range 0 to 9;
begin
if (reset = '1') then
contagem := 0;
elsif (clock'event and clock = '1') then
if (enable = '1') then
if(direction = '1') then
contagem := contagem + 1;
else
contagem := contagem - 1;
end if;
end if;
end if;
q <= conv_std_logic_vector(contagem,4);
end process;
end Behavioral;
|
mit
|
dc8315ca7b0149d4c24c643c33445e99
| 0.630312 | 2.978903 | false | false | false | false |
andrewandrepowell/kernel-on-chip
|
hdl/projects/Nexys4/plasoc_interconnect_crossbar_wrap_pack.vhd
| 1 | 23,691 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
package plasoc_interconnect_crossbar_wrap_pack is
function clogb2(bit_depth : in integer ) return integer;
component plasoc_interconnect_crossbar_wrap is
generic
(
axi_address_width : integer := 32;
axi_data_width : integer := 32;
axi_slave_id_width : integer := 0;
axi_master_amount : integer := 7;
axi_slave_amount : integer := 3;
axi_master_base_address : std_logic_vector := X"20000000200400002003000020020000200100001000000000000000";
axi_master_high_address : std_logic_vector := X"2000ffff2004ffff2003ffff2002ffff2001ffff1fffffff0000ffff"
);
port
(
cpu_0_s_axi_awid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_0_s_axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
cpu_0_s_axi_awlen : in std_logic_vector(7 downto 0);
cpu_0_s_axi_awsize : in std_logic_vector(2 downto 0);
cpu_0_s_axi_awburst : in std_logic_vector(1 downto 0);
cpu_0_s_axi_awlock : in std_logic;
cpu_0_s_axi_awcache : in std_logic_vector(3 downto 0);
cpu_0_s_axi_awprot : in std_logic_vector(2 downto 0);
cpu_0_s_axi_awqos : in std_logic_vector(3 downto 0);
cpu_0_s_axi_awregion : in std_logic_vector(3 downto 0);
cpu_0_s_axi_awvalid : in std_logic;
cpu_0_s_axi_awready : out std_logic;
cpu_0_s_axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
cpu_0_s_axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
cpu_0_s_axi_wlast : in std_logic;
cpu_0_s_axi_wvalid : in std_logic;
cpu_0_s_axi_wready : out std_logic;
cpu_0_s_axi_bid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_0_s_axi_bresp : out std_logic_vector(1 downto 0);
cpu_0_s_axi_bvalid : out std_logic;
cpu_0_s_axi_bready : in std_logic;
cpu_0_s_axi_arid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_0_s_axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
cpu_0_s_axi_arlen : in std_logic_vector(7 downto 0);
cpu_0_s_axi_arsize : in std_logic_vector(2 downto 0);
cpu_0_s_axi_arburst : in std_logic_vector(1 downto 0);
cpu_0_s_axi_arlock : in std_logic;
cpu_0_s_axi_arcache : in std_logic_vector(3 downto 0);
cpu_0_s_axi_arprot : in std_logic_vector(2 downto 0);
cpu_0_s_axi_arqos : in std_logic_vector(3 downto 0);
cpu_0_s_axi_arregion : in std_logic_vector(3 downto 0);
cpu_0_s_axi_arvalid : in std_logic;
cpu_0_s_axi_arready : out std_logic;
cpu_0_s_axi_rid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_0_s_axi_rdata : out std_logic_vector(axi_data_width-1 downto 0);
cpu_0_s_axi_rresp : out std_logic_vector(1 downto 0);
cpu_0_s_axi_rlast : out std_logic;
cpu_0_s_axi_rvalid : out std_logic;
cpu_0_s_axi_rready : in std_logic;
cpu_1_s_axi_awid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_1_s_axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
cpu_1_s_axi_awlen : in std_logic_vector(7 downto 0);
cpu_1_s_axi_awsize : in std_logic_vector(2 downto 0);
cpu_1_s_axi_awburst : in std_logic_vector(1 downto 0);
cpu_1_s_axi_awlock : in std_logic;
cpu_1_s_axi_awcache : in std_logic_vector(3 downto 0);
cpu_1_s_axi_awprot : in std_logic_vector(2 downto 0);
cpu_1_s_axi_awqos : in std_logic_vector(3 downto 0);
cpu_1_s_axi_awregion : in std_logic_vector(3 downto 0);
cpu_1_s_axi_awvalid : in std_logic;
cpu_1_s_axi_awready : out std_logic;
cpu_1_s_axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
cpu_1_s_axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
cpu_1_s_axi_wlast : in std_logic;
cpu_1_s_axi_wvalid : in std_logic;
cpu_1_s_axi_wready : out std_logic;
cpu_1_s_axi_bid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_1_s_axi_bresp : out std_logic_vector(1 downto 0);
cpu_1_s_axi_bvalid : out std_logic;
cpu_1_s_axi_bready : in std_logic;
cpu_1_s_axi_arid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_1_s_axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
cpu_1_s_axi_arlen : in std_logic_vector(7 downto 0);
cpu_1_s_axi_arsize : in std_logic_vector(2 downto 0);
cpu_1_s_axi_arburst : in std_logic_vector(1 downto 0);
cpu_1_s_axi_arlock : in std_logic;
cpu_1_s_axi_arcache : in std_logic_vector(3 downto 0);
cpu_1_s_axi_arprot : in std_logic_vector(2 downto 0);
cpu_1_s_axi_arqos : in std_logic_vector(3 downto 0);
cpu_1_s_axi_arregion : in std_logic_vector(3 downto 0);
cpu_1_s_axi_arvalid : in std_logic;
cpu_1_s_axi_arready : out std_logic;
cpu_1_s_axi_rid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_1_s_axi_rdata : out std_logic_vector(axi_data_width-1 downto 0);
cpu_1_s_axi_rresp : out std_logic_vector(1 downto 0);
cpu_1_s_axi_rlast : out std_logic;
cpu_1_s_axi_rvalid : out std_logic;
cpu_1_s_axi_rready : in std_logic;
cpu_2_s_axi_awid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_2_s_axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
cpu_2_s_axi_awlen : in std_logic_vector(7 downto 0);
cpu_2_s_axi_awsize : in std_logic_vector(2 downto 0);
cpu_2_s_axi_awburst : in std_logic_vector(1 downto 0);
cpu_2_s_axi_awlock : in std_logic;
cpu_2_s_axi_awcache : in std_logic_vector(3 downto 0);
cpu_2_s_axi_awprot : in std_logic_vector(2 downto 0);
cpu_2_s_axi_awqos : in std_logic_vector(3 downto 0);
cpu_2_s_axi_awregion : in std_logic_vector(3 downto 0);
cpu_2_s_axi_awvalid : in std_logic;
cpu_2_s_axi_awready : out std_logic;
cpu_2_s_axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
cpu_2_s_axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
cpu_2_s_axi_wlast : in std_logic;
cpu_2_s_axi_wvalid : in std_logic;
cpu_2_s_axi_wready : out std_logic;
cpu_2_s_axi_bid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_2_s_axi_bresp : out std_logic_vector(1 downto 0);
cpu_2_s_axi_bvalid : out std_logic;
cpu_2_s_axi_bready : in std_logic;
cpu_2_s_axi_arid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_2_s_axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
cpu_2_s_axi_arlen : in std_logic_vector(7 downto 0);
cpu_2_s_axi_arsize : in std_logic_vector(2 downto 0);
cpu_2_s_axi_arburst : in std_logic_vector(1 downto 0);
cpu_2_s_axi_arlock : in std_logic;
cpu_2_s_axi_arcache : in std_logic_vector(3 downto 0);
cpu_2_s_axi_arprot : in std_logic_vector(2 downto 0);
cpu_2_s_axi_arqos : in std_logic_vector(3 downto 0);
cpu_2_s_axi_arregion : in std_logic_vector(3 downto 0);
cpu_2_s_axi_arvalid : in std_logic;
cpu_2_s_axi_arready : out std_logic;
cpu_2_s_axi_rid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_2_s_axi_rdata : out std_logic_vector(axi_data_width-1 downto 0);
cpu_2_s_axi_rresp : out std_logic_vector(1 downto 0);
cpu_2_s_axi_rlast : out std_logic;
cpu_2_s_axi_rvalid : out std_logic;
cpu_2_s_axi_rready : in std_logic;
boot_bram_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
boot_bram_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
boot_bram_m_axi_awlen : out std_logic_vector(7 downto 0);
boot_bram_m_axi_awsize : out std_logic_vector(2 downto 0);
boot_bram_m_axi_awburst : out std_logic_vector(1 downto 0);
boot_bram_m_axi_awlock : out std_logic;
boot_bram_m_axi_awcache : out std_logic_vector(3 downto 0);
boot_bram_m_axi_awprot : out std_logic_vector(2 downto 0);
boot_bram_m_axi_awqos : out std_logic_vector(3 downto 0);
boot_bram_m_axi_awregion : out std_logic_vector(3 downto 0);
boot_bram_m_axi_awvalid : out std_logic;
boot_bram_m_axi_awready : in std_logic;
boot_bram_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
boot_bram_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
boot_bram_m_axi_wlast : out std_logic;
boot_bram_m_axi_wvalid : out std_logic;
boot_bram_m_axi_wready : in std_logic;
boot_bram_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
boot_bram_m_axi_bresp : in std_logic_vector(1 downto 0);
boot_bram_m_axi_bvalid : in std_logic;
boot_bram_m_axi_bready : out std_logic;
boot_bram_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
boot_bram_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
boot_bram_m_axi_arlen : out std_logic_vector(7 downto 0);
boot_bram_m_axi_arsize : out std_logic_vector(2 downto 0);
boot_bram_m_axi_arburst : out std_logic_vector(1 downto 0);
boot_bram_m_axi_arlock : out std_logic;
boot_bram_m_axi_arcache : out std_logic_vector(3 downto 0);
boot_bram_m_axi_arprot : out std_logic_vector(2 downto 0);
boot_bram_m_axi_arqos : out std_logic_vector(3 downto 0);
boot_bram_m_axi_arregion : out std_logic_vector(3 downto 0);
boot_bram_m_axi_arvalid : out std_logic;
boot_bram_m_axi_arready : in std_logic;
boot_bram_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
boot_bram_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
boot_bram_m_axi_rresp : in std_logic_vector(1 downto 0);
boot_bram_m_axi_rlast : in std_logic;
boot_bram_m_axi_rvalid : in std_logic;
boot_bram_m_axi_rready : out std_logic;
ram_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ram_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
ram_m_axi_awlen : out std_logic_vector(7 downto 0);
ram_m_axi_awsize : out std_logic_vector(2 downto 0);
ram_m_axi_awburst : out std_logic_vector(1 downto 0);
ram_m_axi_awlock : out std_logic;
ram_m_axi_awcache : out std_logic_vector(3 downto 0);
ram_m_axi_awprot : out std_logic_vector(2 downto 0);
ram_m_axi_awqos : out std_logic_vector(3 downto 0);
ram_m_axi_awregion : out std_logic_vector(3 downto 0);
ram_m_axi_awvalid : out std_logic;
ram_m_axi_awready : in std_logic;
ram_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
ram_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
ram_m_axi_wlast : out std_logic;
ram_m_axi_wvalid : out std_logic;
ram_m_axi_wready : in std_logic;
ram_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ram_m_axi_bresp : in std_logic_vector(1 downto 0);
ram_m_axi_bvalid : in std_logic;
ram_m_axi_bready : out std_logic;
ram_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ram_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
ram_m_axi_arlen : out std_logic_vector(7 downto 0);
ram_m_axi_arsize : out std_logic_vector(2 downto 0);
ram_m_axi_arburst : out std_logic_vector(1 downto 0);
ram_m_axi_arlock : out std_logic;
ram_m_axi_arcache : out std_logic_vector(3 downto 0);
ram_m_axi_arprot : out std_logic_vector(2 downto 0);
ram_m_axi_arqos : out std_logic_vector(3 downto 0);
ram_m_axi_arregion : out std_logic_vector(3 downto 0);
ram_m_axi_arvalid : out std_logic;
ram_m_axi_arready : in std_logic;
ram_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ram_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
ram_m_axi_rresp : in std_logic_vector(1 downto 0);
ram_m_axi_rlast : in std_logic;
ram_m_axi_rvalid : in std_logic;
ram_m_axi_rready : out std_logic;
int_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
int_m_axi_awlen : out std_logic_vector(7 downto 0);
int_m_axi_awsize : out std_logic_vector(2 downto 0);
int_m_axi_awburst : out std_logic_vector(1 downto 0);
int_m_axi_awlock : out std_logic;
int_m_axi_awcache : out std_logic_vector(3 downto 0);
int_m_axi_awprot : out std_logic_vector(2 downto 0);
int_m_axi_awqos : out std_logic_vector(3 downto 0);
int_m_axi_awregion : out std_logic_vector(3 downto 0);
int_m_axi_awvalid : out std_logic;
int_m_axi_awready : in std_logic;
int_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
int_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
int_m_axi_wlast : out std_logic;
int_m_axi_wvalid : out std_logic;
int_m_axi_wready : in std_logic;
int_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_bresp : in std_logic_vector(1 downto 0);
int_m_axi_bvalid : in std_logic;
int_m_axi_bready : out std_logic;
int_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
int_m_axi_arlen : out std_logic_vector(7 downto 0);
int_m_axi_arsize : out std_logic_vector(2 downto 0);
int_m_axi_arburst : out std_logic_vector(1 downto 0);
int_m_axi_arlock : out std_logic;
int_m_axi_arcache : out std_logic_vector(3 downto 0);
int_m_axi_arprot : out std_logic_vector(2 downto 0);
int_m_axi_arqos : out std_logic_vector(3 downto 0);
int_m_axi_arregion : out std_logic_vector(3 downto 0);
int_m_axi_arvalid : out std_logic;
int_m_axi_arready : in std_logic;
int_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
int_m_axi_rresp : in std_logic_vector(1 downto 0);
int_m_axi_rlast : in std_logic;
int_m_axi_rvalid : in std_logic;
int_m_axi_rready : out std_logic;
timer_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
timer_m_axi_awlen : out std_logic_vector(7 downto 0);
timer_m_axi_awsize : out std_logic_vector(2 downto 0);
timer_m_axi_awburst : out std_logic_vector(1 downto 0);
timer_m_axi_awlock : out std_logic;
timer_m_axi_awcache : out std_logic_vector(3 downto 0);
timer_m_axi_awprot : out std_logic_vector(2 downto 0);
timer_m_axi_awqos : out std_logic_vector(3 downto 0);
timer_m_axi_awregion : out std_logic_vector(3 downto 0);
timer_m_axi_awvalid : out std_logic;
timer_m_axi_awready : in std_logic;
timer_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
timer_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
timer_m_axi_wlast : out std_logic;
timer_m_axi_wvalid : out std_logic;
timer_m_axi_wready : in std_logic;
timer_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_bresp : in std_logic_vector(1 downto 0);
timer_m_axi_bvalid : in std_logic;
timer_m_axi_bready : out std_logic;
timer_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
timer_m_axi_arlen : out std_logic_vector(7 downto 0);
timer_m_axi_arsize : out std_logic_vector(2 downto 0);
timer_m_axi_arburst : out std_logic_vector(1 downto 0);
timer_m_axi_arlock : out std_logic;
timer_m_axi_arcache : out std_logic_vector(3 downto 0);
timer_m_axi_arprot : out std_logic_vector(2 downto 0);
timer_m_axi_arqos : out std_logic_vector(3 downto 0);
timer_m_axi_arregion : out std_logic_vector(3 downto 0);
timer_m_axi_arvalid : out std_logic;
timer_m_axi_arready : in std_logic;
timer_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
timer_m_axi_rresp : in std_logic_vector(1 downto 0);
timer_m_axi_rlast : in std_logic;
timer_m_axi_rvalid : in std_logic;
timer_m_axi_rready : out std_logic;
gpio_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
gpio_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
gpio_m_axi_awlen : out std_logic_vector(7 downto 0);
gpio_m_axi_awsize : out std_logic_vector(2 downto 0);
gpio_m_axi_awburst : out std_logic_vector(1 downto 0);
gpio_m_axi_awlock : out std_logic;
gpio_m_axi_awcache : out std_logic_vector(3 downto 0);
gpio_m_axi_awprot : out std_logic_vector(2 downto 0);
gpio_m_axi_awqos : out std_logic_vector(3 downto 0);
gpio_m_axi_awregion : out std_logic_vector(3 downto 0);
gpio_m_axi_awvalid : out std_logic;
gpio_m_axi_awready : in std_logic;
gpio_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
gpio_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
gpio_m_axi_wlast : out std_logic;
gpio_m_axi_wvalid : out std_logic;
gpio_m_axi_wready : in std_logic;
gpio_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
gpio_m_axi_bresp : in std_logic_vector(1 downto 0);
gpio_m_axi_bvalid : in std_logic;
gpio_m_axi_bready : out std_logic;
gpio_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
gpio_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
gpio_m_axi_arlen : out std_logic_vector(7 downto 0);
gpio_m_axi_arsize : out std_logic_vector(2 downto 0);
gpio_m_axi_arburst : out std_logic_vector(1 downto 0);
gpio_m_axi_arlock : out std_logic;
gpio_m_axi_arcache : out std_logic_vector(3 downto 0);
gpio_m_axi_arprot : out std_logic_vector(2 downto 0);
gpio_m_axi_arqos : out std_logic_vector(3 downto 0);
gpio_m_axi_arregion : out std_logic_vector(3 downto 0);
gpio_m_axi_arvalid : out std_logic;
gpio_m_axi_arready : in std_logic;
gpio_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
gpio_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
gpio_m_axi_rresp : in std_logic_vector(1 downto 0);
gpio_m_axi_rlast : in std_logic;
gpio_m_axi_rvalid : in std_logic;
gpio_m_axi_rready : out std_logic;
uart_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
uart_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
uart_m_axi_awlen : out std_logic_vector(7 downto 0);
uart_m_axi_awsize : out std_logic_vector(2 downto 0);
uart_m_axi_awburst : out std_logic_vector(1 downto 0);
uart_m_axi_awlock : out std_logic;
uart_m_axi_awcache : out std_logic_vector(3 downto 0);
uart_m_axi_awprot : out std_logic_vector(2 downto 0);
uart_m_axi_awqos : out std_logic_vector(3 downto 0);
uart_m_axi_awregion : out std_logic_vector(3 downto 0);
uart_m_axi_awvalid : out std_logic;
uart_m_axi_awready : in std_logic;
uart_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
uart_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
uart_m_axi_wlast : out std_logic;
uart_m_axi_wvalid : out std_logic;
uart_m_axi_wready : in std_logic;
uart_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
uart_m_axi_bresp : in std_logic_vector(1 downto 0);
uart_m_axi_bvalid : in std_logic;
uart_m_axi_bready : out std_logic;
uart_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
uart_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
uart_m_axi_arlen : out std_logic_vector(7 downto 0);
uart_m_axi_arsize : out std_logic_vector(2 downto 0);
uart_m_axi_arburst : out std_logic_vector(1 downto 0);
uart_m_axi_arlock : out std_logic;
uart_m_axi_arcache : out std_logic_vector(3 downto 0);
uart_m_axi_arprot : out std_logic_vector(2 downto 0);
uart_m_axi_arqos : out std_logic_vector(3 downto 0);
uart_m_axi_arregion : out std_logic_vector(3 downto 0);
uart_m_axi_arvalid : out std_logic;
uart_m_axi_arready : in std_logic;
uart_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
uart_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
uart_m_axi_rresp : in std_logic_vector(1 downto 0);
uart_m_axi_rlast : in std_logic;
uart_m_axi_rvalid : in std_logic;
uart_m_axi_rready : out std_logic;
lock_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
lock_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
lock_m_axi_awlen : out std_logic_vector(7 downto 0);
lock_m_axi_awsize : out std_logic_vector(2 downto 0);
lock_m_axi_awburst : out std_logic_vector(1 downto 0);
lock_m_axi_awlock : out std_logic;
lock_m_axi_awcache : out std_logic_vector(3 downto 0);
lock_m_axi_awprot : out std_logic_vector(2 downto 0);
lock_m_axi_awqos : out std_logic_vector(3 downto 0);
lock_m_axi_awregion : out std_logic_vector(3 downto 0);
lock_m_axi_awvalid : out std_logic;
lock_m_axi_awready : in std_logic;
lock_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
lock_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
lock_m_axi_wlast : out std_logic;
lock_m_axi_wvalid : out std_logic;
lock_m_axi_wready : in std_logic;
lock_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
lock_m_axi_bresp : in std_logic_vector(1 downto 0);
lock_m_axi_bvalid : in std_logic;
lock_m_axi_bready : out std_logic;
lock_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
lock_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
lock_m_axi_arlen : out std_logic_vector(7 downto 0);
lock_m_axi_arsize : out std_logic_vector(2 downto 0);
lock_m_axi_arburst : out std_logic_vector(1 downto 0);
lock_m_axi_arlock : out std_logic;
lock_m_axi_arcache : out std_logic_vector(3 downto 0);
lock_m_axi_arprot : out std_logic_vector(2 downto 0);
lock_m_axi_arqos : out std_logic_vector(3 downto 0);
lock_m_axi_arregion : out std_logic_vector(3 downto 0);
lock_m_axi_arvalid : out std_logic;
lock_m_axi_arready : in std_logic;
lock_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
lock_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
lock_m_axi_rresp : in std_logic_vector(1 downto 0);
lock_m_axi_rlast : in std_logic;
lock_m_axi_rvalid : in std_logic;
lock_m_axi_rready : out std_logic;
aclk : in std_logic;
aresetn : in std_logic
);
end component;
end;
package body plasoc_interconnect_crossbar_wrap_pack is
function flogb2(bit_depth : in natural ) return integer is
variable result : integer := 0;
variable bit_depth_buff : integer := bit_depth;
begin
while bit_depth_buff>1 loop
bit_depth_buff := bit_depth_buff/2;
result := result+1;
end loop;
return result;
end function flogb2;
function clogb2 (bit_depth : in natural ) return natural is
variable result : integer := 0;
begin
result := flogb2(bit_depth);
if (bit_depth > (2**result)) then
return(result + 1);
else
return result;
end if;
end function clogb2;
end;
|
mit
|
6c75bd433fb09ec0fbd6869aebb621e0
| 0.672154 | 2.424376 | false | false | false | false |
rinatzakirov/vhdl
|
testbench_mm_master.vhd
| 1 | 2,225 |
library work;
use work.util.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
USE IEEE.math_real.ALL;
package testbench_mm_master_pkg is
constant do_idle: integer := 0;
constant do_write: integer := 1;
--constant do_read: integer := 2;
constant do_goto: integer := 3;
type instruction_t is array(integer range <>) of integer;
type instructions_t is array(positive range <>) of instruction_t(0 to 2);
end package;
use work.testbench_mm_master_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
USE IEEE.math_real.ALL;
library work;
use work.util.all;
entity testbench_mm_master is
generic
(
instructions: instructions_t
);
port
(
clk: in std_logic;
rst: in std_logic;
mm_write : out std_logic ;
mm_waitrequest: in std_logic ;
mm_address : out std_logic_vector(31 downto 0);
mm_writedata : out std_logic_vector(31 downto 0)
);
end entity;
architecture syn of testbench_mm_master is
type state_t is (s_idle, s_write);
signal state: state_t;
begin
process (clk)
variable pc: integer;
begin
if rising_edge(clk) then
if rst = '1' then
pc := 1;
state <= s_idle;
mm_write <= '0';
mm_address <= (others => '0');
mm_writedata <= (others => '0');
else
case state is
when s_idle =>
if instructions(pc)(0) = do_write then
state <= s_write;
mm_write <= '1';
mm_address <= toSlv(instructions(pc)(1), 32);
mm_writedata <= toSlv(instructions(pc)(2), 32);
pc := pc + 1;
end if;
if instructions(pc)(0) = do_goto then
pc := instructions(pc)(1);
end if;
when s_write =>
if mm_waitrequest = '0' then
state <= s_idle;
mm_write <= '0';
mm_address <= (others => '0');
mm_writedata <= (others => '0');
end if;
end case;
end if;
end if;
end process;
end architecture;
|
lgpl-2.1
|
ee4613c63e03783f9c8dcaabe51d57fe
| 0.529438 | 3.623779 | false | false | false | false |
wyvernSemi/vproc
|
f_vproc_pkg.vhd
| 1 | 2,842 |
-- =============================================================
--
-- Copyright (c) 2021 Simon Southwell. All rights reserved.
--
-- Date: 4th May 2021
--
-- This file is part of the VProc package.
--
-- VProc is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- VProc is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with VProc. If not, see <http://www.gnu.org/licenses/>.
--
-- $Id: f_vproc_pkg.vhd,v 1.2 2021/05/05 08:07:40 simon Exp $
-- $Source: /home/simon/CVS/src/HDL/VProc/f_vproc_pkg.vhd,v $
--
-- =============================================================
-- altera vhdl_input_version vhdl_2008
package vproc_pkg is
procedure VInit (
node : in integer
);
attribute foreign of VInit : procedure is "VInit VProc.so";
procedure VSched (
node : in integer;
Interrupt : in integer;
VPDataIn : in integer;
VPDataOut : out integer;
VPAddr : out integer;
VPRw : out integer;
VPTicks : out integer
);
attribute foreign of VSched : procedure is "VSched VProc.so";
procedure VProcUser (
node : in integer;
value : in integer
);
attribute foreign of VProcUser : procedure is "VProcUser VProc.so";
procedure VAccess (
node : in integer;
idx : in integer;
VPDataIn : in integer;
VPDataOut : out integer
);
attribute foreign of VAccess : procedure is "VAccess VProc.so";
end;
package body vproc_pkg is
procedure VInit (
node : in integer
) is
begin
report "ERROR: foreign subprogram out_params not called";
end;
procedure VSched (
node : in integer;
Interrupt : in integer;
VPDataIn : in integer;
VPDataOut : out integer;
VPAddr : out integer;
VPRw : out integer;
VPTicks : out integer
) is
begin
report "ERROR: foreign subprogram out_params not called";
end;
procedure VProcUser (
node : in integer;
value : in integer
) is
begin
report "ERROR: foreign subprogram out_params not called";
end;
procedure VAccess (
node : in integer;
idx : in integer;
VPDataIn : in integer;
VPDataOut : out integer
) is
begin
report "ERROR: foreign subprogram out_params not called";
end;
end;
|
gpl-3.0
|
dc619bf68d756d9fcd9b182ff12b339a
| 0.595004 | 3.903846 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/flashyLights/ipcore_dir/memmory/simulation/memmory_tb.vhd
| 1 | 4,349 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: memmory_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY memmory_tb IS
END ENTITY;
ARCHITECTURE memmory_tb_ARCH OF memmory_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
memmory_synth_inst:ENTITY work.memmory_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
gpl-3.0
|
9236474b323ffe4bdd3af5b02d5adf60
| 0.619913 | 4.676344 | false | false | false | false |
phil91stud/protocol_hdl
|
I2C_master/hdl/i2c_master.vhd
| 1 | 2,737 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity i2c_master is
generic(
clock_freq : natural := 50000000; -- 50MHz
bus_freq : natural := 200000 -- 200 kHz
);
port(
clock_50 : in std_logic;
slave_addr : in std_logic_vector(7 downto 0);
rw_addr : in std_logic_vector(7 downto 0);
rnw : in std_logic; -- 1 when read 0 when write
tx_data : in std_logic_vector(7 downto 0);
rx_data : out std_logic_vector(7 downto 0);
ack_err : out std_logic;
tx_start : in std_logic;
tx_done : out std_logic;
-- bus interface
sda : inout std_logic;
sck : out std_logic
);
end entity i2c_master;
architecture behavioral of i2c_master is
constant divider : integer := (clock_freq/bus_freq);
type sm_t is (idle, start, dev_addr, ack, d_addr, dread, dwrite, stop, done);
signal state : sm_t := idle;
signal prev_state : sm_t := idle;
signal counter : integer range 0 to divider := 0;
signal serial_clk : std_logic := '0';
signal rx_reg : std_logic_vector(7 downto 0);
signal tx_reg : std_logic_vector(7 downto 0);
begin
clock_gen:
process(clock_50)
begin
if clock_50'event and clock_50='1' then
if state /= idle and state /= done then
counter <= counter + 1;
if counter = divider then
serial_clk <= not serial_clk;
end if;
end if;
end if;
end process clock_gen;
statemachine:
process(serial_clk, rw_addr, slave_addr, rnw, tx_data, tx_start, sda)
begin
if serial_clk'event and serial_clk='1' then
case(state) is
when idle => -- idle, no transmissions
sda <= '1';
sck <= '1';
tx_done <= '0';
ack_err <= '0';
if tx_start = '1' then
prev_state <= idle;
state <= start;
end if;
when start => -- start condition
sda <= '1';
sck <= '0';
prev_state <= start;
state <= dev_addr;
when dev_addr => -- transmit i2c slave address
-- todo
when ack => -- check acknowledge bit
sda <= 'Z';
-- todo
prev_state <= ack;
if prev_state = dev_addr then state <= d_addr;
elsif prev_state = d_addr and rnw = '1' then state <= dread;
elsif prev_state = d_addr and rnw = '0' then state <= dwrite;
elsif prev_state = dread or prev_state = dwrite then state <= stop;
end if;
when d_addr => -- transmit requested register
prev_state <= d_addr;
state <= ack;
when dread => -- read from slave
prev_state <= dread;
state <= ack;
when dwrite => -- write to slave
prev_state <= dwrite;
state <= ack;
when stop => -- transmit stop condition
sda <= '1';
sck <= '0';
prev_state <= stop;
state <= done;
when done => -- go to idle
prev_state <= done;
state <= idle;
tx_done <= '1';
rx_data <= rx_reg;
end case;
end if;
end process statemachine;
end architecture;
|
gpl-2.0
|
58faf35319633c365d88bfa61c82d827
| 0.623676 | 2.761857 | false | false | false | false |
arthurTemporim/SD_SS
|
pre/6/projetos/projeto1/projeto1.vhd
| 1 | 440 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity projeto1 is
port (
siw : in std_logic_vector (7 downto 0) := "00000000";
led : out std_logic_vector (7 downto 0)
);
end projeto1;
architecture Behavioral of projeto1 is
begin
led(0) <= (not siw(0));
led(1) <= siw(1) and (not siw(2));
led(2) <= siw(1) or siw(3);
led(3) <= siw(2) and siw(3);
led(4) <= siw(4);
led(5) <= siw(5);
led(6) <= siw(6);
led(7) <= siw(7);
end Behavioral;
|
mit
|
f19bd003ccde6eaa518ee8ae3e060005
| 0.611364 | 2.391304 | false | false | false | false |
JosiCoder/CtLab
|
FPGA/Common/Source/Toggler.vhd
| 1 | 3,309 |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Creates a signal that toggles at every rising edge of an input signal. This
-- can be used before passing a signal (e.g. of short pulses) to a different
-- clock domain. A dual edge detector can be used in the destination clock domain
-- to reconstruct the signal.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Toggler is
port
(
-- The system clock.
clk: in std_logic;
-- The signal to create a toggled signal from.
sigin: in std_logic;
-- The created toggled signal.
toggled_sigout: out std_logic
);
end entity;
architecture stdarch of Toggler is
type reg_type is record
sigout: std_logic;
end record;
signal state, next_state: reg_type := (sigout => '0');
signal sigin_edge: std_logic := '0';
begin
--------------------------------------------------------------------------------
-- Instantiate components.
--------------------------------------------------------------------------------
detect_edges_of_sigin: entity work.EdgeDetector
port map
(
clk => clk,
sigin => sigin,
edge => sigin_edge
);
--------------------------------------------------------------------------------
-- State register.
--------------------------------------------------------------------------------
state_register: process is
begin
wait until rising_edge(clk);
state <= next_state;
end process;
--------------------------------------------------------------------------------
-- Next state logic.
--------------------------------------------------------------------------------
next_state_logic: process(state, sigin_edge) is
begin
-- Defaults.
next_state <= state;
if (sigin_edge = '1') then
next_state.sigout <= not state.sigout;
end if;
end process;
--------------------------------------------------------------------------------
-- Output logic.
--------------------------------------------------------------------------------
toggled_sigout <= state.sigout;
end architecture;
|
gpl-3.0
|
77264d364f97b97e25493a928bf925ce
| 0.430039 | 5.705172 | false | false | false | false |
rinatzakirov/vhdl
|
TwoClockStreamFifo.vhdl
| 1 | 4,671 |
------------------------------------------------------------------------
-- TwoClockStreamFifo
--
-- Copyright (c) 2014-2014 Rinat Zakirov
-- SPDX-License-Identifier: BSL-1.0
--
-- Configurable buffering between an input and output stream.
-- See vhdl-extras simple_fifo for additional documentation.
-- SYNC_READ = true uses block ram
-- SYNC_READ = false uses dist ram
------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity TwoClockStreamFifo is
generic(
MEM_SIZE : positive
);
port(
-- input bus
in_clk : in std_ulogic;
in_rst : in std_ulogic;
in_data : in std_ulogic_vector;
in_valid : in std_ulogic;
in_ready : out std_ulogic;
-- output bus
out_clk : in std_ulogic;
out_rst : in std_ulogic;
out_data : out std_ulogic_vector;
out_valid : out std_ulogic;
out_ready : in std_ulogic;
--space and availability
empty : out std_ulogic; -- This is a workaround to avoid making this fifo be an appropriate fifo which asserts valid when it has data
-- almost_empty_thresh is a little tricky:
-- Values below 3 should not be used here because of the additional buffering on the output stage
-- It is assumed that by the time the fill level reaches the required amount, the output clock has done at least a couple of cycles for the output to
-- have been able to read one item and put it into the store. If that didn't happen, the threshold would reach on one too little number of items.
-- So, it if generally safe if the threshold is not too small compared to the speed at which the data is filling as seen by the output clock
almost_empty_thresh : in natural range 3 to MEM_SIZE-1 := 3;
almost_full_thresh : in natural range 0 to MEM_SIZE-1 := 1;
almost_empty : out std_ulogic;
almost_full : out std_ulogic
);
end entity TwoClockStreamFifo;
architecture rtl of TwoClockStreamFifo is
signal Empty_i : std_ulogic;
signal Full : std_ulogic;
signal We : std_ulogic;
signal Re : std_ulogic;
signal data_buf, fifo_rd_data: std_ulogic_vector(out_data'range);
signal data_buf_val: std_logic;
signal fifo_val: std_logic;
signal out_valid_i: std_logic;
signal almost_empty_thresh_minus_one: natural range 2 to MEM_SIZE-2;
begin
almost_empty_thresh_minus_one <= almost_empty_thresh - 1;
in_ready <= not Full;
We <= in_valid and not Full;
Empty <= Empty_i;
out_valid <= out_valid_i;
out_valid_i <= data_buf_val or fifo_val;
out_data <= data_buf when data_buf_val = '1' else fifo_rd_data;
Re <= (not Empty_i) when
(data_buf_val = '0' and fifo_val = '0') or
(data_buf_val = '0' and fifo_val = '1' and out_ready = '1') or
(data_buf_val = '1' and fifo_val = '0' and out_ready = '1')
else '0';
process (out_clk)
begin
if (rising_edge(out_clk)) then
fifo_val <= Re;
if (out_rst = '1') then
fifo_val <= '0';
data_buf_val <= '0';
else
if out_ready = '1' then
if data_buf_val = '1' then
if fifo_val = '1' then
data_buf <= fifo_rd_data;
else
data_buf_val <= '0';
end if;
end if;
else
if data_buf_val = '1' then
if fifo_val = '1' then
assert false report "BAD LOGIC" severity failure;
end if;
else
if fifo_val = '1' then
data_buf_val <= '1';
data_buf <= fifo_rd_data;
end if;
end if;
end if;
end if;
end if;
end process;
fifo: entity work.fifo
generic map (
RESET_ACTIVE_LEVEL => '1',
MEM_SIZE => MEM_SIZE,
SYNC_READ => true,
READ_AHEAD => false
)
port map (
Wr_Clock => in_clk,
Wr_Reset => in_rst,
Rd_Clock => out_clk,
Rd_Reset => out_rst,
We => We,
Wr_data => in_data,
Re => Re,
Rd_data => fifo_rd_data,
Empty => Empty_i,
Full => Full,
Almost_empty_thresh => almost_empty_thresh_minus_one,
Almost_full_thresh => almost_full_thresh,
Almost_empty => almost_empty,
Almost_full => almost_full
);
end architecture rtl;
|
lgpl-2.1
|
51e909d654b89523321a9be16c6c8c90
| 0.531578 | 3.882793 | false | false | false | false |
maijohnson/comp3601_blue_15s2
|
AudioController/EppCtrl.vhd
| 1 | 16,346 |
------------------------------------------------------------------------
-- EppCtrl.vhd -- Digilent Epp Interface Module
------------------------------------------------------------------------
-- Author : Mircea Dabacan
-- Copyright 2004 Digilent, Inc.
------------------------------------------------------------------------
-- Software version: Xilinx ISE 6.2.03i
-- WebPack
------------------------------------------------------------------------
-- This file contains the design for an EPP interface controller.
-- This configuration, in conjunction with a communication module,
-- (Digilent USB, Serial, Network or Parallel module) allows the user
-- to interface some other FPGA implemented "client" components
-- (Digilent Library components or user generated ones)
-- to a PC application program (a Digilent utility or user generated).
------------------------------------------------------------------------
-- Behavioral description
------------------------------------------------------------------------
-- All the Digilent communication modules above emulate an EPP interface
-- at the FPGA board connector pins, compatible to EppCtrl controller.
-- The controller performs the following functions:
-- - manages the EPP standard handshake
-- - implements the standard EPP Address Register
-- - provides the signals needed to read/write EPP Data Registers.
-- The "client" component(s) is (are) responsible to implement the
-- specific required data registers, as explained below:
-- - declare the data read and write registers;
-- - assign an Epp address for each.
-- A couple of read- respective write- registers can be
-- assigned to the same Epp address. Assign a unique address
-- to each register (couple) throughout all the
-- client components connected to the same EppCtrl.
-- The totality of assigned addresses builds the component
-- address range. If less the 256 (couples of) registers are
-- required, "mirror" or "alias" addresses can be used
-- (incomplete regEppAdrOut(7:0) decoding).
-- The mirror addresses are not allowed to overlap throughout
-- all the client components connected to the same EppCtrl.
-- - use the same clock signal for all data registers as well as
-- for EppCtrl component Write Data registers
-- - connect the inputs of all write registers to busEppOut(7:0)
-- - decode regEppAdrOut(7:0) to generate the CS signal for each
-- write register
-- - use ctlEppDwrOut as WE signal for all the write registers
-- Read Data registers
-- - connect the outputs of all read registers to busEppIn(7:0)
-- THROUGH A MUX
-- - use the regEppAdrOut(7:0) as MUX address lines.
-- - defines two types of Data Register access
-- - Register Transfer - reads or writes a client data register,
-- - no handshake to the client component.
-- - Process Launch - launches a client process and
-- - waits it to complete.
-- The client process is required to conform to the handshake
-- protocol described below.
-- A client data register transfer is also performed.
-- The client component decides to which type the current
-- Data Register Access belongs: a clock period (20ns for 50MHz
-- clock frequency) after ctlEppDwrOut becomes active,
-- EppCtrl samples the HandShakeReqIn input signal.
-- - if inactive, the current transfer cycle completes without a
-- handshake protocol.
-- - if active (HIGH), the current transfer cycle uses a
-- handshake protocol:
--
-- The Handshake protocol
-- - the busEppOut, ctlEppRdCycleOut and regEppAdrOut(7:0)
-- signals freeze
-- - (for a WRITE cycle, ctlEppDwrOut pulses LOW for
-- 1 CK period - the selected write register is set)
-- - the ctlEppStartOut signal is set active (HIGH)
-- - (for a READ cycle, client application places data on
-- busEppIn(7:0))
-- - the controller waits for the ctlEppDoneIn signal to
-- become active (HIGH)
-- - (for a READ cycle, the data transfer is performed 1 CK
-- period later)
-- - the ctlEppStartOut signal is set inactive (LOW)
-- - the controller waits for the ctlEppDoneIn signal to
-- become inactive (LOW)
-- - a new transfer cycle can begin (if required by the PC
-- application)
-- A client component can use the handshake protocol feature for
-- various purposes:
-- - blocking the EppCtrl at all:
-- - activate the HandShakeReqIn input signal
-- - wait for the ctlEppStartOut signal to become active.
-- - keep the ctlEppDoneIn signal inactive (LOW) for the
-- desired time (the Epp interface freezes - the PC
-- software could exit with a time-out error)
-- - activate the ctlEppDoneIn signal.
-- - wait for the ctlEppStartOut signal to become inactive.
-- - inactivate ctlEppDoneIn,
-- - continue its own action.
-- - blocking the EppCtrl cycles for a specific client component:
-- - activate the HandShakeReqIn input signal when the
-- regEppAdrOut(7:0) value belongs to the address range
-- assigned to the specific client component.
-- - wait for the ctlEppStartOut signal to become active.
-- - keep the ctlEppDoneIn signal inactive (LOW) for the
-- desired time (the Epp interface freezes - the PC
-- software could exit with a time-out error)
-- - activate the ctlEppDoneIn signal.
-- - wait for the ctlEppStartOut signal to become inactive.
-- - inactivate ctlEppDoneIn,
-- - continue its own action.
-- - enlarging the EppCtrl cycles for specific data register
-- transfer cycles:
-- - activate the HandShakeReqIn input signal when the
-- regEppAdrOut(7:0) value equals any Data Register address
-- that requires an internal process.
-- (ctlEppRdCycleOut signal can be used to discriminate
-- between read and write cycles; ctlEppDwrOut signal
-- cannot be used because it is not yet active when
-- HandshakeReqIn is sampled)
-- - wait for the ctlEppStartOut signal to become active.
-- - launch the appropriate process (based on the
-- regEppAdrOut(7:0) and ctlEppRdCycleOut values)
-- - keep the ctlEppDoneIn signal inactive (LOW) until the
-- process completes(the Epp interface freezes - the PC
-- software could exit with a time-out error)
-- - get ready for the current transfer cycle completion.
-- - activate the ctlEppDoneIn signal.
-- - wait for the ctlEppStartOut signal to become inactive.
-- - inactivate ctlEppDoneIn,
-- - continue its own action.
------------------------------------------------------------------------
-- Port definitions
------------------------------------------------------------------------
-- Epp bus signals
-- clk : in std_logic; -- system clock (50MHz)
-- EppAstb: in std_logic; -- Address strobe
-- EppDstb: in std_logic; -- Data strobe
-- EppWr : in std_logic; -- Port write signal
-- EppRst : in std_logic; -- Port reset signal
-- pint : out std_logic; -- Port interrupt request (not used)
-- EppDB : inout std_logic_vector(7 downto 0); -- port data bus
-- EppWait: out std_logic; -- Port wait signal
-- User signals
-- busEppOut: out std_logic_vector(7 downto 0); -- Data Output bus
-- busEppIn: in std_logic_vector(7 downto 0); -- Data Input bus
-- ctlEppDwrOut: out std_logic; -- Data Write pulse
-- ctlEppRdCycleOut: inout std_logic; -- Indicates a READ Epp cycle
-- regEppAdrOut: inout std_logic_vector(7 downto 0) := "00000000";
-- Epp Address Register content
-- HandShakeReqIn: in std_logic; -- User Handshake Request
-- ctlEppStartOut: out std_logic; -- Automatic process Start
-- ctlEppDoneIn: in std_logic -- Automatic process Done
------------------------------------------------------------------------
-- Revision History:
-- 10/21/2004(MirceaD): created
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity EppCtrl is
Port (
-- Epp-like bus signals
clk : in std_logic; -- system clock (50MHz)
EppAstb: in std_logic; -- Address strobe
EppDstb: in std_logic; -- Data strobe
EppWr : in std_logic; -- Port write signal
EppRst : in std_logic; -- Port reset signal
-- pint : out std_logic; -- Port interrupt request (not used)
EppDB : inout std_logic_vector(7 downto 0); -- port data bus
EppWait: out std_logic; -- Port wait signal
-- User signals
busEppOut: out std_logic_vector(7 downto 0); -- Data Output bus
busEppIn: in std_logic_vector(7 downto 0); -- Data Input bus
ctlEppDwrOut: out std_logic; -- Data Write pulse
ctlEppRdCycleOut: inout std_logic; -- Indicates a READ Epp cycle
regEppAdrOut: inout std_logic_vector(7 downto 0) := "00000000";
-- Epp Address Register content
HandShakeReqIn: in std_logic; -- User Handshake Request
ctlEppStartOut: out std_logic; -- Automatic process Start
ctlEppDoneIn: in std_logic -- Automatic process Done
);
end EppCtrl;
architecture Behavioral of EppCtrl is
------------------------------------------------------------------------
-- Constant and Signal Declarations
------------------------------------------------------------------------
-- The following constants define state codes for the EPP port interface
-- state machine.
-- The states are such a way assigned that each transition
-- changes a single state register bit (Grey code - like)
constant stEppReady : std_logic_vector(2 downto 0) := "000";
constant stEppStb : std_logic_vector(2 downto 0) := "010";
constant stEppRegTransf : std_logic_vector(2 downto 0) := "110";
constant stEppSetProc : std_logic_vector(2 downto 0) := "011";
constant stEppLaunchProc: std_logic_vector(2 downto 0) := "111";
constant stEppWaitProc : std_logic_vector(2 downto 0) := "101";
constant stEppDone : std_logic_vector(2 downto 0) := "100";
-- Epp state register and next state signal for the Epp FSM
signal stEppCur: std_logic_vector(2 downto 0) := stEppReady;
signal stEppNext: std_logic_vector(2 downto 0);
-- The attribute lines below prevent the ISE compiler to extract and
-- optimize the state machines.
-- WebPack 5.1 doesn't need them (the default value is NO)
-- WebPack 6.2 has the default value YES, so without these lines would
-- "optimize" the state machines.
-- Although the overall circuit would be optimized, the particular goal
-- of "glitch free output signals" may not be reached.
-- That is the reason of implementing the state machine as described in
-- the constant declarations above.
attribute fsm_extract : string;
attribute fsm_extract of stEppCur: signal is "no";
attribute fsm_extract of stEppNext: signal is "no";
attribute fsm_encoding : string;
attribute fsm_encoding of stEppCur: signal is "user";
attribute fsm_encoding of stEppNext: signal is "user";
attribute signal_encoding : string;
attribute signal_encoding of stEppCur: signal is "user";
attribute signal_encoding of stEppNext: signal is "user";
-- Signals used by Epp state machine
signal busEppInternal: std_logic_vector(7 downto 0);
-- signal ctlEppDir : std_logic;
signal ctlEppAwr : std_logic;
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
------------------------------------------------------------------------
-- Map basic status and control signals
------------------------------------------------------------------------
-- Epp signals
-- Port signals
-- Synchronized Epp inputs:
process(clk)
begin
if clk'event and clk='1' then
if stEppCur = stEppReady then
ctlEppRdCycleOut <= '0';
elsif stEppCur = stEppStb then
ctlEppRdCycleOut <= EppWr;
-- not equivalent to EppWr due to default state
end if;
end if;
end process;
busEppOut <= EppDB; -- name meaning change!!!
EppDB <=busEppInternal when (ctlEppRdCycleOut = '1') else "ZZZZZZZZ";
busEppInternal <= regEppAdrOut when EppAstb = '0' else busEppIn;
-- Epp State machine related signals
EppWait <= '1' when stEppCur = stEppDone else '0';
ctlEppAwr <= '1' when stEppCur = stEppRegTransf and
EppAstb = '0' and
EppWr = '0' else
'0';
ctlEppDwrOut <= '1' when (stEppCur = stEppRegTransf or
stEppCur = stEppSetProc)
and EppDstb = '0'
and EppWr = '0' else
'0';
ctlEppStartOut <= '1' when stEppCur = stEppLaunchProc else
'0';
------------------------------------------------------------------------
-- EPP Interface Control State Machine
------------------------------------------------------------------------
process (clk)
begin
if clk = '1' and clk'Event then
if EppRst = '0' then
stEppCur <= stEppReady;
else
stEppCur <= stEppNext;
end if;
end if;
end process;
process (stEppCur)
begin
case stEppCur is
-- Idle state waiting for the beginning of an EPP cycle
when stEppReady =>
if EppAstb = '0' or EppDstb = '0' then
-- Epp cycle recognized
stEppNext <= stEppStb;
else
-- Remain in ready state
stEppNext <= stEppReady;
end if;
when stEppStb =>
if EppDstb = '0' and HandShakeReqIn = '1' then
stEppNext <= stEppSetProc;
else
stEppNext <= stEppRegTransf;
end if;
-- Data or Address register transfer
when stEppRegTransf =>
stEppNext <= stEppDone;
-- Automatic Process
when stEppSetProc =>
stEppNext <= stEppLaunchProc;
when stEppLaunchProc =>
if ctlEppDoneIn = '0' then
stEppNext <= stEppLaunchProc;
else
stEppNext <= stEppWaitProc;
end if;
when stEppWaitProc =>
if ctlEppDoneIn = '1' then
stEppNext <= stEppWaitProc;
else
stEppNext <= stEppDone;
end if;
when stEppDone =>
if EppAstb = '0' or EppDstb = '0' then
stEppNext <= stEppDone;
else
stEppNext <= stEppReady;
end if;
-- Some unknown state
when others =>
stEppNext <= stEppReady;
end case;
end process;
-- EPP Address register
process (clk, ctlEppAwr)
begin
if clk = '1' and clk'Event then
if ctlEppAwr = '1' then
regEppAdrOut <= EppDB;
end if;
end if;
end process;
end Behavioral;
|
mit
|
47e7d45989308ebc9c567100c4fd6d54
| 0.551389 | 4.975951 | false | false | false | false |
JosiCoder/CtLab
|
FPGA/FPGA SigGen/Source/ModulatedGenerator.vhd
| 1 | 11,080 |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Provides a set of generators that create periodic signals (e.g. sine, square,
-- and sawtooth) and that can modulate each other. The generators´ current phases
-- are also available.
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.FunctionGenerator_Declarations.all;
use work.ModulatedGenerator_Declarations.all;
entity ModulatedGenerator is
generic
(
-- The number of signal generators to create.
number_of_generators: natural := 2;
-- The width of the phase values.
phase_width: natural := 32;
-- The width of the phase values of the waveform lookup table (must not
-- exceed phase_width).
lookup_table_phase_width: natural := 12;
-- The width of the level values.
level_width: natural := 16;
-- The width of the sample values.
sample_width: natural := 16
);
port
(
-- The system clock.
clk: in std_logic;
-- For each generator, the configuration (e.g. modulation source or waveforms).
configs: in modulated_generator_config_vector(number_of_generators-1 downto 0);
-- For each generator, the increment to be added to the phase accumulator
-- in each clock cycle.
phase_increments: in modulated_generator_phase_vector(number_of_generators-1 downto 0);
-- For each generator, the phase value to be added to the current phase value.
phase_shifts: in modulated_generator_phase_vector(number_of_generators-1 downto 0);
-- For each generator, the level value used to attenuate the sample signal.
levels: in modulated_generator_level_vector(number_of_generators-1 downto 0);
-- For each generator, the current internal phase value. This is exactly
-- synchronized to sample. Its MSB is 0 for the first half of the period
-- and 1 for the second half.
phases: out modulated_generator_phase_vector(number_of_generators-1 downto 0);
-- For each generator, the sample value according to the current phase.
samples: out modulated_generator_sample_vector(number_of_generators-1 downto 0)
);
end entity;
architecture stdarch of ModulatedGenerator is
-- Registered and internal input signals.
type input_type is record
configs: modulated_generator_config_vector(number_of_generators-1 downto 0);
phase_increments: modulated_generator_phase_vector(number_of_generators-1 downto 0);
phase_shifts: modulated_generator_phase_vector(number_of_generators-1 downto 0);
levels: modulated_generator_level_vector(number_of_generators-1 downto 0);
end record;
signal reg_input, int_input: input_type;
-- FM modulation phase increments shifted according to the selected FM range.
signal shifted_phase_increments_reg: modulated_generator_phase_vector(number_of_generators-1 downto 0);
-- Generator´s unregistered and registered interconnection signals.
signal phases_int, phases_reg: modulated_generator_phase_vector(number_of_generators-1 downto 0);
signal samples_int, samples_reg: modulated_generator_sample_vector(number_of_generators-1 downto 0);
-- Generator´s synchronization signals.
signal phase_resets: std_logic_vector(number_of_generators-1 downto 0);
begin
--------------------------------------------------------------------------------
-- Connections to and from internal signals.
--------------------------------------------------------------------------------
-- Shifts the phase increment according to the selected FM range. Also adds one
-- clock cycle latency for all input signals to satisfy the timing constraints.
shift_phase_increments: process is
variable source: integer;
begin
wait until rising_edge(clk);
for i in 0 to number_of_generators-1 loop
-- Derive the phase increment from the (propably shifted) sample.
-- If the sample is less bits wide than the phase, a trade-off must
-- be found between range and resolution. Several ranges using a
-- factor of 8 are supported here for this case.
source := to_integer(reg_input.configs(i).FM_source);
shifted_phase_increments_reg(i) <=
unsigned
(
shift_left(resize(samples_reg(source), phase_width),
3*to_integer(reg_input.configs(i).FM_range))
);
end loop;
end process;
-- Adds one clock cycle latency for all input signals to satisfy the timing
-- constraints.
register_inputs: process is
begin
wait until rising_edge(clk);
reg_input.configs <= configs;
reg_input.phase_increments <= phase_increments;
reg_input.phase_shifts <= phase_shifts;
reg_input.levels <= levels;
end process;
-- Adds one clock cycle latency for all signals connecting signal generators
-- together to satisfy the timing constraints.
register_interconnection: process is
begin
wait until rising_edge(clk);
phases_reg <= phases_int;
samples_reg <= samples_int;
end process;
-- Synchronizes the generators according to the synchronization sources selected.
select_synchronization: process is
variable source: integer;
variable last_phase_msb: std_logic_vector(number_of_generators-1 downto 0)
:= (others => '0');
begin
wait until rising_edge(clk);
-- Defaults (no phase reset).
phase_resets <= (phase_resets'range => '0');
for i in 0 to number_of_generators-1 loop
-- Phase reset (synchronizatition).
source := to_integer(reg_input.configs(i).sync_source);
if (i /= source) then
if phases_reg(source)(phases_reg(source)'high) = '0' and
last_phase_msb(source) = '1' then
-- There was a falling edge on the source´s phase MSB.
phase_resets(i) <= '1';
end if;
last_phase_msb(source) :=
phases_reg(source)(phases_reg(source)'high);
end if;
end loop;
end process;
-- Modifies the generators´ base values according to the modulations selected.
-- This is done synchronously to meet timing requirements (otherwise the adders
-- need too much time).
select_modulation: process is
constant width_difference: integer := phase_width - sample_width;
variable source: integer;
variable phase_from_sample: modulated_generator_phase;
begin
wait until rising_edge(clk);
-- Defaults (no modulation).
int_input <= reg_input;
-- Modulate each generator using the selected modulation sources. If a
-- generator is selected as its own modulation source, modulation is
-- deactivated.
for i in 0 to number_of_generators-1 loop
-- Amplitude modulation.
source := to_integer(reg_input.configs(i).AM_source);
if (i /= source) then
int_input.levels(i) <= reg_input.levels(i) + samples_reg(source);
end if;
-- Frequency modulation.
source := to_integer(reg_input.configs(i).FM_source);
if (i /= source) then
-- Derive the phase increment from the (propably shifted) sample.
int_input.phase_increments(i) <=
reg_input.phase_increments(i) + shifted_phase_increments_reg(i);
end if;
-- Phase modulation.
source := to_integer(reg_input.configs(i).PM_source);
if (i /= source) then
-- Derive the phase from the sample (pad or truncate LSBs when
-- widths are different).
phase_from_sample := (others => '0');
if (width_difference >= 0) then
phase_from_sample(phase_from_sample'high downto width_difference) := unsigned(samples_reg(source));
else
phase_from_sample := unsigned(samples_reg(source)(samples_reg(source)'high downto -width_difference));
end if;
-- Add derived phase to current phase.
int_input.phase_shifts(i) <= reg_input.phase_shifts(i) + phase_from_sample;
end if;
end loop;
end process;
--------------------------------------------------------------------------------
-- Component instantiation.
--------------------------------------------------------------------------------
-- Create all the signal generators.
signal_generators: for i in 0 to number_of_generators-1 generate
signal_generator: entity work.SignalGenerator
generic map
(
phase_width => phase_width,
lookup_table_phase_width => lookup_table_phase_width,
level_width => level_width,
sample_width => sample_width
)
port map
(
clk => clk,
config => int_input.configs(i).generator,
phase_increment => int_input.phase_increments(i),
phase_shift => int_input.phase_shifts(i),
level => int_input.levels(i),
phase => phases_int(i),
reset_phase => phase_resets(i),
sample => samples_int(i)
);
end generate;
--------------------------------------------------------------------------------
-- Output logic.
--------------------------------------------------------------------------------
phases <= phases_reg;
samples <= samples_reg;
end architecture;
|
gpl-3.0
|
96f9d6fa20c6e8f36b40d5538a5e9dbd
| 0.566336 | 4.836316 | false | true | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
twi_master_1.vhd
| 1 | 5,525 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- twi_master_1.vhd
-- This file was auto-generated as part of a generation operation.
-- If you edit it your changes will probably be lost.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity twi_master_1 is
port (
addr : in std_logic_vector(1 downto 0) := (others => '0'); -- avalon_slave_0.address
wr_en : in std_logic := '0'; -- .write
out_data : out std_logic_vector(15 downto 0); -- .readdata
byte_en : in std_logic_vector(1 downto 0) := (others => '0'); -- .byteenable
in_data : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
clk : in std_logic := '0'; -- clock.clk
rst : in std_logic := '0'; -- reset_sink.reset
in_octet : in std_logic_vector(7 downto 0) := (others => '0'); -- avalon_streaming_sink.data
in_valid : in std_logic := '0'; -- .valid
in_ready : out std_logic; -- .ready
out_octet : out std_logic_vector(7 downto 0); -- avalon_streaming_source.data
out_valid : out std_logic; -- .valid
out_ready : in std_logic := '0'; -- .ready
scl_in : in std_logic := '0'; -- conduit_end.export
scl_act : out std_logic; -- .export
sda_in : in std_logic := '0'; -- .export
sda_act : out std_logic; -- .export
sink_irq : in std_logic := '0'; -- .export
source_irq : in std_logic := '0'; -- .export
irq : out std_logic -- .export
);
end entity twi_master_1;
architecture rtl of twi_master_1 is
component twi_master is
port (
addr : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
wr_en : in std_logic := 'X'; -- write
out_data : out std_logic_vector(15 downto 0); -- readdata
byte_en : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
in_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
clk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
in_octet : in std_logic_vector(7 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
out_octet : out std_logic_vector(7 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
scl_in : in std_logic := 'X'; -- export
scl_act : out std_logic; -- export
sda_in : in std_logic := 'X'; -- export
sda_act : out std_logic; -- export
sink_irq : in std_logic := 'X'; -- export
source_irq : in std_logic := 'X'; -- export
irq : out std_logic -- export
);
end component twi_master;
begin
twi_master_1 : component twi_master
port map (
addr => addr, -- avalon_slave_0.address
wr_en => wr_en, -- .write
out_data => out_data, -- .readdata
byte_en => byte_en, -- .byteenable
in_data => in_data, -- .writedata
clk => clk, -- clock.clk
rst => rst, -- reset_sink.reset
in_octet => in_octet, -- avalon_streaming_sink.data
in_valid => in_valid, -- .valid
in_ready => in_ready, -- .ready
out_octet => out_octet, -- avalon_streaming_source.data
out_valid => out_valid, -- .valid
out_ready => out_ready, -- .ready
scl_in => scl_in, -- conduit_end.export
scl_act => scl_act, -- .export
sda_in => sda_in, -- .export
sda_act => sda_act, -- .export
sink_irq => sink_irq, -- .export
source_irq => source_irq, -- .export
irq => irq -- .export
);
end architecture rtl; -- of twi_master_1
|
gpl-3.0
|
88bf2950a5d074188048647582b73ec2
| 0.375023 | 3.983417 | false | false | false | false |
arthurTemporim/SD_SS
|
pre/7/projetos/projeto1/t_display.vhd
| 1 | 1,168 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY t_display IS
END t_display;
ARCHITECTURE behavior OF t_display IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT display
PORT(
a : IN std_logic_vector(3 downto 0);
clk : IN std_logic;
display1 : OUT std_logic_vector(6 downto 0)
);
END COMPONENT;
--Inputs
signal a : std_logic_vector(3 downto 0) := (others => '0');
signal clk : std_logic := '0';
--Outputs
signal display1 : std_logic_vector(6 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: display PORT MAP (
a => a,
clk => clk,
display1 => display1
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
mit
|
5b06034d7194b7e74663140e584fafb6
| 0.583904 | 3.719745 | false | false | false | false |
SalvatoreBarone/Zynq7000DriverPack
|
Src/myGPIO/VHDL/GPIOarray.vhd
| 1 | 3,138 |
--! @file GPIOarray.vhd
--! @author Salvatore Barone <[email protected]>
--! @date 07 04 2017
--!
--! @copyright
--! Copyright 2017 Salvatore Barone <[email protected]>
--!
--! This file is part of Zynq7000DriverPack
--!
--! Zynq7000DriverPack is free software; you can redistribute it and/or modify it under the terms of
--! the GNU General Public License as published by the Free Software Foundation; either version 3 of
--! the License, or any later version.
--!
--! Zynq7000DriverPack is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
--! without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--! GNU General Public License for more details.
--!
--! You should have received a copy of the GNU General Public License along with this program; if not,
--! write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
--! USA.
--!
--! @addtogroup myGPIO
--! @{
--! @addtogroup GPIO-array
--! @{
library ieee;
use ieee.std_logic_1164.all;
--! @brief Array di celle GPIO, pilotabili singolarmente
entity GPIOarray is
Generic ( GPIO_width : natural := 4); --!
--! numero di istanze GPIO create, di default pari a 4 celle.
Port ( GPIO_enable : in std_logic_vector (GPIO_width-1 downto 0); --!
--! segnale di abilitazione, permette di pilotare la linea "GPIO_inout".
--! Quando GPIO_enable(i)=1, la linea GPIO_inout(i) e quella GPIO_write(i) sono connesse tra loro, consentendo
--! la scrittura del valore del pin.
GPIO_write : in std_logic_vector (GPIO_width-1 downto 0); --!
--! segnale di input, diretto verso l'esterno del device.
--! Quando GPIO_enable(i)=1, la linea GPIO_inout(i) e quella GPIO_write(i) sono connesse tra loro, consentendo
--! la scrittura del valore del pin.
GPIO_inout : inout std_logic_vector (GPIO_width-1 downto 0); --!
--! segnale bidirezionale diretto verso l'esterno del device. Può essere usato per leggere/scrivere
--! segnali digitali da/verso l'esterno del device.
GPIO_read : out std_logic_vector (GPIO_width-1 downto 0)); --!
--! segnale di output, diretto verso l'esterno del device.
--! Quando GPIO_enable(i)=1, la linea GPIO_inout(i) e quella GPIO_write(i) sono connesse tra loro, consentendo
--! la scrittura del valore del pin, per cui questo segnale assume esattamente il valore con cui viene
--! impostato il segnale GPIO_write(i). Se GPIO_enable(i)=0, il valore del segnale può essere forzato dall'
--! esterno del device.
end GPIOarray;
architecture Structural of GPIOarray is
component GPIOsingle is
Port ( GPIO_enable : in std_logic;
GPIO_write : in std_logic;
GPIO_inout : inout std_logic;
GPIO_read : out std_logic);
end component;
begin
gpio_array : for i in GPIO_width-1 downto 0 generate
single_gpio : GPIOsingle
Port map( GPIO_enable => GPIO_enable(i),
GPIO_write => GPIO_write(i),
GPIO_inout => GPIO_inout(i),
GPIO_read => GPIO_read(i));
end generate;
end Structural;
--! @}
--! @}
|
gpl-3.0
|
05311312fd1ae087b107bbf50ced7bce
| 0.6875 | 3.449945 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
pipeline_bridge_0.vhd
| 1 | 43,986 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
--Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity pipeline_bridge_0_downstream_adapter is
port (
-- inputs:
signal m1_clk : IN STD_LOGIC;
signal m1_endofpacket : IN STD_LOGIC;
signal m1_readdata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal m1_readdatavalid : IN STD_LOGIC;
signal m1_reset_n : IN STD_LOGIC;
signal m1_waitrequest : IN STD_LOGIC;
signal s1_address : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal s1_arbiterlock : IN STD_LOGIC;
signal s1_arbiterlock2 : IN STD_LOGIC;
signal s1_burstcount : IN STD_LOGIC;
signal s1_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal s1_chipselect : IN STD_LOGIC;
signal s1_debugaccess : IN STD_LOGIC;
signal s1_nativeaddress : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
signal s1_read : IN STD_LOGIC;
signal s1_write : IN STD_LOGIC;
signal s1_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
-- outputs:
signal m1_address : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
signal m1_arbiterlock : OUT STD_LOGIC;
signal m1_arbiterlock2 : OUT STD_LOGIC;
signal m1_burstcount : OUT STD_LOGIC;
signal m1_byteenable : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal m1_chipselect : OUT STD_LOGIC;
signal m1_debugaccess : OUT STD_LOGIC;
signal m1_nativeaddress : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
signal m1_read : OUT STD_LOGIC;
signal m1_write : OUT STD_LOGIC;
signal m1_writedata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal s1_endofpacket : OUT STD_LOGIC;
signal s1_readdata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal s1_readdatavalid : OUT STD_LOGIC;
signal s1_waitrequest : OUT STD_LOGIC
);
end entity pipeline_bridge_0_downstream_adapter;
architecture europa of pipeline_bridge_0_downstream_adapter is
begin
--s1, which is an e_avalon_adapter_slave
--m1, which is an e_avalon_adapter_master
s1_endofpacket <= m1_endofpacket;
s1_readdata <= m1_readdata;
s1_readdatavalid <= m1_readdatavalid;
s1_waitrequest <= m1_waitrequest;
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
m1_address <= std_logic_vector'("000000000000000");
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(NOT m1_waitrequest) = '1' then
m1_address <= s1_address;
end if;
end if;
end process;
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
m1_arbiterlock <= std_logic'('0');
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(NOT m1_waitrequest) = '1' then
m1_arbiterlock <= s1_arbiterlock;
end if;
end if;
end process;
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
m1_arbiterlock2 <= std_logic'('0');
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(NOT m1_waitrequest) = '1' then
m1_arbiterlock2 <= s1_arbiterlock2;
end if;
end if;
end process;
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
m1_burstcount <= std_logic'('0');
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(NOT m1_waitrequest) = '1' then
m1_burstcount <= s1_burstcount;
end if;
end if;
end process;
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
m1_byteenable <= std_logic_vector'("00000000");
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(NOT m1_waitrequest) = '1' then
m1_byteenable <= s1_byteenable;
end if;
end if;
end process;
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
m1_chipselect <= std_logic'('0');
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(NOT m1_waitrequest) = '1' then
m1_chipselect <= s1_chipselect;
end if;
end if;
end process;
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
m1_debugaccess <= std_logic'('0');
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(NOT m1_waitrequest) = '1' then
m1_debugaccess <= s1_debugaccess;
end if;
end if;
end process;
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
m1_nativeaddress <= std_logic_vector'("000000000000");
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(NOT m1_waitrequest) = '1' then
m1_nativeaddress <= s1_nativeaddress;
end if;
end if;
end process;
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
m1_read <= std_logic'('0');
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(NOT m1_waitrequest) = '1' then
m1_read <= s1_read;
end if;
end if;
end process;
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
m1_write <= std_logic'('0');
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(NOT m1_waitrequest) = '1' then
m1_write <= s1_write;
end if;
end if;
end process;
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
m1_writedata <= std_logic_vector'("0000000000000000000000000000000000000000000000000000000000000000");
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(NOT m1_waitrequest) = '1' then
m1_writedata <= s1_writedata;
end if;
end if;
end process;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity pipeline_bridge_0_upstream_adapter is
port (
-- inputs:
signal m1_clk : IN STD_LOGIC;
signal m1_endofpacket : IN STD_LOGIC;
signal m1_readdata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal m1_readdatavalid : IN STD_LOGIC;
signal m1_reset_n : IN STD_LOGIC;
signal m1_waitrequest : IN STD_LOGIC;
signal s1_address : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal s1_arbiterlock : IN STD_LOGIC;
signal s1_arbiterlock2 : IN STD_LOGIC;
signal s1_burstcount : IN STD_LOGIC;
signal s1_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal s1_chipselect : IN STD_LOGIC;
signal s1_clk : IN STD_LOGIC;
signal s1_debugaccess : IN STD_LOGIC;
signal s1_flush : IN STD_LOGIC;
signal s1_nativeaddress : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
signal s1_read : IN STD_LOGIC;
signal s1_reset_n : IN STD_LOGIC;
signal s1_write : IN STD_LOGIC;
signal s1_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
-- outputs:
signal m1_address : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
signal m1_arbiterlock : OUT STD_LOGIC;
signal m1_arbiterlock2 : OUT STD_LOGIC;
signal m1_burstcount : OUT STD_LOGIC;
signal m1_byteenable : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal m1_chipselect : OUT STD_LOGIC;
signal m1_debugaccess : OUT STD_LOGIC;
signal m1_nativeaddress : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
signal m1_read : OUT STD_LOGIC;
signal m1_write : OUT STD_LOGIC;
signal m1_writedata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal s1_endofpacket : OUT STD_LOGIC;
signal s1_readdata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal s1_readdatavalid : OUT STD_LOGIC;
signal s1_waitrequest : OUT STD_LOGIC
);
end entity pipeline_bridge_0_upstream_adapter;
architecture europa of pipeline_bridge_0_upstream_adapter is
begin
--s1, which is an e_avalon_adapter_slave
--m1, which is an e_avalon_adapter_master
process (s1_clk, s1_reset_n)
begin
if s1_reset_n = '0' then
s1_readdatavalid <= std_logic'('0');
elsif s1_clk'event and s1_clk = '1' then
if std_logic'(s1_flush) = '1' then
s1_readdatavalid <= std_logic'('0');
else
s1_readdatavalid <= m1_readdatavalid;
end if;
end if;
end process;
s1_waitrequest <= m1_waitrequest;
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
s1_endofpacket <= std_logic'('0');
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(m1_readdatavalid) = '1' then
s1_endofpacket <= m1_endofpacket;
end if;
end if;
end process;
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
s1_readdata <= std_logic_vector'("0000000000000000000000000000000000000000000000000000000000000000");
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(m1_readdatavalid) = '1' then
s1_readdata <= m1_readdata;
end if;
end if;
end process;
m1_address <= s1_address;
m1_arbiterlock <= s1_arbiterlock;
m1_arbiterlock2 <= s1_arbiterlock2;
m1_burstcount <= s1_burstcount;
m1_byteenable <= s1_byteenable;
m1_chipselect <= s1_chipselect;
m1_debugaccess <= s1_debugaccess;
m1_nativeaddress <= s1_nativeaddress;
m1_read <= s1_read;
m1_write <= s1_write;
m1_writedata <= s1_writedata;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity pipeline_bridge_0_waitrequest_adapter is
port (
-- inputs:
signal m1_clk : IN STD_LOGIC;
signal m1_endofpacket : IN STD_LOGIC;
signal m1_readdata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal m1_readdatavalid : IN STD_LOGIC;
signal m1_reset_n : IN STD_LOGIC;
signal m1_waitrequest : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal s1_address : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal s1_arbiterlock : IN STD_LOGIC;
signal s1_arbiterlock2 : IN STD_LOGIC;
signal s1_burstcount : IN STD_LOGIC;
signal s1_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal s1_chipselect : IN STD_LOGIC;
signal s1_debugaccess : IN STD_LOGIC;
signal s1_nativeaddress : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
signal s1_read : IN STD_LOGIC;
signal s1_write : IN STD_LOGIC;
signal s1_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
-- outputs:
signal m1_address : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
signal m1_arbiterlock : OUT STD_LOGIC;
signal m1_arbiterlock2 : OUT STD_LOGIC;
signal m1_burstcount : OUT STD_LOGIC;
signal m1_byteenable : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal m1_chipselect : OUT STD_LOGIC;
signal m1_debugaccess : OUT STD_LOGIC;
signal m1_nativeaddress : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
signal m1_read : OUT STD_LOGIC;
signal m1_write : OUT STD_LOGIC;
signal m1_writedata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal s1_endofpacket : OUT STD_LOGIC;
signal s1_readdata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal s1_readdatavalid : OUT STD_LOGIC;
signal s1_waitrequest : OUT STD_LOGIC
);
end entity pipeline_bridge_0_waitrequest_adapter;
architecture europa of pipeline_bridge_0_waitrequest_adapter is
signal d1_s1_address : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal d1_s1_arbiterlock : STD_LOGIC;
signal d1_s1_arbiterlock2 : STD_LOGIC;
signal d1_s1_burstcount : STD_LOGIC;
signal d1_s1_byteenable : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal d1_s1_chipselect : STD_LOGIC;
signal d1_s1_debugaccess : STD_LOGIC;
signal d1_s1_nativeaddress : STD_LOGIC_VECTOR (11 DOWNTO 0);
signal d1_s1_read : STD_LOGIC;
signal d1_s1_write : STD_LOGIC;
signal d1_s1_writedata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal internal_s1_waitrequest : STD_LOGIC;
signal set_use_registered : STD_LOGIC;
signal use_registered : STD_LOGIC;
begin
--s1, which is an e_avalon_adapter_slave
--m1, which is an e_avalon_adapter_master
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
internal_s1_waitrequest <= std_logic'('0');
elsif m1_clk'event and m1_clk = '1' then
internal_s1_waitrequest <= m1_waitrequest;
end if;
end process;
s1_endofpacket <= m1_endofpacket;
s1_readdata <= m1_readdata;
s1_readdatavalid <= m1_readdatavalid;
--set use registered, which is an e_assign
set_use_registered <= m1_waitrequest AND NOT internal_s1_waitrequest;
--use registered, which is an e_register
process (m1_clk, reset_n)
begin
if reset_n = '0' then
use_registered <= std_logic'('0');
elsif m1_clk'event and m1_clk = '1' then
if std_logic'((NOT m1_waitrequest AND internal_s1_waitrequest)) = '1' then
use_registered <= std_logic'('0');
elsif std_logic'(set_use_registered) = '1' then
use_registered <= Vector_To_Std_Logic(-SIGNED(std_logic_vector'("00000000000000000000000000000001")));
end if;
end if;
end process;
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
d1_s1_address <= std_logic_vector'("000000000000000");
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(set_use_registered) = '1' then
d1_s1_address <= s1_address;
end if;
end if;
end process;
m1_address <= A_WE_StdLogicVector((std_logic'((use_registered)) = '1'), d1_s1_address, s1_address);
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
d1_s1_arbiterlock <= std_logic'('0');
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(set_use_registered) = '1' then
d1_s1_arbiterlock <= s1_arbiterlock;
end if;
end if;
end process;
m1_arbiterlock <= A_WE_StdLogic((std_logic'((use_registered)) = '1'), d1_s1_arbiterlock, s1_arbiterlock);
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
d1_s1_arbiterlock2 <= std_logic'('0');
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(set_use_registered) = '1' then
d1_s1_arbiterlock2 <= s1_arbiterlock2;
end if;
end if;
end process;
m1_arbiterlock2 <= A_WE_StdLogic((std_logic'((use_registered)) = '1'), d1_s1_arbiterlock2, s1_arbiterlock2);
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
d1_s1_burstcount <= std_logic'('0');
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(set_use_registered) = '1' then
d1_s1_burstcount <= s1_burstcount;
end if;
end if;
end process;
m1_burstcount <= A_WE_StdLogic((std_logic'((use_registered)) = '1'), d1_s1_burstcount, s1_burstcount);
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
d1_s1_byteenable <= std_logic_vector'("00000000");
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(set_use_registered) = '1' then
d1_s1_byteenable <= s1_byteenable;
end if;
end if;
end process;
m1_byteenable <= A_WE_StdLogicVector((std_logic'((use_registered)) = '1'), d1_s1_byteenable, s1_byteenable);
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
d1_s1_chipselect <= std_logic'('0');
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(set_use_registered) = '1' then
d1_s1_chipselect <= s1_chipselect;
end if;
end if;
end process;
m1_chipselect <= A_WE_StdLogic((std_logic'((use_registered)) = '1'), d1_s1_chipselect, s1_chipselect);
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
d1_s1_debugaccess <= std_logic'('0');
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(set_use_registered) = '1' then
d1_s1_debugaccess <= s1_debugaccess;
end if;
end if;
end process;
m1_debugaccess <= A_WE_StdLogic((std_logic'((use_registered)) = '1'), d1_s1_debugaccess, s1_debugaccess);
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
d1_s1_nativeaddress <= std_logic_vector'("000000000000");
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(set_use_registered) = '1' then
d1_s1_nativeaddress <= s1_nativeaddress;
end if;
end if;
end process;
m1_nativeaddress <= A_WE_StdLogicVector((std_logic'((use_registered)) = '1'), d1_s1_nativeaddress, s1_nativeaddress);
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
d1_s1_read <= std_logic'('0');
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(set_use_registered) = '1' then
d1_s1_read <= s1_read;
end if;
end if;
end process;
m1_read <= A_WE_StdLogic((std_logic'((use_registered)) = '1'), d1_s1_read, s1_read);
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
d1_s1_write <= std_logic'('0');
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(set_use_registered) = '1' then
d1_s1_write <= s1_write;
end if;
end if;
end process;
m1_write <= A_WE_StdLogic((std_logic'((use_registered)) = '1'), d1_s1_write, s1_write);
process (m1_clk, m1_reset_n)
begin
if m1_reset_n = '0' then
d1_s1_writedata <= std_logic_vector'("0000000000000000000000000000000000000000000000000000000000000000");
elsif m1_clk'event and m1_clk = '1' then
if std_logic'(set_use_registered) = '1' then
d1_s1_writedata <= s1_writedata;
end if;
end if;
end process;
m1_writedata <= A_WE_StdLogicVector((std_logic'((use_registered)) = '1'), d1_s1_writedata, s1_writedata);
--vhdl renameroo for output signals
s1_waitrequest <= internal_s1_waitrequest;
end europa;
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity pipeline_bridge_0 is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal m1_endofpacket : IN STD_LOGIC;
signal m1_readdata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal m1_readdatavalid : IN STD_LOGIC;
signal m1_waitrequest : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal s1_address : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
signal s1_arbiterlock : IN STD_LOGIC;
signal s1_arbiterlock2 : IN STD_LOGIC;
signal s1_burstcount : IN STD_LOGIC;
signal s1_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal s1_chipselect : IN STD_LOGIC;
signal s1_debugaccess : IN STD_LOGIC;
signal s1_nativeaddress : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
signal s1_read : IN STD_LOGIC;
signal s1_write : IN STD_LOGIC;
signal s1_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
-- outputs:
signal m1_address : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
signal m1_burstcount : OUT STD_LOGIC;
signal m1_byteenable : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal m1_chipselect : OUT STD_LOGIC;
signal m1_debugaccess : OUT STD_LOGIC;
signal m1_read : OUT STD_LOGIC;
signal m1_write : OUT STD_LOGIC;
signal m1_writedata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal s1_endofpacket : OUT STD_LOGIC;
signal s1_readdata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal s1_readdatavalid : OUT STD_LOGIC;
signal s1_waitrequest : OUT STD_LOGIC
);
end entity pipeline_bridge_0;
architecture europa of pipeline_bridge_0 is
component pipeline_bridge_0_downstream_adapter is
port (
-- inputs:
signal m1_clk : IN STD_LOGIC;
signal m1_endofpacket : IN STD_LOGIC;
signal m1_readdata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal m1_readdatavalid : IN STD_LOGIC;
signal m1_reset_n : IN STD_LOGIC;
signal m1_waitrequest : IN STD_LOGIC;
signal s1_address : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal s1_arbiterlock : IN STD_LOGIC;
signal s1_arbiterlock2 : IN STD_LOGIC;
signal s1_burstcount : IN STD_LOGIC;
signal s1_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal s1_chipselect : IN STD_LOGIC;
signal s1_debugaccess : IN STD_LOGIC;
signal s1_nativeaddress : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
signal s1_read : IN STD_LOGIC;
signal s1_write : IN STD_LOGIC;
signal s1_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
-- outputs:
signal m1_address : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
signal m1_arbiterlock : OUT STD_LOGIC;
signal m1_arbiterlock2 : OUT STD_LOGIC;
signal m1_burstcount : OUT STD_LOGIC;
signal m1_byteenable : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal m1_chipselect : OUT STD_LOGIC;
signal m1_debugaccess : OUT STD_LOGIC;
signal m1_nativeaddress : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
signal m1_read : OUT STD_LOGIC;
signal m1_write : OUT STD_LOGIC;
signal m1_writedata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal s1_endofpacket : OUT STD_LOGIC;
signal s1_readdata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal s1_readdatavalid : OUT STD_LOGIC;
signal s1_waitrequest : OUT STD_LOGIC
);
end component pipeline_bridge_0_downstream_adapter;
component pipeline_bridge_0_upstream_adapter is
port (
-- inputs:
signal m1_clk : IN STD_LOGIC;
signal m1_endofpacket : IN STD_LOGIC;
signal m1_readdata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal m1_readdatavalid : IN STD_LOGIC;
signal m1_reset_n : IN STD_LOGIC;
signal m1_waitrequest : IN STD_LOGIC;
signal s1_address : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal s1_arbiterlock : IN STD_LOGIC;
signal s1_arbiterlock2 : IN STD_LOGIC;
signal s1_burstcount : IN STD_LOGIC;
signal s1_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal s1_chipselect : IN STD_LOGIC;
signal s1_clk : IN STD_LOGIC;
signal s1_debugaccess : IN STD_LOGIC;
signal s1_flush : IN STD_LOGIC;
signal s1_nativeaddress : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
signal s1_read : IN STD_LOGIC;
signal s1_reset_n : IN STD_LOGIC;
signal s1_write : IN STD_LOGIC;
signal s1_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
-- outputs:
signal m1_address : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
signal m1_arbiterlock : OUT STD_LOGIC;
signal m1_arbiterlock2 : OUT STD_LOGIC;
signal m1_burstcount : OUT STD_LOGIC;
signal m1_byteenable : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal m1_chipselect : OUT STD_LOGIC;
signal m1_debugaccess : OUT STD_LOGIC;
signal m1_nativeaddress : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
signal m1_read : OUT STD_LOGIC;
signal m1_write : OUT STD_LOGIC;
signal m1_writedata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal s1_endofpacket : OUT STD_LOGIC;
signal s1_readdata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal s1_readdatavalid : OUT STD_LOGIC;
signal s1_waitrequest : OUT STD_LOGIC
);
end component pipeline_bridge_0_upstream_adapter;
component pipeline_bridge_0_waitrequest_adapter is
port (
-- inputs:
signal m1_clk : IN STD_LOGIC;
signal m1_endofpacket : IN STD_LOGIC;
signal m1_readdata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
signal m1_readdatavalid : IN STD_LOGIC;
signal m1_reset_n : IN STD_LOGIC;
signal m1_waitrequest : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal s1_address : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
signal s1_arbiterlock : IN STD_LOGIC;
signal s1_arbiterlock2 : IN STD_LOGIC;
signal s1_burstcount : IN STD_LOGIC;
signal s1_byteenable : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal s1_chipselect : IN STD_LOGIC;
signal s1_debugaccess : IN STD_LOGIC;
signal s1_nativeaddress : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
signal s1_read : IN STD_LOGIC;
signal s1_write : IN STD_LOGIC;
signal s1_writedata : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
-- outputs:
signal m1_address : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
signal m1_arbiterlock : OUT STD_LOGIC;
signal m1_arbiterlock2 : OUT STD_LOGIC;
signal m1_burstcount : OUT STD_LOGIC;
signal m1_byteenable : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal m1_chipselect : OUT STD_LOGIC;
signal m1_debugaccess : OUT STD_LOGIC;
signal m1_nativeaddress : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
signal m1_read : OUT STD_LOGIC;
signal m1_write : OUT STD_LOGIC;
signal m1_writedata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal s1_endofpacket : OUT STD_LOGIC;
signal s1_readdata : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
signal s1_readdatavalid : OUT STD_LOGIC;
signal s1_waitrequest : OUT STD_LOGIC
);
end component pipeline_bridge_0_waitrequest_adapter;
signal downstream_m1_address : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal downstream_m1_arbiterlock : STD_LOGIC;
signal downstream_m1_arbiterlock2 : STD_LOGIC;
signal downstream_m1_burstcount : STD_LOGIC;
signal downstream_m1_byteenable : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal downstream_m1_chipselect : STD_LOGIC;
signal downstream_m1_debugaccess : STD_LOGIC;
signal downstream_m1_endofpacket : STD_LOGIC;
signal downstream_m1_nativeaddress : STD_LOGIC_VECTOR (11 DOWNTO 0);
signal downstream_m1_read : STD_LOGIC;
signal downstream_m1_readdata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal downstream_m1_readdatavalid : STD_LOGIC;
signal downstream_m1_waitrequest : STD_LOGIC;
signal downstream_m1_write : STD_LOGIC;
signal downstream_m1_writedata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal downstream_s1_address : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal downstream_s1_arbiterlock : STD_LOGIC;
signal downstream_s1_arbiterlock2 : STD_LOGIC;
signal downstream_s1_burstcount : STD_LOGIC;
signal downstream_s1_byteenable : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal downstream_s1_chipselect : STD_LOGIC;
signal downstream_s1_debugaccess : STD_LOGIC;
signal downstream_s1_endofpacket : STD_LOGIC;
signal downstream_s1_nativeaddress : STD_LOGIC_VECTOR (11 DOWNTO 0);
signal downstream_s1_read : STD_LOGIC;
signal downstream_s1_readdata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal downstream_s1_readdatavalid : STD_LOGIC;
signal downstream_s1_waitrequest : STD_LOGIC;
signal downstream_s1_write : STD_LOGIC;
signal downstream_s1_writedata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal m1_arbiterlock : STD_LOGIC;
signal m1_arbiterlock2 : STD_LOGIC;
signal m1_nativeaddress : STD_LOGIC_VECTOR (11 DOWNTO 0);
signal module_input : STD_LOGIC;
signal upstream_m1_address : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal upstream_m1_arbiterlock : STD_LOGIC;
signal upstream_m1_arbiterlock2 : STD_LOGIC;
signal upstream_m1_burstcount : STD_LOGIC;
signal upstream_m1_byteenable : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal upstream_m1_chipselect : STD_LOGIC;
signal upstream_m1_debugaccess : STD_LOGIC;
signal upstream_m1_endofpacket : STD_LOGIC;
signal upstream_m1_nativeaddress : STD_LOGIC_VECTOR (11 DOWNTO 0);
signal upstream_m1_read : STD_LOGIC;
signal upstream_m1_readdata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal upstream_m1_readdatavalid : STD_LOGIC;
signal upstream_m1_waitrequest : STD_LOGIC;
signal upstream_m1_write : STD_LOGIC;
signal upstream_m1_writedata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal upstream_s1_address : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal upstream_s1_arbiterlock : STD_LOGIC;
signal upstream_s1_arbiterlock2 : STD_LOGIC;
signal upstream_s1_burstcount : STD_LOGIC;
signal upstream_s1_byteenable : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal upstream_s1_chipselect : STD_LOGIC;
signal upstream_s1_debugaccess : STD_LOGIC;
signal upstream_s1_endofpacket : STD_LOGIC;
signal upstream_s1_nativeaddress : STD_LOGIC_VECTOR (11 DOWNTO 0);
signal upstream_s1_read : STD_LOGIC;
signal upstream_s1_readdata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal upstream_s1_readdatavalid : STD_LOGIC;
signal upstream_s1_waitrequest : STD_LOGIC;
signal upstream_s1_write : STD_LOGIC;
signal upstream_s1_writedata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal waitrequest_m1_address : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal waitrequest_m1_arbiterlock : STD_LOGIC;
signal waitrequest_m1_arbiterlock2 : STD_LOGIC;
signal waitrequest_m1_burstcount : STD_LOGIC;
signal waitrequest_m1_byteenable : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal waitrequest_m1_chipselect : STD_LOGIC;
signal waitrequest_m1_debugaccess : STD_LOGIC;
signal waitrequest_m1_endofpacket : STD_LOGIC;
signal waitrequest_m1_nativeaddress : STD_LOGIC_VECTOR (11 DOWNTO 0);
signal waitrequest_m1_read : STD_LOGIC;
signal waitrequest_m1_readdata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal waitrequest_m1_readdatavalid : STD_LOGIC;
signal waitrequest_m1_waitrequest : STD_LOGIC;
signal waitrequest_m1_write : STD_LOGIC;
signal waitrequest_m1_writedata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal waitrequest_s1_address : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal waitrequest_s1_arbiterlock : STD_LOGIC;
signal waitrequest_s1_arbiterlock2 : STD_LOGIC;
signal waitrequest_s1_burstcount : STD_LOGIC;
signal waitrequest_s1_byteenable : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal waitrequest_s1_chipselect : STD_LOGIC;
signal waitrequest_s1_debugaccess : STD_LOGIC;
signal waitrequest_s1_endofpacket : STD_LOGIC;
signal waitrequest_s1_nativeaddress : STD_LOGIC_VECTOR (11 DOWNTO 0);
signal waitrequest_s1_read : STD_LOGIC;
signal waitrequest_s1_readdata : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal waitrequest_s1_readdatavalid : STD_LOGIC;
signal waitrequest_s1_waitrequest : STD_LOGIC;
signal waitrequest_s1_write : STD_LOGIC;
signal waitrequest_s1_writedata : STD_LOGIC_VECTOR (63 DOWNTO 0);
begin
--the_pipeline_bridge_0_downstream_adapter, which is an e_instance
the_pipeline_bridge_0_downstream_adapter : pipeline_bridge_0_downstream_adapter
port map(
m1_address => downstream_m1_address,
m1_arbiterlock => downstream_m1_arbiterlock,
m1_arbiterlock2 => downstream_m1_arbiterlock2,
m1_burstcount => downstream_m1_burstcount,
m1_byteenable => downstream_m1_byteenable,
m1_chipselect => downstream_m1_chipselect,
m1_debugaccess => downstream_m1_debugaccess,
m1_nativeaddress => downstream_m1_nativeaddress,
m1_read => downstream_m1_read,
m1_write => downstream_m1_write,
m1_writedata => downstream_m1_writedata,
s1_endofpacket => downstream_s1_endofpacket,
s1_readdata => downstream_s1_readdata,
s1_readdatavalid => downstream_s1_readdatavalid,
s1_waitrequest => downstream_s1_waitrequest,
m1_clk => clk,
m1_endofpacket => downstream_m1_endofpacket,
m1_readdata => downstream_m1_readdata,
m1_readdatavalid => downstream_m1_readdatavalid,
m1_reset_n => reset_n,
m1_waitrequest => downstream_m1_waitrequest,
s1_address => downstream_s1_address,
s1_arbiterlock => downstream_s1_arbiterlock,
s1_arbiterlock2 => downstream_s1_arbiterlock2,
s1_burstcount => downstream_s1_burstcount,
s1_byteenable => downstream_s1_byteenable,
s1_chipselect => downstream_s1_chipselect,
s1_debugaccess => downstream_s1_debugaccess,
s1_nativeaddress => downstream_s1_nativeaddress,
s1_read => downstream_s1_read,
s1_write => downstream_s1_write,
s1_writedata => downstream_s1_writedata
);
--the_pipeline_bridge_0_upstream_adapter, which is an e_instance
the_pipeline_bridge_0_upstream_adapter : pipeline_bridge_0_upstream_adapter
port map(
m1_address => upstream_m1_address,
m1_arbiterlock => upstream_m1_arbiterlock,
m1_arbiterlock2 => upstream_m1_arbiterlock2,
m1_burstcount => upstream_m1_burstcount,
m1_byteenable => upstream_m1_byteenable,
m1_chipselect => upstream_m1_chipselect,
m1_debugaccess => upstream_m1_debugaccess,
m1_nativeaddress => upstream_m1_nativeaddress,
m1_read => upstream_m1_read,
m1_write => upstream_m1_write,
m1_writedata => upstream_m1_writedata,
s1_endofpacket => upstream_s1_endofpacket,
s1_readdata => upstream_s1_readdata,
s1_readdatavalid => upstream_s1_readdatavalid,
s1_waitrequest => upstream_s1_waitrequest,
m1_clk => clk,
m1_endofpacket => upstream_m1_endofpacket,
m1_readdata => upstream_m1_readdata,
m1_readdatavalid => upstream_m1_readdatavalid,
m1_reset_n => reset_n,
m1_waitrequest => upstream_m1_waitrequest,
s1_address => upstream_s1_address,
s1_arbiterlock => upstream_s1_arbiterlock,
s1_arbiterlock2 => upstream_s1_arbiterlock2,
s1_burstcount => upstream_s1_burstcount,
s1_byteenable => upstream_s1_byteenable,
s1_chipselect => upstream_s1_chipselect,
s1_clk => clk,
s1_debugaccess => upstream_s1_debugaccess,
s1_flush => module_input,
s1_nativeaddress => upstream_s1_nativeaddress,
s1_read => upstream_s1_read,
s1_reset_n => reset_n,
s1_write => upstream_s1_write,
s1_writedata => upstream_s1_writedata
);
module_input <= std_logic'('0');
--the_pipeline_bridge_0_waitrequest_adapter, which is an e_instance
the_pipeline_bridge_0_waitrequest_adapter : pipeline_bridge_0_waitrequest_adapter
port map(
m1_address => waitrequest_m1_address,
m1_arbiterlock => waitrequest_m1_arbiterlock,
m1_arbiterlock2 => waitrequest_m1_arbiterlock2,
m1_burstcount => waitrequest_m1_burstcount,
m1_byteenable => waitrequest_m1_byteenable,
m1_chipselect => waitrequest_m1_chipselect,
m1_debugaccess => waitrequest_m1_debugaccess,
m1_nativeaddress => waitrequest_m1_nativeaddress,
m1_read => waitrequest_m1_read,
m1_write => waitrequest_m1_write,
m1_writedata => waitrequest_m1_writedata,
s1_endofpacket => waitrequest_s1_endofpacket,
s1_readdata => waitrequest_s1_readdata,
s1_readdatavalid => waitrequest_s1_readdatavalid,
s1_waitrequest => waitrequest_s1_waitrequest,
m1_clk => clk,
m1_endofpacket => waitrequest_m1_endofpacket,
m1_readdata => waitrequest_m1_readdata,
m1_readdatavalid => waitrequest_m1_readdatavalid,
m1_reset_n => reset_n,
m1_waitrequest => waitrequest_m1_waitrequest,
reset_n => reset_n,
s1_address => waitrequest_s1_address,
s1_arbiterlock => waitrequest_s1_arbiterlock,
s1_arbiterlock2 => waitrequest_s1_arbiterlock2,
s1_burstcount => waitrequest_s1_burstcount,
s1_byteenable => waitrequest_s1_byteenable,
s1_chipselect => waitrequest_s1_chipselect,
s1_debugaccess => waitrequest_s1_debugaccess,
s1_nativeaddress => waitrequest_s1_nativeaddress,
s1_read => waitrequest_s1_read,
s1_write => waitrequest_s1_write,
s1_writedata => waitrequest_s1_writedata
);
m1_nativeaddress <= downstream_m1_nativeaddress;
downstream_s1_nativeaddress <= upstream_m1_nativeaddress;
upstream_s1_nativeaddress <= waitrequest_m1_nativeaddress;
waitrequest_s1_nativeaddress <= s1_nativeaddress;
m1_debugaccess <= downstream_m1_debugaccess;
downstream_s1_debugaccess <= upstream_m1_debugaccess;
upstream_s1_debugaccess <= waitrequest_m1_debugaccess;
waitrequest_s1_debugaccess <= s1_debugaccess;
m1_arbiterlock <= downstream_m1_arbiterlock;
downstream_s1_arbiterlock <= upstream_m1_arbiterlock;
upstream_s1_arbiterlock <= waitrequest_m1_arbiterlock;
waitrequest_s1_arbiterlock <= s1_arbiterlock;
m1_writedata <= downstream_m1_writedata;
downstream_s1_writedata <= upstream_m1_writedata;
upstream_s1_writedata <= waitrequest_m1_writedata;
waitrequest_s1_writedata <= s1_writedata;
m1_chipselect <= downstream_m1_chipselect;
downstream_s1_chipselect <= upstream_m1_chipselect;
upstream_s1_chipselect <= waitrequest_m1_chipselect;
waitrequest_s1_chipselect <= s1_chipselect;
m1_burstcount <= downstream_m1_burstcount;
downstream_s1_burstcount <= upstream_m1_burstcount;
upstream_s1_burstcount <= waitrequest_m1_burstcount;
waitrequest_s1_burstcount <= s1_burstcount;
m1_byteenable <= downstream_m1_byteenable;
downstream_s1_byteenable <= upstream_m1_byteenable;
upstream_s1_byteenable <= waitrequest_m1_byteenable;
waitrequest_s1_byteenable <= s1_byteenable;
m1_arbiterlock2 <= downstream_m1_arbiterlock2;
downstream_s1_arbiterlock2 <= upstream_m1_arbiterlock2;
upstream_s1_arbiterlock2 <= waitrequest_m1_arbiterlock2;
waitrequest_s1_arbiterlock2 <= s1_arbiterlock2;
m1_read <= downstream_m1_read;
downstream_s1_read <= upstream_m1_read;
upstream_s1_read <= waitrequest_m1_read;
waitrequest_s1_read <= s1_read;
m1_write <= downstream_m1_write;
downstream_s1_write <= upstream_m1_write;
upstream_s1_write <= waitrequest_m1_write;
waitrequest_s1_write <= s1_write;
waitrequest_s1_address <= s1_address & std_logic_vector'("000");
upstream_s1_address <= waitrequest_m1_address;
downstream_s1_address <= upstream_m1_address;
m1_address <= downstream_m1_address;
downstream_m1_readdatavalid <= m1_readdatavalid;
upstream_m1_readdatavalid <= downstream_s1_readdatavalid;
waitrequest_m1_readdatavalid <= upstream_s1_readdatavalid;
s1_readdatavalid <= waitrequest_s1_readdatavalid;
downstream_m1_waitrequest <= m1_waitrequest;
upstream_m1_waitrequest <= downstream_s1_waitrequest;
waitrequest_m1_waitrequest <= upstream_s1_waitrequest;
s1_waitrequest <= waitrequest_s1_waitrequest;
downstream_m1_endofpacket <= m1_endofpacket;
upstream_m1_endofpacket <= downstream_s1_endofpacket;
waitrequest_m1_endofpacket <= upstream_s1_endofpacket;
s1_endofpacket <= waitrequest_s1_endofpacket;
downstream_m1_readdata <= m1_readdata;
upstream_m1_readdata <= downstream_s1_readdata;
waitrequest_m1_readdata <= upstream_s1_readdata;
s1_readdata <= waitrequest_s1_readdata;
--s1, which is an e_avalon_slave
--m1, which is an e_avalon_master
end europa;
|
gpl-3.0
|
f5d29996eeb0cf2acfda18d6067d26ed
| 0.604374 | 3.725102 | false | false | false | false |
arthurbenemann/fpga-bits
|
undocumented/audioDac/ipcore_dir/rom_memory/simulation/rom_memory_tb.vhd
| 1 | 4,367 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: rom_memory_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY rom_memory_tb IS
END ENTITY;
ARCHITECTURE rom_memory_tb_ARCH OF rom_memory_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
rom_memory_synth_inst:ENTITY work.rom_memory_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
gpl-3.0
|
94293bcbcad1b907c127edc62c8f2c51
| 0.620105 | 4.635881 | false | false | false | false |
aospan/NetUP_Dual_Universal_CI-fpga
|
dvb_dma_0.vhd
| 1 | 4,546 |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- dvb_dma_0.vhd
-- This file was auto-generated as part of a generation operation.
-- If you edit it your changes will probably be lost.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity dvb_dma_0 is
port (
address : in std_logic_vector(3 downto 0) := (others => '0'); -- avalon_slave_0.address
byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
write : in std_logic := '0'; -- .write
readdata : out std_logic_vector(31 downto 0); -- .readdata
clk : in std_logic := '0'; -- clock.clk
dvb_sop : in std_logic := '0'; -- conduit_end.export
dvb_data : in std_logic_vector(7 downto 0) := (others => '0'); -- .export
dvb_dval : in std_logic := '0'; -- .export
mem_size : out std_logic_vector(6 downto 0); -- .export
mem_addr : out std_logic_vector(60 downto 0); -- .export
mem_byteen : out std_logic_vector(7 downto 0); -- .export
mem_wrdata : out std_logic_vector(63 downto 0); -- .export
mem_write : out std_logic; -- .export
mem_waitreq : in std_logic := '0'; -- .export
interrupt : out std_logic; -- .export
rst : in std_logic := '0' -- reset_sink.reset
);
end entity dvb_dma_0;
architecture rtl of dvb_dma_0 is
component dvb_dma is
port (
address : in std_logic_vector(3 downto 0) := (others => 'X'); -- address
byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
write : in std_logic := 'X'; -- write
readdata : out std_logic_vector(31 downto 0); -- readdata
clk : in std_logic := 'X'; -- clk
dvb_sop : in std_logic := 'X'; -- export
dvb_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
dvb_dval : in std_logic := 'X'; -- export
mem_size : out std_logic_vector(6 downto 0); -- export
mem_addr : out std_logic_vector(60 downto 0); -- export
mem_byteen : out std_logic_vector(7 downto 0); -- export
mem_wrdata : out std_logic_vector(63 downto 0); -- export
mem_write : out std_logic; -- export
mem_waitreq : in std_logic := 'X'; -- export
interrupt : out std_logic; -- export
rst : in std_logic := 'X' -- reset
);
end component dvb_dma;
begin
dvb_dma_0 : component dvb_dma
port map (
address => address, -- avalon_slave_0.address
byteenable => byteenable, -- .byteenable
writedata => writedata, -- .writedata
write => write, -- .write
readdata => readdata, -- .readdata
clk => clk, -- clock.clk
dvb_sop => dvb_sop, -- conduit_end.export
dvb_data => dvb_data, -- .export
dvb_dval => dvb_dval, -- .export
mem_size => mem_size, -- .export
mem_addr => mem_addr, -- .export
mem_byteen => mem_byteen, -- .export
mem_wrdata => mem_wrdata, -- .export
mem_write => mem_write, -- .export
mem_waitreq => mem_waitreq, -- .export
interrupt => interrupt, -- .export
rst => rst -- reset_sink.reset
);
end architecture rtl; -- of dvb_dma_0
|
gpl-3.0
|
1bb003c9a871f64b81b2a9872357f152
| 0.434888 | 3.791493 | false | false | false | false |
JosiCoder/CtLab
|
FPGA/SRAM_Controller/Source/SRAM_Controller.vhd
| 1 | 11,459 |
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Generates all control signals and provides flow control for accessing the SRAM.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity SRAM_Controller is
generic
(
-- The number of clock cycles to wait before each SRAM access.
num_of_total_wait_states: natural;
-- The number of clock cycles the write pulse must be active.
num_of_write_pulse_wait_states: natural;
-- The number of clock cycles to wait before writing after reading (to
-- provide the SRAM's data bus enough time to get high impedance).
num_of_wait_states_before_write_after_read: natural;
-- The width of the data stored in the memory.
data_width: natural;
-- The width of the address bus of the memory.
address_width: natural
);
port
(
-- The system clock.
clk: in std_logic;
-- The control signals towards the client. If read and write are both set to '1',
-- the secondary address is stored but no read or write is done.
read: in std_logic;
write: in std_logic;
ready: out std_logic;
auto_increment_address: in std_logic;
auto_increment_end_address_reached: out std_logic;
-- The address and data towards the client.
-- For auto_increment_address = '1' the address passed here is the end address.
address: in unsigned(address_width-1 downto 0);
data_in: in std_logic_vector(data_width-1 downto 0);
data_out: out std_logic_vector(data_width-1 downto 0);
-- The control signals towards the SRAM (write enable and output enable, both active low).
ram_we_n: out std_logic;
ram_oe_n: out std_logic;
-- The address and data towards the SRAM.
ram_address: out unsigned(address_width-1 downto 0);
ram_data: inout std_logic_vector(data_width-1 downto 0)
);
end entity;
architecture stdarch of SRAM_Controller is
-- This generates enough bits for maximum number of wait states - 1.
constant wait_states_counter_width : natural := integer(ceil(log2(real(num_of_total_wait_states + num_of_wait_states_before_write_after_read))));
type reg_type is record
wait_states_counter: unsigned(wait_states_counter_width-1 downto 0);
reading: std_logic;
writing: std_logic;
auto_increment_end_address_reached: std_logic;
secondary_address: unsigned(address_width-1 downto 0);
last_access_cycle_was_a_write: std_logic;
data_out: std_logic_vector(data_width-1 downto 0);
ram_we_n: std_logic;
ram_oe_n: std_logic;
ram_address: unsigned(address_width-1 downto 0);
ram_data: std_logic_vector(data_width-1 downto 0);
drive_data_to_ram: std_logic;
end record;
signal state, next_state: reg_type :=
(
wait_states_counter => (others => '0'),
reading => '0',
writing => '0',
auto_increment_end_address_reached => '0',
secondary_address => (others => '0'),
last_access_cycle_was_a_write => '0',
data_out => (others => '0'),
ram_we_n => '1',
ram_oe_n => '1',
ram_address => (others => '0'),
ram_data => (others => '0'),
drive_data_to_ram => '0'
);
begin
--------------------------------------------------------------------------------
-- State register.
--------------------------------------------------------------------------------
state_register: process is
begin
wait until rising_edge(clk);
state <= next_state;
end process;
--------------------------------------------------------------------------------
-- Next state logic.
--------------------------------------------------------------------------------
next_state_logic: process(state, read, write, auto_increment_address, address, data_in, ram_data) is
variable do_read, do_write: std_logic;
variable last_wait_state, first_drive_data_to_ram_wait_state, first_write_pulse_wait_state: natural;
begin
-- Defaults.
next_state <= state;
next_state.wait_states_counter <= (others => '0');
next_state.ram_we_n <= '1';
next_state.ram_oe_n <= '1';
next_state.drive_data_to_ram <= '0';
if (auto_increment_address = '0') then
next_state.auto_increment_end_address_reached <= '0';
end if;
-- Detect read or write mode.
do_read := '0';
do_write := '0';
-- Enter read or write mode or continue the current mode until it is
-- finished during the last clock cycle of the access cycle.
if (state.reading = '1') then
do_read := '1';
elsif (state.writing = '1') then
do_write := '1';
else
-- Check whether to enter read or write mode or just memorize the secondary address.
if (read = '1' and write = '0') then
do_read := '1';
next_state.reading <= '1';
elsif (read = '0' and write = '1') then
do_write := '1';
next_state.writing <= '1';
elsif (read = '1' and write = '1') then
next_state.secondary_address <= address;
end if;
end if;
-- Determine the timing necessary (we have to wait a little before writing
-- immediately after reading).
first_drive_data_to_ram_wait_state := 0;
last_wait_state := num_of_total_wait_states - 1;
if (do_write = '1' and state.last_access_cycle_was_a_write = '0') then
first_drive_data_to_ram_wait_state := first_drive_data_to_ram_wait_state + num_of_wait_states_before_write_after_read;
last_wait_state := last_wait_state + num_of_wait_states_before_write_after_read;
end if;
first_write_pulse_wait_state := last_wait_state - num_of_write_pulse_wait_states;
-- Forward the address and data to the SRAM at the beginning of the access cycle
-- and the data from the SRAM at the end of the access cycle.
if (do_read = '1' or do_write = '1') then
-- For read access only.
if (do_read = '1') then
next_state.ram_oe_n <= '0';
next_state.last_access_cycle_was_a_write <= '0';
end if;
-- For write access only.
if (do_write = '1') then
-- Take the data at the beginning of the access cycle.
if (state.wait_states_counter = to_unsigned(0, wait_states_counter_width)) then
next_state.ram_data <= data_in;
end if;
if (state.wait_states_counter >= to_unsigned(first_drive_data_to_ram_wait_state, wait_states_counter_width)) then
next_state.drive_data_to_ram <= '1';
end if;
-- For all clock cycles during which the write happens.
if (state.wait_states_counter >= to_unsigned(first_write_pulse_wait_state, wait_states_counter_width)
and state.wait_states_counter < to_unsigned(last_wait_state, wait_states_counter_width)) then
next_state.ram_we_n <= '0';
end if;
end if;
-- For all clock cycles of the access cycle except the last one.
if (state.wait_states_counter /= to_unsigned(last_wait_state, wait_states_counter_width)) then
next_state.wait_states_counter <= state.wait_states_counter + 1;
-- At the beginning of the access cycle, determine the address to access.
if (state.wait_states_counter = to_unsigned(0, wait_states_counter_width)) then
if (auto_increment_address = '0') then
-- Auto-increment mode is not used, just use the the specified address.
next_state.ram_address <= address;
elsif (state.ram_address /= state.secondary_address) then
-- Auto-increment mode is used and we have not reached the specified (end) address,
-- increment the address. By using /= instead of < in the condition, this also works
-- if the address wraps around (i.e. if the start address is higher than the end address).
-- Note that the new address is accessed immediately in the next cycle if the read
-- or write signal is still active.
next_state.ram_address <= state.ram_address + 1;
else
-- Auto-increment mode is used but we have reached the specified (end) address,
-- keep the address from the previous cycle and set the end flag.
next_state.auto_increment_end_address_reached <= '1';
end if;
end if;
-- For the last clock cycle of the access cycle.
else
-- Memorize if this cycle was a write, so the next write can follow immediately.
if (state.writing = '1') then
next_state.last_access_cycle_was_a_write <= '1';
end if;
-- Take the data at the end of the access cycle, reset the reading/writing state.
-- (For write access, the input data are mirrored back as output data.)
next_state.data_out <= ram_data;
next_state.reading <= '0';
next_state.writing <= '0';
next_state.wait_states_counter <= (others => '0');
end if;
end if;
end process;
--------------------------------------------------------------------------------
-- Output logic.
--------------------------------------------------------------------------------
ready <= not state.reading and not state.writing;
auto_increment_end_address_reached <= state.auto_increment_end_address_reached;
data_out <= state.data_out;
ram_we_n <= state.ram_we_n;
ram_oe_n <= state.ram_oe_n;
ram_address <= state.ram_address;
ram_data <= state.ram_data when state.drive_data_to_ram = '1' else (others => 'Z');
end architecture;
|
gpl-3.0
|
27e8f5fad83eb57630bda1c2db949b59
| 0.539576 | 4.266195 | false | false | false | false |
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