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karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/vgd_bitmap_640x480.vhd | 1 | 13,300 | -------------------------------------------------------------------------------
-- Bitmap VGA display with 640x480 pixel resolution
-------------------------------------------------------------------------------
-- V 1.1.2 (2015/11/29)
-- Bertrand Le Gal ([email protected])
-- Some little modifications to support data reading
-- from file for RAM initilization.
--
-- V 1.1.1 (2015/07/28)
-- Yannick Bornat ([email protected])
--
-- For more information on this module, refer to module page :
-- http://bornat.vvv.enseirb.fr/wiki/doku.php?id=en202:vga_bitmap
--
-- V1.1.1 :
-- - Comment additions
-- - Code cleanup
-- V1.1.0 :
-- - added capacity above 3bpp
-- - ability to display grayscale pictures
-- - Module works @ 100MHz clock frequency
-- V1.0.1 :
-- - Fixed : image not centered on screen
-- V1.0.0 :
-- - Initial release
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use std.textio.ALL;
entity VGA_bitmap_640x480 is
generic(bit_per_pixel : integer range 1 to 12:=1; -- number of bits per pixel
grayscale : boolean := false); -- should data be displayed in grayscale
port(clk : in std_logic;
clk_vga : in std_logic;
reset : in std_logic;
VGA_hs : out std_logic; -- horisontal vga syncr.
VGA_vs : out std_logic; -- vertical vga syncr.
VGA_red : out std_logic_vector(3 downto 0); -- red output
VGA_green : out std_logic_vector(3 downto 0); -- green output
VGA_blue : out std_logic_vector(3 downto 0); -- blue output
ADDR : in std_logic_vector(18 downto 0);
data_in : in std_logic_vector(bit_per_pixel - 1 downto 0);
data_write : in std_logic);
--data_out : out std_logic_vector(bit_per_pixel - 1 downto 0));
end VGA_bitmap_640x480;
architecture Behavioral of VGA_bitmap_640x480 is
-- Graphic RAM type. this object is the content of the displayed image
type GRAM is array (0 to 307199) of BIT_vector(bit_per_pixel - 1 downto 0);
impure function ram_function_name (ram_file_name : in string) return GRAM is
FILE ram_file : text is in ram_file_name;
variable line_name : line;
variable ram_name : GRAM;
begin
for I in GRAM'range loop
readline (ram_file, line_name);
read (line_name, ram_name(I));
end loop;
return ram_name;
end function;
signal screen : GRAM;-- := ram_function_name("../mandelbrot.bin"); -- the memory representation of the image
signal h_counter : integer range 0 to 3199:=0; -- counter for H sync. (size depends of frequ because of division)
signal v_counter : integer range 0 to 520 :=0; -- counter for V sync. (base on v_counter, so no frequ issue)
signal TOP_line : boolean := false; -- this signal is true when the current pixel column is visible on the screen
signal TOP_display : boolean := false; -- this signal is true when the current pixel line is visible on the screen
signal pix_read_addr : integer range 0 to 307199:=0; -- the address at which displayed data is read
signal next_pixel : std_logic_vector(bit_per_pixel - 1 downto 0); -- the data coding the value of the pixel to be displayed
begin
-- This process performs data access (read and write) to the memory
--memory_read : process(clk_vga)
--begin
-- if clk_vga'event and clk_vga='1' then
-- next_pixel <= To_StdLogicVector( screen(pix_read_addr) );
-- data_out <= To_StdLogicVector( screen(to_integer(unsigned(ADDR))) );
---- if data_write = '1' then
---- screen(to_integer(unsigned(ADDR))) <= TO_BitVector( data_in );
---- end if;
-- end if;
--end process;
--
--------------------------------------------------------------------------------
process (clk)
begin
if (clk'event and clk = '1') then
-- if (<enableA> = '1') then
if (data_write = '1') then
screen(to_integer(unsigned(ADDR))) <= TO_BitVector( data_in );
end if;
-- data_out <= To_StdLogicVector( screen(to_integer(unsigned(ADDR))) );
-- end if;
end if;
end process;
process (clk_vga)
begin
if (clk_vga'event and clk_vga = '1') then
-- if (<enableB> = '1') then
next_pixel <= To_StdLogicVector( screen(pix_read_addr) );
-- end if;
end if;
end process;
--------------------------------------------------------------------------------
pixel_read_addr : process(clk_vga)
begin
if clk_vga'event and clk_vga='1' then
if reset = '1' or (not TOP_display) then
pix_read_addr <= 0;
elsif TOP_line and (h_counter mod 4)=0 then
pix_read_addr <= pix_read_addr + 1;
elsif (pix_read_addr = 307199) then
pix_read_addr <= 0;
end if;
end if;
end process;
-- this process manages the horizontal synchro using the counters
process(clk_vga)
begin
if clk_vga'event and clk_vga='1' then
if reset = '1' then
VGA_vs <= '0';
TOP_display <= false;
else
case v_counter is
when 0 => VGA_vs <= '0'; -- start of Tpw ( 0 -> 0 + 1)
when 2 => VGA_vs <= '1'; -- start of Tbp ( 2 -> 2 + 28 = 30)
when 31 => TOP_display <= true; -- start of Tdisp ( 31 -> 31 + 479 = 510)
when 511 => TOP_display <= false; -- start of Tfp (511 -> 511 + 9 = 520)
when others => null;
end case;
-- if v_counter = 0 then VGA_vs <= '0'; -- start of Tpw ( 0 -> 0 + 1)
-- elsif v_counter = 2 then VGA_vs <= '1'; -- start of Tbp ( 2 -> 2 + 28 = 30)
-- elsif v_counter = 75 then TOP_display <= true; -- start of Tdisp ( 31 -> 31 + 479 = 510)
-- elsif v_counter = 475 then TOP_display <= false; -- start of Tfp (511 -> 511 + 9 = 520)
-- end if;
end if;
end if;
end process;
process(clk_vga)
begin
if clk_vga'event and clk_vga='1' then
if (not TOP_line) or (not TOP_display) then
VGA_red <= "0000";
VGA_green <= "0000";
VGA_blue <= "0000";
else
case bit_per_pixel is
when 1 =>
VGA_red <= (others => next_pixel(0));
VGA_green <= (others => next_pixel(0));
VGA_blue <= (others => next_pixel(0));
when 2 =>
if grayscale then
VGA_blue <= next_pixel & next_pixel;
VGA_green <= next_pixel & next_pixel;
VGA_red <= next_pixel & next_pixel;
else
VGA_red <= (others => (next_pixel(0) and next_pixel(1)));
VGA_green <= (others => (next_pixel(1) and not next_pixel(0)));
VGA_blue <= (others => (next_pixel(0) and not next_pixel(1)));
end if;
when 3 =>
if grayscale then
VGA_blue <= next_pixel & next_pixel(bit_per_pixel - 1);
VGA_green <= next_pixel & next_pixel(bit_per_pixel - 1);
VGA_red <= next_pixel & next_pixel(bit_per_pixel - 1);
else
VGA_red <= (others => next_pixel(2));
VGA_green <= (others => next_pixel(1));
VGA_blue <= (others => next_pixel(0));
end if;
when 4 =>
if grayscale then
VGA_blue <= next_pixel;
VGA_green <= next_pixel;
VGA_red <= next_pixel;
elsif next_pixel="1000" then
VGA_red <= "0100";
VGA_green <= "0100";
VGA_blue <= "0100";
else
VGA_red(2 downto 0) <= (others => (next_pixel(2) and next_pixel(3)));
VGA_green(2 downto 0) <= (others => (next_pixel(1) and next_pixel(3)));
VGA_blue(2 downto 0) <= (others => (next_pixel(0) and next_pixel(3)));
VGA_red(3) <= next_pixel(2);
VGA_green(3) <= next_pixel(1);
VGA_blue(3) <= next_pixel(0);
end if;
when 5 =>
case to_integer(unsigned(next_pixel)) is
when 0 | 3 | 6 | 9 | 12 | 15 | 18 | 21 | 24 => VGA_blue <= "0000";
when 1 | 4 | 7 | 10 | 13 | 16 | 19 | 22 | 25 => VGA_blue <= "1000";
when others => VGA_blue <= "1111";
end case;
case to_integer(unsigned(next_pixel)) is
when 0 | 1 | 2 | 9 | 10 | 11 | 18 | 19 | 20 => VGA_green <= "0000";
when 3 | 4 | 5 | 12 | 13 | 14 | 21 | 22 | 23 => VGA_green <= "1000";
when others => VGA_green <= "1111";
end case;
case to_integer(unsigned(next_pixel)) is
when 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 => VGA_red <= "0000";
when 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 => VGA_red <= "1000";
when others => VGA_red <= "1111";
end case;
when 6 =>
VGA_red <= next_pixel(5 downto 4) & next_pixel(5 downto 4);
VGA_green <= next_pixel(3 downto 2) & next_pixel(3 downto 2);
VGA_blue <= next_pixel(1 downto 0) & next_pixel(1 downto 0);
when 7 =>
VGA_red <= next_pixel(6 downto 5) & next_pixel(6 downto 5);
VGA_green <= next_pixel(4 downto 2) & next_pixel(4);
VGA_blue <= next_pixel(1 downto 0) & next_pixel(1 downto 0);
when 8 =>
VGA_red <= next_pixel(7 downto 5) & next_pixel(7);
VGA_green <= next_pixel(4 downto 2) & next_pixel(4);
VGA_blue <= next_pixel(1 downto 0) & next_pixel(1 downto 0);
when 9 =>
VGA_red <= next_pixel(8 downto 6) & next_pixel(8);
VGA_green <= next_pixel(5 downto 3) & next_pixel(5);
VGA_blue <= next_pixel(2 downto 0) & next_pixel(2);
when 10 =>
VGA_red <= next_pixel(9 downto 7) & next_pixel(9);
VGA_green <= next_pixel(6 downto 3);
VGA_blue <= next_pixel(2 downto 0) & next_pixel(2);
when 11 =>
VGA_red <= next_pixel(10 downto 7);
VGA_green <= next_pixel( 6 downto 3);
VGA_blue <= next_pixel( 2 downto 0) & next_pixel(2);
when 12 =>
VGA_red <= next_pixel(11 downto 8);
VGA_green <= next_pixel( 7 downto 4);
VGA_blue <= next_pixel( 3 downto 0);
end case;
end if;
end if;
end process;
-- this process manages the horizontal synchro using the counters
process(clk_vga)
begin
if clk_vga'event and clk_vga='1' then
if reset = '1' then
VGA_hs <= '0';
TOP_line <= false;
else
case h_counter is
when 2 => VGA_hs <= '0'; -- start of Tpw ( 0 -> 0 + 95) -- +2 because of delay in RAM
when 386 => VGA_hs <= '1'; -- start of Tbp ( 96 -> 96 + 47 = 143) -- 384=96*4 -- -- +2 because of delay in RAM
when 576 => TOP_line <= true; -- start of Tdisp ( 144 -> 144 + 639 = 783) -- 576=144*4
when 3136 => TOP_line <= false; -- start of Tfp ( 784 -> 784 + 15 = 799) -- 3136 = 784*4
when others => null;
end case;
-- if h_counter=2 then VGA_hs <= '0'; -- start of Tpw ( 0 -> 0 + 95) -- +2 because of delay in RAM
-- elsif h_counter=386 then VGA_hs <= '1'; -- start of Tbp ( 96 -> 96 + 47 = 143) -- 384=96*4 -- -- +2 because of delay in RAM
-- elsif h_counter=576 then TOP_line <= true; -- start of Tdisp ( 144 -> 144 + 639 = 783) -- 576=144*4
-- elsif h_counter=3136 then TOP_line <= false; -- start of Tfp ( 784 -> 784 + 15 = 799) -- 3136 = 784*4
-- end if;
end if;
end if;
end process;
-- counter management for synchro
process(clk_vga)
begin
if clk_vga'event and clk_vga='1' then
if reset='1' then
h_counter <= 0;
v_counter <= 0;
else
if h_counter = 3199 then
h_counter <= 0;
if v_counter = 520 then
v_counter <= 0;
else
v_counter <= v_counter + 1;
end if;
else
h_counter <= h_counter +1;
end if;
end if;
end if;
end process;
end Behavioral; | gpl-3.0 | bb42172a994baba68c3361df9c073172 | 0.474361 | 3.722362 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Ram/example_design/Ram_exdes.vhd | 1 | 4,746 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Ram_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY Ram_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END Ram_exdes;
ARCHITECTURE xilinx OF Ram_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT Ram IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : Ram
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
| mit | 300ac1cddc5b0561cacbe0e3efa95b6a | 0.546144 | 4.585507 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/custom/mandelbrot/vga_bitmap_640x480_single_port.vhd | 1 | 13,899 | -------------------------------------------------------------------------------
-- Bitmap VGA display with 640x480 pixel resolution
-------------------------------------------------------------------------------
-- V 1.1.2 (2015/11/29)
-- Bertrand Le Gal ([email protected])
-- Some little modifications to support data reading
-- from file for RAM initilization.
--
-- V 1.1.1 (2015/07/28)
-- Yannick Bornat ([email protected])
--
-- For more information on this module, refer to module page :
-- http://bornat.vvv.enseirb.fr/wiki/doku.php?id=en202:vga_bitmap
--
-- V1.1.1 :
-- - Comment additions
-- - Code cleanup
-- V1.1.0 :
-- - added capacity above 3bpp
-- - ability to display grayscale pictures
-- - Module works @ 100MHz clock frequency
-- V1.0.1 :
-- - Fixed : image not centered on screen
-- V1.0.0 :
-- - Initial release
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use std.textio.ALL;
entity VGA_bitmap_640x480 is
port(clk : in std_logic;
clk_vga : in std_logic;
reset : in std_logic;
VGA_hs : out std_logic; -- horisontal vga syncr.
VGA_vs : out std_logic; -- vertical vga syncr.
iter : out std_logic_vector(7 downto 0); -- iter output
ADDR1 : in std_logic_vector(15 downto 0);
data_in1 : in std_logic_vector(7 downto 0);
data_write1 : in std_logic;
ADDR2 : in std_logic_vector(15 downto 0);
data_in2 : in std_logic_vector(7 downto 0);
data_write2 : in std_logic;
ADDR3 : in std_logic_vector(15 downto 0);
data_in3 : in std_logic_vector(7 downto 0);
data_write3 : in std_logic;
ADDR4 : in std_logic_vector(15 downto 0);
data_in4 : in std_logic_vector(7 downto 0);
data_write4 : in std_logic;
ADDR5 : in std_logic_vector(15 downto 0);
data_in5 : in std_logic_vector(7 downto 0);
data_write5 : in std_logic;
ADDR6 : in std_logic_vector(15 downto 0);
data_in6 : in std_logic_vector(7 downto 0);
data_write6 : in std_logic;
ADDR7 : in std_logic_vector(15 downto 0);
data_in7 : in std_logic_vector(7 downto 0);
data_write7 : in std_logic;
ADDR8 : in std_logic_vector(15 downto 0);
data_in8 : in std_logic_vector(7 downto 0);
data_write8 : in std_logic);
end VGA_bitmap_640x480;
architecture Behavioral of VGA_bitmap_640x480 is
component RAM_single_port
Port ( clk : in STD_LOGIC;
data_write : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(7 downto 0);
ADDR : in STD_LOGIC_VECTOR (15 downto 0);
data_out : out STD_LOGIC_VECTOR (7 downto 0));
end component;
signal h_counter : integer range 0 to 3199:=0; -- counter for H sync. (size depends of frequ because of division)
signal v_counter : integer range 0 to 520 :=0; -- counter for V sync. (base on v_counter, so no frequ issue)
signal TOP_line : boolean := false; -- this signal is true when the current pixel column is visible on the screen
signal TOP_display : boolean := false; -- this signal is true when the current pixel line is visible on the screen
signal pix_read_addr : integer range 0 to 307199:=0; -- the address at which displayed data is read
signal pix_read_addr1, pix_read1 : integer range 0 to 38399:=0; -- the address at which displayed data is read
--signal next_pixel,next_pixel1,next_pixel2 : std_logic_vector(3 downto 0); -- the data coding the value of the pixel to be displayed
signal pix_read_addrb : integer range 0 to 38399 := 0; -- the address at which displayed data is read
signal next_pixel1, data_temp1, data_temp2 , data_outtemp1, data_outtemp2,data_temp3, data_temp4 , data_outtemp3, data_outtemp4, data_temp5, data_temp6 , data_outtemp5, data_outtemp6,data_temp7, data_temp8 , data_outtemp7, data_outtemp8 : std_logic_vector(7 downto 0); -- the data coding the value of the pixel to be displayed
signal next_pixel2 : std_logic_vector(7 downto 0); -- the data coding the value of the pixel to be displayed
signal next_pixel : std_logic_vector(7 downto 0); -- the data coding the value of the pixel to be displayed
--signal data_writetemp1, data_writetemp2 : std_logic;
signal ADDRtemp1, ADDRtemp2, ADDRtemp3, ADDRtemp4, ADDRtemp5, ADDRtemp6, ADDRtemp7, ADDRtemp8 : std_logic_vector(15 downto 0); -- the data coding the value of the pixel to be displayed
begin
--------------------------------------------------------------------------------
RAM1: RAM_single_port
port map (clk,
data_write1,
data_in1,
ADDRtemp1,
data_outtemp1);
RAM2: RAM_single_port
port map (clk,
data_write2,
data_in2,
ADDRtemp2,
data_outtemp2);
RAM3: RAM_single_port
port map (clk,
data_write3,
data_in3,
ADDRtemp3,
data_outtemp3);
RAM4: RAM_single_port
port map (clk,
data_write4,
data_in4,
ADDRtemp4,
data_outtemp4);
RAM5: RAM_single_port
port map (clk,
data_write5,
data_in5,
ADDRtemp5,
data_outtemp5);
RAM6: RAM_single_port
port map (clk,
data_write6,
data_in6,
ADDRtemp6,
data_outtemp6);
--RAM7: RAM_single_port
--port map (clk,
-- data_write7,
-- data_in7,
-- ADDRtemp7,
-- data_outtemp7);
--
--RAM8: RAM_single_port
--port map (clk,
-- data_write8,
-- data_in8,
-- ADDRtemp8,
-- data_outtemp8);
-- pix_read_addrb <= pix_read_addr when pix_read_addr < 153599 else pix_read_addr - 153599;
ADDRtemp1<= ADDR1 when (data_write1 = '1') else std_logic_vector(to_unsigned(pix_read1, 16)) ;
ADDRtemp2<= ADDR2 when (data_write2 = '1') else std_logic_vector(to_unsigned(pix_read1, 16)) ;
ADDRtemp3<= ADDR3 when (data_write3 = '1') else std_logic_vector(to_unsigned(pix_read1, 16)) ;
ADDRtemp4<= ADDR4 when (data_write4 = '1') else std_logic_vector(to_unsigned(pix_read1, 16)) ;
ADDRtemp5<= ADDR5 when (data_write5 = '1') else std_logic_vector(to_unsigned(pix_read1, 16)) ;
ADDRtemp6<= ADDR6 when (data_write6 = '1') else std_logic_vector(to_unsigned(pix_read1, 16)) ;
ADDRtemp7<= ADDR7 when (data_write7 = '1') else std_logic_vector(to_unsigned(pix_read1, 16)) ;
ADDRtemp8<= ADDR8 when (data_write8 = '1') else std_logic_vector(to_unsigned(pix_read1, 16)) ;
--data_writetemp1 <= clk_VGA when (data_write1 = '0') else '1' ;
--data_writetemp2 <= clk_VGA when (data_write2 = '0') else '1' ;
-- process (clk)
-- begin
-- if (clk'event and clk = '1') then
-- if (data_write1 = '1') then
-- screen1(to_integer(unsigned(ADDR1))) <= data_in1 ;
-- end if;
-- end if;
-- end process;
--
-- process (clk_vga)
-- begin
-- if (clk_vga'event and clk_vga = '1') then
-- next_pixel1 <= screen1(pix_read_addrb) ;
-- end if;
-- end process;
--
-- process (clk)
-- begin
-- if (clk'event and clk = '1') then
-- if (data_write2 = '1') then
-- screen2(to_integer(unsigned(ADDR2))) <= data_in2 ;
-- end if;
-- end if;
-- end process;
--
-- process (clk_vga)
-- begin
-- if (clk_vga'event and clk_vga = '1') then
-- next_pixel2 <= screen2(pix_read_addrb);
-- end if;
-- end process;
process (clk_vga)
begin
if (clk_vga'event and clk_vga = '1') then
IF pix_read_addr < 38399 THEN
next_pixel <= data_outtemp1;
ELSif pix_read_addr < 76799 THEN
next_pixel <= data_outtemp2;
ELSif pix_read_addr < 115199 THEN
next_pixel <= data_outtemp3;
ELSif pix_read_addr < 153599 THEN
next_pixel <= data_outtemp4;
ELSif pix_read_addr < 191999 THEN
next_pixel <= data_outtemp5;
ELSif pix_read_addr < 230399 THEN
next_pixel <= data_outtemp6;
-- ELSif pix_read_addr < 230399 THEN
-- next_pixel <= data_outtemp7;
else
next_pixel <= (others=>'0');
END IF;
end if;
end process;
--process (clk_vga)
--begin
-- if (clk_vga'event and clk_vga = '1') then
-- if (data_write1 = '1') then
-- screen1(to_integer(unsigned(ADDR1))) <= data_in1;
-- next_pixel1 <= data_in1;
-- else
-- next_pixel1 <= screen1(to_integer(unsigned(ADDR1)));
-- end if;
-- end if;
--end process;
--
--process (clk_vga)
--begin
-- if (clk_vga'event and clk_vga = '1') then
-- if (data_write2 = '1') then
-- screen2(to_integer(unsigned(ADDR2))) <= data_in2;
-- next_pixel2 <= data_in2;
-- else
-- next_pixel2 <= screen2(to_integer(unsigned(ADDR2));
-- end if;
-- end if;
--end process;
--process (next_pixel)
--begin
-- if (clk_vga'event and clk_vga = '1') then
-- next_pixel <= To_StdLogicVector( ram_out(pix_read_addr) );
-- end if;
--end process;
--ram_out <= screen1 when to_unsigned(pix_read_addr,16)(15) = '0' else screen2;
--------------------------------------------------------------------------------
--proc<='0' when (pix_read_addr <153599) else '1';
pixel_read_addr : process(clk_vga, clk)
begin
if clk_vga'event and clk_vga='1' then
if reset = '1' or (not TOP_display) then
pix_read_addr <= 0;
elsif TOP_line and (h_counter mod 4)=0 then
pix_read_addr <= pix_read_addr + 1;
elsif (pix_read_addr = 307199) then
pix_read_addr <= 0;
end if;
end if;
end process;
pixel_read1 : process(clk_vga, clk)
begin
if clk_vga'event and clk_vga='1' then
if reset = '1' or (not TOP_display) then
pix_read1 <= 0;
elsif TOP_line and (h_counter mod 4)=0 then
pix_read1 <= pix_read1 + 1;
elsif (pix_read1 = 38399) then
pix_read1 <= 0;
end if;
end if;
end process;
--pixel_read_addrb : process(clk_vga, clk)
--begin
-- if clk_vga'event and clk_vga='1' then
-- if reset = '1' or (not TOP_display) then
-- pix_read_addrb <= 0;
-- elsif TOP_line and (h_counter mod 4)=0 then
-- pix_read_addrb <= pix_read_addrb + 1;
-- elsif (pix_read_addrb = 153599) then
-- pix_read_addrb <= 0;
-- end if;
-- end if;
--end process;
--process(pix_read_addr)
--begin
-- if pix_read_addr < 153599 then
-- ram_number <= '0';
-- elsif pix_read_addr <307199 then
-- ram_number <= '1';
-- else
-- ram_number <= '0';
-- end if;
--end process;
-- this process manages the horizontal synchro using the counters
process(clk_vga)
begin
if clk_vga'event and clk_vga='1' then
if reset = '1' then
VGA_vs <= '0';
TOP_display <= false;
else
case v_counter is
when 0 => VGA_vs <= '0'; -- start of Tpw ( 0 -> 0 + 1)
when 2 => VGA_vs <= '1'; -- start of Tbp ( 2 -> 2 + 28 = 30)
when 31 => TOP_display <= true; -- start of Tdisp ( 31 -> 31 + 479 = 510)
when 511 => TOP_display <= false; -- start of Tfp (511 -> 511 + 9 = 520)
when others => null;
end case;
-- if v_counter = 0 then VGA_vs <= '0'; -- start of Tpw ( 0 -> 0 + 1)
-- elsif v_counter = 2 then VGA_vs <= '1'; -- start of Tbp ( 2 -> 2 + 28 = 30)
-- elsif v_counter = 75 then TOP_display <= true; -- start of Tdisp ( 31 -> 31 + 479 = 510)
-- elsif v_counter = 475 then TOP_display <= false; -- start of Tfp (511 -> 511 + 9 = 520)
-- end if;
end if;
end if;
end process;
process(clk_vga)
begin
if clk_vga'event and clk_vga='1' then
if (not TOP_line) or (not TOP_display) then
iter <= "00000000";
else
iter<= next_pixel;
end if;
end if;
end process;
-- this process manages the horizontal synchro using the counters
process(clk_vga)
begin
if clk_vga'event and clk_vga='1' then
if reset = '1' then
VGA_hs <= '0';
TOP_line <= false;
else
case h_counter is
when 2 => VGA_hs <= '0'; -- start of Tpw ( 0 -> 0 + 95) -- +2 because of delay in RAM
when 386 => VGA_hs <= '1'; -- start of Tbp ( 96 -> 96 + 47 = 143) -- 384=96*4 -- -- +2 because of delay in RAM
when 576 => TOP_line <= true; -- start of Tdisp ( 144 -> 144 + 639 = 783) -- 576=144*4
when 3136 => TOP_line <= false; -- start of Tfp ( 784 -> 784 + 15 = 799) -- 3136 = 784*4
when others => null;
end case;
-- if h_counter=2 then VGA_hs <= '0'; -- start of Tpw ( 0 -> 0 + 95) -- +2 because of delay in RAM
-- elsif h_counter=386 then VGA_hs <= '1'; -- start of Tbp ( 96 -> 96 + 47 = 143) -- 384=96*4 -- -- +2 because of delay in RAM
-- elsif h_counter=576 then TOP_line <= true; -- start of Tdisp ( 144 -> 144 + 639 = 783) -- 576=144*4
-- elsif h_counter=3136 then TOP_line <= false; -- start of Tfp ( 784 -> 784 + 15 = 799) -- 3136 = 784*4
-- end if;
end if;
end if;
end process;
-- counter management for synchro
process(clk_vga)
begin
if clk_vga'event and clk_vga='1' then
if reset='1' then
h_counter <= 0;
v_counter <= 0;
else
if h_counter = 3199 then
h_counter <= 0;
if v_counter = 520 then
v_counter <= 0;
else
v_counter <= v_counter + 1;
end if;
else
h_counter <= h_counter +1;
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | e99f28c9b9c0de8c20ce3a82918f4713 | 0.554141 | 3.174737 | false | false | false | false |
chibby0ne/vhdl-book | Chapter9/my_component_dir/my_component.vhd | 1 | 1,199 | --!
--! @file: my_component.vhd
--! @brief: min_max package
--! @author: Antonio Gutierrez
--! @date: 2013-11-27
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
package my_component is
procedure min_max(a, b, c : in integer; min, max: out integer)
end package my_component;
------------------------------
package body my_component is
procedure min_max(signal a, b, c : in integer; signal min, max: out integer)
begin
if (a >= b) then
if (a >= c) then
max <= a;
if (b >= c) then
min <= c;
end if;
else
max <= c;
min <= b;
end if;
else
if (b >= c) then
max <= b;
if (a >= c) then
min <= c;
else
min <= a;
end if;
else
max <= c;
min <= a;
end if;
end if;
end procedure min_max;
end package body my_component;
--------------------------------------
| gpl-3.0 | fcf2ad22a009c922b8dacd9457e84b4d | 0.373645 | 4.408088 | false | false | false | false |
siam28/neppielight | averager.vhd | 2 | 6,662 | ----------------------------------------------------------------------------------
-- Engineer: [email protected]
--
-- Create Date: 22:35:50 01/09/2015
-- Design Name: HDMI block averager
-- Module Name: - Behavioral
-- Project Name: Neppielight
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity averager is
Port (
clk_pixel : IN std_logic;
--
i_red : IN std_logic_vector(7 downto 0);
i_green : IN std_logic_vector(7 downto 0);
i_blue : IN std_logic_vector(7 downto 0);
i_blank : IN std_logic;
i_hsync : IN std_logic;
i_vsync : IN std_logic;
--
framebuffer : OUT std_logic_vector(0 to 25*24-1);
o_red : OUT std_logic_vector(7 downto 0);
o_green : OUT std_logic_vector(7 downto 0);
o_blue : OUT std_logic_vector(7 downto 0);
o_blank : OUT std_logic;
o_hsync : OUT std_logic;
o_vsync : OUT std_logic);
end averager;
architecture Behavioral of averager is
-------------------------
-- Part of the pipeline
-------------------------
signal a_red : std_logic_vector(7 downto 0);
signal a_green : std_logic_vector(7 downto 0);
signal a_blue : std_logic_vector(7 downto 0);
signal a_blank : std_logic;
signal a_hsync : std_logic;
signal a_vsync : std_logic;
-------------------------------
-- Counters for screen position
-------------------------------
signal x : STD_LOGIC_VECTOR (10 downto 0);
signal y : STD_LOGIC_VECTOR (10 downto 0);
constant nblocks : integer := 25;
-- signal pixel : std_logic_vector(23 downto 0) := (others => '0');
type accumulator_type is array (0 to nblocks-1,0 to 3) of std_logic_vector(21 downto 0);
signal accumulator : accumulator_type;
--signal blocknr : integer range 0 to 10;
type blockcoords_type is array (0 to nblocks-1) of integer;
-- Due to the details of the construction, we start in the lower left corner
-- and work our way clockwise.
-- Laterally, we've got more leds than pixels, so we'll have partially verlapping boxes.
constant startx : blockcoords_type := ( 0, 0, 0, 0, 0,0,144,288,432,576,720,864,1008,1152,1152,1152,1152,1152,1152,987,823,658,494,329,164);
constant starty : blockcoords_type := (592,472,356,238,118,0, 0, 0, 0, 0, 0, 0, 0, 0, 118, 238, 356, 472, 592,592,592,592,592,592,592);
type gamma_lut_type is array ( 0 to 255) of std_logic_vector(7 downto 0);
constant gamma_lut : gamma_lut_type := (
X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01",
X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"02", X"02", X"02", X"02", X"02", X"02",
X"02", X"02", X"02", X"02", X"02", X"03", X"03", X"03", X"03", X"03", X"03", X"03", X"03", X"04",
X"04", X"04", X"04", X"04", X"05", X"05", X"05", X"05", X"05", X"06", X"06", X"06", X"06", X"06",
X"07", X"07", X"07", X"08", X"08", X"08", X"08", X"09", X"09", X"09", X"0A", X"0A", X"0A", X"0B",
X"0B", X"0B", X"0C", X"0C", X"0D", X"0D", X"0D", X"0E", X"0E", X"0F", X"0F", X"0F", X"10", X"10",
X"11", X"11", X"12", X"12", X"13", X"13", X"14", X"14", X"15", X"15", X"16", X"17", X"17", X"18",
X"18", X"19", X"19", X"1A", X"1B", X"1B", X"1C", X"1D", X"1D", X"1E", X"1F", X"1F", X"20", X"21",
X"21", X"22", X"23", X"24", X"24", X"25", X"26", X"27", X"28", X"28", X"29", X"2A", X"2B", X"2C",
X"2D", X"2D", X"2E", X"2F", X"30", X"31", X"32", X"33", X"34", X"35", X"36", X"37", X"38", X"39",
X"3A", X"3B", X"3C", X"3D", X"3E", X"3F", X"40", X"41", X"42", X"43", X"44", X"46", X"47", X"48",
X"49", X"4A", X"4B", X"4D", X"4E", X"4F", X"50", X"51", X"53", X"54", X"55", X"57", X"58", X"59",
X"5A", X"5C", X"5D", X"5F", X"60", X"61", X"63", X"64", X"66", X"67", X"68", X"6A", X"6B", X"6D",
X"6E", X"70", X"71", X"73", X"74", X"76", X"78", X"79", X"7B", X"7C", X"7E", X"80", X"81", X"83",
X"85", X"86", X"88", X"8A", X"8B", X"8D", X"8F", X"91", X"92", X"94", X"96", X"98", X"9A", X"9B",
X"9D", X"9F", X"A1", X"A3", X"A5", X"A7", X"A9", X"AB", X"AD", X"AF", X"B1", X"B3", X"B5", X"B7",
X"B9", X"BB", X"BD", X"BF", X"C1", X"C3", X"C5", X"C7", X"CA", X"CC", X"CE", X"D0", X"D2", X"D5",
X"D7", X"D9", X"DB", X"DE", X"E0", X"E2", X"E4", X"E7", X"E9", X"EC", X"EE", X"F0", X"F3", X"F5",
X"F8", X"FA", X"FD", X"FF");
begin
process(clk_pixel)
variable blockedge : std_logic := '0';
begin
if rising_edge(clk_pixel) then
for bn in 0 to nblocks-1 loop
if unsigned(x) >= startx(bn) and unsigned(x) < startx(bn)+128 and
unsigned(y) >= starty(bn) and unsigned(y) < starty(bn)+128 then
-- We are a part of block bn. Accumulate the color info.
accumulator(bn,0) <= std_logic_vector(unsigned(accumulator(bn,0)) + unsigned(a_red));
accumulator(bn,1) <= std_logic_vector(unsigned(accumulator(bn,1)) + unsigned(a_green));
accumulator(bn,2) <= std_logic_vector(unsigned(accumulator(bn,2)) + unsigned(a_blue));
end if;
end loop;
-- debug, mark the block corners in red
-- blockedge := '0';
-- for bn in 0 to nblocks-1 loop
-- if (unsigned(x) = startx(bn) or unsigned(x) = startx(bn)+128) and
-- (unsigned(y) = starty(bn) or unsigned(y) = starty(bn)+128) then
-- blockedge := '1';
-- end if;
-- end loop;
--
-- if blockedge = '0' then
o_red <= a_red;
o_green <= a_green;
o_blue <= a_blue;
-- else
-- o_red <= X"FF";
-- o_green <= X"00";
-- o_blue <= X"00";
-- end if;
o_blank <= a_blank;
o_hsync <= a_hsync;
o_vsync <= a_vsync;
a_red <= i_red;
a_green <= i_green;
a_blue <= i_blue;
a_blank <= i_blank;
a_hsync <= i_hsync;
a_vsync <= i_vsync;
-- Working out where we are in the screen..
if i_vsync /= a_vsync then
y <= (others => '0');
if i_vsync = '1' then
for i in 0 to nblocks-1 loop
for c in 0 to 2 loop
framebuffer(c * 8 + i * 24 to i * 24 + c * 8 + 7) <= gamma_lut(to_integer(unsigned(accumulator(i,c)(21 downto 14))));
accumulator(i,c) <= (others => '0');
end loop;
end loop;
end if;
end if;
if i_blank = '0' then
x <= std_logic_vector(unsigned(x) + 1);
end if;
-- Start of the blanking interval?
if a_blank = '0' and i_blank = '1' then
y <= std_logic_vector(unsigned(y) + 1);
x <= (others => '0');
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | 486158f58d5f3a2af5e10c7148210fca | 0.511108 | 2.457396 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/MMX/MMX_MAX_8b.vhd | 1 | 1,778 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library ims;
--use ims.coprocessor.all;
entity MMX_MAX_8b is
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end;
architecture rtl of MMX_MAX_8b is
begin
-------------------------------------------------------------------------
-- synthesis translate_off
process
begin
wait for 1 ns;
REPORT "(IMS) MMX 8bis MAX RESSOURCE : ALLOCATION OK !";
wait;
end process;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : STD_LOGIC_VECTOR(7 downto 0);
variable rTemp2 : STD_LOGIC_VECTOR(7 downto 0);
variable rTemp3 : STD_LOGIC_VECTOR(7 downto 0);
variable rTemp4 : STD_LOGIC_VECTOR(7 downto 0);
begin
if( UNSIGNED(INPUT_1( 7 downto 0)) > UNSIGNED(INPUT_2( 7 downto 0)) ) then rTemp1 := INPUT_1( 7 downto 0); else rTemp1 := INPUT_2( 7 downto 0); end if;
if( UNSIGNED(INPUT_1(15 downto 8)) > UNSIGNED(INPUT_2(15 downto 8)) ) then rTemp2 := INPUT_1(15 downto 8); else rTemp2 := INPUT_2(15 downto 8); end if;
if( UNSIGNED(INPUT_1(23 downto 16)) > UNSIGNED(INPUT_2(23 downto 16)) ) then rTemp3 := INPUT_1(23 downto 16); else rTemp3 := INPUT_2(23 downto 16); end if;
if( UNSIGNED(INPUT_1(31 downto 24)) > UNSIGNED(INPUT_2(31 downto 24)) ) then rTemp4 := INPUT_1(31 downto 24); else rTemp4 := INPUT_2(31 downto 24); end if;
OUTPUT_1 <= (rTemp4 & rTemp3 & rTemp2 & rTemp1);
end process;
-------------------------------------------------------------------------
end;
| gpl-3.0 | 8b48e22bf8d588d2edfc26f0eb7b1bb2 | 0.556243 | 3.323364 | false | false | false | false |
mohamed/tdm-hw-arbiter | tdm_arbiter.vhd | 1 | 2,138 | -- TDM with RR Arbiter
-- Author: Mohamed A. Bamakhrama <[email protected]>
-- Copyrights (c) 2009-2014 by Leiden University, The Netherlands
-- Description:
-- This arbiter implements TDM+RR arbitration between active transmitters.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tdm_arbiter_pkg.all;
entity tdm_arbiter is
port
(
clk : in std_logic;
reset_n : in std_logic;
hold : in std_logic;
exists : in std_logic_vector(NUM_OF_FIFOS-1 downto 0);
read : out std_logic_vector(NUM_OF_FIFOS-1 downto 0)
);
end tdm_arbiter;
architecture rtl of tdm_arbiter is
signal grant_r : std_logic_vector(NUM_OF_FIFOS downto 0);
signal grant_i : std_logic_vector(NUM_OF_FIFOS downto 0);
signal grant_hold_i : std_logic_vector(NUM_OF_FIFOS downto 0);
signal bypass : std_logic_vector(NUM_OF_FIFOS downto 0);
signal nored_present : std_logic;
begin
nor_reduc: process(exists)
begin
nored_present <= nor_reduce(exists);
end process;
stages: for i in 0 to NUM_OF_FIFOS generate
x: if i = 0 generate
grant_i(i) <= grant_r(NUM_OF_FIFOS) or bypass(NUM_OF_FIFOS) when exists(i) = '1' else '0';
bypass(i) <= grant_r(NUM_OF_FIFOS) or bypass(NUM_OF_FIFOS) when exists(i) = '0' else '0';
end generate;
y: if i > 0 and i < NUM_OF_FIFOS generate
grant_i(i) <= grant_r(i - 1) or bypass(i - 1) when exists(i) = '1' else '0';
bypass(i) <= grant_r(i - 1) or bypass(i - 1) when exists(i) = '0' else '0';
end generate;
z: if i = NUM_OF_FIFOS generate
grant_i(i) <= grant_r(i - 1) or bypass(i - 1) when nored_present = '1' else '0';
bypass(i) <= grant_r(i - 1) or bypass(i - 1) when nored_present = '0' else '0';
end generate;
end generate;
read <= grant_r(NUM_OF_FIFOS-1 downto 0) and exists;
grant_hold_i <= grant_r when (hold = '1') else grant_i;
registers: process(clk, reset_n)
begin
if (reset_n = '0') then
grant_r <= (NUM_OF_FIFOS => '1', others => '0');
elsif rising_edge(clk) then
grant_r <= grant_hold_i;
end if;
end process;
end rtl;
| bsd-3-clause | b75f58312a9bd893e2175e7a6bb08d8e | 0.63985 | 2.692695 | false | false | false | false |
chibby0ne/vhdl-book | Chapter11/example3_dir/testbench/counter_tb.vhd | 1 | 2,135 | --!
--! Copyright (C) 2010 - 2013 Creonic GmbH
--!
--! @file: counter_tb.vhd
--! @brief: tb of counter
--! @author: Antonio Gutierrez
--! @date: 2014-05-23
--!
--!
--------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------
entity counter_tb is
generic (PERIOD: time := 40 ns;
PD: time := 3 ns);
end entity counter_tb;
--------------------------------------------------------
architecture circuit of counter_tb is
--------------------------------------------------------
-- component declaration
--------------------------------------------------------
component counter is
port (
clk, rst: in std_logic;
output: out natural range 0 to 9);
end component counter;
--------------------------------------------------------
-- signal declaration
--------------------------------------------------------
signal clk_tb: std_logic := '0';
signal rst_tb: std_logic := '1';
signal output_tb: natural range 0 to 9 := 0;
begin
--------------------------------------------------------
-- component instantiation
--------------------------------------------------------
dut: counter port map (
clk => clk_tb,
rst => rst_tb,
output => output_tb
);
--------------------------------------------------------
-- stimuli generation
--------------------------------------------------------
-- rst
process
begin
rst_tb <= '1';
wait for PERIOD;
rst_tb <= '0';
wait;
end process;
-- clk
clk_tb <= not clk_tb after PERIOD / 2;
--------------------------------------------------------------------------------------
-- stop simulation
--------------------------------------------------------------------------------------
process
begin
wait for PERIOD * 10;
assert false
report "simulation end"
severity failure;
end process;
end architecture circuit;
| gpl-3.0 | 126b68136978d1fa8ecc69765faf1d28 | 0.340047 | 5.997191 | false | false | false | false |
VLSI-EDA/UVVM_All | bitvis_vip_axilite/src/vvc_context.vhd | 1 | 1,412 | --========================================================================================================================
-- Copyright (c) 2018 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
context vvc_context is
library bitvis_vip_axilite;
use bitvis_vip_axilite.vvc_cmd_pkg.all;
use bitvis_vip_axilite.vvc_methods_pkg.all;
use bitvis_vip_axilite.td_vvc_framework_common_methods_pkg.all;
end context; | mit | af8de5c0d16b1ae8c4fbfbd3226023b9 | 0.531161 | 5.559055 | false | false | false | false |
VLSI-EDA/UVVM_All | uvvm_util/src/types_pkg.vhd | 1 | 9,056 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package types_pkg is
file ALERT_FILE : text;
file LOG_FILE : text;
constant C_LOG_HDR_FOR_WAVEVIEW_WIDTH : natural := 100; -- For string in waveview indicating last log header
constant C_FLAG_NAME_LENGTH : positive := 20;
type t_void is (VOID);
type t_natural_array is array (natural range <>) of natural;
type t_integer_array is array (natural range <>) of integer;
type t_byte_array is array (natural range <>) of std_logic_vector(7 downto 0);
type t_slv_array is array (natural range <>) of std_logic_vector;
type t_signed_array is array (natural range <>) of signed;
type t_unsigned_array is array (natural range <>) of unsigned;
-- Additions to predefined vector types
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
-- Note: Most types below have a matching to_string() in 'string_methods_pkg.vhd'
type t_info_target is (LOG_INFO, ALERT_INFO, USER_INFO);
type t_alert_level is (NO_ALERT, NOTE, TB_NOTE, WARNING, TB_WARNING, MANUAL_CHECK, ERROR, TB_ERROR, FAILURE, TB_FAILURE);
type t_enabled is (ENABLED, DISABLED);
type t_attention is (REGARD, EXPECT, IGNORE);
type t_radix is (BIN, HEX, DEC, HEX_BIN_IF_INVALID);
type t_radix_prefix is (EXCL_RADIX, INCL_RADIX);
type t_order is (INTERMEDIATE, FINAL);
type t_ascii_allow is (ALLOW_ALL, ALLOW_PRINTABLE_ONLY);
type t_blocking_mode is (BLOCKING, NON_BLOCKING);
type t_from_point_in_time is (FROM_NOW, FROM_LAST_EVENT);
type t_format_zeros is (AS_IS, KEEP_LEADING_0, SKIP_LEADING_0); -- AS_IS is deprecated and will be removed. Use KEEP_LEADING_0.
type t_format_string is (AS_IS, TRUNCATE, SKIP_LEADING_SPACE); -- Deprecated, will be removed.
type t_format_spaces is (KEEP_LEADING_SPACE, SKIP_LEADING_SPACE);
type t_truncate_string is (ALLOW_TRUNCATE, DISALLOW_TRUNCATE);
type t_log_format is (FORMATTED, UNFORMATTED);
type t_log_if_block_empty is (WRITE_HDR_IF_BLOCK_EMPTY, SKIP_LOG_IF_BLOCK_EMPTY, NOTIFY_IF_BLOCK_EMPTY);
type t_log_destination is (CONSOLE_AND_LOG, CONSOLE_ONLY, LOG_ONLY);
type t_match_strictness is (MATCH_STD, MATCH_STD_INCL_Z, MATCH_EXACT);
type t_alert_counters is array (NOTE to t_alert_level'right) of natural;
type t_alert_attention is array (NOTE to t_alert_level'right) of t_attention;
type t_attention_counters is array (t_attention'left to t_attention'right) of natural; -- Only used to build below type
type t_alert_attention_counters is array (NOTE to t_alert_level'right) of t_attention_counters;
type t_quietness is (NON_QUIET, QUIET);
type t_deprecate_setting is (NO_DEPRECATE, DEPRECATE_ONCE, ALWAYS_DEPRECATE);
type t_deprecate_list is array(0 to 9) of string(1 to 100);
type t_action_when_transfer_is_done is (RELEASE_LINE_AFTER_TRANSFER, HOLD_LINE_AFTER_TRANSFER);
type t_when_to_start_transfer is (START_TRANSFER_IMMEDIATE, START_TRANSFER_ON_NEXT_SS);
type t_action_between_words is (RELEASE_LINE_BETWEEN_WORDS, HOLD_LINE_BETWEEN_WORDS);
type t_byte_endianness is (FIRST_BYTE_LEFT, FIRST_BYTE_RIGHT);
type t_pulse_continuation is (ALLOW_PULSE_CONTINUATION, NO_PULSE_CONTINUATION_ALLOWED);
type t_global_ctrl is record
attention : t_alert_attention;
stop_limit : t_alert_counters;
end record;
type t_current_log_hdr is record
normal : string(1 to C_LOG_HDR_FOR_WAVEVIEW_WIDTH);
large : string(1 to C_LOG_HDR_FOR_WAVEVIEW_WIDTH);
xl : string(1 to C_LOG_HDR_FOR_WAVEVIEW_WIDTH);
end record;
-- type for await_unblock_flag whether the method should set the flag back to blocked or not
type t_flag_returning is (KEEP_UNBLOCKED, RETURN_TO_BLOCK); -- value after unblock
type t_sync_flag_record is record
flag_name : string(1 to C_FLAG_NAME_LENGTH);
is_blocked : boolean;
end record;
constant C_SYNC_FLAG_DEFAULT : t_sync_flag_record := (
flag_name => (others => NUL),
is_blocked => true
);
type t_sync_flag_record_array is array (natural range <>) of t_sync_flag_record;
-- type for identifying VVC and command index finishing await_any_completion()
type t_info_on_finishing_await_any_completion is record
vvc_name : string(1 to 100); -- VVC name should not exceed this length
vvc_cmd_idx : natural; -- VVC command index
vvc_time_of_completion : time; -- time of completion
end record;
type t_uvvm_status is record
found_unexpected_simulation_warnings_or_worse : natural range 0 to 1; -- simulation end status: 0=no unexpected, 1=unexpected
found_unexpected_simulation_errors_or_worse : natural range 0 to 1; -- simulation end status: 0=no unexpected, 1=unexpected
mismatch_on_expected_simulation_warnings_or_worse : natural range 0 to 1; -- simulation status: 0=no mismatch, 1=mismatch
mismatch_on_expected_simulation_errors_or_worse : natural range 0 to 1; -- simulation status: 0=no mismatch, 1=mismatch
info_on_finishing_await_any_completion : t_info_on_finishing_await_any_completion; -- await_any_completion() trigger identifyer
end record t_uvvm_status;
-- defaults for t_uvvm_status and t_info_on_finishing_await_any_completion
constant C_INFO_ON_FINISHING_AWAIT_ANY_COMPLETION_VVC_NAME_DEFAULT : string := "no await_any_completion() finshed yet\n";
constant C_UVVM_STATUS_DEFAULT : t_uvvm_status := (
found_unexpected_simulation_warnings_or_worse => 0,
found_unexpected_simulation_errors_or_worse => 0,
mismatch_on_expected_simulation_warnings_or_worse => 0,
mismatch_on_expected_simulation_errors_or_worse => 0,
info_on_finishing_await_any_completion => (vvc_name => (C_INFO_ON_FINISHING_AWAIT_ANY_COMPLETION_VVC_NAME_DEFAULT, others => ' '),
vvc_cmd_idx => 0,
vvc_time_of_completion => 0 ns)
);
type t_justify_center is (center);
-------------------------------------
-- BFMs and above
-------------------------------------
type t_transaction_result is (ACK, NAK, ERROR); -- add more when needed
type t_hierarchy_alert_level_print is array (NOTE to t_alert_level'right) of boolean;
constant C_HIERARCHY_NODE_NAME_LENGTH : natural := 20;
type t_hierarchy_node is
record
name : string(1 to C_HIERARCHY_NODE_NAME_LENGTH);
alert_attention_counters : t_alert_attention_counters;
alert_stop_limit : t_alert_counters;
alert_level_print : t_hierarchy_alert_level_print;
end record;
type t_bfm_delay_type is (NO_DELAY, TIME_FINISH2START, TIME_START2START);
type t_inter_bfm_delay is
record
delay_type : t_bfm_delay_type;
delay_in_time : time;
inter_bfm_delay_violation_severity : t_alert_level;
end record;
type t_void_bfm_config is (VOID);
constant C_VOID_BFM_CONFIG : t_void_bfm_config := VOID;
-------------------------------------
-- SB
-------------------------------------
-- Identifier_option: Typically describes what the next parameter means.
-- - ENTRY_NUM :
-- Incremented for each entry added to the queue.
-- Unlike POSITION, the ENTRY_NUMBER will stay the same for this entry, even if entries are inserted before this entry
-- - POSITION :
-- Position of entry in queue, independent of when the entry was inserted.
type t_identifier_option is (ENTRY_NUM, POSITION);
type t_range_option is (SINGLE, AND_LOWER, AND_HIGHER);
type t_tag_usage is (TAG, NO_TAG);
end package types_pkg;
package body types_pkg is
end package body types_pkg;
| mit | b92429914c81762db6b0a63180d62f9c | 0.646201 | 3.784371 | false | false | false | false |
chibby0ne/vhdl-book | Chapter10/exercise3_dir/writing_to_file.vhd | 1 | 2,422 | --!
--! Copyright (C) 2010 - 2013 Creonic GmbH
--!
--! @file: writing_to_file.vhd
--! @brief:
--! @author: Antonio Gutierrez
--! @date: 2014-04-01
--!
--!
--------------------------------------
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pkg_support.all;
use work.pkg_types.all;
--------------------------------------
entity writing_to_file is
--generic declarations
end entity writing_to_file;
--------------------------------------
architecture circuit of writing_to_file is
file f: text open write_mode is "text.txt";
signal inp: natural range 0 to 7 := 1;
signal outp: std_logic_vector(2 downto 0) := '100';
begin
proc: process
variable inp: natural range 0 to 7 := '1';
variable outp: std_logic_vector(2 downto 0) := "100";
variable l: line;
variable t: time range 0 to 400 ns;
variable i: natural range 0 to 8 := '0';
variable str1: string(1 to 2) := "t=";
variable str2: string(1 to 5) := " inp=";
variable str3: string(1 to 6) := " outp=";
variable space: character := ' ';
variable str_time: string(1 to 4) := "time";
variable str_inp: string(1 to 3) := "inp";
variable str_outp: string(1 to 4) := "outp";
variable str_ns: string(1 to 2) := "ns";
begin
if (now < 400 ns) then
wait for period/2;
t := period/2 + i*period;
case i is
when 0 => inp := '1', outp := "100";
when 1 => inp := '2', outp := "110";
when 2 => inp := '0', outp := "011";
when 3 => inp := '3', outp := "111";
when 4 => inp := '4', outp := "010";
when 5 => inp := '6', outp := "101";
when 6 => inp := '7', outp := "000";
when 7 => inp := '5', outp := "001";
end case;
if (i = 0) then
write(l, str_time); write(l, space); write(l, str_inp); write(l, space); write(l, str_outp);
else
write(l, t); write(l, str_ns); write(l, space); write(l, inp); write(l, space); write(l, outp);
end if;
-- write(l, str1); write(l, t); write(l, str2); write(l, inp); write(l, str3); write(l, outp);
i = i + 1;
else
wait;
end if;
end process proc;
end architecture circuit;
| gpl-3.0 | 0bde7384a96640a1f02408a9ef7465da | 0.48142 | 3.572271 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ram_boot.vhd | 1 | 6,652 |
-- The libraries ieee.std_logic_unsigned and std.textio will need to be included
-- with this example
-- The following code will infer a Single port Block RAM and initialize it using a FILE
-- Place the following code before the begin of the architecture
---------------------------------------------------------------------
-- TITLE: Random Access Memory for Xilinx
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 11/06/05
-- FILENAME: ram_xilinx.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements Plasma internal RAM as RAMB for Spartan 3x
--
-- Compile the MIPS C and assembly code into "test.axf".
-- Run convert.exe to change "test.axf" to "code.txt" which
-- will contain the hex values of the opcodes.
-- Next run "ram_image ram_xilinx.vhd code.txt ram_image.vhd",
-- to create the "ram_image.vhd" file that will have the opcodes
-- correctly placed inside the INIT_00 => strings.
-- Then include ram_image.vhd in the simulation/synthesis.
--
-- Warning: Addresses 0x1000 - 0x1FFF are reserved for the cache
-- if the DDR cache is enabled.
---------------------------------------------------------------------
-- UPDATED: 09/07/10 Olivier Rinaudo ([email protected])
-- new behaviour: 8KB expandable to 64KB of internal RAM
--
-- MEMORY MAP
-- 0000..1FFF : 8KB 8KB block0 (upper 4KB used as DDR cache)
-- 2000..3FFF : 8KB 16KB block1
-- 4000..5FFF : 8KB 24KB block2
-- 6000..7FFF : 8KB 32KB block3
-- 8000..9FFF : 8KB 40KB block4
-- A000..BFFF : 8KB 48KB block5
-- C000..DFFF : 8KB 56KB block6
-- E000..FFFF : 8KB 64KB block7
---------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE std.textio.ALL;
ENTITY RAM IS
GENERIC(
memory_type : string := "DEFAULT";
plasma_code : string;
block_count : integer := 03
);
PORT(
clk : IN std_logic;
enable : IN std_logic;
write_byte_enable : IN std_logic_vector(3 DOWNTO 0);
address : IN std_logic_vector(31 DOWNTO 2);
data_write : IN std_logic_vector(31 DOWNTO 0);
data_read : OUT std_logic_vector(31 DOWNTO 0)
);
END;
ARCHITECTURE logic OF RAM IS
CONSTANT TAILLE_LOADER : INTEGER := 4096;--1024; -- TAILLE EN OCTETS (NORMALEMENT)
TYPE memoire IS ARRAY(0 TO TAILLE_LOADER-1) OF bit_vector(7 DOWNTO 0);
IMPURE FUNCTION load_memoire (filename : IN string; byte : IN integer) RETURN memoire IS
FILE ram_file : text IS IN filename;
VARIABLE line_name : line;
VARIABLE line_temp : bit_vector(31 DOWNTO 0);
VARIABLE ram_name : memoire;
BEGIN
FOR I IN memoire'range LOOP
IF (NOT endfile(ram_file)) THEN
readline(ram_file, line_name);
read (line_name, line_temp);
IF(byte = 1) THEN
ram_name(I) := line_temp(31 DOWNTO 24);
ELSIF(byte = 2) THEN
ram_name(I) := line_temp(23 DOWNTO 16);
ELSIF(byte = 3) THEN
ram_name(I) := line_temp(15 DOWNTO 8);
ELSIF(byte = 4) THEN
ram_name(I) := line_temp(7 DOWNTO 0);
END IF;
END IF;
END LOOP;
RETURN ram_name;
END FUNCTION;
SIGNAL laRAM1 : memoire := load_memoire(plasma_code, 1);
SIGNAL laRAM2 : memoire := load_memoire(plasma_code, 2);
SIGNAL laRAM3 : memoire := load_memoire(plasma_code, 3);
SIGNAL laRAM4 : memoire := load_memoire(plasma_code, 4);
--
-- CETTE MEMOIRE EST MICROSCOPIQUE... PAS LA PEINE D'UTILISER UN BLOC RAM POUR
-- SON IMPLANTATION...
--
-- attribute RAM_STYLE : string;
-- attribute RAM_STYLE of laRAM1: signal is "PIPE_DISTRIBUTED";
-- attribute RAM_STYLE of laRAM2: signal is "PIPE_DISTRIBUTED";
-- attribute RAM_STYLE of laRAM3: signal is "PIPE_DISTRIBUTED";
-- attribute RAM_STYLE of laRAM4: signal is "PIPE_DISTRIBUTED";
BEGIN
--
-- ON GERE LES BITS (31 => 24)
--
PROCESS (clk)
BEGIN
IF clk'event AND clk = '1' THEN
IF enable = '1' THEN
IF write_byte_enable(3) = '1' THEN
laRAM1(conv_integer(address(16 DOWNTO 2))) <= to_bitvector(data_write(31 DOWNTO 24));
data_read(31 DOWNTO 24) <= data_write(31 DOWNTO 24);
ELSE
data_read(31 DOWNTO 24) <= to_stdlogicvector(laRAM1(conv_integer(address(16 DOWNTO 2))));
END IF;
END IF;
END IF;
END PROCESS;
--
-- ON GERE LES BITS (23 => 16)
--
PROCESS (clk)
BEGIN
IF clk'event AND clk = '1' THEN
IF enable = '1' THEN
IF write_byte_enable(2) = '1' THEN
laRAM2(conv_integer(address(16 DOWNTO 2))) <= to_bitvector(data_write(23 DOWNTO 16));
data_read(23 DOWNTO 16) <= data_write(23 DOWNTO 16);
ELSE
data_read(23 DOWNTO 16) <= to_stdlogicvector(laRAM2(conv_integer(address(16 DOWNTO 2))));
END IF;
END IF;
END IF;
END PROCESS;
--
-- ON GERE LES BITS (15 => 8)
--
PROCESS (clk)
BEGIN
IF clk'event AND clk = '1' THEN
IF enable = '1' THEN
IF write_byte_enable(1) = '1' THEN
laRAM3(conv_integer(address(16 DOWNTO 2))) <= to_bitvector(data_write(15 DOWNTO 8));
data_read(15 DOWNTO 8) <= data_write(15 DOWNTO 8);
ELSE
data_read(15 DOWNTO 8) <= to_stdlogicvector(laRAM3(conv_integer(address(16 DOWNTO 2))));
END IF;
END IF;
END IF;
END PROCESS;
--
-- ON GERE LES BITS (7 => 0)
--
PROCESS (clk)
BEGIN
IF clk'event AND clk = '1' THEN
IF enable = '1' THEN
IF write_byte_enable(0) = '1' THEN
laRAM4(conv_integer(address(16 DOWNTO 2))) <= to_bitvector(data_write(7 DOWNTO 0));
data_read(7 DOWNTO 0) <= data_write(7 DOWNTO 0);
ELSE
data_read(7 DOWNTO 0) <= to_stdlogicvector(laRAM4(conv_integer(address(16 DOWNTO 2))));
END IF;
END IF;
END IF;
END PROCESS;
END; --architecture logic
| gpl-3.0 | e30a1c3597c51020201a07c0b56f7b1b | 0.549609 | 3.836217 | false | false | false | false |
VLSI-EDA/UVVM_All | bitvis_vip_axistream/src/vvc_methods_pkg.vhd | 1 | 43,890 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.axistream_bfm_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_target_support_pkg.all;
--========================================================================================================================
--========================================================================================================================
package vvc_methods_pkg is
--========================================================================================================================
-- Types and constants for the AXISTREAM VVC
--========================================================================================================================
constant C_VVC_NAME : string := "AXISTREAM_VVC";
signal AXISTREAM_VVCT : t_vvc_target_record := set_vvc_target_defaults(C_VVC_NAME);
alias THIS_VVCT : t_vvc_target_record is AXISTREAM_VVCT;
alias t_bfm_config is t_axistream_bfm_config;
-- Type found in UVVM-Util types_pkg
constant C_AXISTREAM_INTER_BFM_DELAY_DEFAULT : t_inter_bfm_delay := (
delay_type => NO_DELAY,
delay_in_time => 0 ns,
inter_bfm_delay_violation_severity => warning
);
type t_vvc_config is
record
inter_bfm_delay : t_inter_bfm_delay; -- Minimum delay between BFM accesses from the VVC. If parameter delay_type is set to NO_DELAY, BFM accesses will be back to back, i.e. no delay.
cmd_queue_count_max : natural; -- Maximum pending number in command queue before queue is full. Adding additional commands will result in an ERROR.
cmd_queue_count_threshold : natural; -- An alert with severity 'cmd_queue_count_threshold_severity' will be issued if command queue exceeds this count. Used for early warning if command queue is almost full. Will be ignored if set to 0.
cmd_queue_count_threshold_severity : t_alert_level; -- Severity of alert to be initiated if exceeding cmd_queue_count_threshold
result_queue_count_max : natural; -- Maximum number of unfetched results before result_queue is full.
result_queue_count_threshold_severity : t_alert_level; -- An alert with severity 'result_queue_count_threshold_severity' will be issued if command queue exceeds this count. Used for early warning if result queue is almost full. Will be ignored if set to 0.
result_queue_count_threshold : natural; -- Severity of alert to be initiated if exceeding result_queue_count_threshold
bfm_config : t_axistream_bfm_config; -- Configuration for the BFM. See BFM quick reference
msg_id_panel : t_msg_id_panel; -- VVC dedicated message ID panel
end record;
type t_vvc_config_array is array (natural range <>) of t_vvc_config;
constant C_AXISTREAM_VVC_CONFIG_DEFAULT : t_vvc_config := (
inter_bfm_delay => C_AXISTREAM_INTER_BFM_DELAY_DEFAULT,
cmd_queue_count_max => C_CMD_QUEUE_COUNT_MAX,
cmd_queue_count_threshold => C_CMD_QUEUE_COUNT_THRESHOLD,
cmd_queue_count_threshold_severity => C_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
result_queue_count_max => C_RESULT_QUEUE_COUNT_MAX,
result_queue_count_threshold_severity => C_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY,
result_queue_count_threshold => C_RESULT_QUEUE_COUNT_THRESHOLD,
bfm_config => C_AXISTREAM_BFM_CONFIG_DEFAULT,
msg_id_panel => C_VVC_MSG_ID_PANEL_DEFAULT
);
type t_vvc_status is
record
current_cmd_idx : natural;
previous_cmd_idx : natural;
pending_cmd_cnt : natural;
end record;
type t_vvc_status_array is array (natural range <>) of t_vvc_status;
constant C_VVC_STATUS_DEFAULT : t_vvc_status := (
current_cmd_idx => 0,
previous_cmd_idx => 0,
pending_cmd_cnt => 0
);
type t_transaction_info is
record
operation : t_operation;
numPacketsSent : natural;
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
end record;
type t_transaction_info_array is array (natural range <>) of t_transaction_info;
constant C_TRANSACTION_INFO_DEFAULT : t_transaction_info := (
operation => NO_OPERATION,
numPacketsSent => 0,
msg => (others => ' ')
);
shared variable shared_axistream_vvc_config : t_vvc_config_array(0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => C_AXISTREAM_VVC_CONFIG_DEFAULT);
shared variable shared_axistream_vvc_status : t_vvc_status_array(0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => C_VVC_STATUS_DEFAULT);
shared variable shared_axistream_transaction_info : t_transaction_info_array(0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => C_TRANSACTION_INFO_DEFAULT);
--==========================================================================================
-- Methods dedicated to this VVC
-- - These procedures are called from the testbench in order for the VVC to execute
-- BFM calls towards the given interface. The VVC interpreter will queue these calls
-- and then the VVC executor will fetch the commands from the queue and handle the
-- actual BFM execution.
-- For details on how the BFM procedures work, see the QuickRef.
--==========================================================================================
--------------------------------------------------------
--
-- AXIStream Transmit
--
--------------------------------------------------------
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_transmit_bytes(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in t_byte_array;
constant user_array : in t_user_array; -- If you need support for more bits per data byte, edit axistream_bfm_pkg.t_user_array
constant strb_array : in t_strb_array; -- If you need support for more bits per data byte, edit axistream_bfm_pkg.t_strb_array
constant id_array : in t_id_array; -- If you need support for more bits per data byte, edit axistream_bfm_pkg.t_id_array
constant dest_array : in t_dest_array; -- If you need support for more bits per data byte, edit axistream_bfm_pkg.t_dest_array
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
procedure axistream_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in t_slv_array;
constant user_array : in t_user_array; -- If you need support for more bits per data byte, edit axistream_bfm_pkg.t_user_array
constant strb_array : in t_strb_array; -- If you need support for more bits per data byte, edit axistream_bfm_pkg.t_strb_array
constant id_array : in t_id_array; -- If you need support for more bits per data byte, edit axistream_bfm_pkg.t_id_array
constant dest_array : in t_dest_array; -- If you need support for more bits per data byte, edit axistream_bfm_pkg.t_dest_array
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
procedure axistream_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in std_logic_vector;
constant user_array : in t_user_array; -- If you need support for more bits per data byte, edit axistream_bfm_pkg.t_user_array
constant strb_array : in t_strb_array; -- If you need support for more bits per data byte, edit axistream_bfm_pkg.t_strb_array
constant id_array : in t_id_array; -- If you need support for more bits per data byte, edit axistream_bfm_pkg.t_id_array
constant dest_array : in t_dest_array; -- If you need support for more bits per data byte, edit axistream_bfm_pkg.t_dest_array
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_transmit_bytes(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in t_byte_array;
constant user_array : in t_user_array; -- If you need support for more bits per data byte, replace this with a wider type:
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
procedure axistream_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in t_slv_array;
constant user_array : in t_user_array; -- If you need support for more bits per data byte, replace this with a wider type:
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
procedure axistream_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in std_logic_vector;
constant user_array : in t_user_array; -- If you need support for more bits per data byte, replace this with a wider type:
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_transmit_bytes(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in t_byte_array;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
procedure axistream_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in t_slv_array;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
procedure axistream_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in std_logic_vector;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
--------------------------------------------------------
--
-- AXIStream Receive
--
--------------------------------------------------------
procedure axistream_receive_bytes(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
procedure axistream_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
--------------------------------------------------------
--
-- AXIStream Expect
--
--------------------------------------------------------
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_expect_bytes(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in t_byte_array;
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
procedure axistream_expect(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in t_slv_array;
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
procedure axistream_expect(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in std_logic_vector;
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_expect_bytes(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in t_byte_array;
constant user_array : in t_user_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
procedure axistream_expect(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in t_slv_array;
constant user_array : in t_user_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
procedure axistream_expect(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in std_logic_vector;
constant user_array : in t_user_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_expect_bytes(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in t_byte_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
procedure axistream_expect(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in t_slv_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
procedure axistream_expect(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
end package vvc_methods_pkg;
package body vvc_methods_pkg is
--========================================================================================================================
-- Methods dedicated to this VVC
--========================================================================================================================
--------------------------------------------------------
--
-- AXIStream Transmit
--
--------------------------------------------------------
-- These procedures will be used to forward commands to the VVC executor, which will
-- call the corresponding BFM procedures.
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_transmit_bytes(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in t_byte_array;
constant user_array : in t_user_array; -- If you need support for more bits per data byte, edit axistream_bfm_pkg.t_user_array
constant strb_array : in t_strb_array; -- If you need support for more bits per data byte, edit axistream_bfm_pkg.t_strb_array
constant id_array : in t_id_array; -- If you need support for more bits per data byte, edit axistream_bfm_pkg.t_id_array
constant dest_array : in t_dest_array; -- If you need support for more bits per data byte, edit axistream_bfm_pkg.t_dest_array
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ", " & to_string(data_array'length, 5) & " bytes)";
begin
-- DEPRECATE: data_array as t_byte_array will be removed in next major release
deprecate(proc_name, "data_array as t_byte_array has been deprecated. Use data_array as t_slv_array.");
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, TRANSMIT);
-- Sanity check to avoid confusing fatal error
check_value(data_array'length > 0, TB_ERROR, proc_call & "data_array length must be > 0", "VVC");
-- Generate cmd record
shared_vvc_cmd.data_array(0 to data_array'high) := data_array;
shared_vvc_cmd.user_array(0 to user_array'high) := user_array;
shared_vvc_cmd.strb_array(0 to strb_array'high) := strb_array;
shared_vvc_cmd.id_array(0 to id_array'high) := id_array;
shared_vvc_cmd.dest_array(0 to dest_array'high) := dest_array;
shared_vvc_cmd.data_array_length := data_array'length;
shared_vvc_cmd.user_array_length := user_array'length;
shared_vvc_cmd.strb_array_length := strb_array'length;
shared_vvc_cmd.id_array_length := id_array'length;
shared_vvc_cmd.dest_array_length := dest_array'length;
-- Send command record
send_command_to_vvc(VVCT, scope => scope);
end procedure;
-- t_slv_array overload
procedure axistream_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in t_slv_array;
constant user_array : in t_user_array; -- If you need support for more bits per data byte, edit axistream_bfm_pkg.t_user_array
constant strb_array : in t_strb_array; -- If you need support for more bits per data byte, edit axistream_bfm_pkg.t_strb_array
constant id_array : in t_id_array; -- If you need support for more bits per data byte, edit axistream_bfm_pkg.t_id_array
constant dest_array : in t_dest_array; -- If you need support for more bits per data byte, edit axistream_bfm_pkg.t_dest_array
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
-- helper variables
variable v_bytes_in_word : integer := (data_array(data_array'low)'length/8);
variable v_num_bytes : integer := (data_array'length) * v_bytes_in_word;
variable v_data_array : t_byte_array(0 to v_num_bytes-1);
variable v_data_array_idx : integer := 0;
variable v_check_ok : boolean := false;
variable v_byte_endianness : t_byte_endianness := shared_axistream_vvc_config(vvc_instance_idx).bfm_config.byte_endianness;
begin
-- t_slv_array sanity check
v_check_ok := check_value(data_array(data_array'low)'length mod 8 = 0, TB_ERROR, "Sanity check: Check that data_array word is N*byte");
if v_check_ok then
-- copy byte(s) from t_slv_array to t_byte_array
v_data_array := convert_slv_array_to_byte_array(data_array, true, v_byte_endianness); -- data_array is ascending, data_array(0 to N)()
-- call t_byte_array overloaded procedure
axistream_transmit_bytes(VVCT, vvc_instance_idx, v_data_array, user_array, strb_array, id_array, dest_array, msg, scope);
end if;
end procedure;
-- std_logic_vector overload
procedure axistream_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in std_logic_vector;
constant user_array : in t_user_array; -- If you need support for more bits per data byte, edit axistream_bfm_pkg.t_user_array
constant strb_array : in t_strb_array; -- If you need support for more bits per data byte, edit axistream_bfm_pkg.t_strb_array
constant id_array : in t_id_array; -- If you need support for more bits per data byte, edit axistream_bfm_pkg.t_id_array
constant dest_array : in t_dest_array; -- If you need support for more bits per data byte, edit axistream_bfm_pkg.t_dest_array
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
-- helper variables
variable v_check_ok : boolean := false;
variable v_data_array : t_slv_array(0 to 0)(data_array'length-1 downto 0);
begin
-- std_logic_vector sanity check
v_check_ok := check_value(data_array'length mod 8 = 0, TB_ERROR, "Sanity check: Check that data_array word is N*byte");
if v_check_ok then
v_data_array(0) := data_array;
axistream_transmit(VVCT, vvc_instance_idx, v_data_array, user_array, strb_array, id_array, dest_array, msg, scope);
end if;
end procedure;
-- Overload, without the strb_array, id_array, dest_array arguments
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_transmit_bytes(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in t_byte_array;
constant user_array : in t_user_array;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
-- Default user data : We don't know c_user_array length (how many words to send), so assume worst case: tdata = 8 bits (one data_array byte per word)
constant c_strb_array : t_strb_array(0 to C_VVC_CMD_DATA_MAX_WORDS-1) := (others => (others => '0'));
constant c_id_array : t_id_array(0 to C_VVC_CMD_DATA_MAX_WORDS-1) := (others => (others => '0'));
constant c_dest_array : t_dest_array(0 to C_VVC_CMD_DATA_MAX_WORDS-1) := (others => (others => '0'));
begin
axistream_transmit_bytes(VVCT, vvc_instance_idx, data_array, user_array, c_strb_array, c_id_array, c_dest_array, msg, scope);
end procedure;
-- t_slv_array overload
procedure axistream_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in t_slv_array;
constant user_array : in t_user_array;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
-- Default user data : We don't know c_user_array length (how many words to send), so assume worst case: tdata = 8 bits (one data_array byte per word)
constant c_strb_array : t_strb_array(0 to C_VVC_CMD_DATA_MAX_WORDS-1) := (others => (others => '0'));
constant c_id_array : t_id_array(0 to C_VVC_CMD_DATA_MAX_WORDS-1) := (others => (others => '0'));
constant c_dest_array : t_dest_array(0 to C_VVC_CMD_DATA_MAX_WORDS-1) := (others => (others => '0'));
begin
axistream_transmit(VVCT, vvc_instance_idx, data_array, user_array, c_strb_array, c_id_array, c_dest_array, msg, scope);
end procedure;
-- std_logic_vector overload
procedure axistream_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in std_logic_vector;
constant user_array : in t_user_array;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
-- Default user data : We don't know c_user_array length (how many words to send), so assume worst case: tdata = 8 bits (one data_array byte per word)
constant c_strb_array : t_strb_array(0 to C_VVC_CMD_DATA_MAX_WORDS-1) := (others => (others => '0'));
constant c_id_array : t_id_array(0 to C_VVC_CMD_DATA_MAX_WORDS-1) := (others => (others => '0'));
constant c_dest_array : t_dest_array(0 to C_VVC_CMD_DATA_MAX_WORDS-1) := (others => (others => '0'));
begin
axistream_transmit(VVCT, vvc_instance_idx, data_array, user_array, c_strb_array, c_id_array, c_dest_array, msg, scope);
end procedure;
-- Overload, without the user_array, strb_array, id_array, dest_array arguments
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_transmit_bytes(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in t_byte_array;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
-- Default user data : We don't know c_user_array length (how many words to send), so assume tdata = 8 bits (one data_array byte per word)
constant c_user_array : t_user_array(0 to C_VVC_CMD_DATA_MAX_WORDS-1) := (others => (others => '0'));
begin
-- Use another overload to fill in the rest
axistream_transmit_bytes(VVCT, vvc_instance_idx, data_array, c_user_array, msg, scope);
end procedure;
-- t_slv_array overload
procedure axistream_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in t_slv_array;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
-- Default user data : We don't know c_user_array length (how many words to send), so assume tdata = 8 bits (one data_array byte per word)
constant c_user_array : t_user_array(0 to C_VVC_CMD_DATA_MAX_WORDS-1) := (others => (others => '0'));
begin
-- Use another overload to fill in the rest
axistream_transmit(VVCT, vvc_instance_idx, data_array, c_user_array, msg, scope);
end procedure;
-- std_logic_vector overload
procedure axistream_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in std_logic_vector;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
-- Default user data : We don't know c_user_array length (how many words to send), so assume tdata = 8 bits (one data_array byte per word)
constant c_user_array : t_user_array(0 to C_VVC_CMD_DATA_MAX_WORDS-1) := (others => (others => '0'));
begin
-- Use another overload to fill in the rest
axistream_transmit(VVCT, vvc_instance_idx, data_array, c_user_array, msg, scope);
end procedure;
--------------------------------------------------------
--
-- AXIStream Receive
--
--------------------------------------------------------
procedure axistream_receive_bytes(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "()";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, RECEIVE);
send_command_to_vvc(VVCT, scope => scope);
end procedure axistream_receive_bytes;
-- Overloading procedure
procedure axistream_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
begin
-- Call overloaded procedure
axistream_receive_bytes(VVCT, vvc_instance_idx, msg, scope);
end procedure axistream_receive;
--------------------------------------------------------
--
-- AXIStream Expect
--
--------------------------------------------------------
-- Expect, receive and compare to specified data_array, user_array, strb_array, id_array, dest_array
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_expect_bytes(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in t_byte_array;
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ", " & to_string(data_array'length) & "B)";
begin
-- DEPRECATE: data_array as t_byte_array will be removed in next major release
deprecate(proc_name, "data_array as t_byte_array has been deprecated. Use data_array as t_slv_array.");
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, EXPECT);
-- Generate cmd record
shared_vvc_cmd.data_array(0 to data_array'high) := data_array;
shared_vvc_cmd.user_array(0 to user_array'high) := user_array; -- user_array Length = data_array_length
shared_vvc_cmd.strb_array(0 to strb_array'high) := strb_array;
shared_vvc_cmd.id_array(0 to id_array'high) := id_array;
shared_vvc_cmd.dest_array(0 to dest_array'high) := dest_array;
shared_vvc_cmd.data_array_length := data_array'length;
shared_vvc_cmd.user_array_length := user_array'length;
shared_vvc_cmd.strb_array_length := strb_array'length;
shared_vvc_cmd.id_array_length := id_array'length;
shared_vvc_cmd.dest_array_length := dest_array'length;
shared_vvc_cmd.alert_level := alert_level;
send_command_to_vvc(VVCT, scope => scope);
end procedure;
-- t_slv_array overload
procedure axistream_expect(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in t_slv_array;
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
-- helper variables
variable v_bytes_in_word : integer := (data_array(data_array'low)'length/8);
variable v_num_bytes : integer := (data_array'length) * v_bytes_in_word;
variable v_data_array : t_byte_array(0 to v_num_bytes-1);
variable v_data_array_idx : integer := 0;
variable v_check_ok : boolean := false;
variable v_byte_endianness : t_byte_endianness := shared_axistream_vvc_config(vvc_instance_idx).bfm_config.byte_endianness;
begin
-- t_slv_array sanity check
v_check_ok := check_value(data_array(data_array'low)'length mod 8 = 0, TB_ERROR, "Sanity check: Check that data_array word is N*byte");
if v_check_ok then
-- copy byte(s) from t_slv_array to t_byte_array
v_data_array := convert_slv_array_to_byte_array(data_array, true, v_byte_endianness); -- data_array is ascending, data_array(0 to N)()
-- call t_byte_array overloaded procedure
axistream_expect_bytes(VVCT, vvc_instance_idx, v_data_array, user_array, strb_array, id_array, dest_array, msg, alert_level, scope);
end if;
end procedure;
-- std_logic_vector overload
procedure axistream_expect(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in std_logic_vector;
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
-- helper variables
variable v_data_array : t_slv_array(0 to 0)(data_array'length-1 downto 0);
variable v_check_ok : boolean := false;
begin
-- std_logic_vector sanity check
v_check_ok := check_value(data_array'length mod 8 = 0, TB_ERROR, "Sanity check: Check that data_array word is N*byte");
if v_check_ok then
v_data_array(0) := data_array;
axistream_expect(VVCT, vvc_instance_idx, v_data_array, user_array, strb_array, id_array, dest_array, msg, alert_level, scope);
end if;
end procedure;
-- Overload for calling axiStreamExpect() without a value for strb_array, id_array, dest_array
-- (will be set to don't care)
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_expect_bytes(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in t_byte_array;
constant user_array : in t_user_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
-- Default expected strb, id, dest
-- Don't know #bytes in AXIStream tdata, so *_array length is unknown.
-- Make the array as short as possible for best simulation time during the check performed in the BFM.
constant c_strb_array : t_strb_array(0 downto 0) := (others => (others => '-'));
constant c_id_array : t_id_array(0 downto 0) := (others => (others => '-'));
constant c_dest_array : t_dest_array(0 downto 0) := (others => (others => '-'));
begin
axistream_expect_bytes(VVCT, vvc_instance_idx, data_array, user_array, c_strb_array, c_id_array, c_dest_array, msg, alert_level, scope);
end procedure;
-- t_slv_array overload
procedure axistream_expect(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in t_slv_array;
constant user_array : in t_user_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
-- Default expected strb, id, dest
-- Don't know #bytes in AXIStream tdata, so *_array length is unknown.
-- Make the array as short as possible for best simulation time during the check performed in the BFM.
constant c_strb_array : t_strb_array(0 downto 0) := (others => (others => '-'));
constant c_id_array : t_id_array(0 downto 0) := (others => (others => '-'));
constant c_dest_array : t_dest_array(0 downto 0) := (others => (others => '-'));
begin
axistream_expect(VVCT, vvc_instance_idx, data_array, user_array, c_strb_array, c_id_array, c_dest_array, msg, alert_level, scope);
end procedure;
-- std_logic_vector overload
procedure axistream_expect(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in std_logic_vector;
constant user_array : in t_user_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
-- Default expected strb, id, dest
-- Don't know #bytes in AXIStream tdata, so *_array length is unknown.
-- Make the array as short as possible for best simulation time during the check performed in the BFM.
constant c_strb_array : t_strb_array(0 downto 0) := (others => (others => '-'));
constant c_id_array : t_id_array(0 downto 0) := (others => (others => '-'));
constant c_dest_array : t_dest_array(0 downto 0) := (others => (others => '-'));
begin
axistream_expect(VVCT, vvc_instance_idx, data_array, user_array, c_strb_array, c_id_array, c_dest_array, msg, alert_level, scope);
end procedure;
-- Overload, without the user_array, strb_array, id_array, dest_array arguments
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_expect_bytes(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in t_byte_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
-- Default user data
-- Don't know #bytes in AXIStream tdata, so user_array length is unknown.
-- Make the array as short as possible for best simulation time during the check performed in the BFM.
constant c_user_array : t_user_array(0 downto 0) := (others => (others => '-'));
begin
-- Use another overload to fill in the rest: strb_array, id_array, dest_array
axistream_expect_bytes(VVCT, vvc_instance_idx, data_array, c_user_array, msg, alert_level, scope);
end procedure;
-- t_slv_array overload
procedure axistream_expect(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in t_slv_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
-- Default user data
-- Don't know #bytes in AXIStream tdata, so user_array length is unknown.
-- Make the array as short as possible for best simulation time during the check performed in the BFM.
constant c_user_array : t_user_array(0 downto 0) := (others => (others => '-'));
begin
-- Use another overload to fill in the rest: strb_array, id_array, dest_array
axistream_expect(VVCT, vvc_instance_idx, data_array, c_user_array, msg, alert_level, scope);
end procedure;
-- std_logic_vector overload
procedure axistream_expect(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data_array : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
-- Default user data
-- Don't know #bytes in AXIStream tdata, so user_array length is unknown.
-- Make the array as short as possible for best simulation time during the check performed in the BFM.
constant c_user_array : t_user_array(0 downto 0) := (others => (others => '-'));
begin
-- Use another overload to fill in the rest: strb_array, id_array, dest_array
axistream_expect(VVCT, vvc_instance_idx, data_array, c_user_array, msg, alert_level, scope);
end procedure;
end package body vvc_methods_pkg;
| mit | 290f21a1a5d36a1e5ba140af53e7de78 | 0.5982 | 3.87037 | false | false | false | false |
VLSI-EDA/UVVM_All | bitvis_uart/tb/uart_vvc_demo_tb.vhd | 1 | 15,209 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
library bitvis_vip_sbi;
use bitvis_vip_sbi.vvc_methods_pkg.all;
use bitvis_vip_sbi.td_vvc_framework_common_methods_pkg.all;
library bitvis_vip_uart;
use bitvis_vip_uart.vvc_methods_pkg.all;
use bitvis_vip_uart.td_vvc_framework_common_methods_pkg.all;
library bitvis_vip_clock_generator;
context bitvis_vip_clock_generator.vvc_context;
-- Test bench entity
entity uart_vvc_demo_tb is
end entity;
-- Test bench architecture
architecture func of uart_vvc_demo_tb is
constant C_SCOPE : string := C_TB_SCOPE_DEFAULT;
-- Clock and bit period settings
constant C_CLK_PERIOD : time := 10 ns;
constant C_BIT_PERIOD : time := 16 * C_CLK_PERIOD;
-- Time for one UART transmission to complete
constant C_TIME_OF_ONE_UART_TX : time := 11*C_BIT_PERIOD; -- =1760 ns;
-- Predefined SBI addresses
constant C_ADDR_RX_DATA : unsigned(2 downto 0) := "000";
constant C_ADDR_RX_DATA_VALID : unsigned(2 downto 0) := "001";
constant C_ADDR_TX_DATA : unsigned(2 downto 0) := "010";
constant C_ADDR_TX_READY : unsigned(2 downto 0) := "011";
begin
-----------------------------------------------------------------------------
-- Instantiate test harness, containing DUT and Executors
-----------------------------------------------------------------------------
i_test_harness : entity work.uart_vvc_demo_th;
------------------------------------------------
-- PROCESS: p_main
------------------------------------------------
p_main: process
begin
-- Wait for UVVM to finish initialization
await_uvvm_initialization(VOID);
start_clock(CLOCK_GENERATOR_VVCT, 1, "Start clock generator");
-- Print the configuration to the log
report_global_ctrl(VOID);
report_msg_id_panel(VOID);
--enable_log_msg(ALL_MESSAGES);
disable_log_msg(ALL_MESSAGES);
enable_log_msg(ID_LOG_HDR);
enable_log_msg(ID_SEQUENCER);
enable_log_msg(ID_UVVM_SEND_CMD);
disable_log_msg(SBI_VVCT, 1, ALL_MESSAGES);
enable_log_msg(SBI_VVCT, 1, ID_BFM);
enable_log_msg(SBI_VVCT, 1, ID_FINISH_OR_STOP);
disable_log_msg(UART_VVCT, 1, RX, ALL_MESSAGES);
enable_log_msg(UART_VVCT, 1, RX, ID_BFM);
disable_log_msg(UART_VVCT, 1, TX, ALL_MESSAGES);
enable_log_msg(UART_VVCT, 1, TX, ID_BFM);
log(ID_LOG_HDR, "Starting simulation of TB for UART using VVCs", C_SCOPE);
------------------------------------------------------------
log("Wait 10 clock period for reset to be turned off");
wait for (10 * C_CLK_PERIOD); -- for reset to be turned off
log(ID_LOG_HDR, "Configure UART VVC 1", C_SCOPE);
------------------------------------------------------------
shared_uart_vvc_config(RX,1).bfm_config.bit_time := C_BIT_PERIOD;
shared_uart_vvc_config(TX,1).bfm_config.bit_time := C_BIT_PERIOD;
log(ID_LOG_HDR, "Check register defaults ", C_SCOPE);
------------------------------------------------------------
-- This test will send three sbi_check commands to the SBI VVC, and then
-- wait for them all to complete before continuing the test sequence.
sbi_check(SBI_VVCT, 1, C_ADDR_RX_DATA, x"00", "RX_DATA default");
sbi_check(SBI_VVCT, 1, C_ADDR_TX_READY, x"01", "TX_READY default");
sbi_check(SBI_VVCT, 1, C_ADDR_RX_DATA_VALID, x"00", "RX_DATA_VALID default");
await_completion(SBI_VVCT,1, 10 * C_CLK_PERIOD);
log(ID_LOG_HDR, "Check simple transmit", C_SCOPE);
------------------------------------------------------------
-- This test case will instruct the SBI VVC to send the data x"55" to the DUT C_ADDR_TX_DATA address.
-- This will cause the DUT to transmit x"55" on the UART line. In order to receive the data, the
-- UART VVC is instructed to expect the data x"55" on the RX port. The test sequence will not continue
-- until the UART VVC has received the data from the DUT, indicated by the await_completion method.
sbi_write(SBI_VVCT,1, C_ADDR_TX_DATA, x"55", "TX_DATA");
uart_expect(UART_VVCT,1,RX, x"55", "Expecting data on UART RX");
await_completion(UART_VVCT,1,RX, 13 * C_BIT_PERIOD);
wait for 200 ns; -- margin
log(ID_LOG_HDR, "Check simple receive", C_SCOPE);
------------------------------------------------------------
-- In this test case the UART VVC (TX channel) is instructed to send the data x"AA" to the DUT.
-- This data should be received and stored to a RX buffer by the DUT. After the UART VVC has completed
-- the transmission, the SBI VVC is instructed to check read and check (sbi_check) the C_ADDR_RX_DATA
-- register, and verify that it is in fact x"AA" that the DUT received. The test sequencer will continue
-- when the SBI VVC is done checking the C_ADDR_RX_DATA register.
uart_transmit(UART_VVCT,1,TX, x"AA", "UART TX");
await_completion(UART_VVCT,1,TX, 13 * C_BIT_PERIOD);
wait for 200 ns; -- margin
sbi_check(SBI_VVCT,1, C_ADDR_RX_DATA, x"AA", "RX_DATA");
await_completion(SBI_VVCT,1, 13 * C_BIT_PERIOD);
log(ID_LOG_HDR, "Check single simultaneous transmit and receive", C_SCOPE);
------------------------------------------------------------
-- Since the UART consists of two individual VVCs (TX and RX), it is capable of full duplex operation.
-- This test case will instruct the SBI VVC to write x"B4" to the C_ADDR_TX_DATA register of the DUT,
-- which will cause the DUT to send x"B4" on its UART TX line. Simultaneously, the UART VVC is instructed
-- to both transmit x"87" to the DUT, and expect x"B4" from the DUT. When the UART VVC is done transmitting
-- to the DUT, the SBI VVC will be instructed to read and check the DUT C_ADDR_RX_DATA register and verify
-- that the DUT received the correct data from the UART VVC. After this check is completed, the test sequencer
-- can continue to the next test case.
sbi_write(SBI_VVCT,1, C_ADDR_TX_DATA, x"B4", "TX_DATA");
uart_transmit(UART_VVCT,1,TX, x"87", "UART TX");
uart_expect(UART_VVCT,1,RX, x"B4", "Expecting data on UART RX");
await_completion(UART_VVCT,1,TX, 13 * C_BIT_PERIOD);
wait for 200 ns; -- margin
sbi_check(SBI_VVCT,1, C_ADDR_RX_DATA, x"87", "RX_DATA");
await_completion(SBI_VVCT,1, 13 * C_BIT_PERIOD);
log(ID_LOG_HDR, "Check multiple simultaneous receive and read", C_SCOPE);
------------------------------------------------------------
-- This test case will instruct the UART VVC to transmit three messages to the DUT. These UART VVC (TX channel)
-- will add the three "uart_transmit" commands to the command queue, and execute them sequentially when
-- await_completion is called. After the UART VVC is done transmitting, the SBI VVC is instructed to read and
-- verify that the three consecutive bytes from the C_ADDR_RX_DATA register of the DUT are equal to the data
-- transmitted from the UART VVC. When the SBI VVC is done with these checks, the testbench sequencer can continue
-- to the next test case.
uart_transmit(UART_VVCT,1,TX, x"A1", "UART TX");
uart_transmit(UART_VVCT,1,TX, x"A2", "UART TX");
uart_transmit(UART_VVCT,1,TX, x"A3", "UART TX");
await_completion(UART_VVCT,1,TX, 3 * 13 * C_BIT_PERIOD);
wait for 200 ns; -- margin
sbi_check(SBI_VVCT,1, C_ADDR_RX_DATA, x"A1", "RX_DATA");
sbi_check(SBI_VVCT,1, C_ADDR_RX_DATA, x"A2", "RX_DATA");
sbi_check(SBI_VVCT,1, C_ADDR_RX_DATA, x"A3", "RX_DATA");
await_completion(SBI_VVCT,1, 10 * C_CLK_PERIOD);
log(ID_LOG_HDR, "Skew SBI read over UART receive ", C_SCOPE);
------------------------------------------------------------
-- This test case will show how using VVCs in UVVM can be used for simultaneous UART and SBI operation,
-- which enables testing of corner cases. In the UART DUT one of these corner cases often occurs when the UART DUT
-- must handle UART RX data and SBI reads simultaneously. To test if this is handled properly in the DUT,
-- this test case will transmit data from the UART VVC, and check the data received in the C_ADDR_RX_DATA register.
-- The DUT RX buffer will always contain at least one received byte, and the SBI VVC will check the oldest entry in
-- the RX buffer. The UART VVC will be set up to transmit bytes to the DUT continuously. When the SBI_VVC checks the
-- DUT RX buffer, relative to the UART TX operation, will vary on each iteration.
-- First, the UART VVC will transmit a complete frame to the DUT. Then, when the UART VVC is 50 clock periods from
-- completing the transmission of the second byte, the SBI VVC checks the DUT RX buffer for the first received byte.
-- When the UART VVC is 49 clock periods from transmitting the third byte, the SBI VVC will check the DUT RX buffer
-- for the second byte received. This process repeats until the SBI VVC is checking the DUT RX register 50 clock periods
-- after the UART VVC has completed its transmission. At this point there will be two complete bytes in the DUT RX buffer
-- when the SBI VVC reads from it. After the test is completed the two final bytes in the RX buffer are checked. When this
-- is done, the test case is complete.
log("Setting up the UART VVC to transmit 102 samples to the DUT");
for i in 1 to 102 loop
uart_transmit(UART_VVCT,1,TX, std_logic_vector(to_unsigned(16#80# + i, 8)), string'("Set up new data. Now byte # " & to_string(i)));
end loop;
log("Setting up the SBI VVC to read and check the DUT RX register after each completed UART TX operation");
-- 1760 ns is measured time from start of UART receive to received data is available in the DUT C_ADDR_RX_DATA register
-- The SBI VVC will wait until the UART VVC is 50 clock periods away from successfully transmitting the first byte.
insert_delay(SBI_VVCT,1, C_TIME_OF_ONE_UART_TX - 50 * C_CLK_PERIOD, "Inserting delay in SBI VVC to wait for first byte to complete");
for i in 1 to 100 loop
-- Wait for the time of one complete UART transmission + one clock cycle (for skew).
-- Every read will now be 1T later relative to a new byte being valid internally
insert_delay(SBI_VVCT,1, C_TIME_OF_ONE_UART_TX, "Delaying for the time of one uart transmission");
insert_delay(SBI_VVCT,1, C_CLK_PERIOD, "Skewing the SBI read one clock cycle");
sbi_check(SBI_VVCT,1, C_ADDR_RX_DATA, std_logic_vector(to_unsigned(16#80# + i, 8)), "Reading data number " & to_string(i));
end loop;
await_completion(UART_VVCT,1,TX, 103 * C_TIME_OF_ONE_UART_TX);
wait for 50 ns; -- to assure UART RX complete internally
-- Check the last two bytes in the DUT RX buffer.
sbi_check(SBI_VVCT,1, C_ADDR_RX_DATA, std_logic_vector(to_unsigned(16#80# + 101, 8)), "Reading data number " & to_string(101));
sbi_check(SBI_VVCT,1, C_ADDR_RX_DATA, std_logic_vector(to_unsigned(16#80# + 102, 8)), "Reading data number " & to_string(102));
await_completion(SBI_VVCT,1, 10 * C_CLK_PERIOD);
log(ID_LOG_HDR, "Skew SBI read over UART receive with inter-BFM delay functionality", C_SCOPE);
------------------------------------------------------------
-- This test case will test the same as the test case above, but using the built in delay functionality in the SBI VVC
log("Setting up the UART VVC to transmit 102 samples to the DUT");
for i in 1 to 102 loop
uart_transmit(UART_VVCT,1,TX, std_logic_vector(to_unsigned(16#80# + i, 8)), string'("Set up new data. Now byte # " & to_string(i)));
end loop;
log("Setting up the SBI VVC to read and check the DUT RX register after each completed UART TX operation");
-- The SBI VVC will wait until the UART VVC is 50 clock periods away from successfully transmitting the second byte.
insert_delay(SBI_VVCT,1, C_TIME_OF_ONE_UART_TX, "Insert delay in SBI VVC until the first UART transmission has completed");
insert_delay(SBI_VVCT,1, C_TIME_OF_ONE_UART_TX - 50 * C_CLK_PERIOD, "Inserting delay in SBI VVC until second UART transmission has almost completed");
log("Setting the SBI VVC to separate each BFM access with 1760 ns");
shared_sbi_vvc_config(1).inter_bfm_delay.delay_type := TIME_START2START;
shared_sbi_vvc_config(1).inter_bfm_delay.delay_in_time := C_TIME_OF_ONE_UART_TX+C_CLK_PERIOD;
for i in 1 to 100 loop
sbi_check(SBI_VVCT,1, C_ADDR_RX_DATA, std_logic_vector(to_unsigned(16#80# + i, 8)), "Reading data number " & to_string(i));
end loop;
await_completion(UART_VVCT,1,TX, 103 * C_TIME_OF_ONE_UART_TX);
await_completion(SBI_VVCT,1, 2 * C_TIME_OF_ONE_UART_TX);
wait for 50 ns; -- to assure UART RX complete internally
-- Check the last two bytes in the DUT RX buffer.
log("Setting the SBI VVC back to no delay between BFM accesses");
shared_sbi_vvc_config(1).inter_bfm_delay.delay_type := NO_DELAY;
shared_sbi_vvc_config(1).inter_bfm_delay.delay_in_time := 0 ns;
sbi_check(SBI_VVCT,1, C_ADDR_RX_DATA, std_logic_vector(to_unsigned(16#80# + 101, 8)), "Reading data number " & to_string(101));
sbi_check(SBI_VVCT,1, C_ADDR_RX_DATA, std_logic_vector(to_unsigned(16#80# + 102, 8)), "Reading data number " & to_string(102));
await_completion(SBI_VVCT,1, 2*C_TIME_OF_ONE_UART_TX);
-----------------------------------------------------------------------------
-- Ending the simulation
-----------------------------------------------------------------------------
wait for 1000 ns; -- to allow some time for completion
report_alert_counters(FINAL); -- Report final counters and print conclusion for simulation (Success/Fail)
log(ID_LOG_HDR, "SIMULATION COMPLETED", C_SCOPE);
-- Finish the simulation
std.env.stop;
wait; -- to stop completely
end process p_main;
end func;
| mit | cfe1cea6665f534c1a24c201cb7a9b44 | 0.627326 | 3.756236 | false | true | false | false |
MForever78/CPUFly | ipcore_dir/dist_mem_gen_v7_2/simulation/dist_mem_gen_v7_2_tb_dgen.vhd | 1 | 5,172 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: dist_mem_gen_v7_2_tb_dgen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.dist_mem_gen_v7_2_TB_PKG.ALL;
ENTITY dist_mem_gen_v7_2_TB_DGEN IS
GENERIC (
DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END dist_mem_gen_v7_2_TB_DGEN;
ARCHITECTURE DATA_GEN_ARCH OF dist_mem_gen_v7_2_TB_DGEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.dist_mem_gen_v7_2_TB_RNG
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
| mit | 506587d69a93ee8252ec59ed791b729b | 0.578113 | 3.951108 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Instruction_Memory/example_design/Instruction_Memory_exdes ([email protected] 2015-09-19-15-43-09).vhd | 1 | 3,975 |
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
--
-- Description:
-- This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity Instruction_Memory_exdes is
PORT (
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
A : IN STD_LOGIC_VECTOR(14-1-(4*0*boolean'pos(14>4)) downto 0)
:= (OTHERS => '0')
);
end Instruction_Memory_exdes;
architecture xilinx of Instruction_Memory_exdes is
component Instruction_Memory is
PORT (
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
A : IN STD_LOGIC_VECTOR(14-1-(4*0*boolean'pos(14>4)) downto 0)
:= (OTHERS => '0')
);
end component;
begin
dmg0 : Instruction_Memory
port map (
SPO => SPO,
A => A
);
end xilinx;
| mit | 4b351cb986ec56c425576e70c7517887 | 0.576101 | 4.632867 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Video_Memory/simulation/Video_Memory_tb_agen.vhd | 1 | 4,462 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Video_Memory_tb_agen.vhd
--
-- Description:
-- Address Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY Video_Memory_TB_AGEN IS
GENERIC (
C_MAX_DEPTH : INTEGER := 1024 ;
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
RST_INC : INTEGER := 0);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
LOAD :IN STD_LOGIC;
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
);
END Video_Memory_TB_AGEN;
ARCHITECTURE BEHAVIORAL OF Video_Memory_TB_AGEN IS
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
BEGIN
ADDR_OUT <= ADDR_TEMP;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
IF(EN='1') THEN
IF(LOAD='1') THEN
ADDR_TEMP <=LOAD_VALUE;
ELSE
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
ADDR_TEMP <= ADDR_TEMP + '1';
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
| mit | 3032305c6147c47a6dd9549b56e5b44e | 0.58113 | 4.257634 | false | false | false | false |
makestuff/swled | templates/epp/vhdl/top_level.vhdl | 1 | 4,271 | --
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_level is
port(
sysClk_in : in std_logic; -- clock input (asynchronous with EPP signals)
-- EPP interface -----------------------------------------------------------------------------
eppData_io : inout std_logic_vector(7 downto 0); -- bidirectional 8-bit data bus
eppAddrStb_in : in std_logic; -- active-low asynchronous address strobe
eppDataStb_in : in std_logic; -- active-low asynchronous data strobe
eppWrite_in : in std_logic; -- read='1'; write='0'
eppWait_out : out std_logic; -- active-low asynchronous wait signal
-- Onboard peripherals -----------------------------------------------------------------------
sseg_out : out std_logic_vector(7 downto 0); -- seven-segment display cathodes (one for each segment)
anode_out : out std_logic_vector(3 downto 0); -- seven-segment display anodes (one for each digit)
led_out : out std_logic_vector(7 downto 0); -- eight LEDs
sw_in : in std_logic_vector(7 downto 0) -- eight switches
);
end entity;
architecture structural of top_level is
-- Channel read/write interface -----------------------------------------------------------------
signal chanAddr : std_logic_vector(6 downto 0); -- the selected channel (0-127)
-- Host >> FPGA pipe:
signal h2fData : std_logic_vector(7 downto 0); -- data lines used when the host writes to a channel
signal h2fValid : std_logic; -- '1' means "on the next clock rising edge, please accept the data on h2fData"
signal h2fReady : std_logic; -- channel logic can drive this low to say "I'm not ready for more data yet"
-- Host << FPGA pipe:
signal f2hData : std_logic_vector(7 downto 0); -- data lines used when the host reads from a channel
signal f2hValid : std_logic; -- channel logic can drive this low to say "I don't have data ready for you"
signal f2hReady : std_logic; -- '1' means "on the next clock rising edge, put your next byte of data on f2hData"
-- ----------------------------------------------------------------------------------------------
signal eppReset : std_logic;
begin
-- CommFPGA module
comm_fpga_epp : entity work.comm_fpga_epp
port map(
clk_in => sysClk_in,
reset_in => '0',
reset_out => eppReset,
-- EPP interface
eppData_io => eppData_io,
eppAddrStb_in => eppAddrStb_in,
eppDataStb_in => eppDataStb_in,
eppWrite_in => eppWrite_in,
eppWait_out => eppWait_out,
-- DVR interface -> Connects to application module
chanAddr_out => chanAddr,
h2fData_out => h2fData,
h2fValid_out => h2fValid,
h2fReady_in => h2fReady,
f2hData_in => f2hData,
f2hValid_in => f2hValid,
f2hReady_out => f2hReady
);
-- Switches & LEDs application
swled_app : entity work.swled
port map(
clk_in => sysClk_in,
reset_in => eppReset,
-- DVR interface -> Connects to comm_fpga module
chanAddr_in => chanAddr,
h2fData_in => h2fData,
h2fValid_in => h2fValid,
h2fReady_out => h2fReady,
f2hData_out => f2hData,
f2hValid_out => f2hValid,
f2hReady_in => f2hReady,
-- External interface
sseg_out => sseg_out,
anode_out => anode_out,
led_out => led_out,
sw_in => sw_in
);
end architecture;
| gpl-3.0 | 300d0824979e7f9b429394fb9ab3957c | 0.589792 | 3.70425 | false | false | false | false |
karvonz/Mandelbrot | src_vhd/Colorgen.vhd | 2 | 74,636 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library WORK;
use WORK.CONSTANTS.ALL;
use WORK.FUNCTIONS.ALL;
entity Colorgen is
Port ( iters : in STD_LOGIC_VECTOR (ITER_RANGE-1 downto 0);
itermax : in STD_LOGIC_VECTOR (ITER_RANGE-1 downto 0);
color : out STD_LOGIC_VECTOR (bit_per_pixel-1 downto 0));
end Colorgen;
architecture Behavioral of Colorgen is -- TODO : Améliorer colorgen (comparaison OpenGL)
type rom_type is array (0 to ITER_MAX-1) of std_logic_vector (bit_per_pixel-1 downto 0);
constant color_scheme : rom_type := (
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000110",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000000111",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001000",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001001",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001010",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001011",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001100",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001101",
"000000001110",
"000000001110",
"000000001110",
"000000001110",
"000000001110",
"000000001110",
"000000001110",
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begin
process(iters, itermax)
begin
--color <= not iters;
if (iters = itermax) then
color<= (others=>'0');
else
color <= not color_scheme(to_integer(unsigned(iters)));
end if;
end process;end Behavioral;
--Cut and paste following lines into Shared.vhd.
-- constant ITER_MAX : integer := 4095;
-- constant ITER_RANGE : integer := 12;
| gpl-3.0 | afedca7160c42d0f52fe5d35f2aed5e3 | 0.667091 | 3.593625 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Ram/simulation/Ram_synth ([email protected] 2015-09-19-17-37-53).vhd | 1 | 8,143 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
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--------------------------------------------------------------------------------
--
-- Filename: Ram_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY Ram_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE Ram_synth_ARCH OF Ram_synth IS
COMPONENT Ram_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 32,
READ_WIDTH => 32 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: Ram_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| mit | 128ffb570395d0835d0bdb368171ab93 | 0.544271 | 3.768163 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Font/simulation/Font_tb_checker.vhd | 1 | 5,682 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Font_tb_checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.Font_TB_PKG.ALL;
ENTITY Font_TB_CHECKER IS
GENERIC (
WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END Font_TB_CHECKER;
ARCHITECTURE CHECKER_ARCH OF Font_TB_CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DGEN_INST:ENTITY work.Font_TB_DGEN
GENERIC MAP (
DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
| mit | 45d867fc1cc35351c718a8597d3db063 | 0.585357 | 4.049893 | false | false | false | false |
chibby0ne/vhdl-book | Chapter3/user_defined_types_dir/user_defined_types.vhd | 1 | 1,499 | -- integer types --
-- type type_nam is range range_specifications;
type negative is range integer'low to -1;
type temperature is range 0 to 273;
type my_integer is range -32 to 32;
-- enumerated type --
-- type type_name is (type_values_list);
type bit is ('0', '1');
type boolean is (FALSE, TRUE);
type std_ulogic is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
-- array types (integer array types) --
-- type type_name is array (range_specs) of element_types
-- type type_name is array (range_specs) of element_types
type bit_vector is array (natural range <>) of bit;
type boolean_vector is array (natural range <>) of boolean;
type integer_vector is array (natural range <>) of integer;
type std_ulogic_vector is array (natural range <>) of std_logic;
-- 1D x 1D
type type1 is array (positive range <>) of integer;
constant const1: type1(1 to 4) := (5, -5, 3, 0);
type type2 is array (0 to 3) of natural;
constant const2: type2 := (2, 0, 9, 4);
------------------------------
-- 1D x 1D x 1D
type type3 is array (1 to 2) of type2;
const const3: type3 := ((5, 5, 7, 99), (33, 4, 0, 0));
-- enumerated type
-- type type_name is array (range specs) of enum_elements_type;
-- 1D arrays
------------------------------
type type1 is array (natural range <>) of std_logic;
constant const1: type1(4 downto 1) := "Z111";
------------------------------
type type2 is array (7 downto 0) of bit;
constant const2: type2 := "00001111";
------------------------------
-- 1D x 1D array
type tpe
| gpl-3.0 | 6b1acb9dc55c1d27557cd73758e17d16 | 0.610407 | 3.20985 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/dist_mem_gen_v7_2/example_design/dist_mem_gen_v7_2_prod_exdes.vhd | 1 | 5,307 |
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator v6.3 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
--
-- Description:
-- This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity dist_mem_gen_v7_2_exdes is
PORT (
A : IN STD_LOGIC_VECTOR(14-1-(4*0*boolean'pos(14>4)) downto 0)
:= (OTHERS => '0');
D : IN STD_LOGIC_VECTOR(32-1 downto 0) := (OTHERS => '0');
DPRA : IN STD_LOGIC_VECTOR(14-1 downto 0) := (OTHERS => '0');
SPRA : IN STD_LOGIC_VECTOR(14-1 downto 0) := (OTHERS => '0');
CLK : IN STD_LOGIC := '0';
WE : IN STD_LOGIC := '0';
I_CE : IN STD_LOGIC := '1';
QSPO_CE : IN STD_LOGIC := '1';
QDPO_CE : IN STD_LOGIC := '1';
QDPO_CLK : IN STD_LOGIC := '0';
QSPO_RST : IN STD_LOGIC := '0';
QDPO_RST : IN STD_LOGIC := '0';
QSPO_SRST : IN STD_LOGIC := '0';
QDPO_SRST : IN STD_LOGIC := '0';
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
DPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
QSPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
QDPO : OUT STD_LOGIC_VECTOR(32-1 downto 0)
);
end dist_mem_gen_v7_2_exdes;
architecture xilinx of dist_mem_gen_v7_2_exdes is
component dist_mem_gen_v7_2 is
PORT (
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
A : IN STD_LOGIC_VECTOR(14-1-(4*0*boolean'pos(14>4)) downto 0)
:= (OTHERS => '0')
);
end component;
begin
dmg0 : dist_mem_gen_v7_2
port map (
SPO => SPO,
A => A
);
end xilinx;
| mit | 18cf2830461137f4233afbb0ea4d3fdf | 0.497456 | 4.486052 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Video_Memory/simulation/Video_Memory_tb_synth.vhd | 1 | 9,958 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Video_Memory_tb_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.Video_Memory_TB_PKG.ALL;
ENTITY Video_Memory_tb_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 0
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END Video_Memory_tb_synth;
ARCHITECTURE Video_Memory_synth_ARCH OF Video_Memory_tb_synth IS
COMPONENT Video_Memory_exdes
PORT (
DPRA : IN STD_LOGIC_VECTOR(12-1 downto 0) := (OTHERS => '0');
CLK : IN STD_LOGIC := '0';
WE : IN STD_LOGIC := '0';
SPO : OUT STD_LOGIC_VECTOR(16-1 downto 0);
DPO : OUT STD_LOGIC_VECTOR(16-1 downto 0);
A : IN STD_LOGIC_VECTOR(12-1-(4*0*boolean'pos(12>4)) downto 0)
:= (OTHERS => '0');
D : IN STD_LOGIC_VECTOR(16-1 downto 0) := (OTHERS => '0')
);
END COMPONENT;
CONSTANT STIM_CNT : INTEGER := if_then_else(C_ROM_SYNTH = 0, 8, 22);
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i : STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ADDR: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDR_R: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DPRA: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DPRA_R: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL WE : STD_LOGIC:='0';
SIGNAL WE_R : STD_LOGIC:='0';
SIGNAL SPO: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL SPO_R: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DPO: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DPO_R: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL D: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL D_R: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_DATA_TDP : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECKER_EN_R: STD_LOGIC:='0';
SIGNAL CHECKER_ENB_R : STD_LOGIC := '0';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
Video_Memory_TB_STIM_GEN_INST:ENTITY work.Video_Memory_TB_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
A => ADDR,
D => D,
DPRA => DPRA,
WE => WE,
DATA_IN => SPO_R,
DATA_IN_B => DPO_R,
CHECK_DATA => CHECK_DATA_TDP
);
DMG_DATA_CHECKER_INST_A: ENTITY work.Video_Memory_TB_CHECKER
GENERIC MAP (
WRITE_WIDTH => 16,
READ_WIDTH => 16 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => SPO_R,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECK_DATA_TDP(0) AFTER 50 ns;
END IF;
END IF;
END PROCESS;
DMG_DATA_CHECKER_INST_B: ENTITY work.Video_Memory_TB_CHECKER
GENERIC MAP (
WRITE_WIDTH => 16,
READ_WIDTH => 16 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_ENB_R,
DATA_IN => DPO_R,
STATUS => ISSUE_FLAG(1)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_ENB_R <= '0';
ELSE
CHECKER_ENB_R <= CHECK_DATA_TDP(1) AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(STIM_CNT);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDR(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW + 1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
DPRA_R <= (OTHERS=>'0') AFTER 50 ns;
WE_R <= '0' AFTER 50 ns;
SPO_R <= (OTHERS=>'0') AFTER 50 ns;
DPO_R <= (OTHERS=>'0') AFTER 50 ns;
D_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
DPRA_R <= DPRA AFTER 50 ns;
WE_R <= WE AFTER 50 ns;
SPO_R <= SPO AFTER 50 ns;
DPO_R <= DPO AFTER 50 ns;
D_R <= D AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDR_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDR_R <= ADDR AFTER 50 ns;
END IF;
END IF;
END PROCESS;
DMG_PORT: Video_Memory_exdes PORT MAP (
DPRA => DPRA_R,
CLK => CLKA,
WE => WE_R,
SPO => SPO,
DPO => DPO,
A => ADDR_R,
D => D_R
);
END ARCHITECTURE;
| mit | b40ed3a4ee3cf11e163ddb0e98119a32 | 0.5237 | 3.705992 | false | false | false | false |
chibby0ne/vhdl-book | Chapter3/array_slicing_2d_dir/array_slicing_2d.vhd | 1 | 925 | ------------------------------
entity array_slices is
--generic declarations
port (
row: in integer range 0 to 3;
column: in integer range 0 to 4;
slice1: out bit ;
slice2: out bit_vector(1 to 2) ;
slice3: out bit_vector(1 to 4) ;
slice4: out bit_vector(1 to 3) ;);
end entity;
------------------------------
architecture circuit of array_slices is
type twod is array (1 to 3, 1 to 4) of bit;
constant table: twod := (('0', '0', '0', '1'),
('1', '0', '0', '1'),
('1', '1', '0', '1'));
begin
slice1 <= table(row)(column);
-- slice2 <= table(row, 1 to 2);
-- slice3 <= table(row, 1 to 4);
-- slice4 <= table(1, column) & table(2, column) & table(3, column);
gen: for i in 1 to 3 generate
slice4(i) <= table(i, column);
end generate;
end architecture;
------------------------------
| gpl-3.0 | e996f89af8cf61ceef76cbf7f7b4f0f6 | 0.469189 | 3.613281 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/xilinx/RAM32X1D.vhd | 1 | 2,686 | -- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/RAM32X1D.vhd,v 1.1 2008/06/19 16:59:25 vandanad Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 11.1
-- \ \ Description : Xilinx Functional Simulation Library Component
-- / / Static Dual Port Synchronous RAM 32-Deep by 1-Wide
-- /___/ /\ Filename : RAM32X1D.vhd
-- \ \ / \ Timestamp : Thu Apr 8 10:56:48 PDT 2004
-- \___\/\___\
--
-- Revision:
-- 03/23/04 - Initial version.
----- CELL RAM32X1D -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library UNISIM;
use UNISIM.VPKG.all;
entity RAM32X1D is
generic (
INIT : bit_vector(31 downto 0) := X"00000000"
);
port (
DPO : out std_ulogic;
SPO : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic;
D : in std_ulogic;
DPRA0 : in std_ulogic;
DPRA1 : in std_ulogic;
DPRA2 : in std_ulogic;
DPRA3 : in std_ulogic;
DPRA4 : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic
);
end RAM32X1D;
architecture RAM32X1D_V of RAM32X1D is
signal MEM : std_logic_vector( 32 downto 0 ) := ('X' & To_StdLogicVector(INIT) );
begin
VITALReadBehavior : process(A0, A1, A2, A3, A4, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0, MEM)
Variable Index_SP : integer := 32 ;
Variable Index_DP : integer := 32 ;
variable Raddress : std_logic_vector (4 downto 0);
variable Waddress : std_logic_vector (4 downto 0);
begin
Waddress := (A4, A3, A2, A1, A0);
Raddress := (DPRA4, DPRA3, DPRA2, DPRA1, DPRA0);
Index_SP := SLV_TO_INT(SLV => Waddress);
Index_DP := SLV_TO_INT(SLV => Raddress);
SPO <= MEM(Index_SP);
DPO <= MEM(Index_DP);
end process VITALReadBehavior;
VITALWriteBehavior : process(WCLK)
variable Index_SP : integer := 32;
variable Index_DP : integer := 32;
variable Address : std_logic_vector( 4 downto 0);
begin
Address := (A4, A3, A2, A1, A0);
Index_SP := SLV_TO_INT(SLV => Address );
if ((WE = '1') and (wclk'event) and (wclk'last_value = '0') and (wclk = '1')) then
MEM(Index_SP) <= D after 100 ps;
end if;
end process VITALWriteBehavior;
end RAM32X1D_V;
| gpl-3.0 | 527e0764def13cc385f97e695f5187c5 | 0.527178 | 3.259709 | false | false | false | false |
makestuff/swled | fifo/vhdl/fifo-gen/fifo_wrapper_xilinx.vhdl | 1 | 2,005 | --
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo_wrapper is
port(
-- Clock and depth
clk_in : in std_logic;
depth_out : out std_logic_vector(7 downto 0);
-- Data is clocked into the FIFO on each clock edge where both valid & ready are high
inputData_in : in std_logic_vector(7 downto 0);
inputValid_in : in std_logic;
inputReady_out : out std_logic;
-- Data is clocked out of the FIFO on each clock edge where both valid & ready are high
outputData_out : out std_logic_vector(7 downto 0);
outputValid_out : out std_logic;
outputReady_in : in std_logic
);
end entity;
architecture structural of fifo_wrapper is
signal inputFull : std_logic;
signal outputEmpty : std_logic;
begin
-- Invert "full/empty" signals to give "ready/valid" signals
inputReady_out <= not(inputFull);
outputValid_out <= not(outputEmpty);
-- The encapsulated FIFO
fifo : entity work.xilinx_fifo
port map(
clk => clk_in,
data_count => depth_out,
-- Production end
din => inputData_in,
wr_en => inputValid_in,
full => inputFull,
-- Consumption end
dout => outputData_out,
empty => outputEmpty,
rd_en => outputReady_in
);
end architecture;
| gpl-3.0 | 63019dcf6911cf64047566293d7d237f | 0.687781 | 3.59319 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/coproc_2.vhd | 2 | 3,581 | ---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
use work.cam_pkg.all;
entity coproc_2 is
port(
clock : in std_logic;
reset : in std_logic;
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_1_valid : in std_logic;
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of coproc_2 is
signal min_reg : unsigned(7 downto 0);
signal beta_reg : unsigned(15 downto 0);
signal beta_tmp : unsigned(15 downto 0);
signal min_tmp, max_tmp : unsigned(7 downto 0);
signal store_min_beta : std_logic;
signal a,b : unsigned(15 downto 0);
signal OUTPUT_1_tmp : std_logic_vector(31 downto 0);
begin
-------------------------------------------------------------------------
scaling_computation : process (INPUT_1, min_reg, beta_reg)
variable mini : UNSIGNED(7 downto 0);
variable data1, data2, data3, data4 : UNSIGNED(7 downto 0);
variable diff1, diff2, diff3, diff4 : UNSIGNED(7 downto 0);
variable mult1, mult2, mult3, mult4 : UNSIGNED(23 downto 0);
begin
data1 := UNSIGNED( INPUT_1(7 downto 0) );
data2 := UNSIGNED( INPUT_1(15 downto 8) );
data3 := UNSIGNED( INPUT_1(23 downto 16) );
data4 := UNSIGNED( INPUT_1(31 downto 24) );
diff1 := data1 - min_reg; -- 8
diff2 := data2 - min_reg; -- 8
diff3 := data3 - min_reg; -- 8
diff4 := data4 - min_reg; -- 8
mult1 := diff1 * beta_reg; -- 24
mult2 := diff2 * beta_reg; -- 24
mult3 := diff3 * beta_reg; -- 24
mult4 := diff4 * beta_reg; -- 24
OUTPUT_1_tmp(7 downto 0) <= std_logic_vector(mult1(15 downto 8));
OUTPUT_1_tmp(15 downto 8) <= std_logic_vector(mult2(15 downto 8));
OUTPUT_1_tmp(23 downto 16) <= std_logic_vector(mult3(15 downto 8));
OUTPUT_1_tmp(31 downto 24) <= std_logic_vector(mult4(15 downto 8));
end process;
-------------------------------------------------------------------------
max_tmp <= UNSIGNED(INPUT_1(7 downto 0));
min_tmp <= UNSIGNED(INPUT_1(15 downto 8));
b <= "00000000"&(max_tmp-min_tmp);
a <= TO_UNSIGNED( 255, 8)&"00000000";
--beta_tmp <= divide(TO_UNSIGNED( 255, 8), (max_tmp-min_tmp));
beta_tmp <= divide(a,b); --(8,8)
--beta_tmp <= "00000000"&max_tmp-min_tmp;
-------------------------------------------------------------------------
process (clock, reset)
begin
IF clock'event AND clock = '1' THEN
IF reset = '1' THEN
store_min_beta <= '1';
min_reg <= (others => '0');
beta_reg <= (others => '0');
OUTPUT_1 <= (others => '0');
ELSE
IF (INPUT_1_valid = '1' and store_min_beta ='1') THEN
store_min_beta <= '0';
min_reg <= UNSIGNED(INPUT_1(15 downto 8));
beta_reg <= beta_tmp;
OUTPUT_1 <= INPUT_1;
ELSIF (INPUT_1_valid = '1' and store_min_beta = '0') THEN
store_min_beta <= '0';
min_reg <= min_reg;
beta_reg <= beta_reg;
OUTPUT_1 <= OUTPUT_1_tmp;
--OUTPUT_1 <= "000000000000000000000000"&std_logic_vector(min_reg);
END IF;
END IF;
END IF;
end process;
-------------------------------------------------------------------------
end; --architecture logic
| gpl-3.0 | c29b8f1053fefeb4a361e4a255bb92a0 | 0.550405 | 3.183111 | false | false | false | false |
chibby0ne/vhdl-book | Chapter5/exercise5_1_dir/exercise5_1.vhd | 1 | 724 | -- author: Antonio Gutierrez
-- date: 09/10/13
-- description:
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------
entity ent is
--generic declarations
port (
x: in std_logic_vector(2 downto 0);
y: out std_logic_vector(1 downto 0));
end entity;
--------------------------------------
architecture circuit of ent is
--signals and declarations
begin
y(0) <= '1' when not x(2) or (x(1) and x(0)
else '0';);
y(1) <= '1' when x(1)
else '0';
-- with x select
-- y <= "01" when "0--",
-- <= "10" when "11-",
-- <= "00" when others;
end architecture;
--------------------------------------
| gpl-3.0 | 5551fc19fe3f8b4cbcd79cb4366f428f | 0.437845 | 3.712821 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/LDPC/XOR_MIN_8b.vhd | 1 | 2,058 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library ims;
--use ims.coprocessor.all;
entity XOR_MIN_8b is
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end;
architecture rtl of XOR_MIN_8b is
begin
-------------------------------------------------------------------------
PROCESS (INPUT_1, INPUT_2)
VARIABLE rTemp1 : STD_LOGIC_VECTOR(7 downto 0);
VARIABLE rTemp2 : STD_LOGIC_VECTOR(7 downto 0);
VARIABLE rTemp3 : STD_LOGIC_VECTOR(7 downto 0);
VARIABLE rTemp4 : STD_LOGIC_VECTOR(7 downto 0);
begin
-- ON TRAITE LE PREMIER MOT DE 8 BITS CONTENU DANS LES OPERANDES
if( UNSIGNED(INPUT_1( 6 downto 0)) < UNSIGNED(INPUT_2( 6 downto 0)) ) then rTemp1(6 downto 0) := INPUT_1( 6 downto 0); else rTemp1(6 downto 0) := INPUT_2( 6 downto 0); end if;
rTemp1(7) := INPUT_1(7) xor INPUT_2(7);
-- ON TRAITE LE SECOND MOT DE 8 BITS CONTENU DANS LES OPERANDES
if( UNSIGNED(INPUT_1(14 downto 8)) < UNSIGNED(INPUT_2(14 downto 8)) ) then rTemp2(6 downto 0) := INPUT_1(14 downto 8); else rTemp2(6 downto 0) := INPUT_2(14 downto 8); end if;
rTemp2(7) := INPUT_1(15) xor INPUT_2(15);
-- ON TRAITE LE TROISIEME MOT DE 8 BITS CONTENU DANS LES OPERANDES
if( UNSIGNED(INPUT_1(22 downto 16)) < UNSIGNED(INPUT_2(22 downto 16)) ) then rTemp3(6 downto 0) := INPUT_1(22 downto 16); else rTemp3(6 downto 0) := INPUT_2(22 downto 16); end if;
rTemp3(7) := INPUT_1(23) xor INPUT_2(23);
-- ON TRAITE LE QUATRIEME MOT DE 8 BITS CONTENU DANS LES OPERANDES
if( UNSIGNED(INPUT_1(30 downto 24)) < UNSIGNED(INPUT_2(30 downto 24)) ) then rTemp4(6 downto 0) := INPUT_1(30 downto 24); else rTemp4(6 downto 0) := INPUT_2(30 downto 24); end if;
rTemp4(7) := INPUT_1(31) xor INPUT_2(31);
-- ON REGROUPE LES 4 MOTS AFIN DE RECONSTITUER LE RESULTAT SUR 32 BITS
OUTPUT_1 <= (rTemp4 & rTemp3 & rTemp2 & rTemp1);
END PROCESS;
-------------------------------------------------------------------------
end;
| gpl-3.0 | 377a2e5ce2cc9ed3628d6d71a4d106c6 | 0.624393 | 2.991279 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/MMX/MMX_SUM_8b.vhd | 1 | 2,095 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library ims;
--use ims.coprocessor.all;
entity MMX_SUM_8b is
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end;
architecture rtl of MMX_SUM_8b is
begin
-------------------------------------------------------------------------
-- synthesis translate_off
process
begin
wait for 1 ns;
REPORT "(IMS) MMX 8bis ADD RESSOURCE : ALLOCATION OK !";
wait;
end process;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable opCode : STD_LOGIC_VECTOR(8 downto 0);
variable rTemp1 : STD_LOGIC_VECTOR(7 downto 0);
variable rTemp2 : STD_LOGIC_VECTOR(7 downto 0);
variable rTemp3 : STD_LOGIC_VECTOR(7 downto 0);
variable rTemp4 : STD_LOGIC_VECTOR(7 downto 0);
variable rTempS1 : UNSIGNED( 8 downto 0);
variable rTempS2 : UNSIGNED( 8 downto 0);
variable rTempS3 : UNSIGNED( 8 downto 0);
variable rTempS4 : UNSIGNED( 8 downto 0);
variable rTempS5 : UNSIGNED( 9 downto 0);
variable rTempS6 : UNSIGNED( 9 downto 0);
variable rTempS7 : UNSIGNED(10 downto 0);
begin
rTempS1 := UNSIGNED('0' & INPUT_1( 7 downto 0)) + UNSIGNED('0' & INPUT_2( 7 downto 0));
rTempS2 := UNSIGNED('0' & INPUT_1(15 downto 8)) + UNSIGNED('0' & INPUT_2(15 downto 8));
rTempS3 := UNSIGNED('0' & INPUT_1(23 downto 16)) + UNSIGNED('0' & INPUT_2(23 downto 16));
rTempS4 := UNSIGNED('0' & INPUT_1(31 downto 24)) + UNSIGNED('0' & INPUT_2(31 downto 24));
rTempS5 := UNSIGNED('0' & rTempS1) + UNSIGNED('0' & rTempS2);
rTempS6 := UNSIGNED('0' & rTempS3) + UNSIGNED('0' & rTempS4);
rTempS7 := UNSIGNED('0' & rTempS5) + UNSIGNED('0' & rTempS6);
OUTPUT_1 <= "000000000000000000000" & STD_LOGIC_VECTOR(rTempS7);
end process;
-------------------------------------------------------------------------
end;
| gpl-3.0 | c6384160ea616449337824229dd14fa9 | 0.565155 | 3.362761 | false | false | false | false |
YosysHQ/nextpnr | machxo2/examples/tinyfpga.vhd | 2 | 604 | library ieee ;
context ieee.ieee_std_context;
use work.components.all;
entity top is
port (
pin1: out std_logic
);
attribute LOC: string;
attribute LOC of pin1: signal is "13";
end;
architecture arch of top is
signal clk: std_logic;
signal led_timer: unsigned(23 downto 0) := (others=>'0');
begin
internal_oscillator_inst: OSCH
generic map (
NOM_FREQ => "16.63"
)
port map (
STDBY => '0',
OSC => clk
);
process(clk)
begin
if rising_edge(clk) then
led_timer <= led_timer + 1;
end if;
end process;
pin1 <= led_timer(led_timer'left);
end;
| isc | 0cf03558eab68a854c470dedc60395f6 | 0.624172 | 3.162304 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/pipeline.vhd | 1 | 6,178 | ---------------------------------------------------------------------
-- TITLE: Pipeline
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 6/24/02
-- FILENAME: pipeline.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Controls the three stage pipeline by delaying the signals:
-- a_bus, b_bus, alu/shift/mult_func, c_source, and rs_index.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
--Note: sigD <= sig after rising_edge(clk)
entity pipeline is
port(clk : in std_logic;
reset : in std_logic;
a_bus : in std_logic_vector(31 downto 0);
a_busD : out std_logic_vector(31 downto 0);
b_bus : in std_logic_vector(31 downto 0);
b_busD : out std_logic_vector(31 downto 0);
alu_func : in alu_function_type;
alu_funcD : out alu_function_type;
shift_func : in shift_function_type;
shift_funcD : out shift_function_type;
mult_func : in mult_function_type;
mult_funcD : out mult_function_type;
calu_1_func : in std_logic_vector(5 downto 0);
calu_1_funcD : out std_logic_vector(5 downto 0);
salu_1_func : in std_logic_vector(5 downto 0);
salu_1_funcD : out std_logic_vector(5 downto 0);
reg_dest : in std_logic_vector(31 downto 0);
reg_destD : out std_logic_vector(31 downto 0);
rd_index : in std_logic_vector(5 downto 0);
rd_indexD : out std_logic_vector(5 downto 0);
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
pc_source : in pc_source_type;
mem_source : in mem_source_type;
a_source : in a_source_type;
b_source : in b_source_type;
c_source : in c_source_type;
c_bus : in std_logic_vector(31 downto 0);
pause_any : in std_logic;
pause_pipeline : out std_logic);
end; --entity pipeline
architecture logic of pipeline is
signal rd_index_reg : std_logic_vector(5 downto 0);
signal reg_dest_reg : std_logic_vector(31 downto 0);
signal reg_dest_delay : std_logic_vector(31 downto 0);
signal c_source_reg : c_source_type;
signal pause_enable_reg : std_logic;
begin
--When operating in three stage pipeline mode, the following signals
--are delayed by one clock cycle: a_bus, b_bus, alu / shift / mult_func,
--c_source, and rd_index.
pipeline3: process(clk, reset, a_bus, b_bus, alu_func, shift_func, mult_func,
rd_index, rd_index_reg, pause_any, pause_enable_reg,
rs_index, rt_index,
pc_source, mem_source, a_source, b_source, c_source, c_source_reg,
reg_dest, reg_dest_reg, reg_dest_delay, c_bus)
variable pause_mult_clock : std_logic;
variable freeze_pipeline : std_logic;
begin
if (pc_source /= FROM_INC4 and pc_source /= FROM_OPCODE25_0)
or mem_source /= MEM_FETCH
-- BEGIN ENABLE_(MFLO)
or (mult_func = MULT_READ_LO)
-- END ENABLE_(MFLO)
-- BEGIN ENABLE_(MFHI)
or (mult_func = MULT_READ_HI)
-- END ENABLE_(MFHI)
then
pause_mult_clock := '1';
else
pause_mult_clock := '0';
end if;
freeze_pipeline := not (pause_mult_clock and pause_enable_reg) and pause_any;
pause_pipeline <= pause_mult_clock and pause_enable_reg;
rd_indexD <= rd_index_reg;
-- The value written back into the register bank, signal reg_dest is tricky.
-- If reg_dest comes from the ALU via the signal c_bus, it is already delayed
-- into stage #3, because a_busD and b_busD are delayed. If reg_dest comes from
-- c_memory, pc_current, or pc_plus4 then reg_dest hasn't yet been delayed into
-- stage #3.
-- Instead of delaying c_memory, pc_current, and pc_plus4, these signals
-- are multiplexed into reg_dest which is then delayed. The decision to use
-- the already delayed c_bus or the delayed value of reg_dest (reg_dest_reg) is
-- based on a delayed value of c_source (c_source_reg).
if c_source_reg = C_FROM_ALU then
reg_dest_delay <= c_bus; --delayed by 1 clock cycle via a_busD & b_busD
else
reg_dest_delay <= reg_dest_reg; --need to delay 1 clock cycle from reg_dest
end if;
reg_destD <= reg_dest_delay;
if reset = '1' then
a_busD <= ZERO;
b_busD <= ZERO;
alu_funcD <= ALU_NOTHING;
shift_funcD <= SHIFT_NOTHING;
mult_funcD <= MULT_NOTHING;
calu_1_funcD <= "000000";
salu_1_funcD <= "000000";
reg_dest_reg <= ZERO;
c_source_reg <= "000";
rd_index_reg <= "000000";
pause_enable_reg <= '0';
elsif rising_edge(clk) then
if freeze_pipeline = '0' then
if (rs_index = "000000" or rs_index /= rd_index_reg) or
(a_source /= A_FROM_REG_SOURCE or pause_enable_reg = '0') then
a_busD <= a_bus;
else
a_busD <= reg_dest_delay; --rs from previous operation (bypass stage)
end if;
if (rt_index = "000000" or rt_index /= rd_index_reg) or
(b_source /= B_FROM_REG_TARGET or pause_enable_reg = '0') then
b_busD <= b_bus;
else
b_busD <= reg_dest_delay; --rt from previous operation
end if;
alu_funcD <= alu_func;
shift_funcD <= shift_func;
mult_funcD <= mult_func;
calu_1_funcD <= calu_1_func;
salu_1_funcD <= salu_1_func;
reg_dest_reg <= reg_dest;
c_source_reg <= c_source;
rd_index_reg <= rd_index;
end if;
if pause_enable_reg = '0' and pause_any = '0' then
pause_enable_reg <= '1'; --enable pause_pipeline
elsif pause_mult_clock = '1' then
pause_enable_reg <= '0'; --disable pause_pipeline
end if;
end if;
end process; --pipeline3
end; --logic
| gpl-3.0 | fd3c2e6638d32bb6a233ae760bcb8e3f | 0.576886 | 3.28967 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/OTHERS/DIVIDER_AND_MODULUS_32b.vhd | 1 | 3,184 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
entity DIVIDER_AND_MODULUS_32b is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
start : in STD_LOGIC;
flush : in std_logic;
holdn : in std_ulogic;
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
FONCTION : in STD_LOGIC_VECTOR(1 downto 0);
ready : out std_logic;
nready : out std_logic;
icc : out std_logic_vector(3 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end DIVIDER_AND_MODULUS_32b;
-- ready = 0 indique que le circuit est pret a calculer
-- 1 signifie que le circuit est occupe
-- nready = 1 indique que le calcul est termine (1 cycle suffit)
architecture behav of DIVIDER_AND_MODULUS_32b is
signal buf : STD_LOGIC_VECTOR(63 downto 0);
signal dbuf : STD_LOGIC_VECTOR(31 downto 0);
signal sm : INTEGER range 0 to 32;
alias buf1 is buf(63 downto 32);
alias buf2 is buf(31 downto 0);
signal fFunction : std_logic;
begin
ICC <= "0000";
-------------------------------------------------------------------------
reg : process(rst, clk)
variable sready, snready : std_logic;
begin
sready := '0';
snready := '0';
-- Si l'on recoit une demande de reset alors on reinitialise
if rst = '0' then
OUTPUT_1 <= (others => '0');
sm <= 0;
ready <= '0';
ready <= sready;
nready <= snready;
fFunction <= '0';
-- En cas de front montant de l'horloge alors on calcule
elsif rising_edge(clk) then
-- Si Flush alors on reset le composant
if (flush = '1') then
sm <= 0;
-- Si le signal de maintient est actif alors on gel l'execution
elsif (holdn = '0') then
sm <= sm;
-- Sinon on déroule l'execution de la division
else
case sm is
-- Etat d'attente du signal start
when 0 =>
if( fFunction = '1' ) then
OUTPUT_1 <= buf2; -- ON RETOURNE LE RESULTAT DE LA DIVISION
else
OUTPUT_1 <= buf1; -- ON RETOURNE LE RESTE DE LA DIVISION (MODULO)
end if;
if start = '1' then
buf1 <= (others => '0');
buf2 <= INPUT_1;
dbuf <= INPUT_2;
sm <= sm + 1; -- le calcul est en cours
fFunction <= FONCTION(0);
else
sm <= sm;
end if;
-- Tous les autres états sont utiles au calcul
when others =>
sready := '1'; -- le calcul est en cours
sm <= 0;
if buf(62 downto 31) >= dbuf then
buf1 <= '0' & (buf(61 downto 31) - dbuf(30 downto 0));
buf2 <= buf2(30 downto 0) & '1';
else
buf <= buf(62 downto 0) & '0';
end if;
if sm /= 32 then
sm <= sm + 1;
snready := '0'; -- le resultat n'est pas disponible
else
snready := '1'; -- le resultat du calcul est disponible
sm <= 0;
end if;
end case;
-- On transmet les signaux au systeme
ready <= sready;
nready <= snready;
end if; -- Fin du process de calcul
end if;
end process;
end behav;
| gpl-3.0 | f1299bb9e2601069059f3ebb33761304 | 0.550879 | 3.168159 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Instruction_Memory/example_design/Instruction_Memory_prod_exdes.vhd | 1 | 5,312 |
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator v6.3 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
--
-- Description:
-- This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity Instruction_Memory_exdes is
PORT (
A : IN STD_LOGIC_VECTOR(12-1-(4*0*boolean'pos(12>4)) downto 0)
:= (OTHERS => '0');
D : IN STD_LOGIC_VECTOR(32-1 downto 0) := (OTHERS => '0');
DPRA : IN STD_LOGIC_VECTOR(12-1 downto 0) := (OTHERS => '0');
SPRA : IN STD_LOGIC_VECTOR(12-1 downto 0) := (OTHERS => '0');
CLK : IN STD_LOGIC := '0';
WE : IN STD_LOGIC := '0';
I_CE : IN STD_LOGIC := '1';
QSPO_CE : IN STD_LOGIC := '1';
QDPO_CE : IN STD_LOGIC := '1';
QDPO_CLK : IN STD_LOGIC := '0';
QSPO_RST : IN STD_LOGIC := '0';
QDPO_RST : IN STD_LOGIC := '0';
QSPO_SRST : IN STD_LOGIC := '0';
QDPO_SRST : IN STD_LOGIC := '0';
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
DPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
QSPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
QDPO : OUT STD_LOGIC_VECTOR(32-1 downto 0)
);
end Instruction_Memory_exdes;
architecture xilinx of Instruction_Memory_exdes is
component Instruction_Memory is
PORT (
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
A : IN STD_LOGIC_VECTOR(12-1-(4*0*boolean'pos(12>4)) downto 0)
:= (OTHERS => '0')
);
end component;
begin
dmg0 : Instruction_Memory
port map (
SPO => SPO,
A => A
);
end xilinx;
| mit | d44292b8419f305b103cd83e05f9e9bd | 0.500753 | 4.627178 | false | false | false | false |
VLSI-EDA/UVVM_All | bitvis_irqc/tb/irqc_demo_tb.vhd | 1 | 19,059 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis IRQC Library : irqc_demo_tb
--
-- Description : See dedicated powerpoint presentation and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library STD;
use std.env.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library bitvis_vip_sbi;
use bitvis_vip_sbi.sbi_bfm_pkg.all;
use work.irqc_pif_pkg.all;
-- Test case entity
entity irqc_demo_tb is
end entity;
-- Test case architecture
architecture func of irqc_demo_tb is
-- DSP interface and general control signals
signal clk : std_logic := '0';
signal arst : std_logic := '0';
-- CPU interface
signal sbi_if : t_sbi_if(addr(2 downto 0), wdata(7 downto 0), rdata(7 downto 0)) := init_sbi_if_signals(3, 8);
-- Interrupt related signals
signal irq_source : std_logic_vector(C_NUM_SOURCES-1 downto 0) := (others => '0');
signal irq2cpu : std_logic := '0';
signal irq2cpu_ack : std_logic := '0';
signal clock_ena : boolean := false;
constant C_CLK_PERIOD : time := 10 ns;
subtype t_irq_source is std_logic_vector(C_NUM_SOURCES-1 downto 0);
-- Trim (cut) a given vector to fit the number of irq sources (i.e. pot. reduce width)
function trim(
constant source : std_logic_vector;
constant num_bits : positive := C_NUM_SOURCES)
return t_irq_source is
variable v_result : std_logic_vector(source'length-1 downto 0) := source;
begin
return v_result(num_bits-1 downto 0);
end;
-- Fit a given vector to the number of irq sources by masking with zeros above irq width
function fit(
constant source : std_logic_vector;
constant num_bits : positive := C_NUM_SOURCES)
return std_logic_vector is
variable v_result : std_logic_vector(source'length-1 downto 0) := (others => '0');
variable v_source : std_logic_vector(source'length-1 downto 0) := source;
begin
v_result(num_bits-1 downto 0) := v_source(num_bits-1 downto 0);
return v_result;
end;
begin
-----------------------------------------------------------------------------
-- Instantiate DUT
-----------------------------------------------------------------------------
i_irqc: entity work.irqc
port map (
-- DSP interface and general control signals
clk => clk,
arst => arst,
-- CPU interface
cs => sbi_if.cs,
addr => sbi_if.addr,
wr => sbi_if.wena,
rd => sbi_if.rena,
din => sbi_if.wdata,
dout => sbi_if.rdata,
-- Interrupt related signals
irq_source => irq_source,
irq2cpu => irq2cpu,
irq2cpu_ack => irq2cpu_ack
);
sbi_if.ready <= '1'; -- always ready in the same clock cycle.
-----------------------------------------------------------------------------
-- Clock Generator
-----------------------------------------------------------------------------
clock_generator(clk, clock_ena, C_CLK_PERIOD, "IRQC TB clock");
------------------------------------------------
-- PROCESS: p_main
------------------------------------------------
p_main: process
constant C_SCOPE : string := C_TB_SCOPE_DEFAULT;
-- Overloads for PIF BFMs for SBI (Simple Bus Interface)
procedure write(
constant addr_value : in natural;
constant data_value : in std_logic_vector;
constant msg : in string) is
begin
sbi_write(to_unsigned(addr_value, sbi_if.addr'length), data_value, msg,
clk, sbi_if, C_SCOPE);
end;
procedure check(
constant addr_value : in natural;
constant data_exp : in std_logic_vector;
constant alert_level : in t_alert_level;
constant msg : in string) is
begin
sbi_check(to_unsigned(addr_value, sbi_if.addr'length), data_exp, msg,
clk, sbi_if, alert_level, C_SCOPE);
end;
procedure set_inputs_passive(
dummy : t_void) is
begin
sbi_if.cs <= '0';
sbi_if.addr <= (others => '0');
sbi_if.wena <= '0';
sbi_if.rena <= '0';
sbi_if.wdata <= (others => '0');
irq_source <= (others => '0');
irq2cpu_ack <= '0';
log(ID_SEQUENCER_SUB, "All inputs set passive", C_SCOPE);
end;
variable v_time_stamp : time := 0 ns;
variable v_irq_mask : std_logic_vector(7 downto 0);
variable v_irq_mask_inv : std_logic_vector(7 downto 0);
begin
-- Print the configuration to the log
report_global_ctrl(VOID);
report_msg_id_panel(VOID);
enable_log_msg(ALL_MESSAGES);
--disable_log_msg(ALL_MESSAGES);
--enable_log_msg(ID_LOG_HDR);
log(ID_LOG_HDR, "Start Simulation of TB for IRQC", C_SCOPE);
------------------------------------------------------------
set_inputs_passive(VOID);
clock_ena <= true; -- to start clock generator
gen_pulse(arst, 10 * C_CLK_PERIOD, "Pulsed reset-signal - active for 10T");
v_time_stamp := now; -- time from which irq2cpu should be stable off until triggered
check_value(C_NUM_SOURCES > 0, FAILURE, "Must be at least 1 interrupt source", C_SCOPE);
check_value(C_NUM_SOURCES <= 8, TB_WARNING, "This TB is only checking IRQC with up to 8 interrupt sources", C_SCOPE);
log(ID_LOG_HDR, "Check defaults on output ports", C_SCOPE);
------------------------------------------------------------
check_value(irq2cpu, '0', ERROR, "Interrupt to CPU must be default inactive", C_SCOPE);
check_value(sbi_if.rdata, x"00", ERROR, "Register data bus output must be default passive");
log(ID_LOG_HDR, "Check register defaults and access (write + read)", C_SCOPE);
------------------------------------------------------------
log("\nChecking Register defaults");
check(C_ADDR_IRR, x"00", ERROR, "IRR default");
check(C_ADDR_IER, x"00", ERROR, "IER default");
check(C_ADDR_IPR, x"00", ERROR, "IPR default");
check(C_ADDR_IRQ2CPU_ALLOWED, x"00", ERROR, "IRQ2CPU_ALLOWED default");
log("\nChecking Register Write/Read");
write(C_ADDR_IER, fit(x"55"), "IER");
check(C_ADDR_IER, fit(x"55"), ERROR, "IER pure readback");
write(C_ADDR_IER, fit(x"AA"), "IER");
check(C_ADDR_IER, fit(x"AA"), ERROR, "IER pure readback");
write(C_ADDR_IER, fit(x"00"), "IER");
check(C_ADDR_IER, fit(x"00"), ERROR, "IER pure readback");
log(ID_LOG_HDR, "Check register trigger/clear mechanism", C_SCOPE);
------------------------------------------------------------
write(C_ADDR_ITR, fit(x"AA"), "ITR : Set interrupts");
check(C_ADDR_IRR, fit(x"AA"), ERROR, "IRR");
write(C_ADDR_ITR, fit(x"55"), "ITR : Set more interrupts");
check(C_ADDR_IRR, fit(x"FF"), ERROR, "IRR");
write(C_ADDR_ICR, fit(x"71"), "ICR : Clear interrupts");
check(C_ADDR_IRR, fit(x"8E"), ERROR, "IRR");
write(C_ADDR_ICR, fit(x"85"), "ICR : Clear interrupts");
check(C_ADDR_IRR, fit(x"0A"), ERROR, "IRR");
write(C_ADDR_ITR, fit(x"55"), "ITR : Set more interrupts");
check(C_ADDR_IRR, fit(x"5F"), ERROR, "IRR");
write(C_ADDR_ICR, fit(x"5F"), "ICR : Clear interrupts");
check(C_ADDR_IRR, fit(x"00"), ERROR, "IRR");
log(ID_LOG_HDR, "Check interrupt sources, IER, IPR and irq2cpu", C_SCOPE);
------------------------------------------------------------
log("\nChecking interrupts and IRR");
write(C_ADDR_ICR, fit(x"FF"), "ICR : Clear all interrupts");
gen_pulse(irq_source, trim(x"AA"), clk, 1, "Pulse irq_source 1T");
check(C_ADDR_IRR, fit(x"AA"), ERROR, "IRR after irq pulses");
gen_pulse(irq_source, trim(x"01"), clk, 1, "Add more interrupts");
check(C_ADDR_IRR, fit(x"AB"), ERROR, "IRR after irq pulses");
gen_pulse(irq_source, trim(x"A1"), clk, 1, "Repeat same interrupts");
check(C_ADDR_IRR, fit(x"AB"), ERROR, "IRR after irq pulses");
gen_pulse(irq_source, trim(x"54"), clk, 1, "Add remaining interrupts");
check(C_ADDR_IRR, fit(x"FF"), ERROR, "IRR after irq pulses");
write(C_ADDR_ICR, fit(x"AA"), "ICR : Clear half the interrupts");
gen_pulse(irq_source, trim(x"A0"), clk, 1, "Add more interrupts");
check(C_ADDR_IRR, fit(x"F5"), ERROR, "IRR after irq pulses");
write(C_ADDR_ICR, fit(x"FF"), "ICR : Clear all interrupts");
check(C_ADDR_IRR, fit(x"00"), ERROR, "IRR after clearing all");
log("\nChecking IER, IPR and irq2cpu");
write(C_ADDR_ICR, fit(x"FF"), "ICR : Clear all interrupts");
write(C_ADDR_IER, fit(x"55"), "IER : Enable some interrupts");
write(C_ADDR_ITR, fit(x"AA"), "ITR : Trigger non-enable interrupts");
check(C_ADDR_IPR, fit(x"00"), ERROR, "IPR should not be active");
check(C_ADDR_IRQ2CPU_ALLOWED, x"00", ERROR, "IRQ2CPU_ALLOWED should not be active");
write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Enable main interrupt to CPU");
check(C_ADDR_IRQ2CPU_ALLOWED, x"01", ERROR, "IRQ2CPU_ALLOWED should now be active");
check_value(irq2cpu, '0', ERROR, "Interrupt to CPU must still be inactive", C_SCOPE);
check_stable(irq2cpu, (now - v_time_stamp), ERROR, "No spikes allowed on irq2cpu", C_SCOPE);
gen_pulse(irq_source, trim(x"01"), clk, 1, "Add a single enabled interrupt");
await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt expected immediately", C_SCOPE);
v_time_stamp := now; -- from time of stable active irq2cpu
check(C_ADDR_IRR, fit(x"AB"), ERROR, "IRR should now be active");
check(C_ADDR_IPR, fit(x"01"), ERROR, "IPR should now be active");
log("\nMore details checked in the autonomy section below");
check_value(irq2cpu, '1', ERROR, "Interrupt to CPU must still be active", C_SCOPE);
check_stable(irq2cpu, (now - v_time_stamp), ERROR, "No spikes allowed on irq2cpu", C_SCOPE);
log(ID_LOG_HDR, "Check autonomy for all interrupts", C_SCOPE);
------------------------------------------------------------
write(C_ADDR_ICR, fit(x"FF"), "ICR : Clear all interrupts");
write(C_ADDR_IER, fit(x"FF"), "IER : Disable all interrupts");
write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Allow interrupt to CPU");
for i in 0 to C_NUM_SOURCES-1 loop
log(" ");
log("- Checking irq_source(" & to_string(i) & ") and all corresponding functionality");
log("- - Check interrupt activation not affected by non related interrupts or registers");
v_time_stamp := now; -- from time of stable inactive irq2cpu
v_irq_mask := (others => '0');
v_irq_mask(i) := '1';
v_irq_mask_inv := (others => '1');
v_irq_mask_inv(i) := '0';
write(C_ADDR_IER, v_irq_mask, "IER : Enable selected interrupt");
gen_pulse(irq_source, trim(v_irq_mask_inv), clk, 1, "Pulse all non-enabled interrupts");
write(C_ADDR_ITR, v_irq_mask_inv, "ITR : Trigger all non-enabled interrupts");
check(C_ADDR_IRR, fit(v_irq_mask_inv), ERROR, "IRR not yet triggered");
check(C_ADDR_IPR, x"00", ERROR, "IPR not yet triggered");
check_value(irq2cpu, '0', ERROR, "Interrupt to CPU must still be inactive", C_SCOPE);
check_stable(irq2cpu, (now - v_time_stamp), ERROR, "No spikes allowed on irq2cpu", C_SCOPE);
gen_pulse(irq_source, trim(v_irq_mask), clk, 1, "Pulse the enabled interrupt");
await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt expected immediately", C_SCOPE);
check(C_ADDR_IRR, fit(x"FF"), ERROR, "All IRR triggered");
check(C_ADDR_IPR, v_irq_mask, ERROR, "IPR triggered for selected");
log("\n- - Check interrupt deactivation not affected by non related interrupts or registers");
v_time_stamp := now; -- from time of stable active irq2cpu
write(C_ADDR_ICR, v_irq_mask_inv, "ICR : Clear all non-enabled interrupts");
write(C_ADDR_IER, fit(x"FF"), "IER : Enable all interrupts");
write(C_ADDR_IER, v_irq_mask, "IER : Disable non-selected interrupts");
gen_pulse(irq_source, trim(x"FF"), clk, 1, "Pulse all interrupts");
write(C_ADDR_ITR, x"FF", "ITR : Trigger all interrupts");
check_stable(irq2cpu, (now - v_time_stamp), ERROR, "No spikes allowed on irq2cpu (='1')", C_SCOPE);
write(C_ADDR_IER, v_irq_mask_inv, "IER : Enable all interrupts but disable selected");
check_value(irq2cpu, '1', ERROR, "Interrupt to CPU still active", C_SCOPE);
check(C_ADDR_IRR, fit(x"FF"), ERROR, "IRR still active for all");
write(C_ADDR_ICR, v_irq_mask_inv, "ICR : Clear all non-enabled interrupts");
await_value(irq2cpu, '0', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt deactivation expected immediately", C_SCOPE);
write(C_ADDR_IER, v_irq_mask, "IER : Re-enable selected interrupt");
await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt reactivation expected immediately", C_SCOPE);
check(C_ADDR_IPR, v_irq_mask, ERROR, "IPR still active for selected");
write(C_ADDR_ICR, v_irq_mask, "ICR : Clear selected interrupt");
check_value(irq2cpu, '0', ERROR, "Interrupt to CPU must go inactive", C_SCOPE);
check(C_ADDR_IRR, x"00", ERROR, "IRR all inactive");
check(C_ADDR_IPR, x"00", ERROR, "IPR all inactive");
write(C_ADDR_IER, x"00", "IER : Disable all interrupts");
end loop;
report_alert_counters(INTERMEDIATE); -- Report intermediate counters
log(ID_LOG_HDR, "Check irq acknowledge and re-enable", C_SCOPE);
------------------------------------------------------------
log("- Activate interrupt");
write(C_ADDR_ITR, v_irq_mask, "ICR : Set single upper interrupt");
write(C_ADDR_IER, v_irq_mask, "IER : Enable single upper interrupts");
write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Allow interrupt to CPU");
await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt activation expected", C_SCOPE);
v_time_stamp := now; -- from time of stable active irq2cpu
log("\n- Try potential malfunction");
write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Allow interrupt to CPU again - should not affect anything");
write(C_ADDR_IRQ2CPU_ENA, x"00", "IRQ2CPU_ENA : Set to 0 - should not affect anything");
write(C_ADDR_IRQ2CPU_DISABLE, x"00", "IRQ2CPU_DISABLE : Set to 0 - should not affect anything");
check_stable(irq2cpu, (now - v_time_stamp), ERROR, "No spikes allowed on irq2cpu (='1')", C_SCOPE);
log("\n- Acknowledge and deactivate interrupt");
gen_pulse(irq2cpu_ack, clk, 1, "Pulse irq2cpu_ack");
await_value(irq2cpu, '0', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt deactivation expected", C_SCOPE);
v_time_stamp := now; -- from time of stable inactive irq2cpu
log("\n- Test for potential malfunction");
write(C_ADDR_IRQ2CPU_DISABLE, x"01", "IRQ2CPU_DISABLE : Disable interrupt to CPU again - should not affect anything");
write(C_ADDR_IRQ2CPU_DISABLE, x"00", "IRQ2CPU_DISABLE : Set to 0 - should not affect anything");
write(C_ADDR_IRQ2CPU_ENA, x"00", "IRQ2CPU_ENA : Set to 0 - should not affect anything");
write(C_ADDR_ITR, x"FF", "ICR : Trigger all interrupts");
write(C_ADDR_IER, x"FF", "IER : Enable all interrupts");
gen_pulse(irq_source, trim(x"FF"), clk, 1, "Pulse all interrupts");
gen_pulse(irq2cpu_ack, clk, 1, "Pulse irq2cpu_ack");
check_stable(irq2cpu, (now - v_time_stamp), ERROR, "No spikes allowed on irq2cpu (='0')", C_SCOPE);
log("\n- Re-/de-activation");
write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Reactivate interrupt to CPU");
await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt reactivation expected", C_SCOPE);
write(C_ADDR_IRQ2CPU_DISABLE, x"01", "IRQ2CPU_DISABLE : Deactivate interrupt to CPU");
await_value(irq2cpu, '0', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt deactivation expected", C_SCOPE);
write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Reactivate interrupt to CPU");
await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt reactivation expected", C_SCOPE);
log(ID_LOG_HDR, "Check Reset", C_SCOPE);
------------------------------------------------------------
log("- Activate all interrupts");
write(C_ADDR_ITR, x"FF", "ICR : Set all interrupts");
write(C_ADDR_IER, x"FF", "IER : Enable all interrupts");
write(C_ADDR_IRQ2CPU_ENA, x"01", "IRQ2CPU_ENA : Allow interrupt to CPU");
await_value(irq2cpu, '1', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt activation expected", C_SCOPE);
gen_pulse(arst, clk, 1, "Pulse reset");
await_value(irq2cpu, '0', 0 ns, C_CLK_PERIOD, ERROR, "Interrupt deactivation", C_SCOPE);
check(C_ADDR_IER, x"00", ERROR, "IER all inactive");
check(C_ADDR_IRR, x"00", ERROR, "IRR all inactive");
check(C_ADDR_IPR, x"00", ERROR, "IPR all inactive");
--==================================================================================================
-- Ending the simulation
--------------------------------------------------------------------------------------
wait for 1000 ns; -- to allow some time for completion
report_alert_counters(FINAL); -- Report final counters and print conclusion for simulation (Success/Fail)
log(ID_LOG_HDR, "SIMULATION COMPLETED", C_SCOPE);
-- Finish the simulation
std.env.stop;
wait; -- to stop completely
end process p_main;
end func;
| mit | e2b9d492eaf1c714a602bfd37f7e41f0 | 0.56556 | 3.655351 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/plasma_if.vhd | 1 | 5,137 | ---------------------------------------------------------------------
-- TITLE: Plamsa Interface (clock divider and interface to FPGA board)
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 6/6/02
-- FILENAME: plasma_if.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity divides the clock by two and interfaces to the
-- Altera EP20K200EFC484-2X FPGA board.
-- Xilinx Spartan-3 XC3S200FT256-4 FPGA.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--use work.mlite_pack.all;
entity plasma_if is
port(clk_in : in std_logic;
reset : in std_logic;
uart_read : in std_logic;
uart_write : out std_logic;
ram_address : out std_logic_vector(31 downto 2);
ram_data : inout std_logic_vector(31 downto 0);
ram_ce1_n : out std_logic;
ram_ub1_n : out std_logic;
ram_lb1_n : out std_logic;
ram_ce2_n : out std_logic;
ram_ub2_n : out std_logic;
ram_lb2_n : out std_logic;
ram_we_n : out std_logic;
ram_oe_n : out std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0));
end; --entity plasma_if
architecture logic of plasma_if is
component plasma
generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED");
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0));
end component; --plasma
signal clk_reg : std_logic;
signal we_n_next : std_logic;
signal we_n_reg : std_logic;
signal mem_address : std_logic_vector(31 downto 2);
signal data_write : std_logic_vector(31 downto 0);
signal data_reg : std_logic_vector(31 downto 0);
signal byte_we : std_logic_vector(3 downto 0);
signal mem_pause_in : std_logic;
begin --architecture
--Divide 50 MHz clock by two
clk_div: process(reset, clk_in, clk_reg, we_n_next)
begin
if reset = '1' then
clk_reg <= '0';
elsif rising_edge(clk_in) then
clk_reg <= not clk_reg;
end if;
if reset = '1' then
we_n_reg <= '1';
data_reg <= (others => '0');
elsif falling_edge(clk_in) then
we_n_reg <= we_n_next or not clk_reg;
data_reg <= ram_data;
end if;
end process; --clk_div
mem_pause_in <= '0';
ram_address <= mem_address(31 downto 2);
ram_we_n <= we_n_reg;
--For Xilinx Spartan-3 Starter Kit
ram_control:
process(clk_reg, mem_address, byte_we, data_write)
begin
if mem_address(30 downto 28) = "001" then --RAM
ram_ce1_n <= '0';
ram_ce2_n <= '0';
if byte_we = "0000" then --read
ram_data <= (others => 'Z');
ram_ub1_n <= '0';
ram_lb1_n <= '0';
ram_ub2_n <= '0';
ram_lb2_n <= '0';
we_n_next <= '1';
ram_oe_n <= '0';
else --write
if clk_reg = '1' then
ram_data <= (others => 'Z');
else
ram_data <= data_write;
end if;
ram_ub1_n <= not byte_we(3);
ram_lb1_n <= not byte_we(2);
ram_ub2_n <= not byte_we(1);
ram_lb2_n <= not byte_we(0);
we_n_next <= '0';
ram_oe_n <= '1';
end if;
else
ram_data <= (others => 'Z');
ram_ce1_n <= '1';
ram_ub1_n <= '1';
ram_lb1_n <= '1';
ram_ce2_n <= '1';
ram_ub2_n <= '1';
ram_lb2_n <= '1';
we_n_next <= '1';
ram_oe_n <= '1';
end if;
end process; --ram_control
u1_plama: plasma
generic map (memory_type => "XILINX_16X",
log_file => "UNUSED")
PORT MAP (
clk => clk_reg,
reset => reset,
uart_write => uart_write,
uart_read => uart_read,
address => mem_address,
byte_we => byte_we,
data_write => data_write,
data_read => data_reg,
mem_pause_in => mem_pause_in,
gpio0_out => gpio0_out,
gpioA_in => gpioA_in);
end; --architecture logic
| gpl-3.0 | 264b0ae6e0bd5be4f48b04f87a39ac18 | 0.481215 | 3.466262 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/dist_mem_gen_v7_2/simulation/dist_mem_gen_v7_2_tb_agen.vhd | 1 | 4,482 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: dist_mem_gen_v7_2_tb_agen.vhd
--
-- Description:
-- Address Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY dist_mem_gen_v7_2_TB_AGEN IS
GENERIC (
C_MAX_DEPTH : INTEGER := 1024 ;
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
RST_INC : INTEGER := 0);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
LOAD :IN STD_LOGIC;
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
);
END dist_mem_gen_v7_2_TB_AGEN;
ARCHITECTURE BEHAVIORAL OF dist_mem_gen_v7_2_TB_AGEN IS
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
BEGIN
ADDR_OUT <= ADDR_TEMP;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
IF(EN='1') THEN
IF(LOAD='1') THEN
ADDR_TEMP <=LOAD_VALUE;
ELSE
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
ADDR_TEMP <= ADDR_TEMP + '1';
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
| mit | 19f16f625bf1d4585cfad0336ba3dc9a | 0.580321 | 4.165428 | false | false | false | false |
makestuff/swled | templates/fx2foo/vhdl/top_level.vhdl | 1 | 4,851 | --
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_level is
port(
-- FX2LP interface ---------------------------------------------------------------------------
fx2Clk_in : in std_logic; -- 48MHz clock from FX2LP
fx2Addr_out : out std_logic_vector(1 downto 0); -- select FIFO: "00" for EP2OUT, "10" for EP6IN
fx2Data_io : inout std_logic_vector(7 downto 0); -- 8-bit data to/from FX2LP
-- When EP2OUT selected:
fx2Read_out : out std_logic; -- asserted (active-low) when reading from FX2LP
fx2GotData_in : in std_logic; -- asserted (active-high) when FX2LP has data for us
-- When EP6IN selected:
fx2Write_out : out std_logic; -- asserted (active-low) when writing to FX2LP
fx2GotRoom_in : in std_logic; -- asserted (active-high) when FX2LP has room for more data from us
fx2PktEnd_out : out std_logic; -- asserted (active-low) when a host read needs to be committed early
-- Onboard peripherals -----------------------------------------------------------------------
sseg_out : out std_logic_vector(7 downto 0); -- seven-segment display cathodes (one for each segment)
anode_out : out std_logic_vector(3 downto 0); -- seven-segment display anodes (one for each digit)
led_out : out std_logic_vector(7 downto 0); -- eight LEDs
sw_in : in std_logic_vector(7 downto 0) -- eight switches
);
end entity;
architecture structural of top_level is
-- Channel read/write interface -----------------------------------------------------------------
signal chanAddr : std_logic_vector(6 downto 0); -- the selected channel (0-127)
-- Host >> FPGA pipe:
signal h2fData : std_logic_vector(7 downto 0); -- data lines used when the host writes to a channel
signal h2fValid : std_logic; -- '1' means "on the next clock rising edge, please accept the data on h2fData"
signal h2fReady : std_logic; -- channel logic can drive this low to say "I'm not ready for more data yet"
-- Host << FPGA pipe:
signal f2hData : std_logic_vector(7 downto 0); -- data lines used when the host reads from a channel
signal f2hValid : std_logic; -- channel logic can drive this low to say "I don't have data ready for you"
signal f2hReady : std_logic; -- '1' means "on the next clock rising edge, put your next byte of data on f2hData"
-- ----------------------------------------------------------------------------------------------
-- Reset signal so host can delay startup
signal fx2Reset : std_logic;
begin
-- CommFPGA module
fx2Addr_out(0) <= -- So fx2Addr_out(1)='0' selects EP2OUT, fx2Addr_out(1)='1' selects EP6IN
'0' when fx2Reset = '0'
else 'Z';
comm_fpga_fx2 : entity work.comm_fpga_fx2
port map(
clk_in => fx2Clk_in,
reset_in => '0',
reset_out => fx2Reset,
-- FX2LP interface
fx2FifoSel_out => fx2Addr_out(1),
fx2Data_io => fx2Data_io,
fx2Read_out => fx2Read_out,
fx2GotData_in => fx2GotData_in,
fx2Write_out => fx2Write_out,
fx2GotRoom_in => fx2GotRoom_in,
fx2PktEnd_out => fx2PktEnd_out,
-- DVR interface -> Connects to application module
chanAddr_out => chanAddr,
h2fData_out => h2fData,
h2fValid_out => h2fValid,
h2fReady_in => h2fReady,
f2hData_in => f2hData,
f2hValid_in => f2hValid,
f2hReady_out => f2hReady
);
-- Switches & LEDs application
swled_app : entity work.swled
port map(
clk_in => fx2Clk_in,
reset_in => '0',
-- DVR interface -> Connects to comm_fpga module
chanAddr_in => chanAddr,
h2fData_in => h2fData,
h2fValid_in => h2fValid,
h2fReady_out => h2fReady,
f2hData_out => f2hData,
f2hValid_out => f2hValid,
f2hReady_in => f2hReady,
-- External interface
sseg_out => sseg_out,
anode_out => anode_out,
led_out => led_out,
sw_in => sw_in
);
end architecture;
| gpl-3.0 | 1b8959bb1bbf5a189e4e2def8aed8e85 | 0.59596 | 3.416197 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/MMX/MMX_MUL_8b.vhd | 1 | 1,630 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library ims;
--use ims.coprocessor.all;
entity MMX_MUL_8b is
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end;
architecture rtl of MMX_MUL_8b is
begin
-------------------------------------------------------------------------
-- synthesis translate_off
process
begin
wait for 1 ns;
REPORT "(IMS) MMX 8bis MUL RESSOURCE : ALLOCATION OK !";
wait;
end process;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : STD_LOGIC_VECTOR(7 downto 0);
variable rTemp2 : STD_LOGIC_VECTOR(7 downto 0);
variable rTemp3 : STD_LOGIC_VECTOR(7 downto 0);
variable rTemp4 : STD_LOGIC_VECTOR(7 downto 0);
begin
rTemp1 := STD_LOGIC_VECTOR( RESIZE(UNSIGNED(INPUT_1( 7 downto 0)) * UNSIGNED(INPUT_2( 7 downto 0)), 8) );
rTemp2 := STD_LOGIC_VECTOR( RESIZE(UNSIGNED(INPUT_1(15 downto 8)) * UNSIGNED(INPUT_2(15 downto 8)), 8) );
rTemp3 := STD_LOGIC_VECTOR( RESIZE(UNSIGNED(INPUT_1(23 downto 16)) * UNSIGNED(INPUT_2(23 downto 16)), 8) );
rTemp4 := STD_LOGIC_VECTOR( RESIZE(UNSIGNED(INPUT_1(31 downto 24)) * UNSIGNED(INPUT_2(31 downto 24)), 8) );
OUTPUT_1 <= (rTemp4 & rTemp3 & rTemp2 & rTemp1);
end process;
-------------------------------------------------------------------------
end; | gpl-3.0 | 9cc1c051281c7de6f58f0fe0962f89da | 0.531902 | 3.520518 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/MMX/MMX_MIX_8b.vhd | 1 | 2,383 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library ims;
--use ims.coprocessor.all;
entity MMX_MIX_8b is
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end;
architecture rtl of MMX_MIX_8b is
begin
-------------------------------------------------------------------------
-- synthesis translate_off
process
begin
wait for 1 ns;
REPORT "(IMS) MMX 8bis MIX RESSOURCE : ALLOCATION OK !";
wait;
end process;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : STD_LOGIC_VECTOR(7 downto 0);
variable rTemp2 : STD_LOGIC_VECTOR(7 downto 0);
variable rTemp3 : STD_LOGIC_VECTOR(7 downto 0);
variable rTemp4 : STD_LOGIC_VECTOR(7 downto 0);
begin
CASE INPUT_2(7 downto 0) is
when "00000001" => rTemp1 := INPUT_1( 7 downto 0);
when "00000010" => rTemp1 := INPUT_1(15 downto 8);
when "00000011" => rTemp1 := INPUT_1(23 downto 16);
when "00000100" => rTemp1 := INPUT_1(31 downto 24);
when others => rTemp1 := "00000000";
end case;
CASE INPUT_2(15 downto 8) is
when "00000001" => rTemp2 := INPUT_1( 7 downto 0);
when "00000010" => rTemp2 := INPUT_1(15 downto 8);
when "00000011" => rTemp2 := INPUT_1(23 downto 16);
when "00000100" => rTemp2 := INPUT_1(31 downto 24);
when others => rTemp2 := "00000000";
end case;
CASE INPUT_2(23 downto 16) is
when "00000001" => rTemp3 := INPUT_1( 7 downto 0);
when "00000010" => rTemp3 := INPUT_1(15 downto 8);
when "00000011" => rTemp3 := INPUT_1(23 downto 16);
when "00000100" => rTemp3 := INPUT_1(31 downto 24);
when others => rTemp3 := "00000000";
end case;
CASE INPUT_2(31 downto 24) is
when "00000001" => rTemp4 := INPUT_1( 7 downto 0);
when "00000010" => rTemp4 := INPUT_1(15 downto 8);
when "00000011" => rTemp4 := INPUT_1(23 downto 16);
when "00000100" => rTemp4 := INPUT_1(31 downto 24);
when others => rTemp4 := "00000000";
end case;
OUTPUT_1 <= (rTemp4 & rTemp3 & rTemp2 & rTemp1);
end process;
-------------------------------------------------------------------------
end;
| gpl-3.0 | 776c0b387c0abc6e202bdb2cfb9588b2 | 0.551406 | 3.246594 | false | false | false | false |
chibby0ne/vhdl-book | Chapter6/exercise6_3_dir/exercise6_3.vhd | 1 | 1,383 | --!
--! @file: exercise6_3.vhd
--! @brief: registered multiplexer
--! @author: Antonio Gutierrez
--! @date: 2013-10-24
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
use work.my_data_types.all;
--------------------------------------
entity reg_mux is
generic (M: integer := 5; -- number of inputs
N: integer := 8); -- number of bits per input
port (
x: in matrix(0 to M-1, N-1 downto 0);
sel: in std_logic_vector(M-1 downto 0); ;
y: out std_logic_vector(N-1 downto 0));
end entity reg_mux;
--------------------------------------
architecture circuit of reg_mux is
signal mux_out: std_logic_vector(N-1 downto 0);
signal sel_un: unsigned(M-1 downto 0);
begin
-- using sel as an index we need to use an unsigned
sel_un <= unsigned(sel);
-- assign depending on sel each one of bits in the selected input to the output
gen: for i in 0 to N-1 generate
mux_out(i) <= x(sel_un, i);
end generate gen;
proc: process (clk)
begin
if (clk'event and clk='1') then
y <= mux_out;
end if;
end process label;
-- maybe this can work as well
-- with sel_un select
-- mux_out <= x(0) when 0,
-- x(sel_un) when others;
end architecture circuit;
--------------------------------------
| gpl-3.0 | 3c0c79c0219a9d132e2d17551b4bdcbf | 0.532176 | 3.649077 | false | false | false | false |
muhd7rosli/mblite-vivado | mblite_ip/sim/core_tb.vhd | 1 | 7,261 | ----------------------------------------------------------------------------------------------
-- This file is part of mblite_ip.
--
-- mblite_ip is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- mblite_ip is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with mblite_ip. If not, see <http://www.gnu.org/licenses/>.
--
-- Input file : core_tb.vhd
-- Design name : core testbench
-- Author : Muhammad Bin Rosli
-- Company :
-- :
-- :
--
-- Description : Testbench for the processor
-- Date : 01 November 2015
--
----------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.STD_LOGIC_UNSIGNED.all;
library std;
use std.textio.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
entity core_tb is
generic
(
CFG_IMEM_WIDTH : integer := 32;
CFG_IMEM_SIZE : integer := 16;
CFG_DMEM_WIDTH : integer := 32;
CFG_DMEM_SIZE : integer := 32;
G_INTERRUPT : boolean := true;
G_USE_HW_MUL : boolean := true;
G_USE_BARREL : boolean := true;
G_DEBUG : boolean := true
);
-- Port ( );
end core_tb;
architecture arch of core_tb is
-- instruction memory interface
signal imem_dat_i : std_logic_vector(CFG_IMEM_WIDTH - 1 downto 0);
signal imem_adr_o : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
signal imem_ena_o : std_logic;
-- data memory interface
signal dmem_dat_i : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
signal dmem_ena_i : std_logic;
signal dmem_dat_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
signal dmem_adr_o : std_logic_vector(CFG_DMEM_SIZE - 1 downto 0);
signal dmem_sel_o : std_logic_vector(3 downto 0);
signal dmem_we_o : std_logic;
signal dmem_ena_o : std_logic;
signal sys_clk_i : std_logic := '0';
signal sys_int_i : std_logic := '0';
signal sys_rst_i : std_logic := '0';
signal sys_ena_i : std_logic := '1';
constant std_out_adr : std_logic_vector(CFG_DMEM_SIZE - 1 downto 0) := X"FFFFFFC0";
constant rom_size : integer := 16;
constant ram_size : integer := 16;
signal mem_enable : std_logic;
signal chr_enable : std_logic;
signal chr_read : std_logic;
signal sel_o : std_logic_vector(3 downto 0);
signal mem_dat : std_logic_vector(31 downto 0);
signal chr_dat : std_logic_vector(31 downto 0);
signal chr_cnt : integer := 0;
begin
sys_clk_i <= not sys_clk_i after 10 ns;
sys_rst_i <= '1' after 0 ps, '0' after 150 ns;
sys_int_i <= '1' after 500000 ns, '0' after 500040 ns;
dmem_ena_i <= sys_ena_i;
sel_o <= dmem_sel_o when dmem_we_o = '1' else (others => '0');
mem_enable <= not sys_rst_i and dmem_ena_o and not compare(dmem_adr_o, std_out_adr);
chr_enable <= not sys_rst_i and dmem_ena_o and compare(dmem_adr_o, std_out_adr);
dmem_dat_i <= chr_dat when chr_read = '1' else mem_dat;
-- Character device
stdio: process(sys_clk_i)
variable s : line;
variable byte : std_logic_vector(7 downto 0);
variable char : character;
begin
if rising_edge(sys_clk_i) then
if chr_enable = '1' then
if dmem_we_o = '1' then
-- WRITE STDOUT
case dmem_sel_o is
when "0001" => byte := dmem_dat_o( 7 downto 0);
when "0010" => byte := dmem_dat_o(15 downto 8);
when "0100" => byte := dmem_dat_o(23 downto 16);
when "1000" => byte := dmem_dat_o(31 downto 24);
when others => null;
end case;
char := character'val(my_conv_integer(byte));
if byte = X"0D" then
-- Ignore character 13
elsif byte = X"0A" then
-- Writeline on character 10 (newline)
writeline(output, s);
else
-- Write to buffer
write(s, char);
end if;
chr_read <= '0';
else
chr_read <= '1';
if chr_cnt = 0 then
chr_cnt <= 1;
chr_dat <= X"4C4C4C4C";
elsif chr_cnt = 1 then
chr_cnt <= 2;
chr_dat <= X"4D4D4D4D";
elsif chr_cnt = 2 then
chr_cnt <= 3;
chr_dat <= X"4E4E4E4E";
elsif chr_cnt = 3 then
chr_cnt <= 0;
chr_dat <= X"0A0A0A0A";
end if;
end if;
else
chr_read <= '0';
end if;
end if;
end process;
-- Warning: an infinite loop like while(1) {} triggers this timeout too!
-- disable this feature when a premature finish occur.
timeout: process(sys_clk_i)
begin
if now = 10 ms then
report "TIMEOUT" severity FAILURE;
end if;
-- BREAK ON EXIT (0xB8000000)
if compare(imem_dat_i, "10111000000000000000000000000000") = '1' then
-- Make sure the simulator finishes when an error is encountered.
-- For modelsim: see menu Simulate -> Runtime options -> Assertions
report "FINISHED" severity FAILURE;
end if;
end process;
imem : sram generic map
(
WIDTH => CFG_IMEM_WIDTH,
SIZE => rom_size - 2
)
port map
(
dat_o => imem_dat_i,
dat_i => "00000000000000000000000000000000",
adr_i => imem_adr_o(rom_size - 1 downto 2),
wre_i => '0',
ena_i => imem_ena_o,
clk_i => sys_clk_i
);
dmem : sram_4en generic map
(
WIDTH => CFG_DMEM_WIDTH,
SIZE => ram_size - 2
)
port map
(
dat_o => mem_dat,
dat_i => dmem_dat_o,
adr_i => dmem_adr_o(ram_size - 1 downto 2),
wre_i => sel_o,
ena_i => mem_enable,
clk_i => sys_clk_i
);
core0 : core port map
(
imem_dat_i => imem_dat_i,
imem_adr_o => imem_adr_o,
imem_ena_o => imem_ena_o,
dmem_dat_i => dmem_dat_i,
dmem_ena_i => dmem_ena_i,
dmem_dat_o => dmem_dat_o,
dmem_adr_o => dmem_adr_o,
dmem_sel_o => dmem_sel_o,
dmem_we_o => dmem_we_o,
dmem_ena_o => dmem_ena_o,
int_i => sys_int_i,
rst_i => sys_rst_i,
clk_i => sys_clk_i
);
end arch; | lgpl-3.0 | 06462ec851b2f13491020bd11e1b6511 | 0.505991 | 3.674595 | false | false | false | false |
VLSI-EDA/UVVM_All | uvvm_util/src/license_pkg.vhd | 1 | 5,311 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.types_pkg.all;
use work.string_methods_pkg.all;
use work.adaptations_pkg.all;
package license_pkg is
impure function show_license(
constant dummy : in t_void
) return boolean;
impure function show_uvvm_utility_library_info(
constant dummy : in t_void
) return boolean;
impure function show_uvvm_utility_library_release_info(
constant dummy : in t_void
) return boolean;
end package license_pkg;
package body license_pkg is
impure function show_license(
constant dummy : in t_void
) return boolean is
constant C_SEPARATOR : string :=
"*****************************************************************************************************";
constant C_LICENSE_STR : string :=
LF & LF & LF &
C_SEPARATOR & LF &
" This is a *** LICENSED PRODUCT *** as given in the LICENSE.TXT in the root directory." & LF &
C_SEPARATOR & LF & LF;
begin
report (C_LICENSE_STR);
return true;
end;
impure function show_uvvm_utility_library_info(
constant dummy : in t_void
) return boolean is
constant C_SEPARATOR : string :=
"=====================================================================================================";
constant C_LICENSE_STR : string :=
LF & LF &
C_SEPARATOR & LF &
C_SEPARATOR & LF &
"This info section may be turned off via C_SHOW_UVVM_UTILITY_LIBRARY_INFO in adaptations_pkg.vhd" & LF & LF &
"Important Simulator setup: " & LF &
"- Set simulator to break on severity 'FAILURE' " & LF &
"- Set simulator transcript to a monospace font (e.g. Courier new)" & LF & LF &
"UVVM Utility Library setup:" & LF &
"- It is recommended to go through the two powerpoint presentations provided with the download" & LF &
"- There is a Quick-Reference in the doc-directory" & LF &
"- In order to change layout or behaviour - please check the src*/adaptations_pkg.vhd" & LF &
" This is intended for personal or company customization" & LF & LF &
"License conditions are given in LICENSE.TXT" & LF &
C_SEPARATOR & LF &
C_SEPARATOR & LF & LF;
begin
if C_SHOW_UVVM_UTILITY_LIBRARY_INFO then
report (C_LICENSE_STR);
end if;
return true;
end;
impure function show_uvvm_utility_library_release_info(
constant dummy : in t_void
) return boolean is
constant C_IMPORTANT_UPDATE_FOR_THIS_VERSION : boolean := false; -- ***** NOTE: Evaluate a change here
constant C_SEPARATOR : string :=
"=====================================================================================================";
constant C_LICENSE_STR : string :=
LF & LF &
C_SEPARATOR & LF &
C_SEPARATOR & LF &
"This release info may be turned off via C_SHOW_UVVM_UTILITY_LIBRARY_INFO in adaptations_pkg.vhd" & LF & LF &
"Important Issues for this version update: " & LF &
"- First release" & LF & LF & LF &
C_SEPARATOR & LF &
C_SEPARATOR & LF & LF;
begin
if C_SHOW_UVVM_UTILITY_LIBRARY_INFO and C_IMPORTANT_UPDATE_FOR_THIS_VERSION then
report (C_LICENSE_STR);
end if;
return true;
end;
end package body license_pkg;
| mit | e4476aa85a5b2f244ba5cba8b9cf6674 | 0.472227 | 5.196673 | false | false | false | false |
chibby0ne/vhdl-book | Chapter4/exercise7_dir/exercise7/texercise7.vhd | 1 | 2,120 | ------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
------------------------------
entity test_circuit is
--generic declarations
end entity;
------------------------------
architecture only of test_circuit is
--DUT declaration--
component ent is
port (
reset: in std_logic ;
clk: in std_logic ;
v: in std_logic_vector(3 downto 0) ;
x: in std_logic_vector(3 downto 0) ;
y: in std_logic_vector(7 downto 0) ;
z: in std_logic_vector(7 downto 0) ;
out1: out std_logic ;
out2: out std_logic ;
out3: out std_logic ;
out4: out std_logic );
end component;
-- signal declaration --
signal reset_tb: std_logic := '0' ;
signal clk_tb: std_logic := '0' ;
signal v_tb: std_logic_vector(3 downto 0) := (others => '0');
signal x_tb: std_logic_vector(3 downto 0):= (others => '0');
signal y_tb: std_logic_vector(7 downto 0):= (others => '0');
signal z_tb: std_logic_vector(7 downto 0):= (others => '0');
signal out1_tb: std_logic := '0' ;
signal out2_tb: std_logic := '0';
signal out3_tb: std_logic := '0';
signal out4_tb: std_logic := '0';
begin
-- DUT instantiation
dut : ent
port map (
reset => reset_tb,
clk => clk_tb,
v => v_tb,
x => x_tb,
y => y_tb,
z => z_tb,
out1 => out1_tb,
out2 => out2_tb,
out3 => out3_tb,
out4 => out4_tb
);
-- clock
clock : process
begin
wait for 10 ns;
clk_tb <= not clk_tb;
end process;
-- stimuli generation
-- reset : process
-- begin
-- wait for 4 ns;
-- reset_tb <= '1';
-- wait for 4 ns;
-- reset_tb <= '0';
-- end process;
stimuli : process
begin
wait for 6 ns;
v_tb <= "0011";
wait for 10 ns;
x_tb <= "1100";
wait for 10 ns;
y_tb <= "01000000";
wait for 10 ns;
z_tb <= (others => '1');
end process;
end architecture;
| gpl-3.0 | 99b0f4418a908543f89d111f594cc235 | 0.483962 | 3.452769 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/custom/tuto_plasma/coproc_2.vhd | 2 | 3,613 | ---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
use work.cam_pkg.all;
entity coproc_2 is
port(
clock : in std_logic;
reset : in std_logic;
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_1_valid : in std_logic;
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of coproc_2 is
signal min_reg : unsigned(7 downto 0);
signal beta_reg : unsigned(15 downto 0);
signal beta_tmp : unsigned(15 downto 0);
signal min_tmp, max_tmp : unsigned(7 downto 0);
signal store_min_beta : std_logic;
signal a,b : unsigned(15 downto 0);
signal OUTPUT_1_tmp : std_logic_vector(31 downto 0);
begin
-------------------------------------------------------------------------
scaling_computation : process (INPUT_1, min_reg, beta_reg)
variable mini : UNSIGNED(7 downto 0);
variable data1, data2, data3, data4 : UNSIGNED(7 downto 0);
variable diff1, diff2, diff3, diff4 : UNSIGNED(7 downto 0);
variable mult1, mult2, mult3, mult4 : UNSIGNED(23 downto 0);
begin
-- data1 := UNSIGNED( INPUT_1(7 downto 0) );
-- data2 := UNSIGNED( INPUT_1(15 downto 8) );
-- data3 := UNSIGNED( INPUT_1(23 downto 16) );
-- data4 := UNSIGNED( INPUT_1(31 downto 24) );
-- diff1 := data1 - min_reg; -- 8
-- diff2 := data2 - min_reg; -- 8
-- diff3 := data3 - min_reg; -- 8
-- diff4 := data4 - min_reg; -- 8
-- mult1 := diff1 * beta_reg; -- 24
-- mult2 := diff2 * beta_reg; -- 24
-- mult3 := diff3 * beta_reg; -- 24
-- mult4 := diff4 * beta_reg; -- 24
-- OUTPUT_1_tmp(7 downto 0) <= std_logic_vector(mult1(15 downto 8));
-- OUTPUT_1_tmp(15 downto 8) <= std_logic_vector(mult2(15 downto 8));
-- OUTPUT_1_tmp(23 downto 16) <= std_logic_vector(mult3(15 downto 8));
-- OUTPUT_1_tmp(31 downto 24) <= std_logic_vector(mult4(15 downto 8));
end process;
-------------------------------------------------------------------------
max_tmp <= UNSIGNED(INPUT_1(7 downto 0));
min_tmp <= UNSIGNED(INPUT_1(15 downto 8));
b <= "00000000"&(max_tmp-min_tmp);
a <= TO_UNSIGNED( 255, 8)&"00000000";
--beta_tmp <= divide(TO_UNSIGNED( 255, 8), (max_tmp-min_tmp));
beta_tmp <= divide(a,b); --(8,8)
--beta_tmp <= "00000000"&max_tmp-min_tmp;
-------------------------------------------------------------------------
process (clock, reset)
begin
IF clock'event AND clock = '1' THEN
IF reset = '1' THEN
store_min_beta <= '1';
min_reg <= (others => '0');
beta_reg <= (others => '0');
OUTPUT_1 <= (others => '0');
ELSE
IF (INPUT_1_valid = '1' and store_min_beta ='1') THEN
store_min_beta <= '0';
min_reg <= UNSIGNED(INPUT_1(15 downto 8));
beta_reg <= beta_tmp;
OUTPUT_1 <= INPUT_1;
ELSIF (INPUT_1_valid = '1' and store_min_beta = '0') THEN
store_min_beta <= '0';
min_reg <= min_reg;
beta_reg <= beta_reg;
OUTPUT_1 <= OUTPUT_1_tmp;
--OUTPUT_1 <= "000000000000000000000000"&std_logic_vector(min_reg);
END IF;
END IF;
END IF;
end process;
-------------------------------------------------------------------------
end; --architecture logic
| gpl-3.0 | 19786b9a75e79cbcd96156c7a6a8c940 | 0.54553 | 3.122731 | false | false | false | false |
VLSI-EDA/UVVM_All | bitvis_vip_sbi/src/sbi_bfm_pkg.vhd | 1 | 38,355 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
--
-- Important : For systems not using 'ready' a dummy signal must be declared and set to '1'
-- For systems not using 'terminate' a dummy signal must be declared and set to '1' if using sbi_poll_until()
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
--=================================================================================================
package sbi_bfm_pkg is
--===============================================================================================
-- Types and constants for SBI BFMs
--===============================================================================================
constant C_SCOPE : string := "SBI BFM";
type t_sbi_if is record
cs : std_logic; -- to dut
addr : unsigned; -- to dut
rena : std_logic; -- to dut
wena : std_logic; -- to dut
wdata : std_logic_vector; -- to dut
ready : std_logic; -- from dut
rdata : std_logic_vector; -- from dut
end record;
-- Configuration record to be assigned in the test harness.
type t_sbi_bfm_config is
record
max_wait_cycles : integer; -- The maximum number of clock cycles to wait for the DUT ready signal before reporting a timeout alert.
max_wait_cycles_severity : t_alert_level; -- The above timeout will have this severity
use_fixed_wait_cycles_read : boolean; -- When true, wait 'fixed_wait_cycles_read' after asserting rena, before sampling rdata
fixed_wait_cycles_read : natural; -- Number of clock cycles to wait after asserting rd signal, before sampling rdata from DUT.
clock_period : time; -- Period of the clock signal
clock_period_margin : time; -- Input clock period margin to specified clock_period.
-- Checking low period of input clock if BFM is called while CLK is high.
-- Checking clock_period of input clock if BFM is called while CLK is low.
clock_margin_severity : t_alert_level; -- The above margin will have this severity
setup_time : time; -- Generated signals setup time, set to clock_period/4
hold_time : time; -- Generated signals hold time, set to clock_period/4
id_for_bfm : t_msg_id; -- The message ID used as a general message ID in the SBI BFM
id_for_bfm_wait : t_msg_id; -- The message ID used for logging waits in the SBI BFM
id_for_bfm_poll : t_msg_id; -- The message ID used for logging polling in the SBI BFM
use_ready_signal : boolean; -- Whether or not to use the interface �ready� signal
end record;
constant C_SBI_BFM_CONFIG_DEFAULT : t_sbi_bfm_config := (
max_wait_cycles => 10,
max_wait_cycles_severity => failure,
use_fixed_wait_cycles_read => false,
fixed_wait_cycles_read => 0,
clock_period => 10 ns,
clock_period_margin => 0 ns,
clock_margin_severity => TB_ERROR,
setup_time => 2.5 ns,
hold_time => 2.5 ns,
id_for_bfm => ID_BFM,
id_for_bfm_wait => ID_BFM_WAIT,
id_for_bfm_poll => ID_BFM_POLL,
use_ready_signal => true
);
--===============================================================================================
-- BFM procedures
--===============================================================================================
------------------------------------------
-- init_sbi_if_signals
------------------------------------------
-- - This function returns an SBI interface with initialized signals.
-- - All SBI input signals are initialized to 0
-- - All SBI output signals are initialized to Z
function init_sbi_if_signals(
addr_width : natural;
data_width : natural
) return t_sbi_if;
------------------------------------------
-- sbi_write
------------------------------------------
-- - This procedure writes data to the SBI DUT
-- - The SBI interface in this procedure is given as individual signals
procedure sbi_write (
constant addr_value : in unsigned;
constant data_value : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal cs : inout std_logic;
signal addr : inout unsigned;
signal rena : inout std_logic;
signal wena : inout std_logic;
signal ready : in std_logic;
signal wdata : inout std_logic_vector;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- sbi_write
------------------------------------------
-- - This procedure writes data 'data_value' to the SBI DUT address 'addr_value'
-- - The SBI interface in this procedure is given as a t_sbi_if signal record
procedure sbi_write (
constant addr_value : in unsigned;
constant data_value : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal sbi_if : inout t_sbi_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- sbi_read
------------------------------------------
-- - This procedure reads data from the SBI DUT address 'addr_value' and
-- returns the read data in the output 'data_value'
-- - The SBI interface in this procedure is given as individual signals
procedure sbi_read (
constant addr_value : in unsigned;
variable data_value : out std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal cs : inout std_logic;
signal addr : inout unsigned;
signal rena : inout std_logic;
signal wena : inout std_logic;
signal ready : in std_logic;
signal rdata : in std_logic_vector;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like sbi_check
);
------------------------------------------
-- sbi_read
------------------------------------------
-- - This procedure reads data from the SBI DUT address 'addr_value' and returns
-- the read data in the output 'data_value'
-- - The SBI interface in this procedure is given as a t_sbi_if signal record
procedure sbi_read (
constant addr_value : in unsigned;
variable data_value : out std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal sbi_if : inout t_sbi_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like sbi_check
);
------------------------------------------
-- sbi_check
------------------------------------------
-- - This procedure reads data from the SBI DUT address 'addr_value' and
-- compares the read data to the expected data in 'data_exp'.
-- - If the read data is inconsistent with the expected data, an alert with
-- severity 'alert_level' is triggered.
-- - The SBI interface in this procedure is given as individual signals
procedure sbi_check (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal cs : inout std_logic;
signal addr : inout unsigned;
signal rena : inout std_logic;
signal wena : inout std_logic;
signal ready : in std_logic;
signal rdata : in std_logic_vector;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- sbi_check
------------------------------------------
-- - This procedure reads data from the SBI DUT address 'addr_value' and
-- compares the read data to the expected data in 'data_exp'.
-- - If the read data is inconsistent with the expected data, an alert with
-- severity 'alert_level' is triggered.
-- - The SBI interface in this procedure is given as a t_sbi_if signal record
procedure sbi_check (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal sbi_if : inout t_sbi_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- sbi_poll_until
------------------------------------------
-- - This procedure reads data from the SBI DUT address 'addr_value' and
-- compares the read data to the expected data in 'data_exp'.
-- - If the read data is inconsistent with the expected data, a new read
-- will be performed, and the new read data will be compared with the
-- 'data_exp'. This process will continue until one of the following
-- conditions are met:
-- a) The read data is equal to the expected data
-- b) The number of reads equal 'max_polls'
-- c) The time spent polling is equal to the 'timeout'
-- - If 'timeout' is set to 0, it will be interpreted as no timeout
-- - If 'max_polls' is set to 0, it will be interpreted as no limitation on number of polls
-- - The SBI interface in this procedure is given as individual signals
procedure sbi_poll_until (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant max_polls : in integer := 1;
constant timeout : in time := 0 ns;
constant msg : in string;
signal clk : in std_logic;
signal cs : inout std_logic;
signal addr : inout unsigned;
signal rena : inout std_logic;
signal wena : inout std_logic;
signal ready : in std_logic;
signal rdata : in std_logic_vector;
signal terminate_loop : in std_logic;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- sbi_poll_until
------------------------------------------
-- - This procedure reads data from the SBI DUT address 'addr_value' and
-- compares the read data to the expected data in 'data_exp'.
-- - If the read data is inconsistent with the expected data, a new read
-- will be performed, and the new read data will be compared with the
-- 'data_exp'. This process will continue until one of the following
-- conditions are met:
-- a) The read data is equal to the expected data
-- b) The number of reads equal 'max_polls'
-- c) The time spent polling is equal to the 'timeout'
-- - If 'timeout' is set to 0, it will be interpreted as no timeout
-- - If 'max_polls' is set to 0, it will be interpreted as no limitation on number of polls
-- - The SBI interface in this procedure is given as a t_sbi_if signal record
procedure sbi_poll_until (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant max_polls : in integer := 1;
constant timeout : in time := 0 ns;
constant msg : in string;
signal clk : in std_logic;
signal sbi_if : inout t_sbi_if;
signal terminate_loop : in std_logic;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT
);
end package sbi_bfm_pkg;
--=================================================================================================
--=================================================================================================
package body sbi_bfm_pkg is
---------------------------------------------------------------------------------
-- initialize sbi to dut signals
---------------------------------------------------------------------------------
function init_sbi_if_signals(
addr_width : natural;
data_width : natural
) return t_sbi_if is
variable result : t_sbi_if(addr(addr_width - 1 downto 0),
wdata(data_width - 1 downto 0),
rdata(data_width - 1 downto 0));
begin
result.cs := '0';
result.rena := '0';
result.wena := '0';
result.addr := (result.addr'range => '0');
result.wdata := (result.wdata'range => '0');
result.ready := 'Z';
result.rdata := (result.rdata'range => 'Z');
return result;
end function;
---------------------------------------------------------------------------------
-- write
---------------------------------------------------------------------------------
procedure sbi_write (
constant addr_value : in unsigned;
constant data_value : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal cs : inout std_logic;
signal addr : inout unsigned;
signal rena : inout std_logic;
signal wena : inout std_logic;
signal ready : in std_logic;
signal wdata : inout std_logic_vector;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT
) is
constant proc_name : string := "sbi_write";
constant proc_call : string := "sbi_write(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) &
", " & to_string(data_value, HEX, AS_IS, INCL_RADIX) & ")";
-- Normalise to the DUT addr/data widths
variable v_normalised_addr : unsigned(addr'length-1 downto 0) :=
normalize_and_check(addr_value, addr, ALLOW_WIDER_NARROWER, "addr_value", "sbi_core_in.addr", msg);
variable v_normalised_data : std_logic_vector(wdata'length-1 downto 0) :=
normalize_and_check(data_value, wdata, ALLOW_NARROWER, "data_value", "sbi_core_in.wdata", msg);
variable v_clk_cycles_waited : natural := 0;
variable v_min_time : time := -1 ns; -- min allowed clk low period
variable v_max_time : time := -1 ns; -- max allowed clk low period
variable v_start_time : time := -1 ns; -- time of previoud clock edge
variable v_clk_was_high : boolean := false; -- clk high/low status on BFM call
begin
-- setup_time and hold_time checking
check_value(config.setup_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that setup_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(config.hold_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that hold_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(config.setup_time > 0 ns, TB_FAILURE, "Sanity check: Check that setup_time is more than 0 ns.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(config.hold_time > 0 ns, TB_FAILURE, "Sanity check: Check that hold_time is more than 0 ns.", scope, ID_NEVER, msg_id_panel, proc_call);
-- check if enough room for setup_time in low period
if (clk = '0') and (config.setup_time > (config.clock_period/2 - clk'last_event))then
await_value(clk, '1', 0 ns, config.clock_period/2, TB_FAILURE, proc_name & ": timeout waiting for clk low period for setup_time.");
end if;
-- check if clk was high when BFM was called
if clk = '1' then
v_clk_was_high := true;
end if;
-- get time stamp of previous clk edge
v_start_time := now - clk'last_event;
-- Wait setup_time specified in config record
wait_until_given_time_before_rising_edge(clk, config.setup_time, config.clock_period);
cs <= '1';
wena <= '1';
rena <= '0';
addr <= v_normalised_addr;
wdata <= v_normalised_data;
if config.use_ready_signal then
check_value(ready = '1' or ready = '0', failure, "Verifying that ready signal is set to either '1' or '0' when in use", scope, ID_NEVER, msg_id_panel);
end if;
wait until rising_edge(clk);
-- check if clk meet requirements
if v_clk_was_high then -- rising_edge to rising_edge
v_min_time := v_start_time + config.clock_period - config.clock_period_margin;
v_max_time := v_start_time + config.clock_period + config.clock_period_margin;
check_value_in_range(now, v_min_time, v_max_time, config.clock_margin_severity, proc_name & ": checking clk period is within requirement (rising_edge to rising_edge).", scope, ID_NEVER, msg_id_panel);
else -- falling_edge to rising_edge
v_min_time := v_start_time + (config.clock_period/2) - config.clock_period_margin;
v_max_time := v_start_time + (config.clock_period/2) + config.clock_period_margin;
check_value_in_range(now, v_min_time, v_max_time, config.clock_margin_severity, proc_name & ": checking clk low period is within requirement (falling_edge to rising_edge).", scope, ID_NEVER, msg_id_panel);
end if;
while (config.use_ready_signal and ready = '0') loop
if v_clk_cycles_waited = 0 then
log(config.id_for_bfm_wait, proc_call & " waiting for response (sbi ready=0) " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
wait until rising_edge(clk);
v_clk_cycles_waited := v_clk_cycles_waited + 1;
check_value(v_clk_cycles_waited <= config.max_wait_cycles, config.max_wait_cycles_severity,
": Timeout while waiting for sbi ready", scope, ID_NEVER, msg_id_panel, proc_call);
end loop;
-- Wait hold time specified in config record
wait_until_given_time_after_rising_edge(clk, config.hold_time);
cs <= '0';
wena <= '0';
log(config.id_for_bfm, proc_call & " completed. " & add_msg_delimiter(msg), scope, msg_id_panel);
end procedure;
procedure sbi_write (
constant addr_value : in unsigned;
constant data_value : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal sbi_if : inout t_sbi_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT
) is
begin
sbi_write(addr_value, data_value, msg, clk, sbi_if.cs, sbi_if.addr,
sbi_if.rena, sbi_if.wena, sbi_if.ready, sbi_if.wdata,
scope, msg_id_panel, config);
end procedure;
---------------------------------------------------------------------------------
-- sbi_read
---------------------------------------------------------------------------------
procedure sbi_read (
constant addr_value : in unsigned;
variable data_value : out std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal cs : inout std_logic;
signal addr : inout unsigned;
signal rena : inout std_logic;
signal wena : inout std_logic;
signal ready : in std_logic;
signal rdata : in std_logic_vector;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like sbi_check
) is
-- local_proc_* used if called from sequencer or VVC
constant local_proc_name : string := "sbi_read";
constant local_proc_call : string := local_proc_name & "(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) & ")";
-- Normalize to the DUT addr/data widths
variable v_normalised_addr : unsigned(addr'length-1 downto 0) :=
normalize_and_check(addr_value, addr, ALLOW_WIDER_NARROWER, "addr_value", "sbi_core_in.addr", msg);
variable v_data_value : std_logic_vector(data_value'range);
variable v_clk_cycles_waited : natural := 0;
variable v_proc_call : line;
variable v_min_time : time := -1 ns; -- min allowed clk low period
variable v_max_time : time := -1 ns; -- max allowed clk low period
variable v_start_time : time := -1 ns; -- time of previoud clock edge
variable v_clk_was_high : boolean := false; -- clk high/low status on BFM call
begin
-- setup_time and hold_time checking
check_value(config.setup_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that setup_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, local_proc_call);
check_value(config.hold_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that hold_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, local_proc_call);
check_value(config.setup_time > 0 ns, TB_FAILURE, "Sanity check: Check that setup_time is more than 0 ns.", scope, ID_NEVER, msg_id_panel, local_proc_call);
check_value(config.hold_time > 0 ns, TB_FAILURE, "Sanity check: Check that hold_time is more than 0 ns.", scope, ID_NEVER, msg_id_panel, local_proc_call);
if ext_proc_call = "" then
-- called directly from sequencer/VVC, show 'sbi_read...' in log
write(v_proc_call, local_proc_call);
else
-- called from other BFM procedure like sbi_check, log 'sbi_check(..) while executing sbi_read..'
write(v_proc_call, ext_proc_call & " while executing " & local_proc_name);
end if;
-- check if enough room for setup_time in low period
if (clk = '0') and (config.setup_time > (config.clock_period/2 - clk'last_event))then
await_value(clk, '1', 0 ns, config.clock_period/2, TB_FAILURE, local_proc_name & ": timeout waiting for clk low period for setup_time.");
end if;
-- check if clk was high when BFM was called
if clk = '1' then
v_clk_was_high := true;
end if;
-- get time stamp of previous clk edge
v_start_time := now - clk'last_event;
-- Wait setup_time specified in config record
wait_until_given_time_before_rising_edge(clk, config.setup_time, config.clock_period);
cs <= '1';
wena <= '0';
rena <= '1';
addr <= v_normalised_addr;
if config.use_ready_signal then
check_value(ready = '1' or ready = '0', failure, "Verifying that ready signal is set to either '1' or '0' when in use", scope, ID_NEVER, msg_id_panel);
end if;
wait until rising_edge(clk);
-- check if clk meet requirements
if v_clk_was_high then -- rising_edge to rising_edge
v_min_time := v_start_time + config.clock_period - config.clock_period_margin;
v_max_time := v_start_time + config.clock_period + config.clock_period_margin;
check_value_in_range(now, v_min_time, v_max_time, config.clock_margin_severity, local_proc_name & ": checking clk period is within requirement (rising_edge to rising_edge).", scope, ID_NEVER, msg_id_panel);
else -- falling_edge to rising_edge
v_min_time := v_start_time + (config.clock_period/2) - config.clock_period_margin;
v_max_time := v_start_time + (config.clock_period/2) + config.clock_period_margin;
check_value_in_range(now, v_min_time, v_max_time, config.clock_margin_severity, local_proc_name & ": checking clk low period is within requirement (falling_edge to rising_edge).", scope, ID_NEVER, msg_id_panel);
end if;
if config.use_fixed_wait_cycles_read then
-- Wait for a fixed number of clk cycles
for i in 1 to config.fixed_wait_cycles_read loop
v_clk_cycles_waited := v_clk_cycles_waited + 1;
wait until rising_edge(clk);
end loop;
else
-- If configured, wait for ready = '1'
while (config.use_ready_signal and ready = '0') loop
if v_clk_cycles_waited = 0 then
log(config.id_for_bfm_wait, v_proc_call.all & " waiting for response (sbi ready=0) " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
wait until rising_edge(clk);
v_clk_cycles_waited := v_clk_cycles_waited + 1;
check_value(v_clk_cycles_waited <= config.max_wait_cycles, config.max_wait_cycles_severity,
": Timeout while waiting for sbi ready", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
end loop;
end if;
v_data_value := rdata;
data_value := v_data_value;
-- Wait hold_time specified in config record
wait_until_given_time_after_rising_edge(clk, config.hold_time);
cs <= '0';
rena <= '0';
if ext_proc_call = "" then -- proc_name = "sbi_read"
log(config.id_for_bfm, v_proc_call.all & "=> " & to_string(v_data_value, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
-- Log will be handled by calling procedure (e.g. sbi_check)
end if;
end procedure;
procedure sbi_read (
constant addr_value : in unsigned;
variable data_value : out std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal sbi_if : inout t_sbi_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like sbi_check
) is
begin
sbi_read(addr_value, data_value, msg, clk, sbi_if.cs, sbi_if.addr,
sbi_if.rena, sbi_if.wena, sbi_if.ready, sbi_if.rdata,
scope, msg_id_panel, config, ext_proc_call);
end procedure;
---------------------------------------------------------------------------------
-- sbi_check
---------------------------------------------------------------------------------
-- Perform a read operation, then compare the read value to the POLL_UNTILed value.
procedure sbi_check (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal cs : inout std_logic;
signal addr : inout unsigned;
signal rena : inout std_logic;
signal wena : inout std_logic;
signal ready : in std_logic;
signal rdata : in std_logic_vector;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT
) is
constant proc_name : string := "sbi_check";
constant proc_call : string := "sbi_check(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) &
", " & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & ")";
-- Normalize to the DUT addr/data widths
variable v_normalised_addr : unsigned(addr'length-1 downto 0) :=
normalize_and_check(addr_value, addr, ALLOW_WIDER_NARROWER, "addr_value", "sbi_core_in.addr", msg);
-- Helper variables
variable v_data_value : std_logic_vector(rdata'length - 1 downto 0);
variable v_check_ok : boolean;
variable v_clk_cycles_waited : natural := 0;
begin
sbi_read(addr_value, v_data_value, msg, clk, cs, addr, rena, wena, ready, rdata, scope, msg_id_panel, config, proc_call);
-- Compare values, but ignore any leading zero's if widths are different.
-- Use ID_NEVER so that check_value method does not log when check is OK,
-- log it here instead.
v_check_ok := check_value(v_data_value, data_exp, alert_level, msg, scope, HEX_BIN_IF_INVALID, SKIP_LEADING_0, ID_NEVER, msg_id_panel, proc_call);
if v_check_ok then
log(config.id_for_bfm, proc_call & "=> OK, read data = " & to_string(v_data_value, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end procedure;
procedure sbi_check (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal sbi_if : inout t_sbi_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT
) is
begin
sbi_check(addr_value, data_exp, msg, clk, sbi_if.cs, sbi_if.addr,
sbi_if.rena, sbi_if.wena, sbi_if.ready, sbi_if.rdata,
alert_level, scope, msg_id_panel, config);
end procedure;
---------------------------------------------------------------------------------
-- sbi_poll_until
---------------------------------------------------------------------------------
-- Perform a read operation, then compare the read value to the POLL_UNTILed value.
-- The checking is repeated until timeout or N occurrences (reads) without POLL_UNTILed data.
procedure sbi_poll_until (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant max_polls : in integer := 1;
constant timeout : in time := 0 ns;
constant msg : in string;
signal clk : in std_logic;
signal cs : inout std_logic;
signal addr : inout unsigned;
signal rena : inout std_logic;
signal wena : inout std_logic;
signal ready : in std_logic;
signal rdata : in std_logic_vector;
signal terminate_loop : in std_logic;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT
) is
constant proc_name : string := "sbi_poll_until";
constant proc_call : string := proc_name & "(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) &
", " & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & ", " & to_string(max_polls) & ", " & to_string(timeout, ns) & ")";
constant start_time : time := now;
-- Normalise to the DUT addr/data widths
variable v_normalised_addr : unsigned(addr'length-1 downto 0) :=
normalize_and_check(addr_value, addr, ALLOW_WIDER_NARROWER, "addr_value", "sbi_core_in.addr", msg);
-- Helper variables
variable v_data_value : std_logic_vector(rdata'length - 1 downto 0);
variable v_check_ok : boolean;
variable v_timeout_ok : boolean;
variable v_num_of_occurrences_ok : boolean;
variable v_num_of_occurrences : integer := 0;
variable v_clk_cycles_waited : natural := 0;
variable v_config : t_sbi_bfm_config := config;
begin
-- Check for timeout = 0 and max_polls = 0. This combination can result in an infinite loop if the POLL_UNTILed data does not appear.
if max_polls = 0 and timeout = 0 ns then
alert(TB_WARNING, proc_name & " called with timeout=0 and max_polls=0. This can result in an infinite loop. " & add_msg_delimiter(msg), scope);
end if;
-- Initial status of the checks
v_check_ok := false;
v_timeout_ok := true;
v_num_of_occurrences_ok := true;
v_config.id_for_bfm := ID_BFM_POLL;
while not v_check_ok and v_timeout_ok and v_num_of_occurrences_ok and (terminate_loop = '0') loop
-- Read data on SBI register
sbi_read(v_normalised_addr, v_data_value, "As a part of " & proc_call & ". " & add_msg_delimiter(msg), clk, cs, addr, rena, wena, ready, rdata, scope, msg_id_panel, v_config,
return_string1_if_true_otherwise_string2("", proc_call, is_log_msg_enabled(ID_BFM_POLL, msg_id_panel))); -- ID_BFM_POLL will allow the logging inside sbi_read to be executed
-- Evaluate data
v_check_ok := matching_values(v_data_value, data_exp);
-- Evaluate number of occurrences, if limited by user
v_num_of_occurrences := v_num_of_occurrences + 1;
if max_polls > 0 then
v_num_of_occurrences_ok := v_num_of_occurrences < max_polls;
end if;
-- Evaluate timeout, if specified by user
if timeout = 0 ns then
v_timeout_ok := true;
else
v_timeout_ok := (now - start_time) < timeout;
end if;
end loop;
if v_check_ok then
log(config.id_for_bfm, proc_call & "=> OK, read data = " & to_string(v_data_value, HEX, SKIP_LEADING_0, INCL_RADIX) & " after " & to_string(v_num_of_occurrences) & " occurrences and " & to_string((now - start_time), ns) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
elsif not v_timeout_ok then
alert(alert_level, proc_call & "=> Failed due to timeout. Did not get POLL_UNTILed value " & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & " before time " & to_string(timeout, ns) & ". " & add_msg_delimiter(msg), scope);
elsif terminate_loop = '1' then
log(ID_TERMINATE_CMD, proc_call & " Terminated from outside this BFM. " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, proc_call & "=> Failed. POLL_UNTILed value " & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & " did not appear within " & to_string(max_polls) & " occurrences. " & add_msg_delimiter(msg), scope);
end if;
end procedure;
procedure sbi_poll_until (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant max_polls : in integer := 1;
constant timeout : in time := 0 ns;
constant msg : in string;
signal clk : in std_logic;
signal sbi_if : inout t_sbi_if;
signal terminate_loop : in std_logic;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT
) is
begin
sbi_poll_until(addr_value, data_exp, max_polls, timeout, msg, clk, sbi_if.cs, sbi_if.addr,
sbi_if.rena, sbi_if.wena, sbi_if.ready, sbi_if.rdata,
terminate_loop, alert_level, scope, msg_id_panel, config);
end procedure;
end package body sbi_bfm_pkg;
| mit | 8e11a1a99e574b2bcb679b92a852d3c1 | 0.562697 | 3.857861 | false | true | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/video/LWT_FIR1.vhd | 1 | 7,231 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:38:59 01/04/2010
-- Design Name:
-- Module Name: FiltreFIR_9taps - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
ENTITY LWT_FIR1 is
PORT (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
start : in STD_LOGIC;
flush : in std_logic;
holdn : in std_ulogic;
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
ready : out std_logic;
nready : out std_logic;
icc : out std_logic_vector(3 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end LWT_FIR1;
architecture Behavioral of LWT_FIR1 is
CONSTANT N : INTEGER := 8;
CONSTANT C : INTEGER := 12;
SIGNAL memXn : SIGNED(N-1 downto 0);
SIGNAL memX1 : SIGNED(N-1 downto 0);
SIGNAL memX2 : SIGNED(N-1 downto 0);
SIGNAL memX3 : SIGNED(N-1 downto 0);
SIGNAL memX4 : SIGNED(N-1 downto 0);
SIGNAL memX5 : SIGNED(N-1 downto 0);
SIGNAL memX6 : SIGNED(N-1 downto 0);
SIGNAL memX7 : SIGNED(N-1 downto 0);
SIGNAL memX8 : SIGNED(N-1 downto 0);
SIGNAL tm_1 : SIGNED(N+C-1 downto 0);
SIGNAL tm_2 : SIGNED(N+C-1 downto 0);
SIGNAL tm_3 : SIGNED(N+C-1 downto 0);
SIGNAL tm_4 : SIGNED(N+C-1 downto 0);
SIGNAL tm_5 : SIGNED(N+C-1 downto 0);
SIGNAL tm_6 : SIGNED(N+C-1 downto 0);
SIGNAL tm_7 : SIGNED(N+C-1 downto 0);
SIGNAL tm_8 : SIGNED(N+C-1 downto 0);
SIGNAL tm_9 : SIGNED(N+C-1 downto 0);
SIGNAL t2_1 : SIGNED(N+C-1 downto 0);
SIGNAL t2_2 : SIGNED(N+C-1 downto 0);
SIGNAL t2_3 : SIGNED(N+C-1 downto 0);
SIGNAL t2_4 : SIGNED(N+C-1 downto 0);
SIGNAL t2_5 : SIGNED(N+C-1 downto 0);
SIGNAL t3_1 : SIGNED(N+C-1 downto 0);
SIGNAL t3_2 : SIGNED(N+C-1 downto 0);
SIGNAL t3_3 : SIGNED(N+C-1 downto 0);
SIGNAL t4_1 : SIGNED(N+C-1 downto 0);
SIGNAL t4_2 : SIGNED(N+C-1 downto 0);
SIGNAL START_PIPE : std_logic_vector(4 downto 0);
begin
--
-- GESTION DES SIGNAUX DE SYNCHRONISATION EN PROVENANCE DU SYSTEME
--
PROCESS( clk, rst )
BEGIN
IF (rst = '0') THEN
START_PIPE <= (OTHERS => '0');
ELSIF clk'event and clk = '1' THEN
IF (flush = '1') THEN
START_PIPE <= (OTHERS => '0');
ELSIF (holdn = '0') THEN
START_PIPE <= START_PIPE;
ELSE
START_PIPE <= START_PIPE(3 downto 0) & start;
END IF;
END IF;
END PROCESS;
--
-- ON CREE UNE TRANCHE DE PIPELINE POUR LES MULTIPLICATIONS
--
PROCESS( clk, rst )
BEGIN
IF (rst = '0') THEN
tm_1 <= (OTHERS => '0');
tm_2 <= (OTHERS => '0');
tm_3 <= (OTHERS => '0');
tm_4 <= (OTHERS => '0');
tm_5 <= (OTHERS => '0');
tm_6 <= (OTHERS => '0');
tm_7 <= (OTHERS => '0');
tm_8 <= (OTHERS => '0');
tm_9 <= (OTHERS => '0');
ELSIF clk'event and clk = '1' then
IF START_PIPE(0) = '1' THEN
tm_1 <= TO_SIGNED( INTEGER( REAL( 0.02674874108097600 ) * REAL(2**(C-1)) ), C ) * memXn;
tm_2 <= TO_SIGNED( INTEGER( REAL( -0.01686411844287495 ) * REAL(2**(C-1)) ), C ) * memX1;
tm_3 <= TO_SIGNED( INTEGER( REAL( -0.07822326652898785 ) * REAL(2**(C-1)) ), C ) * memX2;
tm_4 <= TO_SIGNED( INTEGER( REAL( 0.26686411844287230 ) * REAL(2**(C-1)) ), C ) * memX3;
tm_5 <= TO_SIGNED( INTEGER( REAL( 0.60294901823635790 ) * REAL(2**(C-1)) ), C ) * memX4;
tm_6 <= TO_SIGNED( INTEGER( REAL( 0.26686411844287230 ) * REAL(2**(C-1)) ), C ) * memX5;
tm_7 <= TO_SIGNED( INTEGER( REAL( -0.07822326652898785 ) * REAL(2**(C-1)) ), C ) * memX6;
tm_8 <= TO_SIGNED( INTEGER( REAL( -0.01686411844287495 ) * REAL(2**(C-1)) ), C ) * memX7;
tm_9 <= TO_SIGNED( INTEGER( REAL( 0.02674874108097600 ) * REAL(2**(C-1)) ), C ) * memX8;
ELSE
tm_1 <= tm_1;
tm_2 <= tm_2;
tm_3 <= tm_3;
tm_4 <= tm_4;
tm_5 <= tm_5;
tm_6 <= tm_6;
tm_7 <= tm_7;
tm_8 <= tm_8;
tm_9 <= tm_9;
END IF;
END IF;
END PROCESS;
--
-- ON CREE UNE TRANCHE DE PIPELINE POUR LES SOMMES PARTIELLES 1/4
--
PROCESS( clk, rst )
BEGIN
IF (rst = '0') THEN
t2_1 <= (OTHERS => '0');
t2_2 <= (OTHERS => '0');
t2_3 <= (OTHERS => '0');
t2_4 <= (OTHERS => '0');
t2_5 <= (OTHERS => '0');
ELSIF clk'event and clk = '1' then
IF START_PIPE(1) = '1' THEN
t2_1 <= tm_1 + tm_2;
t2_2 <= tm_3 + tm_4;
t2_3 <= tm_5 + tm_6;
t2_4 <= tm_7 + tm_8;
t2_5 <= tm_9;
ELSE
t2_1 <= t2_1;
t2_2 <= t2_2;
t2_3 <= t2_3;
t2_4 <= t2_4;
t2_5 <= t2_5;
END IF;
END IF;
END PROCESS;
--
-- ON CREE UNE TRANCHE DE PIPELINE POUR LES SOMMES PARTIELLES 2/4
--
PROCESS( clk, rst )
BEGIN
IF (rst = '0') THEN
t3_1 <= (OTHERS => '0');
t3_2 <= (OTHERS => '0');
t3_3 <= (OTHERS => '0');
ELSIF clk'event and clk = '1' then
IF START_PIPE(2) = '1' THEN
t3_1 <= t2_1 + t2_2;
t3_2 <= t2_3 + t2_4;
t3_3 <= t2_5;
ELSE
t3_1 <= t3_1;
t3_2 <= t3_2;
t3_3 <= t3_3;
END IF;
END IF;
END PROCESS;
--
-- ON CREE UNE TRANCHE DE PIPELINE POUR LES SOMMES PARTIELLES 3/4
--
PROCESS( clk, rst )
VARIABLE RESU : SIGNED(N+C-1 downto 0);
BEGIN
IF (rst = '0') THEN
t4_1 <= (OTHERS => '0');
t4_2 <= (OTHERS => '0');
ELSIF clk'event and clk = '1' then
IF START_PIPE(3) = '1' THEN
t4_1 <= t3_1 + t3_2;
t4_2 <= t3_3;
ELSE
t4_1 <= t4_1;
t4_2 <= t4_2;
END IF;
END IF;
END PROCESS;
-- ON CREE UNE TRANCHE DE PIPELINE POUR LES GROUPES DE RESULTATS 8 BITS
--
-- ON CREE UNE TRANCHE DE PIPELINE POUR LES SOMMES PARTIELLES 1/4
--
PROCESS( clk, rst )
VARIABLE RESU : SIGNED(N+C-1 downto 0);
BEGIN
IF (rst = '0') THEN
OUTPUT_1 <= (OTHERS => '0');
ELSIF clk'event and clk = '1' then
IF START_PIPE(4) = '1' THEN
RESU := t4_1 + t4_2;
OUTPUT_1 <= STD_LOGIC_VECTOR( RESIZE(RESU(N+C-1 downto C-1), 32) );
END IF;
END IF;
END PROCESS;
--
-- ON REALISE LE VIEILLISSEMENT DES ECHANTILLONS DANS LE TEMPS
--
PROCESS( clk, rst )
VARIABLE RESU : SIGNED(N+C-1 downto 0);
BEGIN
IF (rst = '0') THEN
memXn <= (OTHERS => '0');
memX1 <= (OTHERS => '0');
memX2 <= (OTHERS => '0');
memX3 <= (OTHERS => '0');
memX4 <= (OTHERS => '0');
memX5 <= (OTHERS => '0');
memX6 <= (OTHERS => '0');
memX7 <= (OTHERS => '0');
memX8 <= (OTHERS => '0');
ELSIF clk'event and clk = '1' then
IF START_PIPE(1) = '1' THEN
memXn <= SIGNED(INPUT_1(7 DOWNTO 0));
memX1 <= memXn;
memX2 <= memX1;
memX3 <= memX2;
memX4 <= memX3;
memX5 <= memX4;
memX6 <= memX5;
memX7 <= memX6;
memX8 <= memX7;
ELSE
memXn <= memXn;
memX1 <= memX1;
memX2 <= memX2;
memX3 <= memX3;
memX4 <= memX4;
memX5 <= memX5;
memX6 <= memX6;
memX7 <= memX7;
memX8 <= memX8;
END IF;
END IF;
END PROCESS;
end Behavioral;
| gpl-3.0 | 648d82cdc33b992e9e8c177ce4552c1c | 0.521366 | 2.553319 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Video_Memory/simulation/Video_Memory_tb.vhd | 1 | 4,373 | --------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: Video_Memory_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY Video_Memory_tb IS
END ENTITY;
ARCHITECTURE Video_Memory_tb_ARCH OF Video_Memory_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
Video_Memory_tb_synth_inst:ENTITY work.Video_Memory_tb_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| mit | ef5d03e9528bc4a200a0417645171ce5 | 0.606677 | 4.394975 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ram_image.vhd | 1 | 362,811 | ---------------------------------------------------------------------
-- TITLE: Random Access Memory for Xilinx
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 11/06/05
-- FILENAME: ram_xilinx.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements Plasma internal RAM as RAMB for Spartan 3x
--
-- Compile the MIPS C and assembly code into "test.axf".
-- Run convert.exe to change "test.axf" to "code.txt" which
-- will contain the hex values of the opcodes.
-- Next run "ram_image ram_xilinx.vhd code.txt ram_image.vhd",
-- to create the "ram_image.vhd" file that will have the opcodes
-- correctly placed inside the INIT_00 => strings.
-- Then include ram_image.vhd in the simulation/synthesis.
--
-- Warning: Addresses 0x1000 - 0x1FFF are reserved for the cache
-- if the DDR cache is enabled.
---------------------------------------------------------------------
-- UPDATED: 09/07/10 Olivier Rinaudo ([email protected])
-- new behaviour: 8KB expandable to 64KB of internal RAM
--
-- MEMORY MAP
-- 0000..1FFF : 8KB 8KB block0 (upper 4KB used as DDR cache)
-- 2000..3FFF : 8KB 16KB block1
-- 4000..5FFF : 8KB 24KB block2
-- 6000..7FFF : 8KB 32KB block3
-- 8000..9FFF : 8KB 40KB block4
-- A000..BFFF : 8KB 48KB block5
-- C000..DFFF : 8KB 56KB block6
-- E000..FFFF : 8KB 64KB block7
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity ram is
generic(memory_type : string := "DEFAULT";
--Number of 8KB blocks of internal RAM, up to 64KB (1 to 8)
block_count : integer := 03);
port(clk : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector( 3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
--type
type mem32_vector IS ARRAY (NATURAL RANGE<>) OF std_logic_vector(31 downto 0);
--Which 8KB block
alias block_sel: std_logic_vector(3 downto 0) is address(16 downto 13);
--Address within a 8KB block (without lower two bits)
alias block_addr : std_logic_vector(10 downto 0) is address(12 downto 2);
--Block enable with 1 bit per memory block
signal block_enable: std_logic_vector(15 downto 0);
--Block Data Out
signal block_do: mem32_vector(15 downto 0);
--Remember which block was selected
signal block_sel_buf: std_logic_vector(3 downto 0);
begin
block_enable<= "0000000000000001" when (enable='1') and (block_sel="0000") else
"0000000000000010" when (enable='1') and (block_sel="0001") else
"0000000000000100" when (enable='1') and (block_sel="0010") else
"0000000000001000" when (enable='1') and (block_sel="0011") else
"0000000000010000" when (enable='1') and (block_sel="0100") else
"0000000000100000" when (enable='1') and (block_sel="0101") else
"0000000001000000" when (enable='1') and (block_sel="0110") else
"0000000010000000" when (enable='1') and (block_sel="0111") else
"0000000100000000" when (enable='1') and (block_sel="1000") else
"0000001000000000" when (enable='1') and (block_sel="1001") else
"0000010000000000" when (enable='1') and (block_sel="1010") else
"0000100000000000" when (enable='1') and (block_sel="1011") else
"0001000000000000" when (enable='1') and (block_sel="1100") else
"0010000000000000" when (enable='1') and (block_sel="1101") else
"0100000000000000" when (enable='1') and (block_sel="1110") else
"1000000000000000" when (enable='1') and (block_sel="1111") else
"0000000000000000";
proc_blocksel: process (clk, block_sel) is
begin
if rising_edge(clk) then
block_sel_buf <= block_sel;
end if;
end process;
proc_do: process (block_do, block_sel_buf) is
begin
data_read <= block_do(conv_integer(block_sel_buf));
end process;
-----------------------------------------------------------------------------
--
-- BLOCKS generation
--
-----------------------------------------------------------------------------
block0: if (block_count > 0) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"8c8c8c3403acacacacacacacacacacacac08000c241400ac273c243c243c273c",
INIT_01 => X"0c243c240c3c01012424afafafaf2700030003000334038c8c8c8c8c8c8c8c8c",
INIT_02 => X"8f8f8f248f00260c020c240c3c260c020c240c3c260c240c240c3c260c240c3c",
INIT_03 => X"000300140080ac001131008c3c243c1024241000800003ac001030008c3c2703",
INIT_04 => X"8c3c00030014ac24001131008c3c2424102c30002424240880ac001030008c3c",
INIT_05 => X"a941581f94dc984500204d204d20420a204100726f4800080014ac2400113100",
INIT_06 => X"d3b9c682adc2c81a8df5f8c42476d0bd84a8b16130ba50fbc4c2f90fcd230800",
INIT_07 => X"47314a8f82840b7ee457b6b6af8c1565b7f0ed85de4078f97f898d9ad44258d7",
INIT_08 => X"e75582185a8fac373024844fc3d60e7ea85ed9e011caee81d3b13e2bc5473f12",
INIT_09 => X"47f1f606c685af8a2e4a8d6be3ac12ffb717218d6a91fe6a28c51b5deaca9912",
INIT_0A => X"5d2c3946ccae80f6ab5e0b2f4885362e2e8c8c4ce7679e4e9df8f39db657b9fe",
INIT_0B => X"f56cd26f2c5b42368df4d83e95b24163ab1b7125795700cf6eacd963f881df4f",
INIT_0C => X"17664d419cdf454c467b252bb8bdac97bde56a809470b6b772f29ab9d371b409",
INIT_0D => X"7a5efd28b262b9aed638e6acd74523257f694a1a10e177d0c06f8d12b243077d",
INIT_0E => X"b6a66541d6cbc4ce3ca13e2d54b204c300b9aa1d3fef6e606b2f3a29a172ec02",
INIT_0F => X"7b429184329011100da1fbab8d51aa9dbd512cad86f056d227c9ec84e1609f53",
INIT_10 => X"d4bce03d4373837538676d43b101a0a0b7f5fe9514a40345fbf2d4e5d3b2deac",
INIT_11 => X"5726158d465604dc19e162c9e42b2dcf1acd850153167cd7fbed62e717e8af2e",
INIT_12 => X"17a26d42dc8fdeb1b597c7e4ed350e92f7edb7dca6cfcaf872fa48d739c8adfa",
INIT_13 => X"cba58d562a0a24682ec7d2e0afd47feec635b1f062407f66db4e31b34d6e8f09",
INIT_14 => X"d0a9a452d9c0b34267a233f1266a1317d9e9029e08209703758626800616f1aa",
INIT_15 => X"be5c15563bc4d6b5ac7cac764644095b3e0fa8d4ed1a1fccaa7966629dfcef47",
INIT_16 => X"c6a2381ba0adb181835217e9fb925ea72b142117a964f74dc972d5046e6e1083",
INIT_17 => X"eae967c338af3cc8bf23dcbc303214617743748aa72a27351dc0372bc8f35f9f",
INIT_18 => X"523744c50bdd139bf3eaf4f2fe60898af2eba0bea5d5d8bcb51c163846db9eb5",
INIT_19 => X"35df83a66d06907522d7c8c98968533e1b630f23e8996c6dcc5ead3ac0ac27c7",
INIT_1A => X"9510ca8d9a782a146ca3b9616350be5fb692a0b96fefcf40e54a8ec8ed9d08e1",
INIT_1B => X"956571fc507c72a0a98fde8e08b27fa873acbff15f111cb54c020dc4abff6d41",
INIT_1C => X"9e222db76675cf8e93b4c8064b904d3d1c1192a9baee48cfa9f55fd4ed3fb5c5",
INIT_1D => X"4d701fe3078f58837daf9c58c53f6e7039a6e5b62e66559a0b4b2bd41027dd1b",
INIT_1E => X"d056d5b51b95da26a53b7d154e6ff47fb8d576675d0874872806372fc23b786f",
INIT_1F => X"152a5994e619c43f70579a6759914f4e2060b9f4fd78466b65f0ab66cd7b91bf",
INIT_20 => X"060078104ead933235a6f255b2544e477465cdd091434869be5041a2b681432b",
INIT_21 => X"6b0c7c92ab2cb24c65f3db0c13c43709ef99ada733273c086e9355b8f05a11a4",
INIT_22 => X"2f8750eea4106f183a449e43eec1094abb693b99817c957fe4d577f4afcc796d",
INIT_23 => X"aa27ea8a1d4814e29253e7c57d26b356666fed0d12a6885745da4e3eb9f2e841",
INIT_24 => X"268d041445342f26c028f45e348220d779b9ced47d4aabde0e3f300f2bcbc5a0",
INIT_25 => X"c002e009b5da123fcf66661386f67a01af7c92bcf9b062bbd4ca8fa3d29309bd",
INIT_26 => X"c81192cc7b3c16bd2f4833f88765e065af5a6aa9eadaab7abb7b7833d8879747",
INIT_27 => X"a706ef7c3d1af0579f00568d30384972ead0ff61fc0cffdaf5aad0ea88626389",
INIT_28 => X"2edc7bb432b80746b55ea410ada7b19adc28015e5e37e2c75826887e84c34d27",
INIT_29 => X"87be116c17fffd0e61f18f3983c1f7496d4c3c1b79aab5a93bf05cb74e14d381",
INIT_2A => X"8332ef2fca1faac9cc6a2112b89e8cf54f4aef89b9ca1da0555528c8fbc466bf",
INIT_2B => X"922e07245eec16344368aa57794a4339cebda6748efdeec7ef91117bf997e1f3",
INIT_2C => X"7add5a1219e4e1cf04640b1b7c2746003bf198a4159340c8d6da523d95123985",
INIT_2D => X"5035fe9d44207cea9eaa70c84a9690f63b54ba8063a4b4f6cc83ad3a969cef0a",
INIT_2E => X"5bcd1be90e784e204f150b713f5e666897063737cea8f20c4c791b01cc07be64",
INIT_2F => X"515022967b8865cb55288de236f649da69d9bc660ae312e277295141c6f5a608",
INIT_30 => X"0102e6682180a9075673c9d0ec2fadb3057ec78bcec1d756ec5d98b8caabf99c",
INIT_31 => X"c98375cc16b67be1eda8afe0072d10e71608355e35e553a9c4822586032715eb",
INIT_32 => X"84a8106df4fa9e801426b6b5d4b2ce18b72e75c92cd36760a7be31ad9bed79b9",
INIT_33 => X"24ba6b10ae1d96cc3fad8c7eca20b19abc0dc35235baf477501fe6a20bbdc7f8",
INIT_34 => X"2d35fdfaf96b2d2e25caa1672ba0bc867a438c6cb05c4b23fbf8b0298f92adab",
INIT_35 => X"5d3cd7225da07622a3e2cce4c1492eef724dd880d7a002949448fddc0a35d5a0",
INIT_36 => X"263ad895d64800d0bf25003ed8786d6c12ff83a9def1151d2c2fd4d201c35192",
INIT_37 => X"6b6d9997ac55c0d0d6ee4982ce6c5a88e642cd047ea3d444c341b05c1304d64f",
INIT_38 => X"5d55d99220049fa13d50fadb836aad9797c66433acf30dfcf3c87bd07234823d",
INIT_39 => X"f71567fc5b25454363dbf491482e361639b8aef66fc25032d718aa3a2f2bb989",
INIT_3A => X"c02c0bcab6bc13a0f42035d61e058864de303e9c278c36e693edcfaa2c946e94",
INIT_3B => X"5165d89606e2f428bacb9c45a95236d821c1cf65cb0ab8b5bcea9794ecfd8938",
INIT_3C => X"e28f0ba46488dbd11e5c48496182ebc5b24cec0e78fe314e4ad620fde0ab13a6",
INIT_3D => X"9398325cd1322e71cac237369e89e2229c5a72b891dd0271af6102a88599c583",
INIT_3E => X"7007b77d115a8b7aedd2ef62afc04ebb3461b0e25f9dcd42ae0cacb6eede7631",
INIT_3F => X"498dda4fd64c7cc95d359b2badf79f538db123c30dc7ee76515bcd68cdfb5d97"
)
port map (
DO => block_do(0)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"92919002e09f9d9c9e9796959493929190000000a560a4a0bd1d8404a5059c1c",
INIT_01 => X"00a405c4000607070708b0b1b2bfbd85e085e085e0a2e09f9d9c9e9796959493",
INIT_02 => X"b0b1b202bf010400200084000404004000440002040004006400030400040010",
INIT_03 => X"00e000a00085450000280049028402a60706a0008500e0440060a3004502bde0",
INIT_04 => X"4b0200e0a4a647a50000280049024747604342a40605840085470060a3004502",
INIT_05 => X"e3f2ba294a516967003d613d693d20003d20006c20650000a4a647a500406a00",
INIT_06 => X"6bea7e3efc413e70dc21740e549bcdab5e580525a3310d66c9332e76e71b547c",
INIT_07 => X"6448cbca3ae9f705f1b10fa85c89be757c05d1fbaafbfe02dbec3c323bec5c8f",
INIT_08 => X"4eb51bf8f87f1a0b7dba22bb1548e333af1bacaa0911643b795e5a14641c1e1f",
INIT_09 => X"a80ebc9a548ad4084efd154fe4e2b3365c3bb5be55aa21ac6cfa4ebc3d793898",
INIT_0A => X"d914a39933d9f13e86200bf407fb8520304a1cde76ad7fa3afc4e5092d4cf3ac",
INIT_0B => X"fad0d2605ee90825e99b443299fb3a84b3514c6adad0e64978bcbe94f610a0f7",
INIT_0C => X"2fb4bcaf0bdae4227c7c668c85178086add357897c44803f5a6587d96466e8d8",
INIT_0D => X"a6ac68cdae6c8295f496d177f8e5024512ed6724c735b689ef2d11b8079327ff",
INIT_0E => X"627c87152f01d9c9019145d9fe189a228b4cd3ed6a4c286e80c9cfcb37b2cab4",
INIT_0F => X"6710f001ec72b202a4c78cf9327ee9bf9bfe618164ea4f75ce71493e65cd7269",
INIT_10 => X"a116fd0d01211a56de708a63c6af2e8ec57dd6e501d5ab9b0dbc030ad49f5b99",
INIT_11 => X"3a1feb0d264746f36aac1e3b24eb1a1c81a4abc7e513edbcdd6c55614bd2d2e3",
INIT_12 => X"2a09fd50b5d8fa0d9cf20f864cd5789b5d0d0d03b54d0a60db119ec7f8ba2ac0",
INIT_13 => X"3db5025bed9c0d5a7b4a73d14a1e199cdc80cf2e2821b675764e32315413fbe2",
INIT_14 => X"1841981169e37fe249202fee3b5533e107a84dffc8165661d280b5c824c402b6",
INIT_15 => X"1e5be7abf51bb62b67027feebc758a8aa9e52745ae5c25e8964bfef41aa2c8a8",
INIT_16 => X"c0844305d17554082f6969181957d691795cca39e48f286874767487e14d1102",
INIT_17 => X"4e1530cdc60d4fff76e603e6d067821d689dc7cf9d61637ad3c4f3997d4df347",
INIT_18 => X"6b2bbeab01d541c9e2d08774953db60d3166edea9cb596b2793762325dd19df4",
INIT_19 => X"e271ab42642bfd90b5c965073d4fab5e8df1d02a43143aaff5f255a36a3516be",
INIT_1A => X"15cceade9f239ffc9ce11953e3edb495ebad25abcab0114973dca4311da362dc",
INIT_1B => X"b107885ae7fdbbd466c811c3ef264d640e1a85df5a1a7c6811d31e052e9b9a23",
INIT_1C => X"7a92f814e33ba3274670abe96413b7ae4d13ffdbf431871b60c4d36890796b3f",
INIT_1D => X"2d894cc725a8e4a13d63038cfd8ec5215bb374897538c423fd4510028e7967ff",
INIT_1E => X"6b1f24a18410dcd2df707e26ec7e12d6f8b0b7c5bc7506e2378ca34e8845446a",
INIT_1F => X"91cf4c80fac827d35db05bd7f2d30e9dc6dbb5b29ac3f3b34edaef8ca517105a",
INIT_20 => X"9500bb51d6856a74778d3c6579a3d3fc6f2dcc33cdf1898a081fdbf41b5221e9",
INIT_21 => X"488090d38cfd2c7b853695213ed6f72cc6dc2fc9f65f51b8be784019f7564bbb",
INIT_22 => X"a87979616c91c0db2c3a8d85e57e9569e0efe2b4085f6c441116e8ec2d2d2f68",
INIT_23 => X"d5c0914ad87c579deaf914148c82e206aa901f4ebd6d92e6e47d202b5200796a",
INIT_24 => X"fe65a681b2bd6ed65dfcc386eabf51fc9a0e6e14414944fbde9d930590edcc60",
INIT_25 => X"446442febd2c88b76f1bfe790a9d5e221e4fd45867c285d8a590dab22c314aa8",
INIT_26 => X"d8664141f1307658642225ff527c967fc06798d6c44d8714d557b0c7b52dd9c9",
INIT_27 => X"b738e869b19bfd93b810a1698fb38c1d3ed9d7f395ee795e3e7b0ee65bb9919b",
INIT_28 => X"01142bd734d3d8f975794a5ecf86390f9d9a14108b68d662d9c2795a422b2cf6",
INIT_29 => X"2e429362a902e4ca4a2a61834fff4887759d4c3ea904c2f3c8663374f8b55d92",
INIT_2A => X"aa00861ef01e116f8e1a4f0e87780f951e58f012bd8f737a1eda24d64fb705db",
INIT_2B => X"3bc11c41a902df479b84b091d86d229a2218368deea2bb9ec34d0f149017e2c8",
INIT_2C => X"a037fca185187f035e9c3e69032152532e5ebb110220887073577fcc330f0d43",
INIT_2D => X"7d14987cfbc23022294b6e60a9ee3a4f114ebc4f281c8ae61a63a1727478ed65",
INIT_2E => X"3e83b69f31a2926c0c050312ca78b99f777c6a003a244d659cec8820f5652ba7",
INIT_2F => X"823bde2a60c2b49992da9d20620d5c04f243ce4c60147f1cb583b645e0a628d0",
INIT_30 => X"e34ce0f19f86697a259f5e184dbde6f68903950f55fd80843439df634a1be9eb",
INIT_31 => X"b539b4aa188831b7b04a2de05af20d4cfe979e704cb89c3090aa65cebafb53dc",
INIT_32 => X"09867555450ebce7664f5f6cb347d2bd55d84697725ac7f2aba1f6e6b68acc03",
INIT_33 => X"8c1453d73f4716241d2277a2ff5882ca8d65e5c32663f27378cadee860648ceb",
INIT_34 => X"a0c4723e2647ed66ba4a0c9f2a1701a4feb3080b7ff4a72ea1fb01e993f20dfa",
INIT_35 => X"28bc179ddd8ce0c14984a848ebb616e08f089f63256f0e8a164d6f549335fe7b",
INIT_36 => X"b1c93e3d3a3661bbc307c54e3150be1affa0b3a5e2714b678b5ac6f8f4e7b334",
INIT_37 => X"f599d11b66afe8db6ce27577f153a361587541acfa2784e8829c170d8721e4ef",
INIT_38 => X"47ff107ad89539e36732b97e27edd42704b39971b7ec64ac21874f751ac47c67",
INIT_39 => X"68e9f0d97f0c1630e104771184e592f3997d917259ea29bec0768cb0e3091294",
INIT_3A => X"4539341df4d82ea008381b1d44384851fff9ee397fbda8f5375d096faf70da35",
INIT_3B => X"26bdfecad2671677c392c36e4fcf7926f227532fc01e58d6435a1ddeec854c0d",
INIT_3C => X"778a4a3786950856ba6bb5552f8c37b51d08ef7b1832841a45773c4bad069030",
INIT_3D => X"f10622d23e95dfa502ee8c5dcaf2b94ecc05280154b106ae8827b4977793fb14",
INIT_3E => X"e8756228f3771ee69df8f2537a046364cd05c872f41dcdc80ad2be8032dc36b6",
INIT_3F => X"ad8579d1887ee7f663a9cf28553fbe3f91550a43c4b4946384aa5bccbbe11a32"
)
port map (
DO => block_do(0)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000ff18004200420002008200",
INIT_01 => X"0002000200008890000000000000ff1000100010000000000000000000000000",
INIT_02 => X"0000000000000200200002000002002000020000020000000200000200000000",
INIT_03 => X"100000ff00000000ff00000020002000000000000010000000ff000000200000",
INIT_04 => X"0020000010ff00ff00ff00000020000000000010ff000000000000ff00000020",
INIT_05 => X"e11ed77c585c4823002078206e20200020200064776c000010ff00ff00ff0000",
INIT_06 => X"774a2a5f23f8d4ddf0bd861d869ee08ca85aa389d9e4d75d07d7722543e92762",
INIT_07 => X"96027f700aeabf5d5035403c26e9a80fc7c13fa5c326bb48a41b8fcc067c4ea4",
INIT_08 => X"d32a773470bd011ea557010101d4c5e77021115b597006df2f23827bfdee9e5d",
INIT_09 => X"f0ae1de8131a1b2cb5b531ff0afcc9502909e3ecaa59fad4fd4b826e1a5ce8f6",
INIT_0A => X"5a67d258fb685d4aaca8283b23ec85e88ad33dde6e64d44d8222e843c29dab5a",
INIT_0B => X"d07e8a9d81bb8d8ec346ea6f163ae48b6bcf51b39ecd7eefa285c104b127d594",
INIT_0C => X"fe0b270660dabcfc32971d53767f0872ef60ed67dfe213b42828aeabaf4abc37",
INIT_0D => X"837c92fd7cca8f4e09a71b6558d56886e761805e2213b006bbd38ed76fbf3bc3",
INIT_0E => X"6966fa81e804beaa01a95d8fdba535edbc257c3c1820c225de1162881fc4489d",
INIT_0F => X"df4fd65f3d98006374237579d58cfe5da5e253eb312c9dec9828251f8ef405ba",
INIT_10 => X"5c98324109971a3cad683685e6745396a27ad7a52836d60c02e186cf5e6bfe26",
INIT_11 => X"f5305acb5858f396b95db6461344b7cafc5abd3453bf4a7e629b4e842c613074",
INIT_12 => X"34652f936b85807f9039de350d485ba4e70e02bc5c104e77d762b99c91912684",
INIT_13 => X"94538bdcfa86a8ae2dad2fe087cc5c563fc892d0825cf6baffe64b14527d3f25",
INIT_14 => X"c17d3bdb5fbc62fea5a9784ceb192eca94cd449576c20d99ee5548d8f7a07e4a",
INIT_15 => X"b75466e498c4cfcb4857f0ada7a6582e57787d926cf88d5ebcce05d0ee16b1e3",
INIT_16 => X"4a632fc2c45be57a9fe05bd096cd153b97df73bfbb3311a02781801be556c7c7",
INIT_17 => X"4ade07ad39e3f3e659f97d685edd54d7e23b2ddf45c8e2cf41bb7edfdc5b3125",
INIT_18 => X"c136b1ab9cb871cca7aa0e1498d06590a18ba70c99116bf1e5d55c2298cfe8fe",
INIT_19 => X"1d9f0a7d29790e8e45952736a214ea422b625a2d5e774be0faa125b49e2527dc",
INIT_1A => X"7081203a319a043be49eacf219abfdbf74d699f3953c4676c0b19fb566914a89",
INIT_1B => X"0de4a8106ed2b1c5452a9116762aa8e0ed54022a9eb72d761779676460d19253",
INIT_1C => X"604ac8f91f8a7cdb8372fcab643b7dd1d6280e2cea994c1c960964cbcebe7714",
INIT_1D => X"e0588aec4687e9d349a8a3f1137f9716c283d95c1dbc0fdbd9be88d92e28acec",
INIT_1E => X"d58e8b92fc382f19c3a51b869eb6bb3145c3d87dec7b17818ab4de5e933eaebb",
INIT_1F => X"797af5a00ec1b8b7c3ff5805f81cc9b1208a4ad22e6200401751a14b90df2ec4",
INIT_20 => X"47ed751c7d25767e10b0a5f4f704c9b791e3fbebd82f83828fb2fa50e99dbd64",
INIT_21 => X"156c2c58d4e673a1fb4a9f687c2863013eb3a7ac378bb602c58a5ee3afc3f955",
INIT_22 => X"d10c58e0aaf095cfc3821866b6b81635d7a7a6fd0f40ac9621dde88ad88c32a3",
INIT_23 => X"7d51f90a5527891bab2c9fcb646d484fb01c9463942c68b5f388825735d70239",
INIT_24 => X"657ecd1408ac716b07039e65914ba33f5979fb67d4c9272322c362129143c65e",
INIT_25 => X"038f8648960bf031213bde159a4c94b839b949fec5a8f004f150ccc6f13e4047",
INIT_26 => X"764226e6e60197dac2ee740099b9ec47a22aaccbe46154cebb48993f9a1d3e3a",
INIT_27 => X"78da4d3d7ced649fda4b370023d1d44d5ac8738ed97b160b67ff33bb5beaefa9",
INIT_28 => X"7657dd3316667e9825fd373625355d2950a8644eb320e1497e287eda507d60f1",
INIT_29 => X"077fb8531a77b8179bcb29df79465e40ce6af7f45ee76243371115f3258129df",
INIT_2A => X"273e79baa86393ea0a7667e06787bab50a7747cb36359f536489ba8afee9817e",
INIT_2B => X"68d5e10460a53132309ae88ac53cd0b0b029a67e2cb9e6995adde51aa99a920f",
INIT_2C => X"dd9603b288f662442de1f5ce64db1274762ad21cb79fb4ed0e96a63f69b2cfd5",
INIT_2D => X"2b39f1ffa1df8e52a13c4bf8d126922a5e355dbeb6cedaad52b29fa1b76b31c0",
INIT_2E => X"36b3f045af1cc8412157ea5b5f3370556b876ccc45372dc864b9ab3dcf08fbe0",
INIT_2F => X"2a8c6f38ef70ae680a050b883710cf10e2183326cc205ac649a056d166e567c1",
INIT_30 => X"b6ece6e90b77c92dcab52d85e8785fff1a19dbf15852df5128eee1578d30929a",
INIT_31 => X"6a8cd54b14b0c7415173632cb4130f2cf437601c4e75296d8a7bfacdf8011baf",
INIT_32 => X"c1c79c69c3cb547c875e7406606a0631e73e4ca2a07d1722a01f564ace81e6d9",
INIT_33 => X"54271e7270cb863424dc9eb1c3bc58840647fb4527e971efa0fbc9c1729cab52",
INIT_34 => X"bc783d85d7de8b71ed9c60dbca4b1928efb0261b6df94091c5efd71c1178ccd6",
INIT_35 => X"2c496f36204ec3a577602cbf26382548ed06b6d49afbffc27623a6ab9c0140e9",
INIT_36 => X"a6eb9459f1dfc2d5422d6dac4b6f306491e0e6b51473bda35278b5cea813db8b",
INIT_37 => X"f580d9795a3f74aa330cc47fc86e8cbd92f33f5738aa8dc3126f811442afc894",
INIT_38 => X"ed705985384b954a4ceda4fe3b1fcb1904d0a1468bb952b49951bfbbb751a9c6",
INIT_39 => X"2ca1b50a1bb406b40dcca9f3696641f2420b4c4855713776bae78a2a063cf40b",
INIT_3A => X"90eafbf5593a2d2a07c8c3edafb4f84dc536b28f89920cd83032852125b7c32d",
INIT_3B => X"3dfa57d647bf327381592f40e723d5abf98f91d6d46f72cf8a8bb522d3a73d48",
INIT_3C => X"55bdf0519753cf50aa921f817fcb70c5f23e74519438303efedac87df0bcf887",
INIT_3D => X"baceb643eac04fcc34e797a13268bb62dd54479c8166fa8a322105cee22705cd",
INIT_3E => X"c2ecdec23ceb18bb159d6f5c763c9aab92447a92f99f75dc7e7679251515bb76",
INIT_3F => X"e06801f90f8a914baced867a606d4fea4893cac54400d0dcd6ba3bbd5e0c57bf"
)
port map (
DO => block_do(0)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"08040000082c2824201c1814100c0804000e003104fd2a00c800e000dc00d001",
INIT_01 => X"6bb800a86b003f3e0d051014181ce03d083f083e0800082c2824201c1814100c",
INIT_02 => X"101418011c0dc06b218ad46b00c06b218acc6b00c06b0d8ac46b00c06b058a00",
INIT_03 => X"210800f300000000fb020020000100100d0a10000021080000fb020020002008",
INIT_04 => X"2000000806f200fc00fb0200200030570e0a0f06fc1c0173000000fb02002000",
INIT_05 => X"46fbabcdecff73c600006900690020000020000a6f6c009c06e600fc00fb0200",
INIT_06 => X"96dc970167e1a1e9873d418211b4c6b2d4e9175d5a58b7329a9f635a8de8f8c2",
INIT_07 => X"bd47d00be5a100efb3eb9599bbf961d8943ce6293afa431a5c1854affbb02a38",
INIT_08 => X"e8ca13a429231ce1f59b196f5c4750cd3b10f2d4dc9e2470634bc573c57ba823",
INIT_09 => X"4418d50a4829b270a98249329ef0af94d3047370a21a2b8605cb775f344de032",
INIT_0A => X"34d3e350b767ec05c3bab9ec04b26c23f6c4ec3247d42d84cd3306429bd78e5b",
INIT_0B => X"5485b2aa53e2f5cfe5bcee579031945348257e7e691a2369fa44b40105a8f25e",
INIT_0C => X"3a698362636166fcbbc0f10cf1e4ec95ac51594ea5de29628a7075a89882d435",
INIT_0D => X"f27aba169049caaa1fc1a5099d0ad839ec96d883e4c163d44f8d346d1fac16af",
INIT_0E => X"9e136102ee43152affc6a3cde4d1d456007999d219d7da035ec361082ac299a8",
INIT_0F => X"cf8b004df316edf43c5b6a7cbd4e8c0d67c3fdebff7e76a73a4bcfaba67181fc",
INIT_10 => X"a4c28bd8071b2b890c971fc9b9022d21163ef6f2d6980ebfbea7d161988e1750",
INIT_11 => X"3b6cb2d20e2b065868fba8794c66ee53884ddde220efdef7c233d1d5359892cf",
INIT_12 => X"a55a5dc2dbb05aa753eb98ea9c705687cd4722a05b31a72204087316f64eab54",
INIT_13 => X"52dedbbcca367b31c0e91f7c4f6db0d762f93725716b4d715bce23639a47b7a3",
INIT_14 => X"229fb9b6e347f8a081026ef01d57a6095e8ab5ca7143fde0db301297954cd457",
INIT_15 => X"e590901c6164878cea1539ba6aa42c718d3f86466d8fcb152d4815499004fd4b",
INIT_16 => X"15bc619bae399757d1dd8e8ddfb7de8a5ee894cc3a1d832aa1db8a603bcd77a8",
INIT_17 => X"32996a8ddded60d960d7aac401006b5be48753e06634ef28cc2202e6650c9e96",
INIT_18 => X"38ef11efbfde7e788200abf76f13decf5a3cffcd835cbfc836d81860b76e5cd1",
INIT_19 => X"cf3833355540a5ef785afa92f21593a3af3c5501bf3b8436bb3773f2a9abfb22",
INIT_1A => X"62d58cc4ce69acad2b8c2f871ed1384d89081c75f27674706c5afa82aa9f2b8d",
INIT_1B => X"6b96746cdc15eee23023960d2b7b00a83d9aac44f91b8bb1cfbae647ef7d10ca",
INIT_1C => X"404628e2169758cd8b0bad377b4727b952b0e27d8b6e181b983930a13c5a65fe",
INIT_1D => X"aaa77a9a3159d9018600d10d90539ac2b2ef1b6d4ca75ea06c56723962cb1232",
INIT_1E => X"f51d513bd69847e552b6b28fcd9a1b3d1ae44e083c2b8a1c2de0b18bd141f8f2",
INIT_1F => X"6c135baf7bc1965163a9b1e15fb3b4d63520d1be6477c42aaccefc243dfcd87d",
INIT_20 => X"fc2b7ea2b83765011744845498ee4f90165d031a7184522ff339a4762a13bc9f",
INIT_21 => X"ac56b0bbc722dbd6ee53997eefee831198c4c9b1b1273d28ecb7a633bbc45f68",
INIT_22 => X"e35a514f45c83a997e9e9bcd6ac29610572a349932f8413d916d22c24e6e3e3f",
INIT_23 => X"c63cdbf8ca140a7ddff892acae350624fac8c736ceff77a4584d66df855ee83e",
INIT_24 => X"61419021d2af1fa1f7a1237ec4e1e9676e44d4d2931c77353a7efea40158e2b8",
INIT_25 => X"86604d9184f079f4f3a309e44f8a5368f7d2bd0e443795136637aeefb734674f",
INIT_26 => X"e502a889073aa5eb36fa5602434bac9930dc3a064b45405d0e1fe2b3a6e366a2",
INIT_27 => X"552642888e9281316edfe49e99e8d7cf74af59d72f6a8eb4d3720881b8e3186e",
INIT_28 => X"23c87148e363624bdb232048e07b3aca90cb4873d287fdd655316ae394bca943",
INIT_29 => X"c908fff5408dce0c1d2aea8274403cd32f4d52d4dbf6c6a060a8ed43132c183a",
INIT_2A => X"95a476e131ceff01946de9ab4f5e4c24341f5550f11d7c02a56e00b03a54db76",
INIT_2B => X"5b3f5ae08fcde9562273dee782b2b204e1e18d74c0acbdd4bc9d2edf266941b9",
INIT_2C => X"8a2aff40298223e60cb1c082ed85623ba1f6d21f613173529e1a50e3a0e5b15d",
INIT_2D => X"63a9cab712583eb33188c34b60aec8feb35c8624bd0ffe9a66000eb2e1f086f3",
INIT_2E => X"232d1b9ba2cc90596a9ffe5398ae05a323e814d2a04828cc0eb26b63c5d595b7",
INIT_2F => X"3fd06e2e0e14ad12f652a318523daa1a140ccf16b3b0be47efc24ae3b8f248f7",
INIT_30 => X"426af53496be77a52392522d20311172ee174a3327e146e8d3723de73c4bf8de",
INIT_31 => X"85b241b7f87d6f4c7abd8bc0c0c847517382bc2da93bb6f9258a6d1813a19aca",
INIT_32 => X"44ca2d8ba52e412e410a0ea92e884821dcfbd02604e07adc58a631e46b26f6c2",
INIT_33 => X"dee13c250a3c870f95f06cdd40e32e1950ef499bb8378134b14537bfd03f32db",
INIT_34 => X"6870f22f536c5a6178ae9a2b0094960bae951fd2cce675b81f1e0c0b940c530f",
INIT_35 => X"9da6a57def0530570ebe965a0aa9168d833f2797ad34d203b3299e9fd52892a1",
INIT_36 => X"e33dddeddc432c0e6e50a8f748b201b2d4db62f90e28f36b1b0f7c9c309eea3e",
INIT_37 => X"fa2a91a75ce302f0caf71408602b823d64f2753864bf1ee358da144c6f163f6f",
INIT_38 => X"27142d7106f1d0cbdeda057662eeeb801a8e0a8908ca5b0962bb578f3b6dba99",
INIT_39 => X"dd8957117e701b0ac33787119575fdab11d87269640153f959f3e29c8739811b",
INIT_3A => X"8a3317e211ad5db02d527a4da7f7c2d92e5622709728014d8dea7426825e1afb",
INIT_3B => X"e4f1f22596d6961b6806c86cad66ac3f349868f43c4cae71fa251608a390458e",
INIT_3C => X"40673f751120893f86facc6cd7e4bbad38153917fd56825ceeffdd7074dfffa0",
INIT_3D => X"54eed866963456089c14847f8931e2c7199f8c9ee88c43907d6f022ce82ba0af",
INIT_3E => X"d92f2dbbe912036bc0fc263884954003bbb97816f00c5de977c06ebe3901a8ab",
INIT_3F => X"c40b2692c1ababf70c54d2b00b7a20ab87f3b826dd87daa290f8c4ae3594374c"
)
port map (
DO => block_do(0)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block0
block1: if (block_count > 1) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"aaf04db58201beaf0d0dbfdd9edaedc5cd50925e0e418eb239330857aa562f52",
INIT_01 => X"6451a429508a86bc0cf436a2abfb9b6dba922b142a6e7ec8e3dd1d16232fd117",
INIT_02 => X"8bd7ea56349e6d95ebf2099c247375040da59ffda2ba31788249e0d1f8be5dea",
INIT_03 => X"1dfef39689e04bed80bf368af7b34b805112f49d30a296f625b0eec81a6d9e63",
INIT_04 => X"213323628a2e58e6bd1f1be376c8e34cf8c4c57b8b87742bc0f6944964cf6c35",
INIT_05 => X"4e533aac9405e5a830c53ea9f3e4d97534114e80d1c4a5f888500a1d5a4d9c80",
INIT_06 => X"3bd21681754c228e3110a62ee0e4a27ed83c06bb929d4306012dff7e265c8c40",
INIT_07 => X"7116babd82ba5028fb55dd99c1f2bc45b9302c962beca4d714e931ed9ba62b53",
INIT_08 => X"4b6759fe0f6cb0c276787856372d2092dd79f26b4a48393e7cfba2fb2c85475a",
INIT_09 => X"adfe5a9ac9faa8ce162c7818f3b83f2c5d5c74fcccfdea87531e6123b0b8115a",
INIT_0A => X"b3a04ffe220b3cda0bbebe3d52e04d82cc46e8a233579b4139ff2a58bbdc0f27",
INIT_0B => X"7e00edc94e4996d87e1a7d13051b30b3c55eff01f1bbd4370fc88451120a81f8",
INIT_0C => X"ce21d809a6a98fc466e25174a234f3ab4ce57d97468cfab16e8ce00081f171f8",
INIT_0D => X"47c0e8b2254a2242be95a63ed7a352f62c59663e5b6c7272065eab8f4c366ae2",
INIT_0E => X"f5e6d6a126220a796bb79f7cd08dcf1ef0d43b7ad77dc803dbd6143e833ae2ab",
INIT_0F => X"13fae3b2f4eb506fc622592eeb7da641f3e3880845717f85850fe512f4165c9a",
INIT_10 => X"f1240bfa7db1bbc63f363ff4ef7a33176668492fad02becc1b6dc05033549426",
INIT_11 => X"56801d8b8ab81b438429852523c08217802f021fb2a6db20814be247b28ba86c",
INIT_12 => X"d04d925fe4530ed43a4407c37812223877d5095f1ac24788d819a4658d0c3bc6",
INIT_13 => X"b8354ab4ef20174203c653cc064f31fd41a23a6e05a69cfe7031425f49a2cbbe",
INIT_14 => X"e99fc29f0aa14e91fb871c5b250ed98f5f59eef582e2dad3aeae2f249764d498",
INIT_15 => X"b612df53b7304bd51cd4858ca7c240e555863888a2a1846a807f989d97332355",
INIT_16 => X"aac2bdb12709b24aff37e76e4b2345205a2472500f44a9250b5d67f8d1cf10af",
INIT_17 => X"03fc87388e54de283effaab979cf4dfbdd2361384eda77ea659d42d1c107d383",
INIT_18 => X"53c2c9da4af6c8c68faab2e48a4f2c0fdf31baeb45256c641a4070318661fb15",
INIT_19 => X"acd4efff0585f17c3069b0c45d756a1167143dd4a25785c881d33ec753334183",
INIT_1A => X"2ba983ae494dd1bf781d4fce8b9eb51dea3e5930f645e717bf963024b4d52a00",
INIT_1B => X"e6b301377a706df4186f7ed3f860bb93631586f423eb075852427f00e44bb883",
INIT_1C => X"f919ed3b9271ccc32598bb092c2103d7de9e50e436cb6861cd93299543402582",
INIT_1D => X"f3d31ae6d3972fbb8783b0ea8affdff9bf1e03b464ee3f9c1fece98ca74309cf",
INIT_1E => X"c8a308a0f5b3eb2bb3819d97c203892362425dc04d721669afb01c0b2e5a0ba3",
INIT_1F => X"d3b8aef2003ac8750545e82dbe9cb9125204f7e890749f6751d6e9e4eb0944d8",
INIT_20 => X"b291f0e526d45f6e6207233b3b42e6abb51b4b316b62390e40d8634db631e797",
INIT_21 => X"3c7313127e946422b286a00817b1ba6d44f420765f3bdd84119d86f314361841",
INIT_22 => X"76bc183965ae756b74716d97d571df404fc40cfb58f4ddb7cc5d743a0bc685b5",
INIT_23 => X"0c0ff2f826ea08e9e931f579213b56065e6b39a6eb01cd94be02cd245a41033c",
INIT_24 => X"d489064bfe4a0c4185cc6ba5d05b0e2e7b6abe552562cfaa66fb096f50145eb4",
INIT_25 => X"5f1bc054f46fb15a22a27d5e0b68ece1a4d628634e27a762e8c188a38342fa5d",
INIT_26 => X"1e7397fee0e56a577faed46c19b0fd44638e9a4b691a3826685c39c178ba2003",
INIT_27 => X"b9041dec02ff2c38284b806c3d8a55ac01a771d514e67bfda6b2c723a092b87f",
INIT_28 => X"3437267d1815fbc5f5400b4df45aaa7c3b6fb28532330e5dc6b891331106f0d8",
INIT_29 => X"a16463cded407200028ae693b8439a34e12321f69ab812e88f54eeb1769b368e",
INIT_2A => X"214ee0c1a52fac4cefa94b0e122ffee2a40103a65845a9e1c7f0cac8944e695d",
INIT_2B => X"1952bd1ebfe1a2934be1dfcb709809fac4b3b9464d35f8488319c04fbbb36093",
INIT_2C => X"572781ceb134ad19ea7d2384020657699d702efc313cc527a969979d26e6fca7",
INIT_2D => X"ed2b79b05ea5ed3669444aa61cd2ba400e413a56a02cc4399f549e7d642ce0b9",
INIT_2E => X"b2d1c5f5c2dc3935b09363e059c16326f5a2915fa1ed660072cc68af99c6d777",
INIT_2F => X"7e1ebef4d9252f6dc885e4aa9650d2912d00c9637f3b4d6627f39f00b912e588",
INIT_30 => X"b84becfd1988d64460a6f1d08f2dab29f05e5923b470a7059191271fa0dd53fd",
INIT_31 => X"eb42d23fea5f5901383e03d81bdab3ec5345cf937c750649130de1c199af7b20",
INIT_32 => X"a58c92d0660810751f6ac90fdac53428146f9da376d8ff23a987abe26beccaf5",
INIT_33 => X"56a84b326afe7723acb0cdd44f0f214ba14ecc5f14baf55f2231202af47ac986",
INIT_34 => X"0dc4d21a8f26a2e6f931ff19b15e0bbe9d4def02163b60b9385e69789f8fb857",
INIT_35 => X"89d8be499e6a845d6607491d60e027bc8f3c9648f91339abb831569bfbc5cfc6",
INIT_36 => X"b6d8c425d7fc9eb515a35c0bbbf5adf56571bcf764ec2448ea56402f0ad417ad",
INIT_37 => X"ddb3c6c980a2735a55c5fcd79cb8f959ccb63d25c980bbd8df648950c01c98a6",
INIT_38 => X"e9123855f177a57867efb3e651647656c5cda1067457c709a893a444b99181f7",
INIT_39 => X"ab9ff6034084d3683b50c0fb09a0a003abb1ba2f7b41ab868063f098538f5144",
INIT_3A => X"bff81d01d8e71ed1871e4024ac806f310c8e39cbf6828fbd5e7d9b377a4035a0",
INIT_3B => X"38df6a0c8248be061cdad4429397b83db65f4e9518bda97e8984df8ea4189a6c",
INIT_3C => X"b7252f70734949e06a8ec69cc4f866e57feabc835e432e39ad635779304e7272",
INIT_3D => X"4ac7e613a9e10d69d71b33670f658708214a33ef6a674b537647511f0cb53fa2",
INIT_3E => X"4b7a1bb1297177f3f2a7d027d5b64ea0891883f129116b778a307dfe52668e68",
INIT_3F => X"f74c18f7b3581cac969510f82cd2d38cb8a0a722df2a4c0a1155bb4b2a3b22bd"
)
port map (
DO => block_do(1)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"71281bbd27d34ef1be5bc97e374aab432bff29e17a32c63aa025e0eb01e6e5b6",
INIT_01 => X"d668445130edc99e8898a98304890ef22a176397b6ea1f2ed309ebe2d6ca9456",
INIT_02 => X"2fcd0fa621406e6d3171d20138271225f62d6b337ab16f076949d80923c8162d",
INIT_03 => X"cb32ff003bcf60c1a6f72c4b4169a654715ce4b1486903941377c2296976df11",
INIT_04 => X"b1c4bfb2fcad56ba46ca2a3208098bbb289e7e702e2116de17298e95bd8150c2",
INIT_05 => X"c7b99f18b3da58b1cb3fc129d443f098c427aa8080a809b5cd7412590785bb5f",
INIT_06 => X"595985dac56ca6907ba17da3ebec59643b4de6304a8e1e155d137529c4ae6ee4",
INIT_07 => X"a6528023df6110eeb7275fa05a854c18f98c0de3460b723e74c3291c6bcfd06a",
INIT_08 => X"a21a7dff8787151c9b959272830d3d8f0f2ff6523524868fbc9dad2f6baa5244",
INIT_09 => X"b7b0dd6a53d2a0f7638d4317e082185f3b30dd7826ae74c64f1809953687e2ed",
INIT_0A => X"1c7ee47db2a6253bcc125b88e551a39186b40ac7bd0643a09fa665bed11ef536",
INIT_0B => X"ded911a7e9840ef5a0d9692c367a444516286a87dabb19c7b39cebee4634bfe5",
INIT_0C => X"643b8be1ab22bb4021425e5f5fa537d93fc3d9488a610cfa6a66a1efdfad98fd",
INIT_0D => X"952324e7bdc1fbe44c903206c2f9ef0063060114b07ce5247b02d6fbdcb19ba2",
INIT_0E => X"0d36fc49bcb43e9bc8c2b43db5c4240c581ff212731d97dd755360307351d486",
INIT_0F => X"b057bf1571dca3b1496fdb7d794454aa4f8c6cd63bbb6bbfcc18976a3ac8a082",
INIT_10 => X"0b87330c2d20e6de90c303fb2e98408a3601d4de331d8fa39c72a6fdf09374fd",
INIT_11 => X"9d804bee8fe959cf40133498bc100fca854d73edb15abe935ae5e330437b2e14",
INIT_12 => X"5552a47352de03552c77b32a10c9497bed2e312212079151a49913ebd6fe9085",
INIT_13 => X"05fa679fd7d20fbfe90448617fdd93da40abe72176d24b96b999ac7a8dbd460f",
INIT_14 => X"8a05674a9645f06370b9e954a6b844d262083494f94aff32b5ae151664b96b2f",
INIT_15 => X"b67af32432be2363ba83a10a7760e437f4fddf18cc42b6ad68a6cdc41e766397",
INIT_16 => X"2f7c4e0c785eea913c25d1faba19d077e6f227bb17e17883ce6f581ac49c5e3f",
INIT_17 => X"83004e4aa4303f7f44125346e787eac5c0e096515e8c3ae7a136f7d3c5940678",
INIT_18 => X"5c32b4232edf2b4c24b42ea6b054e33030b2406a55cc8ba3efffe0e4b71c1ed5",
INIT_19 => X"857bf7d8dea4de6d910a4a2998b5793ca5bca01023a772fafc0d26f0c1dbb034",
INIT_1A => X"8c4c4a66c35962c3be637b97a024b305ed1a81bb86145e2d35dd99264d38cff2",
INIT_1B => X"063afee6905273db40cbc062738c225bcd168e3094a727275c8d4c6862408ff4",
INIT_1C => X"e7a1e0349f7d408123a3cb39673823ac63457e947a9ce5a52187fe64aaac3029",
INIT_1D => X"53b5c219c3a61fde04a8e3bce15d99f7abb105bd8c5801fd5d63d271acd8a5d8",
INIT_1E => X"b459fc58f0e95787df85afe368e8294a104f0baf1f2823165c0f0c0feb317bbe",
INIT_1F => X"36ab943b2792ebfed0b071e642f6497a5132e7542ae868a91b31c7fb77f21e97",
INIT_20 => X"ee070525b5aa12ae40f3f7c9a98ddc4428398e58bfe62146e63c3ddd3e3f9156",
INIT_21 => X"8e37d13e63f1365f54e235423c868fab3f34f3ec016ff4548bb2b35edee4cfe7",
INIT_22 => X"d01c2f93e22e655c73b5b917db9cd1827e0fd5652e24ac5fb67ec29d888b711e",
INIT_23 => X"73b0e729a2a9043fd962fc489ffdab91cbd71e11fbe8763aee9aa82572fbab9c",
INIT_24 => X"b4147972e6d6a35408d8ed692f24db6fea8dddf9f4b49691b13067b3483ccd28",
INIT_25 => X"536b5377f4e5f9a2f96a935bf6d13c2545e0e1ad0270025c36a5b6f518b42e1c",
INIT_26 => X"bd72cd801c62d33f0283ca5d0a4682e57b980180ac32b6353e01400da4e56a0c",
INIT_27 => X"c7c6d92bcd5b1e42a7050b33c19cd99a4f369e8520054cdbb29a2175c765212e",
INIT_28 => X"0d9c583d2fea3178e81c8785f07bea3afa1bd3d319459adde910420348415f99",
INIT_29 => X"f0eee03ea738365b5fed15aa7b0ed6a178029d065807d5af8a9e4575a62a52ac",
INIT_2A => X"5a0f8a425776e0507f15da504ac1d01a907a641340e428c91f6a3596b5435b24",
INIT_2B => X"00f715ed13eea243a66ad76e781e54c9c586458be04778e045f4b9521faf8706",
INIT_2C => X"1f21b590e7faf081f947b0627082207199b41de2c5bc775d97aa98e2b5c83826",
INIT_2D => X"61439aafcc286f8dc699394797658b0b5cc9aca8c5d7bdee32fe84460615cc20",
INIT_2E => X"50d2f67958a146de4b76eb179b0f7f599bdc0c094ce5c55441d30a212f7d6e1e",
INIT_2F => X"3407543e63defc345ba6e9955ceef3494fad2952255b95da82f47f42db7e029b",
INIT_30 => X"bb5664f5a21fc0375f204a559b03421b7668c01f70962e61786a145015f518f5",
INIT_31 => X"8763ab3644aa6891659cf594693bca6a9cf4b1d5b45fd1566ecd6acdc0548169",
INIT_32 => X"4aa396cca2b8f0b36d699dda61709315ee8c3cbd98dc836e5701d1c8a9db8c66",
INIT_33 => X"9c1726b695896cdcef5bf0cc500ce14358741bfd5af67b2c7e38ce3da719a9fe",
INIT_34 => X"7b839834af2e9082d3a7038e0c5af1359be31b293f3be3300934d527d605b780",
INIT_35 => X"145ae9cec90b0e17f5c4c78ee85cc6f269600a2d94bfb30d607284e26234f386",
INIT_36 => X"f07343e54761155a4baa8ec2903968fb6aae0cc4730f26305f3892c8490373ae",
INIT_37 => X"fc0a4c77a4981e3a45b4db67daef4c0482fcbba00b420684a542c721c60a6e8b",
INIT_38 => X"3a8e0aac215ac60f1735e5ab1aff54fdebe7b8d2cdcdcffc86196b99be5b1cbf",
INIT_39 => X"4d036322c63dea967971fe9f37c5904ae59681cc9742d10fe9e5118294a1e3fd",
INIT_3A => X"2a18435ee840989a96855bfbc079c31cd1ddf180311671eaaa0226b81c023810",
INIT_3B => X"67d4a7d0d521c3d64fba616098ea720284bcea3764507464ee2ac6f9c9cd531e",
INIT_3C => X"a0b0f1decff81e3e27d6914f869f4efdbc5fbd128c607e137581009bcf14a502",
INIT_3D => X"ffc8b6b84790cfc002e58bc1671d5bff199b70bbfc545ff88b812bccea0cbf10",
INIT_3E => X"6da2c4f536b3792b20da3dbd91bfd590b3683624e22926078f51a3ccaea0d2a7",
INIT_3F => X"2ff67ab570efec081549c746059d78bc48be0c7482b9d1f8e452922748c662fd"
)
port map (
DO => block_do(1)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"b51a061460ccf19cbff910a732971cfda3dbece89165feb6fd668d4582dd49e9",
INIT_01 => X"bf5ebb7b9fb12b8abc1a7fc812be9d8ba9d504772400caa28c2b24e30d6ff198",
INIT_02 => X"dbf8fbd39b0f501c6a8ce505446dc26b8f044e46e481020905edc52e6108e5ff",
INIT_03 => X"7e45a87e7e7b9016b65b3ae67b66edf07580751af9ca949245d9ba2409c3d600",
INIT_04 => X"801b2750aae36d314bdbd90a11481c64fae3797f1dfd0c0be315099a5963e969",
INIT_05 => X"c96fbde386b66dd5bdc7f9fd0133c3d19170b4f5273027e137c73d7530124805",
INIT_06 => X"50eebe7c07b42c7416a75be063c9db647d550ecc49d70be6d530436505802528",
INIT_07 => X"5b74edae517b14a02cf183f2df57ebe5836769416d1a23377862fd41d50c38dd",
INIT_08 => X"f9367802d7fa0ab0b7f552da284c1824d364810405bcf8cc249e50091f084c2d",
INIT_09 => X"2bb8f63ef774cc00b4cb3654dcefe46fb7c06325fcf9f403e0d79c280e49876b",
INIT_0A => X"231c450aae6f31a7fff73d7d39095edc6d95a18ef1643ce2ce408534f403dfec",
INIT_0B => X"b4b2274e4b879452528ddb8a6d42bd4657b2a241baf6434ba29010d047d4d900",
INIT_0C => X"cd24ef2440d6506094bf008335759dbddefc98335648fb04655f1bff047614af",
INIT_0D => X"b6140b8b887eaf3107ac9c83339f2c963b345f3476191b962211729eab0c17c1",
INIT_0E => X"04c775629ce1f634bb7b52e5cb5258d37f833abf30ee4efe19d2d32978ba4f9a",
INIT_0F => X"3cd7957cf495e145a8df3dd18f9a584f7e7def1c13a6a8908851ca93932d28c4",
INIT_10 => X"3c7162c7e069c8fe035a62afcb676cfa8e5d2a90b4b3b86cdd86738d837fa4ba",
INIT_11 => X"989dbb8dd8ceea5f490671060734a3289bf344bda058d13d12227df18097e624",
INIT_12 => X"850a34edb3289681cce0dc1c78b045b39b5fdf374dd241f35d288e13325f86d8",
INIT_13 => X"338b572a8e1ce9a0c4c4fd49af7ba00c600bbb980680527e057ca3516543d0f2",
INIT_14 => X"2e21f8f896d173d65acb0a543270f433f1a62bcd96caf4c5f132eaea31dae8e9",
INIT_15 => X"f735daf0b8ed76a13f060b4060d81879dc222765408f0bcf119425b48e4964c2",
INIT_16 => X"e218d5995ac28fa85cf3ccb31b17f06bd42863ef986056563284cc575bb771f7",
INIT_17 => X"f7655cf08c2c03b5e90f56bca10f03b0a70bfa0b8b9ef418e74208a9761ea6ef",
INIT_18 => X"d1a80b04e20decfb0fcd25fb81b370da47bde7cc5efbb8f969af30311a75e551",
INIT_19 => X"e55714435994d4b63232979b3dbe45a99790966b31cfbf4a99cd720518ccd280",
INIT_1A => X"c66eeca37ec70460340e65bcc26af2153f0605e644ed9cb113618d6499887616",
INIT_1B => X"46654c016491e01fc7d11577609fde1c99b29da69a50a52302f81d33194422e1",
INIT_1C => X"f1ccd9e356028f8efa889c56b64618032036973803e3d13a884205c2141de2a1",
INIT_1D => X"cdda04d64c93aac620d0d7748b873dc9eefcce5229d10eebaf0e25634d36f1fd",
INIT_1E => X"c66be25274389dcaea4d47de0eb87d6de650946758e900de6ba38edf4496a3d2",
INIT_1F => X"cb00f6f82259eaa5ad3904a881a41c96dcc08b9915951b3c019d6689a106dc51",
INIT_20 => X"3ca5007206cad19b1664149e909ddc9cb21eea1a553948094e69939e5fa5348c",
INIT_21 => X"e058069f0bc35d900bb1a59da4cfa45d36d3074f200458700ce8fb3872548499",
INIT_22 => X"fc67fd72a9cd5f52293af44aaceb07d479496e6b065c4c307f27c1abce9c66f7",
INIT_23 => X"1651645f90f3ebb7c5b47bef60b14862a8af62043b3342346d4295c8d9d9ae56",
INIT_24 => X"b782b5bda032a45477d2a0d9ca5f42da1ecb65185af6956ee4f3a1468d80f063",
INIT_25 => X"fc642b1dd3ff82c9046520940c6f239e33fdec5472a5adf4020d70efe8cab8e3",
INIT_26 => X"b8fb8d7a30d471b7d43dc8527176ff8391f9662a6e2d961ab65c63f6192c6b4b",
INIT_27 => X"b11f9374d4401ea348261e04aef63eb9269048abe45be3110946d175fed12f1c",
INIT_28 => X"b362eccb9b2df8049dd205868dbc822c476c8a4f1f115df3f0b97e91722e630f",
INIT_29 => X"9945f00f360cb8157375e8a6f411cf17b1552dc0352bfe8a1ae4f182e82be9de",
INIT_2A => X"3085c2a8d50592988a12fedcf893300d5ea50bbc13962239f0cc537ae121a03c",
INIT_2B => X"4d81d27828f0c8442a63e531e7c4ae2546da942ef69d783066b0f806c172c220",
INIT_2C => X"901f3fe031df56b0a4cdee9aa47d509917474fee5b84094cfce37f06b26c3f22",
INIT_2D => X"6b87f299fb8e632e7ee9fbbb4f1e6ceffa917d22fb766e4d6e89fa87b0e3bfae",
INIT_2E => X"f8bb98533bda231793d6acc170fceccd197e8a1a9ec5a55f03d1f3e36cf449a7",
INIT_2F => X"afebf4a289afa815ec0c9e35518ca312897b3545300f4360294f931df23e4915",
INIT_30 => X"74dc5c73ab8bb407ab8261b64c4b07435cd7417264802bc1feefa48488e94e51",
INIT_31 => X"2e2685b9f3d6763f8717e6fc9c4d9bcf6688df697320d1ea5241678b7f0b4d63",
INIT_32 => X"b4a74003ac874e1e8d729686a8a014df6488e64918e9830288e4216fc5e5cf9f",
INIT_33 => X"f3ec81365e8bdea20ff006703916c56bd571eca68b5c6733a64094be89a44cd9",
INIT_34 => X"8270687e28b8215aea37771ad6ab4d56a545aa616dcbb7af8216286d63086678",
INIT_35 => X"954e8634b27d70a0b2024fb77c23825f02a30ccc2dc9d15a1750cdfade812419",
INIT_36 => X"ce299793f402a139eb4661fc25b7c97c1f45d02335c2b26eb3a73754f1788eb0",
INIT_37 => X"0c9280bec83cda109edc3b2609ba75645df4fe8da692d47d199ff31d27539b64",
INIT_38 => X"69fd23927e1acf2ef95c79f5a930e847c57fb93b2148ac1bedf90ab6681db0d7",
INIT_39 => X"a2a2b4fbb44fa9e7d6415ff939f492fdf6a342b3969cfd26db57870776a2a95f",
INIT_3A => X"292a9012b2145317dc9fa147b8e971422ee56aec85d04232e5d6883b3b3e404b",
INIT_3B => X"1c216cd1ddd7c4c5595ec673265d5550cb0e8d35be8265a85567ade53d47ec2e",
INIT_3C => X"0baf5b30cda72398c774ff1b729734f25cf562c950b1816c6a735405900609f0",
INIT_3D => X"d0075edcd178d1226faaaf608494be60eceb159ad8bf9dbf27bbaed351049a1d",
INIT_3E => X"1ba5caac62a1045d1e5a5853b5a1071881ceb810241458989a541a86ce9ecdd2",
INIT_3F => X"d9d0985a7bfcd6e2a0224de71dfdc8da5ef29dfbdc767c8948adf3fa63f7749a"
)
port map (
DO => block_do(1)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"6b46bc51b4c92485956aa31735ad2910b5d766f4034eb9871b4394d10e3af66c",
INIT_01 => X"5a6f6893857f88a7c77c8def6ce4bcbe6dd5bfd1a7460221fba93d9f48cba01d",
INIT_02 => X"f205d48c73e81fa1793b4a113035ed0c5b419bbe029ff532e760a2cc4b1ab7e4",
INIT_03 => X"86715d1f80a92baa8b40c203920fca516e137f571025d581e4f39a3b77183841",
INIT_04 => X"7fe7507b1d84db5ca9425b969e483c786049a22d2151ad78eb348ce9cc912b71",
INIT_05 => X"5164405e5ad859d4f58e9de69df71d80875b45405a0563232e592432b7c3693c",
INIT_06 => X"bdc027ab9cf01e9ab7dbb660151d13a931ade9e9a6d2efb5c5416885d84227b7",
INIT_07 => X"6a7aafec4457fa2a66d36383a1b7e7caf6663ccce537aa1b54a4bde872bb56b2",
INIT_08 => X"a98c2f7dd94a4021244f0f303ca83961739ca4b54765f0cd8c6556ca4aacc9f2",
INIT_09 => X"0f199a304bc6a5d753922fe9184ee61d1d7f92a3aefb4d6434a42bc9f965fadf",
INIT_0A => X"106a31bc6de2410fb2fb2f4a0f74af7beac2779b709672409dc84c1435d5b9cf",
INIT_0B => X"1e27d0530be9b0b9a11dc821688a79d50e8606be38cb6dd8d7b801a1bca436bf",
INIT_0C => X"14caa4846a45a22d3dc8c501951686d7c0b7219b09f57e785b41c949d9ce7722",
INIT_0D => X"2387edbed5ac6031b5ad0999f4ccb1fea8654f3b5d90463643f73e3a11fa479b",
INIT_0E => X"425568aec7b1b8609f2a9115f4975d2da587359704549e7137acc0a657977f85",
INIT_0F => X"010ea2ddb3de6cb42fa79510ae8e73ef0e790c370428740ab35f2cee06554631",
INIT_10 => X"11690d02fe19fb1f669f6dd496301dabfe8535f23200803f23ef6dcb10ed4105",
INIT_11 => X"4ad13b02d70a29fea68e7d9f415245b4627e74e466ebb340c373f346765cad4b",
INIT_12 => X"cd91a18301155dbec858c423b51f797db3cea35df5203bfd6853fe0b964c95ac",
INIT_13 => X"d4a84bbef48591349a02fa2b57209787ba3c731a459e75bdeed8f141e856d89e",
INIT_14 => X"d7c952cbd9e9ad6feb9e03bbcfa88bcd373a8e60e9d605c46dfe1aac1aeb0c98",
INIT_15 => X"b1e72111d6f0a571300ab1452402ad5794691d348c4df359093e7d08ca094fce",
INIT_16 => X"f334fe9f190172b4a89f69123494134431dd350a05aa41f1d2129d65a7d59f9a",
INIT_17 => X"c50e2a3b819d0c7ef9f47dde5baf59c658c5cdac98b2458bc733f8978ec191ff",
INIT_18 => X"63e5d56f498018af571ea590389b4d4f87c36ba3162fd32e7f24f60b63055c6d",
INIT_19 => X"b79c957eb4011403044637bfa53a1755f0fc42d7caa1d9275a4ba4ef81608840",
INIT_1A => X"5137804514e9d71c90b074394a003ebc0c07367dec3cd2134a2a30976267a7fe",
INIT_1B => X"95ccfc1f82078267f21cefc0f5849b5d0a1b7cde0eeb80be500bcbddd82f1840",
INIT_1C => X"4d44791d12bb1d0848ecc0659cce58946e84ce798275f894623e2f6b0ea4b528",
INIT_1D => X"ac6dcac863ac3605a5401fb3cf45cf5189ec5e6d8ca07a9de4f51477110c100a",
INIT_1E => X"a30ca7fb9876af029b0bf274f7147b8b0d5e64e141e6bc7ced10b7ceed5c1cec",
INIT_1F => X"25e66d0fe615e739598c1709f1c06c70c99cae2640599272b9a68026d5867fde",
INIT_20 => X"4b2d5e4302d194613add05e66a1a83b98fc403532149d8d13a0d8daf25d34c7f",
INIT_21 => X"e2107356dd37ce4837c1f4efe46d8f0e1be1f30794a9ff9e60f351d5ad7874ca",
INIT_22 => X"9eada3b89394801f146f959e39590def2d649cff620f51ecdd177fbdceada41e",
INIT_23 => X"41b200c1baff27509cebe347221d8c7673ef2d2a7b596854f61bda2b128738a2",
INIT_24 => X"8364ffc4d097099e699f9997d824abb8b550a9dbdd383ab56f411545846c261e",
INIT_25 => X"909857d592fb12fcc6c900acc655d973fc95c17ce2e932d9f9becd061d5e4090",
INIT_26 => X"5749181de28072b8b9085e4a5326cae5a455eb00aaaa1a37a33977374060dd90",
INIT_27 => X"6028626be13e48f3e0bdcde212a1ff71655bf8ed85683d85da23f992c22b743f",
INIT_28 => X"d6525802be4bbe82f97195327e327c5ab49a9af27168380752e90953742136a0",
INIT_29 => X"8f5941443e8e62349c9f48c0837ccbcbafaaa2b044049abc172d912daf4327f7",
INIT_2A => X"2a1bbcbb892134a7defaba8057855deb9e54012123cf0256c59583caedd632c6",
INIT_2B => X"c0da73587a828a1e4b1d62317074784c8c9f9b6b89d05726443967faffd2c82a",
INIT_2C => X"924e4404dcb53d70a4480c0964d53ad1db1dd9daa98a4b39ed3e4c8d36b04554",
INIT_2D => X"4ef67878d0346483876b461bab912028e9cbc97a67a4e822807d8db6773da23f",
INIT_2E => X"2b915564aa92c310ca2deaa531aed609fb6d4ce694917cb160d0ba68c40684ec",
INIT_2F => X"50a4eb8d30228ff1816c89dc31cec751487a241cd4ed7bc8d2cab8c7959daacf",
INIT_30 => X"71db5d623e30cd8d81c2c0b05357108e5ef426c4d4923f749f70f7fe8b74e427",
INIT_31 => X"cd482af6801df037f26361d3088abf1e5d6d2b195473762e04c9ed0aaa1d6cfd",
INIT_32 => X"b88458df758890f0d7f4db32383cf17af2c4204412c718bf9237649e70f5a151",
INIT_33 => X"5a7e2ab186c6d26b876e041f49885d027266a0f0c31ee46eeb3ca644f30a6edd",
INIT_34 => X"b83317cb58cfbeb6d70dc2e281c73b5264b84065f178b97510c582c6d1088d7d",
INIT_35 => X"4c522ed438a2d6a8d227006d3e28265ce686b02cf3623cf0f5578965c200e06c",
INIT_36 => X"6fae935325886971daedfb2201b1ffdd5d201e5cddf03b6d50878d11915b0bdb",
INIT_37 => X"0ece745f38297c4b3880a9a210120ef088ab134e274de5ba9c12cb54ccfec458",
INIT_38 => X"8bf593d92d93dce7316bc48598125808a6b4dd19447394a453b04d99c2f7ae48",
INIT_39 => X"4d48b9480981d84b80e784484725ebc894bb5aa1eef26aaff528b77a4cfdfc8e",
INIT_3A => X"34143cdac0c9b0087005fde632e01e09ee3e839538382894999f291ba170d5dd",
INIT_3B => X"d62b8cbf582826c41f508b5ee33bcfd7da144fa8ae5da486c45c7e25c81397ed",
INIT_3C => X"adae3e8c0baa9fa5e906d0863b1e11626224e63430533438574f5631753decd9",
INIT_3D => X"c7cf54b74bcb1461de174292e9450bd8ab106bed322ef1a9c053a27b5b45afee",
INIT_3E => X"32775d6cd75c5446e2cc0e348b8330861035ec99e26d975e11a6b13a6139c55a",
INIT_3F => X"b2c2737c636fc2e741ab9897c5c182aabb791646ae08ab5d7db2028583f3bd42"
)
port map (
DO => block_do(1)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block1
block2: if (block_count > 2) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"fe0d65c9ec58f9eb0192f7b6dff76e568644945f5b045287ebcf0eb59bc8a2ab",
INIT_01 => X"8c0ea4a0c5d807620b9d6df735378c90506b24de194d7008fd94b351b9778315",
INIT_02 => X"3bd7054b92b0b392040879de38525d82d092dc23f93073690861e2c48a5fa6c9",
INIT_03 => X"f554ddb1f0f16dd14d870e5245e969673b7b940a9f69081a07b49e8eb77f3b4d",
INIT_04 => X"e3de03944683e2b051f85357f83167a6a56051966972207cf714d9cdf07fa38e",
INIT_05 => X"0000000000005faf5886072567248bc9d6759a72c812942ae2c1667522a3aaf2",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"a4b3ac91c3c4ea9e3c73fab0ce0e4ab7a1d3e0f996b70c445c4147d1cf68346d",
INIT_01 => X"874c100eb9e6002379dd09194bbafe8ad8abf7bbb102552f9860ab6e10088922",
INIT_02 => X"0f5ec4e6bc67e9227025f9a05cc73e1aaaef0d88f6451f6f94d628aa2c94684a",
INIT_03 => X"f70b88ca6e87bf7233be058db2d120a327564751238bcccdc141ce07bab72681",
INIT_04 => X"57abdb2c94c3e57f8f5eb8368f84e31ec0170f06df25e28084734e3ba7f109fd",
INIT_05 => X"000000000000d583c2c59b05ebb2fa2c70aa9afb332bc3a6819ea545a9c4d965",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"64ec0e81b855f05319e385eeac0a1f28f08cac74fc05e0087ba44bacc0ce7eca",
INIT_01 => X"9ef40beab720af7ba66a8be8894607d48023ec7f165d60f77fb4e3b12d630c6c",
INIT_02 => X"59d6de6ed3adc2777182401a17e7e1775c68319ed038420fc3ed62f756db0119",
INIT_03 => X"bb182d84fb0c3a55a21506e47720e776c8cfe1a4b59bcbbb46a396315e73a098",
INIT_04 => X"84a9f497194c2272744b6bd1fe582648ef47ea4723116e65e52654fed2e8785f",
INIT_05 => X"000000000000c1edb1eae6ce99ae6c81687d51cca6dbaec572b86d76faa3234b",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"6a4d64a3bd805648b756f216df1a1fd5400fef106d7c33484a5d1a96af390aa7",
INIT_01 => X"d6e8b9b0a1b125ce0ca17af6280f9262cd9b6e5d9318f382ffe7e10ab95831ee",
INIT_02 => X"786ed5c9efe0688f948e7684716aae133994d40654d85594f9a18835aeb40485",
INIT_03 => X"aeaf20b5d8e2fdff8bc7cf80d8da5a4ed756afe7718834ab643e2db35783484d",
INIT_04 => X"c99c43a4c9c4a572de3caaddbf8a10c914071267ef510743e581f9ac7fbbce17",
INIT_05 => X"000000000000ae856b1ca490f7a3f04910f1a60e575769661e34a362fb68ea3a",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block2
block3: if (block_count > 3) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block3
block4: if (block_count > 4) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block4
block5: if (block_count > 5) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block5
block6: if (block_count > 6) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block6
block7: if (block_count > 7) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block7
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 8)
--
-----------------------------------------------------------------------------
block8: if (block_count > 8) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000c080400",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(8)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(8),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000d090501",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(8)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(8),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000e0a0602",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(8)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(8),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000f0b0703",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(8)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(8),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block0
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 9)
--
-----------------------------------------------------------------------------
block9: if (block_count > 9) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(9)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(9),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(9)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(9),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(9)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(9),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(9)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(9),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block1
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 10)
--
-----------------------------------------------------------------------------
block10: if (block_count > 10) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(10)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(10),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(10)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(10),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(10)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(10),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(10)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(10),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block2
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 11)
--
-----------------------------------------------------------------------------
block11: if (block_count > 11) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(11)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(11),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(11)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(11),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(11)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(11),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(11)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(11),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block3
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 12)
--
-----------------------------------------------------------------------------
block12: if (block_count > 12) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(12)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(12),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(12)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(12),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(12)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(12),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(12)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(12),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block4
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 8)
--
-----------------------------------------------------------------------------
block13: if (block_count > 13) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(13)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(13),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(13)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(13),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(13)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(13),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(13)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(13),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block5
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 8)
--
-----------------------------------------------------------------------------
block14: if (block_count > 14) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(14)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(14),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(14)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(14),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(14)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(14),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(14)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(14),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block6
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 15)
--
-----------------------------------------------------------------------------
block15: if (block_count > 15) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(15)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(15),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(15)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(15),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(15)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(15),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(15)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(15),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block7
end; --architecture logic
| gpl-3.0 | dcc3888eaff4909bcd00004bd56fcb73 | 0.839029 | 5.275946 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/dist_mem_gen_v7_2/simulation/dist_mem_gen_v7_2_tb_synth.vhd | 1 | 7,270 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: dist_mem_gen_v7_2_tb_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.dist_mem_gen_v7_2_TB_PKG.ALL;
ENTITY dist_mem_gen_v7_2_tb_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 0
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END dist_mem_gen_v7_2_tb_synth;
ARCHITECTURE dist_mem_gen_v7_2_synth_ARCH OF dist_mem_gen_v7_2_tb_synth IS
COMPONENT dist_mem_gen_v7_2_exdes
PORT (
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
A : IN STD_LOGIC_VECTOR(14-1-(4*0*boolean'pos(14>4)) downto 0)
:= (OTHERS => '0')
);
END COMPONENT;
CONSTANT STIM_CNT : INTEGER := if_then_else(C_ROM_SYNTH = 0, 8, 22);
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i : STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ADDR: STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDR_R: STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL SPO: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL SPO_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
dist_mem_gen_v7_2_TB_STIM_GEN_INST:ENTITY work.dist_mem_gen_v7_2_TB_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
A => ADDR,
DATA_IN => SPO_R,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(STIM_CNT);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDR(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW + 1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
SPO_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
SPO_R <= SPO AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDR_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDR_R <= ADDR AFTER 50 ns;
END IF;
END IF;
END PROCESS;
DMG_PORT: dist_mem_gen_v7_2_exdes PORT MAP (
SPO => SPO,
A => ADDR_R
);
END ARCHITECTURE;
| mit | 41a0afe33324f92c6fe9f6ec4d335802 | 0.558735 | 3.656942 | false | false | false | false |
chibby0ne/vhdl-book | Chapter7/exercise7_10_dir/exercise7_10.vhd | 1 | 1,056 | --!
--! @file: exercise7_9.vhd
--! @brief: frequency divider with signal
--! @author: Antonio Gutierrez
--! @date: 2013-10-29
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity freq_divider is
generic (M: integer := 4;);
port (
clkin: in std_logic;
clkout: out std_logic);
end entity freq_divider;
--------------------------------------
architecture circuit of freq_divider is
signal counter: integer range 0 to M := 0;;
begin
proc: process (clk)
begin
if (clk'event and clk = '1') then
counter <= counter + 1;
if (counter = M/2) then
clkout <= '1';
elsif (counter = M) then
counter <= 0;
clkout <= '0';
end if;
end if;
end process proc;
end architecture circuit;
--------------------------------------
-- question: by which integer value wil the clock frequency be divided?
-- answer: by M + 1
| gpl-3.0 | b52832190253b075a047690674a4a872 | 0.485795 | 4.292683 | false | false | false | false |
muhd7rosli/mblite-vivado | mblite_ip/src/vhdl/core/core.vhd | 1 | 6,115 | ----------------------------------------------------------------------------------------------
-- This file is part of mblite_ip.
--
-- mblite_ip is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- mblite_ip is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with mblite_ip. If not, see <http://www.gnu.org/licenses/>.
-- Input file : core.vhd
-- Design name : core
-- Author : Muhammad Bin Rosli
-- Company :
-- :
-- :
--
-- Description : Top level entity of the processor modified
-- : for Vivado IP Packager
--
-- Date : 01 November 2015
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library mblite;
use mblite.config_pkg.all;
use mblite.core_pkg.all;
entity core is generic
(
CFG_IMEM_WIDTH : integer := 32;
CFG_IMEM_SIZE : integer := 16;
CFG_DMEM_WIDTH : integer := 32;
CFG_DMEM_SIZE : integer := 32;
G_INTERRUPT : boolean := true;
G_USE_HW_MUL : boolean := true;
G_USE_BARREL : boolean := true;
G_DEBUG : boolean := true
);
port
(
-- instruction memory interface
imem_dat_i : in std_logic_vector(CFG_IMEM_WIDTH - 1 downto 0);
imem_adr_o : out std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
imem_ena_o : out std_logic;
-- data memory interfa
dmem_dat_i : in std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
dmem_ena_i : in std_logic;
dmem_dat_o : out std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
dmem_adr_o : out std_logic_vector(CFG_DMEM_SIZE - 1 downto 0);
dmem_sel_o : out std_logic_vector(3 downto 0);
dmem_we_o : out std_logic;
dmem_ena_o : out std_logic;
int_i : in std_logic;
rst_i : in std_logic;
clk_i : in std_logic
);
end core;
architecture arch of core is
signal imem_o : imem_out_type;
signal dmem_o : dmem_out_type;
signal imem_i : imem_in_type;
signal dmem_i : dmem_in_type;
signal fetch_i : fetch_in_type;
signal fetch_o : fetch_out_type;
signal decode_i : decode_in_type;
signal decode_o : decode_out_type;
signal gprf_o : gprf_out_type;
signal exec_i : execute_in_type;
signal exec_o : execute_out_type;
signal mem_i : mem_in_type;
signal mem_o : mem_out_type;
signal ena_i : std_logic;
begin
-- connecting the entity port
imem_i.dat_i <= imem_dat_i;
imem_adr_o <= imem_o.adr_o;
imem_ena_o <= imem_o.ena_o;
dmem_i.dat_i <= dmem_dat_i;
dmem_i.ena_i <= dmem_ena_i;
dmem_dat_o <= dmem_o.dat_o;
dmem_adr_o <= dmem_o.adr_o;
dmem_sel_o <= dmem_o.sel_o;
dmem_we_o <= dmem_o.we_o;
dmem_ena_o <= dmem_o.ena_o;
ena_i <= dmem_i.ena_i;
fetch_i.hazard <= decode_o.hazard;
fetch_i.branch <= exec_o.branch;
fetch_i.branch_target <= exec_o.alu_result(CFG_IMEM_SIZE - 1 downto 0);
fetch0 : fetch port map
(
fetch_o => fetch_o,
imem_o => imem_o,
fetch_i => fetch_i,
rst_i => rst_i,
ena_i => ena_i,
clk_i => clk_i
);
decode_i.program_counter <= fetch_o.program_counter;
decode_i.instruction <= imem_i.dat_i;
decode_i.ctrl_wrb <= mem_o.ctrl_wrb;
decode_i.ctrl_mem_wrb <= mem_o.ctrl_mem_wrb;
decode_i.mem_result <= dmem_i.dat_i;
decode_i.alu_result <= mem_o.alu_result;
decode_i.interrupt <= int_i;
decode_i.flush_id <= exec_o.flush_id;
decode0: decode generic map
(
G_INTERRUPT => G_INTERRUPT,
G_USE_HW_MUL => G_USE_HW_MUL,
G_USE_BARREL => G_USE_BARREL,
G_DEBUG => G_DEBUG
)
port map
(
decode_o => decode_o,
decode_i => decode_i,
gprf_o => gprf_o,
ena_i => ena_i,
rst_i => rst_i,
clk_i => clk_i
);
exec_i.fwd_dec <= decode_o.fwd_dec;
exec_i.fwd_dec_result <= decode_o.fwd_dec_result;
exec_i.dat_a <= gprf_o.dat_a_o;
exec_i.dat_b <= gprf_o.dat_b_o;
exec_i.dat_d <= gprf_o.dat_d_o;
exec_i.reg_a <= decode_o.reg_a;
exec_i.reg_b <= decode_o.reg_b;
exec_i.imm <= decode_o.imm;
exec_i.program_counter <= decode_o.program_counter;
exec_i.ctrl_wrb <= decode_o.ctrl_wrb;
exec_i.ctrl_mem <= decode_o.ctrl_mem;
exec_i.ctrl_ex <= decode_o.ctrl_ex;
exec_i.fwd_mem <= mem_o.ctrl_wrb;
exec_i.mem_result <= dmem_i.dat_i;
exec_i.alu_result <= mem_o.alu_result;
exec_i.ctrl_mem_wrb <= mem_o.ctrl_mem_wrb;
execute0 : execute generic map
(
G_USE_HW_MUL => G_USE_HW_MUL,
G_USE_BARREL => G_USE_BARREL
)
port map
(
exec_o => exec_o,
exec_i => exec_i,
ena_i => ena_i,
rst_i => rst_i,
clk_i => clk_i
);
mem_i.alu_result <= exec_o.alu_result;
mem_i.program_counter <= exec_o.program_counter;
mem_i.branch <= exec_o.branch;
mem_i.dat_d <= exec_o.dat_d;
mem_i.ctrl_wrb <= exec_o.ctrl_wrb;
mem_i.ctrl_mem <= exec_o.ctrl_mem;
mem_i.mem_result <= dmem_i.dat_i;
mem0 : mem port map
(
mem_o => mem_o,
dmem_o => dmem_o,
mem_i => mem_i,
ena_i => ena_i,
rst_i => rst_i,
clk_i => clk_i
);
end arch;
| lgpl-3.0 | bbb37eee6676e03636de0bdf3644568b | 0.525429 | 3.119898 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/custom/mandelbrot/coproc_4.vhd | 1 | 4,817 | ---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity coproc_4 is
port(
clock : in std_logic;
clock_vga : in std_logic;
reset : in std_logic;
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_1_valid : in std_logic;
OUTPUT_1 : out std_logic_vector(31 downto 0);
VGA_hs : out std_logic; -- horisontal vga syncr.
VGA_vs : out std_logic; -- vertical vga syncr.
VGA_red : out std_logic_vector(3 downto 0); -- red output
VGA_green : out std_logic_vector(3 downto 0); -- green output
VGA_blue : out std_logic_vector(3 downto 0) -- blue output
);
end; --comb_alu_1
architecture logic of coproc_4 is
component VGA_bitmap_640x480 is
generic(bit_per_pixel : integer range 1 to 12:=1; -- number of bits per pixel
grayscale : boolean := false); -- should data be displayed in grayscale
port(clk : in std_logic;
clk_VGA : in std_logic;
reset : in std_logic;
VGA_hs : out std_logic; -- horisontal vga syncr.
VGA_vs : out std_logic; -- vertical vga syncr.
VGA_red : out std_logic_vector(3 downto 0); -- red output
VGA_green : out std_logic_vector(3 downto 0); -- green output
VGA_blue : out std_logic_vector(3 downto 0); -- blue output
ADDR : in std_logic_vector(18 downto 0);
data_in : in std_logic_vector(bit_per_pixel - 1 downto 0);
data_write : in std_logic;
data_out : out std_logic_vector(bit_per_pixel - 1 downto 0));
end component;
SIGNAL mem : UNSIGNED(31 downto 0);
signal tmp_addr : std_logic_vector(18 downto 0);
signal pixel, tmp_out : std_logic_vector(7 downto 0);
signal data_write : std_logic;
signal counter : integer range 0 to 307199:= 0;
begin
--tmp_addr <= INPUT_1(31 downto 13);
--pixel <= INPUT_1(7 downto 0);
--
process (clock)
begin
IF clock'event AND clock = '1' THEN
IF reset = '1' THEN
counter <= 0;
ELSE
IF INPUT_1_valid = '1' THEN
IF counter < 307199 THEN
counter <= counter + 1;
ELSE
counter <= 0;
END IF;
END IF;
END IF;
END IF;
end process;
--
--
-- process (clock, reset)
-- begin
-- IF clock'event AND clock = '1' THEN
-- IF reset = '1' THEN
-- tmp_addr <= (others => '1');
-- pixel <= (others => '0');
-- data_write <= '0';
-- ELSE
-- IF INPUT_1_valid = '1' THEN
-- tmp_addr <= INPUT_1(31 downto 13);
-- pixel <= INPUT_1(7 downto 0);
-- data_write <= '1';
-- else
-- data_write <= '0';
-- END IF;
-- END IF;
-- END IF;
-- end process;
--
tmp_addr <= std_logic_vector(to_signed(counter, 19));
--
vga : VGA_bitmap_640x480 generic map(8, false) -- should data be displayed in grayscale
port map(
clk => clock,
clk_vga => clock_vga,
reset => reset,
VGA_hs => VGA_hs,
VGA_vs => VGA_vs,
VGA_red => VGA_red,
VGA_green => VGA_green,
VGA_blue => VGA_blue,
ADDR => tmp_addr,
data_in => INPUT_1(7 downto 0),
data_write => INPUT_1_valid,
data_out => tmp_out);
OUTPUT_1 <= "0000000000000"&tmp_addr;
-- process (clock)
-- begin
-- IF clock'event AND clock = '1' THEN
-- IF reset = '1' THEN
-- mem <= TO_UNSIGNED( 0, 32);
-- ELSE
-- IF INPUT_1_valid = '1' THEN
---- assert INPUT_1_valid /= '1' severity failure;
-- mem <= UNSIGNED(INPUT_1) + TO_UNSIGNED( 3, 32);
-- ELSE
-- mem <= mem;
-- END IF;
-- END IF;
-- END IF;
-- end process;
-------------------------------------------------------------------------
-- OUTPUT_1 <= STD_LOGIC_VECTOR( mem );
-------------------------------------------------------------------------
-- process (clock, reset)
-- begin
-- IF clock'event AND clock = '1' THEN
-- IF reset = '1' THEN
-- mem <= TO_UNSIGNED( 0, 32);
-- ELSE
-- IF INPUT_1_valid = '1' THEN
-- mem <= UNSIGNED(INPUT_1) + TO_UNSIGNED( 4, 32);
-- ELSE
-- mem <= mem;
-- END IF;
-- END IF;
-- END IF;
-- end process;
-- -------------------------------------------------------------------------
--
-- OUTPUT_1 <= STD_LOGIC_VECTOR( mem );
end; --architecture logic
| gpl-3.0 | 3a32c04446bbad7850aba009413bc914 | 0.518995 | 3.150425 | false | false | false | false |
chibby0ne/vhdl-book | Chapter2/multiplexer_4x8_dir/multiplexer_4x8.vhd | 1 | 904 | ------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------
entity multiplexer_4x8 is
generic (
N: natural := 8; -- bits in in/out signals
M: natural := 2); -- bits in select
port (
mux_inp0: in std_logic_vector(N-1 downto 0);
mux_inp1: in std_logic_vector(N-1 downto 0);
mux_inp2: in std_logic_vector(N-1 downto 0);
mux_inp3: in std_logic_vector(N-1 downto 0);
selec: in std_logic_vector(M-1 downto 0);
mux_outp: out std_logic_vector(N-1 downto 0);
);
end entity;
------------------------------
architecture circuit of multiplexer_4x8 is
--signals and declarations
begin
mux_outp <= mux_inp0 when selec = "00" else
mux_inp1 when selec = "01" else
mux_inp2 when selec = "10" else
mux_inp3
end architecture;
------------------------------
| gpl-3.0 | 6d2f5a818adb5ed41e6fccab53b39bce | 0.52323 | 3.674797 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/tbench.vhd | 1 | 6,665 | ---------------------------------------------------------------------
-- TITLE: Test Bench
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 4/21/01
-- FILENAME: tbench.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity provides a test bench for testing the Plasma CPU core.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
use ieee.std_logic_unsigned.all;
entity tbench is
end; --entity tbench
architecture logic of tbench is
constant memory_type : string :=
-- "TRI_PORT_X";
"DUAL_PORT_";
-- "ALTERA_LPM";
-- "XILINX_16X";
constant log_file : string :=
-- "UNUSED";
"output.txt";
signal clk : std_logic := '1';
signal reset : std_logic := '1';
signal interrupt : std_logic := '0';
--signal mem_write : std_logic;
signal address : std_logic_vector(31 downto 2);
signal data_write : std_logic_vector(31 downto 0);
signal data_read : std_logic_vector(31 downto 0);
signal pause1 : std_logic := '0';
signal pause2 : std_logic := '0';
signal pause : std_logic;
signal no_ddr_start: std_logic;
signal no_ddr_stop : std_logic;
signal byte_we : std_logic_vector(3 downto 0);
signal uart_write : std_logic;
signal gpioA_in : std_logic_vector(31 downto 0) := (others => '0');
--
-- SIGNAUX PERMETTANT D'INTERCONNECTER LE PROCESSEUR AVEC LE BUS PCIe
-- EN SIMULATION CES DERNIERS SONT CABLES A LA MASSE (PAS DE PCIe)
--
signal fifo_1_out_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_1_compteur : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_2_compteur : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_2_in_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal fifo_1_read_en : STD_LOGIC;
signal fifo_1_empty : STD_LOGIC;
signal fifo_2_write_en : STD_LOGIC;
signal fifo_2_full : STD_LOGIC;
signal fifo_1_full : STD_LOGIC;
signal fifo_1_valid : STD_LOGIC;
signal fifo_2_empty : STD_LOGIC;
signal fifo_2_valid : STD_LOGIC;
--
-- Fin de gestion du PCIe
--
COMPONENT PCIE_IN is
PORT(
clk : IN std_logic;
fifo_out_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
fifo_compteur : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
fifo_read_en : IN std_logic;
fifo_full : OUT std_logic;
fifo_empty : OUT std_logic;
fifo_valid : OUT std_logic
);
END COMPONENT;
COMPONENT PCIE_OUT is
PORT(
clk : IN std_logic;
fifo_in_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
fifo_compteur : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
fifo_write_en : IN std_logic;
fifo_full : OUT std_logic;
fifo_valid : OUT std_logic
);
END COMPONENT;
begin --architecture
--Uncomment the line below to test interrupts
interrupt <= '1' after 20 us when interrupt = '0' else '0' after 445 ns;
pcie_i: PCIE_IN
port map (
clk => clk,
fifo_out_data => fifo_1_out_data,
fifo_compteur => fifo_1_compteur,
fifo_read_en => fifo_1_read_en,
fifo_empty => fifo_1_empty,
fifo_full => fifo_1_full,
fifo_valid => fifo_1_valid
);
pcie_o: PCIE_OUT
port map (
clk => clk,
fifo_in_data => fifo_2_in_data,
fifo_compteur => fifo_2_compteur,
fifo_write_en => fifo_2_write_en,
fifo_full => fifo_2_full,
fifo_valid => fifo_2_valid
);
clk <= not clk after 50 ns;
reset <= '0' after 500 ns;
pause1 <= '1' after 700 ns when pause1 = '0' else '0' after 200 ns;
pause2 <= '1' after 300 ns when pause2 = '0' else '0' after 200 ns;
pause <= pause1 or pause2;
-- gpioA_in(20) <= not gpioA_in(20) after 200 ns; --E_RX_CLK
-- gpioA_in(19) <= not gpioA_in(19) after 20 us; --E_RX_DV
-- gpioA_in(18 downto 15) <= gpioA_in(18 downto 15) + 1 after 400 ns; --E_RX_RXD
-- gpioA_in(14) <= not gpioA_in(14) after 200 ns; --E_TX_CLK
gpioA_in(7 downto 0) <= "00000010";
u1_plasma: plasma
generic map (memory_type => memory_type,
ethernet => '1',
eUart => '1',
use_cache => '0',
log_file => log_file)
PORT MAP (
clk => clk,
reset => reset,
uart_read => uart_write,
uart_write => uart_write,
address => address,
byte_we => byte_we,
data_write => data_write,
data_read => data_read,
--mem_pause_in => pause,
-- BLG START
fifo_1_out_data => fifo_1_out_data,
fifo_1_read_en => fifo_1_read_en,
fifo_1_empty => fifo_1_empty,
fifo_2_in_data => fifo_2_in_data,
fifo_1_write_en => fifo_2_write_en,
fifo_2_full => fifo_2_full,
fifo_1_full => fifo_1_full,
fifo_1_valid => fifo_1_valid,
fifo_2_empty => fifo_2_empty,
fifo_2_valid => fifo_2_valid,
fifo_1_compteur => fifo_1_compteur,
fifo_2_compteur => fifo_2_compteur,
-- BLG END
--no_ddr_start => no_ddr_start,
--no_ddr_stop => no_ddr_stop,
gpio0_out => open,
gpioA_in => gpioA_in);
dram_proc: process(clk, address, byte_we, data_write, pause)
constant ADDRESS_WIDTH : natural := 16;
type storage_array is
array(natural range 0 to (2 ** ADDRESS_WIDTH) / 4 - 1) of
std_logic_vector(31 downto 0);
variable storage : storage_array;
variable data : std_logic_vector(31 downto 0);
variable index : natural := 0;
begin
index := conv_integer(address(ADDRESS_WIDTH-1 downto 2));
data := storage(index);
if byte_we(0) = '1' then
data( 7 downto 0) := data_write(7 downto 0);
end if;
if byte_we(1) = '1' then
data(15 downto 8) := data_write(15 downto 8);
end if;
if byte_we(2) = '1' then
data(23 downto 16) := data_write(23 downto 16);
end if;
if byte_we(3) = '1' then
data(31 downto 24) := data_write(31 downto 24);
end if;
if rising_edge(clk) then
if address(30 downto 28) = "001" and byte_we /= "0000" then
storage(index) := data;
end if;
end if;
if pause = '0' then
data_read <= data;
end if;
end process;
end; --architecture logic
| gpl-3.0 | ab28e7fc10fc2138cda7dec57ef3cc14 | 0.548987 | 3.198177 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/OTHERS/DIVIDER_AND_MODULUS_2x_32b.vhd | 1 | 3,823 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
entity DIVIDER_AND_MODULUS_2x_32b is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
start : in STD_LOGIC;
flush : in std_logic;
holdn : in std_ulogic;
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
FONCTION : in STD_LOGIC_VECTOR(1 downto 0);
ready : out std_logic;
nready : out std_logic;
icc : out std_logic_vector(3 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END DIVIDER_AND_MODULUS_2x_32b;
architecture behav of DIVIDER_AND_MODULUS_2x_32b is
constant SIZE : INTEGER := 32;
signal buf : STD_LOGIC_VECTOR((2 * SIZE - 1) downto 0);
signal dbuf : STD_LOGIC_VECTOR((SIZE - 1) downto 0);
signal sm : INTEGER range 0 to SIZE;
signal fFunction : std_logic;
alias buf1 is buf((2 * SIZE - 1) downto SIZE);
alias buf2 is buf((SIZE - 1) downto 0);
BEGIN
ICC <= "0000";
-------------------------------------------------------------------------
process(rst, clk)
variable sready, snready : std_logic;
variable tbuf : STD_LOGIC_VECTOR((2*SIZE - 1) downto 0);
variable xx1 : std_logic;
variable xx2 : std_logic;
variable yy : STD_LOGIC_VECTOR((2 * SIZE - 1) downto 0);
begin
sready := '0';
snready := '0';
-- Si l'on recoit une demande de reset alors on reinitialise
if rst = '0' then
OUTPUT_1 <= (others => '0');
sm <= 0;
ready <= '0';
ready <= sready;
nready <= snready;
fFunction <= '0';
-- En cas de front montant de l'horloge alors on calcule
elsif rising_edge(clk) then
-- Si Flush alors on reset le composant
if (flush = '1') then
sm <= 0;
-- Si le signal de maintient est actif alors on gel l'execution
elsif (holdn = '0') then
sm <= sm;
-- Sinon on déroule l'execution de la division
else
case sm is
-- Etat d'attente du signal start
when 0 =>
if( fFunction = '1' ) then
OUTPUT_1 <= buf2; -- ON RETOURNE LE RESULTAT DE LA DIVISION
else
OUTPUT_1 <= buf1; -- ON RETOURNE LE RESTE DE LA DIVISION (MODULO)
end if;
if start = '1' then
buf1 <= (others => '0');
buf2 <= INPUT_1;
dbuf <= INPUT_2;
sm <= sm + 1; -- le calcul est en cours
fFunction <= FONCTION(0);
else
sm <= sm;
end if;
when others =>
sready := '1'; -- le calcul est en cours
sm <= 0;
-- ON TRAITE LE PREMIER BIT DE L'ITERATION
if buf((2 * SIZE - 2) downto (SIZE - 1)) >= dbuf then
tbuf((2 * SIZE - 1) downto SIZE) := '0' & (buf((2 * SIZE - 3) downto (SIZE - 1)) - dbuf((SIZE - 2) downto 0));
tbuf((SIZE - 1) downto 0) := buf2((SIZE - 2) downto 0) & '1'; -- ON POUSSE LE RESULTAT
else
tbuf := buf((2 * SIZE - 2) downto 0) & '0';
end if;
-- ON TRAITE LE SECOND BIT DE L'ITERATION
if tbuf((2 * SIZE - 2) downto (SIZE - 1)) >= dbuf then
buf1 <= '0' & (tbuf((2 * SIZE - 3) downto (SIZE - 1)) - dbuf((SIZE - 2) downto 0));
buf2 <= tbuf((SIZE - 2) downto 0) & '1';
else
buf <= tbuf((2 * SIZE - 2) downto 0) & '0';
end if;
-- EN FONCTION DE LA VALEUR DU COMPTEUR ON CHOISI NOTRE DESTIN
if sm /= 16 then
sm <= sm + 1;
snready := '0'; -- le resultat n'est pas disponible
else
snready := '1'; -- le resultat du calcul est disponible
sm <= 0;
end if;
end case;
-- On transmet les signaux au systeme
ready <= sready;
nready <= snready;
end if; -- clock
end if; -- reset
end process;
end behav;
| gpl-3.0 | 05a879044a4bd5a2b3c53968ca8835e3 | 0.537013 | 3.083065 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/TRIGO/SINUS_32b.vhd | 1 | 30,117 | -------------------------------------------------------------------------------
-- --
-- Simple Cordic --
-- Copyright (C) 1999 HT-LAB --
-- --
-- Contact/Feedback : http://www.ht-lab.com/feedback.htm --
-- Web: http://www.ht-lab.com --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-- Cordic Top --
-- --
-- Simple SIN/COS Cordic example --
-- 32 bits fixed format Sign,2^0, 2^-1,2^-2 etc. --
-- angle input +/-0.5phi --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity SINUS_32b is
port(clk : in std_logic;
reset : in std_logic; -- Active low reset
angle : in std_logic_vector(31 downto 0); -- input radian
sin : out std_logic_vector(31 downto 0); -- THIS OUTPUT ¨PROVIDES THE SINUS RESULT
cos : out std_logic_vector(31 downto 0);
start : in std_logic;
done : out std_logic);
end SINUS_32b;
architecture synthesis of SINUS_32b is
constant xinit_c : std_logic_vector(31 downto 0):=X"26dd3b44";
constant yinit_c : std_logic_vector(31 downto 0):=X"00000000";
component addsub is
port(abus : in std_logic_vector(31 downto 0);
bbus : in std_logic_vector(31 downto 0);
obus : out std_logic_vector(31 downto 0);
as : in std_logic); --add=1, subtract=0
end component;
component shiftn is
port(ibus : in std_logic_vector(31 downto 0);
obus : out std_logic_vector(31 downto 0);
n : in std_logic_vector(4 downto 0)); --shift by n
end component;
component atan32 is --ARCTAN(x) lut
port (ZA : in Std_Logic_Vector(4 downto 0);
ZData : out Std_Logic_Vector(31 downto 0));
end component;
component fsm is
port(clk : in std_logic;
reset : in std_logic; -- Active low reset
start : in std_logic;
cnt : in std_logic_vector(4 downto 0);
init : out std_logic;
load : out std_logic;
done : out std_logic);
end component;
signal cnt_s : std_logic_vector(4 downto 0); -- bit counter, 2^5
signal newx_s : std_logic_vector(31 downto 0);
signal newy_s : std_logic_vector(31 downto 0);
signal newz_s : std_logic_vector(31 downto 0);
signal xreg_s : std_logic_vector(31 downto 0);
signal yreg_s : std_logic_vector(31 downto 0);
signal zreg_s : std_logic_vector(31 downto 0);
signal sxreg_s: std_logic_vector(31 downto 0);
signal syreg_s: std_logic_vector(31 downto 0);
signal atan_s : std_logic_vector(31 downto 0); -- arctan LUT
signal init_s : std_logic;
signal load_s : std_logic;
signal as_s : std_logic;
signal nas_s : std_logic;
begin
SHIFT1: shiftn port map (xreg_s,sxreg_s,cnt_s);
SHIFT2: shiftn port map (yreg_s,syreg_s,cnt_s);
nas_s <= not as_s;
ADD1 : addsub port map (xreg_s,syreg_s,newx_s,as_s); -- xreg
ADD2 : addsub port map (yreg_s,sxreg_s,newy_s,nas_s); -- yreg
LUT : atan32 port map(cnt_s,atan_s);
ADD3 : addsub port map (zreg_s,atan_s(31 downto 0),newz_s,as_s); -- zreg
FSM1 : fsm port map (clk,reset,start,cnt_s,init_s,load_s,done);
-- COS(X) Register
process (clk,newx_s)
begin
if (rising_edge(clk)) then
if init_s='1' then xreg_s(31 downto 0) <= xinit_c; -- fails in vh2sc xinit_c(31 downto 0); -- 0.607
elsif load_s='1' then xreg_s <= newx_s;
end if;
end if;
end process;
-- SIN(Y) Register
process (clk,newy_s)
begin
if (rising_edge(clk)) then
if init_s='1' then yreg_s <= yinit_c; -- 0.0000 fails in vh2sc yinit_c(31 downto 0)
elsif load_s='1' then yreg_s <= newy_s;
end if;
end if;
end process;
-- Z Register
process (clk,newz_s,angle)
begin
if (rising_edge(clk)) then
if init_s='1' then zreg_s <= angle; -- x
elsif load_s='1' then zreg_s <= newz_s;
end if;
end if;
end process;
as_s <= zreg_s(31); -- MSB=Sign bit
process (clk,load_s,init_s) -- bit counter
begin
if (rising_edge(clk)) then
if init_s='1' then cnt_s<=(others=> '0');
elsif (load_s='1') then cnt_s <= cnt_s + '1';
end if;
end if;
end process;
sin <= yreg_s;
cos <= xreg_s;
end synthesis;
-------------------------------------------------------------------------------
-- --
-- Simple Cordic --
-- Copyright (C) 1999 HT-LAB --
-- --
-- Contact/Feedback : http://www.ht-lab.com/feedback.htm --
-- Web: http://www.ht-lab.com --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-- Adder/Subtracter --
-- no overflow. --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity addsub is
port (abus : in std_logic_vector(31 downto 0);
bbus : in std_logic_vector(31 downto 0);
obus : out std_logic_vector(31 downto 0);
as : in std_logic); --add=1, subtract=0
end addsub;
architecture synthesis of addsub is
begin
process(as,abus,bbus)
begin
if as='1' then
obus <= abus + bbus;
else
obus <= abus - bbus;
end if;
end process;
end synthesis;
-------------------------------------------------------------------------------
-- --
-- Simple Cordic --
-- Copyright (C) 1999 HT-LAB --
-- --
-- Contact/Feedback : http://www.ht-lab.com/feedback.htm --
-- Web: http://www.ht-lab.com --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity atan32 is
port ( za : in std_logic_vector(4 downto 0);
zdata : out std_logic_vector(31 downto 0));
end atan32;
Architecture synthesis of atan32 Is
Begin
process(ZA)
begin
Case ZA is
when "00000" => ZData <= X"3243f6a8";
when "00001" => ZData <= X"1dac6705";
when "00010" => ZData <= X"0fadbafc";
when "00011" => ZData <= X"07f56ea6";
when "00100" => ZData <= X"03feab76";
when "00101" => ZData <= X"01ffd55b";
when "00110" => ZData <= X"00fffaaa";
when "00111" => ZData <= X"007fff55";
when "01000" => ZData <= X"003fffea";
when "01001" => ZData <= X"001ffffd";
when "01010" => ZData <= X"000fffff";
when "01011" => ZData <= X"0007ffff";
when "01100" => ZData <= X"0003ffff";
when "01101" => ZData <= X"0001ffff";
when "01110" => ZData <= X"0000ffff";
when "01111" => ZData <= X"00007fff";
when "10000" => ZData <= X"00003fff";
when "10001" => ZData <= X"00001fff";
when "10010" => ZData <= X"00000fff";
when "10011" => ZData <= X"000007ff";
when "10100" => ZData <= X"000003ff";
when "10101" => ZData <= X"000001ff";
when "10110" => ZData <= X"000000ff";
when "10111" => ZData <= X"0000007f";
when "11000" => ZData <= X"0000003f";
when "11001" => ZData <= X"0000001f";
when "11010" => ZData <= X"0000000f";
when "11011" => ZData <= X"00000007";
when "11100" => ZData <= X"00000003";
when "11101" => ZData <= X"00000001";
when "11110" => ZData <= X"00000000";
when "11111" => ZData <= X"00000000";
When others => ZData <= "--------------------------------";
end case;
end process;
end synthesis;
-------------------------------------------------------------------------------
-- --
-- Simple Cordic --
-- Copyright (C) 1999 HT-LAB --
-- --
-- Contact/Feedback : http://www.ht-lab.com/feedback.htm --
-- Web: http://www.ht-lab.com --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY fsm IS
PORT(
clk : IN std_logic;
reset : IN std_logic; -- Active low reset
start : IN std_logic;
cnt : IN std_logic_vector (4 DOWNTO 0);
init : OUT std_logic;
load : OUT std_logic;
done : OUT std_logic);
END fsm ;
architecture synthesis of fsm is
type states is (s0,s1,s2,s3);
signal state,nextstate : states;
begin
Process (clk,reset) -- Process to create current state variables
begin
if (reset='0') then -- Reset State
state <= s0;
elsif (rising_edge(clk)) then
state <= nextstate; -- Set Current state
end if;
end process;
process(state,start,cnt)
begin
case state is
when s0 => -- Step 1 load regs
if start='1' then nextstate <= s1;
else nextstate <= s0; -- Wait for start signal
end if;
when s1 => -- latch result register
if cnt="11111" then nextstate <= s2; -- done
else nextstate <= s1; -- wait
end if;
when s2 =>
if start='0' then nextstate <= s0;
else nextstate <= s2; -- Wait for start signal
end if;
when others => nextstate <= s0;
end case;
end process;
process(state)
begin
case state is
when s0 =>done <= '0'; init <= '1'; load <= '0';
when s1 =>done <= '0'; init <= '0'; load <= '1';
when s2 =>done <= '1'; init <= '0'; load <= '0';
when others => done <= '-'; init <= '-'; load <= '-';
end case;
end process;
end synthesis;
-------------------------------------------------------------------------------
-- --
-- Simple Cordic --
-- Copyright (C) 1999 HT-LAB --
-- --
-- Contact/Feedback : http://www.ht-lab.com/feedback.htm --
-- Web: http://www.ht-lab.com --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-- Shift Right preserving sign bit --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shiftn is
port (ibus : in std_logic_vector(31 downto 0);
obus : out std_logic_vector(31 downto 0);
n : in std_logic_vector(4 downto 0)); --shift by n
end shiftn;
architecture synthesis of shiftn is
begin
process(n,ibus)
begin
case n is
when "00000" => obus <= ibus(31)&ibus(30 downto 0); -- ibus
when "00001" => obus <= ibus(31)&ibus(31)&ibus(30 downto 1);
when "00010" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 2);
when "00011" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 3);
when "00100" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 4);
when "00101" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 5);
when "00110" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 6);
when "00111" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(30 downto 7);
when "01000" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(30 downto 8);
when "01001" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 9);
when "01010" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 10);
when "01011" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 11);
when "01100" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 12);
when "01101" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 13);
when "01110" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 14);
when "01111" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 15);
when "10000" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(30 downto 16);
when "10001" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(30 downto 17);
when "10010" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(30 downto 18);
when "10011" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 19);
when "10100" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 20);
when "10101" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 21);
when "10110" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 22);
when "10111" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 23);
when "11000" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 24);
when "11001" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 25);
when "11010" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(30 downto 26);
when "11011" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(30 downto 27);
when "11100" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(30 downto 28);
when "11101" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 29);
when "11110" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30);
when others => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31);
end case;
end process;
end synthesis;
| gpl-3.0 | cfffe22af5161d5a31999584c9e87e9f | 0.409005 | 4.3012 | false | false | false | false |
VLSI-EDA/UVVM_All | bitvis_vip_uart/src/vvc_context.vhd | 1 | 1,401 | --========================================================================================================================
-- Copyright (c) 2018 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
context vvc_context is
library bitvis_vip_uart;
use bitvis_vip_uart.vvc_cmd_pkg.all;
use bitvis_vip_uart.vvc_methods_pkg.all;
use bitvis_vip_uart.td_vvc_framework_common_methods_pkg.all;
end context;
| mit | 44da521e138769f74cf397e079ba38de | 0.526767 | 5.494118 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/function_17.vhd | 5 | 1,887 | ---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_17 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_17 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable vTemp1 : std_logic_vector(7 downto 0);
variable vTemp2 : std_logic_vector(7 downto 0);
variable vTemp3 : std_logic_vector(7 downto 0);
variable vTemp4 : std_logic_vector(7 downto 0);
begin
IF INPUT_2( 0 ) = '0' THEN
vTemp1 := INPUT_1( 7 downto 0);
ELSE
vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(0, 8) - SIGNED(INPUT_2( 7 downto 0)) );
END IF;
IF INPUT_2( 8 ) = '0' THEN
vTemp1 := INPUT_1(15 downto 8);
ELSE
vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(0, 8) - SIGNED(INPUT_2(15 downto 8)) );
END IF;
IF INPUT_2( 16 ) = '0' THEN
vTemp1 := INPUT_1(23 downto 16);
ELSE
vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(0, 8) - SIGNED(INPUT_2(23 downto 16)) );
END IF;
IF INPUT_2( 24 ) = '0' THEN
vTemp1 := INPUT_1(31 downto 24);
ELSE
vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(0, 8) - SIGNED(INPUT_2(31 downto 24)) );
END IF;
OUTPUT_1 <= (vTemp4 & vTemp3 & vTemp2 & vTemp1);
end process;
end; --architecture logic
| gpl-3.0 | 9c055a670d25eee7476a0b72f2c963e6 | 0.579756 | 3.139767 | false | false | false | false |
chibby0ne/vhdl-book | Chapter13/rom_dir/rom.vhd | 1 | 1,409 | --!
--! Copyright (C) 2010 - 2013 Creonic GmbH
--!
--! @file: rom.vhd
--! @brief:
--! @author: Antonio Gutierrez
--! @date: 2014-04-23
--!
--!
--------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------------------------
entity rom is
port (
clk: in std_logic;
address: in integer range 0 to 15;
data_out: out std_logic_vector(7 downto 0));
end entity rom;
--------------------------------------------------------
architecture circuit of rom is
signal reg_address: integer range 0 to 15;
type memory is array (0 to 15) of std_logic_vector(7 downto 0);
constant myrom: memory := (
2 => "11111111", --255
3 => "00011010", --26
4 => "00000101", --5
5 => "01010000", --80
6 => "10110000", --176
15 => "00010001", --17
others => "00000000");
begin
--------------------------------------------------------
-- register the address
--------------------------------------------------------
process (clk)
begin
if (clk'event and clk = '1') then
reg_address <= address;
end if;
end process;
--------------------------------------------------------
-- get unregistered output
--------------------------------------------------------
data_out <= myrom(reg_address);
end architecture circuit;
| gpl-3.0 | 06434ddf05cc157a8a4f665f774ef3e4 | 0.405252 | 4.792517 | false | false | false | false |
muhd7rosli/mblite-vivado | mblite_ip/src/vhdl/core/gprf.vhd | 1 | 2,990 | ----------------------------------------------------------------------------------------------
-- This file is part of mblite_ip.
--
-- mblite_ip is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- mblite_ip is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with mblite_ip. If not, see <http://www.gnu.org/licenses/>.
--
-- Input file : gprf.vhd
-- Design name : gprf
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : The general purpose register infers memory blocks to implement
-- the register file. All outputs are registered, possibly by using
-- registered memory elements.
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
entity gprf is port
(
gprf_o : out gprf_out_type;
gprf_i : in gprf_in_type;
ena_i : in std_logic;
clk_i : in std_logic
);
end gprf;
-- This architecture is the default implementation. It
-- consists of three dual port memories. Other
-- architectures can be added while configurations can
-- control the implemented architecture.
architecture arch of gprf is
begin
a : dsram generic map
(
WIDTH => CFG_DMEM_WIDTH,
SIZE => CFG_GPRF_SIZE
)
port map
(
dat_o => gprf_o.dat_a_o,
adr_i => gprf_i.adr_a_i,
ena_i => ena_i,
dat_w_i => gprf_i.dat_w_i,
adr_w_i => gprf_i.adr_w_i,
wre_i => gprf_i.wre_i,
clk_i => clk_i
);
b : dsram generic map
(
WIDTH => CFG_DMEM_WIDTH,
SIZE => CFG_GPRF_SIZE
)
port map
(
dat_o => gprf_o.dat_b_o,
adr_i => gprf_i.adr_b_i,
ena_i => ena_i,
dat_w_i => gprf_i.dat_w_i,
adr_w_i => gprf_i.adr_w_i,
wre_i => gprf_i.wre_i,
clk_i => clk_i
);
d : dsram generic map
(
WIDTH => CFG_DMEM_WIDTH,
SIZE => CFG_GPRF_SIZE
)
port map
(
dat_o => gprf_o.dat_d_o,
adr_i => gprf_i.adr_d_i,
ena_i => ena_i,
dat_w_i => gprf_i.dat_w_i,
adr_w_i => gprf_i.adr_w_i,
wre_i => gprf_i.wre_i,
clk_i => clk_i
);
end arch;
| lgpl-3.0 | 73a4f99d94efbbe3c20a97bda7268d3d | 0.539799 | 3.572282 | false | false | false | false |
chibby0ne/vhdl-book | Chapter11/example4_dir/fsm_timer.vhd | 1 | 2,481 | --------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------
entity simple_car_alarm is
port (
clk, rst, remote, sensors: in std_logic;
siren: out std_logic);
end entity simple_car_alarm;
--------------------------------------
architecture circuit of simple_car_alarm is
type state is (disarmed, armed, intrusion);
signal pr_state, nx_state: state;
attribute enum_encoding: string;
attribute enum_encoding of state: type is "sequential";
signal flag: std_logic;
begin
-- flag generator
process (clk, rst)
--declarativepart
begin
if (rst = '1') then
flag <= '0';
elsif (clk'event and clk = '1') then
if (remote = '0') then
flag <= '1';
else
flag <= '0';
end if;
end if;
end process;
--------------------------------------
-- lower section of FSM
--------------------------------------
process (clk, rst)
--declarativepart
begin
if (rst = '1') then
pr_state <= disarmed;
elsif (clk'event and clk = '1') then
pr_state <= nx_state;
end if;
end process;
--------------------------------------
--------------------------------------
-- Upper section of FSM
--------------------------------------
process (pr_state, remote, sensors, flag)
--declarativepart
begin
case pr_state is
when disarmed =>
siren <= '0';
if (remote = '1' and flag = '1') then
nx_state <= armed;
else
nx_state <= disarmed;
end if;
when armed =>
siren <= '0';
if (sensors = '1') then
nx_state <= intrusion;
elsif (remote = '1' and flag = '1') then
nx_state <= disarmed;
else
nx_state <= armed;
end if;
when intrusion =>
siren <= '1';
if (remote = '1' and flag = '1') then
nx_state <= disarmed;
else
nx_state <= intrusion;
end if;
end case;
end process;
end architecture circuit;
--------------------------------------
| gpl-3.0 | 52c378e8787390c8d55fafb8de679cbe | 0.39339 | 5.042683 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Ram/simulation/Ram_synth.vhd | 1 | 8,143 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Ram_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY Ram_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE Ram_synth_ARCH OF Ram_synth IS
COMPONENT Ram_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 32,
READ_WIDTH => 32 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: Ram_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| mit | f6dfe104eadc5c9e4d48f8192ab5877e | 0.544271 | 3.768163 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Instruction_Memory/simulation/Instruction_Memory_tb_synth ([email protected] 2015-09-19-15-43-09).vhd | 1 | 7,280 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Instruction_Memory_tb_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.Instruction_Memory_TB_PKG.ALL;
ENTITY Instruction_Memory_tb_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 0
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END Instruction_Memory_tb_synth;
ARCHITECTURE Instruction_Memory_synth_ARCH OF Instruction_Memory_tb_synth IS
COMPONENT Instruction_Memory_exdes
PORT (
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
A : IN STD_LOGIC_VECTOR(14-1-(4*0*boolean'pos(14>4)) downto 0)
:= (OTHERS => '0')
);
END COMPONENT;
CONSTANT STIM_CNT : INTEGER := if_then_else(C_ROM_SYNTH = 0, 8, 22);
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i : STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ADDR: STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDR_R: STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL SPO: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL SPO_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
Instruction_Memory_TB_STIM_GEN_INST:ENTITY work.Instruction_Memory_TB_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
A => ADDR,
DATA_IN => SPO_R,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(STIM_CNT);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDR(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW + 1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
SPO_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
SPO_R <= SPO AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDR_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDR_R <= ADDR AFTER 50 ns;
END IF;
END IF;
END PROCESS;
DMG_PORT: Instruction_Memory_exdes PORT MAP (
SPO => SPO,
A => ADDR_R
);
END ARCHITECTURE;
| mit | f378a77f23a9eb686df6979fee58d0d2 | 0.563462 | 3.79562 | false | false | false | false |
chibby0ne/vhdl-book | Chapter2/texercise2-2_dir/texercise2-2.vhd | 1 | 1,283 | ------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------
entity test_circuit is
--generic declarations
end entity;
------------------------------
architecture only of test_circuit is
--DUT declaration--
component circuit is
port ( a: in std_logic;
b: in std_logic;
c: in std_logic;
z: out std_logic);
end component;
-- signal declaration --
signal a_tb: std_logic := '1';
signal b_tb: std_logic := '0';
signal c_tb: std_logic := '0';
signal x_tb: std_logic;
signal y_tb: std_logic;
signal z_tb: std_logic;
begin
-- DUT instantiation --
dut: circuit
PORT MAP (
a => a_tb,
b => b_tb,
c => c_tb,
z => z_tb);
-- stimuli generation --
x_tb <= a_tb nand b_tb;
y_tb <= c_tb or x_tb;
stimuli : process
begin
wait for 5 ns;
b_tb <= '1';
wait for 5 ns;
c_tb <= '1';
wait for 5 ns;
b_tb <= '0';
wait for 5 ns;
c_tb <= '0';
wait for 5 ns;
a_tb <= '0';
wait for 5 ns;
b_tb <= '1';
wait;
end process;
end architecture;
------------------------------
| gpl-3.0 | 28581bce49196c8319a07aea88a2fd12 | 0.431021 | 3.740525 | false | false | false | false |
chibby0ne/vhdl-book | Chapter10/exercise12_dir/addr_deco_tb.vhd | 1 | 2,722 | --type IV testbench for an address decoder
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
--------------------------------------
entity addr_deco_tb is
generic (N: integer := 3);
end entity addr_deco_tb;
--------------------------------------
architecture circuit of addr_deco_tb is
-- dut declaration
component addr_deco is
generic (N: integer := 3);
port (
address: in natural range 0 to 2**N-1;
ena: in bit;
word_line: out bit_vector(2**N-1 downto 0));
end component addr_deco;
-- signals declarations
signal address_tb: natural range 0 to 2**N-1 := 0;
signal ena_tb: bit := '1';
signal word_line_tb: bit_vector(2**N-1 downto 0);
signal expected: bit_vector(2**N-1 downto 0);
begin
-- dut instantiation
dut: addr_deco port map (
address => address_tb,
ena => ena_tb,
word_line => word_line_tb
);
-- stimuli generation
-- ena
process
begin
wait for 20 ns;
ena_tb <= '0';
wait for 20 ns;
ena_tb <= '1';
wait;
end process;
-- stimuli generation
-- address
process
begin
wait for 60 ns;
address_tb <= 1;
wait for 20 ns;
address_tb <= 2;
wait for 20 ns;
address_tb <= 3;
wait for 20 ns;
address_tb <= 4;
wait for 20 ns;
address_tb <= 5;
wait for 20 ns;
address_tb <= 6;
wait for 20 ns;
address_tb <= 7;
wait;
end process;
-- output verification
-- generate template
expected <= "11111110",
"11111111" after 21 ns,
"11111110" after 41 ns,
"11111101" after 61 ns,
"11111011" after 81 ns,
"11110111" after 101 ns,
"11101111" after 121 ns,
"11011111" after 141 ns,
"10111111" after 161 ns,
"01111111" after 181 ns;
-- make comparison
process
begin
wait for 1 ns;
if (ena_tb = '0') then
assert word_line_tb = "11111111"
report "error. enable is not reseting output"
severity failure;
else
if (now > 180 ns) then
assert false
report "no errors"
severity note;
wait;
else
assert word_line_tb = expected
report "error. for address_tb = " & natural'image(address_tb)
severity failure;
end if;
end if;
end process;
end architecture circuit;
| gpl-3.0 | f6c1f2f94eb04791cc7fa83a6d165ac3 | 0.495959 | 4.273155 | false | false | false | false |
idpromnut/tek7854mpu | debugger/debug_hdl/serial_tx.vhd | 1 | 3,614 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity serial_tx is
generic(
baud: time := 104.167 us; -- 9600
width: natural := 8; -- 8 data bits
stop_bits: natural := 1; -- 1 stop bit
clk_period: time );
port(
data_in: in std_ulogic_vector(width-1 downto 0);
data_out: out std_ulogic;
ready: out std_ulogic;
wr: in std_ulogic;
clk: in std_ulogic );
end serial_tx;
architecture behavioral of serial_tx is
type tx_state is ( state_init, state_startbit, state_tx_data, state_stopbits );
signal state: tx_state := state_init;
signal bits_transmitted: natural := 0;
signal data_shift_reg: std_ulogic_vector(width-1 downto 0);
signal baud_divider: natural := 0;
signal baud_clk_edge: std_ulogic := '0';
signal tx_out: std_ulogic;
begin
-- Baud rate generator
process(clk)
constant div_top: natural := (baud / clk_period);
begin
if rising_edge(clk) then
if baud_divider = div_top then
baud_divider <= 0;
else
baud_divider <= baud_divider + 1;
end if;
if baud_divider = (div_top / 2) then
baud_clk_edge <= '1';
else
baud_clk_edge <= '0';
end if;
end if;
end process;
data_out <= tx_out;
-- Main transmitter
process(clk, data_in, wr, state)
begin
if rising_edge(clk) then
case state is
when state_init =>
data_shift_reg <= data_in;
bits_transmitted <= 0;
tx_out <= '1';
ready <= '1';
if wr = '1' and baud_clk_edge = '1' then
state <= state_startbit;
else
state <= state_init;
end if;
when state_startbit =>
bits_transmitted <= 0;
tx_out <= '0';
ready <= '0';
if baud_clk_edge = '1' then
state <= state_tx_data;
else
state <= state_startbit;
end if;
when state_tx_data =>
tx_out <= data_shift_reg(0);
ready <= '0';
if baud_clk_edge = '1' then
data_shift_reg(width-2 downto 0) <= data_shift_reg(width-1 downto 1);
if bits_transmitted = width - 1 then
state <= state_stopbits;
bits_transmitted <= 0;
elsif stop_bits > 0 then
state <= state_tx_data;
bits_transmitted <= bits_transmitted + 1;
else
state <= state_init;
bits_transmitted <= 0;
end if;
else
state <= state_tx_data;
bits_transmitted <= bits_transmitted;
data_shift_reg <= data_shift_reg;
end if;
when state_stopbits =>
tx_out <= '1';
ready <= '0';
if bits_transmitted = stop_bits - 1 and baud_clk_edge = '1' then
state <= state_init;
bits_transmitted <= 0;
elsif baud_clk_edge = '1' then
state <= state_stopbits;
bits_transmitted <= bits_transmitted + 1;
else
state <= state_stopbits;
bits_transmitted <= bits_transmitted;
end if;
end case;
end if;
end process;
end behavioral;
| mit | 91929dd5fef4100877e08024b5d044cb | 0.469563 | 4.202326 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/TRIGO/COSINUS_32b.vhd | 1 | 30,123 | -------------------------------------------------------------------------------
-- --
-- Simple Cordic --
-- Copyright (C) 1999 HT-LAB --
-- --
-- Contact/Feedback : http://www.ht-lab.com/feedback.htm --
-- Web: http://www.ht-lab.com --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-- Cordic Top --
-- --
-- Simple SIN/COS Cordic example --
-- 32 bits fixed format Sign,2^0, 2^-1,2^-2 etc. --
-- angle input +/-0.5phi --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity COSINUS_32b is
port(clk : in std_logic;
reset : in std_logic; -- Active low reset
angle : in std_logic_vector(31 downto 0); -- input radian
sin : out std_logic_vector(31 downto 0); -- THIS OUTPUT ¨PROVIDES THE SINUS RESULT
cos : out std_logic_vector(31 downto 0);
start : in std_logic;
done : out std_logic);
end COSINUS_32b;
architecture synthesis of COSINUS_32b is
constant xinit_c : std_logic_vector(31 downto 0):=X"26dd3b44";
constant yinit_c : std_logic_vector(31 downto 0):=X"00000000";
component addsub is
port(abus : in std_logic_vector(31 downto 0);
bbus : in std_logic_vector(31 downto 0);
obus : out std_logic_vector(31 downto 0);
as : in std_logic); --add=1, subtract=0
end component;
component shiftn is
port(ibus : in std_logic_vector(31 downto 0);
obus : out std_logic_vector(31 downto 0);
n : in std_logic_vector(4 downto 0)); --shift by n
end component;
component atan32 is --ARCTAN(x) lut
port (ZA : in Std_Logic_Vector(4 downto 0);
ZData : out Std_Logic_Vector(31 downto 0));
end component;
component fsm is
port(clk : in std_logic;
reset : in std_logic; -- Active low reset
start : in std_logic;
cnt : in std_logic_vector(4 downto 0);
init : out std_logic;
load : out std_logic;
done : out std_logic);
end component;
signal cnt_s : std_logic_vector(4 downto 0); -- bit counter, 2^5
signal newx_s : std_logic_vector(31 downto 0);
signal newy_s : std_logic_vector(31 downto 0);
signal newz_s : std_logic_vector(31 downto 0);
signal xreg_s : std_logic_vector(31 downto 0);
signal yreg_s : std_logic_vector(31 downto 0);
signal zreg_s : std_logic_vector(31 downto 0);
signal sxreg_s: std_logic_vector(31 downto 0);
signal syreg_s: std_logic_vector(31 downto 0);
signal atan_s : std_logic_vector(31 downto 0); -- arctan LUT
signal init_s : std_logic;
signal load_s : std_logic;
signal as_s : std_logic;
signal nas_s : std_logic;
begin
SHIFT1: shiftn port map (xreg_s,sxreg_s,cnt_s);
SHIFT2: shiftn port map (yreg_s,syreg_s,cnt_s);
nas_s <= not as_s;
ADD1 : addsub port map (xreg_s,syreg_s,newx_s,as_s); -- xreg
ADD2 : addsub port map (yreg_s,sxreg_s,newy_s,nas_s); -- yreg
LUT : atan32 port map(cnt_s,atan_s);
ADD3 : addsub port map (zreg_s,atan_s(31 downto 0),newz_s,as_s); -- zreg
FSM1 : fsm port map (clk,reset,start,cnt_s,init_s,load_s,done);
-- COS(X) Register
process (clk,newx_s)
begin
if (rising_edge(clk)) then
if init_s='1' then xreg_s(31 downto 0) <= xinit_c; -- fails in vh2sc xinit_c(31 downto 0); -- 0.607
elsif load_s='1' then xreg_s <= newx_s;
end if;
end if;
end process;
-- SIN(Y) Register
process (clk,newy_s)
begin
if (rising_edge(clk)) then
if init_s='1' then yreg_s <= yinit_c; -- 0.0000 fails in vh2sc yinit_c(31 downto 0)
elsif load_s='1' then yreg_s <= newy_s;
end if;
end if;
end process;
-- Z Register
process (clk,newz_s,angle)
begin
if (rising_edge(clk)) then
if init_s='1' then zreg_s <= angle; -- x
elsif load_s='1' then zreg_s <= newz_s;
end if;
end if;
end process;
as_s <= zreg_s(31); -- MSB=Sign bit
process (clk,load_s,init_s) -- bit counter
begin
if (rising_edge(clk)) then
if init_s='1' then cnt_s<=(others=> '0');
elsif (load_s='1') then cnt_s <= cnt_s + '1';
end if;
end if;
end process;
sin <= yreg_s;
cos <= xreg_s;
end synthesis;
-------------------------------------------------------------------------------
-- --
-- Simple Cordic --
-- Copyright (C) 1999 HT-LAB --
-- --
-- Contact/Feedback : http://www.ht-lab.com/feedback.htm --
-- Web: http://www.ht-lab.com --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-- Adder/Subtracter --
-- no overflow. --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity addsub is
port (abus : in std_logic_vector(31 downto 0);
bbus : in std_logic_vector(31 downto 0);
obus : out std_logic_vector(31 downto 0);
as : in std_logic); --add=1, subtract=0
end addsub;
architecture synthesis of addsub is
begin
process(as,abus,bbus)
begin
if as='1' then
obus <= abus + bbus;
else
obus <= abus - bbus;
end if;
end process;
end synthesis;
-------------------------------------------------------------------------------
-- --
-- Simple Cordic --
-- Copyright (C) 1999 HT-LAB --
-- --
-- Contact/Feedback : http://www.ht-lab.com/feedback.htm --
-- Web: http://www.ht-lab.com --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity atan32 is
port ( za : in std_logic_vector(4 downto 0);
zdata : out std_logic_vector(31 downto 0));
end atan32;
Architecture synthesis of atan32 Is
Begin
process(ZA)
begin
Case ZA is
when "00000" => ZData <= X"3243f6a8";
when "00001" => ZData <= X"1dac6705";
when "00010" => ZData <= X"0fadbafc";
when "00011" => ZData <= X"07f56ea6";
when "00100" => ZData <= X"03feab76";
when "00101" => ZData <= X"01ffd55b";
when "00110" => ZData <= X"00fffaaa";
when "00111" => ZData <= X"007fff55";
when "01000" => ZData <= X"003fffea";
when "01001" => ZData <= X"001ffffd";
when "01010" => ZData <= X"000fffff";
when "01011" => ZData <= X"0007ffff";
when "01100" => ZData <= X"0003ffff";
when "01101" => ZData <= X"0001ffff";
when "01110" => ZData <= X"0000ffff";
when "01111" => ZData <= X"00007fff";
when "10000" => ZData <= X"00003fff";
when "10001" => ZData <= X"00001fff";
when "10010" => ZData <= X"00000fff";
when "10011" => ZData <= X"000007ff";
when "10100" => ZData <= X"000003ff";
when "10101" => ZData <= X"000001ff";
when "10110" => ZData <= X"000000ff";
when "10111" => ZData <= X"0000007f";
when "11000" => ZData <= X"0000003f";
when "11001" => ZData <= X"0000001f";
when "11010" => ZData <= X"0000000f";
when "11011" => ZData <= X"00000007";
when "11100" => ZData <= X"00000003";
when "11101" => ZData <= X"00000001";
when "11110" => ZData <= X"00000000";
when "11111" => ZData <= X"00000000";
When others => ZData <= "--------------------------------";
end case;
end process;
end synthesis;
-------------------------------------------------------------------------------
-- --
-- Simple Cordic --
-- Copyright (C) 1999 HT-LAB --
-- --
-- Contact/Feedback : http://www.ht-lab.com/feedback.htm --
-- Web: http://www.ht-lab.com --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY fsm IS
PORT(
clk : IN std_logic;
reset : IN std_logic; -- Active low reset
start : IN std_logic;
cnt : IN std_logic_vector (4 DOWNTO 0);
init : OUT std_logic;
load : OUT std_logic;
done : OUT std_logic);
END fsm ;
architecture synthesis of fsm is
type states is (s0,s1,s2,s3);
signal state,nextstate : states;
begin
Process (clk,reset) -- Process to create current state variables
begin
if (reset='0') then -- Reset State
state <= s0;
elsif (rising_edge(clk)) then
state <= nextstate; -- Set Current state
end if;
end process;
process(state,start,cnt)
begin
case state is
when s0 => -- Step 1 load regs
if start='1' then nextstate <= s1;
else nextstate <= s0; -- Wait for start signal
end if;
when s1 => -- latch result register
if cnt="11111" then nextstate <= s2; -- done
else nextstate <= s1; -- wait
end if;
when s2 =>
if start='0' then nextstate <= s0;
else nextstate <= s2; -- Wait for start signal
end if;
when others => nextstate <= s0;
end case;
end process;
process(state)
begin
case state is
when s0 =>done <= '0'; init <= '1'; load <= '0';
when s1 =>done <= '0'; init <= '0'; load <= '1';
when s2 =>done <= '1'; init <= '0'; load <= '0';
when others => done <= '-'; init <= '-'; load <= '-';
end case;
end process;
end synthesis;
-------------------------------------------------------------------------------
-- --
-- Simple Cordic --
-- Copyright (C) 1999 HT-LAB --
-- --
-- Contact/Feedback : http://www.ht-lab.com/feedback.htm --
-- Web: http://www.ht-lab.com --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-- Shift Right preserving sign bit --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shiftn is
port (ibus : in std_logic_vector(31 downto 0);
obus : out std_logic_vector(31 downto 0);
n : in std_logic_vector(4 downto 0)); --shift by n
end shiftn;
architecture synthesis of shiftn is
begin
process(n,ibus)
begin
case n is
when "00000" => obus <= ibus(31)&ibus(30 downto 0); -- ibus
when "00001" => obus <= ibus(31)&ibus(31)&ibus(30 downto 1);
when "00010" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 2);
when "00011" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 3);
when "00100" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 4);
when "00101" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 5);
when "00110" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 6);
when "00111" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(30 downto 7);
when "01000" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(30 downto 8);
when "01001" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 9);
when "01010" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 10);
when "01011" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 11);
when "01100" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 12);
when "01101" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 13);
when "01110" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 14);
when "01111" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 15);
when "10000" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(30 downto 16);
when "10001" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(30 downto 17);
when "10010" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(30 downto 18);
when "10011" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 19);
when "10100" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 20);
when "10101" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 21);
when "10110" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 22);
when "10111" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 23);
when "11000" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 24);
when "11001" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 25);
when "11010" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(30 downto 26);
when "11011" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(30 downto 27);
when "11100" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(30 downto 28);
when "11101" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 29);
when "11110" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30);
when others => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31);
end case;
end process;
end synthesis;
| gpl-3.0 | f9e6766c0af2a0246b9e0cf89391cd2f | 0.409123 | 4.302057 | false | false | false | false |
VLSI-EDA/UVVM_All | uvvm_util/src/adaptations_pkg.vhd | 1 | 17,077 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.types_pkg.all;
package adaptations_pkg is
constant C_ALERT_FILE_NAME : string := "_Alert.txt";
constant C_LOG_FILE_NAME : string := "_Log.txt";
constant C_SHOW_UVVM_UTILITY_LIBRARY_INFO : boolean := true; -- Set this to false when you no longer need the initial info
constant C_SHOW_UVVM_UTILITY_LIBRARY_RELEASE_INFO : boolean := true; -- Set this to false when you no longer need the release info
-------------------------------------------------------------------------------
-- Log format
-------------------------------------------------------------------------------
--UVVM: [<ID>] <time> <Scope> Msg
--PPPPPPPPIIIIII TTTTTTTT SSSSSSSSSSSSSS MMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMM
constant C_LOG_PREFIX : string := "UVVM: "; -- Note: ': ' is recommended as final characters
constant C_LOG_PREFIX_WIDTH : natural := C_LOG_PREFIX'length;
constant C_LOG_MSG_ID_WIDTH : natural := 24;
constant C_LOG_TIME_WIDTH : natural := 16; -- 3 chars used for unit eg. " ns"
constant C_LOG_TIME_BASE : time := ns; -- Unit in which time is shown in log (ns | ps)
constant C_LOG_TIME_DECIMALS : natural := 1; -- Decimals to show for given C_LOG_TIME_BASE
constant C_LOG_SCOPE_WIDTH : natural := 30;
constant C_LOG_LINE_WIDTH : natural := 175;
constant C_LOG_INFO_WIDTH : natural := C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH;
constant C_USE_BACKSLASH_N_AS_LF : boolean := true; -- If true interprets '\n' as Line feed
constant C_USE_BACKSLASH_R_AS_LF : boolean := true; -- If true, inserts an empty line if '\r'
-- is the first character of the string.
constant C_SINGLE_LINE_ALERT : boolean := false; -- If true prints alerts on a single line.
constant C_SINGLE_LINE_LOG : boolean := false; -- If true prints log messages on a single line.
constant C_TB_SCOPE_DEFAULT : string := "TB seq."; -- Default scope in test sequencer
constant C_LOG_TIME_TRUNC_WARNING : boolean := true; -- Yields a single TB_WARNING if time stamp truncated. Otherwise none
constant C_SHOW_LOG_ID : boolean := true; -- This constant has replaced the global_show_log_id
constant C_SHOW_LOG_SCOPE : boolean := true; -- This constant has replaced the global_show_log_scope
constant C_WARNING_ON_LOG_ALERT_FILE_RUNTIME_RENAME : boolean := false;
constant C_USE_STD_STOP_ON_ALERT_STOP_LIMIT : boolean := true; -- true: break using std.env.stop, false: break using failure
shared variable shared_default_log_destination : t_log_destination := CONSOLE_AND_LOG;
-------------------------------------------------------------------------------
-- Verbosity control
-- NOTE: Do not enter new IDs without proper evaluation:
-- 1. Is it - or could it be covered by an existing ID
-- 2. Could it be combined with other needs for a more general new ID
-- Feel free to suggest new ID for future versions of UVVM Utility Library ([email protected])
-------------------------------------------------------------------------------
type t_msg_id is (
-- Bitvis utility methods
NO_ID, -- Used as default prior to setting actual ID when transfering ID as a field in a record
ID_UTIL_BURIED, -- Used for buried log messages where msg and scope cannot be modified from outside
ID_BITVIS_DEBUG, -- Bitvis internal ID used for UVVM debugging
ID_UTIL_SETUP, -- Used for Utility setup
ID_LOG_MSG_CTRL, -- Used inside Utility library only - when enabling/disabling msg IDs.
ID_ALERT_CTRL, -- Used inside Utility library only - when setting IGNORE or REGARD on various alerts.
ID_NEVER, -- Used for avoiding log entry. Cannot be enabled.
ID_FINISH_OR_STOP, -- Used when terminating the complete simulation - independent of why
ID_CLOCK_GEN, -- Used for logging when clock generators are enabled or disabled
ID_GEN_PULSE, -- Used for logging when a gen_pulse procedure starts pulsing a signal
ID_BLOCKING, -- Used for logging when using synchronisation flags
-- General
ID_POS_ACK, -- To write a positive acknowledge on a check
ID_DATA, -- To write general handling of data
ID_CTRL, -- To write general control/config information
-- Directly inside test sequencers
ID_LOG_HDR, -- ONLY allowed in test sequencer, Log section headers
ID_LOG_HDR_LARGE, -- ONLY allowed in test sequencer, Large log section headers
ID_LOG_HDR_XL, -- ONLY allowed in test sequencer, Extra large log section headers
ID_SEQUENCER, -- ONLY allowed in test sequencer, Normal log (not log headers)
ID_SEQUENCER_SUB, -- ONLY allowed in test sequencer, Subprograms defined in sequencer
-- BFMs
ID_BFM, -- Used inside a BFM (to log BFM access)
ID_BFM_WAIT, -- Used inside a BFM to indicate that it is waiting for something (e.g. for ready)
ID_BFM_POLL, -- Used inside a BFM when polling until reading a given value. I.e. to show all reads until expected value found (e.g. for sbi_poll_until())
ID_BFM_POLL_SUMMARY, -- Used inside a BFM when showing the summary of data that has been received while waiting for expected data.
ID_TERMINATE_CMD, -- Typically used inside a loop in a procedure to end the loop (e.g. for sbi_poll_until() or any looped generation of random stimuli
-- Packet related data Ids with three levels of granularity, for differentiating between frames, packets and segments.
-- Segment Ids, finest granularity of packet data
ID_SEGMENT_INITIATE, -- Notify that a segment is about to be transmitted or received
ID_SEGMENT_COMPLETE, -- Notify that a segment has been transmitted or received
ID_SEGMENT_HDR, -- AS ID_SEGMENT_COMPLETE, but also writes header info
ID_SEGMENT_DATA, -- AS ID_SEGMENT_COMPLETE, but also writes segment data (could be huge)
-- Packet Ids, medium granularity of packet data
ID_PACKET_INITIATE, -- Notify that a packet is about to be transmitted or received
ID_PACKET_COMPLETE, -- Notify that a packet has been transmitted or received
ID_PACKET_HDR, -- AS ID_PACKET_COMPLETED, but also writes header info
ID_PACKET_DATA, -- AS ID_PACKET_COMPLETED, but also writes packet data (could be huge)
-- Frame Ids, roughest granularity of packet data
ID_FRAME_INITIATE, -- Notify that a frame is about to be transmitted or received
ID_FRAME_COMPLETE, -- Notify that a frame has been transmitted or received
ID_FRAME_HDR, -- AS ID_FRAME_COMPLETE, but also writes header info
ID_FRAME_DATA, -- AS ID_FRAME_COMPLETE, but also writes frame data (could be huge)
-- OSVVM Ids
ID_COVERAGE_MAKEBIN, -- Log messages from MakeBin (IllegalBin/GenBin/IgnoreBin)
ID_COVERAGE_ADDBIN, -- Log messages from AddBin/AddCross
ID_COVERAGE_ICOVER, -- ICover logging, NB: Very low level debugging. Can result in large amount of data.
ID_COVERAGE_CONFIG, -- Logging of configuration in the coverage package
ID_COVERAGE_SUMMARY, -- Report logging : Summary of coverage, with both covered bins and holes
ID_COVERAGE_HOLES, -- Report logging : Holes only
-- Distributed command systems
ID_UVVM_SEND_CMD, -- Logs the commands sent to the VVC
ID_UVVM_CMD_ACK, -- Logs the command's ACKs or timeouts from the VVC
ID_UVVM_CMD_RESULT, -- Logs the fetched results from the VVC
ID_CMD_INTERPRETER, -- Message from VVC interpreter about correctly received and queued/issued command
ID_CMD_INTERPRETER_WAIT, -- Message from VVC interpreter that it is actively waiting for a command
ID_IMMEDIATE_CMD, -- Message from VVC interpreter that an IMMEDIATE command has been executed
ID_IMMEDIATE_CMD_WAIT, -- Message from VVC interpreter that an IMMEDIATE command is waiting for command to complete
ID_CMD_EXECUTOR, -- Message from VVC executor about correctly received command - prior to actual execution
ID_CMD_EXECUTOR_WAIT, -- Message from VVC executor that it is actively waiting for a command
ID_INSERTED_DELAY, -- Message from VVC executor that it is waiting a given delay
-- Distributed data
ID_UVVM_DATA_QUEUE, -- Information about UVVM data FIFO/stack (initialization, put, get, etc)
-- VVC system
ID_CONSTRUCTOR, -- Constructor message from VVCs (or other components/process when needed)
ID_CONSTRUCTOR_SUB, -- Constructor message for lower level constructor messages (like Queue-information and other limitations)
-- Special purpose - Not really IDs
ALL_MESSAGES -- Applies to ALL message ID apart from ID_NEVER
);
type t_msg_id_panel is array (t_msg_id'left to t_msg_id'right) of t_enabled;
constant C_TB_MSG_ID_DEFAULT : t_msg_id := ID_SEQUENCER; -- msg ID used when calling the log method without any msg ID switch.
-- Default message Id panel to be used for all message Id panels, except:
-- - VVC message Id panels, see constant C_VVC_MSG_ID_PANEL_DEFAULT
constant C_MSG_ID_PANEL_DEFAULT : t_msg_id_panel := (
ID_NEVER => DISABLED,
ID_UTIL_BURIED => DISABLED,
ID_BITVIS_DEBUG => DISABLED,
ID_COVERAGE_MAKEBIN => DISABLED,
ID_COVERAGE_ADDBIN => DISABLED,
ID_COVERAGE_ICOVER => DISABLED,
others => ENABLED
);
-- If false, OSVVM uses the default message id panel. If true, it uses a separate message id panel.
constant C_USE_LOCAL_OSVVM_MSG_ID_PANELS : boolean := TRUE;
type t_msg_id_indent is array (t_msg_id'left to t_msg_id'right) of string(1 to 4);
constant C_MSG_ID_INDENT : t_msg_id_indent := (
ID_IMMEDIATE_CMD_WAIT => " ..",
ID_CMD_INTERPRETER => " " & NUL & NUL,
ID_CMD_INTERPRETER_WAIT => " ..",
ID_CMD_EXECUTOR => " " & NUL & NUL,
ID_CMD_EXECUTOR_WAIT => " ..",
ID_UVVM_SEND_CMD => "->" & NUL & NUL,
ID_UVVM_CMD_ACK => " ",
others => "" & NUL & NUL & NUL & NUL
);
constant C_MSG_DELIMITER : character := ''';
-------------------------------------------------------------------------
-- Alert counters
-------------------------------------------------------------------------
-- Default values. These can be overwritten in each sequencer by using
-- set_alert_attention or set_alert_stop_limit (see quick ref).
constant C_DEFAULT_ALERT_ATTENTION : t_alert_attention := (others => REGARD);
-- 0 = Never stop
constant C_DEFAULT_STOP_LIMIT : t_alert_counters := (note to manual_check => 0,
others => 1);
-------------------------------------------------------------------------
-- Hierarchical alerts
-------------------------------------------------------------------------
constant C_ENABLE_HIERARCHICAL_ALERTS : boolean := false;
constant C_BASE_HIERARCHY_LEVEL : string(1 to 5) := "Total";
constant C_EMPTY_NODE : t_hierarchy_node := (" ",
(others => (others => 0)),
(others => 0),
(others => true));
-------------------------------------------------------------------------
-- Synchronisation
-------------------------------------------------------------------------
constant C_NUM_SYNC_FLAGS : positive := 100; -- Maximum number of sync flags
-------------------------------------------------------------------------
-- Deprecate
-------------------------------------------------------------------------
-- These values are used to indicate outdated sub-programs
constant C_DEPRECATE_SETTING : t_deprecate_setting := DEPRECATE_ONCE;
shared variable deprecated_subprogram_list : t_deprecate_list := (others=>(others => ' '));
------------------------------------------------------------------------
-- UVVM VVC Framework adaptations
------------------------------------------------------------------------
constant C_SCOPE : string := C_TB_SCOPE_DEFAULT & "(uvvm)";
signal global_show_msg_for_uvvm_cmd : boolean := true;
constant C_CMD_QUEUE_COUNT_MAX : natural := 20; -- (VVC Command queue) May be overwritten for dedicated VVC
constant C_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING;
constant C_CMD_QUEUE_COUNT_THRESHOLD : natural := 18;
constant C_RESULT_QUEUE_COUNT_MAX : natural := 20; -- (VVC Result queue) May be overwritten for dedicated VVC
constant C_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING;
constant C_RESULT_QUEUE_COUNT_THRESHOLD : natural := 18;
constant C_MAX_VVC_INSTANCE_NUM : natural := 20;
constant C_MAX_NUM_SEQUENCERS : natural := 10; -- Max number of sequencers
-- Maximum allowed length of VVC names
constant C_MAX_VVC_NAME_LENGTH : positive := 20;
-- Minimum width of vvc name and channel displayed in scope.
-- These combined + the length of instance + 2 (commas), cannot exceed C_LOG_SCOPE_WIDTH.
constant C_MINIMUM_CHANNEL_SCOPE_WIDTH : natural := 10;
constant C_MINIMUM_VVC_NAME_SCOPE_WIDTH : natural := 10;
constant C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER : natural := 2048;
constant C_NUMBER_OF_DATA_BUFFERS : natural := 10;
-- Default message Id panel intended for use in the VVCs
constant C_VVC_MSG_ID_PANEL_DEFAULT : t_msg_id_panel := (
ID_NEVER => DISABLED,
ID_UTIL_BURIED => DISABLED,
others => ENABLED
);
type t_data_source is ( -- May add more types of random ++ later
NA,
FROM_BUFFER,
RANDOM,
RANDOM_TO_BUFFER
);
type t_error_injection is ( -- May add more controlled error injection later
NA,
RANDOM_BIT_ERROR,
RANDOM_DATA_ERROR,
RANDOM_ADDRESS_ERROR
);
constant C_CMD_IDX_PREFIX : string := " [";
constant C_CMD_IDX_SUFFIX : string := "]";
type t_channel is ( -- NOTE: Add more types of channels when needed for a VVC
NA, -- When channel is not relevant
ALL_CHANNELS, -- When command shall be received by all channels
RX,
TX);
constant C_VVCT_ALL_INSTANCES, ALL_INSTANCES : integer := -2;
constant ALL_ENABLED_INSTANCES : integer := -3;
constant C_NUM_SEMAPHORE_LOCK_TRIES : natural := 500;
------------------------------------------------------------------------
-- Scoreboard adaptations
------------------------------------------------------------------------
constant C_MAX_QUEUE_INSTANCE_NUM : positive := 100; -- Maximum number of instances
constant C_SB_TAG_WIDTH : positive := 128; -- Number of characters in SB tag
constant C_SB_SOURCE_WIDTH : positive := 128; -- Number of characters in SB source element
constant C_SB_SLV_WIDTH : positive := 8; -- Width of the SLV in the predefined SLV SB
-- Default message Id panel intended for use in SB
constant C_SB_MSG_ID_PANEL_DEFAULT : t_msg_id_panel := (
ID_CTRL => ENABLED,
ID_DATA => DISABLED,
others => DISABLED
);
end package adaptations_pkg;
package body adaptations_pkg is
end package body adaptations_pkg;
| mit | 72fedb4eec53d5379c9f9c4252774655 | 0.58406 | 4.464575 | false | false | false | false |
makestuff/swled | fifo/vhdl/timer/timer.vhdl | 1 | 2,075 | --
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity timer is
generic (
-- This gives the number of bits to be counted when ceiling_in is zero
COUNTER_WIDTH : integer := 25;
-- This gives the number of bits in the ceiling value
CEILING_WIDTH : integer := 4
);
port(
clk_in : in std_logic;
ceiling_in : in std_logic_vector(CEILING_WIDTH-1 downto 0);
tick_out : out std_logic
);
end entity;
architecture rtl of timer is
constant TOP_BIT : natural := 2**CEILING_WIDTH - 1;
function reverse(fwd : in std_logic_vector) return std_logic_vector is
variable result : std_logic_vector(TOP_BIT downto 0);
begin
for i in result'range loop
result(i) := fwd(COUNTER_WIDTH-i);
end loop;
return result;
end;
signal count, count_next : std_logic_vector(COUNTER_WIDTH downto 0) := (others => '0');
signal revCount : std_logic_vector(TOP_BIT downto 0);
begin
-- Infer registers
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
count <= count_next;
end if;
end process;
revCount <= reverse(count);
process(count, revCount, ceiling_in)
begin
if ( revCount(to_integer(unsigned(ceiling_in))) = '0' ) then
count_next <= std_logic_vector(unsigned(count) + 1);
tick_out <= '0';
else
count_next <= (others => '0');
tick_out <= '1';
end if;
end process;
end architecture;
| gpl-3.0 | d094bcab17951cdf9483aae663290bdd | 0.698313 | 3.288431 | false | false | false | false |
chibby0ne/vhdl-book | Chapter6/basic_counter_dir/basic_counter.vhd | 1 | 812 | -- author: Antonio Gutierrez
-- date: 03/10/13
-- description: basic counter
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------
entity counter is
--generic declarations
port (
clk: in std_logic;
count: out integer range 0 to 9);
end entity counter;
--------------------------------------
architecture counter of counter is
--signals and declarations
begin
counting: process (clk)
variable temp: integer range 0 to 10;
begin
if (clk'event and clk = '1') then
temp := temp + 1;
if (temp = 10) then
temp := 0;
end if;
end if;
count <= temp;
end process counting;
end architecture counter;
--------------------------------------
| gpl-3.0 | 606c18a947c933f2036589690e00679a | 0.485222 | 4.862275 | false | false | false | false |
chibby0ne/vhdl-book | Chapter9/example9_1_dir/example9_1.vhd | 1 | 1,112 | --!
--! @file: example9_1.vhd
--! @brief: function max in an architecture
--! @author: Antonio Gutierrez
--! @date: 2013-11-27
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity comparator is
--generic declarations
port (
a, b, c: in integer range 0 to 255;
y: out integer range 0 to 255);
end entity comparator;
--------------------------------------
architecture circuit of comparator is
function max(in1, in2, in3 : integer) return boolean is
begin
-- check that in-out signal ranges coincide
assert (y'left = a'left and y'left = b'left and y'left = c'left and y'right = a'right and y'right = b'right and y'right = c'right)
-- find maximum
if (in1 >= in2 and in1 >= in3) then
return in1;
elsif (in2 >= in1 and in2 >= in3) then
return in2;
else
return in3;
end if;
end function max;
begin
y <= max(a, b, c);
end architecture circuit;
--------------------------------------
| gpl-3.0 | 21bdadfe3119cb52caebcc93f63fe5d0 | 0.519784 | 3.915493 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/LDPC/Q16_8_CondInv.vhd | 1 | 1,378 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------
-- synthesis translate_off
library ims;
use ims.coprocessor.all;
-- synthesis translate_on
-------------------------------------------------------------------------
ENTITY Q16_8_CondInv is
PORT (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END;
ARCHITECTURE rtl of Q16_8_CondInv IS
BEGIN
-------------------------------------------------------------------------
-- synthesis translate_off
PROCESS
BEGIN
WAIT FOR 1 ns;
printmsg("(IMS) Q16_8_CondInv : ALLOCATION OK !");
WAIT;
END PROCESS;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
PROCESS (INPUT_1, INPUT_2)
VARIABLE OP1 : SIGNED(15 downto 0);
VARIABLE OP2 : SIGNED(15 downto 0);
BEGIN
OP1 := SIGNED(INPUT_2(15 downto 0));
OP2 := -OP1;
IF( INPUT_1(0) = '0' ) THEN
OUTPUT_1 <= STD_LOGIC_VECTOR( RESIZE(OP2,32) );
ELSE
OUTPUT_1 <= STD_LOGIC_VECTOR( RESIZE(OP1,32) );
END IF;
END PROCESS;
-------------------------------------------------------------------------
END;
| gpl-3.0 | 7057ed73088d85e9d9d055a4a6240d27 | 0.433237 | 4.005814 | false | false | false | false |
karvonz/Mandelbrot | vhdlpur_vincent/test/ADDR_calculator.vhd | 1 | 1,633 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:52:04 05/20/2016
-- Design Name:
-- Module Name: ADDR_calculator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use WORK.CONSTANTS.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ADDR_calculator is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
data_write : in STD_LOGIC;
endcalcul : in STD_LOGIC;
ADDRout : out STD_LOGIC_VECTOR (ADDR_BIT_MUX-1 downto 0));
end ADDR_calculator;
architecture Behavioral of ADDR_calculator is
Signal ADDR : unsigned(ADDR_BIT_MUX-1 downto 0);
begin
ADDRmanagement : process(clk,reset, data_write, endcalcul)
begin
if reset='1' then
ADDR<=(others=>'0'); --to_unsigned(15999, 14);
elsif rising_edge(clk) then
if endcalcul='1' then
ADDR<=(others=>'0');
else
if data_write = '1' then
if ADDR = NBR_PIXEL then
ADDR<=(others=>'0');
else
ADDR<=ADDR+1;
end if;
end if;
end if;
end if;
end process;
ADDRout<=std_logic_vector(ADDR);
end Behavioral;
| gpl-3.0 | 045b83638b58bbd86027822ef4f648f7 | 0.597061 | 3.628889 | false | false | false | false |
chibby0ne/vhdl-book | Chapter7/exercise7_5_dir/exercise7_5.vhd | 1 | 1,797 | --!
--! @file: exericse7_5.vhd
--! @brief:
--! @author: Antonio Gutierrez
--! @date: 2013-10-29
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity slow_counter is
generic (fclk: integer := 50_000_000);
port (
clk, rst: in std_logic;
ssd: out std_logic_vector(6 downto 0));
end entity slow_counter;
--------------------------------------
architecture counter of slow_counter is
--signals and declarations
begin
proc: process (clk, rst)
variable counter1: natural range 0 to fclk := 0;
variable counter2: natural range 0 to 10 := 0;
begin
-- counter:
if (rst = '1') then
counter1 := 0;
counter2 := 0;
elsif (clk'event and clk = '1') then
counter1 := counter1 + 1;
if (counter1 := fclk) then
counter1 := 0;
counter2 := counter2 + 1;
if (counter2 = 10) then
counter := 0;
end if;
end if;
-- SSD driver:
ssdriver: case counter2 is
when 0 => ssd <= "0000001";
when 1 => ssd <= "1011111";
when 2 => ssd <= "0010010";
when 3 => ssd <= "0000110";
when 4 => ssd <= "1001100";
when 5 => ssd <= "0100100";
when 6 => ssd <= "0100000";
when 7 => ssd <= "0001111";
when 8 => ssd <= "0000000";
when 8 => ssd <= "0000100";
when others => ssd <= "0110000";
end case ssdriver;
end if;
end process proc;
end architecture counter;
--------------------------------------
| gpl-3.0 | 23a0501229540f0c9b998bc4549f965c | 0.435726 | 4.437037 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/memory_64k_simu.vhd | 1 | 4,783 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:40:23 07/17/2011
-- Design Name:
-- Module Name: memory_64k - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
USE std.textio.ALL;
ENTITY memory_64k IS
PORT (
clk : IN STD_LOGIC;
addr_in : IN STD_LOGIC_VECTOR (31 DOWNTO 2);
data_in : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
enable : IN STD_LOGIC;
we_select : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data_out : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END memory_64k;
ARCHITECTURE Behavioral OF memory_64k IS
CONSTANT ADDRESS_WIDTH : NATURAL := 17; -- 2**X = NOMBRE D'OCTETS DE LA MEMOIRE
-- 14 => 16ko of memory
-- 15 => 32ko of memory
-- 16 => 64ko of memory
-- 17 => 128ko of memory
TYPE ptorage_array IS ARRAY(NATURAL RANGE 0 TO (2 ** ADDRESS_WIDTH) / 4 - 1) OF bit_vector(7 DOWNTO 0);
-- TYPE memoire IS ARRAY(0 TO TAILLE_LOADER-1) OF bit_vector(7 DOWNTO 0);
IMPURE FUNCTION load_memoire (filename : IN string; byte : IN integer) RETURN ptorage_array IS
FILE ram_file : text IS IN filename;
VARIABLE line_name : line;
VARIABLE line_temp : bit_vector(31 DOWNTO 0);
VARIABLE ram_name : ptorage_array;
BEGIN
FOR I IN ptorage_array'range LOOP
IF (NOT endfile(ram_file)) THEN
readline(ram_file, line_name);
read (line_name, line_temp);
IF(byte = 1) THEN
ram_name(I) := line_temp(31 DOWNTO 24);
ELSIF(byte = 2) THEN
ram_name(I) := line_temp(23 DOWNTO 16);
ELSIF(byte = 3) THEN
ram_name(I) := line_temp(15 DOWNTO 8);
ELSIF(byte = 4) THEN
ram_name(I) := line_temp(7 DOWNTO 0);
END IF;
END IF;
END LOOP;
RETURN ram_name;
END FUNCTION;
SIGNAL memBank1 : ptorage_array := load_memoire("../prog_bin.txt", 1);
SIGNAL memBank2 : ptorage_array := load_memoire("../prog_bin.txt", 2);
SIGNAL memBank3 : ptorage_array := load_memoire("../prog_bin.txt", 3);
SIGNAL memBank4 : ptorage_array := load_memoire("../prog_bin.txt", 4);
BEGIN
process (CLK)
VARIABLE index : INTEGER RANGE 0 TO (2**(ADDRESS_WIDTH-2)-1) := 0;
begin
if CLK'event and CLK = '1' then
if enable = '1' then
index := conv_integer(addr_in(ADDRESS_WIDTH-1 DOWNTO 2));
if We_select(0) = '1' then
memBank1(index) <= to_bitvector(data_in(7 DOWNTO 0));
end if;
data_out(7 DOWNTO 0) <= to_stdlogicvector(memBank1(index));
end if;
end if;
end process;
process (CLK)
VARIABLE index : INTEGER RANGE 0 TO (2**(ADDRESS_WIDTH-2)-1) := 0;
begin
if CLK'event and CLK = '1' then
if enable = '1' then
index := conv_integer(addr_in(ADDRESS_WIDTH-1 DOWNTO 2));
if We_select(1) = '1' then
memBank2(index) <= to_bitvector(data_in(15 DOWNTO 8));
end if;
data_out(15 DOWNTO 8) <= to_stdlogicvector(memBank2(index));
end if;
end if;
end process;
process (CLK)
VARIABLE index : INTEGER RANGE 0 TO (2**(ADDRESS_WIDTH-2)-1) := 0;
begin
if CLK'event and CLK = '1' then
if enable = '1' then
index := conv_integer(addr_in(ADDRESS_WIDTH-1 DOWNTO 2));
if We_select(2) = '1' then
memBank3(index) <= to_bitvector(data_in(23 DOWNTO 16));
end if;
data_out(23 DOWNTO 16) <= to_stdlogicvector(memBank3(index));
end if;
end if;
end process;
process (CLK)
VARIABLE index : INTEGER RANGE 0 TO (2**(ADDRESS_WIDTH-2)-1) := 0;
begin
if CLK'event and CLK = '1' then
if enable = '1' then
index := conv_integer(addr_in(ADDRESS_WIDTH-1 DOWNTO 2));
if We_select(3) = '1' then
memBank4(index) <= to_bitvector(data_in(31 DOWNTO 24));
end if;
data_out(31 DOWNTO 24) <= to_stdlogicvector(memBank4(index));
end if;
end if;
end process;
END Behavioral;
| gpl-3.0 | 2078b8559c57f97107ee4d244bb3183c | 0.516412 | 3.727981 | false | false | false | false |
chibby0ne/vhdl-book | Chapter5/exercise5_2_dir/exercise5_2.vhd | 1 | 1,267 | --!
--! @file: exercise5_2.vhd
--! @brief:
--! @author: Antonio Gutierrez
--! @date: 2013-10-23
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------
entity dual_edge_ff is
--generic declarations
port (
d: in std_logic;
clk: in std_logic;
q: out std_logic);
end entity dual_edge_ff;
--------------------------------------
architecture circuit of dual_edge_ff is
signal p: std_logic;
signal r: std_logic;
signal q_p: std_logic;
signal q_r: std_logic;
begin
-- positive edge flip flop
p <= d when clk = '0' else p;
q_p <= p when clk = '1' else q_p;
-- negative edge flip flop
r <= d when clk = '1' else r;
q_r <= r when clk = '0' else q_r;
-- multiplexer for output
q <= q_p when clk = '1' else q_r;
end architecture circuit;
--------------------------------------
-- according to the example 7.6 of book
architecture circuit1 of dual_edge_ff is
signal q1: std_logic;
signal q2: std_logic;
begin
q1 <= d when clk = '1' else q1;
q2 <= d when clk = '0' else q2;
q <= q1 when clk = '0' else q2;
end architecture circuit;
--------------------------------------
| gpl-3.0 | 60a0609db3c0152dca91eee32ec6fe43 | 0.505919 | 3.461749 | false | false | false | false |
chibby0ne/vhdl-book | Chapter8/exercise8_2_dir/exercise8_2.vhd | 1 | 1,405 | --!
--! @file: exercise8_2.vhd
--! @brief: circuilar shift with compenet #1 constant width
--! @author: Antonio Gutierrez
--! @date: 2013-11-26
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
library work;
use work.my_components.all;
-- Main code
--------------------------------------
entity exercise8_2 is
generic (M: integer := 5); -- num of stages
port (
clk, load: in std_logic;
d: in twoD(0 to M-1, N-1 downto 0);
q: buffer twoD(0 to M-1, N-1 downto 0));
constant N: integer := 8; -- bits per stage
end entity exercise8_2;
--------------------------------------
architecture circuit of exercise8_2 is
signal u: twoD(0 to M-1, N-1 downto 0); -- output of muxes
signal v: twoD(0 to M-1, N-1 downto 0); -- output of ffs
begin
gen1: for i in N-1 downto 0 generate -- width
gen2: for j in 0 to M-1 generate -- length
mux1: mux port map (
a => d(i, j),
b => v(i, M-1( - j)),
sel => load,
q => u(i, j)
);
dff1: flipflop port map (
d => u(i, j),
clk => clk,
q => v(i, j)
);
end generate gen2;
end generate gen1;
end architecture circuit;
--------------------------------------
| gpl-3.0 | 3a7ec2f3f951b0eca602afc6c7a64aec | 0.455516 | 3.716931 | false | false | false | false |
siam28/neppielight | dvid_out/tmds_encoder.vhd | 2 | 4,194 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Description: TMDS Encoder
-- 8 bits colour, 2 control bits and one blanking bits in
-- 10 bits of TMDS encoded data out
-- Clocked at the pixel clock
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TMDS_encoder is
Port ( clk : in STD_LOGIC;
data : in STD_LOGIC_VECTOR (7 downto 0);
c : in STD_LOGIC_VECTOR (1 downto 0);
blank : in STD_LOGIC;
encoded : out STD_LOGIC_VECTOR (9 downto 0));
end TMDS_encoder;
architecture Behavioral of TMDS_encoder is
signal xored : STD_LOGIC_VECTOR (8 downto 0);
signal xnored : STD_LOGIC_VECTOR (8 downto 0);
signal ones : STD_LOGIC_VECTOR (3 downto 0);
signal data_word : STD_LOGIC_VECTOR (8 downto 0);
signal data_word_inv : STD_LOGIC_VECTOR (8 downto 0);
signal data_word_disparity : STD_LOGIC_VECTOR (3 downto 0);
signal dc_bias : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
begin
-- Work our the two different encodings for the byte
xored(0) <= data(0);
xored(1) <= data(1) xor xored(0);
xored(2) <= data(2) xor xored(1);
xored(3) <= data(3) xor xored(2);
xored(4) <= data(4) xor xored(3);
xored(5) <= data(5) xor xored(4);
xored(6) <= data(6) xor xored(5);
xored(7) <= data(7) xor xored(6);
xored(8) <= '1';
xnored(0) <= data(0);
xnored(1) <= data(1) xnor xnored(0);
xnored(2) <= data(2) xnor xnored(1);
xnored(3) <= data(3) xnor xnored(2);
xnored(4) <= data(4) xnor xnored(3);
xnored(5) <= data(5) xnor xnored(4);
xnored(6) <= data(6) xnor xnored(5);
xnored(7) <= data(7) xnor xnored(6);
xnored(8) <= '0';
-- Count how many ones are set in data
ones <= "0000" + data(0) + data(1) + data(2) + data(3)
+ data(4) + data(5) + data(6) + data(7);
-- Decide which encoding to use
process(ones, data(0), xnored, xored)
begin
if ones > 4 or (ones = 4 and data(0) = '0') then
data_word <= xnored;
data_word_inv <= NOT(xnored);
else
data_word <= xored;
data_word_inv <= NOT(xored);
end if;
end process;
-- Work out the DC bias of the dataword;
data_word_disparity <= "1100" + data_word(0) + data_word(1) + data_word(2) + data_word(3)
+ data_word(4) + data_word(5) + data_word(6) + data_word(7);
-- Now work out what the output should be
process(clk)
begin
if rising_edge(clk) then
if blank = '1' then
-- In the control periods, all values have and have balanced bit count
case c is
when "00" => encoded <= "1101010100";
when "01" => encoded <= "0010101011";
when "10" => encoded <= "0101010100";
when others => encoded <= "1010101011";
end case;
dc_bias <= (others => '0');
else
if dc_bias = "00000" or data_word_disparity = 0 then
-- dataword has no disparity
if data_word(8) = '1' then
encoded <= "01" & data_word(7 downto 0);
dc_bias <= dc_bias + data_word_disparity;
else
encoded <= "10" & data_word_inv(7 downto 0);
dc_bias <= dc_bias - data_word_disparity;
end if;
elsif (dc_bias(3) = '0' and data_word_disparity(3) = '0') or
(dc_bias(3) = '1' and data_word_disparity(3) = '1') then
encoded <= '1' & data_word(8) & data_word_inv(7 downto 0);
dc_bias <= dc_bias + data_word(8) - data_word_disparity;
else
encoded <= '0' & data_word;
dc_bias <= dc_bias - data_word_inv(8) + data_word_disparity;
end if;
end if;
end if;
end process;
end Behavioral; | gpl-2.0 | 0c3e850de8f8673b5a6d98f725cc4383 | 0.500954 | 3.581554 | false | false | false | false |
AlmuHS/VHDL-Binary-Clock | Reloj.vhd | 1 | 3,949 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Almudena Garcia Jurado-Centurion, based on vhdlguru's digital clock code.
--
-- Create Date: 22:54:18 02/12/2016
-- Design Name:
-- Module Name: Reloj - Behavioral
-- Project Name: RelojBinario
-- Target Devices: Papilio One 500K
-- Tool versions:
-- Description: Binary Clock. Show hours, minutes and seconds using binary system
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments: Original code from http://vhdlguru.blogspot.com.es/2010/03/digital-clock-in-vhdl.html
-- Adapted for Papilio One 500K
--
----------------------------------------------------------------------------------
--Copyright (C) 2016 Almudena Garcia Jurado-Centurion
--This program is free software: you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation, either version 3 of the License, or
--(at your option) any later version.
--This program is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License
--along with this program. If not, see <http://www.gnu.org/licenses/>
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
entity digi_clk is
port (clk1 : in std_logic;
seconds : inout std_logic_vector(5 downto 0);
minutes : inout std_logic_vector(5 downto 0);
hours : inout std_logic_vector(3 downto 0);
set_hour: in std_logic;
set_minutes: in std_logic;
set_t: in std_logic;
set_enable: out std_logic
);
end digi_clk;
architecture Behavioral of digi_clk is
signal min_set, sec_clk, min_clk: integer range 0 to 60 := 0;
signal hour_set, hour_clk: integer range 0 to 12 := 0;
signal count : integer := 1;
signal clk : std_logic :='0';
constant clock: std_logic := '0';
constant set_time: std_logic := '1';
signal state: std_logic := clock;
begin
seconds <= conv_std_logic_vector(sec_clk,6) when(state = clock) else conv_std_logic_vector(0,6);
minutes <= conv_std_logic_vector(min_clk,6) when(state = clock and min_clk > min_set) else conv_std_logic_vector(min_set, 6);
hours <= conv_std_logic_vector(hour_clk,4) when(state = clock and hour_clk > hour_set) else conv_std_logic_vector(hour_set,4);
set_enable <= state;
transitions: process(set_t)
begin
if(set_t = '1') then
case state is
when clock => state <= set_time;
when set_time => state <= clock;
when others => state <= clock;
end case;
end if;
end process;
process(set_hour, set_minutes, state)
begin
if(state = set_time) then
if(set_hour = '1') then
if(hour_set = 11) then
hour_set <= 0;
else
hour_set <= hour_set + 1;
end if;
end if;
if(set_minutes='1') then
if(min_set < 59) then
min_set <= min_set + 1;
else min_set <= 0;
end if;
end if;
end if;
end process;
--clk generation.For 32 MHz clock this generates 1 Hz clock.
process(clk1)
begin
if(clk1'event and clk1='1') then
count <=count+1;
if(count = 16000000) then
clk <= not clk;
count <=1;
end if;
end if;
end process;
process(clk) --period of clk is 1 second.
begin
if(clk'event and clk='1') then
min_clk <= conv_integer(minutes);
hour_clk <= conv_integer(hours);
if(sec_clk < 59) then
sec_clk <= sec_clk + 1;
else
sec_clk <= 0;
if(min_clk < 59) then min_clk <= min_clk + 1;
else
min_clk <= 0;
if(hour_clk < 12) then
hour_clk <= hour_clk + 1;
else hour_clk <= 0;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 7287697e30349fa5516a85f0dd1bfe91 | 0.632312 | 3.156675 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Instruction_Memory/simulation/Instruction_Memory_tb_stim_gen.vhd | 1 | 11,025 | --------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Stimulus Generator For ROM Configuration
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Instruction_Memory_tb_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For ROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.Instruction_Memory_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_ROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_ROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_ROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.Instruction_Memory_TB_PKG.ALL;
ENTITY Instruction_Memory_TB_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
A : OUT STD_LOGIC_VECTOR(12-1 downto 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (31 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END Instruction_Memory_TB_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF Instruction_Memory_TB_STIM_GEN IS
FUNCTION std_logic_vector_len(
hex_str : STD_LOGIC_VECTOR;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR(return_width DOWNTO 0) := (OTHERS => '0');
VARIABLE tmp_z : STD_LOGIC_VECTOR(return_width-(hex_str'LENGTH) DOWNTO 0) := (OTHERS => '0');
BEGIN
tmp := tmp_z & hex_str;
RETURN tmp(return_width-1 DOWNTO 0);
END std_logic_vector_len;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0):= std_logic_vector_len("0",32);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (4095 downto 0) of std_logic_vector(31 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF(input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory(
C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Distributed Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(1,
1,
"Instruction_Memory.mif",
DEFAULT_DATA,
32,
4096);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_AGEN_INST:ENTITY work.Instruction_Memory_TB_AGEN
GENERIC MAP( C_MAX_DEPTH =>4096 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA(2),
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => check_read_addr
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(2) ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(2)='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(11 DOWNTO 0) <= READ_ADDR(11 DOWNTO 0);
A <= READ_ADDR_INT ;
CHECK_DATA(0) <= DO_READ;
RD_AGEN_INST:ENTITY work.Instruction_Memory_TB_AGEN
GENERIC MAP( C_MAX_DEPTH => 4096 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_EN_REG: FOR I IN 0 TO 2 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(0)
);
END GENERATE DFF_RIGHT;
DFF_CE_OTHERS: IF ((I>0) AND (I<2)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(I+1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(I)
);
END GENERATE DFF_CE_OTHERS;
END GENERATE BEGIN_EN_REG;
END ARCHITECTURE;
| mit | 4185c31e7b4365adc19554d337559c1b | 0.576417 | 3.760232 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/OTHERS/PGDC_32b.vhd | 1 | 4,449 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:18:09 02/17/2011
-- Design Name:
-- Module Name: PGDC_32b - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.conversion.all;
entity PGDC_32b is
PORT(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
start : in STD_LOGIC;
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
working : out std_logic;
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end PGDC_32b;
architecture Behavioral of PGDC_32b is
signal A : std_logic_vector(31 downto 0);
signal B : std_logic_vector(31 downto 0);
signal state : std_logic_vector(1 downto 0);
begin
-------------------------------------------------------------------------
-- synthesis translate_off
process
begin
wait for 1 ns;
ASSERT false REPORT "(IMS) PGDC_32b : ALLOCATION OK !";
wait;
end process;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
REG : process(clk, rst)
variable min : std_logic_vector(31 downto 0);
variable max : std_logic_vector(31 downto 0);
variable res : std_logic_vector(31 downto 0);
variable decision : std_logic;
begin
if (rst = '1') then
state <= "00";
elsif clk'event and clk = '1' then
case state is
-----------------------------------------------------------------
-- ON ATTEND LA COMMANDE DE START
-----------------------------------------------------------------
when "00" =>
if (start = '1') then
A <= INPUT_1;
B <= INPUT_2;
state <= "01";
--REPORT "TIME START";
--printmsg("(PGDC) ===> (000) THE START SIGNAL HAS BEEN RECEIVED !");
--printmsg("(PGDC) ===> (000) MEMORISATION PROCESS (" & to_int_str(INPUT_1,6) & ")");
--printmsg("(PGDC) ===> (000) MEMORISATION PROCESS (" & to_int_str(INPUT_2,6) & ")");
else
A <= A;
B <= A;
state <= "00";
end if;
-----------------------------------------------------------------
-- ON COMMENCE LE CALCUL
-----------------------------------------------------------------
when "01" =>
-- ON CHOISI LES OPERANDES POUR LE CALCUL A VENIR
if( SIGNED(A) > SIGNED(B) ) then
decision := '1';
min := B;
max := A;
else
decision := '0';
min := A;
max := B;
end if;
-- ON REALISE LA SOUSTRACTION DU GRAND MOINS LE PETIT
res := STD_LOGIC_VECTOR(SIGNED(max) - SIGNED(min));
-- ON MEMORISE LE RESULTAT DU CALCUL
if( decision = '1' ) then
A <= res;
B <= B;
else
A <= A;
B <= res;
end if;
state <= "10";
-----------------------------------------------------------------
-- ON TEST LES DONNEES (FIN D'ITERATION)
-----------------------------------------------------------------
when "10" =>
if(SIGNED(A) = SIGNED(B)) then
state <= "00";
elsif( SIGNED(A) = TO_SIGNED(0,32) ) then
state <= "00";
elsif( SIGNED(B) = TO_SIGNED(0,32) ) then
A <= STD_LOGIC_VECTOR(TO_SIGNED(0,32));
state <= "00";
else
state <= "01";
end if;
when others =>
state <= "00";
end case;
end if; -- if clock
end process;
-------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
-- ON PLACE LA SORTIE WORKING A '1' DES QUE LE CALCUL COMMENCE (RECEPTION DU SIGNAL START) ET TANT QUE
-- LE CALCUL EST EN COURS (STATE /= WAITING)
working <= '1' WHEN state /= "000" ELSE start;
OUTPUT_1 <= A;
------------------------------------------------------------------------------------------------------
end Behavioral;
| gpl-3.0 | b21a35a66170ff11576b0dfe887ae194 | 0.398741 | 3.96171 | false | false | false | false |
chibby0ne/vhdl-book | Chapter6/dff_reset_clear_dir/dff_reset_clear.vhd | 1 | 1,083 | -- author: Antonio Gutierrez
-- date: 03/10/13
-- description: dff with clk and clear
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------
entity dff is
--generic declarations
port (
d1, d2, clk, rst, clr: in std_logic;
q1, q2: out std_logic);
end entity dff;
--------------------------------------
architecture flipflops of dff is
--signals and declarations
begin
---- DFF figure 6.1(c)
with_reset: process (clk, rst)
--declarativepart
begin
if (rst = '1') then
q1 <= '0';
elsif (clk'event and clk = '1') then
q1 <= d1;
end if;
end process with_reset;
---- DFF figure 6.1(e)
with_clear: process (clk)
--declarativepart
begin
if (clk'event and clk = '1') then
if (clr = '1') then
q2 <= '0';
else
q2 <= d2;
end if;
end if;
end process with_clear;
end architecture flipflops;
--------------------------------------
| gpl-3.0 | 23251e103f584a50b37526566ae151a0 | 0.459834 | 4.133588 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/dist_mem_gen_v7_2/simulation/dist_mem_gen_v7_2_tb.vhd | 1 | 4,403 | --------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: dist_mem_gen_v7_2_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY dist_mem_gen_v7_2_tb IS
END ENTITY;
ARCHITECTURE dist_mem_gen_v7_2_tb_ARCH OF dist_mem_gen_v7_2_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
dist_mem_gen_v7_2_tb_synth_inst:ENTITY work.dist_mem_gen_v7_2_tb_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| mit | 112158e577a9d70067d7549bb2201220 | 0.605269 | 4.245902 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Font/simulation/Font_tb_stim_gen.vhd | 1 | 10,892 | --------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Stimulus Generator For ROM Configuration
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Font_tb_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For ROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.Font_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_ROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_ROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_ROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.Font_TB_PKG.ALL;
ENTITY Font_TB_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
A : OUT STD_LOGIC_VECTOR(12-1 downto 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (7 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END Font_TB_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF Font_TB_STIM_GEN IS
FUNCTION std_logic_vector_len(
hex_str : STD_LOGIC_VECTOR;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR(return_width DOWNTO 0) := (OTHERS => '0');
VARIABLE tmp_z : STD_LOGIC_VECTOR(return_width-(hex_str'LENGTH) DOWNTO 0) := (OTHERS => '0');
BEGIN
tmp := tmp_z & hex_str;
RETURN tmp(return_width-1 DOWNTO 0);
END std_logic_vector_len;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0):= std_logic_vector_len("0",8);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (4095 downto 0) of std_logic_vector(7 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF(input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory(
C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Distributed Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(1,
1,
"Font.mif",
DEFAULT_DATA,
8,
4096);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_AGEN_INST:ENTITY work.Font_TB_AGEN
GENERIC MAP( C_MAX_DEPTH =>4096 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA(2),
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => check_read_addr
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(2) ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(2)='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(11 DOWNTO 0) <= READ_ADDR(11 DOWNTO 0);
A <= READ_ADDR_INT ;
CHECK_DATA(0) <= DO_READ;
RD_AGEN_INST:ENTITY work.Font_TB_AGEN
GENERIC MAP( C_MAX_DEPTH => 4096 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_EN_REG: FOR I IN 0 TO 2 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(0)
);
END GENERATE DFF_RIGHT;
DFF_CE_OTHERS: IF ((I>0) AND (I<2)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(I+1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(I)
);
END GENERATE DFF_CE_OTHERS;
END GENERATE BEGIN_EN_REG;
END ARCHITECTURE;
| mit | 2aa865926bc66561e106f63354fe2b6d | 0.572071 | 3.737817 | false | false | false | false |
chibby0ne/vhdl-book | Chapter10/example10_5_dir/bin_to_gray_tb.vhd | 1 | 2,493 | library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
--------------------------------------
entity bin_to_gray_tb is
generic (period: TIME := 100 ns);
end entity bin_to_gray_tb;
--------------------------------------
architecture circuit of bin_to_gray_tb is
-- DUT declaration
component bin_to_gray is
port (
bin: in std_logic_vector(N-1 downto 0);
gray: out std_logic_vector(N-1 downto 0));
end component bin_to_gray;
-- signals declarations
signal b: std_logic_vector(2 downto 0);
signal g, gtest: std_logic_vector(2 downto 0);
file f: text open read_mode is "template.txt";
begin
-- DUT instantiation
dut: bin_to_gray port map (
bin => b,
grey => g
);
-- output verification
proc: process
variable good_value: boolean;
variable space: character;
variable bfile, gfile: bit_vector(2 downto 0);
begin
-- read file line by line until end
wh: while not endfile(f) loop
readline(f, l);
-- read bin value
read(l, bfile, good_value);
-- check if type of value outputed is the same as in template
assert good_value
report "Improper value for 'bin' in file!"
severity failure;
-- convert same type as entity
b <= to_stdlogicvector(bfile);
-- get space from between and skip it
read(l, space);
-- read grey value expected
read(l, gfile, goodvalue);
-- check if type of value outputed is the same as in template
assert good_value
report "Improper value for 'gray' in file!"
severity failure;
-- convert grey value expected to same type as entity for correct comparison
gtest <= to_stdlogicvector(gfile);
-- compare and verify output from design vs. output expected
assert(gtest = g)
report "Data mismatch!"
severity failure;
wait for period;
end loop wh;
-- once the end of file is reach then have satisfied the testbench so no errors where found
assert false
report "No errors found!"
severity note;
wait;
end process proc;
end architecture circuit;
--------------------------------------
| gpl-3.0 | b672ba6f11ff0cf27138a173564b7f56 | 0.531889 | 4.757634 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Instruction_Memory/example_design/Instruction_Memory_exdes.vhd | 1 | 3,975 |
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
--
-- Description:
-- This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity Instruction_Memory_exdes is
PORT (
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
A : IN STD_LOGIC_VECTOR(12-1-(4*0*boolean'pos(12>4)) downto 0)
:= (OTHERS => '0')
);
end Instruction_Memory_exdes;
architecture xilinx of Instruction_Memory_exdes is
component Instruction_Memory is
PORT (
SPO : OUT STD_LOGIC_VECTOR(32-1 downto 0);
A : IN STD_LOGIC_VECTOR(12-1-(4*0*boolean'pos(12>4)) downto 0)
:= (OTHERS => '0')
);
end component;
begin
dmg0 : Instruction_Memory
port map (
SPO => SPO,
A => A
);
end xilinx;
| mit | 15c2100a6040b87b3933fd0ca54eaeae | 0.576101 | 4.632867 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/LDPC/Q16_8_DoubleMini.vhd | 1 | 1,697 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------
-- synthesis translate_off
library ims;
use ims.coprocessor.all;
-- synthesis translate_on
-------------------------------------------------------------------------
ENTITY Q16_8_DoubleMini is
PORT (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END;
ARCHITECTURE rtl of Q16_8_DoubleMini IS
BEGIN
-------------------------------------------------------------------------
-- synthesis translate_off
PROCESS
BEGIN
WAIT FOR 1 ns;
printmsg("(IMS) Q16_8_DoubleMini : ALLOCATION OK !");
WAIT;
END PROCESS;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
PROCESS (INPUT_1, INPUT_2)
VARIABLE OP1 : SIGNED(15 downto 0);
VARIABLE MIN1 : SIGNED(15 downto 0);
VARIABLE MIN2 : SIGNED(15 downto 0);
BEGIN
--
-- ON RECUPERE NOS OPERANDES
--
OP1 := SIGNED(INPUT_1(15 downto 0));
MIN1 := SIGNED(INPUT_2(31 downto 16));
MIN2 := SIGNED(INPUT_2(15 downto 0));
--
-- ON CALCULE LA VALEUR ABSOLUE DE L'ENTREE
--
OP1 := abs( OP1 );
--
-- ON CALCULE LE MIN QUI VA BIEN
--
IF OP1 < MIN1 THEN
MIN2 := MIN1;
MIN1 := OP1;
ELSIF OP1 < MIN2 THEN
MIN2 := OP1;
END IF;
OUTPUT_1 <= STD_LOGIC_VECTOR(MIN1) & STD_LOGIC_VECTOR(MIN2);
END PROCESS;
-------------------------------------------------------------------------
END;
| gpl-3.0 | 26c99923170113dffc015aa449575a91 | 0.458456 | 3.737885 | false | false | false | false |
siam28/neppielight | dvid_out/output_serialiser.vhd | 2 | 5,345 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: output_serialiser - Behavioral
-- Description: A 5-bit SDR output serialiser
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity output_serialiser is
Port ( clk_load : in STD_LOGIC;
clk_output : in STD_LOGIC;
strobe : in STD_LOGIC;
ser_data : in STD_LOGIC_VECTOR (4 downto 0);
ser_output : out STD_LOGIC);
end output_serialiser;
architecture Behavioral of output_serialiser is
signal clk0, clk1, clkdiv : std_logic;
signal cascade1, cascade2, cascade3, cascade4 : std_logic;
begin
clkdiv <= clk_load;
clk0 <= clk_output;
clk1 <= '0';
OSERDES2_master : OSERDES2
generic map (
BYPASS_GCLK_FF => FALSE, -- Bypass CLKDIV syncronization registers (TRUE/FALSE)
DATA_RATE_OQ => "SDR", -- Output Data Rate ("SDR" or "DDR")
DATA_RATE_OT => "SDR", -- 3-state Data Rate ("SDR" or "DDR")
DATA_WIDTH => 5, -- Parallel data width (2-8)
OUTPUT_MODE => "SINGLE_ENDED", -- "SINGLE_ENDED" or "DIFFERENTIAL"
SERDES_MODE => "MASTER", -- "NONE", "MASTER" or "SLAVE"
TRAIN_PATTERN => 0 -- Training Pattern (0-15)
) port map (
OQ => ser_output, -- 1-bit output: Data output to pad or IODELAY2
SHIFTOUT1 => cascade1, -- 1-bit output: Cascade data output
SHIFTOUT2 => cascade2, -- 1-bit output: Cascade 3-state output
SHIFTOUT3 => open, -- 1-bit output: Cascade differential data output
SHIFTOUT4 => open, -- 1-bit output: Cascade differential 3-state output
SHIFTIN1 => '1', -- 1-bit input: Cascade data input
SHIFTIN2 => '1', -- 1-bit input: Cascade 3-state input
SHIFTIN3 => cascade3, -- 1-bit input: Cascade differential data input
SHIFTIN4 => cascade4, -- 1-bit input: Cascade differential 3-state input
TQ => open, -- 1-bit output: 3-state output to pad or IODELAY2
CLK0 => CLK0, -- 1-bit input: I/O clock input
CLK1 => CLK1, -- 1-bit input: Secondary I/O clock input
CLKDIV => CLKDIV, -- 1-bit input: Logic domain clock input
-- D1 - D4: 1-bit (each) input: Parallel data inputs
D1 => ser_data(4),
D2 => '0',
D3 => '0',
D4 => '0',
IOCE => strobe, -- 1-bit input: Data strobe input
OCE => '1', -- 1-bit input: Clock enable input
RST => '0', -- 1-bit input: Asynchrnous reset input
-- T1 - T4: 1-bit (each) input: 3-state control inputs
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1', -- 1-bit input: 3-state clock enable input
TRAIN => '0' -- 1-bit input: Training pattern enable input
);
OSERDES2_slave : OSERDES2
generic map (
BYPASS_GCLK_FF => FALSE, -- Bypass CLKDIV syncronization registers (TRUE/FALSE)
DATA_RATE_OQ => "SDR", -- Output Data Rate ("SDR" or "DDR")
DATA_RATE_OT => "SDR", -- 3-state Data Rate ("SDR" or "DDR")
DATA_WIDTH => 5, -- Parallel data width (2-8)
OUTPUT_MODE => "SINGLE_ENDED", -- "SINGLE_ENDED" or "DIFFERENTIAL"
SERDES_MODE => "SLAVE", -- "NONE", "MASTER" or "SLAVE"
TRAIN_PATTERN => 0 -- Training Pattern (0-15)
) port map (
OQ => open, -- 1-bit output: Data output to pad or IODELAY2
SHIFTOUT1 => open, -- 1-bit output: Cascade data output
SHIFTOUT2 => open, -- 1-bit output: Cascade 3-state output
SHIFTOUT3 => cascade3, -- 1-bit output: Cascade differential data output
SHIFTOUT4 => cascade4, -- 1-bit output: Cascade differential 3-state output
SHIFTIN1 => cascade1, -- 1-bit input: Cascade data input
SHIFTIN2 => cascade2, -- 1-bit input: Cascade 3-state input
SHIFTIN3 => '1', -- 1-bit input: Cascade differential data input
SHIFTIN4 => '1', -- 1-bit input: Cascade differential 3-state input
TQ => open, -- 1-bit output: 3-state output to pad or IODELAY2
CLK0 => CLK0, -- 1-bit input: I/O clock input
CLK1 => CLK1, -- 1-bit input: Secondary I/O clock input
CLKDIV => CLKDIV, -- 1-bit input: Logic domain clock input
-- D1 - D4: 1-bit (each) input: Parallel data inputs
D1 => ser_data(0),
D2 => ser_data(1),
D3 => ser_data(2),
D4 => ser_data(3),
IOCE => strobe, -- 1-bit input: Data strobe input
OCE => '1', -- 1-bit input: Clock enable input
RST => '0', -- 1-bit input: Asynchrnous reset input
-- T1 - T4: 1-bit (each) input: 3-state control inputs
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1', -- 1-bit input: 3-state clock enable input
TRAIN => '0' -- 1-bit input: Training pattern enable input
);
end Behavioral;
| gpl-2.0 | fcd764da9df9e16e7f301dc49148e360 | 0.526473 | 3.719555 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/LDPC/Q16_8_OPR_CtoV_RAM.vhd | 1 | 48,498 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------
-- synthesis translate_off
library ims;
use ims.coprocessor.all;
use ims.conversion.all;
-- synthesis translate_on
-------------------------------------------------------------------------
ENTITY Q16_8_opr_CtoV_RAM is
PORT (
RESET : in STD_LOGIC;
CLOCK : in STD_LOGIC;
HOLDN : in std_ulogic;
WRITE_EN : in STD_LOGIC;
READ_EN : in STD_LOGIC;
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END;
architecture cRAM of Q16_8_opr_CtoV_RAM is
type ram_type is array (0 to 1824-1) of STD_LOGIC_VECTOR (15 downto 0);
type rom_type is array (0 to 1824-1) of UNSIGNED (10 downto 0);
signal RAM : ram_type;
constant ROM : rom_type:= (
TO_UNSIGNED( 75, 11), TO_UNSIGNED( 618, 11), TO_UNSIGNED( 732, 11), TO_UNSIGNED(1425, 11), TO_UNSIGNED(1500, 11), TO_UNSIGNED(1683, 11), TO_UNSIGNED( 84, 11), TO_UNSIGNED( 621, 11),
TO_UNSIGNED( 738, 11), TO_UNSIGNED(1428, 11), TO_UNSIGNED(1506, 11), TO_UNSIGNED(1614, 11), TO_UNSIGNED( 86, 11), TO_UNSIGNED( 624, 11), TO_UNSIGNED( 744, 11), TO_UNSIGNED(1437, 11),
TO_UNSIGNED(1488, 11), TO_UNSIGNED(1819, 11), TO_UNSIGNED( 12, 11), TO_UNSIGNED( 88, 11), TO_UNSIGNED( 627, 11), TO_UNSIGNED( 750, 11), TO_UNSIGNED(1440, 11), TO_UNSIGNED(1512, 11),
TO_UNSIGNED( 15, 11), TO_UNSIGNED( 90, 11), TO_UNSIGNED( 630, 11), TO_UNSIGNED( 756, 11), TO_UNSIGNED(1443, 11), TO_UNSIGNED(1524, 11), TO_UNSIGNED( 18, 11), TO_UNSIGNED( 92, 11),
TO_UNSIGNED( 633, 11), TO_UNSIGNED( 762, 11), TO_UNSIGNED(1446, 11), TO_UNSIGNED(1518, 11), TO_UNSIGNED( 21, 11), TO_UNSIGNED( 94, 11), TO_UNSIGNED( 636, 11), TO_UNSIGNED( 768, 11),
TO_UNSIGNED(1449, 11), TO_UNSIGNED(1542, 11), TO_UNSIGNED( 24, 11), TO_UNSIGNED( 96, 11), TO_UNSIGNED( 639, 11), TO_UNSIGNED( 774, 11), TO_UNSIGNED(1452, 11), TO_UNSIGNED(1548, 11),
TO_UNSIGNED( 27, 11), TO_UNSIGNED( 98, 11), TO_UNSIGNED( 642, 11), TO_UNSIGNED( 780, 11), TO_UNSIGNED(1455, 11), TO_UNSIGNED(1530, 11), TO_UNSIGNED( 30, 11), TO_UNSIGNED( 100, 11),
TO_UNSIGNED( 645, 11), TO_UNSIGNED( 786, 11), TO_UNSIGNED(1461, 11), TO_UNSIGNED(1536, 11), TO_UNSIGNED( 33, 11), TO_UNSIGNED( 102, 11), TO_UNSIGNED( 648, 11), TO_UNSIGNED( 792, 11),
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TO_UNSIGNED(1018, 11), TO_UNSIGNED(1132, 11), TO_UNSIGNED(1306, 11), TO_UNSIGNED(1739, 11), TO_UNSIGNED( 20, 11), TO_UNSIGNED( 291, 11), TO_UNSIGNED( 339, 11), TO_UNSIGNED(1024, 11),
TO_UNSIGNED(1135, 11), TO_UNSIGNED(1318, 11), TO_UNSIGNED(1775, 11), TO_UNSIGNED( 23, 11), TO_UNSIGNED( 293, 11), TO_UNSIGNED( 341, 11), TO_UNSIGNED(1030, 11), TO_UNSIGNED(1138, 11),
TO_UNSIGNED(1324, 11), TO_UNSIGNED(1781, 11), TO_UNSIGNED( 26, 11), TO_UNSIGNED( 295, 11), TO_UNSIGNED( 343, 11), TO_UNSIGNED(1036, 11), TO_UNSIGNED(1141, 11), TO_UNSIGNED(1336, 11),
TO_UNSIGNED(1745, 11), TO_UNSIGNED( 29, 11), TO_UNSIGNED( 297, 11), TO_UNSIGNED( 345, 11), TO_UNSIGNED(1042, 11), TO_UNSIGNED(1144, 11), TO_UNSIGNED(1330, 11), TO_UNSIGNED(1751, 11),
TO_UNSIGNED( 32, 11), TO_UNSIGNED( 299, 11), TO_UNSIGNED( 347, 11), TO_UNSIGNED(1048, 11), TO_UNSIGNED(1147, 11), TO_UNSIGNED(1354, 11), TO_UNSIGNED(1757, 11), TO_UNSIGNED( 35, 11),
TO_UNSIGNED( 301, 11), TO_UNSIGNED( 349, 11), TO_UNSIGNED(1054, 11), TO_UNSIGNED(1150, 11), TO_UNSIGNED(1360, 11), TO_UNSIGNED(1763, 11), TO_UNSIGNED( 38, 11), TO_UNSIGNED( 303, 11),
TO_UNSIGNED( 351, 11), TO_UNSIGNED(1060, 11), TO_UNSIGNED(1153, 11), TO_UNSIGNED(1342, 11), TO_UNSIGNED(1769, 11), TO_UNSIGNED( 41, 11), TO_UNSIGNED( 305, 11), TO_UNSIGNED( 353, 11),
TO_UNSIGNED(1066, 11), TO_UNSIGNED(1156, 11), TO_UNSIGNED(1348, 11), TO_UNSIGNED(1805, 11), TO_UNSIGNED( 44, 11), TO_UNSIGNED( 307, 11), TO_UNSIGNED( 355, 11), TO_UNSIGNED(1072, 11),
TO_UNSIGNED(1159, 11), TO_UNSIGNED(1372, 11), TO_UNSIGNED(1793, 11), TO_UNSIGNED( 47, 11), TO_UNSIGNED( 309, 11), TO_UNSIGNED( 357, 11), TO_UNSIGNED(1078, 11), TO_UNSIGNED(1162, 11),
TO_UNSIGNED(1378, 11), TO_UNSIGNED(1799, 11), TO_UNSIGNED( 50, 11), TO_UNSIGNED( 311, 11), TO_UNSIGNED( 359, 11), TO_UNSIGNED(1084, 11), TO_UNSIGNED(1165, 11), TO_UNSIGNED(1366, 11),
TO_UNSIGNED(1811, 11), TO_UNSIGNED( 53, 11), TO_UNSIGNED( 313, 11), TO_UNSIGNED( 361, 11), TO_UNSIGNED(1090, 11), TO_UNSIGNED(1168, 11), TO_UNSIGNED(1396, 11), TO_UNSIGNED(1787, 11),
TO_UNSIGNED( 10, 11), TO_UNSIGNED( 56, 11), TO_UNSIGNED( 315, 11), TO_UNSIGNED( 363, 11), TO_UNSIGNED(1096, 11), TO_UNSIGNED(1171, 11), TO_UNSIGNED(1384, 11), TO_UNSIGNED( 59, 11),
TO_UNSIGNED( 317, 11), TO_UNSIGNED( 365, 11), TO_UNSIGNED(1102, 11), TO_UNSIGNED(1174, 11), TO_UNSIGNED(1390, 11), TO_UNSIGNED(1817, 11), TO_UNSIGNED( 62, 11), TO_UNSIGNED( 134, 11),
TO_UNSIGNED( 140, 11), TO_UNSIGNED( 319, 11), TO_UNSIGNED( 367, 11), TO_UNSIGNED(1108, 11), TO_UNSIGNED(1177, 11), TO_UNSIGNED( 65, 11), TO_UNSIGNED( 82, 11), TO_UNSIGNED( 321, 11),
TO_UNSIGNED( 369, 11), TO_UNSIGNED(1114, 11), TO_UNSIGNED(1180, 11), TO_UNSIGNED(1691, 11), TO_UNSIGNED( 68, 11), TO_UNSIGNED( 323, 11), TO_UNSIGNED( 371, 11), TO_UNSIGNED(1120, 11),
TO_UNSIGNED(1183, 11), TO_UNSIGNED(1276, 11), TO_UNSIGNED(1715, 11), TO_UNSIGNED( 71, 11), TO_UNSIGNED( 325, 11), TO_UNSIGNED( 373, 11), TO_UNSIGNED( 982, 11), TO_UNSIGNED(1186, 11),
TO_UNSIGNED(1282, 11), TO_UNSIGNED(1703, 11), TO_UNSIGNED( 74, 11), TO_UNSIGNED( 327, 11), TO_UNSIGNED( 375, 11), TO_UNSIGNED( 988, 11), TO_UNSIGNED(1189, 11), TO_UNSIGNED(1288, 11),
TO_UNSIGNED(1709, 11), TO_UNSIGNED( 77, 11), TO_UNSIGNED( 329, 11), TO_UNSIGNED( 377, 11), TO_UNSIGNED( 994, 11), TO_UNSIGNED(1192, 11), TO_UNSIGNED(1270, 11), TO_UNSIGNED(1697, 11),
TO_UNSIGNED( 427, 11), TO_UNSIGNED( 475, 11), TO_UNSIGNED( 944, 11), TO_UNSIGNED(1025, 11), TO_UNSIGNED(1169, 11), TO_UNSIGNED(1343, 11), TO_UNSIGNED(1752, 11), TO_UNSIGNED( 429, 11),
TO_UNSIGNED( 477, 11), TO_UNSIGNED( 947, 11), TO_UNSIGNED(1031, 11), TO_UNSIGNED(1172, 11), TO_UNSIGNED(1349, 11), TO_UNSIGNED(1758, 11), TO_UNSIGNED( 431, 11), TO_UNSIGNED( 479, 11),
TO_UNSIGNED( 950, 11), TO_UNSIGNED(1037, 11), TO_UNSIGNED(1175, 11), TO_UNSIGNED(1373, 11), TO_UNSIGNED(1764, 11), TO_UNSIGNED( 433, 11), TO_UNSIGNED( 481, 11), TO_UNSIGNED( 953, 11),
TO_UNSIGNED(1043, 11), TO_UNSIGNED(1178, 11), TO_UNSIGNED(1379, 11), TO_UNSIGNED(1770, 11), TO_UNSIGNED( 435, 11), TO_UNSIGNED( 483, 11), TO_UNSIGNED( 956, 11), TO_UNSIGNED(1049, 11),
TO_UNSIGNED(1181, 11), TO_UNSIGNED(1367, 11), TO_UNSIGNED(1806, 11), TO_UNSIGNED( 437, 11), TO_UNSIGNED( 485, 11), TO_UNSIGNED( 959, 11), TO_UNSIGNED(1055, 11), TO_UNSIGNED(1184, 11),
TO_UNSIGNED(1397, 11), TO_UNSIGNED(1794, 11), TO_UNSIGNED( 439, 11), TO_UNSIGNED( 487, 11), TO_UNSIGNED( 962, 11), TO_UNSIGNED(1061, 11), TO_UNSIGNED(1187, 11), TO_UNSIGNED(1385, 11),
TO_UNSIGNED(1800, 11), TO_UNSIGNED( 441, 11), TO_UNSIGNED( 489, 11), TO_UNSIGNED( 965, 11), TO_UNSIGNED(1067, 11), TO_UNSIGNED(1190, 11), TO_UNSIGNED(1391, 11), TO_UNSIGNED(1812, 11),
TO_UNSIGNED( 135, 11), TO_UNSIGNED( 443, 11), TO_UNSIGNED( 491, 11), TO_UNSIGNED( 968, 11), TO_UNSIGNED(1073, 11), TO_UNSIGNED(1193, 11), TO_UNSIGNED(1788, 11), TO_UNSIGNED( 11, 11),
TO_UNSIGNED( 83, 11), TO_UNSIGNED( 445, 11), TO_UNSIGNED( 493, 11), TO_UNSIGNED( 971, 11), TO_UNSIGNED(1079, 11), TO_UNSIGNED(1124, 11), TO_UNSIGNED( 447, 11), TO_UNSIGNED( 495, 11),
TO_UNSIGNED( 974, 11), TO_UNSIGNED(1085, 11), TO_UNSIGNED(1127, 11), TO_UNSIGNED(1277, 11), TO_UNSIGNED(1818, 11), TO_UNSIGNED( 141, 11), TO_UNSIGNED( 449, 11), TO_UNSIGNED( 497, 11),
TO_UNSIGNED( 977, 11), TO_UNSIGNED(1091, 11), TO_UNSIGNED(1130, 11), TO_UNSIGNED(1283, 11), TO_UNSIGNED( 451, 11), TO_UNSIGNED( 499, 11), TO_UNSIGNED( 908, 11), TO_UNSIGNED(1097, 11),
TO_UNSIGNED(1133, 11), TO_UNSIGNED(1289, 11), TO_UNSIGNED(1692, 11), TO_UNSIGNED( 453, 11), TO_UNSIGNED( 501, 11), TO_UNSIGNED( 911, 11), TO_UNSIGNED(1103, 11), TO_UNSIGNED(1136, 11),
TO_UNSIGNED(1271, 11), TO_UNSIGNED(1716, 11), TO_UNSIGNED( 455, 11), TO_UNSIGNED( 503, 11), TO_UNSIGNED( 914, 11), TO_UNSIGNED(1109, 11), TO_UNSIGNED(1139, 11), TO_UNSIGNED(1301, 11),
TO_UNSIGNED(1704, 11), TO_UNSIGNED( 457, 11), TO_UNSIGNED( 505, 11), TO_UNSIGNED( 917, 11), TO_UNSIGNED(1115, 11), TO_UNSIGNED(1142, 11), TO_UNSIGNED(1295, 11), TO_UNSIGNED(1710, 11),
TO_UNSIGNED( 459, 11), TO_UNSIGNED( 507, 11), TO_UNSIGNED( 920, 11), TO_UNSIGNED(1121, 11), TO_UNSIGNED(1145, 11), TO_UNSIGNED(1313, 11), TO_UNSIGNED(1698, 11), TO_UNSIGNED( 461, 11),
TO_UNSIGNED( 509, 11), TO_UNSIGNED( 923, 11), TO_UNSIGNED( 983, 11), TO_UNSIGNED(1148, 11), TO_UNSIGNED(1307, 11), TO_UNSIGNED(1722, 11), TO_UNSIGNED( 463, 11), TO_UNSIGNED( 511, 11),
TO_UNSIGNED( 926, 11), TO_UNSIGNED( 989, 11), TO_UNSIGNED(1151, 11), TO_UNSIGNED(1319, 11), TO_UNSIGNED(1734, 11), TO_UNSIGNED( 465, 11), TO_UNSIGNED( 513, 11), TO_UNSIGNED( 929, 11),
TO_UNSIGNED( 995, 11), TO_UNSIGNED(1154, 11), TO_UNSIGNED(1325, 11), TO_UNSIGNED(1728, 11), TO_UNSIGNED( 467, 11), TO_UNSIGNED( 515, 11), TO_UNSIGNED( 932, 11), TO_UNSIGNED(1001, 11),
TO_UNSIGNED(1157, 11), TO_UNSIGNED(1337, 11), TO_UNSIGNED(1740, 11), TO_UNSIGNED( 469, 11), TO_UNSIGNED( 517, 11), TO_UNSIGNED( 935, 11), TO_UNSIGNED(1007, 11), TO_UNSIGNED(1160, 11),
TO_UNSIGNED(1331, 11), TO_UNSIGNED(1776, 11), TO_UNSIGNED( 471, 11), TO_UNSIGNED( 519, 11), TO_UNSIGNED( 938, 11), TO_UNSIGNED(1013, 11), TO_UNSIGNED(1163, 11), TO_UNSIGNED(1355, 11),
TO_UNSIGNED(1782, 11), TO_UNSIGNED( 473, 11), TO_UNSIGNED( 521, 11), TO_UNSIGNED( 941, 11), TO_UNSIGNED(1019, 11), TO_UNSIGNED(1166, 11), TO_UNSIGNED(1361, 11), TO_UNSIGNED(1746, 11)
);
SIGNAL READ_C : UNSIGNED(10 downto 0);
SIGNAL WRITE_C : UNSIGNED(10 downto 0);
SIGNAL ROM_ADR : UNSIGNED(10 downto 0);
SIGNAL cINPUT : STD_LOGIC_VECTOR (15 downto 0);
SIGNAL IN_BIS : STD_LOGIC_VECTOR (15 downto 0);
SIGNAL WE_BIS : STD_LOGIC;
SIGNAL OUT_BIS : STD_LOGIC_VECTOR (15 downto 0);
BEGIN
-------------------------------------------------------------------------
PROCESS (INPUT_1, INPUT_2)
VARIABLE OP1 : SIGNED(15 downto 0);
VARIABLE aOP1 : SIGNED(15 downto 0);
VARIABLE MIN1 : SIGNED(15 downto 0);
VARIABLE MIN2 : SIGNED(15 downto 0);
VARIABLE CST1 : SIGNED(15 downto 0);
VARIABLE CST2 : SIGNED(15 downto 0);
VARIABLE RESU : SIGNED(15 downto 0);
VARIABLE RESUp : SIGNED(15 downto 0);
VARIABLE iSIGN : STD_LOGIC;
VARIABLE sSIGN : STD_LOGIC;
BEGIN
OP1 := SIGNED( INPUT_1(15 downto 0)); -- DONNEE SIGNEE SUR 16 bits
MIN1 := SIGNED('0' & INPUT_2(30 downto 16)); -- DONNEE TJS POSITIVE SUR 16 BITS
MIN2 := SIGNED('0' & INPUT_2(14 downto 0)); -- DONNEE TJS POSITIVE SUR 16 BITS
iSIGN := INPUT_1(15); -- ON EXTRAIT LA VALEUR DU SIGNE DE LA SOMME
sSIGN := INPUT_2(31); -- ON EXTRAIT LA VALEUR DU SIGNE DE LA SOMME
aOP1 := abs( OP1 );
CST1 := MIN2 - TO_SIGNED(38, 16); -- BETA_FIX;
CST2 := MIN1 - TO_SIGNED(38, 16); -- BETA_FIX;
IF CST1 < TO_SIGNED(0, 16) THEN CST1 := TO_SIGNED(0, 16); END IF;
IF CST2 < TO_SIGNED(0, 16) THEN CST2 := TO_SIGNED(0, 16); END IF;
if ( aOP1 = MIN1 ) THEN
RESU := CST1;
ELSE
RESU := CST2;
END IF;
RESUp := -RESU;
iSIGN := iSIGN XOR sSIGN;
IF( iSIGN = '0' ) THEN
cINPUT <= STD_LOGIC_VECTOR( RESU );
ELSE
cINPUT <= STD_LOGIC_VECTOR( RESUp );
END IF;
END PROCESS;
-------------------------------------------------------------------------
--
--
--
PROCESS(clock, reset)
VARIABLE TEMP : UNSIGNED(10 downto 0);
BEGIN
IF reset = '0' THEN
WRITE_C <= TO_UNSIGNED(0, 11);
elsif clock'event and clock = '1' THEN
IF WRITE_EN = '1' AND HOLDN = '1' THEN
TEMP := WRITE_C + TO_UNSIGNED(1, 11);
IF TEMP = 1824 THEN
TEMP := TO_UNSIGNED(0, 11);
END IF;
WE_BIS <= '1';
WRITE_C <= TEMP;
ELSE
WE_BIS <= '0';
WRITE_C <= WRITE_C;
END IF;
IN_BIS <= cINPUT;
END if;
END PROCESS;
--
--
--
-- process(clock, reset)
-- VARIABLE TEMP : UNSIGNED(10 downto 0);
-- begin
-- if reset = '0' then
-- READ_C <= TO_UNSIGNED(0, 11);
-- elsif clock'event and clock = '1' then
-- if read_en = '1' AND holdn = '1' then
-- TEMP := READ_C + TO_UNSIGNED(1, 11);
-- IF TEMP = 1824 THEN
-- TEMP := TO_UNSIGNED(0, 11);
-- END IF;
-- READ_C <= TEMP;
-- else
-- READ_C <= READ_C;
-- end if;
-- end if;
-- end process;
process(clock, reset)
VARIABLE TEMP : UNSIGNED(10 downto 0);
VARIABLE TMP : STD_LOGIC_VECTOR(15 downto 0);
begin
if reset = '0' then
READ_C <= TO_UNSIGNED(0, 11);
elsif clock'event and clock = '1' then
TEMP := READ_C;
if read_en = '1' AND holdn = '1' then
TEMP := TEMP + TO_UNSIGNED(1, 11);
IF TEMP = 1824 THEN
TEMP := TO_UNSIGNED(0, 11);
END IF;
end if;
READ_C <= TEMP;
TMP := RAM( to_integer( TEMP ) );
OUT_BIS <= STD_LOGIC_VECTOR( TMP ) ;
end if;
end process;
--
--
--
process(clock)
VARIABLE ADR : INTEGER RANGE 0 to 1823;
VARIABLE POS : INTEGER RANGE 0 to 1823;
begin
if clock'event and clock = '1' then
ADR := to_integer( WRITE_C );
ROM_ADR <= ROM( ADR );
end if;
end process;
--
--
--
process(clock)
begin
if clock'event and clock = '1' then
if WE_BIS = '1' then
RAM( to_integer( ROM_ADR ) ) <= IN_BIS;
end if;
--OUT_BIS <= STD_LOGIC_VECTOR( RAM( to_integer(READ_C) ) );
end if;
end process;
-------------------------------------------------------------------------
PROCESS (INPUT_1, OUT_BIS)
VARIABLE OP1 : SIGNED(16 downto 0);
VARIABLE OP2 : SIGNED(16 downto 0);
VARIABLE OP3 : SIGNED(16 downto 0);
begin
OP1 := SIGNED( OUT_BIS(15) & OUT_BIS );
OP2 := SIGNED( INPUT_1(15) & INPUT_1(15 downto 0) );
OP3 := OP1 + OP2;
if( OP3 > TO_SIGNED(32767, 17) ) THEN
OUTPUT_1 <= OUT_BIS & STD_LOGIC_VECTOR(TO_SIGNED( 32767, 16));
elsif( OP3 < TO_SIGNED(-32768, 17) ) THEN
OUTPUT_1 <= OUT_BIS & STD_LOGIC_VECTOR(TO_SIGNED(-32768, 16));
else
OUTPUT_1 <= OUT_BIS & STD_LOGIC_VECTOR( OP3(15 downto 0) );
end if;
END PROCESS;
-------------------------------------------------------------------------
END cRAM; | gpl-3.0 | 578ec4cae8ae40d23c79a35382d8fc4d | 0.640356 | 2.847129 | false | false | false | false |
VLSI-EDA/UVVM_All | xConstrRandFuncCov/src/TranscriptPkg.vhd | 3 | 7,712 | --
-- File Name: TranscriptPkg.vhd
-- Design Unit Name: TranscriptPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis [email protected]
--
--
-- Description:
-- Define file identifier TranscriptFile
-- provide subprograms to open, close, and print to it.
--
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 01/2015: 2015.01 Initial revision
-- 01/2016: 2016.01 TranscriptOpen function now calls procedure of same name
-- 11/2016: 2016.l1 Added procedure BlankLine
--
--
-- Copyright (c) 2015-2016 by SynthWorks Design Inc. All rights reserved.
--
-- Verbatim copies of this source file may be used and
-- distributed without restriction.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the ARTISTIC License
-- as published by The Perl Foundation; either version 2.0 of
-- the License, or (at your option) any later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the Artistic License for details.
--
-- You should have received a copy of the license with this source.
-- If not download it from,
-- http://www.perlfoundation.org/artistic_license_2_0
--
use std.textio.all ;
package TranscriptPkg is
-- File Identifier to facilitate usage of one transcript file
file TranscriptFile : text ;
-- Cause compile errors if READ_MODE is passed to TranscriptOpen
subtype WRITE_APPEND_OPEN_KIND is FILE_OPEN_KIND range WRITE_MODE to APPEND_MODE ;
-- Open and close TranscriptFile. Function allows declarative opens
procedure TranscriptOpen (Status: out FILE_OPEN_STATUS; ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) ;
procedure TranscriptOpen (ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) ;
impure function TranscriptOpen (ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) return FILE_OPEN_STATUS ;
procedure TranscriptClose ;
impure function IsTranscriptOpen return boolean ;
alias IsTranscriptEnabled is IsTranscriptOpen [return boolean] ;
-- Mirroring. When using TranscriptPkw WriteLine and Print, uses both TranscriptFile and OUTPUT
procedure SetTranscriptMirror (A : boolean := TRUE) ;
impure function IsTranscriptMirrored return boolean ;
alias GetTranscriptMirror is IsTranscriptMirrored [return boolean] ;
-- Write to TranscriptFile when open. Write to OUTPUT when not open or IsTranscriptMirrored
procedure WriteLine(buf : inout line) ;
procedure Print(s : string) ;
-- Create "count" number of blank lines
procedure BlankLine (count : integer := 1) ;
end TranscriptPkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body TranscriptPkg is
------------------------------------------------------------
type LocalBooleanPType is protected
procedure Set (A : boolean) ;
impure function get return boolean ;
end protected LocalBooleanPType ;
type LocalBooleanPType is protected body
variable GlobalVar : boolean := FALSE ;
procedure Set (A : boolean) is
begin
GlobalVar := A ;
end procedure Set ;
impure function get return boolean is
begin
return GlobalVar ;
end function get ;
end protected body LocalBooleanPType ;
------------------------------------------------------------
shared variable TranscriptEnable : LocalBooleanPType ;
shared variable TranscriptMirror : LocalBooleanPType ;
------------------------------------------------------------
procedure TranscriptOpen (Status: out FILE_OPEN_STATUS; ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) is
------------------------------------------------------------
begin
file_open(Status, TranscriptFile, ExternalName, OpenKind) ;
if Status = OPEN_OK then
TranscriptEnable.Set(TRUE) ;
end if ;
end procedure TranscriptOpen ;
------------------------------------------------------------
procedure TranscriptOpen (ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) is
------------------------------------------------------------
variable Status : FILE_OPEN_STATUS ;
begin
TranscriptOpen(Status, ExternalName, OpenKind) ;
if Status /= OPEN_OK then
report "TranscriptPkg.TranscriptOpen file: " &
ExternalName & " status is: " & to_string(status) & " and is not OPEN_OK" severity FAILURE ;
end if ;
end procedure TranscriptOpen ;
------------------------------------------------------------
impure function TranscriptOpen (ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) return FILE_OPEN_STATUS is
------------------------------------------------------------
variable Status : FILE_OPEN_STATUS ;
begin
TranscriptOpen(Status, ExternalName, OpenKind) ;
return Status ;
end function TranscriptOpen ;
------------------------------------------------------------
procedure TranscriptClose is
------------------------------------------------------------
begin
if TranscriptEnable.Get then
file_close(TranscriptFile) ;
end if ;
TranscriptEnable.Set(FALSE) ;
end procedure TranscriptClose ;
------------------------------------------------------------
impure function IsTranscriptOpen return boolean is
------------------------------------------------------------
begin
return TranscriptEnable.Get ;
end function IsTranscriptOpen ;
------------------------------------------------------------
procedure SetTranscriptMirror (A : boolean := TRUE) is
------------------------------------------------------------
begin
TranscriptMirror.Set(A) ;
end procedure SetTranscriptMirror ;
------------------------------------------------------------
impure function IsTranscriptMirrored return boolean is
------------------------------------------------------------
begin
return TranscriptMirror.Get ;
end function IsTranscriptMirrored ;
------------------------------------------------------------
procedure WriteLine(buf : inout line) is
------------------------------------------------------------
begin
if not TranscriptEnable.Get then
WriteLine(OUTPUT, buf) ;
elsif TranscriptMirror.Get then
TEE(TranscriptFile, buf) ;
else
WriteLine(TranscriptFile, buf) ;
end if ;
end procedure WriteLine ;
------------------------------------------------------------
procedure Print(s : string) is
------------------------------------------------------------
variable buf : line ;
begin
write(buf, s) ;
WriteLine(buf) ;
end procedure Print ;
------------------------------------------------------------
procedure BlankLine (count : integer := 1) is
------------------------------------------------------------
begin
for i in 1 to count loop
print("") ;
end loop ;
end procedure Blankline ;
end package body TranscriptPkg ; | mit | b42811ae69a75db00eee6a20410ca362 | 0.54707 | 5.189771 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/OTHERS/DIVIDER_2x_32b.vhd | 1 | 4,132 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
--library ims;
--use ims.coprocessor.all;
--use ims.conversion.all;
entity DIVIDER_2x_32b is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
start : in STD_LOGIC;
flush : in std_logic;
holdn : in std_ulogic;
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
ready : out std_logic;
nready : out std_logic;
icc : out std_logic_vector(3 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END;
architecture behav of DIVIDER_2x_32b is
constant SIZE : INTEGER := 32;
signal buf : STD_LOGIC_VECTOR((2 * SIZE - 1) downto 0);
signal dbuf : STD_LOGIC_VECTOR((SIZE - 1) downto 0);
signal sm : INTEGER range 0 to SIZE;
alias buf1 is buf((2 * SIZE - 1) downto SIZE);
alias buf2 is buf((SIZE - 1) downto 0);
BEGIN
process(rst, clk)
variable sready, snready : std_logic;
variable tbuf : STD_LOGIC_VECTOR((2*SIZE - 1) downto 0);
variable xx1 : std_logic;
variable xx2 : std_logic;
variable yy : STD_LOGIC_VECTOR((2 * SIZE - 1) downto 0);
begin
sready := '0';
snready := '0';
-- Si l'on recoit une demande de reset alors on reinitialise
if rst = '0' then
OUTPUT_1 <= (others => '0');
sm <= 0;
ready <= sready;
nready <= snready;
-- En cas de front montant de l'horloge alors on calcule
elsif rising_edge(clk) then
-- Si Flush alors on reset le composant
if (flush = '1') then
sm <= 0;
-- Si le signal de maintient est actif alors on gel l'execution
elsif (holdn = '0') AND (sm /= 0) then
sm <= sm;
-- Sinon on déroule l'execution de la division
else
case sm is
-- Etat d'attente du signal start
when 0 =>
OUTPUT_1 <= buf2;
if start = '1' then
buf1 <= (others => '0');
--printmsg("(DIVx2) ===> (001) STARTING THE COMPUTATION...)");
--buf2 <= INPUT_1;
--dbuf <= INPUT_2;
sm <= sm + 1; -- le calcul est en cours
else
sm <= sm;
end if;
when 1 =>
--printmsg("(DIVx2) ===> (001) MEMORISATION PROCESS (" & to_int_str(INPUT_1,6) & ")");
--printmsg("(DIVx2) ===> (001) MEMORISATION PROCESS (" & to_int_str(INPUT_2,6) & ")");
buf2 <= INPUT_1;
dbuf <= INPUT_2;
sm <= sm + 1; -- le calcul est en cours
when others =>
sready := '1'; -- le calcul est en cours
sm <= 0;
-- ON TRAITE LE PREMIER BIT DE L'ITERATION
if buf((2 * SIZE - 2) downto (SIZE - 1)) >= dbuf then
tbuf((2 * SIZE - 1) downto SIZE) := '0' & (buf((2 * SIZE - 3) downto (SIZE - 1)) - dbuf((SIZE - 2) downto 0));
tbuf((SIZE - 1) downto 0) := buf2((SIZE - 2) downto 0) & '1'; -- ON POUSSE LE RESULTAT
else
tbuf := buf((2 * SIZE - 2) downto 0) & '0';
end if;
-- ON TRAITE LE SECOND BIT DE L'ITERATION
if tbuf((2 * SIZE - 2) downto (SIZE - 1)) >= dbuf then
buf1 <= '0' & (tbuf((2 * SIZE - 3) downto (SIZE - 1)) - dbuf((SIZE - 2) downto 0));
buf2 <= tbuf((SIZE - 2) downto 0) & '1';
else
buf <= tbuf((2 * SIZE - 2) downto 0) & '0';
end if;
-- EN FONCTION DE LA VALEUR DU COMPTEUR ON CHOISI NOTRE DESTIN
if sm /= (17) then
sm <= sm + 1;
snready := '0'; -- le resultat n'est pas disponible
else
--if tbuf((2 * SIZE - 2) downto (SIZE - 1)) >= dbuf then
--printmsg("(DIVx2) ===> (111) COMPUTATION IS FINISHED (" & to_int_str(tbuf((SIZE - 2) downto 0) & '1',6) & ")");
--else
--printmsg("(DIVx2) ===> (111) COMPUTATION IS FINISHED (" & to_int_str(tbuf((SIZE - 2) downto 0) & '0',6) & ")");
--end if;
snready := '1'; -- le resultat du calcul est disponible
sm <= 0;
end if;
end case;
-- On transmet les signaux au systeme
ready <= sready;
nready <= snready;
end if;
end if;
end process;
end behav;
| gpl-3.0 | f17d2df744161f63806e6eda0c6886a6 | 0.534608 | 3.040471 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/function_4.vhd | 4 | 2,074 | ---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_4 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_4 is
signal val0, val1, val2, val3, min, max , max_out, min_out: std_logic_vector(7 downto 0);
signal max01, max23, max0123, min01, min23, min0123: std_logic_vector(7 downto 0);
begin
val0 <= INPUT_1(31 downto 24 );
val1 <= INPUT_1(23 downto 16 );
val2 <= INPUT_1(15 downto 8 );
val3 <= INPUT_1(7 downto 0 );
min <= INPUT_2(15 downto 8);
max <= INPUT_2(7 downto 0);
compute_max : process(max, val0, val1, val2, val3, max01, max23, max0123)
begin
if(val0 > val1) then
max01 <= val0;
else
max01 <= val1;
end if;
if(val2 > val3) then
max23 <= val2;
else
max23 <= val3;
end if;
if(max01 > max23) then
max0123 <= max01;
else
max0123 <= max23;
end if;
if(max0123 > max) then
max_out <= max0123;
else
max_out <= max;
end if;
end process;
compute_min : process(min, val0, val1, val2, val3, min01, min23, min0123)
begin
if(val0 < val1) then
min01 <= val0;
else
min01 <= val1;
end if;
if(val2 < val3) then
min23 <= val2;
else
min23 <= val3;
end if;
if(min01 < min23) then
min0123 <= min01;
else
min0123 <= min23;
end if;
if(min0123 < min) then
min_out <= min0123;
else
min_out <= min;
end if;
end process;
OUTPUT_1 <= "0000000000000000"&min_out&max_out;
end; --architecture logic
| gpl-3.0 | b54dd399c0b7238d24929b0db634cfb2 | 0.603182 | 3.005797 | false | false | false | false |
karvonz/Mandelbrot | vhdlpur_vincent/vga_bitmap_640x480_single_port.vhd | 1 | 17,933 | -------------------------------------------------------------------------------
-- Bitmap VGA display with 640x480 pixel resolution
-------------------------------------------------------------------------------
-- V 1.1.2 (2012/11/29)
-- Bertrand Le Gal ([email protected])
-- Some little modifications to support data reading
-- from file for RAM initilization.
--
-- V 1.1.1 (2012/07/28)
-- Yannick Bornat ([email protected])
--
-- For more information on this module, refer to module page :
-- http://bornat.vvv.enseirb.fr/wiki/doku.php?id=en202:vga_bitmap
--
-- V1.1.1 :
-- - Comment additions
-- - Code cleanup
-- V1.1.0 :
-- - added capacity above 3bpp
-- - ability to display grayscale pictures
-- - Module works @ 100MHz clock frequency
-- V1.0.1 :
-- - Fixed : image not centered on screen
-- V1.0.0 :
-- - Initial release
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use std.textio.ALL;
entity VGA_bitmap_640x480 is
port(--clk_vga : in std_logic;
clk_vga : in std_logic;
reset : in std_logic;
VGA_hs : out std_logic; -- horisontal vga syncr.
VGA_vs : out std_logic; -- vertical vga syncr.
iter : out std_logic_vector(7 downto 0); -- iter output
ADDR1 : in std_logic_vector(12 downto 0);
data_in1 : in std_logic_vector(7 downto 0);
data_write1 : in std_logic;
ADDR2 : in std_logic_vector(12 downto 0);
data_in2 : in std_logic_vector(7 downto 0);
data_write2 : in std_logic;
ADDR3 : in std_logic_vector(12 downto 0);
data_in3 : in std_logic_vector(7 downto 0);
data_write3 : in std_logic;
ADDR4 : in std_logic_vector(12 downto 0);
data_in4 : in std_logic_vector(7 downto 0);
data_write4 : in std_logic;
ADDR5 : in std_logic_vector(12 downto 0);
data_in5 : in std_logic_vector(7 downto 0);
data_write5 : in std_logic;
ADDR6 : in std_logic_vector(12 downto 0);
data_in6 : in std_logic_vector(7 downto 0);
data_write6 : in std_logic;
ADDR7 : in std_logic_vector(12 downto 0);
data_in7 : in std_logic_vector(7 downto 0);
data_write7 : in std_logic;
ADDR8 : in std_logic_vector(12 downto 0);
data_in8 : in std_logic_vector(7 downto 0);
data_write8 : in std_logic;
ADDR9 : in std_logic_vector(12 downto 0);
data_in9 : in std_logic_vector(7 downto 0);
data_write9 : in std_logic;
ADDR10 : in std_logic_vector(12 downto 0);
data_in10 : in std_logic_vector(7 downto 0);
data_write10 : in std_logic;
ADDR11 : in std_logic_vector(12 downto 0);
data_in11 : in std_logic_vector(7 downto 0);
data_write11 : in std_logic;
ADDR12 : in std_logic_vector(12 downto 0);
data_in12 : in std_logic_vector(7 downto 0);
data_write12 : in std_logic;
ADDR13 : in std_logic_vector(12 downto 0);
data_in13 : in std_logic_vector(7 downto 0);
data_write13 : in std_logic;
ADDR14 : in std_logic_vector(12 downto 0);
data_in14 : in std_logic_vector(7 downto 0);
data_write14 : in std_logic;
ADDR15 : in std_logic_vector(12 downto 0);
data_in15 : in std_logic_vector(7 downto 0);
data_write15 : in std_logic;
ADDR16 : in std_logic_vector(12 downto 0);
data_in16 : in std_logic_vector(7 downto 0);
data_write16 : in std_logic
);
end VGA_bitmap_640x480;
architecture Behavioral of VGA_bitmap_640x480 is
component RAM_single_port
Port ( clk : in STD_LOGIC;
data_write : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(7 downto 0);
ADDR : in STD_LOGIC_VECTOR (12 downto 0);
data_out : out STD_LOGIC_VECTOR (7 downto 0));
end component;
signal h_counter : integer range 0 to 3199:=0; -- counter for H sync. (size depends of frequ because of division)
signal v_counter : integer range 0 to 520 :=0; -- counter for V sync. (base on v_counter, so no frequ issue)
signal TOP_line : boolean := false; -- this signal is true when the current pixel column is visible on the screen
signal TOP_display : boolean := false; -- this signal is true when the current pixel line is visible on the screen
signal pix_read_addr : integer range 0 to 307199:=0; -- the address at which displayed data is read
signal pix_read_addr1, pix_read1 : integer range 0 to 19199:=0; -- the address at which displayed data is read
--signal next_pixel,next_pixel1,next_pixel2 : std_logic_vector(3 downto 0); -- the data coding the value of the pixel to be displayed
signal pix_read_addrb : integer range 0 to 38399 := 0; -- the address at which displayed data is read
signal next_pixel1, data_temp1, data_temp2 , data_outtemp1, data_outtemp2,data_temp3, data_temp4 , data_outtemp3, data_outtemp4, data_temp5, data_temp6 , data_outtemp5, data_outtemp6,data_temp7, data_temp8 , data_outtemp7, data_outtemp8 : std_logic_vector(7 downto 0); -- the data coding the value of the pixel to be displayed
signal data_temp9, data_temp10 , data_outtemp9, data_outtemp10,data_temp11, data_temp12 , data_outtemp11, data_outtemp12, data_temp13, data_temp14 , data_outtemp13, data_outtemp14,data_temp15, data_temp16 , data_outtemp15, data_outtemp16 : std_logic_vector(7 downto 0);
signal next_pixel2 : std_logic_vector(7 downto 0); -- the data coding the value of the pixel to be displayed
signal next_pixel : std_logic_vector(7 downto 0); -- the data coding the value of the pixel to be displayed
--signal data_writetemp1, data_writetemp2 : std_logic;
signal ADDRtemp1, ADDRtemp2, ADDRtemp3, ADDRtemp4, ADDRtemp5, ADDRtemp6, ADDRtemp7, ADDRtemp8 : std_logic_vector(12 downto 0); -- the data coding the value of the pixel to be displayed
signal ADDRtemp9, ADDRtemp10, ADDRtemp11, ADDRtemp12, ADDRtemp13, ADDRtemp14, ADDRtemp15, ADDRtemp16 : std_logic_vector(12 downto 0); -- the data coding the value of the pixel to be displayed
begin
--------------------------------------------------------------------------------
RAM1: RAM_single_port
port map (clk_vga,
data_write1,
data_in1,
ADDRtemp1,
data_outtemp1);
RAM2: RAM_single_port
port map (clk_vga,
data_write2,
data_in2,
ADDRtemp2,
data_outtemp2);
RAM3: RAM_single_port
port map (clk_vga,
data_write3,
data_in3,
ADDRtemp3,
data_outtemp3);
RAM4: RAM_single_port
port map (clk_vga,
data_write4,
data_in4,
ADDRtemp4,
data_outtemp4);
RAM5: RAM_single_port
port map (clk_vga,
data_write5,
data_in5,
ADDRtemp5,
data_outtemp5);
RAM6: RAM_single_port
port map (clk_vga,
data_write6,
data_in6,
ADDRtemp6,
data_outtemp6);
RAM7: RAM_single_port
port map (clk_vga,
data_write7,
data_in7,
ADDRtemp7,
data_outtemp7);
RAM8: RAM_single_port
port map (clk_vga,
data_write8,
data_in8,
ADDRtemp8,
data_outtemp8);
RAM9: RAM_single_port
port map (clk_vga,
data_write9,
data_in9,
ADDRtemp9,
data_outtemp9);
RAM10: RAM_single_port
port map (clk_vga,
data_write10,
data_in10,
ADDRtemp10,
data_outtemp10);
RAM11: RAM_single_port
port map (clk_vga,
data_write11,
data_in11,
ADDRtemp11,
data_outtemp11);
RAM12: RAM_single_port
port map (clk_vga,
data_write12,
data_in12,
ADDRtemp12,
data_outtemp12);
RAM13: RAM_single_port
port map (clk_vga,
data_write13,
data_in13,
ADDRtemp13,
data_outtemp13);
RAM14: RAM_single_port
port map (clk_vga,
data_write14,
data_in14,
ADDRtemp14,
data_outtemp14);
RAM15: RAM_single_port
port map (clk_vga,
data_write15,
data_in15,
ADDRtemp15,
data_outtemp15);
RAM16: RAM_single_port
port map (clk_vga,
data_write16,
data_in16,
ADDRtemp16,
data_outtemp16);
-- pix_read_addrb <= pix_read_addr when pix_read_addr < 123599 else pix_read_addr - 123599;
ADDRtemp1<= ADDR1 when (data_write1 = '1') else std_logic_vector(to_unsigned(pix_read1, 13)) ;
ADDRtemp2<= ADDR2 when (data_write2 = '1') else std_logic_vector(to_unsigned(pix_read1, 13)) ;
ADDRtemp3<= ADDR3 when (data_write3 = '1') else std_logic_vector(to_unsigned(pix_read1, 13)) ;
ADDRtemp4<= ADDR4 when (data_write4 = '1') else std_logic_vector(to_unsigned(pix_read1, 13)) ;
ADDRtemp5<= ADDR5 when (data_write5 = '1') else std_logic_vector(to_unsigned(pix_read1, 13)) ;
ADDRtemp6<= ADDR6 when (data_write6 = '1') else std_logic_vector(to_unsigned(pix_read1, 13)) ;
ADDRtemp7<= ADDR7 when (data_write7 = '1') else std_logic_vector(to_unsigned(pix_read1, 13)) ;
ADDRtemp8<= ADDR8 when (data_write8 = '1') else std_logic_vector(to_unsigned(pix_read1, 13)) ;
ADDRtemp9<= ADDR9 when (data_write9 = '1') else std_logic_vector(to_unsigned(pix_read1, 13)) ;
ADDRtemp10<= ADDR10 when (data_write10 = '1') else std_logic_vector(to_unsigned(pix_read1, 13)) ;
ADDRtemp11<= ADDR11 when (data_write11 = '1') else std_logic_vector(to_unsigned(pix_read1, 13)) ;
ADDRtemp12<= ADDR12 when (data_write12 = '1') else std_logic_vector(to_unsigned(pix_read1, 13)) ;
ADDRtemp13<= ADDR13 when (data_write13 = '1') else std_logic_vector(to_unsigned(pix_read1, 13)) ;
ADDRtemp14<= ADDR14 when (data_write14 = '1') else std_logic_vector(to_unsigned(pix_read1, 13)) ;
ADDRtemp15<= ADDR15 when (data_write15 = '1') else std_logic_vector(to_unsigned(pix_read1, 13)) ;
ADDRtemp16<= ADDR16 when (data_write16 = '1') else std_logic_vector(to_unsigned(pix_read1, 13)) ;
--data_writetemp1 <= clk_VGA when (data_write1 = '0') else '1' ;
--data_writetemp2 <= clk_VGA when (data_write2 = '0') else '1' ;
-- process (clk)
-- begin
-- if (clk'event and clk = '1') then
-- if (data_write1 = '1') then
-- screen1(to_integer(unsigned(ADDR1))) <= data_in1 ;
-- end if;
-- end if;
-- end process;
--
-- process (clk_vga)
-- begin
-- if (clk_vga'event and clk_vga = '1') then
-- next_pixel1 <= screen1(pix_read_addrb) ;
-- end if;
-- end process;
--
-- process (clk)
-- begin
-- if (clk'event and clk = '1') then
-- if (data_write2 = '1') then
-- screen2(to_integer(unsigned(ADDR2))) <= data_in2 ;
-- end if;
-- end if;
-- end process;
--
-- process (clk_vga)
-- begin
-- if (clk_vga'event and clk_vga = '1') then
-- next_pixel2 <= screen2(pix_read_addrb);
-- end if;
-- end process;
process (clk_vga)
begin
if (clk_vga'event and clk_vga = '1') then
IF pix_read_addr < 19199 THEN
next_pixel <= data_outtemp1;
ELSif pix_read_addr < 38399 THEN
next_pixel <= data_outtemp2;
ELSif pix_read_addr < 57599 THEN
next_pixel <= data_outtemp3;
ELSif pix_read_addr < 76799 THEN
next_pixel <= data_outtemp4;
ELSif pix_read_addr < 95999 THEN
next_pixel <= data_outtemp5;
ELSif pix_read_addr < 115199 THEN
next_pixel <= data_outtemp6;
ELSif pix_read_addr < 134399 THEN
next_pixel <= data_outtemp7;
ELSif pix_read_addr < 153599 THEN
next_pixel <= data_outtemp8;
ELSif pix_read_addr < 172799 THEN
next_pixel <= data_outtemp9;
ELSif pix_read_addr < 191999 THEN
next_pixel <= data_outtemp10;
ELSif pix_read_addr < 211199 THEN
next_pixel <= data_outtemp11;
ELSif pix_read_addr < 230399 THEN
next_pixel <= data_outtemp12;
ELSif pix_read_addr < 249599 THEN
next_pixel <= data_outtemp13;
ELSif pix_read_addr < 268799 THEN
next_pixel <= data_outtemp14;
ELSif pix_read_addr < 28799 THEN
next_pixel <= data_outtemp15;
else
next_pixel <= data_outtemp16;
END IF;
end if;
end process;
--process (clk_vga)
--begin
-- if (clk_vga'event and clk_vga = '1') then
-- if (data_write1 = '1') then
-- screen1(to_integer(unsigned(ADDR1))) <= data_in1;
-- next_pixel1 <= data_in1;
-- else
-- next_pixel1 <= screen1(to_integer(unsigned(ADDR1)));
-- end if;
-- end if;
--end process;
--
--process (clk_vga)
--begin
-- if (clk_vga'event and clk_vga = '1') then
-- if (data_write2 = '1') then
-- screen2(to_integer(unsigned(ADDR2))) <= data_in2;
-- next_pixel2 <= data_in2;
-- else
-- next_pixel2 <= screen2(to_integer(unsigned(ADDR2));
-- end if;
-- end if;
--end process;
--process (next_pixel)
--begin
-- if (clk_vga'event and clk_vga = '1') then
-- next_pixel <= To_StdLogicVector( ram_out(pix_read_addr) );
-- end if;
--end process;
--ram_out <= screen1 when to_unsigned(pix_read_addr,13)(12) = '0' else screen2;
--------------------------------------------------------------------------------
--proc<='0' when (pix_read_addr <123599) else '1';
pixel_read_addr : process(clk_vga)
begin
if clk_vga'event and clk_vga='1' then
if reset = '1' or (not TOP_display) then
pix_read_addr <= 0;
elsif TOP_line and (h_counter mod 4)=0 then
pix_read_addr <= pix_read_addr + 1;
elsif (pix_read_addr = 307199) then
pix_read_addr <= 0;
end if;
end if;
end process;
pixel_read1 : process(clk_vga)
begin
if clk_vga'event and clk_vga='1' then
if reset = '1' or (not TOP_display) then
pix_read1 <= 0;
elsif TOP_line and (h_counter mod 4)=0 then
pix_read1 <= pix_read1 + 1;
elsif (pix_read1 = 19199) then
pix_read1 <= 0;
end if;
end if;
end process;
--pixel_read_addrb : process(clk_vga, clk)
--begin
-- if clk_vga'event and clk_vga='1' then
-- if reset = '1' or (not TOP_display) then
-- pix_read_addrb <= 0;
-- elsif TOP_line and (h_counter mod 4)=0 then
-- pix_read_addrb <= pix_read_addrb + 1;
-- elsif (pix_read_addrb = 123599) then
-- pix_read_addrb <= 0;
-- end if;
-- end if;
--end process;
--process(pix_read_addr)
--begin
-- if pix_read_addr < 123599 then
-- ram_number <= '0';
-- elsif pix_read_addr <307199 then
-- ram_number <= '1';
-- else
-- ram_number <= '0';
-- end if;
--end process;
-- this process manages the horizontal synchro using the counters
process(clk_vga)
begin
if clk_vga'event and clk_vga='1' then
if reset = '1' then
VGA_vs <= '0';
TOP_display <= false;
else
case v_counter is
when 0 => VGA_vs <= '0'; -- start of Tpw ( 0 -> 0 + 1)
when 2 => VGA_vs <= '1'; -- start of Tbp ( 2 -> 2 + 28 = 30)
when 31 => TOP_display <= true; -- start of Tdisp ( 31 -> 31 + 479 = 510)
when 511 => TOP_display <= false; -- start of Tfp (511 -> 511 + 9 = 520)
when others => null;
end case;
-- if v_counter = 0 then VGA_vs <= '0'; -- start of Tpw ( 0 -> 0 + 1)
-- elsif v_counter = 2 then VGA_vs <= '1'; -- start of Tbp ( 2 -> 2 + 28 = 30)
-- elsif v_counter = 75 then TOP_display <= true; -- start of Tdisp ( 31 -> 31 + 479 = 510)
-- elsif v_counter = 475 then TOP_display <= false; -- start of Tfp (511 -> 511 + 9 = 520)
-- end if;
end if;
end if;
end process;
process(clk_vga)
begin
if clk_vga'event and clk_vga='1' then
if (not TOP_line) or (not TOP_display) then
iter <= "00000000";
else
iter<= next_pixel;
end if;
end if;
end process;
-- this process manages the horizontal synchro using the counters
process(clk_vga)
begin
if clk_vga'event and clk_vga='1' then
if reset = '1' then
VGA_hs <= '0';
TOP_line <= false;
else
case h_counter is
when 2 => VGA_hs <= '0'; -- start of Tpw ( 0 -> 0 + 95) -- +2 because of delay in RAM
when 386 => VGA_hs <= '1'; -- start of Tbp ( 96 -> 96 + 47 = 143) -- 384=96*4 -- -- +2 because of delay in RAM
when 576 => TOP_line <= true; -- start of Tdisp ( 144 -> 144 + 639 = 783) -- 576=144*4
when 3136 => TOP_line <= false; -- start of Tfp ( 784 -> 784 + 12 = 799) -- 3136 = 784*4
when others => null;
end case;
-- if h_counter=2 then VGA_hs <= '0'; -- start of Tpw ( 0 -> 0 + 95) -- +2 because of delay in RAM
-- elsif h_counter=386 then VGA_hs <= '1'; -- start of Tbp ( 96 -> 96 + 47 = 143) -- 384=96*4 -- -- +2 because of delay in RAM
-- elsif h_counter=576 then TOP_line <= true; -- start of Tdisp ( 144 -> 144 + 639 = 783) -- 576=144*4
-- elsif h_counter=3136 then TOP_line <= false; -- start of Tfp ( 784 -> 784 + 12 = 799) -- 3136 = 784*4
-- end if;
end if;
end if;
end process;
-- counter management for synchro
process(clk_vga)
begin
if clk_vga'event and clk_vga='1' then
if reset='1' then
h_counter <= 0;
v_counter <= 0;
else
if h_counter = 3199 then
h_counter <= 0;
if v_counter = 520 then
v_counter <= 0;
else
v_counter <= v_counter + 1;
end if;
else
h_counter <= h_counter +1;
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 503c65120fdab339e5466d222d4c86d5 | 0.57291 | 3.134592 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/custom/mandelbrot/vga_bitmap_640x480_dualport.vhd | 1 | 13,711 | -------------------------------------------------------------------------------
-- Bitmap VGA display with 640x480 pixel resolution
-------------------------------------------------------------------------------
-- V 1.1.2 (2015/11/29)
-- Bertrand Le Gal ([email protected])
-- Some little modifications to support data reading
-- from file for RAM initilization.
--
-- V 1.1.1 (2015/07/28)
-- Yannick Bornat ([email protected])
--
-- For more information on this module, refer to module page :
-- http://bornat.vvv.enseirb.fr/wiki/doku.php?id=en202:vga_bitmap
--
-- V1.1.1 :
-- - Comment additions
-- - Code cleanup
-- V1.1.0 :
-- - added capacity above 3bpp
-- - ability to display grayscale pictures
-- - Module works @ 100MHz clock frequency
-- V1.0.1 :
-- - Fixed : image not centered on screen
-- V1.0.0 :
-- - Initial release
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use std.textio.ALL;
entity VGA_bitmap_640x480 is
port(clk : in std_logic;
clk_vga : in std_logic;
reset : in std_logic;
VGA_hs : out std_logic; -- horisontal vga syncr.
VGA_vs : out std_logic; -- vertical vga syncr.
iter : out std_logic_vector(7 downto 0); -- iter output
ADDR1 : in std_logic_vector(15 downto 0);
data_in1 : in std_logic_vector(7 downto 0);
data_write1 : in std_logic;
ADDR2 : in std_logic_vector(15 downto 0);
data_in2 : in std_logic_vector(7 downto 0);
data_write2 : in std_logic;
ADDR3 : in std_logic_vector(15 downto 0);
data_in3 : in std_logic_vector(7 downto 0);
data_write3 : in std_logic;
ADDR4 : in std_logic_vector(15 downto 0);
data_in4 : in std_logic_vector(7 downto 0);
data_write4 : in std_logic;
ADDR5 : in std_logic_vector(15 downto 0);
data_in5 : in std_logic_vector(7 downto 0);
data_write5 : in std_logic;
ADDR6 : in std_logic_vector(15 downto 0);
data_in6 : in std_logic_vector(7 downto 0);
data_write6 : in std_logic;
ADDR7 : in std_logic_vector(15 downto 0);
data_in7 : in std_logic_vector(7 downto 0);
data_write7 : in std_logic;
ADDR8 : in std_logic_vector(15 downto 0);
data_in8 : in std_logic_vector(7 downto 0);
data_write8 : in std_logic);
end VGA_bitmap_640x480;
architecture Behavioral of VGA_bitmap_640x480 is
-- Graphic RAM type. this object is the content of the displayed image
type GRAM is array (0 to 38399) of std_logic_vector(7 downto 0); --153599
signal screen1, screen2,screen3, screen4,screen5, screen6,screen7,screen8 : GRAM;-- := ram_function_name("../mandelbrot.bin"); -- the memory representation of the image
signal h_counter : integer range 0 to 3199:=0; -- counter for H sync. (size depends of frequ because of division)
signal v_counter : integer range 0 to 520 :=0; -- counter for V sync. (base on v_counter, so no frequ issue)
signal TOP_line : boolean := false; -- this signal is true when the current pixel column is visible on the screen
signal TOP_display : boolean := false; -- this signal is true when the current pixel line is visible on the screen
signal pix_read_addr : integer range 0 to 307199:=0; -- the address at which displayed data is read
signal pix_read_addr1 : integer range 0 to 38399:=0; -- the address at which displayed data is read
--signal next_pixel,next_pixel1,next_pixel2 : std_logic_vector(3 downto 0); -- the data coding the value of the pixel to be displayed
signal pix_read_addrb : integer range 0 to 38399 := 0; -- the address at which displayed data is read
signal next_pixel1 , next_pixel2, next_pixel3 , next_pixel4, next_pixel5 , next_pixel6, next_pixel7, next_pixel8 : std_logic_vector(7 downto 0); -- the data coding the value of the pixel to be displayed
signal next_pixel : std_logic_vector(7 downto 0); -- the data coding the value of the pixel to be displayed
signal proc : std_logic_vector(2 downto 0);
begin
--------------------------------------------------------------------------------
-- pix_read_addrb <= pix_read_addr when pix_read_addr < 153599 else pix_read_addr - 153599;
process (clk)
begin
if (clk'event and clk = '1') then
if (data_write1 = '1') then
screen1(to_integer(unsigned(ADDR1))) <= data_in1 ;
end if;
end if;
end process;
process (clk_vga)
begin
if (clk_vga'event and clk_vga = '1') then
next_pixel1 <= screen1(pix_read_addr1) ;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
if (data_write2 = '1') then
screen2(to_integer(unsigned(ADDR2))) <= data_in2 ;
end if;
end if;
end process;
process (clk_vga)
begin
if (clk_vga'event and clk_vga = '1') then
next_pixel2 <= screen2(pix_read_addr1);
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
if (data_write3 = '1') then
screen3(to_integer(unsigned(ADDR3))) <= data_in3 ;
end if;
end if;
end process;
process (clk_vga)
begin
if (clk_vga'event and clk_vga = '1') then
next_pixel3 <= screen3(pix_read_addr1) ;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
if (data_write4 = '1') then
screen4(to_integer(unsigned(ADDR4))) <= data_in4 ;
end if;
end if;
end process;
process (clk_vga)
begin
if (clk_vga'event and clk_vga = '1') then
next_pixel4 <= screen4(pix_read_addr1);
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
if (data_write5 = '1') then
screen5(to_integer(unsigned(ADDR5))) <= data_in5 ;
end if;
end if;
end process;
process (clk_vga)
begin
if (clk_vga'event and clk_vga = '1') then
next_pixel5 <= screen5(pix_read_addr1) ;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
if (data_write6 = '1') then
screen6(to_integer(unsigned(ADDR6))) <= data_in6 ;
end if;
end if;
end process;
process (clk_vga)
begin
if (clk_vga'event and clk_vga = '1') then
next_pixel6 <= screen6(pix_read_addr1);
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
if (data_write7 = '1') then
screen7(to_integer(unsigned(ADDR7))) <= data_in7 ;
end if;
end if;
end process;
process (clk_vga)
begin
if (clk_vga'event and clk_vga = '1') then
next_pixel7 <= screen7(pix_read_addr1) ;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
if (data_write8 = '1') then
screen8(to_integer(unsigned(ADDR8))) <= data_in8 ;
end if;
end if;
end process;
process (clk_vga)
begin
if (clk_vga'event and clk_vga = '1') then
next_pixel8 <= screen8(pix_read_addr1);
end if;
end process;
process (clk_vga)
begin
if (clk_vga'event and clk_vga = '1') then
IF proc= "000" THEN
next_pixel <= next_pixel1;
ELSif proc ="001" then
next_pixel <= next_pixel2;
ELSif proc ="010" then
next_pixel <= next_pixel3;
ELSif proc ="011" then
next_pixel <= next_pixel4;
ELSif proc ="100" then
next_pixel <= next_pixel5;
ELSif proc ="101" then
next_pixel <= next_pixel6;
ELSif proc ="110" then
next_pixel <= next_pixel7;
else
next_pixel <= next_pixel8;
END IF;
end if;
end process;
--process (next_pixel)
--begin
-- if (clk_vga'event and clk_vga = '1') then
-- next_pixel <= To_StdLogicVector( ram_out(pix_read_addr) );
-- end if;
--end process;
--ram_out <= screen1 when to_unsigned(pix_read_addr,18)(17) = '0' else screen2;
--------------------------------------------------------------------------------
process(pix_read_addr)
begin
IF pix_read_addr < 38399 THEN
proc <= "000";
ELSif pix_read_addr < 76799 THEN
proc <= "001";
ELSif pix_read_addr < 115199 THEN
proc <= "010";
ELSif pix_read_addr < 153599 THEN
proc <= "011";
ELSif pix_read_addr < 191999 THEN
proc <= "100";
ELSif pix_read_addr < 153599 THEN
proc <= "101";
ELSif pix_read_addr < 230399 THEN
proc <= "110";
else
proc <= "111";
END IF;
end process;
--proc<='0' when (pix_read_addr <153599) else '1';
pixel_read_addr : process(clk_vga, clk)
begin
if clk_vga'event and clk_vga='1' then
if reset = '1' or (not TOP_display) then
pix_read_addr <= 0;
elsif TOP_line and (h_counter mod 4)=0 then
pix_read_addr <= pix_read_addr + 1;
elsif (pix_read_addr = 307199) then
pix_read_addr <= 0;
end if;
end if;
end process;
pixel_read_addr1 : process(clk_vga, clk)
begin
if clk_vga'event and clk_vga='1' then
if reset = '1' or (not TOP_display) then
pix_read_addr1 <= 0;
elsif TOP_line and (h_counter mod 4)=0 then
pix_read_addr1 <= pix_read_addr1 + 1;
elsif (pix_read_addr1 = 38399) then
pix_read_addr1 <= 0;
end if;
end if;
end process;
--pixel_read_addrb : process(clk_vga, clk)
--begin
-- if clk_vga'event and clk_vga='1' then
-- if reset = '1' or (not TOP_display) then
-- pix_read_addrb <= 0;
-- elsif TOP_line and (h_counter mod 4)=0 then
-- pix_read_addrb <= pix_read_addrb + 1;
-- elsif (pix_read_addrb = 153599) then
-- pix_read_addrb <= 0;
-- end if;
-- end if;
--end process;
--process(pix_read_addr)
--begin
-- if pix_read_addr < 153599 then
-- ram_number <= '0';
-- elsif pix_read_addr <307199 then
-- ram_number <= '1';
-- else
-- ram_number <= '0';
-- end if;
--end process;
-- this process manages the horizontal synchro using the counters
process(clk_vga)
begin
if clk_vga'event and clk_vga='1' then
if reset = '1' then
VGA_vs <= '0';
TOP_display <= false;
else
case v_counter is
when 0 => VGA_vs <= '0'; -- start of Tpw ( 0 -> 0 + 1)
when 2 => VGA_vs <= '1'; -- start of Tbp ( 2 -> 2 + 28 = 30)
when 31 => TOP_display <= true; -- start of Tdisp ( 31 -> 31 + 479 = 510)
when 511 => TOP_display <= false; -- start of Tfp (511 -> 511 + 9 = 520)
when others => null;
end case;
-- if v_counter = 0 then VGA_vs <= '0'; -- start of Tpw ( 0 -> 0 + 1)
-- elsif v_counter = 2 then VGA_vs <= '1'; -- start of Tbp ( 2 -> 2 + 28 = 30)
-- elsif v_counter = 75 then TOP_display <= true; -- start of Tdisp ( 31 -> 31 + 479 = 510)
-- elsif v_counter = 475 then TOP_display <= false; -- start of Tfp (511 -> 511 + 9 = 520)
-- end if;
end if;
end if;
end process;
process(clk_vga)
begin
if clk_vga'event and clk_vga='1' then
if (not TOP_line) or (not TOP_display) then
iter <= "00000000";
else
iter<= next_pixel;
end if;
end if;
end process;
-- this process manages the horizontal synchro using the counters
process(clk_vga)
begin
if clk_vga'event and clk_vga='1' then
if reset = '1' then
VGA_hs <= '0';
TOP_line <= false;
else
case h_counter is
when 2 => VGA_hs <= '0'; -- start of Tpw ( 0 -> 0 + 95) -- +2 because of delay in RAM
when 386 => VGA_hs <= '1'; -- start of Tbp ( 96 -> 96 + 47 = 143) -- 384=96*4 -- -- +2 because of delay in RAM
when 576 => TOP_line <= true; -- start of Tdisp ( 144 -> 144 + 639 = 783) -- 576=144*4
when 3136 => TOP_line <= false; -- start of Tfp ( 784 -> 784 + 15 = 799) -- 3136 = 784*4
when others => null;
end case;
-- if h_counter=2 then VGA_hs <= '0'; -- start of Tpw ( 0 -> 0 + 95) -- +2 because of delay in RAM
-- elsif h_counter=386 then VGA_hs <= '1'; -- start of Tbp ( 96 -> 96 + 47 = 143) -- 384=96*4 -- -- +2 because of delay in RAM
-- elsif h_counter=576 then TOP_line <= true; -- start of Tdisp ( 144 -> 144 + 639 = 783) -- 576=144*4
-- elsif h_counter=3136 then TOP_line <= false; -- start of Tfp ( 784 -> 784 + 15 = 799) -- 3136 = 784*4
-- end if;
end if;
end if;
end process;
-- counter management for synchro
process(clk_vga)
begin
if clk_vga'event and clk_vga='1' then
if reset='1' then
h_counter <= 0;
v_counter <= 0;
else
if h_counter = 3199 then
h_counter <= 0;
if v_counter = 520 then
v_counter <= 0;
else
v_counter <= v_counter + 1;
end if;
else
h_counter <= h_counter +1;
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 3e8ca0fbc906f9657d1d8acf91926ad5 | 0.535993 | 3.3746 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Font/simulation/Font_tb_rng.vhd | 1 | 4,214 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Font_tb_rng.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY Font_TB_RNG IS
GENERIC (
WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END Font_TB_RNG;
ARCHITECTURE BEHAVIORAL OF Font_TB_RNG IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
| mit | dae912132d5a120bc62724ec2f7f0141 | 0.58187 | 4.403344 | false | false | false | false |
chibby0ne/vhdl-book | Chapter13/ram_dir/ram_tb.vhd | 1 | 3,900 | --!
--! Copyright (C) 2010 - 2013 Creonic GmbH
--!
--! @file: ram_tb.vhd
--! @brief: tb of ram
--! @author: Antonio Gutierrez
--! @date: 2014-04-23
--!
--!
--------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------
entity ram_tb is
generic (M: natural := 4; -- 2**M = depth
N: natural := 8;
PERIOD: time := 40 ns;
PD: time := 3 ns); -- N = width
end entity ram_tb;
--------------------------------------------------------
architecture circuit of ram_tb is
-- dut declaration
component ram is
port (
clk: in std_logic;
we: in std_logic;
address: in std_logic_vector(M-1 downto 0);
data_in: in std_logic_vector(N-1 downto 0);
data_out: out std_logic_vector(N-1 downto 0));
end component ram;
-- signal declaration
signal clk_tb: std_logic := '0';
signal we_tb: std_logic := '0';
signal address_tb: std_logic_vector(M-1 downto 0) := (others => '0');
signal data_in_tb: std_logic_vector(N-1 downto 0) := (others => '0');
signal data_out_tb: std_logic_vector(N-1 downto 0);
begin
-- dut instantiation
dut: ram port map (
clk => clk_tb,
we => we_tb,
address => address_tb,
data_in => data_in_tb,
data_out => data_out_tb
);
-- stimuli generation
-- clk
clk_tb <= not clk_tb after PERIOD / 2;
-- addrss
process
variable addr: integer range 0 to 2**M - 1 := 0;
begin
if (addr < 2**M - 1) then
wait for PERIOD;
addr := addr + 1;
address_tb <= std_logic_vector(to_unsigned(addr, M));
else
wait for PERIOD;
assert false
report "simulation end"
severity failure;
end if;
end process;
-- we
process
begin
wait for 2 * PERIOD; -- addr = 2 --100 ns
we_tb <= '1';
wait for 2 * PERIOD; -- 180 ns
we_tb <= '0';
wait;
end process;
-- data_in
process
begin
data_in_tb <= std_logic_vector(to_unsigned(4, N));
wait for 3 * PERIOD;
data_in_tb <= std_logic_vector(to_unsigned(15, N));
wait;
end process;
-- output comparison
process
begin
wait for PD;
-- addr 0
assert 0 = to_integer(unsigned(data_out_tb))
report "output mismatch"
severity failure;
wait for PERIOD;
-- addr 1
assert 0 = to_integer(unsigned(data_out_tb))
report "output mismatch"
severity failure;
wait for PERIOD;
-- addr 2
assert 255 = to_integer(unsigned(data_out_tb))
report "output mismatch"
severity failure;
wait for PERIOD / 2;
-- addr 2
assert 4 = to_integer(unsigned(data_out_tb))
report "output mismatch"
severity failure;
wait for PERIOD / 2;
-- addr 3
assert 26 = to_integer(unsigned(data_out_tb))
report "output mismatch"
severity failure;
wait for PERIOD / 2;
-- addr 3
assert 15 = to_integer(unsigned(data_out_tb))
report "output mismatch"
severity failure;
wait for PERIOD / 2;
-- addr 4
assert 5 = to_integer(unsigned(data_out_tb))
report "output mismatch"
severity failure;
wait for PERIOD;
-- addr 5
assert 80 = to_integer(unsigned(data_out_tb))
report "output mismatch"
severity failure;
wait;
-- assert false
-- report "no errors"
-- severity failure;
end process;
end architecture circuit;
| gpl-3.0 | e64c58d2765dce4a0ebcb559d3854d66 | 0.496923 | 4.070981 | false | false | false | false |
VLSI-EDA/UVVM_All | bitvis_vip_sbi/src/vvc_context.vhd | 1 | 1,396 | --========================================================================================================================
-- Copyright (c) 2018 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
context vvc_context is
library bitvis_vip_sbi;
use bitvis_vip_sbi.vvc_cmd_pkg.all;
use bitvis_vip_sbi.vvc_methods_pkg.all;
use bitvis_vip_sbi.td_vvc_framework_common_methods_pkg.all;
end context; | mit | 1ab132d4fe2a180539ea31321aa37329 | 0.525788 | 5.496063 | false | false | false | false |
chibby0ne/vhdl-book | Chapter10/example10_1_dir/example10_1/example10_1.vhd | 1 | 1,064 | --!
--! @file: example10_1.vhd
--! @brief: writing values to a file
--! @author: Antonio Gutierrez
--! @date: 2013-11-27
--!
--!
--------------------------------------
use std.textio.all;
--------------------------------------
entity write_to_file is
end entity write_to_file;
--------------------------------------
architecture circuit of write_to_file is
constant period: time := 100 ns;
signal clk: bit := '0';
file f: text open write_mode is "test_file.txt";
begin
proc: process
constant str1: string(1 to 2) := "t=";
constant str2: string(1 to 3) := " i=";
variable l: line;
variable t: time := 0 ns;
variable i: natural range 0 to 7 := 0;
begin
wait for period/2;
clk <= '1';
t := period/2 + i * period;
write(l, str1);
write(l, t);
write(l, str2);
write(l, i);
writeline(f, l);
i := i + 1;
wait for period/2;
clk <= '0';
end process proc;
end architecture circuit;
--------------------------------------
| gpl-3.0 | 5956e769352abb756b1072d02446f6af | 0.462406 | 3.827338 | false | false | false | false |
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