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VLSI-EDA/UVVM_All | bitvis_vip_avalon_mm/src/vvc_context.vhd | 1 | 1,420 | --========================================================================================================================
-- Copyright (c) 2018 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
context vvc_context is
library bitvis_vip_avalon_mm;
use bitvis_vip_avalon_mm.vvc_cmd_pkg.all;
use bitvis_vip_avalon_mm.vvc_methods_pkg.all;
use bitvis_vip_avalon_mm.td_vvc_framework_common_methods_pkg.all;
end context; | mit | 8c4afb1262e46cb6cfdc731552220c91 | 0.530986 | 5.419847 | false | false | false | false |
chibby0ne/vhdl-book | Chapter5/addersubstracter_dir/addersubstracter.vhd | 1 | 1,055 | -- author: Antonio Gutierrez
-- description: adder and substracter
------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
------------------------------
entity signed_adder_sub is
generic (N: integer := 4); -- number of input bits
port (
a, b: in std_logic_vector(N-1 downto 0);
cin: in std_logic;
sum, sub: out std_logic_vector(N downto 0));
end entity;
------------------------------
architecture signed_adder_sub of signed_adder_sub is
signal a_sig, b_sig: signed(N-1 downto 0);
signal sum_sig, sub_sig: signed(N downto 0);
begin
---------convert to signed---------
a_sig <= signed(a);
b_sig <= signed(b);
---------add and substract---------
sum_sig <= (a_sig(N-1) & a_sig) + (b_sig(N-1) & b_sig) + ('0' & cin);
sub_sig <= (a_sig(N-1) & a_sig) - (b_sig(N-1) & b_sig) + ('0' & cin);
---------output option 1---------
sum <= std_logic_vector(sum_sig);
sub <= std_logic_vector(sub_sig);
end architecture;
------------------------------
| gpl-3.0 | 0521cf67868a41e17208c472c3040bc6 | 0.511848 | 3.31761 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/dist_mem_gen_v7_2/simulation/dist_mem_gen_v7_2_tb_checker.vhd | 1 | 5,760 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: dist_mem_gen_v7_2_tb_checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.dist_mem_gen_v7_2_TB_PKG.ALL;
ENTITY dist_mem_gen_v7_2_TB_CHECKER IS
GENERIC (
WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END dist_mem_gen_v7_2_TB_CHECKER;
ARCHITECTURE CHECKER_ARCH OF dist_mem_gen_v7_2_TB_CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DGEN_INST:ENTITY work.dist_mem_gen_v7_2_TB_DGEN
GENERIC MAP (
DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
| mit | 318cb88fea30450921a80a2b166f14c3 | 0.586806 | 3.953329 | false | false | false | false |
karvonz/Mandelbrot | vhdlpur_vincent/RAM_single_port.vhd | 1 | 1,793 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:46:34 05/19/2016
-- Design Name:
-- Module Name: RAM_single_port - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RAM_single_port is
Port ( clk : in STD_LOGIC;
data_write : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(7 downto 0);
ADDR : in STD_LOGIC_VECTOR (17 downto 0);
data_out : out STD_LOGIC_VECTOR (7 downto 0));
end RAM_single_port;
architecture Behavioral of RAM_single_port is
constant ADDR_WIDTH : integer := 16;
constant DATA_WIDTH : integer := 8;
-- Graphic RAM type. this object is the content of the displayed image
type GRAM is array (0 to 76799) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal screen : GRAM;-- := ram_function_name("../mandelbrot.bin"); -- the memory representation of the image
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (data_write = '1') then
screen(to_integer(unsigned(ADDR))) <= data_in;
data_out <= data_in;
else
data_out <= screen(to_integer(unsigned(ADDR)));
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 5470a2b6cb82492da3ee5fcf1bbe725e | 0.606804 | 3.681725 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/LDPC/Q16_8_FullCondSelect.vhd | 1 | 2,545 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------
-- synthesis translate_off
library ims;
use ims.coprocessor.all;
-- synthesis translate_on
-------------------------------------------------------------------------
ENTITY Q16_8_FullCondSelect is
PORT (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END;
ARCHITECTURE rtl of Q16_8_FullCondSelect IS
BEGIN
-------------------------------------------------------------------------
-- synthesis translate_off
PROCESS
BEGIN
WAIT FOR 1 ns;
printmsg("(IMS) Q16_8_FullCondSelect : ALLOCATION OK !");
WAIT;
END PROCESS;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
PROCESS (INPUT_1, INPUT_2)
VARIABLE OP1 : SIGNED(15 downto 0);
VARIABLE aOP1 : SIGNED(15 downto 0);
VARIABLE MIN1 : SIGNED(15 downto 0);
VARIABLE MIN2 : SIGNED(15 downto 0);
VARIABLE CST1 : SIGNED(15 downto 0);
VARIABLE CST2 : SIGNED(15 downto 0);
VARIABLE RESU : SIGNED(15 downto 0);
VARIABLE RESUp : SIGNED(15 downto 0);
VARIABLE iSIGN : STD_LOGIC;
VARIABLE sSIGN : STD_LOGIC;
BEGIN
--
-- ON RECUPERE NOS OPERANDES
--
OP1 := SIGNED( INPUT_1(15 downto 0)); -- DONNEE SIGNEE SUR 16 bits
MIN1 := SIGNED('0' & INPUT_2(30 downto 16)); -- DONNEE TJS POSITIVE SUR 16 BITS
MIN2 := SIGNED('0' & INPUT_2(14 downto 0)); -- DONNEE TJS POSITIVE SUR 16 BITS
iSIGN := INPUT_1(15); -- ON EXTRAIT LA VALEUR DU SIGNE DE LA SOMME
sSIGN := INPUT_2(31); -- ON EXTRAIT LA VALEUR DU SIGNE DE LA SOMME
--
--
--
aOP1 := abs( OP1 );
--
--
--
CST1 := MIN2 - TO_SIGNED(38, 16); -- BETA_FIX;
CST2 := MIN1 - TO_SIGNED(38, 16); -- BETA_FIX;
IF CST1 < TO_SIGNED(0, 16) THEN CST1 := TO_SIGNED(0, 16); END IF;
IF CST2 < TO_SIGNED(0, 16) THEN CST2 := TO_SIGNED(0, 16); END IF;
--
--
--
if ( aOP1 = MIN1 ) THEN
RESU := CST1;
ELSE
RESU := CST2;
END IF;
--
--
--
RESUp := -RESU;
iSIGN := iSIGN XOR sSIGN;
--
--
--
IF( iSIGN = '0' ) THEN
OUTPUT_1 <= STD_LOGIC_VECTOR( RESIZE(RESU, 32) );
ELSE
OUTPUT_1 <= STD_LOGIC_VECTOR( RESIZE(RESUp, 32) );
END IF;
END PROCESS;
-------------------------------------------------------------------------
END;
| gpl-3.0 | dee6878c6855bb327fe9e1398a42e62c | 0.499411 | 3.366402 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/GRAPHLAB/INTEGER_LIBRARY.vhd | 1 | 6,858 | -- ADDER COMPONENT WITH VARIABLE INPUTS AND OUTPUT BITWIDTH
-- DEVELOPPED FOR THE GRAPHLAB TOOL BY BERTRAND LE GAL
-- IMS LABORATORY - UMR-CNRS 5218
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
ENTITY ADD_Dynamic IS
GENERIC(
C_SIGNED : NATURAL := 0;
INPUT_1_WIDTH : NATURAL := 8;
INPUT_2_WIDTH : NATURAL := 8;
OUTPUT_1_WIDTH : NATURAL := 8
);
PORT (
INPUT_1 :IN STD_LOGIC_VECTOR(INPUT_1_WIDTH-1 DOWNTO 0);
INPUT_2 :IN STD_LOGIC_VECTOR(INPUT_2_WIDTH-1 DOWNTO 0);
OUTPUT_1 :OUT STD_LOGIC_VECTOR(OUTPUT_1_WIDTH-1 DOWNTO 0)
);
END;
architecture behavior of ADD_Dynamic is
-- MAXIMUM FUNCTION TO COMPUTE THE INTERNAL DATA SIZE
FUNCTION maximum (left, right : NATURAL) return NATURAL IS
BEGIN -- function max
IF LEFT > RIGHT THEN RETURN LEFT;
ELSE RETURN RIGHT;
END IF;
END FUNCTION maximum;
BEGIN
PROCESS (INPUT_1, INPUT_2)
CONSTANT SIZI : NATURAL := maximum(INPUT_1_WIDTH, INPUT_2_WIDTH);
CONSTANT SIZE : NATURAL := maximum(SIZI, OUTPUT_1_WIDTH);
VARIABLE Stmp : SIGNED (SIZE-1 DOWNTO 0);
VARIABLE UStmp : UNSIGNED(SIZE-1 DOWNTO 0);
BEGIN
IF C_SIGNED = 0 THEN
UStmp := RESIZE( UNSIGNED( INPUT_1 ) + UNSIGNED( INPUT_2 ), OUTPUT_1_WIDTH);
OUTPUT_1 <= STD_LOGIC_VECTOR( UStmp(OUTPUT_1_WIDTH-1 DOWNTO 0) );
ELSE
Stmp := RESIZE( SIGNED( INPUT_1 ) + SIGNED( INPUT_2 ), OUTPUT_1_WIDTH);
OUTPUT_1 <= STD_LOGIC_VECTOR( Stmp(OUTPUT_1_WIDTH-1 DOWNTO 0) );
END IF;
END PROCESS;
END;
-- SUBSTRACTOR COMPONENT WITH VARIABLE INPUTS AND OUTPUT BITWIDTH
-- DEVELOPPED FOR THE GRAPHLAB TOOL BY BERTRAND LE GAL
-- IMS LABORATORY - UMR-CNRS 5218
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
ENTITY SUB_Dynamic IS
GENERIC(
C_SIGNED : NATURAL := 0;
INPUT_1_WIDTH : NATURAL := 8;
INPUT_2_WIDTH : NATURAL := 8;
OUTPUT_1_WIDTH : NATURAL := 8
);
PORT (
INPUT_1 :IN STD_LOGIC_VECTOR(INPUT_1_WIDTH-1 DOWNTO 0);
INPUT_2 :IN STD_LOGIC_VECTOR(INPUT_2_WIDTH-1 DOWNTO 0);
OUTPUT_1 :OUT STD_LOGIC_VECTOR(OUTPUT_1_WIDTH-1 DOWNTO 0)
);
END;
ARCHITECTURE behavior OF SUB_Dynamic IS
-- MAXIMUM FUNCTION TO COMPUTE THE INTERNAL DATA SIZE
FUNCTION maximum (left, right : NATURAL) return NATURAL IS
BEGIN -- function max
IF LEFT > RIGHT THEN RETURN LEFT;
ELSE RETURN RIGHT;
END IF;
END FUNCTION maximum;
BEGIN
PROCESS (INPUT_1, INPUT_2)
CONSTANT SIZI : NATURAL := maximum(INPUT_1_WIDTH, INPUT_2_WIDTH);
CONSTANT SIZE : NATURAL := maximum(SIZI, OUTPUT_1_WIDTH);
VARIABLE Stmp : SIGNED (SIZE-1 DOWNTO 0);
VARIABLE UStmp : UNSIGNED(SIZE-1 DOWNTO 0);
BEGIN
IF C_SIGNED = 0 THEN
UStmp := RESIZE( UNSIGNED( INPUT_1 ) - UNSIGNED( INPUT_2 ), OUTPUT_1_WIDTH);
OUTPUT_1 <= STD_LOGIC_VECTOR( UStmp(OUTPUT_1_WIDTH-1 DOWNTO 0) );
ELSE
Stmp := RESIZE( SIGNED( INPUT_1 ) - SIGNED( INPUT_2 ), OUTPUT_1_WIDTH);
OUTPUT_1 <= STD_LOGIC_VECTOR( Stmp(OUTPUT_1_WIDTH-1 DOWNTO 0) );
END IF;
END PROCESS;
END;
-- MULTIPLIER COMPONENT WITH VARIABLE INPUTS AND OUTPUT BITWIDTH
-- DEVELOPPED FOR THE GRAPHLAB TOOL BY BERTRAND LE GAL
-- IMS LABORATORY - UMR-CNRS 5218
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
entity MUL_Dynamic is
GENERIC(
C_SIGNED : NATURAL := 0;
INPUT_1_WIDTH : NATURAL := 8;
INPUT_2_WIDTH : NATURAL := 8;
OUTPUT_1_WIDTH : NATURAL := 8
);
port (
INPUT_1 :in STD_LOGIC_VECTOR(INPUT_1_WIDTH-1 DOWNTO 0);
INPUT_2 :in STD_LOGIC_VECTOR(INPUT_2_WIDTH-1 DOWNTO 0);
OUTPUT_1 :out STD_LOGIC_VECTOR(OUTPUT_1_WIDTH-1 DOWNTO 0)
);
end;
architecture behavior of MUL_Dynamic is
-- MAXIMUM FUNCTION TO COMPUTE THE INTERNAL DATA SIZE
FUNCTION maximum (left, right : NATURAL) return NATURAL IS
BEGIN -- function max
IF LEFT > RIGHT THEN RETURN LEFT;
ELSE RETURN RIGHT;
END IF;
END FUNCTION maximum;
BEGIN
process (INPUT_1, INPUT_2)
VARIABLE Stmp : SIGNED ((INPUT_1_WIDTH+INPUT_2_WIDTH)-1 DOWNTO 0);
VARIABLE UStmp : UNSIGNED((INPUT_1_WIDTH+INPUT_2_WIDTH)-1 DOWNTO 0);
begin
IF C_SIGNED = 0 THEN
UStmp := RESIZE( UNSIGNED( INPUT_1 ) * UNSIGNED( INPUT_2 ), INPUT_1_WIDTH+INPUT_2_WIDTH);
OUTPUT_1 <= STD_LOGIC_VECTOR( UStmp(OUTPUT_1_WIDTH-1 DOWNTO 0) );
ELSE
Stmp := RESIZE( SIGNED( INPUT_1 ) * SIGNED( INPUT_2 ), INPUT_1_WIDTH+INPUT_2_WIDTH);
OUTPUT_1 <= STD_LOGIC_VECTOR( Stmp(OUTPUT_1_WIDTH-1 DOWNTO 0) );
END IF;
end process;
end;
-- SQUARE COMPONENT WITH VARIABLE INPUTS AND OUTPUT BITWIDTH
-- DEVELOPPED FOR THE GRAPHLAB TOOL BY BERTRAND LE GAL
-- IMS LABORATORY - UMR-CNRS 5218
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
entity SQR_Dynamic is
GENERIC(
C_SIGNED : NATURAL := 0;
INPUT_1_WIDTH : NATURAL := 8;
OUTPUT_1_WIDTH : NATURAL := 8
);
port (
INPUT_1 :in STD_LOGIC_VECTOR(INPUT_1_WIDTH-1 DOWNTO 0);
OUTPUT_1 :out STD_LOGIC_VECTOR(OUTPUT_1_WIDTH-1 DOWNTO 0)
);
end;
architecture behavior of SQR_Dynamic is
begin
process (INPUT_1)
VARIABLE Stmp : SIGNED ((INPUT_1_WIDTH+INPUT_1_WIDTH)-1 DOWNTO 0);
VARIABLE UStmp : UNSIGNED((INPUT_1_WIDTH+INPUT_1_WIDTH)-1 DOWNTO 0);
begin
IF C_SIGNED = 0 THEN
UStmp := UNSIGNED( INPUT_1 ) * UNSIGNED( INPUT_1 );
OUTPUT_1 <= STD_LOGIC_VECTOR( UStmp(OUTPUT_1_WIDTH-1 DOWNTO 0) );
ELSE
Stmp := SIGNED( INPUT_1 ) * SIGNED( INPUT_1 );
OUTPUT_1 <= STD_LOGIC_VECTOR( Stmp(OUTPUT_1_WIDTH-1 DOWNTO 0) );
END IF;
end process;
end;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
ENTITY ABS_Dynamic IS
GENERIC(
C_SIGNED : NATURAL := 0;
INPUT_1_WIDTH : NATURAL := 8;
OUTPUT_1_WIDTH : NATURAL := 8
);
PORT (
INPUT_1 :IN STD_LOGIC_VECTOR(INPUT_1_WIDTH-1 DOWNTO 0);
OUTPUT_1 :OUT STD_LOGIC_VECTOR(OUTPUT_1_WIDTH-1 DOWNTO 0)
);
END;
architecture behavior of ABS_Dynamic is
-- MAXIMUM FUNCTION TO COMPUTE THE INTERNAL DATA SIZE
FUNCTION minimum (left, right : NATURAL) return NATURAL IS
BEGIN -- function max
IF LEFT < RIGHT THEN RETURN LEFT;
ELSE RETURN RIGHT;
END IF;
END FUNCTION minimum;
BEGIN
PROCESS (INPUT_1)
CONSTANT SIZE : NATURAL := minimum(INPUT_1_WIDTH, OUTPUT_1_WIDTH);
VARIABLE Stmp : SIGNED (SIZE-1 DOWNTO 0);
VARIABLE UStmp : UNSIGNED(SIZE-1 DOWNTO 0);
BEGIN
IF C_SIGNED = 0 THEN
UStmp := RESIZE( UNSIGNED(INPUT_1), OUTPUT_1_WIDTH);
OUTPUT_1 <= STD_LOGIC_VECTOR( UStmp(OUTPUT_1_WIDTH-1 DOWNTO 0) );
ELSE
Stmp := RESIZE( abs(SIGNED( INPUT_1 )), OUTPUT_1_WIDTH);
OUTPUT_1 <= STD_LOGIC_VECTOR( Stmp(OUTPUT_1_WIDTH-1 DOWNTO 0) );
END IF;
END PROCESS;
END;
| gpl-3.0 | b5846aca6f0ecc976f9d326bdb479bfb | 0.656605 | 3.079479 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/plasma_asic.vhd | 1 | 12,506 | ---------------------------------------------------------------------
-- TITLE: Plamsa Interface (clock divider and interface to FPGA board)
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 9/15/07
-- FILENAME: plasma_3e.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity divides the clock by two and interfaces to the
-- Xilinx Spartan-3E XC3S200FT256-4 FPGA with DDR.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
--use work.mlite_pack.all;
entity plasma_asic is
port(CLK_50MHZ : in std_logic;
RS232_DCE_RXD : in std_logic;
RS232_DCE_TXD : out std_logic;
SD_CK_P : out std_logic; --DDR SDRAM clock_positive
SD_CK_N : out std_logic; --clock_negative
SD_CKE : out std_logic; --clock_enable
SD_BA : out std_logic_vector(1 downto 0); --bank_address
SD_A : out std_logic_vector(12 downto 0); --address(row or col)
SD_CS : out std_logic; --chip_select
SD_RAS : out std_logic; --row_address_strobe
SD_CAS : out std_logic; --column_address_strobe
SD_WE : out std_logic; --write_enable
SD_DQ : inout std_logic_vector(15 downto 0); --data
SD_UDM : out std_logic; --upper_byte_enable
SD_UDQS : inout std_logic; --upper_data_strobe
SD_LDM : out std_logic; --low_byte_enable
SD_LDQS : inout std_logic; --low_data_strobe
E_MDC : out std_logic; --Ethernet PHY
E_MDIO : inout std_logic; --management data in/out
E_RX_CLK : in std_logic; --receive clock
E_RX_DV : in std_logic; --data valid
E_RXD : in std_logic_vector(3 downto 0);
E_TX_CLK : in std_logic; --transmit clock
E_TX_EN : out std_logic; --data valid
E_TXD : out std_logic_vector(3 downto 0);
SF_CE0 : out std_logic; --NOR flash
SF_OE : out std_logic;
SF_WE : out std_logic;
SF_BYTE : out std_logic;
SF_STS : in std_logic; --status
SF_A : out std_logic_vector(24 downto 0);
SF_D : inout std_logic_vector(15 downto 1);
SPI_MISO : inout std_logic;
VGA_VSYNC : out std_logic; --VGA port
VGA_HSYNC : out std_logic;
VGA_RED : out std_logic;
VGA_GREEN : out std_logic;
VGA_BLUE : out std_logic;
PS2_CLK : in std_logic; --Keyboard
PS2_DATA : in std_logic;
LED : out std_logic_vector(7 downto 0);
ROT_CENTER : in std_logic;
ROT_A : in std_logic;
ROT_B : in std_logic;
BTN_EAST : in std_logic;
BTN_NORTH : in std_logic;
BTN_SOUTH : in std_logic;
BTN_WEST : in std_logic;
SW : in std_logic_vector(3 downto 0));
end; --entity plasma_asic
architecture logic of plasma_asic is
component plasma
generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0';
use_cache : std_logic := '0');
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic;
no_ddr_start : out std_logic;
no_ddr_stop : out std_logic;
--
-- SIGNAUX PERMETTANT D'INTERCONNECTER LE PROCESSEUR AVEC LE BUS PCIe
-- EN SIMULATION CES DERNIERS SONT CABLES A LA MASSE (PAS DE PCIe)
--
signal fifo_1_out_data : STD_LOGIC_VECTOR (31 DOWNTO 0) := (others => '0');
signal fifo_1_compteur : STD_LOGIC_VECTOR (31 DOWNTO 0) := (others => '0');
signal fifo_2_compteur : STD_LOGIC_VECTOR (31 DOWNTO 0) := (others => '0');
signal fifo_2_in_data : STD_LOGIC_VECTOR (31 DOWNTO 0) := (others => '0');
signal fifo_1_read_en : STD_LOGIC := '0';
signal fifo_1_empty : STD_LOGIC := '0';
signal fifo_1_write_en : STD_LOGIC := '0';
signal fifo_2_full : STD_LOGIC := '0';
signal fifo_1_full : STD_LOGIC := '0';
signal fifo_1_valid : STD_LOGIC := '0';
signal fifo_2_empty : STD_LOGIC := '0';
signal fifo_2_valid : STD_LOGIC := '0';
--
-- Fin de gestion du PCIe
--
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0));
end component; --plasma
component ddr_ctrl
port(clk : in std_logic;
clk_2x : in std_logic;
reset_in : in std_logic;
address : in std_logic_vector(25 downto 2);
byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
data_r : out std_logic_vector(31 downto 0);
active : in std_logic;
no_start : in std_logic;
no_stop : in std_logic;
pause : out std_logic;
SD_CK_P : out std_logic; --clock_positive
SD_CK_N : out std_logic; --clock_negative
SD_CKE : out std_logic; --clock_enable
SD_BA : out std_logic_vector(1 downto 0); --bank_address
SD_A : out std_logic_vector(12 downto 0); --address(row or col)
SD_CS : out std_logic; --chip_select
SD_RAS : out std_logic; --row_address_strobe
SD_CAS : out std_logic; --column_address_strobe
SD_WE : out std_logic; --write_enable
SD_DQ : inout std_logic_vector(15 downto 0); --data
SD_UDM : out std_logic; --upper_byte_enable
SD_UDQS : inout std_logic; --upper_data_strobe
SD_LDM : out std_logic; --low_byte_enable
SD_LDQS : inout std_logic); --low_data_strobe
end component; --ddr
signal clk_reg : std_logic;
signal address : std_logic_vector(31 downto 2);
signal data_write : std_logic_vector(31 downto 0);
signal data_read : std_logic_vector(31 downto 0);
signal data_r_ddr : std_logic_vector(31 downto 0);
signal byte_we : std_logic_vector(3 downto 0);
signal write_enable : std_logic;
signal pause_ddr : std_logic;
signal pause : std_logic;
signal no_ddr_start : std_logic;
signal no_ddr_stop : std_logic;
signal ddr_active : std_logic;
signal flash_active : std_logic;
signal flash_cnt : std_logic_vector(1 downto 0);
signal flash_we : std_logic;
signal reset : std_logic;
signal gpio0_out : std_logic_vector(31 downto 0);
signal gpio0_in : std_logic_vector(31 downto 0);
begin --architecture
--Divide 50 MHz clock by two
clk_div: process(reset, CLK_50MHZ, clk_reg)
begin
if reset = '1' then
clk_reg <= '0';
elsif rising_edge(CLK_50MHZ) then
clk_reg <= not clk_reg;
end if;
end process; --clk_div
reset <= ROT_CENTER;
E_TX_EN <= gpio0_out(28); --Ethernet
E_TXD <= gpio0_out(27 downto 24);
E_MDC <= gpio0_out(23);
E_MDIO <= gpio0_out(21) when gpio0_out(22) = '1' else 'Z';
VGA_VSYNC <= gpio0_out(20);
VGA_HSYNC <= gpio0_out(19);
VGA_RED <= gpio0_out(18);
VGA_GREEN <= gpio0_out(17);
VGA_BLUE <= gpio0_out(16);
LED <= gpio0_out(7 downto 0);
gpio0_in(31 downto 21) <= (others => '0');
gpio0_in(20 downto 13) <= E_RX_CLK & E_RX_DV & E_RXD & E_TX_CLK & E_MDIO;
gpio0_in(12 downto 10) <= SF_STS & PS2_CLK & PS2_DATA;
gpio0_in(9 downto 0) <= ROT_A & ROT_B & BTN_EAST & BTN_NORTH &
BTN_SOUTH & BTN_WEST & SW;
ddr_active <= '1' when address(31 downto 28) = "0001" else '0';
flash_active <= '1' when address(31 downto 28) = "0011" else '0';
write_enable <= '1' when byte_we /= "0000" else '0';
u1_plama: plasma
generic map (memory_type => "XILINX_16X",
log_file => "UNUSED",
ethernet => '0',
use_cache => '0')
--generic map (memory_type => "DUAL_PORT_",
-- log_file => "output2.txt",
-- ethernet => '1')
PORT MAP (
clk => clk_reg,
reset => reset,
uart_write => RS232_DCE_TXD,
uart_read => RS232_DCE_RXD,
address => address,
byte_we => byte_we,
data_write => data_write,
data_read => data_read,
mem_pause_in => pause,
-- BLG START
fifo_1_out_data => fifo_1_out_data,
fifo_1_read_en => fifo_1_read_en,
fifo_1_empty => fifo_1_empty,
fifo_2_in_data => fifo_2_in_data,
fifo_1_write_en => fifo_1_write_en,
fifo_2_full => fifo_2_full,
fifo_1_full => fifo_1_full,
fifo_1_valid => fifo_1_valid,
fifo_2_empty => fifo_2_empty,
fifo_2_valid => fifo_2_valid,
fifo_1_compteur => fifo_1_compteur,
fifo_2_compteur => fifo_2_compteur,
-- BLG END
no_ddr_start => no_ddr_start,
no_ddr_stop => no_ddr_stop,
gpio0_out => gpio0_out,
gpioA_in => gpio0_in);
-- u2_ddr: ddr_ctrl
-- port map (
-- clk => clk_reg,
-- clk_2x => CLK_50MHZ,
-- reset_in => reset,
--
-- address => address(25 downto 2),
-- byte_we => byte_we,
-- data_w => data_write,
-- data_r => data_r_ddr,
-- active => ddr_active,
-- no_start => no_ddr_start,
-- no_stop => no_ddr_stop,
-- pause => pause_ddr,
--
-- SD_CK_P => SD_CK_P, --clock_positive
-- SD_CK_N => SD_CK_N, --clock_negative
-- SD_CKE => SD_CKE, --clock_enable
--
-- SD_BA => SD_BA, --bank_address
-- SD_A => SD_A, --address(row or col)
-- SD_CS => SD_CS, --chip_select
-- SD_RAS => SD_RAS, --row_address_strobe
-- SD_CAS => SD_CAS, --column_address_strobe
-- SD_WE => SD_WE, --write_enable
--
-- SD_DQ => SD_DQ, --data
-- SD_UDM => SD_UDM, --upper_byte_enable
-- SD_UDQS => SD_UDQS, --upper_data_strobe
-- SD_LDM => SD_LDM, --low_byte_enable
-- SD_LDQS => SD_LDQS); --low_data_strobe
--Flash control (only lower 16-bit data lines connected)
-- flash_ctrl: process(reset, clk_reg, flash_active, write_enable, flash_cnt, pause_ddr)
-- begin
-- if reset = '1' then
-- flash_cnt <= "00";
-- flash_we <= '1';
-- elsif rising_edge(clk_reg) then
-- if flash_active = '0' then
-- flash_cnt <= "00";
-- flash_we <= '1';
-- else
-- if write_enable = '1' and flash_cnt(1) = '0' then
-- flash_we <= '0';
-- else
-- flash_we <= '1';
-- end if;
-- if flash_cnt /= "11" then
-- flash_cnt <= flash_cnt + 1;
-- end if;
-- end if;
-- end if; --rising_edge(clk_reg)
-- if pause_ddr = '1' or (flash_active = '1' and flash_cnt /= "11") then
-- pause <= '1';
-- else
-- pause <= '0';
-- end if;
-- end process; --flash_ctrl
SF_CE0 <= not flash_active;
SF_OE <= write_enable or not flash_active;
SF_WE <= flash_we;
SF_BYTE <= '1'; --16-bit access
SF_A <= address(25 downto 2) & '0' when flash_active = '1' else "0000000000000000000000000";
SF_D <= data_write(15 downto 1) when flash_active = '1' and write_enable = '1' else "ZZZZZZZZZZZZZZZ";
SPI_MISO <= data_write(0) when flash_active = '1' and write_enable = '1' else 'Z';
data_read(31 downto 16) <= data_r_ddr(31 downto 16);
data_read(15 downto 0) <= data_r_ddr(15 downto 0) when flash_active = '0' else SF_D & SPI_MISO;
end; --architecture logic
| gpl-3.0 | c55b744bb92dd4c38083525b2b7b7a84 | 0.518871 | 3.174917 | false | false | false | false |
VLSI-EDA/UVVM_All | uvvm_vvc_framework/src/ti_data_queue_pkg.vhd | 2 | 26,776 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
package ti_data_queue_pkg is
-- Declaration of storage
subtype t_data_buffer is std_logic_vector(C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER - 1 downto 0);
shared variable shared_data_buffer : t_data_buffer;
type t_buffer_natural_array is array (C_NUMBER_OF_DATA_BUFFERS-1 downto 0) of natural;
type t_buffer_boolean_array is array (C_NUMBER_OF_DATA_BUFFERS-1 downto 0) of boolean;
type t_data_queue is protected
------------------------------------------
-- init_queue
------------------------------------------
-- This function allocates space in the buffer and returns an index that
-- must be used to access the queue.
--
-- - Parameters:
-- - queue_size_in_bits (natural) - The size of the queue
-- - scope - Log scope for all alerts/logs
--
-- - Returns: The index of the initiated queue (natural).
-- Returns 0 on error.
--
impure function init_queue(
queue_size_in_bits : natural;
scope : string := "data_queue"
) return natural;
------------------------------------------
-- init_queue
------------------------------------------
-- This procedure allocates space in the buffer at the given queue_idx.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
-- that shall be initialized.
-- - queue_size_in_bits (natural) - The size of the queue
-- - scope - Log scope for all alerts/logs
--
procedure init_queue(
queue_idx : natural;
queue_size_in_bits : natural;
scope : string := "data_queue"
);
------------------------------------------
-- flush
------------------------------------------
-- This procedure empties the queue given
-- by queue_idx.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
-- that shall be flushed.
--
procedure flush(
queue_idx : natural
);
------------------------------------------
-- push_back
------------------------------------------
-- This procedure pushes data to the end of a queue.
-- The size of the data is unconstrained, meaning that
-- it can be any size. Pushing data with a size that is
-- larger than the queue size results in wrapping, i.e.,
-- that when reaching the end the data remaining will over-
-- write the data that was written first.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
-- that shall be pushed to.
-- - data - The data that shall be pushed (slv)
--
procedure push_back(
queue_idx : natural;
data : std_logic_vector
);
------------------------------------------
-- peek_front
------------------------------------------
-- This function returns the data from the front
-- of the queue without popping it.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: The data from the front of the queue (slv). The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to peek from an empty queue is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to peek a larger value than the queue size is allowed
-- but triggers a TB_WARNING. Will wrap.
--
--
impure function peek_front(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- peek_back
------------------------------------------
-- This function returns the data from the back
-- of the queue without popping it.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: The data from the back of the queue (slv). The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to peek from an empty queue is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to peek a larger value than the queue size is allowed
-- but triggers a TB_WARNING. Will wrap.
--
--
impure function peek_back(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- pop_back
------------------------------------------
-- This function returns the data from the back
-- and removes the returned data from the queue.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: The data from the back of the queue (slv). The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to pop from an empty queue is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to pop a larger value than the queue size is allowed
-- but triggers a TB_WARNING.
--
--
impure function pop_back(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- pop_front
------------------------------------------
-- This function returns the data from the front
-- and removes the returned data from the queue.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: The data from the front of the queue (slv). The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to pop from an empty queue is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to pop a larger value than the queue size is allowed
-- but triggers a TB_WARNING.
--
--
impure function pop_front(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- get_count
------------------------------------------
-- This function returns a natural indicating the number of elements
-- currently occupying the buffer given by queue_idx.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
--
-- - Returns: The number of elements occupying the queue (natural).
--
--
impure function get_count(
queue_idx : natural
) return natural;
------------------------------------------
-- get_queue_count_max
------------------------------------------
-- This function returns a natural indicating the maximum number
-- of elements that can occupy the buffer given by queue_idx.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
--
-- - Returns: The maximum number of elements that can be placed
-- in the queue (natural).
--
--
impure function get_queue_count_max(
queue_idx : natural
) return natural;
------------------------------------------
-- get_queue_is_full
------------------------------------------
-- This function returns a boolean indicating if the
-- queue is full or not.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
--
-- - Returns: TRUE if queue is full, FALSE if not.
--
--
impure function get_queue_is_full(
queue_idx : natural
) return boolean;
------------------------------------------
-- deallocate_buffer
------------------------------------------
-- This procedure resets the entire std_logic_vector and all
-- variable arrays related to the buffer, effectively removing all queues.
--
-- - Parameters:
-- - dummy - VOID
--
--
procedure deallocate_buffer(
dummy : t_void
);
end protected;
end package ti_data_queue_pkg;
package body ti_data_queue_pkg is
type t_data_queue is protected body
-- Internal variables for the data queue
-- The buffer is one large std_logic_vector of size C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER.
-- There are several queues that can be instantiated in the slv.
-- There is one set of variables per queue.
variable v_queue_initialized : t_buffer_boolean_array := (others => false);
variable v_queue_size_in_bits : t_buffer_natural_array := (others => 0);
variable v_count : t_buffer_natural_array := (others => 0);
-- min_idx/max idx: These variables set the upper and lower limit of each queue in the buffer.
-- This is how the large slv buffer is divided into several smaller queues.
-- After a queue has been instantiated, all queue operations in the buffer
-- for a given idx will happen within the v_min_idx and v_max_idx boundary.
-- These variables will be set when a queue is instantiated, and will not
-- change afterwards.
variable v_min_idx : t_buffer_natural_array := (others => 0);
variable v_max_idx : t_buffer_natural_array := (others => 0);
variable v_next_available_idx : natural := 0; -- Where the v_min_idx of the next queue initialized shall be set.
-- first_idx/last_idx: These variables set the current indices within a queue, i.e., within
-- the min_idx/max_idx boundary. These variables will change every time
-- a given queue has data pushed or popped.
variable v_first_idx : t_buffer_natural_array := (others => 0);
variable v_last_idx : t_buffer_natural_array := (others => 0);
type t_string_pointer is access string;
variable v_scope : t_string_pointer := NULL;
------------------------------------------
-- init_queue
------------------------------------------
impure function init_queue(
queue_size_in_bits : natural;
scope : string := "data_queue"
) return natural is
variable vr_queue_idx : natural;
variable vr_queue_idx_found : boolean := false;
begin
if v_scope = NULL then
v_scope := new string'(scope);
end if;
if not check_value(v_next_available_idx < C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER, TB_ERROR,
"init_queue called, but no more space in buffer!", v_scope.all, ID_NEVER)
then
return 0;
end if;
-- Find first available queue
-- and tag as initialized
for i in t_buffer_boolean_array'range loop
if not v_queue_initialized(i) then
-- Save queue idx
vr_queue_idx := i;
vr_queue_idx_found := true;
-- Tag this queue as initialized
v_queue_initialized(vr_queue_idx) := true;
exit; -- exit loop
end if;
end loop;
-- Verify that an available queue idx was found, else trigger alert and return 0
if not check_value(vr_queue_idx_found, TB_ERROR,
"init_queue called, but all queues have already been initialized!", v_scope.all, ID_NEVER)
then
return 0;
end if;
-- Set buffer size for this buffer to queue_size_in_bits
if queue_size_in_bits <= (C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER - 1) - (v_next_available_idx - 1) then -- less than or equal to the remaining total buffer space available
v_queue_size_in_bits(vr_queue_idx) := queue_size_in_bits;
else
alert(TB_ERROR, "queue_size_in_bits larger than maximum allowed!", v_scope.all);
v_queue_size_in_bits(vr_queue_idx) := (C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER - 1) - v_next_available_idx; -- Set to remaining available bits
end if;
-- Set starting and ending indices for this queue_idx
v_min_idx(vr_queue_idx) := v_next_available_idx;
v_max_idx(vr_queue_idx) := v_min_idx(vr_queue_idx) + v_queue_size_in_bits(vr_queue_idx) - 1;
v_first_idx(vr_queue_idx) := v_min_idx(vr_queue_idx);
v_last_idx(vr_queue_idx) := v_min_idx(vr_queue_idx);
v_next_available_idx := v_max_idx(vr_queue_idx) + 1;
log(ID_UVVM_DATA_QUEUE, "Queue " & to_string(vr_queue_idx) & " initialized with buffer size " & to_string(v_queue_size_in_bits(vr_queue_idx)) & ".", v_scope.all);
-- Clear the buffer just to be sure
flush(vr_queue_idx);
-- Return the index of the buffer
return vr_queue_idx;
end function;
------------------------------------------
-- init_queue
------------------------------------------
procedure init_queue(
queue_idx : natural;
queue_size_in_bits : natural;
scope : string := "data_queue"
) is
begin
if v_scope = NULL then
v_scope := new string'(scope);
end if;
if not v_queue_initialized(queue_idx) then
-- Set buffer size for this buffer to queue_size_in_bits
if queue_size_in_bits <= (C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER - 1) - (v_next_available_idx - 1) then -- less than or equal to the remaining total buffer space available
v_queue_size_in_bits(queue_idx) := queue_size_in_bits;
else
alert(TB_ERROR, "queue_size_in_bits larger than maximum allowed!", v_scope.all);
v_queue_size_in_bits(queue_idx) := (C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER - 1) - v_next_available_idx; -- Set to remaining available bits
end if;
-- Set starting and ending indices for this queue_idx
v_min_idx(queue_idx) := v_next_available_idx;
v_max_idx(queue_idx) := v_min_idx(queue_idx) + v_queue_size_in_bits(queue_idx) - 1;
v_first_idx(queue_idx) := v_min_idx(queue_idx);
v_last_idx(queue_idx) := v_min_idx(queue_idx);
v_next_available_idx := v_max_idx(queue_idx) + 1;
-- Tag this buffer as initialized
v_queue_initialized(queue_idx) := true;
log(ID_UVVM_DATA_QUEUE, "Queue " & to_string(queue_idx) & " initialized with buffer size " & to_string(v_queue_size_in_bits(queue_idx)) & ".", v_scope.all);
-- Clear the buffer just to be sure
flush(queue_idx);
else
alert(TB_ERROR, "init_queue called, but the desired buffer index is already in use! No action taken.", v_scope.all);
return;
end if;
end procedure;
------------------------------------------
-- push_back
------------------------------------------
procedure push_back(
queue_idx : natural;
data : std_logic_vector
) is
alias a_data : std_logic_vector(data'length - 1 downto 0) is data;
begin
if check_value(v_queue_initialized(queue_idx), TB_ERROR,
"push_back called, but queue " & to_string(queue_idx) & " not initialized.", v_scope.all, ID_NEVER)
then
for i in a_data'right to a_data'left loop -- From right to left since LSB shall be first in the queue.
shared_data_buffer(v_last_idx(queue_idx)) := a_data(i);
if v_last_idx(queue_idx) /= v_max_idx(queue_idx) then
v_last_idx(queue_idx) := v_last_idx(queue_idx) + 1;
else
v_last_idx(queue_idx) := v_min_idx(queue_idx);
end if;
v_count(queue_idx) := v_count(queue_idx) + 1;
end loop;
log(ID_UVVM_DATA_QUEUE, "Data " & to_string(data, HEX) & " pushed to back of queue " & to_string(queue_idx) & " (index " & to_string(v_last_idx(queue_idx)) & "). Fill level is " & to_string(v_count(queue_idx)) & "/" & to_string(v_queue_size_in_bits(queue_idx)) & ".", v_scope.all);
end if;
end procedure;
------------------------------------------
-- flush
------------------------------------------
procedure flush(
queue_idx : natural
) is
begin
check_value(v_queue_initialized(queue_idx), TB_WARNING, "flush called, but queue " & to_string(queue_idx) & " not initialized.", v_scope.all, ID_NEVER);
shared_data_buffer(v_max_idx(queue_idx) downto v_min_idx(queue_idx)) := (others => '0');
v_first_idx(queue_idx) := v_min_idx(queue_idx);
v_last_idx(queue_idx) := v_min_idx(queue_idx);
v_count(queue_idx) := 0;
end procedure;
------------------------------------------
-- peek_front
------------------------------------------
impure function peek_front(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector is
variable v_return_entry : std_logic_vector(entry_size_in_bits - 1 downto 0) := (others => '0');
variable v_current_idx : natural;
begin
check_value(v_queue_initialized(queue_idx), TB_ERROR, "peek_front() called, but queue " & to_string(queue_idx) & " not initialized.", v_scope.all, ID_NEVER);
check_value(v_count(queue_idx) > 0, TB_WARNING, "peek_front() when queue " & to_string(queue_idx) & " is empty. Return value will be garbage.", v_scope.all, ID_NEVER);
check_value(entry_size_in_bits <= v_queue_size_in_bits(queue_idx), TB_WARNING, "peek_front called, but entry size is larger than buffer size!", v_scope.all, ID_NEVER);
v_current_idx := v_first_idx(queue_idx);
-- Generate return value
for i in 0 to v_return_entry'length - 1 loop
v_return_entry(i) := shared_data_buffer(v_current_idx);
if v_current_idx < v_max_idx(queue_idx) then
v_current_idx := v_current_idx + 1;
else
v_current_idx := v_min_idx(queue_idx);
end if;
end loop;
return v_return_entry;
end function;
------------------------------------------
-- peek_back
------------------------------------------
impure function peek_back(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector is
variable v_return_entry : std_logic_vector(entry_size_in_bits - 1 downto 0) := (others => '0');
variable v_current_idx : natural;
begin
check_value(v_queue_initialized(queue_idx), TB_ERROR, "peek_back called, but queue not initialized.", v_scope.all, ID_NEVER);
check_value(v_count(queue_idx) > 0, TB_WARNING, "peek_back() when queue " & to_string(queue_idx) & " is empty. Return value will be garbage.", v_scope.all, ID_NEVER);
check_value(entry_size_in_bits <= v_queue_size_in_bits(queue_idx), TB_WARNING, "peek_back called, but entry size is larger than buffer size!", v_scope.all, ID_NEVER);
if v_last_idx(queue_idx) > 0 then
v_current_idx := v_last_idx(queue_idx) - 1;
else
v_current_idx := v_max_idx(queue_idx);
end if;
-- Generate return value
for i in v_return_entry'length - 1 downto 0 loop
v_return_entry(i) := shared_data_buffer(v_current_idx);
if v_current_idx > v_min_idx(queue_idx) then
v_current_idx := v_current_idx - 1;
else
v_current_idx := v_max_idx(queue_idx);
end if;
end loop;
return v_return_entry;
end function;
------------------------------------------
-- pop_back
------------------------------------------
impure function pop_back(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector is
variable v_return_entry : std_logic_vector(entry_size_in_bits-1 downto 0);
variable v_current_idx : natural;
begin
check_value(v_queue_initialized(queue_idx), TB_ERROR, "pop_back called, but queue " & to_string(queue_idx) & " not initialized.", v_scope.all, ID_NEVER);
check_value(entry_size_in_bits <= v_queue_size_in_bits(queue_idx), TB_WARNING, "pop_back called, but entry size is larger than buffer size!", v_scope.all, ID_NEVER);
if v_queue_initialized(queue_idx) then
v_return_entry := peek_back(queue_idx, entry_size_in_bits);
if v_count(queue_idx) > 0 then
if v_last_idx(queue_idx) > v_min_idx(queue_idx) then
v_current_idx := v_last_idx(queue_idx) - 1;
else
v_current_idx := v_max_idx(queue_idx);
end if;
-- Clear fields that belong to the return value
for i in 0 to entry_size_in_bits - 1 loop
shared_data_buffer(v_current_idx) := '0';
if v_current_idx > v_min_idx(queue_idx) then
v_current_idx := v_current_idx - 1;
else
v_current_idx := v_max_idx(queue_idx);
end if;
v_count(queue_idx) := v_count(queue_idx) - 1;
end loop;
-- Set last idx
if v_current_idx < v_max_idx(queue_idx) then
v_last_idx(queue_idx) := v_current_idx + 1;
else
v_last_idx(queue_idx) := v_min_idx(queue_idx);
end if;
end if;
end if;
return v_return_entry;
end function;
------------------------------------------
-- pop_front
------------------------------------------
impure function pop_front(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector is
variable v_return_entry : std_logic_vector(entry_size_in_bits-1 downto 0);
variable v_current_idx : natural := v_first_idx(queue_idx);
begin
check_value(entry_size_in_bits <= v_queue_size_in_bits(queue_idx), TB_WARNING, "pop_front called, but entry size is larger than buffer size!", v_scope.all, ID_NEVER);
if check_value(v_queue_initialized(queue_idx), TB_ERROR,
"pop_front called, but queue " & to_string(queue_idx) & " not initialized.", v_scope.all, ID_NEVER)
then
v_return_entry := peek_front(queue_idx, entry_size_in_bits);
if v_count(queue_idx) > 0 then
-- v_first_idx points to the idx PREVIOUS to the first element in the buffer.
-- Therefore must correct if at max_idx.
v_current_idx := v_first_idx(queue_idx);
-- Clear fields that belong to the return value
for i in 0 to entry_size_in_bits - 1 loop
shared_data_buffer(v_current_idx) := '0';
if v_current_idx < v_max_idx(queue_idx) then
v_current_idx := v_current_idx + 1;
else
v_current_idx := v_min_idx(queue_idx);
end if;
v_count(queue_idx) := v_count(queue_idx) - 1;
end loop;
v_first_idx(queue_idx) := v_current_idx;
end if;
return v_return_entry;
end if;
v_return_entry := (others => '0');
return v_return_entry;
end function;
------------------------------------------
-- get_count
------------------------------------------
impure function get_count(
queue_idx : natural
) return natural is
begin
check_value(v_queue_initialized(queue_idx), TB_WARNING, "get_count called, but queue " & to_string(queue_idx) & " not initialized.", v_scope.all, ID_NEVER);
return v_count(queue_idx);
end function;
------------------------------------------
-- get_queue_count_max
------------------------------------------
impure function get_queue_count_max(
queue_idx : natural
) return natural is
begin
check_value(v_queue_initialized(queue_idx), TB_WARNING, "get_queue_count_max called, but queue " & to_string(queue_idx) & " not initialized.", v_scope.all, ID_NEVER);
return v_queue_size_in_bits(queue_idx);
end function;
------------------------------------------
-- get_queue_is_full
------------------------------------------
impure function get_queue_is_full(
queue_idx : natural
) return boolean is
begin
check_value(v_queue_initialized(queue_idx), TB_WARNING, "get_queue_is_full called, but queue " & to_string(queue_idx) & " not initialized.", v_scope.all, ID_NEVER);
if v_count(queue_idx) >= v_queue_size_in_bits(queue_idx) then
return true;
else
return false;
end if;
end function;
------------------------------------------
-- deallocate_buffer
------------------------------------------
procedure deallocate_buffer(
dummy : t_void
) is
begin
shared_data_buffer := (others => '0');
v_queue_initialized := (others => false);
v_queue_size_in_bits := (others => 0);
v_count := (others => 0);
v_min_idx := (others => 0);
v_max_idx := (others => 0);
v_first_idx := (others => 0);
v_last_idx := (others => 0);
v_next_available_idx := 0;
log(ID_UVVM_DATA_QUEUE, "Buffer has been deallocated, i.e., all queues removed.", v_scope.all);
end procedure;
end protected body;
end package body ti_data_queue_pkg;
| mit | 38020bb32ee2535638fbf553854e53f0 | 0.540708 | 3.942285 | false | false | false | false |
chibby0ne/vhdl-book | Chapter8/example8_2_dir/example8_2_tb.vhd | 1 | 1,237 | --!
--! Copyright (C) 2010 - 2013 Creonic GmbH
--!
--! @file: example8_2_tb.vhd
--! @brief: testbench for circular shift register with component
--! @author: Antonio Gutierrez
--! @date: 2014-04-10
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------
entity circular_shift_tb is
end entity circular_shift_tb;
--------------------------------------
architecture circuit of circular_shift_tb is
-- dut declaration
component circular_shift is
port (
clk, load: in bit;
d: in bit_vector(0 to 3);
q: buffer bit_vector(0 to 3));
end component circular_shift;
-- signal declarations
signal clk_tb: bit := '0';
signal load_tb: bit := '1';
signal d_tb: bit_vector(0 to 3) := "0110";
signal q_tb: bit_vector(0 to 3);
begin
-- dut instantiation
dut: circular_shift port map (
clk_tb, load_tb, d_tb, q_tb
);
-- stimuli generation
-- clk
clk_tb <= not clk_tb after 20 ns;
-- load
load_tb <= '0' after 21 ns, '1' after 200 ns, '0' after 221 ns;
-- d_tb
d_tb <= "1001" after 200 ns, "0000" after 221 ns;
end architecture circuit;
| gpl-3.0 | aa2d27ef5b5ef5aa9b3ac8114a2ebeac | 0.552142 | 3.575145 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/LDPC/Q16_8_ADD.vhd | 1 | 1,666 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------
-- synthesis translate_off
library ims;
use ims.coprocessor.all;
-- synthesis translate_on
-------------------------------------------------------------------------
entity Q16_8_ADD is
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end;
architecture rtl of Q16_8_ADD is
begin
-------------------------------------------------------------------------
-- synthesis translate_off
PROCESS
BEGIN
WAIT FOR 1 ns;
printmsg("(IMS) Q16_8_ADD : ALLOCATION OK !");
WAIT;
END PROCESS;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
PROCESS (INPUT_1, INPUT_2)
VARIABLE OP1 : SIGNED(16 downto 0);
VARIABLE OP2 : SIGNED(16 downto 0);
VARIABLE OP3 : SIGNED(16 downto 0);
begin
OP1 := SIGNED( INPUT_1(15) & INPUT_1(15 downto 0) );
OP2 := SIGNED( INPUT_2(15) & INPUT_2(15 downto 0) );
OP3 := OP1 + OP2;
if( OP3 > TO_SIGNED(32767, 17) ) THEN
OUTPUT_1 <= "0000000000000000" & STD_LOGIC_VECTOR(TO_SIGNED( 32767, 16));
elsif( OP3 < TO_SIGNED(-32768, 17) ) THEN
OUTPUT_1 <= "0000000000000000" & STD_LOGIC_VECTOR(TO_SIGNED(-32768, 16));
else
OUTPUT_1 <= "0000000000000000" & STD_LOGIC_VECTOR( OP3(15 downto 0) );
end if;
END PROCESS;
-------------------------------------------------------------------------
end;
| gpl-3.0 | ebb8a187dd349095bc146cc861cdaa2e | 0.468187 | 3.812357 | false | false | false | false |
chibby0ne/vhdl-book | Chapter10/exercise5_dir/lut_tb.vhd | 1 | 2,182 | --!
--! Copyright (C) 2010 - 2013 Creonic GmbH
--!
--! @file: lut_tb.vhd
--! @brief:
--! @author: Antonio Gutierrez
--! @date: 2014-04-03
--!
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------
entity lut_tb is
generic (PERIOD: time := 50 ns);
end entity lut_tb;
--------------------------------------
architecture circuit of lut_tb is
-- dut declaration
component lut is
-- generic(const_name const_type = const_value)
port (
clk: in std_logic;
inp: in integer range 0 to 7;
outp: out std_logic_vector(2 downto 0));
end component lut;
-- signal declarations
signal clk_tb: std_logic := '0';
signal inp_tb: integer range 0 to 7 := 0;
signal outp_tb: std_logic_vector(2 downto 0);
constant tp: time := 10 ns;
type t_lut is array (0 to 7) of std_logic_vector(2 downto 0);
constant luts_ver: t_lut := (
"011", -- 0
"100", -- 1
"110", -- 2
"111", -- 3
"010", -- 4
"001", -- 5
"101", -- 6
"000"); -- 7
begin
-- dut instantiation
lut_ins: lut port map (
clk => clk_tb,
inp => inp_tb,
outp => outp_tb
);
-- clock generation
clk_tb <= not clk_tb after PERIOD/2;
-- stimuli generation (inp)
process
variable i: natural range 0 to 7 := 0;
begin
if (now < 350 ns) then
wait for PERIOD/2 + tp;
inp_tb <= i;
i := i + 1;
wait for PERIOD/2 - tp;
else
wait;
end if;
end process;
-- output verification
process
variable outp_ver: std_logic_vector(2 downto 0);
begin
if (now < 350 ns) then
wait for PERIOD/2 + tp;
outp_ver := luts_ver(inp_tb);
assert outp_tb = outp_ver
report "results is not expected at t = " & time'image(now)
severity failure;
wait for PERIOD/2 - tp;
else
assert false
report "all good"
severity note;
wait;
end if;
end process;
end architecture circuit;
| gpl-3.0 | e96e52491f58a54b21d63b5e70423d3f | 0.500917 | 3.749141 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/LDPC/Q16_8_V_to_C_RAM.vhd | 1 | 46,866 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------
-- synthesis translate_off
library ims;
use ims.coprocessor.all;
use ims.conversion.all;
-- synthesis translate_on
-------------------------------------------------------------------------
ENTITY Q16_8_V_to_C_RAM is
PORT (
RESET : in STD_LOGIC;
CLOCK : in STD_LOGIC;
HOLDN : in std_ulogic;
WRITE_EN : in STD_LOGIC;
READ_EN : in STD_LOGIC;
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END;
architecture cRAM of Q16_8_V_to_C_RAM is
type ram_type is array (0 to 1824-1) of STD_LOGIC_VECTOR (15 downto 0);
type rom_type is array (0 to 1824-1) of UNSIGNED (10 downto 0);
signal RAM : ram_type;
constant ROM : rom_type:= (
TO_UNSIGNED( 114, 11), TO_UNSIGNED( 174, 11), TO_UNSIGNED( 342, 11), TO_UNSIGNED( 444, 11), TO_UNSIGNED( 636, 11), TO_UNSIGNED( 930, 11), TO_UNSIGNED( 810, 11), TO_UNSIGNED(1026, 11),
TO_UNSIGNED(1152, 11), TO_UNSIGNED(1467, 11), TO_UNSIGNED(1600, 11), TO_UNSIGNED(1719, 11), TO_UNSIGNED( 18, 11), TO_UNSIGNED(1027, 11), TO_UNSIGNED(1502, 11), TO_UNSIGNED( 24, 11),
TO_UNSIGNED(1032, 11), TO_UNSIGNED(1509, 11), TO_UNSIGNED( 30, 11), TO_UNSIGNED(1038, 11), TO_UNSIGNED(1516, 11), TO_UNSIGNED( 36, 11), TO_UNSIGNED(1044, 11), TO_UNSIGNED(1523, 11),
TO_UNSIGNED( 42, 11), TO_UNSIGNED(1050, 11), TO_UNSIGNED(1530, 11), TO_UNSIGNED( 48, 11), TO_UNSIGNED(1056, 11), TO_UNSIGNED(1537, 11), TO_UNSIGNED( 54, 11), TO_UNSIGNED(1062, 11),
TO_UNSIGNED(1544, 11), TO_UNSIGNED( 60, 11), TO_UNSIGNED(1068, 11), TO_UNSIGNED(1551, 11), TO_UNSIGNED( 66, 11), TO_UNSIGNED(1074, 11), TO_UNSIGNED(1558, 11), TO_UNSIGNED( 72, 11),
TO_UNSIGNED(1080, 11), TO_UNSIGNED(1565, 11), TO_UNSIGNED( 78, 11), TO_UNSIGNED(1086, 11), TO_UNSIGNED(1572, 11), TO_UNSIGNED( 84, 11), TO_UNSIGNED(1092, 11), TO_UNSIGNED(1579, 11),
TO_UNSIGNED( 90, 11), TO_UNSIGNED(1098, 11), TO_UNSIGNED(1586, 11), TO_UNSIGNED( 96, 11), TO_UNSIGNED(1104, 11), TO_UNSIGNED(1593, 11), TO_UNSIGNED( 102, 11), TO_UNSIGNED(1110, 11),
TO_UNSIGNED(1601, 11), TO_UNSIGNED( 108, 11), TO_UNSIGNED(1116, 11), TO_UNSIGNED(1607, 11), TO_UNSIGNED( 115, 11), TO_UNSIGNED(1122, 11), TO_UNSIGNED(1614, 11), TO_UNSIGNED( 120, 11),
TO_UNSIGNED(1128, 11), TO_UNSIGNED(1621, 11), TO_UNSIGNED( 126, 11), TO_UNSIGNED(1134, 11), TO_UNSIGNED(1628, 11), TO_UNSIGNED( 132, 11), TO_UNSIGNED(1140, 11), TO_UNSIGNED(1635, 11),
TO_UNSIGNED( 138, 11), TO_UNSIGNED(1146, 11), TO_UNSIGNED(1642, 11), TO_UNSIGNED( 0, 11), TO_UNSIGNED(1008, 11), TO_UNSIGNED(1649, 11), TO_UNSIGNED( 798, 11), TO_UNSIGNED(1063, 11),
TO_UNSIGNED(1159, 11), TO_UNSIGNED(1369, 11), TO_UNSIGNED(1622, 11), TO_UNSIGNED(1720, 11), TO_UNSIGNED( 6, 11), TO_UNSIGNED(1160, 11), TO_UNSIGNED( 12, 11), TO_UNSIGNED(1166, 11),
TO_UNSIGNED( 19, 11), TO_UNSIGNED(1173, 11), TO_UNSIGNED( 25, 11), TO_UNSIGNED(1180, 11), TO_UNSIGNED( 31, 11), TO_UNSIGNED(1187, 11), TO_UNSIGNED( 37, 11), TO_UNSIGNED(1194, 11),
TO_UNSIGNED( 43, 11), TO_UNSIGNED(1201, 11), TO_UNSIGNED( 49, 11), TO_UNSIGNED(1208, 11), TO_UNSIGNED( 55, 11), TO_UNSIGNED(1215, 11), TO_UNSIGNED( 61, 11), TO_UNSIGNED(1222, 11),
TO_UNSIGNED( 67, 11), TO_UNSIGNED(1229, 11), TO_UNSIGNED( 73, 11), TO_UNSIGNED(1236, 11), TO_UNSIGNED( 79, 11), TO_UNSIGNED(1243, 11), TO_UNSIGNED( 85, 11), TO_UNSIGNED(1250, 11),
TO_UNSIGNED( 91, 11), TO_UNSIGNED(1257, 11), TO_UNSIGNED( 97, 11), TO_UNSIGNED(1264, 11), TO_UNSIGNED( 103, 11), TO_UNSIGNED(1271, 11), TO_UNSIGNED( 109, 11), TO_UNSIGNED(1278, 11),
TO_UNSIGNED( 116, 11), TO_UNSIGNED(1285, 11), TO_UNSIGNED( 121, 11), TO_UNSIGNED(1292, 11), TO_UNSIGNED( 127, 11), TO_UNSIGNED(1299, 11), TO_UNSIGNED( 133, 11), TO_UNSIGNED(1306, 11),
TO_UNSIGNED( 139, 11), TO_UNSIGNED(1313, 11), TO_UNSIGNED( 792, 11), TO_UNSIGNED(1057, 11), TO_UNSIGNED(1153, 11), TO_UNSIGNED(1362, 11), TO_UNSIGNED(1615, 11), TO_UNSIGNED(1712, 11),
TO_UNSIGNED( 822, 11), TO_UNSIGNED(1039, 11), TO_UNSIGNED(1167, 11), TO_UNSIGNED(1481, 11), TO_UNSIGNED(1616, 11), TO_UNSIGNED(1733, 11), TO_UNSIGNED(1168, 11), TO_UNSIGNED(1334, 11),
TO_UNSIGNED(1174, 11), TO_UNSIGNED(1341, 11), TO_UNSIGNED(1181, 11), TO_UNSIGNED(1348, 11), TO_UNSIGNED(1188, 11), TO_UNSIGNED(1355, 11), TO_UNSIGNED(1195, 11), TO_UNSIGNED(1363, 11),
TO_UNSIGNED(1202, 11), TO_UNSIGNED(1370, 11), TO_UNSIGNED(1209, 11), TO_UNSIGNED(1376, 11), TO_UNSIGNED(1216, 11), TO_UNSIGNED(1383, 11), TO_UNSIGNED(1223, 11), TO_UNSIGNED(1390, 11),
TO_UNSIGNED(1230, 11), TO_UNSIGNED(1397, 11), TO_UNSIGNED(1237, 11), TO_UNSIGNED(1404, 11), TO_UNSIGNED(1244, 11), TO_UNSIGNED(1411, 11), TO_UNSIGNED(1251, 11), TO_UNSIGNED(1418, 11),
TO_UNSIGNED(1258, 11), TO_UNSIGNED(1425, 11), TO_UNSIGNED(1265, 11), TO_UNSIGNED(1432, 11), TO_UNSIGNED(1272, 11), TO_UNSIGNED(1439, 11), TO_UNSIGNED(1279, 11), TO_UNSIGNED(1446, 11),
TO_UNSIGNED(1286, 11), TO_UNSIGNED(1453, 11), TO_UNSIGNED(1293, 11), TO_UNSIGNED(1460, 11), TO_UNSIGNED(1300, 11), TO_UNSIGNED(1468, 11), TO_UNSIGNED(1307, 11), TO_UNSIGNED(1474, 11),
TO_UNSIGNED(1314, 11), TO_UNSIGNED(1482, 11), TO_UNSIGNED( 144, 11), TO_UNSIGNED(1320, 11), TO_UNSIGNED( 150, 11), TO_UNSIGNED(1327, 11), TO_UNSIGNED( 156, 11), TO_UNSIGNED(1335, 11),
TO_UNSIGNED( 162, 11), TO_UNSIGNED(1342, 11), TO_UNSIGNED( 168, 11), TO_UNSIGNED(1349, 11), TO_UNSIGNED( 175, 11), TO_UNSIGNED(1356, 11), TO_UNSIGNED( 180, 11), TO_UNSIGNED(1364, 11),
TO_UNSIGNED( 186, 11), TO_UNSIGNED(1371, 11), TO_UNSIGNED( 192, 11), TO_UNSIGNED(1377, 11), TO_UNSIGNED( 198, 11), TO_UNSIGNED(1384, 11), TO_UNSIGNED( 204, 11), TO_UNSIGNED(1391, 11),
TO_UNSIGNED( 210, 11), TO_UNSIGNED(1398, 11), TO_UNSIGNED( 216, 11), TO_UNSIGNED(1405, 11), TO_UNSIGNED( 222, 11), TO_UNSIGNED(1412, 11), TO_UNSIGNED( 228, 11), TO_UNSIGNED(1419, 11),
TO_UNSIGNED( 234, 11), TO_UNSIGNED(1426, 11), TO_UNSIGNED( 240, 11), TO_UNSIGNED(1433, 11), TO_UNSIGNED( 246, 11), TO_UNSIGNED(1440, 11), TO_UNSIGNED( 252, 11), TO_UNSIGNED(1447, 11),
TO_UNSIGNED( 258, 11), TO_UNSIGNED(1454, 11), TO_UNSIGNED( 264, 11), TO_UNSIGNED(1461, 11), TO_UNSIGNED( 270, 11), TO_UNSIGNED(1469, 11), TO_UNSIGNED( 276, 11), TO_UNSIGNED(1475, 11),
TO_UNSIGNED( 282, 11), TO_UNSIGNED(1483, 11), TO_UNSIGNED( 145, 11), TO_UNSIGNED( 288, 11), TO_UNSIGNED( 151, 11), TO_UNSIGNED( 294, 11), TO_UNSIGNED( 157, 11), TO_UNSIGNED( 300, 11),
TO_UNSIGNED( 163, 11), TO_UNSIGNED( 306, 11), TO_UNSIGNED( 169, 11), TO_UNSIGNED( 312, 11), TO_UNSIGNED( 176, 11), TO_UNSIGNED( 318, 11), TO_UNSIGNED( 181, 11), TO_UNSIGNED( 324, 11),
TO_UNSIGNED( 187, 11), TO_UNSIGNED( 330, 11), TO_UNSIGNED( 193, 11), TO_UNSIGNED( 336, 11), TO_UNSIGNED( 199, 11), TO_UNSIGNED( 343, 11), TO_UNSIGNED( 205, 11), TO_UNSIGNED( 348, 11),
TO_UNSIGNED( 211, 11), TO_UNSIGNED( 354, 11), TO_UNSIGNED( 217, 11), TO_UNSIGNED( 360, 11), TO_UNSIGNED( 223, 11), TO_UNSIGNED( 366, 11), TO_UNSIGNED( 229, 11), TO_UNSIGNED( 372, 11),
TO_UNSIGNED( 235, 11), TO_UNSIGNED( 378, 11), TO_UNSIGNED( 241, 11), TO_UNSIGNED( 384, 11), TO_UNSIGNED( 247, 11), TO_UNSIGNED( 390, 11), TO_UNSIGNED( 253, 11), TO_UNSIGNED( 396, 11),
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TO_UNSIGNED(1361, 11), TO_UNSIGNED(1494, 11), TO_UNSIGNED(1781, 11), TO_UNSIGNED( 731, 11), TO_UNSIGNED(1091, 11), TO_UNSIGNED(1228, 11), TO_UNSIGNED(1375, 11), TO_UNSIGNED(1508, 11),
TO_UNSIGNED(1795, 11), TO_UNSIGNED( 725, 11), TO_UNSIGNED(1085, 11), TO_UNSIGNED(1221, 11), TO_UNSIGNED(1368, 11), TO_UNSIGNED(1500, 11), TO_UNSIGNED(1788, 11), TO_UNSIGNED( 737, 11),
TO_UNSIGNED(1097, 11), TO_UNSIGNED(1235, 11), TO_UNSIGNED(1382, 11), TO_UNSIGNED(1515, 11), TO_UNSIGNED(1802, 11), TO_UNSIGNED( 755, 11), TO_UNSIGNED(1115, 11), TO_UNSIGNED(1256, 11),
TO_UNSIGNED(1403, 11), TO_UNSIGNED(1536, 11), TO_UNSIGNED(1823, 11), TO_UNSIGNED( 761, 11), TO_UNSIGNED(1121, 11), TO_UNSIGNED(1263, 11), TO_UNSIGNED(1410, 11), TO_UNSIGNED(1543, 11),
TO_UNSIGNED(1662, 11), TO_UNSIGNED( 767, 11), TO_UNSIGNED(1127, 11), TO_UNSIGNED(1270, 11), TO_UNSIGNED(1417, 11), TO_UNSIGNED(1550, 11), TO_UNSIGNED(1669, 11), TO_UNSIGNED( 773, 11),
TO_UNSIGNED(1133, 11), TO_UNSIGNED(1277, 11), TO_UNSIGNED(1424, 11), TO_UNSIGNED(1557, 11), TO_UNSIGNED(1676, 11), TO_UNSIGNED( 779, 11), TO_UNSIGNED(1139, 11), TO_UNSIGNED(1284, 11),
TO_UNSIGNED(1431, 11), TO_UNSIGNED(1564, 11), TO_UNSIGNED(1683, 11), TO_UNSIGNED( 743, 11), TO_UNSIGNED(1103, 11), TO_UNSIGNED(1242, 11), TO_UNSIGNED(1389, 11), TO_UNSIGNED(1522, 11),
TO_UNSIGNED(1809, 11), TO_UNSIGNED( 749, 11), TO_UNSIGNED(1109, 11), TO_UNSIGNED(1249, 11), TO_UNSIGNED(1396, 11), TO_UNSIGNED(1529, 11), TO_UNSIGNED(1816, 11), TO_UNSIGNED( 809, 11),
TO_UNSIGNED(1024, 11), TO_UNSIGNED(1319, 11), TO_UNSIGNED(1466, 11), TO_UNSIGNED(1599, 11), TO_UNSIGNED(1718, 11), TO_UNSIGNED( 791, 11), TO_UNSIGNED(1151, 11), TO_UNSIGNED(1298, 11),
TO_UNSIGNED(1445, 11), TO_UNSIGNED(1578, 11), TO_UNSIGNED(1697, 11), TO_UNSIGNED( 797, 11), TO_UNSIGNED(1013, 11), TO_UNSIGNED(1305, 11), TO_UNSIGNED(1452, 11), TO_UNSIGNED(1585, 11),
TO_UNSIGNED(1704, 11), TO_UNSIGNED( 785, 11), TO_UNSIGNED(1145, 11), TO_UNSIGNED(1291, 11), TO_UNSIGNED(1438, 11), TO_UNSIGNED(1571, 11), TO_UNSIGNED(1690, 11), TO_UNSIGNED( 803, 11),
TO_UNSIGNED(1019, 11), TO_UNSIGNED(1312, 11), TO_UNSIGNED(1459, 11), TO_UNSIGNED(1592, 11), TO_UNSIGNED(1711, 11), TO_UNSIGNED( 821, 11), TO_UNSIGNED(1037, 11), TO_UNSIGNED(1164, 11),
TO_UNSIGNED(1480, 11), TO_UNSIGNED(1613, 11), TO_UNSIGNED(1732, 11), TO_UNSIGNED( 17, 11), TO_UNSIGNED(1025, 11), TO_UNSIGNED(1501, 11), TO_UNSIGNED(1165, 11), TO_UNSIGNED(1333, 11)
);
SIGNAL READ_C : UNSIGNED(10 downto 0);
SIGNAL WRITE_C : UNSIGNED(10 downto 0);
SIGNAL ROM_ADR : UNSIGNED(10 downto 0);
SIGNAL IN_BIS : STD_LOGIC_VECTOR (15 downto 0);
SIGNAL WE_BIS : STD_LOGIC;
SIGNAL HD_BIS : STD_LOGIC;
BEGIN
-------------------------------------------------------------------------
-- synthesis translate_off
PROCESS
BEGIN
WAIT FOR 1 ns;
printmsg("(IMS) Q16_8_V_to_C_RAM : ALLOCATION OK !");
WAIT;
END PROCESS;
-- synthesis translate_on
-------------------------------------------------------------------------
--
--
--
PROCESS(clock, reset)
VARIABLE TEMP : UNSIGNED(10 downto 0);
BEGIN
IF reset = '0' THEN
WRITE_C <= TO_UNSIGNED(0, 11);
elsif clock'event and clock = '1' THEN
IF WRITE_EN = '1' AND HOLDN = '1' THEN
TEMP := WRITE_C + TO_UNSIGNED(1, 11);
IF TEMP = 1824 THEN
TEMP := TO_UNSIGNED(0, 11);
END IF;
WE_BIS <= '1';
WRITE_C <= TEMP;
ELSE
WE_BIS <= '0';
WRITE_C <= WRITE_C;
END IF;
IN_BIS <= INPUT_1(15 downto 0);
END if;
END PROCESS;
--
--
--
-- process(clock, reset)
-- VARIABLE TEMP : UNSIGNED(10 downto 0);
-- begin
-- if reset = '0' then
-- READ_C <= TO_UNSIGNED(0, 11);
-- elsif clock'event and clock = '1' then
-- if read_en = '1' AND holdn = '1' then
-- TEMP := READ_C + TO_UNSIGNED(1, 11);
-- IF TEMP = 1824 THEN
-- TEMP := TO_UNSIGNED(0, 11);
-- END IF;
-- -- synthesis translate_off
-- -- printmsg("(Q16_8_V_to_C_RAM) ===> READING (" & to_int_str( STD_LOGIC_VECTOR(READ_C),6) & ") = " & to_int_str( RAM( to_integer(READ_C) ), 6) & " NOW GOING TO : " & to_int_str( STD_LOGIC_VECTOR(TEMP),6) );
-- -- synthesis translate_on
-- READ_C <= TEMP;
-- else
-- READ_C <= READ_C;
-- end if;
-- end if;
-- end process;
--
--
--
process(clock, reset)
VARIABLE TEMP : UNSIGNED(10 downto 0);
VARIABLE TMP : STD_LOGIC_VECTOR(15 downto 0);
begin
if reset = '0' then
READ_C <= TO_UNSIGNED(0, 11);
elsif clock'event and clock = '1' then
TEMP := READ_C;
if read_en = '1' AND holdn = '1' then
TEMP := TEMP + TO_UNSIGNED(1, 11);
IF TEMP = 1824 THEN
TEMP := TO_UNSIGNED(0, 11);
END IF;
end if;
READ_C <= TEMP;
TMP := RAM( to_integer( TEMP ) );
OUTPUT_1 <= STD_LOGIC_VECTOR(RESIZE( SIGNED( TMP ), 32 )) ;
end if;
end process;
--
--
--
process(clock)
VARIABLE ADR : INTEGER RANGE 0 to 1823;
VARIABLE POS : INTEGER RANGE 0 to 1823;
begin
if clock'event and clock = '1' then
ADR := to_integer( WRITE_C );
ROM_ADR <= ROM( ADR );
--ROM_ADR <= WRITE_C;
end if;
end process;
--
--
--
process(clock)
VARIABLE TMP : STD_LOGIC_VECTOR(15 downto 0);
begin
if clock'event and clock = '1' then
if WE_BIS = '1' then
-- synthesis translate_off
-- printmsg("(Q16_8_V_to_C_RAM) ===> WRITING (" & to_int_str( STD_LOGIC_VECTOR(IN_BIS),6) & ") AT POSITION : " & to_int_str( STD_LOGIC_VECTOR(ROM_ADR),6) );
-- synthesis translate_on
RAM( to_integer( ROM_ADR ) ) <= IN_BIS;
end if;
-- TMP := RAM( to_integer(READ_C) );
-- OUTPUT_1 <= STD_LOGIC_VECTOR(RESIZE( SIGNED( TMP ), 32 )) ;
end if;
end process;
END cRAM; | gpl-3.0 | b0bf0221cfbcf82e3ef39aeed3c275e5 | 0.646247 | 2.821723 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Font/simulation/Font_tb_dgen.vhd | 1 | 5,094 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Font_tb_dgen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.Font_TB_PKG.ALL;
ENTITY Font_TB_DGEN IS
GENERIC (
DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END Font_TB_DGEN;
ARCHITECTURE DATA_GEN_ARCH OF Font_TB_DGEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.Font_TB_RNG
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
| mit | b091e39ddca3c245a9ef1b535aed58dc | 0.576364 | 4.058964 | false | false | false | false |
karvonz/Mandelbrot | src_vhd/Zoom.vhd | 1 | 2,050 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library WORK;
use WORK.CONSTANTS.ALL;
use WORK.FUNCTIONS.ALL;
entity Zoom is
generic( ystartini : STD_LOGIC_VECTOR(31 downto 0) := x"F0000000");
Port ( bleft : in STD_LOGIC;
bright : in STD_LOGIC;
bup : in STD_LOGIC;
bdwn : in STD_LOGIC;
bctr : in STD_LOGIC;
clock : in STD_LOGIC;
reset : in STD_LOGIC;
ce_param : in std_logic;
x_start : out STD_LOGIC_VECTOR(XY_RANGE-1 downto 0);
y_start : out STD_LOGIC_VECTOR(XY_RANGE-1 downto 0);
step : out STD_LOGIC_VECTOR(XY_RANGE-1 downto 0));
end Zoom;
architecture Behavioral of Zoom is
signal s_xstart, s_ystart, s_step : signed(XY_RANGE-1 downto 0);
begin
process(clock, ce_param, reset, bup, bdwn, bleft, bright, bctr)
begin
if reset = '1' then
s_xstart <= x"E0000000";
s_ystart <= signed(ystartini);
s_step <= x"00111111"; --Mandelbrot -2 1 x -1 1 sur 640x480
elsif ((rising_edge(clock)) and (ce_param='1')) then -- TODO : Centrer le zoom
if bctr = '1' then
-- if bup = '1' then
s_xstart <= s_xstart + (mult(s_step srl 2,x"28000000",FIXED) sll 8);
s_ystart <= s_ystart + (mult(s_step srl 2,x"1E000000",FIXED) sll 8);
s_step <= s_step srl 1; --Zoom x2> réduction du step
-- elsif bdwn = '1' then
-- s_step <= s_step sll 1; --Dezoom x0.5> augmentation du step
-- s_xstart <= s_xstart + not (mult(s_step srl 2,x"28000000",FIXED) sll 8) + 1;
-- s_ystart <= s_ystart + not (mult(s_step srl 2,x"1E000000",FIXED) sll 8) +1;
-- end if;
elsif bup = '1' then
s_ystart <= s_ystart + (s_step sll 7);
elsif bdwn = '1' then
s_ystart <= s_ystart - (s_step sll 7);
end if;
if bleft = '1' then
s_xstart <= s_xstart - (s_step sll 7);
elsif bright = '1' then
s_xstart <= s_xstart + (s_step sll 7);
end if;
end if;
end process;
x_start <= STD_LOGIC_VECTOR(s_xstart);
y_start <= STD_LOGIC_VECTOR(s_ystart);
step <= STD_LOGIC_VECTOR(s_step);
end Behavioral;
| gpl-3.0 | b11065f07c2d55efa333af96f9cee2c6 | 0.606341 | 2.777778 | false | false | false | false |
chibby0ne/vhdl-book | Chapter6/exercise6_7_dir/exercise6_7.vhd | 1 | 1,351 | --!
--! @file: exercise6_7.vhd
--! @brief: Binary Sorter with Loop
--! @author: Antonio Gutierrez
--! @date: 2013-10-27
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity binary_sorter is
generic (N: integer := 5);
port (
input: in bit_vector(N-1 downto 0);
output: out bit_vector(N-1 downto 0));
end entity binary_sorter;
--------------------------------------
architecture circuit of binary_sorter is
begin
proc: process (input)
variable count: integer range 0 to N := 0;
variable output_buffer: std_logic_vector(N-1 downto 0);
begin
-- first loop: counts the number of 1's there are in the vector
forloop: for i in 0 to N-1 loop
if (input(i) = '1') then
count = count + 1;
end if;
end loop forloop;
-- second loop: assigns 1's at the beginning and then the rest is 0
forloop1: for i in N-1 downto (N-1)-count loop
if (count = 0) then
output(i) <= '0';
else
output(i) <= '1';
end if;
count = count - 1;
end loop forloop1;
end process proc;
end architecture circuit;
--------------------------------------
| gpl-3.0 | c847cfe23dd9c2bfaa253fc6815575fe | 0.493708 | 4.144172 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/top_sp605.vhd | 1 | 12,496 | -- Top-level design for ipbus demo
--
-- This version is for xc6vlx240t on Xilinx ML605 eval board
-- Uses the v6 hard EMAC core with GMII interface to an external Gb PHY
--
-- You must edit this file to set the IP and MAC addresses
--
-- Dave Newbold, May 2011
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use work.ipbus.ALL;
--use work.bus_arb_decl.all;
--use work.mac_arbiter_decl.all;
library unisim;
use unisim.VComponents.all;
entity top_ml605_extphy is port(
clk100: in std_logic;
rst: in std_logic;
sw : in std_logic;
--led: out std_logic_vector(7 downto 0);
led: out std_logic;
i_uart : in std_logic;
o_uart : out std_logic;
o_uart2 : out std_logic;
buttons : in std_logic_vector( 2 downto 0 );
BTNU : in std_logic;
BTNC : in std_logic;
BTND : in std_logic;
BTNL : in std_logic;
BTNR : in std_logic;
VGA_hs : out std_logic; -- horisontal vga syncr.
VGA_vs : out std_logic; -- vertical vga syncr.
VGA_red : out std_logic_vector(3 downto 0); -- red output
VGA_green : out std_logic_vector(3 downto 0); -- green output
VGA_blue : out std_logic_vector(3 downto 0) -- blue output
);
end top_ml605_extphy;
architecture rtl of top_ml605_extphy is
component pulse_filter
Generic ( DEBNC_CLOCKS : INTEGER range 2 to (INTEGER'high) := 2**16);
Port (
SIGNAL_I : in STD_LOGIC;
CLK_I : in STD_LOGIC;
SIGNAL_O : out STD_LOGIC
);
end component;
component Colorgen
Port ( iter : in STD_LOGIC_VECTOR (11 downto 0);
VGA_red : out std_logic_vector(3 downto 0); -- red output
VGA_green : out std_logic_vector(3 downto 0); -- green output
VGA_blue : out std_logic_vector(3 downto 0)); -- blue output
end component;
component VGA_bitmap_640x480
port(clk : in std_logic;
clk_vga : in std_logic;
reset : in std_logic;
VGA_hs : out std_logic; -- horisontal vga syncr.
VGA_vs : out std_logic; -- vertical vga syncr.
iter : out std_logic_vector(11 downto 0); -- iter output
ADDR1 : in std_logic_vector(16 downto 0);
data_in1 : in std_logic_vector(11 downto 0);
data_write1 : in std_logic;
ADDR2 : in std_logic_vector(16 downto 0);
data_in2 : in std_logic_vector(11 downto 0);
data_write2 : in std_logic;
ADDR3 : in std_logic_vector(16 downto 0);
data_in3 : in std_logic_vector(11 downto 0);
data_write3 : in std_logic;
ADDR4 : in std_logic_vector(16 downto 0);
data_in4 : in std_logic_vector(11 downto 0);
data_write4 : in std_logic);
end component;
signal BTNUB, BTNCB, BTNDB, BTNRB, BTNLB, data_write1, data_write2,data_write3, data_write4,data_write5, data_write6,data_write7, data_write8, clk50, clk100_sig: std_logic;
signal iterS, data_out1,data_out2, data_out3 ,data_out4, data_out5,data_out6, data_out7 ,data_out8 : std_logic_vector(11 downto 0);
signal ADDR1, ADDR2, ADDR3, ADDR4, ADDR5, ADDR6, ADDR7, ADDR8 : std_logic_vector(16 downto 0);
--component clk_wiz_0 is -- vivado
-- component clkgen is --ise
-- port
-- (-- Clock in ports
-- clk_in1 : in std_logic;
-- -- Clock out ports
-- clk_out1 : out std_logic;
-- clk_out2 : out std_logic
-- );
-- end component;
begin
process(rst, clk50)
begin
if(rst='1') then
--o_uart <= '0';
led <= '0';
elsif(clk50'event and clk50='1') then
--o_uart <= i_uart;
led <= sw;
end if;
end process;
clk_div : process(clk100, rst)
begin
if(rst='1') then
clk50 <= '0';
elsif(clk100'event and clk100 = '1') then
clk50 <= not(clk50);
end if;
end process;
-- leds(7 downto 0) <= ('0','0','0','0','0','0', locked, onehz);
-- Inst_plasma8: entity work.plasma
-- GENERIC MAP (
-- memory_type => "XILINX_16X",
-- log_file => "UNUSED",
-- ethernet => '0',
-- eUart => '1',
-- use_cache => '0',
-- plasma_code => "../code_bin8.txt"
-- )
-- PORT MAP(
-- clk => clk50,
---- clk_VGA => clk100,
-- reset => rst,
-- uart_write => open,
-- uart_read => i_uart,
-- fifo_1_out_data => x"00000000",
-- fifo_1_read_en => open,
-- fifo_1_empty => '0',
-- fifo_2_in_data => open,
-- fifo_1_write_en => open,
-- fifo_2_full => '0',
--
-- fifo_1_full => '0',
-- fifo_1_valid => '0',
-- fifo_2_empty => '0',
-- fifo_2_valid => '0',
-- fifo_1_compteur => x"00000000",
-- fifo_2_compteur => x"00000000",
--
-- data_enable => data_write8,
-- ADDR => ADDR8,
-- data_out => data_out8,
--
-- gpio0_out => open,
-- gpioA_in => x"000000" & buttons & BTNDB & BTNRB & BTNLB & BTNUB & BTNCB
-- );
--Inst_plasma7: entity work.plasma
-- GENERIC MAP (
-- memory_type => "XILINX_16X",
-- log_file => "UNUSED",
-- ethernet => '0',
-- eUart => '1',
-- use_cache => '0',
-- plasma_code => "../code_bin7.txt"
-- )
-- PORT MAP(
-- clk => clk50,
---- clk_VGA => clk100,
-- reset => rst,
-- uart_write => open,
-- uart_read => i_uart,
-- fifo_1_out_data => x"00000000",
-- fifo_1_read_en => open,
-- fifo_1_empty => '0',
-- fifo_2_in_data => open,
-- fifo_1_write_en => open,
-- fifo_2_full => '0',
--
-- fifo_1_full => '0',
-- fifo_1_valid => '0',
-- fifo_2_empty => '0',
-- fifo_2_valid => '0',
-- fifo_1_compteur => x"00000000",
-- fifo_2_compteur => x"00000000",
--
-- data_enable => data_write7,
-- ADDR => ADDR7,
-- data_out => data_out7,
--
-- gpio0_out => open,
-- gpioA_in => x"000000" & buttons & BTNDB & BTNRB & BTNLB & BTNUB & BTNCB --open
-- );
--
--
-- Inst_plasma5: entity work.plasma
-- GENERIC MAP (
-- memory_type => "XILINX_16X",
-- log_file => "UNUSED",
-- ethernet => '0',
-- eUart => '1',
-- use_cache => '0',
-- plasma_code => "../code_bin5.txt"
-- )
-- PORT MAP(
-- clk => clk50,
-- -- clk_VGA => clk100,
-- reset => rst,
-- uart_write => open,
-- uart_read => i_uart,
-- fifo_1_out_data => x"00000000",
-- fifo_1_read_en => open,
-- fifo_1_empty => '0',
-- fifo_2_in_data => open,
-- fifo_1_write_en => open,
-- fifo_2_full => '0',
--
-- fifo_1_full => '0',
-- fifo_1_valid => '0',
-- fifo_2_empty => '0',
-- fifo_2_valid => '0',
-- fifo_1_compteur => x"00000000",
-- fifo_2_compteur => x"00000000",
--
-- data_enable => data_write5,
-- ADDR => ADDR5,
-- data_out => data_out5,
--
-- gpio0_out => open,
-- gpioA_in => x"000000" & buttons & BTNDB & BTNRB & BTNLB & BTNUB & BTNCB--open
-- );
Inst_plasma4: entity work.plasma
GENERIC MAP (
memory_type => "XILINX_16X",
log_file => "UNUSED",
ethernet => '0',
eUart => '1',
use_cache => '0',
plasma_code => "../code_bin4.txt"
)
PORT MAP(
clk => clk50,
-- clk_VGA => clk100,
reset => rst,
uart_write => open,
uart_read => i_uart,
fifo_1_out_data => x"00000000",
fifo_1_read_en => open,
fifo_1_empty => '0',
fifo_2_in_data => open,
fifo_1_write_en => open,
fifo_2_full => '0',
fifo_1_full => '0',
fifo_1_valid => '0',
fifo_2_empty => '0',
fifo_2_valid => '0',
fifo_1_compteur => x"00000000",
fifo_2_compteur => x"00000000",
data_enable => data_write4,
ADDR => ADDR4,
data_out => data_out4,
gpio0_out => open,
gpioA_in => x"000000" & buttons & BTNDB & BTNRB & BTNLB & BTNUB & BTNCB
);
--
Inst_plasma3: entity work.plasma
GENERIC MAP (
memory_type => "XILINX_16X",
log_file => "UNUSED",
ethernet => '0',
eUart => '1',
use_cache => '0',
plasma_code => "../code_bin3.txt"
)
PORT MAP(
clk => clk50,
-- clk_VGA => clk100,
reset => rst,
uart_write => open,
uart_read => i_uart,
fifo_1_out_data => x"00000000",
fifo_1_read_en => open,
fifo_1_empty => '0',
fifo_2_in_data => open,
fifo_1_write_en => open,
fifo_2_full => '0',
fifo_1_full => '0',
fifo_1_valid => '0',
fifo_2_empty => '0',
fifo_2_valid => '0',
fifo_1_compteur => x"00000000",
fifo_2_compteur => x"00000000",
data_enable => data_write3,
ADDR => ADDR3,
data_out => data_out3,
gpio0_out => open,
gpioA_in => x"000000" & buttons & BTNDB & BTNRB & BTNLB & BTNUB & BTNCB --open
);
-- Inst_plasma6: entity work.plasma
-- GENERIC MAP (
-- memory_type => "XILINX_16X",
-- log_file => "UNUSED",
-- ethernet => '0',
-- eUart => '1',
-- use_cache => '0',
-- plasma_code => "../code_bin6.txt"
-- )
-- PORT MAP(
-- clk => clk50,
---- clk_VGA => clk100,
-- reset => rst,
-- uart_write => open,
-- uart_read => i_uart,
-- fifo_1_out_data => x"00000000",
-- fifo_1_read_en => open,
-- fifo_1_empty => '0',
-- fifo_2_in_data => open,
-- fifo_1_write_en => open,
-- fifo_2_full => '0',
--
-- fifo_1_full => '0',
-- fifo_1_valid => '0',
-- fifo_2_empty => '0',
-- fifo_2_valid => '0',
-- fifo_1_compteur => x"00000000",
-- fifo_2_compteur => x"00000000",
--
-- data_enable => data_write6,
-- ADDR => ADDR6,
-- data_out => data_out6,
--
-- gpio0_out => open,
-- gpioA_in => x"000000" & buttons & BTNDB & BTNRB & BTNLB & BTNUB & BTNCB --open
-- );
Inst_plasma2: entity work.plasma
GENERIC MAP (
memory_type => "XILINX_16X",
log_file => "UNUSED",
ethernet => '0',
eUart => '1',
use_cache => '0',
plasma_code => "../code_bin2.txt"
)
PORT MAP(
clk => clk50,
-- clk_VGA => clk100,
reset => rst,
uart_write => o_uart,
uart_read => i_uart,
fifo_1_out_data => x"00000000",
fifo_1_read_en => open,
fifo_1_empty => '0',
fifo_2_in_data => open,
fifo_1_write_en => open,
fifo_2_full => '0',
fifo_1_full => '0',
fifo_1_valid => '0',
fifo_2_empty => '0',
fifo_2_valid => '0',
fifo_1_compteur => x"00000000",
fifo_2_compteur => x"00000000",
data_enable => data_write2,
ADDR => ADDR2,
data_out => data_out2,
gpio0_out => open,
gpioA_in => x"000000" & buttons & BTNDB & BTNRB & BTNLB & BTNUB & BTNCB --open
);
Inst_plasma1: entity work.plasma
GENERIC MAP (
memory_type => "XILINX_16X",
log_file => "UNUSED",
ethernet => '0',
eUart => '1',
use_cache => '0',
plasma_code => "../code_bin1.txt"
)
PORT MAP(
clk => clk50,
-- clk_VGA => clk100,
reset => rst,
uart_write => o_uart2,
uart_read => i_uart,
fifo_1_out_data => x"00000000",
fifo_1_read_en => open,
fifo_1_empty => '0',
fifo_2_in_data => open,
fifo_1_write_en => open,
fifo_2_full => '0',
fifo_1_full => '0',
fifo_1_valid => '0',
fifo_2_empty => '0',
fifo_2_valid => '0',
fifo_1_compteur => x"00000000",
fifo_2_compteur => x"00000000",
data_enable => data_write1,
ADDR => ADDR1,
data_out => data_out1,
gpio0_out => open,
gpioA_in => x"000000" & buttons & BTNDB & BTNRB & BTNLB & BTNUB & BTNCB--open
);
InstVGA: VGA_bitmap_640x480
port map(clk50,
clk100,
rst,
VGA_hs,
VGA_vs,
iterS,
ADDR1,
data_out1,
data_write1,
ADDR2,
data_out2,
data_write2,
ADDR3,
data_out3,
data_write3,
ADDR4,
data_out4,
data_write4
);
InstColorgen: Colorgen
port map(iterS,VGA_red,VGA_green,VGA_blue);
InstancepulsBTNU: pulse_filter
port map(BTNU,
clk50,
BTNUB);
InstancepulsBTND: pulse_filter
port map(BTND,
clk50,
BTNDB);
InstancepulsBTNL: pulse_filter
port map(BTNL,
clk50,
BTNLB);
InstancepulsBTNR: pulse_filter
port map(BTNR,
clk50,
BTNRB);
InstancepulsBTNC: pulse_filter
port map(BTNC,
clk50,
BTNCB);
end rtl;
| gpl-3.0 | 59773fbe1406431976077ef1d043f2ea | 0.513844 | 2.641302 | false | false | false | false |
DGideas/THU-FPGA-makecomputer | src/cpu/mux_result.vhd | 1 | 1,366 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:10:20 05/21/2017
-- Design Name:
-- Module Name: mux_result - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mux_result is
Port ( alusrc : in STD_LOGIC_VECTOR (1 downto 0);
mux_alures : in STD_LOGIC_VECTOR (15 downto 0);
mux_menres : in STD_LOGIC_VECTOR (15 downto 0);
mux_dataC : out STD_LOGIC_VECTOR (15 downto 0));
end mux_result;
architecture Behavioral of mux_result is
begin
process(alusrc)
begin
case alusrc is
when "00"=>
mux_dataC<=mux_alures;
when "01"=>
mux_dataC<=mux_menres;
when others=>null;
end case;
end process;
end Behavioral;
| apache-2.0 | 2ab5145881c1c219dd3d027ab610f544 | 0.565886 | 3.794444 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/mt46v16m16.vhd | 1 | 54,691 | -----------------------------------------------------------------------------------------
--
-- File Name: MT46V16M16.VHD
-- Version: 2.1
-- Date: January 14th, 2002
-- Model: Behavioral
-- Simulator: NCDesktop - http://www.cadence.com
-- ModelSim PE - http://www.model.com
--
-- Dependencies: None
--
-- Author: Son P. Huynh
-- Email: [email protected]
-- Phone: (208) 368-3825
-- Company: Micron Technology, Inc.
-- Part Number: MT46V16M16 (4 Mb x 16 x 4 Banks)
--
-- Description: Micron 256 Mb SDRAM DDR (Double Data Rate)
--
-- Limitation: Doesn't model internal refresh counter
--
-- Note:
--
-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
-- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Copyright (c) 1998 Micron Semiconductor Products, Inc.
-- All rights researved
--
-- Rev Author Date Changes
-- --- ---------------------------- ---------- -------------------------------------
-- 2.1 Son P. Huynh 01/14/2002 - Fix Burst_counter
-- Micron Technology, Inc.
--
-- 2.0 Son P. Huynh 11/08/2001 - Second release
-- Micron Technology, Inc. - Rewrote and remove SHARED VARIABLE
--
-----------------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY MT46V16M16 IS
GENERIC ( -- Timing for -75Z CL2
tCK : TIME := 7.500 ns;
tCH : TIME := 3.375 ns; -- 0.45*tCK
tCL : TIME := 3.375 ns; -- 0.45*tCK
tDH : TIME := 0.500 ns;
tDS : TIME := 0.500 ns;
tIH : TIME := 0.900 ns;
tIS : TIME := 0.900 ns;
tMRD : TIME := 15.000 ns;
tRAS : TIME := 40.000 ns;
tRAP : TIME := 20.000 ns;
tRC : TIME := 65.000 ns;
tRFC : TIME := 75.000 ns;
tRCD : TIME := 20.000 ns;
tRP : TIME := 20.000 ns;
tRRD : TIME := 15.000 ns;
tWR : TIME := 15.000 ns;
addr_bits : INTEGER := 13;
data_bits : INTEGER := 16;
cols_bits : INTEGER := 9
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
Clk : IN STD_LOGIC;
Clk_n : IN STD_LOGIC;
Cke : IN STD_LOGIC;
Cs_n : IN STD_LOGIC;
Ras_n : IN STD_LOGIC;
Cas_n : IN STD_LOGIC;
We_n : IN STD_LOGIC;
Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END MT46V16M16;
ARCHITECTURE behave OF MT46V16M16 IS
-- Array for Read pipeline
TYPE Array_Read_cmnd IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
TYPE Array_Read_bank IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
TYPE Array_Read_cols IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
-- Array for Write pipeline
TYPE Array_Write_cmnd IS ARRAY (2 DOWNTO 0) OF STD_LOGIC;
TYPE Array_Write_bank IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
TYPE Array_Write_cols IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
-- Array for Auto Precharge
TYPE Array_Read_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC;
TYPE Array_Write_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC;
TYPE Array_Count_precharge IS ARRAY (3 DOWNTO 0) OF INTEGER;
-- Array for Manual Precharge
TYPE Array_A10_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
TYPE Array_Bank_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
TYPE Array_Cmnd_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
-- Array for Burst Terminate
TYPE Array_Cmnd_bst IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
-- Array for Memory Access
TYPE Array_ram_type IS ARRAY (2**cols_bits - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
TYPE Array_ram_pntr IS ACCESS Array_ram_type;
TYPE Array_ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF Array_ram_pntr;
-- Data pair
SIGNAL Dq_pair : STD_LOGIC_VECTOR (2 * data_bits - 1 DOWNTO 0);
SIGNAL Dm_pair : STD_LOGIC_VECTOR (3 DOWNTO 0);
-- Mode Register
SIGNAL Mode_reg : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
-- Command Decode Variables
SIGNAL Active_enable, Aref_enable, Burst_term, Ext_mode_enable : STD_LOGIC := '0';
SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : STD_LOGIC := '0';
-- Burst Length Decode Variables
SIGNAL Burst_length_2, Burst_length_4, Burst_length_8, Burst_length_f : STD_LOGIC := '0';
-- Cas Latency Decode Variables
SIGNAL Cas_latency_15, Cas_latency_2, Cas_latency_25, Cas_latency_3, Cas_latency_4 : STD_LOGIC := '0';
-- Internal Control Signals
SIGNAL Cs_in, Ras_in, Cas_in, We_in : STD_LOGIC := '0';
-- System Clock
SIGNAL Sys_clk : STD_LOGIC := '0';
-- Dqs buffer
SIGNAL Dqs_out : STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
BEGIN
-- Strip the strength
Cs_in <= To_X01 (Cs_n);
Ras_in <= To_X01 (Ras_n);
Cas_in <= To_X01 (Cas_n);
We_in <= To_X01 (We_n);
-- Commands Decode
Active_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND We_in;
Aref_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND We_in;
Burst_term <= NOT(Cs_in) AND Ras_in AND Cas_in AND NOT(We_in);
Ext_mode_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND Ba(0) AND NOT(Ba(1));
Mode_reg_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND NOT(Ba(0)) AND NOT(Ba(1));
Prech_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND NOT(We_in);
Read_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND We_in;
Write_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND NOT(We_in);
-- Burst Length Decode
Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0);
Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0));
Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0);
Burst_length_f <= (Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0);
-- CAS Latency Decode
Cas_latency_15 <= Mode_reg(6) AND NOT(Mode_reg(5)) AND (Mode_reg(4));
Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4));
Cas_latency_25 <= Mode_reg(6) AND Mode_reg(5) AND NOT(Mode_reg(4));
Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4);
Cas_latency_4 <= (Mode_reg(6)) AND NOT(Mode_reg(5)) AND NOT(Mode_reg(4));
-- Dqs buffer
Dqs <= Dqs_out;
--
-- System Clock
--
int_clk : PROCESS (Clk, Clk_n)
VARIABLE ClkZ, CkeZ : STD_LOGIC := '0';
begin
IF Clk = '1' AND Clk_n = '0' THEN
ClkZ := '1';
CkeZ := Cke;
ELSIF Clk = '0' AND Clk_n = '1' THEN
ClkZ := '0';
END IF;
Sys_clk <= CkeZ AND ClkZ;
END PROCESS;
--
-- Main Process
--
state_register : PROCESS
-- Precharge Variables
VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : STD_LOGIC := '0';
-- Activate Variables
VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : STD_LOGIC := '1';
-- Data IO variables
VARIABLE Data_in_enable, Data_out_enable : STD_LOGIC := '0';
-- Internal address mux variables
VARIABLE Cols_brst : STD_LOGIC_VECTOR (2 DOWNTO 0);
VARIABLE Prev_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
VARIABLE Bank_addr : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
VARIABLE Cols_addr : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
VARIABLE Rows_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
VARIABLE B0_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
VARIABLE B1_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
VARIABLE B2_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
VARIABLE B3_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
-- DLL Reset variables
VARIABLE DLL_enable : STD_LOGIC := '0';
VARIABLE DLL_reset : STD_LOGIC := '0';
VARIABLE DLL_done : STD_LOGIC := '0';
VARIABLE DLL_count : INTEGER := 0;
-- Timing Check
VARIABLE MRD_chk : TIME := 0 ns;
VARIABLE RFC_chk : TIME := 0 ns;
VARIABLE RRD_chk : TIME := 0 ns;
VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns;
VARIABLE RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3 : TIME := 0 ns;
VARIABLE RC_chk0, RC_chk1, RC_chk2, RC_chk3 : TIME := 0 ns;
VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns;
VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns;
VARIABLE WR_chk0, WR_chk1, WR_chk2, WR_chk3 : TIME := 0 ns;
-- Read pipeline variables
VARIABLE Read_cmnd : Array_Read_cmnd;
VARIABLE Read_bank : Array_Read_bank;
VARIABLE Read_cols : Array_Read_cols;
-- Write pipeline variables
VARIABLE Write_cmnd : Array_Write_cmnd;
VARIABLE Write_bank : Array_Write_bank;
VARIABLE Write_cols : Array_Write_cols;
-- Auto Precharge variables
VARIABLE Read_precharge : Array_Read_precharge := ('0' & '0' & '0' & '0');
VARIABLE Write_precharge : Array_Write_precharge := ('0' & '0' & '0' & '0');
VARIABLE Count_precharge : Array_Count_precharge := ( 0 & 0 & 0 & 0 );
-- Manual Precharge variables
VARIABLE A10_precharge : Array_A10_precharge;
VARIABLE Bank_precharge : Array_Bank_precharge;
VARIABLE Cmnd_precharge : Array_Cmnd_precharge;
-- Burst Terminate variable
VARIABLE Cmnd_bst : Array_Cmnd_bst;
-- Memory Banks
VARIABLE Bank0 : Array_ram_stor;
VARIABLE Bank1 : Array_ram_stor;
VARIABLE Bank2 : Array_ram_stor;
VARIABLE Bank3 : Array_ram_stor;
-- Burst Counter
VARIABLE Burst_counter : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
-- Internal Dqs initialize
VARIABLE Dqs_int : STD_LOGIC := '0';
-- Data buffer for DM Mask
VARIABLE Data_buf : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
--
-- Initialize empty rows
--
PROCEDURE Init_mem (Bank : STD_LOGIC_VECTOR; Row_index : INTEGER) IS
VARIABLE i, j : INTEGER := 0;
BEGIN
IF Bank = "00" THEN
IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty
Bank0 (Row_index) := NEW Array_ram_type; -- Open new row for access
FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros
FOR j IN (data_bits - 1) DOWNTO 0 LOOP
Bank0 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "01" THEN
IF Bank1 (Row_index) = NULL THEN
Bank1 (Row_index) := NEW Array_ram_type;
FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits - 1) DOWNTO 0 LOOP
Bank1 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "10" THEN
IF Bank2 (Row_index) = NULL THEN
Bank2 (Row_index) := NEW Array_ram_type;
FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits - 1) DOWNTO 0 LOOP
Bank2 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "11" THEN
IF Bank3 (Row_index) = NULL THEN
Bank3 (Row_index) := NEW Array_ram_type;
FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits - 1) DOWNTO 0 LOOP
Bank3 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
END IF;
END;
--
-- Burst Counter
--
PROCEDURE Burst_decode IS
VARIABLE Cols_temp : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- Advance burst counter
Burst_counter := Burst_counter + 1;
-- Burst Type
IF Mode_reg (3) = '0' THEN
Cols_temp := Cols_addr + 1;
ELSIF Mode_reg (3) = '1' THEN
Cols_temp (2) := Burst_counter (2) XOR Cols_brst (2);
Cols_temp (1) := Burst_counter (1) XOR Cols_brst (1);
Cols_temp (0) := Burst_counter (0) XOR Cols_brst (0);
END IF;
-- Burst Length
IF Burst_length_2 = '1' THEN
Cols_addr (0) := Cols_temp (0);
ELSIF Burst_length_4 = '1' THEN
Cols_addr (1 DOWNTO 0) := Cols_temp (1 DOWNTO 0);
ELSIF Burst_length_8 = '1' THEN
Cols_addr (2 DOWNTO 0) := Cols_temp (2 DOWNTO 0);
ELSE
Cols_addr := Cols_temp;
END IF;
-- Data counter
IF Burst_length_2 = '1' THEN
IF Burst_counter >= 2 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_4 = '1' THEN
IF Burst_counter >= 4 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_8 = '1' THEN
IF Burst_counter >= 8 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
END IF;
END;
BEGIN
WAIT ON Sys_clk;
--
-- Manual Precharge Pipeline
--
IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN
-- A10 Precharge Pipeline
A10_precharge(0) := A10_precharge(1);
A10_precharge(1) := A10_precharge(2);
A10_precharge(2) := A10_precharge(3);
A10_precharge(3) := A10_precharge(4);
A10_precharge(4) := A10_precharge(5);
A10_precharge(5) := A10_precharge(6);
A10_precharge(6) := A10_precharge(7);
A10_precharge(7) := A10_precharge(8);
A10_precharge(8) := '0';
-- Bank Precharge Pipeline
Bank_precharge(0) := Bank_precharge(1);
Bank_precharge(1) := Bank_precharge(2);
Bank_precharge(2) := Bank_precharge(3);
Bank_precharge(3) := Bank_precharge(4);
Bank_precharge(4) := Bank_precharge(5);
Bank_precharge(5) := Bank_precharge(6);
Bank_precharge(6) := Bank_precharge(7);
Bank_precharge(7) := Bank_precharge(8);
Bank_precharge(8) := "00";
-- Command Precharge Pipeline
Cmnd_precharge(0) := Cmnd_precharge(1);
Cmnd_precharge(1) := Cmnd_precharge(2);
Cmnd_precharge(2) := Cmnd_precharge(3);
Cmnd_precharge(3) := Cmnd_precharge(4);
Cmnd_precharge(4) := Cmnd_precharge(5);
Cmnd_precharge(5) := Cmnd_precharge(6);
Cmnd_precharge(6) := Cmnd_precharge(7);
Cmnd_precharge(7) := Cmnd_precharge(8);
Cmnd_precharge(8) := '0';
-- Terminate Read if same bank or all banks
IF ((Cmnd_precharge (0) = '1') AND
(Bank_precharge (0) = Bank_addr OR A10_precharge (0) = '1') AND
(Data_out_enable = '1')) THEN
Data_out_enable := '0';
END IF;
END IF;
--
-- Burst Terminate Pipeline
--
IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN
-- Burst Terminate pipeline
Cmnd_bst (0) := Cmnd_bst (1);
Cmnd_bst (1) := Cmnd_bst (2);
Cmnd_bst (2) := Cmnd_bst (3);
Cmnd_bst (3) := Cmnd_bst (4);
Cmnd_bst (4) := Cmnd_bst (5);
Cmnd_bst (5) := Cmnd_bst (6);
Cmnd_bst (6) := Cmnd_bst (7);
Cmnd_bst (7) := Cmnd_bst (8);
Cmnd_bst (8) := '0';
-- Terminate current Read
IF ((Cmnd_bst (0) = '1') AND (Data_out_enable = '1')) THEN
Data_out_enable := '0';
END IF;
END IF;
--
-- Dq and Dqs Drivers
--
IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN
-- Read Command Pipeline
Read_cmnd (0) := Read_cmnd (1);
Read_cmnd (1) := Read_cmnd (2);
Read_cmnd (2) := Read_cmnd (3);
Read_cmnd (3) := Read_cmnd (4);
Read_cmnd (4) := Read_cmnd (5);
Read_cmnd (5) := Read_cmnd (6);
Read_cmnd (6) := Read_cmnd (7);
Read_cmnd (7) := Read_cmnd (8);
Read_cmnd (8) := '0';
-- Read Bank Pipeline
Read_bank (0) := Read_bank (1);
Read_bank (1) := Read_bank (2);
Read_bank (2) := Read_bank (3);
Read_bank (3) := Read_bank (4);
Read_bank (4) := Read_bank (5);
Read_bank (5) := Read_bank (6);
Read_bank (6) := Read_bank (7);
Read_bank (7) := Read_bank (8);
Read_bank (8) := "00";
-- Read Column Pipeline
Read_cols (0) := Read_cols (1);
Read_cols (1) := Read_cols (2);
Read_cols (2) := Read_cols (3);
Read_cols (3) := Read_cols (4);
Read_cols (4) := Read_cols (5);
Read_cols (5) := Read_cols (6);
Read_cols (6) := Read_cols (7);
Read_cols (7) := Read_cols (8);
Read_cols (8) := (OTHERS => '0');
-- Initialize Read command
IF Read_cmnd (0) = '1' THEN
Data_out_enable := '1';
Bank_addr := Read_bank (0);
Cols_addr := Read_cols (0);
Cols_brst := Cols_addr (2 DOWNTO 0);
Burst_counter := (OTHERS => '0');
-- Row address mux
CASE Bank_addr IS
WHEN "00" => Rows_addr := B0_row_addr;
WHEN "01" => Rows_addr := B1_row_addr;
WHEN "10" => Rows_addr := B2_row_addr;
WHEN OTHERS => Rows_addr := B3_row_addr;
END CASE;
END IF;
-- Toggle Dqs during Read command
IF Data_out_enable = '1' THEN
Dqs_int := '0';
IF Dqs_out = "00" THEN
Dqs_out <= "11";
ELSIF Dqs_out = "11" THEN
Dqs_out <= "00";
ELSE
Dqs_out <= "00";
END IF;
ELSIF Data_out_enable = '0' AND Dqs_int = '0' THEN
Dqs_out <= "ZZ";
END IF;
-- Initialize Dqs for Read command
IF Read_cmnd (2) = '1' THEN
IF Data_out_enable = '0' THEN
Dqs_int := '1';
Dqs_out <= "00";
END IF;
END IF;
-- Read Latch
IF Data_out_enable = '1' THEN
-- Initialize Memory
Init_mem (Bank_addr, CONV_INTEGER(Rows_addr));
-- Output Data
CASE Bank_addr IS
WHEN "00" => Dq <= Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
WHEN "01" => Dq <= Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
WHEN "10" => Dq <= Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
WHEN OTHERS => Dq <= Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
END CASE;
-- Increase Burst Counter
Burst_decode;
ELSE
Dq <= (OTHERS => 'Z');
END IF;
END IF;
--
-- Write FIFO and DM Mask Logic
--
IF Sys_clk'EVENT AND Sys_clk = '1' THEN
-- Write command pipeline
Write_cmnd (0) := Write_cmnd (1);
Write_cmnd (1) := Write_cmnd (2);
Write_cmnd (2) := '0';
-- Write command pipeline
Write_bank (0) := Write_bank (1);
Write_bank (1) := Write_bank (2);
Write_bank (2) := "00";
-- Write column pipeline
Write_cols (0) := Write_cols (1);
Write_cols (1) := Write_cols (2);
Write_cols (2) := (OTHERS => '0');
-- Initialize Write command
IF Write_cmnd (0) = '1' THEN
Data_in_enable := '1';
Bank_addr := Write_bank (0);
Cols_addr := Write_cols (0);
Cols_brst := Cols_addr (2 DOWNTO 0);
Burst_counter := (OTHERS => '0');
-- Row address mux
CASE Bank_addr IS
WHEN "00" => Rows_addr := B0_row_addr;
WHEN "01" => Rows_addr := B1_row_addr;
WHEN "10" => Rows_addr := B2_row_addr;
WHEN OTHERS => Rows_addr := B3_row_addr;
END CASE;
END IF;
-- Write data
IF Data_in_enable = '1' THEN
-- Initialize memory
Init_mem (Bank_addr, CONV_INTEGER(Rows_addr));
-- Write first data
IF Dm_pair (1) = '0' OR Dm_pair (0) = '0' THEN
-- Data Buffer
CASE Bank_addr IS
WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
END CASE;
-- Perform DM Mask
IF Dm_pair (0) = '0' THEN
Data_buf ( 7 DOWNTO 0) := Dq_pair ( 7 DOWNTO 0);
END IF;
IF Dm_pair (1) = '0' THEN
Data_buf (15 DOWNTO 8) := Dq_pair (15 DOWNTO 8);
END IF;
-- Write Data
CASE Bank_addr IS
WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
END CASE;
END IF;
-- Increase Burst Counter
Burst_decode;
-- Write second data
IF Dm_pair (3) = '0' OR Dm_pair (2) = '0' THEN
-- Data Buffer
CASE Bank_addr IS
WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
END CASE;
-- Perform DM Mask
IF Dm_pair (2) = '0' THEN
Data_buf ( 7 DOWNTO 0) := Dq_pair (23 DOWNTO 16);
END IF;
IF Dm_pair (3) = '0' THEN
Data_buf (15 DOWNTO 8) := Dq_pair (31 DOWNTO 24);
END IF;
-- Write Data
CASE Bank_addr IS
WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
END CASE;
END IF;
-- Increase Burst Counter
Burst_decode;
-- tWR start and tWTR check
IF Dm_pair (3 DOWNTO 2) = "00" OR Dm_pair (1 DOWNTO 0) = "00" THEN
CASE Bank_addr IS
WHEN "00" => WR_chk0 := NOW;
WHEN "01" => WR_chk1 := NOW;
WHEN "10" => WR_chk2 := NOW;
WHEN OTHERS => WR_chk3 := NOW;
END CASE;
-- tWTR check
ASSERT (Read_enable = '0')
REPORT "tWTR violation during Read"
SEVERITY WARNING;
END IF;
END IF;
END IF;
--
-- Auto Precharge Calculation
--
IF Sys_clk'EVENT AND Sys_clk = '1' THEN
-- Precharge counter
IF Read_precharge (0) = '1' OR Write_precharge (0) = '1' THEN
Count_precharge (0) := Count_precharge (0) + 1;
END IF;
IF Read_precharge (1) = '1' OR Write_precharge (1) = '1' THEN
Count_precharge (1) := Count_precharge (1) + 1;
END IF;
IF Read_precharge (2) = '1' OR Write_precharge (2) = '1' THEN
Count_precharge (2) := Count_precharge (2) + 1;
END IF;
IF Read_precharge (3) = '1' OR Write_precharge (3) = '1' THEN
Count_precharge (3) := Count_precharge (3) + 1;
END IF;
-- Read with AutoPrecharge Calculation
-- The device start internal precharge when:
-- 1. Meet tRAS requirement
-- 2. BL/2 cycles after command
IF ((Read_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN
IF ((Burst_length_2 = '1' AND Count_precharge(0) >= 1) OR
(Burst_length_4 = '1' AND Count_precharge(0) >= 2) OR
(Burst_length_8 = '1' AND Count_precharge(0) >= 4)) THEN
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
Read_precharge(0) := '0';
END IF;
END IF;
IF ((Read_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN
IF ((Burst_length_2 = '1' AND Count_precharge(1) >= 1) OR
(Burst_length_4 = '1' AND Count_precharge(1) >= 2) OR
(Burst_length_8 = '1' AND Count_precharge(1) >= 4)) THEN
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
Read_precharge(1) := '0';
END IF;
END IF;
IF ((Read_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN
IF ((Burst_length_2 = '1' AND Count_precharge(2) >= 1) OR
(Burst_length_4 = '1' AND Count_precharge(2) >= 2) OR
(Burst_length_8 = '1' AND Count_precharge(2) >= 4)) THEN
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW;
Read_precharge(2) := '0';
END IF;
END IF;
IF ((Read_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN
IF ((Burst_length_2 = '1' AND Count_precharge(3) >= 1) OR
(Burst_length_4 = '1' AND Count_precharge(3) >= 2) OR
(Burst_length_8 = '1' AND Count_precharge(3) >= 4)) THEN
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW;
Read_precharge(3) := '0';
END IF;
END IF;
-- Write with AutoPrecharge Calculation
-- The device start internal precharge when:
-- 1. Meet tRAS requirement
-- 2. Two clock after last burst
-- Since tWR is time base, the model will compensate tRP
IF ((Write_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN
IF ((Burst_length_2 = '1' AND Count_precharge (0) >= 4) OR
(Burst_length_4 = '1' AND Count_precharge (0) >= 5) OR
(Burst_length_8 = '1' AND Count_precharge (0) >= 7)) THEN
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW - ((2 * tCK) - tWR);
Write_precharge(0) := '0';
END IF;
END IF;
IF ((Write_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN
IF ((Burst_length_2 = '1' AND Count_precharge (1) >= 4) OR
(Burst_length_4 = '1' AND Count_precharge (1) >= 5) OR
(Burst_length_8 = '1' AND Count_precharge (1) >= 7)) THEN
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW - ((2 * tCK) - tWR);
Write_precharge(1) := '0';
END IF;
END IF;
IF ((Write_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN
IF ((Burst_length_2 = '1' AND Count_precharge (2) >= 4) OR
(Burst_length_4 = '1' AND Count_precharge (2) >= 5) OR
(Burst_length_8 = '1' AND Count_precharge (2) >= 7)) THEN
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW - ((2 * tCK) - tWR);
Write_precharge(2) := '0';
END IF;
END IF;
IF ((Write_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN
IF ((Burst_length_2 = '1' AND Count_precharge (3) >= 4) OR
(Burst_length_4 = '1' AND Count_precharge (3) >= 5) OR
(Burst_length_8 = '1' AND Count_precharge (3) >= 7)) THEN
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW - ((2 * tCK) - tWR);
Write_precharge(3) := '0';
END IF;
END IF;
END IF;
--
-- DLL Counter
--
IF Sys_clk'EVENT AND Sys_clk = '1' THEN
IF (DLL_Reset = '1' AND DLL_done = '0') THEN
DLL_count := DLL_count + 1;
IF (DLL_count >= 200) THEN
DLL_done := '1';
END IF;
END IF;
END IF;
--
-- Control Logic
--
IF Sys_clk'EVENT AND Sys_clk = '1' THEN
-- Auto Refresh
IF Aref_enable = '1' THEN
-- Auto Refresh to Auto Refresh
ASSERT (NOW - RFC_chk >= tRFC)
REPORT "tRFC violation during Auto Refresh"
SEVERITY WARNING;
-- Precharge to Auto Refresh
ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
(NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))
REPORT "tRP violation during Auto Refresh"
SEVERITY WARNING;
-- Precharge to Auto Refresh
ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
REPORT "All banks must be Precharge before Auto Refresh"
SEVERITY WARNING;
-- Record current tRFC time
RFC_chk := NOW;
END IF;
-- Extended Load Mode Register
IF Ext_mode_enable = '1' THEN
IF (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') THEN
IF (Addr (0) = '0') THEN
DLL_enable := '1';
ELSE
DLL_enable := '0';
END IF;
END IF;
-- Precharge to EMR
ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
REPORT "All bank must be Precharged before Extended Mode Register"
SEVERITY WARNING;
-- Precharge to EMR
ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
(NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))
REPORT "tRP violation during Extended Load Register"
SEVERITY WARNING;
-- LMR/EMR to EMR
ASSERT (NOW - MRD_chk >= tMRD)
REPORT "tMRD violation during Extended Mode Register"
SEVERITY WARNING;
-- Record current tMRD time
MRD_chk := NOW;
END IF;
-- Load Mode Register
IF Mode_reg_enable = '1' THEN
-- Register mode
Mode_reg <= Addr;
-- DLL Reset
IF (DLL_enable = '1' AND Addr (8) = '1') THEN
DLL_reset := '1';
DLL_done := '0';
DLL_count := 0;
ELSIF (DLL_enable = '1' AND DLL_reset = '0' AND Addr (8) = '0') THEN
ASSERT (FALSE)
REPORT "DLL is ENABLE: DLL RESET is require"
SEVERITY WARNING;
ELSIF (DLL_enable = '0' AND Addr (8) = '1') THEN
ASSERT (FALSE)
REPORT "DLL is DISABLE: DLL RESET will be ignored"
SEVERITY WARNING;
END IF;
-- Precharge to LMR
ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
REPORT "All bank must be Precharged before Load Mode Register"
SEVERITY WARNING;
-- Precharge to EMR
ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
(NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))
REPORT "tRP violation during Load Mode Register"
SEVERITY WARNING;
-- LMR/ELMR to LMR
ASSERT (NOW - MRD_chk >= tMRD)
REPORT "tMRD violation during Load Mode Register"
SEVERITY WARNING;
-- Check for invalid Burst Length
ASSERT ((Addr (2 DOWNTO 0) = "001") OR -- BL = 2
(Addr (2 DOWNTO 0) = "010") OR -- BL = 4
(Addr (2 DOWNTO 0) = "011")) -- BL = 8
REPORT "Invalid Burst Length during Load Mode Register"
SEVERITY WARNING;
-- Check for invalid CAS Latency
ASSERT ((Addr (6 DOWNTO 4) = "010") OR -- CL = 2.0
(Addr (6 DOWNTO 4) = "110")) -- CL = 2.5
REPORT "Invalid CAS Latency during Load Mode Register"
SEVERITY WARNING;
-- Record current tMRD time
MRD_chk := NOW;
END IF;
-- Active Block (latch Bank and Row Address)
IF Active_enable = '1' THEN
-- Activate an OPEN bank can corrupt data
ASSERT ((Ba = "00" AND Act_b0 = '0') OR
(Ba = "01" AND Act_b1 = '0') OR
(Ba = "10" AND Act_b2 = '0') OR
(Ba = "11" AND Act_b3 = '0'))
REPORT "Bank is already activated - data can be corrupted"
SEVERITY WARNING;
-- Activate Bank 0
IF Ba = "00" AND Pc_b0 = '1' THEN
-- Activate to Activate (same bank)
ASSERT (NOW - RC_chk0 >= tRC)
REPORT "tRC violation during Activate Bank 0"
SEVERITY WARNING;
-- Precharge to Active
ASSERT (NOW - RP_chk0 >= tRP)
REPORT "tRP violation during Activate Bank 0"
SEVERITY WARNING;
-- Record Variables for checking violation
Act_b0 := '1';
Pc_b0 := '0';
B0_row_addr := Addr;
RC_chk0 := NOW;
RCD_chk0 := NOW;
RAS_chk0 := NOW;
RAP_chk0 := NOW;
END IF;
-- Activate Bank 1
IF Ba = "01" AND Pc_b1 = '1' THEN
-- Activate to Activate (same bank)
ASSERT (NOW - RC_chk1 >= tRC)
REPORT "tRC violation during Activate Bank 1"
SEVERITY WARNING;
-- Precharge to Active
ASSERT (NOW - RP_chk1 >= tRP)
REPORT "tRP violation during Activate Bank 1"
SEVERITY WARNING;
-- Record Variables for checking violation
Act_b1 := '1';
Pc_b1 := '0';
B1_row_addr := Addr;
RC_chk1 := NOW;
RCD_chk1 := NOW;
RAS_chk1 := NOW;
RAP_chk1 := NOW;
END IF;
-- Activate Bank 2
IF Ba = "10" AND Pc_b2 = '1' THEN
-- Activate to Activate (same bank)
ASSERT (NOW - RC_chk2 >= tRC)
REPORT "tRC violation during Activate Bank 2"
SEVERITY WARNING;
-- Precharge to Active
ASSERT (NOW - RP_chk2 >= tRP)
REPORT "tRP violation during Activate Bank 2"
SEVERITY WARNING;
-- Record Variables for checking violation
Act_b2 := '1';
Pc_b2 := '0';
B2_row_addr := Addr;
RC_chk2 := NOW;
RCD_chk2 := NOW;
RAS_chk2 := NOW;
RAP_chk2 := NOW;
END IF;
-- Activate Bank 3
IF Ba = "11" AND Pc_b3 = '1' THEN
-- Activate to Activate (same bank)
ASSERT (NOW - RC_chk3 >= tRC)
REPORT "tRC violation during Activate Bank 3"
SEVERITY WARNING;
-- Precharge to Active
ASSERT (NOW - RP_chk3 >= tRP)
REPORT "tRP violation during Activate Bank 3"
SEVERITY WARNING;
-- Record Variables for checking violation
Act_b3 := '1';
Pc_b3 := '0';
B3_row_addr := Addr;
RC_chk3 := NOW;
RCD_chk3 := NOW;
RAS_chk3 := NOW;
RAP_chk3 := NOW;
END IF;
-- Activate Bank A to Activate Bank B
IF (Prev_bank /= Ba) THEN
ASSERT (NOW - RRD_chk >= tRRD)
REPORT "tRRD violation during Activate"
SEVERITY WARNING;
END IF;
-- AutoRefresh to Activate
ASSERT (NOW - RFC_chk >= tRFC)
REPORT "tRFC violation during Activate"
SEVERITY WARNING;
-- Record Variables for Checking Violation
RRD_chk := NOW;
Prev_bank := Ba;
END IF;
-- Precharge Block - Consider NOP if bank already precharged or in process of precharging
IF Prech_enable = '1' THEN
-- EMR or LMR to Precharge
ASSERT (NOW - MRD_chk >= tMRD)
REPORT "tMRD violation during Precharge"
SEVERITY WARNING;
-- Precharge Bank 0
IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "00")) AND Act_b0 = '1') THEN
Act_b0 := '0';
Pc_b0 := '1';
RP_chk0 := NOW;
-- Activate to Precharge bank 0
ASSERT (NOW - RAS_chk0 >= tRAS)
REPORT "tRAS violation during Precharge"
SEVERITY WARNING;
-- tWR violation check for Write
ASSERT (NOW - WR_chk0 >= tWR)
REPORT "tWR violation during Precharge"
SEVERITY WARNING;
END IF;
-- Precharge Bank 1
IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "01")) AND Act_b1 = '1') THEN
Act_b1 := '0';
Pc_b1 := '1';
RP_chk1 := NOW;
-- Activate to Precharge
ASSERT (NOW - RAS_chk1 >= tRAS)
REPORT "tRAS violation during Precharge"
SEVERITY WARNING;
-- tWR violation check for Write
ASSERT (NOW - WR_chk1 >= tWR)
REPORT "tWR violation during Precharge"
SEVERITY WARNING;
END IF;
-- Precharge Bank 2
IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "10")) AND Act_b2 = '1') THEN
Act_b2 := '0';
Pc_b2 := '1';
RP_chk2 := NOW;
-- Activate to Precharge
ASSERT (NOW - RAS_chk2 >= tRAS)
REPORT "tRAS violation during Precharge"
SEVERITY WARNING;
-- tWR violation check for Write
ASSERT (NOW - WR_chk2 >= tWR)
REPORT "tWR violation during Precharge"
SEVERITY WARNING;
END IF;
-- Precharge Bank 3
IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "11")) AND Act_b3 = '1') THEN
Act_b3 := '0';
Pc_b3 := '1';
RP_chk3 := NOW;
-- Activate to Precharge
ASSERT (NOW - RAS_chk3 >= tRAS)
REPORT "tRAS violation during Precharge"
SEVERITY WARNING;
-- tWR violation check for Write
ASSERT (NOW - WR_chk3 >= tWR)
REPORT "tWR violation during Precharge"
SEVERITY WARNING;
END IF;
-- Pipeline for READ
IF CAS_latency_15 = '1' THEN
A10_precharge (3) := Addr(10);
Bank_precharge (3) := Ba;
Cmnd_precharge (3) := '1';
ELSIF CAS_latency_2 = '1' THEN
A10_precharge (4) := Addr(10);
Bank_precharge (4) := Ba;
Cmnd_precharge (4) := '1';
ELSIF CAS_latency_25 = '1' THEN
A10_precharge (5) := Addr(10);
Bank_precharge (5) := Ba;
Cmnd_precharge (5) := '1';
ELSIF CAS_latency_3 = '1' THEN
A10_precharge (6) := Addr(10);
Bank_precharge (6) := Ba;
Cmnd_precharge (6) := '1';
ELSIF CAS_latency_4 = '1' THEN
A10_precharge (8) := Addr(10);
Bank_precharge (8) := Ba;
Cmnd_precharge (8) := '1';
END IF;
END IF;
-- Burst Terminate
IF Burst_term = '1' THEN
-- Pipeline for Read
IF CAS_latency_15 = '1' THEN
Cmnd_bst (3) := '1';
ELSIF CAS_latency_2 = '1' THEN
Cmnd_bst (4) := '1';
ELSIF CAS_latency_25 = '1' THEN
Cmnd_bst (5) := '1';
ELSIF CAS_latency_3 = '1' THEN
Cmnd_bst (6) := '1';
ELSIF CAS_latency_4 = '1' THEN
Cmnd_bst (8) := '1';
END IF;
-- Terminate Write
ASSERT (Data_in_enable = '0')
REPORT "It's illegal to Burst Terminate a Write"
SEVERITY WARNING;
-- Terminate Read with Auto Precharge
ASSERT (Read_precharge (0) = '0' AND Read_precharge (1) = '0' AND
Read_precharge (2) = '0' AND Read_precharge (3) = '0')
REPORT "It's illegal to Burst Terminate a Read with Auto Precharge"
SEVERITY WARNING;
END IF;
-- Read Command
IF Read_enable = '1' THEN
-- CAS Latency Pipeline
IF Cas_latency_15 = '1' THEN
Read_cmnd (3) := '1';
Read_bank (3) := Ba;
Read_cols (3) := Addr (8 DOWNTO 0);
ELSIF Cas_latency_2 = '1' THEN
Read_cmnd (4) := '1';
Read_bank (4) := Ba;
Read_cols (4) := Addr (8 DOWNTO 0);
ELSIF Cas_latency_25 = '1' THEN
Read_cmnd (5) := '1';
Read_bank (5) := Ba;
Read_cols (5) := Addr (8 DOWNTO 0);
ELSIF Cas_latency_3 = '1' THEN
Read_cmnd (6) := '1';
Read_bank (6) := Ba;
Read_cols (6) := Addr (8 DOWNTO 0);
ELSIF Cas_latency_4 = '1' THEN
Read_cmnd (8) := '1';
Read_bank (8) := Ba;
Read_cols (8) := Addr (8 DOWNTO 0);
END IF;
-- Write to Read: Terminate Write Immediately
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Interrupting a Read with Auto Precharge (same bank only)
ASSERT (Read_precharge(CONV_INTEGER(Ba)) = '0')
REPORT "It's illegal to interrupt a Read with Auto Precharge"
SEVERITY WARNING;
-- Activate to Read
ASSERT ((Ba = "00" AND Act_b0 = '1') OR
(Ba = "01" AND Act_b1 = '1') OR
(Ba = "10" AND Act_b2 = '1') OR
(Ba = "11" AND Act_b3 = '1'))
REPORT "Bank is not Activated for Read"
SEVERITY WARNING;
-- Activate to Read without Auto Precharge
IF Addr (10) = '0' THEN
ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR
(Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR
(Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR
(Ba = "11" AND NOW - RCD_chk3 >= tRCD))
REPORT "tRCD violation during Read"
SEVERITY WARNING;
END IF;
-- Activate to Read with Auto Precharge
IF Addr (10) = '1' THEN
ASSERT ((Ba = "00" AND NOW - RAP_chk0 >= tRAP) OR
(Ba = "01" AND NOW - RAP_chk1 >= tRAP) OR
(Ba = "10" AND NOW - RAP_chk2 >= tRAP) OR
(Ba = "11" AND NOW - RAP_chk3 >= tRAP))
REPORT "tRAP violation during Read"
SEVERITY WARNING;
END IF;
-- Auto precharge
IF Addr (10) = '1' THEN
Read_precharge (Conv_INTEGER(Ba)) := '1';
Count_precharge (Conv_INTEGER(Ba)) := 0;
END IF;
-- DLL Check
IF (DLL_reset = '1') THEN
ASSERT (DLL_done = '1')
REPORT "DLL RESET not complete"
SEVERITY WARNING;
END IF;
END IF;
-- Write Command
IF Write_enable = '1' THEN
-- Pipeline for Write
Write_cmnd (2) := '1';
Write_bank (2) := Ba;
Write_cols (2) := Addr (8 DOWNTO 0);
-- Interrupting a Write with Auto Precharge (same bank only)
ASSERT (Write_precharge(CONV_INTEGER(Ba)) = '0')
REPORT "It's illegal to interrupt a Write with Auto Precharge"
SEVERITY WARNING;
-- Activate to Write
ASSERT ((Ba = "00" AND Act_b0 = '1') OR
(Ba = "01" AND Act_b1 = '1') OR
(Ba = "10" AND Act_b2 = '1') OR
(Ba = "11" AND Act_b3 = '1'))
REPORT "Bank is not Activated for Write"
SEVERITY WARNING;
-- Activate to Write
ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR
(Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR
(Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR
(Ba = "11" AND NOW - RCD_chk3 >= tRCD))
REPORT "tRCD violation during Write"
SEVERITY WARNING;
-- Auto precharge
IF Addr (10) = '1' THEN
Write_precharge (Conv_INTEGER(Ba)) := '1';
Count_precharge (Conv_INTEGER(Ba)) := 0;
END IF;
END IF;
END IF;
END PROCESS;
--
-- Dqs Receiver
--
dqs_rcvrs : PROCESS
VARIABLE Dm_temp : STD_LOGIC_VECTOR (1 DOWNTO 0);
VARIABLE Dq_temp : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
BEGIN
WAIT ON Dqs;
-- Latch data at posedge Dqs
IF Dqs'EVENT AND Dqs (1) = '1' AND Dqs (0) = '1' THEN
Dq_temp := Dq;
Dm_temp := Dm;
END IF;
-- Latch data at negedge Dqs
IF Dqs'EVENT AND Dqs (1) = '0' AND Dqs (0) = '0' THEN
Dq_pair <= (Dq & Dq_temp);
Dm_pair <= (Dm & Dm_temp);
END IF;
END PROCESS;
--
-- Setup timing checks
--
Setup_check : PROCESS
BEGIN
WAIT ON Sys_clk;
IF Sys_clk'EVENT AND Sys_clk = '1' THEN
ASSERT(Cke'LAST_EVENT >= tIS)
REPORT "CKE Setup time violation -- tIS"
SEVERITY WARNING;
ASSERT(Cs_n'LAST_EVENT >= tIS)
REPORT "CS# Setup time violation -- tIS"
SEVERITY WARNING;
ASSERT(Cas_n'LAST_EVENT >= tIS)
REPORT "CAS# Setup time violation -- tIS"
SEVERITY WARNING;
ASSERT(Ras_n'LAST_EVENT >= tIS)
REPORT "RAS# Setup time violation -- tIS"
SEVERITY WARNING;
ASSERT(We_n'LAST_EVENT >= tIS)
REPORT "WE# Setup time violation -- tIS"
SEVERITY WARNING;
ASSERT(Addr'LAST_EVENT >= tIS)
REPORT "ADDR Setup time violation -- tIS"
SEVERITY WARNING;
ASSERT(Ba'LAST_EVENT >= tIS)
REPORT "BA Setup time violation -- tIS"
SEVERITY WARNING;
END IF;
END PROCESS;
--
-- Hold timing checks
--
Hold_check : PROCESS
BEGIN
WAIT ON Sys_clk'DELAYED (tIH);
IF Sys_clk'DELAYED (tIH) = '1' THEN
ASSERT(Cke'LAST_EVENT >= tIH)
REPORT "CKE Hold time violation -- tIH"
SEVERITY WARNING;
ASSERT(Cs_n'LAST_EVENT >= tIH)
REPORT "CS# Hold time violation -- tIH"
SEVERITY WARNING;
ASSERT(Cas_n'LAST_EVENT >= tIH)
REPORT "CAS# Hold time violation -- tIH"
SEVERITY WARNING;
ASSERT(Ras_n'LAST_EVENT >= tIH)
REPORT "RAS# Hold time violation -- tIH"
SEVERITY WARNING;
ASSERT(We_n'LAST_EVENT >= tIH)
REPORT "WE# Hold time violation -- tIH"
SEVERITY WARNING;
ASSERT(Addr'LAST_EVENT >= tIH)
REPORT "ADDR Hold time violation -- tIH"
SEVERITY WARNING;
ASSERT(Ba'LAST_EVENT >= tIH)
REPORT "BA Hold time violation -- tIH"
SEVERITY WARNING;
END IF;
END PROCESS;
END behave;
| gpl-3.0 | 66b440db674e24c1936660bf7146a74c | 0.438335 | 4.100082 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/MMX/MMX_EQU_8b.vhd | 1 | 1,692 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library ims;
--use ims.coprocessor.all;
entity MMX_EQU_8b is
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end;
architecture rtl of MMX_EQU_8b is
begin
-------------------------------------------------------------------------
-- synthesis translate_off
process
begin
wait for 1 ns;
REPORT "(IMS) MMX 8bis EQU RESSOURCE : ALLOCATION OK !";
wait;
end process;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : STD_LOGIC_VECTOR(7 downto 0);
variable rTemp2 : STD_LOGIC_VECTOR(7 downto 0);
variable rTemp3 : STD_LOGIC_VECTOR(7 downto 0);
variable rTemp4 : STD_LOGIC_VECTOR(7 downto 0);
begin
if( UNSIGNED(INPUT_1( 7 downto 0)) = UNSIGNED(INPUT_2( 7 downto 0)) ) then rTemp1 := "11111111"; else rTemp1 := "00000000"; end if;
if( UNSIGNED(INPUT_1(15 downto 8)) = UNSIGNED(INPUT_2(15 downto 8)) ) then rTemp2 := "11111111"; else rTemp2 := "00000000"; end if;
if( UNSIGNED(INPUT_1(23 downto 16)) = UNSIGNED(INPUT_2(23 downto 16)) ) then rTemp3 := "11111111"; else rTemp3 := "00000000"; end if;
if( UNSIGNED(INPUT_1(31 downto 24)) = UNSIGNED(INPUT_2(31 downto 24)) ) then rTemp4 := "11111111"; else rTemp4 := "00000000"; end if;
OUTPUT_1 <= (rTemp4 & rTemp3 & rTemp2 & rTemp1);
end process;
-------------------------------------------------------------------------
end;
| gpl-3.0 | f547bd4c03c4ab96af65f30358d29403 | 0.550236 | 3.453061 | false | false | false | false |
MForever78/CPUFly | ipcore_dir/Video_Memory/simulation/Video_Memory_tb_checker.vhd | 1 | 5,730 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Video_Memory_tb_checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.Video_Memory_TB_PKG.ALL;
ENTITY Video_Memory_TB_CHECKER IS
GENERIC (
WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END Video_Memory_TB_CHECKER;
ARCHITECTURE CHECKER_ARCH OF Video_Memory_TB_CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DGEN_INST:ENTITY work.Video_Memory_TB_DGEN
GENERIC MAP (
DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
| mit | 779123797466014f14ae111b7d97c13e | 0.587784 | 4.04947 | false | false | false | false |
makestuff/swled | fifo/vhdl/timer/tb_unit/timer_tb.vhdl | 1 | 2,532 | --
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity timer_tb is
end entity;
architecture behavioural of timer_tb is
constant COUNTER_WIDTH : integer := 4;
constant CEILING_WIDTH : integer := 2;
signal sysClk : std_logic;
signal dispClk : std_logic; -- display version of sysClk, which leads it by 4ns
signal ceiling : std_logic_vector(CEILING_WIDTH-1 downto 0);
signal tick : std_logic;
begin
-- Instantiate timer for testing
uut: entity work.timer
generic map(
COUNTER_WIDTH => COUNTER_WIDTH,
CEILING_WIDTH => CEILING_WIDTH
)
port map(
clk_in => sysClk,
ceiling_in => ceiling,
tick_out => tick
);
-- Drive the clocks. In simulation, sysClk lags 4ns behind dispClk, to give a visual hold time for
-- signals in GTKWave.
process
begin
sysClk <= '0';
dispClk <= '1';
wait for 10 ns;
dispClk <= '0';
wait for 10 ns;
loop
dispClk <= '1';
wait for 4 ns;
sysClk <= '1';
wait for 6 ns;
dispClk <= '0';
wait for 4 ns;
sysClk <= '0';
wait for 6 ns;
end loop;
end process;
-- Drive the timer
process
begin
ceiling <= "00";
wait until rising_edge(tick); wait until falling_edge(tick);
wait until rising_edge(tick); wait until falling_edge(tick);
ceiling <= "01";
wait until rising_edge(tick); wait until falling_edge(tick);
wait until rising_edge(tick); wait until falling_edge(tick);
ceiling <= "10";
wait until rising_edge(tick); wait until falling_edge(tick);
wait until rising_edge(tick); wait until falling_edge(tick);
ceiling <= "11";
wait until rising_edge(tick); wait until falling_edge(tick);
wait until rising_edge(tick); wait until falling_edge(tick);
ceiling <= "00";
wait;
end process;
end architecture;
| gpl-3.0 | 3aacd14efd85cdd271bea96ee10525b6 | 0.684439 | 3.407806 | false | false | false | false |
DGideas/THU-FPGA-makecomputer | src/cpu/mux_reg2.vhd | 1 | 1,296 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:25:11 05/06/2017
-- Design Name:
-- Module Name: Mux_reg2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mux_reg2 is
Port ( alusrcb : in STD_LOGIC_VECTOR (1 downto 0);
muxreg2 : in STD_LOGIC_VECTOR (15 downto 0);
mux_imm : in STD_LOGIC_VECTOR (15 downto 0);
mux_dataB : out STD_LOGIC_VECTOR (15 downto 0));
end mux_reg2;
architecture Behavioral of mux_reg2 is
begin
process(alusrcb)
begin
case alusrcb is
when "00"=>
mux_dataB<=muxreg2;
when "01"=>
mux_dataB<=mux_imm;
when others=>null;
end case;
end process;
end Behavioral;
| apache-2.0 | 4f41c1635fbf12d38d74944a9b97a176 | 0.584877 | 3.800587 | false | false | false | false |
makestuff/swled | cksum/vhdl/cksum_rtl.vhdl | 1 | 2,752 | --
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture rtl of swled is
-- Flags for display on the 7-seg decimal points
signal flags : std_logic_vector(3 downto 0);
-- Registers implementing the channels
signal checksum, checksum_next : std_logic_vector(15 downto 0) := (others => '0');
signal reg0, reg0_next : std_logic_vector(7 downto 0) := (others => '0');
begin --BEGIN_SNIPPET(registers)
-- Infer registers
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
if ( reset_in = '1' ) then
reg0 <= (others => '0');
checksum <= (others => '0');
else
reg0 <= reg0_next;
checksum <= checksum_next;
end if;
end if;
end process;
-- Drive register inputs for each channel when the host is writing
reg0_next <=
h2fData_in when chanAddr_in = "0000000" and h2fValid_in = '1'
else reg0;
checksum_next <=
std_logic_vector(unsigned(checksum) + unsigned(h2fData_in))
when chanAddr_in = "0000000" and h2fValid_in = '1'
else h2fData_in & checksum(7 downto 0)
when chanAddr_in = "0000001" and h2fValid_in = '1'
else checksum(15 downto 8) & h2fData_in
when chanAddr_in = "0000010" and h2fValid_in = '1'
else checksum;
-- Select values to return for each channel when the host is reading
with chanAddr_in select f2hData_out <=
sw_in when "0000000",
checksum(15 downto 8) when "0000001",
checksum(7 downto 0) when "0000010",
x"00" when others;
-- Assert that there's always data for reading, and always room for writing
f2hValid_out <= '1';
h2fReady_out <= '1'; --END_SNIPPET(registers)
-- LEDs and 7-seg display
led_out <= reg0;
flags <= "00" & f2hReady_in & reset_in;
seven_seg : entity work.seven_seg
port map(
clk_in => clk_in,
data_in => checksum,
dots_in => flags,
segs_out => sseg_out,
anodes_out => anode_out
);
end architecture;
| gpl-3.0 | b1cdd3248a4e1d41fc1042e4c66876b3 | 0.645349 | 3.384994 | false | false | false | false |
chibby0ne/vhdl-book | Chapter11/example2_dir/vending_machine_noglitch.vhd | 1 | 5,186 | --
-- vending machine FSM
--
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------
entity vending_machine_noglitch is
--generic declarations
port (
clk, rst: in std_logic;
nickel_in, dime_in, quarter_in: in boolean;
new_candy_out, new_nickel_out, new_dime_out: out std_logic);
end entity vending_machine_noglitch;
--------------------------------------
architecture circuit of vending_machine_noglitch is
type state is (st0, st5, st10, st15, st20, st25, st30, st35, st40, st45);
signal pr_state, nx_state: state;
attribute enum_encoding: string;
attribute enum_encoding of state: type is "sequential";
-- output signals of fsm
signal candy_out, nickel_out, dime_out: std_logic;
begin
--------------------------------------
-- lower section of FSM (sequential part)
--------------------------------------
process (rst, clk)
--declarativepart
begin
if (rst = '1') then
pr_state <= st0;
elsif (clk'event and clk = '1') then
pr_state <= nx_state;
end if;
end process;
--------------------------------------
--------------------------------------
-- upper section of FSM (combinational part)
--------------------------------------
process (pr_state, nickel_in, dime_in, quarter_in)
--declarativepart
begin
case pr_state is
when st0 =>
candy_out <= '0';
nickel_out <= '0';
dime_out <= '0';
if (nickel_in) then
nx_state <= st5;
elsif (dime_in) then
nx_state <= st10;
elsif (quarter_in) then
nx_state <= st25;
else
nx_state <= st0;
end if;
when st5 =>
candy_out <= '0';
nickel_out <= '0';
dime_out <= '0';
if (nickel_in) then
nx_state <= st10;
elsif (dime_in) then
nx_state <= st15;
elsif (quarter_in) then
nx_state <= st30;
else
nx_state <= st5;
end if;
when st10 =>
candy_out <= '0';
nickel_out <= '0';
dime_out <= '0';
if (nickel_in) then
nx_state <= st15;
elsif (dime_in) then
nx_state <= st20;
elsif (quarter_in) then
nx_state <= st35;
else
nx_state <= st10;
end if;
when st15 =>
candy_out <= '0';
nickel_out <= '0';
dime_out <= '0';
if (nickel_in) then
nx_state <= st20;
elsif (dime_in) then
nx_state <= st25;
elsif (quarter_in) then
nx_state <= st40;
else
nx_state <= st15;
end if;
when st20 =>
candy_out <= '0';
nickel_out <= '0';
dime_out <= '0';
if (nickel_in) then
nx_state <= st25;
elsif (dime_in) then
nx_state <= st30;
elsif (quarter_in) then
nx_state <= st45;
else
nx_state <= st20;
end if;
when st25 =>
candy_out <= '1';
nickel_out <= '0';
dime_out <= '0';
nx_state <= st0;
when st30 =>
candy_out <= '1';
nickel_out <= '1';
dime_out <= '0';
nx_state <= st0;
when st35 =>
candy_out <= '1';
nickel_out <= '0';
dime_out <= '0';
nx_state <= st0;
when st40 =>
candy_out <= '0';
nickel_out <= '1';
dime_out <= '0';
nx_state <= st35;
when st45 =>
candy_out <= '0';
nickel_out <= '0';
dime_out <= '1';
nx_state <= st35;
end case;
end process;
--------------------------------------
--------------------------------------
-- Output section of FSM (for glitch free operation)
--------------------------------------
process (rst, clk)
--declarativepart
begin
if (rst = '1') then
new_candy_out <= '0';
new_nickel_out <= '0';
new_dime_out <= '0';
elsif (clk'event and clk = '1') then
new_candy_out <= candy_out;
new_nickel_out <= nickel_out;
new_dime_out <= dime_out;
end if;
end process;
--------------------------------------
end architecture circuit;
| gpl-3.0 | 3e64b164a6fb14b96dd219a697cd852c | 0.36425 | 4.626227 | false | false | false | false |
chibby0ne/vhdl-book | Chapter13/rom_dir/rom_tb.vhd | 1 | 3,142 | --!
--! Copyright (C) 2010 - 2013 Creonic GmbH
--!
--! @file: rom_tb.vhd
--! @brief: tb for rom
--! @author: Antonio Gutierrez
--! @date: 2014-04-23
--!
--!
--------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------
entity rom_tb is
generic (PERIOD: time := 40 ns;
PD: time := 3 ns);
end entity rom_tb;
--------------------------------------------------------
architecture circuit of rom_tb is
-- component declaration
component rom is
port (
clk: in std_logic;
address: in integer range 0 to 15;
data_out: out std_logic_vector(7 downto 0));
end component rom;
-- comp instantiation signal declaration
signal clk_tb: std_logic := '0';
signal address_tb: integer range 0 to 15 := 0;
signal data_out_tb: std_logic_vector(7 downto 0);
-- signal for comparison of output
type memory is array (0 to 15) of std_logic_vector(7 downto 0);
constant myrom: memory := (
2 => "11111111", --255
3 => "00011010", --26
4 => "00000101", --5
5 => "01010000", --80
6 => "10110000", --176
15 => "00010001", --17
others => "00000000");
begin
--------------------------------------------------------------------------------------
-- dut instantiation
--------------------------------------------------------------------------------------
dut: rom port map (
clk =>clk_tb,
address => address_tb,
data_out => data_out_tb
);
--------------------------------------------------------------------------------------
-- stimuli generation
--------------------------------------------------------------------------------------
-- clk
clk_tb <= not clk_tb after PERIOD/2;
-- address
process
variable i: integer range 0 to 15 := 0;
begin
if (i < 15) then
wait for PERIOD;
i := i + 1;
address_tb <= i;
end if;
end process;
--------------------------------------------------------------------------------------
-- output comparison
--------------------------------------------------------------------------------------
process
variable first: integer range 0 to 1 := 0;
variable i: integer range 0 to 15 := 0;
begin
-- add PD to compare output at a time after signal toogling
if (first = 0) then
first := 1;
wait for PD;
end if;
-- wait for clk rising edge
wait for PERIOD/2;
assert data_out_tb = myrom(i)
report "output mismatch!"
severity failure;
-- checked all possible outputs
if (i = 15) then
assert false
report "no errors"
severity failure;
end if;
-- increment address
i := i + 1;
-- wait for clock falling edge
wait for PERIOD/2;
end process;
end architecture circuit;
| gpl-3.0 | d389f8111beff7de2dc4e04fd10e7d0c | 0.408339 | 5.108943 | false | false | false | false |
chibby0ne/vhdl-book | Chapter3/array_slicing_1x1_dir/array_slicing_1x1.vhd | 1 | 1,069 | ------------------------------
entity array_slices is
--generic declarations
port (
row: in integer range 1 to 3;
column: in integer range 0 to 4;
slice1 out bit;
slice2: out bit_vector(1 to 2););
slice2: out bit_vector(1 to 4););
slice2: out bit_vector(1 to 3););
end entity;
------------------------------
architecture circuit of array_slices is
type onedoned is array (1 to 3) of bit_vector(1 to 4);
constant table: onedoned := (('0', '0', '0', '1'),
('1', '0', '0', '1'),
('1', '1', '0', '1'));
begin
slice1 <= table(row)(column);
slice2 <= table(row)(1 to 2);
slice3 <= table(row)(1 to 4);
-- slice4 <= table(1 to 3)(column); -- not synthesizable
-- slice <= table(1)(column) & table(2)(column) & table(3)(column); -- one solution but becomes cumbersome when there are many rows
gen: for i in 1 to 3 generate
slice4(i) <= table(i)(column);
end generate;
end architecture;
------------------------------
| gpl-3.0 | de8bb2d725b4e6b99e9b0be5ccd7591d | 0.500468 | 3.764085 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/custom/filtre/coproc_1.vhd | 1 | 2,239 | ---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity coproc_1 is
port(
clock : in std_logic;
reset : in std_logic;
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_1_valid : in std_logic;
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of coproc_1 is
SIGNAL mem : UNSIGNED(31 downto 0);
signal val0, val1, val2: unsigned(7 downto 0);
signal r_0_0, r_0_1, r_0_2, r_1_0, r_1_1, r_1_2, r_2_0, r_2_1, r_2_2 : unsigned(7 downto 0);
signal sum1, sum2 : unsigned(9 downto 0);
begin
shift_register : process (clock, reset)
begin
IF clock'event AND clock = '1' THEN
IF reset = '1' THEN
r_0_0 <= (others => '0');
r_0_1 <= (others => '0');
r_0_2 <= (others => '0');
r_1_0 <= (others => '0');
r_1_1 <= (others => '0');
r_1_2 <= (others => '0');
r_2_0 <= (others => '0');
r_2_1 <= (others => '0');
r_2_2 <= (others => '0');
ELSE
IF INPUT_1_valid = '1' THEN
r_0_0 <= val0;
r_0_1 <= r_0_0;
r_0_2 <= r_0_1;
r_1_0 <= val1;
r_1_1 <= r_1_0;
r_1_2 <= r_1_1;
r_2_0 <= val2;
r_2_1 <= r_2_0;
r_2_2 <= r_2_1;
END IF;
END IF;
END IF;
end process;
-------------------------------------------------------------------------
val0 <= unsigned(INPUT_1(23 downto 16 ));
val1 <= unsigned(INPUT_1(15 downto 8 ));
val2 <= unsigned(INPUT_1(7 downto 0 ));
sum1 <= resize( (resize(r_0_1,9) + resize(r_0_2,9)) , 10 ) + resize(r_1_2,10);
sum2 <= resize( (resize(r_1_0,9) + resize(r_2_0,9)) , 10 ) + resize(r_2_1,10);
OUTPUT_1 <= std_logic_vector( resize( (signed(resize(sum2,11)) - signed(resize(sum1,11))), 32));
end; --architecture logic
| gpl-3.0 | 998f1217221eb6fdefdb807d15556f03 | 0.509603 | 2.687875 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/comb_alu_1.vhd | 1 | 4,927 | ---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity comb_alu_1 is
port(
clk : in std_logic;
reset_in : in std_logic;
a_in : in std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0);
alu_function : in std_logic_vector( 5 downto 0);
c_alu : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of comb_alu_1 is
signal HOLDN : STD_LOGIC;
signal CLK_LDPC : STD_LOGIC;
signal ldpc_instruction : STD_LOGIC_VECTOR(12 downto 0);
signal OUTPUT_LDPC : STD_LOGIC_VECTOR(31 downto 0);
signal sDESIGN_ID : STD_LOGIC_VECTOR(31 downto 0);
signal INTPUT_LDPC : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_1 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_2 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_3 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_4 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_5 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_6 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_7 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_8 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_9 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_10 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_11 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_12 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_13 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_14 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_15 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_16 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_17 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_18 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL RESULT_19 : STD_LOGIC_VECTOR(31 downto 0);
begin
FX1 : ENTITY WORK.function_1 PORT MAP( INPUT_1 => a_in, INPUT_2 => b_in, OUTPUT_1 => RESULT_1 );
FX2 : ENTITY WORK.function_2 PORT MAP( INPUT_1 => a_in, INPUT_2 => b_in, OUTPUT_1 => RESULT_2 );
FX3 : ENTITY WORK.function_3 PORT MAP( INPUT_1 => a_in, INPUT_2 => b_in, OUTPUT_1 => RESULT_3 );
FX4 : ENTITY WORK.function_4 PORT MAP( INPUT_1 => a_in, INPUT_2 => b_in, OUTPUT_1 => RESULT_4 );
FX5 : ENTITY WORK.function_5 PORT MAP( INPUT_1 => a_in, INPUT_2 => b_in, OUTPUT_1 => RESULT_5 );
FX6 : ENTITY WORK.function_6 PORT MAP( INPUT_1 => a_in, INPUT_2 => b_in, OUTPUT_1 => RESULT_6 );
FX7 : ENTITY WORK.function_7 PORT MAP( INPUT_1 => a_in, INPUT_2 => b_in, OUTPUT_1 => RESULT_7 );
FX8 : ENTITY WORK.function_8 PORT MAP( INPUT_1 => a_in, INPUT_2 => b_in, OUTPUT_1 => RESULT_8 );
FX9 : ENTITY WORK.function_9 PORT MAP( INPUT_1 => a_in, INPUT_2 => b_in, OUTPUT_1 => RESULT_9 );
FX10 : ENTITY WORK.function_10 PORT MAP( INPUT_1 => a_in, INPUT_2 => b_in, OUTPUT_1 => RESULT_10 );
FX11 : ENTITY WORK.function_11 PORT MAP( INPUT_1 => a_in, INPUT_2 => b_in, OUTPUT_1 => RESULT_11 );
FX12 : ENTITY WORK.function_12 PORT MAP( INPUT_1 => a_in, INPUT_2 => b_in, OUTPUT_1 => RESULT_12 );
FX13 : ENTITY WORK.function_13 PORT MAP( INPUT_1 => a_in, INPUT_2 => b_in, OUTPUT_1 => RESULT_13 );
FX14 : ENTITY WORK.function_14 PORT MAP( INPUT_1 => a_in, INPUT_2 => b_in, OUTPUT_1 => RESULT_14 );
FX15 : ENTITY WORK.function_15 PORT MAP( INPUT_1 => a_in, INPUT_2 => b_in, OUTPUT_1 => RESULT_15 );
FX16 : ENTITY WORK.function_16 PORT MAP( INPUT_1 => a_in, INPUT_2 => b_in, OUTPUT_1 => RESULT_16 );
FX17 : ENTITY WORK.function_17 PORT MAP( INPUT_1 => a_in, INPUT_2 => b_in, OUTPUT_1 => RESULT_17 );
FX18 : ENTITY WORK.function_18 PORT MAP( INPUT_1 => a_in, INPUT_2 => b_in, OUTPUT_1 => RESULT_18 );
-- FX19 : ENTITY WORK.function_19 PORT MAP( INPUT_1 => a_in, INPUT_2 => b_in, OUTPUT_1 => RESULT_19 );
with alu_function select
c_alu <=
RESULT_1 WHEN "000001",-- (01)
RESULT_2 WHEN "000101",-- (05)
RESULT_3 WHEN "001010",-- (0A)
RESULT_4 WHEN "011110",-- (1E)
RESULT_5 WHEN "011111",-- (1F)
RESULT_6 WHEN "101001",-- (29)
RESULT_7 WHEN "101100",-- (2C)
RESULT_8 WHEN "101110",-- (2E)
RESULT_9 WHEN "101111",-- (2F)
RESULT_10 WHEN "110000",-- (30)
RESULT_11 WHEN "110101",-- (35)
RESULT_12 WHEN "110111",-- (37)
RESULT_13 WHEN "111000",-- (38)
RESULT_14 WHEN "111001",-- (39)
RESULT_15 WHEN "111010",-- (3A)
RESULT_16 WHEN "111011",-- (3B)
RESULT_17 WHEN "111100",-- (3C)
RESULT_18 WHEN "111101",-- (3D)
-- RESULT_19 WHEN "111110",-- (3E)
"00000000000000000000000000000000" WHEN OTHERS; -- nop
end; --architecture logic
| gpl-3.0 | 35a54390cce7e21b134b40fc5a25de77 | 0.622285 | 2.802617 | false | false | false | false |
chibby0ne/vhdl-book | Chapter8/synchronous_counter_dir/synchronous_counter.vhd | 1 | 840 | --!
--! @file: synchronous_counter.vhd
--! @brief: synchronous counter cell
--! @author: Antonio Gutierrez
--! @date: 2013-11-27
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity sync_counter is
--generic declarations
port (
a, b, clk: in std_logic;
andq, q: out std_logic);
end entity sync_counter;
--------------------------------------
architecture circuit of sync_counter is
signal temp: std_logic;
begin
temp <= a and b;
ff: process (clk)
variable q_ff: std_logic;
begin
if (clk'event and clk = '1') then
q_ff := q_ff xor temp;
end if;
end process ff;
q <= q_ff;
andq <= temp;
end architecture circuit;
--------------------------------------
| gpl-3.0 | 435f7c012059bc50dc44d5e2634de9cd | 0.495238 | 4 | false | false | false | false |
makestuff/swled | templates/ss/vhdl/top_level.vhdl | 1 | 3,785 | --
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_level is
port(
sysClk_in : in std_logic; -- 50MHz system clock
-- USB interface -----------------------------------------------------------------------------
serClk_in : in std_logic; -- serial clock (async to sysClk_in)
serData_in : in std_logic; -- serial data in
serData_out : out std_logic; -- serial data out
-- Onboard peripherals -----------------------------------------------------------------------
sseg_out : out std_logic_vector(7 downto 0); -- seven-segment display cathodes (one for each segment)
anode_out : out std_logic_vector(3 downto 0); -- seven-segment display anodes (one for each digit)
led_out : out std_logic_vector(7 downto 0); -- eight LEDs
sw_in : in std_logic_vector(7 downto 0) -- eight switches
);
end entity;
architecture structural of top_level is
-- Channel read/write interface -----------------------------------------------------------------
signal chanAddr : std_logic_vector(6 downto 0); -- the selected channel (0-127)
-- Host >> FPGA pipe:
signal h2fData : std_logic_vector(7 downto 0); -- data lines used when the host writes to a channel
signal h2fValid : std_logic; -- '1' means "on the next clock rising edge, please accept the data on h2fData"
signal h2fReady : std_logic; -- channel logic can drive this low to say "I'm not ready for more data yet"
-- Host << FPGA pipe:
signal f2hData : std_logic_vector(7 downto 0); -- data lines used when the host reads from a channel
signal f2hValid : std_logic; -- channel logic can drive this low to say "I don't have data ready for you"
signal f2hReady : std_logic; -- '1' means "on the next clock rising edge, put your next byte of data on f2hData"
-- ----------------------------------------------------------------------------------------------
begin
-- CommFPGA module
comm_fpga_ss : entity work.comm_fpga_ss
port map(
clk_in => sysClk_in,
reset_in => '0',
-- USB interface
serClk_in => serClk_in,
serData_in => serData_in,
serData_out => serData_out,
-- DVR interface -> Connects to application module
chanAddr_out => chanAddr,
h2fData_out => h2fData,
h2fValid_out => h2fValid,
h2fReady_in => h2fReady,
f2hData_in => f2hData,
f2hValid_in => f2hValid,
f2hReady_out => f2hReady
);
-- Switches & LEDs application
swled_app : entity work.swled
port map(
clk_in => sysClk_in,
reset_in => '0',
-- DVR interface -> Connects to comm_fpga module
chanAddr_in => chanAddr,
h2fData_in => h2fData,
h2fValid_in => h2fValid,
h2fReady_out => h2fReady,
f2hData_out => f2hData,
f2hValid_out => f2hValid,
f2hReady_in => f2hReady,
-- External interface
sseg_out => sseg_out,
anode_out => anode_out,
led_out => led_out,
sw_in => sw_in
);
end architecture;
| gpl-3.0 | 1420cb456acd599cc18fe669ea03a05c | 0.596301 | 3.611641 | false | false | false | false |
chibby0ne/vhdl-book | Chapter9/exercise9_4_dir/exercise9_4.vhd | 1 | 1,108 | --!
--! @file: pkg_sll_slv.vhd
--! @brief: fucntion shift logical left
--! @author: Antonio Gutierrez
--! @date: 2013-11-27
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
package pkg_sll_slv is
function "sll"(slv : std_logic_vector; shift : integer) return std_logic_vector
end package pkg_sll_slv;
------------------------------
package body pkg_sll_slv is
function "sll"(slv : std_logic_vector; shift : integer) return std_logic_vector is
variable result: std_logic_vector(slv'left downto 0);
begin
if (shift > 0) then
result(result'left downto shift) := slv(slv'left - shift downto 0);
result(shift-1 downto 0) := (others => '0');
else
result(result'left-shift downto 0) := slv(slv'left downto shift);
result(result'left downto result'left-shift) := (others => '0');
end if;
return result;
end function shift_logical_left;
end package body pkg_sll_slv;
--------------------------------------
| gpl-3.0 | 5a15be26d95f5720ac3fd4a983e3b9fa | 0.548736 | 3.915194 | false | false | false | false |
chibby0ne/vhdl-book | Chapter7/exercise7_3_dir/exercise7_3.vhd | 1 | 1,442 | --!
--! @file: exericse7_3.vhd
--! @brief: latches and flip flop
--! @author: Antonio Gutierrez
--! @date: 2013-10-29
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity test is
--generic declarations
port (
d, clk, rst: in std_logic;
q: out std_logic);
end entity test;
--------------------------------------
architecture circuit of test is
--signals and declarations
begin
----code 1:----------------------------------
proc: process (d, clk, rst)
--declarativepart
begin
if (rst = '1') then
q <= '0';
elsif (clk = '1') then
q <= d
end if;
end process proc;
----code 2:-----------------------------------
proc2: process (clk)
--declarativepart
begin
if (clk'event and clk = '1') then
if (rst = '1') then
q <= '0';
else
q <= d;
end if;
end if;
end process proc2;
----code 3:----------------------------------
proc3: process (clk)
--declarativepart
begin
if (clk = '1') then
if (rst = '1') then
q <= '0';
else
q <= d;
end if;
end if;
end process proc3;
--------------------------------------------
end architecture circuit;
| gpl-3.0 | 8b1c9e0b7367ffe6c9f44aee7ddea5dc | 0.39043 | 4.464396 | false | true | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/coprocessor/INTERFACE_SEQU_1.vhd | 1 | 7,750 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library grlib;
--use grlib.stdlib.all;
library ims;
use ims.coprocessor.all;
use ims.conversion.all;
entity INTERFACE_SEQU_1 is
port (
rst : in std_ulogic;
clk : in std_ulogic;
holdn : in std_ulogic;
inp : in sequential32_in_type;
outp : out sequential32_out_type
);
end;
architecture rtl of INTERFACE_SEQU_1 is
-------------------------------------------------------------------------
-- PRAGMA BEGIN DECLARATION
-- PRAGMA END DECLARATION
-------------------------------------------------------------------------
-------------------------------------------------------------------------
-- PRAGMA BEGIN SIGNAL
-- PRAGMA END SIGNAL
-------------------------------------------------------------------------
SIGNAL INPUT_1 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL INPUT_2 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL FLUSH : STD_LOGIC;
SIGNAL START : STD_LOGIC;
SIGNAL dInstr : STD_LOGIC_VECTOR(8 downto 0);
SIGNAL aInstr : STD_LOGIC_VECTOR(8 downto 0);
SIGNAL eInstr : STD_LOGIC_VECTOR(8 downto 0);
SIGNAL mInstr : STD_LOGIC_VECTOR(8 downto 0);
SIGNAL op1d : std_logic_vector(1 downto 0);
SIGNAL op3d : std_logic_vector(5 downto 0);
SIGNAL op1a : std_logic_vector(1 downto 0);
SIGNAL op3a : std_logic_vector(5 downto 0);
SIGNAL op1e : std_logic_vector(1 downto 0);
SIGNAL op3e : std_logic_vector(5 downto 0);
SIGNAL holdI : std_logic;
SIGNAL gclock : std_logic;
SIGNAL gValue : std_logic;
SIGNAL gpipeline : std_logic; -- a, e, m
BEGIN
-- ON SIMPLIFIE LE CODE POUR LA SUITE
INPUT_1 <= inp.op1(31 downto 0);
INPUT_2 <= inp.op2(31 downto 0);
FLUSH <= inp.flush;
DELAY_START : process(clk, rst)
BEGIN
IF (rst = '0') then
START <= '0';
ELSE
START <= inp.start;
END IF;
END PROCESS;
dInstr <= inp.dInstr(13 downto 5);
aInstr <= inp.aInstr(13 downto 5);
eInstr <= inp.eInstr(13 downto 5);
mInstr <= inp.mInstr(13 downto 5);
-- op1d <= inp.dInstr(31 downto 30);
-- op3d <= inp.dInstr(24 downto 19);
-- op1a <= inp.aInstr(31 downto 30);
-- op3a <= inp.aInstr(24 downto 19);
-- op1e <= inp.eInstr(31 downto 30);
-- op3e <= inp.eInstr(24 downto 19);
-------------------------------------------------------------------------
--
-- VERSION FONCTIONNELLE DU PIPELINE ...
--
--GATED_CLOCK : process(clk, rst)
--BEGIN
-- if (rst = '0') then
-- gpipeline <= '0';
-- elsif clk'event and clk = '1' then
-- if HOLDn = '0' then
-- gpipeline <= gpipeline;
-- else
-- gpipeline <= (aInstr(2) AND START) OR (gpipeline AND (NOT nREADY_3));
-- end if;
-- end if;
--END PROCESS;
--gclock <= clk and (gpipeline OR (aInstr(2) AND START)); --gpipeline(0) OR gpipeline(1) OR gpipeline(2) OR (aInstr(2) AND START);
--PROCESS( gclock )
--BEGIN
--if clk'event and clk = '1' then
--printmsg("(SEQ1) => (GCLOCK) VALUE (" & to_bin_str(gpipeline(0) & gpipeline(1) & gpipeline(2) & aInstr(2) & START & gclock) & ")");
--if gclock = '1' then
--REPORT "(PGDC) CLOCK ENABLE (1)";
--elsif gclock = '0' then
--REPORT "(PGDC) CLOCK DISABLE (1)";
--else
--REPORT "(PGDC) CLOCK XXXXXXX (1)";
--end if;
--end if;
--END PROCESS;
--PROCESS( gpipeline )
--BEGIN
--if gpipeline'event then
--printmsg("(SEQ1) => (GCLOCK) VALUE (" & to_bin_str(gpipeline(0) & gpipeline(1) & gpipeline(2) & aInstr(2) & START & gclock) & ")");
--if gpipeline = '1' then
--REPORT "(PGDC) gpipeline ENABLE (1)";
--elsif gpipeline = '0' then
--REPORT "(PGDC) gpipeline DISABLE (1)";
--else
--REPORT "(PGDC) CLOCK XXXXXXX (1)";
--end if;
--end if;
--END PROCESS;
--WITH gpipeline SELECT
-- gclock <= '0' WHEN "000", '1' WHEN OTHERS;
-------------------------------------------------------------------------
-- PROCESS( inp )
-- BEGIN
-- if clk'event and clk = '1' then
-- IF inp.start = '1' THEN REPORT "(INT) inp.start = '1'"; END IF;
-- IF( (inp.dInstr(31 downto 30) = "10") AND (inp.dInstr(24 downto 19) = "101111") ) THEN
-- IF (dInstr(0) AND inp.start) = '1' THEN REPORT "(INT) dSTART TO DIVIDER"; END IF;
-- IF (dInstr(1) AND inp.start) = '1' THEN REPORT "(INT) dSTART TO MODULUS"; END IF;
-- IF (dInstr(2) AND inp.start) = '1' THEN REPORT "(INT) dSTART TO PGCD"; END IF;
-- IF ((dInstr(2) AND inp.start) = '1') AND (holdn = '0') THEN REPORT "(INT) dSTART AND holdN"; END IF;
-- printmsg("(INT) dSTART MEMORISATION PROCESS (" & to_int_str(INPUT_1,6) & ")");
-- printmsg("(INT) dSTART MEMORISATION PROCESS (" & to_int_str(INPUT_2,6) & ")");
-- printmsg("(INT) dSTART INSTRUCTION (" & to_bin_str(dInstr) & ")");
-- END IF;
-- IF START(0) = '1' THEN REPORT "(INT) aSTART = '1'"; END IF;
-- case op1a is
-- when "10" =>
-- case op3a is
-- when "101111" =>
-- IF (START(0) AND aInstr(0)) = '1' THEN REPORT "(INT) aSTART TO DIVIDER"; END IF;
-- IF (START(0) AND aInstr(1)) = '1' THEN REPORT "(INT) aSTART TO MODULUS"; END IF;
-- IF (START(0) AND aInstr(2)) = '1' THEN REPORT "(INT) aSTART TO PGCD"; END IF;
-- IF ((START(0) AND aInstr(2)) = '1') AND (holdn = '0') THEN REPORT "(INT) aSTART AND holdN"; END IF;
-- printmsg("(INT) aSTART MEMORISATION PROCESS (" & to_int_str(INPUT_1,6) & ")");
-- printmsg("(INT) aSTART MEMORISATION PROCESS (" & to_int_str(INPUT_2,6) & ")");
-- printmsg("(INT) aSTART INSTRUCTION (" & to_bin_str(aInstr) & ")");
-- when others => null;
-- end case;
-- when others => null;
-- end case;
-- IF START(1) = '1' THEN REPORT "(INT) eSTART = '1'"; END IF;
-- case op1e is
-- when "10" =>
-- case op3e is
-- when "101111" =>
-- IF (START(1) AND eInstr(0)) = '1' THEN REPORT "(INT) eSTART TO DIVIDER"; END IF;
-- IF (START(1) AND eInstr(1)) = '1' THEN REPORT "(INT) eSTART TO MODULUS"; END IF;
-- IF (START(1) AND eInstr(2)) = '1' THEN REPORT "(INT) eSTART TO PGCD"; END IF;
-- IF ((START(1) AND eInstr(2)) = '1') AND (holdn = '0') THEN REPORT "(INT) eSTART AND holdN"; END IF;
-- printmsg("(INT) eSTART MEMORISATION PROCESS (" & to_int_str(INPUT_1,6) & ")");
-- printmsg("(INT) eSTART MEMORISATION PROCESS (" & to_int_str(INPUT_2,6) & ")");
-- printmsg("(INT) eSTART INSTRUCTION (" & to_bin_str(eInstr) & ")");
-- when others => null;
-- end case;
-- when others => null;
-- end case;
-- end if;
-- end process;
-------------------------------------------------------------------------
-- PRAGMA BEGIN START_SIGNAL_GENERATION
-- PRAGMA END START_SIGNAL_GENERATION
-------------------------------------------------------------------------
-------------------------------------------------------------------------
-- PRAGMA BEGIN INSTANCIATION
-- PRAGMA END INSTANCIATION
-------------------------------------------------------------------------
-------------------------------------------------------------------------
-- PRAGMA BEGIN RESULT SELECTION
-- PRAGMA END RESULT SELECTION
-------------------------------------------------------------------------
-------------------------------------------------------------------------
-- PRAGMA BEGIN READY_SIGNAL_SELECTION
-- PRAGMA END READY_SIGNAL_SELECTION
-------------------------------------------------------------------------
END;
| gpl-3.0 | 23ecdf25fce8751177abe7d4bbe8fe2b | 0.488129 | 3.445976 | false | false | false | false |
jotego/jt51 | syn/xilinx/ym09/hdl/cpu09new.vhd | 1 | 330,051 | -- $Id: cpu09new.vhd,v 1.1 2007-12-09 16:06:03 dilbert57 Exp $
--===========================================================================----
--
-- S Y N T H E S I Z A B L E CPU09 - 6809 compatible CPU Core
--
-- www.OpenCores.Org - September 2003
-- This core adheres to the GNU public license
--
-- File name : cpu09.vhd
--
-- Purpose : 6809 CPU core
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_unsigned
--
-- Uses : None
--
-- Author : John E. Kent
-- [email protected]
--
--===========================================================================----
--
-- Revision History:
--===========================================================================--
--
-- Version 0.1 - 26 June 2003 - John Kent
-- Added extra level in state stack
-- fixed some calls to the extended addressing state
--
-- Version 0.2 - 5 Sept 2003 - John Kent
-- Fixed 16 bit indexed offset (was doing read rather than fetch)
-- Added/Fixed STY and STS instructions.
-- ORCC_STATE ANDed CC state rather than ORed it - Now fixed
-- CMPX Loaded ACCA and ACCB - Now fixed
--
-- Version 1.0 - 6 Sep 2003 - John Kent
-- Initial release to Open Cores
-- reversed clock edge
--
-- Version 1.1 - 29 November 2003 John kent
-- ACCA and ACCB indexed offsets are 2's complement.
-- ALU Right Mux now sign extends ACCA & ACCB offsets
-- Absolute Indirect addressing performed a read on the
-- second byte of the address rather than a fetch
-- so it formed an incorrect address. Now fixed.
--
-- Version 1.2 - 29 November 2003 John Kent
-- LEAX and LEAY affect the Z bit only
-- LEAS and LEAU do not affect any condition codes
-- added an extra ALU control for LEA.
--
-- Version 1.3 - 12 December 2003 John Kent
-- CWAI did not work, was missed a PUSH_ST on calling
-- the ANDCC_STATE. Thanks go to Ghassan Kraidy for
-- finding this fault.
--
-- Version 1.4 - 12 December 2003 John Kent
-- Missing cc_ctrl assignment in otherwise case of
-- lea_state resulted in cc_ctrl being latched in
-- that state.
-- The otherwise statement should never be reached,
-- and has been fixed simply to resolve synthesis warnings.
--
-- Version 1.5 - 17 january 2004 John kent
-- The clear instruction used "alu_ld8" to control the ALU
-- rather than "alu_clr". This mean the Carry was not being
-- cleared correctly.
--
-- Version 1.6 - 24 January 2004 John Kent
-- Fixed problems in PSHU instruction
--
-- Version 1.7 - 25 January 2004 John Kent
-- removed redundant "alu_inx" and "alu_dex'
-- Removed "test_alu" and "test_cc"
-- STD instruction did not set condition codes
-- JMP direct was not decoded properly
-- CLR direct performed an unwanted read cycle
-- Bogus "latch_md" in Page2 indexed addressing
--
-- Version 1.8 - 27 January 2004 John Kent
-- CWAI in decode1_state should increment the PC.
-- ABX is supposed to be an unsigned addition.
-- Added extra ALU function
-- ASR8 slightly changed in the ALU.
--
-- Version 1.9 - 20 August 2005
-- LSR8 is now handled in ASR8 and ROR8 case in the ALU,
-- rather than LSR16. There was a problem with single
-- operand instructions using the MD register which is
-- sign extended on the first 8 bit fetch.
--
-- Version 1.10 - 13 September 2005
-- TFR & EXG instructions did not work for the Condition Code Register
-- An extra case has been added to the ALU for the alu_tfr control
-- to assign the left ALU input (alu_left) to the condition code
-- outputs (cc_out).
--
-- Version 1.11 - 16 September 2005
-- JSR ,X should not predecrement S before calculating the jump address.
-- The reason is that JSR [0,S] needs S to point to the top of the stack
-- to fetch a valid vector address. The solution is to have the addressing
-- mode microcode called before decrementing S and then decrementing S in
-- JSR_STATE. JSR_STATE in turn calls PUSH_RETURN_LO_STATE rather than
-- PUSH_RETURN_HI_STATE so that both the High & Low halves of the PC are
-- pushed on the stack. This adds one extra bus cycle, but resolves the
-- addressing conflict. I've also removed the pre-decement S in
-- JSR EXTENDED as it also calls JSR_STATE.
--
-- Version 1.12 - 6th June 2006
-- 6809 Programming reference manual says V is not affected by ASR, LSR and ROR
-- This is different to the 6800. CLR should reset the V bit.
--
-- Version 1.13 - 7th July 2006
-- Disable NMI on reset until S Stack pointer has been loaded.
-- Added nmi_enable signal in sp_reg process and nmi_handler process.
--
-- Version 1.4 - 11th July 2006
-- 1. Added new state to RTI called rti_entire_state.
-- This state tests the CC register after it has been loaded
-- from the stack. Previously the current CC was tested which
-- was incorrect. The Entire Flag should be set before the
-- interrupt stacks the CC.
-- 2. On bogus Interrupts, int_cc_state went to rti_state,
-- which was an enumerated state, but not defined anywhere.
-- rti_state has been changed to rti_cc_state so that bogus interrupt
-- will perform an RTI after entering that state.
-- 3. Sync should generate an interrupt if the interrupt masks
-- are cleared. If the interrupt masks are set, then an interrupt
-- will cause the the PC to advance to the next instruction.
-- Note that I don't wait for an interrupt to be asserted for
-- three clock cycles.
-- 4. Added new ALU control state "alu_mul". "alu_mul" is used in
-- the Multiply instruction replacing "alu_add16". This is similar
-- to "alu_add16" except it sets the Carry bit to B7 of the result
-- in ACCB, sets the Zero bit if the 16 bit result is zero, but
-- does not affect The Half carry (H), Negative (N) or Overflow (V)
-- flags. The logic was re-arranged so that it adds md or zero so
-- that the Carry condition code is set on zero multiplicands.
-- 5. DAA (Decimal Adjust Accumulator) should set the Negative (N)
-- and Zero Flags. It will also affect the Overflow (V) flag although
-- the operation is undefined. It's anyones guess what DAA does to V.
--
--
-- Version 1.5 Jan 2007 - B. Cuzeau
-- * all rising_edge !
-- * code style,
-- * sensitivity lists
-- * cosmetic changes
-- * Added PC_OUT for debug purpose
-- * if halt <='1' line 9618 fixed
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity cpu09 is
port ( clk : in std_logic;
rst : in std_logic;
rw : out std_logic;
vma : out std_logic;
address : out std_logic_vector(15 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
halt : in std_logic;
hold : in std_logic;
irq : in std_logic;
firq : in std_logic;
nmi : in std_logic;
pc_out : out std_logic_vector(15 downto 0) -- For debug purpose
);
end;
architecture CPU_ARCH of cpu09 is
constant EBIT : integer := 7;
constant FBIT : integer := 6;
constant HBIT : integer := 5;
constant IBIT : integer := 4;
constant NBIT : integer := 3;
constant ZBIT : integer := 2;
constant VBIT : integer := 1;
constant CBIT : integer := 0;
--
-- Interrupt vector modifiers
--
constant RST_VEC : std_logic_vector(2 downto 0) := "111";
constant NMI_VEC : std_logic_vector(2 downto 0) := "110";
constant SWI_VEC : std_logic_vector(2 downto 0) := "101";
constant IRQ_VEC : std_logic_vector(2 downto 0) := "100";
constant FIRQ_VEC : std_logic_vector(2 downto 0) := "011";
constant SWI2_VEC : std_logic_vector(2 downto 0) := "010";
constant SWI3_VEC : std_logic_vector(2 downto 0) := "001";
constant RESV_VEC : std_logic_vector(2 downto 0) := "000";
type state_type is (
-- Start off in Reset
reset_state,
-- Fetch Interrupt Vectors (including reset)
vect_lo_state, vect_hi_state,
-- Fetch Instruction Cycle
fetch_state,
-- Decode Instruction Cycles
decode1_state, decode2_state, decode3_state,
-- Calculate Effective Address
imm16_state,
indexed_state, index8_state, index16_state, index16_2_state,
pcrel8_state, pcrel16_state, pcrel16_2_state,
indexaddr_state, indexaddr2_state,
postincr1_state, postincr2_state,
indirect_state, indirect2_state, indirect3_state,
extended_state,
-- single ops
single_op_read_state,
single_op_exec_state,
single_op_write_state,
-- Dual op states
dual_op_read8_state, dual_op_read16_state, dual_op_read16_2_state,
dual_op_write8_state, dual_op_write16_state,
--
sync_state, halt_state, error_state,
--
andcc_state, orcc_state,
tfr_state, exg_state, exg1_state,
lea_state,
-- Multiplication
mul_state, mulea_state, muld_state,
mul0_state, mul1_state, mul2_state, mul3_state,
mul4_state, mul5_state, mul6_state, mul7_state,
-- Branches
lbranch_state, sbranch_state,
-- Jumps, Subroutine Calls and Returns
jsr_state, jmp_state,
push_return_hi_state, push_return_lo_state,
pull_return_hi_state, pull_return_lo_state,
-- Interrupt cycles
int_decr_state,
int_entire_state,
int_pcl_state, int_pch_state,
int_upl_state, int_uph_state,
int_iyl_state, int_iyh_state,
int_ixl_state, int_ixh_state,
int_cc_state,
int_acca_state, int_accb_state,
int_dp_state,
int_cwai_state, int_mask_state,
-- Return From Interrupt
rti_cc_state, rti_entire_state,
rti_acca_state, rti_accb_state,
rti_dp_state,
rti_ixl_state, rti_ixh_state,
rti_iyl_state, rti_iyh_state,
rti_upl_state, rti_uph_state,
rti_pcl_state, rti_pch_state,
-- Push Registers using SP
pshs_state,
pshs_pcl_state, pshs_pch_state,
pshs_upl_state, pshs_uph_state,
pshs_iyl_state, pshs_iyh_state,
pshs_ixl_state, pshs_ixh_state,
pshs_dp_state,
pshs_acca_state, pshs_accb_state,
pshs_cc_state,
-- Pull Registers using SP
puls_state,
puls_cc_state,
puls_acca_state, puls_accb_state,
puls_dp_state,
puls_ixl_state, puls_ixh_state,
puls_iyl_state, puls_iyh_state,
puls_upl_state, puls_uph_state,
puls_pcl_state, puls_pch_state,
-- Push Registers using UP
pshu_state,
pshu_pcl_state, pshu_pch_state,
pshu_spl_state, pshu_sph_state,
pshu_iyl_state, pshu_iyh_state,
pshu_ixl_state, pshu_ixh_state,
pshu_dp_state,
pshu_acca_state, pshu_accb_state,
pshu_cc_state,
-- Pull Registers using UP
pulu_state,
pulu_cc_state,
pulu_acca_state, pulu_accb_state,
pulu_dp_state,
pulu_ixl_state, pulu_ixh_state,
pulu_iyl_state, pulu_iyh_state,
pulu_spl_state, pulu_sph_state,
pulu_pcl_state, pulu_pch_state);
type stack_type is array(2 downto 0) of state_type;
type st_type is (idle_st, push_st, pull_st);
type addr_type is (idle_ad, fetch_ad, read_ad, write_ad, pushu_ad, pullu_ad, pushs_ad, pulls_ad, int_hi_ad, int_lo_ad);
type dout_type is (cc_dout, acca_dout, accb_dout, dp_dout,
ix_lo_dout, ix_hi_dout, iy_lo_dout, iy_hi_dout,
up_lo_dout, up_hi_dout, sp_lo_dout, sp_hi_dout,
pc_lo_dout, pc_hi_dout, md_lo_dout, md_hi_dout);
type op_type is (reset_op, fetch_op, latch_op);
type pre_type is (reset_pre, fetch_pre, latch_pre);
type cc_type is (reset_cc, load_cc, pull_cc, latch_cc);
type acca_type is (reset_acca, load_acca, load_hi_acca, pull_acca, latch_acca);
type accb_type is (reset_accb, load_accb, pull_accb, latch_accb);
type dp_type is (reset_dp, load_dp, pull_dp, latch_dp);
type ix_type is (reset_ix, load_ix, pull_lo_ix, pull_hi_ix, latch_ix);
type iy_type is (reset_iy, load_iy, pull_lo_iy, pull_hi_iy, latch_iy);
type sp_type is (reset_sp, latch_sp, load_sp, pull_hi_sp, pull_lo_sp);
type up_type is (reset_up, latch_up, load_up, pull_hi_up, pull_lo_up);
type pc_type is (reset_pc, latch_pc, load_pc, pull_lo_pc, pull_hi_pc, incr_pc);
type md_type is (reset_md, latch_md, load_md, fetch_first_md, fetch_next_md, shiftl_md);
type ea_type is (reset_ea, latch_ea, load_ea, fetch_first_ea, fetch_next_ea);
type iv_type is (reset_iv, latch_iv, nmi_iv, irq_iv, firq_iv, swi_iv, swi2_iv, swi3_iv, resv_iv);
type nmi_type is (reset_nmi, set_nmi, latch_nmi);
type left_type is (cc_left, acca_left, accb_left, dp_left,
ix_left, iy_left, up_left, sp_left,
accd_left, md_left, pc_left, ea_left);
type right_type is (ea_right, zero_right, one_right, two_right,
acca_right, accb_right, accd_right,
md_right, md_sign5_right, md_sign8_right);
type alu_type is (alu_add8, alu_sub8, alu_add16, alu_sub16, alu_adc, alu_sbc,
alu_and, alu_ora, alu_eor,
alu_tst, alu_inc, alu_dec, alu_clr, alu_neg, alu_com,
alu_lsr16, alu_lsl16,
alu_ror8, alu_rol8, alu_mul,
alu_asr8, alu_asl8, alu_lsr8,
alu_andcc, alu_orcc, alu_sex, alu_tfr, alu_abx,
alu_seif, alu_sei, alu_see, alu_cle,
alu_ld8, alu_st8, alu_ld16, alu_st16, alu_lea, alu_nop, alu_daa);
signal op_code : std_logic_vector(7 downto 0);
signal pre_code : std_logic_vector(7 downto 0);
signal acca : std_logic_vector(7 downto 0);
signal accb : std_logic_vector(7 downto 0);
signal cc : std_logic_vector(7 downto 0);
signal cc_out : std_logic_vector(7 downto 0);
signal dp : std_logic_vector(7 downto 0);
signal xreg : std_logic_vector(15 downto 0);
signal yreg : std_logic_vector(15 downto 0);
signal sp : std_logic_vector(15 downto 0);
signal up : std_logic_vector(15 downto 0);
signal ea : std_logic_vector(15 downto 0);
signal pc : std_logic_vector(15 downto 0);
signal md : std_logic_vector(15 downto 0);
signal left : std_logic_vector(15 downto 0);
signal right : std_logic_vector(15 downto 0);
signal out_alu : std_logic_vector(15 downto 0);
signal iv : std_logic_vector(2 downto 0);
signal nmi_req : std_logic;
signal nmi_ack : std_logic;
signal nmi_enable : std_logic;
signal state : state_type;
signal next_state : state_type;
signal saved_state : state_type;
signal return_state : state_type;
signal state_stack : stack_type;
signal st_ctrl : st_type;
signal pc_ctrl : pc_type;
signal ea_ctrl : ea_type;
signal op_ctrl : op_type;
signal pre_ctrl : pre_type;
signal md_ctrl : md_type;
signal acca_ctrl : acca_type;
signal accb_ctrl : accb_type;
signal ix_ctrl : ix_type;
signal iy_ctrl : iy_type;
signal cc_ctrl : cc_type;
signal dp_ctrl : dp_type;
signal sp_ctrl : sp_type;
signal up_ctrl : up_type;
signal iv_ctrl : iv_type;
signal left_ctrl : left_type;
signal right_ctrl : right_type;
signal alu_ctrl : alu_type;
signal addr_ctrl : addr_type;
signal dout_ctrl : dout_type;
signal nmi_ctrl : nmi_type;
------
BEGIN
------
pc_out <= pc when rising_edge(clk); -- register to avoid timing path issues
----------------------------------
--
-- State machine stack
--
----------------------------------
state_stack_proc : process(clk)
begin
if rising_edge(clk) then
if hold = '0' then
case st_ctrl is
when push_st =>
state_stack(0) <= return_state;
state_stack(1) <= state_stack(0);
state_stack(2) <= state_stack(1);
when pull_st =>
state_stack(0) <= state_stack(1);
state_stack(1) <= state_stack(2);
state_stack(2) <= fetch_state;
when others => -- including idle_st
null;
end case;
end if;
end if;
end process;
saved_state <= state_stack(0);
----------------------------------
--
-- Program Counter Control
--
----------------------------------
pc_reg : process(clk)
begin
if rising_edge(clk) then
if hold = '0' then
case pc_ctrl is
when reset_pc =>
pc <= (others=>'0');
when load_pc =>
pc <= out_alu(15 downto 0);
when pull_lo_pc =>
pc(7 downto 0) <= data_in;
when pull_hi_pc =>
pc(15 downto 8) <= data_in;
when incr_pc =>
pc <= pc + 1;
when others => -- including when latch_pc =>
null;
end case;
end if;
end if;
end process;
----------------------------------
--
-- Effective Address Control
--
----------------------------------
ea_reg : process(clk)
begin
if rising_edge(clk) then
if hold = '0' then
case ea_ctrl is
when reset_ea =>
ea <= (others=>'0');
when fetch_first_ea =>
ea(7 downto 0) <= data_in;
ea(15 downto 8) <= dp;
when fetch_next_ea =>
ea(15 downto 8) <= ea(7 downto 0);
ea(7 downto 0) <= data_in;
when load_ea =>
ea <= out_alu(15 downto 0);
when others => -- when latch_ea =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- Accumulator A
--
--------------------------------
acca_reg : process(clk)
begin
if rising_edge(clk) then
if hold = '0' then
case acca_ctrl is
when reset_acca =>
acca <= x"00";
when load_acca =>
acca <= out_alu(7 downto 0);
when load_hi_acca =>
acca <= out_alu(15 downto 8);
when pull_acca =>
acca <= data_in;
when others => -- when latch_acca =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- Accumulator B
--
--------------------------------
accb_reg : process(clk)
begin
if rising_edge(clk) then
if hold = '0' then
case accb_ctrl is
when reset_accb =>
accb <= x"00";
when load_accb =>
accb <= out_alu(7 downto 0);
when pull_accb =>
accb <= data_in;
when others => -- when latch_accb =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- X Index register
--
--------------------------------
ix_reg : process(clk)
begin
if rising_edge(clk) then
if hold = '0' then
case ix_ctrl is
when reset_ix =>
xreg <= (others=>'0');
when load_ix =>
xreg <= out_alu(15 downto 0);
when pull_hi_ix =>
xreg(15 downto 8) <= data_in;
when pull_lo_ix =>
xreg(7 downto 0) <= data_in;
when others => -- when latch_ix =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- Y Index register
--
--------------------------------
iy_reg : process(clk)
begin
if rising_edge(clk) then
if hold = '0' then
case iy_ctrl is
when reset_iy =>
yreg <= (others=>'0');
when load_iy =>
yreg <= out_alu(15 downto 0);
when pull_hi_iy =>
yreg(15 downto 8) <= data_in;
when pull_lo_iy =>
yreg(7 downto 0) <= data_in;
when others => -- when latch_iy =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- S stack pointer
--
--------------------------------
sp_reg : process(clk)
begin
if rising_edge(clk) then
if hold = '0' then
case sp_ctrl is
when reset_sp =>
sp <= (others=>'0');
nmi_enable <= '0';
when load_sp =>
sp <= out_alu(15 downto 0);
nmi_enable <= '1';
when pull_hi_sp =>
sp(15 downto 8) <= data_in;
when pull_lo_sp =>
sp(7 downto 0) <= data_in;
nmi_enable <= '1';
when others => -- when latch_sp =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- U stack pointer
--
--------------------------------
up_reg : process(clk)
begin
if rising_edge(clk) then
if hold = '0' then
case up_ctrl is
when reset_up =>
up <= (others=>'0');
when load_up =>
up <= out_alu(15 downto 0);
when pull_hi_up =>
up(15 downto 8) <= data_in;
when pull_lo_up =>
up(7 downto 0) <= data_in;
when others => -- when latch_up =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- Memory Data
--
--------------------------------
md_reg : process(clk)
begin
if rising_edge(clk) then
if hold = '0' then
case md_ctrl is
when reset_md =>
md <= (others=>'0');
when load_md =>
md <= out_alu(15 downto 0);
when fetch_first_md => -- sign extend md for branches
md(15 downto 8) <= data_in(7) & data_in(7) & data_in(7) & data_in(7) &
data_in(7) & data_in(7) & data_in(7) & data_in(7);
md(7 downto 0) <= data_in;
when fetch_next_md =>
md(15 downto 8) <= md(7 downto 0);
md(7 downto 0) <= data_in;
when shiftl_md =>
md(15 downto 1) <= md(14 downto 0);
md(0) <= '0';
when others => -- when latch_md =>
null;
end case;
end if;
end if;
end process;
----------------------------------
--
-- Condition Codes
--
----------------------------------
cc_reg : process(clk)
begin
if rising_edge(clk) then
if hold = '0' then
case cc_ctrl is
when reset_cc =>
cc <= "11010000"; -- set EBIT, FBIT & IBIT
when load_cc =>
cc <= cc_out;
when pull_cc =>
cc <= data_in;
when others => -- when latch_cc =>
null;
end case;
end if;
end if;
end process;
----------------------------------
--
-- Direct Page register
--
----------------------------------
dp_reg : process(clk)
begin
if rising_edge(clk) then
if hold = '0' then
case dp_ctrl is
when reset_dp =>
dp <= (others=>'0');
when load_dp =>
dp <= out_alu(7 downto 0);
when pull_dp =>
dp <= data_in;
when others => -- when latch_dp =>
null;
end case;
end if;
end if;
end process;
----------------------------------
--
-- interrupt vector
--
----------------------------------
iv_mux : process(clk)
begin
if rising_edge(clk) then
if hold = '0' then
case iv_ctrl is
when reset_iv =>
iv <= RST_VEC;
when nmi_iv =>
iv <= NMI_VEC;
when swi_iv =>
iv <= SWI_VEC;
when irq_iv =>
iv <= IRQ_VEC;
when firq_iv =>
iv <= FIRQ_VEC;
when swi2_iv =>
iv <= SWI2_VEC;
when swi3_iv =>
iv <= SWI3_VEC;
when resv_iv =>
iv <= RESV_VEC;
when others =>
iv <= iv;
end case;
end if;
end if;
end process;
----------------------------------
--
-- op code register
--
----------------------------------
op_reg : process(clk)
begin
if rising_edge(clk) then
if hold = '0' then
case op_ctrl is
when reset_op =>
op_code <= "00010010";
when fetch_op =>
op_code <= data_in;
when others => -- when latch_op =>
null;
end case;
end if;
end if;
end process;
----------------------------------
--
-- pre byte op code register
--
----------------------------------
pre_reg : process(clk)
begin
if rising_edge(clk) then
if hold = '0' then
case pre_ctrl is
when reset_pre =>
pre_code <= x"00";
when fetch_pre =>
pre_code <= data_in;
when others => -- when latch_pre =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- state machine
--
--------------------------------
change_state : process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
state <= reset_state;
else
if hold = '0' then
state <= next_state;
end if;
end if;
end if;
end process;
-- output
------------------------------------
--
-- Nmi register
--
------------------------------------
nmi_reg : process(clk)
begin
if rising_edge(clk) then
if hold = '0' then
case nmi_ctrl is
when set_nmi =>
nmi_ack <= '1';
when reset_nmi =>
nmi_ack <= '0';
when others => -- when latch_nmi =>
null;
end case;
end if;
end if;
end process;
------------------------------------
--
-- Detect Edge of NMI interrupt
--
------------------------------------
nmi_handler : process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
nmi_req <= '0';
else
if (nmi = '1') and (nmi_ack = '0') and (nmi_enable = '1') then
nmi_req <= '1';
else
if (nmi = '0') and (nmi_ack = '1') then
nmi_req <= '0';
end if;
end if;
end if;
end if;
end process;
----------------------------------
--
-- Address output multiplexer
--
----------------------------------
addr_mux : process(addr_ctrl, pc, ea, up, sp, iv)
begin
case addr_ctrl is
when idle_ad =>
address <= "1111111111111111";
vma <= '0';
rw <= '1';
when fetch_ad =>
address <= pc;
vma <= '1';
rw <= '1';
when read_ad =>
address <= ea;
vma <= '1';
rw <= '1';
when write_ad =>
address <= ea;
vma <= '1';
rw <= '0';
when pushs_ad =>
address <= sp;
vma <= '1';
rw <= '0';
when pulls_ad =>
address <= sp;
vma <= '1';
rw <= '1';
when pushu_ad =>
address <= up;
vma <= '1';
rw <= '0';
when pullu_ad =>
address <= up;
vma <= '1';
rw <= '1';
when int_hi_ad =>
address <= "111111111111" & iv & "0";
vma <= '1';
rw <= '1';
when int_lo_ad =>
address <= "111111111111" & iv & "1";
vma <= '1';
rw <= '1';
when others =>
address <= "1111111111111111";
vma <= '0';
rw <= '1';
end case;
end process;
--------------------------------
--
-- Data Bus output
--
--------------------------------
dout_mux : process(dout_ctrl, md, acca, accb, dp, xreg, yreg, sp, up, pc, cc)
begin
case dout_ctrl is
when md_hi_dout => -- alu output
data_out <= md(15 downto 8);
when md_lo_dout => -- alu output
data_out <= md(7 downto 0);
when acca_dout => -- accumulator a
data_out <= acca;
when accb_dout => -- accumulator b
data_out <= accb;
when ix_lo_dout => -- index reg
data_out <= xreg(7 downto 0);
when ix_hi_dout => -- index reg
data_out <= xreg(15 downto 8);
when iy_lo_dout => -- index reg
data_out <= yreg(7 downto 0);
when iy_hi_dout => -- index reg
data_out <= yreg(15 downto 8);
when sp_lo_dout => -- s stack pointer
data_out <= sp(7 downto 0);
when sp_hi_dout => -- s stack pointer
data_out <= sp(15 downto 8);
when up_lo_dout => -- u stack pointer
data_out <= up(7 downto 0);
when up_hi_dout => -- u stack pointer
data_out <= up(15 downto 8);
when cc_dout => -- condition code register
data_out <= cc;
when dp_dout => -- direct page register
data_out <= dp;
when pc_lo_dout => -- low order pc
data_out <= pc(7 downto 0);
when pc_hi_dout => -- high order pc
data_out <= pc(15 downto 8);
when others =>
data_out <= "00000000";
end case;
end process;
----------------------------------
--
-- Left Mux
--
----------------------------------
left_mux : process(left_ctrl, acca, accb, cc, dp, xreg, yreg, up, sp, pc, ea, md)
begin
case left_ctrl is
when cc_left =>
left(15 downto 8) <= "00000000";
left(7 downto 0) <= cc;
when acca_left =>
left(15 downto 8) <= "00000000";
left(7 downto 0) <= acca;
when accb_left =>
left(15 downto 8) <= "00000000";
left(7 downto 0) <= accb;
when dp_left =>
left(15 downto 8) <= "00000000";
left(7 downto 0) <= dp;
when accd_left =>
left(15 downto 8) <= acca;
left(7 downto 0) <= accb;
when md_left =>
left <= md;
when ix_left =>
left <= xreg;
when iy_left =>
left <= yreg;
when sp_left =>
left <= sp;
when up_left =>
left <= up;
when pc_left =>
left <= pc;
when others => -- when ea_left =>
left <= ea;
end case;
end process;
----------------------------------
--
-- Right Mux
--
----------------------------------
right_mux : process(right_ctrl, md, acca, accb, ea)
begin
case right_ctrl is
when ea_right =>
right <= ea;
when zero_right =>
right <= x"0000"; -- "0000000000000000";
when one_right =>
right <= x"0001";
when two_right =>
right <= x"0002";
when acca_right =>
if acca(7) = '0' then
right <= x"00" & acca(7 downto 0);
else
right <= x"FF" & acca(7 downto 0);
end if;
when accb_right =>
if accb(7) = '0' then
right <= x"00" & accb(7 downto 0);
else
right <= x"FF" & accb(7 downto 0);
end if;
when accd_right =>
right <= acca & accb;
when md_sign5_right =>
if md(4) = '0' then
right <= "00000000000" & md(4 downto 0);
else
right <= "11111111111" & md(4 downto 0);
end if;
when md_sign8_right =>
if md(7) = '0' then
right <= x"00" & md(7 downto 0);
else
right <= x"FF" & md(7 downto 0);
end if;
when others => -- when md_right =>
right <= md;
end case;
end process;
----------------------------------
--
-- Arithmetic Logic Unit
--
----------------------------------
ALU: process(alu_ctrl, cc, left, right, out_alu, cc_out)
variable valid_lo, valid_hi : boolean;
variable carry_in : std_logic;
variable daa_reg : std_logic_vector(7 downto 0);
begin
case alu_ctrl is
when alu_adc | alu_sbc | alu_rol8 | alu_ror8 =>
carry_in := cc(CBIT);
when alu_asr8 =>
carry_in := left(7);
when others =>
carry_in := '0';
end case;
valid_lo := left(3 downto 0) <= 9;
valid_hi := left(7 downto 4) <= 9;
if (cc(CBIT) = '0') then
if(cc(HBIT) = '1') then
if valid_hi then
daa_reg := "00000110";
else
daa_reg := "01100110";
end if;
else
if valid_lo then
if valid_hi then
daa_reg := "00000000";
else
daa_reg := "01100000";
end if;
else
if(left(7 downto 4) <= 8) then
daa_reg := "00000110";
else
daa_reg := "01100110";
end if;
end if;
end if;
else
if (cc(HBIT) = '1')then
daa_reg := "01100110";
else
if valid_lo then
daa_reg := "01100000";
else
daa_reg := "01100110";
end if;
end if;
end if;
case alu_ctrl is
when alu_add8 | alu_inc |
alu_add16 | alu_adc | alu_mul =>
out_alu <= left + right + ("000000000000000" & carry_in);
when alu_sub8 | alu_dec |
alu_sub16 | alu_sbc =>
out_alu <= left - right - ("000000000000000" & carry_in);
when alu_abx =>
out_alu <= left + ("00000000" & right(7 downto 0));
when alu_and =>
out_alu <= left and right; -- and/bit
when alu_ora =>
out_alu <= left or right; -- or
when alu_eor =>
out_alu <= left xor right; -- eor/xor
when alu_lsl16 | alu_asl8 | alu_rol8 =>
out_alu <= left(14 downto 0) & carry_in; -- rol8/asl8/lsl16
when alu_lsr16 =>
out_alu <= carry_in & left(15 downto 1); -- lsr16
when alu_lsr8 | alu_asr8 | alu_ror8 =>
out_alu <= "00000000" & carry_in & left(7 downto 1); -- ror8/asr8/lsr8
when alu_neg =>
out_alu <= right - left; -- neg (right=0)
when alu_com =>
out_alu <= not left;
when alu_clr | alu_ld8 | alu_ld16 | alu_lea =>
out_alu <= right; -- clr, ld
when alu_st8 | alu_st16 | alu_andcc | alu_orcc | alu_tfr =>
out_alu <= left;
when alu_daa =>
out_alu <= left + ("00000000" & daa_reg);
when alu_sex =>
if left(7) = '0' then
out_alu <= "00000000" & left(7 downto 0);
else
out_alu <= "11111111" & left(7 downto 0);
end if;
when others =>
out_alu <= left; -- nop
end case;
--
-- carry bit
--
case alu_ctrl is
when alu_add8 | alu_adc =>
cc_out(CBIT) <= (left(7) and right(7)) or
(left(7) and not out_alu(7)) or
(right(7) and not out_alu(7));
when alu_sub8 | alu_sbc =>
cc_out(CBIT) <= ((not left(7)) and right(7)) or
((not left(7)) and out_alu(7)) or
(right(7) and out_alu(7));
when alu_add16 =>
cc_out(CBIT) <= (left(15) and right(15)) or
(left(15) and not out_alu(15)) or
(right(15) and not out_alu(15));
when alu_sub16 =>
cc_out(CBIT) <= ((not left(15)) and right(15)) or
((not left(15)) and out_alu(15)) or
(right(15) and out_alu(15));
when alu_ror8 | alu_lsr16 | alu_lsr8 | alu_asr8 =>
cc_out(CBIT) <= left(0);
when alu_rol8 | alu_asl8 =>
cc_out(CBIT) <= left(7);
when alu_lsl16 =>
cc_out(CBIT) <= left(15);
when alu_com =>
cc_out(CBIT) <= '1';
when alu_neg | alu_clr =>
cc_out(CBIT) <= out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0);
when alu_mul =>
cc_out(CBIT) <= out_alu(7);
when alu_daa =>
if (daa_reg(7 downto 4) = "0110") then
cc_out(CBIT) <= '1';
else
cc_out(CBIT) <= '0';
end if;
when alu_andcc =>
cc_out(CBIT) <= left(CBIT) and cc(CBIT);
when alu_orcc =>
cc_out(CBIT) <= left(CBIT) or cc(CBIT);
when alu_tfr =>
cc_out(CBIT) <= left(CBIT);
when others =>
cc_out(CBIT) <= cc(CBIT);
end case;
--
-- Zero flag
--
case alu_ctrl is
when alu_add8 | alu_sub8 |
alu_adc | alu_sbc |
alu_and | alu_ora | alu_eor |
alu_inc | alu_dec |
alu_neg | alu_com | alu_clr |
alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
alu_ld8 | alu_st8 | alu_sex | alu_daa =>
cc_out(ZBIT) <= not(out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0));
when alu_add16 | alu_sub16 | alu_mul |
alu_lsl16 | alu_lsr16 |
alu_ld16 | alu_st16 | alu_lea =>
cc_out(ZBIT) <= not(out_alu(15) or out_alu(14) or out_alu(13) or out_alu(12) or
out_alu(11) or out_alu(10) or out_alu(9) or out_alu(8) or
out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0));
when alu_andcc =>
cc_out(ZBIT) <= left(ZBIT) and cc(ZBIT);
when alu_orcc =>
cc_out(ZBIT) <= left(ZBIT) or cc(ZBIT);
when alu_tfr =>
cc_out(ZBIT) <= left(ZBIT);
when others =>
cc_out(ZBIT) <= cc(ZBIT);
end case;
--
-- negative flag
--
case alu_ctrl is
when alu_add8 | alu_sub8 |
alu_adc | alu_sbc |
alu_and | alu_ora | alu_eor |
alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
alu_inc | alu_dec | alu_neg | alu_com | alu_clr |
alu_ld8 | alu_st8 | alu_sex | alu_daa =>
cc_out(NBIT) <= out_alu(7);
when alu_add16 | alu_sub16 |
alu_lsl16 | alu_lsr16 |
alu_ld16 | alu_st16 =>
cc_out(NBIT) <= out_alu(15);
when alu_andcc =>
cc_out(NBIT) <= left(NBIT) and cc(NBIT);
when alu_orcc =>
cc_out(NBIT) <= left(NBIT) or cc(NBIT);
when alu_tfr =>
cc_out(NBIT) <= left(NBIT);
when others =>
cc_out(NBIT) <= cc(NBIT);
end case;
--
-- Interrupt mask flag
--
case alu_ctrl is
when alu_andcc =>
cc_out(IBIT) <= left(IBIT) and cc(IBIT);
when alu_orcc =>
cc_out(IBIT) <= left(IBIT) or cc(IBIT);
when alu_tfr =>
cc_out(IBIT) <= left(IBIT);
when alu_seif | alu_sei =>
cc_out(IBIT) <= '1';
when others =>
cc_out(IBIT) <= cc(IBIT); -- interrupt mask
end case;
--
-- Half Carry flag
--
case alu_ctrl is
when alu_add8 | alu_adc =>
cc_out(HBIT) <= (left(3) and right(3)) or
(right(3) and not out_alu(3)) or
(left(3) and not out_alu(3));
when alu_andcc =>
cc_out(HBIT) <= left(HBIT) and cc(HBIT);
when alu_orcc =>
cc_out(HBIT) <= left(HBIT) or cc(HBIT);
when alu_tfr =>
cc_out(HBIT) <= left(HBIT);
when others =>
cc_out(HBIT) <= cc(HBIT);
end case;
--
-- Overflow flag
--
case alu_ctrl is
when alu_add8 | alu_adc =>
cc_out(VBIT) <= (left(7) and right(7) and (not out_alu(7))) or
((not left(7)) and (not right(7)) and out_alu(7));
when alu_sub8 | alu_sbc =>
cc_out(VBIT) <= (left(7) and (not right(7)) and (not out_alu(7))) or
((not left(7)) and right(7) and out_alu(7));
when alu_add16 =>
cc_out(VBIT) <= (left(15) and right(15) and (not out_alu(15))) or
((not left(15)) and (not right(15)) and out_alu(15));
when alu_sub16 =>
cc_out(VBIT) <= (left(15) and (not right(15)) and (not out_alu(15))) or
((not left(15)) and right(15) and out_alu(15));
when alu_inc =>
cc_out(VBIT) <= ((not left(7)) and left(6) and left(5) and left(4) and
left(3) and left(2) and left(1) and left(0));
when alu_dec | alu_neg =>
cc_out(VBIT) <= (left(7) and (not left(6)) and (not left(5)) and (not left(4)) and
(not left(3)) and (not left(2)) and (not left(1)) and (not left(0)));
-- 6809 Programming reference manual says
-- V not affected by ASR, LSR and ROR
-- This is different to the 6800
-- John Kent 6th June 2006
-- when alu_asr8 =>
-- cc_out(VBIT) <= left(0) xor left(7);
-- when alu_lsr8 | alu_lsr16 =>
-- cc_out(VBIT) <= left(0);
-- when alu_ror8 =>
-- cc_out(VBIT) <= left(0) xor cc(CBIT);
when alu_lsl16 =>
cc_out(VBIT) <= left(15) xor left(14);
when alu_rol8 | alu_asl8 =>
cc_out(VBIT) <= left(7) xor left(6);
--
-- 11th July 2006 - John Kent
-- What DAA does with V is anyones guess
-- It is undefined in the 6809 programming manual
--
when alu_daa =>
cc_out(VBIT) <= left(7) xor out_alu(7) xor cc(CBIT);
-- CLR resets V Bit
-- John Kent 6th June 2006
when alu_and | alu_ora | alu_eor | alu_com | alu_clr |
alu_st8 | alu_st16 | alu_ld8 | alu_ld16 | alu_sex =>
cc_out(VBIT) <= '0';
when alu_andcc =>
cc_out(VBIT) <= left(VBIT) and cc(VBIT);
when alu_orcc =>
cc_out(VBIT) <= left(VBIT) or cc(VBIT);
when alu_tfr =>
cc_out(VBIT) <= left(VBIT);
when others =>
cc_out(VBIT) <= cc(VBIT);
end case;
case alu_ctrl is
when alu_andcc =>
cc_out(FBIT) <= left(FBIT) and cc(FBIT);
when alu_orcc =>
cc_out(FBIT) <= left(FBIT) or cc(FBIT);
when alu_tfr =>
cc_out(FBIT) <= left(FBIT);
when alu_seif =>
cc_out(FBIT) <= '1';
when others =>
cc_out(FBIT) <= cc(FBIT);
end case;
case alu_ctrl is
when alu_andcc =>
cc_out(EBIT) <= left(EBIT) and cc(EBIT);
when alu_orcc =>
cc_out(EBIT) <= left(EBIT) or cc(EBIT);
when alu_tfr =>
cc_out(EBIT) <= left(EBIT);
when alu_see =>
cc_out(EBIT) <= '1';
when alu_cle =>
cc_out(EBIT) <= '0';
when others =>
cc_out(EBIT) <= cc(EBIT);
end case;
end process;
------------------------------------
--
-- state sequencer
--
------------------------------------
process(state, saved_state,
op_code, pre_code,
cc, ea, md, iv,
irq, firq, nmi_req, nmi_ack, halt)
variable cond_true : boolean; -- variable used to evaluate coditional branches
begin
case state is
when reset_state => -- released from reset
-- reset the registers
op_ctrl <= reset_op;
pre_ctrl <= reset_pre;
acca_ctrl <= reset_acca;
accb_ctrl <= reset_accb;
ix_ctrl <= reset_ix;
iy_ctrl <= reset_iy;
sp_ctrl <= reset_sp;
up_ctrl <= reset_up;
pc_ctrl <= reset_pc;
ea_ctrl <= reset_ea;
md_ctrl <= reset_md;
iv_ctrl <= reset_iv;
nmi_ctrl <= reset_nmi;
-- idle the ALU
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= reset_cc;
dp_ctrl <= reset_dp;
-- idle the bus
dout_ctrl <= md_lo_dout;
addr_ctrl <= idle_ad;
st_ctrl <= idle_st;
return_state <= vect_hi_state;
next_state <= vect_hi_state;
--
-- Jump via interrupt vector
-- iv holds interrupt type
-- fetch PC hi from vector location
--
when vect_hi_state =>
-- default the registers
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
up_ctrl <= latch_up;
md_ctrl <= latch_md;
ea_ctrl <= latch_ea;
iv_ctrl <= latch_iv;
-- idle the ALU
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
-- fetch pc low interrupt vector
pc_ctrl <= pull_hi_pc;
addr_ctrl <= int_hi_ad;
dout_ctrl <= pc_hi_dout;
st_ctrl <= idle_st;
return_state <= vect_lo_state;
next_state <= vect_lo_state;
--
-- jump via interrupt vector
-- iv holds vector type
-- fetch PC lo from vector location
--
when vect_lo_state =>
-- default the registers
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
up_ctrl <= latch_up;
md_ctrl <= latch_md;
ea_ctrl <= latch_ea;
iv_ctrl <= latch_iv;
-- idle the ALU
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
-- fetch the vector low byte
pc_ctrl <= pull_lo_pc;
addr_ctrl <= int_lo_ad;
dout_ctrl <= pc_lo_dout;
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
--
-- Here to fetch an instruction
-- PC points to opcode
-- Should service interrupt requests at this point
-- either from the timer
-- or from the external input.
--
when fetch_state =>
-- fetch the op code
op_ctrl <= fetch_op;
pre_ctrl <= fetch_pre;
ea_ctrl <= reset_ea;
md_ctrl <= latch_md;
-- Fetch op code
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
dp_ctrl <= latch_dp;
--
case op_code(7 downto 6) is
when "10" => -- acca
case op_code(3 downto 0) is
when "0000" => -- suba
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "0001" => -- cmpa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "0010" => -- sbca
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sbc;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "0011" =>
case pre_code is
when "00010000" => -- page 2 -- cmpd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "00010001" => -- page 3 -- cmpu
left_ctrl <= up_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when others => -- page 1 -- subd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
end case;
when "0100" => -- anda
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "0101" => -- bita
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "0110" => -- ldaa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "0111" => -- staa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "1000" => -- eora
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_eor;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "1001" => -- adca
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_adc;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "1010" => -- oraa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ora;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "1011" => -- adda
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "1100" =>
case pre_code is
when "00010000" => -- page 2 -- cmpy
left_ctrl <= iy_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "00010001" => -- page 3 -- cmps
left_ctrl <= sp_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when others => -- page 1 -- cmpx
left_ctrl <= ix_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
end case;
when "1101" => -- bsr / jsr
left_ctrl <= pc_left;
right_ctrl <= md_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "1110" => -- ldx
case pre_code is
when "00010000" => -- page 2 -- ldy
left_ctrl <= iy_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= load_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when others => -- page 1 -- ldx
left_ctrl <= ix_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= load_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
end case;
when "1111" => -- stx
case pre_code is
when "00010000" => -- page 2 -- sty
left_ctrl <= iy_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when others => -- page 1 -- stx
left_ctrl <= ix_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
end case;
when others =>
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
end case;
when "11" => -- accb dual op
case op_code(3 downto 0) is
when "0000" => -- subb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "0001" => -- cmpb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "0010" => -- sbcb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sbc;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "0011" => -- addd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "0100" => -- andb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "0101" => -- bitb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "0110" => -- ldab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "0111" => -- stab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "1000" => -- eorb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_eor;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "1001" => -- adcb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_adc;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "1010" => -- orab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ora;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "1011" => -- addb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "1100" => -- ldd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "1101" => -- std
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "1110" => -- ldu
case pre_code is
when "00010000" => -- page 2 -- lds
left_ctrl <= sp_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= load_sp;
when others => -- page 1 -- ldu
left_ctrl <= up_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= load_up;
sp_ctrl <= latch_sp;
end case;
when "1111" =>
case pre_code is
when "00010000" => -- page 2 -- sts
left_ctrl <= sp_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when others => -- page 1 -- stu
left_ctrl <= up_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
end case;
when others =>
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
end case;
when others =>
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
end case;
if halt = '1' then
iv_ctrl <= reset_iv;
pc_ctrl <= latch_pc;
nmi_ctrl <= latch_nmi;
st_ctrl <= push_st;
return_state <= fetch_state;
next_state <= halt_state;
-- service non maskable interrupts
elsif (nmi_req = '1') and (nmi_ack = '0') then
iv_ctrl <= nmi_iv;
pc_ctrl <= latch_pc;
nmi_ctrl <= set_nmi;
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= int_decr_state;
-- service maskable interrupts
else
--
-- nmi request is not cleared until nmi input goes low
--
if(nmi_req = '0') and (nmi_ack = '1') then
nmi_ctrl <= reset_nmi;
else
nmi_ctrl <= latch_nmi;
end if;
--
-- IRQ is level sensitive
--
if (irq = '1') and (cc(IBIT) = '0') then
iv_ctrl <= irq_iv;
pc_ctrl <= latch_pc;
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= int_decr_state;
elsif (firq = '1') and (cc(FBIT) = '0') then
iv_ctrl <= firq_iv;
pc_ctrl <= latch_pc;
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= int_decr_state;
else
-- Advance the PC to fetch next instruction byte
iv_ctrl <= reset_iv; -- default to reset
pc_ctrl <= incr_pc;
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= decode1_state;
end if;
end if;
--
-- Here to decode instruction
-- and fetch next byte of intruction
-- whether it be necessary or not
--
when decode1_state =>
pre_ctrl <= latch_pre;
-- fetch first byte of address or immediate data
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
nmi_ctrl <= latch_nmi;
dp_ctrl <= latch_dp;
case op_code(7 downto 4) is
--
-- direct single op (2 bytes)
-- 6809 => 6 cycles
-- cpu09 => 5 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 ea_hi=dp / ea_lo=(pc) / pc=pc+1
-- 3 md_lo=(ea) / pc=pc
-- 4 alu_left=md / md=alu_out / pc=pc
-- 5 (ea)=md_lo / pc=pc
--
-- Exception is JMP
-- 6809 => 3 cycles
-- cpu09 => 3 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 ea_hi=dp / ea_lo=(pc) / pc=pc+1
-- 3 pc=ea
--
when "0000" =>
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
up_ctrl <= latch_up;
iv_ctrl <= latch_iv;
-- idle ALU
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
-- advance the PC
pc_ctrl <= incr_pc;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
case op_code(3 downto 0) is
when "1110" => -- jmp
next_state <= jmp_state;
when "1111" => -- clr
next_state <= single_op_exec_state;
when others =>
next_state <= single_op_read_state;
end case;
-- acca / accb inherent instructions
when "0001" =>
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
iv_ctrl <= latch_iv;
case op_code(3 downto 0) is
--
-- Page2 pre byte
-- pre=(pc) / pc=pc+1
-- op=(pc) / pc=pc+1
--
when "0000" => -- page2
op_ctrl <= fetch_op;
acca_ctrl <= latch_acca;
--
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
-- advance pc
pc_ctrl <= incr_pc;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= decode2_state;
--
-- Page3 pre byte
-- pre=(pc) / pc=pc+1
-- op=(pc) / pc=pc+1
--
when "0001" => -- page3
op_ctrl <= fetch_op;
acca_ctrl <= latch_acca;
-- idle ALU
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
-- advance pc
pc_ctrl <= incr_pc;
-- Next state
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= decode3_state;
--
-- nop - No operation ( 1 byte )
-- 6809 => 2 cycles
-- cpu09 => 2 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 decode
--
when "0010" => -- nop
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
--
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
--
pc_ctrl <= latch_pc;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
--
-- sync - halt execution until an interrupt is received
-- interrupt may be NMI, IRQ or FIRQ
-- program execution continues if the
-- interrupt is asserted for 3 clock cycles
-- note that registers are not pushed onto the stack
-- CPU09 => Interrupts need only be asserted for one clock cycle
--
when "0011" => -- sync
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
--
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
--
pc_ctrl <= latch_pc;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= sync_state;
--
-- lbra -- long branch (3 bytes)
-- 6809 => 5 cycles
-- cpu09 => 4 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1
-- 3 md_hi=md_lo / md_lo=(pc) / pc=pc+1
-- 4 pc=pc+md
--
when "0110" =>
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
-- idle ALU
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
-- increment the pc
pc_ctrl <= incr_pc;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= lbranch_state;
--
-- lbsr - long branch to subroutine (3 bytes)
-- 6809 => 9 cycles
-- cpu09 => 6 cycles
-- 1 op=(pc) /pc=pc+1
-- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 / sp=sp-1
-- 3 md_hi=md_lo / md_lo=(pc) / pc=pc+1
-- 4 (sp)= pc_lo / sp=sp-1 / pc=pc
-- 5 (sp)=pc_hi / pc=pc
-- 6 pc=pc+md
--
when "0111" =>
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
-- pre decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- increment the pc
pc_ctrl <= incr_pc;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= lbranch_state;
when "1001" => -- daa
op_ctrl <= latch_op;
--
left_ctrl <= acca_left;
right_ctrl <= accb_right;
alu_ctrl <= alu_daa;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
sp_ctrl <= latch_sp;
-- idle pc
pc_ctrl <= latch_pc;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
when "1010" => -- orcc
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
-- idle ALU
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
-- increment the pc
pc_ctrl <= incr_pc;
-- next state
st_ctrl <= push_st;
return_state <= fetch_state;
next_state <= orcc_state;
when "1100" => -- andcc
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
-- idle ALU
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
-- increment the pc
pc_ctrl <= incr_pc;
--
st_ctrl <= push_st;
return_state <= fetch_state;
next_state <= andcc_state;
when "1101" => -- sex
op_ctrl <= latch_op;
-- have sex
left_ctrl <= accb_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_sex;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
sp_ctrl <= latch_sp;
-- idle PC
pc_ctrl <= latch_pc;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
when "1110" => -- exg
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
-- idle ALU
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
-- increment the pc
pc_ctrl <= incr_pc;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= exg_state;
when "1111" => -- tfr
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
-- idle ALU
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
-- increment the pc
pc_ctrl <= incr_pc;
-- call transfer as a subroutine
st_ctrl <= push_st;
return_state <= fetch_state;
next_state <= tfr_state;
when others =>
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
-- idle ALU
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
-- increment the pc
pc_ctrl <= incr_pc;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
end case;
--
-- Short branch conditional
-- 6809 => always 3 cycles
-- cpu09 => always = 3 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 / test cc
-- 3 if cc tru pc=pc+md else pc=pc
--
when "0010" => -- branch conditional
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
up_ctrl <= latch_up;
iv_ctrl <= latch_iv;
-- idle ALU
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
-- increment the pc
pc_ctrl <= incr_pc;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= sbranch_state;
--
-- Single byte stack operators
-- Do not advance PC
--
when "0011" =>
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
--
-- lea - load effective address (2+ bytes)
-- 6809 => 4 cycles + addressing mode
-- cpu09 => 4 cycles + addressing mode
-- 1 op=(pc) / pc=pc+1
-- 2 md_lo=(pc) / pc=pc+1
-- 3 calculate ea
-- 4 ix/iy/sp/up = ea
--
case op_code(3 downto 0) is
when "0000" | -- leax
"0001" | -- leay
"0010" | -- leas
"0011" => -- leau
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
-- advance PC
pc_ctrl <= incr_pc;
--
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
up_ctrl <= latch_up;
iv_ctrl <= latch_iv;
--
st_ctrl <= push_st;
return_state <= lea_state;
next_state <= indexed_state;
--
-- pshs - push registers onto sp stack
-- 6809 => 5 cycles + registers
-- cpu09 => 3 cycles + registers
-- 1 op=(pc) / pc=pc+1
-- 2 ea_lo=(pc) / pc=pc+1
-- 3 if ea(7 downto 0) != "00000000" then sp=sp-1
-- 4 if ea(7) = 1 (sp)=pcl, sp=sp-1
-- 5 if ea(7) = 1 (sp)=pch
-- if ea(6 downto 0) != "0000000" then sp=sp-1
-- 6 if ea(6) = 1 (sp)=upl, sp=sp-1
-- 7 if ea(6) = 1 (sp)=uph
-- if ea(5 downto 0) != "000000" then sp=sp-1
-- 8 if ea(5) = 1 (sp)=iyl, sp=sp-1
-- 9 if ea(5) = 1 (sp)=iyh
-- if ea(4 downto 0) != "00000" then sp=sp-1
-- 10 if ea(4) = 1 (sp)=ixl, sp=sp-1
-- 11 if ea(4) = 1 (sp)=ixh
-- if ea(3 downto 0) != "0000" then sp=sp-1
-- 12 if ea(3) = 1 (sp)=dp
-- if ea(2 downto 0) != "000" then sp=sp-1
-- 13 if ea(2) = 1 (sp)=accb
-- if ea(1 downto 0) != "00" then sp=sp-1
-- 14 if ea(1) = 1 (sp)=acca
-- if ea(0 downto 0) != "0" then sp=sp-1
-- 15 if ea(0) = 1 (sp)=cc
--
when "0100" => -- pshs
--
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- advance PC
pc_ctrl <= incr_pc;
--
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
up_ctrl <= latch_up;
iv_ctrl <= latch_iv;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= pshs_state;
--
-- puls - pull registers of sp stack
-- 6809 => 5 cycles + registers
-- cpu09 => 3 cycles + registers
--
when "0101" => -- puls
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
-- advance PC
pc_ctrl <= incr_pc;
--
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
up_ctrl <= latch_up;
iv_ctrl <= latch_iv;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= puls_state;
--
-- pshu - push registers onto up stack
-- 6809 => 5 cycles + registers
-- cpu09 => 3 cycles + registers
--
when "0110" => -- pshu
-- idle UP
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- advance PC
pc_ctrl <= incr_pc;
--
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
up_ctrl <= latch_up;
iv_ctrl <= latch_iv;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= pshu_state;
--
-- pulu - pull registers of up stack
-- 6809 => 5 cycles + registers
-- cpu09 => 3 cycles + registers
--
when "0111" => -- pulu
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
-- advance PC
pc_ctrl <= incr_pc;
--
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
up_ctrl <= latch_up;
iv_ctrl <= latch_iv;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= pulu_state;
--
-- rts - return from subroutine
-- 6809 => 5 cycles
-- cpu09 => 4 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 decode op
-- 3 pc_hi = (sp) / sp=sp+1
-- 4 pc_lo = (sp) / sp=sp+1
--
when "1001" =>
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- idle PC
pc_ctrl <= latch_pc;
--
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
up_ctrl <= latch_up;
iv_ctrl <= latch_iv;
--
st_ctrl <= push_st;
return_state <= fetch_state;
next_state <= pull_return_hi_state;
--
-- add accb to index register
-- *** Note: this is an unsigned addition.
-- does not affect any condition codes
-- 6809 => 3 cycles
-- cpu09 => 2 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 alu_left=ix / alu_right=accb / ix=alu_out / pc=pc
--
when "1010" => -- abx
left_ctrl <= ix_left;
right_ctrl <= accb_right;
alu_ctrl <= alu_abx;
cc_ctrl <= latch_cc;
ix_ctrl <= load_ix;
--
pc_ctrl <= latch_pc;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
up_ctrl <= latch_up;
iv_ctrl <= latch_iv;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
when "1011" => -- rti
-- idle ALU
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
--
pc_ctrl <= latch_pc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
up_ctrl <= latch_up;
iv_ctrl <= latch_iv;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= rti_cc_state;
when "1100" => -- cwai #$<cc_mask>
-- pre decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
--
pc_ctrl <= incr_pc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
iv_ctrl <= latch_iv;
--
st_ctrl <= push_st;
return_state <= int_entire_state; -- set entire flag
next_state <= andcc_state;
when "1101" => -- mul
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
--
pc_ctrl <= latch_pc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
up_ctrl <= latch_up;
iv_ctrl <= latch_iv;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= mul_state;
when "1111" => -- swi
-- predecrement SP
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
--
pc_ctrl <= latch_pc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
iv_ctrl <= swi_iv;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= int_entire_state;
when others =>
-- idle ALU
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- idle PC
pc_ctrl <= latch_pc;
--
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
up_ctrl <= latch_up;
iv_ctrl <= latch_iv;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
end case;
--
-- Accumulator A Single operand
-- source = acca, dest = acca
-- Do not advance PC
-- Typically 2 cycles 1 bytes
-- 1 opcode fetch
-- 2 post byte fetch / instruction decode
-- Note that there is no post byte
-- so do not advance PC in decode cycle
-- Re-run opcode fetch cycle after decode
--
when "0100" => -- acca single op
op_ctrl <= latch_op;
accb_ctrl <= latch_accb;
pc_ctrl <= latch_pc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
left_ctrl <= acca_left;
case op_code(3 downto 0) is
when "0000" => -- neg
right_ctrl <= zero_right;
alu_ctrl <= alu_neg;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0011" => -- com
right_ctrl <= zero_right;
alu_ctrl <= alu_com;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0100" => -- lsr
right_ctrl <= zero_right;
alu_ctrl <= alu_lsr8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0110" => -- ror
right_ctrl <= zero_right;
alu_ctrl <= alu_ror8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0111" => -- asr
right_ctrl <= zero_right;
alu_ctrl <= alu_asr8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1000" => -- asl
right_ctrl <= zero_right;
alu_ctrl <= alu_asl8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1001" => -- rol
right_ctrl <= zero_right;
alu_ctrl <= alu_rol8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1010" => -- dec
right_ctrl <= one_right;
alu_ctrl <= alu_dec;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1011" => -- undefined
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
acca_ctrl <= latch_acca;
cc_ctrl <= latch_cc;
when "1100" => -- inc
right_ctrl <= one_right;
alu_ctrl <= alu_inc;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1101" => -- tst
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
acca_ctrl <= latch_acca;
cc_ctrl <= load_cc;
when "1110" => -- jmp (not defined)
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
acca_ctrl <= latch_acca;
cc_ctrl <= latch_cc;
when "1111" => -- clr
right_ctrl <= zero_right;
alu_ctrl <= alu_clr;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when others =>
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
acca_ctrl <= latch_acca;
cc_ctrl <= latch_cc;
end case;
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
--
-- Single Operand accb
-- source = accb, dest = accb
-- Typically 2 cycles 1 bytes
-- 1 opcode fetch
-- 2 post byte fetch / instruction decode
-- Note that there is no post byte
-- so do not advance PC in decode cycle
-- Re-run opcode fetch cycle after decode
--
when "0101" =>
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
pc_ctrl <= latch_pc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
left_ctrl <= accb_left;
case op_code(3 downto 0) is
when "0000" => -- neg
right_ctrl <= zero_right;
alu_ctrl <= alu_neg;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0011" => -- com
right_ctrl <= zero_right;
alu_ctrl <= alu_com;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0100" => -- lsr
right_ctrl <= zero_right;
alu_ctrl <= alu_lsr8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0110" => -- ror
right_ctrl <= zero_right;
alu_ctrl <= alu_ror8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0111" => -- asr
right_ctrl <= zero_right;
alu_ctrl <= alu_asr8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1000" => -- asl
right_ctrl <= zero_right;
alu_ctrl <= alu_asl8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1001" => -- rol
right_ctrl <= zero_right;
alu_ctrl <= alu_rol8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1010" => -- dec
right_ctrl <= one_right;
alu_ctrl <= alu_dec;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1011" => -- undefined
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
when "1100" => -- inc
right_ctrl <= one_right;
alu_ctrl <= alu_inc;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1101" => -- tst
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
accb_ctrl <= latch_accb;
cc_ctrl <= load_cc;
when "1110" => -- jmp (undefined)
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
when "1111" => -- clr
right_ctrl <= zero_right;
alu_ctrl <= alu_clr;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when others =>
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
end case;
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
--
-- Single operand indexed
-- Two byte instruction so advance PC
-- EA should hold index offset
--
when "0110" => -- indexed single op
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
-- idle ALU
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
-- increment the pc
pc_ctrl <= incr_pc;
-- next state
case op_code(3 downto 0) is
when "1110" => -- jmp
return_state <= jmp_state;
when "1111" => -- clr
return_state <= single_op_exec_state;
when others =>
return_state <= single_op_read_state;
end case;
st_ctrl <= push_st;
next_state <= indexed_state;
--
-- Single operand extended addressing
-- three byte instruction so advance the PC
-- Low order EA holds high order address
--
when "0111" => -- extended single op
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
-- idle ALU
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
-- increment PC
pc_ctrl <= incr_pc;
--
case op_code(3 downto 0) is
when "1110" => -- jmp
return_state <= jmp_state;
when "1111" => -- clr
return_state <= single_op_exec_state;
when others =>
return_state <= single_op_read_state;
end case;
st_ctrl <= push_st;
next_state <= extended_state;
when "1000" => -- acca immediate
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
iv_ctrl <= latch_iv;
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- subd #
"1100" | -- cmpx #
"1110" => -- ldx #
-- idle ALU
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
--
st_ctrl <= push_st;
return_state <= fetch_state;
next_state <= imm16_state;
--
-- bsr offset - Branch to subroutine (2 bytes)
-- 6809 => 7 cycles
-- cpu09 => 5 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 md_hi=sign(pc) / md_lo=(pc) / sp=sp-1 / pc=pc+1
-- 3 (sp)=pc_lo / sp=sp-1
-- 4 (sp)=pc_hi
-- 5 pc=pc+md
--
when "1101" => -- bsr
-- pre decrement SP
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
--
st_ctrl <= push_st;
return_state <= sbranch_state;
next_state <= push_return_lo_state;
when others =>
-- idle ALU
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
end case;
when "1001" => -- acca direct
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
iv_ctrl <= latch_iv;
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- subd
"1100" | -- cmpx
"1110" => -- ldx
-- idle ALU
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= dual_op_read16_state;
when "0111" => -- sta direct
-- idle ALU
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= dual_op_write8_state;
when "1111" => -- stx direct
-- idle ALU
left_ctrl <= ix_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= dual_op_write16_state;
--
-- jsr direct - Jump to subroutine in direct page (2 bytes)
-- 6809 => 7 cycles
-- cpu09 => 5 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 ea_hi=0 / ea_lo=(pc) / sp=sp-1 / pc=pc+1
-- 3 (sp)=pc_lo / sp=sp-1
-- 4 (sp)=pc_hi
-- 5 pc=ea
--
when "1101" => -- jsr direct
-- pre decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
--
st_ctrl <= push_st;
return_state <= jmp_state;
next_state <= push_return_lo_state;
when others =>
-- idle ALU
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= dual_op_read8_state;
end case;
when "1010" => -- acca indexed
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
iv_ctrl <= latch_iv;
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- subd
"1100" | -- cmpx
"1110" => -- ldx
-- idle ALU
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
--
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= indexed_state;
when "0111" => -- staa ,x
-- idle ALU
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
--
st_ctrl <= push_st;
return_state <= dual_op_write8_state;
next_state <= indexed_state;
when "1111" => -- stx ,x
-- idle ALU
left_ctrl <= ix_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
--
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= indexed_state;
when "1101" => -- jsr ,x
-- DO NOT pre decrement SP
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
--
st_ctrl <= push_st;
return_state <= jsr_state;
next_state <= indexed_state;
when others =>
-- idle ALU
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
--
st_ctrl <= push_st;
return_state <= dual_op_read8_state;
next_state <= indexed_state;
end case;
when "1011" => -- acca extended
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
iv_ctrl <= latch_iv;
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- subd
"1100" | -- cmpx
"1110" => -- ldx
-- idle ALU
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
--
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= extended_state;
when "0111" => -- staa >
-- idle ALU
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
--
st_ctrl <= push_st;
return_state <= dual_op_write8_state;
next_state <= extended_state;
when "1111" => -- stx >
-- idle ALU
left_ctrl <= ix_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
--
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= extended_state;
when "1101" => -- jsr >extended
-- DO NOT pre decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
--
st_ctrl <= push_st;
return_state <= jsr_state;
next_state <= extended_state;
when others =>
-- idle ALU
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
--
st_ctrl <= push_st;
return_state <= dual_op_read8_state;
next_state <= extended_state;
end case;
when "1100" => -- accb immediate
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
--
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- addd #
"1100" | -- ldd #
"1110" => -- ldu #
st_ctrl <= push_st;
return_state <= fetch_state;
next_state <= imm16_state;
when others =>
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
end case;
when "1101" => -- accb direct
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
-- increment the pc
pc_ctrl <= incr_pc;
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
case op_code(3 downto 0) is
when "0011" | -- addd
"1100" | -- ldd
"1110" => -- ldu
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= dual_op_read16_state;
when "0111" => -- stab direct
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= dual_op_write8_state;
when "1101" => -- std direct
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= dual_op_write16_state;
when "1111" => -- stu direct
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= dual_op_write16_state;
when others =>
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= dual_op_read8_state;
end case;
when "1110" => -- accb indexed
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
-- increment the pc
pc_ctrl <= incr_pc;
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
case op_code(3 downto 0) is
when "0011" | -- addd
"1100" | -- ldd
"1110" => -- ldu
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= indexed_state;
when "0111" => -- stab indexed
st_ctrl <= push_st;
return_state <= dual_op_write8_state;
next_state <= indexed_state;
when "1101" => -- std indexed
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= indexed_state;
when "1111" => -- stu indexed
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= indexed_state;
when others =>
st_ctrl <= push_st;
return_state <= dual_op_read8_state;
next_state <= indexed_state;
end case;
when "1111" => -- accb extended
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
-- increment the pc
pc_ctrl <= incr_pc;
--
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
--
case op_code(3 downto 0) is
when "0011" | -- addd
"1100" | -- ldd
"1110" => -- ldu
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= extended_state;
when "0111" => -- stab extended
st_ctrl <= push_st;
return_state <= dual_op_write8_state;
next_state <= extended_state;
when "1101" => -- std extended
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= extended_state;
when "1111" => -- stu extended
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= extended_state;
when others =>
st_ctrl <= push_st;
return_state <= dual_op_read8_state;
next_state <= extended_state;
end case;
when others =>
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
-- idle the ALU
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- idle the pc
pc_ctrl <= latch_pc;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
end case;
--
-- Here to decode prefix 2 instruction
-- and fetch next byte of intruction
-- whether it be necessary or not
--
when decode2_state =>
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
-- fetch first byte of address or immediate data
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
nmi_ctrl <= latch_nmi;
dp_ctrl <= latch_dp;
case op_code(7 downto 4) is
--
-- lbcc -- long branch conditional
-- 6809 => branch 6 cycles, no branch 5 cycles
-- cpu09 => always 5 cycles
-- 1 pre=(pc) / pc=pc+1
-- 2 op=(pc) / pc=pc+1
-- 3 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1
-- 4 md_hi=md_lo / md_lo=(pc) / pc=pc+1
-- 5 if cond pc=pc+md else pc=pc
--
when "0010" =>
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
up_ctrl <= latch_up;
iv_ctrl <= latch_iv;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
pc_ctrl <= incr_pc;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= lbranch_state;
--
-- Single byte stack operators
-- Do not advance PC
--
when "0011" =>
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
case op_code(3 downto 0) is
when "1111" => -- swi 2
-- predecrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
iv_ctrl <= swi2_iv;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= int_entire_state;
when others =>
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
end case;
when "1000" => -- acca immediate
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
-- Idle the ALU
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpd #
"1100" | -- cmpy #
"1110" => -- ldy #
st_ctrl <= push_st;
return_state <= fetch_state;
next_state <= imm16_state;
when others =>
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
end case;
when "1001" => -- acca direct
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
-- idle the ALU
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpd <
"1100" | -- cmpy <
"1110" => -- ldy <
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= dual_op_read16_state;
when "1111" => -- sty <
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= dual_op_write16_state;
when others =>
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
end case;
when "1010" => -- acca indexed
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
-- idle the ALU
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpd ,ind
"1100" | -- cmpy ,ind
"1110" => -- ldy ,ind
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= indexed_state;
when "1111" => -- sty ,ind
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= indexed_state;
when others =>
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
end case;
when "1011" => -- acca extended
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
-- idle the ALU
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpd <
"1100" | -- cmpy <
"1110" => -- ldy <
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= extended_state;
when "1111" => -- sty >
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= extended_state;
when others =>
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
end case;
when "1100" => -- accb immediate
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
-- idle the alu
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- undef #
"1100" | -- undef #
"1110" => -- lds #
st_ctrl <= push_st;
return_state <= fetch_state;
next_state <= imm16_state;
when others =>
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
end case;
when "1101" => -- accb direct
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
-- idle the alu
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- undef <
"1100" | -- undef <
"1110" => -- lds <
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= dual_op_read16_state;
when "1111" => -- sts <
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= dual_op_write16_state;
when others =>
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
end case;
when "1110" => -- accb indexed
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
-- idle the alu
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- undef ,ind
"1100" | -- undef ,ind
"1110" => -- lds ,ind
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= indexed_state;
when "1111" => -- sts ,ind
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= indexed_state;
when others =>
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
end case;
when "1111" => -- accb extended
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
-- idle the alu
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- undef >
"1100" | -- undef >
"1110" => -- lds >
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= extended_state;
when "1111" => -- sts >
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= extended_state;
when others =>
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
end case;
when others =>
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
-- idle the alu
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- idle the pc
pc_ctrl <= latch_pc;
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
end case;
--
-- Here to decode instruction
-- and fetch next byte of intruction
-- whether it be necessary or not
--
when decode3_state =>
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
nmi_ctrl <= latch_nmi;
dp_ctrl <= latch_dp;
case op_code(7 downto 4) is
--
-- Single byte stack operators
-- Do not advance PC
--
when "0011" =>
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
--
case op_code(3 downto 0) is
when "1111" => -- swi3
-- predecrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
iv_ctrl <= swi3_iv;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= int_entire_state;
when others =>
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
end case;
when "1000" => -- acca immediate
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
-- idle the alu
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpu #
"1100" | -- cmps #
"1110" => -- undef #
st_ctrl <= push_st;
return_state <= fetch_state;
next_state <= imm16_state;
when others =>
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
end case;
when "1001" => -- acca direct
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
-- idle the alu
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpu <
"1100" | -- cmps <
"1110" => -- undef <
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= dual_op_read16_state;
when others =>
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
end case;
when "1010" => -- acca indexed
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
-- idle the alu
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpu ,X
"1100" | -- cmps ,X
"1110" => -- undef ,X
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= indexed_state;
when others =>
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
end case;
when "1011" => -- acca extended
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
-- idle the alu
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpu >
"1100" | -- cmps >
"1110" => -- undef >
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= extended_state;
when others =>
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
end case;
when others =>
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
-- idle the alu
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- idle the pc
pc_ctrl <= latch_pc;
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
end case;
--
-- here if ea holds low byte
-- Direct
-- Extended
-- Indexed
-- read memory location
--
when single_op_read_state =>
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
dp_ctrl <= latch_dp;
nmi_ctrl <= latch_nmi;
-- idle ALU
left_ctrl <= ea_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ea_ctrl <= latch_ea;
-- read memory into md
md_ctrl <= fetch_first_md;
addr_ctrl <= read_ad;
dout_ctrl <= md_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= single_op_exec_state;
when single_op_exec_state =>
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
dp_ctrl <= latch_dp;
nmi_ctrl <= latch_nmi;
iv_ctrl <= latch_iv;
ea_ctrl <= latch_ea;
-- idle the bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
st_ctrl <= idle_st;
return_state <= fetch_state;
case op_code(3 downto 0) is
when "0000" => -- neg
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_neg;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
pc_ctrl <= latch_pc;
next_state <= single_op_write_state;
when "0011" => -- com
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_com;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
pc_ctrl <= latch_pc;
next_state <= single_op_write_state;
when "0100" => -- lsr
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_lsr8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
pc_ctrl <= latch_pc;
next_state <= single_op_write_state;
when "0110" => -- ror
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_ror8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
pc_ctrl <= latch_pc;
next_state <= single_op_write_state;
when "0111" => -- asr
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_asr8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
pc_ctrl <= latch_pc;
next_state <= single_op_write_state;
when "1000" => -- asl
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_asl8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
pc_ctrl <= latch_pc;
next_state <= single_op_write_state;
when "1001" => -- rol
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_rol8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
pc_ctrl <= latch_pc;
next_state <= single_op_write_state;
when "1010" => -- dec
left_ctrl <= md_left;
right_ctrl <= one_right;
alu_ctrl <= alu_dec;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
pc_ctrl <= latch_pc;
next_state <= single_op_write_state;
when "1011" => -- undefined
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
pc_ctrl <= latch_pc;
next_state <= fetch_state;
when "1100" => -- inc
left_ctrl <= md_left;
right_ctrl <= one_right;
alu_ctrl <= alu_inc;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
pc_ctrl <= latch_pc;
next_state <= single_op_write_state;
when "1101" => -- tst
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
md_ctrl <= latch_md;
pc_ctrl <= latch_pc;
next_state <= fetch_state;
when "1110" => -- jmp
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
pc_ctrl <= load_pc;
next_state <= fetch_state;
when "1111" => -- clr
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_clr;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
pc_ctrl <= latch_pc;
next_state <= single_op_write_state;
when others =>
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
pc_ctrl <= latch_pc;
next_state <= fetch_state;
end case;
--
-- single operand 8 bit write
-- Write low 8 bits of ALU output
-- EA holds address
-- MD holds data
--
when single_op_write_state =>
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
dp_ctrl <= latch_dp;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- idle the ALU
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- write ALU low byte output
addr_ctrl <= write_ad;
dout_ctrl <= md_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
--
-- here if ea holds address of low byte
-- read memory location
--
when dual_op_read8_state =>
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
dp_ctrl <= latch_dp;
nmi_ctrl <= latch_nmi;
left_ctrl <= ea_left;
-- Leave the ea alone
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ea_ctrl <= latch_ea;
-- read first data byte from ea
md_ctrl <= fetch_first_md;
addr_ctrl <= read_ad;
dout_ctrl <= md_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
--
-- Here to read a 16 bit value into MD
-- pointed to by the EA register
-- The first byte is read
-- and the EA is incremented
--
when dual_op_read16_state =>
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
nmi_ctrl <= latch_nmi;
-- increment the effective address
left_ctrl <= ea_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- read the low byte of the 16 bit data
md_ctrl <= fetch_first_md;
addr_ctrl <= read_ad;
dout_ctrl <= md_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= dual_op_read16_2_state;
--
-- here to read the second byte
-- pointed to by EA into MD
--
when dual_op_read16_2_state =>
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
nmi_ctrl <= latch_nmi;
-- idle the effective address
left_ctrl <= ea_left;
right_ctrl <= one_right;
alu_ctrl <= alu_nop;
ea_ctrl <= latch_ea;
-- read the low byte of the 16 bit data
md_ctrl <= fetch_next_md;
addr_ctrl <= read_ad;
dout_ctrl <= md_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
--
-- 16 bit Write state
-- EA hold address of memory to write to
-- Advance the effective address in ALU
-- decode op_code to determine which
-- register to write
--
when dual_op_write16_state =>
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
dp_ctrl <= latch_dp;
nmi_ctrl <= latch_nmi;
-- increment the effective address
left_ctrl <= ea_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ea_ctrl <= load_ea;
-- write the ALU hi byte at ea
addr_ctrl <= write_ad;
if op_code(6) = '0' then
case op_code(3 downto 0) is
when "1111" => -- stx / sty
case pre_code is
when "00010000" => -- page 2 -- sty
dout_ctrl <= iy_hi_dout;
when others => -- page 1 -- stx
dout_ctrl <= ix_hi_dout;
end case;
when others =>
dout_ctrl <= md_hi_dout;
end case;
else
case op_code(3 downto 0) is
when "1101" => -- std
dout_ctrl <= acca_dout; -- acca is high byte of ACCD
when "1111" => -- stu / sts
case pre_code is
when "00010000" => -- page 2 -- sts
dout_ctrl <= sp_hi_dout;
when others => -- page 1 -- stu
dout_ctrl <= up_hi_dout;
end case;
when others =>
dout_ctrl <= md_hi_dout;
end case;
end if;
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= dual_op_write8_state;
--
-- Dual operand 8 bit write
-- Write 8 bit accumulator
-- or low byte of 16 bit register
-- EA holds address
-- decode opcode to determine
-- which register to apply to the bus
-- Also set the condition codes here
--
when dual_op_write8_state =>
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
dp_ctrl <= latch_dp;
nmi_ctrl <= latch_nmi;
md_ctrl <= latch_md;
-- idle ALU
left_ctrl <= ea_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ea_ctrl <= latch_ea;
--
if op_code(6) = '0' then -- '0' = acca line
case op_code(3 downto 0) is
when "0111" => -- sta
dout_ctrl <= acca_dout;
when "1111" => -- stx / sty
case pre_code is
when "00010000" => -- page 2 -- sty
dout_ctrl <= iy_lo_dout;
when others => -- page 1 -- stx
dout_ctrl <= ix_lo_dout;
end case;
when others =>
dout_ctrl <= md_lo_dout;
end case;
else -- '1' = accb line
case op_code(3 downto 0) is
when "0111" => -- stb
dout_ctrl <= accb_dout;
when "1101" => -- std
dout_ctrl <= accb_dout; -- accb is low byte of accd
when "1111" => -- stu / sts
case pre_code is
when "00010000" => -- page 2 -- sts
dout_ctrl <= sp_lo_dout;
when others => -- page 1 -- stu
dout_ctrl <= up_lo_dout;
end case;
when others =>
dout_ctrl <= md_lo_dout;
end case;
end if;
-- write ALU low byte output
addr_ctrl <= write_ad;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
--
-- 16 bit immediate addressing mode
--
when imm16_state =>
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
--
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
--
iv_ctrl <= latch_iv;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment pc
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
pc_ctrl <= incr_pc;
-- fetch next immediate byte
md_ctrl <= fetch_next_md;
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
-- return to caller
st_ctrl <= pull_st;
return_state <= fetch_state;
next_state <= saved_state;
--
-- md & ea holds 8 bit index offset
-- calculate the effective memory address
-- using the alu
--
when indexed_state =>
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
iv_ctrl <= latch_iv;
dp_ctrl <= latch_dp;
nmi_ctrl <= latch_nmi;
dout_ctrl <= md_lo_dout;
--
-- decode indexing mode
--
if md(7) = '0' then
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= md_sign5_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ea_ctrl <= load_ea;
--
md_ctrl <= latch_md;
addr_ctrl <= idle_ad;
pc_ctrl <= latch_pc;
--
st_ctrl <= pull_st;
return_state <= fetch_state;
next_state <= saved_state;
else
case md(3 downto 0) is
when "0000" => -- ,R+
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
left_ctrl <= sp_left;
end case;
--
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
ea_ctrl <= load_ea;
--
md_ctrl <= latch_md;
addr_ctrl <= idle_ad;
pc_ctrl <= latch_pc;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= postincr1_state;
when "0001" => -- ,R++
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
ea_ctrl <= load_ea;
--
md_ctrl <= latch_md;
addr_ctrl <= idle_ad;
pc_ctrl <= latch_pc;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= postincr2_state;
when "0010" => -- ,-R
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
ix_ctrl <= load_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "01" =>
left_ctrl <= iy_left;
ix_ctrl <= latch_ix;
iy_ctrl <= load_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "10" =>
left_ctrl <= up_left;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= load_up;
sp_ctrl <= latch_sp;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= load_sp;
end case;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
ea_ctrl <= load_ea;
--
md_ctrl <= latch_md;
addr_ctrl <= idle_ad;
pc_ctrl <= latch_pc;
--
st_ctrl <= pull_st;
return_state <= fetch_state;
next_state <= saved_state;
when "0011" => -- ,--R
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
ix_ctrl <= load_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "01" =>
left_ctrl <= iy_left;
ix_ctrl <= latch_ix;
iy_ctrl <= load_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "10" =>
left_ctrl <= up_left;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= load_up;
sp_ctrl <= latch_sp;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= load_sp;
end case;
right_ctrl <= two_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
ea_ctrl <= load_ea;
--
md_ctrl <= latch_md;
addr_ctrl <= idle_ad;
pc_ctrl <= latch_pc;
--
if md(4) = '0' then
st_ctrl <= pull_st;
return_state <= fetch_state;
next_state <= saved_state;
else
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= indirect_state;
end if;
when "0100" => -- ,R (zero offset)
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
ea_ctrl <= load_ea;
--
md_ctrl <= latch_md;
addr_ctrl <= idle_ad;
pc_ctrl <= latch_pc;
--
if md(4) = '0' then
st_ctrl <= pull_st;
return_state <= fetch_state;
next_state <= saved_state;
else
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= indirect_state;
end if;
when "0101" => -- ACCB,R
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= accb_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ea_ctrl <= load_ea;
--
md_ctrl <= latch_md;
addr_ctrl <= idle_ad;
pc_ctrl <= latch_pc;
--
if md(4) = '0' then
st_ctrl <= pull_st;
return_state <= fetch_state;
next_state <= saved_state;
else
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= indirect_state;
end if;
when "0110" => -- ACCA,R
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= acca_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ea_ctrl <= load_ea;
--
md_ctrl <= latch_md;
addr_ctrl <= idle_ad;
pc_ctrl <= latch_pc;
--
if md(4) = '0' then
st_ctrl <= pull_st;
return_state <= fetch_state;
next_state <= saved_state;
else
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= indirect_state;
end if;
when "0111" => -- undefined
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ea_ctrl <= latch_ea;
--
md_ctrl <= latch_md;
addr_ctrl <= idle_ad;
pc_ctrl <= latch_pc;
--
if md(4) = '0' then
st_ctrl <= pull_st;
return_state <= fetch_state;
next_state <= saved_state;
else
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= indirect_state;
end if;
when "1000" => -- offset8,R
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
--
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ea_ctrl <= latch_ea;
--
md_ctrl <= fetch_first_md; -- pick up 8 bit offset
addr_ctrl <= fetch_ad;
pc_ctrl <= incr_pc;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= index8_state;
when "1001" => -- offset16,R
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
--
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ea_ctrl <= latch_ea;
--
md_ctrl <= fetch_first_md; -- pick up first byte of 16 bit offset
addr_ctrl <= fetch_ad;
pc_ctrl <= incr_pc;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= index16_state;
when "1010" => -- undefined
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ea_ctrl <= latch_ea;
--
md_ctrl <= latch_md;
addr_ctrl <= idle_ad;
pc_ctrl <= latch_pc;
--
if md(4) = '0' then
st_ctrl <= pull_st;
return_state <= fetch_state;
next_state <= saved_state;
else
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= indirect_state;
end if;
when "1011" => -- ACCD,R
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= accd_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ea_ctrl <= load_ea;
--
md_ctrl <= latch_md;
addr_ctrl <= idle_ad;
pc_ctrl <= latch_pc;
--
if md(4) = '0' then
st_ctrl <= pull_st;
return_state <= fetch_state;
next_state <= saved_state;
else
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= indirect_state;
end if;
when "1100" => -- offset8,PC
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
--
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ea_ctrl <= latch_ea;
-- fetch 8 bit offset
md_ctrl <= fetch_first_md;
addr_ctrl <= fetch_ad;
pc_ctrl <= incr_pc;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= pcrel8_state;
when "1101" => -- offset16,PC
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
--
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ea_ctrl <= latch_ea;
-- fetch offset
md_ctrl <= fetch_first_md;
addr_ctrl <= fetch_ad;
pc_ctrl <= incr_pc;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= pcrel16_state;
when "1110" => -- undefined
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ea_ctrl <= load_ea;
--
md_ctrl <= latch_md;
addr_ctrl <= idle_ad;
pc_ctrl <= latch_pc;
--
if md(4) = '0' then
st_ctrl <= pull_st;
return_state <= fetch_state;
next_state <= saved_state;
else
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= indirect_state;
end if;
when others => -- when "1111" => -- [,address]
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
-- idle ALU
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ea_ctrl <= latch_ea;
-- advance PC to pick up address
md_ctrl <= fetch_first_md;
addr_ctrl <= fetch_ad;
pc_ctrl <= incr_pc;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= indexaddr_state;
end case;
end if;
-- load index register with ea plus one
when postincr1_state =>
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
iv_ctrl <= latch_iv;
nmi_ctrl <= latch_nmi;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
ea_ctrl <= latch_ea;
--
left_ctrl <= ea_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
case md(6 downto 5) is
when "00" =>
ix_ctrl <= load_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "01" =>
ix_ctrl <= latch_ix;
iy_ctrl <= load_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "10" =>
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= load_up;
sp_ctrl <= latch_sp;
when others => -- when "11" =>
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= load_sp;
end case;
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
-- return to previous state
if md(4) = '0' then
st_ctrl <= pull_st;
return_state <= fetch_state;
next_state <= saved_state;
else
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= indirect_state;
end if;
-- load index register with ea plus two
when postincr2_state =>
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
iv_ctrl <= latch_iv;
nmi_ctrl <= latch_nmi;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
ea_ctrl <= latch_ea;
-- increment register by two (address)
left_ctrl <= ea_left;
right_ctrl <= two_right;
alu_ctrl <= alu_add16;
case md(6 downto 5) is
when "00" =>
ix_ctrl <= load_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "01" =>
ix_ctrl <= latch_ix;
iy_ctrl <= load_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "10" =>
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= load_up;
sp_ctrl <= latch_sp;
when others =>
-- when "11" =>
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= load_sp;
end case;
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
-- return to previous state
if md(4) = '0' then
st_ctrl <= pull_st;
return_state <= fetch_state;
next_state <= saved_state;
else
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= indirect_state;
end if;
--
-- ea = index register + md (8 bit signed offset)
-- ea holds post byte
--
when index8_state =>
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
nmi_ctrl <= latch_nmi;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
case ea(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
-- ea = index reg + md
right_ctrl <= md_sign8_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
-- return to previous state
if ea(4) = '0' then
st_ctrl <= pull_st;
return_state <= fetch_state;
next_state <= saved_state;
else
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= indirect_state;
end if;
-- fetch low byte of 16 bit indexed offset
when index16_state =>
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
nmi_ctrl <= latch_nmi;
-- advance pc
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
pc_ctrl <= incr_pc;
-- fetch low byte
ea_ctrl <= latch_ea;
md_ctrl <= fetch_next_md;
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= index16_2_state;
-- ea = index register + md (16 bit offset)
-- ea holds post byte
when index16_2_state =>
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
nmi_ctrl <= latch_nmi;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
case ea(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
-- ea = index reg + md
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
-- return to previous state
if ea(4) = '0' then
st_ctrl <= pull_st;
return_state <= fetch_state;
next_state <= saved_state;
else
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= indirect_state;
end if;
--
-- pc relative with 8 bit signed offest
-- md holds signed offset
--
when pcrel8_state =>
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
nmi_ctrl <= latch_nmi;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
-- ea = pc + signed md
left_ctrl <= pc_left;
right_ctrl <= md_sign8_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
-- return to previous state
if ea(4) = '0' then
st_ctrl <= pull_st;
return_state <= fetch_state;
next_state <= saved_state;
else
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= indirect_state;
end if;
-- pc relative addressing with 16 bit offset
-- pick up the low byte of the offset in md
-- advance the pc
when pcrel16_state =>
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- advance pc
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
pc_ctrl <= incr_pc;
-- fetch low byte
ea_ctrl <= latch_ea;
md_ctrl <= fetch_next_md;
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= pcrel16_2_state;
-- pc relative with16 bit signed offest
-- md holds signed offset
when pcrel16_2_state =>
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
nmi_ctrl <= latch_nmi;
pc_ctrl <= latch_pc;
-- ea = pc + md
left_ctrl <= pc_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
md_ctrl <= latch_md;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
-- return to previous state
if ea(4) = '0' then
st_ctrl <= pull_st;
return_state <= fetch_state;
next_state <= saved_state;
else
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= indirect_state;
end if;
-- indexed to address
-- pick up the low byte of the address
-- advance the pc
when indexaddr_state =>
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
-- advance pc
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
pc_ctrl <= incr_pc;
-- fetch low byte
ea_ctrl <= latch_ea;
md_ctrl <= fetch_next_md;
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= indexaddr2_state;
-- indexed to absolute address
-- md holds address
-- ea hold indexing mode byte
when indexaddr2_state =>
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
nmi_ctrl <= latch_nmi;
pc_ctrl <= latch_pc;
-- ea = md
left_ctrl <= pc_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
ea_ctrl <= load_ea;
md_ctrl <= latch_md;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
-- return to previous state
if ea(4) = '0' then
st_ctrl <= pull_st;
return_state <= fetch_state;
next_state <= saved_state;
else
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= indirect_state;
end if;
--
-- load md with high byte of indirect address
-- pointed to by ea
-- increment ea
--
when indirect_state =>
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
pc_ctrl <= latch_pc;
-- increment ea
left_ctrl <= ea_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- fetch high byte
md_ctrl <= fetch_first_md;
addr_ctrl <= read_ad;
dout_ctrl <= md_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= indirect2_state;
--
-- load md with low byte of indirect address
-- pointed to by ea
-- ea has previously been incremented
--
when indirect2_state =>
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
pc_ctrl <= latch_pc;
-- idle ea
left_ctrl <= ea_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
ea_ctrl <= latch_ea;
-- fetch high byte
md_ctrl <= fetch_next_md;
addr_ctrl <= read_ad;
dout_ctrl <= md_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= indirect3_state;
--
-- complete idirect addressing
-- by loading ea with md
--
when indirect3_state =>
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
pc_ctrl <= latch_pc;
-- load ea with md
left_ctrl <= ea_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
ea_ctrl <= load_ea;
-- idle cycle
md_ctrl <= latch_md;
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
-- return to previous state
st_ctrl <= pull_st;
return_state <= fetch_state;
next_state <= saved_state;
--
-- ea holds the low byte of the absolute address
-- Move ea low byte into ea high byte
-- load new ea low byte to for absolute 16 bit address
-- advance the program counter
--
when extended_state => -- fetch ea low byte
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
dp_ctrl <= latch_dp;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
-- increment pc
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
pc_ctrl <= incr_pc;
-- fetch next effective address bytes
ea_ctrl <= fetch_next_ea;
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
-- return to previous state
st_ctrl <= pull_st;
return_state <= fetch_state;
next_state <= saved_state;
when lea_state => -- here on load effective address
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
iv_ctrl <= latch_iv;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
md_ctrl <= latch_md;
ea_ctrl <= latch_ea;
pc_ctrl <= latch_pc;
-- load index register with effective address
left_ctrl <= pc_left;
right_ctrl <= ea_right;
alu_ctrl <= alu_lea;
case op_code(3 downto 0) is
when "0000" => -- leax
cc_ctrl <= load_cc;
ix_ctrl <= load_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "0001" => -- leay
cc_ctrl <= load_cc;
ix_ctrl <= latch_ix;
iy_ctrl <= load_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
when "0010" => -- leas
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= load_sp;
when "0011" => -- leau
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= load_up;
sp_ctrl <= latch_sp;
when others =>
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
end case;
-- idle the bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
--
-- jump to subroutine
-- sp=sp-1
-- call push_return_lo_state to save pc
-- return to jmp_state
--
when jsr_state =>
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
md_ctrl <= latch_md;
ea_ctrl <= latch_ea;
pc_ctrl <= latch_pc;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= pc_lo_dout;
-- call push_return_state
st_ctrl <= push_st;
return_state <= jmp_state;
next_state <= push_return_lo_state;
--
-- Load pc with ea
-- (JMP)
--
when jmp_state =>
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
md_ctrl <= latch_md;
ea_ctrl <= latch_ea;
-- load PC with effective address
left_ctrl <= pc_left;
right_ctrl <= ea_right;
alu_ctrl <= alu_ld16;
pc_ctrl <= load_pc;
-- idle the bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
--
-- long branch or branch to subroutine
-- pick up next md byte
-- md_hi = md_lo
-- md_lo = (pc)
-- pc=pc+1
-- if a lbsr push return address
-- continue to sbranch_state
-- to evaluate conditional branches
--
when lbranch_state =>
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
--
left_ctrl <= pc_left;
right_ctrl <= ea_right;
alu_ctrl <= alu_ld16;
pc_ctrl <= incr_pc;
-- fetch the next byte into md_lo
md_ctrl <= fetch_next_md;
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
-- if lbsr - push return address
-- then continue on to short branch
if op_code = "00010111" then
st_ctrl <= push_st;
return_state <= sbranch_state;
next_state <= push_return_lo_state;
else
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= sbranch_state;
end if;
--
-- here to execute conditional branch
-- short conditional branch md = signed 8 bit offset
-- long branch md = 16 bit offset
--
when sbranch_state =>
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
md_ctrl <= latch_md;
--
left_ctrl <= pc_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
--
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
if op_code(7 downto 4) = "0010" then -- conditional branch
case op_code(3 downto 0) is
when "0000" => -- bra
cond_true := (1 = 1);
when "0001" => -- brn
cond_true := (1 = 0);
when "0010" => -- bhi
cond_true := ((cc(CBIT) or cc(ZBIT)) = '0');
when "0011" => -- bls
cond_true := ((cc(CBIT) or cc(ZBIT)) = '1');
when "0100" => -- bcc/bhs
cond_true := (cc(CBIT) = '0');
when "0101" => -- bcs/blo
cond_true := (cc(CBIT) = '1');
when "0110" => -- bne
cond_true := (cc(ZBIT) = '0');
when "0111" => -- beq
cond_true := (cc(ZBIT) = '1');
when "1000" => -- bvc
cond_true := (cc(VBIT) = '0');
when "1001" => -- bvs
cond_true := (cc(VBIT) = '1');
when "1010" => -- bpl
cond_true := (cc(NBIT) = '0');
when "1011" => -- bmi
cond_true := (cc(NBIT) = '1');
when "1100" => -- bge
cond_true := ((cc(NBIT) xor cc(VBIT)) = '0');
when "1101" => -- blt
cond_true := ((cc(NBIT) xor cc(VBIT)) = '1');
when "1110" => -- bgt
cond_true := ((cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '0');
when "1111" => -- ble
cond_true := ((cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '1');
when others =>
cond_true := (1 = 1);
end case;
else
cond_true := (1 = 1); -- lbra, lbsr, bsr
end if;
if cond_true then
pc_ctrl <= load_pc;
else
pc_ctrl <= latch_pc;
end if;
--
-- push return address onto the S stack
--
-- (sp) = pc_lo
-- sp = sp - 1
--
when push_return_lo_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
dp_ctrl <= latch_dp;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement the sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write PC low
pc_ctrl <= latch_pc;
addr_ctrl <= pushs_ad;
dout_ctrl <= pc_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= push_return_hi_state;
--
-- push program counter hi byte onto the stack
-- (sp) = pc_hi
-- sp = sp
-- return to originating state
--
when push_return_hi_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
dp_ctrl <= latch_dp;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- idle the SP
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
-- write pc hi bytes
pc_ctrl <= latch_pc;
addr_ctrl <= pushs_ad;
dout_ctrl <= pc_hi_dout;
--
st_ctrl <= pull_st;
return_state <= fetch_state;
next_state <= saved_state;
when pull_return_hi_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
dp_ctrl <= latch_dp;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment the sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- read pc hi
pc_ctrl <= pull_hi_pc;
addr_ctrl <= pulls_ad;
dout_ctrl <= pc_hi_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= pull_return_lo_state;
when pull_return_lo_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
dp_ctrl <= latch_dp;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment the SP
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- read pc low
pc_ctrl <= pull_lo_pc;
addr_ctrl <= pulls_ad;
dout_ctrl <= pc_lo_dout;
--
st_ctrl <= pull_st;
return_state <= fetch_state;
next_state <= saved_state;
when andcc_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
dp_ctrl <= latch_dp;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
md_ctrl <= latch_md;
-- AND CC with md
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_andcc;
cc_ctrl <= load_cc;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
--
st_ctrl <= pull_st;
return_state <= fetch_state;
next_state <= saved_state;
when orcc_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
dp_ctrl <= latch_dp;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
md_ctrl <= latch_md;
-- OR CC with md
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_orcc;
cc_ctrl <= load_cc;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
--
st_ctrl <= pull_st;
return_state <= fetch_state;
next_state <= saved_state;
when tfr_state =>
-- default
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
md_ctrl <= latch_md;
-- select source register
case md(7 downto 4) is
when "0000" =>
left_ctrl <= accd_left;
when "0001" =>
left_ctrl <= ix_left;
when "0010" =>
left_ctrl <= iy_left;
when "0011" =>
left_ctrl <= up_left;
when "0100" =>
left_ctrl <= sp_left;
when "0101" =>
left_ctrl <= pc_left;
when "1000" =>
left_ctrl <= acca_left;
when "1001" =>
left_ctrl <= accb_left;
when "1010" =>
left_ctrl <= cc_left;
when "1011" =>
left_ctrl <= dp_left;
when others =>
left_ctrl <= md_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_tfr;
-- select destination register
case md(3 downto 0) is
when "0000" => -- accd
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
when "0001" => -- ix
ix_ctrl <= load_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
when "0010" => -- iy
ix_ctrl <= latch_ix;
iy_ctrl <= load_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
when "0011" => -- up
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= load_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
when "0100" => -- sp
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= load_sp;
pc_ctrl <= latch_pc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
when "0101" => -- pc
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= load_pc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
when "1000" => -- acca
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
when "1001" => -- accb
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
when "1010" => -- cc
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= load_cc;
dp_ctrl <= latch_dp;
when "1011" => --dp
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= load_dp;
when others =>
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
end case;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
--
st_ctrl <= pull_st;
return_state <= fetch_state;
next_state <= saved_state;
when exg_state =>
-- default
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
md_ctrl <= latch_md;
-- save destination register
case md(3 downto 0) is
when "0000" =>
left_ctrl <= accd_left;
when "0001" =>
left_ctrl <= ix_left;
when "0010" =>
left_ctrl <= iy_left;
when "0011" =>
left_ctrl <= up_left;
when "0100" =>
left_ctrl <= sp_left;
when "0101" =>
left_ctrl <= pc_left;
when "1000" =>
left_ctrl <= acca_left;
when "1001" =>
left_ctrl <= accb_left;
when "1010" =>
left_ctrl <= cc_left;
when "1011" =>
left_ctrl <= dp_left;
when others =>
left_ctrl <= md_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_tfr;
ea_ctrl <= load_ea;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
-- call tranfer microcode
st_ctrl <= push_st;
return_state <= exg1_state;
next_state <= tfr_state;
when exg1_state =>
-- default
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
md_ctrl <= latch_md;
-- restore destination
left_ctrl <= ea_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_tfr;
-- save as source register
case md(7 downto 4) is
when "0000" => -- accd
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
when "0001" => -- ix
ix_ctrl <= load_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
when "0010" => -- iy
ix_ctrl <= latch_ix;
iy_ctrl <= load_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
when "0011" => -- up
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= load_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
when "0100" => -- sp
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= load_sp;
pc_ctrl <= latch_pc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
when "0101" => -- pc
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= load_pc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
when "1000" => -- acca
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
when "1001" => -- accb
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
when "1010" => -- cc
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= load_cc;
dp_ctrl <= latch_dp;
when "1011" => --dp
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= load_dp;
when others =>
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
dp_ctrl <= latch_dp;
end case;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
when mul_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
dp_ctrl <= latch_dp;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- move acca to md
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= mulea_state;
when mulea_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
dp_ctrl <= latch_dp;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
md_ctrl <= latch_md;
-- move accb to ea
left_ctrl <= accb_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
ea_ctrl <= load_ea;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= muld_state;
when muld_state =>
-- default
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
dp_ctrl <= latch_dp;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
md_ctrl <= latch_md;
-- clear accd
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_ld8;
cc_ctrl <= latch_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= mul0_state;
when mul0_state =>
-- default
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
dp_ctrl <= latch_dp;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- if bit 0 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(0) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= mul1_state;
when mul1_state =>
-- default
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
dp_ctrl <= latch_dp;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- if bit 1 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(1) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= mul2_state;
when mul2_state =>
-- default
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
dp_ctrl <= latch_dp;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- if bit 2 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(2) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= mul3_state;
when mul3_state =>
-- default
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
dp_ctrl <= latch_dp;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- if bit 3 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(3) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= mul4_state;
when mul4_state =>
-- default
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
dp_ctrl <= latch_dp;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- if bit 4 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(4) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= mul5_state;
when mul5_state =>
-- default
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
dp_ctrl <= latch_dp;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- if bit 5 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(5) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= mul6_state;
when mul6_state =>
-- default
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
dp_ctrl <= latch_dp;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- if bit 6 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(6) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= mul7_state;
when mul7_state =>
-- default
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
dp_ctrl <= latch_dp;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- if bit 7 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(7) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
--
-- Enter here on pushs
-- ea holds post byte
--
when pshs_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
dp_ctrl <= latch_dp;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp if any registers to be pushed
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(7 downto 0) = "00000000" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
-- write idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
if ea(7) = '1' then
next_state <= pshs_pcl_state;
elsif ea(6) = '1' then
next_state <= pshs_upl_state;
elsif ea(5) = '1' then
next_state <= pshs_iyl_state;
elsif ea(4) = '1' then
next_state <= pshs_ixl_state;
elsif ea(3) = '1' then
next_state <= pshs_dp_state;
elsif ea(2) = '1' then
next_state <= pshs_accb_state;
elsif ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
next_state <= fetch_state;
end if;
when pshs_pcl_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
dp_ctrl <= latch_dp;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write pc low
addr_ctrl <= pushs_ad;
dout_ctrl <= pc_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= pshs_pch_state;
when pshs_pch_state =>
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
dp_ctrl <= latch_dp;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(6 downto 0) = "0000000" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
-- write pc hi
addr_ctrl <= pushs_ad;
dout_ctrl <= pc_hi_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
if ea(6) = '1' then
next_state <= pshs_upl_state;
elsif ea(5) = '1' then
next_state <= pshs_iyl_state;
elsif ea(4) = '1' then
next_state <= pshs_ixl_state;
elsif ea(3) = '1' then
next_state <= pshs_dp_state;
elsif ea(2) = '1' then
next_state <= pshs_accb_state;
elsif ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
next_state <= fetch_state;
end if;
when pshs_upl_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write pc low
addr_ctrl <= pushs_ad;
dout_ctrl <= up_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= pshs_uph_state;
when pshs_uph_state =>
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(5 downto 0) = "000000" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
-- write pc hi
addr_ctrl <= pushs_ad;
dout_ctrl <= up_hi_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
if ea(5) = '1' then
next_state <= pshs_iyl_state;
elsif ea(4) = '1' then
next_state <= pshs_ixl_state;
elsif ea(3) = '1' then
next_state <= pshs_dp_state;
elsif ea(2) = '1' then
next_state <= pshs_accb_state;
elsif ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
next_state <= fetch_state;
end if;
when pshs_iyl_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write iy low
addr_ctrl <= pushs_ad;
dout_ctrl <= iy_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= pshs_iyh_state;
when pshs_iyh_state =>
-- default registers
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(4 downto 0) = "00000" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
-- write iy hi
addr_ctrl <= pushs_ad;
dout_ctrl <= iy_hi_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
if ea(4) = '1' then
next_state <= pshs_ixl_state;
elsif ea(3) = '1' then
next_state <= pshs_dp_state;
elsif ea(2) = '1' then
next_state <= pshs_accb_state;
elsif ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
next_state <= fetch_state;
end if;
when pshs_ixl_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write ix low
addr_ctrl <= pushs_ad;
dout_ctrl <= ix_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= pshs_ixh_state;
when pshs_ixh_state =>
-- default registers
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(3 downto 0) = "0000" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
-- write ix hi
addr_ctrl <= pushs_ad;
dout_ctrl <= ix_hi_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
if ea(3) = '1' then
next_state <= pshs_dp_state;
elsif ea(2) = '1' then
next_state <= pshs_accb_state;
elsif ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
next_state <= fetch_state;
end if;
when pshs_dp_state =>
-- default registers
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(2 downto 0) = "000" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
-- write dp
addr_ctrl <= pushs_ad;
dout_ctrl <= dp_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
if ea(2) = '1' then
next_state <= pshs_accb_state;
elsif ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
next_state <= fetch_state;
end if;
when pshs_accb_state =>
-- default registers
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(1 downto 0) = "00" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
-- write accb
addr_ctrl <= pushs_ad;
dout_ctrl <= accb_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
if ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
next_state <= fetch_state;
end if;
when pshs_acca_state =>
-- default registers
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(0) = '1' then
sp_ctrl <= load_sp;
else
sp_ctrl <= latch_sp;
end if;
-- write acca
addr_ctrl <= pushs_ad;
dout_ctrl <= acca_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
if ea(0) = '1' then
next_state <= pshs_cc_state;
else
next_state <= fetch_state;
end if;
when pshs_cc_state =>
-- default registers
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- idle sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_nop;
sp_ctrl <= latch_sp;
-- write cc
addr_ctrl <= pushs_ad;
dout_ctrl <= cc_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
--
-- enter here on PULS
-- ea hold register mask
--
when puls_state =>
-- default registers
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- idle SP
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= latch_sp;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
if ea(0) = '1' then
next_state <= puls_cc_state;
elsif ea(1) = '1' then
next_state <= puls_acca_state;
elsif ea(2) = '1' then
next_state <= puls_accb_state;
elsif ea(3) = '1' then
next_state <= puls_dp_state;
elsif ea(4) = '1' then
next_state <= puls_ixh_state;
elsif ea(5) = '1' then
next_state <= puls_iyh_state;
elsif ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
next_state <= fetch_state;
end if;
when puls_cc_state =>
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- Increment SP
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read cc
cc_ctrl <= pull_cc;
addr_ctrl <= pulls_ad;
dout_ctrl <= cc_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
if ea(1) = '1' then
next_state <= puls_acca_state;
elsif ea(2) = '1' then
next_state <= puls_accb_state;
elsif ea(3) = '1' then
next_state <= puls_dp_state;
elsif ea(4) = '1' then
next_state <= puls_ixh_state;
elsif ea(5) = '1' then
next_state <= puls_iyh_state;
elsif ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
next_state <= fetch_state;
end if;
when puls_acca_state =>
-- default registers
cc_ctrl <= latch_cc;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- Increment SP
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read acca
acca_ctrl <= pull_acca;
addr_ctrl <= pulls_ad;
dout_ctrl <= acca_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
if ea(2) = '1' then
next_state <= puls_accb_state;
elsif ea(3) = '1' then
next_state <= puls_dp_state;
elsif ea(4) = '1' then
next_state <= puls_ixh_state;
elsif ea(5) = '1' then
next_state <= puls_iyh_state;
elsif ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
next_state <= fetch_state;
end if;
when puls_accb_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- Increment SP
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read accb
accb_ctrl <= pull_accb;
addr_ctrl <= pulls_ad;
dout_ctrl <= accb_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
if ea(3) = '1' then
next_state <= puls_dp_state;
elsif ea(4) = '1' then
next_state <= puls_ixh_state;
elsif ea(5) = '1' then
next_state <= puls_iyh_state;
elsif ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
next_state <= fetch_state;
end if;
when puls_dp_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- idle sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read dp
dp_ctrl <= pull_dp;
addr_ctrl <= pulls_ad;
dout_ctrl <= dp_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
if ea(4) = '1' then
next_state <= puls_ixh_state;
elsif ea(5) = '1' then
next_state <= puls_iyh_state;
elsif ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
next_state <= fetch_state;
end if;
when puls_ixh_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- pull ix hi
ix_ctrl <= pull_hi_ix;
addr_ctrl <= pulls_ad;
dout_ctrl <= ix_hi_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= puls_ixl_state;
when puls_ixl_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- idle sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read ix low
ix_ctrl <= pull_lo_ix;
addr_ctrl <= pulls_ad;
dout_ctrl <= ix_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
if ea(5) = '1' then
next_state <= puls_iyh_state;
elsif ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
next_state <= fetch_state;
end if;
when puls_iyh_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- pull iy hi
iy_ctrl <= pull_hi_iy;
addr_ctrl <= pulls_ad;
dout_ctrl <= iy_hi_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= puls_iyl_state;
when puls_iyl_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read iy low
iy_ctrl <= pull_lo_iy;
addr_ctrl <= pulls_ad;
dout_ctrl <= iy_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
if ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
next_state <= fetch_state;
end if;
when puls_uph_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- pull up hi
up_ctrl <= pull_hi_up;
addr_ctrl <= pulls_ad;
dout_ctrl <= up_hi_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= puls_upl_state;
when puls_upl_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read up low
up_ctrl <= pull_lo_up;
addr_ctrl <= pulls_ad;
dout_ctrl <= up_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
if ea(7) = '1' then
next_state <= puls_pch_state;
else
next_state <= fetch_state;
end if;
when puls_pch_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- pull pc hi
pc_ctrl <= pull_hi_pc;
addr_ctrl <= pulls_ad;
dout_ctrl <= pc_hi_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= puls_pcl_state;
when puls_pcl_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read pc low
pc_ctrl <= pull_lo_pc;
addr_ctrl <= pulls_ad;
dout_ctrl <= pc_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
--
-- Enter here on pshu
-- ea holds post byte
--
when pshu_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
dp_ctrl <= latch_dp;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement up if any registers to be pushed
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(7 downto 0) = "00000000" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
if ea(7) = '1' then
next_state <= pshu_pcl_state;
elsif ea(6) = '1' then
next_state <= pshu_spl_state;
elsif ea(5) = '1' then
next_state <= pshu_iyl_state;
elsif ea(4) = '1' then
next_state <= pshu_ixl_state;
elsif ea(3) = '1' then
next_state <= pshu_dp_state;
elsif ea(2) = '1' then
next_state <= pshu_accb_state;
elsif ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
next_state <= fetch_state;
end if;
--
-- push PC onto U stack
--
when pshu_pcl_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
up_ctrl <= load_up;
-- write pc low
addr_ctrl <= pushu_ad;
dout_ctrl <= pc_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= pshu_pch_state;
when pshu_pch_state =>
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(6 downto 0) = "0000000" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write pc hi
addr_ctrl <= pushu_ad;
dout_ctrl <= pc_hi_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
if ea(6) = '1' then
next_state <= pshu_spl_state;
elsif ea(5) = '1' then
next_state <= pshu_iyl_state;
elsif ea(4) = '1' then
next_state <= pshu_ixl_state;
elsif ea(3) = '1' then
next_state <= pshu_dp_state;
elsif ea(2) = '1' then
next_state <= pshu_accb_state;
elsif ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
next_state <= fetch_state;
end if;
when pshu_spl_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
up_ctrl <= load_up;
-- write pc low
addr_ctrl <= pushu_ad;
dout_ctrl <= sp_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= pshu_sph_state;
when pshu_sph_state =>
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(5 downto 0) = "000000" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write sp hi
addr_ctrl <= pushu_ad;
dout_ctrl <= sp_hi_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
if ea(5) = '1' then
next_state <= pshu_iyl_state;
elsif ea(4) = '1' then
next_state <= pshu_ixl_state;
elsif ea(3) = '1' then
next_state <= pshu_dp_state;
elsif ea(2) = '1' then
next_state <= pshu_accb_state;
elsif ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
next_state <= fetch_state;
end if;
when pshu_iyl_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
up_ctrl <= load_up;
-- write iy low
addr_ctrl <= pushu_ad;
dout_ctrl <= iy_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= pshu_iyh_state;
when pshu_iyh_state =>
-- default registers
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(4 downto 0) = "00000" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write iy hi
addr_ctrl <= pushu_ad;
dout_ctrl <= iy_hi_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
if ea(4) = '1' then
next_state <= pshu_ixl_state;
elsif ea(3) = '1' then
next_state <= pshu_dp_state;
elsif ea(2) = '1' then
next_state <= pshu_accb_state;
elsif ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
next_state <= fetch_state;
end if;
when pshu_ixl_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
up_ctrl <= load_up;
-- write ix low
addr_ctrl <= pushu_ad;
dout_ctrl <= ix_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= pshu_ixh_state;
when pshu_ixh_state =>
-- default registers
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(3 downto 0) = "0000" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write ix hi
addr_ctrl <= pushu_ad;
dout_ctrl <= ix_hi_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
if ea(3) = '1' then
next_state <= pshu_dp_state;
elsif ea(2) = '1' then
next_state <= pshu_accb_state;
elsif ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
next_state <= fetch_state;
end if;
when pshu_dp_state =>
-- default registers
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(2 downto 0) = "000" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write accb
addr_ctrl <= pushu_ad;
dout_ctrl <= dp_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
if ea(2) = '1' then
next_state <= pshu_accb_state;
elsif ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
next_state <= fetch_state;
end if;
when pshu_accb_state =>
-- default registers
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(1 downto 0) = "00" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write accb
addr_ctrl <= pushu_ad;
dout_ctrl <= accb_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
if ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
next_state <= fetch_state;
end if;
when pshu_acca_state =>
-- default registers
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(0) = '0' then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write acca
addr_ctrl <= pushu_ad;
dout_ctrl <= acca_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
if ea(0) = '1' then
next_state <= pshu_cc_state;
else
next_state <= fetch_state;
end if;
when pshu_cc_state =>
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- idle up
left_ctrl <= up_left;
right_ctrl <= one_right;
cc_ctrl <= latch_cc;
alu_ctrl <= alu_nop;
up_ctrl <= latch_up;
-- write cc
addr_ctrl <= pushu_ad;
dout_ctrl <= cc_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
--
-- enter here on PULU
-- ea hold register mask
--
when pulu_state =>
-- default registers
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- idle UP
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= latch_up;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
if ea(0) = '1' then
next_state <= pulu_cc_state;
elsif ea(1) = '1' then
next_state <= pulu_acca_state;
elsif ea(2) = '1' then
next_state <= pulu_accb_state;
elsif ea(3) = '1' then
next_state <= pulu_dp_state;
elsif ea(4) = '1' then
next_state <= pulu_ixh_state;
elsif ea(5) = '1' then
next_state <= pulu_iyh_state;
elsif ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
next_state <= fetch_state;
end if;
when pulu_cc_state =>
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read cc
cc_ctrl <= pull_cc;
addr_ctrl <= pullu_ad;
dout_ctrl <= cc_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
if ea(1) = '1' then
next_state <= pulu_acca_state;
elsif ea(2) = '1' then
next_state <= pulu_accb_state;
elsif ea(3) = '1' then
next_state <= pulu_dp_state;
elsif ea(4) = '1' then
next_state <= pulu_ixh_state;
elsif ea(5) = '1' then
next_state <= pulu_iyh_state;
elsif ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
next_state <= fetch_state;
end if;
when pulu_acca_state =>
-- default registers
cc_ctrl <= latch_cc;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read acca
acca_ctrl <= pull_acca;
addr_ctrl <= pullu_ad;
dout_ctrl <= acca_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
if ea(2) = '1' then
next_state <= pulu_accb_state;
elsif ea(3) = '1' then
next_state <= pulu_dp_state;
elsif ea(4) = '1' then
next_state <= pulu_ixh_state;
elsif ea(5) = '1' then
next_state <= pulu_iyh_state;
elsif ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
next_state <= fetch_state;
end if;
when pulu_accb_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read accb
accb_ctrl <= pull_accb;
addr_ctrl <= pullu_ad;
dout_ctrl <= accb_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
if ea(3) = '1' then
next_state <= pulu_dp_state;
elsif ea(4) = '1' then
next_state <= pulu_ixh_state;
elsif ea(5) = '1' then
next_state <= pulu_iyh_state;
elsif ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
next_state <= fetch_state;
end if;
when pulu_dp_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read dp
dp_ctrl <= pull_dp;
addr_ctrl <= pullu_ad;
dout_ctrl <= dp_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
if ea(4) = '1' then
next_state <= pulu_ixh_state;
elsif ea(5) = '1' then
next_state <= pulu_iyh_state;
elsif ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
next_state <= fetch_state;
end if;
when pulu_ixh_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- pull ix hi
ix_ctrl <= pull_hi_ix;
addr_ctrl <= pullu_ad;
dout_ctrl <= ix_hi_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= pulu_ixl_state;
when pulu_ixl_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read ix low
ix_ctrl <= pull_lo_ix;
addr_ctrl <= pullu_ad;
dout_ctrl <= ix_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
if ea(5) = '1' then
next_state <= pulu_iyh_state;
elsif ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
next_state <= fetch_state;
end if;
when pulu_iyh_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- pull iy hi
iy_ctrl <= pull_hi_iy;
addr_ctrl <= pullu_ad;
dout_ctrl <= iy_hi_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= pulu_iyl_state;
when pulu_iyl_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read iy low
iy_ctrl <= pull_lo_iy;
addr_ctrl <= pullu_ad;
dout_ctrl <= iy_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
if ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
next_state <= fetch_state;
end if;
when pulu_sph_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- pull sp hi
sp_ctrl <= pull_hi_sp;
addr_ctrl <= pullu_ad;
dout_ctrl <= up_hi_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= pulu_spl_state;
when pulu_spl_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read sp low
sp_ctrl <= pull_lo_sp;
addr_ctrl <= pullu_ad;
dout_ctrl <= up_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
if ea(7) = '1' then
next_state <= pulu_pch_state;
else
next_state <= fetch_state;
end if;
when pulu_pch_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- pull pc hi
pc_ctrl <= pull_hi_pc;
addr_ctrl <= pullu_ad;
dout_ctrl <= pc_hi_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= pulu_pcl_state;
when pulu_pcl_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read pc low
pc_ctrl <= pull_lo_pc;
addr_ctrl <= pullu_ad;
dout_ctrl <= pc_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
--
-- pop the Condition codes
--
when rti_cc_state =>
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read cc
cc_ctrl <= pull_cc;
addr_ctrl <= pulls_ad;
dout_ctrl <= cc_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= rti_entire_state;
--
-- Added RTI cycle 11th July 2006 John Kent.
-- test the "Entire" Flag
-- that has just been popped off the stack
--
when rti_entire_state =>
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- idle sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_nop;
sp_ctrl <= latch_sp;
-- idle cc
cc_ctrl <= latch_cc;
addr_ctrl <= idle_ad;
dout_ctrl <= cc_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
--
-- The Entire flag must be recovered from the stack
-- before testing.
--
if cc(EBIT) = '1' then
next_state <= rti_acca_state;
else
next_state <= rti_pch_state;
end if;
when rti_acca_state =>
-- default registers
cc_ctrl <= latch_cc;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read acca
acca_ctrl <= pull_acca;
addr_ctrl <= pulls_ad;
dout_ctrl <= acca_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= rti_accb_state;
when rti_accb_state =>
-- default registers
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read accb
accb_ctrl <= pull_accb;
addr_ctrl <= pulls_ad;
dout_ctrl <= accb_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= rti_dp_state;
when rti_dp_state =>
-- default registers
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read dp
dp_ctrl <= pull_dp;
addr_ctrl <= pulls_ad;
dout_ctrl <= dp_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= rti_ixh_state;
when rti_ixh_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read ix hi
ix_ctrl <= pull_hi_ix;
addr_ctrl <= pulls_ad;
dout_ctrl <= ix_hi_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= rti_ixl_state;
when rti_ixl_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read ix low
ix_ctrl <= pull_lo_ix;
addr_ctrl <= pulls_ad;
dout_ctrl <= ix_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= rti_iyh_state;
when rti_iyh_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read iy hi
iy_ctrl <= pull_hi_iy;
addr_ctrl <= pulls_ad;
dout_ctrl <= iy_hi_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= rti_iyl_state;
when rti_iyl_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read iy low
iy_ctrl <= pull_lo_iy;
addr_ctrl <= pulls_ad;
dout_ctrl <= iy_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= rti_uph_state;
when rti_uph_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read up hi
up_ctrl <= pull_hi_up;
addr_ctrl <= pulls_ad;
dout_ctrl <= up_hi_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= rti_upl_state;
when rti_upl_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
iy_ctrl <= latch_iy;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read up low
up_ctrl <= pull_lo_up;
addr_ctrl <= pulls_ad;
dout_ctrl <= up_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= rti_pch_state;
when rti_pch_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- pull pc hi
pc_ctrl <= pull_hi_pc;
addr_ctrl <= pulls_ad;
dout_ctrl <= pc_hi_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= rti_pcl_state;
when rti_pcl_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- pull pc low
pc_ctrl <= pull_lo_pc;
addr_ctrl <= pulls_ad;
dout_ctrl <= pc_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
--
-- here on IRQ, NMI or FIRQ interrupt
-- pre decrement the sp
--
when int_decr_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= pc_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= int_entire_state;
--
-- set Entire Flag on SWI, SWI2, SWI3 and CWAI, IRQ and NMI
-- clear Entire Flag on FIRQ
-- before stacking all registers
--
when int_entire_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
--
left_ctrl <= sp_left;
right_ctrl <= zero_right;
if iv = FIRQ_VEC then
-- clear entire flag
alu_ctrl <= alu_cle;
else
-- set entire flag
alu_ctrl <= alu_see;
end if;
cc_ctrl <= load_cc;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= pc_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= int_pcl_state;
when int_pcl_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write pc low
addr_ctrl <= pushs_ad;
dout_ctrl <= pc_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= int_pch_state;
when int_pch_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write pc hi
addr_ctrl <= pushs_ad;
dout_ctrl <= pc_hi_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
if cc(EBIT) = '1' then
next_state <= int_upl_state;
else
next_state <= int_cc_state;
end if;
when int_upl_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write up low
addr_ctrl <= pushs_ad;
dout_ctrl <= up_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= int_uph_state;
when int_uph_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write ix hi
addr_ctrl <= pushs_ad;
dout_ctrl <= up_hi_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= int_iyl_state;
when int_iyl_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write ix low
addr_ctrl <= pushs_ad;
dout_ctrl <= iy_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= int_iyh_state;
when int_iyh_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write ix hi
addr_ctrl <= pushs_ad;
dout_ctrl <= iy_hi_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= int_ixl_state;
when int_ixl_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write ix low
addr_ctrl <= pushs_ad;
dout_ctrl <= ix_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= int_ixh_state;
when int_ixh_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write ix hi
addr_ctrl <= pushs_ad;
dout_ctrl <= ix_hi_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= int_dp_state;
when int_dp_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write accb
addr_ctrl <= pushs_ad;
dout_ctrl <= dp_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= int_accb_state;
when int_accb_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write accb
addr_ctrl <= pushs_ad;
dout_ctrl <= accb_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= int_acca_state;
when int_acca_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write acca
addr_ctrl <= pushs_ad;
dout_ctrl <= acca_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= int_cc_state;
when int_cc_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
iv_ctrl <= latch_iv;
ea_ctrl <= latch_ea;
-- idle sp
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
sp_ctrl <= latch_sp;
-- write cc
addr_ctrl <= pushs_ad;
dout_ctrl <= cc_dout;
nmi_ctrl <= latch_nmi;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
case iv is
when NMI_VEC =>
next_state <= int_mask_state;
when SWI_VEC =>
next_state <= int_mask_state;
when IRQ_VEC =>
next_state <= int_mask_state;
when SWI2_VEC =>
next_state <= vect_hi_state;
when FIRQ_VEC =>
next_state <= int_mask_state;
when SWI3_VEC =>
next_state <= vect_hi_state;
when others =>
if op_code = "00111100" then -- CWAI
next_state <= int_cwai_state;
else
next_state <= rti_cc_state; -- spurious interrupt, do a RTI
end if;
end case;
--
-- wait here for an inteerupt
--
when int_cwai_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
--
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= cc_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
--
if (nmi_req = '1') and (nmi_ack = '0') then
iv_ctrl <= nmi_iv;
nmi_ctrl <= set_nmi;
next_state <= vect_hi_state;
else
--
-- nmi request is not cleared until nmi input goes low
--
if (nmi_req = '0') and (nmi_ack = '1') then
nmi_ctrl <= reset_nmi;
else
nmi_ctrl <= latch_nmi;
end if;
--
-- IRQ is level sensitive
--
if (irq = '1') and (cc(IBIT) = '0') then
iv_ctrl <= irq_iv;
next_state <= int_mask_state;
elsif (firq = '1') and (cc(FBIT) = '0') then
--
-- FIRQ is level sensitive
--
iv_ctrl <= firq_iv;
next_state <= int_mask_state;
else
iv_ctrl <= latch_iv;
next_state <= int_cwai_state;
end if;
end if;
when int_mask_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- Mask IRQ and FIRQ
left_ctrl <= sp_left;
right_ctrl <= zero_right;
--
-- FIRQ can interrupt an IRQ service routine
--
if iv = IRQ_VEC then
alu_ctrl <= alu_sei;
else
alu_ctrl <= alu_seif;
end if;
cc_ctrl <= load_cc;
sp_ctrl <= latch_sp;
-- idle bus cycle
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= vect_hi_state;
--
-- According to the 6809 programming manual:
-- If an interrupt is received and is masked
-- or lasts for less than three cycles, the PC
-- will advance to the next instruction.
-- If an interrupt is unmasked and lasts
-- for more than three cycles, an interrupt
-- will be generated.
-- Note that I don't wait 3 clock cycles.
-- John Kent 11th July 2006
--
when sync_state =>
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
--
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_nop;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= cc_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
--
if (nmi_req = '1') and (nmi_ack = '0') then
iv_ctrl <= nmi_iv;
nmi_ctrl <= set_nmi;
next_state <= int_decr_state;
else
--
-- nmi request is not cleared until nmi input goes low
--
if (nmi_req = '0') and (nmi_ack = '1') then
nmi_ctrl <= reset_nmi;
else
nmi_ctrl <= latch_nmi;
end if;
--
-- IRQ is level sensitive
--
if (irq = '1') then
iv_ctrl <= irq_iv;
if (cc(IBIT) = '0') then
next_state <= int_decr_state;
else
next_state <= fetch_state;
end if;
elsif (firq = '1') then
--
-- FIRQ is level sensitive
--
iv_ctrl <= firq_iv;
if (cc(FBIT) = '0') then
next_state <= int_decr_state;
else
next_state <= fetch_state;
end if;
else
iv_ctrl <= latch_iv;
next_state <= sync_state;
end if;
end if;
when halt_state =>
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- idle ALU
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
sp_ctrl <= latch_sp;
-- idle bus cycle
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
--
if halt = '1' then -- there was a bug there : if halt <= '1'
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= halt_state;
else
st_ctrl <= pull_st;
return_state <= fetch_state;
next_state <= saved_state;
end if;
when others => -- halt on undefine states
-- default
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- do nothing in ALU
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
-- idle bus cycle
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
--
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= error_state;
end case;
end process;
end CPU_ARCH;
| gpl-3.0 | bceb54673d90393322aa4813cd2f45fe | 0.398484 | 3.906992 | false | false | false | false |
muhd7rosli/mblite-vivado | mblite_ip/src/vhdl/core/execute.vhd | 1 | 10,832 | ----------------------------------------------------------------------------------------------
-- This file is part of mblite_ip.
--
-- mblite_ip is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- mblite_ip is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with mblite_ip. If not, see <http://www.gnu.org/licenses/>.
--
-- Input file : execute.vhd
-- Design name : execute
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : The Execution Unit performs all arithmetic operations and makes
-- the branch decision. Furthermore the forwarding logic is located
-- here. Everything is computed within a single clock-cycle
--
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library mblite;
use mblite.config_pkg.all;
use mblite.core_pkg.all;
use mblite.std_pkg.all;
entity execute is generic
(
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL
);
port
(
exec_o : out execute_out_type;
exec_i : in execute_in_type;
ena_i : in std_logic;
rst_i : in std_logic;
clk_i : in std_logic
);
end execute;
architecture arch of execute is
type execute_reg_type is record
carry : std_logic;
flush_ex : std_logic;
end record;
signal r, rin : execute_out_type;
signal reg, regin : execute_reg_type;
begin
exec_o <= r;
execute_comb: process(exec_i,exec_i.fwd_mem,exec_i.ctrl_ex,
exec_i.ctrl_wrb,exec_i.ctrl_mem,
exec_i.ctrl_mem.transfer_size,
exec_i.ctrl_mem_wrb,exec_i.fwd_dec,
r,r.ctrl_mem,r.ctrl_mem.transfer_size,
r.ctrl_wrb,reg)
variable v : execute_out_type;
variable v_reg : execute_reg_type;
variable alu_src_a : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
variable alu_src_b : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
variable carry : std_logic;
variable result : std_logic_vector(CFG_DMEM_WIDTH downto 0);
variable result_add : std_logic_vector(CFG_DMEM_WIDTH downto 0);
variable zero : std_logic;
variable dat_a, dat_b : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
variable sel_dat_a, sel_dat_b, sel_dat_d : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
variable mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
begin
v := r;
sel_dat_a := select_register_data(exec_i.dat_a, exec_i.reg_a, exec_i.fwd_dec_result, forward_condition(exec_i.fwd_dec.reg_write, exec_i.fwd_dec.reg_d, exec_i.reg_a));
sel_dat_b := select_register_data(exec_i.dat_b, exec_i.reg_b, exec_i.fwd_dec_result, forward_condition(exec_i.fwd_dec.reg_write, exec_i.fwd_dec.reg_d, exec_i.reg_b));
sel_dat_d := select_register_data(exec_i.dat_d, exec_i.ctrl_wrb.reg_d, exec_i.fwd_dec_result, forward_condition(exec_i.fwd_dec.reg_write, exec_i.fwd_dec.reg_d, exec_i.ctrl_wrb.reg_d));
if reg.flush_ex = '1' then
v.ctrl_mem.mem_write := '0';
v.ctrl_mem.mem_read := '0';
v.ctrl_wrb.reg_write := '0';
v.ctrl_wrb.reg_d := (others => '0');
else
v.ctrl_mem := exec_i.ctrl_mem;
v.ctrl_wrb := exec_i.ctrl_wrb;
end if;
if exec_i.ctrl_mem_wrb.mem_read = '1' then
mem_result := align_mem_load(exec_i.mem_result, exec_i.ctrl_mem_wrb.transfer_size, exec_i.alu_result(1 downto 0));
else
mem_result := exec_i.alu_result;
end if;
if forward_condition(r.ctrl_wrb.reg_write, r.ctrl_wrb.reg_d, exec_i.reg_a) = '1' then
-- Forward Execution Result to REG a
dat_a := r.alu_result;
elsif forward_condition(exec_i.fwd_mem.reg_write, exec_i.fwd_mem.reg_d, exec_i.reg_a) = '1' then
-- Forward Memory Result to REG a
dat_a := mem_result;
else
-- DEFAULT: value of REG a
dat_a := sel_dat_a;
end if;
if forward_condition(r.ctrl_wrb.reg_write, r.ctrl_wrb.reg_d, exec_i.reg_b) = '1' then
-- Forward (latched) Execution Result to REG b
dat_b := r.alu_result;
elsif forward_condition(exec_i.fwd_mem.reg_write, exec_i.fwd_mem.reg_d, exec_i.reg_b) = '1' then
-- Forward Memory Result to REG b
dat_b := mem_result;
else
-- DEFAULT: value of REG b
dat_b := sel_dat_b;
end if;
if forward_condition(r.ctrl_wrb.reg_write, r.ctrl_wrb.reg_d, exec_i.ctrl_wrb.reg_d) = '1' then
-- Forward Execution Result to REG d
v.dat_d := align_mem_store(r.alu_result, exec_i.ctrl_mem.transfer_size);
elsif forward_condition(exec_i.fwd_mem.reg_write, exec_i.fwd_mem.reg_d, exec_i.ctrl_wrb.reg_d) = '1' then
-- Forward Memory Result to REG d
v.dat_d := align_mem_store(mem_result, exec_i.ctrl_mem.transfer_size);
else
-- DEFAULT: value of REG d
v.dat_d := align_mem_store(sel_dat_d, exec_i.ctrl_mem.transfer_size);
end if;
-- Set the first operand of the ALU
case exec_i.ctrl_ex.alu_src_a is
when ALU_SRC_PC => alu_src_a := sign_extend(exec_i.program_counter, '0', 32);
when ALU_SRC_NOT_REGA => alu_src_a := not dat_a;
when ALU_SRC_ZERO => alu_src_a := (others => '0');
when others => alu_src_a := dat_a;
end case;
-- Set the second operand of the ALU
case exec_i.ctrl_ex.alu_src_b is
when ALU_SRC_IMM => alu_src_b := exec_i.imm;
when ALU_SRC_NOT_IMM => alu_src_b := not exec_i.imm;
when ALU_SRC_NOT_REGB => alu_src_b := not dat_b;
when others => alu_src_b := dat_b;
end case;
-- Determine value of carry in
case exec_i.ctrl_ex.carry is
when CARRY_ALU => carry := reg.carry;
when CARRY_ONE => carry := '1';
when CARRY_ARITH => carry := alu_src_a(CFG_DMEM_WIDTH - 1);
when others => carry := '0';
end case;
result_add := add(alu_src_a, alu_src_b, carry);
case exec_i.ctrl_ex.alu_op is
when ALU_ADD => result := result_add;
when ALU_OR => result := '0' & (alu_src_a or alu_src_b);
when ALU_AND => result := '0' & (alu_src_a and alu_src_b);
when ALU_XOR => result := '0' & (alu_src_a xor alu_src_b);
when ALU_SHIFT => result := alu_src_a(0) & carry & alu_src_a(CFG_DMEM_WIDTH - 1 downto 1);
when ALU_SEXT8 => result := '0' & sign_extend(alu_src_a(7 downto 0), alu_src_a(7), 32);
when ALU_SEXT16 => result := '0' & sign_extend(alu_src_a(15 downto 0), alu_src_a(15), 32);
when ALU_MUL =>
if G_USE_HW_MUL = true then
result := '0' & multiply(alu_src_a, alu_src_b);
else
result := (others => '0');
end if;
when ALU_BS =>
if G_USE_BARREL = true then
result := '0' & shift(alu_src_a, alu_src_b(4 downto 0), exec_i.imm(10), exec_i.imm(9));
else
result := (others => '0');
end if;
when others =>
result := (others => '0');
--report "Invalid ALU operation" severity FAILURE;
end case;
-- Set carry register
if exec_i.ctrl_ex.carry_keep = CARRY_KEEP then
v_reg.carry := reg.carry;
else
v_reg.carry := result(CFG_DMEM_WIDTH);
end if;
zero := is_zero(dat_a);
-- Overwrite branch condition
if reg.flush_ex = '1' then
v.branch := '0';
else
-- Determine branch condition
case exec_i.ctrl_ex.branch_cond is
when BNC => v.branch := '1';
when BEQ => v.branch := zero;
when BNE => v.branch := not zero;
when BLT => v.branch := dat_a(CFG_DMEM_WIDTH - 1);
when BLE => v.branch := dat_a(CFG_DMEM_WIDTH - 1) or zero;
when BGT => v.branch := not (dat_a(CFG_DMEM_WIDTH - 1) or zero);
when BGE => v.branch := not dat_a(CFG_DMEM_WIDTH - 1);
when others => v.branch := '0';
end case;
end if;
-- Handle CMPU
if ( exec_i.ctrl_ex.operation and not (alu_src_a(CFG_DMEM_WIDTH - 1) xor alu_src_b(CFG_DMEM_WIDTH - 1))) = '1' then
-- Set MSB
v.alu_result(CFG_DMEM_WIDTH - 1 downto 0) := (not result(CFG_DMEM_WIDTH - 1)) & result(CFG_DMEM_WIDTH - 2 downto 0);
else
-- Use ALU result
v.alu_result := result(CFG_DMEM_WIDTH - 1 downto 0);
end if;
v.program_counter := exec_i.program_counter;
-- Determine flush signals
v.flush_id := v.branch;
v_reg.flush_ex := v.branch and not exec_i.ctrl_ex.delay;
rin <= v;
regin <= v_reg;
end process;
execute_seq: process(clk_i)
procedure proc_execute_reset is
begin
r.alu_result <= (others => '0');
r.dat_d <= (others => '0');
r.branch <= '0';
r.program_counter <= (others => '0');
r.flush_id <= '0';
r.ctrl_mem.mem_write <= '0';
r.ctrl_mem.mem_read <= '0';
r.ctrl_mem.transfer_size <= WORD;
r.ctrl_wrb.reg_d <= (others => '0');
r.ctrl_wrb.reg_write <= '0';
reg.carry <= '0';
reg.flush_ex <= '0';
end procedure proc_execute_reset;
begin
if rising_edge(clk_i) then
if rst_i = '1' then
proc_execute_reset;
elsif ena_i = '1' then
r <= rin;
reg <= regin;
end if;
end if;
end process;
end arch;
| lgpl-3.0 | 51fb018307ba61b086e6d0b218f88785 | 0.525849 | 3.421352 | false | false | false | false |
muhd7rosli/mblite-vivado | mblite_ip/src/vhdl/core/fetch.vhd | 1 | 2,828 | ----------------------------------------------------------------------------------------------
-- This file is part of mblite_ip.
--
-- mblite_ip is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- mblite_ip is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with mblite_ip. If not, see <http://www.gnu.org/licenses/>.
--
-- Input file : fetch.vhd
-- Design name : fetch
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Instruction Fetch Stage inserts instruction into the pipeline. It
-- uses a single port Random Access Memory component which holds
-- the instructions. The next instruction is computed in the decode
-- stage.
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library mblite;
use mblite.config_pkg.all;
use mblite.core_pkg.all;
use mblite.std_pkg.all;
entity fetch is port
(
fetch_o : out fetch_out_type;
imem_o : out imem_out_type;
fetch_i : in fetch_in_type;
rst_i : in std_logic;
ena_i : in std_logic;
clk_i : in std_logic
);
end fetch;
architecture arch of fetch is
signal r, rin : fetch_out_type;
begin
fetch_o.program_counter <= r.program_counter;
imem_o.adr_o <= rin.program_counter;
imem_o.ena_o <= ena_i;
fetch_comb: process(fetch_i, r, rst_i)
variable v : fetch_out_type;
begin
v := r;
if rst_i = '1' then
v.program_counter := (OTHERS => '0');
elsif fetch_i.hazard = '1' then
v.program_counter := r.program_counter;
elsif fetch_i.branch = '1' then
v.program_counter := fetch_i.branch_target;
else
v.program_counter := increment(r.program_counter(CFG_IMEM_SIZE - 1 downto 2)) & "00";
end if;
rin <= v;
end process;
fetch_seq: process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
r.program_counter <= (others => '0');
elsif ena_i = '1' then
r <= rin;
end if;
end if;
end process;
end arch;
| lgpl-3.0 | c903bf721bbd63a5806ebd868a02b18f | 0.56471 | 3.933241 | false | false | false | false |
chibby0ne/vhdl-book | Chapter11/example3_dir/src/counter.vhd | 1 | 2,591 | --!
--! Copyright (C) 2010 - 2013 Creonic GmbH
--!
--! @file: counter.vhd
--! @brief:
--! @author: Antonio Gutierrez
--! @date: 2014-05-23
--!
--!
--------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------
entity counter is
--generic declarations
port (
clk, rst: in std_logic;
output: out natural range 0 to 9);
end entity counter;
--------------------------------------------------------
architecture circuit of counter is
type state is (zero, one, two, three, four, five, six, seven, eight, nine);
signal pr_state, nx_state: state;
attribute enum_encoding: string;
attribute enum_encoding of state: type is "sequential";
begin
--------------------------------------------------------------------------------------
-- lower section of fsm (sequential)
--------------------------------------------------------------------------------------
process (clk, rst)
--declarativepart
begin
if (rst = '1') then
pr_state <= zero;
elsif (clk'event and clk = '1') then
pr_state <= nx_state;
end if;
end process;
--------------------------------------------------------------------------------------
-- upper section of fsm (combinational)
--------------------------------------------------------------------------------------
process (pr_state)
--declarativepart
begin
case pr_state is
when zero =>
output <= 0;
nx_state <= one;
when one =>
output <= 1;
nx_state <= two;
when two =>
output <= 2;
nx_state <= three;
when three =>
output <= 3;
nx_state <= four;
when four =>
output <= 4;
nx_state <= five;
when five =>
output <= 5;
nx_state <= six;
when six =>
output <= 6;
nx_state <= seven;
when seven =>
output <= 7;
nx_state <= eight;
when eight =>
output <= 8;
nx_state <= nine;
when nine =>
output <= 9;
nx_state <= zero;
end case;
end process;
end architecture circuit;
--------------------------------------------------------
| gpl-3.0 | 6d84cc52f966af3e63b407722e35f9fc | 0.355847 | 5.584052 | false | false | false | false |
VLSI-EDA/UVVM_All | uvvm_vvc_framework/src/ti_generic_queue_pkg.vhd | 1 | 49,633 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
package ti_generic_queue_pkg is
generic (type t_generic_element;
scope : string := C_SCOPE;
GC_QUEUE_COUNT_MAX : natural := 1000;
GC_QUEUE_COUNT_THRESHOLD : natural := 950);
-- When find_* doesn't find a match, they return C_NO_MATCH.
constant C_NO_MATCH : integer := -1;
-- A generic queue for verification
type t_generic_queue is protected
procedure add(
constant instance : in integer;
constant element : in t_generic_element);
procedure add(
constant element : in t_generic_element);
procedure put(
constant instance : in integer;
constant element : in t_generic_element);
procedure put(
constant element : in t_generic_element);
impure function get(
constant instance : in integer)
return t_generic_element;
impure function get(
constant dummy : in t_void)
return t_generic_element;
impure function is_empty(
constant instance : in integer)
return boolean;
impure function is_empty(
constant dummy : in t_void)
return boolean;
procedure set_scope(
constant instance : in integer;
constant scope : in string);
procedure set_scope(
constant scope : in string);
procedure set_name(
constant name : in string);
impure function get_scope(
constant instance : in integer)
return string;
impure function get_scope(
constant dummy : in t_void)
return string;
impure function get_count(
constant instance : in integer)
return natural;
impure function get_count(
constant dummy : in t_void)
return natural;
procedure set_queue_count_threshold(
constant instance : in integer;
constant queue_count_alert_level : in natural);
procedure set_queue_count_threshold(
constant queue_count_alert_level : in natural);
impure function get_queue_count_threshold(
constant instance : in integer) return natural;
impure function get_queue_count_threshold(
constant dummy : in t_void) return natural;
impure function get_queue_count_threshold_severity(
constant dummy : in t_void) return t_alert_level;
procedure set_queue_count_threshold_severity(
constant alert_level : in t_alert_level);
impure function get_queue_count_max(
constant instance : in integer) return natural;
impure function get_queue_count_max(
constant dummy : in t_void) return natural;
procedure set_queue_count_max(
constant instance : in integer;
constant queue_count_max : in natural);
procedure set_queue_count_max(
constant queue_count_max : in natural);
procedure flush(
constant instance : in integer);
procedure flush(
constant dummy : in t_void);
procedure reset(
constant instance : in integer);
procedure reset(
constant dummy : in t_void);
procedure insert(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant element : in t_generic_element);
procedure insert(
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant element : in t_generic_element);
procedure delete(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier_min : in positive;
constant identifier_max : in positive);
procedure delete(
constant identifier_option : in t_identifier_option;
constant identifier_min : in positive;
constant identifier_max : in positive);
procedure delete(
constant instance : in integer;
constant element : in t_generic_element
);
procedure delete(
constant element : in t_generic_element
);
procedure delete(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant range_option : in t_range_option
);
procedure delete(
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant range_option : in t_range_option
);
impure function peek(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element;
impure function peek(
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element;
impure function peek(
constant instance : in integer
) return t_generic_element;
impure function peek(
constant dummy : in t_void
) return t_generic_element;
impure function fetch(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element;
impure function fetch(
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element;
impure function fetch(
constant instance : in integer
) return t_generic_element;
impure function fetch(
constant dummy : in t_void
) return t_generic_element;
impure function find_position(
constant element : in t_generic_element) return integer;
impure function find_position(
constant instance : in integer;
constant element : in t_generic_element) return integer;
impure function find_entry_num(
constant element : in t_generic_element) return integer;
impure function find_entry_num(
constant instance : in integer;
constant element : in t_generic_element) return integer;
impure function exists(
constant instance : in integer;
constant element : in t_generic_element
) return boolean;
impure function exists(
constant element : in t_generic_element
) return boolean;
impure function get_entry_num(
constant instance : in integer;
constant position_val : in positive) return integer;
impure function get_entry_num(
constant position_val : in positive) return integer;
procedure print_queue(
constant instance : in integer);
procedure print_queue(
constant dummy : in t_void);
end protected;
end package ti_generic_queue_pkg;
package body ti_generic_queue_pkg is
type t_generic_queue is protected body
-- Types and control variables for the linked list implementation
type t_element;
type t_element_ptr is access t_element;
type t_element is
record
entry_num : natural;
next_element : t_element_ptr;
element_data : t_generic_element;
end record;
type t_element_ptr_array is array(integer range 0 to C_MAX_QUEUE_INSTANCE_NUM) of t_element_ptr;
type t_string_array is array(integer range 0 to C_MAX_QUEUE_INSTANCE_NUM) of string(1 to C_LOG_SCOPE_WIDTH);
variable vr_last_element : t_element_ptr_array := (others => null); -- Back entry
variable vr_first_element : t_element_ptr_array := (others => null); -- Front entry
variable vr_num_elements_in_queue : integer_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => 0);
-- Scope variables
variable vr_scope : t_string_array := (others => (others => NUL));
variable vr_scope_is_defined : boolean_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => false);
-- Name variables
variable vr_name : string(1 to C_LOG_SCOPE_WIDTH) := (others => NUL);
variable vr_name_is_defined : boolean := false;
variable vr_queue_count_max : integer_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => GC_QUEUE_COUNT_MAX);
variable vr_queue_count_threshold : integer_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => GC_QUEUE_COUNT_THRESHOLD);
variable vr_queue_count_threshold_severity : t_alert_level := TB_WARNING;
variable vr_entry_num : integer_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => 0); -- Incremented before first insert
-- Fill level alert
type t_queue_count_threshold_alert_frequency is (ALWAYS, FIRST_TIME_ONLY);
constant C_ALERT_FREQUENCY : t_queue_count_threshold_alert_frequency := FIRST_TIME_ONLY;
variable vr_queue_count_threshold_triggered : boolean_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => false);
------------------------------------------------------------------------------------------------------
--
-- Helper methods (not visible from outside)
--
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
-- Helper method: Check if an Alert shall be triggered (to be called before adding another entry)
------------------------------------------------------------------------------------------------------
procedure perform_pre_add_checks (
constant instance : in integer
) is
begin
if((vr_queue_count_threshold(instance) /= 0) and (vr_num_elements_in_queue(instance) >= vr_queue_count_threshold(instance))) then
if((C_ALERT_FREQUENCY = ALWAYS) or (C_ALERT_FREQUENCY = FIRST_TIME_ONLY and not vr_queue_count_threshold_triggered(instance))) then
alert(vr_queue_count_threshold_severity, "Queue is now at " & to_string(vr_queue_count_threshold(instance)) & " of " & to_string(vr_queue_count_max(instance)) & " elements.", vr_scope(instance));
vr_queue_count_threshold_triggered(instance) := true;
end if;
end if;
end procedure;
------------------------------------------------------------------------------------------------------
-- Helper method: Iterate through all entries, and match the one with element_data = element
-- This also works if the element is a record or array, whereas all entries/indexes must match
------------------------------------------------------------------------------------------------------
procedure match_element_data (
instance : in integer; -- Queue instance
element : in t_generic_element; -- Element to search for
found_match : out boolean; -- True if a match was found.
matched_position : out integer; -- valid if found_match=true
matched_element_ptr : out t_element_ptr -- valid if found_match=true
) is
variable v_position_ctr : integer := 1; -- Keep track of POSITION when traversing the linked list
variable v_element_ptr : t_element_ptr; -- Entry currently being checked for match
begin
-- Default
found_match := false;
matched_position := C_NO_MATCH;
matched_element_ptr := null;
if vr_num_elements_in_queue(instance) > 0 then
-- Search from front to back element
v_element_ptr := vr_first_element(instance);
loop
if v_element_ptr.element_data = element then -- Element matched entry
found_match := true;
matched_position := v_position_ctr;
matched_element_ptr := v_element_ptr;
exit;
else -- No match.
if v_element_ptr.next_element = null then
exit; -- Last entry. All queue entries have been searched through.
end if;
v_element_ptr := v_element_ptr.next_element; -- next queue entry
v_position_ctr := v_position_ctr + 1;
end if;
end loop;
end if;
end procedure;
-- Find and return entry that matches the identifier
procedure match_identifier (
instance : in integer; -- Queue instance
identifier_option : in t_identifier_option; -- Determines what 'identifier' means
identifier : in positive; -- Identifier value to search for
found_match : out boolean; -- True if a match was found.
matched_position : out integer; -- valid if found_match=true
matched_element_ptr : out t_element_ptr; -- valid if found_match=true
preceding_element_ptr : out t_element_ptr -- valid if found_match=true. Element at position-1, pointing to elemnt_ptr
) is
-- Search from front to back element. Init pointers/counters to the first entry:
variable v_element_ptr : t_element_ptr := vr_first_element(instance); -- Entry currently being checked for match
variable v_position_ctr : integer := 1; -- Keep track of POSITION when traversing the linked list
begin
-- Default
found_match := false;
matched_position := C_NO_MATCH;
matched_element_ptr := null;
preceding_element_ptr := null;
-- If queue is not empty and indentifier in valid range
if (vr_num_elements_in_queue(instance) > 0) and
((identifier_option = POSITION and identifier <= vr_num_elements_in_queue(instance)) or
(identifier_option = ENTRY_NUM and identifier <= vr_entry_num(instance))) then
loop
-- For each element in queue:
-- Check if POSITION or ENTRY_NUM matches v_element_ptr
if (identifier_option = POSITION) and (v_position_ctr = identifier) then
found_match := true;
end if;
if (identifier_option = ENTRY_NUM) and (v_element_ptr.entry_num = identifier) then
found_match := true;
end if;
if found_match then
-- This element matched. Done searching.
matched_position := v_position_ctr;
matched_element_ptr := v_element_ptr;
exit;
else
-- No match.
if v_element_ptr.next_element = null then
-- report "last v_position_ctr = " & to_string(v_position_ctr);
exit; -- Last entry. All queue entries have been searched through.
end if;
preceding_element_ptr := v_element_ptr; -- the entry at the postition before element_ptr
v_element_ptr := v_element_ptr.next_element; -- next queue entry
v_position_ctr := v_position_ctr + 1;
end if;
end loop; -- for each element in queue
end if; -- Not empty
end procedure;
------------------------------------------------------------------------------------------------------
--
-- Public methods, visible from outside
--
------------------------------------------------------------------------------------------------------
-- add : Insert element in the back of queue, i.e. at the highest position
procedure add(
constant instance : in integer;
constant element : in t_generic_element
) is
constant proc_name : string := "add";
variable v_previous_ptr : t_element_ptr;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, proc_name & ": Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
perform_pre_add_checks(instance);
check_value(vr_num_elements_in_queue(instance) < vr_queue_count_max(instance), TB_ERROR, proc_name & "() into generic queue (of size " & to_string(vr_queue_count_max(instance)) & ") when full", vr_scope(instance), ID_NEVER);
-- Increment vr_entry_num
vr_entry_num(instance) := vr_entry_num(instance)+1;
-- Set read and write pointers when appending element to existing list
if vr_num_elements_in_queue(instance) > 0 then
v_previous_ptr := vr_last_element(instance);
vr_last_element(instance) := new t_element'(entry_num => vr_entry_num(instance), next_element => null, element_data => element);
v_previous_ptr.next_element := vr_last_element(instance); -- Insert the new element into the linked list
else -- List is empty
vr_last_element(instance) := new t_element'(entry_num => vr_entry_num(instance), next_element => null, element_data => element);
vr_first_element(instance) := vr_last_element(instance); -- Update read pointer, since this is the first and only element in the list.
end if;
-- Increment number of elements
vr_num_elements_in_queue(instance) := vr_num_elements_in_queue(instance) + 1;
end procedure;
procedure add(
constant element : in t_generic_element
) is
begin
add(1, element);
end procedure;
procedure put(
constant instance : in integer;
constant element : in t_generic_element
) is
begin
add(instance, element);
end procedure;
procedure put(
constant element : in t_generic_element
) is
begin
put(1, element);
end procedure;
impure function get(
constant instance : in integer
) return t_generic_element is
begin
return fetch(instance);
end function;
impure function get(
constant dummy : in t_void
) return t_generic_element is
begin
return get(1);
end function;
procedure flush(
constant instance : in integer
) is
variable v_to_be_deallocated_ptr : t_element_ptr;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, "Scope name must be defined for this generic queue " &to_string(instance), "???", ID_NEVER);
-- Deallocate all entries in the list
-- Setting the last element to null and iterating over the queue until finding the null element
vr_last_element(instance) := null;
while vr_first_element(instance) /= null loop
v_to_be_deallocated_ptr := vr_first_element(instance);
vr_first_element(instance) := vr_first_element(instance).next_element;
DEALLOCATE(v_to_be_deallocated_ptr);
end loop;
-- Reset the queue counter
vr_num_elements_in_queue(instance) := 0;
vr_queue_count_threshold_triggered(instance) := false;
end procedure;
procedure flush(
constant dummy : in t_void
) is
begin
flush(1);
end procedure;
procedure reset(
constant instance : in integer) is
begin
flush(instance);
vr_entry_num(instance) := 0; -- Incremented before first insert
end procedure;
procedure reset(
constant dummy : in t_void) is
begin
reset(1);
end procedure;
impure function is_empty(
constant instance : in integer
) return boolean is
begin
if vr_num_elements_in_queue(instance) = 0 then
return true;
else
return false;
end if;
end function;
impure function is_empty(
constant dummy : in t_void
) return boolean is
begin
return is_empty(1);
end function;
procedure set_scope(
constant instance : in integer;
constant scope : in string) is
begin
if instance = ALL_INSTANCES then
if scope'length > C_LOG_SCOPE_WIDTH then
vr_scope := (others => scope(1 to C_LOG_SCOPE_WIDTH));
else
for idx in vr_scope'range loop
vr_scope(idx) := (others => NUL);
vr_scope(idx)(1 to scope'length) := scope;
end loop;
end if;
vr_scope_is_defined := (others => true);
else
if scope'length > C_LOG_SCOPE_WIDTH then
vr_scope(instance) := scope(1 to C_LOG_SCOPE_WIDTH);
else
vr_scope(instance) := (others => NUL);
vr_scope(instance)(1 to scope'length) := scope;
end if;
vr_scope_is_defined(instance) := true;
end if;
end procedure;
procedure set_scope(
constant scope : in string) is
begin
set_scope(1, scope);
end procedure;
procedure set_name(
constant name : in string) is
begin
vr_name(1 to name'length) := name;
vr_name_is_defined := true;
end procedure;
impure function get_scope(
constant instance : in integer
) return string is
begin
return to_string(vr_scope(instance));
end function;
impure function get_scope(
constant dummy : in t_void
) return string is
begin
return get_scope(1);
end function;
impure function get_count(
constant instance : in integer
) return natural is
begin
return vr_num_elements_in_queue(instance);
end function;
impure function get_count(
constant dummy : in t_void
) return natural is
begin
return get_count(1);
end function;
impure function get_queue_count_max(
constant instance : in integer
) return natural is
begin
return vr_queue_count_max(instance);
end function;
impure function get_queue_count_max(
constant dummy : in t_void
) return natural is
begin
return get_queue_count_max(1);
end function;
procedure set_queue_count_max(
constant instance : in integer;
constant queue_count_max : in natural
) is
begin
vr_queue_count_max(instance) := queue_count_max;
check_value(vr_num_elements_in_queue(instance) < vr_queue_count_max(instance), TB_ERROR, "set_queue_count_max() new queue max count (" & to_string(vr_queue_count_max(instance)) & ") is less than current queue count(" & to_string(vr_num_elements_in_queue(instance)) & ").", vr_scope(instance), ID_NEVER);
end procedure;
procedure set_queue_count_max(
constant queue_count_max : in natural
) is
begin
set_queue_count_max(1, queue_count_max);
end procedure;
procedure set_queue_count_threshold(
constant instance : in integer;
constant queue_count_alert_level : in natural
) is
begin
vr_queue_count_threshold(instance) := queue_count_alert_level;
end procedure;
procedure set_queue_count_threshold(
constant queue_count_alert_level : in natural
) is
begin
set_queue_count_threshold(1, queue_count_alert_level);
end procedure;
impure function get_queue_count_threshold(
constant instance : in integer
) return natural is
begin
return vr_queue_count_threshold(instance);
end function;
impure function get_queue_count_threshold(
constant dummy : in t_void
) return natural is
begin
return get_queue_count_threshold(1);
end function;
impure function get_queue_count_threshold_severity(
constant dummy : in t_void
) return t_alert_level is
begin
return vr_queue_count_threshold_severity;
end function;
procedure set_queue_count_threshold_severity(
constant alert_level : in t_alert_level) is
begin
vr_queue_count_threshold_severity := alert_level;
end procedure;
----------------------------------------------------
-- Insert:
----------------------------------------------------
-- Inserts element into the queue after the matching entry with specified identifier:
--
-- When identifier_option = POSITION:
-- identifier = position in queue, counting from 1
--
-- When identifier_option = ENTRY_NUM:
-- identifier = entry number, counting from 1
procedure insert(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant element : in t_generic_element)
is
constant proc_name : string := "insert";
variable v_element_ptr : t_element_ptr; -- The element currently being processed
variable v_new_element_ptr : t_element_ptr; -- Used when creating a new element
variable v_preceding_element_ptr : t_element_ptr; -- Used when creating a new element
variable v_found_match : boolean;
variable v_matched_position : integer;
begin
-- pre insert checks
check_value(vr_scope_is_defined(instance), TB_WARNING, proc_name & ": Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
perform_pre_add_checks(instance);
check_value(vr_num_elements_in_queue(instance) < vr_queue_count_max(instance), TB_ERROR, proc_name & "() into generic queue (of size " & to_string(vr_queue_count_max(instance)) & ") when full", vr_scope(instance), ID_NEVER);
check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, proc_name & "() into empty queue isn't supported. Use add() instead", vr_scope(instance), ID_NEVER);
if identifier_option = POSITION then
check_value(vr_num_elements_in_queue(instance) >= identifier, TB_ERROR, proc_name & "() into position larger than number of elements in queue. Use add() instead when inserting at the back of the queue", vr_scope(instance), ID_NEVER);
end if;
-- Search from front to back element.
match_identifier(
instance => instance ,
identifier_option => identifier_option ,
identifier => identifier ,
found_match => v_found_match ,
matched_position => v_matched_position ,
matched_element_ptr => v_element_ptr ,
preceding_element_ptr => v_preceding_element_ptr
);
if v_found_match then
-- Make new element
vr_entry_num(instance) := vr_entry_num(instance)+1; -- Increment vr_entry_num
-- POSITION: insert at matched position
if identifier_option = POSITION then
v_new_element_ptr := new t_element'(entry_num => vr_entry_num(instance),
next_element => v_element_ptr,
element_data => element);
-- if match is first element
if v_preceding_element_ptr = null then
vr_first_element(instance) := v_new_element_ptr; -- Insert the new element into the front of the linked list
else
v_preceding_element_ptr.next_element := v_new_element_ptr; -- Insert the new element into the linked list
end if;
--ENTRY_NUM: insert at position after match
else
v_new_element_ptr := new t_element'(entry_num => vr_entry_num(instance),
next_element => v_element_ptr.next_element,
element_data => element);
v_element_ptr.next_element := v_new_element_ptr; -- Insert the new element into the linked list
end if;
vr_num_elements_in_queue(instance) := vr_num_elements_in_queue(instance) + 1; -- Increment number of elements
elsif identifier_option = ENTRY_NUM then
if (vr_num_elements_in_queue(instance) > 0) then -- if not already reported tb_error due to empty
tb_error(proc_name & "() did not match an element in queue. It was called with the following parameters: " &
"instance=" & to_string(instance) &
", identifier_option=" & t_identifier_option'image(identifier_option) &
", identifier=" & to_string(identifier) &
", element...", scope);
end if;
end if;
end procedure;
procedure insert(
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant element : in t_generic_element) is
begin
insert(1, identifier_option, identifier, element);
end procedure;
----------------------------------------------------
-- delete:
----------------------------------------------------
-- Read and remove the entry matching the identifier
--
-- When identifier_option = POSITION:
-- identifier = position in queue, counting from 1
--
-- When identifier_option = ENTRY_NUM:
-- identifier = entry number, counting from 1
procedure delete(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier_min : in positive;
constant identifier_max : in positive
) is
constant proc_name : string := "delete";
variable v_matched_element_ptr : t_element_ptr; -- The element being deleted
variable v_element_to_delete_ptr : t_element_ptr; -- The element being deleted
variable v_matched_element_data : t_generic_element; -- Return value
variable v_preceding_element_ptr : t_element_ptr;
variable v_matched_position : integer;
variable v_found_match : boolean;
variable v_deletes_remaining : integer;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, proc_name & ": Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
if(vr_num_elements_in_queue(instance) < vr_queue_count_threshold(instance)) then
-- reset alert trigger if set
vr_queue_count_threshold_triggered(instance) := false;
end if;
-- delete based on POSITION :
-- Note that when deleting the first position, all above positions are decremented by one.
-- Find the identifier_min, delete it, and following next_element until we reach number of positions to delete
if (identifier_option = POSITION) then
check_value(vr_num_elements_in_queue(instance) >= identifier_max, TB_ERROR, proc_name & " where identifier_max > generic queue size", vr_scope(instance), ID_NEVER);
check_value(identifier_max >= identifier_min, TB_ERROR, "Check that identifier_max >= identifier_min", vr_scope(instance), ID_NEVER);
v_deletes_remaining := 1 + identifier_max - identifier_min;
-- Find min position
match_identifier(
instance => instance ,
identifier_option => identifier_option ,
identifier => identifier_min,
found_match => v_found_match ,
matched_position => v_matched_position ,
matched_element_ptr => v_matched_element_ptr ,
preceding_element_ptr => v_preceding_element_ptr
);
if v_found_match then
v_element_to_delete_ptr := v_matched_element_ptr; -- Delete element at identifier_min first
while v_deletes_remaining > 0 loop
-- Update pointer to the element about to be removed.
if (v_preceding_element_ptr = null) then -- Removing the first entry,
vr_first_element(instance) := vr_first_element(instance).next_element;
else -- Removing an intermediate or last entry
v_preceding_element_ptr.next_element := v_element_to_delete_ptr.next_element;
end if;
-- Decrement number of elements
vr_num_elements_in_queue(instance) := vr_num_elements_in_queue(instance) - 1;
-- Memory management
DEALLOCATE(v_element_to_delete_ptr);
v_deletes_remaining := v_deletes_remaining - 1;
-- Prepare next iteration:
-- Next element to delete:
if v_deletes_remaining > 0 then
if (v_preceding_element_ptr = null) then
-- We just removed the first entry, so there's no pointer from a preceding entry. Next to delete is the first entry.
v_element_to_delete_ptr := vr_first_element(instance);
else -- Removed an intermediate or last entry. Next to delete is the pointer from the preceding element
v_element_to_delete_ptr := v_preceding_element_ptr.next_element;
end if;
end if;
end loop;
else -- v_found_match
if (vr_num_elements_in_queue(instance) > 0) then -- if not already reported tb_error due to empty
tb_error(proc_name & "() did not match an element in queue. It was called with the following parameters: " &
"instance=" & to_string(instance) &
", identifier_option=" & t_identifier_option'image(identifier_option) &
", identifier_min=" & to_string(identifier_min) &
", identifier_max=" & to_string(identifier_max) &
", non-matching identifier=" & to_string(identifier_min), scope);
end if;
end if; -- v_found_match
-- delete based on ENTRY_NUM :
-- Unlike position, an entry's Entry_num is stable when deleting other entries
-- Entry_num is not necessarily increasing as we follow next_element pointers.
-- This means that we must do a complete search for each entry we want to delete
elsif (identifier_option = ENTRY_NUM) then
check_value(vr_entry_num(instance) >= identifier_max, TB_ERROR, proc_name & " where identifier_max > highest entry number", vr_scope(instance), ID_NEVER);
check_value(identifier_max >= identifier_min, TB_ERROR, "Check that identifier_max >= identifier_min", vr_scope(instance), ID_NEVER);
v_deletes_remaining := 1 + identifier_max - identifier_min;
-- For each entry to delete, find it based on entry_num , then delete it
for identifier in identifier_min to identifier_max loop
match_identifier(
instance => instance ,
identifier_option => identifier_option ,
identifier => identifier,
found_match => v_found_match ,
matched_position => v_matched_position ,
matched_element_ptr => v_matched_element_ptr ,
preceding_element_ptr => v_preceding_element_ptr
);
if v_found_match then
v_element_to_delete_ptr := v_matched_element_ptr;
-- Update pointer to the element about to be removed.
if (v_preceding_element_ptr = null) then -- Removing the first entry,
vr_first_element(instance) := vr_first_element(instance).next_element;
else -- Removing an intermediate or last entry
v_preceding_element_ptr.next_element := v_element_to_delete_ptr.next_element;
end if;
-- Decrement number of elements
vr_num_elements_in_queue(instance) := vr_num_elements_in_queue(instance) - 1;
-- Memory management
DEALLOCATE(v_element_to_delete_ptr);
else -- v_found_match
if (vr_num_elements_in_queue(instance) > 0) then -- if not already reported tb_error due to empty
tb_error(proc_name & "() did not match an element in queue. It was called with the following parameters: " &
"instance=" & to_string(instance) &
", identifier_option=" & t_identifier_option'image(identifier_option) &
", identifier_min=" & to_string(identifier_min) &
", identifier_max=" & to_string(identifier_max) &
", non-matching identifier=" & to_string(identifier), scope);
end if;
end if; -- v_found_match
end loop;
end if; -- identifier_option
end procedure;
procedure delete(
constant identifier_option : in t_identifier_option;
constant identifier_min : in positive;
constant identifier_max : in positive
) is
begin
delete(1, identifier_option, identifier_min, identifier_max);
end procedure;
procedure delete(
constant instance : in integer;
constant element : in t_generic_element
) is
variable v_entry_num : integer:= find_entry_num(element);
begin
delete(instance, POSITION, v_entry_num, v_entry_num);
end procedure;
procedure delete(
constant element : in t_generic_element
) is
begin
delete(1, element);
end procedure;
procedure delete(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant range_option : in t_range_option
) is
begin
case range_option is
when SINGLE =>
delete(instance, identifier_option, identifier, identifier);
when AND_LOWER =>
delete(instance, identifier_option, 1, identifier);
when AND_HIGHER =>
if identifier_option = POSITION then
delete(instance, identifier_option, identifier, vr_num_elements_in_queue(instance));
elsif identifier_option = ENTRY_NUM then
delete(instance, identifier_option, identifier, vr_entry_num(instance));
end if;
end case;
end procedure;
procedure delete(
constant identifier_option : in t_identifier_option;
constant identifier : in positive;
constant range_option : in t_range_option
) is
begin
delete(1, identifier_option, identifier, range_option);
end procedure;
----------------------------------------------------
-- peek:
----------------------------------------------------
-- Read the entry matching the identifier, but don't remove it.
--
-- When identifier_option = POSITION:
-- identifier = position in queue, counting from 1
--
-- When identifier_option = ENTRY_NUM:
-- identifier = entry number, counting from 1
impure function peek(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element is
constant proc_name : string := "peek";
variable v_matched_element_data : t_generic_element; -- Return value
variable v_matched_element_ptr : t_element_ptr; -- The element currently being processed
variable v_preceding_element_ptr : t_element_ptr;
variable v_matched_position : integer; -- Keep track of POSITION when traversing the linked list
variable v_found_match : boolean := false;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, proc_name & ": Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, proc_name & "() from generic queue when empty", vr_scope(instance), ID_NEVER);
match_identifier(
instance => instance ,
identifier_option => identifier_option ,
identifier => identifier ,
found_match => v_found_match ,
matched_position => v_matched_position ,
matched_element_ptr => v_matched_element_ptr ,
preceding_element_ptr => v_preceding_element_ptr
);
if v_found_match then
v_matched_element_data := v_matched_element_ptr.element_data;
else
if (vr_num_elements_in_queue(instance) > 0) then -- if not already reported tb_error due to empty
tb_error(proc_name & "() did not match an element in queue. It was called with the following parameters: " &
"instance=" & to_string(instance) &
", identifier_option=" & t_identifier_option'image(identifier_option) &
", identifier=" & to_string(identifier), scope);
end if;
end if;
return v_matched_element_data;
end function;
impure function peek(
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element is
begin
return peek(1, identifier_option, identifier);
end function;
-- If no identifier is specified, return the oldest entry (first position)
impure function peek(
constant instance : in integer
) return t_generic_element is
begin
return peek(instance, POSITION, 1);
end function;
impure function peek(
constant dummy : in t_void
) return t_generic_element is
begin
return peek(1);
end function;
----------------------------------------------------
-- Fetch:
----------------------------------------------------
-- Read and remove the entry matching the identifier
--
-- When identifier_option = POSITION:
-- identifier = position in queue, counting from 1
--
-- When identifier_option = ENTRY_NUM:
-- identifier = entry number, counting from 1
impure function fetch(
constant instance : in integer;
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element is
constant proc_name : string := "fetch";
variable v_matched_element_ptr : t_element_ptr; -- The element being fetched
variable v_matched_element_data : t_generic_element; -- Return value
variable v_preceding_element_ptr : t_element_ptr;
variable v_matched_position : integer;
variable v_found_match : boolean;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, proc_name & ": Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, proc_name & "() from generic queue when empty", vr_scope(instance), ID_NEVER);
if(vr_num_elements_in_queue(instance) < vr_queue_count_threshold(instance)) then
-- reset alert trigger if set
vr_queue_count_threshold_triggered(instance) := false;
end if;
match_identifier(
instance => instance ,
identifier_option => identifier_option ,
identifier => identifier ,
found_match => v_found_match ,
matched_position => v_matched_position ,
matched_element_ptr => v_matched_element_ptr ,
preceding_element_ptr => v_preceding_element_ptr
);
if v_found_match then
-- Keep info about element before removing it from queue
v_matched_element_data := v_matched_element_ptr.element_data;
-- Update pointer to the element about to be removed.
if (v_preceding_element_ptr = null) then -- Removing the first entry,
vr_first_element(instance) := vr_first_element(instance).next_element;
else -- Removing an intermediate or last entry
v_preceding_element_ptr.next_element := v_matched_element_ptr.next_element;
end if;
-- Decrement number of elements
vr_num_elements_in_queue(instance) := vr_num_elements_in_queue(instance) - 1;
-- Memory management
DEALLOCATE(v_matched_element_ptr);
else
if (vr_num_elements_in_queue(instance) > 0) then -- if not already reported tb_error due to empty
tb_error(proc_name & "() did not match an element in queue. It was called with the following parameters: " &
"instance=" & to_string(instance) &
", identifier_option=" & t_identifier_option'image(identifier_option) &
", identifier=" & to_string(identifier), scope);
end if;
end if;
return v_matched_element_data;
end function;
impure function fetch(
constant identifier_option : in t_identifier_option;
constant identifier : in positive
) return t_generic_element is
begin
return fetch(1, identifier_option, identifier);
end function;
-- If no identifier is specified, return the oldest entry (first position)
impure function fetch(
constant instance : in integer
) return t_generic_element is
begin
return fetch(instance, POSITION, 1);
end function;
impure function fetch(
constant dummy : in t_void
) return t_generic_element is
begin
return fetch(1);
end function;
-- Returns position of entry if found, else C_NO_MATCH.
impure function find_position(
constant instance : in integer;
constant element : in t_generic_element --
) return integer is
variable v_element_ptr : t_element_ptr;
variable v_matched_position : integer;
variable v_found_match : boolean;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, "find_position: Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
-- Don't include this check, because we may want to use exists() on an empty queue.
-- check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, "find_position() from generic queue when empty", vr_scope(instance), ID_NEVER);
match_element_data(
instance => instance,
element => element,
found_match => v_found_match,
matched_position => v_matched_position,
matched_element_ptr => v_element_ptr
);
if v_found_match then
return v_matched_position;
else
return C_NO_MATCH;
end if;
end function;
impure function find_position(
constant element : in t_generic_element
) return integer is
begin
return find_position(1, element);
end function;
impure function exists(
constant instance : in integer;
constant element : in t_generic_element
) return boolean is
begin
return (find_position(instance, element) /= C_NO_MATCH);
end function;
impure function exists(
constant element : in t_generic_element
) return boolean is
begin
return exists(1, element);
end function;
-- Returns entry number or position to entry if found, else C_NO_MATCH.
impure function find_entry_num(
constant instance : in integer;
constant element : in t_generic_element
) return integer is
variable v_element_ptr : t_element_ptr;
variable v_matched_position : integer;
variable v_found_match : boolean;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, "find_entry_num(): Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, "find_entry_num() from generic queue when empty", vr_scope(instance), ID_NEVER);
match_element_data(
instance => instance,
element => element,
found_match => v_found_match,
matched_position => v_matched_position,
matched_element_ptr => v_element_ptr
);
if v_found_match then
return v_element_ptr.entry_num;
else
return C_NO_MATCH;
end if;
end function;
impure function find_entry_num(
constant element : in t_generic_element
) return integer is
begin
return find_entry_num(1, element);
end function;
impure function get_entry_num(
constant instance : in integer;
constant position_val : in positive
) return integer is
variable v_found_match : boolean;
variable v_matched_position : integer;
variable v_matched_element_ptr : t_element_ptr;
variable v_preceding_element_ptr : t_element_ptr;
begin
check_value(vr_scope_is_defined(instance), TB_WARNING, "get_entry_num(): Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER);
check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, "get_entry_num() from generic queue when empty", vr_scope(instance), ID_NEVER);
match_identifier(
instance => instance ,
identifier_option => POSITION ,
identifier => position_val,
found_match => v_found_match ,
matched_position => v_matched_position ,
matched_element_ptr => v_matched_element_ptr ,
preceding_element_ptr => v_preceding_element_ptr
);
if v_found_match then
return v_matched_element_ptr.entry_num;
else
return -1;
end if;
end function get_entry_num;
impure function get_entry_num(
constant position_val : in positive
) return integer is
begin
return get_entry_num(1, position_val);
end function get_entry_num;
-- for debugging:
-- print each entry's position and entry_num
procedure print_queue(
constant instance : in integer
)
is
variable v_element_ptr : t_element_ptr; -- The element currently being processed
variable v_new_element_ptr : t_element_ptr; -- Used when creating a new element
variable v_position_ctr : natural := 1; -- Keep track of POSITION when traversing the linked list
variable v_found_match : boolean := false;
begin
-- Search from front to back element. Initalise pointers/counters to the first entry:
v_element_ptr := vr_first_element(instance);
loop
log(ID_UVVM_DATA_QUEUE, "Pos=" & to_string(v_position_ctr) & ", entry_num=" & to_string(v_element_ptr.entry_num) , scope);
if v_element_ptr.next_element = null then
exit; -- Last entry. All queue entries have been searched through.
end if;
v_element_ptr := v_element_ptr.next_element; -- next queue entry
v_position_ctr := v_position_ctr + 1;
end loop;
end procedure;
procedure print_queue(
constant dummy : in t_void) is
begin
print_queue(1);
end procedure;
end protected body;
end package body ti_generic_queue_pkg;
| mit | a136c38c43c96d35098ace82a267acac | 0.622952 | 4.189499 | false | false | false | false |
chibby0ne/vhdl-book | Chapter7/exercise7_11_dir/exercise7_11.vhd | 1 | 1,928 | --!
--! @file: exercise7_9.vhd
--! @brief: frequency divider with symmetric phase
--! @author: Antonio Gutierrez
--! @date: 2013-10-29
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity freq_divider is
generic (M: integer := 4;);
port (
clkin: in std_logic;
clkout: out std_logic);
end entity freq_divider;
--------------------------------------
architecture circuit of freq_divider is
--signals and declarations
begin
proc: process (clk)
variable counter: integer range 0 to M := 0;
begin
-- if M is even
if (M % 2 = 0) then
if (clk'event and clk = '1') then
counter := counter + 1;
if (counter = M/2) then -- if we reach the middle of the cycle flip bit
clkout <= '1';
elsif (counter = M) then -- if we reach full cycle flip bit again and reset count
counter := 0;
clkout <= '0';
end if;
end if;
else
-- if M is odd
if (clk'event) then
if (clk = '1') then -- if it is a rising edge, increment count
counter := counter + 1;
if (counter = M) then -- check if we reached M then reset count and flip output
counter := 0;
clkout <= '0';
end if;
elsif (clk = '0' and counter = M/2) then -- if it's falling edge and counter is half way (we are in the middle of the cycle), flip output
clkout <= '1';
end if;
end if;
end if;
end process proc;
end architecture circuit;
--------------------------------------
| gpl-3.0 | d2cb69588db4868a1c68bfa3018a90eb | 0.442427 | 4.748768 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/plasma.vhd | 1 | 24,383 | ---------------------------------------------------------------------
-- TITLE: Plasma (CPU core with memory)
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 6/4/02
-- FILENAME: plasma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity combines the CPU core with memory and a UART.
--
-- Memory Map:
-- 0x00000000 - 0x0000ffff Internal RAM (8KB) - 0000 0000 0000
-- 0x10000000 - 0x100fffff External RAM (1MB) - 0001 0000 0000
-- Access all Misc registers with 32-bit accesses
-- 0x20000000 Uart Write (will pause CPU if busy)
-- 0x20000000 Uart Read
-- 0x20000010 IRQ Mask
-- 0x20000020 IRQ Status
-- 0x20000030 GPIO0 Out Set bits
-- 0x20000040 GPIO0 Out Clear bits
-- 0x20000050 GPIOA In
-- 0x20000060 Counter
-- 0x20000070 Ethernet transmit count
-- IRQ bits:
-- 7 GPIO31
-- 6 ^GPIO31
-- 5 EthernetSendDone
-- 4 EthernetReceive
-- 3 Counter(18)
-- 2 ^Counter(18)
-- 1 ^UartWriteBusy
-- 0 UartDataAvailable
-- 0x30000000 FIFO IN EMPTY
-- 0x30000010 FIFO OUT EMPTY
-- 0x30000020 FIFO IN VALID
-- 0x30000030 FIFO OUT VALID
-- 0x30000040 FIFO IN FULL
-- 0x30000050 FIFO IN FULL
-- 0x30000060 FIFO IN COUNTER
-- 0x30000070 FIFO OUT COUNTER
-- 0x30000080 FIFO IN READ DATA
-- 0x30000090 FIFO OUT WRITE DATA
-- 0x40000000 COPROCESSOR 1 (reset)
-- 0x40000010 COPROCESSOR 1 (input/output)
-- 0x40000030 COPROCESSOR 2 (reset)
-- 0x40000040 COPROCESSOR 2 (input/output)
-- 0x40000060 COPROCESSOR 3 (reset)
-- 0x40000070 COPROCESSOR 3 (input/output)
-- 0x40000090 COPROCESSOR 4 (reset)
-- 0x400000A0 COPROCESSOR 4 (input/output)
-- 0x80000000 DMA ENGINE (NOT WORKING YET)
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity plasma is
generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0';
eUart : std_logic := '0';
use_cache : std_logic := '0';
plasma_code : string
);
port(clk : in std_logic;
--clk_VGA : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
--data_write : out std_logic_vector(31 downto 0);
--data_read : in std_logic_vector(31 downto 0);
---mem_pause_in : in std_logic;
no_ddr_start : out std_logic;
no_ddr_stop : out std_logic;
-- BLG START
fifo_1_out_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
fifo_1_read_en : OUT STD_LOGIC;
fifo_1_empty : IN STD_LOGIC;
fifo_2_in_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
fifo_1_write_en : OUT STD_LOGIC;
fifo_2_full : IN STD_LOGIC;
fifo_1_full : IN STD_LOGIC;
fifo_1_valid : IN STD_LOGIC;
fifo_2_empty : IN STD_LOGIC;
fifo_2_valid : IN STD_LOGIC;
fifo_1_compteur : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
fifo_2_compteur : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- BLG END
--VGA_hs : out std_logic; -- horisontal vga syncr.
-- VGA_vs : out std_logic; -- vertical vga syncr.
data_enable :out std_logic;
ADDR : out std_logic_vector(16 downto 0);
data_out : out std_logic_vector(11 downto 0);
--VGA_green : out std_logic_vector(3 downto 0); -- green output
--VGA_blue : out std_logic_vector(3 downto 0); -- blue output
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0));
end; --entity plasma
architecture logic of plasma is
signal address_next : std_logic_vector(31 downto 2);
signal byte_we_next : std_logic_vector(3 downto 0);
signal cpu_address : std_logic_vector(31 downto 0);
signal cpu_byte_we : std_logic_vector(3 downto 0);
signal cpu_data_w : std_logic_vector(31 downto 0);
signal cpu_data_r : std_logic_vector(31 downto 0);
signal cpu_pause : std_logic;
signal ppcie_rdata : std_logic_vector(31 downto 0);
signal data_read_uart : std_logic_vector(7 downto 0);
signal write_enable : std_logic;
signal eth_pause_in : std_logic;
signal eth_pause : std_logic;
signal mem_busy : std_logic;
signal enable_misc : std_logic;
signal enable_uart : std_logic;
signal enable_uart_read : std_logic;
signal enable_uart_write : std_logic;
signal enable_eth : std_logic;
signal enable_local_mem : std_logic;
signal gpio0_reg : std_logic_vector(31 downto 0);
signal uart_write_busy : std_logic;
signal uart_data_avail : std_logic;
signal irq_mask_reg : std_logic_vector(7 downto 0);
signal irq_status : std_logic_vector(7 downto 0);
signal irq : std_logic;
signal irq_eth_rec : std_logic;
signal irq_eth_send : std_logic;
signal counter_reg : std_logic_vector(31 downto 0);
signal ram_boot_enable : std_logic;
signal ram_enable : std_logic;
signal ram_byte_we : std_logic_vector( 3 downto 0);
signal ram_address : std_logic_vector(31 downto 2);
signal ram_data_w : std_logic_vector(31 downto 0);
signal ram_data_r : std_logic_vector(31 downto 0);
signal ram_data_lm : std_logic_vector(31 downto 0);
signal dma_address : std_logic_vector(31 downto 0);
signal dma_byte_we : std_logic_vector( 3 downto 0);
signal dma_data_write : std_logic_vector(31 downto 0);
signal dma_data_read : std_logic_vector(31 downto 0);
signal dma_start : std_logic;
signal cop_1_reset : std_logic;
signal cop_1_valid : std_logic;
signal cop_1_output : std_logic_vector(31 downto 0);
signal cop_2_reset : std_logic;
signal cop_2_valid : std_logic;
signal cop_2_output : std_logic_vector(31 downto 0);
signal cop_3_reset : std_logic;
signal cop_3_valid : std_logic;
signal cop_3_output : std_logic_vector(31 downto 0);
signal cop_4_reset : std_logic;
signal cop_4_valid : std_logic;
signal cop_4_output : std_logic_vector(31 downto 0);
signal cache_access : std_logic;
signal cache_checking : std_logic;
signal cache_miss : std_logic;
signal cache_hit : std_logic;
COMPONENT memory_64k
Port ( clk : in STD_LOGIC;
addr_in : in STD_LOGIC_VECTOR (31 downto 2);
data_in : in STD_LOGIC_VECTOR (31 downto 0);
enable : in STD_LOGIC;
we_select : in STD_LOGIC_VECTOR (3 downto 0);
data_out : out STD_LOGIC_VECTOR (31 downto 0));
end COMPONENT;
begin --architecture
write_enable <= '1' when cpu_byte_we /= "0000" else '0';
mem_busy <= eth_pause;-- or mem_pause_in;
cache_hit <= cache_checking and not cache_miss;
cpu_pause <= (uart_write_busy and enable_uart and write_enable) --UART busy
-- or cache_miss --Cache wait
-- or (cpu_address(31) and not cache_hit and mem_busy); --DDR or flash
or (eth_pause); -- DMA ENGINE FREEZE ALL (BLG)
irq_status <= gpioA_in(31) & not gpioA_in(31) &
irq_eth_send & irq_eth_rec &
counter_reg(18) & not counter_reg(18) &
not uart_write_busy & uart_data_avail;
irq <= '1' when (irq_status and irq_mask_reg) /= ZERO(7 downto 0) else '0';
gpio0_out(31 downto 29) <= gpio0_reg(31 downto 29);
gpio0_out(23 downto 0) <= gpio0_reg(23 downto 0);
enable_misc <= '1' when cpu_address(30 downto 28) = "010" else '0';
enable_uart <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0000" else '0';
enable_uart_read <= enable_uart and not write_enable;
enable_uart_write <= enable_uart and write_enable;
enable_eth <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0111" else '0';
cpu_address(1 downto 0) <= "00";
--
-- ON GENERE LES SIGNAUX DE COMMANDE EN DIRECTION DU PORT PCIe
--
--fifo_1_read_en <= '1' when ((cpu_address(31 downto 28) = "0011") AND (cpu_address(7 downto 4) = "1000") ) else '0';
--fifo_1_write_en <= '1' when ((cpu_address(31 downto 28) = "0011") AND (cpu_address(7 downto 4) = "1001") AND (write_enable = '1')) else '0';
fifo_1_read_en <= '1' when (cpu_address = x"30000080") AND (cpu_pause = '0') else '0';
fifo_1_write_en <= '1' when (cpu_address = x"30000090") AND (cpu_pause = '0') AND(write_enable = '1') else '0';
cop_1_reset <= '1' when (cpu_address = x"40000000") AND (cpu_pause = '0') AND (write_enable = '1') else '0';
cop_1_valid <= '1' when (cpu_address = x"40000004") AND (cpu_pause = '0') AND (write_enable = '1') else '0';
cop_2_reset <= '1' when (cpu_address = x"40000030") AND (cpu_pause = '0') AND (write_enable = '1') else '0';
cop_2_valid <= '1' when (cpu_address = x"40000034") AND (cpu_pause = '0') AND (write_enable = '1') else '0';
cop_3_reset <= '1' when (cpu_address = x"40000060") AND (cpu_pause = '0') AND (write_enable = '1') else '0';
cop_3_valid <= '1' when (cpu_address = x"40000064") AND (cpu_pause = '0') AND (write_enable = '1') else '0';
cop_4_reset <= '1' when (cpu_address = x"40000090") AND (cpu_pause = '0') AND (write_enable = '1') else '0';
cop_4_valid <= '1' when (cpu_address = x"40000094") AND (cpu_pause = '0') AND (write_enable = '1') else '0';
-- assert cop_4_valid /= '1' severity failure;
--
-- ON LIT/ECRIT DANS LA MEMOIRE LOCALE UNIQUEMENT LORSQUE LE BUS
-- D'ADRESSE (MSB) = "001". SINON ON ADRESSE UN AUTRE PERIPHERIQUE
--
--dram_procr: process(clk)
--begin
-- if rising_edge(clk) then
-- ppcie_rdata <= pcie_rdata;
-- end if;
--end process;
--
-- INTERNAL RAM MEMORY (64ko)
--
-- enable_local_mem <= '1' when (cpu_address(31 downto 28) = "0001") else '0';
-- enable_local_mem <= '1' when (ram_address(31 downto 28) = "0001") else '0';
local_memory: memory_64k
port map (
clk => clk,
addr_in => ram_address, --cpu_data_r,
data_in => ram_data_w,
enable => enable_local_mem,
we_select => ram_byte_we,
data_out => ram_data_lm
);
--
--
--
u1_cpu: mlite_cpu
generic map (memory_type => memory_type)
PORT MAP (
clk => clk,
reset_in => reset,
intr_in => irq,
address_next => address_next, --before rising_edge(clk)
byte_we_next => byte_we_next,
address => cpu_address(31 downto 2), --after rising_edge(clk)
byte_we => cpu_byte_we,
data_w => cpu_data_w,
data_r => cpu_data_r,
mem_pause => cpu_pause);
--
--
--
opt_cache: if use_cache = '0' generate
cache_access <= '0';
cache_checking <= '0';
cache_miss <= '0';
end generate;
--
--
--
opt_cache2: if use_cache = '1' generate
--Control 4KB unified cache that uses the upper 4KB of the 8KB
--internal RAM. Only lowest 2MB of DDR is cached.
u_cache: cache
generic map (memory_type => memory_type)
PORT MAP (
clk => clk,
reset => reset,
address_next => address_next,
byte_we_next => byte_we_next,
cpu_address => cpu_address(31 downto 2),
mem_busy => mem_busy,
cache_access => cache_access, --access 4KB cache
cache_checking => cache_checking, --checking if cache hit
cache_miss => cache_miss); --cache miss
end generate; --opt_cache2
no_ddr_start <= not eth_pause and cache_checking;
no_ddr_stop <= not eth_pause and cache_miss;
eth_pause_in <= (not eth_pause and cache_miss and not cache_checking);
--
--
--
misc_proc: process(clk, reset, cpu_address, enable_misc,
ram_data_r, data_read_uart, cpu_pause,
irq_mask_reg, irq_status, gpio0_reg, write_enable,
cache_checking,
gpioA_in, counter_reg, cpu_data_w, ram_data_lm,
fifo_1_empty, fifo_2_empty, fifo_1_full, fifo_2_full,
fifo_1_valid, fifo_2_valid, fifo_1_compteur, fifo_2_compteur, fifo_1_out_data, cop_1_output)
begin
case cpu_address(30 downto 28) is
-- ON LIT LES DONNEES DE LA MEMOIRE INTERNE
when "000" => --internal ROM
cpu_data_r <= ram_data_r;
-- ON LIT LES DONNEES DE LA MEMOIRE EXTERNE (LOCAL RAM)
when "001" => --external (local) RAM
--if cache_checking = '1' then
--cpu_data_r <= ram_data_r; --cache
--else
--cpu_data_r <= data_read; --DDR
--end if;
cpu_data_r <= ram_data_lm;
-- ON LIT LES DONNEES DES PERIPHERIQUES MISC.
when "010" => --misc
case cpu_address(6 downto 4) is
when "000" => --uart
cpu_data_r <= ZERO(31 downto 8) & data_read_uart;
when "001" => --irq_mask
cpu_data_r <= ZERO(31 downto 8) & irq_mask_reg;
when "010" => --irq_status
cpu_data_r <= ZERO(31 downto 8) & irq_status;
when "011" => --gpio0
cpu_data_r <= gpio0_reg;
when "101" => --gpioA
cpu_data_r <= gpioA_in;
when "110" => --counter
cpu_data_r <= counter_reg;
when others => -- ce n'est pas pr\E9vu...
cpu_data_r <= x"FFFFFFFF";
end case;
-- ON LIT LES DONNEES EN PROVENANCE DU PCIe 0x3....XX
when "011" =>
case cpu_address(7 downto 4) is
when "0000" => cpu_data_r <= ZERO(31 downto 1) & fifo_1_empty;
when "0001" => cpu_data_r <= ZERO(31 downto 1) & fifo_2_empty;
when "0010" => cpu_data_r <= ZERO(31 downto 1) & fifo_1_full;
when "0011" => cpu_data_r <= ZERO(31 downto 1) & fifo_2_full;
when "0100" => cpu_data_r <= ZERO(31 downto 1) & fifo_1_valid;
when "0101" => cpu_data_r <= ZERO(31 downto 1) & fifo_2_valid;
when "0110" => cpu_data_r <= fifo_1_compteur;
when "0111" => cpu_data_r <= fifo_2_compteur;
when "1000" => cpu_data_r <= fifo_1_out_data;
when others => -- ce n'est pas pr\E9vu...
cpu_data_r <= x"FFFFFFFF";
end case;
--
-- LECTURE DES RESULTATS DES COPROCESSEURS
--
when "100" =>
case cpu_address(7 downto 0) is
when "00000100" => cpu_data_r <= cop_1_output; -- COPROCESSOR 1 (OUTPUT)
when "00110100" => cpu_data_r <= cop_2_output; -- COPROCESSOR 2 (OUTPUT)
when "01100100" => cpu_data_r <= cop_3_output; -- COPROCESSOR 3 (OUTPUT)
when "10010100" => cpu_data_r <= cop_4_output; -- COPROCESSOR 4 (OUTPUT)
when others => cpu_data_r <= x"FFFFFFFF";
end case;
--when "011" => --flash
-- cpu_data_r <= data_read;
when others =>
cpu_data_r <= ZERO(31 downto 8) & x"FF";
end case;
if reset = '1' then
irq_mask_reg <= ZERO(7 downto 0);
gpio0_reg <= ZERO;
counter_reg <= ZERO;
elsif rising_edge(clk) then
if cpu_pause = '0' then
if enable_misc = '1' and write_enable = '1' then
if cpu_address(6 downto 4) = "001" then
irq_mask_reg <= cpu_data_w(7 downto 0);
elsif cpu_address(6 downto 4) = "011" then
gpio0_reg <= gpio0_reg or cpu_data_w;
elsif cpu_address(6 downto 4) = "100" then
gpio0_reg <= gpio0_reg and not cpu_data_w;
end if;
end if;
end if;
counter_reg <= bv_inc(counter_reg);
end if;
end process;
ram_proc: process(cache_access, cache_miss,
address_next, cpu_address,
byte_we_next, cpu_data_w,
dma_address,
dma_byte_we, eth_pause,
dma_data_write,
dma_start, eth_pause)
begin
if eth_pause = '1' then --Check if cache hit or write through
if dma_address(31 downto 28) = "0000" then
ram_boot_enable <= '1';
else
ram_boot_enable <= '0';
end if;
if dma_address(31 downto 28) = "0001" then
enable_local_mem <= '1';
else
enable_local_mem <= '0';
end if;
ram_address <= dma_address(31 downto 2); -- adr from ram
ram_byte_we <= dma_byte_we;
ram_data_w <= dma_data_write;
else --Normal non-cache access
if address_next(31 downto 28) = "0000" then
ram_boot_enable <= '1';
else
ram_boot_enable <= '0';
end if;
if address_next(31 downto 28) = "0001" then
enable_local_mem <= '1';
else
enable_local_mem <= '0';
end if;
ram_byte_we <= byte_we_next;
ram_address(31 downto 2) <= address_next(31 downto 2);
ram_data_w <= cpu_data_w;
end if;
end process;
--
-- RAM DATA CONTROLLER
--
--ram_boot_enable <= '1' WHEN (ram_enable = '1') AND eth_pause = '0' ELSE '0';
u2_boot: ram
generic map (memory_type => memory_type,
plasma_code => plasma_code)
port map (
clk => clk,
enable => ram_boot_enable,
write_byte_enable => ram_byte_we,
address => ram_address,
data_write => ram_data_w,
data_read => ram_data_r);
-- ON RELIT L'ENTREE DU PCIe (port de sortie) AU BUS DE DONNEE DU PROCESSEUR
-- PLASMA
fifo_2_in_data <= cpu_data_w;
--
-- UART CONTROLLER CAN BE REMOVED (FOR ASIC DESIGN)
--
uart_gen: if eUart = '1' generate
u3_uart: uart
generic map (log_file => log_file)
port map(
clk => clk,
reset => reset,
enable_read => enable_uart_read,
enable_write => enable_uart_write,
data_in => cpu_data_w(7 downto 0),
data_out => data_read_uart,
uart_read => uart_read,
uart_write => uart_write,
busy_write => uart_write_busy,
data_avail => uart_data_avail
);
end generate;
uart_gen2: if eUart = '0' generate
data_read_uart <= "00000000";
uart_write_busy <= '0';
uart_data_avail <= '0';
end generate;
--
-- ETHERNET CONTROLLER CAN BE REMOVED (FOR ASIC DESIGN)
--
-- dma_gen: if ethernet = '2' generate
-- address <= cpu_address(31 downto 2);
-- byte_we <= cpu_byte_we;
-- data_write <= cpu_data_w;
-- eth_pause <= '0';
-- irq_eth_rec <= '0';
-- irq_eth_send <= '0';
-- gpio0_out(28 downto 24) <= ZERO(28 downto 24);
-- end generate;
-- dma_gen2: if ethernet = '1' generate
-- u4_eth: eth_dma
-- port map(
-- clk => clk,
-- reset => reset,
-- enable_eth => gpio0_reg(24),
-- select_eth => enable_eth,
-- rec_isr => irq_eth_rec,
-- send_isr => irq_eth_send,
--
-- address => address, --to DDR
-- byte_we => byte_we,
-- data_write => data_write,
-- data_read => data_read,
-- pause_in => eth_pause_in,
--
-- mem_address => cpu_address(31 downto 2), --from CPU
-- mem_byte_we => cpu_byte_we,
-- data_w => cpu_data_w,
-- pause_out => eth_pause,
--
-- E_RX_CLK => gpioA_in(20),
-- E_RX_DV => gpioA_in(19),
-- E_RXD => gpioA_in(18 downto 15),
-- E_TX_CLK => gpioA_in(14),
-- E_TX_EN => gpio0_out(28),
-- E_TXD => gpio0_out(27 downto 24));
-- end generate;
dma_start <= '1' when ((cpu_address(31 downto 28) = "1000") and (cpu_byte_we = "1111")) else '0';
------------------------------------------------------------------------------------------------------
--
--
--
--
--
------------------------------------------------------------------------------------------------------
dma_input_mux_proc: process(clk, reset, dma_address, enable_misc,
ram_data_r, data_read_uart, cpu_pause,
irq_mask_reg, irq_status, gpio0_reg, write_enable,
cache_checking,
gpioA_in, counter_reg, cpu_data_w, ram_data_lm,
fifo_1_empty, fifo_2_empty, fifo_1_full, fifo_2_full,
fifo_1_valid, fifo_2_valid, fifo_1_compteur, fifo_2_compteur, fifo_1_out_data)
begin
case dma_address(30 downto 28) is
when "000" => --internal ROM
dma_data_read <= ram_data_r;
when "001" => --external (local) RAM
dma_data_read <= ram_data_lm;
when "010" => --misc
case dma_address(6 downto 4) is
when "000" => dma_data_read <= ZERO(31 downto 8) & data_read_uart;
when "001" => dma_data_read <= ZERO(31 downto 8) & irq_mask_reg;
when "010" => dma_data_read <= ZERO(31 downto 8) & irq_status;
when "011" => dma_data_read <= gpio0_reg;
when "101" => dma_data_read <= gpioA_in;
when "110" => dma_data_read <= counter_reg;
when others => dma_data_read <= x"FFFFFFFF";
end case;
when "011" =>
case dma_address(7 downto 4) is
when "0000" => dma_data_read <= ZERO(31 downto 1) & fifo_1_empty;
when "0001" => dma_data_read <= ZERO(31 downto 1) & fifo_2_empty;
when "0010" => dma_data_read <= ZERO(31 downto 1) & fifo_1_full;
when "0011" => dma_data_read <= ZERO(31 downto 1) & fifo_2_full;
when "0100" => dma_data_read <= ZERO(31 downto 1) & fifo_1_valid;
when "0101" => dma_data_read <= ZERO(31 downto 1) & fifo_2_valid;
when "0110" => dma_data_read <= fifo_1_compteur;
when "0111" => dma_data_read <= fifo_2_compteur;
when "1000" => dma_data_read <= fifo_1_out_data;
when others => dma_data_read <= x"FFFFFFFF";
end case;
when others =>
dma_data_read <= ZERO(31 downto 8) & x"FF";
end case;
end process;
u4_dma: entity WORK.dma_engine
port map(
clk => clk,
reset => reset,
start_dma => dma_start,
--
address => dma_address, -- adr from ram
byte_we => dma_byte_we,
data_write => dma_data_write,
data_read => dma_data_read,
--
mem_address => cpu_address, -- adr from cpu
mem_byte_we => cpu_byte_we,
data_w => cpu_data_w,
pause_out => eth_pause
);
------------------------------------------------------------------------------------------------------
--
--
--
--
--
------------------------------------------------------------------------------------------------------
u5a_coproc: entity WORK.coproc_1 port map(
clock => clk,
reset => cop_1_reset,
INPUT_1 => cpu_data_w,
INPUT_1_valid => cop_1_valid,
OUTPUT_1 => cop_1_output
);
u5b_coproc: entity WORK.coproc_2 port map(
clock => clk,
reset => cop_2_reset,
INPUT_1 => cpu_data_w,
INPUT_1_valid => cop_2_valid,
OUTPUT_1 => cop_2_output
);
u5c_coproc: entity WORK.coproc_3 port map(
clock => clk,
reset => cop_3_reset,
INPUT_1 => cpu_data_w,
INPUT_1_valid => cop_3_valid,
OUTPUT_1 => cop_3_output
);
u5d_coproc: entity WORK.coproc_4
port map(
clock => clk,
--clock_VGA => clk_VGA,
reset => cop_4_reset,
INPUT_1 => cpu_data_w,
INPUT_1_valid => cop_4_valid,
OUTPUT_1 => cop_4_output,
data_out => data_out,
data_write => data_enable,
ADDR => ADDR
-- VGA_hs => VGA_hs,
-- VGA_vs => VGA_vs,
--iter => iter
--VGA_green => VGA_green,
--VGA_blue => VGA_blue
);
end; --architecture logic
| gpl-3.0 | 0723c45d9aedf8ec6192ab5d75250a54 | 0.533445 | 3.148225 | false | false | false | false |
karvonz/Mandelbrot | soc_plasma/vhdl/plasma_core/vhdl/cam/cam_pkg.vhd | 1 | 867 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
PACKAGE cam_pkg IS
FUNCTION divide(a : IN unsigned;
b : IN unsigned) RETURN unsigned;
END; --package cam_pkg declaration
PACKAGE BODY cam_pkg IS
function divide (a : UNSIGNED; b : UNSIGNED) return UNSIGNED is
variable a1 : unsigned(a'length-1 downto 0):=a;
variable b1 : unsigned(b'length-1 downto 0):=b;
variable p1 : unsigned(b'length downto 0):= (others => '0');
variable i : integer:=0;
begin
for i in 0 to b'length-1 loop
p1(b'length-1 downto 1) := p1(b'length-2 downto 0);
p1(0) := a1(a'length-1);
a1(a'length-1 downto 1) := a1(a'length-2 downto 0);
p1 := p1-b1;
if(p1(b'length-1) ='1') then
a1(0) :='0';
p1 := p1+b1;
else
a1(0) :='1';
end if;
end loop;
return a1;
end divide;
END; --package body | gpl-3.0 | b06150693e963016babd712c59554089 | 0.607843 | 2.805825 | false | false | false | false |
karvonz/Mandelbrot | src_vhd/increment.vhd | 1 | 1,674 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.CONSTANTS.all;
use work.CONFIG_MANDELBROT.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity increment is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
start : in STD_LOGIC;
x_start : in STD_LOGIC_VECTOR (XY_RANGE-1 downto 0);
y_start : in STD_LOGIC_VECTOR (XY_RANGE-1 downto 0);
step : in STD_LOGIC_VECTOR (XY_RANGE-1 downto 0);
x : out STD_LOGIC_VECTOR (XY_RANGE-1 downto 0);
y : out STD_LOGIC_VECTOR (XY_RANGE-1 downto 0);
stop : out std_logic);
end increment;
architecture Behavioral of increment is
signal xs, ys : signed(XY_RANGE-1 downto 0);
signal xcount : integer range 0 to XRES-1:=0;
signal ycount : integer range 0 to YRES-1:=0;
begin
process(clock, reset,start,x_start,y_start,step)
begin
if reset='1' then
xcount<=0;
ycount<=0;
xs<= signed(x_start);
ys<= signed(y_start);
stop<='0';
elsif rising_edge(clock) then
if(start='1') then
if xcount = XRES-1 then
if ycount = YRES-1 then
xcount <= 0;
ycount <= 0;
xs<=signed(x_start);
ys<=signed(y_start);
stop<='1';
else
xcount <= 0;
ycount <= ycount+1;
ys<=ys+signed(step);
xs<=signed(x_start);
stop<='0';
end if;
else
stop<='0';
xs<=xs+signed(step);
xcount<=xcount+1;
end if;
end if;
end if;
end process;
x<=std_logic_vector(xs);
y<=std_logic_vector(ys);
end Behavioral; | gpl-3.0 | e3cccf1971cdf4f101abcf6083fae5c1 | 0.658303 | 2.978648 | false | false | false | false |
ryos36/polyphony-tutorial | Xorshift/xorshift_tb.vhdl | 1 | 3,370 | library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_textio.all;
library std;
use std.textio.all;
entity xorshift_tb is
end xorshift_tb;
architecture behav of xorshift_tb is
component xorshift
port(
clk : in std_logic;
rst_n : in std_logic;
kick_n : in std_logic;
d_en_n : out std_logic;
data : out std_logic_vector(3 downto 0)
);
end component;
component xorshift16
port(
clk : in std_logic;
rst_n : in std_logic;
kick_n : in std_logic;
d_en_n : out std_logic;
data : out std_logic_vector(3 downto 0)
);
end component;
component xorshift8
port(
clk : in std_logic;
kick_n : in std_logic;
d_en_n : out std_logic;
data : out std_logic_vector(7 downto 0)
);
end component;
signal clk : std_logic;
signal rst_n : std_logic;
signal kick_n : std_logic;
signal d_en_n : std_logic;
signal data : std_logic_vector(3 downto 0);
signal data8 : std_logic_vector(7 downto 0);
signal d_en_n_d : std_logic;
signal result : std_logic_vector(31 downto 0);
signal result_done : std_logic;
constant clk_period : time := 10 ns;
begin
-------------------------------------------------------------------
xorshift0 : xorshift8
port map (
clk => clk,
kick_n => kick_n,
d_en_n => d_en_n,
data => data8
);
-------------------------------------------------------------------
clk_producer: process
begin
clk <= '0';
wait for clk_period / 2;
clk <= '1';
wait for clk_period / 2;
end process;
-------------------------------------------------------------------
reset_sequence: process
begin
rst_n <= '1';
wait for clk_period * 2;
rst_n <= '0';
wait for clk_period * 8;
rst_n <= '1';
wait;
end process;
-------------------------------------------------------------------
kicker: process
variable line0 : line;
begin
kick_n <= '1';
wait for clk_period * 16;
kick_n <= '0';
wait for clk_period * 3;
write( line0, String'("kick it!"));
writeline( output, line0);
kick_n <= '1';
while( result_done = '0') loop
wait for clk_period / 2;
end loop;
wait for clk_period * 160000;
end process;
-------------------------------------------------------------------
data_cosumer: process(clk)
variable line0 : line;
begin
if rst_n = '0' then
result_done <= '0';
end if;
if clk'event and clk = '1' then
d_en_n_d <= d_en_n;
if d_en_n = '1' then
result <= ( others => '0' );
if d_en_n_d = '0' then
write( line0, String'("result:"));
write( line0, result );
writeline( output, line0);
end if;
else
result(7 downto 0) <= data8;
--result(31 downto 28) <= data;
--result(27 downto 0) <= result(31 downto 4);
-- write( line0, String'("now get data:"));
-- write( line0, result );
-- writeline( output, line0);
end if;
if result_done = '1' then
result_done <= '0';
end if;
if d_en_n_d = '0' and d_en_n = '1' then
result_done <= '1';
end if;
end if;
end process;
end behav;
| mit | 193b315eba25f1254a07c9e6953ac156 | 0.478635 | 3.547368 | false | false | false | false |
ruygargar/LCSE_lab | dma/dma_rx.vhd | 1 | 4,774 | -- Author: Aragonés Orellana, Silvia
-- García Garcia, Ruy
-- Project Name: PIC
-- Design Name: dma.vhd
-- Module Name: dma_rx.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dma_rx is
Port ( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
-- Señales procedentes del bus del uP.
Databus : out STD_LOGIC_VECTOR (7 downto 0);
Address : out STD_LOGIC_VECTOR (7 downto 0);
ChipSelect : out STD_LOGIC;
WriteEnable : out STD_LOGIC;
OutputEnable : out STD_LOGIC;
-- Señales procedentes de la FSM del Controlador de Bus.
Start_RX : in STD_LOGIC;
End_RX : out STD_LOGIC;
-- Bus de datos y señales de handshake orientadas al receptor del
-- RS232.
DataIn : in STD_LOGIC_VECTOR (7 downto 0);
Read_DI : out STD_LOGIC;
Empty : in STD_LOGIC);
end dma_rx;
architecture Behavioral of dma_rx is
-- Definición de los posibles estados de la FSM del Transmisor:
type Receiver_ST is (idle, MVE_REGX, CPY_NEWINST);
signal RX_now, RX_next : Receiver_ST;
-- Tabla de direcciones:
-- El valor contenido en cada posición de la tabla será empleado como
-- dirección de memoria en la que se escribirá el dato de entrada,
-- utilizando como índice el orden de llegada de los bytes entrantes.
type table is array (natural range <>) of std_logic_vector(7 downto 0);
constant AddressTable : table := (X"00", X"01", X"02", X"03");
-- Señales usadas para inferir un contador que vaya barriendo la tabla de
-- direcciones para ir almacenando los datos recibidos en su respectiva
-- posición de memoria.
signal count : std_logic_vector(1 downto 0);
-- Señal de enable y clear del contador anterior.
signal count_enable, count_clear : std_logic;
begin
-- El Receptor nunca leerá un valor de memoria. Únicamente escribe los
-- datos recibidos en ella.
OutputEnable <= '0';
-- Proceso secuencial que describe el contador necesario para indexar la
-- tabla de direcciones del Receptor.
-- Dispone de una señal de Reset asíncrono activa a nivel bajo que
-- inicializa a 0 el valor del contador.
-- Además dispone de dos entradas de control síncronas y activas a nivel
-- alto (enable y clear), procedentes de la FSM del Receptor, desde las
-- cuales se gobernará el contador.
process(Clk, Reset)
begin
if (Reset = '0') then
count <= (others => '0');
elsif Clk'event and Clk = '1' then
if count_clear = '1' then
count <= (others => '0');
elsif count_enable = '1' then
count <= count + '1';
end if;
end if;
end process;
-- Proceso secuencial de la máquina de estados del Receptor.
-- Dispone de una señal de Reset asíncrono activa a nivel bajo. Mientras que
-- esta señal se mantenga activa, la FSM se mantiene en el estado de 'Idle'.
process(Clk, Reset)
begin
if (Reset = '0') then
RX_now <= idle;
elsif Clk'event and Clk = '1' then
RX_now <= RX_next;
end if;
end process;
-- Proceso combinacional de la máquina de estados.
process(RX_now, Start_RX, DataIn, Empty, count)
begin
-- Valores preasignados por defecto.
Databus <= DataIn;
Address <= X"00";
ChipSelect <= '0';
WriteEnable <= '0';
End_RX <= '0';
Read_DI <= '0';
count_enable <= '0';
count_clear <= '0';
case RX_now is
when idle =>
-- Si el Controlador de Bus da permiso para iniciar una nueva
-- recepción...
if Start_RX = '1' then
RX_next <= MVE_REGX;
else
RX_next <= idle;
end if;
when MVE_REGX =>
Address <= AddressTable(conv_integer(count));
ChipSelect <= '1';
WriteEnable <= '1';
Read_DI <= '1';
count_enable <= '1';
-- Si el RS232 ya no tiene más datos recibidos...
if (Empty = '1') then
-- No se realiza la transferencia .
ChipSelect <= '0';
WriteEnable <= '0';
Read_DI <= '0';
-- Ni se actualiza el contador.
count_enable <= '0';
-- Y se vuelve al estado de espera, devolviendo el control de
-- los buses.
End_RX <= '1';
RX_next <= idle;
-- Si se está recibiendo correctamente el LSB...
elsif (count = X"2") then
RX_next <= CPY_NEWINST;
else
RX_next <= MVE_REGX;
end if;
when CPY_NEWINST =>
Address <= AddressTable(conv_integer(count));
Databus <= X"FF";
ChipSelect <= '1';
WriteEnable <= '1';
-- Se reinicia el contador y se vuelve al estado de espera,
-- devolviendo el control de los buses.
count_clear <= '1';
End_RX <= '1';
RX_next <= idle;
end case;
end process;
end Behavioral;
| gpl-3.0 | a19c20a9318d7dfa59c7d88809c52678 | 0.61437 | 3.385816 | false | false | false | false |
achan1989/In64 | FPGA/SD_card_test.srcs/sources_1/ip/mig_v3_92_0/ATLYS_DDR/user_design/sim/sim_tb_top.vhd | 1 | 32,486 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : sim_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:56 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Spartan-6
-- Design Name : DDR/DDR2/DDR3/LPDDR
-- Purpose : This is the simulation testbench which is used to verify the
-- design. The basic clocks and resets to the interface are
-- generated here. This also connects the memory interface to the
-- memory model.
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity sim_tb_top is
end entity sim_tb_top;
architecture arch of sim_tb_top is
-- ========================================================================== --
-- Parameters --
-- ========================================================================== --
constant DEBUG_EN : integer :=0;
constant C3_HW_TESTING : string := "FALSE";
function c3_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is
begin
if (C3_HW_TESTING = "FALSE") then
return val1;
else
return val2;
end if;
end function;
constant C3_MEMCLK_PERIOD : integer := 3000;
constant C3_RST_ACT_LOW : integer := 0;
constant C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
constant C3_CLK_PERIOD_NS : real := 3000.0 / 1000.0;
constant C3_TCYC_SYS : real := C3_CLK_PERIOD_NS/2.0;
constant C3_TCYC_SYS_DIV2 : time := C3_TCYC_SYS * 1 ns;
constant C3_NUM_DQ_PINS : integer := 16;
constant C3_MEM_ADDR_WIDTH : integer := 13;
constant C3_MEM_BANKADDR_WIDTH : integer := 3;
constant C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
constant C3_P0_MASK_SIZE : integer := 4;
constant C3_P0_DATA_PORT_SIZE : integer := 32;
constant C3_P1_MASK_SIZE : integer := 4;
constant C3_P1_DATA_PORT_SIZE : integer := 32;
constant C3_MEM_BURST_LEN : integer := 4;
constant C3_MEM_NUM_COL_BITS : integer := 10;
constant C3_SIMULATION : string := "TRUE";
constant C3_CALIB_SOFT_IP : string := "TRUE";
constant C3_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
constant C3_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C3_p0_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000002ff", x"02ffffff");
constant C3_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffffc00", x"fc000000");
constant C3_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
constant C3_p2_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
constant C3_p2_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C3_p2_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000002ff", x"02ffffff");
constant C3_p2_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffffc00", x"fc000000");
constant C3_p2_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
-- ========================================================================== --
-- Component Declarations
-- ========================================================================== --
component ATLYS_DDR is
generic
(
C3_P0_MASK_SIZE : integer;
C3_P0_DATA_PORT_SIZE : integer;
C3_P1_MASK_SIZE : integer;
C3_P1_DATA_PORT_SIZE : integer;
C3_MEMCLK_PERIOD : integer;
C3_RST_ACT_LOW : integer;
C3_INPUT_CLK_TYPE : string;
DEBUG_EN : integer;
C3_CALIB_SOFT_IP : string;
C3_SIMULATION : string;
C3_MEM_ADDR_ORDER : string;
C3_NUM_DQ_PINS : integer;
C3_MEM_ADDR_WIDTH : integer;
C3_MEM_BANKADDR_WIDTH : integer
);
port
(
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_i : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic; c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic;
c3_p2_cmd_clk : in std_logic;
c3_p2_cmd_en : in std_logic;
c3_p2_cmd_instr : in std_logic_vector(2 downto 0);
c3_p2_cmd_bl : in std_logic_vector(5 downto 0);
c3_p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p2_cmd_empty : out std_logic;
c3_p2_cmd_full : out std_logic;
c3_p2_rd_clk : in std_logic;
c3_p2_rd_en : in std_logic;
c3_p2_rd_data : out std_logic_vector(31 downto 0);
c3_p2_rd_full : out std_logic;
c3_p2_rd_empty : out std_logic;
c3_p2_rd_count : out std_logic_vector(6 downto 0);
c3_p2_rd_overflow : out std_logic;
c3_p2_rd_error : out std_logic
);
end component;
component ddr2_model_c3 is
port (
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ras_n : in std_logic;
cas_n : in std_logic;
we_n : in std_logic;
dm_rdqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
ba : in std_logic_vector((C3_MEM_BANKADDR_WIDTH - 1) downto 0);
addr : in std_logic_vector((C3_MEM_ADDR_WIDTH - 1) downto 0);
dq : inout std_logic_vector((C3_NUM_DQ_PINS - 1) downto 0);
dqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
dqs_n : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
rdqs_n : out std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
odt : in std_logic
);
end component;
component memc3_tb_top is
generic
(
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_MEM_BURST_LEN : integer := 8;
C_MEM_NUM_COL_BITS : integer := 11;
C_NUM_DQ_PINS : integer := 8;
C_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
C_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p0_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
C_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
C_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100";
C_p2_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
C_p2_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p2_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
C_p2_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
C_p2_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100"
);
port
(
clk0 : in std_logic;
rst0 : in std_logic;
calib_done : in std_logic;
p0_mcb_cmd_en_o : out std_logic;
p0_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p0_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p0_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p0_mcb_cmd_full_i : in std_logic;
p0_mcb_wr_en_o : out std_logic;
p0_mcb_wr_mask_o : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_mcb_wr_data_o : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_wr_full_i : in std_logic;
p0_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p0_mcb_rd_en_o : out std_logic;
p0_mcb_rd_data_i : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_rd_empty_i : in std_logic;
p0_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
p2_mcb_cmd_en_o : out std_logic;
p2_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p2_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p2_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p2_mcb_cmd_full_i : in std_logic;
p2_mcb_rd_en_o : out std_logic;
p2_mcb_rd_data_i : in std_logic_vector(31 downto 0);
p2_mcb_rd_empty_i : in std_logic;
p2_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_error : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(127 downto 0)
);
end component;
-- ========================================================================== --
-- Signal Declarations --
-- ========================================================================== --
-- Clocks
-- Clocks
signal c3_sys_clk : std_logic := '0';
signal c3_sys_clk_p : std_logic;
signal c3_sys_clk_n : std_logic;
-- System Reset
signal c3_sys_rst : std_logic := '0';
signal c3_sys_rst_i : std_logic;
-- Design-Top Port Map
signal c3_error : std_logic;
signal c3_calib_done : std_logic;
signal c3_error_status : std_logic_vector(127 downto 0);
signal mcb3_dram_a : std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
signal mcb3_dram_ba : std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
signal mcb3_dram_ck : std_logic;
signal mcb3_dram_ck_n : std_logic;
signal mcb3_dram_dq : std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
signal mcb3_dram_dqs : std_logic;
signal mcb3_dram_dqs_n : std_logic;
signal mcb3_dram_dm : std_logic;
signal mcb3_dram_ras_n : std_logic;
signal mcb3_dram_cas_n : std_logic;
signal mcb3_dram_we_n : std_logic;
signal mcb3_dram_cke : std_logic;
signal mcb3_dram_odt : std_logic;
signal mcb3_dram_udqs : std_logic;
signal mcb3_dram_udqs_n : std_logic;
signal mcb3_dram_dqs_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_dqs_n_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_udm :std_logic; -- for X16 parts
signal mcb3_dram_dm_vector : std_logic_vector(1 downto 0);
-- User design Sim
signal c3_clk0 : std_logic;
signal c3_rst0 : std_logic;
signal c3_cmp_error : std_logic;
signal c3_vio_modify_enable : std_logic;
signal c3_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c3_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal mcb3_command : std_logic_vector(2 downto 0);
signal mcb3_enable1 : std_logic;
signal mcb3_enable2 : std_logic;
signal c3_p0_cmd_en : std_logic;
signal c3_p0_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p0_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p0_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p0_cmd_empty : std_logic;
signal c3_p0_cmd_full : std_logic;
signal c3_p0_wr_en : std_logic;
signal c3_p0_wr_mask : std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
signal c3_p0_wr_data : std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
signal c3_p0_wr_full : std_logic;
signal c3_p0_wr_empty : std_logic;
signal c3_p0_wr_count : std_logic_vector(6 downto 0);
signal c3_p0_wr_underrun : std_logic;
signal c3_p0_wr_error : std_logic;
signal c3_p0_rd_en : std_logic;
signal c3_p0_rd_data : std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
signal c3_p0_rd_full : std_logic;
signal c3_p0_rd_empty : std_logic;
signal c3_p0_rd_count : std_logic_vector(6 downto 0);
signal c3_p0_rd_overflow : std_logic;
signal c3_p0_rd_error : std_logic;
signal c3_p2_cmd_en : std_logic;
signal c3_p2_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p2_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p2_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p2_cmd_empty : std_logic;
signal c3_p2_cmd_full : std_logic;
signal c3_p2_rd_en : std_logic;
signal c3_p2_rd_data : std_logic_vector(31 downto 0);
signal c3_p2_rd_full : std_logic;
signal c3_p2_rd_empty : std_logic;
signal c3_p2_rd_count : std_logic_vector(6 downto 0);
signal c3_p2_rd_overflow : std_logic;
signal c3_p2_rd_error : std_logic;
signal c3_selfrefresh_enter : std_logic;
signal c3_selfrefresh_mode : std_logic;
signal rzq3 : std_logic;
signal zio3 : std_logic;
signal calib_done : std_logic;
signal error : std_logic;
function vector (asi:std_logic) return std_logic_vector is
variable v : std_logic_vector(0 downto 0) ;
begin
v(0) := asi;
return(v);
end function vector;
begin
-- ========================================================================== --
-- Clocks Generation --
-- ========================================================================== --
process
begin
c3_sys_clk <= not c3_sys_clk;
wait for (C3_TCYC_SYS_DIV2);
end process;
c3_sys_clk_p <= c3_sys_clk;
c3_sys_clk_n <= not c3_sys_clk;
-- ========================================================================== --
-- Reset Generation --
-- ========================================================================== --
process
begin
c3_sys_rst <= '0';
wait for 200 ns;
c3_sys_rst <= '1';
wait;
end process;
c3_sys_rst_i <= c3_sys_rst when (C3_RST_ACT_LOW = 1) else (not c3_sys_rst);
error <= c3_error;
calib_done <= c3_calib_done;
-- The PULLDOWN component is connected to the ZIO signal primarily to avoid the
-- unknown state in simulation. In real hardware, ZIO should be a no connect(NC) pin.
zio_pulldown3 : PULLDOWN port map(O => zio3);
rzq_pulldown3 : PULLDOWN port map(O => rzq3);
-- ========================================================================== --
-- DESIGN TOP INSTANTIATION --
-- ========================================================================== --
design_top : ATLYS_DDR generic map
(
C3_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C3_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C3_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C3_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C3_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C3_RST_ACT_LOW => C3_RST_ACT_LOW,
C3_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
DEBUG_EN => DEBUG_EN,
C3_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C3_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C3_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C3_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
C3_SIMULATION => C3_SIMULATION,
C3_CALIB_SOFT_IP => C3_CALIB_SOFT_IP
)
port map (
c3_sys_clk => c3_sys_clk,
c3_sys_rst_i => c3_sys_rst_i,
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
mcb3_dram_udqs_n => mcb3_dram_udqs_n, -- for X16 parts
mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
mcb3_dram_dm => mcb3_dram_dm,
c3_clk0 => c3_clk0,
c3_rst0 => c3_rst0,
c3_calib_done => c3_calib_done,
mcb3_rzq => rzq3,
mcb3_zio => zio3,
c3_p0_cmd_clk => (c3_clk0),
c3_p0_cmd_en => c3_p0_cmd_en,
c3_p0_cmd_instr => c3_p0_cmd_instr,
c3_p0_cmd_bl => c3_p0_cmd_bl,
c3_p0_cmd_byte_addr => c3_p0_cmd_byte_addr,
c3_p0_cmd_empty => c3_p0_cmd_empty,
c3_p0_cmd_full => c3_p0_cmd_full,
c3_p0_wr_clk => (c3_clk0),
c3_p0_wr_en => c3_p0_wr_en,
c3_p0_wr_mask => c3_p0_wr_mask,
c3_p0_wr_data => c3_p0_wr_data,
c3_p0_wr_full => c3_p0_wr_full,
c3_p0_wr_empty => c3_p0_wr_empty,
c3_p0_wr_count => c3_p0_wr_count,
c3_p0_wr_underrun => c3_p0_wr_underrun,
c3_p0_wr_error => c3_p0_wr_error,
c3_p0_rd_clk => (c3_clk0),
c3_p0_rd_en => c3_p0_rd_en,
c3_p0_rd_data => c3_p0_rd_data,
c3_p0_rd_full => c3_p0_rd_full,
c3_p0_rd_empty => c3_p0_rd_empty,
c3_p0_rd_count => c3_p0_rd_count,
c3_p0_rd_overflow => c3_p0_rd_overflow,
c3_p0_rd_error => c3_p0_rd_error,
c3_p2_cmd_clk => (c3_clk0),
c3_p2_cmd_en => c3_p2_cmd_en,
c3_p2_cmd_instr => c3_p2_cmd_instr,
c3_p2_cmd_bl => c3_p2_cmd_bl,
c3_p2_cmd_byte_addr => c3_p2_cmd_byte_addr,
c3_p2_cmd_empty => c3_p2_cmd_empty,
c3_p2_cmd_full => c3_p2_cmd_full,
c3_p2_rd_clk => (c3_clk0),
c3_p2_rd_en => c3_p2_rd_en,
c3_p2_rd_data => c3_p2_rd_data,
c3_p2_rd_full => c3_p2_rd_full,
c3_p2_rd_empty => c3_p2_rd_empty,
c3_p2_rd_count => c3_p2_rd_count,
c3_p2_rd_overflow => c3_p2_rd_overflow,
c3_p2_rd_error => c3_p2_rd_error
);
-- user interface
memc3_tb_top_inst : memc3_tb_top generic map
(
C_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C_MEM_BURST_LEN => C3_MEM_BURST_LEN,
C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS,
C_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C_p0_BEGIN_ADDRESS => C3_p0_BEGIN_ADDRESS,
C_p0_DATA_MODE => C3_p0_DATA_MODE,
C_p0_END_ADDRESS => C3_p0_END_ADDRESS,
C_p0_PRBS_EADDR_MASK_POS => C3_p0_PRBS_EADDR_MASK_POS,
C_p0_PRBS_SADDR_MASK_POS => C3_p0_PRBS_SADDR_MASK_POS,
C_p2_BEGIN_ADDRESS => C3_p2_BEGIN_ADDRESS,
C_p2_DATA_MODE => C3_p2_DATA_MODE,
C_p2_END_ADDRESS => C3_p2_END_ADDRESS,
C_p2_PRBS_EADDR_MASK_POS => C3_p2_PRBS_EADDR_MASK_POS,
C_p2_PRBS_SADDR_MASK_POS => C3_p2_PRBS_SADDR_MASK_POS
)
port map
(
clk0 => c3_clk0,
rst0 => c3_rst0,
calib_done => c3_calib_done,
cmp_error => c3_cmp_error,
error => c3_error,
error_status => c3_error_status,
vio_modify_enable => c3_vio_modify_enable,
vio_data_mode_value => c3_vio_data_mode_value,
vio_addr_mode_value => c3_vio_addr_mode_value,
p0_mcb_cmd_en_o => c3_p0_cmd_en,
p0_mcb_cmd_instr_o => c3_p0_cmd_instr,
p0_mcb_cmd_bl_o => c3_p0_cmd_bl,
p0_mcb_cmd_addr_o => c3_p0_cmd_byte_addr,
p0_mcb_cmd_full_i => c3_p0_cmd_full,
p0_mcb_wr_en_o => c3_p0_wr_en,
p0_mcb_wr_mask_o => c3_p0_wr_mask,
p0_mcb_wr_data_o => c3_p0_wr_data,
p0_mcb_wr_full_i => c3_p0_wr_full,
p0_mcb_wr_fifo_counts => c3_p0_wr_count,
p0_mcb_rd_en_o => c3_p0_rd_en,
p0_mcb_rd_data_i => c3_p0_rd_data,
p0_mcb_rd_empty_i => c3_p0_rd_empty,
p0_mcb_rd_fifo_counts => c3_p0_rd_count,
p2_mcb_cmd_en_o => c3_p2_cmd_en,
p2_mcb_cmd_instr_o => c3_p2_cmd_instr,
p2_mcb_cmd_bl_o => c3_p2_cmd_bl,
p2_mcb_cmd_addr_o => c3_p2_cmd_byte_addr,
p2_mcb_cmd_full_i => c3_p2_cmd_full,
p2_mcb_rd_en_o => c3_p2_rd_en,
p2_mcb_rd_data_i => c3_p2_rd_data,
p2_mcb_rd_empty_i => c3_p2_rd_empty,
p2_mcb_rd_fifo_counts => c3_p2_rd_count
);
-- ========================================================================== --
-- Memory model instances --
-- ========================================================================== --
mcb3_command <= (mcb3_dram_ras_n & mcb3_dram_cas_n & mcb3_dram_we_n);
process(mcb3_dram_ck)
begin
if (rising_edge(mcb3_dram_ck)) then
if (c3_sys_rst = '0') then
mcb3_enable1 <= '0';
mcb3_enable2 <= '0';
elsif (mcb3_command = "100") then
mcb3_enable2 <= '0';
elsif (mcb3_command = "101") then
mcb3_enable2 <= '1';
else
mcb3_enable2 <= mcb3_enable2;
end if;
mcb3_enable1 <= mcb3_enable2;
end if;
end process;
-----------------------------------------------------------------------------
--read
-----------------------------------------------------------------------------
mcb3_dram_dqs_vector(1 downto 0) <= (mcb3_dram_udqs & mcb3_dram_dqs)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
mcb3_dram_dqs_n_vector(1 downto 0) <= (mcb3_dram_udqs_n & mcb3_dram_dqs_n)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
-----------------------------------------------------------------------------
--write
-----------------------------------------------------------------------------
mcb3_dram_dqs <= mcb3_dram_dqs_vector(0)
when ( mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs <= mcb3_dram_dqs_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_dqs_n <= mcb3_dram_dqs_n_vector(0)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs_n <= mcb3_dram_dqs_n_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_dm_vector <= (mcb3_dram_udm & mcb3_dram_dm);
u_mem_c3 : ddr2_model_c3 port map(
ck => mcb3_dram_ck,
ck_n => mcb3_dram_ck_n,
cke => mcb3_dram_cke,
cs_n => '0',
ras_n => mcb3_dram_ras_n,
cas_n => mcb3_dram_cas_n,
we_n => mcb3_dram_we_n,
dm_rdqs => mcb3_dram_dm_vector ,
ba => mcb3_dram_ba,
addr => mcb3_dram_a,
dq => mcb3_dram_dq,
dqs => mcb3_dram_dqs_vector,
dqs_n => mcb3_dram_dqs_n_vector,
rdqs_n => open,
odt => mcb3_dram_odt
);
-----------------------------------------------------------------------------
-- Reporting the test case status
-----------------------------------------------------------------------------
Logging: process
begin
wait for 200 us;
if (calib_done = '1') then
if (error = '0') then
report ("****TEST PASSED****");
else
report ("****TEST FAILED: DATA ERROR****");
end if;
else
report ("****TEST FAILED: INITIALIZATION DID NOT COMPLETE****");
end if;
end process;
end architecture;
| lgpl-3.0 | 3239b15e6f38be986df2696b7f4b92e9 | 0.457028 | 3.349763 | false | false | false | false |
laurivosandi/hdl | arithmetic/src/multiplier.vhd | 1 | 4,952 | library ieee;
use ieee.std_logic_1164.all;
entity multiplier is
port (
a : in std_logic_vector (15 downto 0);
b : in std_logic_vector (15 downto 0);
m : out std_logic_vector (31 downto 0)
);
end multiplier;
architecture behavioral of multiplier is
-- Booth encoder
component booth4 is
port (
a : in std_logic_vector (15 downto 0);
d : in std_logic_vector (2 downto 0);
m : out std_logic_vector (16 downto 0)
);
end component;
-- Bit-vector based 4:2 counter
component counter42 is
generic (N : integer := 24);
port (
a : in std_logic_vector (N-1 downto 0);
b : in std_logic_vector (N-1 downto 0);
c : in std_logic_vector (N-1 downto 0);
d : in std_logic_vector (N-1 downto 0);
s : out std_logic_vector (N-1 downto 0);
co : out std_logic_vector (N-1 downto 0)
);
end component;
-- Carry lookahead adder
component cla is
generic (N : integer := 32);
port (
a : in std_logic_vector (N-1 downto 0);
b : in std_logic_vector (N-1 downto 0);
ci : in std_logic;
s : out std_logic_vector (N-1 downto 0);
co : out std_logic
);
end component;
-- First Booth digit
signal d0 : std_logic_vector(2 downto 0);
-- Products
signal p0 : std_logic_vector(16 downto 0);
signal p1 : std_logic_vector(16 downto 0);
signal p2 : std_logic_vector(16 downto 0);
signal p3 : std_logic_vector(16 downto 0);
signal p4 : std_logic_vector(16 downto 0);
signal p5 : std_logic_vector(16 downto 0);
signal p6 : std_logic_vector(16 downto 0);
signal p7 : std_logic_vector(16 downto 0);
-- Sign extension
signal se0 : std_logic_vector(23 downto 0);
signal se1 : std_logic_vector(23 downto 0);
signal se2 : std_logic_vector(23 downto 0);
signal se3 : std_logic_vector(23 downto 0);
signal se4 : std_logic_vector(23 downto 0);
signal se5 : std_logic_vector(23 downto 0);
signal se6 : std_logic_vector(23 downto 0);
signal se7 : std_logic_vector(23 downto 0);
-- Intermediary sums and carries
signal s1 : std_logic_vector(23 downto 0);
signal s2 : std_logic_vector(23 downto 0);
signal co1 : std_logic_vector(23 downto 0);
signal co2 : std_logic_vector(23 downto 0);
-- Final sum and carry
signal s3 : std_logic_vector(31 downto 0);
signal co3 : std_logic_vector(31 downto 0);
-- Padded sums abd carries
signal s1p : std_logic_vector(31 downto 0);
signal s2p : std_logic_vector(31 downto 0);
signal co1p : std_logic_vector(31 downto 0);
signal co2p : std_logic_vector(31 downto 0);
signal co3p : std_logic_vector(31 downto 0);
begin
-- Pad first booth digit
d0 <= b( 1 downto 0) & "0";
-- Product stages
p0_stage: booth4 port map(a=>a, d=>d0, m=>p0);
p1_stage: booth4 port map(a=>a, d=>b( 3 downto 1), m=>p1);
p2_stage: booth4 port map(a=>a, d=>b( 5 downto 3), m=>p2);
p3_stage: booth4 port map(a=>a, d=>b( 7 downto 5), m=>p3);
p4_stage: booth4 port map(a=>a, d=>b( 9 downto 7), m=>p4);
p5_stage: booth4 port map(a=>a, d=>b(11 downto 9), m=>p5);
p6_stage: booth4 port map(a=>a, d=>b(13 downto 11), m=>p6);
p7_stage: booth4 port map(a=>a, d=>b(15 downto 13), m=>p7);
-- Reduced sign extension, assuming that compiler takes
-- care of getting rid of constants of course
se0 <= "0000" & (not p0(16)) & p0(16) & p0(16) & p0;
se1 <= "0001" & (not p1(16)) & p1 & "00";
se2 <= "01" & (not p2(16)) & p2 & "0000";
se3 <= not(p3(16)) & p3 & "000000";
se4 <= "000001" & (not p4(16)) & p4;
se5 <= "0001" & (not p5(16)) & p5 & "00";
se6 <= "01" & (not p6(16)) & p6 & "0000";
se7 <= not(p7(16)) & p7 & "000000";
-- Add first 4 products
counter_stage1: counter42 port map(
a => se0, b => se1, c => se2, d => se3,
s => s1, co => co1);
-- Add remaining 4 products
counter_stage2: counter42 port map(
a => se4, b => se5, c => se6, d => se7,
s => s2, co => co2);
-- Pad carries
s1p <= "00000001" & s1;
s2p <= s2 & "00000000";
co1p <= "0000000" & co1 & "0";
co2p <= co2(22 downto 0) & "000000000";
-- Add shifted operands
counter_stage3: counter42 generic map (N=>32) port map(
a => s1p,
b => s2p,
c => co1p,
d => co2p,
s => s3,
co => co3
);
-- Pad carries
co3p <= co3(30 downto 0) & "0";
-- Add sum and carries
cla_stage2: cla port map(
a => s3, b => co3p, ci => '0', s => m
);
end behavioral;
| mit | 885edefb615dbee9f73d4b7f833ee598 | 0.534128 | 3.093067 | false | false | false | false |
pmassolino/hw-goppa-mceliece | mceliece/backup/polynomial_evaluator_n.vhd | 1 | 17,961 | ----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Polynomial_Evaluator_N
-- Module Name: Polynomial_Evaluator_N
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 3rd step in Goppa Code Decoding.
--
-- This circuit is to be used together with find_correct_erros_n to find the roots
-- of polynomial sigma. This circuit can also be alone to evaluate a polynomial withing
-- a range of values.
--
-- For the computation this circuit applies the school book algorithm of powering x
-- and multiplying by the respective polynomial coefficient and adding into the accumulator.
-- This method is not appropriate for this computation, so in polynomial_evaluator_n_v2
-- Horner scheme is applied to reduce circuits costs.
--
-- The circuits parameters
--
-- number_of_pipelines :
--
-- Number of pipelines used in the circuit to test the support elements and
-- correct the message. Each pipeline needs at least 2 memory ram to store
-- intermediate results.
--
-- pipeline_size :
--
-- The number of stages the pipeline has. More stages means more values of value_sigma
-- are tested at once.
--
-- size_pipeline_size :
--
-- The number of bits necessary to store the pipeline_size.
-- This number is ceil(log2(pipeline_size))
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- polynomial_degree :
--
-- The polynomial degree to be evaluated. Therefore the polynomial has
-- polynomial_degree+1 coefficients. This parameters depends of the Goppa code used.
--
-- size_polynomial_degree :
--
-- The number of bits necessary to store polynomial_degree.
-- This number is ceil(log2(polynomial_degree+1))
--
-- number_of_values_x :
--
-- The size of the memory that holds all support elements. This parameter
-- depends of the Goppa code used.
--
-- size_number_of_values_x :
-- The number of bits necessary to store all support elements.
-- this number is ceil(log2(number_of_values_x)).
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- pipeline_polynomial_calc Rev 1.0
-- shift_register_rst_nbits Rev 1.0
-- shift_register_nbits Rev 1.0
-- register_nbits Rev 1.0
-- register_rst_nbits Rev 1.0
-- counter_rst_nbits Rev 1.0
-- controller_polynomial_evaluator Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity polynomial_evaluator_n is
Generic (
-- GOPPA [2048, 1751, 27, 11] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 2;
-- size_pipeline_size : integer := 5;
-- gf_2_m : integer range 1 to 20 := 11;
-- polynomial_degree : integer := 27;
-- size_polynomial_degree : integer := 5;
-- number_of_values_x: integer := 2048;
-- size_number_of_values_x : integer := 11
-- GOPPA [2048, 1498, 50, 11] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 2;
-- size_pipeline_size : integer := 5;
-- gf_2_m : integer range 1 to 20 := 11;
-- polynomial_degree : integer := 50;
-- size_polynomial_degree : integer := 6;
-- number_of_values_x: integer := 2048;
-- size_number_of_values_x : integer := 11
-- GOPPA [3307, 2515, 66, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 2;
-- size_pipeline_size : integer := 5;
-- gf_2_m : integer range 1 to 20 := 12;
-- polynomial_degree : integer := 66;
-- size_polynomial_degree : integer := 7;
-- number_of_values_x: integer := 3307;
-- size_number_of_values_x : integer := 12
-- QD-GOPPA [2528, 2144, 32, 12] --
number_of_pipelines : integer := 1;
pipeline_size : integer := 9;
size_pipeline_size : integer := 5;
gf_2_m : integer range 1 to 20 := 12;
polynomial_degree : integer := 32;
size_polynomial_degree : integer := 6;
number_of_values_x: integer := 2528;
size_number_of_values_x : integer := 12
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 2;
-- size_pipeline_size : integer := 5;
-- gf_2_m : integer range 1 to 20 := 12;
-- polynomial_degree : integer := 64;
-- size_polynomial_degree : integer := 6;
-- number_of_values_x: integer := 2816;
-- size_number_of_values_x : integer := 12
-- QD-GOPPA [3328, 2560, 64, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 2;
-- size_pipeline_size : integer := 5;
-- gf_2_m : integer range 1 to 20 := 12;
-- polynomial_degree : integer := 128;
-- size_polynomial_degree : integer := 7;
-- number_of_values_x: integer := 3200;
-- size_number_of_values_x : integer := 12
-- QD-GOPPA [7296, 5632, 128, 13] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 2;
-- size_pipeline_size : integer := 5;
-- gf_2_m : integer range 1 to 20 := 15;
-- polynomial_degree : integer := 128;
-- size_polynomial_degree : integer := 7;
-- number_of_values_x: integer := 8320;
-- size_number_of_values_x : integer := 14
);
Port(
value_x : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
value_x_pow : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
value_polynomial : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
last_evaluations : out STD_LOGIC;
evaluation_finalized : out STD_LOGIC;
address_value_polynomial : out STD_LOGIC_VECTOR((size_polynomial_degree - 1) downto 0);
address_value_x : out STD_LOGIC_VECTOR((size_number_of_values_x - 1) downto 0);
address_value_acc : out STD_LOGIC_VECTOR((size_number_of_values_x - 1) downto 0);
address_value_x_pow : out STD_LOGIC_VECTOR((size_number_of_values_x - 1) downto 0);
address_new_value_acc : out STD_LOGIC_VECTOR((size_number_of_values_x - 1) downto 0);
address_new_value_x_pow : out STD_LOGIC_VECTOR((size_number_of_values_x - 1) downto 0);
write_enable_new_value_acc : out STD_LOGIC;
write_enable_new_value_x_pow : out STD_LOGIC;
new_value_acc : out STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
new_value_x_pow : out STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0)
);
end polynomial_evaluator_n;
architecture RTL of polynomial_evaluator_n is
component pipeline_polynomial_calc
Generic (
gf_2_m : integer range 1 to 20 := 11;
size : integer := 2
);
Port (
value_x : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_polynomial : in STD_LOGIC_VECTOR((((gf_2_m)*size) - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_x_pow : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
clk : in STD_LOGIC;
new_value_x_pow : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_acc : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
component shift_register_rst_nbits
Generic (size : integer);
Port (
data_in : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0);
data_out : out STD_LOGIC
);
end component;
component shift_register_nbits
Generic (size : integer);
Port (
data_in : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR((size - 1) downto 0);
data_out : out STD_LOGIC
);
end component;
component register_nbits
Generic(size : integer);
Port(
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component register_rst_nbits
Generic(size : integer);
Port(
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_rst_nbits
Generic (
size : integer;
increment_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component controller_polynomial_evaluator
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
last_load_x_values : in STD_LOGIC;
last_store_x_values : in STD_LOGIC;
limit_polynomial_degree : in STD_LOGIC;
pipeline_ready : in STD_LOGIC;
evaluation_data_in : out STD_LOGIC;
reg_write_enable_rst : out STD_LOGIC;
ctr_load_x_address_ce : out STD_LOGIC;
ctr_load_x_address_rst : out STD_LOGIC;
ctr_store_x_address_ce : out STD_LOGIC;
ctr_store_x_address_rst : out STD_LOGIC;
reg_first_values_ce : out STD_LOGIC;
reg_first_values_rst : out STD_LOGIC;
ctr_address_polynomial_ce : out STD_LOGIC;
ctr_address_polynomial_rst : out STD_LOGIC;
shift_polynomial_ce_ce : out STD_LOGIC;
shift_polynomial_ce_rst : out STD_LOGIC;
last_coefficients : out STD_LOGIC;
evaluation_finalized : out STD_LOGIC
);
end component;
signal pipeline_value_acc : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
signal pipeline_value_x_pow : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
constant coefficient_zero : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(0, gf_2_m));
constant first_acc : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(0, gf_2_m));
constant first_x_pow : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(1, gf_2_m));
signal reg_polynomial_coefficients_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_polynomial_coefficients_ce : STD_LOGIC_VECTOR((pipeline_size - 1) downto 0);
signal reg_polynomial_coefficients_q : STD_LOGIC_VECTOR((((gf_2_m)*pipeline_size) - 1) downto 0);
signal shift_polynomial_ce_data_in : STD_LOGIC;
signal shift_polynomial_ce_ce : STD_LOGIC;
signal shift_polynomial_ce_rst : STD_LOGIC;
constant shift_polynomial_ce_rst_value : STD_LOGIC_VECTOR(pipeline_size downto 0) := std_logic_vector(to_unsigned(1, pipeline_size+1));
signal shift_polynomial_ce_q : STD_LOGIC_VECTOR(pipeline_size downto 0);
signal ctr_address_polynomial_ce : STD_LOGIC;
signal ctr_address_polynomial_rst : STD_LOGIC;
constant ctr_address_polynomial_rst_value : STD_LOGIC_VECTOR((size_polynomial_degree) downto 0) := std_logic_vector(to_unsigned(0, size_polynomial_degree+1));
signal ctr_address_polynomial_q : STD_LOGIC_VECTOR((size_polynomial_degree) downto 0);
signal ctr_load_x_address_ce : STD_LOGIC;
signal ctr_load_x_address_rst : STD_LOGIC;
constant ctr_load_x_address_rst_value : STD_LOGIC_VECTOR((size_number_of_values_x - 1) downto 0) := std_logic_vector(to_unsigned(0, size_number_of_values_x));
signal ctr_load_x_address_q : STD_LOGIC_VECTOR((size_number_of_values_x - 1) downto 0);
signal ctr_store_x_address_ce : STD_LOGIC;
signal ctr_store_x_address_rst : STD_LOGIC;
constant ctr_store_x_message_address_rst_value : STD_LOGIC_VECTOR((size_number_of_values_x - 1) downto 0) := std_logic_vector(to_unsigned(0, size_number_of_values_x));
signal ctr_store_x_address_q : STD_LOGIC_VECTOR((size_number_of_values_x - 1) downto 0);
signal reg_first_values_ce : STD_LOGIC;
signal reg_first_values_rst : STD_LOGIC;
signal reg_first_values_rst_value : STD_LOGIC_VECTOR(0 downto 0) := "1";
signal reg_first_values_q : STD_LOGIC_VECTOR(0 downto 0);
signal evaluation_data_in : STD_LOGIC;
signal evaluation_data_out : STD_LOGIC;
signal reg_write_enable_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_write_enable_rst : STD_LOGIC;
constant reg_write_enable_rst_value : STD_LOGIC_VECTOR(0 downto 0) := "0";
signal reg_write_enable_q : STD_LOGIC_VECTOR(0 downto 0);
signal pipeline_ready : STD_LOGIC;
signal limit_polynomial_degree : STD_LOGIC;
signal last_coefficients : STD_LOGIC;
signal last_load_x_values : STD_LOGIC;
signal last_store_x_values : STD_LOGIC;
begin
pipelines : for I in 0 to (number_of_pipelines - 1) generate
pipeline_I : pipeline_polynomial_calc
Generic Map (
gf_2_m => gf_2_m,
size => pipeline_size
)
Port Map(
value_x => value_x(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))),
value_polynomial => reg_polynomial_coefficients_q,
value_acc => pipeline_value_acc(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))),
value_x_pow => pipeline_value_x_pow(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))),
clk => clk,
new_value_x_pow => new_value_x_pow(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))),
new_value_acc => new_value_acc(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I)))
);
pipeline_value_acc(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))) <= first_acc when reg_first_values_q = "1" else
value_acc(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I)));
pipeline_value_x_pow(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I))) <= first_x_pow when reg_first_values_q = "1" else
value_x_pow(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I)));
end generate;
polynomial : for I in 0 to (pipeline_size - 1) generate
reg_polynomial_coefficients_I : register_nbits
Generic Map (size => gf_2_m)
Port Map(
d => reg_polynomial_coefficients_d,
clk => clk,
ce => reg_polynomial_coefficients_ce(I),
q => reg_polynomial_coefficients_q(((gf_2_m)*(I + 1) - 1) downto ((gf_2_m)*(I)))
);
end generate;
controller : controller_polynomial_evaluator
Port Map(
clk => clk,
rst => rst,
last_load_x_values => last_load_x_values,
last_store_x_values => last_store_x_values,
limit_polynomial_degree => limit_polynomial_degree,
pipeline_ready => pipeline_ready,
evaluation_data_in => evaluation_data_in,
reg_write_enable_rst => reg_write_enable_rst,
ctr_load_x_address_ce => ctr_load_x_address_ce,
ctr_load_x_address_rst => ctr_load_x_address_rst,
ctr_store_x_address_ce => ctr_store_x_address_ce,
ctr_store_x_address_rst => ctr_store_x_address_rst,
reg_first_values_ce => reg_first_values_ce,
reg_first_values_rst => reg_first_values_rst,
ctr_address_polynomial_ce => ctr_address_polynomial_ce,
ctr_address_polynomial_rst => ctr_address_polynomial_rst,
shift_polynomial_ce_ce => shift_polynomial_ce_ce,
shift_polynomial_ce_rst => shift_polynomial_ce_rst,
last_coefficients => last_coefficients,
evaluation_finalized => evaluation_finalized
);
shift_polynomial_ce : shift_register_rst_nbits
Generic Map(
size => pipeline_size + 1
)
Port Map(
data_in => shift_polynomial_ce_data_in,
clk => clk,
ce => shift_polynomial_ce_ce,
rst => shift_polynomial_ce_rst,
rst_value => shift_polynomial_ce_rst_value,
q => shift_polynomial_ce_q,
data_out => shift_polynomial_ce_data_in
);
evaluation : shift_register_nbits
Generic Map(
size => pipeline_size - 1
)
Port Map(
data_in => evaluation_data_in,
clk => clk,
ce => '1',
q => open,
data_out => evaluation_data_out
);
reg_write_enable : register_rst_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_write_enable_d,
clk => clk,
ce => '1',
rst => reg_write_enable_rst,
rst_value => reg_write_enable_rst_value,
q => reg_write_enable_q
);
ctr_address_polynomial : counter_rst_nbits
Generic Map(
size => size_polynomial_degree+1,
increment_value => 1
)
Port Map(
clk => clk,
ce => ctr_address_polynomial_ce,
rst => ctr_address_polynomial_rst,
rst_value => ctr_address_polynomial_rst_value,
q => ctr_address_polynomial_q
);
ctr_load_x_address : counter_rst_nbits
Generic Map(
size => size_number_of_values_x,
increment_value => number_of_pipelines
)
Port Map(
clk => clk,
ce => ctr_load_x_address_ce,
rst => ctr_load_x_address_rst,
rst_value => ctr_load_x_address_rst_value,
q => ctr_load_x_address_q
);
ctr_store_x_address : counter_rst_nbits
Generic Map(
size => size_number_of_values_x,
increment_value => number_of_pipelines
)
Port Map(
clk => clk,
ce => ctr_store_x_address_ce,
rst => ctr_store_x_address_rst,
rst_value => ctr_store_x_message_address_rst_value,
q => ctr_store_x_address_q
);
reg_first_values : register_rst_nbits
Generic Map(size => 1)
Port Map(
d => "0",
clk => clk,
ce => reg_first_values_ce,
rst => reg_first_values_rst,
rst_value => reg_first_values_rst_value,
q => reg_first_values_q
);
reg_polynomial_coefficients_d <= coefficient_zero when last_coefficients = '1' else
value_polynomial;
reg_polynomial_coefficients_ce <= shift_polynomial_ce_q((pipeline_size - 1) downto 0);
address_value_polynomial <= ctr_address_polynomial_q((size_polynomial_degree - 1) downto 0);
address_value_x <= ctr_load_x_address_q;
address_value_acc <= ctr_load_x_address_q;
address_value_x_pow <= ctr_load_x_address_q;
address_new_value_acc <= ctr_store_x_address_q;
address_new_value_x_pow <= ctr_store_x_address_q;
pipeline_ready <= shift_polynomial_ce_q(pipeline_size-1);
limit_polynomial_degree <= '1' when (unsigned(ctr_address_polynomial_q) = to_unsigned(polynomial_degree+1, ctr_address_polynomial_q'length)) else '0';
last_evaluations <= limit_polynomial_degree and shift_polynomial_ce_q(pipeline_size);
reg_write_enable_d(0) <= evaluation_data_out;
write_enable_new_value_acc <= reg_write_enable_q(0);
write_enable_new_value_x_pow <= reg_write_enable_q(0);
last_load_x_values <= '1' when ctr_load_x_address_q = std_logic_vector(to_unsigned(((number_of_values_x - 1)/number_of_pipelines)*number_of_pipelines, ctr_load_x_address_q'Length)) else '0';
last_store_x_values <= '1' when ctr_store_x_address_q = std_logic_vector(to_unsigned(((number_of_values_x - 1)/number_of_pipelines)*number_of_pipelines, ctr_load_x_address_q'Length)) else '0';
end RTL; | bsd-2-clause | 281ee4294ee4b8955663bc13efd4d17e | 0.665776 | 2.869628 | false | false | false | false |
pmassolino/hw-goppa-mceliece | mceliece/backup/controller_syndrome_calculator_2_pipe_v2.vhd | 1 | 22,800 | ----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Controller_Syndrome_Calculator_2_pipe_v2
-- Module Name: Controller_Syndrome_Calculator_2_pipe_v2
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 1st step in Goppa Code Decoding.
--
-- This circuit is the state machine that controls the syndrome_calculator_n_pipe_v2
--
-- Dependencies:
-- VHDL-93
--
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity controller_syndrome_calculator_2_pipe_v2 is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
almost_units_ready : in STD_LOGIC;
empty_units : in STD_LOGIC;
limit_ctr_codeword_q : in STD_LOGIC;
limit_ctr_syndrome_q : in STD_LOGIC;
reg_first_syndrome_q : in STD_LOGIC_VECTOR(0 downto 0);
reg_codeword_q : in STD_LOGIC_VECTOR(0 downto 0);
syndrome_finalized : out STD_LOGIC;
write_enable_new_syndrome : out STD_LOGIC;
control_units_ce : out STD_LOGIC;
control_units_rst : out STD_LOGIC;
int_reg_L_ce : out STD_LOGIC;
square_h : out STD_LOGIC;
int_reg_h_ce : out STD_LOGIC;
int_reg_h_rst : out STD_LOGIC;
int_sel_reg_h : out STD_LOGIC;
reg_load_L_ce : out STD_LOGIC;
reg_load_h_ce : out STD_LOGIC;
reg_load_h_rst : out STD_LOGIC;
reg_load_syndrome_ce : out STD_LOGIC;
reg_load_syndrome_rst : out STD_LOGIC;
reg_new_value_syndrome_ce : out STD_LOGIC;
reg_codeword_ce : out STD_LOGIC;
reg_first_syndrome_ce : out STD_LOGIC;
reg_first_syndrome_rst : out STD_LOGIC;
ctr_load_address_syndrome_ce : out STD_LOGIC;
ctr_load_address_syndrome_rst : out STD_LOGIC;
reg_bus_address_syndrome_ce : out STD_LOGIC;
reg_calc_address_syndrome_ce : out STD_LOGIC;
reg_store_address_syndrome_ce : out STD_LOGIC;
ctr_load_address_codeword_ce : out STD_LOGIC;
ctr_load_address_codeword_rst : out STD_LOGIC;
reg_load_limit_codeword_rst : out STD_LOGIC;
reg_load_limit_codeword_ce : out STD_LOGIC;
reg_calc_limit_codeword_rst : out STD_LOGIC;
reg_calc_limit_codeword_ce : out STD_LOGIC
);
end controller_syndrome_calculator_2_pipe_v2;
architecture Behavioral of controller_syndrome_calculator_2_pipe_v2 is
type State is (reset, load_counters, prepare_values, load_values, jump_codeword, clear_remaining_units, prepare_synd, prepare_synd_2, prepare_synd_3, load_store_synd, final);
signal actual_state, next_state : State;
begin
Clock: process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
actual_state <= reset;
else
actual_state <= next_state;
end if;
end if;
end process;
Output: process (actual_state, limit_ctr_codeword_q, limit_ctr_syndrome_q, reg_first_syndrome_q, reg_codeword_q, almost_units_ready, empty_units)
begin
case (actual_state) is
when reset =>
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '1';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '1';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '1';
reg_new_value_syndrome_ce <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '1';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '1';
reg_bus_address_syndrome_ce <= '0';
reg_calc_address_syndrome_ce <= '0';
reg_store_address_syndrome_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '1';
reg_load_limit_codeword_rst <= '1';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '1';
reg_calc_limit_codeword_ce <= '0';
when load_counters =>
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '1';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '1';
reg_new_value_syndrome_ce <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '1';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '1';
reg_bus_address_syndrome_ce <= '0';
reg_calc_address_syndrome_ce <= '0';
reg_store_address_syndrome_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '1';
reg_load_limit_codeword_rst <= '1';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '1';
reg_calc_limit_codeword_ce <= '0';
when prepare_values =>
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '0';
reg_bus_address_syndrome_ce <= '0';
reg_calc_address_syndrome_ce <= '0';
reg_store_address_syndrome_ce <= '0';
ctr_load_address_codeword_ce <= '1';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '1';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '1';
when load_values =>
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '1';
reg_load_h_ce <= '1';
reg_load_h_rst <= '0';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_codeword_ce <= '1';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '0';
reg_bus_address_syndrome_ce <= '0';
reg_calc_address_syndrome_ce <= '0';
reg_store_address_syndrome_ce <= '0';
ctr_load_address_codeword_ce <= '1';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '1';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '1';
when jump_codeword =>
if(reg_codeword_q(0) = '1') then
if(almost_units_ready = '1' or limit_ctr_codeword_q = '1') then
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '1';
control_units_rst <= '0';
int_reg_L_ce <= '1';
square_h <= '0';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '1';
reg_load_h_ce <= '1';
reg_load_h_rst <= '0';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_codeword_ce <= '1';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '1';
reg_bus_address_syndrome_ce <= '0';
reg_calc_address_syndrome_ce <= '0';
reg_store_address_syndrome_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
else
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '1';
control_units_rst <= '0';
int_reg_L_ce <= '1';
square_h <= '0';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '1';
reg_load_h_ce <= '1';
reg_load_h_rst <= '0';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_codeword_ce <= '1';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '1';
reg_bus_address_syndrome_ce <= '0';
reg_calc_address_syndrome_ce <= '0';
reg_store_address_syndrome_ce <= '0';
ctr_load_address_codeword_ce <= '1';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '1';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '1';
end if;
elsif(limit_ctr_codeword_q = '1') then
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '1';
reg_load_h_ce <= '1';
reg_load_h_rst <= '0';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_codeword_ce <= '1';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '0';
reg_bus_address_syndrome_ce <= '0';
reg_calc_address_syndrome_ce <= '0';
reg_store_address_syndrome_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
else
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '1';
reg_load_h_ce <= '1';
reg_load_h_rst <= '0';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_codeword_ce <= '1';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '0';
reg_bus_address_syndrome_ce <= '0';
reg_calc_address_syndrome_ce <= '0';
reg_store_address_syndrome_ce <= '0';
ctr_load_address_codeword_ce <= '1';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '1';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '1';
end if;
when clear_remaining_units =>
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '1';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '1';
int_sel_reg_h <= '0';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '0';
reg_bus_address_syndrome_ce <= '0';
reg_calc_address_syndrome_ce <= '0';
reg_store_address_syndrome_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
when prepare_synd =>
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '1';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '1';
ctr_load_address_syndrome_rst <= '0';
reg_bus_address_syndrome_ce <= '1';
reg_calc_address_syndrome_ce <= '0';
reg_store_address_syndrome_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
when prepare_synd_2 =>
if(reg_first_syndrome_q(0) = '1') then
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '1';
reg_new_value_syndrome_ce <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '1';
ctr_load_address_syndrome_rst <= '0';
reg_bus_address_syndrome_ce <= '1';
reg_calc_address_syndrome_ce <= '1';
reg_store_address_syndrome_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
else
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_load_syndrome_ce <= '1';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '1';
ctr_load_address_syndrome_rst <= '0';
reg_bus_address_syndrome_ce <= '1';
reg_calc_address_syndrome_ce <= '1';
reg_store_address_syndrome_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
end if;
when prepare_synd_3 =>
if(reg_first_syndrome_q(0) = '1') then
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '1';
reg_new_value_syndrome_ce <= '1';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '1';
ctr_load_address_syndrome_rst <= '0';
reg_bus_address_syndrome_ce <= '1';
reg_calc_address_syndrome_ce <= '1';
reg_store_address_syndrome_ce <= '1';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
else
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_load_syndrome_ce <= '1';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '1';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '1';
ctr_load_address_syndrome_rst <= '0';
reg_bus_address_syndrome_ce <= '1';
reg_calc_address_syndrome_ce <= '1';
reg_store_address_syndrome_ce <= '1';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
end if;
when load_store_synd =>
if(limit_ctr_syndrome_q = '1') then
syndrome_finalized <= '0';
write_enable_new_syndrome <= '1';
control_units_ce <= '1';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_load_syndrome_ce <= '1';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '1';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '1';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '1';
reg_bus_address_syndrome_ce <= '0';
reg_calc_address_syndrome_ce <= '0';
reg_store_address_syndrome_ce <= '0';
ctr_load_address_codeword_ce <= '1';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '1';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '1';
else
syndrome_finalized <= '0';
write_enable_new_syndrome <= '1';
control_units_ce <= '0';
control_units_rst <= '0';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '1';
int_reg_h_rst <= '0';
int_sel_reg_h <= '1';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_load_syndrome_ce <= '1';
reg_load_syndrome_rst <= '0';
reg_new_value_syndrome_ce <= '1';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_load_address_syndrome_ce <= '1';
ctr_load_address_syndrome_rst <= '0';
reg_bus_address_syndrome_ce <= '1';
reg_calc_address_syndrome_ce <= '1';
reg_store_address_syndrome_ce <= '1';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '0';
reg_load_limit_codeword_rst <= '0';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '0';
reg_calc_limit_codeword_ce <= '0';
end if;
when final =>
syndrome_finalized <= '1';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '1';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '0';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '1';
reg_new_value_syndrome_ce <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '1';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '1';
reg_bus_address_syndrome_ce <= '0';
reg_calc_address_syndrome_ce <= '0';
reg_store_address_syndrome_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '1';
reg_load_limit_codeword_rst <= '1';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '1';
reg_calc_limit_codeword_ce <= '0';
when others =>
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
control_units_ce <= '0';
control_units_rst <= '1';
int_reg_L_ce <= '0';
square_h <= '0';
int_reg_h_ce <= '0';
int_reg_h_rst <= '0';
int_sel_reg_h <= '0';
reg_load_L_ce <= '0';
reg_load_h_ce <= '0';
reg_load_h_rst <= '1';
reg_load_syndrome_ce <= '0';
reg_load_syndrome_rst <= '1';
reg_new_value_syndrome_ce <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '1';
ctr_load_address_syndrome_ce <= '0';
ctr_load_address_syndrome_rst <= '1';
reg_bus_address_syndrome_ce <= '0';
reg_calc_address_syndrome_ce <= '0';
reg_store_address_syndrome_ce <= '0';
ctr_load_address_codeword_ce <= '0';
ctr_load_address_codeword_rst <= '1';
reg_load_limit_codeword_rst <= '1';
reg_load_limit_codeword_ce <= '0';
reg_calc_limit_codeword_rst <= '1';
reg_calc_limit_codeword_ce <= '0';
end case;
end process;
NewState: process (actual_state, limit_ctr_codeword_q, limit_ctr_syndrome_q, reg_first_syndrome_q, reg_codeword_q, almost_units_ready, empty_units)
begin
case (actual_state) is
when reset =>
next_state <= load_counters;
when load_counters =>
next_state <= prepare_values;
when prepare_values =>
next_state <= load_values;
when load_values =>
next_state <= jump_codeword;
when jump_codeword =>
if(reg_codeword_q(0) = '1') then
if(almost_units_ready = '1') then
next_state <= prepare_synd;
elsif(limit_ctr_codeword_q = '1') then
next_state <= clear_remaining_units;
else
next_state <= jump_codeword;
end if;
elsif(limit_ctr_codeword_q = '1') then
if(empty_units = '1') then
next_state <= final;
else
next_state <= clear_remaining_units;
end if;
else
next_state <= jump_codeword;
end if;
when clear_remaining_units =>
if(almost_units_ready = '1') then
next_state <= prepare_synd;
else
next_state <= clear_remaining_units;
end if;
when prepare_synd =>
next_state <= prepare_synd_2;
when prepare_synd_2 =>
next_state <= prepare_synd_3;
when prepare_synd_3 =>
next_state <= load_store_synd;
when load_store_synd =>
if(limit_ctr_syndrome_q = '1') then
if(limit_ctr_codeword_q = '1') then
next_state <= final;
else
next_state <= jump_codeword;
end if;
else
next_state <= load_store_synd;
end if;
when final =>
next_state <= final;
when others =>
next_state <= reset;
end case;
end process;
end Behavioral; | bsd-2-clause | ab93da2a42be2932f6b0995cfdf870e4 | 0.577237 | 2.600068 | false | false | false | false |
Xero-Hige/LuGus-VHDL | TPS-2016/tps-Gaston/TP1-Contador/bcd_counter_tb.vhd | 1 | 809 | library ieee;
use ieee.std_logic_1164.all;
entity bcd_counter_tb is
end;
architecture bcd_counter_tb_func of bcd_counter_tb is
signal rst_in: std_logic:='1';
signal clk_in: std_logic:='0';
signal ena_in: std_logic:='0';
signal carry_out: std_logic;
signal counter_out: std_logic_vector(3 downto 0);
component bcd_counter is
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
counter_out: out std_logic_vector(3 downto 0);
carry_out: out std_logic
);
end component;
begin
clk_in <= not(clk_in) after 1 ns;
rst_in <= '0' after 10 ns;
ena_in <= '1' after 20 ns;
bcd_counterMap: bcd_counter
port map(
clk => clk_in,
rst => rst_in,
ena => ena_in,
counter_out => counter_out,
carry_out => carry_out
);
end architecture;
| gpl-3.0 | d0484dd80bbaa792b3b610126d79824a | 0.631644 | 2.714765 | false | false | false | false |
Ricky-Gong/LegoCar | DE0-Nano/DE0Course/ip/TERASIC_ADC_READ/ADC_READ.vhd | 3 | 4,608 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ADC_READ IS
PORT (
clk : IN STD_LOGIC;
reset_n : IN STD_LOGIC;
Channel : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
Data : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
Start : IN STD_LOGIC;
Done : OUT STD_LOGIC;
oDIN : OUT STD_LOGIC;
oCS_n : OUT STD_LOGIC;
oSCLK : OUT STD_LOGIC;
iDOUT : IN STD_LOGIC
);
END ADC_READ;
ARCHITECTURE TERASIC OF ADC_READ IS
TYPE STATE IS (st_00,st_01,st_02,st_03);
SIGNAL st : STATE;
SIGNAL start_en : STD_LOGIC;
SIGNAL start_ack : STD_LOGIC;
SIGNAL read_en : STD_LOGIC;
SIGNAL read_ack : STD_LOGIC;
SIGNAL read_cont : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL read_clk : STD_LOGIC;
SIGNAL read_data : STD_LOGIC_VECTOR(11 DOWNTO 0);
---------------------------------------------------------------------------------------------
--PROGRAM START
BEGIN
PROCESS(clk,reset_n)
BEGIN
IF reset_n = '0' THEN
st <= st_00;
ELSIF clk'EVENT AND clk = '1' THEN
CASE st IS
WHEN st_00 =>
IF start_en = '1' THEN
st <= st_01;
END IF;
WHEN st_01 => --READ DATA
IF read_ack = '1' THEN
st <= st_02;
END IF;
WHEN st_02 => --READ DATA to register
st <= st_03;
WHEN st_03 => --finish
IF start_en = '1' THEN
st <= st_01;
END IF;
END CASE;
END IF;
END PROCESS;
--------------------------------------------------------------------------------------------
-- STATUS CONTROL
PROCESS(Start,start_ack)
BEGIN
IF start_ack = '1' THEN
start_en <= '0';
ELSIF Start' EVENT AND Start = '1' THEN
start_en <= '1';
END IF;
END PROCESS;
WITH st SELECT
read_en <= '1' WHEN st_01,
'0' WHEN OTHERS;
WITH st SELECT
read_clk <= '0' WHEN st_02,
'1' WHEN OTHERS;
WITH st SELECT
oSCLK <= clk WHEN st_01,
'1' WHEN OTHERS;
WITH st SELECT
oCS_n <= '1' WHEN st_00|st_03,
'0' WHEN OTHERS;
WITH st SELECT
Done <= '1' WHEN st_03,
'0' WHEN OTHERS;
WITH st SELECT
start_ack <= '1' WHEN st_02,
'0' WHEN OTHERS;
--------------------------------------------------------------------------------------------
-- st_01
PROCESS(clk,read_en)
BEGIN
IF read_en = '0' THEN
read_cont <= "0000";
ELSIF clk' EVENT AND clk = '1' THEN
read_cont <= read_cont + '1';
END IF;
IF read_en = '0' THEN
read_ack <= '0';
ELSIF clk' EVENT AND clk = '0' THEN
IF read_cont >= "1111" THEN
read_ack <= '1';
ELSE
read_ack <= '0';
END IF;
END IF;
END PROCESS;
PROCESS(clk,read_en) --A/D CH SELECT
BEGIN
IF clk' EVENT AND clk = '0' THEN
IF read_cont = "0010" THEN --ADDR2
oDIN <= Channel(2);
ELSIF read_cont = "0011" THEN --ADDR1
oDIN <= Channel(1);
ELSIF read_cont = "0100" THEN --ADDR0
oDIN <= Channel(0);
ELSE
oDIN <= '0';
END IF;
END IF;
IF read_en = '0' THEN --A/D DATA READ
read_data <= read_data;
ELSIF clk' EVENT AND clk = '1' THEN
IF read_cont = "0100" THEN
read_data(11) <= iDOUT;
ELSIF read_cont = "0101" THEN
read_data(10) <= iDOUT;
ELSIF read_cont = "0110" THEN
read_data(9) <= iDOUT;
ELSIF read_cont = "0111" THEN
read_data(8) <= iDOUT;
ELSIF read_cont = "1000" THEN
read_data(7) <= iDOUT;
ELSIF read_cont = "1001" THEN
read_data(6) <= iDOUT;
ELSIF read_cont= "1010" THEN
read_data(5) <= iDOUT;
ELSIF read_cont = "1011" THEN
read_data(4) <= iDOUT;
ELSIF read_cont = "1100" THEN
read_data(3) <= iDOUT;
ELSIF read_cont = "1101" THEN
read_data(2) <= iDOUT;
ELSIF read_cont = "1110" THEN
read_data(1) <= iDOUT;
ELSIF read_cont = "1111" THEN
read_data(0) <= iDOUT;
END IF;
END IF;
END PROCESS;
--------------------------------------------------------------------------------------------
-- st_02
PROCESS(read_clk,reset_n)
BEGIN
IF reset_n = '0' THEN
Data <= "000000000000";
ELSIF read_clk' EVENT AND read_clk = '1' THEN
Data <= read_data;
END IF;
END PROCESS;
--------------------------------------------------------------------------------------------
-- OUTPUT CONTROL
--------------------------------------------------------------------------------------------
END TERASIC;
| gpl-2.0 | b1089fde4c10a2d91aa6738b480f388e | 0.469401 | 2.851485 | false | false | false | false |
ruygargar/LCSE_lab | doc/PIC/PICtop.vhd | 1 | 1,635 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.PIC_pkg.all;
entity PICtop is
port (
Reset : in std_logic; -- Asynchronous, active low
Clk : in std_logic; -- System clock, 20 MHz, rising_edge
RS232_RX : in std_logic; -- RS232 RX line
RS232_TX : out std_logic; -- RS232 TX line
switches : out std_logic_vector(7 downto 0); -- Switch status bargraph
Temp_L : out std_logic_vector(6 downto 0); -- Less significant figure of T_STAT
Temp_H : out std_logic_vector(6 downto 0)); -- Most significant figure of T_STAT
end PICtop;
architecture behavior of PICtop is
component RS232top
port (
Reset : in std_logic;
Clk : in std_logic;
Data_in : in std_logic_vector(7 downto 0);
Valid_D : in std_logic;
Ack_in : out std_logic;
TX_RDY : out std_logic;
TD : out std_logic;
RD : in std_logic;
Data_out : out std_logic_vector(7 downto 0);
Data_read : in std_logic;
Full : out std_logic;
Empty : out std_logic);
end component;
begin -- behavior
RS232_PHY: RS232top
port map (
Reset => Reset,
Clk => Clk,
Data_in => TX_Data,
Valid_D => Valid_D,
Ack_in => Ack_out,
TX_RDY => TX_RDY,
TD => RS232_TX,
RD => RS232_RX,
Data_out => RCVD_Data,
Data_read => Data_read,
Full => RX_Full,
Empty => RX_Empty);
end behavior;
| gpl-3.0 | 2c8ad667a72985fcbb5add3ff25e8c3e | 0.538226 | 3.31643 | false | false | false | false |
Xero-Hige/LuGus-VHDL | TPS-2016/tps-Lucho/TP1-Contador/bcd_controller/bcd_controller.vhd | 1 | 6,219 | library ieee;
use ieee.std_logic_1164.all;
entity bcd_controller is
port(
rst: in std_logic;
clk: in std_logic;
anod_out: out std_logic_vector(3 downto 0);
a: out std_logic;
b: out std_logic;
c: out std_logic;
d: out std_logic;
e: out std_logic;
f: out std_logic;
g: out std_logic;
dp: out std_logic
);
attribute LOC : string;
attribute LOC of clk: signal is "B8";
attribute LOC of anod_out: signal is "F15 C18 H17 F17";
attribute LOC of rst: signal is "B18";
attribute LOC of a: signal is "L18";
attribute LOC of b: signal is "F18";
attribute LOC of c: signal is "D17";
attribute LOC of d: signal is "D16";
attribute LOC of e: signal is "G14";
attribute LOC of f: signal is "J17";
attribute LOC of g: signal is "H14";
attribute LOC of dp: signal is "C17";
end entity;
architecture bcd_controller_arq of bcd_controller is
signal multiplexer_to_decoder: std_logic_vector(3 downto 0); --Signal from counter multiplexer to bcd decoder
signal anod_enabler_to_anod_counter: std_logic; --Connects anod enabler output with anod counter to control counting frequence
signal anod_counter_to_multiplexer: std_logic_vector(1 downto 0); --Connects anod counter with bcd multiplexer
signal c_out0: std_logic;
signal c_out1: std_logic;
signal c_out2: std_logic;
signal counter_enabler_to_bcd_counter: std_logic;
signal counter_to_mp0: std_logic_vector(3 downto 0);
signal counter_to_mp1: std_logic_vector(3 downto 0);
signal counter_to_mp2: std_logic_vector(3 downto 0);
signal counter_to_mp3: std_logic_vector(3 downto 0);
--Needed to make de AND work
signal ena_to_bcd_counter1: std_logic;
signal ena_to_bcd_counter2: std_logic;
signal ena_to_bcd_counter3: std_logic;
--Para contar y activar los anodos
component genericCounter is
generic (
BITS:natural := 4;
MAX_COUNT:natural := 15);
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
count: out std_logic_vector(BITS-1 downto 0);
carry_o: out std_logic
);
end component;
--Para multiplexar las entradas
component four_port_multiplexer is
generic(
BITS:natural := 1);
port (
data_in_a: in std_logic_vector(BITS-1 downto 0);
data_in_b: in std_logic_vector(BITS-1 downto 0);
data_in_c: in std_logic_vector(BITS-1 downto 0);
data_in_d: in std_logic_vector(BITS-1 downto 0);
select_in: in std_logic_vector(1 downto 0); --2 bits, 4 opciones
data_out: out std_logic_vector(BITS-1 downto 0)
);
end component;
--Para regular la frecuencia en la que se activan los anodos
component generic_enabler is
generic(PERIOD:natural := 1000000 ); --1MHz
port(
clk: in std_logic;
rst: in std_logic;
ena_out: out std_logic
);
end component;
component contBCD is
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
s: out std_logic_vector(3 downto 0);
co: out std_logic
);
end component;
--Para decodificar la entrada
component decoBCD is
port(
ena: in std_logic; --Estara conectado al anodo del BCD para habilitarlo o no
count: in std_logic_vector(3 downto 0); --Bits del contador
a: out std_logic;
b: out std_logic;
c: out std_logic;
d: out std_logic;
e: out std_logic;
f: out std_logic;
g: out std_logic;
dp: out std_logic;
anod: out std_logic
);
end component;
--To decode from binary to anod code
component anod_enabler_decoder is
port(
binary_in: in std_logic_vector(1 downto 0); --"2 bit vector to switch between the 4 possible anod values"
code_out: out std_logic_vector(3 downto 0) --4 bit output to switch between anod
);
end component;
begin
ena_to_bcd_counter1 <= c_out0 AND counter_enabler_to_bcd_counter;
ena_to_bcd_counter2 <= c_out1 AND ena_to_bcd_counter1;
ena_to_bcd_counter3 <= c_out2 AND ena_to_bcd_counter2;
--Need one counter to count between the anods
anodCounter: genericCounter generic map (2,3) --2 bits, cuenta hasta 3
port map(
clk => anod_enabler_to_anod_counter,
rst => '0',
ena => '1',
--carry_o => '0', --El count_dummy esta conectado siempre a tierra.
count => anod_counter_to_multiplexer
);
--Need one decoder to decode from binary to anod code
anodEnablerDecoder: anod_enabler_decoder
port map(
binary_in => anod_counter_to_multiplexer,
code_out => anod_out
);
--Need one enabler to control the speed of anod switching
anodEnabler: generic_enabler generic map (300)
port map(
clk => clk,
rst => '0',
ena_out => anod_enabler_to_anod_counter
);
--Need a generic enabler to control count frequency
counterEnabler: generic_enabler generic map (50000000) --50MHz
port map(
clk => clk,
rst => rst,
ena_out => counter_enabler_to_bcd_counter
);
--Need 4 bcd counters
bcdCounter0: contBCD
port map(
clk => clk,
rst => rst,
ena => counter_enabler_to_bcd_counter, --The input is generated by the enabler
s => counter_to_mp0,
co => c_out0
);
bcdCounter1: contBCD
port map(
clk => clk,
rst => rst,
ena => ena_to_bcd_counter1,
s => counter_to_mp1,
co => c_out1
);
bcdCounter2: contBCD
port map(
clk => clk,
rst => rst,
ena => ena_to_bcd_counter2,
s => counter_to_mp2,
co => c_out2
);
bcdCounter3: contBCD
port map(
clk => clk,
rst => rst,
ena => ena_to_bcd_counter3,
s => counter_to_mp3
--co
);
--Need a multiplexer to switch between the bcd counters
bcdCounterMultiplexer: four_port_multiplexer generic map (4) --4 bits inputs
port map(
data_in_a => counter_to_mp0,
data_in_b => counter_to_mp1,
data_in_c => counter_to_mp2,
data_in_d => counter_to_mp3,
select_in => anod_counter_to_multiplexer,
data_out => multiplexer_to_decoder
);
decoBCDMap: decoBCD
port map(
ena => '1',
count => multiplexer_to_decoder,
a => a,
b => b,
c => c,
d => d,
e => e,
f => f,
g => g,
dp => dp
--anod => not('1') --siempre activado
);
end; | gpl-3.0 | 190bdf802f307fd05be1550ceac13875 | 0.636276 | 2.998554 | false | false | false | false |
pmassolino/hw-goppa-mceliece | mceliece/util/counter_decrement_load_nbits.vhd | 1 | 1,818 | ----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Counter_decrement_load_n_bits
-- Module Name: Counter_decrement_load_n_bits
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Counter of size bits with no reset signal, that only decrements when ce equals to 1.
-- The counter has a synchronous load signal, which will register the value on input d,
-- when load is 1.
--
-- The circuits parameters
--
-- size :
--
-- The size of the counter in bits.
--
-- decrement_value :
--
-- The amount will be decremented each cycle.
--
-- Dependencies:
-- VHDL-93
--
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity counter_decrement_load_nbits is
Generic (
size : integer;
decrement_value : integer
);
Port (
d : in STD_LOGIC_VECTOR((size - 1) downto 0);
clk : in STD_LOGIC;
load : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR((size - 1) downto 0)
);
end counter_decrement_load_nbits;
architecture Behavioral of counter_decrement_load_nbits is
signal internal_value : UNSIGNED((size - 1) downto 0);
begin
process(clk, ce)
begin
if(clk'event and clk = '1')then
if(ce = '1') then
if(load = '1') then
internal_value <= unsigned(d);
else
internal_value <= internal_value - to_unsigned(decrement_value, internal_value'Length);
end if;
else
null;
end if;
end if;
end process;
q <= std_logic_vector(internal_value);
end Behavioral; | bsd-2-clause | 29d894e5811ad39abe2d433cdacaf112 | 0.614961 | 3.449715 | false | false | false | false |
rajvinjamuri/ECE385_VHDL | game_handler.vhd | 1 | 2,877 | ---------------------------------------------------------------------------
-- game_handler.vhd --
-- Raj Vinjamuri --
-- 4-13 --
-- --
-- Purpose/Description: --
-- handles game status --
-- --
-- based on 4-bit register given by UIUC --
-- Final Modifications by Raj Vinjamuri and Sai Koppula --
-- --
-- see theory.txt for what each bit means --
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity game_handler is
Port ( frame_clk : in std_logic;
paddle_loss_statusIn : in std_logic_vector(1 downto 0);
win_statusIn, ResetIn, ResetScore : in std_logic;
brick_hitIn : in std_logic_vector(19 downto 0);
score: out std_logic_vector(7 downto 0);
game_status : out std_logic_vector(3 downto 0));
end game_handler;
architecture Behavioral of game_handler is
signal reg_value: std_logic_vector(3 downto 0);
signal scoreSig: std_logic_vector(7 downto 0);
begin
operate_reg: process(paddle_loss_statusIn, brick_hitIn, win_statusIn, ResetIn)
begin
if (ResetIn = '1') then
reg_value <= "0000";
elsif(rising_edge(frame_clk)) then
reg_value(0) <= paddle_loss_statusIn(0);
reg_value(1) <= paddle_loss_statusIn(1);
reg_value(2) <= (brick_hitIn(0) OR brick_hitIn(1) OR brick_hitIn(2) OR brick_hitIn(3) OR
brick_hitIn(4) OR brick_hitIn(5) OR brick_hitIn(6) OR brick_hitIn(7) OR
brick_hitIn(8) OR brick_hitIn(9) OR brick_hitIn(10) OR brick_hitIn(11) OR
brick_hitIn(12) OR brick_hitIn(13) OR brick_hitIn(14) OR brick_hitIn(15) OR
brick_hitIn(16) OR brick_hitIn(17) OR brick_hitIn(18) OR brick_hitIn(19));
reg_value(3) <= win_statusIn;
end if;
end process;
operate_score: process(reg_value, ResetScore)
begin
if (ResetScore = '1') then
scoreSig <= "00000000";
elsif(rising_edge(frame_clk)) then
if (reg_value(1) = '1') then
scoreSig <= scoreSig + "00000001";
elsif (reg_value(2) = '1') then
scoreSig <= scoreSig + "00001010";
elsif (reg_value(3) = '1') then
scoreSig <= scoreSig + "00110010";
else
scoreSig <= scoreSig;
end if;
end if;
end process;
-- decimel: process(scoreOutSig)
-- begin
-- scoreH <= (scoreOutSig mod "00001010");
-- scoreL <=
score <= scoreSig;
game_status <= reg_value;
end Behavioral; | mit | 526771dc56101e23f615156fb9137d25 | 0.509559 | 3.697943 | false | false | false | false |
pmassolino/hw-goppa-mceliece | mceliece/util/counter_double_rst_nbits.vhd | 1 | 2,190 | ----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Counter_double_rst_n_bits
-- Module Name: Counter_double_rst_n_bits
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Counter of size bits with reset signal, that only increments when ce equals to 1.
-- The reset is synchronous and the value loaded during reset is defined by reset_value.
-- This counter has two different values that can be incremented.
--
-- The circuits parameters
--
-- size :
--
-- The size of the counter in bits.
--
-- increment_value_0 :
--
-- The amount will be incremented each cycle, if increment_value = 0.
--
-- increment_value_1 :
--
-- The amount will be incremented each cycle, if increment_value = 1.
--
-- Dependencies:
-- VHDL-93
--
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity counter_double_rst_nbits is
Generic (
size : integer;
increment_value_0 : integer;
increment_value_1 : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
increment_value : in STD_LOGIC;
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end counter_double_rst_nbits;
architecture Behavioral of counter_double_rst_nbits is
signal internal_value : UNSIGNED((size - 1) downto 0);
begin
process(clk, ce, rst)
begin
if(clk'event and clk = '1')then
if(rst = '1') then
internal_value <= unsigned(rst_value);
elsif(ce = '1') then
if(increment_value = '1') then
internal_value <= internal_value + to_unsigned(increment_value_1, internal_value'Length);
else
internal_value <= internal_value + to_unsigned(increment_value_0, internal_value'Length);
end if;
else
null;
end if;
end if;
end process;
q <= std_logic_vector(internal_value);
end Behavioral; | bsd-2-clause | 1be7e6e9b6214c6cea6636dc3750a0f9 | 0.630594 | 3.411215 | false | false | false | false |
Xero-Hige/LuGus-VHDL | TPS-2016/tps-Lucho/TP1-Contador/anod_enabler_decoder/anod_enabler_decoder_tb.vhd | 1 | 813 | library ieee;
use ieee.std_logic_1164.all;
entity anod_enabler_decoder_tb is
end;
architecture anod_enabler_decoder_tb_func of anod_enabler_decoder_tb is
signal data_in: std_logic_vector(1 downto 0) := (others => '0');
signal data_out: std_logic_vector(3 downto 0) := (others => '0');
component anod_enabler_decoder is
port(
binary_in: in std_logic_vector(1 downto 0); --"2 bit vector to switch between the 4 possible anod values"
code_out: out std_logic_vector(3 downto 0) --4 bit output to switch between anod
);
end component;
begin
data_in(0) <= not(data_in(0)) after 20 ns;
data_in(1) <= not(data_in(1)) after 40 ns;
anodEnablerMap: anod_enabler_decoder
port map(
binary_in => data_in,
code_out => data_out
);
end architecture;
| gpl-3.0 | 872437f18fa8c37cc61d0b0381bc7003 | 0.653137 | 3.056391 | false | false | false | false |
pwuertz/digitizer2fw | sim/ft2232fifo_tb.vhd | 1 | 5,528 | -------------------------------------------------------------------------------
-- FT2232H Sync FIFO Interface test bench
--
-- Author: Peter Würtz, TU Kaiserslautern (2016)
-- Distributed under the terms of the GNU General Public License Version 3.
-- The full license is in the file COPYING.txt, distributed with this software.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use std.textio.all;
entity ft2232fifo_tb is
end ft2232fifo_tb;
architecture ft2232fifo_tb_arch of ft2232fifo_tb is
component ft2232fifo
port (
-- ftdi interface
usb_clk: in std_logic;
usb_oe_n: out std_logic;
usb_rd_n: out std_logic;
usb_wr_n: out std_logic;
usb_rxf_n: in std_logic;
usb_txe_n: in std_logic;
usb_d: inout std_logic_vector(7 downto 0);
-- application/fifo interface
rst: in std_logic;
fifo_in_wr_en: out std_logic;
fifo_in_full: in std_logic;
fifo_in_data: out std_logic_vector(7 downto 0);
fifo_out_rd_en: out std_logic;
fifo_out_empty: in std_logic;
fifo_out_data: in std_logic_vector(7 downto 0)
);
end component;
signal usb_clk: std_logic := '0';
signal usb_oe_n: std_logic;
signal usb_rd_n: std_logic;
signal usb_wr_n: std_logic;
signal usb_rxf_n: std_logic := '1';
signal usb_txe_n: std_logic := '1';
signal usb_d: std_logic_vector(7 downto 0) := (others => '0');
signal usb_d_out: std_logic_vector(7 downto 0) := (others => '0');
signal rst: std_logic := '0';
signal fifo_in_wr_en: std_logic;
signal fifo_in_full: std_logic := '1';
signal fifo_in_data: std_logic_vector(7 downto 0);
signal fifo_out_rd_en: std_logic;
signal fifo_out_empty: std_logic := '1';
signal fifo_out_data: std_logic_vector(7 downto 0) := (others => '0');
constant clk_period : time := 16 ns;
begin
ft2232fifo_inst: ft2232fifo
port map (
-- ftdi interface
usb_clk => usb_clk,
usb_oe_n => usb_oe_n,
usb_rd_n => usb_rd_n,
usb_wr_n => usb_wr_n,
usb_rxf_n => usb_rxf_n,
usb_txe_n => usb_txe_n,
usb_d => usb_d,
-- application/fifo interface
rst => rst,
fifo_in_wr_en => fifo_in_wr_en,
fifo_in_full => fifo_in_full,
fifo_in_data => fifo_in_data,
fifo_out_rd_en => fifo_out_rd_en,
fifo_out_empty => fifo_out_empty,
fifo_out_data => fifo_out_data
);
clk_process: process
begin
usb_clk <= '0';
wait for clk_period/2;
usb_clk <= '1';
wait for clk_period/2;
end process;
process(usb_oe_n, usb_d_out, usb_rxf_n)
begin
usb_d <= (others => 'Z');
if (usb_oe_n = '0') then
if (usb_rxf_n = '1') then
usb_d <= (others => 'X');
else
usb_d <= usb_d_out;
end if;
end if;
end process;
data_from_usb: process(usb_clk)
begin
if rising_edge(usb_clk) then
if (usb_rd_n = '0') and (usb_rxf_n = '0') then
usb_d_out <= std_logic_vector(unsigned(usb_d_out) + 1);
end if;
end if;
end process;
data_received: process(usb_clk)
variable data_expected: integer := 0;
variable data_received: integer;
begin
if rising_edge(usb_clk) then
if (fifo_in_wr_en = '1') and (fifo_in_full = '0') then
data_received := to_integer(unsigned(fifo_in_data));
report "RX: " & integer'image(data_received);
assert (data_received = data_expected) report "recieved bad data" severity failure;
data_expected := data_expected + 1;
end if;
end if;
end process;
data_from_fifo: process(usb_clk)
begin
if rising_edge(usb_clk) then
if (fifo_out_rd_en = '1') and (fifo_out_empty = '0') then
fifo_out_data <= std_logic_vector(unsigned(fifo_out_data) + 1);
end if;
end if;
end process;
data_transmitted: process(usb_clk)
variable data_expected: integer := 0;
variable data_transmitted: integer;
begin
if rising_edge(usb_clk) then
if (usb_wr_n = '0') and (usb_txe_n = '0') then
data_transmitted := to_integer(unsigned(usb_d));
report "TX: " & integer'image(data_transmitted);
assert (data_transmitted = data_expected) report "transmitted bad data" severity failure;
data_expected := data_expected + 1;
end if;
end if;
end process;
stimulus: process
constant usb_txe_n_pattern: std_logic_vector := "111100000011111111110000000000000000000000";
constant usb_rxf_n_pattern: std_logic_vector := "111111111111111111111110000000000000001111";
constant fifo_in_full_pattern: std_logic_vector := "000000000000000000000000000000000000000000";
constant fifo_out_empty_pattern: std_logic_vector := "000000000000000000000000000111000000000000";
begin
usb_txe_n <= usb_txe_n_pattern(0);
usb_rxf_n <= usb_rxf_n_pattern(0);
fifo_in_full <= fifo_in_full_pattern(0);
fifo_out_empty <= fifo_out_empty_pattern(0);
for i in usb_txe_n_pattern'range loop
wait for clk_period;
usb_txe_n <= usb_txe_n_pattern(i);
usb_rxf_n <= usb_rxf_n_pattern(i);
fifo_in_full <= fifo_in_full_pattern(i);
fifo_out_empty <= fifo_out_empty_pattern(i);
end loop;
assert false report "Stimulus finished" severity note;
wait;
end process;
end ft2232fifo_tb_arch;
| gpl-3.0 | 1f408e165d2586f105fc275788908ad3 | 0.588927 | 3.282067 | false | false | false | false |
Xero-Hige/LuGus-VHDL | TPS-2016/tps-Lucho/TP1-Contador/4_port_multiplexer/4_port_multiplexer_tb.vhd | 1 | 1,399 | library ieee;
use ieee.std_logic_1164.all;
entity four_port_multiplexer_tb is
end;
architecture four_port_multiplexer_tb_func of four_port_multiplexer_tb is
signal data_in_a: std_logic_vector(3 downto 0) := (others => '0');
signal data_in_b: std_logic_vector(3 downto 0) := (others => '1');
signal data_in_c: std_logic_vector(3 downto 0) := "0101";
signal data_in_d: std_logic_vector(3 downto 0) := "1010";
signal data_out: std_logic_vector(3 downto 0) := (others => '0');
signal select_in: std_logic_vector(1 downto 0) := (others => '0');
component four_port_multiplexer is
generic(
BITS:natural := 1);
port (
data_in_a: in std_logic_vector(BITS-1 downto 0);
data_in_b: in std_logic_vector(BITS-1 downto 0);
data_in_c: in std_logic_vector(BITS-1 downto 0);
data_in_d: in std_logic_vector(BITS-1 downto 0);
select_in: in std_logic_vector(1 downto 0); --2 bits, 4 opciones
data_out: out std_logic_vector(BITS-1 downto 0)
);
end component;
begin
select_in(0) <= not(select_in(0)) after 20 ns;
select_in(1) <= not(select_in(1)) after 40 ns;
four_port_multiplexerMap: four_port_multiplexer generic map (4)
port map(
data_in_a => data_in_a,
data_in_b => data_in_b,
data_in_c => data_in_c,
data_in_d => data_in_d,
data_out => data_out,
select_in => select_in
);
end architecture;
| gpl-3.0 | a820f0d67902d052ffed10106b2b4bfd | 0.63331 | 2.727096 | false | false | false | false |
Xero-Hige/LuGus-VHDL | TPS-2016/tps-LuGus/TP2-Voltimetro/bcd_1_counter.vhd | 1 | 1,938 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.utility.all;
entity bcd_1_counter is
generic (
COUNTERS:natural := 5;
OUTPUT:natural := 3
);
port (
clk_in: in std_logic;
rst_in: in std_logic;
ena_in: in std_logic;
counter_out: out bcd_vector (OUTPUT-1 downto 0)
);
end;
architecture bcd_1_counter_arq of bcd_1_counter is
component generic_counter is
generic (
BITS:natural := 4;
MAX_COUNT:natural := 15
);
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
counter_out: out std_logic_vector(BITS-1 downto 0);
carry_out: out std_logic
);
end component;
signal bcd_ena_input : signal_vector(0 to COUNTERS) := (others => '1'); --Un valor mas que la cantidad de contadores
signal bcd_cout : signal_vector(COUNTERS downto 0) := (others => '1'); --Un valor mas que la cantidad de contadores
begin
bcd_ena_input(0) <= ena_in;
bcd_counters : for i in 1 to COUNTERS generate
bcd_ena_input(i) <= bcd_ena_input(i-1) AND bcd_cout(i-1);
counter_outs_valid: if i>COUNTERS-OUTPUT generate
counter_out_valid: generic_counter
generic map(4,9)
port map(
clk => clk_in,
rst => rst_in,
ena => bcd_ena_input(i),
counter_out => counter_out(i-1 - COUNTERS + OUTPUT), --Para darlos vuelta y tomar solo los mas significativos
carry_out => bcd_cout(i)
);
end generate counter_outs_valid;
counter_outs_not_valid : if i < COUNTERS-OUTPUT+1 generate
counter_out_not_valid: generic_counter
generic map(4,9)
port map(
clk => clk_in,
rst => rst_in,
ena => bcd_ena_input(i),
--counter_out => counter_out(-i + COUNTERS),
carry_out => bcd_cout(i)
);
end generate counter_outs_not_valid;
end generate bcd_counters;
end; | gpl-3.0 | 981923d8ab64bae1b35018e2e9bbb87d | 0.598555 | 3.156352 | false | false | false | false |
pmassolino/hw-goppa-mceliece | mceliece/util/register_rst_nbits.vhd | 1 | 1,471 | ----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Register_rst_n_bits
-- Module Name: Register_rst_n_bits
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Register of size bits with reset signal, that only registers when ce equals to 1.
-- The reset is synchronous and the value loaded during reset is defined by reset_value.
--
-- The circuits parameters
--
-- size :
--
-- The size of the register in bits.
--
-- Dependencies:
-- VHDL-93
--
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity register_rst_nbits is
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end register_rst_nbits;
architecture Behavioral of register_rst_nbits is
begin
process(clk, ce, rst)
begin
if(clk'event and clk = '1')then
if(rst = '1') then
q <= rst_value;
elsif(ce = '1') then
q <= d;
else
null;
end if;
end if;
end process;
end Behavioral;
| bsd-2-clause | 80dea21624ebea1fa66dc79c06cce404 | 0.582597 | 3.389401 | false | false | false | false |
hitomi2500/wasca | fpga_firmware/abus_avalon_sdram_bridge_tb.vhd | 1 | 20,393 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity abus_avalon_sdram_bridge_tb is
end abus_avalon_sdram_bridge_tb;
architecture Behavioral of abus_avalon_sdram_bridge_tb is
component abus_avalon_sdram_bridge is
port (
clock : in std_logic := '0'; -- clock.clk
abus_address : in std_logic_vector(24 downto 0) := (others => '0'); -- abus.address
abus_data : inout std_logic_vector(15 downto 0) := (others => '0'); -- abus.data
abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
abus_read : in std_logic := '0'; -- .read
abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
abus_interrupt : out std_logic := '0'; -- .interrupt
abus_direction : out std_logic := '0'; -- .direction
abus_interrupt_disable_out : out std_logic := '0'; -- .disableout
sdram_addr : out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr
sdram_ba : out std_logic_vector(1 downto 0); -- .ba
sdram_cas_n : out std_logic; -- .cas_n
sdram_cke : out std_logic; -- .cke
sdram_cs_n : out std_logic; -- .cs_n
sdram_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq
sdram_dqm : out std_logic_vector(1 downto 0); -- .dqm
sdram_ras_n : out std_logic; -- .ras_n
sdram_we_n : out std_logic; -- .we_n
sdram_clk : out std_logic;
avalon_sdram_read : in std_logic := '0'; -- avalon_master.read
avalon_sdram_write : in std_logic := '0'; -- .write
avalon_sdram_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_sdram_address : in std_logic_vector(25 downto 0) := (others => '0'); -- .address
avalon_sdram_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_sdram_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_sdram_readdatavalid : out std_logic := '0'; -- .readdatavalid
avalon_regs_read : in std_logic := '0'; -- avalon_master.read
avalon_regs_write : in std_logic := '0'; -- .write
avalon_regs_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_regs_address : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
avalon_regs_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_regs_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_regs_readdatavalid : out std_logic := '0'; -- .readdatavalid
saturn_reset : in std_logic := '0'; -- .saturn_reset
reset : in std_logic := '0' -- reset.reset
);
end component;
component sdram_controller is
port(
-- HOST INTERFACE
wr_addr: in std_logic_vector(23 downto 0);
wr_data: in std_logic_vector(15 downto 0);
wr_enable: in std_logic;
rd_addr: in std_logic_vector(23 downto 0);
rd_data: out std_logic_vector(15 downto 0);
rd_ready: out std_logic;
rd_enable: in std_logic;
busy: out std_logic;
rst_n: in std_logic;
clk: in std_logic;
-- SDRAM SIDE
addr : out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr
bank_addr : out std_logic_vector(1 downto 0); -- .ba
cas_n : out std_logic; -- .cas_n
clock_enable : out std_logic; -- .cke
cs_n : out std_logic; -- .cs_n
data : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq
data_mask_low: out std_logic;
data_mask_high: out std_logic;
ras_n : out std_logic; -- .ras_n
we_n : out std_logic
);
end component;
----------------------ins
signal clock : std_logic := '0'; -- clock.clk
signal abus_address : std_logic_vector(24 downto 0) := (others => '0'); -- abus.address
signal abus_chipselect : std_logic_vector(2 downto 0) := (others => '1'); -- .chipselect
signal abus_read : std_logic := '1'; -- .read
signal abus_write : std_logic_vector(1 downto 0) := (others => '1'); -- .write
signal avalon_sdram_read : std_logic := '0'; -- avalon_master.read
signal avalon_sdram_write : std_logic := '0'; -- .write
signal avalon_sdram_address : std_logic_vector(25 downto 0) := (others => '0'); -- .address
signal avalon_sdram_writedata : std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
signal avalon_regs_read : std_logic := '0'; -- avalon_master.read
signal avalon_regs_write : std_logic := '0'; -- .write
signal avalon_regs_address : std_logic_vector(7 downto 0) := (others => '0'); -- .address
signal avalon_regs_writedata : std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
signal saturn_reset : std_logic := '0'; -- .saturn_reset
signal reset : std_logic := '0'; -- reset.reset
----------------------outs
signal abus_waitrequest : std_logic := '1'; -- .waitrequest
signal abus_interrupt : std_logic := '0'; -- .interrupt
signal abus_direction : std_logic := '0'; -- .direction
signal abus_interrupt_disable_out : std_logic := '0'; -- .disableout
signal sdram_addr : std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr
signal sdram_ba : std_logic_vector(1 downto 0); -- .ba
signal sdram_cas_n : std_logic; -- .cas_n
signal sdram_cke : std_logic; -- .cke
signal sdram_cs_n : std_logic;
signal sdram_dqm : std_logic_vector(1 downto 0); -- .dqm
signal sdram_ras_n : std_logic; -- .ras_n
signal sdram_we_n : std_logic; -- .we_n
signal sdram_clk : std_logic;
signal avalon_sdram_waitrequest : std_logic := '0'; -- .waitrequest
signal avalon_sdram_readdata : std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
signal avalon_sdram_readdatavalid : std_logic := '0'; -- .readdatavalid
signal avalon_regs_waitrequest : std_logic := '0'; -- .waitrequest
signal avalon_regs_readdata : std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
signal avalon_regs_readdatavalid : std_logic := '0'; -- .readdatavalid
----------------------inouts
signal abus_data : std_logic_vector(15 downto 0) := (others => '0'); -- abus.data
signal sdram_dq : std_logic_vector(15 downto 0) := (others => '0'); -- .dq
signal abus_full_address : std_logic_vector(25 downto 0) := (others => '0');
signal abus_data_in : std_logic_vector(15 downto 0) := (others => '0');
------------- reference controller
signal refer_wr_addr: std_logic_vector(23 downto 0) := (others => '0');
signal refer_wr_data: std_logic_vector(15 downto 0) := (others => '0');
signal refer_wr_enable: std_logic;
signal refer_rd_addr: std_logic_vector(23 downto 0) := (others => '0');
signal refer_rd_data: std_logic_vector(15 downto 0) := (others => '0');
signal refer_rd_ready: std_logic;
signal refer_rd_enable: std_logic := '0';
signal refer_busy: std_logic;
signal refer_rst_n: std_logic := '1';
procedure write_abus_16 (addry : in std_logic_vector(25 downto 0);
datty : in std_logic_vector(15 downto 0);
csy : in std_logic_vector(2 downto 0);
wry : in std_logic_vector(1 downto 0);
signal Abus_Ad : out std_logic_vector(25 downto 0);
signal Abus_Da : out std_logic_vector(15 downto 0);
signal Abus_CS : out std_logic_vector(2 downto 0);
signal Abus_Wri : out std_logic_vector(1 downto 0);
signal Ref_Ad : out std_logic_vector(23 downto 0);
signal Ref_Da : out std_logic_vector(15 downto 0);
signal Ref_Wri : out std_logic
) is
begin
Abus_Ad <= addry;
Ref_Ad <= addry(24 downto 1);
Ref_Da <= datty;
wait for 8620 ps;
Abus_Da <= datty;
wait for 8620 ps;
Abus_CS <= csy;
wait for 8620 ps;
Abus_Wri <= wry;
wait for 4310 ps;
Ref_Wri <= '1';
wait for 8620 ps;
Ref_Wri <= '0';
wait for 159470 ps;
Abus_CS <= "111";
wait for 8620 ps;
Abus_Wri <= "11";
wait for 8620 ps;
end write_abus_16;
procedure read_abus_16 (addry : in std_logic_vector(25 downto 0);
csy : in std_logic_vector(2 downto 0);
signal Abus_Ad : out std_logic_vector(25 downto 0);
signal Abus_CS : out std_logic_vector(2 downto 0);
signal Abus_Re : out std_logic;
signal Ref_Ad : out std_logic_vector(23 downto 0);
signal Ref_Re : out std_logic
) is
begin
Abus_Ad <= addry;
Ref_Ad <= addry(24 downto 1);
wait for 8620 ps;
Abus_CS <= csy;
wait for 8620 ps;
Abus_Re <= '0';
wait for 8620 ps;
Ref_Re <= '1';
wait for 8620 ps;
Ref_Re <= '0';
wait for 172400 ps;
Abus_CS <= "111";
wait for 8620 ps;
Abus_Re <= '1';
wait for 8620 ps;
end read_abus_16;
procedure write_avalon_16 (addry : in std_logic_vector(25 downto 0);
datty : in std_logic_vector(15 downto 0);
signal Ava_Ad : out std_logic_vector(24 downto 0);
signal Ava_Da : out std_logic_vector(15 downto 0);
signal Ava_Wri : out std_logic;
signal Ref_Ad : out std_logic_vector(23 downto 0);
signal Ref_Da : out std_logic_vector(15 downto 0);
signal Ref_Wri : out std_logic
) is
begin
Ava_Ad <= addry(24 downto 0);
Ref_Ad <= addry(24 downto 1);
Ref_Da <= datty;
Ava_Da <= datty;
wait for 8620 ps;
Ava_Wri <= '1';
wait for 8620 ps;
Ref_Wri <= '1';
Ava_Wri <= '0';
wait for 8620 ps;
Ref_Wri <= '0';
end write_avalon_16;
procedure write_avalon_16_regs (addry : in std_logic_vector(7 downto 0);
datty : in std_logic_vector(15 downto 0);
signal Ava_Ad : out std_logic_vector(7 downto 0);
signal Ava_Da : out std_logic_vector(15 downto 0);
signal Ava_Wri : out std_logic
) is
begin
Ava_Ad <= addry;
Ava_Da <= datty;
wait for 8620 ps;
Ava_Wri <= '1';
wait for 8620 ps;
Ava_Wri <= '0';
wait for 8620 ps;
end write_avalon_16_regs;
procedure read_avalon_16 (addry : in std_logic_vector(25 downto 0);
signal Ava_Ad : out std_logic_vector(24 downto 0);
signal Ava_Re : out std_logic;
signal Ref_Ad : out std_logic_vector(23 downto 0);
signal Ref_Re : out std_logic
) is
begin
Ava_Ad <= addry(24 downto 0);
Ref_Ad <= addry(24 downto 1);
wait for 8620 ps;
Ava_Re <= '1';
wait for 8620 ps;
Ref_Re <= '1';
Ava_Re <= '0';
wait for 8620 ps;
Ref_Re <= '0';
end read_avalon_16;
procedure read_avalon_16_regs (addry : in std_logic_vector(7 downto 0);
signal Ava_Ad : out std_logic_vector(7 downto 0);
signal Ava_Re : out std_logic
) is
begin
Ava_Ad <= addry;
wait for 8620 ps;
Ava_Re <= '1';
wait for 8620 ps;
Ava_Re <= '0';
wait for 8620 ps;
end read_avalon_16_regs;
begin
clock <= not clock after 4310 ps; --116 MHz clock
--address/data mux
abus_data <= abus_data_in when abus_direction = '0' else
(others => 'Z');
abus_address <= abus_full_address(24 downto 0);
UUT: abus_avalon_sdram_bridge
port map(
clock => clock,
abus_address => abus_address,
abus_data => abus_data,
abus_chipselect => abus_chipselect,
abus_read => abus_read,
abus_write => abus_write,
abus_interrupt => abus_interrupt,
abus_direction => abus_direction,
abus_interrupt_disable_out => abus_interrupt_disable_out,
sdram_addr => sdram_addr,
sdram_ba => sdram_ba,
sdram_cas_n => sdram_cas_n,
sdram_cke => sdram_cke,
sdram_cs_n => sdram_cs_n,
sdram_dq => sdram_dq,
sdram_dqm => sdram_dqm,
sdram_ras_n => sdram_ras_n,
sdram_we_n => sdram_we_n,
sdram_clk => sdram_clk,
avalon_sdram_read => avalon_sdram_read,
avalon_sdram_write => avalon_sdram_write,
avalon_sdram_waitrequest => avalon_sdram_waitrequest,
avalon_sdram_address => avalon_sdram_address,
avalon_sdram_writedata => avalon_sdram_writedata,
avalon_sdram_readdata => avalon_sdram_readdata,
avalon_sdram_readdatavalid => avalon_sdram_readdatavalid,
avalon_regs_read => avalon_regs_read,
avalon_regs_write => avalon_regs_write,
avalon_regs_waitrequest => avalon_regs_waitrequest,
avalon_regs_address => avalon_regs_address,
avalon_regs_writedata => avalon_regs_writedata,
avalon_regs_readdata => avalon_regs_readdata,
avalon_regs_readdatavalid => avalon_regs_readdatavalid,
saturn_reset => saturn_reset,
reset => reset
);
--REFER: sdram_controller
-- port map(
-- clk => clock,
-- rst_n => refer_rst_n,
-- busy => open,
-- wr_addr => refer_wr_addr,
-- wr_data => refer_wr_data,
-- wr_enable => refer_wr_enable,
-- rd_addr => refer_rd_addr,
-- rd_data => refer_rd_data,
-- rd_ready => refer_rd_ready,
-- rd_enable => refer_rd_enable,
-- addr => open,
-- bank_addr => open,
-- cas_n => open,
-- clock_enable => open,
-- cs_n => open,
-- data => open,
-- data_mask_low => open,
-- data_mask_high => open,
-- ras_n => open,
-- we_n => open
-- );
process
begin
refer_rst_n <= '1';
wait for 100ns;
refer_rst_n <= '0';
wait for 100ns;
refer_rst_n <= '1';
wait for 800ns;
wait for 300us; --sdram init time
--setup sniff fifo - only writes on cs1
write_avalon_16_regs(X"E8",X"000A",avalon_regs_address,avalon_regs_writedata,avalon_regs_write); --filter - only write on cs1
--abus normal read
read_abus_16("00"&X"EFAFAE","101",abus_full_address,abus_chipselect,abus_read,refer_rd_addr,refer_rd_enable);
--abus read while autorefresh
wait for 3150ns;
read_abus_16("00"&X"EFAFAE","101",abus_full_address,abus_chipselect,abus_read,refer_rd_addr,refer_rd_enable);
--abus pack write
for w in 0 to 10 loop
wait for 10 us;
write_abus_16(std_logic_vector(to_unsigned(w*512,26)),X"DADA","101","00",abus_full_address,abus_data_in,abus_chipselect,abus_write,refer_wr_addr,refer_wr_data,refer_wr_enable);
end loop;
wait for 100 us;
wait for 11 ms;
--avalon normal read
for w in 0 to 20 loop
wait for 500 ns;
read_avalon_16_regs(X"E0",avalon_regs_address,avalon_regs_read);
wait for 500 ns;
read_avalon_16_regs(X"EA",avalon_regs_address,avalon_regs_read);
end loop;
wait;
--pack read fifo
for w in 0 to 1025 loop
wait for 1 us;
read_avalon_16_regs(X"E0",avalon_regs_address,avalon_regs_read);
--write_avalon_16_regs(X"E6",X"0000",avalon_regs_address,avalon_regs_writedata,avalon_regs_write); --filter - only write on cs1
end loop;
wait for 10ms;
--abus pack write
for w in 0 to 1025 loop
wait for 10 us;
write_abus_16(std_logic_vector(to_unsigned(w*512,26)),X"DADA","101","00",abus_full_address,abus_data_in,abus_chipselect,abus_write,refer_wr_addr,refer_wr_data,refer_wr_enable);
end loop;
wait for 100 us;
--pack read fifo
for w in 0 to 1025 loop
wait for 1 us;
read_avalon_16_regs(X"E0",avalon_regs_address,avalon_regs_read);
--write_avalon_16_regs(X"E6",X"0000",avalon_regs_address,avalon_regs_writedata,avalon_regs_write); --filter - only write on cs1
end loop;
-- --avalon normal write
-- wait for 500ns;
-- write_avalon_16("00"&X"EEE312",X"DADA",avalon_sdram_address,avalon_sdram_writedata,avalon_sdram_write,refer_wr_addr,refer_wr_data,refer_wr_enable);
-- wait for 500ns;
-- --avalon normal read
-- wait for 500ns;
-- read_avalon_16("00"&X"EEE312",avalon_sdram_address,avalon_sdram_read,refer_rd_addr,refer_rd_enable);
-- wait for 500ns;
wait;
end process;
end Behavioral;
| gpl-2.0 | 0e8ad630069e528d358dba261d13bfa2 | 0.477125 | 3.779281 | false | false | false | false |
achan1989/In64 | FPGA/SD_card_test.srcs/sources_1/imports/picoblaze_Release6_29March13/kcpsm6.vhd | 1 | 108,433 | --
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2012, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
-- KCPSM6 - PicoBlaze for Spartan-6 and Virtex-6 devices.
--
-- Start of design entry - 14th May 2010.
-- Alpha Version - 20th July 2010.
-- Version 1.0 - 30th September 2010.
-- Version 1.1 - 9th February 2011.
-- Correction to parity computation logic.
-- Version 1.2 - 4th October 2012.
-- Addition of WebTalk information.
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- [email protected]
--
-------------------------------------------------------------------------------------------
--
-- Format of this file.
--
-- The module defines the implementation of the logic using Xilinx primitives.
-- These ensure predictable synthesis results and maximise the density of the implementation.
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
-------------------------------------------------------------------------------------------
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
-------------------------------------------------------------------------------------------
--
-- Main Entity for kcpsm6
--
entity kcpsm6 is
generic( hwbuild : std_logic_vector(7 downto 0) := X"00";
interrupt_vector : std_logic_vector(11 downto 0) := X"3FF";
scratch_pad_memory_size : integer := 64);
port ( address : out std_logic_vector(11 downto 0);
instruction : in std_logic_vector(17 downto 0);
bram_enable : out std_logic;
in_port : in std_logic_vector(7 downto 0);
out_port : out std_logic_vector(7 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
k_write_strobe : out std_logic;
read_strobe : out std_logic;
interrupt : in std_logic;
interrupt_ack : out std_logic;
sleep : in std_logic;
reset : in std_logic;
clk : in std_logic);
end kcpsm6;
--
-------------------------------------------------------------------------------------------
--
-- Start of Main Architecture for kcpsm6
--
architecture low_level_definition of kcpsm6 is
--
-------------------------------------------------------------------------------------------
--
-- Signals used in kcpsm6
--
-------------------------------------------------------------------------------------------
--
-- State Machine and Interrupt
--
signal t_state_value : std_logic_vector(2 downto 1);
signal t_state : std_logic_vector(2 downto 1);
signal run_value : std_logic;
signal run : std_logic;
signal internal_reset_value : std_logic;
signal internal_reset : std_logic;
signal sync_sleep : std_logic;
signal int_enable_type : std_logic;
signal interrupt_enable_value : std_logic;
signal interrupt_enable : std_logic;
signal sync_interrupt : std_logic;
signal active_interrupt_value : std_logic;
signal active_interrupt : std_logic;
--
-- Arithmetic and Logical Functions
--
signal arith_logical_sel : std_logic_vector(2 downto 0);
signal arith_carry_in : std_logic;
signal arith_carry_value : std_logic;
signal arith_carry : std_logic;
signal half_arith_logical : std_logic_vector(7 downto 0);
signal logical_carry_mask : std_logic_vector(7 downto 0);
signal carry_arith_logical : std_logic_vector(7 downto 0);
signal arith_logical_value : std_logic_vector(7 downto 0);
signal arith_logical_result : std_logic_vector(7 downto 0);
--
-- Shift and Rotate Functions
--
signal shift_rotate_value : std_logic_vector(7 downto 0);
signal shift_rotate_result : std_logic_vector(7 downto 0);
signal shift_in_bit : std_logic;
--
-- ALU structure
--
signal alu_result : std_logic_vector(7 downto 0);
signal alu_mux_sel_value : std_logic_vector(1 downto 0);
signal alu_mux_sel : std_logic_vector(1 downto 0);
--
-- Strobes
--
signal strobe_type : std_logic;
signal write_strobe_value : std_logic;
signal k_write_strobe_value : std_logic;
signal read_strobe_value : std_logic;
--
-- Flags
--
signal flag_enable_type : std_logic;
signal flag_enable_value : std_logic;
signal flag_enable : std_logic;
signal lower_parity : std_logic;
signal lower_parity_sel : std_logic;
signal carry_lower_parity : std_logic;
signal upper_parity : std_logic;
signal parity : std_logic;
signal shift_carry_value : std_logic;
signal shift_carry : std_logic;
signal carry_flag_value : std_logic;
signal carry_flag : std_logic;
signal use_zero_flag_value : std_logic;
signal use_zero_flag : std_logic;
signal drive_carry_in_zero : std_logic;
signal carry_in_zero : std_logic;
signal lower_zero : std_logic;
signal lower_zero_sel : std_logic;
signal carry_lower_zero : std_logic;
signal middle_zero : std_logic;
signal middle_zero_sel : std_logic;
signal carry_middle_zero : std_logic;
signal upper_zero_sel : std_logic;
signal zero_flag_value : std_logic;
signal zero_flag : std_logic;
--
-- Scratch Pad Memory
--
signal spm_enable_value : std_logic;
signal spm_enable : std_logic;
signal spm_ram_data : std_logic_vector(7 downto 0);
signal spm_data : std_logic_vector(7 downto 0);
--
-- Registers
--
signal regbank_type : std_logic;
signal bank_value : std_logic;
signal bank : std_logic;
signal loadstar_type : std_logic;
signal sx_addr4_value : std_logic;
signal register_enable_type : std_logic;
signal register_enable_value : std_logic;
signal register_enable : std_logic;
signal sx_addr : std_logic_vector(4 downto 0);
signal sy_addr : std_logic_vector(4 downto 0);
signal sx : std_logic_vector(7 downto 0);
signal sy : std_logic_vector(7 downto 0);
--
-- Second Operand
--
signal sy_or_kk : std_logic_vector(7 downto 0);
--
-- Program Counter
--
signal pc_move_is_valid : std_logic;
signal move_type : std_logic;
signal returni_type : std_logic;
signal pc_mode : std_logic_vector(2 downto 0);
signal register_vector : std_logic_vector(11 downto 0);
signal half_pc : std_logic_vector(11 downto 0);
signal carry_pc : std_logic_vector(10 downto 0);
signal pc_value : std_logic_vector(11 downto 0);
signal pc : std_logic_vector(11 downto 0);
signal pc_vector : std_logic_vector(11 downto 0);
--
-- Program Counter Stack
--
signal push_stack : std_logic;
signal pop_stack : std_logic;
signal stack_memory : std_logic_vector(11 downto 0);
signal return_vector : std_logic_vector(11 downto 0);
signal stack_carry_flag : std_logic;
signal shadow_carry_flag : std_logic;
signal stack_zero_flag : std_logic;
signal shadow_zero_value : std_logic;
signal shadow_zero_flag : std_logic;
signal stack_bank : std_logic;
signal shadow_bank : std_logic;
signal stack_bit : std_logic;
signal special_bit : std_logic;
signal half_pointer_value : std_logic_vector(4 downto 0);
signal feed_pointer_value : std_logic_vector(4 downto 0);
signal stack_pointer_carry : std_logic_vector(4 downto 0);
signal stack_pointer_value : std_logic_vector(4 downto 0);
signal stack_pointer : std_logic_vector(4 downto 0);
--
--
--
--**********************************************************************************
--
-- Signals between these *** lines are only made visible during simulation
--
--synthesis translate off
--
signal kcpsm6_opcode : string(1 to 19):= "LOAD s0, s0 ";
signal kcpsm6_status : string(1 to 16):= "A,NZ,NC,ID,Reset";
signal sim_s0 : std_logic_vector(7 downto 0);
signal sim_s1 : std_logic_vector(7 downto 0);
signal sim_s2 : std_logic_vector(7 downto 0);
signal sim_s3 : std_logic_vector(7 downto 0);
signal sim_s4 : std_logic_vector(7 downto 0);
signal sim_s5 : std_logic_vector(7 downto 0);
signal sim_s6 : std_logic_vector(7 downto 0);
signal sim_s7 : std_logic_vector(7 downto 0);
signal sim_s8 : std_logic_vector(7 downto 0);
signal sim_s9 : std_logic_vector(7 downto 0);
signal sim_sA : std_logic_vector(7 downto 0);
signal sim_sB : std_logic_vector(7 downto 0);
signal sim_sC : std_logic_vector(7 downto 0);
signal sim_sD : std_logic_vector(7 downto 0);
signal sim_sE : std_logic_vector(7 downto 0);
signal sim_sF : std_logic_vector(7 downto 0);
signal sim_spm00 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm01 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm02 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm03 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm04 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm05 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm06 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm07 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm08 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm09 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm10 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm11 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm12 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm13 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm14 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm15 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm16 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm17 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm18 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm19 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm20 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm21 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm22 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm23 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm24 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm25 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm26 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm27 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm28 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm29 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm30 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm31 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm32 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm33 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm34 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm35 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm36 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm37 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm38 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm39 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm40 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm41 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm42 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm43 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm44 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm45 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm46 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm47 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm48 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm49 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm50 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm51 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm52 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm53 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm54 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm55 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm56 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm57 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm58 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm59 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm60 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm61 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm62 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm63 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm64 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm65 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm66 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm67 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm68 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm69 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm70 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm71 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm72 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm73 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm74 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm75 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm76 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm77 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm78 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm79 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm80 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm81 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm82 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm83 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm84 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm85 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm86 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm87 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm88 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm89 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm90 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm91 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm92 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm93 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm94 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm95 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm96 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm97 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm98 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm99 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9F : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmED : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFF : std_logic_vector(7 downto 0) := X"00";
--
--synthesis translate on
--
--**********************************************************************************
--
--
-------------------------------------------------------------------------------------------
--
-- WebTalk Attributes
--
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of low_level_definition : ARCHITECTURE IS
"kcpsm6,kcpsm6_v1_2,{component_name=kcpsm6}";
--
-- Attributes to guide mapping of logic into Slices.
--
attribute hblknm : string;
attribute hblknm of reset_lut : label is "kcpsm6_control";
attribute hblknm of run_flop : label is "kcpsm6_control";
attribute hblknm of internal_reset_flop : label is "kcpsm6_control";
attribute hblknm of t_state_lut : label is "kcpsm6_control";
attribute hblknm of t_state1_flop : label is "kcpsm6_control";
attribute hblknm of t_state2_flop : label is "kcpsm6_control";
attribute hblknm of active_interrupt_lut : label is "kcpsm6_control";
attribute hblknm of active_interrupt_flop : label is "kcpsm6_control";
attribute hblknm of sx_addr4_flop : label is "kcpsm6_control";
attribute hblknm of arith_carry_xorcy : label is "kcpsm6_control";
attribute hblknm of arith_carry_flop : label is "kcpsm6_control";
attribute hblknm of zero_flag_flop : label is "kcpsm6_flags";
attribute hblknm of carry_flag_flop : label is "kcpsm6_flags";
attribute hblknm of carry_flag_lut : label is "kcpsm6_flags";
attribute hblknm of lower_zero_lut : label is "kcpsm6_flags";
attribute hblknm of middle_zero_lut : label is "kcpsm6_flags";
attribute hblknm of upper_zero_lut : label is "kcpsm6_flags";
attribute hblknm of init_zero_muxcy : label is "kcpsm6_flags";
attribute hblknm of lower_zero_muxcy : label is "kcpsm6_flags";
attribute hblknm of middle_zero_muxcy : label is "kcpsm6_flags";
attribute hblknm of upper_zero_muxcy : label is "kcpsm6_flags";
attribute hblknm of int_enable_type_lut : label is "kcpsm6_decode0";
attribute hblknm of move_type_lut : label is "kcpsm6_decode0";
attribute hblknm of pc_move_is_valid_lut : label is "kcpsm6_decode0";
attribute hblknm of interrupt_enable_lut : label is "kcpsm6_decode0";
attribute hblknm of interrupt_enable_flop : label is "kcpsm6_decode0";
attribute hblknm of alu_decode1_lut : label is "kcpsm6_decode1";
attribute hblknm of alu_mux_sel1_flop : label is "kcpsm6_decode1";
attribute hblknm of shift_carry_lut : label is "kcpsm6_decode1";
attribute hblknm of shift_carry_flop : label is "kcpsm6_decode1";
attribute hblknm of use_zero_flag_lut : label is "kcpsm6_decode1";
attribute hblknm of use_zero_flag_flop : label is "kcpsm6_decode1";
attribute hblknm of interrupt_ack_flop : label is "kcpsm6_decode1";
attribute hblknm of shadow_zero_flag_flop : label is "kcpsm6_decode1";
attribute hblknm of alu_decode0_lut : label is "kcpsm6_decode2";
attribute hblknm of alu_mux_sel0_flop : label is "kcpsm6_decode2";
attribute hblknm of alu_decode2_lut : label is "kcpsm6_decode2";
attribute hblknm of lower_parity_lut : label is "kcpsm6_decode2";
attribute hblknm of parity_muxcy : label is "kcpsm6_decode2";
attribute hblknm of upper_parity_lut : label is "kcpsm6_decode2";
attribute hblknm of parity_xorcy : label is "kcpsm6_decode2";
attribute hblknm of sync_sleep_flop : label is "kcpsm6_decode2";
attribute hblknm of sync_interrupt_flop : label is "kcpsm6_decode2";
attribute hblknm of push_pop_lut : label is "kcpsm6_stack1";
attribute hblknm of regbank_type_lut : label is "kcpsm6_stack1";
attribute hblknm of bank_lut : label is "kcpsm6_stack1";
attribute hblknm of bank_flop : label is "kcpsm6_stack1";
attribute hblknm of register_enable_type_lut : label is "kcpsm6_strobes";
attribute hblknm of register_enable_lut : label is "kcpsm6_strobes";
attribute hblknm of flag_enable_flop : label is "kcpsm6_strobes";
attribute hblknm of register_enable_flop : label is "kcpsm6_strobes";
attribute hblknm of spm_enable_lut : label is "kcpsm6_strobes";
attribute hblknm of k_write_strobe_flop : label is "kcpsm6_strobes";
attribute hblknm of spm_enable_flop : label is "kcpsm6_strobes";
attribute hblknm of read_strobe_lut : label is "kcpsm6_strobes";
attribute hblknm of write_strobe_flop : label is "kcpsm6_strobes";
attribute hblknm of read_strobe_flop : label is "kcpsm6_strobes";
attribute hblknm of stack_ram_low : label is "kcpsm6_stack_ram0";
attribute hblknm of shadow_carry_flag_flop : label is "kcpsm6_stack_ram0";
attribute hblknm of stack_zero_flop : label is "kcpsm6_stack_ram0";
attribute hblknm of shadow_bank_flop : label is "kcpsm6_stack_ram0";
attribute hblknm of stack_bit_flop : label is "kcpsm6_stack_ram0";
attribute hblknm of stack_ram_high : label is "kcpsm6_stack_ram1";
attribute hblknm of lower_reg_banks : label is "kcpsm6_reg0";
attribute hblknm of upper_reg_banks : label is "kcpsm6_reg1";
attribute hblknm of pc_mode1_lut : label is "kcpsm6_vector1";
attribute hblknm of pc_mode2_lut : label is "kcpsm6_vector1";
--
-------------------------------------------------------------------------------------------
--
-- Start of kcpsm6 circuit description
--
-- Summary of all primitives defined.
--
-- 29 x LUT6 79 LUTs (plus 1 LUT will be required to form a GND signal)
-- 50 x LUT6_2
-- 48 x FD 82 flip-flops
-- 20 x FDR (Depending on the value of 'hwbuild' up)
-- 0 x FDS (to eight FDR will be replaced by FDS )
-- 14 x FDRE
-- 29 x MUXCY
-- 27 x XORCY
-- 4 x RAM32M (16 LUTs)
--
-- 2 x RAM64M or 8 x RAM128X1S or 8 x RAM256X1S
-- (8 LUTs) (16 LUTs) (32 LUTs)
--
-------------------------------------------------------------------------------------------
--
begin
--
-------------------------------------------------------------------------------------------
--
-- Perform check of generic to report error as soon as possible.
--
-------------------------------------------------------------------------------------------
--
assert ((scratch_pad_memory_size = 64)
or (scratch_pad_memory_size = 128)
or (scratch_pad_memory_size = 256))
report "Invalid 'scratch_pad_memory_size'. Please set to 64, 128 or 256."
severity FAILURE;
--
-------------------------------------------------------------------------------------------
--
-- State Machine and Control
--
--
-- 1 x LUT6
-- 4 x LUT6_2
-- 9 x FD
--
-------------------------------------------------------------------------------------------
--
reset_lut: LUT6_2
generic map (INIT => X"FFFFF55500000EEE")
port map( I0 => run,
I1 => internal_reset,
I2 => stack_pointer_carry(4),
I3 => t_state(2),
I4 => reset,
I5 => '1',
O5 => run_value,
O6 => internal_reset_value);
run_flop: FD
port map ( D => run_value,
Q => run,
C => clk);
internal_reset_flop: FD
port map ( D => internal_reset_value,
Q => internal_reset,
C => clk);
sync_sleep_flop: FD
port map ( D => sleep,
Q => sync_sleep,
C => clk);
t_state_lut: LUT6_2
generic map (INIT => X"0083000B00C4004C")
port map( I0 => t_state(1),
I1 => t_state(2),
I2 => sync_sleep,
I3 => internal_reset,
I4 => special_bit,
I5 => '1',
O5 => t_state_value(1),
O6 => t_state_value(2));
t_state1_flop: FD
port map ( D => t_state_value(1),
Q => t_state(1),
C => clk);
t_state2_flop: FD
port map ( D => t_state_value(2),
Q => t_state(2),
C => clk);
int_enable_type_lut: LUT6_2
generic map (INIT => X"0010000000000800")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => instruction(17),
I5 => '1',
O5 => loadstar_type,
O6 => int_enable_type);
interrupt_enable_lut: LUT6
generic map (INIT => X"000000000000CAAA")
port map( I0 => interrupt_enable,
I1 => instruction(0),
I2 => int_enable_type,
I3 => t_state(1),
I4 => active_interrupt,
I5 => internal_reset,
O => interrupt_enable_value);
interrupt_enable_flop: FD
port map ( D => interrupt_enable_value,
Q => interrupt_enable,
C => clk);
sync_interrupt_flop: FD
port map ( D => interrupt,
Q => sync_interrupt,
C => clk);
active_interrupt_lut: LUT6_2
generic map (INIT => X"CC33FF0080808080")
port map( I0 => interrupt_enable,
I1 => t_state(2),
I2 => sync_interrupt,
I3 => bank,
I4 => loadstar_type,
I5 => '1',
O5 => active_interrupt_value,
O6 => sx_addr4_value);
active_interrupt_flop: FD
port map ( D => active_interrupt_value,
Q => active_interrupt,
C => clk);
interrupt_ack_flop: FD
port map ( D => active_interrupt,
Q => interrupt_ack,
C => clk);
--
-------------------------------------------------------------------------------------------
--
-- Decoders
--
--
-- 2 x LUT6
-- 10 x LUT6_2
-- 2 x FD
-- 6 x FDR
--
-------------------------------------------------------------------------------------------
--
--
-- Decoding for Program Counter and Stack
--
pc_move_is_valid_lut: LUT6
generic map (INIT => X"5A3CFFFF00000000")
port map( I0 => carry_flag,
I1 => zero_flag,
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => instruction(17),
O => pc_move_is_valid);
move_type_lut: LUT6_2
generic map (INIT => X"7777027700000200")
port map( I0 => instruction(12),
I1 => instruction(13),
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => '1',
O5 => returni_type,
O6 => move_type);
pc_mode1_lut: LUT6_2
generic map (INIT => X"0000F000000023FF")
port map( I0 => instruction(12),
I1 => returni_type,
I2 => move_type,
I3 => pc_move_is_valid,
I4 => active_interrupt,
I5 => '1',
O5 => pc_mode(0),
O6 => pc_mode(1));
pc_mode2_lut: LUT6
generic map (INIT => X"FFFFFFFF00040000")
port map( I0 => instruction(12),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => instruction(17),
I5 => active_interrupt,
O => pc_mode(2));
push_pop_lut: LUT6_2
generic map (INIT => X"FFFF100000002000")
port map( I0 => instruction(12),
I1 => instruction(13),
I2 => move_type,
I3 => pc_move_is_valid,
I4 => active_interrupt,
I5 => '1',
O5 => pop_stack,
O6 => push_stack);
--
-- Decoding for ALU
--
alu_decode0_lut: LUT6_2
generic map (INIT => X"03CA000004200000")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => '1',
I5 => '1',
O5 => alu_mux_sel_value(0),
O6 => arith_logical_sel(0));
alu_mux_sel0_flop: FD
port map ( D => alu_mux_sel_value(0),
Q => alu_mux_sel(0),
C => clk);
alu_decode1_lut: LUT6_2
generic map (INIT => X"7708000000000F00")
port map( I0 => carry_flag,
I1 => instruction(13),
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => '1',
O5 => alu_mux_sel_value(1),
O6 => arith_carry_in);
alu_mux_sel1_flop: FD
port map ( D => alu_mux_sel_value(1),
Q => alu_mux_sel(1),
C => clk);
alu_decode2_lut: LUT6_2
generic map (INIT => X"D000000002000000")
port map( I0 => instruction(14),
I1 => instruction(15),
I2 => instruction(16),
I3 => '1',
I4 => '1',
I5 => '1',
O5 => arith_logical_sel(1),
O6 => arith_logical_sel(2));
--
-- Decoding for strobes and enables
--
register_enable_type_lut: LUT6_2
generic map (INIT => X"00013F3F0010F7CE")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => instruction(17),
I5 => '1',
O5 => flag_enable_type,
O6 => register_enable_type);
register_enable_lut: LUT6_2
generic map (INIT => X"C0CC0000A0AA0000")
port map( I0 => flag_enable_type,
I1 => register_enable_type,
I2 => instruction(12),
I3 => instruction(17),
I4 => t_state(1),
I5 => '1',
O5 => flag_enable_value,
O6 => register_enable_value);
flag_enable_flop: FDR
port map ( D => flag_enable_value,
Q => flag_enable,
R => active_interrupt,
C => clk);
register_enable_flop: FDR
port map ( D => register_enable_value,
Q => register_enable,
R => active_interrupt,
C => clk);
spm_enable_lut: LUT6_2
generic map (INIT => X"8000000020000000")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(17),
I3 => strobe_type,
I4 => t_state(1),
I5 => '1',
O5 => k_write_strobe_value,
O6 => spm_enable_value);
k_write_strobe_flop: FDR
port map ( D => k_write_strobe_value,
Q => k_write_strobe,
R => active_interrupt,
C => clk);
spm_enable_flop: FDR
port map ( D => spm_enable_value,
Q => spm_enable,
R => active_interrupt,
C => clk);
read_strobe_lut: LUT6_2
generic map (INIT => X"4000000001000000")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(17),
I3 => strobe_type,
I4 => t_state(1),
I5 => '1',
O5 => read_strobe_value,
O6 => write_strobe_value);
write_strobe_flop: FDR
port map ( D => write_strobe_value,
Q => write_strobe,
R => active_interrupt,
C => clk);
read_strobe_flop: FDR
port map ( D => read_strobe_value,
Q => read_strobe,
R => active_interrupt,
C => clk);
--
-------------------------------------------------------------------------------------------
--
-- Register bank control
--
--
-- 2 x LUT6
-- 1 x FDR
-- 1 x FD
--
-------------------------------------------------------------------------------------------
--
regbank_type_lut: LUT6
generic map (INIT => X"0080020000000000")
port map( I0 => instruction(12),
I1 => instruction(13),
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => instruction(17),
O => regbank_type);
bank_lut: LUT6
generic map (INIT => X"ACACFF00FF00FF00")
port map( I0 => instruction(0),
I1 => shadow_bank,
I2 => instruction(16),
I3 => bank,
I4 => regbank_type,
I5 => t_state(1),
O => bank_value);
bank_flop: FDR
port map ( D => bank_value,
Q => bank,
R => internal_reset,
C => clk);
sx_addr4_flop: FD
port map ( D => sx_addr4_value,
Q => sx_addr(4),
C => clk);
sx_addr(3 downto 0) <= instruction(11 downto 8);
sy_addr <= bank & instruction(7 downto 4);
--
-------------------------------------------------------------------------------------------
--
-- Flags
--
--
-- 3 x LUT6
-- 5 x LUT6_2
-- 3 x FD
-- 2 x FDRE
-- 2 x XORCY
-- 5 x MUXCY
--
-------------------------------------------------------------------------------------------
--
arith_carry_xorcy: XORCY
port map( LI => '0',
CI => carry_arith_logical(7),
O => arith_carry_value);
arith_carry_flop: FD
port map ( D => arith_carry_value,
Q => arith_carry,
C => clk);
lower_parity_lut: LUT6_2
generic map (INIT => X"0000000087780000")
port map( I0 => instruction(13),
I1 => carry_flag,
I2 => arith_logical_result(0),
I3 => arith_logical_result(1),
I4 => '1',
I5 => '1',
O5 => lower_parity,
O6 => lower_parity_sel);
parity_muxcy: MUXCY
port map( DI => lower_parity,
CI => '0',
S => lower_parity_sel,
O => carry_lower_parity);
upper_parity_lut: LUT6
generic map (INIT => X"6996966996696996")
port map( I0 => arith_logical_result(2),
I1 => arith_logical_result(3),
I2 => arith_logical_result(4),
I3 => arith_logical_result(5),
I4 => arith_logical_result(6),
I5 => arith_logical_result(7),
O => upper_parity);
parity_xorcy: XORCY
port map( LI => upper_parity,
CI => carry_lower_parity,
O => parity);
shift_carry_lut: LUT6
generic map (INIT => X"FFFFAACCF0F0F0F0")
port map( I0 => sx(0),
I1 => sx(7),
I2 => shadow_carry_flag,
I3 => instruction(3),
I4 => instruction(7),
I5 => instruction(16),
O => shift_carry_value);
shift_carry_flop: FD
port map ( D => shift_carry_value,
Q => shift_carry,
C => clk);
carry_flag_lut: LUT6_2
generic map (INIT => X"3333AACCF0AA0000")
port map( I0 => shift_carry,
I1 => arith_carry,
I2 => parity,
I3 => instruction(14),
I4 => instruction(15),
I5 => instruction(16),
O5 => drive_carry_in_zero,
O6 => carry_flag_value);
carry_flag_flop: FDRE
port map ( D => carry_flag_value,
Q => carry_flag,
CE => flag_enable,
R => internal_reset,
C => clk);
init_zero_muxcy: MUXCY
port map( DI => drive_carry_in_zero,
CI => '0',
S => carry_flag_value,
O => carry_in_zero);
use_zero_flag_lut: LUT6_2
generic map (INIT => X"A280000000F000F0")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => '1',
I5 => '1',
O5 => strobe_type,
O6 => use_zero_flag_value);
use_zero_flag_flop: FD
port map ( D => use_zero_flag_value,
Q => use_zero_flag,
C => clk);
lower_zero_lut: LUT6_2
generic map (INIT => X"0000000000000001")
port map( I0 => alu_result(0),
I1 => alu_result(1),
I2 => alu_result(2),
I3 => alu_result(3),
I4 => alu_result(4),
I5 => '1',
O5 => lower_zero,
O6 => lower_zero_sel);
lower_zero_muxcy: MUXCY
port map( DI => lower_zero,
CI => carry_in_zero,
S => lower_zero_sel,
O => carry_lower_zero);
middle_zero_lut: LUT6_2
generic map (INIT => X"0000000D00000000")
port map( I0 => use_zero_flag,
I1 => zero_flag,
I2 => alu_result(5),
I3 => alu_result(6),
I4 => alu_result(7),
I5 => '1',
O5 => middle_zero,
O6 => middle_zero_sel);
middle_zero_muxcy: MUXCY
port map( DI => middle_zero,
CI => carry_lower_zero,
S => middle_zero_sel,
O => carry_middle_zero);
upper_zero_lut: LUT6
generic map (INIT => X"FBFF000000000000")
port map( I0 => instruction(14),
I1 => instruction(15),
I2 => instruction(16),
I3 => '1',
I4 => '1',
I5 => '1',
O => upper_zero_sel);
upper_zero_muxcy: MUXCY
port map( DI => shadow_zero_flag,
CI => carry_middle_zero,
S => upper_zero_sel,
O => zero_flag_value);
zero_flag_flop: FDRE
port map ( D => zero_flag_value,
Q => zero_flag,
CE => flag_enable,
R => internal_reset,
C => clk);
--
-------------------------------------------------------------------------------------------
--
-- 12-bit Program Address Generation
--
-------------------------------------------------------------------------------------------
--
--
-- Prepare 12-bit vector from the sX and sY register outputs.
--
register_vector <= sx(3 downto 0) & sy;
address_loop: for i in 0 to 11 generate
attribute hblknm : string;
attribute hblknm of pc_flop : label is "kcpsm6_pc" & integer'image(i/4);
attribute hblknm of return_vector_flop : label is "kcpsm6_stack_ram" & integer'image((i+4)/8);
begin
--
-------------------------------------------------------------------------------------------
--
-- Selection of vector to load program counter
--
-- instruction(12)
-- 0 Constant aaa from instruction(11:0)
-- 1 Return vector from stack
--
-- 'aaa' is used during 'JUMP aaa', 'JUMP c, aaa', 'CALL aaa' and 'CALL c, aaa'.
-- Return vector is used during 'RETURN', 'RETURN c', 'RETURN&LOAD' and 'RETURNI'.
--
-- 6 x LUT6_2
-- 12 x FD
--
-------------------------------------------------------------------------------------------
--
--
-- Pipeline output of the stack memory
--
return_vector_flop: FD
port map ( D => stack_memory(i),
Q => return_vector(i),
C => clk);
--
-- Multiplex instruction constant address and output from stack.
-- 2 bits per LUT so only generate when 'i' is even.
--
output_data: if (i rem 2)=0 generate
attribute hblknm : string;
attribute hblknm of pc_vector_mux_lut : label is "kcpsm6_vector" & integer'image(i/8);
begin
pc_vector_mux_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => instruction(i),
I1 => return_vector(i),
I2 => instruction(i+1),
I3 => return_vector(i+1),
I4 => instruction(12),
I5 => '1',
O5 => pc_vector(i),
O6 => pc_vector(i+1));
end generate output_data;
--
-------------------------------------------------------------------------------------------
--
-- Program Counter
--
-- Reset by internal_reset has highest priority.
-- Enabled by t_state(1) has second priority.
--
-- The function performed is defined by pc_mode(2:0).
--
-- pc_mode (2) (1) (0)
-- 0 0 1 pc+1 for normal program flow.
-- 1 0 0 Forces interrupt vector value (+0) during active interrupt.
-- The vector is defined by a generic with default value FF0 hex.
-- 1 1 0 register_vector (+0) for 'JUMP (sX, sY)' and 'CALL (sX, sY)'.
-- 0 1 0 pc_vector (+0) for 'JUMP/CALL aaa' and 'RETURNI'.
-- 0 1 1 pc_vector+1 for 'RETURN'.
--
-- Note that pc_mode(0) is High during operations that require an increment to occur.
-- The LUT6 associated with the LSB must invert pc or pc_vector in these cases and
-- pc_mode(0) also has to be connected to the start of the carry chain.
--
-- 3 Slices
-- 12 x LUT6
-- 11 x MUXCY
-- 12 x XORCY
-- 12 x FDRE
--
-------------------------------------------------------------------------------------------
--
pc_flop: FDRE
port map ( D => pc_value(i),
Q => pc(i),
R => internal_reset,
CE => t_state(1),
C => clk);
lsb_pc: if i=0 generate
attribute hblknm : string;
attribute hblknm of pc_xorcy : label is "kcpsm6_pc" & integer'image(i/4);
attribute hblknm of pc_muxcy : label is "kcpsm6_pc" & integer'image(i/4);
begin
--
-- Logic of LSB must invert selected value when pc_mode(0) is High.
-- The interrupt vector is defined by a generic.
--
low_int_vector: if interrupt_vector(i)='0' generate
attribute hblknm : string;
attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA000033CC0F00")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate low_int_vector;
high_int_vector: if interrupt_vector(i)='1' generate
attribute hblknm : string;
attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA00FF33CC0F00")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate high_int_vector;
--
-- pc_mode(0) connected to first MUXCY and carry input is '0'
--
pc_xorcy: XORCY
port map( LI => half_pc(i),
CI => '0',
O => pc_value(i));
pc_muxcy: MUXCY
port map( DI => pc_mode(0),
CI => '0',
S => half_pc(i),
O => carry_pc(i));
end generate lsb_pc;
upper_pc: if i>0 generate
attribute hblknm : string;
attribute hblknm of pc_xorcy : label is "kcpsm6_pc" & integer'image(i/4);
begin
--
-- Logic of upper section selects required value.
-- The interrupt vector is defined by a generic.
--
low_int_vector: if interrupt_vector(i)='0' generate
attribute hblknm : string;
attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA0000CCCCF000")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate low_int_vector;
high_int_vector: if interrupt_vector(i)='1' generate
attribute hblknm : string;
attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA00FFCCCCF000")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate high_int_vector;
--
-- Carry chain implementing remainder of increment function
--
pc_xorcy: XORCY
port map( LI => half_pc(i),
CI => carry_pc(i-1),
O => pc_value(i));
--
-- No MUXCY required at the top of the chain
--
mid_pc: if i<11 generate
attribute hblknm : string;
attribute hblknm of pc_muxcy : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_muxcy: MUXCY
port map( DI => '0',
CI => carry_pc(i-1),
S => half_pc(i),
O => carry_pc(i));
end generate mid_pc;
end generate upper_pc;
--
-------------------------------------------------------------------------------------------
--
end generate address_loop;
--
-------------------------------------------------------------------------------------------
--
-- Stack
-- Preserves upto 31 nested values of the Program Counter during CALL and RETURN.
-- Also preserves flags and bank selection during interrupt.
--
-- 2 x RAM32M
-- 4 x FD
-- 5 x FDR
-- 1 x LUT6
-- 4 x LUT6_2
-- 5 x XORCY
-- 5 x MUXCY
--
-------------------------------------------------------------------------------------------
--
shadow_carry_flag_flop: FD
port map ( D => stack_carry_flag,
Q => shadow_carry_flag,
C => clk);
stack_zero_flop: FD
port map ( D => stack_zero_flag,
Q => shadow_zero_value,
C => clk);
shadow_zero_flag_flop: FD
port map ( D => shadow_zero_value,
Q => shadow_zero_flag,
C => clk);
shadow_bank_flop: FD
port map ( D => stack_bank,
Q => shadow_bank,
C => clk);
stack_bit_flop: FD
port map ( D => stack_bit,
Q => special_bit,
C => clk);
stack_ram_low : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA(0) => stack_carry_flag,
DOA(1) => stack_zero_flag,
DOB(0) => stack_bank,
DOB(1) => stack_bit,
DOC => stack_memory(1 downto 0),
DOD => stack_memory(3 downto 2),
ADDRA => stack_pointer(4 downto 0),
ADDRB => stack_pointer(4 downto 0),
ADDRC => stack_pointer(4 downto 0),
ADDRD => stack_pointer(4 downto 0),
DIA(0) => carry_flag,
DIA(1) => zero_flag,
DIB(0) => bank,
DIB(1) => run,
DIC => pc(1 downto 0),
DID => pc(3 downto 2),
WE => t_state(1),
WCLK => clk );
stack_ram_high : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => stack_memory(5 downto 4),
DOB => stack_memory(7 downto 6),
DOC => stack_memory(9 downto 8),
DOD => stack_memory(11 downto 10),
ADDRA => stack_pointer(4 downto 0),
ADDRB => stack_pointer(4 downto 0),
ADDRC => stack_pointer(4 downto 0),
ADDRD => stack_pointer(4 downto 0),
DIA => pc(5 downto 4),
DIB => pc(7 downto 6),
DIC => pc(9 downto 8),
DID => pc(11 downto 10),
WE => t_state(1),
WCLK => clk );
stack_loop: for i in 0 to 4 generate
begin
lsb_stack: if i=0 generate
attribute hblknm : string;
attribute hblknm of pointer_flop : label is "kcpsm6_stack" & integer'image(i/4);
attribute hblknm of stack_pointer_lut : label is "kcpsm6_stack" & integer'image(i/4);
attribute hblknm of stack_xorcy : label is "kcpsm6_stack" & integer'image(i/4);
attribute hblknm of stack_muxcy : label is "kcpsm6_stack" & integer'image(i/4);
begin
pointer_flop: FDR
port map ( D => stack_pointer_value(i),
Q => stack_pointer(i),
R => internal_reset,
C => clk);
stack_pointer_lut: LUT6_2
generic map (INIT => X"001529AAAAAAAAAA")
port map( I0 => stack_pointer(i),
I1 => pop_stack,
I2 => push_stack,
I3 => t_state(1),
I4 => t_state(2),
I5 => '1',
O5 => feed_pointer_value(i),
O6 => half_pointer_value(i));
stack_xorcy: XORCY
port map( LI => half_pointer_value(i),
CI => '0',
O => stack_pointer_value(i));
stack_muxcy: MUXCY
port map( DI => feed_pointer_value(i),
CI => '0',
S => half_pointer_value(i),
O => stack_pointer_carry(i));
end generate lsb_stack;
upper_stack: if i>0 generate
attribute hblknm : string;
attribute hblknm of pointer_flop : label is "kcpsm6_stack" & integer'image(i/4);
attribute hblknm of stack_pointer_lut : label is "kcpsm6_stack" & integer'image(i/4);
attribute hblknm of stack_xorcy : label is "kcpsm6_stack" & integer'image(i/4);
attribute hblknm of stack_muxcy : label is "kcpsm6_stack" & integer'image(i/4);
begin
pointer_flop: FDR
port map ( D => stack_pointer_value(i),
Q => stack_pointer(i),
R => internal_reset,
C => clk);
stack_pointer_lut: LUT6_2
generic map (INIT => X"002A252AAAAAAAAA")
port map( I0 => stack_pointer(i),
I1 => pop_stack,
I2 => push_stack,
I3 => t_state(1),
I4 => t_state(2),
I5 => '1',
O5 => feed_pointer_value(i),
O6 => half_pointer_value(i));
stack_xorcy: XORCY
port map( LI => half_pointer_value(i),
CI => stack_pointer_carry(i-1),
O => stack_pointer_value(i));
stack_muxcy: MUXCY
port map( DI => feed_pointer_value(i),
CI => stack_pointer_carry(i-1),
S => half_pointer_value(i),
O => stack_pointer_carry(i));
end generate upper_stack;
end generate stack_loop;
--
-------------------------------------------------------------------------------------------
--
-- 8-bit Data Path
--
-------------------------------------------------------------------------------------------
--
data_path_loop: for i in 0 to 7 generate
attribute hblknm : string;
attribute hblknm of arith_logical_lut : label is "kcpsm6_add" & integer'image(i/4);
attribute hblknm of arith_logical_flop : label is "kcpsm6_add" & integer'image(i/4);
attribute hblknm of alu_mux_lut : label is "kcpsm6_alu" & integer'image(i/4);
begin
--
-------------------------------------------------------------------------------------------
--
-- Selection of second operand to ALU and port_id
--
-- instruction(12)
-- 0 Register sY
-- 1 Constant kk
--
-- 4 x LUT6_2
--
-------------------------------------------------------------------------------------------
--
--
-- 2 bits per LUT so only generate when 'i' is even
--
output_data: if (i rem 2)=0 generate
attribute hblknm : string;
attribute hblknm of sy_kk_mux_lut : label is "kcpsm6_port_id";
begin
sy_kk_mux_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sy(i),
I1 => instruction(i),
I2 => sy(i+1),
I3 => instruction(i+1),
I4 => instruction(12),
I5 => '1',
O5 => sy_or_kk(i),
O6 => sy_or_kk(i+1));
end generate output_data;
--
-------------------------------------------------------------------------------------------
--
-- Selection of out_port value
--
-- instruction(13)
-- 0 Register sX
-- 1 Constant kk from instruction(11:4)
--
-- 4 x LUT6_2
--
-------------------------------------------------------------------------------------------
--
--
-- 2 bits per LUT so only generate when 'i' is even
--
second_operand: if (i rem 2)=0 generate
attribute hblknm : string;
attribute hblknm of out_port_lut : label is "kcpsm6_out_port";
begin
out_port_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sx(i),
I1 => instruction(i+4),
I2 => sx(i+1),
I3 => instruction(i+5),
I4 => instruction(13),
I5 => '1',
O5 => out_port(i),
O6 => out_port(i+1));
end generate second_operand;
--
-------------------------------------------------------------------------------------------
--
-- Arithmetic and Logical operations
--
-- Definition of....
-- ADD and SUB also used for ADDCY, SUBCY, COMPARE and COMPARECY.
-- LOAD, AND, OR and XOR also used for LOAD*, RETURN&LOAD, TEST and TESTCY.
--
-- arith_logical_sel (2) (1) (0)
-- 0 0 0 - LOAD
-- 0 0 1 - AND
-- 0 1 0 - OR
-- 0 1 1 - XOR
-- 1 X 0 - SUB
-- 1 X 1 - ADD
--
-- Includes pipeline stage.
--
-- 2 Slices
-- 8 x LUT6_2
-- 8 x MUXCY
-- 8 x XORCY
-- 8 x FD
--
-------------------------------------------------------------------------------------------
--
arith_logical_lut: LUT6_2
generic map (INIT => X"69696E8ACCCC0000")
port map( I0 => sy_or_kk(i),
I1 => sx(i),
I2 => arith_logical_sel(0),
I3 => arith_logical_sel(1),
I4 => arith_logical_sel(2),
I5 => '1',
O5 => logical_carry_mask(i),
O6 => half_arith_logical(i));
arith_logical_flop: FD
port map ( D => arith_logical_value(i),
Q => arith_logical_result(i),
C => clk);
lsb_arith_logical: if i=0 generate
attribute hblknm : string;
attribute hblknm of arith_logical_muxcy : label is "kcpsm6_add" & integer'image(i/4);
attribute hblknm of arith_logical_xorcy : label is "kcpsm6_add" & integer'image(i/4);
begin
--
-- Carry input to first MUXCY and XORCY
--
arith_logical_muxcy: MUXCY
port map( DI => logical_carry_mask(i),
CI => arith_carry_in,
S => half_arith_logical(i),
O => carry_arith_logical(i));
arith_logical_xorcy: XORCY
port map( LI => half_arith_logical(i),
CI => arith_carry_in,
O => arith_logical_value(i));
end generate lsb_arith_logical;
upper_arith_logical: if i>0 generate
attribute hblknm : string;
attribute hblknm of arith_logical_muxcy : label is "kcpsm6_add" & integer'image(i/4);
attribute hblknm of arith_logical_xorcy : label is "kcpsm6_add" & integer'image(i/4);
begin
--
-- Main carry chain
--
arith_logical_muxcy: MUXCY
port map( DI => logical_carry_mask(i),
CI => carry_arith_logical(i-1),
S => half_arith_logical(i),
O => carry_arith_logical(i));
arith_logical_xorcy: XORCY
port map( LI => half_arith_logical(i),
CI => carry_arith_logical(i-1),
O => arith_logical_value(i));
end generate upper_arith_logical;
--
-------------------------------------------------------------------------------------------
--
-- Shift and Rotate operations
--
-- Definition of SL0, SL1, SLX, SLA, RL, SR0, SR1, SRX, SRA, and RR
--
-- instruction (3) (2) (1) (0)
-- 0 1 1 0 - SL0
-- 0 1 1 1 - SL1
-- 0 1 0 0 - SLX
-- 0 0 0 0 - SLA
-- 0 0 1 0 - RL
-- 1 1 1 0 - SR0
-- 1 1 1 1 - SR1
-- 1 0 1 0 - SRX
-- 1 0 0 0 - SRA
-- 1 1 0 0 - RR
--
-- instruction(3)
-- 0 - Left
-- 1 - Right
--
-- instruction (2) (1) Bit shifted in
-- 0 0 Carry_flag
-- 0 1 sX(7)
-- 1 0 sX(0)
-- 1 1 instruction(0)
--
-- Includes pipeline stage.
--
-- 4 x LUT6_2
-- 1 x LUT6
-- 8 x FD
--
-------------------------------------------------------------------------------------------
--
low_hwbuild: if hwbuild(i)='0' generate
attribute hblknm : string;
attribute hblknm of shift_rotate_flop : label is "kcpsm6_sandr";
begin
--
-- Reset Flip-flop to form '0' for this bit of HWBUILD
--
shift_rotate_flop: FDR
port map ( D => shift_rotate_value(i),
Q => shift_rotate_result(i),
R => instruction(7),
C => clk);
end generate low_hwbuild;
high_hwbuild: if hwbuild(i)='1' generate
attribute hblknm : string;
attribute hblknm of shift_rotate_flop : label is "kcpsm6_sandr";
begin
--
-- Set Flip-flop to form '1' for this bit of HWBUILD
--
shift_rotate_flop: FDS
port map ( D => shift_rotate_value(i),
Q => shift_rotate_result(i),
S => instruction(7),
C => clk);
end generate high_hwbuild;
lsb_shift_rotate: if i=0 generate
attribute hblknm : string;
attribute hblknm of shift_rotate_lut : label is "kcpsm6_sandr";
attribute hblknm of shift_bit_lut : label is "kcpsm6_decode1";
begin
--
-- Select bit to be shifted or rotated into result
--
shift_bit_lut: LUT6
generic map (INIT => X"BFBC8F8CB3B08380")
port map( I0 => instruction(0),
I1 => instruction(1),
I2 => instruction(2),
I3 => carry_flag,
I4 => sx(0),
I5 => sx(7),
O => shift_in_bit);
--
-- Define lower bits of result
--
shift_rotate_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => shift_in_bit,
I1 => sx(i+1),
I2 => sx(i),
I3 => sx(i+2),
I4 => instruction(3),
I5 => '1',
O5 => shift_rotate_value(i),
O6 => shift_rotate_value(i+1));
end generate lsb_shift_rotate;
mid_shift_rotate: if i=2 or i=4 generate
attribute hblknm : string;
attribute hblknm of shift_rotate_lut : label is "kcpsm6_sandr";
begin
--
-- Define middle bits of result
--
shift_rotate_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sx(i-1),
I1 => sx(i+1),
I2 => sx(i),
I3 => sx(i+2),
I4 => instruction(3),
I5 => '1',
O5 => shift_rotate_value(i),
O6 => shift_rotate_value(i+1));
end generate mid_shift_rotate;
msb_shift_rotate: if i=6 generate
attribute hblknm : string;
attribute hblknm of shift_rotate_lut : label is "kcpsm6_sandr";
begin
--
-- Define upper bits of result
--
shift_rotate_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sx(i-1),
I1 => sx(i+1),
I2 => sx(i),
I3 => shift_in_bit,
I4 => instruction(3),
I5 => '1',
O5 => shift_rotate_value(i),
O6 => shift_rotate_value(i+1));
end generate msb_shift_rotate;
--
-------------------------------------------------------------------------------------------
--
-- Multiplex outputs from ALU functions, scratch pad memory and input port.
--
-- alu_mux_sel (1) (0)
-- 0 0 Arithmetic and Logical Instructions
-- 0 1 Shift and Rotate Instructions
-- 1 0 Input Port
-- 1 1 Scratch Pad Memory
--
-- 8 x LUT6
--
-------------------------------------------------------------------------------------------
--
alu_mux_lut: LUT6
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => arith_logical_result(i),
I1 => shift_rotate_result(i),
I2 => in_port(i),
I3 => spm_data(i),
I4 => alu_mux_sel(0),
I5 => alu_mux_sel(1),
O => alu_result(i));
--
-------------------------------------------------------------------------------------------
--
-- Scratchpad Memory with output register.
--
-- The size of the scratch pad memory is defined by the 'scratch_pad_memory_size' generic.
-- The default size is 64 bytes the same as KCPSM3 but this can be increased to 128 or 256
-- bytes at an additional cost of 2 and 6 Slices.
--
--
-- 8 x RAM256X1S (256 bytes).
-- 8 x RAM128X1S (128 bytes).
-- 2 x RAM64M (64 bytes).
--
-- 8 x FD.
--
-------------------------------------------------------------------------------------------
--
small_spm: if scratch_pad_memory_size = 64 generate
attribute hblknm : string;
attribute hblknm of spm_flop : label is "kcpsm6_spm" & integer'image(i/4);
begin
spm_flop: FD
port map ( D => spm_ram_data(i),
Q => spm_data(i),
C => clk);
small_spm_ram: if (i=0 or i=4) generate
attribute hblknm of spm_ram : label is "kcpsm6_spm" & integer'image(i/4);
begin
spm_ram: RAM64M
generic map ( INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => spm_ram_data(i),
DOB => spm_ram_data(i+1),
DOC => spm_ram_data(i+2),
DOD => spm_ram_data(i+3),
ADDRA => sy_or_kk(5 downto 0),
ADDRB => sy_or_kk(5 downto 0),
ADDRC => sy_or_kk(5 downto 0),
ADDRD => sy_or_kk(5 downto 0),
DIA => sx(i),
DIB => sx(i+1),
DIC => sx(i+2),
DID => sx(i+3),
WE => spm_enable,
WCLK => clk );
end generate small_spm_ram;
end generate small_spm;
medium_spm: if scratch_pad_memory_size = 128 generate
attribute hblknm : string;
attribute hblknm of spm_ram : label is "kcpsm6_spm" & integer'image(i/2);
attribute hblknm of spm_flop : label is "kcpsm6_spm" & integer'image(i/2);
begin
spm_ram: RAM128X1S
generic map(INIT => X"00000000000000000000000000000000")
port map ( D => sx(i),
WE => spm_enable,
WCLK => clk,
A0 => sy_or_kk(0),
A1 => sy_or_kk(1),
A2 => sy_or_kk(2),
A3 => sy_or_kk(3),
A4 => sy_or_kk(4),
A5 => sy_or_kk(5),
A6 => sy_or_kk(6),
O => spm_ram_data(i));
spm_flop: FD
port map ( D => spm_ram_data(i),
Q => spm_data(i),
C => clk);
end generate medium_spm;
large_spm: if scratch_pad_memory_size = 256 generate
attribute hblknm : string;
attribute hblknm of spm_ram : label is "kcpsm6_spm" & integer'image(i);
attribute hblknm of spm_flop : label is "kcpsm6_spm" & integer'image(i);
begin
spm_ram: RAM256X1S
generic map(INIT => X"0000000000000000000000000000000000000000000000000000000000000000")
port map ( D => sx(i),
WE => spm_enable,
WCLK => clk,
A => sy_or_kk,
O => spm_ram_data(i));
spm_flop: FD
port map ( D => spm_ram_data(i),
Q => spm_data(i),
C => clk);
end generate large_spm;
--
-------------------------------------------------------------------------------------------
--
end generate data_path_loop;
--
-------------------------------------------------------------------------------------------
--
-- Two Banks of 16 General Purpose Registers.
--
-- sx_addr - Address for sX is formed by bank select and instruction[11:8]
-- sy_addr - Address for sY is formed by bank select and instruction[7:4]
--
-- 2 Slices
-- 2 x RAM32M
--
-------------------------------------------------------------------------------------------
--
lower_reg_banks : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => sy(1 downto 0),
DOB => sx(1 downto 0),
DOC => sy(3 downto 2),
DOD => sx(3 downto 2),
ADDRA => sy_addr,
ADDRB => sx_addr,
ADDRC => sy_addr,
ADDRD => sx_addr,
DIA => alu_result(1 downto 0),
DIB => alu_result(1 downto 0),
DIC => alu_result(3 downto 2),
DID => alu_result(3 downto 2),
WE => register_enable,
WCLK => clk );
upper_reg_banks : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => sy(5 downto 4),
DOB => sx(5 downto 4),
DOC => sy(7 downto 6),
DOD => sx(7 downto 6),
ADDRA => sy_addr,
ADDRB => sx_addr,
ADDRC => sy_addr,
ADDRD => sx_addr,
DIA => alu_result(5 downto 4),
DIB => alu_result(5 downto 4),
DIC => alu_result(7 downto 6),
DID => alu_result(7 downto 6),
WE => register_enable,
WCLK => clk );
--
-------------------------------------------------------------------------------------------
--
-- Connections to KCPSM6 outputs.
--
-------------------------------------------------------------------------------------------
--
address <= pc;
bram_enable <= t_state(2);
--
-------------------------------------------------------------------------------------------
--
-- Connections KCPSM6 Outputs.
--
-------------------------------------------------------------------------------------------
--
port_id <= sy_or_kk;
--
-------------------------------------------------------------------------------------------
--
-- End of description for kcpsm6 macro.
--
-------------------------------------------------------------------------------------------
--
-- *****************************************************
-- * Code for simulation purposes only after this line *
-- *****************************************************
--
--
-- Disassemble the instruction codes to form a text string for display.
-- Determine status of reset and flags and present in the form of a text string.
-- Provide signals to simulate the contents of each register and scratch pad memory
-- location.
--
-------------------------------------------------------------------------------------------
--
--All of this section is ignored during synthesis.
--synthesis translate off
simulation: process (clk, instruction, carry_flag, zero_flag, bank, interrupt_enable)
--
-- Variables for contents of each register in each bank
--
variable bank_a_s0 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s1 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s2 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s3 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s4 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s5 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s6 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s7 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s8 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s9 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sa : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sb : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sc : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sd : std_logic_vector(7 downto 0) := X"00";
variable bank_a_se : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sf : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s0 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s1 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s2 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s3 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s4 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s5 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s6 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s7 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s8 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s9 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sa : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sb : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sc : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sd : std_logic_vector(7 downto 0) := X"00";
variable bank_b_se : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sf : std_logic_vector(7 downto 0) := X"00";
--
-- Temporary variables for instruction decoding
--
variable sx_decode : string(1 to 2); -- sX register specification
variable sy_decode : string(1 to 2); -- sY register specification
variable kk_decode : string(1 to 2); -- constant value kk, pp or ss
variable aaa_decode : string(1 to 3); -- address value aaa
--
-----------------------------------------------------------------------------------------
--
-- Function to convert 4-bit binary nibble to hexadecimal character
--
-----------------------------------------------------------------------------------------
--
function hexcharacter (nibble: std_logic_vector(3 downto 0))
return character is
variable hex: character;
begin
case nibble is
when "0000" => hex := '0';
when "0001" => hex := '1';
when "0010" => hex := '2';
when "0011" => hex := '3';
when "0100" => hex := '4';
when "0101" => hex := '5';
when "0110" => hex := '6';
when "0111" => hex := '7';
when "1000" => hex := '8';
when "1001" => hex := '9';
when "1010" => hex := 'A';
when "1011" => hex := 'B';
when "1100" => hex := 'C';
when "1101" => hex := 'D';
when "1110" => hex := 'E';
when "1111" => hex := 'F';
when others => hex := 'x';
end case;
return hex;
end hexcharacter;
--
-----------------------------------------------------------------------------------------
--
begin
-- decode first register sX
sx_decode(1) := 's';
sx_decode(2) := hexcharacter(instruction(11 downto 8));
-- decode second register sY
sy_decode(1) := 's';
sy_decode(2) := hexcharacter(instruction(7 downto 4));
-- decode constant value
kk_decode(1) := hexcharacter(instruction(7 downto 4));
kk_decode(2) := hexcharacter(instruction(3 downto 0));
-- address value
aaa_decode(1) := hexcharacter(instruction(11 downto 8));
aaa_decode(2) := hexcharacter(instruction(7 downto 4));
aaa_decode(3) := hexcharacter(instruction(3 downto 0));
-- decode instruction
case instruction(17 downto 12) is
when "000000" => kcpsm6_opcode <= "LOAD " & sx_decode & ", " & sy_decode & " ";
when "000001" => kcpsm6_opcode <= "LOAD " & sx_decode & ", " & kk_decode & " ";
when "010110" => kcpsm6_opcode <= "STAR " & sx_decode & ", " & sy_decode & " ";
when "000010" => kcpsm6_opcode <= "AND " & sx_decode & ", " & sy_decode & " ";
when "000011" => kcpsm6_opcode <= "AND " & sx_decode & ", " & kk_decode & " ";
when "000100" => kcpsm6_opcode <= "OR " & sx_decode & ", " & sy_decode & " ";
when "000101" => kcpsm6_opcode <= "OR " & sx_decode & ", " & kk_decode & " ";
when "000110" => kcpsm6_opcode <= "XOR " & sx_decode & ", " & sy_decode & " ";
when "000111" => kcpsm6_opcode <= "XOR " & sx_decode & ", " & kk_decode & " ";
when "001100" => kcpsm6_opcode <= "TEST " & sx_decode & ", " & sy_decode & " ";
when "001101" => kcpsm6_opcode <= "TEST " & sx_decode & ", " & kk_decode & " ";
when "001110" => kcpsm6_opcode <= "TESTCY " & sx_decode & ", " & sy_decode & " ";
when "001111" => kcpsm6_opcode <= "TESTCY " & sx_decode & ", " & kk_decode & " ";
when "010000" => kcpsm6_opcode <= "ADD " & sx_decode & ", " & sy_decode & " ";
when "010001" => kcpsm6_opcode <= "ADD " & sx_decode & ", " & kk_decode & " ";
when "010010" => kcpsm6_opcode <= "ADDCY " & sx_decode & ", " & sy_decode & " ";
when "010011" => kcpsm6_opcode <= "ADDCY " & sx_decode & ", " & kk_decode & " ";
when "011000" => kcpsm6_opcode <= "SUB " & sx_decode & ", " & sy_decode & " ";
when "011001" => kcpsm6_opcode <= "SUB " & sx_decode & ", " & kk_decode & " ";
when "011010" => kcpsm6_opcode <= "SUBCY " & sx_decode & ", " & sy_decode & " ";
when "011011" => kcpsm6_opcode <= "SUBCY " & sx_decode & ", " & kk_decode & " ";
when "011100" => kcpsm6_opcode <= "COMPARE " & sx_decode & ", " & sy_decode & " ";
when "011101" => kcpsm6_opcode <= "COMPARE " & sx_decode & ", " & kk_decode & " ";
when "011110" => kcpsm6_opcode <= "COMPARECY " & sx_decode & ", " & sy_decode & " ";
when "011111" => kcpsm6_opcode <= "COMPARECY " & sx_decode & ", " & kk_decode & " ";
when "010100" =>
if instruction(7) = '1' then
kcpsm6_opcode <= "HWBUILD " & sx_decode & " ";
else
case instruction(3 downto 0) is
when "0110" => kcpsm6_opcode <= "SL0 " & sx_decode & " ";
when "0111" => kcpsm6_opcode <= "SL1 " & sx_decode & " ";
when "0100" => kcpsm6_opcode <= "SLX " & sx_decode & " ";
when "0000" => kcpsm6_opcode <= "SLA " & sx_decode & " ";
when "0010" => kcpsm6_opcode <= "RL " & sx_decode & " ";
when "1110" => kcpsm6_opcode <= "SR0 " & sx_decode & " ";
when "1111" => kcpsm6_opcode <= "SR1 " & sx_decode & " ";
when "1010" => kcpsm6_opcode <= "SRX " & sx_decode & " ";
when "1000" => kcpsm6_opcode <= "SRA " & sx_decode & " ";
when "1100" => kcpsm6_opcode <= "RR " & sx_decode & " ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
end if;
when "101100" => kcpsm6_opcode <= "OUTPUT " & sx_decode & ", (" & sy_decode & ") ";
when "101101" => kcpsm6_opcode <= "OUTPUT " & sx_decode & ", " & kk_decode & " ";
when "101011" => kcpsm6_opcode <= "OUTPUTK " & aaa_decode(1) & aaa_decode(2)
& ", " & aaa_decode(3) & " ";
when "001000" => kcpsm6_opcode <= "INPUT " & sx_decode & ", (" & sy_decode & ") ";
when "001001" => kcpsm6_opcode <= "INPUT " & sx_decode & ", " & kk_decode & " ";
when "101110" => kcpsm6_opcode <= "STORE " & sx_decode & ", (" & sy_decode & ") ";
when "101111" => kcpsm6_opcode <= "STORE " & sx_decode & ", " & kk_decode & " ";
when "001010" => kcpsm6_opcode <= "FETCH " & sx_decode & ", (" & sy_decode & ") ";
when "001011" => kcpsm6_opcode <= "FETCH " & sx_decode & ", " & kk_decode & " ";
when "100010" => kcpsm6_opcode <= "JUMP " & aaa_decode & " ";
when "110010" => kcpsm6_opcode <= "JUMP Z, " & aaa_decode & " ";
when "110110" => kcpsm6_opcode <= "JUMP NZ, " & aaa_decode & " ";
when "111010" => kcpsm6_opcode <= "JUMP C, " & aaa_decode & " ";
when "111110" => kcpsm6_opcode <= "JUMP NC, " & aaa_decode & " ";
when "100110" => kcpsm6_opcode <= "JUMP@ (" & sx_decode & ", " & sy_decode & ") ";
when "100000" => kcpsm6_opcode <= "CALL " & aaa_decode & " ";
when "110000" => kcpsm6_opcode <= "CALL Z, " & aaa_decode & " ";
when "110100" => kcpsm6_opcode <= "CALL NZ, " & aaa_decode & " ";
when "111000" => kcpsm6_opcode <= "CALL C, " & aaa_decode & " ";
when "111100" => kcpsm6_opcode <= "CALL NC, " & aaa_decode & " ";
when "100100" => kcpsm6_opcode <= "CALL@ (" & sx_decode & ", " & sy_decode & ") ";
when "100101" => kcpsm6_opcode <= "RETURN ";
when "110001" => kcpsm6_opcode <= "RETURN Z ";
when "110101" => kcpsm6_opcode <= "RETURN NZ ";
when "111001" => kcpsm6_opcode <= "RETURN C ";
when "111101" => kcpsm6_opcode <= "RETURN NC ";
when "100001" => kcpsm6_opcode <= "LOAD&RETURN " & sx_decode & ", " & kk_decode & " ";
when "101001" =>
case instruction(0) is
when '0' => kcpsm6_opcode <= "RETURNI DISABLE ";
when '1' => kcpsm6_opcode <= "RETURNI ENABLE ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
when "101000" =>
case instruction(0) is
when '0' => kcpsm6_opcode <= "DISABLE INTERRUPT ";
when '1' => kcpsm6_opcode <= "ENABLE INTERRUPT ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
when "110111" =>
case instruction(0) is
when '0' => kcpsm6_opcode <= "REGBANK A ";
when '1' => kcpsm6_opcode <= "REGBANK B ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
-- Flag status information
if zero_flag = '0' then
kcpsm6_status(3 to 5) <= "NZ,";
else
kcpsm6_status(3 to 5) <= " Z,";
end if;
if carry_flag = '0' then
kcpsm6_status(6 to 8) <= "NC,";
else
kcpsm6_status(6 to 8) <= " C,";
end if;
if interrupt_enable = '0' then
kcpsm6_status(9 to 10) <= "ID";
else
kcpsm6_status(9 to 10) <= "IE";
end if;
-- Operational status
if clk'event and clk = '1' then
if internal_reset = '1' then
kcpsm6_status(11 to 16) <= ",Reset";
else
if sync_sleep = '1' and t_state = "00" then
kcpsm6_status(11 to 16) <= ",Sleep";
else
kcpsm6_status(11 to 16) <= " ";
end if;
end if;
end if;
-- Simulation of register contents
if clk'event and clk = '1' then
if register_enable = '1' then
case sx_addr is
when "00000" => bank_a_s0 := alu_result;
when "00001" => bank_a_s1 := alu_result;
when "00010" => bank_a_s2 := alu_result;
when "00011" => bank_a_s3 := alu_result;
when "00100" => bank_a_s4 := alu_result;
when "00101" => bank_a_s5 := alu_result;
when "00110" => bank_a_s6 := alu_result;
when "00111" => bank_a_s7 := alu_result;
when "01000" => bank_a_s8 := alu_result;
when "01001" => bank_a_s9 := alu_result;
when "01010" => bank_a_sa := alu_result;
when "01011" => bank_a_sb := alu_result;
when "01100" => bank_a_sc := alu_result;
when "01101" => bank_a_sd := alu_result;
when "01110" => bank_a_se := alu_result;
when "01111" => bank_a_sf := alu_result;
when "10000" => bank_b_s0 := alu_result;
when "10001" => bank_b_s1 := alu_result;
when "10010" => bank_b_s2 := alu_result;
when "10011" => bank_b_s3 := alu_result;
when "10100" => bank_b_s4 := alu_result;
when "10101" => bank_b_s5 := alu_result;
when "10110" => bank_b_s6 := alu_result;
when "10111" => bank_b_s7 := alu_result;
when "11000" => bank_b_s8 := alu_result;
when "11001" => bank_b_s9 := alu_result;
when "11010" => bank_b_sa := alu_result;
when "11011" => bank_b_sb := alu_result;
when "11100" => bank_b_sc := alu_result;
when "11101" => bank_b_sd := alu_result;
when "11110" => bank_b_se := alu_result;
when "11111" => bank_b_sf := alu_result;
when others => null;
end case;
end if;
--simulation of scratch pad memory contents
if spm_enable = '1' then
case sy_or_kk is
when "00000000" => sim_spm00 <= sx;
when "00000001" => sim_spm01 <= sx;
when "00000010" => sim_spm02 <= sx;
when "00000011" => sim_spm03 <= sx;
when "00000100" => sim_spm04 <= sx;
when "00000101" => sim_spm05 <= sx;
when "00000110" => sim_spm06 <= sx;
when "00000111" => sim_spm07 <= sx;
when "00001000" => sim_spm08 <= sx;
when "00001001" => sim_spm09 <= sx;
when "00001010" => sim_spm0A <= sx;
when "00001011" => sim_spm0B <= sx;
when "00001100" => sim_spm0C <= sx;
when "00001101" => sim_spm0D <= sx;
when "00001110" => sim_spm0E <= sx;
when "00001111" => sim_spm0F <= sx;
when "00010000" => sim_spm10 <= sx;
when "00010001" => sim_spm11 <= sx;
when "00010010" => sim_spm12 <= sx;
when "00010011" => sim_spm13 <= sx;
when "00010100" => sim_spm14 <= sx;
when "00010101" => sim_spm15 <= sx;
when "00010110" => sim_spm16 <= sx;
when "00010111" => sim_spm17 <= sx;
when "00011000" => sim_spm18 <= sx;
when "00011001" => sim_spm19 <= sx;
when "00011010" => sim_spm1A <= sx;
when "00011011" => sim_spm1B <= sx;
when "00011100" => sim_spm1C <= sx;
when "00011101" => sim_spm1D <= sx;
when "00011110" => sim_spm1E <= sx;
when "00011111" => sim_spm1F <= sx;
when "00100000" => sim_spm20 <= sx;
when "00100001" => sim_spm21 <= sx;
when "00100010" => sim_spm22 <= sx;
when "00100011" => sim_spm23 <= sx;
when "00100100" => sim_spm24 <= sx;
when "00100101" => sim_spm25 <= sx;
when "00100110" => sim_spm26 <= sx;
when "00100111" => sim_spm27 <= sx;
when "00101000" => sim_spm28 <= sx;
when "00101001" => sim_spm29 <= sx;
when "00101010" => sim_spm2A <= sx;
when "00101011" => sim_spm2B <= sx;
when "00101100" => sim_spm2C <= sx;
when "00101101" => sim_spm2D <= sx;
when "00101110" => sim_spm2E <= sx;
when "00101111" => sim_spm2F <= sx;
when "00110000" => sim_spm30 <= sx;
when "00110001" => sim_spm31 <= sx;
when "00110010" => sim_spm32 <= sx;
when "00110011" => sim_spm33 <= sx;
when "00110100" => sim_spm34 <= sx;
when "00110101" => sim_spm35 <= sx;
when "00110110" => sim_spm36 <= sx;
when "00110111" => sim_spm37 <= sx;
when "00111000" => sim_spm38 <= sx;
when "00111001" => sim_spm39 <= sx;
when "00111010" => sim_spm3A <= sx;
when "00111011" => sim_spm3B <= sx;
when "00111100" => sim_spm3C <= sx;
when "00111101" => sim_spm3D <= sx;
when "00111110" => sim_spm3E <= sx;
when "00111111" => sim_spm3F <= sx;
when "01000000" => sim_spm40 <= sx;
when "01000001" => sim_spm41 <= sx;
when "01000010" => sim_spm42 <= sx;
when "01000011" => sim_spm43 <= sx;
when "01000100" => sim_spm44 <= sx;
when "01000101" => sim_spm45 <= sx;
when "01000110" => sim_spm46 <= sx;
when "01000111" => sim_spm47 <= sx;
when "01001000" => sim_spm48 <= sx;
when "01001001" => sim_spm49 <= sx;
when "01001010" => sim_spm4A <= sx;
when "01001011" => sim_spm4B <= sx;
when "01001100" => sim_spm4C <= sx;
when "01001101" => sim_spm4D <= sx;
when "01001110" => sim_spm4E <= sx;
when "01001111" => sim_spm4F <= sx;
when "01010000" => sim_spm50 <= sx;
when "01010001" => sim_spm51 <= sx;
when "01010010" => sim_spm52 <= sx;
when "01010011" => sim_spm53 <= sx;
when "01010100" => sim_spm54 <= sx;
when "01010101" => sim_spm55 <= sx;
when "01010110" => sim_spm56 <= sx;
when "01010111" => sim_spm57 <= sx;
when "01011000" => sim_spm58 <= sx;
when "01011001" => sim_spm59 <= sx;
when "01011010" => sim_spm5A <= sx;
when "01011011" => sim_spm5B <= sx;
when "01011100" => sim_spm5C <= sx;
when "01011101" => sim_spm5D <= sx;
when "01011110" => sim_spm5E <= sx;
when "01011111" => sim_spm5F <= sx;
when "01100000" => sim_spm60 <= sx;
when "01100001" => sim_spm61 <= sx;
when "01100010" => sim_spm62 <= sx;
when "01100011" => sim_spm63 <= sx;
when "01100100" => sim_spm64 <= sx;
when "01100101" => sim_spm65 <= sx;
when "01100110" => sim_spm66 <= sx;
when "01100111" => sim_spm67 <= sx;
when "01101000" => sim_spm68 <= sx;
when "01101001" => sim_spm69 <= sx;
when "01101010" => sim_spm6A <= sx;
when "01101011" => sim_spm6B <= sx;
when "01101100" => sim_spm6C <= sx;
when "01101101" => sim_spm6D <= sx;
when "01101110" => sim_spm6E <= sx;
when "01101111" => sim_spm6F <= sx;
when "01110000" => sim_spm70 <= sx;
when "01110001" => sim_spm71 <= sx;
when "01110010" => sim_spm72 <= sx;
when "01110011" => sim_spm73 <= sx;
when "01110100" => sim_spm74 <= sx;
when "01110101" => sim_spm75 <= sx;
when "01110110" => sim_spm76 <= sx;
when "01110111" => sim_spm77 <= sx;
when "01111000" => sim_spm78 <= sx;
when "01111001" => sim_spm79 <= sx;
when "01111010" => sim_spm7A <= sx;
when "01111011" => sim_spm7B <= sx;
when "01111100" => sim_spm7C <= sx;
when "01111101" => sim_spm7D <= sx;
when "01111110" => sim_spm7E <= sx;
when "01111111" => sim_spm7F <= sx;
when "10000000" => sim_spm80 <= sx;
when "10000001" => sim_spm81 <= sx;
when "10000010" => sim_spm82 <= sx;
when "10000011" => sim_spm83 <= sx;
when "10000100" => sim_spm84 <= sx;
when "10000101" => sim_spm85 <= sx;
when "10000110" => sim_spm86 <= sx;
when "10000111" => sim_spm87 <= sx;
when "10001000" => sim_spm88 <= sx;
when "10001001" => sim_spm89 <= sx;
when "10001010" => sim_spm8A <= sx;
when "10001011" => sim_spm8B <= sx;
when "10001100" => sim_spm8C <= sx;
when "10001101" => sim_spm8D <= sx;
when "10001110" => sim_spm8E <= sx;
when "10001111" => sim_spm8F <= sx;
when "10010000" => sim_spm90 <= sx;
when "10010001" => sim_spm91 <= sx;
when "10010010" => sim_spm92 <= sx;
when "10010011" => sim_spm93 <= sx;
when "10010100" => sim_spm94 <= sx;
when "10010101" => sim_spm95 <= sx;
when "10010110" => sim_spm96 <= sx;
when "10010111" => sim_spm97 <= sx;
when "10011000" => sim_spm98 <= sx;
when "10011001" => sim_spm99 <= sx;
when "10011010" => sim_spm9A <= sx;
when "10011011" => sim_spm9B <= sx;
when "10011100" => sim_spm9C <= sx;
when "10011101" => sim_spm9D <= sx;
when "10011110" => sim_spm9E <= sx;
when "10011111" => sim_spm9F <= sx;
when "10100000" => sim_spma0 <= sx;
when "10100001" => sim_spmA1 <= sx;
when "10100010" => sim_spmA2 <= sx;
when "10100011" => sim_spmA3 <= sx;
when "10100100" => sim_spmA4 <= sx;
when "10100101" => sim_spmA5 <= sx;
when "10100110" => sim_spmA6 <= sx;
when "10100111" => sim_spmA7 <= sx;
when "10101000" => sim_spmA8 <= sx;
when "10101001" => sim_spmA9 <= sx;
when "10101010" => sim_spmAA <= sx;
when "10101011" => sim_spmAB <= sx;
when "10101100" => sim_spmAC <= sx;
when "10101101" => sim_spmAD <= sx;
when "10101110" => sim_spmAE <= sx;
when "10101111" => sim_spmAF <= sx;
when "10110000" => sim_spmB0 <= sx;
when "10110001" => sim_spmB1 <= sx;
when "10110010" => sim_spmB2 <= sx;
when "10110011" => sim_spmB3 <= sx;
when "10110100" => sim_spmB4 <= sx;
when "10110101" => sim_spmB5 <= sx;
when "10110110" => sim_spmB6 <= sx;
when "10110111" => sim_spmB7 <= sx;
when "10111000" => sim_spmB8 <= sx;
when "10111001" => sim_spmB9 <= sx;
when "10111010" => sim_spmBA <= sx;
when "10111011" => sim_spmBB <= sx;
when "10111100" => sim_spmBC <= sx;
when "10111101" => sim_spmBD <= sx;
when "10111110" => sim_spmBE <= sx;
when "10111111" => sim_spmBF <= sx;
when "11000000" => sim_spmC0 <= sx;
when "11000001" => sim_spmC1 <= sx;
when "11000010" => sim_spmC2 <= sx;
when "11000011" => sim_spmC3 <= sx;
when "11000100" => sim_spmC4 <= sx;
when "11000101" => sim_spmC5 <= sx;
when "11000110" => sim_spmC6 <= sx;
when "11000111" => sim_spmC7 <= sx;
when "11001000" => sim_spmC8 <= sx;
when "11001001" => sim_spmC9 <= sx;
when "11001010" => sim_spmCA <= sx;
when "11001011" => sim_spmCB <= sx;
when "11001100" => sim_spmCC <= sx;
when "11001101" => sim_spmCD <= sx;
when "11001110" => sim_spmCE <= sx;
when "11001111" => sim_spmCF <= sx;
when "11010000" => sim_spmD0 <= sx;
when "11010001" => sim_spmD1 <= sx;
when "11010010" => sim_spmD2 <= sx;
when "11010011" => sim_spmD3 <= sx;
when "11010100" => sim_spmD4 <= sx;
when "11010101" => sim_spmD5 <= sx;
when "11010110" => sim_spmD6 <= sx;
when "11010111" => sim_spmD7 <= sx;
when "11011000" => sim_spmD8 <= sx;
when "11011001" => sim_spmD9 <= sx;
when "11011010" => sim_spmDA <= sx;
when "11011011" => sim_spmDB <= sx;
when "11011100" => sim_spmDC <= sx;
when "11011101" => sim_spmDD <= sx;
when "11011110" => sim_spmDE <= sx;
when "11011111" => sim_spmDF <= sx;
when "11100000" => sim_spmE0 <= sx;
when "11100001" => sim_spmE1 <= sx;
when "11100010" => sim_spmE2 <= sx;
when "11100011" => sim_spmE3 <= sx;
when "11100100" => sim_spmE4 <= sx;
when "11100101" => sim_spmE5 <= sx;
when "11100110" => sim_spmE6 <= sx;
when "11100111" => sim_spmE7 <= sx;
when "11101000" => sim_spmE8 <= sx;
when "11101001" => sim_spmE9 <= sx;
when "11101010" => sim_spmEA <= sx;
when "11101011" => sim_spmEB <= sx;
when "11101100" => sim_spmEC <= sx;
when "11101101" => sim_spmED <= sx;
when "11101110" => sim_spmEE <= sx;
when "11101111" => sim_spmEF <= sx;
when "11110000" => sim_spmF0 <= sx;
when "11110001" => sim_spmF1 <= sx;
when "11110010" => sim_spmF2 <= sx;
when "11110011" => sim_spmF3 <= sx;
when "11110100" => sim_spmF4 <= sx;
when "11110101" => sim_spmF5 <= sx;
when "11110110" => sim_spmF6 <= sx;
when "11110111" => sim_spmF7 <= sx;
when "11111000" => sim_spmF8 <= sx;
when "11111001" => sim_spmF9 <= sx;
when "11111010" => sim_spmFA <= sx;
when "11111011" => sim_spmFB <= sx;
when "11111100" => sim_spmFC <= sx;
when "11111101" => sim_spmFD <= sx;
when "11111110" => sim_spmFE <= sx;
when "11111111" => sim_spmFF <= sx;
when others => null;
end case;
end if;
end if;
--
-- Assignment of internal register variables to active registers
--
if bank = '0' then
kcpsm6_status(1 to 2) <= "A,";
sim_s0 <= bank_a_s0;
sim_s1 <= bank_a_s1;
sim_s2 <= bank_a_s2;
sim_s3 <= bank_a_s3;
sim_s4 <= bank_a_s4;
sim_s5 <= bank_a_s5;
sim_s6 <= bank_a_s6;
sim_s7 <= bank_a_s7;
sim_s8 <= bank_a_s8;
sim_s9 <= bank_a_s9;
sim_sA <= bank_a_sA;
sim_sB <= bank_a_sB;
sim_sC <= bank_a_sC;
sim_sD <= bank_a_sD;
sim_sE <= bank_a_sE;
sim_sF <= bank_a_sF;
else
kcpsm6_status(1 to 2) <= "B,";
sim_s0 <= bank_b_s0;
sim_s1 <= bank_b_s1;
sim_s2 <= bank_b_s2;
sim_s3 <= bank_b_s3;
sim_s4 <= bank_b_s4;
sim_s5 <= bank_b_s5;
sim_s6 <= bank_b_s6;
sim_s7 <= bank_b_s7;
sim_s8 <= bank_b_s8;
sim_s9 <= bank_b_s9;
sim_sA <= bank_b_sA;
sim_sB <= bank_b_sB;
sim_sC <= bank_b_sC;
sim_sD <= bank_b_sD;
sim_sE <= bank_b_sE;
sim_sF <= bank_b_sF;
end if;
--
end process simulation;
--synthesis translate on
--
-- **************************
-- * End of simulation code *
-- **************************
--
--
-------------------------------------------------------------------------------------------
--
end low_level_definition;
--
-------------------------------------------------------------------------------------------
--
-- END OF FILE kcpsm6.vhd
--
-------------------------------------------------------------------------------------------
| lgpl-3.0 | df18603089010ce67d85ac49df751bec | 0.498501 | 3.605779 | false | false | false | false |
pmassolino/hw-goppa-mceliece | mceliece/util/ram_double_multiple_access_file.vhd | 1 | 5,611 | ----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: RAM_double_multiple_access
-- Module Name: RAM_double_multiple_access_file
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Circuit to simulate the behavioral of multiple memory RAM that shares the same content.
-- It is useful when you want to access more than one location at the same time, and
-- the locations for each access can be anywhere in the memory, where in banks in most
-- time is one address after another.
-- It can be seen as one single with multiple I/O operating at the same time.
-- In this double version it is possible to read and write at same cycle.
--
-- The circuits parameters
--
-- number_of_memories :
--
-- The total number of memories or the total number of I/O's applied.
--
-- ram_address_size :
--
-- Address size of the RAM used on the circuit.
--
-- ram_word_size :
--
-- The size of internal word of the RAM.
--
-- file_ram_word_size :
--
-- The size of the word used in the file to be loaded on the RAM.(ARCH: FILE_LOAD)
--
-- load_file_name :
--
-- The name of file to be loaded.(ARCH: FILE_LOAD)
--
-- dump_file_name :
--
-- The name of the file to be used to dump the memory.(ARCH: FILE_LOAD)
--
-- Dependencies:
-- VHDL-93
--
-- IEEE.NUMERIC_STD.ALL;
-- IEEE.STD_LOGIC_TEXTIO.ALL;
-- STD.TEXTIO.ALL;
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
architecture file_load of ram_double_multiple_access is
type ramtype is array(0 to (2**ram_address_size - 1)) of std_logic_vector((ram_word_size - 1) downto 0);
pure function load_ram (ram_file_name : in string) return ramtype is
FILE ram_file : text is in ram_file_name;
variable line_n : line;
variable memory_ram : ramtype;
variable file_read_buffer : std_logic_vector((file_ram_word_size - 1) downto 0);
variable file_buffer_amount : integer;
variable ram_buffer_amount : integer;
begin
file_buffer_amount := file_ram_word_size;
for I in ramtype'range loop
ram_buffer_amount := 0;
if (not endfile(ram_file) or (file_buffer_amount /= file_ram_word_size)) then
while ram_buffer_amount /= ram_word_size loop
if file_buffer_amount = file_ram_word_size then
if (not endfile(ram_file)) then
readline (ram_file, line_n);
read (line_n, file_read_buffer);
else
file_read_buffer := (others => '0');
end if;
file_buffer_amount := 0;
end if;
memory_ram(I)(ram_buffer_amount) := file_read_buffer(file_buffer_amount);
ram_buffer_amount := ram_buffer_amount + 1;
file_buffer_amount := file_buffer_amount + 1;
end loop;
else
memory_ram(I) := (others => '0');
end if;
end loop;
return memory_ram;
end function;
procedure dump_ram (ram_file_name : in string; memory_ram : in ramtype) is
FILE ram_file : text is out ram_file_name;
variable line_n : line;
begin
for I in ramtype'range loop
write (line_n, memory_ram(I));
writeline (ram_file, line_n);
end loop;
end procedure;
signal memory_ram : ramtype := load_ram(load_file_name);
begin
process (clk)
begin
if clk'event and clk = '1' then
if rst = '1' then
memory_ram <= load_ram(load_file_name);
end if;
if dump = '1' then
dump_ram(dump_file_name, memory_ram);
end if;
if rw_a = '1' then
for index in 0 to (number_of_memories - 1) loop
memory_ram(to_integer(unsigned(address_a(((ram_address_size)*(index + 1) - 1) downto ((ram_address_size)*index))))) <= data_in_a(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index));
end loop;
end if;
if rw_b = '1' then
for index in 0 to (number_of_memories - 1) loop
memory_ram(to_integer(unsigned(address_b(((ram_address_size)*(index + 1) - 1) downto ((ram_address_size)*index))))) <= data_in_b(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index));
end loop;
end if;
for index in 0 to (number_of_memories - 1) loop
data_out_a(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index)) <= memory_ram(to_integer(unsigned(address_a(((ram_address_size)*(index + 1) - 1) downto ((ram_address_size)*index)))));
data_out_b(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index)) <= memory_ram(to_integer(unsigned(address_b(((ram_address_size)*(index + 1) - 1) downto ((ram_address_size)*index)))));
end loop;
end if;
end process;
end file_load;
| bsd-2-clause | 5eff1bec683f2b608822aebe5611ca53 | 0.529317 | 3.796346 | false | false | false | false |
Xero-Hige/LuGus-VHDL | TPS-2016/tps-Gaston/bcd_1_counter.vhd | 1 | 1,176 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bcd_1_counter is
generic (
COUNTERS:natural := 4;
);
port (
clk_in: in std_logic;
rst_in: in std_logic;
bcd1_out: out std_logic_vector(3 downto 0);
clk_led_output: out std_logic_vector(7 downto 0)
);
end;
architecture tp1_arq of tp1 is
component generic_counter is
generic (
BITS:natural := 4;
MAX_COUNT:natural := 15
);
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
counter_out: out std_logic_vector(BITS-1 downto 0);
carry_out: out std_logic
);
end;
begin
counters : for i in 0 to N-1 generate
counter_outs: if i<3 generate
counter_out: generic_counter
port map(
ck => clk ,
rst => rst,
d => carry_out(i-1),
q => d (i +1)
);
end generate counter_outs;
counter_outs: if i>3 generate
counter_out: generic_counter
port map(
ck => clk ,
rst => rst,
d => carry_out(i-1),
q => d (i +1)
);
end generate counter_outs;
end generate counters;
end; | gpl-3.0 | 270896226ba89b6614acd17fb184567a | 0.551871 | 3.03876 | false | false | false | false |
pmassolino/hw-goppa-mceliece | mceliece/util/synth_double_ram.vhd | 1 | 2,857 | ----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Synth Double RAM
-- Module Name: Synth Double RAM
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Circuit to simulate the behavior of a double synthesizable RAM.
--
-- The circuits parameters
--
-- ram_address_size :
--
-- Address size of the synthesizable RAM used on the circuit.
--
-- ram_word_size :
--
-- The size of internal word on the synthesizable RAM.
--
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD.ALL;
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity synth_double_ram is
Generic (
ram_address_size : integer;
ram_word_size : integer
);
Port (
data_in_a : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_in_b : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
rw_a : in STD_LOGIC;
rw_b : in STD_LOGIC;
clk : in STD_LOGIC;
address_a : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
address_b : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
data_out_a : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out_b : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0)
);
end synth_double_ram;
architecture Behavioral of synth_double_ram is
type ramtype is array(0 to (2**ram_address_size - 1)) of std_logic_vector((ram_word_size - 1) downto 0);
shared variable memory_ram : ramtype;
begin
process (clk)
begin
if clk'event and clk = '1' then
if rw_a = '1' then
memory_ram(to_integer(unsigned(address_a))) := data_in_a((ram_word_size - 1) downto (0));
end if;
data_out_a((ram_word_size - 1) downto (0)) <= memory_ram(to_integer(unsigned(address_a)));
end if;
end process;
process (clk)
begin
if clk'event and clk = '1' then
if rw_b = '1' then
memory_ram(to_integer(unsigned(address_b))) := data_in_b((ram_word_size - 1) downto (0));
end if;
data_out_b((ram_word_size - 1) downto (0)) <= memory_ram(to_integer(unsigned(address_b)));
end if;
end process;
end Behavioral; | bsd-2-clause | 3e9b8f1c4752bb0f01b404c14b2993ee | 0.510676 | 3.700777 | false | false | false | false |
KenKeeley/My68k-system | CircuitBoards/MainBoard/DRAMControllerCPLD/MUX.vhd | 1 | 1,232 | ----------------------------------------------------------------------------------------------------
--
-- FileName: MUX.vhd
-- Description: MainBoard DRAM Controller CPLD Multiplexer.
--
----------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY Multiplexer IS
PORT
(
Address : IN STD_LOGIC_VECTOR (23 DOWNTO 0); -- Address Bus
nRAS : IN STD_LOGIC_VECTOR (7 DOWNTO 0); -- Row Address Select
MA : OUT STD_LOGIC_VECTOR (11 DOWNTO 0) -- Multiplexed Address Bus
);
END Multiplexer;
ARCHITECTURE Behavioral OF Multiplexer IS
SIGNAL MUX : std_logic; -- The logical OR of the RAS signals
SIGNAL MXS : std_logic; -- delayed MUX
BEGIN
-- Asserted when any RAS is asserted
MUX <= '0' WHEN nRAS = "11111111" ELSE '1';
-- This is just a delayed version of MUX.
MXS <= MUX;
-- column address during RAS active
MA(11) <= Address(22) WHEN MXS = '1' ELSE Address(23);
MA(10 DOWNTO 0) <= Address(10 DOWNTO 0) WHEN MXS = '1' ELSE Address(21 DOWNTO 11);
END Behavioral; | gpl-3.0 | 011c14b296acd6a31604ac168448661c | 0.496753 | 4.684411 | false | false | false | false |
rodrigoazs/-7-5-Reed-Solomon | code/reedsolomon_encoder.vhd | 1 | 2,030 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Author: R. Azevedo Santos ([email protected])
-- Co-Author: Joao Lucas Magalini Zago
--
-- VHDL Implementation of (7,5) Reed Solomon
-- Course: Information Theory - 2014 - Ohio Northern University
entity ReedSolomonEncoder is
Port ( Clock : in std_logic;
Count7 : in std_logic;
Qs0 : in std_logic_vector(2 downto 0);
Qp : out std_logic_vector(2 downto 0));
end ReedSolomonEncoder;
architecture Behavioral of ReedSolomonEncoder is
component flipflop is
Port ( D: in std_logic_vector(2 downto 0) ;
Clock : in std_logic;
Reset : in std_logic;
Q : out std_logic_vector(2 downto 0)) ;
end component;
component AdderXor is
Port ( a: in std_logic_vector(2 downto 0) ;
b: in std_logic_vector(2 downto 0);
c: out std_logic_vector(2 downto 0)) ;
end component;
component Mult is
port( uncoded_a, uncoded_b:
in std_logic_vector(2 downto 0);
uncoded_multab: out std_logic_vector(2 downto 0)
);
end component;
component mux6 IS
Port (y1: in std_logic_vector(2 downto 0 ) ;
y0: in std_logic_vector(2 downto 0 ) ;
s: in std_logic ;
f: out std_logic_vector(2 downto 0 ));
end component;
signal alpha3 : std_logic_vector(2 downto 0);
signal alpha4 : std_logic_vector(2 downto 0);
signal D1 : std_logic_vector(2 downto 0);
signal D2 : std_logic_vector(2 downto 0);
signal Q1 : std_logic_vector(2 downto 0);
signal Q2 : std_logic_vector(2 downto 0);
signal C0 : std_logic_vector(2 downto 0);
signal multa1 : std_logic_vector(2 downto 0);
signal multa2 : std_logic_vector(2 downto 0);
begin
alpha3(0) <= '0'; alpha3(1) <= '1'; alpha3(2) <= '1';
alpha4(0) <= '1'; alpha4(1) <= '1'; alpha4(2) <= '0';
ff1 : flipflop port map (D1,Clock,Count7,Q1);
ff2 : flipflop port map (D2,Clock,Count7,Q2);
add1 : AdderXor port map (Q2, Qs0, C0);
mult1 : Mult port map (C0, alpha4, multa1);
mult2 : Mult port map (C0, alpha3, multa2);
add2 : AdderXor port map(Q1, multa1, D2);
D1 <= multa2;
Qp <= Q2;
end Behavioral;
| mit | 2dc96de57f848645f3c2fb269538dc06 | 0.686207 | 2.739541 | false | false | false | false |
Xero-Hige/LuGus-VHDL | TPS-2016/tps-Gaston/TP1-Contador/generic_enabler.vhd | 1 | 846 | library ieee;
use ieee.std_logic_1164.all;
entity generic_enabler is
generic(
PERIOD:natural := 1000000 --1MHz
);
port(
clk: in std_logic;
rst: in std_logic;
enabler_out: out std_logic
);
end;
architecture generic_enabler_arq of generic_enabler is
component generic_counter is
generic (
BITS:natural := 4;
MAX_COUNT:natural := 15
);
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
counter_out: out std_logic_vector(BITS-1 downto 0);
carry_out: out std_logic
);
end component;
begin
generic_counterMap: generic_counter
generic map (32,PERIOD) --32 bits son suficientes para hasta 4 GHz
port map(
clk => clk,
rst => rst,
ena => '1',
carry_out => enabler_out
); --El count_dummy esta conectado siempre a tierra.
end;
| gpl-3.0 | e59b0af69c4fe2dada824b4da6e8f348 | 0.62766 | 3.054152 | false | false | false | false |
Xero-Hige/LuGus-VHDL | TP3/addition/result_complementer/result_complementer.vhd | 1 | 1,509 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--This component takes the result of the addition of 2 mantissas and complements it if necessary.
entity result_complementer is
generic(
BITS : natural := 16
);
port(
in_result : in std_logic_vector(BITS - 1 downto 0) := (others => '0');
sign_1_in : in std_logic := '0';
sign_2_in : in std_logic := '0';
result_cout : in std_logic := '0';
out_result : out std_logic_vector(BITS - 1 downto 0) := (others => '0')
);
end result_complementer;
architecture result_complementer_arq of result_complementer is
signal complemented_result : std_logic_vector(BITS - 1 downto 0) := (others => '0');
component base_complementer is
generic(
TOTAL_BITS : natural := 16
);
port(
number_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
number_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0')
);
end component;
for base_complementer_0 : base_complementer use entity work.base_complementer;
begin
base_complementer_0 : base_complementer
generic map(TOTAL_BITS => BITS)
port map (
number_in => in_result,
number_out => complemented_result
);
process(in_result, sign_1_in, sign_2_in, result_cout, complemented_result) is
begin
if((sign_1_in /= sign_2_in) and (result_cout = '0') and (in_result(BITS - 1) = '1')) then
out_result <= complemented_result;
else
out_result <= in_result;
end if;
end process;
end architecture;
| gpl-3.0 | db2569ba25e855e4e4f51f5280b05ddd | 0.659377 | 3.098563 | false | false | false | false |
Xero-Hige/LuGus-VHDL | TP3/addition/normalizer/normalizer_tb.vhd | 1 | 2,878 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity normalizer_tb is
end entity;
architecture normalizer_tb_arq of normalizer_tb is
signal man_in : std_logic_vector(16 downto 0) := (others => '0');
signal exp_in : std_logic_vector(5 downto 0) := (others => '0');
signal cin : std_logic := '0';
signal diff_signs : std_logic := '0';
signal rounding_bit : std_logic := '0';
signal man_out : std_logic_vector(15 downto 0) := (others => '0');
signal exp_out : std_logic_vector(5 downto 0) := (others => '0');
component normalizer is
generic(
TOTAL_BITS : natural := 23;
EXP_BITS : natural := 6
);
port(
man_in : in std_logic_vector((TOTAL_BITS - EXP_BITS - 1) downto 0);
exp_in : in std_logic_vector(EXP_BITS - 1 downto 0);
cin : in std_logic; --To check if the sum had a carry
diff_signs : in std_logic;
rounding_bit : in std_logic;
man_out : out std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0);
exp_out : out std_logic_vector(EXP_BITS - 1 downto 0)
);
end component;
for normalizer_0 : normalizer use entity work.normalizer;
begin
normalizer_0 : normalizer
generic map(TOTAL_BITS => 23, EXP_BITS => 6)
port map(
man_in => man_in,
exp_in => exp_in,
cin => cin,
diff_signs => diff_signs,
rounding_bit => rounding_bit,
man_out => man_out,
exp_out => exp_out
);
process
type pattern_type is record
mi : std_logic_vector(16 downto 0);
ei : std_logic_vector(5 downto 0);
ci : std_logic;
ds : std_logic;
rb : std_logic;
mo : std_logic_vector(15 downto 0);
eo : std_logic_vector(5 downto 0);
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array := (
("00000000000000000","000000",'0','1','0',"0000000000000000","000000"),
("00000000000000000","111111",'0','1','0',"0000000000000000","000000"),
("00000000000000001","011111",'0','1','0',"0000000000000000","001111"),
("01000000000000000","111111",'1','1','0',"0000000000000000","111110"),
("00000111000000000","000101",'0','1','0',"0000000000000000","000000"),
("01110001001010010","011101",'0','0','0',"1100010010100100","011100"),
("01110001001010010","011101",'0','0','1',"1100010010100101","011100")
);
begin
for i in patterns'range loop
-- Set the inputs.
man_in <= patterns(i).mi;
exp_in <= patterns(i).ei;
cin <= patterns(i).ci;
diff_signs <= patterns(i).ds;
rounding_bit <= patterns(i).rb;
wait for 1 ns;
assert patterns(i).mo = man_out report "BAD MANTISSA, GOT: " & integer'image(to_integer(unsigned(man_out)));
assert patterns(i).eo = exp_out report "BAD EXPONENT, GOT: " & integer'image(to_integer(unsigned(exp_out)));
-- Check the outputs.
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
| gpl-3.0 | 1aa52ab925735a38512a75d2813c58ba | 0.640723 | 3.071505 | false | false | false | false |
Xero-Hige/LuGus-VHDL | TP4/enable_generator/enable_generator.vhd | 1 | 1,465 | library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
entity enable_generator is
generic(CYCLE_COUNT: integer := 10; PASSIVE_CYCLES: integer := 0; ACTIVE_CYCLES: integer := 0);
port(
rst : in std_logic := '0';
clk: in std_logic := '0';
enable_in: in std_logic := '0';
enable_out : out std_logic := '0'
);
end entity;
architecture enable_generator_arq of enable_generator is
signal passive : integer := 0;
signal active : integer := 0;
signal counted : integer := 0;
begin
process(clk, rst)
variable passive_count : integer := 0;
variable active_count : integer := 0;
variable counted_cycles : integer := 0;
begin
if(rst = '1') then
passive_count := 0;
active_count := 0;
counted_cycles := 0;
enable_out <= '0';
elsif(enable_in = '1') then
if(rising_edge(clk)) then
if(counted_cycles = CYCLE_COUNT - 1) then
if(passive_count = PASSIVE_CYCLES - 1) then
if(active_count = ACTIVE_CYCLES) then
active_count := 0;
passive_count := 0;
else
active_count := active_count + 1;
enable_out <= '1';
end if;
else
passive_count := passive_count + 1;
enable_out <= '0';
end if;
counted_cycles := 0;
else
counted_cycles := counted_cycles + 1;
enable_out <= '0';
end if;
end if;
passive <= passive_count;
active <= active_count;
counted <= counted_cycles;
end if;
end process;
end enable_generator_arq;
| gpl-3.0 | 840617ffe37e27ee295b00108c34a713 | 0.612287 | 3.058455 | false | false | false | false |
hitomi2500/wasca | obsolete/fpga_firmware_V2/ip_repo/ABus2AXI4Lite/hdl/ABus2AXI4Lite_tb.vhd | 2 | 19,498 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:46:37 02/13/2017
-- Design Name:
-- Module Name: C:/Xilinx/__testbecher/testbencher/a_tb.vhd
-- Project Name: testbencher
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ABus2AXI4Lite
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY a_tb IS
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Master Bus Interface M00_AXI
C_MASTER_AXI_TARGET_SLAVE_BASE_ADDR : std_logic_vector := x"00000000";
C_MASTER_AXI_ADDR_WIDTH : integer := 32;
C_MASTER_AXI_DATA_WIDTH : integer := 32;
C_SLAVE_AXI_ADDR_WIDTH : integer := 32;
C_SLAVE_AXI_DATA_WIDTH : integer := 32;
C_FILESYS_AXI_ADDR_WIDTH : integer := 32;
C_FILESYS_AXI_DATA_WIDTH : integer := 32
);
END a_tb;
ARCHITECTURE behavior OF a_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ABus2AXI4Lite
PORT(
-- abus ports
abus_address : in std_logic_vector(25 downto 0) := (others => '0'); -- abus.address
abus_data_in : in std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_data_out : out std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_data_direction : out std_logic := '0'; -- .direction
abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
abus_read : in std_logic := '0'; -- .read
abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
abus_wait : out std_logic := '1'; -- .waitrequest
abus_wait_direction : out std_logic := '0'; -- .direction
abus_irq : out std_logic := '0'; -- .interrupt
abus_irq_direction : out std_logic := '0'; -- .direction
abus_reset : in std_logic := '0'; -- .saturn_reset
-- Ports of Axi Master Bus Interface
master_axi_aclk : in std_logic;
master_axi_aresetn : in std_logic;
master_axi_awaddr : out std_logic_vector(C_MASTER_AXI_ADDR_WIDTH-1 downto 0);
master_axi_awprot : out std_logic_vector(2 downto 0);
master_axi_awvalid : out std_logic;
master_axi_awready : in std_logic;
master_axi_wdata : out std_logic_vector(C_MASTER_AXI_DATA_WIDTH-1 downto 0);
master_axi_wstrb : out std_logic_vector(C_MASTER_AXI_DATA_WIDTH/8-1 downto 0);
master_axi_wvalid : out std_logic;
master_axi_wready : in std_logic;
master_axi_bresp : in std_logic_vector(1 downto 0);
master_axi_bvalid : in std_logic;
master_axi_bready : out std_logic;
master_axi_araddr : out std_logic_vector(C_MASTER_AXI_ADDR_WIDTH-1 downto 0);
master_axi_arprot : out std_logic_vector(2 downto 0);
master_axi_arvalid : out std_logic;
master_axi_arready : in std_logic;
master_axi_rdata : in std_logic_vector(C_MASTER_AXI_DATA_WIDTH-1 downto 0);
master_axi_rresp : in std_logic_vector(1 downto 0);
master_axi_rvalid : in std_logic;
master_axi_rready : out std_logic;
-- Ports of Slave Bus Interface
slave_axi_aclk : in std_logic;
slave_axi_aresetn : in std_logic;
slave_axi_awaddr : in std_logic_vector(C_SLAVE_AXI_ADDR_WIDTH-1 downto 0);
slave_axi_awprot : in std_logic_vector(2 downto 0);
slave_axi_awvalid : in std_logic;
slave_axi_awready : out std_logic;
slave_axi_wdata : in std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
slave_axi_wstrb : in std_logic_vector(C_SLAVE_AXI_DATA_WIDTH/8-1 downto 0);
slave_axi_wvalid : in std_logic;
slave_axi_wready : out std_logic;
slave_axi_bresp : out std_logic_vector(1 downto 0);
slave_axi_bvalid : out std_logic;
slave_axi_bready : in std_logic;
slave_axi_araddr : in std_logic_vector(C_SLAVE_AXI_ADDR_WIDTH-1 downto 0);
slave_axi_arprot : in std_logic_vector(2 downto 0);
slave_axi_arvalid : in std_logic;
slave_axi_arready : out std_logic;
slave_axi_rdata : out std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
slave_axi_rresp : out std_logic_vector(1 downto 0);
slave_axi_rvalid : out std_logic;
slave_axi_rready : in std_logic
);
END COMPONENT;
COMPONENT test_mem
PORT(
s_aclk : IN std_logic;
s_aresetn : IN std_logic;
s_axi_awaddr : in std_logic_vector(31 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wstrb : in std_logic_vector(3 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(31 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic
);
END COMPONENT;
--Inputs
signal abus_address : std_logic_vector(25 downto 0) := (others => '0');
signal abus_data_in : std_logic_vector(15 downto 0) := (others => '0');
signal abus_chipselect : std_logic_vector(2 downto 0) := (others => '0');
signal abus_read : std_logic := '0';
signal abus_write : std_logic_vector(1 downto 0) := (others => '0');
signal abus_reset : std_logic := '0';
signal master_axi_init_axi_txn : std_logic := '0';
signal master_axi_aclk : std_logic := '0';
signal master_axi_aresetn : std_logic := '0';
signal master_axi_awready : std_logic := '0';
signal master_axi_wready : std_logic := '0';
signal master_axi_bresp : std_logic_vector(1 downto 0) := (others => '0');
signal master_axi_bvalid : std_logic := '0';
signal master_axi_arready : std_logic := '0';
signal master_axi_rdata : std_logic_vector(31 downto 0) := (others => '0');
signal master_axi_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal master_axi_rvalid : std_logic := '0';
signal slave_axi_awaddr : std_logic_vector(31 downto 0) := (others => '0');
signal slave_axi_awprot : std_logic_vector(2 downto 0) := (others => '0');
signal slave_axi_awvalid : std_logic := '0';
signal slave_axi_wdata : std_logic_vector(31 downto 0) := (others => '0');
signal slave_axi_wstrb : std_logic_vector(3 downto 0) := (others => '0');
signal slave_axi_wvalid : std_logic := '0';
signal slave_axi_bready : std_logic := '0';
signal slave_axi_araddr : std_logic_vector(31 downto 0) := (others => '0');
signal slave_axi_arprot : std_logic_vector(2 downto 0) := (others => '0');
signal slave_axi_arvalid : std_logic := '0';
signal slave_axi_rready : std_logic := '0';
--Outputs
signal abus_data_out : std_logic_vector(15 downto 0);
signal abus_data_direction : std_logic := '0';
signal abus_wait : std_logic := '0';
signal abus_wait_direction : std_logic := '0';
signal abus_irq : std_logic := '0';
signal abus_irq_direction : std_logic := '0';
signal master_axi_error : std_logic := '0';
signal master_axi_txn_done : std_logic := '0';
signal master_axi_awaddr : std_logic_vector(31 downto 0) := (others => '0');
signal master_axi_awprot : std_logic_vector(2 downto 0) := (others => '0');
signal master_axi_awvalid : std_logic := '0';
signal master_axi_wdata : std_logic_vector(31 downto 0) := (others => '0');
signal master_axi_wstrb : std_logic_vector(3 downto 0) := (others => '0');
signal master_axi_wvalid : std_logic := '0';
signal master_axi_bready : std_logic := '0';
signal master_axi_araddr : std_logic_vector(31 downto 0) := (others => '0');
signal master_axi_arprot : std_logic_vector(2 downto 0) := (others => '0');
signal master_axi_arvalid : std_logic := '0';
signal master_axi_rready : std_logic := '0';
signal slave_axi_aclk : std_logic := '0';
signal slave_axi_aresetn : std_logic := '0';
signal slave_axi_awready : std_logic := '0';
signal slave_axi_wready : std_logic := '0';
signal slave_axi_bresp : std_logic_vector(1 downto 0) := (others => '0');
signal slave_axi_bvalid : std_logic := '0';
signal slave_axi_arready : std_logic := '0';
signal slave_axi_rdata : std_logic_vector(31 downto 0) := (others => '0');
signal slave_axi_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal slave_axi_rvalid : std_logic := '0';
-- Clock period definitions
constant master_axi_aclk_period : time := 10 ns;
procedure abus_write_proc (addr : in std_logic_vector(25 downto 0);
data : in std_logic_vector(15 downto 0);
chipselect : in std_logic_vector(2 downto 0);
signal ABus_Ad : out std_logic_vector(25 downto 0);
signal ABus_Da : out std_logic_vector(15 downto 0);
signal ABus_CS : out std_logic_vector(2 downto 0);
signal ABus_Wr : out std_logic_vector(1 downto 0)
) is
begin
--set quantizer 25mhz
ABus_Ad <= addr;
ABus_Da <= data;
wait for 100ns;
ABus_CS <= chipselect;
wait for 100ns;
ABus_Wr <= "00";
wait for 1000ns;
ABus_Wr <= "11";
wait for 100ns;
ABus_CS <= "111";
ABus_Da <= (others => 'Z');
wait for 100ns;
end abus_write_proc;
procedure abus_read_proc (addr : in std_logic_vector(25 downto 0);
chipselect : in std_logic_vector(2 downto 0);
signal ABus_Ad : out std_logic_vector(25 downto 0);
signal ABus_CS : out std_logic_vector(2 downto 0);
signal ABus_Re : out std_logic
) is
begin
--set quantizer 25mhz
ABus_Ad <= addr;
wait for 100ns;
ABus_CS <= chipselect;
wait for 100ns;
ABus_Re <= '0';
wait for 1000ns;
ABus_Re <= '1';
wait for 100ns;
ABus_CS <= "111";
wait for 100ns;
end abus_read_proc;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ABus2AXI4Lite PORT MAP (
abus_address => abus_address,
abus_data_in => abus_data_in,
abus_data_out => abus_data_out,
abus_data_direction => abus_data_direction,
abus_chipselect => abus_chipselect,
abus_read => abus_read,
abus_write => abus_write,
abus_wait => abus_wait,
abus_wait_direction => abus_wait_direction,
abus_irq => abus_irq,
abus_irq_direction => abus_irq_direction,
abus_reset => abus_reset,
master_axi_aclk => master_axi_aclk,
master_axi_aresetn => master_axi_aresetn,
master_axi_awaddr => master_axi_awaddr,
master_axi_awprot => master_axi_awprot,
master_axi_awvalid => master_axi_awvalid,
master_axi_awready => master_axi_awready,
master_axi_wdata => master_axi_wdata,
master_axi_wstrb => master_axi_wstrb,
master_axi_wvalid => master_axi_wvalid,
master_axi_wready => master_axi_wready,
master_axi_bresp => master_axi_bresp,
master_axi_bvalid => master_axi_bvalid,
master_axi_bready => master_axi_bready,
master_axi_araddr => master_axi_araddr,
master_axi_arprot => master_axi_arprot,
master_axi_arvalid => master_axi_arvalid,
master_axi_arready => master_axi_arready,
master_axi_rdata => master_axi_rdata,
master_axi_rresp => master_axi_rresp,
master_axi_rvalid => master_axi_rvalid,
master_axi_rready => master_axi_rready,
slave_axi_aclk => slave_axi_aclk,
slave_axi_aresetn => slave_axi_aresetn,
slave_axi_awaddr => slave_axi_awaddr,
slave_axi_awprot => slave_axi_awprot,
slave_axi_awvalid => slave_axi_awvalid,
slave_axi_awready => slave_axi_awready,
slave_axi_wdata => slave_axi_wdata,
slave_axi_wstrb => slave_axi_wstrb,
slave_axi_wvalid => slave_axi_wvalid,
slave_axi_wready => slave_axi_wready,
slave_axi_bresp => slave_axi_bresp,
slave_axi_bvalid => slave_axi_bvalid,
slave_axi_bready => slave_axi_bready,
slave_axi_araddr => slave_axi_araddr,
slave_axi_arprot => slave_axi_arprot,
slave_axi_arvalid => slave_axi_arvalid,
slave_axi_arready => slave_axi_arready,
slave_axi_rdata => slave_axi_rdata,
slave_axi_rresp => slave_axi_rresp,
slave_axi_rvalid => slave_axi_rvalid,
slave_axi_rready => slave_axi_rready
);
das_mem: test_mem PORT MAP (
s_aclk => master_axi_aclk,
s_aresetn => master_axi_aresetn,
s_axi_awaddr => master_axi_awaddr,
s_axi_awvalid => master_axi_awvalid,
s_axi_awready => master_axi_awready,
s_axi_wdata => master_axi_wdata,
s_axi_wstrb => master_axi_wstrb,
s_axi_wvalid => master_axi_wvalid,
s_axi_wready => master_axi_wready,
s_axi_bresp => master_axi_bresp,
s_axi_bvalid => master_axi_bvalid,
s_axi_bready => master_axi_bready,
s_axi_araddr => master_axi_araddr,
s_axi_arvalid => master_axi_arvalid,
s_axi_arready => master_axi_arready,
s_axi_rdata => master_axi_rdata,
s_axi_rresp => master_axi_rresp,
s_axi_rvalid => master_axi_rvalid,
s_axi_rready => master_axi_rready
);
-- Clock process definitions
master_axi_aclk_process :process
begin
master_axi_aclk <= '0';
wait for master_axi_aclk_period/2;
master_axi_aclk <= '1';
wait for master_axi_aclk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
abus_write <= "11";
abus_read <= '1';
abus_chipselect <= "111";
master_axi_aresetn <= '0';
-- hold reset state for 100 ns.
wait for 100 ns;
wait for master_axi_aclk_period*10;
master_axi_aresetn <= '1';
-- insert stimulus here
--abus read transaction
wait for 1000 ns;
abus_write_proc("00"&X"000000",X"FADE","101",abus_address,abus_data_in,abus_chipselect,abus_write);
abus_write_proc("00"&X"000002",X"1193","101",abus_address,abus_data_in,abus_chipselect,abus_write);
abus_write_proc("00"&X"000004",X"0003","101",abus_address,abus_data_in,abus_chipselect,abus_write);
abus_write_proc("00"&X"000006",X"FACE","101",abus_address,abus_data_in,abus_chipselect,abus_write);
abus_read_proc("00"&X"000000","101",abus_address,abus_chipselect,abus_read);
abus_read_proc("00"&X"000002","101",abus_address,abus_chipselect,abus_read);
abus_read_proc("00"&X"000004","101",abus_address,abus_chipselect,abus_read);
abus_read_proc("00"&X"000006","101",abus_address,abus_chipselect,abus_read);
--wasca system regs write and read
wait for 1000 ns;
abus_write_proc("11"&X"FFFFF4",X"ACBD","110",abus_address,abus_data_in,abus_chipselect,abus_write); --mode
abus_read_proc("11"&X"FFFFF0","110",abus_address,abus_chipselect,abus_read);
abus_read_proc("11"&X"FFFFF2","110",abus_address,abus_chipselect,abus_read);
abus_read_proc("11"&X"FFFFF4","110",abus_address,abus_chipselect,abus_read);
abus_read_proc("11"&X"FFFFF8","110",abus_address,abus_chipselect,abus_read);
abus_read_proc("11"&X"FFFFFA","110",abus_address,abus_chipselect,abus_read);
abus_read_proc("11"&X"FFFFFC","110",abus_address,abus_chipselect,abus_read);
abus_read_proc("11"&X"FFFFFE","110",abus_address,abus_chipselect,abus_read);
--wasca filesystem regs write and read
wait for 1000 ns;
abus_write_proc("11"&X"FFEFF0",X"FADE","110",abus_address,abus_data_in,abus_chipselect,abus_write); --lock
abus_write_proc("11"&X"FFEFF2",X"0001","110",abus_address,abus_data_in,abus_chipselect,abus_write); --cmd
abus_read_proc("11"&X"FFFFF4","110",abus_address,abus_chipselect,abus_read);--status
abus_write_proc("11"&X"FFE000",X"DADA","110",abus_address,abus_data_in,abus_chipselect,abus_write); --data buf
abus_write_proc("11"&X"FFE002",X"DADA","110",abus_address,abus_data_in,abus_chipselect,abus_write); --data buf
abus_write_proc("11"&X"FFE7FC",X"DADA","110",abus_address,abus_data_in,abus_chipselect,abus_write); --data buf
abus_write_proc("11"&X"FFE7FE",X"DADA","110",abus_address,abus_data_in,abus_chipselect,abus_write); --data buf
abus_write_proc("11"&X"FFE800",X"CDCD","110",abus_address,abus_data_in,abus_chipselect,abus_write); --data buf
abus_write_proc("11"&X"FFE802",X"CDCD","110",abus_address,abus_data_in,abus_chipselect,abus_write); --data buf
abus_write_proc("11"&X"FFEFEC",X"CDCD","110",abus_address,abus_data_in,abus_chipselect,abus_write); --data buf
abus_write_proc("11"&X"FFEFEE",X"CDCD","110",abus_address,abus_data_in,abus_chipselect,abus_write); --data buf
abus_read_proc("11"&X"FFF000","110",abus_address,abus_chipselect,abus_read);
abus_read_proc("11"&X"FFF002","110",abus_address,abus_chipselect,abus_read);
abus_read_proc("11"&X"FFF7FC","110",abus_address,abus_chipselect,abus_read);
abus_read_proc("11"&X"FFF7FE","110",abus_address,abus_chipselect,abus_read);
abus_read_proc("11"&X"FFF800","110",abus_address,abus_chipselect,abus_read);
abus_read_proc("11"&X"FFF802","110",abus_address,abus_chipselect,abus_read);
abus_read_proc("11"&X"FFFFEC","110",abus_address,abus_chipselect,abus_read);
abus_read_proc("11"&X"FFFFEE","110",abus_address,abus_chipselect,abus_read);
wait;
end process;
END;
| gpl-2.0 | e91bef82a08c9a1a1da706d1b266cee9 | 0.58765 | 3.440014 | false | false | false | false |
Xero-Hige/LuGus-VHDL | TP3/addition/normalizer/normalizer.vhd | 1 | 2,383 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--This component normalizes the number so that it follows the specifications of a floating point representation
entity normalizer is
generic(
TOTAL_BITS : natural := 23;
EXP_BITS : natural := 6
);
port(
man_in : in std_logic_vector(TOTAL_BITS - EXP_BITS - 1 downto 0); --number enters in double precision
exp_in : in std_logic_vector(EXP_BITS - 1 downto 0);
cin : in std_logic; --To check if the sum had a carry
diff_signs : in std_logic;
rounding_bit : in std_logic;
man_out : out std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0);
exp_out : out std_logic_vector(EXP_BITS - 1 downto 0)
);
end normalizer;
architecture normalizer_arq of normalizer is
begin
process(man_in, exp_in, cin, diff_signs, rounding_bit) is
variable tmp_mantissa : std_logic_vector(TOTAL_BITS - EXP_BITS downto 0) := (others => '0');
variable tmp_exp : unsigned(EXP_BITS - 1 downto 0) := (others => '0');
variable zero_mant : std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0) := (others => '0');
variable all_ones_mant : std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0) := (others => '1');
variable max_exp : unsigned(EXP_BITS - 1 downto 0) := (others => '1');
variable internal_man_out : std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0) := (others => '0');
variable internal_exp_out : std_logic_vector(EXP_BITS - 1 downto 0) := (others => '0');
begin
if(cin = '1' and diff_signs = '0') then
internal_man_out := man_in(TOTAL_BITS - EXP_BITS - 1 downto 1);
internal_exp_out := std_logic_vector(unsigned(exp_in) + 1);
else
tmp_mantissa := man_in & rounding_bit;
tmp_exp := unsigned(exp_in);
while(tmp_mantissa(TOTAL_BITS - EXP_BITS) /= '1' and tmp_exp > 0) loop
tmp_mantissa := std_logic_vector(shift_left(unsigned(tmp_mantissa), 1));
tmp_exp := tmp_exp - 1;
end loop;
internal_man_out := tmp_mantissa((TOTAL_BITS - EXP_BITS - 1) downto 1);
internal_exp_out := std_logic_vector(tmp_exp);
end if;
tmp_exp := unsigned(internal_exp_out);
if(tmp_exp = 0) then
man_out <= zero_mant;
exp_out <= internal_exp_out;
elsif (tmp_exp = max_exp) then
man_out <= zero_mant;
exp_out <= std_logic_vector(max_exp);
else
man_out <= internal_man_out;
exp_out <= internal_exp_out;
end if;
end process;
end;
| gpl-3.0 | 40773a2bb76a3f5fe915b8301d07e79a | 0.65086 | 2.945612 | false | false | false | false |
pwuertz/digitizer2fw | src/rtl/ft2232fifo.vhd | 1 | 5,772 | -------------------------------------------------------------------------------
-- FT2232H Sync FIFO Interface
--
-- This component is designed to interface an FT2232H USB chip with two
-- dual-port FIFOs in first-word-fall-through (zero read latency) mode. The
-- FIFOs are used for buffering and (de)serializing data words and for
-- crossing the USB and FPGA clock domains.
--
-- Author: Peter Würtz, TU Kaiserslautern (2016)
-- Distributed under the terms of the GNU General Public License Version 3.
-- The full license is in the file COPYING.txt, distributed with this software.
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ft2232fifo is
port (
-- ftdi interface
usb_clk: in std_logic;
usb_oe_n: out std_logic;
usb_rd_n: out std_logic;
usb_wr_n: out std_logic;
usb_rxf_n: in std_logic;
usb_txe_n: in std_logic;
usb_d: inout std_logic_vector(7 downto 0);
-- application/fifo interface
rst: in std_logic;
fifo_in_wr_en: out std_logic;
fifo_in_full: in std_logic;
fifo_in_data: out std_logic_vector(7 downto 0);
fifo_out_rd_en: out std_logic;
fifo_out_empty: in std_logic;
fifo_out_data: in std_logic_vector(7 downto 0)
);
end ft2232fifo;
architecture ft2232fifo_arch of ft2232fifo is
signal usb_rd_en, usb_wr_en: std_logic;
signal sfifo_out_rd_en: std_logic;
-- data read registers
signal qdata_in: std_logic_vector(7 downto 0) := (others => '-');
signal qdata_in_valid: std_logic := '0';
-- data write registers
signal qdata_out: std_logic_vector(7 downto 0) := (others => '-');
signal qdata_out_valid: std_logic := '0';
-- state register
type state_t is (
s_reset, s_idle,
s_read_mode, s_write_mode,
s_switch_to_write1, s_switch_to_write2, s_switch_to_read
);
signal state, next_state: state_t;
begin
usb_rd_n <= not usb_rd_en;
usb_wr_n <= not usb_wr_en;
fifo_in_data <= qdata_in;
fifo_in_wr_en <= qdata_in_valid;
fifo_out_rd_en <= sfifo_out_rd_en;
sync_state: process(usb_clk)
begin
if rising_edge(usb_clk) then
if rst = '1' then
state <= s_reset;
else
state <= next_state;
end if;
end if;
end process;
sync_data_in: process(usb_clk)
begin
if rising_edge(usb_clk) then
if rst = '1' then
qdata_in_valid <= '0';
qdata_in <= (others => '-');
elsif (usb_rd_en = '1') and (usb_rxf_n = '0') then
-- new data word from usb
qdata_in_valid <= '1';
qdata_in <= usb_d;
elsif (qdata_in_valid = '1') and (fifo_in_full = '0') then
-- data word consumed by fifo and no new data from usb
qdata_in_valid <= '0';
qdata_in <= (others => '-');
end if;
end if;
end process;
sync_data_out: process(usb_clk)
begin
if rising_edge(usb_clk) then
if rst = '1' then
qdata_out_valid <= '0';
qdata_out <= (others => '-');
elsif (sfifo_out_rd_en = '1') and (fifo_out_empty = '0') then
-- new data word from fifo
qdata_out_valid <= '1';
qdata_out <= fifo_out_data;
elsif (usb_wr_en = '1') and (usb_txe_n = '0') then
-- data word consumed by usb and no new data from fifo
qdata_out_valid <= '0';
qdata_out <= (others => '-');
end if;
end if;
end process;
comb_state: process(state, usb_rxf_n, usb_txe_n, qdata_out, qdata_out_valid, fifo_in_full)
variable could_wr, could_rd: boolean;
begin
-- next state
next_state <= state;
-- output defaults
usb_oe_n <= '1';
usb_rd_en <= '0';
usb_wr_en <= '0';
usb_d <= (others => 'Z');
-- always read from fifo if qdata_out is empty
sfifo_out_rd_en <= not qdata_out_valid;
could_wr := (qdata_out_valid = '1') and (usb_txe_n = '0');
could_rd := (fifo_in_full = '0') and (usb_rxf_n = '0');
case state is
when s_reset =>
next_state <= s_idle;
when s_idle =>
if could_wr then
next_state <= s_switch_to_write1;
elsif could_rd then
next_state <= s_switch_to_read;
end if;
when s_switch_to_read =>
-- disable our outputs and enable usb outputs
next_state <= s_read_mode;
usb_oe_n <= '0';
when s_read_mode =>
-- read data from usb if fifo accepts it
usb_oe_n <= '0';
usb_rd_en <= not fifo_in_full;
-- end read mode if there is nothing to read
if not could_rd then
if could_wr then
next_state <= s_switch_to_write1;
else
next_state <= s_idle;
end if;
end if;
when s_switch_to_write1 =>
-- disable usb output for write mode
next_state <= s_switch_to_write2;
when s_switch_to_write2 =>
-- wait one cycle before enabling our output
next_state <= s_write_mode;
when s_write_mode =>
-- write to usb if valid, get next word from fifo if usb accepts data
usb_d <= qdata_out;
if (qdata_out_valid = '1') then
usb_wr_en <= qdata_out_valid;
sfifo_out_rd_en <= not usb_txe_n;
end if;
-- end write mode if there is nothing to write
if not could_wr then
if could_rd then
next_state <= s_switch_to_read;
else
next_state <= s_idle;
end if;
end if;
when others =>
null;
end case;
end process;
end ft2232fifo_arch; | gpl-3.0 | 08283fade0d2fa3a216921b13a22d3cb | 0.545833 | 3.400707 | false | false | false | false |
alainmarcel/Surelog | third_party/tests/ariane/fpga/src/apb_uart/src/slib_input_filter.vhd | 5 | 2,084 | --
-- Input filter
--
-- Author: Sebastian Witt
-- Data: 06.03.2008
-- Version: 1.0
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_input_filter is
generic (
SIZE : natural := 4 -- Filter counter size
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable
D : in std_logic; -- Signal input
Q : out std_logic -- Signal output
);
end slib_input_filter;
architecture rtl of slib_input_filter is
signal iCount : integer range 0 to SIZE;
begin
IF_D: process (RST, CLK)
begin
if (RST = '1') then
iCount <= 0;
Q <= '0';
elsif (CLK'event and CLK='1') then
-- Input counter
if (CE = '1' ) then
if (D = '1' and iCount /= SIZE) then
iCount <= iCount + 1;
elsif (D = '0' and iCount /= 0) then
iCount <= iCount - 1;
end if;
end if;
-- Output
if (iCount = SIZE) then
Q <= '1';
elsif (iCount = 0) then
Q <= '0';
end if;
end if;
end process;
end rtl;
| apache-2.0 | 1dbd63da8cb07a6fbdd9d78971ab16a3 | 0.547985 | 4.023166 | false | false | false | false |
Xero-Hige/LuGus-VHDL | TPS-2016/tps-Gaston/bcd_multiplexer.vhd | 1 | 1,385 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bcd_multiplexer is
port(
bcd0_input : in std_logic_vector(3 downto 0);
bcd1_input : in std_logic_vector(3 downto 0);
bcd2_input : in std_logic_vector(3 downto 0);
bcd3_input : in std_logic_vector(3 downto 0);
bcd4_input : in std_logic_vector(3 downto 0);
bcd5_input : in std_logic_vector(3 downto 0);
bcd6_input : in std_logic_vector(3 downto 0);
mux_selector : in std_logic_vector (2 downto 0);
mux_output : out std_logic_vector (3 downto 0)
);
end bcd_multiplexer;
architecture bcd_multiplexer_arq of bcd_multiplexer is
begin
process (mux_selector,bcd0_input,bcd1_input,bcd2_input,bcd3_input,bcd4_input,bcd5_input,bcd6_input) is
begin
case mux_selector is
when "000" => mux_output <= bcd0_input;
when "001" => mux_output <= bcd1_input;
when "010" => mux_output <= bcd2_input;
when "011" => mux_output <= bcd3_input;
when "100" => mux_output <= bcd4_input;
when "101" => mux_output <= bcd5_input;
when "110" => mux_output <= bcd6_input;
when others => mux_output <= (others => '0');
end case;
end process;
end bcd_multiplexer_arq; | gpl-3.0 | 51fc973e33a24110da0f4e837b7ea87a | 0.571119 | 3.289786 | false | false | false | false |
pmassolino/hw-goppa-mceliece | mceliece/backup/solving_key_equation_2.vhd | 1 | 28,292 | ----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Solving_Key_Equation_2
-- Module Name: Solving_Key_Equation_2
-- Project Name: McEliece QD-Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 2nd step in Goppa Code Decoding.
--
-- This circuit solves the polynomial key equation sigma with the polynomial syndrome.
-- To solve the key equation, this circuit employs a modified extended euclidean algorithm
-- The modification is made to stop the algorithm when polynomial, represented here as G, has
-- degree less or equal than the polynomial key equation sigma desired degree.
-- The syndrome is the input and expected to be of degree 2*final_degree, and after computations
-- polynomial C, will hold sigma with degree less or equal to final_degree.
--
-- This is pipeline circuit version.
-- A bigger area version with 2 computational pipelines was made called solving_key_equation_4,
-- this new version occupies more area, but it can process four polynomials instead of two at
-- the same time.
--
-- Parameters
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- final_degree :
--
-- The final degree size expected for polynomial sigma to have. This parameter depends
-- of the Goppa code used.
--
-- size_final_degree :
--
-- The number of bits necessary to hold the polynomial with degree of final_degree, which
-- has final_degree + 1 coefficients. This is ceil(log2(final_degree+1)).
--
-- Dependencies:
--
-- VHDL-93
--
-- controller_solving_key_equation_2 Rev 1.0
-- register_nbits Rev 1.0
-- register_rst_nbits Rev 1.0
-- counter_decrement_load_nbits Rev 1.0
-- counter_decrement_load_rst_nbits Rev 1.0
-- mult_gf_2_m Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity solving_key_equation_2 is
Generic(
-- GOPPA [2048, 1751, 27, 11] --
gf_2_m : integer range 1 to 20 := 11;
final_degree : integer := 27;
size_final_degree : integer := 5
-- GOPPA [2048, 1498, 50, 11] --
-- gf_2_m : integer range 1 to 20 := 11;
-- final_degree : integer := 50;
-- size_final_degree : integer := 6
-- GOPPA [3307, 2515, 66, 12] --
-- gf_2_m : integer range 1 to 20 := 11;
-- final_degree : integer := 50;
-- size_final_degree : integer := 6
-- QD-GOPPA [2528, 2144, 32, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 32;
-- size_final_degree : integer := 5
-- QD-GOPPA [2816, 2048, 64, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 64;
-- size_final_degree : integer := 6
-- QD-GOPPA [3328, 2560, 64, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 64;
-- size_final_degree : integer := 6
-- QD-GOPPA [7296, 5632, 128, 13] --
-- gf_2_m : integer range 1 to 20 := 13;
-- final_degree : integer := 128;
-- size_final_degree : integer := 7
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
ready_inv : in STD_LOGIC;
value_FB : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_GC : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_inv : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal_inv : out STD_LOGIC;
key_equation_found : out STD_LOGIC;
write_enable_FB : out STD_LOGIC;
write_enable_GC : out STD_LOGIC;
new_value_inv : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_FB : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_GC : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
address_value_FB : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_value_GC : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_FB : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_GC : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0)
);
end solving_key_equation_2;
architecture Behavioral of solving_key_equation_2 is
component controller_solving_key_equation_2
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
FB_equal_zero : in STD_LOGIC;
i_equal_zero : in STD_LOGIC;
i_minus_j_less_than_zero : in STD_LOGIC;
degree_G_less_equal_final_degree : in STD_LOGIC;
degree_F_less_than_degree_G : in STD_LOGIC;
degree_B_equal_degree_C_plus_j : in STD_LOGIC;
degree_B_less_than_degree_C_plus_j : in STD_LOGIC;
reg_looking_degree_q : in STD_LOGIC_VECTOR(0 downto 0);
key_equation_found : out STD_LOGIC;
signal_inv : out STD_LOGIC;
write_enable_FB : out STD_LOGIC;
write_enable_GC : out STD_LOGIC;
sel_base_mul : out STD_LOGIC;
reg_h_ce : out STD_LOGIC;
ctr_i_ce : out STD_LOGIC;
ctr_i_load : out STD_LOGIC;
ctr_i_rst : out STD_LOGIC;
sel_ctr_i_rst_value : out STD_LOGIC;
sel_ctr_i_d : out STD_LOGIC;
reg_j_ce : out STD_LOGIC;
reg_j_rst : out STD_LOGIC;
reg_FB_ce : out STD_LOGIC;
reg_FB_rst : out STD_LOGIC;
reg_new_value_FB_ce : out STD_LOGIC;
reg_new_value_FB_rst : out STD_LOGIC;
sel_reg_new_value_FB : out STD_LOGIC;
sel_load_new_value_FB : out STD_LOGIC;
reg_GC_ce : out STD_LOGIC;
reg_GC_rst : out STD_LOGIC;
reg_new_value_GC_ce : out STD_LOGIC;
reg_new_value_GC_rst : out STD_LOGIC;
sel_reg_new_value_GC : out STD_LOGIC;
ctr_degree_F_ce : out STD_LOGIC;
ctr_degree_F_load : out STD_LOGIC;
ctr_degree_F_rst : out STD_LOGIC;
reg_degree_G_ce : out STD_LOGIC;
reg_degree_G_rst : out STD_LOGIC;
ctr_degree_B_ce : out STD_LOGIC;
ctr_degree_B_load : out STD_LOGIC;
ctr_degree_B_rst : out STD_LOGIC;
sel_ctr_degree_B : out STD_LOGIC;
reg_degree_C_ce : out STD_LOGIC;
reg_degree_C_rst : out STD_LOGIC;
reg_looking_degree_d : out STD_LOGIC_VECTOR(0 downto 0);
reg_looking_degree_ce : out STD_LOGIC;
reg_swap_ce : out STD_LOGIC;
reg_swap_rst : out STD_LOGIC;
sel_address_FB : out STD_LOGIC;
sel_address_GC : out STD_LOGIC;
ctr_load_address_FB_ce : out STD_LOGIC;
ctr_load_address_FB_load : out STD_LOGIC;
ctr_load_address_FB_rst : out STD_LOGIC;
ctr_load_address_GC_ce : out STD_LOGIC;
ctr_load_address_GC_load : out STD_LOGIC;
ctr_load_address_GC_rst : out STD_LOGIC;
reg_bus_address_FB_ce : out STD_LOGIC;
reg_bus_address_GC_ce : out STD_LOGIC;
reg_calc_address_FB_ce : out STD_LOGIC;
reg_calc_address_GC_ce : out STD_LOGIC;
reg_store_address_FB_ce : out STD_LOGIC;
reg_store_address_GC_ce : out STD_LOGIC;
enable_external_swap : out STD_LOGIC
);
end component;
component register_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component register_rst_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_decrement_load_rst_nbits
Generic (
size : integer;
decrement_value : integer
);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
load : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0)
);
end component;
component counter_decrement_load_nbits
Generic (
size : integer;
decrement_value : integer
);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
load : in STD_LOGIC;
q : out STD_LOGIC_VECTOR((size - 1) downto 0)
);
end component;
component mult_gf_2_m
Generic (gf_2_m : integer range 1 to 20 := 11);
Port (
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
b: in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
signal base_mult_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal base_mult_b : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal base_mult_o : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal sel_base_mul : STD_LOGIC;
signal reg_h_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_h_ce : STD_LOGIC;
signal reg_h_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_inv_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_inv_ce : STD_LOGIC;
signal reg_inv_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal ctr_i_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_i_ce : STD_LOGIC;
signal ctr_i_load : STD_LOGIC;
signal ctr_i_rst : STD_LOGIC;
signal ctr_i_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_i_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal sel_ctr_i_d : STD_LOGIC;
signal sel_ctr_i_rst_value : STD_LOGIC;
constant ctr_i_rst_value_F : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(2*final_degree - 1,size_final_degree + 2));
constant ctr_i_rst_value_B : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(final_degree,size_final_degree + 2));
signal reg_j_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_j_ce : STD_LOGIC;
signal reg_j_rst : STD_LOGIC;
constant reg_j_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(0,size_final_degree + 2));
signal reg_j_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_FB_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_FB_ce : STD_LOGIC;
signal reg_FB_rst : STD_LOGIC;
constant reg_FB_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others=> '0');
signal reg_FB_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_GC_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_GC_ce : STD_LOGIC;
signal reg_GC_rst : STD_LOGIC;
constant reg_GC_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others=> '0');
signal reg_GC_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_FB_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_FB_ce : STD_LOGIC;
signal reg_new_value_FB_rst : STD_LOGIC;
constant reg_new_value_FB_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others => '0');
signal reg_new_value_FB_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal sel_reg_new_value_FB : STD_LOGIC;
signal reg_new_value_GC_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_new_value_GC_ce : STD_LOGIC;
signal reg_new_value_GC_rst : STD_LOGIC;
constant reg_new_value_GC_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others=> '0');
signal reg_new_value_GC_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal sel_reg_new_value_GC : STD_LOGIC;
signal ctr_degree_F_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_degree_F_ce : STD_LOGIC;
signal ctr_degree_F_load : STD_LOGIC;
signal ctr_degree_F_rst : STD_LOGIC;
constant ctr_degree_F_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(2*final_degree - 1,size_final_degree + 2));
signal ctr_degree_F_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_degree_G_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_degree_G_ce : STD_LOGIC;
signal reg_degree_G_rst : STD_LOGIC;
constant reg_degree_G_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(2*final_degree,size_final_degree + 2));
signal reg_degree_G_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_degree_B_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_degree_B_ce : STD_LOGIC;
signal ctr_degree_B_load : STD_LOGIC;
signal ctr_degree_B_rst : STD_LOGIC;
constant ctr_degree_B_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(0,size_final_degree + 2));
signal ctr_degree_B_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal sel_ctr_degree_B : STD_LOGIC;
signal reg_degree_C_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_degree_C_ce : STD_LOGIC;
signal reg_degree_C_rst : STD_LOGIC;
constant reg_degree_C_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(0,size_final_degree + 2));
signal reg_degree_C_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_looking_degree_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_looking_degree_ce : STD_LOGIC;
signal reg_looking_degree_q : STD_LOGIC_VECTOR(0 downto 0);
signal reg_swap_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_swap_ce : STD_LOGIC;
signal reg_swap_rst : STD_LOGIC;
constant reg_swap_rst_value : STD_LOGIC_VECTOR(0 downto 0) := "0";
signal reg_swap_q : STD_LOGIC_VECTOR(0 downto 0);
signal i_minus_j : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal degree_C_plus_j : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal int_value_FB : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal int_value_GC : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal sel_load_new_value_FB : STD_LOGIC;
signal int_write_enable_FB : STD_LOGIC;
signal int_write_enable_GC : STD_LOGIC;
signal address_degree_F : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal address_degree_C_plus_J : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal address_degree_G : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal address_degree_C : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal sel_address_FB : STD_LOGIC;
signal sel_address_GC : STD_LOGIC;
signal ctr_load_address_FB_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_load_address_FB_ce : STD_LOGIC;
signal ctr_load_address_FB_load : STD_LOGIC;
signal ctr_load_address_FB_rst : STD_LOGIC;
constant ctr_load_address_FB_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(3*final_degree + 1,size_final_degree + 2));
signal ctr_load_address_FB_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_load_address_GC_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_load_address_GC_ce : STD_LOGIC;
signal ctr_load_address_GC_load : STD_LOGIC;
signal ctr_load_address_GC_rst : STD_LOGIC;
constant ctr_load_address_GC_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(3*final_degree + 1,size_final_degree + 2));
signal ctr_load_address_GC_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_bus_address_FB_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_bus_address_FB_ce : STD_LOGIC;
signal reg_bus_address_FB_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_bus_address_GC_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_bus_address_GC_ce : STD_LOGIC;
signal reg_bus_address_GC_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_calc_address_FB_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_calc_address_FB_ce : STD_LOGIC;
signal reg_calc_address_FB_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_calc_address_GC_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_calc_address_GC_ce : STD_LOGIC;
signal reg_calc_address_GC_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_store_address_FB_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_store_address_FB_ce : STD_LOGIC;
signal reg_store_address_FB_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_store_address_GC_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_store_address_GC_ce : STD_LOGIC;
signal reg_store_address_GC_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal enable_external_swap : STD_LOGIC;
signal FB_equal_zero : STD_LOGIC;
signal i_equal_zero : STD_LOGIC;
signal i_minus_j_less_than_zero : STD_LOGIC;
signal degree_G_less_equal_final_degree : STD_LOGIC;
signal degree_F_less_than_degree_G : STD_LOGIC;
signal degree_B_equal_degree_C_plus_j : STD_LOGIC;
signal degree_B_less_than_degree_C_plus_j : STD_LOGIC;
begin
controller : controller_solving_key_equation_2
Port Map(
clk => clk,
rst => rst,
FB_equal_zero => FB_equal_zero,
i_equal_zero => i_equal_zero,
i_minus_j_less_than_zero => i_minus_j_less_than_zero,
degree_G_less_equal_final_degree => degree_G_less_equal_final_degree,
degree_F_less_than_degree_G => degree_F_less_than_degree_G,
degree_B_equal_degree_C_plus_j => degree_B_equal_degree_C_plus_j,
degree_B_less_than_degree_C_plus_j => degree_B_less_than_degree_C_plus_j,
reg_looking_degree_q => reg_looking_degree_q,
key_equation_found => key_equation_found,
signal_inv => signal_inv,
write_enable_FB => int_write_enable_FB,
write_enable_GC => int_write_enable_GC,
sel_base_mul => sel_base_mul,
reg_h_ce => reg_h_ce,
ctr_i_ce => ctr_i_ce,
ctr_i_load => ctr_i_load,
ctr_i_rst => ctr_i_rst,
sel_ctr_i_rst_value => sel_ctr_i_rst_value,
sel_ctr_i_d => sel_ctr_i_d,
reg_j_ce => reg_j_ce,
reg_j_rst => reg_j_rst,
reg_FB_ce => reg_FB_ce,
reg_FB_rst => reg_FB_rst,
reg_new_value_FB_ce => reg_new_value_FB_ce,
reg_new_value_FB_rst => reg_new_value_FB_rst,
sel_reg_new_value_FB => sel_reg_new_value_FB,
sel_load_new_value_FB => sel_load_new_value_FB,
reg_GC_ce => reg_GC_ce,
reg_GC_rst => reg_GC_rst,
reg_new_value_GC_ce => reg_new_value_GC_ce,
reg_new_value_GC_rst => reg_new_value_GC_rst,
sel_reg_new_value_GC => sel_reg_new_value_GC,
ctr_degree_F_ce => ctr_degree_F_ce,
ctr_degree_F_load => ctr_degree_F_load,
ctr_degree_F_rst => ctr_degree_F_rst,
reg_degree_G_ce => reg_degree_G_ce,
reg_degree_G_rst => reg_degree_G_rst,
ctr_degree_B_ce => ctr_degree_B_ce,
ctr_degree_B_load => ctr_degree_B_load,
ctr_degree_B_rst => ctr_degree_B_rst,
sel_ctr_degree_B => sel_ctr_degree_B,
reg_degree_C_ce => reg_degree_C_ce,
reg_degree_C_rst => reg_degree_C_rst,
reg_looking_degree_d => reg_looking_degree_d,
reg_looking_degree_ce => reg_looking_degree_ce,
reg_swap_ce => reg_swap_ce,
reg_swap_rst => reg_swap_rst,
sel_address_FB => sel_address_FB,
sel_address_GC => sel_address_GC,
ctr_load_address_FB_ce => ctr_load_address_FB_ce,
ctr_load_address_FB_load => ctr_load_address_FB_load,
ctr_load_address_FB_rst => ctr_load_address_FB_rst,
ctr_load_address_GC_ce => ctr_load_address_GC_ce,
ctr_load_address_GC_load => ctr_load_address_GC_load,
ctr_load_address_GC_rst => ctr_load_address_GC_rst,
reg_bus_address_FB_ce => reg_bus_address_FB_ce,
reg_bus_address_GC_ce => reg_bus_address_GC_ce,
reg_calc_address_FB_ce => reg_calc_address_FB_ce,
reg_calc_address_GC_ce => reg_calc_address_GC_ce,
reg_store_address_FB_ce => reg_store_address_FB_ce,
reg_store_address_GC_ce => reg_store_address_GC_ce,
enable_external_swap => enable_external_swap
);
base_mult : mult_gf_2_m
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => base_mult_a,
b => base_mult_b,
o => base_mult_o
);
reg_h : register_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_h_d,
clk => clk,
ce => reg_h_ce,
q => reg_h_q
);
reg_inv : register_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_inv_d,
clk => clk,
ce => reg_inv_ce,
q => reg_inv_q
);
ctr_i : counter_decrement_load_rst_nbits
Generic Map(
size => size_final_degree+2,
decrement_value => 1
)
Port Map(
d => ctr_i_d,
clk => clk,
ce => ctr_i_ce,
load => ctr_i_load,
rst => ctr_i_rst,
rst_value => ctr_i_rst_value,
q => ctr_i_q
);
reg_j : register_rst_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_j_d,
clk => clk,
ce => reg_j_ce,
rst => reg_j_rst,
rst_value => reg_j_rst_value,
q => reg_j_q
);
reg_FB : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_FB_d,
clk => clk,
rst => reg_FB_rst,
rst_value => reg_FB_rst_value,
ce => reg_FB_ce,
q => reg_FB_q
);
reg_GC : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_GC_d,
clk => clk,
rst => reg_GC_rst,
rst_value => reg_GC_rst_value,
ce => reg_GC_ce,
q => reg_GC_q
);
reg_new_value_FB : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_new_value_FB_d,
clk => clk,
ce => reg_new_value_FB_ce,
rst => reg_new_value_FB_rst,
rst_value => reg_new_value_FB_rst_value,
q => reg_new_value_FB_q
);
reg_new_value_GC : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_new_value_GC_d,
clk => clk,
ce => reg_new_value_GC_ce,
rst => reg_new_value_GC_rst,
rst_value => reg_new_value_GC_rst_value,
q => reg_new_value_GC_q
);
ctr_degree_F : counter_decrement_load_rst_nbits
Generic Map(
size => size_final_degree+2,
decrement_value => 1
)
Port Map(
d => ctr_degree_F_d,
clk => clk,
ce => ctr_degree_F_ce,
load => ctr_degree_F_load,
rst => ctr_degree_F_rst,
rst_value => ctr_degree_F_rst_value,
q => ctr_degree_F_q
);
reg_degree_G : register_rst_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_degree_G_d,
clk => clk,
rst => reg_degree_G_rst,
rst_value => reg_degree_G_rst_value,
ce => reg_degree_G_ce,
q => reg_degree_G_q
);
ctr_degree_B : counter_decrement_load_rst_nbits
Generic Map(
size => size_final_degree+2,
decrement_value => 1
)
Port Map(
d => ctr_degree_B_d,
clk => clk,
ce => ctr_degree_B_ce,
load => ctr_degree_B_load,
rst => ctr_degree_B_rst,
rst_value => ctr_degree_B_rst_value,
q => ctr_degree_B_q
);
reg_degree_C : register_rst_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_degree_C_d,
clk => clk,
rst => reg_degree_C_rst,
rst_value => reg_degree_C_rst_value,
ce => reg_degree_C_ce,
q => reg_degree_C_q
);
ctr_load_address_FB : counter_decrement_load_rst_nbits
Generic Map(
size => size_final_degree+2,
decrement_value => 1
)
Port Map(
d => ctr_load_address_FB_d,
clk => clk,
ce => ctr_load_address_FB_ce,
load => ctr_load_address_FB_load,
rst => ctr_load_address_FB_rst,
rst_value => ctr_load_address_FB_rst_value,
q => ctr_load_address_FB_q
);
ctr_load_address_GC : counter_decrement_load_rst_nbits
Generic Map(
size => size_final_degree+2,
decrement_value => 1
)
Port Map(
d => ctr_load_address_GC_d,
clk => clk,
ce => ctr_load_address_GC_ce,
load => ctr_load_address_GC_load,
rst => ctr_load_address_GC_rst,
rst_value => ctr_load_address_GC_rst_value,
q => ctr_load_address_GC_q
);
reg_bus_address_FB : register_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_bus_address_FB_d,
clk => clk,
ce => reg_bus_address_FB_ce,
q => reg_bus_address_FB_q
);
reg_bus_address_GC : register_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_bus_address_GC_d,
clk => clk,
ce => reg_bus_address_GC_ce,
q => reg_bus_address_GC_q
);
reg_calc_address_FB : register_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_calc_address_FB_d,
clk => clk,
ce => reg_calc_address_FB_ce,
q => reg_calc_address_FB_q
);
reg_calc_address_GC : register_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_calc_address_GC_d,
clk => clk,
ce => reg_calc_address_GC_ce,
q => reg_calc_address_GC_q
);
reg_store_address_FB : register_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_store_address_FB_d,
clk => clk,
ce => reg_store_address_FB_ce,
q => reg_store_address_FB_q
);
reg_store_address_GC : register_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_store_address_GC_d,
clk => clk,
ce => reg_store_address_GC_ce,
q => reg_store_address_GC_q
);
reg_looking_degree : register_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_looking_degree_d,
clk => clk,
ce => reg_looking_degree_ce,
q => reg_looking_degree_q
);
reg_swap : register_rst_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_swap_d,
clk => clk,
ce => reg_swap_ce,
rst => reg_swap_rst,
rst_value => reg_swap_rst_value,
q => reg_swap_q
);
base_mult_a <= reg_inv_q when sel_base_mul = '1' else
reg_h_q;
base_mult_b <= reg_FB_q when sel_base_mul = '1' else
reg_GC_q;
reg_h_d <= base_mult_o;
reg_inv_d <= value_inv;
reg_inv_ce <= ready_inv;
ctr_i_d <= ctr_degree_F_q when sel_ctr_i_d = '1' else
degree_C_plus_j;
ctr_i_rst_value <= ctr_i_rst_value_F when sel_ctr_i_rst_value = '1' else
ctr_i_rst_value_B;
reg_j_d <= std_logic_vector(unsigned(ctr_degree_F_q) - unsigned(reg_degree_G_q));
reg_FB_d <= int_value_FB;
reg_GC_d <= int_value_GC;
ctr_degree_F_d <= reg_degree_G_q;
reg_degree_G_d <= ctr_degree_F_q;
ctr_degree_B_d <= degree_C_plus_j when sel_ctr_degree_B = '1' else
reg_degree_C_q;
degree_C_plus_j <= std_logic_vector(unsigned(reg_degree_C_q) + unsigned(reg_j_q));
i_minus_j <= std_logic_vector(unsigned(ctr_i_q) - unsigned(reg_j_q));
reg_degree_C_d <= ctr_degree_B_q;
reg_swap_d <= not reg_swap_q;
reg_new_value_FB_d <= (base_mult_o xor reg_FB_q) when sel_load_new_value_FB = '1' else
std_logic_vector(to_unsigned(1, reg_FB_d'length)) when sel_reg_new_value_FB = '1' else
reg_FB_q;
reg_new_value_GC_d <= std_logic_vector(to_unsigned(1, reg_GC_d'length)) when sel_reg_new_value_GC = '1' else
reg_GC_q;
int_value_FB <= value_GC when reg_swap_q = "1" else value_FB;
int_value_GC <= value_FB when reg_swap_q = "1" else value_GC;
new_value_inv <= reg_new_value_FB_q;
new_value_FB <= reg_new_value_GC_q when (reg_swap_q(0) and enable_external_swap) = '1' else reg_new_value_FB_q;
new_value_GC <= reg_new_value_FB_q when (reg_swap_q(0) and enable_external_swap) = '1' else reg_new_value_GC_q;
write_enable_FB <= int_write_enable_GC when (reg_swap_q(0) and enable_external_swap) = '1' else int_write_enable_FB;
write_enable_GC <= int_write_enable_FB when (reg_swap_q(0) and enable_external_swap) = '1' else int_write_enable_GC;
address_degree_F <= ctr_degree_F_q;
address_degree_C_plus_j <= std_logic_vector(to_unsigned(2*final_degree + 1, address_degree_C_plus_j'length) + unsigned(degree_C_plus_j));
address_degree_G <= reg_degree_G_q;
address_degree_C <= std_logic_vector(to_unsigned(2*final_degree + 1, address_degree_C'length) + unsigned(reg_degree_C_q));
ctr_load_address_FB_d <= address_degree_F when sel_address_FB = '1' else
address_degree_C_plus_j;
ctr_load_address_GC_d <= address_degree_G when sel_address_GC = '1' else
address_degree_C;
reg_bus_address_FB_d <= ctr_load_address_FB_q;
reg_bus_address_GC_d <= ctr_load_address_GC_q;
reg_calc_address_FB_d <= reg_bus_address_FB_q;
reg_calc_address_GC_d <= reg_bus_address_GC_q;
reg_store_address_FB_d <= reg_calc_address_FB_q;
reg_store_address_GC_d <= reg_calc_address_GC_q;
address_value_FB <= ctr_load_address_GC_q when reg_swap_q(0) = '1' else ctr_load_address_FB_q;
address_value_GC <= ctr_load_address_FB_q when reg_swap_q(0) = '1' else ctr_load_address_GC_q;
address_new_value_FB <= reg_store_address_GC_q when (reg_swap_q(0) and enable_external_swap) = '1' else reg_store_address_FB_q;
address_new_value_GC <= reg_store_address_FB_q when (reg_swap_q(0) and enable_external_swap) = '1' else reg_store_address_GC_q;
FB_equal_zero <= '1' when (reg_new_value_FB_q = std_logic_vector(to_unsigned(0,reg_FB_q'length))) else '0';
i_equal_zero <= '1' when (ctr_i_q = std_logic_vector(to_unsigned(0,ctr_i_q'length))) else '0';
i_minus_j_less_than_zero <= '1' when (signed(i_minus_j) < to_signed(0,i_minus_j'length)) else '0';
degree_G_less_equal_final_degree <= '1' when (unsigned(reg_degree_G_q) <= to_unsigned(final_degree-1,reg_degree_G_q'length)) else '0';
degree_F_less_than_degree_G <= '1' when (unsigned(ctr_degree_F_q) < unsigned(reg_degree_G_q)) else '0';
degree_B_equal_degree_C_plus_j <= '1' when (ctr_degree_B_q = degree_C_plus_j) else '0';
degree_B_less_than_degree_C_plus_j <= '1' when (unsigned(ctr_degree_B_q) < unsigned(degree_C_plus_j)) else '0';
end Behavioral; | bsd-2-clause | a7da0d4c9b35890a09e0a7e21a4f89f2 | 0.660363 | 2.551587 | false | false | false | false |
pmassolino/hw-goppa-mceliece | mceliece/util/ram_bank.vhd | 1 | 4,088 | ----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: RAM_Bank
-- Module Name: RAM_Bank
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Circuit to simulate the behavioral of a memory RAM bank. Only used for tests.
-- In this bank all memories are accessed at the same time, therefore it is like
-- to access one big memory with memory word multiplied by number of memories in the bank.
-- It is useful when you want to access more than one location at the same time.
--
-- The circuits parameters
--
-- number_of_memories :
--
-- The total number of memories inside of the memory bank.
--
-- ram_address_size :
--
-- Address size of each RAM in the RAM bank used on the circuit.
--
-- ram_word_size :
--
-- The size of internal word of each RAM in the RAM bank.
--
-- file_ram_word_size :
--
-- The size of the word used in the file to be loaded on each RAM.(ARCH: FILE_LOAD)
--
-- load_file_name :
--
-- The name of file to be loaded.(ARCH: FILE_LOAD)
--
-- dump_file_name :
--
-- The name of the file to be used to dump the memory.(ARCH: FILE_LOAD)
--
-- Dependencies:
-- VHDL-93
--
-- IEEE.NUMERIC_STD.ALL;
-- IEEE.STD_LOGIC_TEXTIO.ALL;
-- STD.TEXTIO.ALL;
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
library STD;
use STD.TEXTIO.ALL;
entity ram_bank is
Generic (
number_of_memories : integer;
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0)
);
end ram_bank;
architecture simple of ram_bank is
type ramtype is array(0 to (2**ram_address_size - 1)) of std_logic_vector((ram_word_size - 1) downto 0);
procedure dump_ram (ram_file_name : in string; memory_ram : in ramtype) is
FILE ram_file : text is out ram_file_name;
variable line_n : line;
begin
for I in ramtype'range loop
write (line_n, memory_ram(I));
writeline (ram_file, line_n);
end loop;
end procedure;
signal memory_ram : ramtype;
begin
process (clk)
begin
if clk'event and clk = '1' then
if rst = '1' then
for I in ramtype'range loop
memory_ram(I) <= rst_value;
end loop;
end if;
if dump = '1' then
dump_ram(dump_file_name, memory_ram);
end if;
if rw = '1' then
for index in 0 to (number_of_memories - 1) loop
memory_ram(to_integer(unsigned(address)) + index) <= data_in(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index));
end loop;
end if;
for index in 0 to (number_of_memories - 1) loop
data_out(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index)) <= memory_ram(to_integer(unsigned(address)) + index);
end loop;
end if;
end process;
end simple;
| bsd-2-clause | 8c5381e7a735506d9b88e9d8db136d03 | 0.543787 | 3.633778 | false | false | false | false |
Xero-Hige/LuGus-VHDL | TP4/UART/serial2vga_system.vhd | 1 | 2,484 | -- ---------------------------------------------
-- UART system to test the simple uart unit and tha VGA Char generator
-- BAUD RATE 115200
-- ---------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
entity serial2vga_system is
port (
clk : in std_logic;
rst : in std_logic;
-- Divisor : in std_logic_vector (11 downto 0); descomentar para otras velocidades
rx : in std_logic;
tx : out std_logic;
hsync : out std_logic;
vsync : out std_logic;
red_out : out std_logic;
grn_out : out std_logic;
blu_out : out std_logic
);
end serial2vga_system;
architecture arch of serial2vga_system is
component uart
generic (
F: natural;
min_baud: natural;
num_data_bits: natural
);
port (
Rx : in std_logic;
Tx : out std_logic;
Din : in std_logic_vector(7 downto 0);
StartTx : in std_logic;
TxBusy : out std_logic;
Dout : out std_logic_vector(7 downto 0);
RxRdy : out std_logic;
RxErr : out std_logic;
Divisor : in std_logic_vector;
clk : in std_logic;
rst : in std_logic
);
end component;
component aplicVGA
port (
clk: in std_logic;
char_in: in std_logic_vector(7 downto 0);
RxRdy: in std_logic;
hsync : out std_logic;
vsync : out std_logic;
red_out : out std_logic;
grn_out : out std_logic;
blu_out : out std_logic
);
end component;
constant Divisor : std_logic_vector := "000000011011"; -- Divisor=27 para 115200 baudios
signal sig_Din : std_logic_vector(7 downto 0);
signal sig_Dout : std_logic_vector(7 downto 0);
signal sig_RxErr : std_logic;
signal sig_RxRdy : std_logic;
signal sig_TxBusy : std_logic;
signal sig_StartTx: std_logic;
begin
-- UART Instanciation :
UUT : uart
generic map (
F => 50000,
min_baud => 1200,
num_data_bits => 8
)
port map (
Rx => rx,
Tx => tx,
Din => sig_Din,
StartTx => sig_StartTx,
TxBusy => sig_TxBusy,
Dout => sig_Dout,
RxRdy => sig_RxRdy,
RxErr => sig_RxErr,
Divisor => Divisor,
clk => clk,
rst => rst
);
-- BACKEND APPLICATION Instanciation :
APPLICATION: aplicVGA
port map (
CLK => clk,
char_in => sig_Dout,
RxRdy => sig_RxRdy,
hsync => hsync,
vsync => vsync,
red_out => red_out,
grn_out => grn_out,
blu_out => blu_out
);
end arch;
| gpl-3.0 | 4dedbb402c28cfcbbf3405e1eef5f63d | 0.561192 | 3.188703 | false | false | false | false |
achan1989/In64 | FPGA/SD_card_test.srcs/sim_1/new/sim_main.vhd | 1 | 1,899 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 24.08.2013 13:49:00
-- Design Name:
-- Module Name: main_sim - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity main_sim is
Port ( uart_tx : out std_ulogic;
sd_cs_out : out std_ulogic;
sd_clk_out : out std_ulogic;
sd_mosi : out std_ulogic);
end main_sim;
architecture sim_arch of main_sim is
component main
Port ( clk : in std_ulogic;
reset_switch : in std_ulogic;
uart_tx : out std_ulogic;
sd_cs_out : out std_ulogic;
sd_clk_out : out std_ulogic;
sd_mosi : out std_ulogic;
sd_miso : in std_ulogic);
end component;
signal clk : std_ulogic := '0';
signal sd_miso : std_ulogic := '0';
signal reset : std_ulogic := '1';
begin
main_being_tested: main
port map( clk => clk,
reset_switch => reset,
uart_tx => uart_tx,
sd_cs_out =>sd_cs_out,
sd_clk_out => sd_clk_out,
sd_mosi => sd_mosi,
sd_miso => sd_miso);
input_clock: process begin
clk <= '0';
sd_miso <= '1';
wait for 10ns;
clk <= '1';
sd_miso <= '0';
wait for 10ns;
end process;
end sim_arch;
| lgpl-3.0 | 3b07993be23a4d78ab8b32ad95004a62 | 0.528699 | 3.716243 | false | false | false | false |
Xero-Hige/LuGus-VHDL | TP4/enable_generator/enable_generator_tb.vhd | 1 | 1,082 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity enable_generator_tb is
end entity;
architecture enable_generator_tb_arq of enable_generator_tb is
signal enable_in : std_logic := '0';
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal enable_out : std_logic := '0';
component enable_generator is
generic(CYCLE_COUNT: integer := 10; PASSIVE_CYCLES: integer := 0; ACTIVE_CYCLES: integer := 0);
port(
rst : in std_logic := '0';
clk: in std_logic := '0';
enable_in: in std_logic := '0';
enable_out : out std_logic := '0'
);
end component;
begin
enable_generator_0 : enable_generator
generic map(CYCLE_COUNT => 2, PASSIVE_CYCLES => 3, ACTIVE_CYCLES => 2)
port map(
rst => rst,
enable_in => enable_in,
clk => clk,
enable_out => enable_out
);
process
begin
enable_in <= '1';
for i in 0 to 100 loop
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
-- Check the outputs.
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
| gpl-3.0 | e992523ac2b91cfcea8600fdae1d4b84 | 0.627542 | 2.900804 | false | false | false | false |
dtysky/3D_Displayer_Controller | VHDL/PLL2.vhd | 1 | 21,015 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: PLL2.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY PLL2 IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC ;
c4 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END PLL2;
ARCHITECTURE SYN OF pll2 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7 : STD_LOGIC ;
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire9_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire9 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
clk3_divide_by : NATURAL;
clk3_duty_cycle : NATURAL;
clk3_multiply_by : NATURAL;
clk3_phase_shift : STRING;
clk4_divide_by : NATURAL;
clk4_duty_cycle : NATURAL;
clk4_multiply_by : NATURAL;
clk4_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire9_bv(0 DOWNTO 0) <= "0";
sub_wire9 <= To_stdlogicvector(sub_wire9_bv);
sub_wire6 <= sub_wire0(4);
sub_wire5 <= sub_wire0(2);
sub_wire4 <= sub_wire0(0);
sub_wire2 <= sub_wire0(3);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
c3 <= sub_wire2;
locked <= sub_wire3;
c0 <= sub_wire4;
c2 <= sub_wire5;
c4 <= sub_wire6;
sub_wire7 <= inclk0;
sub_wire8 <= sub_wire9(0 DOWNTO 0) & sub_wire7;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 4,
clk0_phase_shift => "0",
clk1_divide_by => 1,
clk1_duty_cycle => 50,
clk1_multiply_by => 4,
clk1_phase_shift => "0",
clk2_divide_by => 1,
clk2_duty_cycle => 50,
clk2_multiply_by => 4,
clk2_phase_shift => "3571",
clk3_divide_by => 1,
clk3_duty_cycle => 50,
clk3_multiply_by => 8,
clk3_phase_shift => "0",
clk4_divide_by => 1,
clk4_duty_cycle => 50,
clk4_multiply_by => 8,
clk4_phase_shift => "1786",
compensate_clock => "CLK0",
inclk0_input_frequency => 28571,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=PLL2",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_USED",
port_clk4 => "PORT_USED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
inclk => sub_wire8,
clk => sub_wire0,
locked => sub_wire3
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "140.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "140.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "140.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "280.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "280.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "35.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4"
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "8"
-- Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "8"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "180.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "180.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "PLL2.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK4 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "3571"
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "8"
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "8"
-- Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "1786"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "28571"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
-- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
-- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL2.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL2.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL2.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL2_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| gpl-2.0 | b69300798e45f3dd51321daa51ead99b | 0.7005 | 3.241055 | false | false | false | false |
andrecp/myhdl_simple_uart | generated_files/serial_rx.vhd | 1 | 3,727 | -- File: serial_rx.vhd
-- Generated by MyHDL 0.8
-- Date: Thu Aug 21 10:54:44 2014
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity serial_rx is
port (
sysclk: in std_logic;
reset_n: in std_logic;
half_baud_rate_tick_i: in std_logic;
baud_rate_tick_i: in std_logic;
recieve_i: in std_logic;
data_o: out unsigned(7 downto 0);
ready_o: out std_logic
);
end entity serial_rx;
-- Serial
-- This module implements a reciever serial interface
--
-- Ports:
-- -----
-- sysclk: sysclk input
-- reset_n: reset input
-- half_baud_rate_tick_i: half baud rate tick
-- baud_rate_tick_i: the baud rate
-- n_stop_bits_i: number of stop bits
-- recieve_i: rx
-- data_o: the data output in 1 byte
-- ready_o: indicates data_o is valid
-- -----
architecture MyHDL of serial_rx is
constant n_stop_bits_i: integer := 2;
constant END_OF_BYTE: integer := 7;
type t_enum_t_State_1 is (
ST_WAIT_START_BIT,
ST_GET_DATA_BITS,
ST_GET_STOP_BITS
);
signal data_reg: unsigned(7 downto 0);
signal count_8_bits_reg: unsigned(2 downto 0);
signal data: unsigned(7 downto 0);
signal count_8_bits: unsigned(2 downto 0);
signal ready: std_logic;
signal state: t_enum_t_State_1;
signal count_stop_bits_reg: unsigned(2 downto 0);
signal count_stop_bits: unsigned(2 downto 0);
signal state_reg: t_enum_t_State_1;
signal ready_reg: std_logic;
begin
data_o <= data_reg;
ready_o <= ready_reg;
SERIAL_RX_SEQUENTIAL_PROCESS: process (sysclk, reset_n) is
begin
if (reset_n = '0') then
count_8_bits_reg <= to_unsigned(0, 3);
count_stop_bits_reg <= to_unsigned(0, 3);
ready_reg <= '0';
state_reg <= ST_WAIT_START_BIT;
data_reg <= to_unsigned(0, 8);
elsif rising_edge(sysclk) then
state_reg <= state;
data_reg <= data;
ready_reg <= ready;
count_8_bits_reg <= count_8_bits;
count_stop_bits_reg <= count_stop_bits;
end if;
end process SERIAL_RX_SEQUENTIAL_PROCESS;
SERIAL_RX_COMBINATIONAL_PROCESS: process (count_8_bits_reg, recieve_i, data_reg, baud_rate_tick_i, count_stop_bits_reg, state_reg, ready_reg) is
begin
state <= state_reg;
data <= data_reg;
ready <= ready_reg;
count_8_bits <= count_8_bits_reg;
count_stop_bits <= count_stop_bits_reg;
case state_reg is
when ST_WAIT_START_BIT =>
ready <= '0';
if (baud_rate_tick_i = '1') then
if (recieve_i = '0') then
state <= ST_GET_DATA_BITS;
end if;
end if;
when ST_GET_DATA_BITS =>
if (baud_rate_tick_i = '1') then
data(to_integer(count_8_bits_reg)) <= recieve_i;
if (count_8_bits_reg = END_OF_BYTE) then
count_8_bits <= to_unsigned(0, 3);
state <= ST_GET_STOP_BITS;
else
count_8_bits <= (count_8_bits_reg + 1);
state <= ST_GET_DATA_BITS;
end if;
end if;
when ST_GET_STOP_BITS =>
if (baud_rate_tick_i = '1') then
if (signed(resize(count_stop_bits_reg, 4)) = (n_stop_bits_i - 1)) then
count_stop_bits <= to_unsigned(0, 3);
ready <= '1';
state <= ST_WAIT_START_BIT;
else
count_stop_bits <= (count_stop_bits_reg + 1);
end if;
end if;
when others =>
assert False report "End of Simulation" severity Failure;
end case;
end process SERIAL_RX_COMBINATIONAL_PROCESS;
end architecture MyHDL;
| mit | 3ac398cb27b13addc75106f08cd8b20b | 0.570969 | 3.246516 | false | false | false | false |
Xero-Hige/LuGus-VHDL | TP4/dual_port_ram/dual_port_ram_tb.vhd | 1 | 3,792 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dual_port_ram_tb is
end entity;
architecture dual_port_ram_tb_arq of dual_port_ram_tb is
signal data_in : std_logic_vector (0 downto 0) := (others => '0');
signal write_address : std_logic_vector (13 downto 0) := (others => '0');
signal write_enable : std_logic := '0';
signal ram_write_mask : std_logic_vector(7 downto 0) := (others => '0');
signal enable : std_logic := '0';
signal reset : std_logic := '0';
signal clk : std_logic := '0';
signal ram_read_mask : std_logic_vector(7 downto 0) := (others => '0');
signal read_address : std_logic_vector(13 downto 0) := (others => '0');
signal data_out : std_logic_vector (0 downto 0) := (others => '0');
component dual_port_ram is
port (
data_in : in std_logic_vector (0 downto 0) := (others => '0');
write_address : in std_logic_vector (13 downto 0) := (others => '0');
write_enable : in std_logic := '0';
ram_write_mask : in std_logic_vector(7 downto 0) := (others => '0');
enable : in std_logic := '0';
clk : in std_logic := '0';
reset : in std_logic := '0';
ram_read_mask : in std_logic_vector(7 downto 0) := (others => '0');
read_address : in std_logic_vector(13 downto 0) := (others => '0');
data_out : out std_logic_vector (0 downto 0) := (others => '0')
);
end component;
begin
dual_port_ram_0 : dual_port_ram
port map(
data_in => data_in,
write_address => write_address,
write_enable => write_enable,
ram_write_mask => ram_write_mask,
enable => enable,
reset => reset,
clk => clk,
ram_read_mask => ram_read_mask,
read_address => read_address,
data_out => data_out
);
process
type pattern_type is record
din : std_logic_vector(0 downto 0);
wa : std_logic_vector(13 downto 0);
wen : std_logic;
rwm : std_logic_vector(7 downto 0);
rrm : std_logic_vector(7 downto 0);
ra : std_logic_vector(13 downto 0);
dot : std_logic_vector(0 downto 0);
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array := (
("1",
"00000000000001",
'1',
"00000001",
"00000000",
"00000000000000",
"0"),
("0",
"00000000000000",
'0',
"00000000",
"00000001",
"00000000000001",
"1"),
("1",
"00000001000000",
'1',
"00010000",
"00000000",
"00000000000000",
"0"),
("1",
"10000000000000",
'1',
"10000000",
"00000000",
"00000000000000",
"0"),
("0",
"00000000000000",
'0',
"00000000",
"00010000",
"00000001000000",
"1"),
("0",
"00000000000000",
'0',
"00000000",
"10000000",
"10000000000000",
"1"),
("1",
"00000000000001",
'1',
"00000001",
"00000000",
"00000000000000",
"0"),
("1",
"01110110100001",
'1',
"00100000",
"00000000",
"00000000000000",
"0"),
("0",
"00000000000000",
'0',
"00000000",
"00100000",
"01110110100001",
"1")
);
begin
clk <= '0';
enable <= '1';
reset <= '0';
for i in patterns'range loop
clk <= '0';
wait for 1 ns;
-- Set the inputs.
data_in <= patterns(i).din;
write_address <= patterns(i).wa;
write_enable <= patterns(i).wen;
ram_write_mask <= patterns(i).rwm;
ram_read_mask <= patterns(i).rrm;
read_address <= patterns(i).ra;
clk <= '1';
wait for 1 ns;
assert patterns(i).dot = data_out report "BAD SAVED VALUE, EXPECTED: " & std_logic'image(patterns(i).dot(0)) & " GOT: " & std_logic'image(data_out(0));
-- Check the outputs.
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
| gpl-3.0 | 2516ebd8729d94a4ae79c726afd64133 | 0.568565 | 3.098039 | false | false | false | false |
pmassolino/hw-goppa-mceliece | mceliece/backup/mceliece_qd_goppa_decrypt.vhd | 1 | 32,110 | ----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: McEliece_QD-Goppa_Decrypt
-- Module Name: McEliece_QD-Goppa_Decrypt
-- Project Name: McEliece Goppa Decryption
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- This circuit implements McEliece decryption algorithm for binary Goppa codes.
-- The circuit is divided into 3 phases : Syndrome computation, Solving Key Equation and
-- Finding Roots.
-- Each circuits waits for the next one to begin computation. All circuits share some
-- input and output memories, therefore is not possible to make a pipeline of this 3 phases.
-- First circuit, syndrome_calculator_n_pipe_v3, computes the syndrome from the ciphertext
-- and private keys, support L and polynomial g(x) (In this case g(L)^-1).
-- Second circuit, solving_key_equation_4, computes polynomial sigma through
-- the syndrome computed by first circuit.
-- Third circuit, find_and_correct_errors_n and polynomial_evaluator_n_v2, find the roots
-- of polynomial sigma and correct respective errors in the ciphertext and obtains
-- plaintext array.
-- Inversion circuit, inv_gf_2_m_pipeline, is only used during solving_key_equation_4.
-- This circuit was made outside of solving_key_equation_4 so it can be used by other circuits.
--
-- The circuits parameters
--
-- number_of_syndrome_and_find_units :
--
-- The number of pipelines in find_correct_errors_n, polynomial_evaluator_n_v2 and
-- syndrome_calculator_n_pipe_v3 circuits. The number of pipelines is shared between the root
-- finding process and syndrome computation. This happens because of how shared memories.
-- This number can be 1 or greater, however, tests for this unit were only made for 1 and 2.
--
-- syndrome_calculator_units :
--
-- The number of units inside of each syndrome pipeline computational unit.
-- This number can be 1 or greater.
--
-- find_correct_errors_pipeline_size :
--
-- This is the number of stages on the find_correct_errors_n and polynomial_evaluator_n_v2
-- circuits. This number can be 2 or greater.
--
-- find_correct_errors_size_pipeline_size :
--
-- The number of bits necessary to hold the number of stages on the pipeline.
-- This is ceil(log2(find_correct_errors_pipeline_size))
--
-- gf_2_m :
--
-- The size of the finite field extension used in this circuit.
-- This values depends of the Goppa code used.
--
-- length_codeword :
--
-- The length of the codeword in this Goppa code.
-- This values depends of the Goppa code used.
--
-- size_codeword :
--
-- The number of bits necessary to store an array of codeword lengths.
-- This is ceil(log2(length_codeword))
--
-- number_of_errors :
--
-- The number of errors the Goppa code is able to decode.
-- This values depends of the Goppa code used.
--
-- size_number_of_errors :
--
-- The number of bits necessary to store an array of number of errors + 1 length.
-- This is ceil(log2(number_of_errors+1))
--
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- syndrome_calculator_n_pipe_v3 Rev 1.0
-- solving_key_equation_4 Rev 1.0
-- find_and_correct_errors_n Rev 1.0
-- polynomial_evaluator_n_v2 Rev 1.0
-- inv_gf_2_m_pipeline Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity mceliece_qd_goppa_decrypt is
Generic(
-- GOPPA [2048, 1751, 27, 11] --
-- number_of_syndrome_and_find_units : integer := 1;
-- syndrome_calculator_units : integer := 2;
-- find_correct_errors_pipeline_size : integer := 2;
-- find_correct_errors_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 11;
-- length_codeword : integer := 2048;
-- size_codeword : integer := 11;
-- number_of_errors : integer := 27;
-- size_number_of_errors : integer := 5
-- GOPPA [2048, 1498, 50, 11] --
-- number_of_syndrome_and_find_units : integer := 1;
-- syndrome_calculator_units : integer := 2;
-- find_correct_errors_pipeline_size : integer := 2;
-- find_correct_errors_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 11;
-- length_codeword : integer := 2048;
-- size_codeword : integer := 11;
-- number_of_errors : integer := 50;
-- size_number_of_errors : integer := 6
-- GOPPA [3307, 2515, 66, 12] --
-- number_of_syndrome_and_find_units : integer := 1;
-- syndrome_calculator_units : integer := 2;
-- find_correct_errors_pipeline_size : integer := 2;
-- find_correct_errors_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 3307;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 66;
-- size_number_of_errors : integer := 7
-- QD-GOPPA [2528, 2144, 32, 12] --
-- number_of_syndrome_and_find_units : integer := 1;
-- syndrome_calculator_units : integer := 2;
-- find_correct_errors_pipeline_size : integer := 2;
-- find_correct_errors_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 2528;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 32;
-- size_number_of_errors : integer := 6
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_syndrome_and_find_units : integer := 2;
-- syndrome_calculator_units : integer := 1;
-- find_correct_errors_pipeline_size : integer := 2;
-- find_correct_errors_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 2816;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 64;
-- size_number_of_errors : integer := 7
-- QD-GOPPA [3328, 2560, 64, 12] --
number_of_syndrome_and_find_units : integer := 2;
syndrome_calculator_units : integer := 2;
find_correct_errors_pipeline_size : integer := 17;
find_correct_errors_size_pipeline_size : integer := 5;
gf_2_m : integer range 1 to 20 := 12;
length_codeword : integer := 3328;
size_codeword : integer := 12;
number_of_errors : integer := 64;
size_number_of_errors : integer := 7
-- QD-GOPPA [7296, 5632, 128, 13] --
-- number_of_syndrome_and_find_units : integer := 1;
-- syndrome_calculator_units : integer := 2;
-- find_correct_errors_pipeline_size : integer := 2;
-- find_correct_errors_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 13;
-- length_codeword : integer := 7296;
-- size_codeword : integer := 13;
-- number_of_errors : integer := 128;
-- size_number_of_errors : integer := 8
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
value_h : in STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(gf_2_m) - 1) downto 0);
value_L : in STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(gf_2_m) - 1) downto 0);
value_syndrome : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_codeword : in STD_LOGIC_VECTOR((number_of_syndrome_and_find_units - 1) downto 0);
value_G : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_B : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_sigma : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_sigma_evaluated : in STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(gf_2_m) - 1) downto 0);
syndrome_generation_finalized : out STD_LOGIC;
key_equation_finalized : out STD_LOGIC;
decryption_finalized : out STD_LOGIC;
address_value_h : out STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(size_codeword) - 1) downto 0);
address_value_L : out STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(size_codeword) - 1) downto 0);
address_value_syndrome : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_codeword : out STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(size_codeword) - 1) downto 0);
address_value_G : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_B : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_sigma : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_sigma_evaluated : out STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(size_codeword) - 1) downto 0);
new_value_syndrome : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_G : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_B : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_sigma : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_message : out STD_LOGIC_VECTOR((number_of_syndrome_and_find_units - 1) downto 0);
new_value_error : out STD_LOGIC_VECTOR((number_of_syndrome_and_find_units - 1) downto 0);
new_value_sigma_evaluated : out STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(gf_2_m) - 1) downto 0);
write_enable_new_value_syndrome : out STD_LOGIC;
write_enable_new_value_G : out STD_LOGIC;
write_enable_new_value_B : out STD_LOGIC;
write_enable_new_value_sigma : out STD_LOGIC;
write_enable_new_value_message : out STD_LOGIC;
write_enable_new_value_error : out STD_LOGIC;
write_enable_new_value_sigma_evaluated : out STD_LOGIC;
address_new_value_syndrome : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_G : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_B : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_sigma : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_message : out STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(size_codeword) - 1) downto 0);
address_new_value_error : out STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(size_codeword) - 1) downto 0);
address_new_value_sigma_evaluated : out STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(size_codeword) - 1) downto 0)
);
end mceliece_qd_goppa_decrypt;
architecture Behavioral of mceliece_qd_goppa_decrypt is
component syndrome_calculator_n_pipe_v3
Generic(
number_of_syndrome_calculators : integer;
syndrome_calculator_size : integer;
gf_2_m : integer range 1 to 20;
length_codeword : integer;
size_codeword : integer;
length_syndrome : integer;
size_syndrome : integer
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
value_h : in STD_LOGIC_VECTOR(((number_of_syndrome_calculators)*(gf_2_m) - 1) downto 0);
value_L : in STD_LOGIC_VECTOR(((number_of_syndrome_calculators)*(gf_2_m) - 1) downto 0);
value_syndrome : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_codeword : in STD_LOGIC_VECTOR((number_of_syndrome_calculators - 1) downto 0);
syndrome_finalized : out STD_LOGIC;
write_enable_new_syndrome : out STD_LOGIC;
new_value_syndrome : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
address_h : out STD_LOGIC_VECTOR(((number_of_syndrome_calculators)*(size_codeword) - 1) downto 0);
address_L : out STD_LOGIC_VECTOR(((number_of_syndrome_calculators)*(size_codeword) - 1) downto 0);
address_codeword : out STD_LOGIC_VECTOR(((number_of_syndrome_calculators)*(size_codeword) - 1) downto 0);
address_syndrome : out STD_LOGIC_VECTOR((size_syndrome - 1) downto 0);
address_new_syndrome : out STD_LOGIC_VECTOR((size_syndrome - 1) downto 0)
);
end component;
component solving_key_equation_4
Generic(
gf_2_m : integer range 1 to 20;
final_degree : integer;
size_final_degree : integer
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
ready_inv : in STD_LOGIC;
value_F : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_G : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_B : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_C : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_inv : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal_inv : out STD_LOGIC;
key_equation_found : out STD_LOGIC;
write_enable_F : out STD_LOGIC;
write_enable_G : out STD_LOGIC;
write_enable_B : out STD_LOGIC;
write_enable_C : out STD_LOGIC;
new_value_inv : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_F : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_B : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_G : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_C : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
address_value_F : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_value_G : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_value_B : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_value_C : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_F : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_G : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_B : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_C : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0)
);
end component;
component find_correct_errors_n
Generic (
number_of_pipelines : integer;
pipeline_size : integer;
gf_2_m : integer range 1 to 20;
length_support_elements: integer;
size_support_elements : integer
);
Port(
value_message : in STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
value_evaluated : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
address_value_evaluated : in STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
enable_correction : in STD_LOGIC;
evaluation_finalized : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
correction_finalized : out STD_LOGIC;
address_new_value_message : out STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
address_value_error : out STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
write_enable_new_value_message : out STD_LOGIC;
write_enable_value_error : out STD_LOGIC;
new_value_message : out STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
value_error : out STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0)
);
end component;
component inv_gf_2_m_pipeline
Generic(gf_2_m : integer range 1 to 20 := 13);
Port(
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
flag : in STD_LOGIC;
clk : in STD_LOGIC;
oflag : out STD_LOGIC;
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
component polynomial_evaluator_n_v2
Generic (
number_of_pipelines : integer;
pipeline_size : integer;
size_pipeline_size : integer;
gf_2_m : integer range 1 to 20;
polynomial_degree : integer;
size_polynomial_degree : integer;
number_of_values_x: integer;
size_number_of_values_x : integer
);
Port(
value_x : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
value_polynomial : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
last_evaluations : out STD_LOGIC;
evaluation_finalized : out STD_LOGIC;
address_value_polynomial : out STD_LOGIC_VECTOR((size_polynomial_degree - 1) downto 0);
address_value_x : out STD_LOGIC_VECTOR((size_number_of_values_x - 1) downto 0);
address_value_acc : out STD_LOGIC_VECTOR((size_number_of_values_x - 1) downto 0);
address_new_value_acc : out STD_LOGIC_VECTOR((size_number_of_values_x - 1) downto 0);
write_enable_new_value_acc : out STD_LOGIC;
new_value_acc : out STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0)
);
end component;
signal syndrome_calculator_rst : STD_LOGIC;
signal syndrome_calculator_value_h : STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(gf_2_m) - 1) downto 0);
signal syndrome_calculator_value_L : STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(gf_2_m) - 1) downto 0);
signal syndrome_calculator_value_syndrome : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal syndrome_calculator_value_codeword : STD_LOGIC_VECTOR((number_of_syndrome_and_find_units - 1) downto 0);
signal syndrome_calculator_syndrome_finalized : STD_LOGIC;
signal syndrome_calculator_write_enable_new_syndrome : STD_LOGIC;
signal syndrome_calculator_new_value_syndrome : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal syndrome_calculator_address_h : STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(size_codeword) - 1) downto 0);
signal syndrome_calculator_address_L : STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(size_codeword) - 1) downto 0);
signal syndrome_calculator_address_codeword : STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(size_codeword) - 1) downto 0);
signal syndrome_calculator_address_syndrome : STD_LOGIC_VECTOR((size_number_of_errors) downto 0);
signal syndrome_calculator_address_new_syndrome : STD_LOGIC_VECTOR((size_number_of_errors) downto 0);
signal solving_key_equation_rst : STD_LOGIC;
signal solving_key_equation_value_F : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_value_G : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_value_B : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_value_C : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_key_equation_found : STD_LOGIC;
signal solving_key_equation_write_enable_F : STD_LOGIC;
signal solving_key_equation_write_enable_G : STD_LOGIC;
signal solving_key_equation_write_enable_B : STD_LOGIC;
signal solving_key_equation_write_enable_C : STD_LOGIC;
signal solving_key_equation_new_value_F : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_new_value_B : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_new_value_G : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_new_value_C : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_address_value_F : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_value_G : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_value_B : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_value_C : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_new_value_F : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_new_value_G : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_new_value_B : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_new_value_C : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal find_correct_errors_value_message : STD_LOGIC_VECTOR((number_of_syndrome_and_find_units - 1) downto 0);
signal find_correct_errors_value_evaluated : STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(gf_2_m) - 1) downto 0);
signal find_correct_errors_address_value_evaluated : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal find_correct_errors_enable_correction : STD_LOGIC;
signal find_correct_errors_evaluation_finalized : STD_LOGIC;
signal find_correct_errors_correction_finalized : STD_LOGIC;
signal find_correct_errors_rst : STD_LOGIC;
signal find_correct_errors_address_new_value_message : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal find_correct_errors_address_new_value_message_complete : STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(size_codeword) - 1) downto 0);
signal find_correct_errors_address_value_error : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal find_correct_errors_address_value_error_complete : STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(size_codeword) - 1) downto 0);
signal find_correct_errors_write_enable_new_value_message : STD_LOGIC;
signal find_correct_errors_write_enable_value_error : STD_LOGIC;
signal find_correct_errors_new_value_message : STD_LOGIC_VECTOR((number_of_syndrome_and_find_units - 1) downto 0);
signal find_correct_errors_value_error : STD_LOGIC_VECTOR((number_of_syndrome_and_find_units - 1) downto 0);
signal inv_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal inv_flag : STD_LOGIC;
signal inv_oflag : STD_LOGIC;
signal inv_o : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal polynomial_evaluator_value_x : STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(gf_2_m) - 1) downto 0);
signal polynomial_evaluator_value_acc : STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(gf_2_m) - 1) downto 0);
signal polynomial_evaluator_value_polynomial : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal polynomial_evaluator_rst : STD_LOGIC;
signal polynomial_evaluator_last_evaluations : STD_LOGIC;
signal polynomial_evaluator_evaluation_finalized : STD_LOGIC;
signal polynomial_evaluator_address_value_polynomial : STD_LOGIC_VECTOR((size_number_of_errors - 1) downto 0);
signal polynomial_evaluator_address_value_x : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal polynomial_evaluator_address_value_x_complete : STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(size_codeword) - 1) downto 0);
signal polynomial_evaluator_address_value_acc : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal polynomial_evaluator_address_value_acc_complete : STD_LOGIC_VECTOR((((number_of_syndrome_and_find_units)*(size_codeword)) - 1) downto 0);
signal polynomial_evaluator_address_new_value_acc : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal polynomial_evaluator_address_new_value_acc_complete : STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(size_codeword) - 1) downto 0);
signal polynomial_evaluator_write_enable_new_value_acc : STD_LOGIC;
signal polynomial_evaluator_new_value_acc : STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(gf_2_m) - 1) downto 0);
begin
syndrome_calculator : syndrome_calculator_n_pipe_v3
Generic Map(
number_of_syndrome_calculators => number_of_syndrome_and_find_units,
syndrome_calculator_size => syndrome_calculator_units,
gf_2_m => gf_2_m,
length_codeword => length_codeword,
size_codeword => size_codeword,
length_syndrome => 2*number_of_errors,
size_syndrome => size_number_of_errors + 1
)
Port Map(
clk => clk,
rst => syndrome_calculator_rst,
value_h => syndrome_calculator_value_h,
value_L => syndrome_calculator_value_L,
value_syndrome => syndrome_calculator_value_syndrome,
value_codeword => syndrome_calculator_value_codeword,
syndrome_finalized => syndrome_calculator_syndrome_finalized,
write_enable_new_syndrome => syndrome_calculator_write_enable_new_syndrome,
new_value_syndrome => syndrome_calculator_new_value_syndrome,
address_h => syndrome_calculator_address_h,
address_L => syndrome_calculator_address_L,
address_codeword => syndrome_calculator_address_codeword,
address_syndrome => syndrome_calculator_address_syndrome,
address_new_syndrome => syndrome_calculator_address_new_syndrome
);
solving_key_equation : solving_key_equation_4
Generic Map(
gf_2_m => gf_2_m,
final_degree => number_of_errors,
size_final_degree => size_number_of_errors
)
Port Map(
clk => clk,
rst => solving_key_equation_rst,
ready_inv => inv_oflag,
value_F => solving_key_equation_value_F,
value_G => solving_key_equation_value_G,
value_B => solving_key_equation_value_B,
value_C => solving_key_equation_value_C,
value_inv => inv_o,
signal_inv => inv_flag,
key_equation_found => solving_key_equation_key_equation_found,
write_enable_F => solving_key_equation_write_enable_F,
write_enable_G => solving_key_equation_write_enable_G,
write_enable_B => solving_key_equation_write_enable_B,
write_enable_C => solving_key_equation_write_enable_C,
new_value_inv => inv_a,
new_value_F => solving_key_equation_new_value_F,
new_value_B => solving_key_equation_new_value_B,
new_value_G => solving_key_equation_new_value_G,
new_value_C => solving_key_equation_new_value_C,
address_value_F => solving_key_equation_address_value_F,
address_value_G => solving_key_equation_address_value_G,
address_value_B => solving_key_equation_address_value_B,
address_value_C => solving_key_equation_address_value_C,
address_new_value_F => solving_key_equation_address_new_value_F,
address_new_value_G => solving_key_equation_address_new_value_G,
address_new_value_B => solving_key_equation_address_new_value_B,
address_new_value_C => solving_key_equation_address_new_value_C
);
find_correct_errors : find_correct_errors_n
Generic Map(
number_of_pipelines => number_of_syndrome_and_find_units,
pipeline_size => find_correct_errors_pipeline_size,
gf_2_m => gf_2_m,
length_support_elements => length_codeword,
size_support_elements => size_codeword
)
Port Map(
value_message => find_correct_errors_value_message,
value_evaluated => find_correct_errors_value_evaluated,
address_value_evaluated => find_correct_errors_address_value_evaluated,
enable_correction => find_correct_errors_enable_correction,
evaluation_finalized => find_correct_errors_evaluation_finalized,
clk => clk,
rst => find_correct_errors_rst,
correction_finalized => find_correct_errors_correction_finalized,
address_new_value_message => find_correct_errors_address_new_value_message,
address_value_error => find_correct_errors_address_value_error,
write_enable_new_value_message => find_correct_errors_write_enable_new_value_message,
write_enable_value_error => find_correct_errors_write_enable_value_error,
new_value_message => find_correct_errors_new_value_message,
value_error => find_correct_errors_value_error
);
inverter : inv_gf_2_m_pipeline
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => inv_a,
flag => inv_flag,
clk => clk,
oflag => inv_oflag,
o => inv_o
);
polynomial_evaluator : polynomial_evaluator_n_v2
Generic Map(
number_of_pipelines => number_of_syndrome_and_find_units,
pipeline_size => find_correct_errors_pipeline_size,
size_pipeline_size => find_correct_errors_size_pipeline_size,
gf_2_m => gf_2_m,
polynomial_degree => number_of_errors,
size_polynomial_degree => size_number_of_errors,
number_of_values_x => length_codeword,
size_number_of_values_x => size_codeword
)
Port Map(
value_x => polynomial_evaluator_value_x,
value_acc => polynomial_evaluator_value_acc,
value_polynomial => polynomial_evaluator_value_polynomial,
clk => clk,
rst => polynomial_evaluator_rst,
last_evaluations => polynomial_evaluator_last_evaluations,
evaluation_finalized => polynomial_evaluator_evaluation_finalized,
address_value_polynomial => polynomial_evaluator_address_value_polynomial,
address_value_x => polynomial_evaluator_address_value_x,
address_value_acc => polynomial_evaluator_address_value_acc,
address_new_value_acc => polynomial_evaluator_address_new_value_acc,
write_enable_new_value_acc => polynomial_evaluator_write_enable_new_value_acc,
new_value_acc => polynomial_evaluator_new_value_acc
);
syndrome_calculator_rst <= rst;
syndrome_calculator_value_h <= value_h;
syndrome_calculator_value_L <= value_L;
syndrome_calculator_value_syndrome <= value_syndrome;
syndrome_calculator_value_codeword <= value_codeword;
solving_key_equation_rst <= not syndrome_calculator_syndrome_finalized;
solving_key_equation_value_F <= value_syndrome;
solving_key_equation_value_G <= value_G;
solving_key_equation_value_B <= value_B;
solving_key_equation_value_C <= value_sigma;
find_correct_errors_rst <= not solving_key_equation_key_equation_found;
find_correct_errors_value_message <= value_codeword;
find_correct_errors_value_evaluated <= polynomial_evaluator_new_value_acc;
find_correct_errors_address_value_evaluated <= polynomial_evaluator_address_new_value_acc;
find_correct_errors_enable_correction <= polynomial_evaluator_last_evaluations;
find_correct_errors_evaluation_finalized <= polynomial_evaluator_evaluation_finalized;
polynomial_evaluator_rst <= not solving_key_equation_key_equation_found;
polynomial_evaluator_value_x <= value_L;
polynomial_evaluator_value_acc <= value_sigma_evaluated;
polynomial_evaluator_value_polynomial <= value_sigma;
syndrome_generation_finalized <= syndrome_calculator_syndrome_finalized;
key_equation_finalized <= solving_key_equation_key_equation_found;
decryption_finalized <= syndrome_calculator_syndrome_finalized and solving_key_equation_key_equation_found and find_correct_errors_correction_finalized;
address_value_h <= syndrome_calculator_address_h;
address_value_L <= polynomial_evaluator_address_value_x_complete when syndrome_calculator_syndrome_finalized = '1' else
syndrome_calculator_address_h;
address_value_syndrome <= solving_key_equation_address_value_F when syndrome_calculator_syndrome_finalized = '1' else
"0" & syndrome_calculator_address_syndrome;
address_value_codeword <= polynomial_evaluator_address_value_x_complete when syndrome_calculator_syndrome_finalized = '1' else
syndrome_calculator_address_codeword;
address_value_G <= solving_key_equation_address_value_G;
address_value_B <= solving_key_equation_address_value_B;
address_value_sigma <= "00" & polynomial_evaluator_address_value_polynomial when solving_key_equation_key_equation_found = '1' else
solving_key_equation_address_value_C;
address_value_sigma_evaluated <= polynomial_evaluator_address_value_acc_complete;
new_value_syndrome <= solving_key_equation_new_value_F when syndrome_calculator_syndrome_finalized = '1' else
syndrome_calculator_new_value_syndrome;
new_value_G <= solving_key_equation_new_value_G;
new_value_B <= solving_key_equation_new_value_B;
new_value_sigma <= solving_key_equation_new_value_C;
new_value_message <= find_correct_errors_new_value_message;
new_value_error <= find_correct_errors_value_error;
new_value_sigma_evaluated <= polynomial_evaluator_new_value_acc;
write_enable_new_value_syndrome <= solving_key_equation_write_enable_F when syndrome_calculator_syndrome_finalized = '1' else
syndrome_calculator_write_enable_new_syndrome;
write_enable_new_value_G <= solving_key_equation_write_enable_G;
write_enable_new_value_B <= solving_key_equation_write_enable_B;
write_enable_new_value_sigma <= solving_key_equation_write_enable_C;
write_enable_new_value_message <= find_correct_errors_write_enable_new_value_message;
write_enable_new_value_error <= find_correct_errors_write_enable_value_error;
write_enable_new_value_sigma_evaluated <= polynomial_evaluator_write_enable_new_value_acc;
address_new_value_syndrome <= solving_key_equation_address_new_value_F when syndrome_calculator_syndrome_finalized = '1' else
"0" & syndrome_calculator_address_new_syndrome;
address_new_value_G <= solving_key_equation_address_new_value_G;
address_new_value_B <= solving_key_equation_address_new_value_B;
address_new_value_sigma <= solving_key_equation_address_new_value_C;
address_new_value_message <= find_correct_errors_address_new_value_message_complete;
address_new_value_error <= find_correct_errors_address_value_error_complete;
address_new_value_sigma_evaluated <= polynomial_evaluator_address_new_value_acc_complete;
resolve_address : for I in 0 to (number_of_syndrome_and_find_units - 1) generate
polynomial_evaluator_address_value_x_complete(((I+1)*size_codeword - 1) downto (I*size_codeword)) <= std_logic_vector(unsigned(polynomial_evaluator_address_value_x) + to_unsigned(I, size_codeword));
polynomial_evaluator_address_value_acc_complete(((I+1)*size_codeword - 1) downto (I*size_codeword)) <= std_logic_vector(unsigned(polynomial_evaluator_address_value_acc) + to_unsigned(I, size_codeword));
find_correct_errors_address_new_value_message_complete(((I+1)*size_codeword - 1) downto (I*size_codeword)) <= std_logic_vector(unsigned(find_correct_errors_address_new_value_message) + to_unsigned(I, size_codeword));
find_correct_errors_address_value_error_complete(((I+1)*size_codeword - 1) downto (I*size_codeword)) <= std_logic_vector(unsigned(find_correct_errors_address_value_error) + to_unsigned(I, size_codeword));
polynomial_evaluator_address_new_value_acc_complete(((I+1)*size_codeword - 1) downto (I*size_codeword)) <= std_logic_vector(unsigned(polynomial_evaluator_address_new_value_acc) + to_unsigned(I, size_codeword));
end generate;
end Behavioral;
| bsd-2-clause | 30ba4c56a54420a0b5d9922af85fb149 | 0.719931 | 3.103315 | false | false | false | false |
dtysky/3D_Displayer_Controller | VHDL/PLL1.vhd | 1 | 19,529 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: PLL1.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY PLL1 IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END PLL1;
ARCHITECTURE SYN OF pll1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
clk3_divide_by : NATURAL;
clk3_duty_cycle : NATURAL;
clk3_multiply_by : NATURAL;
clk3_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire8_bv(0 DOWNTO 0) <= "0";
sub_wire8 <= To_stdlogicvector(sub_wire8_bv);
sub_wire5 <= sub_wire0(2);
sub_wire4 <= sub_wire0(0);
sub_wire2 <= sub_wire0(3);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
c3 <= sub_wire2;
locked <= sub_wire3;
c0 <= sub_wire4;
c2 <= sub_wire5;
sub_wire6 <= inclk0;
sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 10,
clk0_duty_cycle => 50,
clk0_multiply_by => 7,
clk0_phase_shift => "0",
clk1_divide_by => 10,
clk1_duty_cycle => 50,
clk1_multiply_by => 7,
clk1_phase_shift => "0",
clk2_divide_by => 10,
clk2_duty_cycle => 50,
clk2_multiply_by => 7,
clk2_phase_shift => "0",
clk3_divide_by => 10,
clk3_duty_cycle => 50,
clk3_multiply_by => 7,
clk3_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=PLL1",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_USED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
inclk => sub_wire7,
clk => sub_wire0,
locked => sub_wire3
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "5"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "5"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "5"
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "5"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "35.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "35.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "35.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "35.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4"
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "4"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "35.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "35.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "35.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "35.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "PLL1.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "10"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "7"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "10"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "7"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "10"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "7"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "10"
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "7"
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL1.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL1.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| gpl-2.0 | 1fd485c4d3bf99252b8eb84f3e98df24 | 0.699985 | 3.260267 | false | false | false | false |
Xero-Hige/LuGus-VHDL | TPS-2016/tps-LuGus/TP2-Voltimetro/generic_counter.vhd | 2 | 1,065 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity generic_counter is
generic (
BITS:natural := 4;
MAX_COUNT:natural := 15
);
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
counter_out: out std_logic_vector(BITS-1 downto 0);
carry_out: out std_logic
);
end;
architecture generic_counter_arq of generic_counter is
begin
--El comportamiento se puede hacer de forma logica o por diagrama karnaugh.
process(clk,rst)
variable tmp_count: integer range 0 to MAX_COUNT+1;
begin
if rst = '1' then
counter_out <= (others => '0');
carry_out <= '0';
tmp_count := 0;
elsif rising_edge(clk) then
if ena = '1' then
tmp_count:=tmp_count + 1;
if tmp_count = MAX_COUNT then
carry_out <= '1';
elsif tmp_count = MAX_COUNT+1 then
tmp_count := 0;
carry_out <= '0';
else
carry_out <= '0';
end if;
end if;
end if;
counter_out <= std_logic_vector(TO_UNSIGNED(tmp_count,BITS));
end process;
end; | gpl-3.0 | 7110598b44900adf3606067e5d4c6c79 | 0.602817 | 2.941989 | false | false | false | false |
Xero-Hige/LuGus-VHDL | TPS-2016/tps-Gaston/TP1-Contador/tp1_circuit.vhd | 1 | 3,492 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tp1 is
port (
clk_in: in std_logic;
rst_in: in std_logic;
clk_anode_ouput: out std_logic_vector(3 downto 0);
clk_led_output: out std_logic_vector(7 downto 0)
);
attribute loc: string;
attribute loc of clk_in: signal is "B8";
attribute loc of rst_in: signal is "B18";
attribute loc of clk_anode_ouput: signal is "F15 C18 H17 F17";
attribute loc of clk_led_output: signal is "L18 F18 D17 D16 G14 J17 H14 C17";
end;
architecture tp1_arq of tp1 is
signal enabler_output : std_logic := '0';
signal bcd0_out : std_logic_vector(3 downto 0) := (others => '0');
signal bcd1_out : std_logic_vector(3 downto 0) := (others => '0');
signal bcd2_out : std_logic_vector(3 downto 0) := (others => '0');
signal bcd3_out : std_logic_vector(3 downto 0) := (others => '0');
signal co_bcd0 : std_logic := '0';
signal co_bcd1 : std_logic := '0';
signal co_bcd2 : std_logic := '0';
signal co_bcd3 : std_logic := '0';
signal bcd1_en : std_logic := '0';
signal bcd2_en : std_logic := '0';
signal bcd3_en : std_logic := '0';
component led_display_controller is
port (
clk_in: in std_logic;
bcd0: in std_logic_vector(3 downto 0);
bcd1: in std_logic_vector(3 downto 0);
bcd2: in std_logic_vector(3 downto 0);
bcd3: in std_logic_vector(3 downto 0);
anode_output: out std_logic_vector(3 downto 0);
led_output: out std_logic_vector(7 downto 0)
);
end component;
component bcd_counter is
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
counter_out: out std_logic_vector(3 downto 0);
carry_out: out std_logic
);
end component;
component generic_enabler is
generic(
PERIOD:natural := 1000000 --1MHz
);
port(
clk: in std_logic;
rst: in std_logic;
enabler_out: out std_logic
);
end component;
begin
bcd1_en <= co_bcd0 and enabler_output;
bcd2_en <= co_bcd1 and bcd1_en;
bcd3_en <= co_bcd2 and bcd2_en;
generic_enablerMap: generic_enabler
generic map(50000000)
port map (
clk => clk_in,
rst => '0',
enabler_out => enabler_output
);
bcd_counter0Map: bcd_counter
port map(
clk => clk_in,
rst => rst_in,
ena => enabler_output,
counter_out => bcd0_out,
carry_out => co_bcd0
);
bcd_counter1Map: bcd_counter
port map(
clk => clk_in,
rst => rst_in,
ena => bcd1_en,
counter_out => bcd1_out,
carry_out => co_bcd1
);
bcd_counter2Map: bcd_counter
port map(
clk => clk_in,
rst => rst_in,
ena => bcd2_en,
counter_out => bcd2_out,
carry_out => co_bcd2
);
bcd_counter3Map: bcd_counter
port map(
clk => clk_in,
rst => rst_in,
ena => bcd3_en,
counter_out => bcd3_out,
carry_out => co_bcd3
);
led_display_controllerMap: led_display_controller
port map (
clk_in => clk_in,
bcd0 => bcd0_out,
bcd1 => bcd1_out,
bcd2 => bcd2_out,
bcd3 => bcd3_out,
anode_output => clk_anode_ouput,
led_output => clk_led_output
);
end;
| gpl-3.0 | 4caef40bd09b0a283855a2017fd21a04 | 0.54181 | 3.239332 | false | false | false | false |
sxpert/magic1 | MicrocodeControl.vhd | 1 | 2,223 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:57:48 02/02/2016
-- Design Name:
-- Module Name: MicrocodeControl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MicrocodeControl is
Port ( I_nRESET : in STD_LOGIC;
I_CLKM : in STD_LOGIC;
O_LATCH : out STD_LOGIC_VECTOR (3 downto 0);
O_NEXT : out STD_LOGIC_VECTOR (7 downto 0)
);
end MicrocodeControl;
architecture Behavioral of MicrocodeControl is
type t_ucs_latch is array (0 to 15) of STD_LOGIC_VECTOR (3 downto 0);
type t_ucs_next is array (0 to 15) of STD_LOGIC_VECTOR (7 downto 0);
-- represents the microcode storage
signal ucs_latch : t_ucs_latch := (
"0001", "0100", "0010", "0110", "0011", "0000", "0111", "0101", others => "1000");
signal ucs_next: t_ucs_next := (
"00000001","00000010","00000011","00000101",
"00000101","00000110","00000111","00000000",
others => "00000000");
-- microcode latch
signal l_LATCH: STD_LOGIC_VECTOR (3 downto 0) := "0000";
signal l_NEXT: STD_LOGIC_VECTOR (7 downto 0) := "00000000";
begin
process (I_CLKM, I_nRESET, l_LATCH, l_NEXT) is
begin
if I_nRESET='0' then
-- reset is asserted. everything is 0
l_LATCH <= "0000";
l_NEXT <= "00000000";
else
if rising_edge (I_CLKM) then
-- generate the next value in a variable
-- reset is 1, normal functionning
l_LATCH <= ucs_latch(to_integer(unsigned(l_NEXT(4 downto 0))));
l_NEXT <= ucs_next(to_integer(unsigned(l_NEXT(4 downto 0))));
end if;
end if;
O_LATCH <= l_LATCH;
O_NEXT <= l_NEXT;
end process;
end Behavioral;
| gpl-3.0 | bfbdd8a429a8eeed2de09a0a0c390c8c | 0.616284 | 3.468019 | false | false | false | false |
Xero-Hige/LuGus-VHDL | TP3/addition/sign_computer/sign_computer_tb.vhd | 1 | 3,609 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sign_computer_tb is
end entity;
architecture sign_computer_tb_arq of sign_computer_tb is
signal man_1_in: std_logic_vector(15 downto 0) := (others => '0');
signal man_2_in: std_logic_vector(15 downto 0) := (others => '0');
signal sign_1_in: std_logic := '0';
signal sign_2_in: std_logic := '0';
signal man_greater_in: std_logic_vector(15 downto 0) := (others => '0');
signal pre_complemented_result: std_logic_vector(16 downto 0) := (others => '0');
signal complemented_result: std_logic_vector(16 downto 0) := (others => '0');
signal sign_out: std_logic := '0';
component sign_computer is
generic(
BITS : natural := 16
);
port(
man_1_in: in std_logic_vector(BITS - 1 downto 0) := (others => '0');
man_2_in: in std_logic_vector(BITS - 1 downto 0) := (others => '0');
sign_1_in: in std_logic := '0';
sign_2_in: in std_logic := '0';
man_greater_in: in std_logic_vector(BITS - 1 downto 0) := (others => '0');
pre_complemented_result: in std_logic_vector(BITS downto 0) := (others => '0');
complemented_result: in std_logic_vector(BITS downto 0) := (others => '0');
sign_out: out std_logic := '0'
);
end component;
for sign_computer_0 : sign_computer use entity work.sign_computer;
begin
sign_computer_0 : sign_computer
generic map(BITS => 16)
port map(
man_1_in => man_1_in,
man_2_in => man_2_in,
sign_1_in => sign_1_in,
sign_2_in => sign_2_in,
man_greater_in => man_greater_in,
pre_complemented_result => pre_complemented_result,
complemented_result => complemented_result,
sign_out => sign_out
);
process
type pattern_type is record
m1 : std_logic_vector(15 downto 0);
m2 : std_logic_vector(15 downto 0);
s1 : std_logic;
s2 : std_logic;
mg : std_logic_vector(15 downto 0);
pcr : std_logic_vector(16 downto 0);
cr : std_logic_vector(16 downto 0);
so : std_logic;
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array := (
("0000000000000000","0000000000000000",'0','0',"0000000000000000","00000000000000000","00000000000000000",'0'),
("0000000000000000","0000000000000000",'1','1',"0000000000000000","00000000000000000","00000000000000000",'1'),
("0000000000000000","1111111111111111",'0','1',"1111111111111111","00000000000000000","00000000000000000",'1'),
("0000000000000000","1111111111111111",'1','0',"1111111111111111","00000000000000000","00000000000000000",'0'),
("0000000000000000","1111111111111111",'0','1',"0000000000000000","00000000000000000","00000000000000000",'0'),
("0000000000000000","1111111111111111",'1','0',"0000000000000000","00000000000000000","00000000000000000",'1'),
("0000000000000000","1111111111111111",'0','1',"0000000000000000","00000000000000000","00000000000000000",'0'),
("0000000000000000","1111111111111111",'1','0',"0000000000000000","00000000000000000","00000000000000000",'1')
);
begin
for i in patterns'range loop
-- Set the inputs.
man_1_in <= patterns(i).m1;
man_2_in <= patterns(i).m2;
sign_1_in <= patterns(i).s1;
sign_2_in <= patterns(i).s2;
man_greater_in <= patterns(i).mg;
pre_complemented_result <= patterns(i).pcr;
complemented_result <= patterns(i).cr;
wait for 1 ms;
assert patterns(i).so = sign_out report "BAD RESULT, GOT: " & std_logic'image(sign_out);
-- Check the outputs.
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
| gpl-3.0 | add152314fb5908bde650302aad56131 | 0.658631 | 3.344764 | false | false | false | false |
pmassolino/hw-goppa-mceliece | mceliece/backup/solving_key_equation_1_v2.vhd | 1 | 22,450 | ----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Solving_Key_Equation_1_v2
-- Module Name: Solving_Key_Equation_1_v2
-- Project Name: McEliece QD-Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 2nd step in Goppa Code Decoding.
--
-- This circuit solves the polynomial key equation sigma with the polynomial syndrome.
-- To solve the key equation, this circuit employs a modified extended euclidean algorithm
-- The modification is made to stop the algorithm when polynomial, represented here as G, has
-- degree less or equal than the polynomial key equation sigma desired degree.
-- The syndrome is the input and expected to be of degree 2*final_degree, and after computations
-- polynomial C, will hold sigma with degree less or equal to final_degree.
--
-- This is the second circuit version. It is a non pipeline version of the algorithm,
-- each coefficient takes more than 1 cycle to be computed.
-- A more optimized version with a pipeline approach was made called solving_key_equation_2.
--
-- Parameters
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- final_degree :
--
-- The final degree size expected for polynomial sigma to have. This parameter depends
-- of the Goppa code used.
--
-- size_final_degree :
--
-- The number of bits necessary to hold the polynomial with degree of final_degree, which
-- has final_degree + 1 coefficients. This is ceil(log2(final_degree+1)).
--
-- Dependencies:
--
-- VHDL-93
--
-- controller_solving_key_equation_1_v2 Rev 1.0
-- register_nbits Rev 1.0
-- register_rst_nbits Rev 1.0
-- counter_decrement_load_nbits Rev 1.0
-- counter_decrement_load_rst_nbits Rev 1.0
-- mult_gf_2_m Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity solving_key_equation_1_v2 is
Generic(
-- GOPPA [2048, 1751, 27, 11] --
gf_2_m : integer range 1 to 20 := 11;
final_degree : integer := 27;
size_final_degree : integer := 5
-- GOPPA [2048, 1498, 50, 11] --
-- gf_2_m : integer range 1 to 20 := 11;
-- final_degree : integer := 50;
-- size_final_degree : integer := 6
-- GOPPA [3307, 2515, 66, 12] --
-- gf_2_m : integer range 1 to 20 := 11;
-- final_degree : integer := 50;
-- size_final_degree : integer := 6
-- QD-GOPPA [2528, 2144, 32, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 32;
-- size_final_degree : integer := 5
-- QD-GOPPA [2816, 2048, 64, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 64;
-- size_final_degree : integer := 6
-- QD-GOPPA [3328, 2560, 64, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 64;
-- size_final_degree : integer := 6
-- QD-GOPPA [7296, 5632, 128, 13] --
-- gf_2_m : integer range 1 to 20 := 13;
-- final_degree : integer := 128;
-- size_final_degree : integer := 7
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
ready_inv : in STD_LOGIC;
value_FB : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_GC : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_inv : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal_inv : out STD_LOGIC;
key_equation_found : out STD_LOGIC;
write_enable_FB : out STD_LOGIC;
write_enable_GC : out STD_LOGIC;
new_value_inv : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_FB : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_GC : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
address_FB : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_GC : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0)
);
end solving_key_equation_1_v2;
architecture Behavioral of solving_key_equation_1_v2 is
component controller_solving_key_equation_1_v2
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
FB_equal_zero : in STD_LOGIC;
i_equal_zero : in STD_LOGIC;
i_minus_j_less_than_zero : in STD_LOGIC;
degree_G_less_equal_final_degree : in STD_LOGIC;
degree_F_less_than_degree_G : in STD_LOGIC;
degree_B_equal_degree_C_plus_j : in STD_LOGIC;
degree_B_less_than_degree_C_plus_j : in STD_LOGIC;
reg_looking_degree_q : in STD_LOGIC_VECTOR(0 downto 0);
key_equation_found : out STD_LOGIC;
signal_inv : out STD_LOGIC;
sel_new_value_inv : out STD_LOGIC;
write_enable_FB : out STD_LOGIC;
write_enable_GC : out STD_LOGIC;
sel_base_mul : out STD_LOGIC;
reg_h_ce : out STD_LOGIC;
ctr_i_ce : out STD_LOGIC;
ctr_i_load : out STD_LOGIC;
ctr_i_rst : out STD_LOGIC;
sel_ctr_i_rst_value : out STD_LOGIC;
sel_ctr_i_d : out STD_LOGIC;
reg_j_ce : out STD_LOGIC;
reg_j_rst : out STD_LOGIC;
reg_FB_ce : out STD_LOGIC;
reg_FB_rst : out STD_LOGIC;
sel_reg_FB : out STD_LOGIC;
sel_load_new_value_FB : out STD_LOGIC;
reg_GC_ce : out STD_LOGIC;
reg_GC_rst : out STD_LOGIC;
sel_reg_GC : out STD_LOGIC;
ctr_degree_F_ce : out STD_LOGIC;
ctr_degree_F_load : out STD_LOGIC;
ctr_degree_F_rst : out STD_LOGIC;
reg_degree_G_ce : out STD_LOGIC;
reg_degree_G_rst : out STD_LOGIC;
ctr_degree_B_ce : out STD_LOGIC;
ctr_degree_B_load : out STD_LOGIC;
ctr_degree_B_rst : out STD_LOGIC;
sel_ctr_degree_B : out STD_LOGIC;
reg_degree_C_ce : out STD_LOGIC;
reg_degree_C_rst : out STD_LOGIC;
reg_looking_degree_d : out STD_LOGIC_VECTOR(0 downto 0);
reg_looking_degree_ce : out STD_LOGIC;
reg_swap_ce : out STD_LOGIC;
reg_swap_rst : out STD_LOGIC;
sel_address_FB : out STD_LOGIC;
sel_address_GC : out STD_LOGIC;
ctr_address_FB_ce : out STD_LOGIC;
ctr_address_FB_load : out STD_LOGIC;
ctr_address_GC_ce : out STD_LOGIC;
ctr_address_GC_load : out STD_LOGIC;
BC_calculation : out STD_LOGIC;
enable_external_swap : out STD_LOGIC
);
end component;
component register_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component register_rst_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_decrement_load_rst_nbits
Generic (
size : integer;
decrement_value : integer
);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
load : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0)
);
end component;
component counter_decrement_load_nbits
Generic (
size : integer;
decrement_value : integer
);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
load : in STD_LOGIC;
q : out STD_LOGIC_VECTOR((size - 1) downto 0)
);
end component;
component mult_gf_2_m
Generic (gf_2_m : integer range 1 to 20 := 11);
Port (
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
b: in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
signal base_mult_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal base_mult_b : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal base_mult_o : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal sel_base_mul : STD_LOGIC;
signal reg_h_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_h_ce : STD_LOGIC;
signal reg_h_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_inv_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_inv_ce : STD_LOGIC;
signal reg_inv_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal ctr_i_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_i_ce : STD_LOGIC;
signal ctr_i_load : STD_LOGIC;
signal ctr_i_rst : STD_LOGIC;
signal ctr_i_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_i_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal sel_ctr_i_d : STD_LOGIC;
signal sel_ctr_i_rst_value : STD_LOGIC;
constant ctr_i_rst_value_F : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(2*final_degree - 1,size_final_degree + 2));
constant ctr_i_rst_value_B : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(final_degree,size_final_degree + 2));
signal reg_j_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_j_ce : STD_LOGIC;
signal reg_j_rst : STD_LOGIC;
signal reg_j_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(0,size_final_degree + 2));
signal reg_j_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_FB_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_FB_ce : STD_LOGIC;
signal reg_FB_rst : STD_LOGIC;
constant reg_FB_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others=> '0');
signal reg_FB_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal sel_reg_FB : STD_LOGIC;
signal reg_GC_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_GC_ce : STD_LOGIC;
signal reg_GC_rst : STD_LOGIC;
constant reg_GC_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others=> '0');
signal reg_GC_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal sel_reg_GC : STD_LOGIC;
signal ctr_degree_F_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_degree_F_ce : STD_LOGIC;
signal ctr_degree_F_load : STD_LOGIC;
signal ctr_degree_F_rst : STD_LOGIC;
constant ctr_degree_F_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(2*final_degree - 1,size_final_degree + 2));
signal ctr_degree_F_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_degree_G_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_degree_G_ce : STD_LOGIC;
signal reg_degree_G_rst : STD_LOGIC;
constant reg_degree_G_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(2*final_degree,size_final_degree + 2));
signal reg_degree_G_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_degree_B_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_degree_B_ce : STD_LOGIC;
signal ctr_degree_B_load : STD_LOGIC;
signal ctr_degree_B_rst : STD_LOGIC;
constant ctr_degree_B_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(0,size_final_degree + 2));
signal ctr_degree_B_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal sel_ctr_degree_B : STD_LOGIC;
signal reg_degree_C_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_degree_C_ce : STD_LOGIC;
signal reg_degree_C_rst : STD_LOGIC;
constant reg_degree_C_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(0,size_final_degree + 2));
signal reg_degree_C_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_looking_degree_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_looking_degree_ce : STD_LOGIC;
signal reg_looking_degree_q : STD_LOGIC_VECTOR(0 downto 0);
signal reg_swap_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_swap_ce : STD_LOGIC;
signal reg_swap_rst : STD_LOGIC;
constant reg_swap_rst_value : STD_LOGIC_VECTOR(0 downto 0) := "0";
signal reg_swap_q : STD_LOGIC_VECTOR(0 downto 0);
signal i_minus_j : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal degree_C_plus_j : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal int_value_FB : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal int_value_GC : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal sel_load_new_value_FB : STD_LOGIC;
signal int_new_value_FB : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal int_new_value_GC : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal int_write_enable_FB : STD_LOGIC;
signal int_write_enable_GC : STD_LOGIC;
signal address_i_FB : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal address_degree_F : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal address_degree_G : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal address_i_minus_j_GC : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal sel_address_FB : STD_LOGIC;
signal sel_address_GC : STD_LOGIC;
signal ctr_address_FB_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_address_FB_ce : STD_LOGIC;
signal ctr_address_FB_load : STD_LOGIC;
signal ctr_address_FB_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_address_GC_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_address_GC_ce : STD_LOGIC;
signal ctr_address_GC_load : STD_LOGIC;
signal ctr_address_GC_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal BC_calculation : STD_LOGIC;
signal enable_external_swap : STD_LOGIC;
signal sel_new_value_inv : STD_LOGIC;
signal FB_equal_zero : STD_LOGIC;
signal i_equal_zero : STD_LOGIC;
signal i_minus_j_less_than_zero : STD_LOGIC;
signal degree_G_less_equal_final_degree : STD_LOGIC;
signal degree_F_less_than_degree_G : STD_LOGIC;
signal degree_B_equal_degree_C_plus_j : STD_LOGIC;
signal degree_B_less_than_degree_C_plus_j : STD_LOGIC;
begin
controller : controller_solving_key_equation_1_v2
Port Map(
clk => clk,
rst => rst,
FB_equal_zero => FB_equal_zero,
i_equal_zero => i_equal_zero,
i_minus_j_less_than_zero => i_minus_j_less_than_zero,
degree_G_less_equal_final_degree => degree_G_less_equal_final_degree,
degree_F_less_than_degree_G => degree_F_less_than_degree_G,
degree_B_equal_degree_C_plus_j => degree_B_equal_degree_C_plus_j,
degree_B_less_than_degree_C_plus_j => degree_B_less_than_degree_C_plus_j,
reg_looking_degree_q => reg_looking_degree_q,
key_equation_found => key_equation_found,
signal_inv => signal_inv,
sel_new_value_inv => sel_new_value_inv,
write_enable_FB => int_write_enable_FB,
write_enable_GC => int_write_enable_GC,
sel_base_mul => sel_base_mul,
reg_h_ce => reg_h_ce,
ctr_i_ce => ctr_i_ce,
ctr_i_load => ctr_i_load,
ctr_i_rst => ctr_i_rst,
sel_ctr_i_rst_value => sel_ctr_i_rst_value,
sel_ctr_i_d => sel_ctr_i_d,
reg_j_ce => reg_j_ce,
reg_j_rst => reg_j_rst,
reg_FB_ce => reg_FB_ce,
reg_FB_rst => reg_FB_rst,
sel_reg_FB => sel_reg_FB,
sel_load_new_value_FB => sel_load_new_value_FB,
reg_GC_ce => reg_GC_ce,
reg_GC_rst => reg_GC_rst,
sel_reg_GC => sel_reg_GC,
ctr_degree_F_ce => ctr_degree_F_ce,
ctr_degree_F_load => ctr_degree_F_load,
ctr_degree_F_rst => ctr_degree_F_rst,
reg_degree_G_ce => reg_degree_G_ce,
reg_degree_G_rst => reg_degree_G_rst,
ctr_degree_B_ce => ctr_degree_B_ce,
ctr_degree_B_load => ctr_degree_B_load,
ctr_degree_B_rst => ctr_degree_B_rst,
sel_ctr_degree_B => sel_ctr_degree_B,
reg_degree_C_ce => reg_degree_C_ce,
reg_degree_C_rst => reg_degree_C_rst,
reg_looking_degree_d => reg_looking_degree_d,
reg_looking_degree_ce => reg_looking_degree_ce,
reg_swap_ce => reg_swap_ce,
reg_swap_rst => reg_swap_rst,
sel_address_FB => sel_address_FB,
sel_address_GC => sel_address_GC,
ctr_address_FB_ce => ctr_address_FB_ce,
ctr_address_FB_load => ctr_address_FB_load,
ctr_address_GC_ce => ctr_address_GC_ce,
ctr_address_GC_load => ctr_address_GC_load,
BC_calculation => BC_calculation,
enable_external_swap => enable_external_swap
);
base_mult : mult_gf_2_m
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => base_mult_a,
b => base_mult_b,
o => base_mult_o
);
reg_h : register_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_h_d,
clk => clk,
ce => reg_h_ce,
q => reg_h_q
);
reg_inv : register_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_inv_d,
clk => clk,
ce => reg_inv_ce,
q => reg_inv_q
);
ctr_i : counter_decrement_load_rst_nbits
Generic Map(
size => size_final_degree+2,
decrement_value => 1
)
Port Map(
d => ctr_i_d,
clk => clk,
ce => ctr_i_ce,
load => ctr_i_load,
rst => ctr_i_rst,
rst_value => ctr_i_rst_value,
q => ctr_i_q
);
reg_j : register_rst_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_j_d,
clk => clk,
ce => reg_j_ce,
rst => reg_j_rst,
rst_value => reg_j_rst_value,
q => reg_j_q
);
reg_FB : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_FB_d,
clk => clk,
rst => reg_FB_rst,
rst_value => reg_FB_rst_value,
ce => reg_FB_ce,
q => reg_FB_q
);
reg_GC : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_GC_d,
clk => clk,
rst => reg_GC_rst,
rst_value => reg_GC_rst_value,
ce => reg_GC_ce,
q => reg_GC_q
);
ctr_degree_F : counter_decrement_load_rst_nbits
Generic Map(
size => size_final_degree+2,
decrement_value => 1
)
Port Map(
d => ctr_degree_F_d,
clk => clk,
ce => ctr_degree_F_ce,
load => ctr_degree_F_load,
rst => ctr_degree_F_rst,
rst_value => ctr_degree_F_rst_value,
q => ctr_degree_F_q
);
reg_degree_G : register_rst_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_degree_G_d,
clk => clk,
rst => reg_degree_G_rst,
rst_value => reg_degree_G_rst_value,
ce => reg_degree_G_ce,
q => reg_degree_G_q
);
ctr_degree_B : counter_decrement_load_rst_nbits
Generic Map(
size => size_final_degree+2,
decrement_value => 1
)
Port Map(
d => ctr_degree_B_d,
clk => clk,
ce => ctr_degree_B_ce,
load => ctr_degree_B_load,
rst => ctr_degree_B_rst,
rst_value => ctr_degree_B_rst_value,
q => ctr_degree_B_q
);
reg_degree_C : register_rst_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_degree_C_d,
clk => clk,
rst => reg_degree_C_rst,
rst_value => reg_degree_C_rst_value,
ce => reg_degree_C_ce,
q => reg_degree_C_q
);
ctr_address_FB : counter_decrement_load_nbits
Generic Map(
size => size_final_degree+2,
decrement_value => 1
)
Port Map(
d => ctr_address_FB_d,
clk => clk,
ce => ctr_address_FB_ce,
load => ctr_address_FB_load,
q => ctr_address_FB_q
);
ctr_address_GC : counter_decrement_load_nbits
Generic Map(
size => size_final_degree+2,
decrement_value => 1
)
Port Map(
d => ctr_address_GC_d,
clk => clk,
ce => ctr_address_GC_ce,
load => ctr_address_GC_load,
q => ctr_address_GC_q
);
reg_looking_degree : register_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_looking_degree_d,
clk => clk,
ce => reg_looking_degree_ce,
q => reg_looking_degree_q
);
reg_swap : register_rst_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_swap_d,
clk => clk,
ce => reg_swap_ce,
rst => reg_swap_rst,
rst_value => reg_swap_rst_value,
q => reg_swap_q
);
base_mult_a <= reg_inv_q when sel_base_mul = '1' else
reg_h_q;
base_mult_b <= reg_FB_q when sel_base_mul = '1' else
reg_GC_q;
reg_h_d <= base_mult_o;
reg_inv_d <= value_inv;
reg_inv_ce <= ready_inv;
ctr_i_d <= ctr_degree_F_q when sel_ctr_i_d = '1' else
degree_C_plus_j;
ctr_i_rst_value <= ctr_i_rst_value_F when sel_ctr_i_rst_value = '1' else
ctr_i_rst_value_B;
reg_j_d <= std_logic_vector(unsigned(ctr_degree_F_q) - unsigned(reg_degree_G_q));
reg_FB_d <= (base_mult_o xor reg_FB_q) when sel_load_new_value_FB = '1' else
std_logic_vector(to_unsigned(1, reg_FB_d'length)) when sel_reg_FB = '1' else
int_value_FB;
reg_GC_d <= std_logic_vector(to_unsigned(1, reg_GC_d'length)) when sel_reg_GC = '1' else
int_value_GC;
ctr_degree_F_d <= reg_degree_G_q;
reg_degree_G_d <= ctr_degree_F_q;
ctr_degree_B_d <= degree_C_plus_j when sel_ctr_degree_B = '1' else
reg_degree_C_q;
degree_C_plus_j <= std_logic_vector(unsigned(reg_degree_C_q) + unsigned(reg_j_q));
i_minus_j <= std_logic_vector(unsigned(ctr_i_q) - unsigned(reg_j_q));
reg_degree_C_d <= ctr_degree_B_q;
reg_swap_d <= not reg_swap_q;
int_new_value_FB <= reg_FB_q;
int_new_value_GC <= reg_GC_q;
int_value_FB <= value_GC when reg_swap_q = "1" else value_FB;
int_value_GC <= value_FB when reg_swap_q = "1" else value_GC;
new_value_inv <= int_new_value_FB when sel_new_value_inv = '1' else
int_new_value_GC;
new_value_FB <= int_new_value_GC when (reg_swap_q(0) and enable_external_swap) = '1' else int_new_value_FB;
new_value_GC <= int_new_value_FB when (reg_swap_q(0) and enable_external_swap) = '1' else int_new_value_GC;
write_enable_FB <= int_write_enable_GC when (reg_swap_q(0) and enable_external_swap) = '1' else int_write_enable_FB;
write_enable_GC <= int_write_enable_FB when (reg_swap_q(0) and enable_external_swap) = '1' else int_write_enable_GC;
address_i_FB <= std_logic_vector(to_unsigned(2*final_degree + 1, address_i_FB'length) + unsigned(ctr_i_q)) when BC_calculation = '1' else
ctr_i_q;
address_degree_F <= ctr_degree_F_q;
address_degree_G <= reg_degree_G_q;
address_i_minus_j_GC <= std_logic_vector(to_unsigned(2*final_degree + 1, address_i_minus_j_GC'length) + unsigned(i_minus_j)) when BC_calculation = '1' else
i_minus_j;
ctr_address_FB_d <= address_degree_F when sel_address_FB = '1' else
address_i_FB;
ctr_address_GC_d <= address_degree_G when sel_address_GC = '1' else
address_i_minus_j_GC;
address_FB <= ctr_address_GC_q when (reg_swap_q(0) and enable_external_swap) = '1' else ctr_address_FB_q;
address_GC <= ctr_address_FB_q when (reg_swap_q(0) and enable_external_swap) = '1' else ctr_address_GC_q;
FB_equal_zero <= '1' when (int_new_value_FB = std_logic_vector(to_unsigned(0,reg_FB_q'length))) else '0';
i_equal_zero <= '1' when (ctr_i_q = std_logic_vector(to_unsigned(0,ctr_i_q'length))) else '0';
i_minus_j_less_than_zero <= '1' when (signed(i_minus_j) < to_signed(0,i_minus_j'length)) else '0';
degree_G_less_equal_final_degree <= '1' when (unsigned(reg_degree_G_q) <= to_unsigned(final_degree-1,reg_degree_G_q'length)) else '0';
degree_F_less_than_degree_G <= '1' when (unsigned(ctr_degree_F_q) < unsigned(reg_degree_G_q)) else '0';
degree_B_equal_degree_C_plus_j <= '1' when (ctr_degree_B_q = degree_C_plus_j) else '0';
degree_B_less_than_degree_C_plus_j <= '1' when (unsigned(ctr_degree_B_q) < unsigned(degree_C_plus_j)) else '0';
end Behavioral;
| bsd-2-clause | ae61a898b92dc0fb62ca285725b9cc64 | 0.654254 | 2.568356 | false | false | false | false |
pmassolino/hw-goppa-mceliece | mceliece/util/ram_file.vhd | 1 | 4,218 | ----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: RAM
-- Module Name: RAM_File
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Circuit to simulate the behavioral of a memory RAM. Only used for tests.
--
-- The circuits parameters
--
-- ram_address_size :
--
-- Address size of the RAM used on the circuit.
--
-- ram_word_size :
--
-- The size of internal word on the RAM.
--
-- file_ram_word_size :
--
-- The size of the word used in the file to be loaded on the RAM.(ARCH: FILE_LOAD)
--
-- load_file_name :
--
-- The name of file to be loaded.(ARCH: FILE_LOAD)
--
-- dump_file_name :
--
-- The name of the file to be used to dump the memory.(ARCH: FILE_LOAD)
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD.ALL;
-- IEEE.STD_LOGIC_TEXTIO.ALL;
-- STD.TEXTIO.ALL;
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
architecture file_load of ram is
type ramtype is array(0 to (2**ram_address_size - 1)) of std_logic_vector((ram_word_size - 1) downto 0);
pure function load_ram (ram_file_name : in string) return ramtype is
FILE ram_file : text is in ram_file_name;
variable line_n : line;
variable memory_ram : ramtype;
variable file_read_buffer : std_logic_vector((file_ram_word_size - 1) downto 0);
variable file_buffer_amount : integer;
variable ram_buffer_amount : integer;
begin
file_buffer_amount := file_ram_word_size;
for I in ramtype'range loop
ram_buffer_amount := 0;
if (not endfile(ram_file) or (file_buffer_amount /= file_ram_word_size)) then
while ram_buffer_amount /= ram_word_size loop
if file_buffer_amount = file_ram_word_size then
if (not endfile(ram_file)) then
readline (ram_file, line_n);
read (line_n, file_read_buffer);
else
file_read_buffer := (others => '0');
end if;
file_buffer_amount := 0;
end if;
memory_ram(I)(ram_buffer_amount) := file_read_buffer(file_buffer_amount);
ram_buffer_amount := ram_buffer_amount + 1;
file_buffer_amount := file_buffer_amount + 1;
end loop;
else
memory_ram(I) := (others => '0');
end if;
end loop;
return memory_ram;
end function;
procedure dump_ram (ram_file_name : in string; memory_ram : in ramtype) is
FILE ram_file : text is out ram_file_name;
variable line_n : line;
begin
for I in ramtype'range loop
write (line_n, memory_ram(I));
writeline (ram_file, line_n);
end loop;
end procedure;
signal memory_ram : ramtype := load_ram(load_file_name);
begin
process (clk)
begin
if clk'event and clk = '1' then
if rst = '1' then
memory_ram <= load_ram(load_file_name);
end if;
if dump = '1' then
dump_ram(dump_file_name, memory_ram);
end if;
if rw = '1' then
memory_ram(to_integer(unsigned(address))) <= data_in;
end if;
data_out <= memory_ram(to_integer(unsigned(address)));
end if;
end process;
end file_load; | bsd-2-clause | 787b16dbbb24966fd5e5e51545d11a57 | 0.470365 | 4.111111 | false | false | false | false |
pwuertz/digitizer2fw | src/rtl/division_lut.vhd | 1 | 1,853 | -------------------------------------------------------------------------------
-- Division lookup table for unsigned values
--
-- Author: Peter Würtz, TU Kaiserslautern (2016)
-- Distributed under the terms of the GNU General Public License Version 3.
-- The full license is in the file COPYING.txt, distributed with this software.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity division_lut is
generic (ROUND_FLOAT: boolean := TRUE);
port (
clk: in std_logic;
clk_en: in std_logic;
divisor: in unsigned;
result: out unsigned
);
end division_lut;
architecture division_lut_arch of division_lut is
constant N_DIVISOR_BITS: natural := divisor'length;
constant N_RESULT_BITS: natural := result'length;
type lut_t is array(0 to 2**N_DIVISOR_BITS-1) of unsigned(N_RESULT_BITS-1 downto 0);
function init_func return lut_t is
constant factor: real := real(2**(N_RESULT_BITS-1));
variable frac: real;
variable frac_repr: natural;
variable result: lut_t;
begin
result(0) := to_unsigned(0, (N_RESULT_BITS));
for I in 1 to lut_t'high loop
frac := 1.0/real(I);
if ROUND_FLOAT then
frac_repr := natural(round(frac*factor));
else
frac_repr := natural(floor(frac*factor));
end if;
result(I) := to_unsigned(frac_repr, N_RESULT_BITS);
end loop;
return result;
end function;
constant lut: lut_t := init_func;
begin
process(clk)
begin
if rising_edge(clk) then
if clk_en = '1' then
result <= lut(to_integer(divisor));
end if;
end if;
end process;
end division_lut_arch;
| gpl-3.0 | 752f246876db08f9256468e6b63986b6 | 0.565335 | 3.948827 | false | false | false | false |
Xero-Hige/LuGus-VHDL | TPS-2016/tps-Lucho/TP1-Contador/FFD_tb.vhd | 2 | 759 | library IEEE;
use IEEE.std_logic_1164.all;
entity FFD_tb is
end;
architecture FFD_sim of FFD_tb is
signal d_in: std_logic:='0';
signal rst_in: std_logic:='0';
signal enable_in: std_logic:='0';
signal clk_in: std_logic:='0';
signal q_out: std_logic:='0';
component FFD is
port(
enable: in std_logic;
reset: in std_logic;
clk: in std_logic;
Q: out std_logic;
D: in std_logic
);
end component;
begin
clk_in <= not clk_in after 20 ns;
d_in <= not(d_in) after 40 ns;
enable_in <= not(enable_in) after 80 ns;
rst_in <= not(rst_in) after 160 ns;
FDDmap: FFD port map(
clk => clk_in,
reset => rst_in,
enable => enable_in,
D => d_in,
Q => q_out
);
end architecture;
| gpl-3.0 | b657ea4a506bdf89276ecd8260239d47 | 0.581028 | 2.653846 | false | false | false | false |
Xero-Hige/LuGus-VHDL | TPS-2016/relocate/gen_ena.vhd | 1 | 471 | library ieee;
use ieee.std_logic_ll64.all;
entity gen_ena is
port{
clk: in std_logic;
rst: in std_logic;
ena: out std_logic;
};
end;
architecture gen_ena_arq of gen_ena is
variable count: integer := 0;
begin
cont: process(clk)
begin
if rst = '1' then
ena := '0';
elsif rising_edge(clk) then
count := count + 1;
if count = '10' then
count := 0;
ena := '1';
else
ena := 0;
end if;
end if;
end; | gpl-3.0 | 0bba119f426b447d532a2bbe8a2e7ff2 | 0.55414 | 2.646067 | false | false | false | false |
Xero-Hige/LuGus-VHDL | TP3/addition/adder_tester/adder_tester_tb.vhd | 1 | 4,526 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity adder_tester_tb is
file TEST_FILE : text open READ_MODE is "testing_files/test_sum_float_23_6.txt";
constant TOTAL_BITS : integer := 23;
constant EXP_BITS : integer := 6;
constant PIPELINE_STEPS : integer := 6;
end entity;
architecture adder_tester_tb_arq of adder_tester_tb is
signal enable_in : std_logic := '0';
signal reset_in : std_logic := '0';
signal clk_in : std_logic := '0';
signal number_1_in : std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
signal number_2_in : std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
signal result : std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
signal expected_result_before : std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
signal expected_result_after : std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
component floating_point_adder is
generic(
TOTAL_BITS : natural := 23;
EXP_BITS : natural := 6
);
port(
enable : in std_logic;
reset : in std_logic;
clk : in std_logic;
number_1_in : in std_logic_vector(TOTAL_BITS - 1 downto 0);
number_2_in : in std_logic_vector(TOTAL_BITS - 1 downto 0);
result: out std_logic_vector(TOTAL_BITS - 1 downto 0)
);
end component;
component shift_register is
generic(REGISTRY_BITS : integer := 32;
STEPS : integer := 4);
port(
enable: in std_logic;
reset: in std_logic;
clk: in std_logic;
D: in std_logic_vector(REGISTRY_BITS - 1 downto 0);
Q: out std_logic_vector(REGISTRY_BITS - 1 downto 0)
);
end component;
for floating_point_adder_0 : floating_point_adder use entity work.floating_point_adder;
for shift_register_0 : shift_register use entity work.shift_register;
begin
shift_register_0 : shift_register
generic map(REGISTRY_BITS => TOTAL_BITS, STEPS => PIPELINE_STEPS + 1)
port map(
enable => enable_in,
reset => reset_in,
clk => clk_in,
D => expected_result_before,
Q => expected_result_after
);
floating_point_adder_0 : floating_point_adder
generic map(TOTAL_BITS => TOTAL_BITS, EXP_BITS => EXP_BITS)
port map(
enable => enable_in,
reset => reset_in,
clk => clk_in,
number_1_in => number_1_in,
number_2_in => number_2_in,
result => result
);
process
variable in_line : line;
variable number1_in : integer;
variable number2_in : integer;
variable precomputed_result_before : integer;
variable precomputed_result_after : integer;
variable to_integer_result : integer;
variable i : integer := 0;
begin
enable_in <= '1';
clk_in <= '0';
while not endfile(TEST_FILE) loop
readline(TEST_FILE, in_line);
read(in_line, number1_in);
read(in_line, number2_in);
read(in_line, precomputed_result_before);
--report "NUMBER 1: " & integer'image(number1_in);
--report "NUMBER 2: " & integer'image(number2_in);
number_1_in <= std_logic_vector(to_unsigned(number1_in, TOTAL_BITS));
number_2_in <= std_logic_vector(to_unsigned(number2_in, TOTAL_BITS));
expected_result_before <= std_logic_vector(to_unsigned(precomputed_result_before, TOTAL_BITS));
--One clock cycle
clk_in <= '1';
wait for 1 ns;
to_integer_result := to_integer(unsigned(result));
precomputed_result_after := to_integer(unsigned(expected_result_after));
--report "REGISTRY RESULT: " & integer'image(precomputed_result_after) & " ADDER RESULT: " & integer'image(to_integer_result);
if(i > PIPELINE_STEPS) then --dont compare in the first iterations because garbage leaves the registers
assert precomputed_result_after = to_integer_result report "EXPECTED: " & integer'image(precomputed_result_after) & " ACTUAL: " & integer'image(to_integer_result);
end if;
clk_in <= '0';
wait for 1 ns;
i := i + 1;
end loop;
--Compare remainder values
for i in 0 to PIPELINE_STEPS loop
clk_in <= '1';
wait for 100 ms;
to_integer_result := to_integer(unsigned(result));
precomputed_result_after := to_integer(unsigned(expected_result_after));
--report "REGISTRY RESULT: " & integer'image(precomputed_result_after) & " ADDER RESULT: " & integer'image(to_integer_result);
assert precomputed_result_after = to_integer_result report "EXPECTED: " & integer'image(precomputed_result_after) & " ACTUAL: " & integer'image(to_integer_result);
clk_in <= '0';
wait for 1 ns;
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
| gpl-3.0 | da6722b0bc20fcd4ee38173752c4d7ac | 0.670128 | 3.087312 | false | true | false | false |
ruygargar/LCSE_lab | PIC/PICtop.vhd | 1 | 3,919 |
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.PIC_pkg.all;
entity PICtop is
port (
Reset : in std_logic; -- Asynchronous, active low
Clk : in std_logic; -- System clock, 20 MHz, rising_edge
RS232_RX : in std_logic; -- RS232 RX line
RS232_TX : out std_logic; -- RS232 TX line
Switches : out std_logic_vector(7 downto 0); -- Switch status bargraph
Temp_L : out std_logic_vector(6 downto 0); -- Less significant figure of T_STAT
Temp_H : out std_logic_vector(6 downto 0)); -- Most significant figure of T_STAT
end PICtop;
architecture behavior of PICtop is
COMPONENT peripherics
PORT(
Clk : IN std_logic;
Reset : IN std_logic;
RX : IN std_logic;
Send : IN std_logic;
DMA_ACK : IN std_logic;
Databus : INOUT std_logic_vector(7 downto 0);
Address : INOUT std_logic_vector(7 downto 0);
ChipSelect : INOUT std_logic;
WriteEnable : INOUT std_logic;
OutputEnable : INOUT std_logic;
TX : OUT std_logic;
Ready : OUT std_logic;
DMA_RQ : OUT std_logic;
Switches : OUT std_logic_vector(7 downto 0);
Temp_L : OUT std_logic_vector(6 downto 0);
Temp_H : OUT std_logic_vector(6 downto 0)
);
END COMPONENT;
COMPONENT ROM
PORT(
Program_counter : IN std_logic_vector(11 downto 0);
Instruction : OUT std_logic_vector(11 downto 0)
);
END COMPONENT;
COMPONENT uc
PORT(
Clk : IN std_logic;
Reset : IN std_logic;
ROM_Data : IN std_logic_vector(11 downto 0);
ALU_Index : IN std_logic_vector(7 downto 0);
Flag_Z : IN std_logic;
Flag_C : IN std_logic;
Flag_N : IN std_logic;
Flag_E : IN std_logic;
DMA_RQ : IN std_logic;
DMA_Ready : IN std_logic;
ROM_Address : OUT std_logic_vector(11 downto 0);
Databus : OUT std_logic_vector(7 downto 0);
RAM_Address : OUT std_logic_vector(7 downto 0);
RAM_CS : OUT std_logic;
RAM_WE : OUT std_logic;
RAM_OE : OUT std_logic;
ALU_Operation : OUT alu_op;
DMA_ACK : OUT std_logic;
Send : OUT std_logic
);
END COMPONENT;
COMPONENT alu
PORT(
Clk : IN std_logic;
Reset : IN std_logic;
u_instruction : IN alu_op;
Databus : INOUT std_logic_vector(7 downto 0);
FlagZ : OUT std_logic;
FlagC : OUT std_logic;
FlagN : OUT std_logic;
FlagE : OUT std_logic;
Index : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
signal Instruction, IAddress : std_logic_vector(11 downto 0);
signal Databus, Address, Index : std_logic_vector(7 downto 0);
signal ChipSelect, WriteEnable, OutputEnable : std_logic;
signal Send, Ready, DMA_RQ, DMA_ACK : std_logic;
signal Operation : alu_op;
signal Flag_Z, Flag_C, Flag_N, Flag_E : std_logic;
begin -- behavior
Peripherics0: peripherics
port map (
Clk => Clk,
Reset => Reset,
TX => RS232_TX,
RX => RS232_RX,
Databus => Databus,
Address => Address,
ChipSelect => ChipSelect,
WriteEnable => WriteEnable,
OutputEnable => OutputEnable,
Send => Send,
Ready => Ready,
DMA_RQ => DMA_RQ,
DMA_ACK => DMA_ACK,
Switches => Switches,
Temp_L => Temp_L,
Temp_H => Temp_H
);
ROM0: ROM PORT MAP(
Instruction => Instruction,
Program_counter => IAddress
);
ALU0: alu PORT MAP(
Clk => Clk,
Reset => Reset,
u_instruction => Operation,
FlagZ => Flag_Z,
FlagC => Flag_C,
FlagN => Flag_N,
FlagE => Flag_E,
Index => Index,
Databus => Databus
);
UC0: uc PORT MAP(
Clk => Clk,
Reset => Reset,
ROM_Data => Instruction,
ROM_Address => IAddress,
Databus => Databus,
RAM_Address => Address,
RAM_CS => ChipSelect,
RAM_WE => WriteEnable,
RAM_OE => OutputEnable,
ALU_Operation => Operation,
ALU_Index => Index,
Flag_Z => Flag_Z,
Flag_C => Flag_C,
Flag_N => Flag_N,
Flag_E => Flag_E,
DMA_RQ => DMA_RQ,
DMA_ACK => DMA_ACK,
Send => Send,
DMA_Ready => Ready
);
end behavior;
| gpl-3.0 | fe43b83d854299b8ce792554612731f2 | 0.63358 | 2.946617 | false | false | false | false |
Xero-Hige/LuGus-VHDL | TP4/UART/receive.vhd | 1 | 2,602 | -----------------------------------------------
-- Receive State Machine --
-----------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity receive is
generic (
NDBits : natural := 8
);
port (
CLK : in std_logic;
RST : in std_logic;
Rx : in std_logic;
Dout : out std_logic_vector (NDBits-1 downto 0);
RxErr : out std_logic;
RxRdy : out std_logic;
Top16 : in std_logic;
ClrDiv : out std_logic;
TopRx : in std_logic
);
end;
architecture arch of receive is
signal Rx_Reg : std_logic_vector (NDBits-1 downto 0);
type State_Type is (Idle, Start_Rx, Edge_Rx, Shift_Rx, Stop_Rx, Rx_Ovf);
signal RxFsm : State_Type;
signal RxBitCnt : integer;
signal Sig_RxRdy : std_logic;
begin
RxRdy <= Sig_RxRdy;
Rx_FSM: process (RST, CLK)
begin
if RST='1' then
Rx_Reg <= (others => '0');
Dout <= (others => '0');
RxBitCnt <= 0;
RxFSM <= Idle;
Sig_RxRdy <= '0';
ClrDiv <= '0';
RxErr <= '0';
elsif rising_edge(CLK) then
ClrDiv <= '0'; -- default value
-- reset error when a word has been received Ok:
if Sig_RxRdy='1' then
RxErr <= '0';
Sig_RxRdy <= '0';
end if;
case RxFSM is
when Idle => -- wait on start bit
RxBitCnt <= 0;
if Top16='1' then
if Rx='0' then
RxFSM <= Start_Rx;
ClrDiv <='1'; -- Synchronize the divisor
end if; -- else false start, stay in Idle
end if;
when Start_Rx => -- wait on first data bit
if TopRx = '1' then
if Rx='1' then -- framing error
RxFSM <= Rx_OVF;
report "Start bit error." severity note;
else
RxFSM <= Edge_Rx;
end if;
end if;
when Edge_Rx => -- should be near Rx edge
if TopRx = '1' then
RxFSM <= Shift_Rx;
if RxBitCnt = NDbits then
RxFSM <= Stop_Rx;
else
RxFSM <= Shift_Rx;
end if;
end if;
when Shift_Rx => -- Sample data !
if TopRx = '1' then
RxBitCnt <= RxBitCnt + 1;
-- shift right :
Rx_Reg <= Rx & Rx_Reg (Rx_Reg'high downto 1);
RxFSM <= Edge_Rx;
end if;
when Stop_Rx => -- during Stop bit
if TopRx = '1' then
Dout <= Rx_reg;
Sig_RxRdy <='1';
RxFSM <= Idle;
-- assert (debug < 1)
report "Character received in decimal is : "
& integer'image(to_integer(unsigned(Rx_Reg)))
severity note;
end if;
when Rx_OVF => -- Overflow / Error
RxErr <= '1';
if Rx='1' then
RxFSM <= Idle;
end if;
end case;
end if;
end process;
end architecture;
| gpl-3.0 | 28c9876370fe585ffffee94b60797640 | 0.536895 | 3.192638 | false | false | false | false |
pmassolino/hw-goppa-mceliece | mceliece/backup/syndrome_calculator_1.vhd | 1 | 11,443 | ----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Syndrome_Calculator_1
-- Module Name: Syndrome_Calculator_1
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 1st step in Goppa Code Decoding.
--
-- This circuit computes the syndrome from the ciphertext, support elements and
-- inverted evaluation of support elements into polynomial g, aka g(L)^(-1).
-- This circuit works by computing the syndrome of only the positions where the ciphertext
-- has value 1.
--
-- This is the first version which still has no optimizations or even variable number of
-- computation units. A version which exploits the parallelism called
-- syndrome_calculator_n.
--
-- The circuits parameters
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- length_codeword :
--
-- The length of the codeword or in this case the ciphertext. Both the codeword
-- and ciphertext has the same size.
--
-- size_codeword :
--
-- The number of bits necessary to hold the ciphertext/codeword.
-- This is ceil(log2(length_codeword)).
--
-- length_syndrome :
--
-- The size of the syndrome array. This parameter depends of the
-- Goppa code used.
--
-- size_syndrome :
--
-- The number of bits necessary to hold the array syndrome.
-- This is ceil(log2(length_syndrome)).
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- controller_syndrome_calculator_1 Rev 1.0
-- register_nbits Rev 1.0
-- register_rst_nbits Rev 1.0
-- counter_rst_nbits Rev 1.0
-- mult_gf_2_m Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity syndrome_calculator_1 is
Generic(
-- GOPPA [2048, 1751, 27, 11] --
gf_2_m : integer range 1 to 20 := 11;
length_codeword : integer := 2048;
size_codeword : integer := 11;
length_syndrome : integer := 54;
size_syndrome : integer := 6
-- GOPPA [2048, 1498, 50, 11] --
-- gf_2_m : integer range 1 to 20 := 11;
-- length_codeword : integer := 2048;
-- size_codeword : integer := 11;
-- length_syndrome : integer := 100;
-- size_syndrome : integer := 7
-- GOPPA [3307, 2515, 66, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 3307;
-- size_codeword : integer := 12;
-- length_syndrome : integer := 132;
-- size_syndrome : integer := 8
-- QD-GOPPA [2528, 2144, 32, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 2528;
-- size_codeword : integer := 12;
-- length_syndrome : integer := 64;
-- size_syndrome : integer := 7
-- QD-GOPPA [2816, 2048, 64, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 2816;
-- size_codeword : integer := 12;
-- length_syndrome : integer := 128;
-- size_syndrome : integer := 7
-- QD-GOPPA [3328, 2560, 64, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 3328;
-- size_codeword : integer := 12;
-- length_syndrome : integer := 128;
-- size_syndrome : integer := 7
-- QD-GOPPA [7296, 5632, 128, 13] --
-- gf_2_m : integer range 1 to 20 := 13;
-- length_codeword : integer := 7296;
-- size_codeword : integer := 13;
-- length_syndrome : integer := 256;
-- size_syndrome : integer := 8
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
value_h : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_L : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_syndrome : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_codeword : in STD_LOGIC_VECTOR(0 downto 0);
syndrome_finalized : out STD_LOGIC;
write_enable_new_syndrome : out STD_LOGIC;
new_value_syndrome : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
address_h : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_L : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_codeword : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_syndrome : out STD_LOGIC_VECTOR((size_syndrome - 1) downto 0)
);
end syndrome_calculator_1;
architecture Behavioral of syndrome_calculator_1 is
component controller_syndrome_calculator_1
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
limit_ctr_codeword_q : in STD_LOGIC;
limit_ctr_syndrome_q : in STD_LOGIC;
reg_first_syndrome_q : in STD_LOGIC_VECTOR(0 downto 0);
reg_codeword_q : in STD_LOGIC_VECTOR(0 downto 0);
syndrome_finalized : out STD_LOGIC;
write_enable_new_syndrome : out STD_LOGIC;
reg_L_ce : out STD_LOGIC;
square_h : out STD_LOGIC;
reg_h_ce : out STD_LOGIC;
sel_reg_h : out STD_LOGIC;
reg_syndrome_ce : out STD_LOGIC;
reg_syndrome_rst : out STD_LOGIC;
reg_codeword_ce : out STD_LOGIC;
reg_first_syndrome_ce : out STD_LOGIC;
reg_first_syndrome_rst : out STD_LOGIC;
ctr_syndrome_ce : out STD_LOGIC;
ctr_syndrome_rst : out STD_LOGIC;
ctr_codeword_ce : out STD_LOGIC;
ctr_codeword_rst : out STD_LOGIC
);
end component;
component register_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component register_rst_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_rst_nbits
Generic (
size : integer;
increment_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component mult_gf_2_m
Generic (gf_2_m : integer range 1 to 20 := 11);
Port (
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
b: in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
signal reg_L_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_L_ce : STD_LOGIC;
signal reg_L_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal square_h : STD_LOGIC;
signal reg_h_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_h_ce : STD_LOGIC;
signal reg_h_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal sel_reg_h : STD_LOGIC;
signal reg_syndrome_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_syndrome_ce : STD_LOGIC;
signal reg_syndrome_rst : STD_LOGIC;
constant reg_syndrome_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := std_logic_vector(to_unsigned(0, gf_2_m));
signal reg_syndrome_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_codeword_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_codeword_ce : STD_LOGIC;
signal reg_codeword_q : STD_LOGIC_VECTOR(0 downto 0);
signal reg_first_syndrome_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_first_syndrome_ce : STD_LOGIC;
signal reg_first_syndrome_rst : STD_LOGIC;
constant reg_first_syndrome_rst_value : STD_LOGIC_VECTOR(0 downto 0) := "1";
signal reg_first_syndrome_q : STD_LOGIC_VECTOR(0 downto 0);
signal mult_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mult_b : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mult_o : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal ctr_syndrome_ce : STD_LOGIC;
signal ctr_syndrome_rst : STD_LOGIC;
constant ctr_syndrome_rst_value : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0) := std_logic_vector(to_unsigned(0, size_syndrome));
signal ctr_syndrome_q : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0);
signal ctr_codeword_ce : STD_LOGIC;
signal ctr_codeword_rst : STD_LOGIC;
constant ctr_codeword_rst_value : STD_LOGIC_VECTOR((size_codeword - 1) downto 0) := std_logic_vector(to_unsigned(0, size_codeword));
signal ctr_codeword_q : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal limit_ctr_codeword_q : STD_LOGIC;
signal limit_ctr_syndrome_q : STD_LOGIC;
begin
controller : controller_syndrome_calculator_1
Port Map(
clk => clk,
rst => rst,
limit_ctr_codeword_q => limit_ctr_codeword_q,
limit_ctr_syndrome_q => limit_ctr_syndrome_q,
reg_first_syndrome_q => reg_first_syndrome_q,
reg_codeword_q => reg_codeword_q,
syndrome_finalized => syndrome_finalized,
write_enable_new_syndrome => write_enable_new_syndrome,
reg_L_ce => reg_L_ce,
square_h => square_h,
reg_h_ce => reg_h_ce,
sel_reg_h => sel_reg_h,
reg_syndrome_ce => reg_syndrome_ce,
reg_syndrome_rst => reg_syndrome_rst,
reg_codeword_ce => reg_codeword_ce,
reg_first_syndrome_ce => reg_first_syndrome_ce,
reg_first_syndrome_rst => reg_first_syndrome_rst,
ctr_syndrome_ce => ctr_syndrome_ce,
ctr_syndrome_rst => ctr_syndrome_rst,
ctr_codeword_ce => ctr_codeword_ce,
ctr_codeword_rst => ctr_codeword_rst
);
reg_L : register_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_L_d,
clk => clk,
ce => reg_L_ce,
q => reg_L_q
);
reg_h : register_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_h_d,
clk => clk,
ce => reg_h_ce,
q => reg_h_q
);
reg_syndrome : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_syndrome_d,
clk => clk,
ce => reg_syndrome_ce,
rst => reg_syndrome_rst,
rst_value => reg_syndrome_rst_value,
q => reg_syndrome_q
);
reg_codeword : register_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_codeword_d,
clk => clk,
ce => reg_codeword_ce,
q => reg_codeword_q
);
reg_first_syndrome : register_rst_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_first_syndrome_d,
clk => clk,
ce => reg_first_syndrome_ce,
rst => reg_first_syndrome_rst,
rst_value => reg_first_syndrome_rst_value,
q => reg_first_syndrome_q
);
mult : mult_gf_2_m
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => mult_a,
b => mult_b,
o => mult_o
);
ctr_syndrome : counter_rst_nbits
Generic Map(
size => size_syndrome,
increment_value => 1
)
Port Map(
clk => clk,
ce => ctr_syndrome_ce,
rst => ctr_syndrome_rst,
rst_value => ctr_syndrome_rst_value,
q => ctr_syndrome_q
);
ctr_codeword : counter_rst_nbits
Generic Map(
size => size_codeword,
increment_value => 1
)
Port Map(
clk => clk,
ce => ctr_codeword_ce,
rst => ctr_codeword_rst,
rst_value => ctr_codeword_rst_value,
q => ctr_codeword_q
);
reg_L_d <= value_L;
reg_h_d <= mult_o when sel_reg_h = '1' else
value_h;
reg_syndrome_d <= value_syndrome;
reg_codeword_d <= value_codeword;
reg_first_syndrome_d <= "0";
mult_a <= reg_h_q when square_h = '1' else
reg_L_q;
mult_b <= reg_h_q;
new_value_syndrome <= reg_h_q xor reg_syndrome_q;
address_h <= ctr_codeword_q;
address_L <= ctr_codeword_q;
address_codeword <= ctr_codeword_q;
address_syndrome <= std_logic_vector(to_unsigned(length_syndrome - 1, ctr_syndrome_q'length) - unsigned(ctr_syndrome_q));
limit_ctr_codeword_q <= '1' when (ctr_codeword_q = std_logic_vector(to_unsigned(length_codeword - 1, ctr_codeword_q'length))) else '0';
limit_ctr_syndrome_q <= '1' when (ctr_syndrome_q = std_logic_vector(to_unsigned(length_syndrome - 1, ctr_syndrome_q'length))) else '0';
end Behavioral;
| bsd-2-clause | e6ed5306d27e72932276e73edc808a6a | 0.648868 | 2.824735 | false | false | false | false |
pmassolino/hw-goppa-mceliece | mceliece/controller_codeword_generator_3.vhd | 1 | 17,501 | ----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Controller_Codeword_Generator_3
-- Module Name: Controller_Codeword_Generator_3
-- Project Name: 1st Step - Codeword Generation
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The first and only step in QD-Goppa Code encoding.
-- This circuit is the state machine controller for Codeword_Generator_n_m_v3.
-- The state machine is composed of two operations: one to copy the
-- original message and another for multiplying the message by matrix A.
-- Both operations happen at the same time.
-- This matrix multiplication is designed for matrices composed of dyadic blocks.
-- The algorithm computes one dyadic matrix at time.
-- Each dyadic matrix is computed in a column wise strategy.
--
-- Dependencies:
-- VHDL-93
--
-- Revision:
-- Revision 1.00
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity controller_codeword_generator_3 is
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
limit_ctr_dyadic_column_q : in STD_LOGIC;
limit_ctr_dyadic_row_q : in STD_LOGIC;
limit_ctr_address_message_q : in STD_LOGIC;
limit_ctr_address_codeword_q : in STD_LOGIC;
zero_ctr_address_message_q : in STD_LOGIC;
write_enable_new_codeword : out STD_LOGIC;
write_enable_new_codeword_copy : out STD_LOGIC;
external_matrix_ce : out STD_LOGIC;
reg_codeword_ce : out STD_LOGIC;
reg_codeword_rst : out STD_LOGIC;
reg_message_ce : out STD_LOGIC;
reg_matrix_ce : out STD_LOGIC;
ctr_dyadic_column_ce : out STD_LOGIC;
ctr_dyadic_column_rst : out STD_LOGIC;
ctr_dyadic_row_ce : out STD_LOGIC;
ctr_dyadic_row_rst : out STD_LOGIC;
ctr_dyadic_matrices_ce : out STD_LOGIC;
ctr_dyadic_matrices_rst : out STD_LOGIC;
ctr_address_base_message_ce : out STD_LOGIC;
ctr_address_base_message_rst : out STD_LOGIC;
ctr_address_base_codeword_ce : out STD_LOGIC;
ctr_address_base_codeword_rst : out STD_LOGIC;
reg_address_new_codeword_copy_ce : out STD_LOGIC;
internal_codeword : out STD_LOGIC;
codeword_finalized : out STD_LOGIC
);
end controller_codeword_generator_3;
architecture Behavioral of controller_codeword_generator_3 is
type State is (reset, load_counter, prepare_counters, load_acc, load_acc_entire_matrix, calc_codeword, last_column_value, write_last_column_value, last_row_value, write_last_row_value, last_value, write_last_value, final);
signal actual_state, next_state : State;
begin
Clock: process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
actual_state <= reset;
else
actual_state <= next_state;
end if;
end if;
end process;
Output: process (actual_state, limit_ctr_dyadic_column_q, limit_ctr_dyadic_row_q, limit_ctr_address_message_q, limit_ctr_address_codeword_q, zero_ctr_address_message_q)
begin
case (actual_state) is
when reset =>
write_enable_new_codeword <= '0';
write_enable_new_codeword_copy <= '0';
external_matrix_ce <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '1';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '1';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '1';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '1';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '1';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '1';
reg_address_new_codeword_copy_ce <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
when load_counter =>
write_enable_new_codeword <= '0';
write_enable_new_codeword_copy <= '0';
external_matrix_ce <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '1';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '1';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '1';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '1';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '1';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
reg_address_new_codeword_copy_ce <= '1';
internal_codeword <= '0';
codeword_finalized <= '0';
when prepare_counters =>
write_enable_new_codeword <= '0';
write_enable_new_codeword_copy <= '0';
external_matrix_ce <= '1';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
reg_address_new_codeword_copy_ce <= '1';
internal_codeword <= '0';
codeword_finalized <= '0';
when load_acc =>
if(zero_ctr_address_message_q = '1') then
write_enable_new_codeword <= '0';
write_enable_new_codeword_copy <= '1';
external_matrix_ce <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '1';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
reg_address_new_codeword_copy_ce <= '1';
internal_codeword <= '0';
codeword_finalized <= '0';
else
write_enable_new_codeword <= '0';
write_enable_new_codeword_copy <= '1';
external_matrix_ce <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
reg_address_new_codeword_copy_ce <= '1';
internal_codeword <= '0';
codeword_finalized <= '0';
end if;
when load_acc_entire_matrix =>
if(zero_ctr_address_message_q = '1') then
write_enable_new_codeword <= '0';
write_enable_new_codeword_copy <= '1';
external_matrix_ce <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '1';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '1';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
reg_address_new_codeword_copy_ce <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
else
write_enable_new_codeword <= '0';
write_enable_new_codeword_copy <= '1';
external_matrix_ce <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '1';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
reg_address_new_codeword_copy_ce <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
end if;
when calc_codeword =>
write_enable_new_codeword <= '0';
write_enable_new_codeword_copy <= '1';
external_matrix_ce <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
reg_address_new_codeword_copy_ce <= '1';
internal_codeword <= '1';
codeword_finalized <= '0';
when last_row_value =>
write_enable_new_codeword <= '0';
write_enable_new_codeword_copy <= '1';
external_matrix_ce <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
reg_address_new_codeword_copy_ce <= '1';
internal_codeword <= '1';
codeword_finalized <= '0';
when write_last_row_value =>
write_enable_new_codeword <= '1';
write_enable_new_codeword_copy <= '0';
external_matrix_ce <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
reg_address_new_codeword_copy_ce <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
when last_column_value =>
write_enable_new_codeword <= '0';
write_enable_new_codeword_copy <= '1';
external_matrix_ce <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '1';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
reg_address_new_codeword_copy_ce <= '1';
internal_codeword <= '1';
codeword_finalized <= '0';
when write_last_column_value =>
if(limit_ctr_address_codeword_q = '1') then
write_enable_new_codeword <= '1';
write_enable_new_codeword_copy <= '0';
external_matrix_ce <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '1';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '1';
reg_address_new_codeword_copy_ce <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
else
write_enable_new_codeword <= '1';
write_enable_new_codeword_copy <= '0';
external_matrix_ce <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '1';
ctr_address_base_codeword_rst <= '0';
reg_address_new_codeword_copy_ce <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
end if;
when last_value =>
write_enable_new_codeword <= '0';
write_enable_new_codeword_copy <= '1';
external_matrix_ce <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
reg_address_new_codeword_copy_ce <= '0';
internal_codeword <= '1';
codeword_finalized <= '0';
when write_last_value =>
write_enable_new_codeword <= '1';
write_enable_new_codeword_copy <= '0';
external_matrix_ce <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '1';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '1';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '1';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '1';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '1';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '1';
reg_address_new_codeword_copy_ce <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
when final =>
write_enable_new_codeword <= '0';
write_enable_new_codeword_copy <= '0';
external_matrix_ce <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '1';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '1';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '1';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '1';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '1';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '1';
reg_address_new_codeword_copy_ce <= '0';
internal_codeword <= '0';
codeword_finalized <= '1';
when others =>
write_enable_new_codeword <= '0';
write_enable_new_codeword_copy <= '0';
external_matrix_ce <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '1';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '1';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '1';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '1';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '1';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '1';
reg_address_new_codeword_copy_ce <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
end case;
end process;
NewState : process(actual_state, limit_ctr_dyadic_column_q, limit_ctr_dyadic_row_q, limit_ctr_address_message_q, limit_ctr_address_codeword_q)
begin
case (actual_state) is
when reset =>
next_state <= load_counter;
when load_counter =>
next_state <= prepare_counters;
when prepare_counters =>
if(limit_ctr_dyadic_row_q = '1') then
next_state <= load_acc_entire_matrix;
else
next_state <= load_acc;
end if;
when load_acc =>
if(limit_ctr_dyadic_row_q = '1') then
if(limit_ctr_dyadic_column_q = '1') then
if(limit_ctr_address_message_q = '1') then
if(limit_ctr_address_codeword_q = '1') then
next_state <= last_value;
else
next_state <= last_column_value;
end if;
else
next_state <= last_column_value;
end if;
else
next_state <= last_row_value;
end if;
else
next_state <= calc_codeword;
end if;
when load_acc_entire_matrix =>
if(limit_ctr_dyadic_column_q = '1') then
if(limit_ctr_address_message_q = '1') then
if(limit_ctr_address_codeword_q = '1') then
next_state <= write_last_value;
else
next_state <= write_last_column_value;
end if;
else
next_state <= write_last_column_value;
end if;
else
next_state <= write_last_row_value;
end if;
when calc_codeword =>
if(limit_ctr_dyadic_row_q = '1') then
if(limit_ctr_dyadic_column_q = '1') then
if(limit_ctr_address_message_q = '1') then
if(limit_ctr_address_codeword_q = '1') then
next_state <= last_value;
else
next_state <= last_column_value;
end if;
else
next_state <= last_column_value;
end if;
else
next_state <= last_row_value;
end if;
else
next_state <= calc_codeword;
end if;
when last_column_value =>
next_state <= write_last_column_value;
when write_last_column_value =>
next_state <= prepare_counters;
when last_row_value =>
next_state <= write_last_row_value;
when write_last_row_value =>
next_state <= prepare_counters;
when last_value =>
next_state <= write_last_value;
when write_last_value =>
next_state <= final;
when final =>
next_state <= final;
when others =>
next_state <= reset;
end case;
end process;
end Behavioral;
| bsd-2-clause | 454dde5ce72a8032f89db7c374c5a7ae | 0.60448 | 2.788115 | false | false | false | false |
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